update(cherryusb): update to v1.5.2

Signed-off-by: sakumisu <[email protected]>

Author: sakumisu

lib/cherryusb

@@ -24,7 +24,7 @@ if (EXISTS ${PICO_CHERRYUSB_PATH}/${CHERRYUSB_TEST_PATH})
     set(CONFIG_CHERRYUSB_DEVICE_MSC 1)
     set(CONFIG_CHERRYUSB_DEVICE_AUDIO 1)
     set(CONFIG_CHERRYUSB_DEVICE_VIDEO 1)
-    set(CONFIG_CHERRYUSB_DEVICE_DCD "rp2040")
+    set(CONFIG_CHERRYUSB_DEVICE_RP2040 1)
     include(${PICO_CHERRYUSB_PATH}/cherryusb.cmake)
     pico_add_library(cherryusb_device NOFLAG)
     target_include_directories(cherryusb_device_headers SYSTEM INTERFACE ${cherryusb_incs})
@@ -35,7 +35,7 @@ if (EXISTS ${PICO_CHERRYUSB_PATH}/${CHERRYUSB_TEST_PATH})
     set(CONFIG_CHERRYUSB_HOST_HID 1)
     set(CONFIG_CHERRYUSB_HOST_MSC 1)
     set(CONFIG_CHERRYUSB_OSAL "freertos")
-    set(CONFIG_CHERRYUSB_HOST_HCD "rp2040")
+    set(CONFIG_CHERRYUSB_HOST_RP2040 1)
 
     include(${PICO_CHERRYUSB_PATH}/cherryusb.cmake)
     pico_add_library(cherryusb_host NOFLAG)

src/rp2_common/cherryusb/CMakeLists.txt

@@ -206,32 +206,13 @@
 #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
 #endif
 
-#ifndef CONFIG_USBDEV_EP_NUM
-#define CONFIG_USBDEV_EP_NUM 16
-#endif
-
 /* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */
 // #define CONFIG_USB_HS
 
 /* ---------------- FSDEV Configuration ---------------- */
 //#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
 
 /* ---------------- DWC2 Configuration ---------------- */
-/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
- * status information) + (2 * number of OUT endpoints) + 1 for Global NAK
- */
-// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
-/* IN Endpoints Max packet Size / 4 */
-// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
-// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4)
-// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
-// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
-// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
-// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
-// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
-// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
-// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
-
 // #define CONFIG_USB_DWC2_DMA_ENABLE
 
 /* ---------------- MUSB Configuration ---------------- */
@@ -242,10 +223,6 @@
 #define CONFIG_USBHOST_MAX_BUS 1
 #endif
 
-#ifndef CONFIG_USBHOST_PIPE_NUM
-#define CONFIG_USBHOST_PIPE_NUM 15
-#endif
-
 /* ---------------- EHCI Configuration ---------------- */
 
 #define CONFIG_USB_EHCI_HCCR_OFFSET     (0x0)
@@ -265,32 +242,11 @@
 #define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
 
 /* ---------------- DWC2 Configuration ---------------- */
-/* largest non-periodic USB packet used / 4 */
-// #define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4)
-/* largest periodic USB packet used / 4 */
-// #define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4)
-/*
- * (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
- * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
- */
-// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
 
 /* ---------------- MUSB Configuration ---------------- */
 // #define CONFIG_USB_MUSB_SUNXI
 
 /* ================ USB Dcache Configuration ==================*/
 
-#ifdef CONFIG_USB_DCACHE_ENABLE
-/* style 1*/
-// void usb_dcache_clean(uintptr_t addr, uint32_t size);
-// void usb_dcache_invalidate(uintptr_t addr, uint32_t size);
-// void usb_dcache_flush(uintptr_t addr, uint32_t size);
-
-/* style 2*/
-// #define usb_dcache_clean(addr, size)
-// #define usb_dcache_invalidate(addr, size)
-// #define usb_dcache_flush(addr, size)
-#endif
-
 #define CONFIG_USBDEV_ADVANCE_DESC
 #endif