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[raulbehl]

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[ayusdixit]

Sir , in day 46 what is the "make " file ?not able to understand

[raulbehl]

I use makefile to manage how different tools are called. Think of it as a script which tells how to invoke various tools.

[singuru1992]

first of all thanks for making this 100days rtl coding series
by seeing few of your posting from day 50 i made intrest to learn this rtl coding
iam beginner in this vlsi domine please explain in detail.
thankyou...
make file of day 13 ---->>> echo "plugin -i systemverilog" > synth.ys
please tell why it is mentioned here for mux.
why you not mentioned for any privious programs.
thankyou for sharing

[raulbehl]

This is to do with the Yosys tool. I upgraded the tool version and hence had to add this option. This option allows Yosys to understand different system Verilog design constructs.

[singuru1992]

for protocols you are using is there any document to study further please give link which is easily understandable. thanks in advance for sharing..

[raulbehl]

Yes, you can look into the AMBA APB protocol or you could look into my new RTL Design course which teaches you this and various other protocols. Here's the link to a free problem on APB protocol:

https://quicksilicon.in/course/rtl-design/module/events-to-apb/

[rahulgupta2024]

Hi sir ,
I am getting a error running for-loop with some designs. I am using Intel Quartus and ModelSim-Altera for design and simulation.

[rahulgupta2024]

I am unable to figure out " Expecting endmodule".

[raulbehl]

Hey, this seems like the SV (system Verilog) style of compilation isn't enabled. You could try adding generate...endgenerate block to make it compatible with Verilog.

Also, if you're interested in such designs then I'd recommend checking out my new course on RTL Design. You can start by solving this freely available problem:
https://quicksilicon.in/course/rtl-design/module/events-to-apb/