From 85712f1d60bda1ead9d3cdaec8d08aabc370fcb0 Mon Sep 17 00:00:00 2001 From: Bryce Callender Date: Tue, 29 Dec 2020 20:02:10 -0800 Subject: [PATCH 01/20] Fixes and updates to Instruction set --- SAP1EMU.Assembler/InstructionValidator.cs | 4 +- SAP1EMU.Engine/EngineProc.cs | 2 +- SAP1EMU.GUI/Controllers/HomeController.cs | 14 +- SAP1EMU.GUI/InstructionSets.json | 6 +- SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml | 25 +- .../Home/{Emulator.cshtml => SAP1.cshtml} | 2 +- SAP1EMU.GUI/Views/Home/SAP2.cshtml | 160 ++ SAP1EMU.GUI/wwwroot/css/site.css | 11 +- SAP1EMU.Lib/Components/SEQ.cs | 2 +- SAP1EMU.Lib/InstructionDecoder.cs | 2 +- SAP1EMU.Lib/InstructionSet.cs | 2 +- SAP1EMU.Lib/InstructionSets.json | 6 +- SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs | 33 +- SAP1EMU.SAP2.Assembler/Assemble.cs | 26 +- SAP1EMU.SAP2.Engine.Test/EngineTest.cs | 56 + .../SAP1EMU.SAP2.Engine.Test.csproj | 15 + SAP1EMU.SAP2.Engine/EngineProc.cs | 20 +- .../SAP1EMU.SAP2.Engine.csproj | 7 +- SAP1EMU.SAP2.Engine/SAP2InstructionSets.json | 816 --------- SAP1EMU.SAP2.Lib.Test/FrameTest.cs | 93 +- SAP1EMU.SAP2.Lib.Test/ProgramTest.cs | 138 +- .../SAP1EMU.SAP2.Lib.Test.csproj | 4 +- .../SAP2InstructionSets.json | 761 --------- SAP1EMU.SAP2.Lib/Components/RAM.cs | 20 +- SAP1EMU.SAP2.Lib/Components/SEQ.cs | 122 +- SAP1EMU.SAP2.Lib/Frame.cs | 121 +- SAP1EMU.SAP2.Lib/RAMProgram.cs | 5 +- SAP1EMU.SAP2.Lib/Registers/AReg.cs | 2 +- SAP1EMU.SAP2.Lib/Registers/BReg.cs | 2 +- SAP1EMU.SAP2.Lib/Registers/CReg.cs | 2 +- SAP1EMU.SAP2.Lib/Registers/Flag.cs | 22 +- SAP1EMU.SAP2.Lib/Registers/IReg.cs | 2 +- SAP1EMU.SAP2.Lib/Registers/MDR.cs | 6 +- SAP1EMU.SAP2.Lib/Registers/PC.cs | 6 +- SAP1EMU.SAP2.Lib/Registers/TReg.cs | 2 +- SAP1EMU.SAP2.Lib/SAP2InstructionSets.json | 1512 ++++++++--------- .../Utilities/ExtensionMethods.cs | 16 + SAP1EMU.sln | 10 + 38 files changed, 1402 insertions(+), 2653 deletions(-) rename SAP1EMU.GUI/Views/Home/{Emulator.cshtml => SAP1.cshtml} (99%) create mode 100644 SAP1EMU.GUI/Views/Home/SAP2.cshtml create mode 100644 SAP1EMU.SAP2.Engine.Test/EngineTest.cs create mode 100644 SAP1EMU.SAP2.Engine.Test/SAP1EMU.SAP2.Engine.Test.csproj delete mode 100644 SAP1EMU.SAP2.Engine/SAP2InstructionSets.json delete mode 100644 SAP1EMU.SAP2.Lib.Test/SAP2InstructionSets.json create mode 100644 SAP1EMU.SAP2.Lib/Utilities/ExtensionMethods.cs diff --git a/SAP1EMU.Assembler/InstructionValidator.cs b/SAP1EMU.Assembler/InstructionValidator.cs index a56df130..413535ee 100644 --- a/SAP1EMU.Assembler/InstructionValidator.cs +++ b/SAP1EMU.Assembler/InstructionValidator.cs @@ -14,7 +14,7 @@ public static bool IsValidInstruction(string instruction, InstructionSet iset) } try { - return !string.IsNullOrEmpty(iset.instructions.Find(x => x.OpCode.ToLower().Equals(instruction.ToLower())).OpCode); + return !string.IsNullOrEmpty(iset.Instructions.Find(x => x.OpCode.ToLower().Equals(instruction.ToLower())).OpCode); } catch (NullReferenceException) { @@ -28,7 +28,7 @@ public static string GetUpperNibble(string instruction, InstructionSet iset) { return "0000"; } - return iset.instructions.Find(x => x.OpCode.ToLower().Equals(instruction.ToLower())).BinCode; + return iset.Instructions.Find(x => x.OpCode.ToLower().Equals(instruction.ToLower())).BinCode; } } } \ No newline at end of file diff --git a/SAP1EMU.Engine/EngineProc.cs b/SAP1EMU.Engine/EngineProc.cs index 08fd8063..5d64b941 100644 --- a/SAP1EMU.Engine/EngineProc.cs +++ b/SAP1EMU.Engine/EngineProc.cs @@ -139,7 +139,7 @@ public void Run() // Log the Instruction if (TState == 4) { - string iname = InstructionSet.instructions.Find(x => x.BinCode.Equals(ireg.ToString())).OpCode; + string iname = InstructionSet.Instructions.Find(x => x.BinCode.Equals(ireg.ToString())).OpCode; int operandVal = Convert.ToInt32(ireg.ToString_Frame_Use().Substring(4, 4), 2); string hexOperand = "0x" + operandVal.ToString("X"); // Log.Information($"SAP1Emu: Instruction: {iname}, Operand: {hexOperand}"); diff --git a/SAP1EMU.GUI/Controllers/HomeController.cs b/SAP1EMU.GUI/Controllers/HomeController.cs index 4f9dffb3..966afcb7 100644 --- a/SAP1EMU.GUI/Controllers/HomeController.cs +++ b/SAP1EMU.GUI/Controllers/HomeController.cs @@ -2,8 +2,6 @@ using Microsoft.Extensions.Logging; using SAP1EMU.GUI.Models; -using System.Collections.Generic; -using System.ComponentModel.DataAnnotations; using System.Diagnostics; namespace SAP1EMU.GUI.Controllers @@ -30,6 +28,18 @@ public IActionResult About() [HttpGet] public IActionResult Emulator() + { + return View("EmulatorPicker"); + } + + [Route("/Emulator/SAP1")] + public IActionResult SAP1() + { + return View(); + } + + [Route("/Emulator/SAP2")] + public IActionResult SAP2() { return View(); } diff --git a/SAP1EMU.GUI/InstructionSets.json b/SAP1EMU.GUI/InstructionSets.json index 990253cc..0c480299 100644 --- a/SAP1EMU.GUI/InstructionSets.json +++ b/SAP1EMU.GUI/InstructionSets.json @@ -2,7 +2,7 @@ { "SetName": "SAP1Emu", "SetDescription": "The full intruction set for the SAP1Emu Project.", - "instructions": [ + "Instructions": [ { "OpCode": "LDA", "BinCode": "0000", @@ -152,7 +152,7 @@ { "SetName": "Malvino", "SetDescription": "The instruction set outlined in Digital Computer Electronics by Malvino & Brown.\nThe SAP1Emu Set is a superset of the Malvino Set.", - "instructions": [ + "Instructions": [ { "OpCode": "LDA", "BinCode": "0000", @@ -218,7 +218,7 @@ { "SetName": "BenEater", "SetDescription": "The instruction set outlined by Ben Eater.", - "instructions": [ + "Instructions": [ { "OpCode": "NOP", "BinCode": "0000", diff --git a/SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml b/SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml index 82ce4cf0..42149325 100644 --- a/SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml +++ b/SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml @@ -2,40 +2,27 @@ ViewData["Title"] = "Emulator"; } +

Choose an Emulator

-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
- +
+ Card image

SAP1

-
- +
+ Card image

SAP2

- Comming Soon -
@*
diff --git a/SAP1EMU.GUI/Views/Home/Emulator.cshtml b/SAP1EMU.GUI/Views/Home/SAP1.cshtml similarity index 99% rename from SAP1EMU.GUI/Views/Home/Emulator.cshtml rename to SAP1EMU.GUI/Views/Home/SAP1.cshtml index e1501274..ddd8da4a 100644 --- a/SAP1EMU.GUI/Views/Home/Emulator.cshtml +++ b/SAP1EMU.GUI/Views/Home/SAP1.cshtml @@ -26,7 +26,7 @@ else } @{ - ViewData["Title"] = "Emulator"; + ViewData["Title"] = "SAP1 Emulator"; }

Emulator

diff --git a/SAP1EMU.GUI/Views/Home/SAP2.cshtml b/SAP1EMU.GUI/Views/Home/SAP2.cshtml new file mode 100644 index 00000000..fcde0faa --- /dev/null +++ b/SAP1EMU.GUI/Views/Home/SAP2.cshtml @@ -0,0 +1,160 @@ +@model CodePacket + + + + + + + + + +@if (Model != null) +{ + +} +else +{ + +} +@{ + ViewData["Title"] = "SAP2 Emulator"; +} + +

Emulator

+ +
+ +
+
+

Assembly

+
+ +
+
+
+ @Html.TextArea("CodeList", null, new { rows = "20", cols = "80", @class = "codebox", id = "asm_code" }) +
+
+ @Html.TextArea("ram_dump", null, new { rows = "16", cols = "20", @class = "codebox", id = "ram_dump" }) +
+
+ +
+
+ + +
+
+ +
+
+ +
+
+
+
+ +
+
+

SAP1

+
+
+
+
+ + + + +
+
+
+ + +
+
+
+
+
+ ??? +
+ +
+
+
+
+
+
+
+
+
+
+
+
+
Program Counter

+                    
MAR

+                    
RAM

+                    
Instruction Register

+                    
Sequencer

+                

+                

+                    

+                        
WBus

+                    

+                

+                

+                    
A Register
 

+                    
ALU

+                    
B Register

+                    
Output Register

+                    
Display

+                

+            

+            

+                

+                    

+                        

+                            Carry
+                        

+                        
+                    

+                

+                

+                    

+                        

+                            Underflow
+                        

+                        
+                    

+                

+                

+                    

+                        

+                            Zero
+                        

+                        
+                    

+                

+            

+        

+    

+

+
+

+    

+        

+            
Emulator Errors

+        

+        

+            

+        

+    

+

\ No newline at end of file
diff --git a/SAP1EMU.GUI/wwwroot/css/site.css b/SAP1EMU.GUI/wwwroot/css/site.css
index e80c4284..cd1975e7 100644
--- a/SAP1EMU.GUI/wwwroot/css/site.css
+++ b/SAP1EMU.GUI/wwwroot/css/site.css
@@ -178,4 +178,13 @@ body {
 
 .toast-error {
     background-color: lightcoral !important;
-}
\ No newline at end of file
+}
+
+.zoom {
+    transition: transform .2s;
+}
+
+.zoom:hover {
+    transform: scale(1.2);
+}
+
diff --git a/SAP1EMU.Lib/Components/SEQ.cs b/SAP1EMU.Lib/Components/SEQ.cs
index 38f98c60..e63431e1 100644
--- a/SAP1EMU.Lib/Components/SEQ.cs
+++ b/SAP1EMU.Lib/Components/SEQ.cs
@@ -54,7 +54,7 @@ public void Load(InstructionSet iset)
             //SupportedCommandsBinTable.Clear();
             ControlTable.Clear();
 
-            foreach (Instruction instruction in iset.instructions)
+            foreach (Instruction instruction in iset.Instructions)
             {
                 //  SupportedCommandsBinTable.Add(instruction.OpCode, instruction.BinCode);
 
diff --git a/SAP1EMU.Lib/InstructionDecoder.cs b/SAP1EMU.Lib/InstructionDecoder.cs
index cc2fc45c..b59d44c3 100644
--- a/SAP1EMU.Lib/InstructionDecoder.cs
+++ b/SAP1EMU.Lib/InstructionDecoder.cs
@@ -17,7 +17,7 @@ public InstructionDecoder()
 
             foreach (InstructionSet iset in sets)
             {
-                foreach (Instruction i in iset.instructions)
+                foreach (Instruction i in iset.Instructions)
                 {
                     _instructions.Add((i.BinCode, iset.SetName).GetHashCode(), i.OpCode);
                 }
diff --git a/SAP1EMU.Lib/InstructionSet.cs b/SAP1EMU.Lib/InstructionSet.cs
index 60167fa0..f95e6bfd 100644
--- a/SAP1EMU.Lib/InstructionSet.cs
+++ b/SAP1EMU.Lib/InstructionSet.cs
@@ -6,6 +6,6 @@ public class InstructionSet
     {
         public string SetName { get; set; }
         public string SetDescription { get; set; }
-        public List instructions { get; set; }
+        public List Instructions { get; set; }
     }
 }
\ No newline at end of file
diff --git a/SAP1EMU.Lib/InstructionSets.json b/SAP1EMU.Lib/InstructionSets.json
index 990253cc..0c480299 100644
--- a/SAP1EMU.Lib/InstructionSets.json
+++ b/SAP1EMU.Lib/InstructionSets.json
@@ -2,7 +2,7 @@
   {
     "SetName": "SAP1Emu",
     "SetDescription": "The full intruction set for the SAP1Emu Project.",
-    "instructions": [
+    "Instructions": [
       {
         "OpCode": "LDA",
         "BinCode": "0000",
@@ -152,7 +152,7 @@
   {
     "SetName": "Malvino",
     "SetDescription": "The instruction set outlined in Digital Computer Electronics by Malvino & Brown.\nThe SAP1Emu Set is a superset of the Malvino Set.",
-    "instructions": [
+    "Instructions": [
       {
         "OpCode": "LDA",
         "BinCode": "0000",
@@ -218,7 +218,7 @@
   {
     "SetName": "BenEater",
     "SetDescription": "The instruction set outlined by Ben Eater.",
-    "instructions": [
+    "Instructions": [
       {
         "OpCode": "NOP",
         "BinCode": "0000",
diff --git a/SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs b/SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs
index 4200a073..82196b85 100644
--- a/SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs
+++ b/SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs
@@ -12,6 +12,34 @@ public class AssemblerTest
 
         [TestMethod]
         public void TestParseList_Valid_Code_1()
+        {
+            List asm = new List
+            {
+                "MVI A,0x5",
+                "MOV B,A",
+                "HLT"
+            };
+
+            List expected_bin = new List
+            {
+                "00111110",
+                "00000101",
+                "01000111",
+                "01110110"
+            };
+
+            List compiled_bin = Assemble.Parse(asm);
+
+            Assert.AreEqual(expected_bin.Count, compiled_bin.Count);
+
+            for (int i = 0; i < compiled_bin.Count; i++)
+            {
+                Assert.AreEqual(expected_bin[i], compiled_bin[i]);
+            }
+        }
+
+        [TestMethod]
+        public void TestParseList_Valid_Code_2()
         {
             List asm = new List
             {
@@ -46,7 +74,7 @@ public void TestParseList_Valid_Code_1()
         }
 
         [TestMethod]
-        public void TestParseList_Valid_Code_With_Labels()
+        public void TestParseList_Valid_Code_2_With_Labels()
         {
             List asm = new List
             {
@@ -91,13 +119,12 @@ public void TestParseList_Valid_Code_With_Label_Decl_Forgotten()
                 "OUT 0x3",
                 "HLT"
             };
-
             try
             {
                 _ = Assemble.Parse(asm);
                 Assert.Fail();
             }
-            catch(ParseException e)
+            catch (ParseException)
             {
                 Assert.IsTrue(true);
             }
diff --git a/SAP1EMU.SAP2.Assembler/Assemble.cs b/SAP1EMU.SAP2.Assembler/Assemble.cs
index cf38edab..b84a5e78 100644
--- a/SAP1EMU.SAP2.Assembler/Assemble.cs
+++ b/SAP1EMU.SAP2.Assembler/Assemble.cs
@@ -29,7 +29,7 @@ public static List Parse(List unchecked_assembly, string Instruc
             unchecked_assembly.RemoveAll(s => Regex.IsMatch(s, "^\\s*$"));
 
             // Remove Newline Comments
-            unchecked_assembly.RemoveAll(s => s.Trim().First() == '#');
+            unchecked_assembly.RemoveAll(s => s.Trim().First().Equals('#'));
 
             // Find and store info on all labels
             labels = unchecked_assembly.Where(line => line.Contains(':'))
@@ -65,7 +65,7 @@ public static List Parse(List unchecked_assembly, string Instruc
             // based on line numbers.
             foreach (Label label in labels)
             {
-                unchecked_assembly[label.LineNumber - 1] = Regex.Replace(unchecked_assembly[label.LineNumber - 1], @"\s*\w{1,6}:", "").Trim();
+                unchecked_assembly[label.LineNumber - 1] = Regex.Replace(unchecked_assembly[label.LineNumber - 1], "\\s*\\w{1,6}:", "").Trim();
             }
 
             // *********************************************************************
@@ -124,7 +124,7 @@ public static List Parse(List unchecked_assembly, string Instruc
                     {
                         string value = line[index..].Trim();
 
-                        // If we have JXX Label
+                        // If we have JXX Label then sub the label for its respective line number in the code
                         if (labels.Any(l => l.Name.Equals(value)))
                         {
                             Label label = labels.First(l => l.Name.Equals(value));
@@ -138,6 +138,7 @@ public static List Parse(List unchecked_assembly, string Instruc
                         binaryRepresentation = binaryRepresentation.PadLeft(8 * (instruction.Bytes - 1), '0');
                         int position = binaryRepresentation.Length == 8 ? 0 : 8;
 
+                        // Add from right to left
                         for(int i = 1; i < instruction.Bytes; i++, position -= 8)
                         {
                             binary.Add(string.Join("", binaryRepresentation.Skip(position).Take(8)));
@@ -149,11 +150,11 @@ public static List Parse(List unchecked_assembly, string Instruc
             }
             // *********************************************************************
 
-            //If a program was executed, but didnt fill in every line of RAM then throw an exception. Must have 16 elements!
-            //if(binary.Count != 16)
-            //{
-            //    throw new ParseException($"SAP1ASM: Program must have 16 lines.", new ParseException("Use \"NOP 0x0\" for a no-operation command or the \"...\" macro to fill in the rest with NOP 0x0.")); 
-            //}
+            // If a program contains way too many instructions
+            if (binary.Count > 0xFFFF) //(65,535)
+            {
+                throw new ParseException($"SAP2ASM: Program contains too many lines of code.", new ParseException("The SAP2 can only contain up to 65,535 lines of code."));
+            }
 
 
             return binary;
@@ -165,7 +166,7 @@ private static bool IsValid(List unchecked_assembly, InstructionSet iset
             bool contains_hlt = false;
 
             // HLT is a special case that cannot be included in this but it is a non data instruction
-            string[] nonDataInstructions = { "CMA", "NOP", "RAL", "RAR", "RET"};
+            string[] nonDataInstructions = { "CMA", "NOP", "RAL", "RAR", "RET", "MOV A,B", "MOV A,C", "MOV B,A", "MOV B,C", "MOV C,A", "MOV C,B"};
 
             int line_number = 1;
             foreach (string line in unchecked_assembly)
@@ -224,17 +225,18 @@ private static bool IsValid(List unchecked_assembly, InstructionSet iset
                     {
                         continue;
                     }
-                    
+
+                    // Special case 
                     if (instruction.OpCode == "HLT")
                     {
                         contains_hlt = true;
                         continue;
                     }
 
-                    //Check the validity of the instructions and their data
+                    // Check the validity of the instructions and their data
                     string value = line[index..].Trim();
 
-                    //Check Jump addresses and check if labels exist to jump too
+                    // Check Jump addresses and check if labels exist to jump too
                     int data = 0;
                     try
                     {
diff --git a/SAP1EMU.SAP2.Engine.Test/EngineTest.cs b/SAP1EMU.SAP2.Engine.Test/EngineTest.cs
new file mode 100644
index 00000000..98e82016
--- /dev/null
+++ b/SAP1EMU.SAP2.Engine.Test/EngineTest.cs
@@ -0,0 +1,56 @@
+using Microsoft.VisualStudio.TestTools.UnitTesting;
+
+using SAP1EMU.SAP2.Engine;
+using SAP1EMU.SAP2.Lib;
+
+using System.Collections.Generic;
+
+namespace SAP1EMU.Engine.Test
+{
+    [TestClass]
+    public class EngineTest
+    {
+        private IDecoder _decoder = new InstructionDecoder();
+        // LDA Tests 1-3 ************************************************************
+
+        #region MVI MOV 1-3
+
+        // Test_LDA_PROG_1 **********************************************************
+        /// 
+        /// This will run the following program
+        ///
+        /// 0x0 MVI A,0x5
+        /// 0x1 MOV B,A
+        /// 0x2 OUT 0x3
+        /// 0x3 HLT
+        ///
+        /// The expected result is OReg: 00000000
+        /// Testing to see if B == A
+        /// 
+        [TestMethod]
+        public void Test_MVI_MOV_PROG_1()
+        {
+            string expectedResult = "00000001";
+            List program = new List()
+            {
+                "00111110",
+                "00000101",
+                "01000111",
+                "01110110"
+            };
+
+            EngineProc engine = new EngineProc();
+
+            RAMProgram rp = new RAMProgram(program);
+             
+            engine.Init(rp, _decoder);
+            engine.Run();
+
+            string output = engine.GetOutputReg();
+
+            Assert.AreEqual(expectedResult, output);
+        }
+    }
+
+    #endregion
+}
\ No newline at end of file
diff --git a/SAP1EMU.SAP2.Engine.Test/SAP1EMU.SAP2.Engine.Test.csproj b/SAP1EMU.SAP2.Engine.Test/SAP1EMU.SAP2.Engine.Test.csproj
new file mode 100644
index 00000000..836817b6
--- /dev/null
+++ b/SAP1EMU.SAP2.Engine.Test/SAP1EMU.SAP2.Engine.Test.csproj
@@ -0,0 +1,15 @@
+
+
+  
+    netcoreapp3.1
+  
+
+  
+    
+    
+    
+  
+  
+    
+  
+
diff --git a/SAP1EMU.SAP2.Engine/EngineProc.cs b/SAP1EMU.SAP2.Engine/EngineProc.cs
index 5a94fca3..6dad1cf3 100644
--- a/SAP1EMU.SAP2.Engine/EngineProc.cs
+++ b/SAP1EMU.SAP2.Engine/EngineProc.cs
@@ -70,7 +70,7 @@ public void Run()
             ALU alu = new ALU(ref areg, ref treg);
             Flag flagReg = new Flag(ref alu);
             PC pc = new PC(ref flagReg);
-            MAR mreg = new MAR(ref ram);
+            MAR mar = new MAR(ref ram);
             SEQ seq = SEQ.Instance();
 
             Wbus.Instance().Value = string.Concat(Enumerable.Repeat('0', 16));
@@ -80,7 +80,7 @@ public void Run()
             breg.Subscribe(clock);
             creg.Subscribe(clock);
             ireg.Subscribe(clock);
-            mreg.Subscribe(clock);
+            mar.Subscribe(clock);
             oreg3.Subscribe(clock);
             hexadecimalDisplay.Subscribe(clock);
             oreg4.Subscribe(clock);
@@ -109,10 +109,10 @@ public void Run()
             int TState = 1;
 
             // A basic empty instruction state with 3 TStates since on the 4th the instruction
-            // will be known and set.
+            // will be known and set to a new object reference.
             Instruction currentInstruction = new Instruction()
             {
-                TStates = 3
+                TStates = 4 // Since by 4 TStates it should know what instruction it is on
             };
 
             while (clock.IsEnabled)
@@ -129,7 +129,7 @@ public void Run()
                 // Log the Instruction
                 if (TState == 4)
                 {
-                    currentInstruction = InstructionSet.Instructions.FirstOrDefault(x => x.BinCode.Equals(ireg.ToString()));
+                    currentInstruction = InstructionSet.Instructions.FirstOrDefault(i => i.BinCode.Equals(ireg.RegContent));
                     string iname = currentInstruction.OpCode;
                     int operandVal = Convert.ToInt32(ireg.RegContent, 2);
                     string hexOperand = "0x" + operandVal.ToString("X");
@@ -140,7 +140,11 @@ public void Run()
                 clock.SendTicTok(tictok);
                 tictok.ToggleClockState();
 
-                tempFrame = new Frame(ireg.RegContent, TState, areg, breg, ireg, mreg, oreg3, pc, alu, ram.RAMDump(), ram, seq, Wbus.Instance().ToString(), flagReg, _decoder, InstructionSet.SetName);
+                tempFrame = new Frame(currentInstruction, TState, port1, port2, pc, mar, ram,
+                                      ram.RAMDump(), mdr, ireg, SEQ.Instance(),
+                                      Wbus.Instance().Value, areg, alu, flagReg,
+                                      treg, breg, creg, oreg3, oreg4, hexadecimalDisplay);
+
                 _FrameStack.Add(tempFrame);
 
                 // HLT 
@@ -158,13 +162,11 @@ public void Run()
                     loop_counter++;
                 }
 
-                // TODO implement this
                 if(pc.WontJump)
                 {
                     currentInstruction.TStates = 7;
                 }
 
-                // TODO -> figure out what to do when jumps take 7
                 if (TState < currentInstruction.TStates)
                 {
                     TState++;
@@ -194,7 +196,7 @@ public Frame FinalFrame()
         {
             if (_FrameStack.Count != 0)
             {
-                return _FrameStack[_FrameStack.Count - 1];
+                return _FrameStack[^1];
             }
             else
             {
diff --git a/SAP1EMU.SAP2.Engine/SAP1EMU.SAP2.Engine.csproj b/SAP1EMU.SAP2.Engine/SAP1EMU.SAP2.Engine.csproj
index ff0d9598..ab06f25e 100644
--- a/SAP1EMU.SAP2.Engine/SAP1EMU.SAP2.Engine.csproj
+++ b/SAP1EMU.SAP2.Engine/SAP1EMU.SAP2.Engine.csproj
@@ -6,12 +6,9 @@
   
 
   
-    
+    
       Always
-    
-    
-      Always
-    
+    
   
 
   
diff --git a/SAP1EMU.SAP2.Engine/SAP2InstructionSets.json b/SAP1EMU.SAP2.Engine/SAP2InstructionSets.json
deleted file mode 100644
index f559c7ca..00000000
--- a/SAP1EMU.SAP2.Engine/SAP2InstructionSets.json
+++ /dev/null
@@ -1,816 +0,0 @@
-[
-  {
-    "SetName": "Mavlino",
-    "SetDescription": "The full intruction set for the SAP1Emu Project.",
-    "instructions": [
-      {
-        "OpCode": "ADD B",
-        "BinCode": "10000000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ADD C",
-        "BinCode": "10000001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANA B",
-        "BinCode": "10100000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANA C",
-        "BinCode": "10100001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANI",
-        "BinCode": "11100110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "CALL",
-        "BinCode": "11001101",
-        "TStates": 18,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "CMA",
-        "BinCode": "00101111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR A",
-        "BinCode": "00111101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR B",
-        "BinCode": "00000101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR C",
-        "BinCode": "00001101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "HLT",
-        "BinCode": "01110110",
-        "TStates": 5,
-        "AffectsFlags": false,
-        "AddressingMode": "None",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "IN",
-        "BinCode": "11011011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR A",
-        "BinCode": "00111100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR B",
-        "BinCode": "00000100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR C",
-        "BinCode": "00001100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JM",
-        "BinCode": "11111010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JMP",
-        "BinCode": "11000011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JNZ",
-        "BinCode": "11000010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JZ",
-        "BinCode": "11001010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "LDA",
-        "BinCode": "00111010",
-        "TStates": 13,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV A,B",
-        "BinCode": "01111000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV A,C",
-        "BinCode": "01111001",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV B,A",
-        "BinCode": "01000111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV B,C",
-        "BinCode": "01000001",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV C,A",
-        "BinCode": "01001111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV C,B",
-        "BinCode": "01001000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI A",
-        "BinCode": "00111110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI B",
-        "BinCode": "00000110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI C",
-        "BinCode": "00001110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "NOP",
-        "BinCode": "00000000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "None",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORA B",
-        "BinCode": "10110000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORA C",
-        "BinCode": "10110001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORI",
-        "BinCode": "11110110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "OUT",
-        "BinCode": "11010011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RAL",
-        "BinCode": "00010111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RAR",
-        "BinCode": "00011111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RET",
-        "BinCode": "11001001",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "STA",
-        "BinCode": "00110010",
-        "TStates": 13,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "SUB B",
-        "BinCode": "10010000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "SUB C",
-        "BinCode": "100010001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRA B",
-        "BinCode": "10101000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRA C",
-        "BinCode": "10101001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRI",
-        "BinCode": "11101110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      }
-    ]
-  }
-]
\ No newline at end of file
diff --git a/SAP1EMU.SAP2.Lib.Test/FrameTest.cs b/SAP1EMU.SAP2.Lib.Test/FrameTest.cs
index 4990f149..1b968b6a 100644
--- a/SAP1EMU.SAP2.Lib.Test/FrameTest.cs
+++ b/SAP1EMU.SAP2.Lib.Test/FrameTest.cs
@@ -1,40 +1,67 @@
-using Microsoft.VisualStudio.TestTools.UnitTesting;
+using System.Linq;
+using Microsoft.VisualStudio.TestTools.UnitTesting;
 
 using SAP1EMU.SAP2.Lib.Components;
 using SAP1EMU.SAP2.Lib.Registers;
 
 namespace SAP1EMU.SAP2.Lib.Test
 {
-    //[TestClass]
-    //public class FrameTest
-    //{
-    //    private IDecoder _decoder = new InstructionDecoder();
-
-    //    [TestMethod]
-    //    public void TestToString()
-    //    {
-            //Clock clock = new Clock();
-            //TicTok tictok = new TicTok();
-
-            //tictok.Init(); ;
-            //int TState = 0;
-            //AReg areg = new AReg();
-            //BReg breg = new BReg();
-            //IReg ireg = new IReg();
-            //OReg oreg = new OReg();
-            //RAM ram = new RAM();
-
-            //PC pc = new PC(ref areg);
-            //ALU alu = new ALU(ref areg, ref breg);
-            //MReg mreg = new MReg(ref ram);
-            //SEQ seq = SEQ.Instance();
-
-            //Wbus.Instance().Value = "00000000";
-            //Flags.Instance().Clear();
-
-            //Frame frame = new Frame(ireg.ToString(), TState, areg, breg, ireg, mreg, oreg, pc, alu, ram.RAMDump(), ram, seq, Wbus.Instance().ToString(), Flags.Instance(), _decoder);
-            //_ = frame.ToString();
-            //_ = frame.OutputRegister();
-    //    }
-    //}
+    [TestClass]
+    public class FrameTest
+    {
+        [TestMethod]
+        public void TestToString()
+        {
+            Clock clock = new Clock();
+            TicTok tictok = new TicTok();
+
+            tictok.Init();
+
+            int TState = 0;
+            AReg areg = new AReg();
+            TReg treg = new TReg();
+            BReg breg = new BReg();
+            CReg creg = new CReg();
+            IReg ireg = new IReg();
+
+            IPort1 port1 = new IPort1();
+            IPort2 port2 = new IPort2();
+            OReg3 oreg3 = new OReg3();
+            OReg4 oreg4 = new OReg4();
+
+            HexadecimalDisplay hexadecimalDisplay = new HexadecimalDisplay(ref oreg3);
+
+            MDR mdr = new MDR();
+            RAM ram = new RAM();
+
+            mdr.SetRefToRAM(ref ram);
+            ram.SetRefToMDR(ref mdr);
+
+            ALU alu = new ALU(ref areg, ref treg);
+            Flag flagReg = new Flag(ref alu);
+            PC pc = new PC(ref flagReg);
+            MAR mar = new MAR(ref ram);
+            SEQ seq = SEQ.Instance();
+
+            Wbus.Instance().Value = string.Concat(Enumerable.Repeat('0', 16));
+
+            Instruction currentInstruction = new Instruction
+            {
+                OpCode = "ADD B",
+                BinCode = "10000000",
+                TStates = 4,
+                AffectsFlags = true,
+                AddressingMode = AddressingMode.Register,
+                Bytes = 1
+            };
+
+            Frame frame = new Frame(currentInstruction, TState, port1, port2, pc, mar, ram,
+                                    ram.RAMDump(), mdr, ireg, SEQ.Instance(),
+                                    Wbus.Instance().Value, areg, alu, flagReg,
+                                    treg, breg, creg, oreg3, oreg4, hexadecimalDisplay);
+
+            _ = frame.ToString();
+            _ = frame.OutputRegister();
+        }
+    }
 }
\ No newline at end of file
diff --git a/SAP1EMU.SAP2.Lib.Test/ProgramTest.cs b/SAP1EMU.SAP2.Lib.Test/ProgramTest.cs
index 326f563f..8fc3c199 100644
--- a/SAP1EMU.SAP2.Lib.Test/ProgramTest.cs
+++ b/SAP1EMU.SAP2.Lib.Test/ProgramTest.cs
@@ -2,88 +2,74 @@
 
 using System;
 using System.Collections.Generic;
+using System.Linq;
 
 namespace SAP1EMU.SAP2.Lib.Test
 {
-    //[TestClass]
-    //public class ProgramTest
-    //{
-    //    [TestMethod]
-    //    public void TestCtorReg()
-    //    {
-    //        // Test 2
-    //        try
-    //        {
-    //            List RamContentsData = new List
-    //            {
-    //                "10101010",
-    //                "01010101",
-    //                "10101010",
-    //                "01010101",
-    //                "10101010",
-    //                "01010101",
-    //                "10101010"
-    //            };
-    //            RAMProgram program = new RAMProgram(RamContentsData);
+    [TestClass]
+    public class ProgramTest
+    {
+        [TestMethod]
+        public void TestCtorReg()
+        {
+            // Test 2
+            try
+            {
+                List RamContentsData = new List
+                {
+                    "10101010",
+                    "01010101",
+                    "10101010",
+                    "01010101",
+                    "10101010",
+                    "01010101",
+                    "10101010"
+                };
 
-    //            List RamContentsResults = program.RamContents;
+                RAMProgram program = new RAMProgram(RamContentsData);
 
-    //            if (RamContentsResults.Count != 15)
-    //            {
-    //                Assert.Fail();
-    //            }
-    //            // Make sure the program copied correctly
-    //            for (int i = 0; i < RamContentsData.Count; i++)
-    //            {
-    //                Assert.IsTrue(RamContentsResults[i] == RamContentsData[i], $"At index {i}, RamContentsResults != RamContentsData");
-    //            }
-    //            // Make sure the end of the program is padded with 0's
-    //            for (int i = RamContentsData.Count; i < 15; i++)
-    //            {
-    //                Assert.IsTrue(RamContentsResults[i] == "00000000");
-    //            }
-    //        }
-    //        catch (ArgumentOutOfRangeException e)
-    //        {
-    //            Assert.Fail(e.ToString());
-    //        }
-    //    }
+                List RamContentsResults = program.RamContents;
 
-    //    [TestMethod]
-    //    public void TestCtorOverflow()
-    //    {
-    //        try
-    //        {
-    //            List RamContentsData = new List
-    //            {
-    //                "10101010",
-    //                "01010101",
-    //                "10101010",
-    //                "01010101",
-    //                "10101010",
-    //                "01010101",
-    //                "10101010",
-    //                "01010101",
-    //                "10101010",
-    //                "01010101",
-    //                "10101010",
-    //                "01010101",
-    //                "10101010",
-    //                "01010101",
-    //                "01010101",
-    //                "01010101",
-    //                "01010101"
-    //            };
+                // Make sure the program copied correctly
+                for (int i = 0; i < RamContentsData.Count; i++)
+                {
+                    Assert.IsTrue(RamContentsResults[i] == RamContentsData[i], $"At index {i}, RamContentsResults != RamContentsData");
+                }
+                // Make sure the end of the program is padded with 0's
+                for (int i = RamContentsData.Count; i < 0xFFFF; i++)
+                {
+                    Assert.IsTrue(RamContentsResults[i] == "00000000");
+                }
+            }
+            catch (ArgumentOutOfRangeException e)
+            {
+                Assert.Fail(e.ToString());
+            }
+        }
 
-    //            RAMProgram program = new RAMProgram(RamContentsData);
+        [TestMethod]
+        public void TestCtorOverflow()
+        {
+            try
+            {
+                Random random = new Random();
+                List RamContentsData = new List();
 
-    //            Assert.Fail("Ctor did not catch overflow");
-    //        }
-    //        catch (ArgumentOutOfRangeException e)
-    //        {
-    //            System.Console.Out.WriteLine(e);
-    //            Assert.IsTrue(true);
-    //        }
-    //    }
-    //}
+                // Just fill up ram with random data for the heck of it
+                for (int i = 0; i <= 0xFFFF; i++)
+                {
+                    RamContentsData.Add(string.Join("", Convert.ToString(random.Next(), 2).PadLeft(8).Take(8)));
+                }
+
+                RAMProgram program = new RAMProgram(RamContentsData);
+
+                Assert.Fail("Ctor did not catch overflow");
+            }
+            catch (ArgumentOutOfRangeException e)
+            {
+                Console.Out.WriteLine(e);
+                Assert.IsTrue(true);
+            }
+        }
+    }
 }
\ No newline at end of file
diff --git a/SAP1EMU.SAP2.Lib.Test/SAP1EMU.SAP2.Lib.Test.csproj b/SAP1EMU.SAP2.Lib.Test/SAP1EMU.SAP2.Lib.Test.csproj
index 3cc9dfd7..f812f8ba 100644
--- a/SAP1EMU.SAP2.Lib.Test/SAP1EMU.SAP2.Lib.Test.csproj
+++ b/SAP1EMU.SAP2.Lib.Test/SAP1EMU.SAP2.Lib.Test.csproj
@@ -13,8 +13,8 @@
     
   
   
-    
+    
       Always
-    
+    
   
 
diff --git a/SAP1EMU.SAP2.Lib.Test/SAP2InstructionSets.json b/SAP1EMU.SAP2.Lib.Test/SAP2InstructionSets.json
deleted file mode 100644
index 61015119..00000000
--- a/SAP1EMU.SAP2.Lib.Test/SAP2InstructionSets.json
+++ /dev/null
@@ -1,761 +0,0 @@
-[
-  {
-    "SetName": "Malvino",
-    "SetDescription": "The full intruction set for the SAP1Emu Project.",
-    "Instructions": [
-      {
-        "OpCode": "ADD B",
-        "BinCode": "10000000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ADD C",
-        "BinCode": "10000001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANA B",
-        "BinCode": "10100000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANA C",
-        "BinCode": "10100001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANI",
-        "BinCode": "11100110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "CALL",
-        "BinCode": "11001101",
-        "TStates": 18,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "CMA",
-        "BinCode": "00101111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR A",
-        "BinCode": "00111101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR B",
-        "BinCode": "00000101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR C",
-        "BinCode": "00001101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "HLT",
-        "BinCode": "01110110",
-        "TStates": 5,
-        "AffectsFlags": false,
-        "AddressingMode": "None",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "IN",
-        "BinCode": "11011011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR A",
-        "BinCode": "00111100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR B",
-        "BinCode": "00000100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR C",
-        "BinCode": "00001100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JM",
-        "BinCode": "11111010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JMP",
-        "BinCode": "11000011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JNZ",
-        "BinCode": "11000010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JZ",
-        "BinCode": "11001010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "LDA",
-        "BinCode": "00111010",
-        "TStates": 13,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV A,B",
-        "BinCode": "01111000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV A,C",
-        "BinCode": "01111001",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV B,A",
-        "BinCode": "01000111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV B,C",
-        "BinCode": "01000001",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV C,A",
-        "BinCode": "01001111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV C,B",
-        "BinCode": "01001000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI A,",
-        "BinCode": "00111110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI B,",
-        "BinCode": "00000110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI C,",
-        "BinCode": "00001110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "NOP",
-        "BinCode": "00000000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "None",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORA B",
-        "BinCode": "10110000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORA C",
-        "BinCode": "10110001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORI",
-        "BinCode": "11110110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "OUT",
-        "BinCode": "11010011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RAL",
-        "BinCode": "00010111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RAR",
-        "BinCode": "00011111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RET",
-        "BinCode": "11001001",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "STA",
-        "BinCode": "00110010",
-        "TStates": 13,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "SUB B",
-        "BinCode": "10010000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "SUB C",
-        "BinCode": "10010001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRA B",
-        "BinCode": "10101000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRA C",
-        "BinCode": "10101001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRI",
-        "BinCode": "11101110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      }
-    ]
-  }
-]
\ No newline at end of file
diff --git a/SAP1EMU.SAP2.Lib/Components/RAM.cs b/SAP1EMU.SAP2.Lib/Components/RAM.cs
index 71400792..6a8ae62d 100644
--- a/SAP1EMU.SAP2.Lib/Components/RAM.cs
+++ b/SAP1EMU.SAP2.Lib/Components/RAM.cs
@@ -9,7 +9,7 @@ public class RAM : IObserver
         private List RamContents = new List();
 
         private string MARContents { get; set; }
-        public string RegContent { get; private set; }
+        public string RegContent { get; private set; } = "00000000";
 
         private MDR mdrReg;
 
@@ -55,21 +55,21 @@ public void LoadProgram(RAMProgram rp)
 
         public string GetWordAt(string addr)
         {
-            int index = Convert.ToInt32(addr, 2);
-            if (index < MIN_RAM_ADDRESS || index > MAX_RAM_ADDRESS)
-            {
-                throw new ArgumentOutOfRangeException($"RAM Index Error - Addr with value {index} is not inbetween the range of {MIN_RAM_ADDRESS}-{MAX_RAM_ADDRESS}");
-            }
+            int index = Convert.ToInt32(addr, 2); // Needs to be from 0x0800 to 0xFFFF
+            //if (index < MIN_RAM_ADDRESS || index > MAX_RAM_ADDRESS)
+            //{
+            //    throw new ArgumentOutOfRangeException($"RAM Index Error - Addr with value {index} is not inbetween the range of {MIN_RAM_ADDRESS}-{MAX_RAM_ADDRESS}");
+            //}
             return RamContents[index];
         }
 
         public void SetWordAt(string addr, string word)
         {
             int index = Convert.ToInt32(addr, 2);
-            if (index < MIN_RAM_ADDRESS || index > MAX_RAM_ADDRESS)
-            {
-                throw new ArgumentOutOfRangeException($"RAM Index Error - Addr with value {index} is not inbetween the range of {MIN_RAM_ADDRESS}-{MAX_RAM_ADDRESS}");
-            }
+            //if (index < MIN_RAM_ADDRESS || index > MAX_RAM_ADDRESS)
+            //{
+            //    throw new ArgumentOutOfRangeException($"RAM Index Error - Addr with value {index} is not inbetween the range of {MIN_RAM_ADDRESS}-{MAX_RAM_ADDRESS}");
+            //}
             RamContents[index] = word;
         }
 
diff --git a/SAP1EMU.SAP2.Lib/Components/SEQ.cs b/SAP1EMU.SAP2.Lib/Components/SEQ.cs
index 1ecc5b74..615c7e05 100644
--- a/SAP1EMU.SAP2.Lib/Components/SEQ.cs
+++ b/SAP1EMU.SAP2.Lib/Components/SEQ.cs
@@ -25,11 +25,14 @@ public class SEQ
         /// CP EP LM_ CE_ LI_ EI_ LA_ EA SU EU LB_ LO_ |  LR_ LP_ | 0bXXX (Jump Code)
         /// 
         /// 
-        private string _controlWord 
+        private string _controlWord = "";
+        private string _controlWordSignals 
         {
-            get => _controlWord;
+            get { return _controlWord; }
             set
             {
+                _controlWord = value;
+
                 //PC
                 ControlWord["CP"] = value[0..1];
                 ControlWord["EP"] = value[1..2];
@@ -52,38 +55,38 @@ private string _controlWord
                 ControlWord["EMDR"] = value[10..11];
 
                 //Registers/Flag/ALU Output
-                ControlWord["LA_"] = value[12..13];
-                ControlWord["EA"] = value[13..14];
+                ControlWord["LA_"] = value[11..12];
+                ControlWord["EA"] = value[12..13];
 
-                ControlWord["LT_"] = value[14..15];
-                ControlWord["ET"] = value[15..16];
+                ControlWord["LT_"] = value[13..14];
+                ControlWord["ET"] = value[14..15];
 
-                ControlWord["LB_"] = value[16..17];
-                ControlWord["EB"] = value[17..18];
+                ControlWord["LB_"] = value[15..16];
+                ControlWord["EB"] = value[16..17];
 
-                ControlWord["LC_"] = value[18..19];
-                ControlWord["EC"] = value[19..29];
+                ControlWord["LC_"] = value[17..18];
+                ControlWord["EC"] = value[18..19];
 
-                ControlWord["LF"] = value[20..21];
+                ControlWord["LF"] = value[19..20];
 
-                ControlWord["EU"] = value[21..22];
+                ControlWord["EU"] = value[20..21];
 
                 //Output
-                ControlWord["L03_"] = value[22..23];
-                ControlWord["L04_"] = value[23..24];
+                ControlWord["L03_"] = value[21..22];
+                ControlWord["L04_"] = value[22..23];
 
                 //ALU
-                ControlWord["ALU"] = value[24..29];
+                ControlWord["ALU"] = value[23..28];
 
                 //Jump
-                ControlWord["JC"] = value[29..32];
+                ControlWord["JC"] = value[28..31];
 
                 //Output to upper byte
-                ControlWord["UB"] = value[32..33];
-                ControlWord["CLR"] = value[33..34];
+                ControlWord["UB"] = value[31..32];
+                ControlWord["CLR"] = value[32..33];
 
                 // Hardcode PC address locations
-                ControlWord["RTNA"] = value[34..35];
+                ControlWord["RTNA"] = value[33..34];
             }
         }
             
@@ -101,10 +104,10 @@ private string _controlWord
         public void UpdateControlWordReg(int TState, string instructionBinaryCode)
         {
             int hash = HashKey(TState, instructionBinaryCode);
-            _controlWord = ControlTable[hash];
+            _controlWordSignals = ControlTable[hash];
 
             //Beginning of a new instruction
-            if(TState == 1)
+            if (TState == 1)
             {
                 executedInstructions.Add(instructionBinaryCode);
             }
@@ -114,7 +117,7 @@ public void UpdateControlWordReg(int TState, string instructionBinaryCode)
             {
                 lastInstructionBinary = executedInstructions[^2]; //similar to count - 2
 
-                Instruction? instruction = instructionsThatModifyNextInstruction.Find(i => string.Equals(i.BinCode, lastInstructionBinary, StringComparison.Ordinal));
+                Instruction? instruction = instructionsThatModifyNextInstruction.FirstOrDefault(i => i.BinCode.Equals(lastInstructionBinary, StringComparison.Ordinal));
 
                 if (instruction != null && instruction.UpdatedFetchCycleStates != null)
                 {
@@ -123,7 +126,7 @@ public void UpdateControlWordReg(int TState, string instructionBinaryCode)
                     //If the code is empty then do nothing to the microcode otherwise modify the control word.
                     if (!string.IsNullOrEmpty(updatedMicroCode[TState]))
                     {
-                        _controlWord = updatedMicroCode[TState];
+                        _controlWordSignals = updatedMicroCode[TState];
                     }
                 }
             }
@@ -153,7 +156,7 @@ public void Load(InstructionSet iset)
                 }
             }
 
-            _instance._controlWord = ControlTable[HashKey(4, "00000000")]; // sets the default to a NOP
+            _instance._controlWordSignals = ControlTable[HashKey(4, "00000000")]; // sets the default to a NOP
         }
 
         // Singleton Pattern
@@ -161,40 +164,41 @@ private SEQ()
         {
             ControlWord = new Dictionary(StringComparer.Ordinal)
             {
-                { "CP", "" },    //Increment PC
-                { "EP", "" },    //Enable PC
-                { "LP_", "" },   //Load PC
-
-                { "LI_", ""},    //Load IR
-
-                { "EIP1", "" },  //Enable Input Port 1
-                { "EIP2", "" },  //Enable Input Port 2
-
-                { "LA_", "" },   //Load Accumulator
-                { "EA", "" },    //Enable Accumulator
-                { "LT_", "" },   //Load Temp
-                { "ET", "" },    //Enable Temp
-                { "LB_", "" },   //Load B
-                { "EB", ""},     //Enable B
-                { "LC_", "" },   //Load C
-                { "EC", "" },    //Enable C
-                { "LF", ""},     //Load flag
-                { "EU", "" },    //Enable ALU
-                { "ALU", "" },   //ALU Control flags
-                { "JC", "" },    //Jump Control flags
-
-                { "LM_", "" },   //Load RAM (MAR)
-                { "EM_", "" },   //Enable RAM
-                { "LR_", "" },   //Load RAM from MDR
-                { "LMDR_", "" }, //Load Memory Data Register
-                { "EMDR", "" },  //Enable Memory Data Register
-
-                { "LO3_", "" },  //Load Output port 3
-                { "LO4_", "" },  //Load Output port 4
-
-                { "UB", "" },    //take bus upper byte if on or output to bus upper byte
-                { "CLR", "" },   //Clear bus value when outputting to bus
-                { "RTNA", "" }   //Return Address => Marks whether to make MAR point to 0xFFFE or 0xFFFF for pc contents in memory
+                { "CP", "0" },    //Increment PC
+                { "EP", "0" },    //Enable PC
+                { "LP_", "1" },   //Load PC
+
+                { "LI_", "1"},    //Load IR
+
+                { "EIP1", "0" },  //Enable Input Port 1
+                { "EIP2", "0" },  //Enable Input Port 2
+
+                { "LM_", "1" },   //Load RAM (MAR)
+                { "EM_", "1" },   //Enable RAM
+                { "LR_", "1" },   //Load RAM from MDR
+                { "LMDR_", "1" }, //Load Memory Data Register
+                { "EMDR", "0" },  //Enable Memory Data Register
+
+                { "LA_", "1" },   //Load Accumulator
+                { "EA", "0" },    //Enable Accumulator
+                { "LT_", "1" },   //Load Temp
+                { "ET", "0" },    //Enable Temp
+                { "LB_", "1" },   //Load B
+                { "EB", "0"},     //Enable B
+                { "LC_", "1" },   //Load C
+                { "EC", "0" },    //Enable C
+                { "LF", "0"},     //Load flag
+                { "EU", "0" },    //Enable ALU
+
+                { "LO3_", "1" },  //Load Output port 3
+                { "LO4_", "1" },  //Load Output port 4
+
+                { "ALU", "00000" },   //ALU Control flags
+                { "JC", "000" },    //Jump Control flags
+
+                { "UB", "0" },    //take bus upper byte if on or output to bus upper byte
+                { "CLR", "0" },   //Clear bus value when outputting to bus
+                { "RTNA", "0" }   //Return Address => Marks whether to make MAR point to 0xFFFE or 0xFFFF for pc contents in memory
             };
         }
 
@@ -211,7 +215,7 @@ public static SEQ Instance()
 
         public override string ToString()
         {
-            return _controlWord;
+            return _controlWordSignals;
         }
     }
 }
\ No newline at end of file
diff --git a/SAP1EMU.SAP2.Lib/Frame.cs b/SAP1EMU.SAP2.Lib/Frame.cs
index 188040f4..d3d733e8 100644
--- a/SAP1EMU.SAP2.Lib/Frame.cs
+++ b/SAP1EMU.SAP2.Lib/Frame.cs
@@ -11,57 +11,80 @@ namespace SAP1EMU.SAP2.Lib
     public class Frame
     {
         public string Instruction { get; private set; } = "???";
+        private Instruction InstructionData { get; set; }
         public int TState { get; private set; } = 0;
-        public string AReg { get; private set; } = "0000 0000";
-        public string BReg { get; private set; } = "0000 0000";
+
+        // left side of computer
+        public string Input_Port_1 { get; private set; } = "0000 0000";
+        public string Input_Port_2 { get; private set; } = "0000 0000";
+
+        public string PC { get; private set; } = "0000 0000 0000 0000";
+
+        public string MAR { get; private set; } = "0000 0000 0000 0000";
+        public string RAM_Reg { get; private set; } = "0000 0000 0000 0000";
+        public List RAM { get; private set; } // The reason this is here is that the RAM might change if a STA simular command is issued.
+        public string MDR { get; private set; } = "0000 0000";
+
         public string IReg { get; private set; } = "0000 0000";
-        public string IRegShort { get; private set; } = "0000 0000";
-        public string MReg { get; private set; } = "0000 0000";
-        public string OReg { get; private set; } = "0000 0000";
-        public string PC { get; private set; } = "0000";
-        public string ALU { get; private set; } = "0000 0000";
+
         public string SEQ { get; private set; } = "0000 0000";
-        public string WBus { get; private set; } = "0000 0000";
-        public string RAM_Reg { get; private set; } = "0000 0000";
+
+        // center
+        public string WBus { get; private set; } = "0000 0000 0000 0000";
+
+        // right side of computer
+        public string AReg { get; private set; } = "0000 0000";
+
+        public string ALU { get; private set; } = "0000 0000";
+        public string Flags { get; private set; } = "0000 0000";
         public string Overflow_Flag { get; private set; } = "0";
         public string Underflow_Flag { get; private set; } = "0";
         public string Zero_Flag { get; private set; } = "0";
 
-        public List RAM { get; private set; } // The reason this is here is that the RAM might change if a STA simular command is issued.
-
-        public Frame(string instruction, int TState, AReg areg, BReg breg, IReg ireg, MAR mreg, OReg3 oreg, PC pc, ALU alu, List ramContents, RAM ram, SEQ seq, string wbus_string, Flag flags, IDecoder decoder, string SetName = "SAP1EMU")
+        public string TReg { get; private set; } = "0000 0000";
+        public string BReg { get; private set; } = "0000 0000";
+        public string CReg { get; private set; } = "0000 0000";
+        
+        public string OReg3 { get; private set; } = "0000 0000";
+        public string HexadecimalDisplay { get; private set; } = "00";
+
+        public string OReg4 { get; private set; } = "0000 0000";
+        
+
+        public Frame(Instruction instruction, int TState, IPort1 ip1, IPort2 ip2, PC pc, MAR mar, RAM ram,
+                     List ramContents, MDR mdr, IReg ireg, SEQ seq, string wbus_string,
+                     AReg areg, ALU alu, Flag flagReg, TReg treg, BReg breg, CReg creg,
+                     OReg3 oreg3, OReg4 oreg4, HexadecimalDisplay hexadecimalDisplay)
         {
-            this.RAM = new List();
+            InstructionData = instruction;
 
             this.TState = TState;
 
             this.AReg = areg.ToString_Frame_Use();
             this.BReg = breg.ToString_Frame_Use();
-            this.IRegShort = ireg.RegContent;
             this.IReg = ireg.ToString_Frame_Use();  // The real ToString() is in use with a substring in it.  This is needed for proper operation
-            this.MReg = mreg.ToString_Frame_Use();
-            this.OReg = oreg.ToString_Frame_Use();
-            this.PC = pc.ToString().Substring(4, 4);
+            this.MAR = mar.ToString_Frame_Use();
+            this.OReg3 = oreg3.ToString_Frame_Use();
+            this.PC = pc.RegContent;
             this.ALU = alu.ToString();
             this.WBus = wbus_string;
+            this.HexadecimalDisplay = hexadecimalDisplay.RegContent;
 
-            foreach (string s in ramContents)
-            {
-                RAM.Add(s);
-            }
+            this.RAM = ramContents;
 
             this.SEQ = seq.ToString();
             this.WBus = wbus_string; // I didnt want to mess with the Singleton in the frame, so the value will just be passed as a string
             this.RAM_Reg = ram.ToString_Frame_Use();
+            this.Flags = flagReg.RegContent;
 
-            if (instruction.Length == 0)
+            if (instruction == null)
             {
                 this.IReg = "???";
             }
 
             if (TState > 3)
             {
-                Instruction = decoder.Decode(IReg, SetName);
+                Instruction = InstructionData.OpCode;
             }
             else
             {
@@ -69,38 +92,17 @@ public Frame(string instruction, int TState, AReg areg, BReg breg, IReg ireg, MA
             }
         }
 
-        // TODO - Repleace with something in the LIB OpCodeLoader
-        // TODO -  is the still used? I think I replaced this somewhere else in the code
-        private string InstuctionDecode(string BinInstruction, int TState)
-        {
-            List KnownInstructions = new List { "LDA", "ADD", "SUB", "STA", "JMP", "JEQ", "", "", "", "JIC", "", "", "", "", "OUT", "HLT" };
-            string temp = KnownInstructions[BinConverter.Bin4ToInt(BinInstruction)];
-
-            if (TState < 4)
-            {
-                return "???";
-            }
-            if (!string.IsNullOrEmpty(temp))
-            {
-                return temp;
-            }
-            else
-            {
-                return BinInstruction;
-            }
-        }
-
         public string OutputRegister()
         {
             StringBuilder sb = new StringBuilder();
             StringWriter tw = new StringWriter(sb);
 
-            int unsigned_ouput = BinConverter.Bin8ToInt(OReg);
+            int unsigned_ouput = BinConverter.Bin8ToInt(OReg3);
 
             int signed_output = 0;
-            if (OReg != null)
+            if (OReg3 != null)
             {
-                if (OReg[0] == '1')
+                if (OReg3.StartsWith('1'))
                 {
                     signed_output = -1 * (255 - unsigned_ouput + 1);
                 }
@@ -109,12 +111,12 @@ public string OutputRegister()
                     signed_output = unsigned_ouput;
                 }
             }
-            if (string.IsNullOrEmpty(OReg))
+            if (string.IsNullOrEmpty(OReg3))
             {
-                OReg = "00000000";
+                OReg3 = "00000000";
             }
             tw.WriteLine($"************************************************************");//60
-            tw.WriteLine($"* Output: {OReg}".PadRight(59) + "*");
+            tw.WriteLine($"* Output: {OReg3}".PadRight(59) + "*");
             tw.WriteLine("************************************************************");
 
             tw.Flush();
@@ -126,12 +128,12 @@ public override string ToString()
             StringBuilder sb = new StringBuilder();
             StringWriter tw = new StringWriter(sb);
 
-            int unsigned_ouput = BinConverter.Bin8ToInt(OReg);
+            int unsigned_ouput = BinConverter.Bin8ToInt(OReg3);
 
             int signed_output = 0;
-            if (OReg != null)
+            if (OReg3 != null)
             {
-                if (OReg[0] == '1')
+                if (OReg3.StartsWith('1'))
                 {
                     signed_output = -1 * (255 - unsigned_ouput + 1);
                 }
@@ -142,12 +144,15 @@ public override string ToString()
             }
 
             tw.WriteLine($"************************************************************");//60
-            tw.WriteLine($"* Instruction: {InstuctionDecode(IRegShort, TState)}     TState: {TState}                           *");
+            tw.WriteLine($"* Instruction: ${InstructionData.OpCode}     TState: {TState}".PadRight(59) + "*");
             tw.WriteLine("************************************************************");
-            tw.WriteLine($"* PC:         {PC}              A Register:      {AReg}".PadRight(59) + "*");
-            tw.WriteLine($"* MAR:        {MReg}              B Register:      {BReg}".PadRight(59) + "*");
-            tw.WriteLine($"* RAM:        {RAM_Reg}          ALU:             {ALU}".PadRight(59) + "*");
-            tw.WriteLine($"* I Register: {IReg}          Output Register: {OReg}".PadRight(59) + "*");
+            tw.WriteLine($"* Input Port 1: {Input_Port_1}       A Register:    {AReg}   *");
+            tw.WriteLine($"* Input Port 2: {Input_Port_2}       ALU:    {ALU}       Flags: {Flags} *");
+            tw.WriteLine($"* PC:         {PC}              Temp Register:      {TReg}".PadRight(59) + "*");
+            tw.WriteLine($"* MAR:        {MAR}              B Register:      {BReg}".PadRight(59) + "*");
+            tw.WriteLine($"* RAM:        {RAM_Reg}          C Register:      {CReg}".PadRight(59) + "*");
+            tw.WriteLine($"* MDR:        {MDR}           Output Register 3: {OReg3}      Display:    {HexadecimalDisplay}".PadRight(59) + "*");
+            tw.WriteLine($"* I Register: {IReg}          Output Register 4: {OReg4}".PadRight(59) + "*");
             tw.WriteLine($"* Sequencer:  {SEQ}      ".PadRight(59) + "*");
             tw.WriteLine($"************************************************************");
             tw.WriteLine($"* Output Unsigned: {unsigned_ouput}".PadRight(59) + "*");
diff --git a/SAP1EMU.SAP2.Lib/RAMProgram.cs b/SAP1EMU.SAP2.Lib/RAMProgram.cs
index a00fab96..bbd3f083 100644
--- a/SAP1EMU.SAP2.Lib/RAMProgram.cs
+++ b/SAP1EMU.SAP2.Lib/RAMProgram.cs
@@ -13,7 +13,8 @@ public class RAMProgram
     {
         public List RamContents { get; }
 
-        private readonly int MAX_RAM_SIZE = 0xFFFF;
+        private const int MIN_RAM_ADDRESS = 0x0800;
+        private readonly int MAX_RAM_SIZE = 0xFFFF - MIN_RAM_ADDRESS;
 
         public RAMProgram(List RamContents)
         {
@@ -22,7 +23,7 @@ public RAMProgram(List RamContents)
 
             if (count > MAX_RAM_SIZE)
             {
-                throw new ArgumentOutOfRangeException($"RAM Overflow - More than {0xFFFF} lines of code.");
+                throw new ArgumentOutOfRangeException($"RAM Overflow - More than {MAX_RAM_SIZE} lines of code.");
             }
 
             this.RamContents = RamContents;
diff --git a/SAP1EMU.SAP2.Lib/Registers/AReg.cs b/SAP1EMU.SAP2.Lib/Registers/AReg.cs
index 08c0c17d..220c40f8 100644
--- a/SAP1EMU.SAP2.Lib/Registers/AReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/AReg.cs
@@ -15,7 +15,7 @@ private void Exec(TicTok tictok)
             if (string.Equals(cw["EA"], "1", StringComparison.Ordinal) & tictok.ClockState == TicTok.State.Tic)
             {
                 // Send A to the WBus while checking if we want to output to the bus upper or lower 8 bits
-                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(cw["UB"]), Convert.ToBoolean(cw["CLR"]));
+                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(Convert.ToInt16(cw["UB"])), Convert.ToBoolean(Convert.ToInt16(cw["CLR"])));
             }
 
             // Active Low, Pull on Tok
diff --git a/SAP1EMU.SAP2.Lib/Registers/BReg.cs b/SAP1EMU.SAP2.Lib/Registers/BReg.cs
index f77a2d64..f14e83c1 100644
--- a/SAP1EMU.SAP2.Lib/Registers/BReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/BReg.cs
@@ -15,7 +15,7 @@ private void Exec(TicTok tictok)
             if (string.Equals(cw["EB"], "1", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tic)
             {
                 // Send B to the WBus
-                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(cw["UB"]), Convert.ToBoolean(cw["CLR"]));
+                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(Convert.ToInt16(cw["UB"])), Convert.ToBoolean(Convert.ToInt16(cw["CLR"])));
             }
 
             // Active Low, Pull on Tok
diff --git a/SAP1EMU.SAP2.Lib/Registers/CReg.cs b/SAP1EMU.SAP2.Lib/Registers/CReg.cs
index 231afbde..129f722e 100644
--- a/SAP1EMU.SAP2.Lib/Registers/CReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/CReg.cs
@@ -15,7 +15,7 @@ private void Exec(TicTok tictok)
             if (string.Equals(cw["EC"], "1", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tic)
             {
                 // Send C to the WBus
-                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(cw["UB"]), Convert.ToBoolean(cw["CLR"]));
+                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(Convert.ToInt16(cw["UB"])), Convert.ToBoolean(Convert.ToInt16(cw["CLR"])));
             }
 
             // Active Low, Pull on Tok
diff --git a/SAP1EMU.SAP2.Lib/Registers/Flag.cs b/SAP1EMU.SAP2.Lib/Registers/Flag.cs
index 8d680ace..657e6d10 100644
--- a/SAP1EMU.SAP2.Lib/Registers/Flag.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/Flag.cs
@@ -1,4 +1,5 @@
 using SAP1EMU.SAP2.Lib.Components;
+using SAP1EMU.SAP2.Lib.Utilities;
 using System;
 using System.Collections.Generic;
 using System.Text;
@@ -8,7 +9,9 @@ namespace SAP1EMU.SAP2.Lib.Registers
     public class Flag : IObserver
     {
         private readonly ALU aluReg;
-        private string RegContent { get; set; }
+
+        //SZ-AC-P-C Flags ('-' is unused bits)
+        public string RegContent { get; private set; }
 
         public Flag(ref ALU aluReg)
         {
@@ -25,11 +28,26 @@ public bool Zero
             get => Convert.ToBoolean(RegContent[1]);
         }
 
+        public bool Parity
+        {
+            get => Convert.ToBoolean(RegContent[5]);
+        }
+
+        public bool Carry
+        {
+            get => Convert.ToBoolean(RegContent[7]);
+        }
+
+        public bool AuxiliaryCarry
+        {
+            get => Convert.ToBoolean(RegContent[3]);
+        }
+
         private void Exec(TicTok tictok)
         {
             var cw = SEQ.Instance().ControlWord;
 
-            if(string.Equals(cw["LF"], "1", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tic)
+            if(cw["LF"].IsActiveHigh() && tictok.ClockState == TicTok.State.Tic)
             {
                 RegContent = aluReg.FlagContent;
             } 
diff --git a/SAP1EMU.SAP2.Lib/Registers/IReg.cs b/SAP1EMU.SAP2.Lib/Registers/IReg.cs
index 42b65b6c..914a25ca 100644
--- a/SAP1EMU.SAP2.Lib/Registers/IReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/IReg.cs
@@ -15,7 +15,7 @@ private void Exec(TicTok tictok)
             // Active Low, Pull on Tok
             if (string.Equals(cw["LI_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
-                RegContent = Wbus.Instance().Value;
+                RegContent = Wbus.Instance().Value[8..];
             }
         }
 
diff --git a/SAP1EMU.SAP2.Lib/Registers/MDR.cs b/SAP1EMU.SAP2.Lib/Registers/MDR.cs
index a8b6e5ef..bce657d7 100644
--- a/SAP1EMU.SAP2.Lib/Registers/MDR.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/MDR.cs
@@ -5,7 +5,7 @@ namespace SAP1EMU.SAP2.Lib.Registers
 {
     public class MDR : IObserver
     {
-        public string RegContent { get; private set; }
+        public string RegContent { get; private set; } = "00000000";
 
         private RAM ram;
 
@@ -36,14 +36,14 @@ private void Exec(TicTok tictok)
             if (string.Equals(cw["EMDR"], "1", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tic)
             {
                 //Wbus.Instance().Value = RegContent;
-                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(cw["UB"]), Convert.ToBoolean(cw["CLR"]));
+                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(Convert.ToInt16(cw["UB"])), Convert.ToBoolean(Convert.ToInt16(cw["CLR"])));
             }
 
             // Active Low, Pull on Tok
             if (string.Equals(cw["LMDR_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
                 //RegContent = Wbus.Instance().Value;
-                RegContent = Multiplexer.Instance().PassThroughToRegister(Convert.ToBoolean(cw["UB"]));
+                RegContent = Multiplexer.Instance().PassThroughToRegister(Convert.ToBoolean(Convert.ToInt16(cw["UB"])));
             }
         }
 
diff --git a/SAP1EMU.SAP2.Lib/Registers/PC.cs b/SAP1EMU.SAP2.Lib/Registers/PC.cs
index ae8f7e9b..0d79b7af 100644
--- a/SAP1EMU.SAP2.Lib/Registers/PC.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/PC.cs
@@ -8,7 +8,7 @@ namespace SAP1EMU.SAP2.Lib.Registers
     public class PC : IObserver
     {
         private readonly Flag flagReg;
-        private string RegContent { get; set; }
+        public string RegContent { get; private set; }
 
         public bool WontJump { get; set; }
 
@@ -33,7 +33,7 @@ public void Exec(TicTok tictok)
             // Active Hi, Push on Tic
             if (string.Equals(cw["EP"], "1", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tic)
             {
-                // Send A to the WBus
+                // Send PC to the WBus
                 Wbus.Instance().Value = RegContent;
             }
 
@@ -46,7 +46,7 @@ public void Exec(TicTok tictok)
 
                 WontJump = jumpType switch
                 {
-                    "001" => true,
+                    "001" => !flagReg.Signed,
                     "010" => true,
                     "011" => true,
                     "100" => true,
diff --git a/SAP1EMU.SAP2.Lib/Registers/TReg.cs b/SAP1EMU.SAP2.Lib/Registers/TReg.cs
index 69e5d824..95000baa 100644
--- a/SAP1EMU.SAP2.Lib/Registers/TReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/TReg.cs
@@ -15,7 +15,7 @@ private void Exec(TicTok tictok)
             if (string.Equals(cw["ET"], "1", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tic)
             {
                 // Send Temp to the WBus
-                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(cw["UB"]), Convert.ToBoolean(cw["CLR"]));
+                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(Convert.ToInt16(cw["UB"])), Convert.ToBoolean(Convert.ToInt16(cw["CLR"])));
             }
 
             // Active Low, Pull on Tok
diff --git a/SAP1EMU.SAP2.Lib/SAP2InstructionSets.json b/SAP1EMU.SAP2.Lib/SAP2InstructionSets.json
index 61015119..ffcf5375 100644
--- a/SAP1EMU.SAP2.Lib/SAP2InstructionSets.json
+++ b/SAP1EMU.SAP2.Lib/SAP2InstructionSets.json
@@ -1,761 +1,755 @@
 [
-  {
-    "SetName": "Malvino",
-    "SetDescription": "The full intruction set for the SAP1Emu Project.",
-    "Instructions": [
-      {
-        "OpCode": "ADD B",
-        "BinCode": "10000000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
+    {
+        "Instructions": [
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10000000",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "ADD B",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10000001",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "ADD C",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10100000",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "ANA B",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10100001",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "ANA C",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": true,
+                "BinCode": "11100110",
+                "Bytes": 2,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "ANI",
+                "TStates": 7,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": false,
+                "BinCode": "11001101",
+                "Bytes": 3,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "CALL",
+                "TStates": 18
+            },
+            {
+                "AddressingMode": "Implied",
+                "AffectsFlags": false,
+                "BinCode": "00101111",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "CMA",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "00111101",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "DCR A",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "00000101",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "DCR B",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "00001101",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "DCR C",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "None",
+                "AffectsFlags": false,
+                "BinCode": "01110110",
+                "Bytes": 1,
+                "MicroCode": [
+                  "0111000111010101010001100000000000",
+                  "1011001111010101010001100000000000",
+                  "0010001011110101010001100000000000",
+                  "0011001111010101010001100000000000",
+                  "0011001111010101010001100000000000"
+                ],
+                "OpCode": "HLT",
+                "TStates": 5
+            },
+            {
+                "AddressingMode": "Direct",
+                "AffectsFlags": false,
+                "BinCode": "11011011",
+                "Bytes": 2,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "IN",
+                "TStates": 10
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "00111100",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "INR A",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "00000100",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "INR B",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "00001100",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "INR C",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": false,
+                "BinCode": "11111010",
+                "Bytes": 3,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "JM",
+                "TStates": 10,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": false,
+                "BinCode": "11000011",
+                "Bytes": 3,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "JMP",
+                "TStates": 10,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": false,
+                "BinCode": "11000010",
+                "Bytes": 3,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "JNZ",
+                "TStates": 10,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": false,
+                "BinCode": "11001010",
+                "Bytes": 3,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "JZ",
+                "TStates": 10,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Direct",
+                "AffectsFlags": false,
+                "BinCode": "00111010",
+                "Bytes": 3,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "LDA",
+                "TStates": 13
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": false,
+                "BinCode": "01111000",
+                "Bytes": 1,
+              "MicroCode": [
+                "0111000111010101010001100000000000",
+                "1011001111010101010001100000000000",
+                "0010001011110101010001100000000000",
+                "0011001111000100110001100000000000"
+              ],
+                "OpCode": "MOV A,B",
+                "TStates": 4
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": false,
+                "BinCode": "01111001",
+                "Bytes": 1,
+              "MicroCode": [
+                "0111000111010101010001100000000000",
+                "1011001111010101010001100000000000",
+                "0010001011110101010001100000000000",
+                "0011001111000100011001100000000000"
+              ],
+                "OpCode": "MOV A,C",
+                "TStates": 4
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": false,
+                "BinCode": "01000111",
+                "Bytes": 1,
+              "MicroCode": [
+                "0111000111010101010001100000000000",
+                "1011001111010101010001100000000000",
+                "0010001011110101010001100000000000",
+                "0011001111011100010001100000000000"
+              ],
+                "OpCode": "MOV B,A",
+                "TStates": 4
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": false,
+                "BinCode": "01000001",
+                "Bytes": 1,
+              "MicroCode": [
+                "0111000111010101010001100000000000",
+                "1011001111010101010001100000000000",
+                "0010001011110101010001100000000000",
+                "0011001111010100011001100000000000"
+              ],
+                "OpCode": "MOV B,C",
+                "TStates": 4
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": false,
+                "BinCode": "01001111",
+                "Bytes": 1,
+              "MicroCode": [
+                "0111000111010101010001100000000000",
+                "1011001111010101010001100000000000",
+                "0010001011110101010001100000000000",
+                "0011001111011101000001100000000000"
+              ],
+                "OpCode": "MOV C,A",
+                "TStates": 4
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": false,
+                "BinCode": "01001000",
+                "Bytes": 1,
+              "MicroCode": [
+                "0111000111010101010001100000000000",
+                "1011001111010101010001100000000000",
+                "0010001011110101010001100000000000",
+                "0011001111010101100001100000000000"
+              ],
+                "OpCode": "MOV C,B",
+                "TStates": 4
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": false,
+                "BinCode": "00111110",
+                "Bytes": 2,
+              "MicroCode": [
+                "0111000111010101010001100000000000",
+                "1011001111010101010001100000000000",
+                "0010001011110101010001100000000000",
+                "0011001111010101010001100000000000",
+                "0111000111010101010001100000000000",
+                "0111001111010101010001100000000000",
+                "0011001011100101010001100000000000"
+              ],
+                "OpCode": "MVI A,",
+                "TStates": 7
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": false,
+                "BinCode": "00000110",
+                "Bytes": 2,
+                "MicroCode": [
+                  "0111000111010101010001100000000000",
+                  "1011001111010101010001100000000000",
+                  "0010001011110101010001100000000000",
+                  "0111000111010101010001100000000000",
+                  "0111001111010101010001100000000000",
+                  "0011001011110100010001100000000000",
+                  "0011001111010101010001100000000000"
+                ],
+                "OpCode": "MVI B,",
+                "TStates": 7
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": false,
+                "BinCode": "00001110",
+                "Bytes": 2,
+                "MicroCode": [
+                  "0111000111010101010001100000000000",
+                  "1011001111010101010001100000000000",
+                  "0010001011110101010001100000000000",
+                  "0111000111010101010001100000000000",
+                  "0111001111010101010001100000000000",
+                  "0011000111110101000001100000000000",
+                  "0011001111010101010001100000000000"
+                ],
+                "OpCode": "MVI C,",
+                "TStates": 7
+            },
+            {
+                "AddressingMode": "None",
+                "AffectsFlags": false,
+                "BinCode": "00000000",
+                "Bytes": 1,
+                "MicroCode": [
+                    "0111000111010101010001100000000000",
+                    "1011001111010101010001100000000000",
+                    "0010001011110101010001100000000000",
+                    "0011001111010101010001100000000000"
+                ],
+                "OpCode": "NOP",
+                "TStates": 4
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10110000",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "ORA B",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10110001",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "ORA C",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": true,
+                "BinCode": "11110110",
+                "Bytes": 2,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "ORI",
+                "TStates": 7,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Direct",
+                "AffectsFlags": false,
+                "BinCode": "11010011",
+                "Bytes": 2,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "OUT",
+                "TStates": 10
+            },
+            {
+                "AddressingMode": "Implied",
+                "AffectsFlags": false,
+                "BinCode": "00010111",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "RAL",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Implied",
+                "AffectsFlags": false,
+                "BinCode": "00011111",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "RAR",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Implied",
+                "AffectsFlags": false,
+                "BinCode": "11001001",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "RET",
+                "TStates": 10,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Direct",
+                "AffectsFlags": false,
+                "BinCode": "00110010",
+                "Bytes": 3,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "STA",
+                "TStates": 13
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10010000",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "SUB B",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10010001",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "SUB C",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10101000",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "XRA B",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Register",
+                "AffectsFlags": true,
+                "BinCode": "10101001",
+                "Bytes": 1,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "XRA C",
+                "TStates": 4,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            },
+            {
+                "AddressingMode": "Immediate",
+                "AffectsFlags": true,
+                "BinCode": "11101110",
+                "Bytes": 2,
+                "MicroCode": [
+                    "",
+                    "",
+                    "",
+                    ""
+                ],
+                "OpCode": "XRI",
+                "TStates": 7,
+                "UpdatedFetchCycleStates": [
+                    "",
+                    "",
+                    ""
+                ]
+            }
         ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ADD C",
-        "BinCode": "10000001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANA B",
-        "BinCode": "10100000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANA C",
-        "BinCode": "10100001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ANI",
-        "BinCode": "11100110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "CALL",
-        "BinCode": "11001101",
-        "TStates": 18,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "CMA",
-        "BinCode": "00101111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR A",
-        "BinCode": "00111101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR B",
-        "BinCode": "00000101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "DCR C",
-        "BinCode": "00001101",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "HLT",
-        "BinCode": "01110110",
-        "TStates": 5,
-        "AffectsFlags": false,
-        "AddressingMode": "None",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "IN",
-        "BinCode": "11011011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR A",
-        "BinCode": "00111100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR B",
-        "BinCode": "00000100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "INR C",
-        "BinCode": "00001100",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JM",
-        "BinCode": "11111010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JMP",
-        "BinCode": "11000011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JNZ",
-        "BinCode": "11000010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "JZ",
-        "BinCode": "11001010",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "LDA",
-        "BinCode": "00111010",
-        "TStates": 13,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV A,B",
-        "BinCode": "01111000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV A,C",
-        "BinCode": "01111001",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV B,A",
-        "BinCode": "01000111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV B,C",
-        "BinCode": "01000001",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV C,A",
-        "BinCode": "01001111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MOV C,B",
-        "BinCode": "01001000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI A,",
-        "BinCode": "00111110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI B,",
-        "BinCode": "00000110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "MVI C,",
-        "BinCode": "00001110",
-        "TStates": 7,
-        "AffectsFlags": false,
-        "AddressingMode": "Register",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "NOP",
-        "BinCode": "00000000",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "None",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORA B",
-        "BinCode": "10110000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORA C",
-        "BinCode": "10110001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "ORI",
-        "BinCode": "11110110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "OUT",
-        "BinCode": "11010011",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RAL",
-        "BinCode": "00010111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RAR",
-        "BinCode": "00011111",
-        "TStates": 4,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "RET",
-        "BinCode": "11001001",
-        "TStates": 10,
-        "AffectsFlags": false,
-        "AddressingMode": "Implied",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "STA",
-        "BinCode": "00110010",
-        "TStates": 13,
-        "AffectsFlags": false,
-        "AddressingMode": "Direct",
-        "Bytes": 3,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "SUB B",
-        "BinCode": "10010000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "SUB C",
-        "BinCode": "10010001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRA B",
-        "BinCode": "10101000",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRA C",
-        "BinCode": "10101001",
-        "TStates": 4,
-        "AffectsFlags": true,
-        "AddressingMode": "Register",
-        "Bytes": 1,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      },
-      {
-        "OpCode": "XRI",
-        "BinCode": "11101110",
-        "TStates": 7,
-        "AffectsFlags": true,
-        "AddressingMode": "Immediate",
-        "Bytes": 2,
-        "MicroCode": [
-          "",
-          "",
-          "",
-          ""
-        ],
-        "UpdatedFetchCycleStates": [
-          "",
-          "",
-          ""
-        ]
-      }
-    ]
-  }
-]
\ No newline at end of file
+        "SetDescription": "The full intruction set for the SAP1Emu Project.",
+        "SetName": "Malvino"
+    }
+]
diff --git a/SAP1EMU.SAP2.Lib/Utilities/ExtensionMethods.cs b/SAP1EMU.SAP2.Lib/Utilities/ExtensionMethods.cs
new file mode 100644
index 00000000..6a3b7446
--- /dev/null
+++ b/SAP1EMU.SAP2.Lib/Utilities/ExtensionMethods.cs
@@ -0,0 +1,16 @@
+using System;
+namespace SAP1EMU.SAP2.Lib.Utilities
+{
+    public static class ExtensionMethods
+    {
+        public static bool IsActiveLow(this string value)
+        {
+            return string.Equals(value, "0", StringComparison.Ordinal);
+        }
+
+        public static bool IsActiveHigh(this string value)
+        {
+            return string.Equals(value, "1", StringComparison.Ordinal);
+        }
+    }
+}
diff --git a/SAP1EMU.sln b/SAP1EMU.sln
index aedf790c..069c3715 100644
--- a/SAP1EMU.sln
+++ b/SAP1EMU.sln
@@ -37,6 +37,8 @@ Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "SAP1EMU.SAP2.Assembler.Test
 EndProject
 Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "SAP1EMU.SAP2.Lib.Test", "SAP1EMU.SAP2.Lib.Test\SAP1EMU.SAP2.Lib.Test.csproj", "{2CDCF8F3-7B5F-4C10-9CD6-E6D9D1FC8A7D}"
 EndProject
+Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "SAP1EMU.SAP2.Engine.Test", "SAP1EMU.SAP2.Engine.Test\SAP1EMU.SAP2.Engine.Test.csproj", "{F147F958-08AA-47C8-9F59-4665B2E2D6E3}"
+EndProject
 Global
 	GlobalSection(SolutionConfigurationPlatforms) = preSolution
 		Debug|Any CPU = Debug|Any CPU
@@ -107,6 +109,14 @@ Global
 		{2CDCF8F3-7B5F-4C10-9CD6-E6D9D1FC8A7D}.Debug|Any CPU.Build.0 = Debug|Any CPU
 		{2CDCF8F3-7B5F-4C10-9CD6-E6D9D1FC8A7D}.Release|Any CPU.ActiveCfg = Release|Any CPU
 		{2CDCF8F3-7B5F-4C10-9CD6-E6D9D1FC8A7D}.Release|Any CPU.Build.0 = Release|Any CPU
+		{0A8B5975-CC04-4131-8229-1BA04AB5B6D0}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
+		{0A8B5975-CC04-4131-8229-1BA04AB5B6D0}.Debug|Any CPU.Build.0 = Debug|Any CPU
+		{0A8B5975-CC04-4131-8229-1BA04AB5B6D0}.Release|Any CPU.ActiveCfg = Release|Any CPU
+		{0A8B5975-CC04-4131-8229-1BA04AB5B6D0}.Release|Any CPU.Build.0 = Release|Any CPU
+		{F147F958-08AA-47C8-9F59-4665B2E2D6E3}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
+		{F147F958-08AA-47C8-9F59-4665B2E2D6E3}.Debug|Any CPU.Build.0 = Debug|Any CPU
+		{F147F958-08AA-47C8-9F59-4665B2E2D6E3}.Release|Any CPU.ActiveCfg = Release|Any CPU
+		{F147F958-08AA-47C8-9F59-4665B2E2D6E3}.Release|Any CPU.Build.0 = Release|Any CPU
 	EndGlobalSection
 	GlobalSection(SolutionProperties) = preSolution
 		HideSolutionNode = FALSE

From 22af3a75f47ec2b32a3e6bb7c76fffab78457029 Mon Sep 17 00:00:00 2001
From: Bryce 
Date: Tue, 29 Dec 2020 20:42:13 -0800
Subject: [PATCH 02/20] Fixes to engine and SEQ

---
 SAP1EMU.SAP2.Engine.Test/EngineTest.cs |  4 +++-
 SAP1EMU.SAP2.Engine/EngineProc.cs      | 32 +++++++++++++++++---------
 SAP1EMU.SAP2.Lib/Components/RAM.cs     |  6 ++---
 SAP1EMU.SAP2.Lib/Components/SEQ.cs     | 10 +++++++-
 SAP1EMU.SAP2.Lib/Registers/OReg3.cs    |  2 +-
 SAP1EMU.SAP2.Lib/Registers/OReg4.cs    |  2 +-
 6 files changed, 38 insertions(+), 18 deletions(-)

diff --git a/SAP1EMU.SAP2.Engine.Test/EngineTest.cs b/SAP1EMU.SAP2.Engine.Test/EngineTest.cs
index 98e82016..ef57aa13 100644
--- a/SAP1EMU.SAP2.Engine.Test/EngineTest.cs
+++ b/SAP1EMU.SAP2.Engine.Test/EngineTest.cs
@@ -30,7 +30,7 @@ public class EngineTest
         [TestMethod]
         public void Test_MVI_MOV_PROG_1()
         {
-            string expectedResult = "00000001";
+            string expectedResult = "00000000";
             List program = new List()
             {
                 "00111110",
@@ -48,6 +48,8 @@ public void Test_MVI_MOV_PROG_1()
 
             string output = engine.GetOutputReg();
 
+            var frames = engine.FrameStack();
+
             Assert.AreEqual(expectedResult, output);
         }
     }
diff --git a/SAP1EMU.SAP2.Engine/EngineProc.cs b/SAP1EMU.SAP2.Engine/EngineProc.cs
index 6dad1cf3..a43eef2e 100644
--- a/SAP1EMU.SAP2.Engine/EngineProc.cs
+++ b/SAP1EMU.SAP2.Engine/EngineProc.cs
@@ -115,24 +115,34 @@ public void Run()
                 TStates = 4 // Since by 4 TStates it should know what instruction it is on
             };
 
+            bool isInstruction = true;
+            int bytesRemaining = 0;
+
             while (clock.IsEnabled)
             {
-                if (TState <= 3)
+                // Log the Instruction
+                if (TState == 4 && bytesRemaining == 0)
                 {
-                    seq.UpdateControlWordReg(TState, "00000000");
+                    currentInstruction = InstructionSet.Instructions.FirstOrDefault(i => i.BinCode.Equals(ireg.RegContent));
+                    isInstruction = currentInstruction != null;
+                    bytesRemaining = currentInstruction?.Bytes - 1 ?? 0;
+                    string iname = currentInstruction?.OpCode ?? "DATA";
+                    int operandVal = Convert.ToInt32(ireg.RegContent, 2);
+                    string hexOperand = "0x" + operandVal.ToString("X");
                 }
-                else
+                else if(TState == 4 && bytesRemaining > 0)
                 {
-                    seq.UpdateControlWordReg(TState, ireg.RegContent);
+                    isInstruction = false;
+                    bytesRemaining -= 1;
                 }
 
-                // Log the Instruction
-                if (TState == 4)
+                if (TState <= 3)
                 {
-                    currentInstruction = InstructionSet.Instructions.FirstOrDefault(i => i.BinCode.Equals(ireg.RegContent));
-                    string iname = currentInstruction.OpCode;
-                    int operandVal = Convert.ToInt32(ireg.RegContent, 2);
-                    string hexOperand = "0x" + operandVal.ToString("X");
+                    seq.UpdateControlWordReg(TState, "00000000");
+                }
+                else
+                {
+                    seq.UpdateControlWordReg(TState, ireg.RegContent, isInstruction);
                 }
 
                 clock.SendTicTok(tictok);
@@ -148,7 +158,7 @@ public void Run()
                 _FrameStack.Add(tempFrame);
 
                 // HLT 
-                if (ireg.ToString() == "01110110" && TState == 5)
+                if (ireg.RegContent.Equals("01110110", StringComparison.Ordinal) && TState == 5)
                 {
                     clock.IsEnabled = false;
                 }
diff --git a/SAP1EMU.SAP2.Lib/Components/RAM.cs b/SAP1EMU.SAP2.Lib/Components/RAM.cs
index 6a8ae62d..7cc00cb6 100644
--- a/SAP1EMU.SAP2.Lib/Components/RAM.cs
+++ b/SAP1EMU.SAP2.Lib/Components/RAM.cs
@@ -36,9 +36,9 @@ private void Exec(TicTok tictok)
             // Active Low, Pull on Tok
             if (string.Equals(cw["LM_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
-                string word = mdrReg.RegContent;
-                SetWordAt(MARContents, word);
-                RegContent = word;
+                //string word = mdrReg.RegContent;
+                //SetWordAt(MARContents, word);
+                //RegContent = word;
             }
         }
 
diff --git a/SAP1EMU.SAP2.Lib/Components/SEQ.cs b/SAP1EMU.SAP2.Lib/Components/SEQ.cs
index 615c7e05..698e8251 100644
--- a/SAP1EMU.SAP2.Lib/Components/SEQ.cs
+++ b/SAP1EMU.SAP2.Lib/Components/SEQ.cs
@@ -101,9 +101,17 @@ private string _controlWordSignals
         /// 
         /// 
         /// 
-        public void UpdateControlWordReg(int TState, string instructionBinaryCode)
+        public void UpdateControlWordReg(int TState, string instructionBinaryCode, bool isInstruction = true)
         {
             int hash = HashKey(TState, instructionBinaryCode);
+
+            // Its the data portion of the instruction that comes after it
+            // Every line of data does not have to be an instruction
+            if(!isInstruction)
+            {
+                return;
+            }
+
             _controlWordSignals = ControlTable[hash];
 
             //Beginning of a new instruction
diff --git a/SAP1EMU.SAP2.Lib/Registers/OReg3.cs b/SAP1EMU.SAP2.Lib/Registers/OReg3.cs
index 09113d21..5905a811 100644
--- a/SAP1EMU.SAP2.Lib/Registers/OReg3.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/OReg3.cs
@@ -5,7 +5,7 @@ namespace SAP1EMU.SAP2.Lib.Registers
 {
     public class OReg3 : IObserver
     {
-        public string RegContent { get; private set; }
+        public string RegContent { get; private set; } = "00000000";
 
         private void Exec(TicTok tictok)
         {
diff --git a/SAP1EMU.SAP2.Lib/Registers/OReg4.cs b/SAP1EMU.SAP2.Lib/Registers/OReg4.cs
index 4c83bca7..5dc1a832 100644
--- a/SAP1EMU.SAP2.Lib/Registers/OReg4.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/OReg4.cs
@@ -5,7 +5,7 @@ namespace SAP1EMU.SAP2.Lib.Registers
 {
     public class OReg4 : IObserver
     {
-        private string RegContent { get; set; }
+        private string RegContent { get; set; } = "00000000";
 
         private void Exec(TicTok tictok)
         {

From c70fc37400d64f795baa506b86cefa1432cfc533 Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sun, 3 Jan 2021 00:50:44 -0800
Subject: [PATCH 03/20] init sap2 layout

---
 SAP1EMU.GUI/Controllers/HomeController.cs |   5 +
 SAP1EMU.GUI/Views/Home/SAP2.cshtml        | 173 +++++++++++++
 SAP1EMU.GUI/Views/Shared/_Layout.cshtml   |   2 +-
 SAP1EMU.GUI/wwwroot/js/Views/SAP2View.js  | 291 ++++++++++++++++++++++
 4 files changed, 470 insertions(+), 1 deletion(-)
 create mode 100644 SAP1EMU.GUI/Views/Home/SAP2.cshtml
 create mode 100644 SAP1EMU.GUI/wwwroot/js/Views/SAP2View.js

diff --git a/SAP1EMU.GUI/Controllers/HomeController.cs b/SAP1EMU.GUI/Controllers/HomeController.cs
index 4f9dffb3..5a5c0ea8 100644
--- a/SAP1EMU.GUI/Controllers/HomeController.cs
+++ b/SAP1EMU.GUI/Controllers/HomeController.cs
@@ -61,6 +61,11 @@ public IActionResult Contributors()
             return View();
         }
 
+        public IActionResult SAP2()
+        {
+            return View();
+        }
+
         public IActionResult TestSignalR()
         {
             return View();
diff --git a/SAP1EMU.GUI/Views/Home/SAP2.cshtml b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
new file mode 100644
index 00000000..bee96260
--- /dev/null
+++ b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
@@ -0,0 +1,173 @@
+
+
+
+
+
+
+
+
SAP-2 Emulator

+
+
+

+
+    

+        

+            
Assembly Editor

+        

+
+        

+            

+                

+                    @Html.TextArea("CodeList", null, new { rows = "20", cols = "80", @class = "codebox", id = "asm_code" })
+                

+
+            

+
+
+        

+    

+    

+        

+            
Emulator Controller

+        

+        

+            

+                

+                    
+                    
+                

+                

+                    
+                

+                

+                    
+                

+            

+            

+                

+                    
+                    
+                    
+                    
+                

+                

+                    

+                        
+                        
+                    

+                

+                

+                    

+                        

+                            ???
+                        

+                        
+                    

+                

+            

+            

+                

+                    

+                        

+                    

+                

+            

+
+
+
+
+
+            

+        

+    

+

+
+

+
+    

+        

+            
SAP-2

+        

+        

+
+            

+                

+                    
Program Counter

+
+                    

+                        

+                            
IPort 1

+                        

+                        

+                            
IPort 2

+                        

+                    

+                    

+                        

+                            
Output 1

+                        

+                        

+                            
Output 2

+                        

+                    

+                    
Display

+
+                    
Instruction Register

+                    
Sequencer

+                    
Flags

+                

+                

+                    

+                        
WBus
0x00 0x00

+                    

+                

+                

+                    
ALU

+
+                    

+
+                        

+                            
MUX
 

+                        

+                        

+                            

+                                

+                                    
A Reg

+                                

+                                

+                                    
T Reg

+                                

+                            

+                            

+                                

+                                    
B Reg

+                                

+                            

+                            

+                                

+                                    
C Reg

+                                

+                            

+                            

+                                

+                                    
MDR

+                                

+                            

+                        

+
+
+
+                    

+                    
RAM

+
+                    
MAR

+                

+                

+                    
RAM

+                    @Html.TextArea("ram_dump", null, new { rows = "16", cols = "20", @class = "codebox", id = "ram_dump" })
+                

+            

+        

+    

+
+

\ No newline at end of file
diff --git a/SAP1EMU.GUI/Views/Shared/_Layout.cshtml b/SAP1EMU.GUI/Views/Shared/_Layout.cshtml
index 49f486ee..35b94d37 100644
--- a/SAP1EMU.GUI/Views/Shared/_Layout.cshtml
+++ b/SAP1EMU.GUI/Views/Shared/_Layout.cshtml
@@ -67,7 +67,7 @@
     

         

             

-                © 2020 - SAP1EMU.WebApp @typeof(SAP1EMU.GUI.Program).Assembly.GetName().Version - Privacy
+                © 2020 - SAP1EMU.WebApp @typeof(SAP1EMU.GUI.Program).Assembly.GetName().Version
 - 
Privacy
                 

                 
Help

             

diff --git a/SAP1EMU.GUI/wwwroot/js/Views/SAP2View.js b/SAP1EMU.GUI/wwwroot/js/Views/SAP2View.js
new file mode 100644
index 00000000..3593bc19
--- /dev/null
+++ b/SAP1EMU.GUI/wwwroot/js/Views/SAP2View.js
@@ -0,0 +1,291 @@
+var asm_editor;
+var ram_dump;
+var frame_stack;
+var interval_slider;
+var interval_time = 500;
+//var playerInstance;
+
+window.onload = function () {
+    interval_slider = document.getElementById("formControlRange");
+
+    asm_editor = CodeMirror.fromTextArea(document.getElementById("asm_code"), {
+        lineNumbers: true,
+        matchBrackets: true,
+        mode: { name: "gas_sap1", architecture: "x86" },
+    });
+
+    //Check when the user is typing
+    asm_editor.on("change", function (cm, obj) { updateGutter(cm); });
+
+    //Check when it updates the DOM so pasting, hitting enter, etc...
+    asm_editor.on("update", function (cm) { updateGutter(cm); });
+
+    ram_dump = CodeMirror.fromTextArea(document.getElementById("ram_dump"), {
+        lineNumbers: true,
+        matchBrackets: true,
+        mode: { name: "gas_sap1", architecture: "x86" },
+        readOnly: true,
+        firstLineNumber: 0,
+        lineNumberFormatter: function (line) { return "0x" + line.toString(16).toLocaleUpperCase(); },
+    });
+
+    initRam();
+    initBoard();
+    setControlButtonsDisabled(true);
+
+    // Setup ComboBox
+    //$.ajax({
+    //    url: "../api/Assembler/supported_sets",
+    //    type: "GET",
+    //    success: function (data) {
+    //        var selectDOM = document.getElementById("langs");
+    //        var options = data;
+
+    //        for (var i = 0; i < options.length; i++) {
+    //            var opt = options[i];
+
+    //            var elem = document.createElement("option");
+    //            elem.text = opt;
+    //            elem.value = opt;
+
+    //            selectDOM.add(elem);
+    //        }
+    //    },
+    //    error: function (request, status, error) {
+    //        alert("SAP1EMU ERROR: JSON CONFIG FILE ERROR:\n" + request.responseText);
+    //    }
+    //});
+
+    // Must be last line of function
+    preloadCode();
+}
+
+
+function initBoard() {
+    //$('#pc-block').html("0000");
+    //$('#wbus-block').html("0000 0000");
+    //$('#areg-block').html("0000 0000");
+    //$('#mar-block').html("0000");
+    //$('#alu-block').html("0000 0000");
+    //$('#ram-block').html("0000 0000");
+    //$('#breg-block').html("0000 0000");
+    //$('#ireg-block').html("0000 0000");
+    //$('#oreg-block').html("0000 0000");
+    //$('#seq-block').html("0011 1110 0011 11");
+    //$('#dis-block').html("0");
+    //$('#carryFlagBox').html("0");
+    //$('#underflowFlagBox').html("0");
+    //$('#zeroFlagBox').html("0");
+}
+
+function updateBoard(frame) {
+    //$('#pc-block').html(frame.pc);
+    //$('#wbus-block').html(frame.wBus.match(/.{1,4}/g).join(' '));
+    //$('#areg-block').html(frame.aReg.match(/.{1,4}/g).join(' '));
+    //$('#mar-block').html(frame.mReg.match(/.{1,4}/g).join(' '));
+    //$('#alu-block').html(frame.alu.match(/.{1,4}/g).join(' '));
+    //$('#ram-block').html(frame.raM_Reg.match(/.{1,4}/g).join(' '));
+    //$('#breg-block').html(frame.bReg.match(/.{1,4}/g).join(' '));
+    //$('#ireg-block').html(frame.iReg.match(/.{1,4}/g).join(' '));
+    //$('#oreg-block').html(frame.oReg.match(/.{1,4}/g).join(' '));
+    //$('#seq-block').html(frame.seq.substring(0, 14).match(/.{1,4}/g).join(' ')); // TODO This substring should be handled at the API level, not the UI level
+    //$('#carryFlagBox').val(frame.overflow_Flag);
+    //$('#underflowFlagBox').val(frame.underflow_Flag);
+    //$('#zeroFlagBox').val(frame.zero_Flag);
+
+    //var posVal = parseInt(frame.oReg, 2);
+    //var negVal = posVal;
+
+    //if (posVal > 127) {
+    //    negVal = (-1) * (256 - posVal);
+    //}
+    //var displayString = "" + posVal;
+    //if (negVal < 0) {
+    //    displayString += " " + negVal;
+    //}
+
+    //$('#dis-block').html(displayString);
+}
+
+function initRam() {
+    // Init RAM Box
+    var ram_string = "";
+
+    for (var i = 0; i < 15; i++) {
+        ram_string += "0000 0000\n";
+    }
+    ram_string += "0000 0000";
+    ram_dump.setValue(ram_string);
+}
+
+function loadRam(ram) {
+    //var tempString = "";
+    //for (var i = 0; i < 16; i++) {
+    //    tempString += ram[i].substring(0, 4);
+    //    tempString += " ";
+    //    tempString += ram[i].substring(4, 8);
+    //    if (i < 15) {
+    //        tempString += "\n";
+    //    }
+    //}
+    //ram_dump.setValue(tempString);
+}
+
+function resetBoard(frame) {
+    //updateBoard(frame);
+
+    ////Change the instruction and tstate to default state
+    //$('#instruction-box').text("???");
+    //$('#tstate-box').val("T1");
+
+    ////Set current frame back to 0 and make progress 0 since its a new program loaded
+    //current_frame = 0;
+    //updateProgressBar(0, frame_stack.length); //In case anyone has a previously loaded program in to know when its loaded.
+}
+
+function LoadIntoRAM() {
+    //var asm_code = asm_editor.getValue().split('\n');
+    //var langChoice = document.getElementById("langs").value;
+
+    //jsonData = JSON.stringify({ CodeList: asm_code, SetName: langChoice });
+    ////console.log(jsonData);
+
+    //$.ajax({
+    //    url: "../api/Emulator",
+    //    type: "POST",
+    //    contentType: 'application/json; charset=UTF-8',
+    //    data: jsonData,
+    //    success: function (data) {
+    //        $('#emulator-out').html('
'); // clear the error msg box
+
+    //        frame_stack = data;
+    //        first_frame = frame_stack[0];
+
+    //        resetBoard(first_frame);
+
+    //        loadRam(first_frame.ram);
+
+    //        return data;
+    //    },
+    //    error: function (request, status, error) {
+    //        initRam();
+    //        $('#emulator-out').html(request.responseText);
+    //    }
+    //});
+
+    //setControlButtonsDisabled(false);
+}
+
+var job_id = null;
+var justPaused = false;
+function play_button_onclick() {
+    //if (job_id == null) {
+    //    $("#play-pause-img").attr("src", "/img/pause-24px.svg");
+    //    job_id = setInterval(frame_advance, interval_time);
+
+    //    // Disable back and next
+    //    $("#back-button").prop('disabled', true);
+    //    $("#next-button").prop('disabled', true);
+    //}
+    //else {
+    //    justPaused = true;
+    //    clearInterval(job_id);
+    //    job_id = null;
+    //    $("#play-pause-img").attr("src", "/img/play_arrow-24px.svg");
+
+    //    // Enable back and next
+    //    $("#back-button").prop('disabled', false);
+    //    $("#next-button").prop('disabled', false);
+    //}
+}
+
+function back_button_onclick() {
+    //frame_reverse();
+}
+
+function next_button_onclick() {
+    //frame_advance();
+}
+
+function reset_button_onclick() {
+    //current_frame = 0;
+    //updateBoard(frame_stack[current_frame]);
+    //loadRam(frame_stack[current_frame].ram);
+    //$("#instruction-box").text(frame_stack[current_frame].instruction);
+    //$("#tstate-box").val('T' + frame_stack[current_frame].tState);
+    //updateProgressBar(current_frame, frame_stack.length);
+}
+
+var current_frame = 0;
+function frame_advance() {
+    //if (current_frame < frame_stack.length - 1) {
+    //    current_frame++;
+    //    updateBoard(frame_stack[current_frame]);
+    //    loadRam(frame_stack[current_frame].ram);
+    //    $("#instruction-box").text(frame_stack[current_frame].instruction);
+    //    $("#tstate-box").val('T' + frame_stack[current_frame].tState);
+
+    //    // Update Progress Bar
+    //    updateProgressBar(current_frame, frame_stack.length);
+    //}
+    //else {
+    //    $('#frameProgressBar').css("width", "100%");
+    //    clearInterval(job_id);
+    //    job_id = null;
+    //}
+
+    ////console.log(frame_stack[current_frame]);
+}
+
+function frame_reverse() {
+    //if (justPaused) {
+    //    current_frame--;
+    //    justPaused = false;
+    //}
+    //if (current_frame > 0) {
+    //    current_frame--;
+    //    updateBoard(frame_stack[current_frame]);
+    //    loadRam(frame_stack[current_frame].ram);
+    //    $("#instruction-box").text(frame_stack[current_frame].instruction);
+    //    $("#tstate-box").val('T' + frame_stack[current_frame].tState);
+
+    //    // Update Progress Bar
+    //    updateProgressBar(current_frame, frame_stack.length);
+    //}
+}
+
+function getFromFile() {
+    //readFromFile(".s,.asm", asm_editor, "emulator-out");
+}
+
+function setControlButtonsDisabled(isDisabled) {
+    //$("#back-button").prop('disabled', isDisabled);
+    //$("#play-pause-button").prop('disabled', isDisabled);
+    //$("#next-button").prop('disabled', isDisabled);
+    //$("#reset-button").prop('disabled', isDisabled);
+}
+
+function updateProgressBar(currentFrame, frameStackLength) {
+    //if (currentFrame == frameStackLength - 1) {
+    //    $('#frameProgressBar').css("width", "100%");
+    //}
+    //else {
+    //    var frameProgress = (current_frame / frame_stack.length) * 100;
+    //    $('#frameProgressBar').css("width", frameProgress + "%");
+    //}
+}
+
+function changeIntervalTiming(value) {
+    //// keep the time from getting too long
+    //if (value <= .250) {
+    //    value = .250;
+    //}
+    //interval_time = (1 / value) * 500;
+
+    //// If we currently have a job in process meaning the code is executing then
+    ////  clear it and change the interval time and start again
+    //if (job_id != null) {
+    //    clearInterval(job_id);
+    //    job_id = setInterval(frame_advance, interval_time);
+    //}
+}
\ No newline at end of file

From bff671cb85ee0134bd58b08a497c778e3a844636 Mon Sep 17 00:00:00 2001
From: Bryce Callender 
Date: Thu, 7 Jan 2021 22:18:29 -0800
Subject: [PATCH 04/20] Progress on Instructions being implemented and tested

---
 SAP1EMU.SAP2.Engine.Test/EngineTest.cs        | 333 +++++++++++++-
 SAP1EMU.SAP2.Engine/EngineProc.cs             |  62 ++-
 SAP1EMU.SAP2.Lib.Test/FrameTest.cs            |  14 +-
 SAP1EMU.SAP2.Lib.Test/ProgramTest.cs          |   2 +-
 SAP1EMU.SAP2.Lib/Components/ALU.cs            |  11 +-
 .../Components/HexadecimalDisplay.cs          |   6 +-
 SAP1EMU.SAP2.Lib/Components/Multiplexer.cs    |   4 +-
 SAP1EMU.SAP2.Lib/Components/RAM.cs            |  15 -
 SAP1EMU.SAP2.Lib/Components/SEQ.cs            |  54 +--
 SAP1EMU.SAP2.Lib/Frame.cs                     |  12 +-
 SAP1EMU.SAP2.Lib/InstructionDecoder.cs        |   6 +-
 SAP1EMU.SAP2.Lib/Registers/AReg.cs            |  27 +-
 SAP1EMU.SAP2.Lib/Registers/BReg.cs            |   4 +-
 SAP1EMU.SAP2.Lib/Registers/CReg.cs            |   4 +-
 SAP1EMU.SAP2.Lib/Registers/OReg3.cs           |  14 +-
 SAP1EMU.SAP2.Lib/Registers/OReg4.cs           |  16 +-
 SAP1EMU.SAP2.Lib/Registers/TReg.cs            |   4 +-
 SAP1EMU.SAP2.Lib/SAP2InstructionSets.json     | 407 +++++++-----------
 18 files changed, 636 insertions(+), 359 deletions(-)

diff --git a/SAP1EMU.SAP2.Engine.Test/EngineTest.cs b/SAP1EMU.SAP2.Engine.Test/EngineTest.cs
index ef57aa13..c06f19d2 100644
--- a/SAP1EMU.SAP2.Engine.Test/EngineTest.cs
+++ b/SAP1EMU.SAP2.Engine.Test/EngineTest.cs
@@ -2,8 +2,9 @@
 
 using SAP1EMU.SAP2.Engine;
 using SAP1EMU.SAP2.Lib;
-
+using System;
 using System.Collections.Generic;
+using System.IO;
 
 namespace SAP1EMU.Engine.Test
 {
@@ -15,7 +16,7 @@ public class EngineTest
 
         #region MVI MOV 1-3
 
-        // Test_LDA_PROG_1 **********************************************************
+        // Test_MVI_MOV_1 **********************************************************
         /// 
         /// This will run the following program
         ///
@@ -24,35 +25,349 @@ public class EngineTest
         /// 0x2 OUT 0x3
         /// 0x3 HLT
         ///
-        /// The expected result is OReg: 00000000
-        /// Testing to see if B == A
+        /// The expected result is OReg: 00000101
         /// 
         [TestMethod]
         public void Test_MVI_MOV_PROG_1()
         {
-            string expectedResult = "00000000";
+            string expectedResult = "00000101";
             List program = new List()
             {
                 "00111110",
                 "00000101",
                 "01000111",
+                "11010011",
+                "00000011",
                 "01110110"
             };
 
             EngineProc engine = new EngineProc();
 
             RAMProgram rp = new RAMProgram(program);
-             
+
             engine.Init(rp, _decoder);
             engine.Run();
 
             string output = engine.GetOutputReg();
 
-            var frames = engine.FrameStack();
+            using (StreamWriter file = new StreamWriter("MVI_MOV_PROG_1_FRAMES.txt"))
+            {
+                foreach (var frame in engine.FrameStack())
+                {
+                    file.WriteLine(frame);
+                }
+            }
 
             Assert.AreEqual(expectedResult, output);
         }
-    }
 
-    #endregion
+        // Test_MVI_MOV_2 **********************************************************
+        /// 
+        /// This will run the following program
+        ///
+        /// 0x0 MVI A,0x1
+        /// 0x1 MOV B,A
+        /// 0x2 MVI B,0xF
+        /// 0x3 MOV C,B
+        /// 0x4 OUT 0x3
+        /// 0x5 HLT
+        ///
+        /// The expected result is OReg: 00000001
+        /// 
+        [TestMethod]
+        public void Test_MVI_MOV_PROG_2()
+        {
+            string expectedResult = "00000001";
+            List program = new List()
+            {
+                "00111110",
+                "00000001",
+                "01000111",
+                "00000110",
+                "00001111",
+                "01001000",
+                "11010011",
+                "00000011",
+                "01110110"
+            };
+
+            EngineProc engine = new EngineProc();
+
+            RAMProgram rp = new RAMProgram(program);
+
+            engine.Init(rp, _decoder);
+            engine.Run();
+
+            string output = engine.GetOutputReg();
+
+            using (StreamWriter file = new StreamWriter("MVI_MOV_PROG_2_FRAMES.txt"))
+            {
+                foreach (var frame in engine.FrameStack())
+                {
+                    file.WriteLine(frame);
+                }
+            }
+
+            Assert.AreEqual(expectedResult, output);
+        }
+
+        // Test_MVI_MOV_3 **********************************************************
+        /// 
+        /// This will run the following program
+        ///
+        /// 0x0 MVI C,0x1
+        /// 0x1 MOV A,C
+        /// 0x2 OUT 0x4
+        /// 0x3 HLT
+        ///
+        /// The expected result is OReg: 00000000
+        /// Testing to see if B == A
+        /// 
+        [TestMethod]
+        public void Test_MVI_MOV_PROG_3()
+        {
+            string expectedResult = "00000000";
+            List program = new List()
+            {
+                "00001110",
+                "00000001",
+                "01111001",
+                "11010011",
+                "00000100",
+                "01110110"
+            };
+
+            EngineProc engine = new EngineProc();
+
+            RAMProgram rp = new RAMProgram(program);
+
+            engine.Init(rp, _decoder);
+            engine.Run();
+
+            string output = engine.GetOutputReg();
+
+            using (StreamWriter file = new StreamWriter("MVI_MOV_PROG_3_FRAMES.txt"))
+            {
+                foreach (var frame in engine.FrameStack())
+                {
+                    file.WriteLine(frame);
+                }
+            }
+
+            Assert.AreEqual(expectedResult, output);
+        }
+
+
+        #endregion
+
+        #region LDA 1
+
+        // Test_MVI_MOV_1 **********************************************************
+        /// 
+        /// This will run the following program
+        ///
+        /// 0x0 MVI A,0x9
+        /// 0x1 STA 0x1000
+        /// 0x2 LDA 0x1000
+        /// 0x3 HLT
+        ///
+        /// The expected result is OReg: 00001001
+        /// 
+        [TestMethod]
+        public void Test_LDA_PROG_1()
+        {
+            string expectedResult = "00001001";
+            int addressChanged = 0x1000;
+
+            List program = new List()
+            {
+                "00111110",
+                "00001001",
+                "00110010",
+                "00000000",
+                "00010000",
+                "00111010",
+                "00000000",
+                "00010000",
+                "01110110"
+            };
+
+            EngineProc engine = new EngineProc();
+
+            RAMProgram rp = new RAMProgram(program);
+
+            engine.Init(rp, _decoder);
+            engine.Run();
+
+            string output = engine.GetOutputReg();
+
+            var ram = engine.GetRAMContents();
+
+            using (StreamWriter file = new StreamWriter("LDA_PROG_1_FRAMES.txt"))
+            {
+                foreach (var frame in engine.FrameStack())
+                {
+                    file.WriteLine(frame);
+                }
+            }
+
+            Assert.AreEqual(expectedResult, ram[addressChanged]);
+        }
+
+        #endregion
+
+        #region STA 1
+
+        // Test_MVI_MOV_1 **********************************************************
+        /// 
+        /// This will run the following program
+        ///
+        /// 0x0 MVI A,0x5
+        /// 0x1 STA 0x0080
+        /// 0x2 HLT
+        ///
+        /// The expected result is OReg: 00000101
+        /// 
+        [TestMethod]
+        public void Test_STA_PROG_1()
+        {
+            string expectedResult = "00000101";
+            int addressChanged = 0x0080;
+
+            List program = new List()
+            {
+                "00111110",
+                "00000101",
+                "00110010",
+                "10000000",
+                "00000000",
+                "01110110"
+            };
+
+            EngineProc engine = new EngineProc();
+
+            RAMProgram rp = new RAMProgram(program);
+
+            engine.Init(rp, _decoder);
+            engine.Run();
+
+            var ram = engine.GetRAMContents();
+
+            using (StreamWriter file = new StreamWriter("STA_PROG_1_FRAMES.txt"))
+            {
+                foreach (var frame in engine.FrameStack())
+                {
+                    file.WriteLine(frame);
+                }
+            }
+
+            Assert.AreEqual(expectedResult, ram[addressChanged]);
+        }
+
+        #endregion
+
+        #region ADD 1-2
+
+        // Test_ADD_1 **********************************************************
+        /// 
+        /// This will run the following program
+        ///
+        /// 0x0 MVI B,0x5
+        /// 0x1 ADD B
+        /// 0x2 OUT 0x3
+        /// 0x3 HLT
+        ///
+        /// The expected result is OReg: 00000101
+        /// 
+        [TestMethod]
+        public void Test_ADD_PROG_1()
+        {
+            string expectedResult = "00000101";
+
+            List program = new List()
+            {
+                "00000110",
+                "00000101",
+                "10000000",
+                "11010011",
+                "00000011",
+                "01110110"
+            };
+
+            EngineProc engine = new EngineProc();
+
+            RAMProgram rp = new RAMProgram(program);
+
+            engine.Init(rp, _decoder);
+            engine.Run();
+
+            var actualOutput = engine.GetOutputReg();
+
+            using (StreamWriter file = new StreamWriter("ADD_PROG_1_FRAMES.txt"))
+            {
+                foreach (var frame in engine.FrameStack())
+                {
+                    file.WriteLine(frame);
+                }
+            }
+
+            Assert.AreEqual(expectedResult, actualOutput);
+        }
+
+        // Test_ADD_2 **********************************************************
+        /// 
+        /// This will run the following program
+        ///
+        /// 0x0 MVI B,0x5
+        /// 0x1 ADD B
+        /// 0x2 OUT 0x3
+        /// 0x3 MVI C,0x2
+        /// 0x4 ADD C
+        /// 0x5 OUT 0x3
+        /// 0x6 HLT
+        ///
+        /// The expected result is OReg: 00000101
+        /// 
+        [TestMethod]
+        public void Test_ADD_PROG_2()
+        {
+            string expectedResult = "00000111";
+
+            List program = new List()
+            {
+                "00000110",
+                "00000101",
+                "10000000",
+                "11010011",
+                "00000011",
+                "00001110",
+                "00000010",
+                "10000001",
+                "11010011",
+                "00000011",
+                "01110110"
+            };
+
+            EngineProc engine = new EngineProc();
+
+            RAMProgram rp = new RAMProgram(program);
+
+            engine.Init(rp, _decoder);
+            engine.Run();
+
+            var actualOutput = engine.GetOutputReg();
+
+            using (StreamWriter file = new StreamWriter("ADD_PROG_1_FRAMES.txt"))
+            {
+                foreach (var frame in engine.FrameStack())
+                {
+                    file.WriteLine(frame);
+                }
+            }
+
+            Assert.AreEqual(expectedResult, actualOutput);
+        }
+
+        #endregion
+    }
 }
\ No newline at end of file
diff --git a/SAP1EMU.SAP2.Engine/EngineProc.cs b/SAP1EMU.SAP2.Engine/EngineProc.cs
index a43eef2e..4d5d4c4c 100644
--- a/SAP1EMU.SAP2.Engine/EngineProc.cs
+++ b/SAP1EMU.SAP2.Engine/EngineProc.cs
@@ -4,6 +4,7 @@
 
 using System;
 using System.Collections.Generic;
+using System.Diagnostics;
 using System.Linq;
 
 namespace SAP1EMU.SAP2.Engine
@@ -12,6 +13,7 @@ public class EngineProc
     {
         private string OutputReg = "";
         private readonly List _FrameStack = new List();
+        private List _RAMDump = new List();
         private RAMProgram Program { get; set; } = new RAMProgram(new List());
         private InstructionSet InstructionSet { get; set; } = new InstructionSet();
         private const string DefaultInstructionSetName = "Malvino";
@@ -56,18 +58,20 @@ public void Run()
 
             IPort1 port1 = new IPort1();
             IPort2 port2 = new IPort2();
-            OReg3 oreg3 = new OReg3();
-            OReg4 oreg4 = new OReg4();
-
-            HexadecimalDisplay hexadecimalDisplay = new HexadecimalDisplay(ref oreg3);
-
+            
             MDR mdr = new MDR();
             RAM ram = new RAM();
 
             mdr.SetRefToRAM(ref ram);
-            ram.SetRefToMDR(ref mdr);
 
             ALU alu = new ALU(ref areg, ref treg);
+
+            areg.SetALUReference(ref alu);
+
+            OReg3 oreg3 = new OReg3(ref alu);
+            OReg4 oreg4 = new OReg4(ref alu);
+            HexadecimalDisplay hexadecimalDisplay = new HexadecimalDisplay(ref oreg3);
+
             Flag flagReg = new Flag(ref alu);
             PC pc = new PC(ref flagReg);
             MAR mar = new MAR(ref ram);
@@ -81,14 +85,16 @@ public void Run()
             creg.Subscribe(clock);
             ireg.Subscribe(clock);
             mar.Subscribe(clock);
-            oreg3.Subscribe(clock);
-            hexadecimalDisplay.Subscribe(clock);
-            oreg4.Subscribe(clock);
+            
             pc.Subscribe(clock);
-            alu.Subscribe(clock); // ALU must come after A and B
+            alu.Subscribe(clock); // ALU must come after A and T
             ram.Subscribe(clock);
             mdr.Subscribe(clock);
 
+            oreg3.Subscribe(clock);
+            hexadecimalDisplay.Subscribe(clock);
+            oreg4.Subscribe(clock);
+
             // Load the program into the RAM
             ram.LoadProgram(Program);
 
@@ -112,29 +118,24 @@ public void Run()
             // will be known and set to a new object reference.
             Instruction currentInstruction = new Instruction()
             {
+                OpCode = "???",
                 TStates = 4 // Since by 4 TStates it should know what instruction it is on
             };
 
-            bool isInstruction = true;
-            int bytesRemaining = 0;
+            List controlWords = new List();
 
             while (clock.IsEnabled)
             {
                 // Log the Instruction
-                if (TState == 4 && bytesRemaining == 0)
+                if (TState == 4)
                 {
                     currentInstruction = InstructionSet.Instructions.FirstOrDefault(i => i.BinCode.Equals(ireg.RegContent));
-                    isInstruction = currentInstruction != null;
-                    bytesRemaining = currentInstruction?.Bytes - 1 ?? 0;
-                    string iname = currentInstruction?.OpCode ?? "DATA";
+                    seq.LoadBackupControlWords(currentInstruction.MicroCode);
+
+                    string iname = currentInstruction.OpCode;
                     int operandVal = Convert.ToInt32(ireg.RegContent, 2);
                     string hexOperand = "0x" + operandVal.ToString("X");
                 }
-                else if(TState == 4 && bytesRemaining > 0)
-                {
-                    isInstruction = false;
-                    bytesRemaining -= 1;
-                }
 
                 if (TState <= 3)
                 {
@@ -142,7 +143,7 @@ public void Run()
                 }
                 else
                 {
-                    seq.UpdateControlWordReg(TState, ireg.RegContent, isInstruction);
+                    seq.UpdateControlWordReg(TState, ireg.RegContent);
                 }
 
                 clock.SendTicTok(tictok);
@@ -150,6 +151,9 @@ public void Run()
                 clock.SendTicTok(tictok);
                 tictok.ToggleClockState();
 
+                Debug.WriteLine(alu);
+                Debug.WriteLine(TState);
+
                 tempFrame = new Frame(currentInstruction, TState, port1, port2, pc, mar, ram,
                                       ram.RAMDump(), mdr, ireg, SEQ.Instance(),
                                       Wbus.Instance().Value, areg, alu, flagReg,
@@ -161,6 +165,8 @@ public void Run()
                 if (ireg.RegContent.Equals("01110110", StringComparison.Ordinal) && TState == 5)
                 {
                     clock.IsEnabled = false;
+
+                    _RAMDump = ram.RAMDump();
                 }
 
                 if (loop_counter >= max_loop_count)
@@ -184,6 +190,11 @@ public void Run()
                 else
                 {
                     TState = 1;
+                    currentInstruction = new Instruction()
+                    {
+                        OpCode = "???",
+                        TStates = 4 // Since by 4 TStates it should know what instruction it is on
+                    };
                 }
             }
 
@@ -202,7 +213,7 @@ public List FrameStack()
             return _FrameStack;
         }
 
-        public Frame FinalFrame()
+        public Frame? FinalFrame()
         {
             if (_FrameStack.Count != 0)
             {
@@ -219,6 +230,11 @@ public string GetOutputReg()
             return OutputReg;
         }
 
+        public List GetRAMContents()
+        {
+            return _RAMDump;
+        }
+
         // *************************************************************************
     }
 }
\ No newline at end of file
diff --git a/SAP1EMU.SAP2.Lib.Test/FrameTest.cs b/SAP1EMU.SAP2.Lib.Test/FrameTest.cs
index 1b968b6a..bb21ba63 100644
--- a/SAP1EMU.SAP2.Lib.Test/FrameTest.cs
+++ b/SAP1EMU.SAP2.Lib.Test/FrameTest.cs
@@ -26,18 +26,20 @@ public void TestToString()
 
             IPort1 port1 = new IPort1();
             IPort2 port2 = new IPort2();
-            OReg3 oreg3 = new OReg3();
-            OReg4 oreg4 = new OReg4();
-
-            HexadecimalDisplay hexadecimalDisplay = new HexadecimalDisplay(ref oreg3);
-
+            
             MDR mdr = new MDR();
             RAM ram = new RAM();
 
             mdr.SetRefToRAM(ref ram);
-            ram.SetRefToMDR(ref mdr);
 
             ALU alu = new ALU(ref areg, ref treg);
+
+            OReg3 oreg3 = new OReg3(ref alu);
+            OReg4 oreg4 = new OReg4(ref alu);
+
+            HexadecimalDisplay hexadecimalDisplay = new HexadecimalDisplay(ref oreg3);
+
+
             Flag flagReg = new Flag(ref alu);
             PC pc = new PC(ref flagReg);
             MAR mar = new MAR(ref ram);
diff --git a/SAP1EMU.SAP2.Lib.Test/ProgramTest.cs b/SAP1EMU.SAP2.Lib.Test/ProgramTest.cs
index 8fc3c199..13899abc 100644
--- a/SAP1EMU.SAP2.Lib.Test/ProgramTest.cs
+++ b/SAP1EMU.SAP2.Lib.Test/ProgramTest.cs
@@ -36,7 +36,7 @@ public void TestCtorReg()
                     Assert.IsTrue(RamContentsResults[i] == RamContentsData[i], $"At index {i}, RamContentsResults != RamContentsData");
                 }
                 // Make sure the end of the program is padded with 0's
-                for (int i = RamContentsData.Count; i < 0xFFFF; i++)
+                for (int i = RamContentsData.Count; i < RamContentsResults.Count; i++)
                 {
                     Assert.IsTrue(RamContentsResults[i] == "00000000");
                 }
diff --git a/SAP1EMU.SAP2.Lib/Components/ALU.cs b/SAP1EMU.SAP2.Lib/Components/ALU.cs
index a4118cb6..1cfed4d2 100644
--- a/SAP1EMU.SAP2.Lib/Components/ALU.cs
+++ b/SAP1EMU.SAP2.Lib/Components/ALU.cs
@@ -1,12 +1,13 @@
 using SAP1EMU.SAP2.Lib.Utilities;
 using SAP1EMU.SAP2.Lib.Registers;
 using System;
+using System.Diagnostics;
 
 namespace SAP1EMU.SAP2.Lib.Components
 {
     public class ALU : IObserver
     {
-        private string RegContent { get; set; }
+        public string RegContent { get; set; }
 
         public string FlagContent { get; private set; }
 
@@ -24,7 +25,8 @@ public enum ALUOPType
             RAL,
             RAR,
             INR,
-            DEC
+            DEC,
+            OUT
         }
 
         public ALU(ref AReg aReg, ref TReg tReg)
@@ -51,7 +53,7 @@ private void Exec(TicTok tictok)
             // Active Hi, Push on Tic
             if (string.Equals(cw["EU"], "1", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tic)
             {
-                Wbus.Instance().Value = RegContent;
+                Multiplexer.Instance().PassThroughToBus(RegContent, Convert.ToBoolean(Convert.ToInt16(cw["UB"])), Convert.ToBoolean(Convert.ToInt16(cw["CLR"])));
             }
         }
 
@@ -102,6 +104,9 @@ public string Compute(string AReg, string TReg, ALUOPType action = ALUOPType.ADD
                 case ALUOPType.DEC:
                     result = ib - 1;
                     break;
+                case ALUOPType.OUT:
+                    result = ib & 1; //Check if byte is 3
+                    break;
             }
 
             //Check to see if a flag needs to be set
diff --git a/SAP1EMU.SAP2.Lib/Components/HexadecimalDisplay.cs b/SAP1EMU.SAP2.Lib/Components/HexadecimalDisplay.cs
index 96b1aa5a..126ea51f 100644
--- a/SAP1EMU.SAP2.Lib/Components/HexadecimalDisplay.cs
+++ b/SAP1EMU.SAP2.Lib/Components/HexadecimalDisplay.cs
@@ -5,7 +5,7 @@ namespace SAP1EMU.SAP2.Lib.Components
 {
     public class HexadecimalDisplay : IObserver
     {
-        public string RegContent { get; set; }
+        public string RegContent { get; set; } = "0";
 
         private readonly OReg3 outputReg;
 
@@ -18,8 +18,10 @@ private void Exec(TicTok tictok)
         {
             var cw = SEQ.Instance().ControlWord;
 
+            var busValue = Wbus.Instance().Value;
+
             // Active Low, Pull on Tok
-            if (string.Equals(cw["L03_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
+            if (busValue[^1].Equals(1) && string.Equals(cw["L0_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
                 int value = Convert.ToInt16(outputReg.RegContent);
                 RegContent = value.ToString("X8");
diff --git a/SAP1EMU.SAP2.Lib/Components/Multiplexer.cs b/SAP1EMU.SAP2.Lib/Components/Multiplexer.cs
index c405ba32..bbeb7e66 100644
--- a/SAP1EMU.SAP2.Lib/Components/Multiplexer.cs
+++ b/SAP1EMU.SAP2.Lib/Components/Multiplexer.cs
@@ -6,8 +6,10 @@ class Multiplexer
 
         public void PassThroughToBus(string bits, bool isUpperByte = false, bool clearByte = true)
         {
+            string test = Wbus.Instance().Value[8..];
+
             // If we want solely the 8 bit value to go out on bus and get rid of the other bytes value in bus
-            if(clearByte)
+            if (clearByte)
             {
                 if(isUpperByte)
                 {
diff --git a/SAP1EMU.SAP2.Lib/Components/RAM.cs b/SAP1EMU.SAP2.Lib/Components/RAM.cs
index 7cc00cb6..01d34517 100644
--- a/SAP1EMU.SAP2.Lib/Components/RAM.cs
+++ b/SAP1EMU.SAP2.Lib/Components/RAM.cs
@@ -11,18 +11,11 @@ public class RAM : IObserver
         private string MARContents { get; set; }
         public string RegContent { get; private set; } = "00000000";
 
-        private MDR mdrReg;
-
         private const int MIN_RAM_ADDRESS = 0x0800;
         private const int MAX_RAM_ADDRESS = 0xFFFF;
 
         public RAM() { }
 
-        public void SetRefToMDR(ref MDR mdrReg)
-        {
-            this.mdrReg = mdrReg;
-        }
-
         private void Exec(TicTok tictok)
         {
             var cw = SEQ.Instance().ControlWord;
@@ -32,14 +25,6 @@ private void Exec(TicTok tictok)
             {
                 RegContent = GetWordAt(MARContents);
             }
-
-            // Active Low, Pull on Tok
-            if (string.Equals(cw["LM_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
-            {
-                //string word = mdrReg.RegContent;
-                //SetWordAt(MARContents, word);
-                //RegContent = word;
-            }
         }
 
         public void LoadProgram(RAMProgram rp)
diff --git a/SAP1EMU.SAP2.Lib/Components/SEQ.cs b/SAP1EMU.SAP2.Lib/Components/SEQ.cs
index 698e8251..1eca3e44 100644
--- a/SAP1EMU.SAP2.Lib/Components/SEQ.cs
+++ b/SAP1EMU.SAP2.Lib/Components/SEQ.cs
@@ -1,5 +1,6 @@
 using System;
 using System.Collections.Generic;
+using System.Diagnostics;
 using System.Linq;
 
 namespace SAP1EMU.SAP2.Lib.Components
@@ -19,6 +20,8 @@ public class SEQ
         private readonly List executedInstructions = new List();
         private string lastInstructionBinary = string.Empty;
 
+        private List backupControlWords = new List();
+
         /// 
         /// The control word storage location for all registers and components
         /// 
@@ -72,27 +75,25 @@ private string _controlWordSignals
                 ControlWord["EU"] = value[20..21];
 
                 //Output
-                ControlWord["L03_"] = value[21..22];
-                ControlWord["L04_"] = value[22..23];
+                ControlWord["LO_"] = value[21..22]; //21-22 are the index to remove
 
                 //ALU
-                ControlWord["ALU"] = value[23..28];
+                ControlWord["ALU"] = value[22..27];
 
                 //Jump
-                ControlWord["JC"] = value[28..31];
+                ControlWord["JC"] = value[27..30];
 
                 //Output to upper byte
-                ControlWord["UB"] = value[31..32];
-                ControlWord["CLR"] = value[32..33];
+                ControlWord["UB"] = value[30..31];
+                ControlWord["CLR"] = value[31..32];
 
                 // Hardcode PC address locations
-                ControlWord["RTNA"] = value[33..34];
+                ControlWord["RTNA"] = value[32..33];
             }
         }
             
         public readonly Dictionary ControlWord;
 
-        //************************************************************************************************************************
 
         //************************************************************************************************************************
         /// 
@@ -101,21 +102,22 @@ private string _controlWordSignals
         /// 
         /// 
         /// 
-        public void UpdateControlWordReg(int TState, string instructionBinaryCode, bool isInstruction = true)
+        public void UpdateControlWordReg(int TState, string instructionBinaryCode)
         {
             int hash = HashKey(TState, instructionBinaryCode);
 
-            // Its the data portion of the instruction that comes after it
-            // Every line of data does not have to be an instruction
-            if(!isInstruction)
+            if(TState <= 3 && ControlTable.ContainsKey(hash))
             {
-                return;
+                _controlWordSignals = ControlTable[hash];
             }
+            else
+            {
+                _controlWordSignals = backupControlWords[TState - 1];
+            }
+                        
 
-            _controlWordSignals = ControlTable[hash];
-
-            //Beginning of a new instruction
-            if (TState == 1)
+            //Beginning of a new instruction since we decoded it
+            if (TState == 4)
             {
                 executedInstructions.Add(instructionBinaryCode);
             }
@@ -123,7 +125,7 @@ public void UpdateControlWordReg(int TState, string instructionBinaryCode, bool
             //If we have more than 1 we need to keep track of the previous one to see if itll influence this instructions fetch cycle control word
             if(executedInstructions.Count > 1 && TState <= 3)
             {
-                lastInstructionBinary = executedInstructions[^2]; //similar to count - 2
+                lastInstructionBinary = executedInstructions[^1];
 
                 Instruction? instruction = instructionsThatModifyNextInstruction.FirstOrDefault(i => i.BinCode.Equals(lastInstructionBinary, StringComparison.Ordinal));
 
@@ -132,15 +134,18 @@ public void UpdateControlWordReg(int TState, string instructionBinaryCode, bool
                     List updatedMicroCode = instruction.UpdatedFetchCycleStates;
 
                     //If the code is empty then do nothing to the microcode otherwise modify the control word.
-                    if (!string.IsNullOrEmpty(updatedMicroCode[TState]))
+                    if (!string.IsNullOrEmpty(updatedMicroCode[TState - 1]))
                     {
-                        _controlWordSignals = updatedMicroCode[TState];
+                        _controlWordSignals = updatedMicroCode[TState - 1];
                     }
                 }
             }
         }
 
-        //************************************************************************************************************************
+        public void LoadBackupControlWords(List controlWords)
+        {
+            backupControlWords = controlWords;
+        }
 
         //************************************************************************************************************************
         private static int HashKey(int TState, string Instruction)
@@ -148,8 +153,6 @@ private static int HashKey(int TState, string Instruction)
             return HashCode.Combine(TState, Instruction);
         }
 
-        //************************************************************************************************************************
-
         public void Load(InstructionSet iset)
         {
             ControlTable.Clear();
@@ -169,7 +172,7 @@ public void Load(InstructionSet iset)
 
         // Singleton Pattern
         private SEQ()
-        {
+        {  
             ControlWord = new Dictionary(StringComparer.Ordinal)
             {
                 { "CP", "0" },    //Increment PC
@@ -198,8 +201,7 @@ private SEQ()
                 { "LF", "0"},     //Load flag
                 { "EU", "0" },    //Enable ALU
 
-                { "LO3_", "1" },  //Load Output port 3
-                { "LO4_", "1" },  //Load Output port 4
+                { "LO_", "1" },  //Load Output 
 
                 { "ALU", "00000" },   //ALU Control flags
                 { "JC", "000" },    //Jump Control flags
diff --git a/SAP1EMU.SAP2.Lib/Frame.cs b/SAP1EMU.SAP2.Lib/Frame.cs
index d3d733e8..746f89ee 100644
--- a/SAP1EMU.SAP2.Lib/Frame.cs
+++ b/SAP1EMU.SAP2.Lib/Frame.cs
@@ -62,12 +62,18 @@ public Frame(Instruction instruction, int TState, IPort1 ip1, IPort2 ip2, PC pc,
 
             this.AReg = areg.ToString_Frame_Use();
             this.BReg = breg.ToString_Frame_Use();
+            this.CReg = creg.ToString_Frame_Use();
+            this.TReg = treg.ToString_Frame_Use();
             this.IReg = ireg.ToString_Frame_Use();  // The real ToString() is in use with a substring in it.  This is needed for proper operation
             this.MAR = mar.ToString_Frame_Use();
-            this.OReg3 = oreg3.ToString_Frame_Use();
+            this.MDR = mdr.RegContent;
+            
             this.PC = pc.RegContent;
             this.ALU = alu.ToString();
             this.WBus = wbus_string;
+
+            this.OReg3 = oreg3.ToString_Frame_Use();
+            this.OReg4 = oreg4.ToString_Frame_Use();
             this.HexadecimalDisplay = hexadecimalDisplay.RegContent;
 
             this.RAM = ramContents;
@@ -144,9 +150,9 @@ public override string ToString()
             }
 
             tw.WriteLine($"************************************************************");//60
-            tw.WriteLine($"* Instruction: ${InstructionData.OpCode}     TState: {TState}".PadRight(59) + "*");
+            tw.WriteLine($"* Instruction: {InstructionData.OpCode}     TState: {TState}".PadRight(59) + "*");
             tw.WriteLine("************************************************************");
-            tw.WriteLine($"* Input Port 1: {Input_Port_1}       A Register:    {AReg}   *");
+            tw.WriteLine($"* Input Port 1: {Input_Port_1}       A Register:    {AReg}".PadRight(59) + "*");
             tw.WriteLine($"* Input Port 2: {Input_Port_2}       ALU:    {ALU}       Flags: {Flags} *");
             tw.WriteLine($"* PC:         {PC}              Temp Register:      {TReg}".PadRight(59) + "*");
             tw.WriteLine($"* MAR:        {MAR}              B Register:      {BReg}".PadRight(59) + "*");
diff --git a/SAP1EMU.SAP2.Lib/InstructionDecoder.cs b/SAP1EMU.SAP2.Lib/InstructionDecoder.cs
index 1a044b9a..5e893024 100644
--- a/SAP1EMU.SAP2.Lib/InstructionDecoder.cs
+++ b/SAP1EMU.SAP2.Lib/InstructionDecoder.cs
@@ -18,9 +18,9 @@ public InstructionDecoder()
             JsonSerializerOptions options = new JsonSerializerOptions
             {
                 Converters =
-                    {
-                        new JsonStringEnumConverter(JsonNamingPolicy.CamelCase)
-                    },
+                {
+                    new JsonStringEnumConverter(JsonNamingPolicy.CamelCase)
+                },
 
             };
 
diff --git a/SAP1EMU.SAP2.Lib/Registers/AReg.cs b/SAP1EMU.SAP2.Lib/Registers/AReg.cs
index 220c40f8..e3dfd0c5 100644
--- a/SAP1EMU.SAP2.Lib/Registers/AReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/AReg.cs
@@ -5,7 +5,14 @@ namespace SAP1EMU.SAP2.Lib.Registers
 {
     public class AReg : IObserver
     {
-        private string RegContent { get; set; }
+        private string RegContent { get; set; } = "00000000";
+
+        private ALU alu;
+
+        public void SetALUReference(ref ALU alu)
+        {
+            this.alu = alu;
+        }
 
         private void Exec(TicTok tictok)
         {
@@ -21,9 +28,25 @@ private void Exec(TicTok tictok)
             // Active Low, Pull on Tok
             if (string.Equals(cw["LA_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
+                // Special logic so we dont have immediate feedback when ALU -> A happens on the updated fetch cycle
+                // Only applies to A Register
+                if(string.Equals(cw["EU"], "1", StringComparison.Ordinal))
+                {
+                    return;
+                }
+
                 // Store Wbus val in A
-                RegContent = Wbus.Instance().Value[0..8];
+                RegContent = Wbus.Instance().Value[8..];
             }
+
+            // Special logic so we dont have immediate feedback when ALU -> A happens on the updated fetch cycle
+            // Only applies to A Register
+            if (string.Equals(cw["EU"], "1", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tic)
+            {
+                // Store ALU in A
+                RegContent = alu.RegContent;
+            }
+
         }
 
         #region IObserver Region
diff --git a/SAP1EMU.SAP2.Lib/Registers/BReg.cs b/SAP1EMU.SAP2.Lib/Registers/BReg.cs
index f14e83c1..77b5681a 100644
--- a/SAP1EMU.SAP2.Lib/Registers/BReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/BReg.cs
@@ -5,7 +5,7 @@ namespace SAP1EMU.SAP2.Lib.Registers
 {
     public class BReg : IObserver
     {
-        private string RegContent { get; set; }
+        private string RegContent { get; set; } = "00000000";
 
         private void Exec(TicTok tictok)
         {
@@ -22,7 +22,7 @@ private void Exec(TicTok tictok)
             if (string.Equals(cw["LB_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
                 // Store Wbus val in B
-                RegContent = Wbus.Instance().Value[0..8];
+                RegContent = Wbus.Instance().Value[8..];
             }
         }
 
diff --git a/SAP1EMU.SAP2.Lib/Registers/CReg.cs b/SAP1EMU.SAP2.Lib/Registers/CReg.cs
index 129f722e..6d4724b2 100644
--- a/SAP1EMU.SAP2.Lib/Registers/CReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/CReg.cs
@@ -5,7 +5,7 @@ namespace SAP1EMU.SAP2.Lib.Registers
 {
     public class CReg : IObserver
     {
-        private string RegContent { get; set; }
+        private string RegContent { get; set; } = "00000000";
 
         private void Exec(TicTok tictok)
         {
@@ -22,7 +22,7 @@ private void Exec(TicTok tictok)
             if (string.Equals(cw["LC_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
                 // Store Wbus val in C
-                RegContent = Wbus.Instance().Value[0..8];
+                RegContent = Wbus.Instance().Value[8..];
             }
         }
 
diff --git a/SAP1EMU.SAP2.Lib/Registers/OReg3.cs b/SAP1EMU.SAP2.Lib/Registers/OReg3.cs
index 5905a811..d0408601 100644
--- a/SAP1EMU.SAP2.Lib/Registers/OReg3.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/OReg3.cs
@@ -1,4 +1,5 @@
 using SAP1EMU.SAP2.Lib.Components;
+using SAP1EMU.SAP2.Lib.Utilities;
 using System;
 
 namespace SAP1EMU.SAP2.Lib.Registers
@@ -7,15 +8,24 @@ public class OReg3 : IObserver
     {
         public string RegContent { get; private set; } = "00000000";
 
+        private ALU alu { get; set; }
+
+        public OReg3(ref ALU alu)
+        {
+            this.alu = alu;
+        }
+
         private void Exec(TicTok tictok)
         {
             var cw = SEQ.Instance().ControlWord;
 
+            string aluResult = alu.RegContent;
+
             // Active Low, Pull on Tok
-            if (string.Equals(cw["L03_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
+            if (aluResult[^1].Equals('1') && string.Equals(cw["LO_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
                 // Store Wbus val in Output port 3
-                RegContent = Wbus.Instance().Value;
+                RegContent = Wbus.Instance().Value[8..];
             }
         }
 
diff --git a/SAP1EMU.SAP2.Lib/Registers/OReg4.cs b/SAP1EMU.SAP2.Lib/Registers/OReg4.cs
index 5dc1a832..373ce45b 100644
--- a/SAP1EMU.SAP2.Lib/Registers/OReg4.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/OReg4.cs
@@ -1,4 +1,5 @@
 using SAP1EMU.SAP2.Lib.Components;
+using SAP1EMU.SAP2.Lib.Utilities;
 using System;
 
 namespace SAP1EMU.SAP2.Lib.Registers
@@ -7,15 +8,24 @@ public class OReg4 : IObserver
     {
         private string RegContent { get; set; } = "00000000";
 
+        private ALU alu { get; set; }
+
+        public OReg4(ref ALU alu)
+        {
+            this.alu = alu;
+        }
+
         private void Exec(TicTok tictok)
         {
             var cw = SEQ.Instance().ControlWord;
 
+            string aluResult = alu.RegContent;
+
             // Active Low, Pull on Tok
-            if (string.Equals(cw["L04_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
+            if (aluResult[^1].Equals('0') && string.Equals(cw["LO_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
-                // Store Wbus val in Output port 3
-                RegContent = Wbus.Instance().Value;
+                // Store Wbus val in Output port 4
+                RegContent = Wbus.Instance().Value[8..];
             }
         }
 
diff --git a/SAP1EMU.SAP2.Lib/Registers/TReg.cs b/SAP1EMU.SAP2.Lib/Registers/TReg.cs
index 95000baa..66e36400 100644
--- a/SAP1EMU.SAP2.Lib/Registers/TReg.cs
+++ b/SAP1EMU.SAP2.Lib/Registers/TReg.cs
@@ -5,7 +5,7 @@ namespace SAP1EMU.SAP2.Lib.Registers
 {
     public class TReg : IObserver
     {
-        private string RegContent { get; set; }
+        private string RegContent { get; set; } = "00000000";
 
         private void Exec(TicTok tictok)
         {
@@ -22,7 +22,7 @@ private void Exec(TicTok tictok)
             if (string.Equals(cw["LT_"], "0", StringComparison.Ordinal) && tictok.ClockState == TicTok.State.Tok)
             {
                 // Store Wbus val in Temp
-                RegContent = Wbus.Instance().Value[0..8];
+                RegContent = Wbus.Instance().Value[8..];
             }
         }
 
diff --git a/SAP1EMU.SAP2.Lib/SAP2InstructionSets.json b/SAP1EMU.SAP2.Lib/SAP2InstructionSets.json
index ffcf5375..8d566636 100644
--- a/SAP1EMU.SAP2.Lib/SAP2InstructionSets.json
+++ b/SAP1EMU.SAP2.Lib/SAP2InstructionSets.json
@@ -2,23 +2,23 @@
     {
         "Instructions": [
             {
-                "AddressingMode": "Register",
-                "AffectsFlags": true,
-                "BinCode": "10000000",
-                "Bytes": 1,
-                "MicroCode": [
-                    "",
-                    "",
-                    "",
-                    ""
-                ],
-                "OpCode": "ADD B",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+              "AddressingMode": "Register",
+              "AffectsFlags": true,
+              "BinCode": "10000000",
+              "Bytes": 1,
+              "MicroCode": [
+                "011100011101010101000100000000010",
+                "101100111101010101000100000000010",
+                "001000101111010101000100000000010",
+                "001100111101000111010100000000010"
+              ],
+              "OpCode": "ADD B",
+              "TStates": 4,
+              "UpdatedFetchCycleStates": [
+                "011100011101010101000100000000010",
+                "101100111100010101001100000000010",
+                "001000101111010101000100000000010"
+              ]
             },
             {
                 "AddressingMode": "Register",
@@ -26,17 +26,17 @@
                 "BinCode": "10000001",
                 "Bytes": 1,
                 "MicroCode": [
-                    "",
-                    "",
-                    "",
-                    ""
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101000101110100000000010"
                 ],
                 "OpCode": "ADD C",
                 "TStates": 4,
                 "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
+                    "011100011101010101000100000000010",
+                    "101100111100010101001100000000010",
+                    "001000101111010101000100000000010"
                 ]
             },
             {
@@ -51,12 +51,7 @@
                     ""
                 ],
                 "OpCode": "ANA B",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -70,12 +65,7 @@
                     ""
                 ],
                 "OpCode": "ANA C",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Immediate",
@@ -89,12 +79,7 @@
                     ""
                 ],
                 "OpCode": "ANI",
-                "TStates": 7,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 7
             },
             {
                 "AddressingMode": "Immediate",
@@ -122,12 +107,7 @@
                     ""
                 ],
                 "OpCode": "CMA",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -141,12 +121,7 @@
                     ""
                 ],
                 "OpCode": "DCR A",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -160,12 +135,7 @@
                     ""
                 ],
                 "OpCode": "DCR B",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -179,12 +149,7 @@
                     ""
                 ],
                 "OpCode": "DCR C",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "None",
@@ -192,11 +157,11 @@
                 "BinCode": "01110110",
                 "Bytes": 1,
                 "MicroCode": [
-                  "0111000111010101010001100000000000",
-                  "1011001111010101010001100000000000",
-                  "0010001011110101010001100000000000",
-                  "0011001111010101010001100000000000",
-                  "0011001111010101010001100000000000"
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010101000100000000010",
+                    "001100111101010101000100000000010"
                 ],
                 "OpCode": "HLT",
                 "TStates": 5
@@ -227,12 +192,7 @@
                     ""
                 ],
                 "OpCode": "INR A",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -246,12 +206,7 @@
                     ""
                 ],
                 "OpCode": "INR B",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -265,12 +220,7 @@
                     ""
                 ],
                 "OpCode": "INR C",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Immediate",
@@ -284,12 +234,7 @@
                     ""
                 ],
                 "OpCode": "JM",
-                "TStates": 10,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 10
             },
             {
                 "AddressingMode": "Immediate",
@@ -303,12 +248,7 @@
                     ""
                 ],
                 "OpCode": "JMP",
-                "TStates": 10,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 10
             },
             {
                 "AddressingMode": "Immediate",
@@ -322,12 +262,7 @@
                     ""
                 ],
                 "OpCode": "JNZ",
-                "TStates": 10,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 10
             },
             {
                 "AddressingMode": "Immediate",
@@ -341,12 +276,7 @@
                     ""
                 ],
                 "OpCode": "JZ",
-                "TStates": 10,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 10
             },
             {
                 "AddressingMode": "Direct",
@@ -354,10 +284,19 @@
                 "BinCode": "00111010",
                 "Bytes": 3,
                 "MicroCode": [
-                    "",
-                    "",
-                    "",
-                    ""
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010101000100000000000",
+                    "011100011101010101000100000000000",
+                    "001100101111000101000100000000000",
+                    "101100111101010101000100000000000",
+                    "011100011101010101000100000000000",
+                    "001100101111010101000100000000100",
+                    "101100111101010101000100000000000",
+                    "001100011101000101000100000000000",
+                    "001100101111010101000100000000000",
+                    "001100111100010101000100000000000"
                 ],
                 "OpCode": "LDA",
                 "TStates": 13
@@ -367,12 +306,12 @@
                 "AffectsFlags": false,
                 "BinCode": "01111000",
                 "Bytes": 1,
-              "MicroCode": [
-                "0111000111010101010001100000000000",
-                "1011001111010101010001100000000000",
-                "0010001011110101010001100000000000",
-                "0011001111000100110001100000000000"
-              ],
+                "MicroCode": [
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111100010011000100000000010"
+                ],
                 "OpCode": "MOV A,B",
                 "TStates": 4
             },
@@ -381,12 +320,12 @@
                 "AffectsFlags": false,
                 "BinCode": "01111001",
                 "Bytes": 1,
-              "MicroCode": [
-                "0111000111010101010001100000000000",
-                "1011001111010101010001100000000000",
-                "0010001011110101010001100000000000",
-                "0011001111000100011001100000000000"
-              ],
+                "MicroCode": [
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111100010001100100000000010"
+                ],
                 "OpCode": "MOV A,C",
                 "TStates": 4
             },
@@ -395,12 +334,12 @@
                 "AffectsFlags": false,
                 "BinCode": "01000111",
                 "Bytes": 1,
-              "MicroCode": [
-                "0111000111010101010001100000000000",
-                "1011001111010101010001100000000000",
-                "0010001011110101010001100000000000",
-                "0011001111011100010001100000000000"
-              ],
+                "MicroCode": [
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101110001000100000000010"
+                ],
                 "OpCode": "MOV B,A",
                 "TStates": 4
             },
@@ -409,12 +348,12 @@
                 "AffectsFlags": false,
                 "BinCode": "01000001",
                 "Bytes": 1,
-              "MicroCode": [
-                "0111000111010101010001100000000000",
-                "1011001111010101010001100000000000",
-                "0010001011110101010001100000000000",
-                "0011001111010100011001100000000000"
-              ],
+                "MicroCode": [
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010001100100000000010"
+                ],
                 "OpCode": "MOV B,C",
                 "TStates": 4
             },
@@ -423,12 +362,12 @@
                 "AffectsFlags": false,
                 "BinCode": "01001111",
                 "Bytes": 1,
-              "MicroCode": [
-                "0111000111010101010001100000000000",
-                "1011001111010101010001100000000000",
-                "0010001011110101010001100000000000",
-                "0011001111011101000001100000000000"
-              ],
+                "MicroCode": [
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101110100000100000000010"
+                ],
                 "OpCode": "MOV C,A",
                 "TStates": 4
             },
@@ -437,12 +376,12 @@
                 "AffectsFlags": false,
                 "BinCode": "01001000",
                 "Bytes": 1,
-              "MicroCode": [
-                "0111000111010101010001100000000000",
-                "1011001111010101010001100000000000",
-                "0010001011110101010001100000000000",
-                "0011001111010101100001100000000000"
-              ],
+                "MicroCode": [
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010110000100000000010"
+                ],
                 "OpCode": "MOV C,B",
                 "TStates": 4
             },
@@ -451,15 +390,15 @@
                 "AffectsFlags": false,
                 "BinCode": "00111110",
                 "Bytes": 2,
-              "MicroCode": [
-                "0111000111010101010001100000000000",
-                "1011001111010101010001100000000000",
-                "0010001011110101010001100000000000",
-                "0011001111010101010001100000000000",
-                "0111000111010101010001100000000000",
-                "0111001111010101010001100000000000",
-                "0011001011100101010001100000000000"
-              ],
+                "MicroCode": [
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010101000100000000010",
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001100101110010101000100000000010"
+                ],
                 "OpCode": "MVI A,",
                 "TStates": 7
             },
@@ -469,13 +408,13 @@
                 "BinCode": "00000110",
                 "Bytes": 2,
                 "MicroCode": [
-                  "0111000111010101010001100000000000",
-                  "1011001111010101010001100000000000",
-                  "0010001011110101010001100000000000",
-                  "0111000111010101010001100000000000",
-                  "0111001111010101010001100000000000",
-                  "0011001011110100010001100000000000",
-                  "0011001111010101010001100000000000"
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100011101010101000100000000010",
+                    "011100011101010101000100000000010",
+                    "101100101111010101000100000000010",
+                    "001100101111010001000100000000010"
                 ],
                 "OpCode": "MVI B,",
                 "TStates": 7
@@ -486,13 +425,13 @@
                 "BinCode": "00001110",
                 "Bytes": 2,
                 "MicroCode": [
-                  "0111000111010101010001100000000000",
-                  "1011001111010101010001100000000000",
-                  "0010001011110101010001100000000000",
-                  "0111000111010101010001100000000000",
-                  "0111001111010101010001100000000000",
-                  "0011000111110101000001100000000000",
-                  "0011001111010101010001100000000000"
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010101000100000000010",
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001100101111010100000100000000010"
                 ],
                 "OpCode": "MVI C,",
                 "TStates": 7
@@ -503,10 +442,10 @@
                 "BinCode": "00000000",
                 "Bytes": 1,
                 "MicroCode": [
-                    "0111000111010101010001100000000000",
-                    "1011001111010101010001100000000000",
-                    "0010001011110101010001100000000000",
-                    "0011001111010101010001100000000000"
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010101000100000000010"
                 ],
                 "OpCode": "NOP",
                 "TStates": 4
@@ -523,12 +462,7 @@
                     ""
                 ],
                 "OpCode": "ORA B",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -542,12 +476,7 @@
                     ""
                 ],
                 "OpCode": "ORA C",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Immediate",
@@ -561,12 +490,7 @@
                     ""
                 ],
                 "OpCode": "ORI",
-                "TStates": 7,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 7
             },
             {
                 "AddressingMode": "Direct",
@@ -574,10 +498,16 @@
                 "BinCode": "11010011",
                 "Bytes": 2,
                 "MicroCode": [
-                    "",
-                    "",
-                    "",
-                    ""
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010101000100000000010",
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001100101111000101000100000000010",
+                    "001100111101010101000101010000010",
+                    "001100111101110101000001010000010",
+                    "001100111101010101000100000000010"
                 ],
                 "OpCode": "OUT",
                 "TStates": 10
@@ -594,12 +524,7 @@
                     ""
                 ],
                 "OpCode": "RAL",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Implied",
@@ -613,12 +538,7 @@
                     ""
                 ],
                 "OpCode": "RAR",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Implied",
@@ -632,12 +552,7 @@
                     ""
                 ],
                 "OpCode": "RET",
-                "TStates": 10,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 10
             },
             {
                 "AddressingMode": "Direct",
@@ -645,10 +560,19 @@
                 "BinCode": "00110010",
                 "Bytes": 3,
                 "MicroCode": [
-                    "",
-                    "",
-                    "",
-                    ""
+                    "011100011101010101000100000000010",
+                    "101100111101010101000100000000010",
+                    "001000101111010101000100000000010",
+                    "001100111101010101000100000000000",
+                    "011100011101010101000100000000000",
+                    "001100101111000101000100000000000",
+                    "101100111101010101000100000000000",
+                    "011100011101010101000100000000000",
+                    "001100101111010101000100000000100",
+                    "101100111101010101000100000000000",
+                    "001100011101011101000100000000000",
+                    "001100111001110101000100000000000",
+                    "001100110101010101000100000000000"
                 ],
                 "OpCode": "STA",
                 "TStates": 13
@@ -665,12 +589,7 @@
                     ""
                 ],
                 "OpCode": "SUB B",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -684,12 +603,7 @@
                     ""
                 ],
                 "OpCode": "SUB C",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -703,12 +617,7 @@
                     ""
                 ],
                 "OpCode": "XRA B",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Register",
@@ -722,12 +631,7 @@
                     ""
                 ],
                 "OpCode": "XRA C",
-                "TStates": 4,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 4
             },
             {
                 "AddressingMode": "Immediate",
@@ -741,12 +645,7 @@
                     ""
                 ],
                 "OpCode": "XRI",
-                "TStates": 7,
-                "UpdatedFetchCycleStates": [
-                    "",
-                    "",
-                    ""
-                ]
+                "TStates": 7
             }
         ],
         "SetDescription": "The full intruction set for the SAP1Emu Project.",

From b7bc3ad322308c0fb81be8d01bd038dac245e73d Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sat, 9 Jan 2021 21:37:55 -0800
Subject: [PATCH 05/20] blocked-out more gui elements

---
 SAP1EMU.GUI/Views/Home/SAP2.cshtml | 54 +++++++++++++++++++-----------
 1 file changed, 34 insertions(+), 20 deletions(-)

diff --git a/SAP1EMU.GUI/Views/Home/SAP2.cshtml b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
index bee96260..d3e746ef 100644
--- a/SAP1EMU.GUI/Views/Home/SAP2.cshtml
+++ b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
@@ -1,4 +1,9 @@
-
+@{
+    ViewData["Title"] = "SAP2";
+}
+
+
+
 
 
 
@@ -73,6 +78,13 @@
                 

             

 
+            

+                
Input

+                
+                

+                
+
+            

 
 
 
@@ -92,65 +104,67 @@
 
             

                 

-                    
Program Counter

+                    
Program Counter0000 0000  0000 0000

 
                     

                         

-                            
IPort 1

+                            
IPort 10000 0000

                         

                         

-                            
IPort 2

+                            
IPort 20000 0000

                         

                     

                     

                         

-                            
Output 1

+                            
OPort 10000 0000

                         

                         

-                            
Output 2

+                            
OPort 20000 0000

                         

                     

-                    
Display

+                    
Display0

+
+                    
Instruction Register0000 0000

+                    
Sequencer
0111 0001 1101 0101 0100 0100 0000 0001 0000

+                    
FlagsSF ZF CF UF

 
-                    
Instruction Register

-                    
Sequencer

-                    
Flags

                 

                 

                     

-                        
WBus
0x00 0x00

+                        WBus
0x00 0x00

                     

                 

                 

-                    
ALU

+
+                    
ALU0000 0000

 
                     

 
                         

-                            
MUX
 

+                            
   MUX
 

                         

                         

                             

                                 

-                                    
A Reg

+                                    
A Reg0x00

                                 

                                 

-                                    
T Reg

+                                    
T Reg0x00

                                 

                             

                             

                                 

-                                    
B Reg

+                                    
B Reg0000 0000

                                 

                             

                             

                                 

-                                    
C Reg

+                                    
C Reg0000 0000

                                 

                             

                             

                                 

-                                    
MDR

+                                    
MDR0000 0000

                                 

                             

                         

@@ -158,9 +172,9 @@
 
 
                     

-                    
RAM

+                    
RAM0000 0000  0000 0000

 
-                    
MAR

+                    
MAR0000 0000  0000 0000

                 

                 

                     
RAM


From 6485a2ec01e7ded8dcb10c765e813a53afe3bf53 Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sat, 9 Jan 2021 22:31:43 -0800
Subject: [PATCH 06/20] col justified all register contents

---
 SAP1EMU.GUI/Views/Home/SAP2.cshtml | 196 ++++++++++++++++++++++++-----
 1 file changed, 165 insertions(+), 31 deletions(-)

diff --git a/SAP1EMU.GUI/Views/Home/SAP2.cshtml b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
index d3e746ef..79001560 100644
--- a/SAP1EMU.GUI/Views/Home/SAP2.cshtml
+++ b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
@@ -83,7 +83,6 @@
                 
                 

                 
-
             

 
 
@@ -103,81 +102,216 @@
         

 
             

-                

-                    
Program Counter0000 0000  0000 0000

-
+                

+                    

+                        

+                            

+                                Program Counter
+                            

+                            

+                                0000 0000 0000 0000
+                            

+                        

+                    

                     

                         

-                            
IPort 10000 0000

+                            

+                                

+                                    

+                                        IPort 1
+                                    

+                                    

+                                        0000 0000
+                                    

+                                

+                            

                         

                         

-                            
IPort 20000 0000

+                            

+                                

+                                    

+                                        IPort 2
+                                    

+                                    

+                                        0000 0000
+                                    

+                                

+                            

                         

                     

                     

                         

-                            
OPort 10000 0000

+                            

+                                

+                                    

+                                        OPort 1
+                                    

+                                    

+                                        0000 0000
+                                    

+                                

+                            

                         

                         

-                            
OPort 20000 0000

+                            

+                                

+                                    

+                                        OPort 2
+                                    

+                                    

+                                        0000 0000
+                                    

+                                

+                            

+                        

+                    

+                    

+                        

+                            

+                                Display
+                            

+                            

+                                0
+                            

                         

                     

-                    
Display0

 
-                    
Instruction Register0000 0000

+                    

+                        

+                            

+                                Instruction Register
+                            

+                            

+                                0000 0000
+                            

+                        

+                    

                     
Sequencer
0111 0001 1101 0101 0100 0100 0000 0001 0000

-                    
FlagsSF ZF CF UF

-
+                    

+                        

+                            

+                                Flags
+                            

+                            

+                                SF ZF CF UF
+                            

+                        

+                    

                 

-                

-                    

+                

+                    

                         WBus
0x00 0x00

                     

                 

-                

-
-                    
ALU0000 0000

-
+                

+                    

+                        

+                            

+                                ALU
+                            

+                            

+                                0000 0000
+                            

+                        

+                    

                     

-
                         

                             
   MUX
 

                         

                         

                             

                                 

-                                    
A Reg0x00

+                                    

+                                        

+                                            

+                                                A Reg
+                                            

+                                            

+                                                0x00
+                                            

+                                        

+                                    

                                 

                                 

-                                    
T Reg0x00

+                                    

+                                        

+                                            

+                                                T Reg
+                                            

+                                            

+                                                0x00
+                                            

+                                        

+                                    

                                 

                             

                             

                                 

-                                    
B Reg0000 0000

+                                    

+                                        

+                                            

+                                                B Reg
+                                            

+                                            

+                                                0000 0000
+                                            

+                                        

+                                    

                                 

                             

                             

                                 

-                                    
C Reg0000 0000

+                                    

+                                        

+                                            

+                                                C Reg
+                                            

+                                            

+                                                0000 0000
+                                            

+                                        

+                                    

                                 

                             

                             

                                 

-                                    
MDR0000 0000

+                                    

+                                        

+                                            

+                                                MDR
+                                            

+                                            

+                                                0000 0000
+                                            

+                                        

+                                    

                                 

                             

                         

-
-
-
                     

-                    
RAM0000 0000  0000 0000

-
-                    
MAR0000 0000  0000 0000

+                    

+                        

+                            

+                                RAM
+                            

+                            

+                                0000 0000 0000 0000
+                            

+                        

+                    

+                    

+                        

+                            

+                                MAR
+                            

+                            

+                                0000 0000 0000 0000
+                            

+                        

+                    

                 

                 

-                    
RAM

+                    
RAM

                     @Html.TextArea("ram_dump", null, new { rows = "16", cols = "20", @class = "codebox", id = "ram_dump" })
                 

             


From 4d70985ca20ee17b08ff37de3f1d24cb20f3b978 Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sat, 9 Jan 2021 22:44:37 -0800
Subject: [PATCH 07/20] reblocked MUX text

---
 SAP1EMU.GUI/Views/Home/SAP2.cshtml | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/SAP1EMU.GUI/Views/Home/SAP2.cshtml b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
index 79001560..c23c3c5f 100644
--- a/SAP1EMU.GUI/Views/Home/SAP2.cshtml
+++ b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
@@ -216,7 +216,21 @@
                     

                     

                         

-                            
   MUX
 

+                            

+                                

+                                    

+                                        

+                                            M
+                                        

+                                        

+                                            U
+                                        

+                                        

+                                            X
+                                        

+                                    

+                                

+                            

                         

                         

                             


From fd001f635bd4f4dd9829ac37cdba85e3175fdf65 Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sat, 9 Jan 2021 23:00:58 -0800
Subject: [PATCH 08/20] centered wbus

---
 SAP1EMU.GUI/Views/Home/SAP2.cshtml | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/SAP1EMU.GUI/Views/Home/SAP2.cshtml b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
index c23c3c5f..42e62455 100644
--- a/SAP1EMU.GUI/Views/Home/SAP2.cshtml
+++ b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
@@ -200,7 +200,12 @@
                 

                 

                     

-                        WBus
0x00 0x00

+                        

+                            WBus
+                        

+                        

+                            0x00 0x00
+                        

                     

                 

                 

@@ -218,7 +223,7 @@
                         

                             

                                 

-                                    

+                                    

                                         

                                             M
                                         


From d1fc91849e12da2cf1f095a74082914adb3c25dc Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sat, 9 Jan 2021 23:10:05 -0800
Subject: [PATCH 09/20] added error box

---
 SAP1EMU.GUI/Views/Home/SAP2.cshtml | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/SAP1EMU.GUI/Views/Home/SAP2.cshtml b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
index 42e62455..788353d5 100644
--- a/SAP1EMU.GUI/Views/Home/SAP2.cshtml
+++ b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
@@ -77,18 +77,17 @@
                     

                 

             

-
             

                 
Input

                 
                 

                 
             

-
-
-
-
-            

+            

+            

+                
Errors

+                
+            

         

     

 

@@ -193,7 +192,13 @@
                                 Flags
                             

                             

-                                SF ZF CF UF
+                                

+                                    
SF

+                                    
ZF

+                                    
CF

+                                    
UF

+                                

+                                @*SF ZF CF UF*@
                             

                         

                     

@@ -336,5 +341,4 @@
             

         

     

-
 

\ No newline at end of file

From e7313fbbe9241422ec215c6354a14572016985ef Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sun, 10 Jan 2021 02:13:23 -0800
Subject: [PATCH 10/20] set ram to 8bits

---
 SAP1EMU.GUI/Views/Home/SAP2.cshtml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/SAP1EMU.GUI/Views/Home/SAP2.cshtml b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
index 788353d5..801e56d0 100644
--- a/SAP1EMU.GUI/Views/Home/SAP2.cshtml
+++ b/SAP1EMU.GUI/Views/Home/SAP2.cshtml
@@ -198,7 +198,6 @@
                                     
CF

                                     
UF

                                 

-                                @*SF ZF CF UF*@
                             

                         

                     

@@ -319,7 +318,7 @@
                                 RAM
                             
                             

-                                0000 0000 0000 0000
+                                0000 0000
                             

                         
                     

From 4df2ee04d3e662c478ab49db6ba6f14a40346f0d Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sun, 10 Jan 2021 17:51:59 -0800
Subject: [PATCH 11/20] added EmulatorPicker to nav link flow

---
 SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml | 54 +++++++++++---------
 SAP1EMU.GUI/Views/Shared/_Layout.cshtml      |  4 +-
 2 files changed, 31 insertions(+), 27 deletions(-)

diff --git a/SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml b/SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml
index 82ce4cf0..c64e620d 100644
--- a/SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml
+++ b/SAP1EMU.GUI/Views/Home/EmulatorPicker.cshtml
@@ -1,7 +1,12 @@
 @{
     ViewData["Title"] = "Emulator";
 }
-
+
 

     
Choose an Emulator

 

@@ -17,34 +22,33 @@
 

 

 

-

 

     

-        

-            

-                
-                    Card image
-                
-                
SAP1

-            

+        

+            
+                

+                    Card image
+                    
SAP-1

+                

+            
         

-        

-            

-                
-                    Card image
-                
-                
SAP2

-                Comming Soon
-
-            

+        

+            
+                

+                    Card image
+                    
SAP-2

+                    Comming Soon
+                

+            
         

-        @*

-            

-                
-                    Card image
-                
-                
8086

-            

+        @*

+            
+                

+                    Card image
+                    
8086

+                    Comming Soon
+                

+            
         
*@
     

 

diff --git a/SAP1EMU.GUI/Views/Shared/_Layout.cshtml b/SAP1EMU.GUI/Views/Shared/_Layout.cshtml
index 35b94d37..abbc8741 100644
--- a/SAP1EMU.GUI/Views/Shared/_Layout.cshtml
+++ b/SAP1EMU.GUI/Views/Shared/_Layout.cshtml
@@ -41,13 +41,13 @@
                             About
                         
                         
  • 
-                            Emulator
+                            Emulator
                         
    • 
                         
  • 
                             Assembler
                         
    • 
                         
  • 
-                            Docs
+                            Learning Center
                         
    • 
                         
  • 
                             GitHub

From 3049df7363e9bad453be9f8385bb30b077aafa23 Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sun, 10 Jan 2021 18:18:00 -0800
Subject: [PATCH 12/20] updated privacy page #122

---
 SAP1EMU.GUI/Views/Home/Privacy.cshtml | 31 +++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/SAP1EMU.GUI/Views/Home/Privacy.cshtml b/SAP1EMU.GUI/Views/Home/Privacy.cshtml
index 73abf963..ba330e2a 100644
--- a/SAP1EMU.GUI/Views/Home/Privacy.cshtml
+++ b/SAP1EMU.GUI/Views/Home/Privacy.cshtml
@@ -4,10 +4,29 @@
 
    @ViewData["Title"]
    
 
 
    
-    This site is still in beta. 
    
-    We don't sell, give away, or transfer any user-data to anyone for any reason.
-    
    
-    
    
-    Any user-data will be used for internal site inprovements for the purposes of this beta. 
    
-    This policy is subject to change in the future.
+    All users of this site and accompanying APIs must agree to the following policy.
+
    
+
    Data that SAP1Emu collects
    
+
      
+    
    • Any Code submitted to the Site via the WebApp or the API.
      • 
+    
    • Google Analytics information such as, but not limited to site-navigation-flow, country of origin, browser type, screen-resolution and time spent on each page.
      • 
+
    
+
    
+    By using this site you agree to the collection of the above information
+
    
+
+
    
+
+
    What we do with that data
    
+
      
+    
    • SAP1Emu does NOT sell any data to anyone for any reason. User Data is not for sale nor will it every be for sale.
      • 
+    
    • SAP1Emu uses submitted code to improve its emulators and processes.
      • 
+    
    • SAP1Emu uses Google Analytics to track how its users interact with the site and how that interaction can be improved.
      • 
+
    
+
+
    
+
+
    Data Removal
    
+
    
+    If you have questions about stored data or with to have user data removed, please contact SAP1Emu via sap1emubot@gmail.com
 
    
\ No newline at end of file

From 6586343f2c25407dc5df5f5c8f16a30433b38f10 Mon Sep 17 00:00:00 2001
From: Bob Baker <007dsi@gmail.com>
Date: Sun, 10 Jan 2021 18:18:47 -0800
Subject: [PATCH 13/20] typo fix

---
 SAP1EMU.GUI/Views/Home/Privacy.cshtml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/SAP1EMU.GUI/Views/Home/Privacy.cshtml b/SAP1EMU.GUI/Views/Home/Privacy.cshtml
index ba330e2a..586e77ce 100644
--- a/SAP1EMU.GUI/Views/Home/Privacy.cshtml
+++ b/SAP1EMU.GUI/Views/Home/Privacy.cshtml
@@ -28,5 +28,5 @@
 
 
    Data Removal
    
 
    
-    If you have questions about stored data or with to have user data removed, please contact SAP1Emu via sap1emubot@gmail.com
+    If you have questions about stored data or wish to have user data removed, please contact SAP1Emu via sap1emubot@gmail.com
 
    
\ No newline at end of file

From 4a711b52baaef804a3ef33f763dfe3fff1b28149 Mon Sep 17 00:00:00 2001
From: Bryce Callender 
Date: Mon, 11 Jan 2021 21:11:26 -0800
Subject: [PATCH 14/20] added jmp and jm with jump correction in SEQ and ALU
 flags are now setup

---
 SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs |    6 +-
 SAP1EMU.SAP2.Assembler/Assemble.cs           |   86 +-
 SAP1EMU.SAP2.Engine.Test/EngineTest.cs       | 1191 +++++++++++++++++-
 SAP1EMU.SAP2.Engine/EngineProc.cs            |   23 +-
 SAP1EMU.SAP2.Lib/Components/ALU.cs           |   22 +-
 SAP1EMU.SAP2.Lib/Components/SEQ.cs           |   10 +-
 SAP1EMU.SAP2.Lib/Frame.cs                    |    1 +
 SAP1EMU.SAP2.Lib/Registers/AReg.cs           |    2 +-
 SAP1EMU.SAP2.Lib/Registers/BReg.cs           |   19 +
 SAP1EMU.SAP2.Lib/Registers/CReg.cs           |   18 +
 SAP1EMU.SAP2.Lib/Registers/Flag.cs           |   29 +-
 SAP1EMU.SAP2.Lib/Registers/PC.cs             |   33 +-
 SAP1EMU.SAP2.Lib/SAP2InstructionSets.json    |  427 +++++--
 SAP1EMU.SAP2.Lib/Utilities/BinConverter.cs   |   15 +
 14 files changed, 1676 insertions(+), 206 deletions(-)

diff --git a/SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs b/SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs
index 82196b85..f7c9f0de 100644
--- a/SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs
+++ b/SAP1EMU.SAP2.Assembler.Test/AssemblerTest.cs
@@ -44,7 +44,7 @@ public void TestParseList_Valid_Code_2()
             List asm = new List
             {
                 "MVI A,0x5",
-                "JNZ 0x4",
+                "JNZ 0x6",
                 "NOP",
                 "OUT 0x3",
                 "HLT"
@@ -55,7 +55,7 @@ public void TestParseList_Valid_Code_2()
                 "00111110",
                 "00000101",
                 "11000010",
-                "00000100",
+                "00000110",
                 "00000000",
                 "00000000",
                 "11010011",
@@ -90,7 +90,7 @@ public void TestParseList_Valid_Code_2_With_Labels()
                 "00111110",
                 "00000101",
                 "11000010",
-                "00000100",
+                "00000110",
                 "00000000",
                 "00000000",
                 "11010011",
diff --git a/SAP1EMU.SAP2.Assembler/Assemble.cs b/SAP1EMU.SAP2.Assembler/Assemble.cs
index b84a5e78..be02aa7b 100644
--- a/SAP1EMU.SAP2.Assembler/Assemble.cs
+++ b/SAP1EMU.SAP2.Assembler/Assemble.cs
@@ -13,10 +13,14 @@ public static class Assemble
     {
         private const string DefaultInstructionSetName = "Malvino";
 
-        private static List