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printins.h
executable file
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printins.h
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#ifndef _PRINTINS_H_#define _PRINTINS_H_#ifdef _PRINTINS_C_#define get( adr ) ((unsigned long) vax_fetchl(adr))#define bget( adr ) ((unsigned long)vax_fetchb( adr ) & BYTE_MASK)#define ARPC ( ®list[ 1 ] )/*floating Literals*/static char * fltimm[64] = { "5.000000e-01", "5.625000e-01", "6.250000e-01", "6.875000e-01", "7.500000e-01", "8.125000e-01", "8.750000e-01", "9.375000e-01", "1.000000e+00", "1.125000e+00", "1.250000e+00", "1.375000e+00", "1.500000e+00", "1.625000e+00", "1.750000e+00", "1.875000e+00", "2.000000e+00", "2.250000e+00", "2.500000e+00", "2.750000e+00", "3.000000e+00", "3.250000e+00", "3.500000e+00", "3.750000e+00", "4.000000e+00", "4.500000e+00", "5.000000e+00", "5.500000e+00", "6.000000e+00", "6.500000e+00", "7.000000e+00", "7.500000e+00", "8.000000e+00", "9.000000e+00", "1.000000e+01", "1.100000e+01", "1.200000e+01", "1.300000e+01", "1.400000e+01", "1.500000e+01", "1.600000e+01", "1.800000e+01", "2.000000e+01", "2.200000e+01", "2.400000e+01", "2.600000e+01", "2.800000e+01", "3.000000e+01", "3.200000e+01", "3.600000e+01", "4.000000e+01", "4.400000e+01", "4.800000e+01", "5.200000e+01", "5.600000e+01", "6.000000e+01", "6.400000e+01", "7.200000e+01", "8.000000e+01", "8.800000e+01", "9.600000e+01", "1.040000e+02", "1.120000e+02", "1.200000e+02"};static char *internal_processor_registers[NUM_IPRS] ={ "KSP", /* 0x0 Kernel Stack pointer*/ "ESP", /* 0x1 Executive Stack pointer*/ "SSP", /* 0x2 Supervisor Stack pointer*/ "USP", /* 0x3 User Stack pointer*/ "ISP", /* 0x4 Interrupt Stack pointer*/ "0x05", "0x06", "0x07", "P0BR", /* 0x8 P0 base register*/ "P0LR", /* 0x9 P0 length register*/ "P1BR", /* 0xA /*P1 base register*/ "P1LR", /* 0xB /*P1 length register*/ "SBR", /* 0xC system base register*/ "SLR", /* 0xD system length register*/ "0x0E", "0x0F", "PCBB", /* 0x10 process control block base */ "SCBB", /* 0x11 system control block base (physical address)*/ "IPLR", /* 0x12 interrupt priority level*/ "ASTR", /* 0x13 Async Trap level*/ "SIRR", /* 0x14 software interrupt request register*/ "SISR", /* 0x15 software interrupt summary register*/ "0x16", "MCSR", /* 0x17 Machine Check Status register*/ "ICCS", /* 0x18 interval clock control/status register*/ "NICR", /* 0x19 next interval count register*/ "ICR", /* 0x1A interval count register*/ "TODR", /* 0x1B time of year*/ "CSRS", /* 0x1C TU58 Control Storage Receive Status*/ "CSRD", /* 0x1D TU58 Control Storage Receive Data*/ "CSTS", /* 0x1E TU58 Control Storage Transmit Status*/ "CSTD", /* 0x1F TU58 Control Storage Transmit Data*/ "RXCS", /* 0x20 Console Receive Control/Status */ "RXDB", /* 0x21 Console Receive Data Buffer*/ "TXCS", /* 0x22 Console Transmit Control/Status */ "TXDB", /* 0x23 Console Transmit Data Buffer*/ "TBDR", /* 0x24 Translation buffer disable Register*/ "CADR", /* 0x25 Cash disable Register*/ "MCESR", /* 0x26 Machine Check Error Summary register*/ "CAER", /* 0x27 Cash Error Register*/ "ACCS", /* 0x28 Accelerator Control/Status*/ "0x29", "0x2A", "0x2B", "0x2C", "0x2D", "0x2E", "0x2F", "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "IORST", /* 0x37 Initialize UNIBUS*/ "MME", /* 0x38 MAPEN Memory Management Enable */ "TBIA", /* 0x39 Translation buffer Invalidate all Register*/ "TBIS", /* 0x3A Translation buffer Invalidate Single Register*/ "TB", /* 0x3B Translation buffer Register*/ "0x3C", "PMR", /* 0x3D Performance Monitor Register*/ "SID", /* 0x3E System Identification Register*/ "TBHP", /* 0x3F Probe Translation Buffer for TB Hit*/};#define MTPR 0xda#define MFPR 0xdbstatic long var[ MAXARGS ];static address base_case;char Was_case = 0;static address jump_address = 0;static char comment_buff[512];static long comment = 0;#elseextern char Was_case;#endif#ifdef _PRINTINS_C_static void printquad( quad);static void printocta( oct);#endif/*Functions*/char *xfc_function_name(int mode);address printins( address dot);address get_branch_dest(void);void display_comment(void);#endif _PRINTINS_H_