Atomics ACT

[jjscheel]

Technical Group

Architecture Test SIG

ratification-pkg

Atomics

Technical Liaison

Allen Baum

Task Category

Arch Tests

Task Sub Category

• gcc
• binutils
• gdb
• intrinsics
• Java
• KVM
• ld
• llvm
• Linux kernel
• QEMU
• Spike

Ratification Target

3Q2023

Statement of Work (SOW)

SOW: link

SOW Signoffs:

• Task group liaison sign-off date:
• Development partner sign-off date:
• ACT SIG sign-off date (if ACT work):

Waiver

• Freeze
• Ratification

Pull Request Details

PR #1 of 2 - Merged
PR #2 of 2 - Merged
PR #3 of 2 - In review

[UmerShahidengr]

Ahad Ali from 10xEngineers will be working on this issue.

[jjscheel]

@UmerShahidengr, good to know.

Would you kindly make sure that Ahad does the following?

• Gets a Portal Id
• Joins the (DevPartners Group)[https://lists.riscv.org/g/dev-partners/topics]
• Puts his GitHub id in his profile per the (discussion)[https://lists.riscv.org/g/dev-partners/topic/risc_v_profile_update/97658653]

Then, I will add him to the project and issue.

[jjscheel]

Status from Umer:

Atomics ACTs: Ahad Ali from 10xE will be working on this project. He is also working on testplan which will be shared before the next meeting.

[jjscheel]

Ahad Ali, you should have an invitation to the project, please accept so that I can assign this issue to you.

[ahadali-10x]

@jjscheel, I haven't received an invitation to the project.

[jjscheel]

Please try looking on GitHub, either:
https://github.com/riscv-admin/ or
https://github.com/orgs/riscv-admin/teams/riscv-devpartner-partners

You should see it on the top of the page. Also, you should have received an email notification per your GitHub settings.

[ahadali-10x]

I have accepted the invitation.

[jjscheel]

I have assigned you to this issue! THANKS!!!

[UmerShahidengr]

Update: Apr 25th, 2023 => The planning phase of this project has been completed, this is the test plan for the viewers to review: Test plan Atomic Ext
Goal for next week: Develop the skeleton code (Basic R/W access) according to the ACT template, and run it on Spike via riscof.

[UmerShahidengr]

Update May 7th, 2023 ⇾ Progress has been slow so far as @ahadali-10x is learning the riscof tool, structure of existing ACTs. The initial tests will be developed till next week.

PS: Our completion date for this project is still 2023Q2, so we will accelerate this task, our 1st PR will be submitted before the next week, hopefully.

[jjscheel]

Thanks for update. Moving next touch point to next meeting and removing from this week's Agenda.

[UmerShahidengr]

Update May 23rd, 2023 => The initial set of tests are ready, and available here. PR will be submitted in 2-3 days after some fine tuning.

[jjscheel]

Excellent news, @UmerShahidengr! Marking Development Complete date. Will update state when first PR submitted. Please let me know when you submit the first one. Thanks!

[ahadali-10x]

The first patch of Atomic ACTs is submitted via PR.

[jjscheel]

Thanks, @ahadali-10x! I've moved the status to "Testing" and recorded the PR date. Is there only 1 PR anticipated?

[ahadali-10x]

No, more PRs are expected. These tests are for RV32. Tests for RV64 are remaining.

[jjscheel]

Ok. Thanks, @ahadali-10x!

[UmerShahidengr]

Update ⇾ June 12th, 2023:
Next major commit (RV64 tests) is expected this week

[jjscheel]

Thanks, Umer. Removed from this week's agenda. Will get update in next meeting.

[jjscheel]

Nice work, @UmerShahidengr and @ahadali-10x!

@allenjbaum, please confirm your sign-off of this item so that we can consider done.

[allenjbaum]

I have marked it done. Hey, that should be in the tech newsletter, eh?

…

On Tue, Sep 26, 2023 at 1:58 AM Jeff Scheel ***@***.***> wrote: Nice work, @UmerShahidengr <https://github.com/UmerShahidengr> and @ahadali-10x <https://github.com/ahadali-10x>! @allenjbaum <https://github.com/allenjbaum>, please confirm your sign-off of this item so that we can consider done. — Reply to this email directly, view it on GitHub <#25 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJQJDL4IHNSMFPJVP4DX4KKLDANCNFSM6AAAAAAV6VGA5E> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[jjscheel]

Thanks, @allenjbaum!

Yes, I opened a Newsletter item: #19.

[allenjbaum]

Well, what is there is good, but it doesn't meet the SOW.
1: No tests for unaligned atomics (which are supposed to trap, & therefore set RVTEST_MTRAP_ROUTINE)
There are actually two different trap causes: address misalign and access fault. Access fault has higher priority, and this can be tested by trying to store at an address that doesn't allow reads or writes (either a malformed address, or PMP or PTE permissions). If we're not counting on S or U modes being implemented, then we can only test this by using a physical address whose upper bits are non-zero. If we don't know the size of the PA, just set the PA to -1 The test should account for the value being intialized by explicitly writing each unaligned half, and adjusting the signature address before to point to the unaligned address and after to be the aligned value.

2. There is also no coverage of LR/SC. While we can't test what happens with an interfering access, we can test what happens in all the other cases mentioned in the spec: too many instructions between LR and SC, load/store between LR and SC (both non-interfering and interfering, where interfering is accessing any byte in the implementation-defined reservation-set size, including when an unaligned address overlaps), LRs or SCs to different addresses between otherwise well formed LR/SC pairs, trapping between LR and SC (e.g. ecall or bkpt) etc.

[jjscheel]

@allenjbaum, thanks for raising this. I've set this back to Signoff state and we likely will adjust more in the future.

@UmerShahidengr, I believe you agreed to take a look at this in the Arch Test SIG call today. I'll assign to you for now. Feel free to re-assign as needed.

[UmerShahidengr]

Thank you @jjscheel , this will be rectified before our next meeting.

[jjscheel]

No worries, @UmerShahidengr. THANKS!

[UmerShahidengr]

Update ⇾ November 28th, 2023
Here is the test plan for LR/SC tests. We will be following this test plan and will deliver the tests before the next meeting.

[UmerShahidengr]

Update ⇾ December 12th, 2023
The ACTs of LR/SC have been developed by @ahadali-10x and are in internal review stage. Tests will be available in the next week, but coverpoint definitions will take some time.

[allenjbaum]

I've added some other test coverpoints to the test plan. (in column F)

[UmerShahidengr]

Update ⇾ January 30th, 2024
Basic LR/SC tests are ready. coverpoint definitions are left. Expecting to deliver it soon.

[UmerShahidengr]

Here is the testplan: Testplan For Atomic ACTs

[UmerShahidengr]

Update ⇾ March 5th, 2024
LR/SC tests have been delivered, and are available in this PR. This SoW will be completed once this PR will be merged.

[jjscheel]

Thanks, @UmerShahidengr. I've updated the description.

[UmerShahidengr]

Update ⇾ April 2nd, 2024
LR/SC PR is yet to be merged. @allenjbaum has been notified to review it.

[jjscheel]

Thanks, Umer.

[UmerShahidengr]

Update ⇾ April 18th, 2024
@allenjbaum has reviewed LR/SC tests, these tests will be updated before the nxt meeting.

[UmerShahidengr]

Update June 11th, 2024:
LR/SC tests were shelved due to the lack of resources in this quarter, we will resume this one in the next quarter

[jjscheel]

Thanks for update, @UmerShahidengr. Let's plan for update in July.