From 32f250cc3c0d13392a7b7d16b1fc9cc6f83993c8 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Wed, 24 Nov 2021 17:43:56 +0800 Subject: [PATCH] Tweak e_flags section --- riscv-elf.adoc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/riscv-elf.adoc b/riscv-elf.adoc index 824c9b3c..f39ef76f 100644 --- a/riscv-elf.adoc +++ b/riscv-elf.adoc @@ -142,9 +142,11 @@ EM_RISCV (243) for RISC-V ELF files. We only support RISC-V v2 family ISAs, this support is implicit. e_flags:: Describes the format of this ELF file. These flags are used by the -linker to disallow linking ELF files with incompatible ABIs together. +linker to disallow linking ELF files with incompatible ABIs together, +<> shows the layout of e_flags, and flag details are listed +below. + - +[[e-flags-layout]] .Layout of e_flags [cols="1,2,1,1,3,5"] [width=80%] @@ -154,6 +156,8 @@ linker to disallow linking ELF files with incompatible ABIs together. | RVC | Float ABI | RVE | TSO | *Reserved* | *Non-standard extensions* |=== ++ +-- EF_RISCV_RVC (0x0001)::: This bit is set when the binary targets the C ABI, which allows instructions to be aligned to 16-bit boundaries (the base RV32 and RV64 ISAs only allow 32-bit instruction alignment). When linking @@ -181,18 +185,19 @@ linker to disallow linking ELF files with incompatible ABIs together. EF_RISCV_TSO (0x0010)::: This bit is set when the binary requires the RVTSO memory consistency model. -+ + Until such a time that the *Reserved* bits (0x00ffffe0) are allocated by future versions of this specification, they shall not be set by standard software. Non-standard extensions are free to use bits 24-31 for any purpose. This many conflict with other non-standard extensions. -+ + NOTE: There is no provision for compatibility between conflicting uses of the e_flags bits reserved for non-standard extensions, and many standard RISC-V tools will ignore them. Do not use them unless you control both the toolchain and the operating system, and the ABI differences are so significant they cannot be done with a .RISCV.attributes tag nor an ELF note, such as using a different syscall ABI. +-- === Sections @@ -211,7 +216,6 @@ the ABI in use. + The defined processor-specific `st_other` flags are listed in <>. + - [[rv-st-other]] .RISC-V-specific `st_other` flags [cols="3,1"]