From 914a3f3cdc4f453d6993a80caa4411e894ad9c3d Mon Sep 17 00:00:00 2001 From: Artemis Rosman Date: Fri, 10 May 2024 19:33:23 +1000 Subject: [PATCH] Add OPs table --- src/ops.rs | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/state.rs | 2 +- src/symbol.rs | 10 ++++++++ 3 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 src/ops.rs create mode 100644 src/symbol.rs diff --git a/src/ops.rs b/src/ops.rs new file mode 100644 index 0000000..7b42cc4 --- /dev/null +++ b/src/ops.rs @@ -0,0 +1,69 @@ +use crate::state::Flag; +use crate::symbol::Register; + +enum Opcodes { + // Add SR1 (source register 1) with SR2 and store in DR (destination register) + ADD { + dest_r: Register, + src_r_1: Register, + src_r_2: Choice, + }, + // Bitwise AND SR1 with SR2 and store in DR + AND { + dest_r: Register, + src_r_1: Register, + src_r_2: Choice, + }, + // Branch based on flag by adding offset to PC + BR { + cc: Flag, + pc_offset9: u16, + }, + // Set PC to BaseR + JMP { + base_r: Register, + }, + JSR { + pc_offset11: u16, + }, + JSRR { + base_r: Register, + }, + LD { + dest_r: Register, + pc_offset9: u16, + }, + LDI { + dest_r: Register, + pc_offset9: u16, + }, + LDR { + dest_r: Register, + base_r: Register, + pc_offset6: u16, + }, + LEA { + dest_r: Register, + pc_offset9: u16, + }, + NOT { + dest_r: Register, + src_r: Register, + }, + RET, + RTI, + ST { + src_r: Register, + pc_offset9: u16, + }, + STI { + src_r: Register, + pc_offset9: u16, + }, +} + +// ADD and AND commands support immediate value +enum Choice { + Reg(Register), + Imm5(u8), +} diff --git a/src/state.rs b/src/state.rs index c6b4d95..fa974b5 100644 --- a/src/state.rs +++ b/src/state.rs @@ -20,7 +20,7 @@ pub struct State { } // Set using result from previous instruction -enum Flag { +pub enum Flag { // Negative N, // Zero diff --git a/src/symbol.rs b/src/symbol.rs new file mode 100644 index 0000000..8754caa --- /dev/null +++ b/src/symbol.rs @@ -0,0 +1,10 @@ +pub enum Register { + R0 = 0, + R1, + R2, + R3, + R4, + R5, + R6, + R7, +}