implement SIMD unordered reduction intrinsics

Author: sayantn

compiler/rustc_const_eval/src/interpret/intrinsics/simd.rs

@@ -333,15 +333,39 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
                 }
                 self.write_immediate(*res, &dest)?;
             }
-            sym::simd_reduce_add_ordered | sym::simd_reduce_mul_ordered => {
+            sym::simd_reduce_add_ordered
+            | sym::simd_reduce_add_unordered
+            | sym::simd_reduce_mul_ordered
+            | sym::simd_reduce_mul_unordered => {
                 use mir::BinOp;
 
                 let (op, op_len) = self.project_to_simd(&args[0])?;
-                let init = self.read_immediate(&args[1])?;
+                let elem_ty = op.layout.ty.sequence_element_type(tcx);
+                let elem_layout = self.layout_of(elem_ty).unwrap();
+                let init = match intrinsic_name {
+                    sym::simd_reduce_add_unordered => ImmTy::from_int(0, elem_layout),
+                    sym::simd_reduce_mul_unordered => match elem_ty.kind() {
+                        ty::Int(_) => ImmTy::from_int(1i128, elem_layout),
+                        ty::Uint(_) => ImmTy::from_uint(1u128, elem_layout),
+                        ty::Float(float_ty) => ImmTy::from_scalar(
+                            match float_ty {
+                                FloatTy::F16 => Scalar::from_f16(Float::from_i128(1).value),
+                                FloatTy::F32 => Scalar::from_f32(Float::from_i128(1).value),
+                                FloatTy::F64 => Scalar::from_f64(Float::from_i128(1).value),
+                                FloatTy::F128 => Scalar::from_f128(Float::from_i128(1).value),
+                            },
+                            elem_layout,
+                        ),
+                        _ => unreachable!(
+                            "`{intrinsic_name} called with unsupported SIMD element type `{elem_ty}`"
+                        ),
+                    },
+                    _ => self.read_immediate(&args[1])?,
+                };
 
                 let mir_op = match intrinsic_name {
-                    sym::simd_reduce_add_ordered => BinOp::Add,
-                    sym::simd_reduce_mul_ordered => BinOp::Mul,
+                    sym::simd_reduce_add_ordered | sym::simd_reduce_add_unordered => BinOp::Add,
+                    sym::simd_reduce_mul_ordered | sym::simd_reduce_mul_unordered => BinOp::Mul,
                     _ => unreachable!(),
                 };