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Tracking issue for release notes of #126624: Tracking Issue for <code>sha512_sm_x86</code>

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.

relnotesMarks issues that should be documented in the release notes of the next release.Marks issues that should be documented in the release notes of the next release.

relnotes-tracking-issueMarks issues tracking what text to put in release notes.Marks issues tracking what text to put in release notes.

T-libs-apiRelevant to the library API team, which will review and decide on the PR/issue.Relevant to the library API team, which will review and decide on the PR/issue.

Status: Open.

#141778 In rust-lang/rust;

· rustbot opened on May 30, 2025

Tracking Issue for AVX10 target features

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.

C-tracking-issueCategory: An issue tracking the progress of sth. like the implementation of an RFCCategory: An issue tracking the progress of sth. like the implementation of an RFC

O-x86_32Target: x86 processors, 32 bit (like i686-*) (IA-32)Target: x86 processors, 32 bit (like i686-*) (IA-32)

O-x86_64Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)

T-libs-apiRelevant to the library API team, which will review and decide on the PR/issue.Relevant to the library API team, which will review and decide on the PR/issue.

Status: Open.

#138843 In rust-lang/rust;

· sayantn opened on Mar 22, 2025

With LLVM 20 the SIMD intrinsic <code>wasm32::u8x16_sub_sat</code> is compiled to a function call

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-bugCategory: This is a bug.Category: This is a bug.

O-wasmTarget: WASM (WebAssembly), http://webassembly.org/Target: WASM (WebAssembly), http://webassembly.org/

Status: Open.

#137419 In rust-lang/rust;

· hkratz opened on Feb 22, 2025

Bad codegen for widen followed by ARM <code>vdupq_n_*</code>

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-optimizationCategory: An issue highlighting optimization opportunities or PRs implementing suchCategory: An issue highlighting optimization opportunities or PRs implementing such

O-AArch64Armv8-A or later processors in AArch64 modeArmv8-A or later processors in AArch64 mode

P-mediumMedium priorityMedium priority

regression-from-stable-to-stablePerformance or correctness regression from one stable version to another.Performance or correctness regression from one stable version to another.

S-has-bisectionStatus: A bisection has been found for this issueStatus: A bisection has been found for this issue

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#137407 In rust-lang/rust;

· CatsAreFluffy opened on Feb 22, 2025

ICE: <code>expected SIMD field to have definite array size</code>

A-const-evalArea: Constant evaluation, covers all const contexts (static, const fn, ...)Area: Constant evaluation, covers all const contexts (static, const fn, ...)

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-bugCategory: This is a bug.Category: This is a bug.

I-ICEIssue: The compiler panicked, giving an Internal Compilation Error (ICE) ❄️Issue: The compiler panicked, giving an Internal Compilation Error (ICE) ❄️

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

WG-const-evalWorking group: Const evaluationWorking group: Const evaluation

Status: Open.

#137291 In rust-lang/rust;

· folkertdev opened on Feb 19, 2025

Projecting into non-power-of-two-lanes <code>repr(simd)</code> types does the wrong thing.

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

requires-nightlyThis issue requires a nightly compiler in some way.This issue requires a nightly compiler in some way.

Status: Open.

#137108 In rust-lang/rust;

· scottmcm opened on Feb 16, 2025

x86 softfloat target: no way to get LLVM to make local use of the FPU or SIMD registers

A-floating-pointArea: Floating point numbers and arithmeticArea: Floating point numbers and arithmetic

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-bugCategory: This is a bug.Category: This is a bug.

C-external-bugCategory: issue that is caused by bugs in software beyond our controlCategory: issue that is caused by bugs in software beyond our control

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#136540 In rust-lang/rust;

· RalfJung opened on Feb 4, 2025

Workaround for llvm bug for f32x3 saturating fp-&gt;int opt-level=0 on aarch64 is fixed in LLVM 20

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-cleanupCategory: PRs that clean code up or issues documenting cleanup.Category: PRs that clean code up or issues documenting cleanup.

O-AArch64Armv8-A or later processors in AArch64 modeArmv8-A or later processors in AArch64 mode

PG-portable-simdProject group: Portable SIMD (https://github.com/rust-lang/project-portable-simd)Project group: Portable SIMD (https://github.com/rust-lang/project-portable-simd)

T-libsRelevant to the library team, which will review and decide on the PR/issue.Relevant to the library team, which will review and decide on the PR/issue.

WG-llvmWorking group: LLVM backend code generationWorking group: LLVM backend code generation

Status: Open.

#135982 In rust-lang/rust;

· programmerjake opened on Jan 24, 2025

How should we handle dynamic vector ABIs?

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-discussionCategory: Discussion or questions that doesn't represent real issues.Category: Discussion or questions that doesn't represent real issues.

E-needs-designThis issue needs exploration and design to see how and if we can fix/implement itThis issue needs exploration and design to see how and if we can fix/implement it

O-AArch64Armv8-A or later processors in AArch64 modeArmv8-A or later processors in AArch64 mode

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#133146 In rust-lang/rust;

· workingjubilee opened on Nov 17, 2024

How should we handle SPARC's vector ABI?

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-discussionCategory: Discussion or questions that doesn't represent real issues.Category: Discussion or questions that doesn't represent real issues.

E-needs-designThis issue needs exploration and design to see how and if we can fix/implement itThis issue needs exploration and design to see how and if we can fix/implement it

O-SPARCTarget: SPARC processorsTarget: SPARC processors

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#133141 In rust-lang/rust;

· workingjubilee opened on Nov 17, 2024

Support calling functions with SIMD vectors that couldn't be used in the caller

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-feature-requestCategory: A feature request, i.e: not implemented / a PR.Category: A feature request, i.e: not implemented / a PR.

T-opsemRelevant to the opsem teamRelevant to the opsem team

WG-llvmWorking group: LLVM backend code generationWorking group: LLVM backend code generation

Status: Open.

#132865 In rust-lang/rust;

· RalfJung opened on Nov 10, 2024

<code>get_unchecked()</code> is never inlined on armv7-unknown-linux-gnueabihf in functions with <code>#[target_feature(enable = "neon")]</code>

A-codegenArea: Code generationArea: Code generation

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.

C-bugCategory: This is a bug.Category: This is a bug.

I-slowIssue: Problems and improvements with respect to performance of generated code.Issue: Problems and improvements with respect to performance of generated code.

O-ArmTarget: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 stateTarget: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#131745 In rust-lang/rust;

· hkratz opened on Oct 15, 2024