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elbertv2topmodule.bgn
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Release 14.6 - Bitgen P.68d (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s50a.nph' in environment
C:\Xilinx\14.6\ISE_DS\ISE\.
"ElbertV2TopModule" is an NCD, version 3.2, device xc3s50a, package tq144,
speed -4
Opened constraints file ElbertV2TopModule.pcf.
Thu Mar 28 11:26:24 2019
C:\Xilinx\14.6\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -filter iseconfig/filter.filter -intstyle ise -w -g Binary:yes -g Compress -g CRC:Enable -g Reset_on_err:No -g ConfigRate:25 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g en_porb:Yes -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 ElbertV2TopModule.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Enabled) |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No* |
+----------------------+----------------------+
| ConfigRate | 25 |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | Yes |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| en_porb | Yes** |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| ICAP_Enable | Auto* |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | Yes |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 1 CONFIG constraint(s) processed from ElbertV2TopModule.pcf.
CONFIG VCCAUX = "3.3"
Running DRC.
WARNING:PhysDesignRules:367 - The signal <Switch<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Switch<3>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Switch<5>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
with the CLKFX and CLKFX180 outputs of the DCM comp
clocking_inst/DCM_SP_INST, consult the device Interactive Data Sheet.
WARNING:PhysDesignRules:812 - Dangling pin <DIA0> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA1> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA2> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA3> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA4> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA5> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA6> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA7> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA8> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA9> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA10> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA11> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA12> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA13> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA14> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA15> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA16> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA17> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA18> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA19> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA20> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA21> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA22> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA23> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA24> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA25> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA26> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA27> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA28> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA29> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA30> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA31> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA0> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA1> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA2> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA3> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA4> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA5> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA6> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA7> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA8> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA9> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA10> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA11> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
DRC detected 0 errors and 47 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "elbertv2topmodule.bit".
Bitstream compression saved 43360 bits.
Saving bit stream in "elbertv2topmodule.bin".
Bitstream generation is complete.