diff --git a/basic/test_data_port_periodic_three_domains_CASE/aadl/.gitignore b/basic/test_data_port_periodic_three_domains_CASE/aadl/.gitignore new file mode 100644 index 0000000..11d04b4 --- /dev/null +++ b/basic/test_data_port_periodic_three_domains_CASE/aadl/.gitignore @@ -0,0 +1 @@ +/.aadlbin-gen/ diff --git a/basic/test_data_port_periodic_three_domains_CASE/aadl/.project b/basic/test_data_port_periodic_three_domains_CASE/aadl/.project new file mode 100644 index 0000000..6464b53 --- /dev/null +++ b/basic/test_data_port_periodic_three_domains_CASE/aadl/.project @@ -0,0 +1,18 @@ + + + test_data_port_periodic_three_domains_CASE + + + + + + org.eclipse.xtext.ui.shared.xtextBuilder + + + + + + org.osate.core.aadlnature + org.eclipse.xtext.ui.shared.xtextNature + + diff --git a/basic/test_data_port_periodic_three_domains_CASE/aadl/behavior_code/T1.c b/basic/test_data_port_periodic_three_domains_CASE/aadl/behavior_code/T1.c new file mode 100644 index 0000000..1d244d7 --- /dev/null +++ b/basic/test_data_port_periodic_three_domains_CASE/aadl/behavior_code/T1.c @@ -0,0 +1,21 @@ +#include +#include +#include +#include + +static int8_t _value; + +void init(const int64_t *in_arg) { + printf("[%s] called\n", get_instance_name()); + _value = 0; +} + +void compute(const int64_t *in_arg) { + printf("---------------------------------------\n"); + if (sb_write_port_write( &_value )) { + printf("[%s] Sent %d\n", get_instance_name(), _value); + _value = (_value + 1) % 500; + } else { + printf("[%s] Unable to send\n", get_instance_name()); + } +} \ No newline at end of file diff --git a/basic/test_data_port_periodic_three_domains_CASE/aadl/behavior_code/T2.c b/basic/test_data_port_periodic_three_domains_CASE/aadl/behavior_code/T2.c new file mode 100644 index 0000000..d05ff54 --- /dev/null +++ b/basic/test_data_port_periodic_three_domains_CASE/aadl/behavior_code/T2.c @@ -0,0 +1,24 @@ +#include +#include +#include +#include + +void init(const int64_t *in_arg) { + printf("[%s] init called\n", get_instance_name()); +} + +void compute(const int64_t * in_arg) { + int8_t _value; + + if (sb_read_port_read(&value)) { + printf("[%s] value {%d}\n", get_instance_name(), value); + + if (sb_write_port_write( &_value )) { + printf("[%s] Sent %d\n", get_instance_name(), _value); + } else { + printf("[%s] Unable to send\n", get_instance_name()); + } + } else { + printf("[%s] no value consumed.\n", get_instance_name()); + } +} \ No newline at end of file diff --git a/basic/test_data_port_periodic_three_domains_CASE/aadl/domain_schedule.c b/basic/test_data_port_periodic_three_domains_CASE/aadl/domain_schedule.c new file mode 100644 index 0000000..7bd5e2f --- /dev/null +++ b/basic/test_data_port_periodic_three_domains_CASE/aadl/domain_schedule.c @@ -0,0 +1,41 @@ +// Copyright 2020 Adventium Labs + +// This is a kernel data structure. + +#include +#include +#include + +// An arbitrary hand generated schedule. The length is in seL4 ticks +// (2 ms default). This schedule should be generated from the AADL model +// using execution time and data flow latency specifications. +// +// Pacer runs at highest rate +// +// This schedule is single-rate, 1Hz, run each thread at 200ms ticks for simplicity. +// Fill space in with domain 0. +// +// 4 T3 | - - - - +// 3 T2 | - - - - +// 2 T1 | - - - - +// 1 pacer | - - - - +// 0 dom0 |-- -- -- - ------ -- -- - ------ -- -- - ------ -- -- - ---- +// |______________|______________________________________________\time +// seconds 1 2 3 4 / +// +// Major frame is 1 seconds, since destination has 1 second period +// +const dschedule_t ksDomSchedule[] = { // (1 tick == 2ms) + { .domain = 0, .length = 100 }, // all other seL4 threads, init, 200ms + { .domain = 1, .length = 5 }, // T1 10ms + { .domain = 0, .length = 95 }, // domain0 190ms + { .domain = 2, .length = 5 }, // T2 10ms + { .domain = 0, .length = 95 }, // domain0 190ms + { .domain = 3, .length = 5 }, // T3 10ms + { .domain = 0, .length = 195 }, // domain0 390ms + // + + // ----------------------------------- + // 1000ms +}; + +const word_t ksDomScheduleLength = sizeof(ksDomSchedule) / sizeof(dschedule_t); diff --git a/basic/test_data_port_periodic_three_domains_CASE/aadl/test_data_port_periodic_three_domains.aadl b/basic/test_data_port_periodic_three_domains_CASE/aadl/test_data_port_periodic_three_domains.aadl new file mode 100644 index 0000000..c8d7f09 --- /dev/null +++ b/basic/test_data_port_periodic_three_domains_CASE/aadl/test_data_port_periodic_three_domains.aadl @@ -0,0 +1,162 @@ +package test_data_port_periodic_three_domains +public + with Base_Types; + with HAMR; + with CASE_Scheduling; + + ---------------------------------------------------------------------- + -- O n e + -- Thread T1 + -- Process P1 + -- + -- thread specifies unit of temporal execution; depending on scheduling + -- model this can provide temporal isolation. + ---------------------------------------------------------------------- + thread T1 + features + write_port: out data port Base_Types::Integer_8; + properties + Dispatch_Protocol => Periodic; + Period => 1000ms; + Compute_Execution_Time => 10ms .. 10ms; + Source_Text => ("behavior_code/T1.c"); + Initialize_Entrypoint_Source_Text => "init"; + Compute_Entrypoint_Source_Text => "compute"; + end T1; + + thread implementation T1.i + end T1.i; + + -- process specifies boundary of spatial isolation + process P1 + features + write_port: out data port Base_Types::Integer_8; + properties + CASE_Scheduling::Domain => 2; + end P1; + + process implementation P1.i + subcomponents + t1: thread T1.i; + connections + write1: port t1.write_port -> write_port; + end P1.i; + + ---------------------------------------------------------------------- + -- T w o + -- Thread T2 + -- Process P2 + -- + ---------------------------------------------------------------------- + thread T2 + features + read_port: in data port Base_Types::Integer_8; + write_port: out data port Base_Types::Integer_8; + properties + Dispatch_Protocol => Periodic; + Period => 1000ms; + Compute_Execution_Time => 10ms .. 10ms; + Source_Text => ("behavior_code/T2.c"); + Initialize_Entrypoint_Source_Text => "init"; + Compute_Entrypoint_Source_Text => "compute"; + end T2; + + thread implementation T2.i + end T2.i; + + -- process specifies boundary of spatial isolation + process P2 + features + read_port: in data port Base_Types::Integer_8; + write_port: out data port Base_Types::Integer_8; + properties + CASE_Scheduling::Domain => 3; + end P2; + + process implementation P2.i + subcomponents + t2: thread T2.i; + connections + read2: port read_port -> t2.read_port; + + write2: port t2.write_port -> write_port; + end P2.i; + + ---------------------------------------------------------------------- + -- T h r e e + -- Thread T3 + -- Process P3 + -- + ---------------------------------------------------------------------- + thread T3 + features + read_port: in data port Base_Types::Integer_8; + properties + Dispatch_Protocol => Periodic; + Period => 1000ms; + Compute_Execution_Time => 10ms .. 10ms; + end T3; + + thread implementation T3.i + end T3.i; + + -- process specifies boundary of spatial isolation + process P3 + features + read_port: in data port Base_Types::Integer_8; + properties + CASE_Scheduling::Domain => 4; + end P3; + + process implementation P3.i + subcomponents + t3: thread T3.i; + connections + read3: port read_port -> t3.read_port; + end P3.i; + + + ---------------------------------------------------------------------- + processor proc + end proc; + + processor implementation proc.impl + properties + Frame_Period => 1000ms; + Clock_Period => 2ms; + CASE_Scheduling::Max_Domain => 5; + CASE_Scheduling::Schedule_Source_Text => "domain_schedule.c"; + + end proc.impl; + + virtual processor virt_proc + properties + Dispatch_Protocol => Periodic; + end virt_proc; + + ---------------------------------------------------------------------- + system top + end top; + + system implementation top.impl + subcomponents + proc: processor proc.impl; + virt_proc: virtual processor virt_proc; + p1: process P1.i; + p2: process P2.i; + p3: process P3.i; + connections + c1: port p1.write_port -> p2.read_port; + c2: port p2.write_port -> p3.read_port; + properties + Actual_Processor_Binding => (reference (virt_proc)) applies to P3; + Actual_Processor_Binding => (reference (proc)) applies to P1, P2, virt_proc; + + HAMR::Platform => (seL4); + + annex resolute {** + check HAMR_Guidelines + **}; + end top.impl; + +end test_data_port_periodic_three_domains; \ No newline at end of file