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bbc.c
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bbc.c
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#include "bbc.h"
#include "adc.h"
#include "bbc_options.h"
#include "cmos.h"
#include "cpu_driver.h"
#include "debug.h"
#include "defs_6502.h"
#include "disc.h"
#include "disc_drive.h"
#include "intel_fdc.h"
#include "joystick.h"
#include "keyboard.h"
#include "log.h"
#include "mc6850.h"
#include "memory_access.h"
#include "os_alloc.h"
#include "os_channel.h"
#include "os_thread.h"
#include "os_time.h"
#include "render.h"
#include "serial_ula.h"
#include "sound.h"
#include "state_6502.h"
#include "tape.h"
#include "teletext.h"
#include "timing.h"
#include "util.h"
#include "via.h"
#include "video.h"
#include "wd_fdc.h"
#include "asm/asm_defs_host.h"
/* For asm_jit_uses_indirect_mappings(). */
#include "asm/asm_jit.h"
#include "asm/asm_opcodes.h"
#include "asm/asm_util.h"
#include <assert.h>
#include <inttypes.h>
#include <string.h>
static const size_t k_bbc_os_rom_offset = 0xC000;
static const size_t k_bbc_sideways_offset = 0x8000;
static const size_t k_bbc_shadow_offset = 0x3000;
static const size_t k_bbc_lynne_size = 0x5000;
static const size_t k_bbc_hazel_size = 0x2000;
static const size_t k_bbc_andy_size = 0x1000;
static const size_t k_bbc_tick_rate = 2000000; /* 2Mhz. */
static const size_t k_bbc_default_wakeup_rate = 500; /* 2ms / 500Hz. */
/* This data is from b-em, thanks b-em! */
static const int k_FE_1mhz_array[8] = { 1, 0, 1, 1, 0, 0, 1, 0 };
/* EMU: where given, any ranges are confirmed on a real model B. */
enum {
k_addr_fred = 0xFC00,
k_addr_jim = 0xFD00,
k_addr_shiela = 0xFE00,
k_addr_shiela_end = 0xFEFF,
/* &FE00 - &FE07. */
k_addr_crtc = 0xFE00,
/* &FE08 - &FE0F. */
k_addr_acia = 0xFE08,
/* &FE10 - &FE17. */
k_addr_serial_ula = 0xFE10,
/* &FE18 - &FE1B. */
k_addr_master_adc = 0xFE18,
/* &FE20 - &FE2F. */
k_addr_video_ula = 0xFE20,
/* &FE30 - &FE3F on model B. */
k_addr_master_floppy = 0xFE24,
/* &FE24 - &FE2F. */
k_addr_rom_select = 0xFE30,
/* &FE40 - &FE5F. */
k_addr_sysvia = 0xFE40,
/* &FE60 - &FE6F. */
k_addr_uservia = 0xFE60,
/* &FE80 - &FE9F. */
k_addr_floppy = 0xFE80,
k_addr_econet = 0xFEA0,
k_addr_adc = 0xFEC0,
k_addr_tube = 0xFEE0,
};
enum {
k_romsel_andy = 0x80,
};
enum {
k_acccon_display_lynne = 0x01,
k_acccon_access_lynne_from_os = 0x02,
k_acccon_lynne = 0x04,
k_acccon_hazel = 0x08,
};
struct bbc_struct {
/* Fields referenced by JIT encoded callbacks. */
struct timing_struct* p_timing;
struct via_struct* p_system_via;
struct via_struct* p_user_via;
void* p_via_read_ORB_func;
void* p_via_read_ORA_func; /* 0x20 */
void* p_via_read_T1CL_func;
void* p_via_read_T1CH_func;
void* p_via_read_T2CL_func;
void* p_via_read_T2CH_func; /* 0x40 */
void* p_via_read_ORAnh_func;
void* p_via_write_ORB_func;
void* p_via_write_ORA_func;
void* p_via_write_DDRA_func; /* 0x60 */
void* p_via_write_T1CL_func;
void* p_via_write_T1CH_func;
void* p_via_write_T2CL_func;
void* p_via_write_T2CH_func; /* 0x80 */
void* p_via_write_ACR_func;
void* p_via_write_IFR_func;
void* p_via_write_IER_func;
void* p_via_write_ORAnh_func; /* 0xA0 */
struct adc_struct* p_adc;
void* p_adc_write_control_func;
struct mc6850_struct* p_serial;
struct intel_fdc_struct* p_intel_fdc;
struct video_struct* p_video;
void* p_video_crtc_write_address_func;
void* p_video_crtc_write_value_func;
void* p_video_ula_write_ctrl_func;
void* p_video_ula_write_palette_func;
struct bbc_struct* p_bbc;
void* p_bbc_write_romsel_func;
/* Internal system mechanics. */
struct os_thread_struct* p_thread_cpu;
int thread_allocated;
int running;
intptr_t handle_channel_read_bbc;
intptr_t handle_channel_write_bbc;
intptr_t handle_channel_read_client;
intptr_t handle_channel_write_client;
uint32_t exit_value;
intptr_t mem_handle;
uint64_t rewind_to_cycles;
uint32_t log_count_shadow_speed;
uint32_t log_count_misc_unimplemented;
struct util_file* p_printer_file;
/* Machine configuration. */
int is_master;
int has_sideways_ram;
int is_sideways_ram_bank[k_bbc_num_roms];
int is_extended_rom_addressing;
int is_wd_fdc;
int is_wd_1772;
int is_nula;
/* Settings. */
uint8_t* p_os_rom;
int debug_flag;
int run_flag;
int print_flag;
int fast_flag;
int test_map_flag;
int autoboot_flag;
int do_video_memory_sync;
int do_paint_every_tick;
struct bbc_options options;
int is_compat_old_1MHz_cycles;
/* Machine state. */
struct state_6502* p_state_6502;
struct memory_access memory_access;
struct os_alloc_mapping* p_mapping_raw;
struct os_alloc_mapping* p_mapping_read;
struct os_alloc_mapping* p_mapping_write;
struct os_alloc_mapping* p_mapping_write_2;
struct os_alloc_mapping* p_mapping_read_ind;
struct os_alloc_mapping* p_mapping_write_ind;
struct os_alloc_mapping* p_mapping_write_ind_2;
uint8_t* p_mem_raw;
uint8_t* p_mem_read;
uint8_t* p_mem_write;
uint8_t* p_mem_read_ind;
uint8_t* p_mem_write_ind;
uint8_t* p_mem_sideways;
uint8_t* p_mem_master;
uint8_t* p_mem_lynne;
uint8_t* p_mem_hazel;
uint8_t* p_mem_andy;
uint8_t romsel;
uint8_t acccon;
int is_acccon_usr_mos_different;
int is_romsel_invalidated;
uint16_t read_callback_from;
uint16_t write_callback_from;
uint32_t IC32;
struct keyboard_struct* p_keyboard;
struct joystick_struct* p_joystick;
struct sound_struct* p_sound;
struct render_struct* p_render;
struct teletext_struct* p_teletext;
struct disc_drive_struct* p_drive_0;
struct disc_drive_struct* p_drive_1;
struct wd_fdc_struct* p_wd_fdc;
struct serial_ula_struct* p_serial_ula;
struct tape_struct* p_tape;
struct cmos_struct* p_cmos;
struct cpu_driver* p_cpu_driver;
struct debug_struct* p_debug;
/* Timing support. */
struct os_time_sleeper* p_sleeper;
uint32_t timer_id_cycles;
uint32_t timer_id_stop_cycles;
int32_t timer_id_autoboot;
int32_t timer_id_test_nmi;
uint32_t wakeup_rate;
uint64_t cycles_per_run_fast;
uint64_t cycles_per_run_normal;
uint64_t last_time_us;
uint64_t last_time_us_perf;
uint64_t last_cycles;
uint64_t last_frames;
uint64_t last_crtc_advances;
uint64_t last_hw_reg_hits;
uint64_t last_c1;
uint64_t last_c2;
uint64_t cycle_count_baseline;
uint64_t num_hw_reg_hits;
int log_speed;
int log_timestamp;
int log_hw_reg_hits;
};
static int
bbc_is_always_ram_address(void* p, uint16_t addr) {
(void) p;
return (addr < k_bbc_ram_size);
}
static uint16_t
bbc_read_needs_callback_from(void* p) {
struct bbc_struct* p_bbc = (struct bbc_struct*) p;
return p_bbc->read_callback_from;
}
static uint16_t
bbc_write_needs_callback_from(void* p) {
struct bbc_struct* p_bbc = (struct bbc_struct*) p;
return p_bbc->write_callback_from;
}
static int
bbc_read_needs_callback(void* p, uint16_t addr) {
struct bbc_struct* p_bbc = (struct bbc_struct*) p;
(void) p_bbc;
assert(!p_bbc->is_master);
if ((addr >= k_bbc_registers_start) &&
(addr < (k_bbc_registers_start + k_bbc_registers_len))) {
return 1;
}
return 0;
}
static int
bbc_write_needs_callback(void* p, uint16_t addr) {
struct bbc_struct* p_bbc = (struct bbc_struct*) p;
(void) p_bbc;
assert(!p_bbc->is_master);
if (p_bbc->has_sideways_ram) {
return (addr >= k_bbc_os_rom_offset);
}
if ((addr >= k_bbc_registers_start) &&
(addr < (k_bbc_registers_start + k_bbc_registers_len))) {
return 1;
}
return 0;
}
static inline int
bbc_is_1MHz_address(struct bbc_struct* p_bbc, uint16_t addr) {
if ((addr & 0xFF00) == k_addr_shiela) {
if (p_bbc->is_master) {
/* See https://stardot.org.uk/forums/viewtopic.php?f=4&t=16114#p221935,
* thanks Tom Seddon!
*/
if ((addr > 0xFEA0) ||
((addr >= 0xFE20) && (addr < 0xFE28)) ||
((addr >= 0xFE2C) && (addr < 0xFE40))) {
return 0;
}
return 1;
} else {
return k_FE_1mhz_array[((addr >> 5) & 7)];
}
}
if ((addr < k_addr_fred) || (addr > k_addr_shiela_end)) {
return 0;
}
return 1;
}
static void
bbc_do_pre_read_write_tick_handling(struct bbc_struct* p_bbc,
uint16_t addr,
uint64_t cycles,
int do_last_tick_callback) {
uint64_t alignment;
int is_1MHz = bbc_is_1MHz_address(p_bbc, addr);
if (!is_1MHz) {
if (do_last_tick_callback) {
/* If it's not 1MHz, this is the last tick. */
p_bbc->memory_access.memory_client_last_tick_callback(
p_bbc->memory_access.p_last_tick_callback_obj);
}
/* Currently, all 2MHz peripherals are handled as tick then access, except
* the video ULA.
*/
if ((addr & ~0x000F) == k_addr_video_ula) {
if (!p_bbc->is_master || (addr < (k_addr_video_ula + 4))) {
/* Access then tick. */
return;
}
}
(void) timing_advance_time_delta(p_bbc->p_timing, 1);
return;
}
/* For 1MHz, the specific peripheral handling can opt to take on the timing
* ticking itself. The VIAs do this.
*/
if ((addr >= k_addr_sysvia) && (addr < k_addr_floppy)) {
return;
}
/* It is 1MHz. Last tick will be in 1 or two ticks depending on alignment. */
alignment = (cycles & 1);
/* For most peripherals, we tick to the end of the stretched cycle and then do * the read or write.
* It's worth noting that this behavior is required for CRTC. If we fail to
* tick to the end of the stretched cycle, the writes take effect too soon.
*/
if (do_last_tick_callback) {
(void) timing_advance_time_delta(p_bbc->p_timing, (alignment + 1));
p_bbc->memory_access.memory_client_last_tick_callback(
p_bbc->memory_access.p_last_tick_callback_obj);
(void) timing_advance_time_delta(p_bbc->p_timing, 1);
} else {
(void) timing_advance_time_delta(p_bbc->p_timing, (alignment + 2));
}
}
static inline uint8_t
bbc_do_master_ram_read(struct bbc_struct* p_bbc, uint16_t addr, uint16_t pc) {
uint8_t* p_mem_raw = p_bbc->p_mem_raw;
if (addr < k_bbc_sideways_offset) {
assert(addr >= k_bbc_shadow_offset);
assert(p_bbc->is_acccon_usr_mos_different);
if ((pc > k_bbc_os_rom_offset) &&
(pc <= (k_bbc_os_rom_offset + k_bbc_hazel_size))) {
return p_bbc->p_mem_master[addr];
}
}
return p_mem_raw[addr];
}
static inline void
bbc_do_master_ram_write(struct bbc_struct* p_bbc,
uint16_t addr,
uint8_t val,
uint16_t pc) {
uint8_t* p_mem_raw = p_bbc->p_mem_raw;
if (addr < k_bbc_sideways_offset) {
assert(addr >= k_bbc_shadow_offset);
assert(p_bbc->is_acccon_usr_mos_different);
if ((pc > k_bbc_os_rom_offset) &&
(pc <= (k_bbc_os_rom_offset + k_bbc_hazel_size))) {
p_bbc->p_mem_master[addr] = val;
} else {
p_bbc->p_mem_raw[addr] = val;
}
return;
}
/* Sideways region is writeable is RAM is paged in. This is true regardless
* of whether ANDY is paged in or not.
*/
if ((addr < k_bbc_os_rom_offset) &&
p_bbc->is_sideways_ram_bank[p_bbc->romsel & 0x0F]) {
p_mem_raw[addr] = val;
return;
}
/* ANDY is writeable if paged in. */
if ((addr < (k_bbc_sideways_offset + k_bbc_andy_size)) &&
(p_bbc->romsel & k_romsel_andy)) {
p_mem_raw[addr] = val;
return;
}
/* HAZEL is writeable if paged in. */
if ((addr >= k_bbc_os_rom_offset) &&
(addr < (k_bbc_os_rom_offset + k_bbc_hazel_size)) &&
(p_bbc->acccon & k_acccon_hazel)) {
p_mem_raw[addr] = val;
return;
}
}
uint8_t
bbc_read_callback(void* p,
uint16_t addr,
uint16_t pc,
int do_last_tick_callback) {
uint8_t ret;
uint64_t cycles;
struct bbc_struct* p_bbc = (struct bbc_struct*) p;
struct timing_struct* p_timing = p_bbc->p_timing;
if (p_bbc->log_hw_reg_hits) {
log_do_log(k_log_misc,
k_log_info,
"register read $%"PRIx16" at PC $%"PRIx16,
addr,
pc);
}
if (p_bbc->is_compat_old_1MHz_cycles) {
cycles = state_6502_get_cycles(p_bbc->p_state_6502);
} else {
cycles = timing_get_total_timer_ticks(p_timing);
}
bbc_do_pre_read_write_tick_handling(p_bbc,
addr,
cycles,
do_last_tick_callback);
if (p_bbc->is_master && (addr < k_addr_fred)) {
return bbc_do_master_ram_read(p_bbc, addr, pc);
}
ret = 0xFE;
p_bbc->num_hw_reg_hits++;
switch (addr & ~3) {
case (k_addr_crtc + 0):
case (k_addr_crtc + 4):
{
struct video_struct* p_video = bbc_get_video(p_bbc);
ret = video_crtc_read(p_video, (addr & 0x1));
}
break;
case (k_addr_acia + 0):
case (k_addr_acia + 4):
ret = mc6850_read(p_bbc->p_serial, (addr & 1));
break;
case (k_addr_serial_ula + 0):
case (k_addr_serial_ula + 4):
ret = serial_ula_read(p_bbc->p_serial_ula);
break;
case (k_addr_master_adc + 0):
/* Syncron reads this even on a model B. */
if (p_bbc->is_master) {
ret = adc_read(p_bbc->p_adc, (addr & 3));
} else {
/* EMU: returns 0 on an issue 3. */
ret = 0;
log_do_log_max_count(&p_bbc->log_count_misc_unimplemented,
k_log_misc,
k_log_unimplemented,
"read of $FE18 region");
}
break;
case 0xFE1C:
/* EMU: a hole here. Returns 0 on an issue 3. */
ret = 0;
log_do_log_max_count(&p_bbc->log_count_misc_unimplemented,
k_log_misc,
k_log_unimplemented,
"read of $FE1C region");
break;
case (k_addr_video_ula + 0):
/* EMU NOTE: ULA is write-only, and reads don't seem to be wired up.
* See: https://stardot.org.uk/forums/viewtopic.php?f=4&t=17509
* Break out to default 0xFE return.
*/
(void) timing_advance_time_delta(p_timing, 1);
break;
case (k_addr_master_floppy + 0): /* k_addr_video_ula + 4 */
case (k_addr_master_floppy + 4):
if (p_bbc->is_master) {
if (addr & 0x4) {
/* TODO: testing in Aug 2023 on Tom's Master revealed that reading this
* actually exposes the last byte read by the 6845!
*/
ret = 0;
break;
}
ret = wd_fdc_read(p_bbc->p_wd_fdc, ((addr - 0x4) & 0x7));
} else {
(void) timing_advance_time_delta(p_timing, 1);
}
break;
case (k_addr_video_ula + 12):
if (!p_bbc->is_master) {
(void) timing_advance_time_delta(p_timing, 1);
}
break;
case (k_addr_rom_select + 0):
/* ROMSEL is readable on a Master but not on a model B. */
if (p_bbc->is_master) {
ret = p_bbc->romsel;
}
break;
case (k_addr_rom_select + 4):
if (p_bbc->is_master) {
ret = p_bbc->acccon;
}
break;
case (k_addr_rom_select + 8):
case (k_addr_rom_select + 12):
break;
case (k_addr_sysvia + 0):
case (k_addr_sysvia + 4):
case (k_addr_sysvia + 8):
case (k_addr_sysvia + 12):
case (k_addr_sysvia + 16):
case (k_addr_sysvia + 20):
case (k_addr_sysvia + 24):
case (k_addr_sysvia + 28):
(void) timing_advance_time_delta(p_timing, ((cycles & 1) + 1));
if (do_last_tick_callback) {
p_bbc->memory_access.memory_client_last_tick_callback(
p_bbc->memory_access.p_last_tick_callback_obj);
}
ret = via_read(p_bbc->p_system_via, (addr & 0xf));
(void) timing_advance_time_delta(p_timing, 1);
break;
case (k_addr_uservia + 0):
case (k_addr_uservia + 4):
case (k_addr_uservia + 8):
case (k_addr_uservia + 12):
case (k_addr_uservia + 16):
case (k_addr_uservia + 20):
case (k_addr_uservia + 24):
case (k_addr_uservia + 28):
(void) timing_advance_time_delta(p_timing, ((cycles & 1) + 1));
if (do_last_tick_callback) {
p_bbc->memory_access.memory_client_last_tick_callback(
p_bbc->memory_access.p_last_tick_callback_obj);
}
ret = via_read(p_bbc->p_user_via, (addr & 0xf));
(void) timing_advance_time_delta(p_timing, 1);
break;
case (k_addr_floppy + 0):
case (k_addr_floppy + 4):
case (k_addr_floppy + 8):
case (k_addr_floppy + 12):
case (k_addr_floppy + 16):
case (k_addr_floppy + 20):
case (k_addr_floppy + 24):
case (k_addr_floppy + 28):
if (!p_bbc->is_master) {
if (p_bbc->is_wd_fdc) {
ret = wd_fdc_read(p_bbc->p_wd_fdc, (addr & 0x7));
} else {
ret = intel_fdc_read(p_bbc->p_intel_fdc, (addr & 0x7));
}
}
break;
case (k_addr_econet + 0):
case (k_addr_econet + 4):
case (k_addr_econet + 8):
case (k_addr_econet + 12):
case (k_addr_econet + 16):
case (k_addr_econet + 20):
case (k_addr_econet + 24):
case (k_addr_econet + 28):
break;
case (k_addr_adc + 0):
case (k_addr_adc + 4):
case (k_addr_adc + 8):
case (k_addr_adc + 12):
case (k_addr_adc + 16):
case (k_addr_adc + 20):
case (k_addr_adc + 24):
case (k_addr_adc + 28):
if (!p_bbc->is_master) {
ret = adc_read(p_bbc->p_adc, (addr & 3));
} else {
log_do_log_max_count(&p_bbc->log_count_misc_unimplemented,
k_log_misc,
k_log_unimplemented,
"read of $FEC0-$FEDF region");
}
break;
case (k_addr_tube + 0):
case (k_addr_tube + 4):
case (k_addr_tube + 8):
case (k_addr_tube + 12):
case (k_addr_tube + 16):
case (k_addr_tube + 20):
case (k_addr_tube + 24):
case (k_addr_tube + 28):
if (p_bbc->test_map_flag) {
switch (addr) {
case (k_addr_tube + 1):
/* &FEE1: read low byte of cycles count. */
ret = (timing_get_total_timer_ticks(p_timing) -
p_bbc->cycle_count_baseline);
default:
break;
}
}
/* Not present. */
break;
default:
assert(addr >= (k_bbc_os_rom_offset - 0x100));
if ((addr < k_bbc_registers_start) ||
(addr >= (k_bbc_registers_start + k_bbc_registers_len))) {
/* If we miss the registers, it will be:
* 1) $FF00 - $FFFF on account of trapping on anything above $FC00, or
* 2) $FBxx on account of the X uncertainty of $FBxx,X, or
* 3) Temporarily(?) $BFxx on account of $BFxx,X uncertainty and we're
* trapping $C000+ on all ports (only really needed on Windows). This
* should only be able to hit with the uncarried address read for
* something like a page-crossing LDA $BFFF,X
*/
uint8_t* p_mem_read = bbc_get_mem_read(p_bbc);
ret = p_mem_read[addr];
} else if (addr >= k_addr_shiela) {
/* We should have every address covered above. */
assert(0);
} else {
/* EMU: This value, as well as the 0xFE default, copied from b-em /
* jsbeeb, and checked against a real BBC, see:
* https://stardot.org.uk/forums/viewtopic.php?f=4&t=17509
*/
ret = 0xFF;
}
break;
}
return ret;
}
uint8_t
bbc_get_romsel(struct bbc_struct* p_bbc) {
return p_bbc->romsel;
}
uint8_t
bbc_get_acccon(struct bbc_struct* p_bbc) {
return p_bbc->acccon;
}
static uint8_t
bbc_get_effective_bank(struct bbc_struct* p_bbc, uint8_t romsel) {
romsel &= 0xF;
if (!p_bbc->is_extended_rom_addressing) {
assert(!p_bbc->is_master);
/* EMU NOTE: unless the BBC has a sideways ROM / RAM board installed, all
* of the 0x0 - 0xF ROMSEL range is aliased into 0xC - 0xF.
* The STH Castle Quest image needs this due to a misguided "Master
* compatability" fix.
* See http://beebwiki.mdfs.net/Paged_ROM.
*/
romsel &= 0x3;
romsel += 0xC;
}
return romsel;
}
static void
bbc_page_rom(struct bbc_struct* p_bbc,
uint8_t effective_curr_bank,
uint8_t effective_new_bank,
uint8_t* p_sideways_old,
uint8_t* p_sideways_new) {
size_t map_size;
size_t half_map_size;
size_t map_offset;
struct cpu_driver* p_cpu_driver = p_bbc->p_cpu_driver;
int curr_is_ram = p_bbc->is_sideways_ram_bank[effective_curr_bank];
int new_is_ram = p_bbc->is_sideways_ram_bank[effective_new_bank];
uint8_t* p_mem_sideways = (p_bbc->p_mem_raw + k_bbc_sideways_offset);
intptr_t mem_handle = p_bbc->mem_handle;
/* If current bank is RAM, save it. */
if (curr_is_ram) {
(void) memcpy(p_sideways_old, p_mem_sideways, k_bbc_rom_size);
}
(void) memcpy(p_mem_sideways, p_sideways_new, k_bbc_rom_size);
/* The BBC Master mode does not support JIT (so no invalidate required).
* The BBC Master has all sorts of pageable regions, and the virtual memory
* tricks possible with the model B's clean RAM / sideways / OS ROM split
* are not possible.
*/
if (p_bbc->is_master) {
return;
}
p_cpu_driver->p_funcs->memory_range_invalidate(p_cpu_driver,
k_bbc_sideways_offset,
k_bbc_rom_size);
if (curr_is_ram == new_is_ram) {
return;
}
/* We flipped from ROM to RAM or visa versa, we need to update the write
* mapping with either a dummy area (ROM) or the real sideways area (RAM).
*/
map_size = (k_6502_addr_space_size * 2);
half_map_size = (map_size / 2);
map_offset = (k_6502_addr_space_size / 2);
os_alloc_free_mapping(p_bbc->p_mapping_write_2);
if (new_is_ram) {
p_bbc->p_mapping_write_2 = os_alloc_get_mapping_from_handle(
mem_handle,
(void*) (size_t) (K_BBC_MEM_WRITE_FULL_ADDR + map_offset),
half_map_size,
half_map_size);
os_alloc_make_mapping_none((p_bbc->p_mem_write + k_bbc_os_rom_offset),
k_bbc_rom_size);
} else {
p_bbc->p_mapping_write_2 = os_alloc_get_mapping(
(void*) (size_t) (K_BBC_MEM_WRITE_FULL_ADDR + map_offset),
half_map_size);
}
os_alloc_make_mapping_none((p_bbc->p_mem_write + k_6502_addr_space_size),
map_offset);
if (p_bbc->p_mapping_write_ind_2 == NULL) {
return;
}
os_alloc_free_mapping(p_bbc->p_mapping_write_ind_2);
if (new_is_ram) {
p_bbc->p_mapping_write_ind_2 = os_alloc_get_mapping_from_handle(
mem_handle,
(void*) (size_t) (K_BBC_MEM_WRITE_IND_ADDR + map_offset),
half_map_size,
half_map_size);
os_alloc_make_mapping_none((p_bbc->p_mem_write_ind + k_bbc_os_rom_offset),
k_bbc_rom_size);
} else {
p_bbc->p_mapping_write_ind_2 = os_alloc_get_mapping(
(void*) (size_t) (K_BBC_MEM_WRITE_IND_ADDR + map_offset),
half_map_size);
os_alloc_make_mapping_none(
(p_bbc->p_mem_write_ind + K_BBC_MEM_INACCESSIBLE_OFFSET),
K_BBC_MEM_INACCESSIBLE_LEN);
}
os_alloc_make_mapping_none(
(p_bbc->p_mem_write_ind + k_6502_addr_space_size),
map_offset);
}
void
bbc_sideways_select(struct bbc_struct* p_bbc, uint8_t val) {
/* The broad approach here is: slower sideways bank switching in order to
* enable faster memory accesses at runtime.
* Other emulators (jsbeeb, b-em) appear to make a different tradeoff: faster
* bank switching but slower memory accesses.
* By just copying ROM bytes into the single memory chunk representing the
* 6502 address space, memory access at runtime can be direct, instead of
* having to go through lookup arrays.
*/
uint8_t effective_curr_bank;
uint8_t effective_new_bank;
int is_sideways_slot_changing;
uint8_t* p_mem_sideways = (p_bbc->p_mem_raw + k_bbc_sideways_offset);
uint8_t* p_sideways_old = p_bbc->p_mem_sideways;
uint8_t* p_sideways_new = p_bbc->p_mem_sideways;
uint8_t curr_romsel = p_bbc->romsel;
int is_curr_andy = 0;
int is_new_andy = 0;
/* TODO: mask so it reads back correctly on Master. */
p_bbc->romsel = val;
effective_curr_bank = bbc_get_effective_bank(p_bbc, curr_romsel);
effective_new_bank = bbc_get_effective_bank(p_bbc, val);
assert(!(effective_curr_bank & 0xF0));
assert(!(effective_new_bank & 0xF0));
is_sideways_slot_changing = 0;
if ((effective_new_bank != effective_curr_bank) ||
p_bbc->is_romsel_invalidated) {
is_sideways_slot_changing = 1;
}
p_sideways_new += (effective_new_bank * k_bbc_rom_size);
p_sideways_old += (effective_curr_bank * k_bbc_rom_size);
if (p_bbc->is_master) {
is_curr_andy = (curr_romsel & k_romsel_andy);
is_new_andy = (val & k_romsel_andy);
if (is_curr_andy) {
if (!is_new_andy || is_sideways_slot_changing) {
/* Save ANDY back to its store. */
(void) memcpy(p_bbc->p_mem_andy, p_mem_sideways, k_bbc_andy_size);
/* Restore what is underneath ANDY. */
(void) memcpy(p_mem_sideways, p_sideways_old, k_bbc_andy_size);
}
}
}
if (is_sideways_slot_changing) {
bbc_page_rom(p_bbc,
effective_curr_bank,
effective_new_bank,
p_sideways_old,
p_sideways_new);
}
p_bbc->is_romsel_invalidated = 0;
if (p_bbc->is_master) {
if (is_new_andy) {
if (!is_curr_andy || is_sideways_slot_changing) {
/* Save data underneath ANDY in case it is RAM. */
(void) memcpy(p_sideways_new, p_mem_sideways, k_bbc_andy_size);
/* Copy in ANDY memory. */
(void) memcpy(p_mem_sideways, p_bbc->p_mem_andy, k_bbc_andy_size);
}
}
}
}
static void
bbc_write_romsel(struct bbc_struct* p_bbc, uint8_t addr, uint8_t val) {
(void) addr;
bbc_sideways_select(p_bbc, val);
}
static int
bbc_set_acccon(struct bbc_struct* p_bbc, uint8_t new_acccon) {
int mos_access_shadow;
uint8_t curr_acccon = p_bbc->acccon;
int is_curr_display_lynne = !!(curr_acccon & k_acccon_display_lynne);
int is_curr_lynne = !!(curr_acccon & k_acccon_lynne);
int is_curr_hazel = !!(curr_acccon & k_acccon_hazel);
int is_new_display_lynne = !!(new_acccon & k_acccon_display_lynne);
int is_new_access_lynne_from_os =
!!(new_acccon & k_acccon_access_lynne_from_os);
int is_new_lynne = !!(new_acccon & k_acccon_lynne);
int is_new_hazel = !!(new_acccon & k_acccon_hazel);
assert(p_bbc->is_master);
/* The video subsystem needs to know if it is displaying shadow RAM or not. */
/* This needs to happen before we page the RAM around, so that the video
* rendering can catch up with the current setup.
*/
if ((is_new_display_lynne != is_curr_display_lynne) ||
(is_new_lynne != is_curr_lynne)) {
/* We currently do copying, not paging, of shadow RAM, thanks to Windows
* paging limitations.
* This means we need to display "shadow" RAM in non-shadow mode, if the
* shadow RAM is paged in. This is because in that case, the normal RAM
* for normal mode will have been copied / swapped with the shadow RAM.
*/
int is_shadow_display = (is_new_display_lynne ^ is_new_lynne);
video_shadow_mode_updated(p_bbc->p_video, is_shadow_display);
}
if (is_curr_lynne ^ is_new_lynne) {
size_t val;
uint32_t i;
uint32_t count = (k_bbc_lynne_size / sizeof(val));
size_t* p1 = (size_t*) p_bbc->p_mem_lynne;
size_t* p2 = (size_t*) (p_bbc->p_mem_raw + k_bbc_shadow_offset);
for (i = 0; i < count; ++i) {
val = p1[i];
p1[i] = p2[i];
p2[i] = val;
}
}
p_bbc->acccon = new_acccon;
/* HAZEL paging. */
if (is_curr_hazel ^ is_new_hazel) {
uint8_t* p_raw_mem_hazel = (p_bbc->p_mem_raw + k_bbc_os_rom_offset);
if (is_new_hazel) {
(void) memcpy(p_raw_mem_hazel, p_bbc->p_mem_hazel, k_bbc_hazel_size);
} else {
(void) memcpy(p_bbc->p_mem_hazel, p_raw_mem_hazel, k_bbc_hazel_size);
(void) memcpy(p_raw_mem_hazel, p_bbc->p_os_rom, k_bbc_hazel_size);
}
}
/* Trap access to 0x3000 - 0x7FFF if the crazy MOS ROM VDU access is different
* to normal access.
*/
/* Reference: b2 source code. Thanks Tom Seddon.
* Also, see test/games/Nubium 20181214 b.ssd, which doesn't run correctly
* on a correctly emulated Master, see:
* https://stardot.org.uk/forums/viewtopic.php?p=223299#p223299
* Note that the combination that surprises me is HAZEL=0, LYNNE=1, E=0.
* This causes the MOS VDU code region to access _main_ RAM, not LYNNE as
* you might expect.
*/
mos_access_shadow = ((is_new_hazel && is_new_lynne) ||
(!is_new_hazel && is_new_access_lynne_from_os));
if (mos_access_shadow != is_new_lynne) {
if (!p_bbc->is_acccon_usr_mos_different) {
log_do_log_max_count(&p_bbc->log_count_shadow_speed,
k_log_misc,
k_log_info,
"shadow region SLOW access");
}
p_bbc->is_acccon_usr_mos_different = 1;
p_bbc->write_callback_from = k_bbc_shadow_offset;
p_bbc->read_callback_from = k_bbc_shadow_offset;
} else {
if (p_bbc->is_acccon_usr_mos_different) {
log_do_log_max_count(&p_bbc->log_count_shadow_speed,
k_log_misc,
k_log_info,
"shadow region fast access");
}
p_bbc->is_acccon_usr_mos_different = 0;
p_bbc->write_callback_from = k_bbc_sideways_offset;
p_bbc->read_callback_from = k_bbc_registers_start;
}
/* Always force reload of write callback address. */
return 1;
}
static void
bbc_test_nmi_timer_callback(void* p) {
struct bbc_struct* p_bbc = (struct bbc_struct*) p;
(void) timing_stop_timer(p_bbc->p_timing, p_bbc->timer_id_test_nmi);
if (p_bbc->p_intel_fdc != NULL) {
intel_fdc_testing_fire_nmi(p_bbc->p_intel_fdc);
}
}
int
bbc_write_callback(void* p,
uint16_t addr,
uint8_t val,
uint16_t pc,
int do_last_tick_callback) {
uint64_t cycles;
int ret = 0;
struct bbc_struct* p_bbc = (struct bbc_struct*) p;
struct timing_struct* p_timing = p_bbc->p_timing;
if (p_bbc->log_hw_reg_hits) {
log_do_log(k_log_misc,
k_log_info,
"register write $%"PRIx16" val $%"PRIx8" at PC $%"PRIx16,
addr,
val,
pc);
}
if (p_bbc->is_compat_old_1MHz_cycles) {
cycles = state_6502_get_cycles(p_bbc->p_state_6502);
} else {
cycles = timing_get_total_timer_ticks(p_timing);
}
bbc_do_pre_read_write_tick_handling(p_bbc,
addr,
cycles,
do_last_tick_callback);
if (p_bbc->is_master && (addr < k_addr_fred)) {
bbc_do_master_ram_write(p_bbc, addr, val, pc);
return 0;