From 1b130b84b99c995ba3238a9a822e0e08cbd59d55 Mon Sep 17 00:00:00 2001 From: Simon Wright Date: Fri, 13 Mar 2020 16:25:54 +0000 Subject: [PATCH] Generate board interface code in Makefiles. * arduino-due/Makefile: generate hardware interface from SVD. * microbit/Makefile: likewise. * stm32f4/Makefile: likewise. * stm32f429i/Makefile: likewise. * arduino-due/atsam3x8e/*: regenerated. * microbit/nrf51/*: regenerated. * microbit/nrf51/nrf51-interrupts.adb: removed. * microbit/nrf51/nrf51-interrupts.ads: likewise. * stm32f4/stm32f40x/*: regenerated. * stm32f429i/stm32f429x/*: regenerated. * arduino-due/adainclude/startup-set_up_clock.adb: register type name changed. * microbit/adainclude/nrf51_clock.adb (Start): likewise. * microbit/build_runtime.gpr (Compiler): apply -gnatwU to nrf51_swi.ads (System was withed but not used). --- arduino-due/Makefile | 13 +- .../adainclude/startup-set_up_clock.adb | 4 +- arduino-due/atsam3x8e/atsam3x8e-adc.ads | 1069 ++-- arduino-due/atsam3x8e/atsam3x8e-can.ads | 1122 ++-- arduino-due/atsam3x8e/atsam3x8e-chipid.ads | 203 +- arduino-due/atsam3x8e/atsam3x8e-dacc.ads | 673 +-- arduino-due/atsam3x8e/atsam3x8e-dmac.ads | 1267 ++--- arduino-due/atsam3x8e/atsam3x8e-ebi.ads | 1497 ++--- arduino-due/atsam3x8e/atsam3x8e-efc.ads | 114 +- arduino-due/atsam3x8e/atsam3x8e-emac.ads | 1138 ++-- arduino-due/atsam3x8e/atsam3x8e-hsmci.ads | 1836 ++++-- arduino-due/atsam3x8e/atsam3x8e-matrix.ads | 214 +- arduino-due/atsam3x8e/atsam3x8e-pio.ads | 1150 ++-- arduino-due/atsam3x8e/atsam3x8e-pmc.ads | 514 +- arduino-due/atsam3x8e/atsam3x8e-pwm.ads | 2388 ++++---- arduino-due/atsam3x8e/atsam3x8e-spi.ads | 464 +- arduino-due/atsam3x8e/atsam3x8e-ssc.ads | 748 +-- arduino-due/atsam3x8e/atsam3x8e-sysc.ads | 2341 ++++---- arduino-due/atsam3x8e/atsam3x8e-tc.ads | 1500 +++-- arduino-due/atsam3x8e/atsam3x8e-trng.ads | 108 +- arduino-due/atsam3x8e/atsam3x8e-twi.ads | 651 +-- arduino-due/atsam3x8e/atsam3x8e-uart.ads | 516 +- arduino-due/atsam3x8e/atsam3x8e-uotghs.ads | 3948 +++++++------ arduino-due/atsam3x8e/atsam3x8e-usart.ads | 1655 +++--- arduino-due/atsam3x8e/atsam3x8e.ads | 125 +- microbit/Makefile | 16 +- microbit/adainclude/nrf51_clock.adb | 2 +- microbit/build_runtime.gpr | 1 + microbit/nrf51/nrf51-aar.ads | 277 +- microbit/nrf51/nrf51-adc.ads | 265 +- microbit/nrf51/nrf51-amli.ads | 393 +- microbit/nrf51/nrf51-ccm.ads | 322 +- microbit/nrf51/nrf51-clock.ads | 471 +- microbit/nrf51/nrf51-ecb.ads | 180 +- microbit/nrf51/nrf51-ficr.ads | 194 +- microbit/nrf51/nrf51-gpio.ads | 289 +- microbit/nrf51/nrf51-gpiote.ads | 219 +- microbit/nrf51/nrf51-interrupts.adb | 39 - microbit/nrf51/nrf51-interrupts.ads | 19 - microbit/nrf51/nrf51-lpcomp.ads | 445 +- microbit/nrf51/nrf51-mpu.ads | 330 +- microbit/nrf51/nrf51-nvmc.ads | 124 +- microbit/nrf51/nrf51-power.ads | 448 +- microbit/nrf51/nrf51-ppi.ads | 343 +- microbit/nrf51/nrf51-qdec.ads | 473 +- microbit/nrf51/nrf51-radio.ads | 1063 ++-- microbit/nrf51/nrf51-rng.ads | 174 +- microbit/nrf51/nrf51-rtc.ads | 487 +- microbit/nrf51/nrf51-spi.ads | 214 +- microbit/nrf51/nrf51-spim.ads | 503 +- microbit/nrf51/nrf51-spis.ads | 472 +- microbit/nrf51/nrf51-swi.ads | 37 +- microbit/nrf51/nrf51-temp.ads | 132 +- microbit/nrf51/nrf51-timer.ads | 312 +- microbit/nrf51/nrf51-twi.ads | 546 +- microbit/nrf51/nrf51-uart.ads | 591 +- microbit/nrf51/nrf51-uicr.ads | 133 +- microbit/nrf51/nrf51-wdt.ads | 345 +- microbit/nrf51/nrf51.ads | 138 +- stm32f4/Makefile | 15 +- stm32f4/stm32f40x/stm32f40x-adc.ads | 394 +- stm32f4/stm32f40x/stm32f40x-can.ads | 1258 ++--- stm32f4/stm32f40x/stm32f40x-crc.ads | 37 +- stm32f4/stm32f40x/stm32f40x-dac.ads | 234 +- stm32f4/stm32f40x/stm32f40x-dbg.ads | 59 +- stm32f4/stm32f40x/stm32f40x-dcmi.ads | 164 +- stm32f4/stm32f40x/stm32f40x-dma.ads | 549 +- stm32f4/stm32f40x/stm32f40x-ethernet.ads | 2369 ++++---- stm32f4/stm32f40x/stm32f40x-exti.ads | 101 +- stm32f4/stm32f40x/stm32f40x-flash.ads | 61 +- stm32f4/stm32f40x/stm32f40x-fsmc.ads | 401 +- stm32f4/stm32f40x/stm32f40x-gpio.ads | 174 +- stm32f4/stm32f40x/stm32f40x-i2c.ads | 139 +- stm32f4/stm32f40x/stm32f40x-iwdg.ads | 61 +- stm32f4/stm32f40x/stm32f40x-nvic.ads | 209 +- stm32f4/stm32f40x/stm32f40x-pwr.ads | 29 +- stm32f4/stm32f40x/stm32f40x-rcc.ads | 291 +- stm32f4/stm32f40x/stm32f40x-rng.ads | 33 +- stm32f4/stm32f40x/stm32f40x-rtc.ads | 398 +- stm32f4/stm32f40x/stm32f40x-sdio.ads | 366 +- stm32f4/stm32f40x/stm32f40x-spi.ads | 151 +- stm32f4/stm32f40x/stm32f40x-syscfg.ads | 208 +- stm32f4/stm32f40x/stm32f40x-tim.ads | 1649 +++--- stm32f4/stm32f40x/stm32f40x-usart.ads | 401 +- stm32f4/stm32f40x/stm32f40x-usb_otg_fs.ads | 3876 +++++++------ stm32f4/stm32f40x/stm32f40x-usb_otg_hs.ads | 4914 ++++++++--------- stm32f4/stm32f40x/stm32f40x-wwdg.ads | 46 +- stm32f4/stm32f40x/stm32f40x.ads | 230 +- stm32f429i/Makefile | 15 +- stm32f429i/stm32f429x/stm32f429x-adc.ads | 458 +- stm32f429i/stm32f429x/stm32f429x-can.ads | 1282 ++--- stm32f429i/stm32f429x/stm32f429x-crc.ads | 40 +- stm32f429i/stm32f429x/stm32f429x-dac.ads | 231 +- stm32f429i/stm32f429x/stm32f429x-dbg.ads | 58 +- stm32f429i/stm32f429x/stm32f429x-dcmi.ads | 167 +- stm32f429i/stm32f429x/stm32f429x-dma.ads | 542 +- stm32f429i/stm32f429x/stm32f429x-dma2d.ads | 235 +- stm32f429i/stm32f429x/stm32f429x-ethernet.ads | 2128 ++++--- stm32f429i/stm32f429x/stm32f429x-exti.ads | 98 +- stm32f429i/stm32f429x/stm32f429x-flash.ads | 77 +- stm32f429i/stm32f429x/stm32f429x-fsmc.ads | 586 +- stm32f429i/stm32f429x/stm32f429x-gpio.ads | 198 +- stm32f429i/stm32f429x/stm32f429x-i2c.ads | 176 +- stm32f429i/stm32f429x/stm32f429x-iwdg.ads | 62 +- stm32f429i/stm32f429x/stm32f429x-ltdc.ads | 455 +- stm32f429i/stm32f429x/stm32f429x-nvic.ads | 217 +- stm32f429i/stm32f429x/stm32f429x-pwr.ads | 85 +- stm32f429i/stm32f429x/stm32f429x-rcc.ads | 343 +- stm32f429i/stm32f429x/stm32f429x-rng.ads | 40 +- stm32f429i/stm32f429x/stm32f429x-rtc.ads | 400 +- stm32f429i/stm32f429x/stm32f429x-sai.ads | 206 +- stm32f429i/stm32f429x/stm32f429x-sdio.ads | 364 +- stm32f429i/stm32f429x/stm32f429x-spi.ads | 167 +- stm32f429i/stm32f429x/stm32f429x-syscfg.ads | 209 +- stm32f429i/stm32f429x/stm32f429x-tim.ads | 2093 +++++-- stm32f429i/stm32f429x/stm32f429x-usart.ads | 366 +- .../stm32f429x/stm32f429x-usb_otg_fs.ads | 3835 +++++++------ .../stm32f429x/stm32f429x-usb_otg_hs.ads | 4862 ++++++++-------- stm32f429i/stm32f429x/stm32f429x-wwdg.ads | 46 +- stm32f429i/stm32f429x/stm32f429x.ads | 263 +- 120 files changed, 37945 insertions(+), 36431 deletions(-) delete mode 100644 microbit/nrf51/nrf51-interrupts.adb delete mode 100644 microbit/nrf51/nrf51-interrupts.ads diff --git a/arduino-due/Makefile b/arduino-due/Makefile index e9d0e16..51a2c59 100644 --- a/arduino-due/Makefile +++ b/arduino-due/Makefile @@ -16,13 +16,22 @@ # along with this program; see the file COPYING3. If not, see # . -all: +SVD2ADA ?= ~/adacore/svd2ada + +all: atsam3x8e gprbuild -p -P build_runtime.gpr +atsam3x8e: + $(SVD2ADA)/svd2ada \ + --output=atsam3x8e \ + --no-vfa-on-types \ + $(SVD2ADA)/CMSIS-SVD/ATMEL/ATSAM3X8E.svd + install: all gprinstall -p -P build_runtime.gpr -f clean: - gprclean -P build_runtime.gpr + -gprclean -P build_runtime.gpr + rm -rf atsam3x8e .PHONY: all install clean diff --git a/arduino-due/adainclude/startup-set_up_clock.adb b/arduino-due/adainclude/startup-set_up_clock.adb index a040cbd..4deeba6 100644 --- a/arduino-due/adainclude/startup-set_up_clock.adb +++ b/arduino-due/adainclude/startup-set_up_clock.adb @@ -1,4 +1,4 @@ --- Copyright (C) 2016 Free Software Foundation, Inc. +-- Copyright (C) 2016, 2020 Free Software Foundation, Inc. -- -- This file is part of the Cortex GNAT RTS project. This file is -- free software; you can redistribute it and/or modify it under @@ -34,7 +34,7 @@ procedure Set_Up_Clock is begin -- Set Flash wait states (FWS) to 4 in both banks declare - FMR : FMR_Register; + FMR : EFC0_FMR_Register; begin FMR := EFC0_Periph.FMR; FMR.FWS := 4; diff --git a/arduino-due/atsam3x8e/atsam3x8e-adc.ads b/arduino-due/atsam3x8e/atsam3x8e-adc.ads index 225a7f1..f187671 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-adc.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-adc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,51 +15,41 @@ package ATSAM3X8E.ADC is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_SWRST_Field is ATSAM3X8E.Bit; - subtype CR_START_Field is ATSAM3X8E.Bit; + subtype ADC_CR_SWRST_Field is ATSAM3X8E.Bit; + subtype ADC_CR_START_Field is ATSAM3X8E.Bit; -- Control Register - type CR_Register is record + type ADC_CR_Register is record -- Write-only. Software Reset - SWRST : CR_SWRST_Field := 16#0#; + SWRST : ADC_CR_SWRST_Field := 16#0#; -- Write-only. Start Conversion - START : CR_START_Field := 16#0#; + START : ADC_CR_START_Field := 16#0#; -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for ADC_CR_Register use record SWRST at 0 range 0 .. 0; START at 0 range 1 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------- - -- MR_Register -- - ----------------- - -- Trigger Enable - type TRGEN_Field is - ( - -- Hardware triggers are disabled. Starting a conversion is only - -- possible by software. + type MR_TRGEN_Field is + (-- Hardware triggers are disabled. Starting a conversion is only possible by +-- software. Dis, -- Hardware trigger selected by TRGSEL field is enabled. En) with Size => 1; - for TRGEN_Field use + for MR_TRGEN_Field use (Dis => 0, En => 1); -- Trigger Selection - type TRGSEL_Field is - ( - -- External : ADCTRG + type MR_TRGSEL_Field is + (-- External : ADCTRG Adc_Trig0, -- TIOA Output of the Timer Counter Channel 0 Adc_Trig1, @@ -71,7 +62,7 @@ package ATSAM3X8E.ADC is -- PWM Event Line 0 Adc_Trig5) with Size => 3; - for TRGSEL_Field use + for MR_TRGSEL_Field use (Adc_Trig0 => 0, Adc_Trig1 => 1, Adc_Trig2 => 2, @@ -80,62 +71,57 @@ package ATSAM3X8E.ADC is Adc_Trig5 => 5); -- Resolution - type LOWRES_Field is - ( - -- 12-bit resolution + type MR_LOWRES_Field is + (-- 12-bit resolution Bits_12, -- 10-bit resolution Bits_10) with Size => 1; - for LOWRES_Field use + for MR_LOWRES_Field use (Bits_12 => 0, Bits_10 => 1); -- Sleep Mode - type SLEEP_Field is - ( - -- Normal Mode: The ADC Core and reference voltage circuitry are kept ON - -- between conversions + type MR_SLEEP_Field is + (-- Normal Mode: The ADC Core and reference voltage circuitry are kept ON +-- between conversions Normal, - -- Sleep Mode: The ADC Core and reference voltage circuitry are OFF - -- between conversions + -- Sleep Mode: The ADC Core and reference voltage circuitry are OFF between +-- conversions Sleep) with Size => 1; - for SLEEP_Field use + for MR_SLEEP_Field use (Normal => 0, Sleep => 1); -- Fast Wake Up - type FWUP_Field is - ( - -- Normal Sleep Mode: The sleep mode is defined by the SLEEP bit + type MR_FWUP_Field is + (-- Normal Sleep Mode: The sleep mode is defined by the SLEEP bit Off, - -- Fast Wake Up Sleep Mode: The Voltage reference is ON between - -- conversions and ADC Core is OFF + -- Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions +-- and ADC Core is OFF On) with Size => 1; - for FWUP_Field use + for MR_FWUP_Field use (Off => 0, On => 1); -- Free Run Mode - type FREERUN_Field is - ( - -- Normal Mode + type MR_FREERUN_Field is + (-- Normal Mode Off, -- Free Run Mode: Never wait for any trigger. On) with Size => 1; - for FREERUN_Field use + for MR_FREERUN_Field use (Off => 0, On => 1); - subtype MR_PRESCAL_Field is ATSAM3X8E.Byte; + subtype ADC_MR_PRESCAL_Field is ATSAM3X8E.Byte; -- Start Up Time - type STARTUP_Field is - ( - -- 0 periods of ADCClock + type MR_STARTUP_Field is + (-- 0 periods of ADCClock Sut0, -- 8 periods of ADCClock Sut8, @@ -168,7 +154,7 @@ package ATSAM3X8E.ADC is -- 960 periods of ADCClock Sut960) with Size => 4; - for STARTUP_Field use + for MR_STARTUP_Field use (Sut0 => 0, Sut8 => 1, Sut16 => 2, @@ -187,9 +173,8 @@ package ATSAM3X8E.ADC is Sut960 => 15); -- Analog Settling Time - type SETTLING_Field is - ( - -- 3 periods of ADCClock + type MR_SETTLING_Field is + (-- 3 periods of ADCClock Ast3, -- 5 periods of ADCClock Ast5, @@ -198,79 +183,76 @@ package ATSAM3X8E.ADC is -- 17 periods of ADCClock Ast17) with Size => 2; - for SETTLING_Field use + for MR_SETTLING_Field use (Ast3 => 0, Ast5 => 1, Ast9 => 2, Ast17 => 3); -- Analog Change - type ANACH_Field is - ( - -- No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used - -- for all channels + type MR_ANACH_Field is + (-- No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for +-- all channels None, - -- Allows different analog settings for each channel. See ADC_CGR and - -- ADC_COR Registers + -- Allows different analog settings for each channel. See ADC_CGR and ADC_COR +-- Registers Allowed) with Size => 1; - for ANACH_Field use + for MR_ANACH_Field use (None => 0, Allowed => 1); - subtype MR_TRACKTIM_Field is ATSAM3X8E.UInt4; - subtype MR_TRANSFER_Field is ATSAM3X8E.UInt2; + subtype ADC_MR_TRACKTIM_Field is ATSAM3X8E.UInt4; + subtype ADC_MR_TRANSFER_Field is ATSAM3X8E.UInt2; -- Use Sequence Enable - type USEQ_Field is - ( - -- Normal Mode: The controller converts channels in a simple numeric - -- order. + type MR_USEQ_Field is + (-- Normal Mode: The controller converts channels in a simple numeric order. Num_Order, - -- User Sequence Mode: The sequence respects what is defined in - -- ADC_SEQR1 and ADC_SEQR2 registers. + -- User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and +-- ADC_SEQR2 registers. Reg_Order) with Size => 1; - for USEQ_Field use + for MR_USEQ_Field use (Num_Order => 0, Reg_Order => 1); -- Mode Register - type MR_Register is record + type ADC_MR_Register is record -- Trigger Enable - TRGEN : TRGEN_Field := Dis; + TRGEN : MR_TRGEN_Field := ATSAM3X8E.ADC.Dis; -- Trigger Selection - TRGSEL : TRGSEL_Field := Adc_Trig0; + TRGSEL : MR_TRGSEL_Field := ATSAM3X8E.ADC.Adc_Trig0; -- Resolution - LOWRES : LOWRES_Field := Bits_12; + LOWRES : MR_LOWRES_Field := ATSAM3X8E.ADC.Bits_12; -- Sleep Mode - SLEEP : SLEEP_Field := Normal; + SLEEP : MR_SLEEP_Field := ATSAM3X8E.ADC.Normal; -- Fast Wake Up - FWUP : FWUP_Field := Off; + FWUP : MR_FWUP_Field := ATSAM3X8E.ADC.Off; -- Free Run Mode - FREERUN : FREERUN_Field := Off; + FREERUN : MR_FREERUN_Field := ATSAM3X8E.ADC.Off; -- Prescaler Rate Selection - PRESCAL : MR_PRESCAL_Field := 16#0#; + PRESCAL : ADC_MR_PRESCAL_Field := 16#0#; -- Start Up Time - STARTUP : STARTUP_Field := Sut0; + STARTUP : MR_STARTUP_Field := ATSAM3X8E.ADC.Sut0; -- Analog Settling Time - SETTLING : SETTLING_Field := Ast3; + SETTLING : MR_SETTLING_Field := ATSAM3X8E.ADC.Ast3; -- unspecified Reserved_22_22 : ATSAM3X8E.Bit := 16#0#; -- Analog Change - ANACH : ANACH_Field := None; + ANACH : MR_ANACH_Field := ATSAM3X8E.ADC.None; -- Tracking Time - TRACKTIM : MR_TRACKTIM_Field := 16#0#; + TRACKTIM : ADC_MR_TRACKTIM_Field := 16#0#; -- Transfer Period - TRANSFER : MR_TRANSFER_Field := 16#0#; + TRANSFER : ADC_MR_TRANSFER_Field := 16#0#; -- unspecified Reserved_30_30 : ATSAM3X8E.Bit := 16#0#; -- Use Sequence Enable - USEQ : USEQ_Field := Num_Order; + USEQ : MR_USEQ_Field := ATSAM3X8E.ADC.Num_Order; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_Register use record + for ADC_MR_Register use record TRGEN at 0 range 0 .. 0; TRGSEL at 0 range 1 .. 3; LOWRES at 0 range 4 .. 4; @@ -288,272 +270,262 @@ package ATSAM3X8E.ADC is USEQ at 0 range 31 .. 31; end record; - ------------------- - -- SEQR_Register -- - ------------------- - - -- SEQR1_USCH array element - subtype SEQR1_USCH_Element is ATSAM3X8E.UInt4; + -- ADC_SEQR1_USCH array element + subtype ADC_SEQR1_USCH_Element is ATSAM3X8E.UInt4; - -- SEQR1_USCH array - type SEQR1_USCH_Field_Array is array (0 .. 7) of SEQR1_USCH_Element + -- ADC_SEQR1_USCH array + type ADC_SEQR1_USCH_Field_Array is array (1 .. 8) + of ADC_SEQR1_USCH_Element with Component_Size => 4, Size => 32; -- Channel Sequence Register 1 - type SEQR_Register + type ADC_SEQR1_Register (As_Array : Boolean := False) is record case As_Array is when False => -- USCH as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- USCH as an array - Arr : SEQR1_USCH_Field_Array; + Arr : ADC_SEQR1_USCH_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for SEQR_Register use record + for ADC_SEQR1_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- CHER_Register -- - ------------------- + -- ADC_SEQR2_USCH array element + subtype ADC_SEQR2_USCH_Element is ATSAM3X8E.UInt4; - ------------- - -- CHER.CH -- - ------------- + -- ADC_SEQR2_USCH array + type ADC_SEQR2_USCH_Field_Array is array (9 .. 16) + of ADC_SEQR2_USCH_Element + with Component_Size => 4, Size => 32; - -- CHER_CH array element - subtype CHER_CH_Element is ATSAM3X8E.Bit; + -- Channel Sequence Register 2 + type ADC_SEQR2_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- USCH as a value + Val : ATSAM3X8E.UInt32; + when True => + -- USCH as an array + Arr : ADC_SEQR2_USCH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Object_Size => 32, + Bit_Order => System.Low_Order_First; - -- CHER_CH array - type CHER_CH_Field_Array is array (0 .. 15) of CHER_CH_Element + for ADC_SEQR2_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- ADC_CHER_CH array element + subtype ADC_CHER_CH_Element is ATSAM3X8E.Bit; + + -- ADC_CHER_CH array + type ADC_CHER_CH_Field_Array is array (0 .. 15) of ADC_CHER_CH_Element with Component_Size => 1, Size => 16; - -- Type definition for CHER_CH - type CHER_CH_Field + -- Type definition for ADC_CHER_CH + type ADC_CHER_CH_Field (As_Array : Boolean := False) is record case As_Array is when False => -- CH as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- CH as an array - Arr : CHER_CH_Field_Array; + Arr : ADC_CHER_CH_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for CHER_CH_Field use record + for ADC_CHER_CH_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; -- Channel Enable Register - type CHER_Register is record + type ADC_CHER_Register is record -- Write-only. Channel 0 Enable - CH : CHER_CH_Field := (As_Array => False, Val => 16#0#); + CH : ADC_CHER_CH_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHER_Register use record + for ADC_CHER_Register use record CH at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- CHDR_Register -- - ------------------- - - ------------- - -- CHDR.CH -- - ------------- - - -- CHDR_CH array element - subtype CHDR_CH_Element is ATSAM3X8E.Bit; + -- ADC_CHDR_CH array element + subtype ADC_CHDR_CH_Element is ATSAM3X8E.Bit; - -- CHDR_CH array - type CHDR_CH_Field_Array is array (0 .. 15) of CHDR_CH_Element + -- ADC_CHDR_CH array + type ADC_CHDR_CH_Field_Array is array (0 .. 15) of ADC_CHDR_CH_Element with Component_Size => 1, Size => 16; - -- Type definition for CHDR_CH - type CHDR_CH_Field + -- Type definition for ADC_CHDR_CH + type ADC_CHDR_CH_Field (As_Array : Boolean := False) is record case As_Array is when False => -- CH as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- CH as an array - Arr : CHDR_CH_Field_Array; + Arr : ADC_CHDR_CH_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for CHDR_CH_Field use record + for ADC_CHDR_CH_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; -- Channel Disable Register - type CHDR_Register is record + type ADC_CHDR_Register is record -- Write-only. Channel 0 Disable - CH : CHDR_CH_Field := (As_Array => False, Val => 16#0#); + CH : ADC_CHDR_CH_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHDR_Register use record + for ADC_CHDR_Register use record CH at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- CHSR_Register -- - ------------------- + -- ADC_CHSR_CH array element + subtype ADC_CHSR_CH_Element is ATSAM3X8E.Bit; - ------------- - -- CHSR.CH -- - ------------- - - -- CHSR_CH array element - subtype CHSR_CH_Element is ATSAM3X8E.Bit; - - -- CHSR_CH array - type CHSR_CH_Field_Array is array (0 .. 15) of CHSR_CH_Element + -- ADC_CHSR_CH array + type ADC_CHSR_CH_Field_Array is array (0 .. 15) of ADC_CHSR_CH_Element with Component_Size => 1, Size => 16; - -- Type definition for CHSR_CH - type CHSR_CH_Field + -- Type definition for ADC_CHSR_CH + type ADC_CHSR_CH_Field (As_Array : Boolean := False) is record case As_Array is when False => -- CH as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- CH as an array - Arr : CHSR_CH_Field_Array; + Arr : ADC_CHSR_CH_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for CHSR_CH_Field use record + for ADC_CHSR_CH_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; -- Channel Status Register - type CHSR_Register is record + type ADC_CHSR_Register is record -- Read-only. Channel 0 Status - CH : CHSR_CH_Field := (As_Array => False, Val => 16#0#); + CH : ADC_CHSR_CH_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHSR_Register use record + for ADC_CHSR_Register use record CH at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- LCDR_Register -- - ------------------- - - subtype LCDR_LDATA_Field is ATSAM3X8E.UInt12; - subtype LCDR_CHNB_Field is ATSAM3X8E.UInt4; + subtype ADC_LCDR_LDATA_Field is ATSAM3X8E.UInt12; + subtype ADC_LCDR_CHNB_Field is ATSAM3X8E.UInt4; -- Last Converted Data Register - type LCDR_Register is record + type ADC_LCDR_Register is record -- Read-only. Last Data Converted - LDATA : LCDR_LDATA_Field := 16#0#; + LDATA : ADC_LCDR_LDATA_Field; -- Read-only. Channel Number - CHNB : LCDR_CHNB_Field := 16#0#; + CHNB : ADC_LCDR_CHNB_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for LCDR_Register use record + for ADC_LCDR_Register use record LDATA at 0 range 0 .. 11; CHNB at 0 range 12 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - ------------- - -- IER.EOC -- - ------------- - - -- IER_EOC array element - subtype IER_EOC_Element is ATSAM3X8E.Bit; + -- ADC_IER_EOC array element + subtype ADC_IER_EOC_Element is ATSAM3X8E.Bit; - -- IER_EOC array - type IER_EOC_Field_Array is array (0 .. 15) of IER_EOC_Element + -- ADC_IER_EOC array + type ADC_IER_EOC_Field_Array is array (0 .. 15) of ADC_IER_EOC_Element with Component_Size => 1, Size => 16; - -- Type definition for IER_EOC - type IER_EOC_Field + -- Type definition for ADC_IER_EOC + type ADC_IER_EOC_Field (As_Array : Boolean := False) is record case As_Array is when False => -- EOC as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- EOC as an array - Arr : IER_EOC_Field_Array; + Arr : ADC_IER_EOC_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for IER_EOC_Field use record + for ADC_IER_EOC_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; - subtype IER_DRDY_Field is ATSAM3X8E.Bit; - subtype IER_GOVRE_Field is ATSAM3X8E.Bit; - subtype IER_COMPE_Field is ATSAM3X8E.Bit; - subtype IER_ENDRX_Field is ATSAM3X8E.Bit; - subtype IER_RXBUFF_Field is ATSAM3X8E.Bit; + subtype ADC_IER_DRDY_Field is ATSAM3X8E.Bit; + subtype ADC_IER_GOVRE_Field is ATSAM3X8E.Bit; + subtype ADC_IER_COMPE_Field is ATSAM3X8E.Bit; + subtype ADC_IER_ENDRX_Field is ATSAM3X8E.Bit; + subtype ADC_IER_RXBUFF_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type ADC_IER_Register is record -- Write-only. End of Conversion Interrupt Enable 0 - EOC : IER_EOC_Field := (As_Array => False, Val => 16#0#); + EOC : ADC_IER_EOC_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_16_23 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Data Ready Interrupt Enable - DRDY : IER_DRDY_Field := 16#0#; + DRDY : ADC_IER_DRDY_Field := 16#0#; -- Write-only. General Overrun Error Interrupt Enable - GOVRE : IER_GOVRE_Field := 16#0#; + GOVRE : ADC_IER_GOVRE_Field := 16#0#; -- Write-only. Comparison Event Interrupt Enable - COMPE : IER_COMPE_Field := 16#0#; + COMPE : ADC_IER_COMPE_Field := 16#0#; -- Write-only. End of Receive Buffer Interrupt Enable - ENDRX : IER_ENDRX_Field := 16#0#; + ENDRX : ADC_IER_ENDRX_Field := 16#0#; -- Write-only. Receive Buffer Full Interrupt Enable - RXBUFF : IER_RXBUFF_Field := 16#0#; + RXBUFF : ADC_IER_RXBUFF_Field := 16#0#; -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for ADC_IER_Register use record EOC at 0 range 0 .. 15; Reserved_16_23 at 0 range 16 .. 23; DRDY at 0 range 24 .. 24; @@ -564,69 +536,61 @@ package ATSAM3X8E.ADC is Reserved_29_31 at 0 range 29 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ + -- ADC_IDR_EOC array element + subtype ADC_IDR_EOC_Element is ATSAM3X8E.Bit; - ------------- - -- IDR.EOC -- - ------------- - - -- IDR_EOC array element - subtype IDR_EOC_Element is ATSAM3X8E.Bit; - - -- IDR_EOC array - type IDR_EOC_Field_Array is array (0 .. 15) of IDR_EOC_Element + -- ADC_IDR_EOC array + type ADC_IDR_EOC_Field_Array is array (0 .. 15) of ADC_IDR_EOC_Element with Component_Size => 1, Size => 16; - -- Type definition for IDR_EOC - type IDR_EOC_Field + -- Type definition for ADC_IDR_EOC + type ADC_IDR_EOC_Field (As_Array : Boolean := False) is record case As_Array is when False => -- EOC as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- EOC as an array - Arr : IDR_EOC_Field_Array; + Arr : ADC_IDR_EOC_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for IDR_EOC_Field use record + for ADC_IDR_EOC_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; - subtype IDR_DRDY_Field is ATSAM3X8E.Bit; - subtype IDR_GOVRE_Field is ATSAM3X8E.Bit; - subtype IDR_COMPE_Field is ATSAM3X8E.Bit; - subtype IDR_ENDRX_Field is ATSAM3X8E.Bit; - subtype IDR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype ADC_IDR_DRDY_Field is ATSAM3X8E.Bit; + subtype ADC_IDR_GOVRE_Field is ATSAM3X8E.Bit; + subtype ADC_IDR_COMPE_Field is ATSAM3X8E.Bit; + subtype ADC_IDR_ENDRX_Field is ATSAM3X8E.Bit; + subtype ADC_IDR_RXBUFF_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type ADC_IDR_Register is record -- Write-only. End of Conversion Interrupt Disable 0 - EOC : IDR_EOC_Field := (As_Array => False, Val => 16#0#); + EOC : ADC_IDR_EOC_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_16_23 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Data Ready Interrupt Disable - DRDY : IDR_DRDY_Field := 16#0#; + DRDY : ADC_IDR_DRDY_Field := 16#0#; -- Write-only. General Overrun Error Interrupt Disable - GOVRE : IDR_GOVRE_Field := 16#0#; + GOVRE : ADC_IDR_GOVRE_Field := 16#0#; -- Write-only. Comparison Event Interrupt Disable - COMPE : IDR_COMPE_Field := 16#0#; + COMPE : ADC_IDR_COMPE_Field := 16#0#; -- Write-only. End of Receive Buffer Interrupt Disable - ENDRX : IDR_ENDRX_Field := 16#0#; + ENDRX : ADC_IDR_ENDRX_Field := 16#0#; -- Write-only. Receive Buffer Full Interrupt Disable - RXBUFF : IDR_RXBUFF_Field := 16#0#; + RXBUFF : ADC_IDR_RXBUFF_Field := 16#0#; -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for ADC_IDR_Register use record EOC at 0 range 0 .. 15; Reserved_16_23 at 0 range 16 .. 23; DRDY at 0 range 24 .. 24; @@ -637,69 +601,61 @@ package ATSAM3X8E.ADC is Reserved_29_31 at 0 range 29 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - ------------- - -- IMR.EOC -- - ------------- - - -- IMR_EOC array element - subtype IMR_EOC_Element is ATSAM3X8E.Bit; + -- ADC_IMR_EOC array element + subtype ADC_IMR_EOC_Element is ATSAM3X8E.Bit; - -- IMR_EOC array - type IMR_EOC_Field_Array is array (0 .. 15) of IMR_EOC_Element + -- ADC_IMR_EOC array + type ADC_IMR_EOC_Field_Array is array (0 .. 15) of ADC_IMR_EOC_Element with Component_Size => 1, Size => 16; - -- Type definition for IMR_EOC - type IMR_EOC_Field + -- Type definition for ADC_IMR_EOC + type ADC_IMR_EOC_Field (As_Array : Boolean := False) is record case As_Array is when False => -- EOC as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- EOC as an array - Arr : IMR_EOC_Field_Array; + Arr : ADC_IMR_EOC_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for IMR_EOC_Field use record + for ADC_IMR_EOC_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; - subtype IMR_DRDY_Field is ATSAM3X8E.Bit; - subtype IMR_GOVRE_Field is ATSAM3X8E.Bit; - subtype IMR_COMPE_Field is ATSAM3X8E.Bit; - subtype IMR_ENDRX_Field is ATSAM3X8E.Bit; - subtype IMR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype ADC_IMR_DRDY_Field is ATSAM3X8E.Bit; + subtype ADC_IMR_GOVRE_Field is ATSAM3X8E.Bit; + subtype ADC_IMR_COMPE_Field is ATSAM3X8E.Bit; + subtype ADC_IMR_ENDRX_Field is ATSAM3X8E.Bit; + subtype ADC_IMR_RXBUFF_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type ADC_IMR_Register is record -- Read-only. End of Conversion Interrupt Mask 0 - EOC : IMR_EOC_Field := (As_Array => False, Val => 16#0#); + EOC : ADC_IMR_EOC_Field; -- unspecified Reserved_16_23 : ATSAM3X8E.Byte; -- Read-only. Data Ready Interrupt Mask - DRDY : IMR_DRDY_Field := 16#0#; + DRDY : ADC_IMR_DRDY_Field; -- Read-only. General Overrun Error Interrupt Mask - GOVRE : IMR_GOVRE_Field := 16#0#; + GOVRE : ADC_IMR_GOVRE_Field; -- Read-only. Comparison Event Interrupt Mask - COMPE : IMR_COMPE_Field := 16#0#; + COMPE : ADC_IMR_COMPE_Field; -- Read-only. End of Receive Buffer Interrupt Mask - ENDRX : IMR_ENDRX_Field := 16#0#; + ENDRX : ADC_IMR_ENDRX_Field; -- Read-only. Receive Buffer Full Interrupt Mask - RXBUFF : IMR_RXBUFF_Field := 16#0#; + RXBUFF : ADC_IMR_RXBUFF_Field; -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for ADC_IMR_Register use record EOC at 0 range 0 .. 15; Reserved_16_23 at 0 range 16 .. 23; DRDY at 0 range 24 .. 24; @@ -710,69 +666,61 @@ package ATSAM3X8E.ADC is Reserved_29_31 at 0 range 29 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ + -- ADC_ISR_EOC array element + subtype ADC_ISR_EOC_Element is ATSAM3X8E.Bit; - ------------- - -- ISR.EOC -- - ------------- - - -- ISR_EOC array element - subtype ISR_EOC_Element is ATSAM3X8E.Bit; - - -- ISR_EOC array - type ISR_EOC_Field_Array is array (0 .. 15) of ISR_EOC_Element + -- ADC_ISR_EOC array + type ADC_ISR_EOC_Field_Array is array (0 .. 15) of ADC_ISR_EOC_Element with Component_Size => 1, Size => 16; - -- Type definition for ISR_EOC - type ISR_EOC_Field + -- Type definition for ADC_ISR_EOC + type ADC_ISR_EOC_Field (As_Array : Boolean := False) is record case As_Array is when False => -- EOC as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- EOC as an array - Arr : ISR_EOC_Field_Array; + Arr : ADC_ISR_EOC_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for ISR_EOC_Field use record + for ADC_ISR_EOC_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; - subtype ISR_DRDY_Field is ATSAM3X8E.Bit; - subtype ISR_GOVRE_Field is ATSAM3X8E.Bit; - subtype ISR_COMPE_Field is ATSAM3X8E.Bit; - subtype ISR_ENDRX_Field is ATSAM3X8E.Bit; - subtype ISR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype ADC_ISR_DRDY_Field is ATSAM3X8E.Bit; + subtype ADC_ISR_GOVRE_Field is ATSAM3X8E.Bit; + subtype ADC_ISR_COMPE_Field is ATSAM3X8E.Bit; + subtype ADC_ISR_ENDRX_Field is ATSAM3X8E.Bit; + subtype ADC_ISR_RXBUFF_Field is ATSAM3X8E.Bit; -- Interrupt Status Register - type ISR_Register is record + type ADC_ISR_Register is record -- Read-only. End of Conversion 0 - EOC : ISR_EOC_Field := (As_Array => False, Val => 16#0#); + EOC : ADC_ISR_EOC_Field; -- unspecified Reserved_16_23 : ATSAM3X8E.Byte; -- Read-only. Data Ready - DRDY : ISR_DRDY_Field := 16#0#; + DRDY : ADC_ISR_DRDY_Field; -- Read-only. General Overrun Error - GOVRE : ISR_GOVRE_Field := 16#0#; + GOVRE : ADC_ISR_GOVRE_Field; -- Read-only. Comparison Error - COMPE : ISR_COMPE_Field := 16#0#; + COMPE : ADC_ISR_COMPE_Field; -- Read-only. End of RX Buffer - ENDRX : ISR_ENDRX_Field := 16#0#; + ENDRX : ADC_ISR_ENDRX_Field; -- Read-only. RX Buffer Full - RXBUFF : ISR_RXBUFF_Field := 16#0#; + RXBUFF : ADC_ISR_RXBUFF_Field; -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ISR_Register use record + for ADC_ISR_Register use record EOC at 0 range 0 .. 15; Reserved_16_23 at 0 range 16 .. 23; DRDY at 0 range 24 .. 24; @@ -783,112 +731,97 @@ package ATSAM3X8E.ADC is Reserved_29_31 at 0 range 29 .. 31; end record; - ------------------- - -- OVER_Register -- - ------------------- - - --------------- - -- OVER.OVRE -- - --------------- - - -- OVER_OVRE array element - subtype OVER_OVRE_Element is ATSAM3X8E.Bit; + -- ADC_OVER_OVRE array element + subtype ADC_OVER_OVRE_Element is ATSAM3X8E.Bit; - -- OVER_OVRE array - type OVER_OVRE_Field_Array is array (0 .. 15) of OVER_OVRE_Element + -- ADC_OVER_OVRE array + type ADC_OVER_OVRE_Field_Array is array (0 .. 15) of ADC_OVER_OVRE_Element with Component_Size => 1, Size => 16; - -- Type definition for OVER_OVRE - type OVER_OVRE_Field + -- Type definition for ADC_OVER_OVRE + type ADC_OVER_OVRE_Field (As_Array : Boolean := False) is record case As_Array is when False => -- OVRE as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- OVRE as an array - Arr : OVER_OVRE_Field_Array; + Arr : ADC_OVER_OVRE_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for OVER_OVRE_Field use record + for ADC_OVER_OVRE_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; -- Overrun Status Register - type OVER_Register is record + type ADC_OVER_Register is record -- Read-only. Overrun Error 0 - OVRE : OVER_OVRE_Field := (As_Array => False, Val => 16#0#); + OVRE : ADC_OVER_OVRE_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OVER_Register use record + for ADC_OVER_Register use record OVRE at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- EMR_Register -- - ------------------ - -- Comparison Mode - type CMPMODE_Field is - ( - -- Generates an event when the converted data is lower than the low - -- threshold of the window. + type EMR_CMPMODE_Field is + (-- Generates an event when the converted data is lower than the low threshold +-- of the window. Low, -- Generates an event when the converted data is higher than the high - -- threshold of the window. +-- threshold of the window. High, - -- Generates an event when the converted data is in the comparison - -- window. + -- Generates an event when the converted data is in the comparison window. In_k, - -- Generates an event when the converted data is out of the comparison - -- window. + -- Generates an event when the converted data is out of the comparison window. Out_k) with Size => 2; - for CMPMODE_Field use + for EMR_CMPMODE_Field use (Low => 0, High => 1, In_k => 2, Out_k => 3); - subtype EMR_CMPSEL_Field is ATSAM3X8E.UInt4; - subtype EMR_CMPALL_Field is ATSAM3X8E.Bit; - subtype EMR_CMPFILTER_Field is ATSAM3X8E.UInt2; - subtype EMR_TAG_Field is ATSAM3X8E.Bit; + subtype ADC_EMR_CMPSEL_Field is ATSAM3X8E.UInt4; + subtype ADC_EMR_CMPALL_Field is ATSAM3X8E.Bit; + subtype ADC_EMR_CMPFILTER_Field is ATSAM3X8E.UInt2; + subtype ADC_EMR_TAG_Field is ATSAM3X8E.Bit; -- Extended Mode Register - type EMR_Register is record + type ADC_EMR_Register is record -- Comparison Mode - CMPMODE : CMPMODE_Field := Low; + CMPMODE : EMR_CMPMODE_Field := ATSAM3X8E.ADC.Low; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- Comparison Selected Channel - CMPSEL : EMR_CMPSEL_Field := 16#0#; + CMPSEL : ADC_EMR_CMPSEL_Field := 16#0#; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit := 16#0#; -- Compare All Channels - CMPALL : EMR_CMPALL_Field := 16#0#; + CMPALL : ADC_EMR_CMPALL_Field := 16#0#; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2 := 16#0#; -- Compare Event Filtering - CMPFILTER : EMR_CMPFILTER_Field := 16#0#; + CMPFILTER : ADC_EMR_CMPFILTER_Field := 16#0#; -- unspecified Reserved_14_23 : ATSAM3X8E.UInt10 := 16#0#; -- TAG of ADC_LDCR register - TAG : EMR_TAG_Field := 16#0#; + TAG : ADC_EMR_TAG_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EMR_Register use record + for ADC_EMR_Register use record CMPMODE at 0 range 0 .. 1; Reserved_2_3 at 0 range 2 .. 3; CMPSEL at 0 range 4 .. 7; @@ -901,191 +834,160 @@ package ATSAM3X8E.ADC is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- CWR_Register -- - ------------------ - - subtype CWR_LOWTHRES_Field is ATSAM3X8E.UInt12; - subtype CWR_HIGHTHRES_Field is ATSAM3X8E.UInt12; + subtype ADC_CWR_LOWTHRES_Field is ATSAM3X8E.UInt12; + subtype ADC_CWR_HIGHTHRES_Field is ATSAM3X8E.UInt12; -- Compare Window Register - type CWR_Register is record + type ADC_CWR_Register is record -- Low Threshold - LOWTHRES : CWR_LOWTHRES_Field := 16#0#; + LOWTHRES : ADC_CWR_LOWTHRES_Field := 16#0#; -- unspecified Reserved_12_15 : ATSAM3X8E.UInt4 := 16#0#; -- High Threshold - HIGHTHRES : CWR_HIGHTHRES_Field := 16#0#; + HIGHTHRES : ADC_CWR_HIGHTHRES_Field := 16#0#; -- unspecified Reserved_28_31 : ATSAM3X8E.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CWR_Register use record + for ADC_CWR_Register use record LOWTHRES at 0 range 0 .. 11; Reserved_12_15 at 0 range 12 .. 15; HIGHTHRES at 0 range 16 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------ - -- CGR_Register -- - ------------------ + -- ADC_CGR_GAIN array element + subtype ADC_CGR_GAIN_Element is ATSAM3X8E.UInt2; - -- CGR_GAIN array element - subtype CGR_GAIN_Element is ATSAM3X8E.UInt2; - - -- CGR_GAIN array - type CGR_GAIN_Field_Array is array (0 .. 15) of CGR_GAIN_Element + -- ADC_CGR_GAIN array + type ADC_CGR_GAIN_Field_Array is array (0 .. 15) of ADC_CGR_GAIN_Element with Component_Size => 2, Size => 32; -- Channel Gain Register - type CGR_Register + type ADC_CGR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- GAIN as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- GAIN as an array - Arr : CGR_GAIN_Field_Array; + Arr : ADC_CGR_GAIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for CGR_Register use record + for ADC_CGR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- COR_Register -- - ------------------ - - ------------- - -- COR.OFF -- - ------------- + -- ADC_COR_OFF array element + subtype ADC_COR_OFF_Element is ATSAM3X8E.Bit; - -- COR_OFF array element - subtype COR_OFF_Element is ATSAM3X8E.Bit; - - -- COR_OFF array - type COR_OFF_Field_Array is array (0 .. 15) of COR_OFF_Element + -- ADC_COR_OFF array + type ADC_COR_OFF_Field_Array is array (0 .. 15) of ADC_COR_OFF_Element with Component_Size => 1, Size => 16; - -- Type definition for COR_OFF - type COR_OFF_Field + -- Type definition for ADC_COR_OFF + type ADC_COR_OFF_Field (As_Array : Boolean := False) is record case As_Array is when False => -- OFF as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- OFF as an array - Arr : COR_OFF_Field_Array; + Arr : ADC_COR_OFF_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for COR_OFF_Field use record + for ADC_COR_OFF_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; - -------------- - -- COR.DIFF -- - -------------- - - -- COR_DIFF array element - subtype COR_DIFF_Element is ATSAM3X8E.Bit; + -- ADC_COR_DIFF array element + subtype ADC_COR_DIFF_Element is ATSAM3X8E.Bit; - -- COR_DIFF array - type COR_DIFF_Field_Array is array (0 .. 15) of COR_DIFF_Element + -- ADC_COR_DIFF array + type ADC_COR_DIFF_Field_Array is array (0 .. 15) of ADC_COR_DIFF_Element with Component_Size => 1, Size => 16; - -- Type definition for COR_DIFF - type COR_DIFF_Field + -- Type definition for ADC_COR_DIFF + type ADC_COR_DIFF_Field (As_Array : Boolean := False) is record case As_Array is when False => -- DIFF as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- DIFF as an array - Arr : COR_DIFF_Field_Array; + Arr : ADC_COR_DIFF_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for COR_DIFF_Field use record + for ADC_COR_DIFF_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; -- Channel Offset Register - type COR_Register is record + type ADC_COR_Register is record -- Offset for channel 0 - OFF : COR_OFF_Field := (As_Array => False, Val => 16#0#); + OFF : ADC_COR_OFF_Field := (As_Array => False, Val => 16#0#); -- Differential inputs for channel 0 - DIFF : COR_DIFF_Field := (As_Array => False, Val => 16#0#); + DIFF : ADC_COR_DIFF_Field := (As_Array => False, Val => 16#0#); end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for COR_Register use record + for ADC_COR_Register use record OFF at 0 range 0 .. 15; DIFF at 0 range 16 .. 31; end record; - ------------------ - -- CDR_Register -- - ------------------ - - subtype CDR_DATA_Field is ATSAM3X8E.UInt12; + subtype ADC_CDR_DATA_Field is ATSAM3X8E.UInt12; -- Channel Data Register - type CDR_Register is record + type ADC_CDR_Register is record -- Read-only. Converted Data - DATA : CDR_DATA_Field := 16#0#; + DATA : ADC_CDR_DATA_Field; -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CDR_Register use record + for ADC_CDR_Register use record DATA at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - -- Channel Data Register - type CDR_Registers is array (0 .. 15) of CDR_Register; - - ------------------ - -- ACR_Register -- - ------------------ - - subtype ACR_TSON_Field is ATSAM3X8E.Bit; - subtype ACR_IBCTL_Field is ATSAM3X8E.UInt2; + subtype ADC_ACR_TSON_Field is ATSAM3X8E.Bit; + subtype ADC_ACR_IBCTL_Field is ATSAM3X8E.UInt2; -- Analog Control Register - type ACR_Register is record + type ADC_ACR_Register is record -- unspecified Reserved_0_3 : ATSAM3X8E.UInt4 := 16#0#; -- Temperature Sensor On - TSON : ACR_TSON_Field := 16#0#; + TSON : ADC_ACR_TSON_Field := 16#0#; -- unspecified Reserved_5_7 : ATSAM3X8E.UInt3 := 16#0#; -- ADC Bias Current Control - IBCTL : ACR_IBCTL_Field := 16#1#; + IBCTL : ADC_ACR_IBCTL_Field := 16#1#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ACR_Register use record + for ADC_ACR_Register use record Reserved_0_3 at 0 range 0 .. 3; TSON at 0 range 4 .. 4; Reserved_5_7 at 0 range 5 .. 7; @@ -1093,124 +995,104 @@ package ATSAM3X8E.ADC is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype ADC_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype ADC_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- Write Protect Mode Register - type WPMR_Register is record + type ADC_WPMR_Register is record -- Write Protect Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : ADC_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protect KEY - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : ADC_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for ADC_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype WPSR_WPVSRC_Field is ATSAM3X8E.Short; + subtype ADC_WPSR_WPVS_Field is ATSAM3X8E.Bit; + subtype ADC_WPSR_WPVSRC_Field is ATSAM3X8E.UInt16; -- Write Protect Status Register - type WPSR_Register is record + type ADC_WPSR_Register is record -- Read-only. Write Protect Violation Status - WPVS : WPSR_WPVS_Field := 16#0#; + WPVS : ADC_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protect Violation Source - WPVSRC : WPSR_WPVSRC_Field := 16#0#; + WPVSRC : ADC_WPSR_WPVSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for ADC_WPSR_Register use record WPVS at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPVSRC at 0 range 8 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- RCR_Register -- - ------------------ - - subtype RCR_RXCTR_Field is ATSAM3X8E.Short; + subtype ADC_RCR_RXCTR_Field is ATSAM3X8E.UInt16; -- Receive Counter Register - type RCR_Register is record + type ADC_RCR_Register is record -- Receive Counter Register - RXCTR : RCR_RXCTR_Field := 16#0#; + RXCTR : ADC_RCR_RXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RCR_Register use record + for ADC_RCR_Register use record RXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- RNCR_Register -- - ------------------- - - subtype RNCR_RXNCTR_Field is ATSAM3X8E.Short; + subtype ADC_RNCR_RXNCTR_Field is ATSAM3X8E.UInt16; -- Receive Next Counter Register - type RNCR_Register is record + type ADC_RNCR_Register is record -- Receive Next Counter - RXNCTR : RNCR_RXNCTR_Field := 16#0#; + RXNCTR : ADC_RNCR_RXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RNCR_Register use record + for ADC_RNCR_Register use record RXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- PTCR_Register -- - ------------------- - - subtype PTCR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_RXTDIS_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTDIS_Field is ATSAM3X8E.Bit; + subtype ADC_PTCR_RXTEN_Field is ATSAM3X8E.Bit; + subtype ADC_PTCR_RXTDIS_Field is ATSAM3X8E.Bit; + subtype ADC_PTCR_TXTEN_Field is ATSAM3X8E.Bit; + subtype ADC_PTCR_TXTDIS_Field is ATSAM3X8E.Bit; -- Transfer Control Register - type PTCR_Register is record + type ADC_PTCR_Register is record -- Write-only. Receiver Transfer Enable - RXTEN : PTCR_RXTEN_Field := 16#0#; + RXTEN : ADC_PTCR_RXTEN_Field := 16#0#; -- Write-only. Receiver Transfer Disable - RXTDIS : PTCR_RXTDIS_Field := 16#0#; + RXTDIS : ADC_PTCR_RXTDIS_Field := 16#0#; -- unspecified Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; -- Write-only. Transmitter Transfer Enable - TXTEN : PTCR_TXTEN_Field := 16#0#; + TXTEN : ADC_PTCR_TXTEN_Field := 16#0#; -- Write-only. Transmitter Transfer Disable - TXTDIS : PTCR_TXTDIS_Field := 16#0#; + TXTDIS : ADC_PTCR_TXTDIS_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTCR_Register use record + for ADC_PTCR_Register use record RXTEN at 0 range 0 .. 0; RXTDIS at 0 range 1 .. 1; Reserved_2_7 at 0 range 2 .. 7; @@ -1219,27 +1101,23 @@ package ATSAM3X8E.ADC is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- PTSR_Register -- - ------------------- - - subtype PTSR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTSR_TXTEN_Field is ATSAM3X8E.Bit; + subtype ADC_PTSR_RXTEN_Field is ATSAM3X8E.Bit; + subtype ADC_PTSR_TXTEN_Field is ATSAM3X8E.Bit; -- Transfer Status Register - type PTSR_Register is record + type ADC_PTSR_Register is record -- Read-only. Receiver Transfer Enable - RXTEN : PTSR_RXTEN_Field := 16#0#; + RXTEN : ADC_PTSR_RXTEN_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Transmitter Transfer Enable - TXTEN : PTSR_TXTEN_Field := 16#0#; + TXTEN : ADC_PTSR_TXTEN_Field; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTSR_Register use record + for ADC_PTSR_Register use record RXTEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; TXTEN at 0 range 8 .. 8; @@ -1253,90 +1131,175 @@ package ATSAM3X8E.ADC is -- Analog-to-Digital Converter type ADC_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased ADC_CR_Register; + pragma Volatile_Full_Access (CR); -- Mode Register - MR : MR_Register; + MR : aliased ADC_MR_Register; + pragma Volatile_Full_Access (MR); -- Channel Sequence Register 1 - SEQR1 : SEQR_Register; + SEQR1 : aliased ADC_SEQR1_Register; + pragma Volatile_Full_Access (SEQR1); -- Channel Sequence Register 2 - SEQR2 : SEQR_Register; + SEQR2 : aliased ADC_SEQR2_Register; + pragma Volatile_Full_Access (SEQR2); -- Channel Enable Register - CHER : CHER_Register; + CHER : aliased ADC_CHER_Register; + pragma Volatile_Full_Access (CHER); -- Channel Disable Register - CHDR : CHDR_Register; + CHDR : aliased ADC_CHDR_Register; + pragma Volatile_Full_Access (CHDR); -- Channel Status Register - CHSR : CHSR_Register; + CHSR : aliased ADC_CHSR_Register; + pragma Volatile_Full_Access (CHSR); -- Last Converted Data Register - LCDR : LCDR_Register; + LCDR : aliased ADC_LCDR_Register; + pragma Volatile_Full_Access (LCDR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased ADC_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased ADC_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased ADC_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Interrupt Status Register - ISR : ISR_Register; + ISR : aliased ADC_ISR_Register; + pragma Volatile_Full_Access (ISR); -- Overrun Status Register - OVER : OVER_Register; + OVER : aliased ADC_OVER_Register; + pragma Volatile_Full_Access (OVER); -- Extended Mode Register - EMR : EMR_Register; + EMR : aliased ADC_EMR_Register; + pragma Volatile_Full_Access (EMR); -- Compare Window Register - CWR : CWR_Register; + CWR : aliased ADC_CWR_Register; + pragma Volatile_Full_Access (CWR); -- Channel Gain Register - CGR : CGR_Register; + CGR : aliased ADC_CGR_Register; + pragma Volatile_Full_Access (CGR); -- Channel Offset Register - COR : COR_Register; + COR : aliased ADC_COR_Register; + pragma Volatile_Full_Access (COR); + -- Channel Data Register + CDR_0 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_0); + -- Channel Data Register + CDR_1 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_1); + -- Channel Data Register + CDR_2 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_2); + -- Channel Data Register + CDR_3 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_3); + -- Channel Data Register + CDR_4 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_4); + -- Channel Data Register + CDR_5 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_5); + -- Channel Data Register + CDR_6 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_6); + -- Channel Data Register + CDR_7 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_7); + -- Channel Data Register + CDR_8 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_8); + -- Channel Data Register + CDR_9 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_9); + -- Channel Data Register + CDR_10 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_10); + -- Channel Data Register + CDR_11 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_11); + -- Channel Data Register + CDR_12 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_12); + -- Channel Data Register + CDR_13 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_13); + -- Channel Data Register + CDR_14 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_14); -- Channel Data Register - CDR : CDR_Registers; + CDR_15 : aliased ADC_CDR_Register; + pragma Volatile_Full_Access (CDR_15); -- Analog Control Register - ACR : ACR_Register; + ACR : aliased ADC_ACR_Register; + pragma Volatile_Full_Access (ACR); -- Write Protect Mode Register - WPMR : WPMR_Register; + WPMR : aliased ADC_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- Write Protect Status Register - WPSR : WPSR_Register; + WPSR : aliased ADC_WPSR_Register; + pragma Volatile_Full_Access (WPSR); -- Receive Pointer Register - RPR : ATSAM3X8E.Word; + RPR : aliased ATSAM3X8E.UInt32; -- Receive Counter Register - RCR : RCR_Register; + RCR : aliased ADC_RCR_Register; + pragma Volatile_Full_Access (RCR); -- Receive Next Pointer Register - RNPR : ATSAM3X8E.Word; + RNPR : aliased ATSAM3X8E.UInt32; -- Receive Next Counter Register - RNCR : RNCR_Register; + RNCR : aliased ADC_RNCR_Register; + pragma Volatile_Full_Access (RNCR); -- Transfer Control Register - PTCR : PTCR_Register; + PTCR : aliased ADC_PTCR_Register; + pragma Volatile_Full_Access (PTCR); -- Transfer Status Register - PTSR : PTSR_Register; + PTSR : aliased ADC_PTSR_Register; + pragma Volatile_Full_Access (PTSR); end record with Volatile; for ADC_Peripheral use record - CR at 0 range 0 .. 31; - MR at 4 range 0 .. 31; - SEQR1 at 8 range 0 .. 31; - SEQR2 at 12 range 0 .. 31; - CHER at 16 range 0 .. 31; - CHDR at 20 range 0 .. 31; - CHSR at 24 range 0 .. 31; - LCDR at 32 range 0 .. 31; - IER at 36 range 0 .. 31; - IDR at 40 range 0 .. 31; - IMR at 44 range 0 .. 31; - ISR at 48 range 0 .. 31; - OVER at 60 range 0 .. 31; - EMR at 64 range 0 .. 31; - CWR at 68 range 0 .. 31; - CGR at 72 range 0 .. 31; - COR at 76 range 0 .. 31; - CDR at 80 range 0 .. 511; - ACR at 148 range 0 .. 31; - WPMR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; - RPR at 256 range 0 .. 31; - RCR at 260 range 0 .. 31; - RNPR at 272 range 0 .. 31; - RNCR at 276 range 0 .. 31; - PTCR at 288 range 0 .. 31; - PTSR at 292 range 0 .. 31; + CR at 16#0# range 0 .. 31; + MR at 16#4# range 0 .. 31; + SEQR1 at 16#8# range 0 .. 31; + SEQR2 at 16#C# range 0 .. 31; + CHER at 16#10# range 0 .. 31; + CHDR at 16#14# range 0 .. 31; + CHSR at 16#18# range 0 .. 31; + LCDR at 16#20# range 0 .. 31; + IER at 16#24# range 0 .. 31; + IDR at 16#28# range 0 .. 31; + IMR at 16#2C# range 0 .. 31; + ISR at 16#30# range 0 .. 31; + OVER at 16#3C# range 0 .. 31; + EMR at 16#40# range 0 .. 31; + CWR at 16#44# range 0 .. 31; + CGR at 16#48# range 0 .. 31; + COR at 16#4C# range 0 .. 31; + CDR_0 at 16#50# range 0 .. 31; + CDR_1 at 16#54# range 0 .. 31; + CDR_2 at 16#58# range 0 .. 31; + CDR_3 at 16#5C# range 0 .. 31; + CDR_4 at 16#60# range 0 .. 31; + CDR_5 at 16#64# range 0 .. 31; + CDR_6 at 16#68# range 0 .. 31; + CDR_7 at 16#6C# range 0 .. 31; + CDR_8 at 16#70# range 0 .. 31; + CDR_9 at 16#74# range 0 .. 31; + CDR_10 at 16#78# range 0 .. 31; + CDR_11 at 16#7C# range 0 .. 31; + CDR_12 at 16#80# range 0 .. 31; + CDR_13 at 16#84# range 0 .. 31; + CDR_14 at 16#88# range 0 .. 31; + CDR_15 at 16#8C# range 0 .. 31; + ACR at 16#94# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; + RPR at 16#100# range 0 .. 31; + RCR at 16#104# range 0 .. 31; + RNPR at 16#110# range 0 .. 31; + RNCR at 16#114# range 0 .. 31; + PTCR at 16#120# range 0 .. 31; + PTSR at 16#124# range 0 .. 31; end record; -- Analog-to-Digital Converter diff --git a/arduino-due/atsam3x8e/atsam3x8e-can.ads b/arduino-due/atsam3x8e/atsam3x8e-can.ads index 60f592f..88bd233 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-can.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-can.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,66 +14,61 @@ package ATSAM3X8E.CAN is -- Registers -- --------------- - ----------------- - -- MR_Register -- - ----------------- - - subtype MR_CANEN_Field is ATSAM3X8E.Bit; - subtype MR_LPM_Field is ATSAM3X8E.Bit; - subtype MR_ABM_Field is ATSAM3X8E.Bit; - subtype MR_OVL_Field is ATSAM3X8E.Bit; - subtype MR_TEOF_Field is ATSAM3X8E.Bit; - subtype MR_TTM_Field is ATSAM3X8E.Bit; - subtype MR_TIMFRZ_Field is ATSAM3X8E.Bit; - subtype MR_DRPT_Field is ATSAM3X8E.Bit; + subtype CAN0_MR_CANEN_Field is ATSAM3X8E.Bit; + subtype CAN0_MR_LPM_Field is ATSAM3X8E.Bit; + subtype CAN0_MR_ABM_Field is ATSAM3X8E.Bit; + subtype CAN0_MR_OVL_Field is ATSAM3X8E.Bit; + subtype CAN0_MR_TEOF_Field is ATSAM3X8E.Bit; + subtype CAN0_MR_TTM_Field is ATSAM3X8E.Bit; + subtype CAN0_MR_TIMFRZ_Field is ATSAM3X8E.Bit; + subtype CAN0_MR_DRPT_Field is ATSAM3X8E.Bit; -- Reception Synchronization Stage (not readable) - type RXSYNC_Field is - ( - -- Rx Signal with Double Synchro Stages (2 Positive Edges) + type MR_RXSYNC_Field is + (-- Rx Signal with Double Synchro Stages (2 Positive Edges) Double_Pp, - -- Rx Signal with Double Synchro Stages (One Positive Edge and One - -- Negative Edge) + -- Rx Signal with Double Synchro Stages (One Positive Edge and One Negative +-- Edge) Double_Pn, -- Rx Signal with Single Synchro Stage (Positive Edge) Single_P, -- Rx Signal with No Synchro Stage None) with Size => 3; - for RXSYNC_Field use + for MR_RXSYNC_Field use (Double_Pp => 0, Double_Pn => 1, Single_P => 2, None => 3); -- Mode Register - type MR_Register is record + type CAN0_MR_Register is record -- CAN Controller Enable - CANEN : MR_CANEN_Field := 16#0#; + CANEN : CAN0_MR_CANEN_Field := 16#0#; -- Disable/Enable Low Power Mode - LPM : MR_LPM_Field := 16#0#; + LPM : CAN0_MR_LPM_Field := 16#0#; -- Disable/Enable Autobaud/Listen mode - ABM : MR_ABM_Field := 16#0#; + ABM : CAN0_MR_ABM_Field := 16#0#; -- Disable/Enable Overload Frame - OVL : MR_OVL_Field := 16#0#; + OVL : CAN0_MR_OVL_Field := 16#0#; -- Timestamp messages at each end of Frame - TEOF : MR_TEOF_Field := 16#0#; + TEOF : CAN0_MR_TEOF_Field := 16#0#; -- Disable/Enable Time Triggered Mode - TTM : MR_TTM_Field := 16#0#; + TTM : CAN0_MR_TTM_Field := 16#0#; -- Enable Timer Freeze - TIMFRZ : MR_TIMFRZ_Field := 16#0#; + TIMFRZ : CAN0_MR_TIMFRZ_Field := 16#0#; -- Disable Repeat - DRPT : MR_DRPT_Field := 16#0#; + DRPT : CAN0_MR_DRPT_Field := 16#0#; -- unspecified - Reserved_8_23 : ATSAM3X8E.Short := 16#0#; + Reserved_8_23 : ATSAM3X8E.UInt16 := 16#0#; -- Reception Synchronization Stage (not readable) - RXSYNC : RXSYNC_Field := Double_Pp; + RXSYNC : MR_RXSYNC_Field := ATSAM3X8E.CAN.Double_Pp; -- unspecified Reserved_27_31 : ATSAM3X8E.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_Register use record + for CAN0_MR_Register use record CANEN at 0 range 0 .. 0; LPM at 0 range 1 .. 1; ABM at 0 range 2 .. 2; @@ -86,23 +82,15 @@ package ATSAM3X8E.CAN is Reserved_27_31 at 0 range 27 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - ------------ - -- IER.MB -- - ------------ + -- CAN0_IER_MB array element + subtype CAN0_IER_MB_Element is ATSAM3X8E.Bit; - -- IER_MB array element - subtype IER_MB_Element is ATSAM3X8E.Bit; - - -- IER_MB array - type IER_MB_Field_Array is array (0 .. 7) of IER_MB_Element + -- CAN0_IER_MB array + type CAN0_IER_MB_Field_Array is array (0 .. 7) of CAN0_IER_MB_Element with Component_Size => 1, Size => 8; - -- Type definition for IER_MB - type IER_MB_Field + -- Type definition for CAN0_IER_MB + type CAN0_IER_MB_Field (As_Array : Boolean := False) is record case As_Array is @@ -111,68 +99,68 @@ package ATSAM3X8E.CAN is Val : ATSAM3X8E.Byte; when True => -- MB as an array - Arr : IER_MB_Field_Array; + Arr : CAN0_IER_MB_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IER_MB_Field use record + for CAN0_IER_MB_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - subtype IER_ERRA_Field is ATSAM3X8E.Bit; - subtype IER_WARN_Field is ATSAM3X8E.Bit; - subtype IER_ERRP_Field is ATSAM3X8E.Bit; - subtype IER_BOFF_Field is ATSAM3X8E.Bit; - subtype IER_SLEEP_Field is ATSAM3X8E.Bit; - subtype IER_WAKEUP_Field is ATSAM3X8E.Bit; - subtype IER_TOVF_Field is ATSAM3X8E.Bit; - subtype IER_TSTP_Field is ATSAM3X8E.Bit; - subtype IER_CERR_Field is ATSAM3X8E.Bit; - subtype IER_SERR_Field is ATSAM3X8E.Bit; - subtype IER_AERR_Field is ATSAM3X8E.Bit; - subtype IER_FERR_Field is ATSAM3X8E.Bit; - subtype IER_BERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_ERRA_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_WARN_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_ERRP_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_BOFF_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_SLEEP_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_WAKEUP_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_TOVF_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_TSTP_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_CERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_SERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_AERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_FERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IER_BERR_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type CAN0_IER_Register is record -- Write-only. Mailbox 0 Interrupt Enable - MB : IER_MB_Field := (As_Array => False, Val => 16#0#); + MB : CAN0_IER_MB_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Error Active Mode Interrupt Enable - ERRA : IER_ERRA_Field := 16#0#; + ERRA : CAN0_IER_ERRA_Field := 16#0#; -- Write-only. Warning Limit Interrupt Enable - WARN : IER_WARN_Field := 16#0#; + WARN : CAN0_IER_WARN_Field := 16#0#; -- Write-only. Error Passive Mode Interrupt Enable - ERRP : IER_ERRP_Field := 16#0#; + ERRP : CAN0_IER_ERRP_Field := 16#0#; -- Write-only. Bus Off Mode Interrupt Enable - BOFF : IER_BOFF_Field := 16#0#; + BOFF : CAN0_IER_BOFF_Field := 16#0#; -- Write-only. Sleep Interrupt Enable - SLEEP : IER_SLEEP_Field := 16#0#; + SLEEP : CAN0_IER_SLEEP_Field := 16#0#; -- Write-only. Wakeup Interrupt Enable - WAKEUP : IER_WAKEUP_Field := 16#0#; + WAKEUP : CAN0_IER_WAKEUP_Field := 16#0#; -- Write-only. Timer Overflow Interrupt Enable - TOVF : IER_TOVF_Field := 16#0#; + TOVF : CAN0_IER_TOVF_Field := 16#0#; -- Write-only. TimeStamp Interrupt Enable - TSTP : IER_TSTP_Field := 16#0#; + TSTP : CAN0_IER_TSTP_Field := 16#0#; -- Write-only. CRC Error Interrupt Enable - CERR : IER_CERR_Field := 16#0#; + CERR : CAN0_IER_CERR_Field := 16#0#; -- Write-only. Stuffing Error Interrupt Enable - SERR : IER_SERR_Field := 16#0#; + SERR : CAN0_IER_SERR_Field := 16#0#; -- Write-only. Acknowledgment Error Interrupt Enable - AERR : IER_AERR_Field := 16#0#; + AERR : CAN0_IER_AERR_Field := 16#0#; -- Write-only. Form Error Interrupt Enable - FERR : IER_FERR_Field := 16#0#; + FERR : CAN0_IER_FERR_Field := 16#0#; -- Write-only. Bit Error Interrupt Enable - BERR : IER_BERR_Field := 16#0#; + BERR : CAN0_IER_BERR_Field := 16#0#; -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for CAN0_IER_Register use record MB at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; ERRA at 0 range 16 .. 16; @@ -191,23 +179,15 @@ package ATSAM3X8E.CAN is Reserved_29_31 at 0 range 29 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - ------------ - -- IDR.MB -- - ------------ + -- CAN0_IDR_MB array element + subtype CAN0_IDR_MB_Element is ATSAM3X8E.Bit; - -- IDR_MB array element - subtype IDR_MB_Element is ATSAM3X8E.Bit; - - -- IDR_MB array - type IDR_MB_Field_Array is array (0 .. 7) of IDR_MB_Element + -- CAN0_IDR_MB array + type CAN0_IDR_MB_Field_Array is array (0 .. 7) of CAN0_IDR_MB_Element with Component_Size => 1, Size => 8; - -- Type definition for IDR_MB - type IDR_MB_Field + -- Type definition for CAN0_IDR_MB + type CAN0_IDR_MB_Field (As_Array : Boolean := False) is record case As_Array is @@ -216,68 +196,68 @@ package ATSAM3X8E.CAN is Val : ATSAM3X8E.Byte; when True => -- MB as an array - Arr : IDR_MB_Field_Array; + Arr : CAN0_IDR_MB_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IDR_MB_Field use record + for CAN0_IDR_MB_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - subtype IDR_ERRA_Field is ATSAM3X8E.Bit; - subtype IDR_WARN_Field is ATSAM3X8E.Bit; - subtype IDR_ERRP_Field is ATSAM3X8E.Bit; - subtype IDR_BOFF_Field is ATSAM3X8E.Bit; - subtype IDR_SLEEP_Field is ATSAM3X8E.Bit; - subtype IDR_WAKEUP_Field is ATSAM3X8E.Bit; - subtype IDR_TOVF_Field is ATSAM3X8E.Bit; - subtype IDR_TSTP_Field is ATSAM3X8E.Bit; - subtype IDR_CERR_Field is ATSAM3X8E.Bit; - subtype IDR_SERR_Field is ATSAM3X8E.Bit; - subtype IDR_AERR_Field is ATSAM3X8E.Bit; - subtype IDR_FERR_Field is ATSAM3X8E.Bit; - subtype IDR_BERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_ERRA_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_WARN_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_ERRP_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_BOFF_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_SLEEP_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_WAKEUP_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_TOVF_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_TSTP_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_CERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_SERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_AERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_FERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IDR_BERR_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type CAN0_IDR_Register is record -- Write-only. Mailbox 0 Interrupt Disable - MB : IDR_MB_Field := (As_Array => False, Val => 16#0#); + MB : CAN0_IDR_MB_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Error Active Mode Interrupt Disable - ERRA : IDR_ERRA_Field := 16#0#; + ERRA : CAN0_IDR_ERRA_Field := 16#0#; -- Write-only. Warning Limit Interrupt Disable - WARN : IDR_WARN_Field := 16#0#; + WARN : CAN0_IDR_WARN_Field := 16#0#; -- Write-only. Error Passive Mode Interrupt Disable - ERRP : IDR_ERRP_Field := 16#0#; + ERRP : CAN0_IDR_ERRP_Field := 16#0#; -- Write-only. Bus Off Mode Interrupt Disable - BOFF : IDR_BOFF_Field := 16#0#; + BOFF : CAN0_IDR_BOFF_Field := 16#0#; -- Write-only. Sleep Interrupt Disable - SLEEP : IDR_SLEEP_Field := 16#0#; + SLEEP : CAN0_IDR_SLEEP_Field := 16#0#; -- Write-only. Wakeup Interrupt Disable - WAKEUP : IDR_WAKEUP_Field := 16#0#; + WAKEUP : CAN0_IDR_WAKEUP_Field := 16#0#; -- Write-only. Timer Overflow Interrupt - TOVF : IDR_TOVF_Field := 16#0#; + TOVF : CAN0_IDR_TOVF_Field := 16#0#; -- Write-only. TimeStamp Interrupt Disable - TSTP : IDR_TSTP_Field := 16#0#; + TSTP : CAN0_IDR_TSTP_Field := 16#0#; -- Write-only. CRC Error Interrupt Disable - CERR : IDR_CERR_Field := 16#0#; + CERR : CAN0_IDR_CERR_Field := 16#0#; -- Write-only. Stuffing Error Interrupt Disable - SERR : IDR_SERR_Field := 16#0#; + SERR : CAN0_IDR_SERR_Field := 16#0#; -- Write-only. Acknowledgment Error Interrupt Disable - AERR : IDR_AERR_Field := 16#0#; + AERR : CAN0_IDR_AERR_Field := 16#0#; -- Write-only. Form Error Interrupt Disable - FERR : IDR_FERR_Field := 16#0#; + FERR : CAN0_IDR_FERR_Field := 16#0#; -- Write-only. Bit Error Interrupt Disable - BERR : IDR_BERR_Field := 16#0#; + BERR : CAN0_IDR_BERR_Field := 16#0#; -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for CAN0_IDR_Register use record MB at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; ERRA at 0 range 16 .. 16; @@ -296,23 +276,15 @@ package ATSAM3X8E.CAN is Reserved_29_31 at 0 range 29 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - ------------ - -- IMR.MB -- - ------------ + -- CAN0_IMR_MB array element + subtype CAN0_IMR_MB_Element is ATSAM3X8E.Bit; - -- IMR_MB array element - subtype IMR_MB_Element is ATSAM3X8E.Bit; - - -- IMR_MB array - type IMR_MB_Field_Array is array (0 .. 7) of IMR_MB_Element + -- CAN0_IMR_MB array + type CAN0_IMR_MB_Field_Array is array (0 .. 7) of CAN0_IMR_MB_Element with Component_Size => 1, Size => 8; - -- Type definition for IMR_MB - type IMR_MB_Field + -- Type definition for CAN0_IMR_MB + type CAN0_IMR_MB_Field (As_Array : Boolean := False) is record case As_Array is @@ -321,68 +293,68 @@ package ATSAM3X8E.CAN is Val : ATSAM3X8E.Byte; when True => -- MB as an array - Arr : IMR_MB_Field_Array; + Arr : CAN0_IMR_MB_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IMR_MB_Field use record + for CAN0_IMR_MB_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - subtype IMR_ERRA_Field is ATSAM3X8E.Bit; - subtype IMR_WARN_Field is ATSAM3X8E.Bit; - subtype IMR_ERRP_Field is ATSAM3X8E.Bit; - subtype IMR_BOFF_Field is ATSAM3X8E.Bit; - subtype IMR_SLEEP_Field is ATSAM3X8E.Bit; - subtype IMR_WAKEUP_Field is ATSAM3X8E.Bit; - subtype IMR_TOVF_Field is ATSAM3X8E.Bit; - subtype IMR_TSTP_Field is ATSAM3X8E.Bit; - subtype IMR_CERR_Field is ATSAM3X8E.Bit; - subtype IMR_SERR_Field is ATSAM3X8E.Bit; - subtype IMR_AERR_Field is ATSAM3X8E.Bit; - subtype IMR_FERR_Field is ATSAM3X8E.Bit; - subtype IMR_BERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_ERRA_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_WARN_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_ERRP_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_BOFF_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_SLEEP_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_WAKEUP_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_TOVF_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_TSTP_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_CERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_SERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_AERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_FERR_Field is ATSAM3X8E.Bit; + subtype CAN0_IMR_BERR_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type CAN0_IMR_Register is record -- Read-only. Mailbox 0 Interrupt Mask - MB : IMR_MB_Field := (As_Array => False, Val => 16#0#); + MB : CAN0_IMR_MB_Field; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte; -- Read-only. Error Active Mode Interrupt Mask - ERRA : IMR_ERRA_Field := 16#0#; + ERRA : CAN0_IMR_ERRA_Field; -- Read-only. Warning Limit Interrupt Mask - WARN : IMR_WARN_Field := 16#0#; + WARN : CAN0_IMR_WARN_Field; -- Read-only. Error Passive Mode Interrupt Mask - ERRP : IMR_ERRP_Field := 16#0#; + ERRP : CAN0_IMR_ERRP_Field; -- Read-only. Bus Off Mode Interrupt Mask - BOFF : IMR_BOFF_Field := 16#0#; + BOFF : CAN0_IMR_BOFF_Field; -- Read-only. Sleep Interrupt Mask - SLEEP : IMR_SLEEP_Field := 16#0#; + SLEEP : CAN0_IMR_SLEEP_Field; -- Read-only. Wakeup Interrupt Mask - WAKEUP : IMR_WAKEUP_Field := 16#0#; + WAKEUP : CAN0_IMR_WAKEUP_Field; -- Read-only. Timer Overflow Interrupt Mask - TOVF : IMR_TOVF_Field := 16#0#; + TOVF : CAN0_IMR_TOVF_Field; -- Read-only. Timestamp Interrupt Mask - TSTP : IMR_TSTP_Field := 16#0#; + TSTP : CAN0_IMR_TSTP_Field; -- Read-only. CRC Error Interrupt Mask - CERR : IMR_CERR_Field := 16#0#; + CERR : CAN0_IMR_CERR_Field; -- Read-only. Stuffing Error Interrupt Mask - SERR : IMR_SERR_Field := 16#0#; + SERR : CAN0_IMR_SERR_Field; -- Read-only. Acknowledgment Error Interrupt Mask - AERR : IMR_AERR_Field := 16#0#; + AERR : CAN0_IMR_AERR_Field; -- Read-only. Form Error Interrupt Mask - FERR : IMR_FERR_Field := 16#0#; + FERR : CAN0_IMR_FERR_Field; -- Read-only. Bit Error Interrupt Mask - BERR : IMR_BERR_Field := 16#0#; + BERR : CAN0_IMR_BERR_Field; -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for CAN0_IMR_Register use record MB at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; ERRA at 0 range 16 .. 16; @@ -401,23 +373,15 @@ package ATSAM3X8E.CAN is Reserved_29_31 at 0 range 29 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - ----------- - -- SR.MB -- - ----------- + -- CAN0_SR_MB array element + subtype CAN0_SR_MB_Element is ATSAM3X8E.Bit; - -- SR_MB array element - subtype SR_MB_Element is ATSAM3X8E.Bit; - - -- SR_MB array - type SR_MB_Field_Array is array (0 .. 7) of SR_MB_Element + -- CAN0_SR_MB array + type CAN0_SR_MB_Field_Array is array (0 .. 7) of CAN0_SR_MB_Element with Component_Size => 1, Size => 8; - -- Type definition for SR_MB - type SR_MB_Field + -- Type definition for CAN0_SR_MB + type CAN0_SR_MB_Field (As_Array : Boolean := False) is record case As_Array is @@ -426,75 +390,75 @@ package ATSAM3X8E.CAN is Val : ATSAM3X8E.Byte; when True => -- MB as an array - Arr : SR_MB_Field_Array; + Arr : CAN0_SR_MB_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for SR_MB_Field use record + for CAN0_SR_MB_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - subtype SR_ERRA_Field is ATSAM3X8E.Bit; - subtype SR_WARN_Field is ATSAM3X8E.Bit; - subtype SR_ERRP_Field is ATSAM3X8E.Bit; - subtype SR_BOFF_Field is ATSAM3X8E.Bit; - subtype SR_SLEEP_Field is ATSAM3X8E.Bit; - subtype SR_WAKEUP_Field is ATSAM3X8E.Bit; - subtype SR_TOVF_Field is ATSAM3X8E.Bit; - subtype SR_TSTP_Field is ATSAM3X8E.Bit; - subtype SR_CERR_Field is ATSAM3X8E.Bit; - subtype SR_SERR_Field is ATSAM3X8E.Bit; - subtype SR_AERR_Field is ATSAM3X8E.Bit; - subtype SR_FERR_Field is ATSAM3X8E.Bit; - subtype SR_BERR_Field is ATSAM3X8E.Bit; - subtype SR_RBSY_Field is ATSAM3X8E.Bit; - subtype SR_TBSY_Field is ATSAM3X8E.Bit; - subtype SR_OVLSY_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_ERRA_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_WARN_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_ERRP_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_BOFF_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_SLEEP_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_WAKEUP_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_TOVF_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_TSTP_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_CERR_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_SERR_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_AERR_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_FERR_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_BERR_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_RBSY_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_TBSY_Field is ATSAM3X8E.Bit; + subtype CAN0_SR_OVLSY_Field is ATSAM3X8E.Bit; -- Status Register - type SR_Register is record + type CAN0_SR_Register is record -- Read-only. Mailbox 0 Event - MB : SR_MB_Field := (As_Array => False, Val => 16#0#); + MB : CAN0_SR_MB_Field; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte; -- Read-only. Error Active Mode - ERRA : SR_ERRA_Field := 16#0#; + ERRA : CAN0_SR_ERRA_Field; -- Read-only. Warning Limit - WARN : SR_WARN_Field := 16#0#; + WARN : CAN0_SR_WARN_Field; -- Read-only. Error Passive Mode - ERRP : SR_ERRP_Field := 16#0#; + ERRP : CAN0_SR_ERRP_Field; -- Read-only. Bus Off Mode - BOFF : SR_BOFF_Field := 16#0#; + BOFF : CAN0_SR_BOFF_Field; -- Read-only. CAN controller in Low power Mode - SLEEP : SR_SLEEP_Field := 16#0#; + SLEEP : CAN0_SR_SLEEP_Field; -- Read-only. CAN controller is not in Low power Mode - WAKEUP : SR_WAKEUP_Field := 16#0#; + WAKEUP : CAN0_SR_WAKEUP_Field; -- Read-only. Timer Overflow - TOVF : SR_TOVF_Field := 16#0#; + TOVF : CAN0_SR_TOVF_Field; -- Read-only. - TSTP : SR_TSTP_Field := 16#0#; + TSTP : CAN0_SR_TSTP_Field; -- Read-only. Mailbox CRC Error - CERR : SR_CERR_Field := 16#0#; + CERR : CAN0_SR_CERR_Field; -- Read-only. Mailbox Stuffing Error - SERR : SR_SERR_Field := 16#0#; + SERR : CAN0_SR_SERR_Field; -- Read-only. Acknowledgment Error - AERR : SR_AERR_Field := 16#0#; + AERR : CAN0_SR_AERR_Field; -- Read-only. Form Error - FERR : SR_FERR_Field := 16#0#; + FERR : CAN0_SR_FERR_Field; -- Read-only. Bit Error - BERR : SR_BERR_Field := 16#0#; + BERR : CAN0_SR_BERR_Field; -- Read-only. Receiver busy - RBSY : SR_RBSY_Field := 16#0#; + RBSY : CAN0_SR_RBSY_Field; -- Read-only. Transmitter busy - TBSY : SR_TBSY_Field := 16#0#; + TBSY : CAN0_SR_TBSY_Field; -- Read-only. Overload busy - OVLSY : SR_OVLSY_Field := 16#0#; + OVLSY : CAN0_SR_OVLSY_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for CAN0_SR_Register use record MB at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; ERRA at 0 range 16 .. 16; @@ -515,59 +479,54 @@ package ATSAM3X8E.CAN is OVLSY at 0 range 31 .. 31; end record; - ----------------- - -- BR_Register -- - ----------------- - - subtype BR_PHASE2_Field is ATSAM3X8E.UInt3; - subtype BR_PHASE1_Field is ATSAM3X8E.UInt3; - subtype BR_PROPAG_Field is ATSAM3X8E.UInt3; - subtype BR_SJW_Field is ATSAM3X8E.UInt2; - subtype BR_BRP_Field is ATSAM3X8E.UInt7; + subtype CAN0_BR_PHASE2_Field is ATSAM3X8E.UInt3; + subtype CAN0_BR_PHASE1_Field is ATSAM3X8E.UInt3; + subtype CAN0_BR_PROPAG_Field is ATSAM3X8E.UInt3; + subtype CAN0_BR_SJW_Field is ATSAM3X8E.UInt2; + subtype CAN0_BR_BRP_Field is ATSAM3X8E.UInt7; -- Sampling Mode - type SMP_Field is - ( - -- The incoming bit stream is sampled once at sample point. + type BR_SMP_Field is + (-- The incoming bit stream is sampled once at sample point. Once, - -- The incoming bit stream is sampled three times with a period of a MCK - -- clock period, centered on sample point. + -- The incoming bit stream is sampled three times with a period of a MCK clock +-- period, centered on sample point. Three) with Size => 1; - for SMP_Field use + for BR_SMP_Field use (Once => 0, Three => 1); -- Baudrate Register - type BR_Register is record + type CAN0_BR_Register is record -- Phase 2 segment - PHASE2 : BR_PHASE2_Field := 16#0#; + PHASE2 : CAN0_BR_PHASE2_Field := 16#0#; -- unspecified Reserved_3_3 : ATSAM3X8E.Bit := 16#0#; -- Phase 1 segment - PHASE1 : BR_PHASE1_Field := 16#0#; + PHASE1 : CAN0_BR_PHASE1_Field := 16#0#; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Programming time segment - PROPAG : BR_PROPAG_Field := 16#0#; + PROPAG : CAN0_BR_PROPAG_Field := 16#0#; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit := 16#0#; -- Re-synchronization jump width - SJW : BR_SJW_Field := 16#0#; + SJW : CAN0_BR_SJW_Field := 16#0#; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Baudrate Prescaler. - BRP : BR_BRP_Field := 16#0#; + BRP : CAN0_BR_BRP_Field := 16#0#; -- unspecified Reserved_23_23 : ATSAM3X8E.Bit := 16#0#; -- Sampling Mode - SMP : SMP_Field := Once; + SMP : BR_SMP_Field := ATSAM3X8E.CAN.Once; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for BR_Register use record + for CAN0_BR_Register use record PHASE2 at 0 range 0 .. 2; Reserved_3_3 at 0 range 3 .. 3; PHASE1 at 0 range 4 .. 6; @@ -582,90 +541,70 @@ package ATSAM3X8E.CAN is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- TIM_Register -- - ------------------ - - subtype TIM_TIMER_Field is ATSAM3X8E.Short; + subtype CAN0_TIM_TIMER_Field is ATSAM3X8E.UInt16; -- Timer Register - type TIM_Register is record + type CAN0_TIM_Register is record -- Read-only. Timer - TIMER : TIM_TIMER_Field := 16#0#; + TIMER : CAN0_TIM_TIMER_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TIM_Register use record + for CAN0_TIM_Register use record TIMER at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- TIMESTP_Register -- - ---------------------- - - subtype TIMESTP_MTIMESTAMP_Field is ATSAM3X8E.Short; + subtype CAN0_TIMESTP_MTIMESTAMP_Field is ATSAM3X8E.UInt16; -- Timestamp Register - type TIMESTP_Register is record + type CAN0_TIMESTP_Register is record -- Read-only. Timestamp - MTIMESTAMP : TIMESTP_MTIMESTAMP_Field := 16#0#; + MTIMESTAMP : CAN0_TIMESTP_MTIMESTAMP_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TIMESTP_Register use record + for CAN0_TIMESTP_Register use record MTIMESTAMP at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- ECR_Register -- - ------------------ - - subtype ECR_REC_Field is ATSAM3X8E.Byte; - subtype ECR_TEC_Field is ATSAM3X8E.Byte; + subtype CAN0_ECR_REC_Field is ATSAM3X8E.Byte; + subtype CAN0_ECR_TEC_Field is ATSAM3X8E.Byte; -- Error Counter Register - type ECR_Register is record + type CAN0_ECR_Register is record -- Read-only. Receive Error Counter - REC : ECR_REC_Field := 16#0#; + REC : CAN0_ECR_REC_Field; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte; -- Read-only. Transmit Error Counter - TEC : ECR_TEC_Field := 16#0#; + TEC : CAN0_ECR_TEC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECR_Register use record + for CAN0_ECR_Register use record REC at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; TEC at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- TCR_Register -- - ------------------ + -- CAN0_TCR_MB array element + subtype CAN0_TCR_MB_Element is ATSAM3X8E.Bit; - ------------ - -- TCR.MB -- - ------------ - - -- TCR_MB array element - subtype TCR_MB_Element is ATSAM3X8E.Bit; - - -- TCR_MB array - type TCR_MB_Field_Array is array (0 .. 7) of TCR_MB_Element + -- CAN0_TCR_MB array + type CAN0_TCR_MB_Field_Array is array (0 .. 7) of CAN0_TCR_MB_Element with Component_Size => 1, Size => 8; - -- Type definition for TCR_MB - type TCR_MB_Field + -- Type definition for CAN0_TCR_MB + type CAN0_TCR_MB_Field (As_Array : Boolean := False) is record case As_Array is @@ -674,52 +613,44 @@ package ATSAM3X8E.CAN is Val : ATSAM3X8E.Byte; when True => -- MB as an array - Arr : TCR_MB_Field_Array; + Arr : CAN0_TCR_MB_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for TCR_MB_Field use record + for CAN0_TCR_MB_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - subtype TCR_TIMRST_Field is ATSAM3X8E.Bit; + subtype CAN0_TCR_TIMRST_Field is ATSAM3X8E.Bit; -- Transfer Command Register - type TCR_Register is record + type CAN0_TCR_Register is record -- Write-only. Transfer Request for Mailbox 0 - MB : TCR_MB_Field := (As_Array => False, Val => 16#0#); + MB : CAN0_TCR_MB_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_30 : ATSAM3X8E.UInt23 := 16#0#; -- Write-only. Timer Reset - TIMRST : TCR_TIMRST_Field := 16#0#; + TIMRST : CAN0_TCR_TIMRST_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TCR_Register use record + for CAN0_TCR_Register use record MB at 0 range 0 .. 7; Reserved_8_30 at 0 range 8 .. 30; TIMRST at 0 range 31 .. 31; end record; - ------------------ - -- ACR_Register -- - ------------------ - - ------------ - -- ACR.MB -- - ------------ - - -- ACR_MB array element - subtype ACR_MB_Element is ATSAM3X8E.Bit; + -- CAN0_ACR_MB array element + subtype CAN0_ACR_MB_Element is ATSAM3X8E.Bit; - -- ACR_MB array - type ACR_MB_Field_Array is array (0 .. 7) of ACR_MB_Element + -- CAN0_ACR_MB array + type CAN0_ACR_MB_Field_Array is array (0 .. 7) of CAN0_ACR_MB_Element with Component_Size => 1, Size => 8; - -- Type definition for ACR_MB - type ACR_MB_Field + -- Type definition for CAN0_ACR_MB + type CAN0_ACR_MB_Field (As_Array : Boolean := False) is record case As_Array is @@ -728,113 +659,99 @@ package ATSAM3X8E.CAN is Val : ATSAM3X8E.Byte; when True => -- MB as an array - Arr : ACR_MB_Field_Array; + Arr : CAN0_ACR_MB_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for ACR_MB_Field use record + for CAN0_ACR_MB_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- Abort Command Register - type ACR_Register is record + type CAN0_ACR_Register is record -- Write-only. Abort Request for Mailbox 0 - MB : ACR_MB_Field := (As_Array => False, Val => 16#0#); + MB : CAN0_ACR_MB_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ACR_Register use record + for CAN0_ACR_Register use record MB at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype CAN0_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype CAN0_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- Write Protect Mode Register - type WPMR_Register is record + type CAN0_WPMR_Register is record -- Write Protection Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : CAN0_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- SPI Write Protection Key Password - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : CAN0_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for CAN0_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype WPSR_WPVSRC_Field is ATSAM3X8E.Byte; + subtype CAN0_WPSR_WPVS_Field is ATSAM3X8E.Bit; + subtype CAN0_WPSR_WPVSRC_Field is ATSAM3X8E.Byte; -- Write Protect Status Register - type WPSR_Register is record + type CAN0_WPSR_Register is record -- Read-only. Write Protection Violation Status - WPVS : WPSR_WPVS_Field := 16#0#; + WPVS : CAN0_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protection Violation Source - WPVSRC : WPSR_WPVSRC_Field := 16#0#; + WPVSRC : CAN0_WPSR_WPVSRC_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for CAN0_WPSR_Register use record WPVS at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPVSRC at 0 range 8 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- MMR_Register -- - ------------------ - - subtype MMR0_MTIMEMARK_Field is ATSAM3X8E.Short; - subtype MMR0_PRIOR_Field is ATSAM3X8E.UInt4; + subtype MMR_MTIMEMARK_Field is ATSAM3X8E.UInt16; + subtype MMR_PRIOR_Field is ATSAM3X8E.UInt4; -- Mailbox Object Type - type MOT_Field is - ( - -- Mailbox is disabled. This prevents receiving or transmitting any - -- messages with this mailbox. + type MMR0_MOT_Field is + (-- Mailbox is disabled. This prevents receiving or transmitting any messages +-- with this mailbox. Mb_Disabled, - -- Reception Mailbox. Mailbox is configured for reception. If a message - -- is received while the mailbox data register is full, it is discarded. + -- Reception Mailbox. Mailbox is configured for reception. If a message is +-- received while the mailbox data register is full, it is discarded. Mb_Rx, - -- Reception mailbox with overwrite. Mailbox is configured for - -- reception. If a message is received while the mailbox is full, it - -- overwrites the previous message. + -- Reception mailbox with overwrite. Mailbox is configured for reception. If a +-- message is received while the mailbox is full, it overwrites the previous +-- message. Mb_Rx_Overwrite, -- Transmit mailbox. Mailbox is configured for transmission. Mb_Tx, -- Consumer Mailbox. Mailbox is configured in reception but behaves as a - -- Transmit Mailbox, i.e., it sends a remote frame and waits for an - -- answer. +-- Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. Mb_Consumer, - -- Producer Mailbox. Mailbox is configured in transmission but also - -- behaves like a reception mailbox, i.e., it waits to receive a Remote - -- Frame before sending its contents. + -- Producer Mailbox. Mailbox is configured in transmission but also behaves +-- like a reception mailbox, i.e., it waits to receive a Remote Frame before +-- sending its contents. Mb_Producer) with Size => 3; - for MOT_Field use + for MMR0_MOT_Field use (Mb_Disabled => 0, Mb_Rx => 1, Mb_Rx_Overwrite => 2, @@ -845,17 +762,17 @@ package ATSAM3X8E.CAN is -- Mailbox Mode Register (MB = 0) type MMR_Register is record -- Mailbox Timemark - MTIMEMARK : MMR0_MTIMEMARK_Field := 16#0#; + MTIMEMARK : MMR_MTIMEMARK_Field := 16#0#; -- Mailbox Priority - PRIOR : MMR0_PRIOR_Field := 16#0#; + PRIOR : MMR_PRIOR_Field := 16#0#; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4 := 16#0#; -- Mailbox Object Type - MOT : MOT_Field := Mb_Disabled; + MOT : MMR0_MOT_Field := ATSAM3X8E.CAN.Mb_Disabled; -- unspecified Reserved_27_31 : ATSAM3X8E.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MMR_Register use record MTIMEMARK at 0 range 0 .. 15; @@ -865,26 +782,22 @@ package ATSAM3X8E.CAN is Reserved_27_31 at 0 range 27 .. 31; end record; - ------------------ - -- MAM_Register -- - ------------------ - - subtype MAM0_MIDvB_Field is ATSAM3X8E.UInt18; - subtype MAM0_MIDvA_Field is ATSAM3X8E.UInt11; - subtype MAM0_MIDE_Field is ATSAM3X8E.Bit; + subtype MAM_MIDvB_Field is ATSAM3X8E.UInt18; + subtype MAM_MIDvA_Field is ATSAM3X8E.UInt11; + subtype MAM_MIDE_Field is ATSAM3X8E.Bit; -- Mailbox Acceptance Mask Register (MB = 0) type MAM_Register is record -- Complementary bits for identifier in extended frame mode - MIDvB : MAM0_MIDvB_Field := 16#0#; + MIDvB : MAM_MIDvB_Field := 16#0#; -- Identifier for standard frame mode - MIDvA : MAM0_MIDvA_Field := 16#0#; + MIDvA : MAM_MIDvA_Field := 16#0#; -- Identifier Version - MIDE : MAM0_MIDE_Field := 16#0#; + MIDE : MAM_MIDE_Field := 16#0#; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MAM_Register use record MIDvB at 0 range 0 .. 17; @@ -893,26 +806,22 @@ package ATSAM3X8E.CAN is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- MID_Register -- - ------------------ - - subtype MID0_MIDvB_Field is ATSAM3X8E.UInt18; - subtype MID0_MIDvA_Field is ATSAM3X8E.UInt11; - subtype MID0_MIDE_Field is ATSAM3X8E.Bit; + subtype MID_MIDvB_Field is ATSAM3X8E.UInt18; + subtype MID_MIDvA_Field is ATSAM3X8E.UInt11; + subtype MID_MIDE_Field is ATSAM3X8E.Bit; -- Mailbox ID Register (MB = 0) type MID_Register is record -- Complementary bits for identifier in extended frame mode - MIDvB : MID0_MIDvB_Field := 16#0#; + MIDvB : MID_MIDvB_Field := 16#0#; -- Identifier for standard frame mode - MIDvA : MID0_MIDvA_Field := 16#0#; + MIDvA : MID_MIDvA_Field := 16#0#; -- Identifier Version - MIDE : MID0_MIDE_Field := 16#0#; + MIDE : MID_MIDE_Field := 16#0#; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MID_Register use record MIDvB at 0 range 0 .. 17; @@ -921,57 +830,49 @@ package ATSAM3X8E.CAN is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- MFID_Register -- - ------------------- - - subtype MFID0_MFID_Field is ATSAM3X8E.UInt29; + subtype MFID_MFID_Field is ATSAM3X8E.UInt29; -- Mailbox Family ID Register (MB = 0) type MFID_Register is record -- Read-only. Family ID - MFID : MFID0_MFID_Field := 16#0#; + MFID : MFID_MFID_Field; -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MFID_Register use record MFID at 0 range 0 .. 28; Reserved_29_31 at 0 range 29 .. 31; end record; - ------------------ - -- MSR_Register -- - ------------------ - - subtype MSR0_MTIMESTAMP_Field is ATSAM3X8E.Short; - subtype MSR0_MDLC_Field is ATSAM3X8E.UInt4; - subtype MSR0_MRTR_Field is ATSAM3X8E.Bit; - subtype MSR0_MABT_Field is ATSAM3X8E.Bit; - subtype MSR0_MRDY_Field is ATSAM3X8E.Bit; - subtype MSR0_MMI_Field is ATSAM3X8E.Bit; + subtype MSR_MTIMESTAMP_Field is ATSAM3X8E.UInt16; + subtype MSR_MDLC_Field is ATSAM3X8E.UInt4; + subtype MSR_MRTR_Field is ATSAM3X8E.Bit; + subtype MSR_MABT_Field is ATSAM3X8E.Bit; + subtype MSR_MRDY_Field is ATSAM3X8E.Bit; + subtype MSR_MMI_Field is ATSAM3X8E.Bit; -- Mailbox Status Register (MB = 0) type MSR_Register is record -- Read-only. Timer value - MTIMESTAMP : MSR0_MTIMESTAMP_Field := 16#0#; + MTIMESTAMP : MSR_MTIMESTAMP_Field; -- Read-only. Mailbox Data Length Code - MDLC : MSR0_MDLC_Field := 16#0#; + MDLC : MSR_MDLC_Field; -- Read-only. Mailbox Remote Transmission Request - MRTR : MSR0_MRTR_Field := 16#0#; + MRTR : MSR_MRTR_Field; -- unspecified Reserved_21_21 : ATSAM3X8E.Bit; -- Read-only. Mailbox Message Abort - MABT : MSR0_MABT_Field := 16#0#; + MABT : MSR_MABT_Field; -- Read-only. Mailbox Ready - MRDY : MSR0_MRDY_Field := 16#0#; + MRDY : MSR_MRDY_Field; -- Read-only. Mailbox Message Ignored - MMI : MSR0_MMI_Field := 16#0#; + MMI : MSR_MMI_Field; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MSR_Register use record MTIMESTAMP at 0 range 0 .. 15; @@ -984,33 +885,29 @@ package ATSAM3X8E.CAN is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- MCR_Register -- - ------------------ - - subtype MCR0_MDLC_Field is ATSAM3X8E.UInt4; - subtype MCR0_MRTR_Field is ATSAM3X8E.Bit; - subtype MCR0_MACR_Field is ATSAM3X8E.Bit; - subtype MCR0_MTCR_Field is ATSAM3X8E.Bit; + subtype MCR_MDLC_Field is ATSAM3X8E.UInt4; + subtype MCR_MRTR_Field is ATSAM3X8E.Bit; + subtype MCR_MACR_Field is ATSAM3X8E.Bit; + subtype MCR_MTCR_Field is ATSAM3X8E.Bit; -- Mailbox Control Register (MB = 0) type MCR_Register is record -- unspecified - Reserved_0_15 : ATSAM3X8E.Short := 16#0#; + Reserved_0_15 : ATSAM3X8E.UInt16 := 16#0#; -- Write-only. Mailbox Data Length Code - MDLC : MCR0_MDLC_Field := 16#0#; + MDLC : MCR_MDLC_Field := 16#0#; -- Write-only. Mailbox Remote Transmission Request - MRTR : MCR0_MRTR_Field := 16#0#; + MRTR : MCR_MRTR_Field := 16#0#; -- unspecified Reserved_21_21 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Abort Request for Mailbox x - MACR : MCR0_MACR_Field := 16#0#; + MACR : MCR_MACR_Field := 16#0#; -- Write-only. Mailbox Transfer Command - MTCR : MCR0_MTCR_Field := 16#0#; + MTCR : MCR_MTCR_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MCR_Register use record Reserved_0_15 at 0 range 0 .. 15; @@ -1029,240 +926,301 @@ package ATSAM3X8E.CAN is -- Controller Area Network 0 type CAN_Peripheral is record -- Mode Register - MR : MR_Register; + MR : aliased CAN0_MR_Register; + pragma Volatile_Full_Access (MR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased CAN0_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased CAN0_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased CAN0_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Status Register - SR : SR_Register; + SR : aliased CAN0_SR_Register; + pragma Volatile_Full_Access (SR); -- Baudrate Register - BR : BR_Register; + BR : aliased CAN0_BR_Register; + pragma Volatile_Full_Access (BR); -- Timer Register - TIM : TIM_Register; + TIM : aliased CAN0_TIM_Register; + pragma Volatile_Full_Access (TIM); -- Timestamp Register - TIMESTP : TIMESTP_Register; + TIMESTP : aliased CAN0_TIMESTP_Register; + pragma Volatile_Full_Access (TIMESTP); -- Error Counter Register - ECR : ECR_Register; + ECR : aliased CAN0_ECR_Register; + pragma Volatile_Full_Access (ECR); -- Transfer Command Register - TCR : TCR_Register; + TCR : aliased CAN0_TCR_Register; + pragma Volatile_Full_Access (TCR); -- Abort Command Register - ACR : ACR_Register; + ACR : aliased CAN0_ACR_Register; + pragma Volatile_Full_Access (ACR); -- Write Protect Mode Register - WPMR : WPMR_Register; + WPMR : aliased CAN0_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- Write Protect Status Register - WPSR : WPSR_Register; + WPSR : aliased CAN0_WPSR_Register; + pragma Volatile_Full_Access (WPSR); -- Mailbox Mode Register (MB = 0) - MMR0 : MMR_Register; + MMR0 : aliased MMR_Register; + pragma Volatile_Full_Access (MMR0); -- Mailbox Acceptance Mask Register (MB = 0) - MAM0 : MAM_Register; + MAM0 : aliased MAM_Register; + pragma Volatile_Full_Access (MAM0); -- Mailbox ID Register (MB = 0) - MID0 : MID_Register; + MID0 : aliased MID_Register; + pragma Volatile_Full_Access (MID0); -- Mailbox Family ID Register (MB = 0) - MFID0 : MFID_Register; + MFID0 : aliased MFID_Register; + pragma Volatile_Full_Access (MFID0); -- Mailbox Status Register (MB = 0) - MSR0 : MSR_Register; + MSR0 : aliased MSR_Register; + pragma Volatile_Full_Access (MSR0); -- Mailbox Data Low Register (MB = 0) - MDL0 : ATSAM3X8E.Word; + MDL0 : aliased ATSAM3X8E.UInt32; -- Mailbox Data High Register (MB = 0) - MDH0 : ATSAM3X8E.Word; + MDH0 : aliased ATSAM3X8E.UInt32; -- Mailbox Control Register (MB = 0) - MCR0 : MCR_Register; + MCR0 : aliased MCR_Register; + pragma Volatile_Full_Access (MCR0); -- Mailbox Mode Register (MB = 1) - MMR1 : MMR_Register; + MMR1 : aliased MMR_Register; + pragma Volatile_Full_Access (MMR1); -- Mailbox Acceptance Mask Register (MB = 1) - MAM1 : MAM_Register; + MAM1 : aliased MAM_Register; + pragma Volatile_Full_Access (MAM1); -- Mailbox ID Register (MB = 1) - MID1 : MID_Register; + MID1 : aliased MID_Register; + pragma Volatile_Full_Access (MID1); -- Mailbox Family ID Register (MB = 1) - MFID1 : MFID_Register; + MFID1 : aliased MFID_Register; + pragma Volatile_Full_Access (MFID1); -- Mailbox Status Register (MB = 1) - MSR1 : MSR_Register; + MSR1 : aliased MSR_Register; + pragma Volatile_Full_Access (MSR1); -- Mailbox Data Low Register (MB = 1) - MDL1 : ATSAM3X8E.Word; + MDL1 : aliased ATSAM3X8E.UInt32; -- Mailbox Data High Register (MB = 1) - MDH1 : ATSAM3X8E.Word; + MDH1 : aliased ATSAM3X8E.UInt32; -- Mailbox Control Register (MB = 1) - MCR1 : MCR_Register; + MCR1 : aliased MCR_Register; + pragma Volatile_Full_Access (MCR1); -- Mailbox Mode Register (MB = 2) - MMR2 : MMR_Register; + MMR2 : aliased MMR_Register; + pragma Volatile_Full_Access (MMR2); -- Mailbox Acceptance Mask Register (MB = 2) - MAM2 : MAM_Register; + MAM2 : aliased MAM_Register; + pragma Volatile_Full_Access (MAM2); -- Mailbox ID Register (MB = 2) - MID2 : MID_Register; + MID2 : aliased MID_Register; + pragma Volatile_Full_Access (MID2); -- Mailbox Family ID Register (MB = 2) - MFID2 : MFID_Register; + MFID2 : aliased MFID_Register; + pragma Volatile_Full_Access (MFID2); -- Mailbox Status Register (MB = 2) - MSR2 : MSR_Register; + MSR2 : aliased MSR_Register; + pragma Volatile_Full_Access (MSR2); -- Mailbox Data Low Register (MB = 2) - MDL2 : ATSAM3X8E.Word; + MDL2 : aliased ATSAM3X8E.UInt32; -- Mailbox Data High Register (MB = 2) - MDH2 : ATSAM3X8E.Word; + MDH2 : aliased ATSAM3X8E.UInt32; -- Mailbox Control Register (MB = 2) - MCR2 : MCR_Register; + MCR2 : aliased MCR_Register; + pragma Volatile_Full_Access (MCR2); -- Mailbox Mode Register (MB = 3) - MMR3 : MMR_Register; + MMR3 : aliased MMR_Register; + pragma Volatile_Full_Access (MMR3); -- Mailbox Acceptance Mask Register (MB = 3) - MAM3 : MAM_Register; + MAM3 : aliased MAM_Register; + pragma Volatile_Full_Access (MAM3); -- Mailbox ID Register (MB = 3) - MID3 : MID_Register; + MID3 : aliased MID_Register; + pragma Volatile_Full_Access (MID3); -- Mailbox Family ID Register (MB = 3) - MFID3 : MFID_Register; + MFID3 : aliased MFID_Register; + pragma Volatile_Full_Access (MFID3); -- Mailbox Status Register (MB = 3) - MSR3 : MSR_Register; + MSR3 : aliased MSR_Register; + pragma Volatile_Full_Access (MSR3); -- Mailbox Data Low Register (MB = 3) - MDL3 : ATSAM3X8E.Word; + MDL3 : aliased ATSAM3X8E.UInt32; -- Mailbox Data High Register (MB = 3) - MDH3 : ATSAM3X8E.Word; + MDH3 : aliased ATSAM3X8E.UInt32; -- Mailbox Control Register (MB = 3) - MCR3 : MCR_Register; + MCR3 : aliased MCR_Register; + pragma Volatile_Full_Access (MCR3); -- Mailbox Mode Register (MB = 4) - MMR4 : MMR_Register; + MMR4 : aliased MMR_Register; + pragma Volatile_Full_Access (MMR4); -- Mailbox Acceptance Mask Register (MB = 4) - MAM4 : MAM_Register; + MAM4 : aliased MAM_Register; + pragma Volatile_Full_Access (MAM4); -- Mailbox ID Register (MB = 4) - MID4 : MID_Register; + MID4 : aliased MID_Register; + pragma Volatile_Full_Access (MID4); -- Mailbox Family ID Register (MB = 4) - MFID4 : MFID_Register; + MFID4 : aliased MFID_Register; + pragma Volatile_Full_Access (MFID4); -- Mailbox Status Register (MB = 4) - MSR4 : MSR_Register; + MSR4 : aliased MSR_Register; + pragma Volatile_Full_Access (MSR4); -- Mailbox Data Low Register (MB = 4) - MDL4 : ATSAM3X8E.Word; + MDL4 : aliased ATSAM3X8E.UInt32; -- Mailbox Data High Register (MB = 4) - MDH4 : ATSAM3X8E.Word; + MDH4 : aliased ATSAM3X8E.UInt32; -- Mailbox Control Register (MB = 4) - MCR4 : MCR_Register; + MCR4 : aliased MCR_Register; + pragma Volatile_Full_Access (MCR4); -- Mailbox Mode Register (MB = 5) - MMR5 : MMR_Register; + MMR5 : aliased MMR_Register; + pragma Volatile_Full_Access (MMR5); -- Mailbox Acceptance Mask Register (MB = 5) - MAM5 : MAM_Register; + MAM5 : aliased MAM_Register; + pragma Volatile_Full_Access (MAM5); -- Mailbox ID Register (MB = 5) - MID5 : MID_Register; + MID5 : aliased MID_Register; + pragma Volatile_Full_Access (MID5); -- Mailbox Family ID Register (MB = 5) - MFID5 : MFID_Register; + MFID5 : aliased MFID_Register; + pragma Volatile_Full_Access (MFID5); -- Mailbox Status Register (MB = 5) - MSR5 : MSR_Register; + MSR5 : aliased MSR_Register; + pragma Volatile_Full_Access (MSR5); -- Mailbox Data Low Register (MB = 5) - MDL5 : ATSAM3X8E.Word; + MDL5 : aliased ATSAM3X8E.UInt32; -- Mailbox Data High Register (MB = 5) - MDH5 : ATSAM3X8E.Word; + MDH5 : aliased ATSAM3X8E.UInt32; -- Mailbox Control Register (MB = 5) - MCR5 : MCR_Register; + MCR5 : aliased MCR_Register; + pragma Volatile_Full_Access (MCR5); -- Mailbox Mode Register (MB = 6) - MMR6 : MMR_Register; + MMR6 : aliased MMR_Register; + pragma Volatile_Full_Access (MMR6); -- Mailbox Acceptance Mask Register (MB = 6) - MAM6 : MAM_Register; + MAM6 : aliased MAM_Register; + pragma Volatile_Full_Access (MAM6); -- Mailbox ID Register (MB = 6) - MID6 : MID_Register; + MID6 : aliased MID_Register; + pragma Volatile_Full_Access (MID6); -- Mailbox Family ID Register (MB = 6) - MFID6 : MFID_Register; + MFID6 : aliased MFID_Register; + pragma Volatile_Full_Access (MFID6); -- Mailbox Status Register (MB = 6) - MSR6 : MSR_Register; + MSR6 : aliased MSR_Register; + pragma Volatile_Full_Access (MSR6); -- Mailbox Data Low Register (MB = 6) - MDL6 : ATSAM3X8E.Word; + MDL6 : aliased ATSAM3X8E.UInt32; -- Mailbox Data High Register (MB = 6) - MDH6 : ATSAM3X8E.Word; + MDH6 : aliased ATSAM3X8E.UInt32; -- Mailbox Control Register (MB = 6) - MCR6 : MCR_Register; + MCR6 : aliased MCR_Register; + pragma Volatile_Full_Access (MCR6); -- Mailbox Mode Register (MB = 7) - MMR7 : MMR_Register; + MMR7 : aliased MMR_Register; + pragma Volatile_Full_Access (MMR7); -- Mailbox Acceptance Mask Register (MB = 7) - MAM7 : MAM_Register; + MAM7 : aliased MAM_Register; + pragma Volatile_Full_Access (MAM7); -- Mailbox ID Register (MB = 7) - MID7 : MID_Register; + MID7 : aliased MID_Register; + pragma Volatile_Full_Access (MID7); -- Mailbox Family ID Register (MB = 7) - MFID7 : MFID_Register; + MFID7 : aliased MFID_Register; + pragma Volatile_Full_Access (MFID7); -- Mailbox Status Register (MB = 7) - MSR7 : MSR_Register; + MSR7 : aliased MSR_Register; + pragma Volatile_Full_Access (MSR7); -- Mailbox Data Low Register (MB = 7) - MDL7 : ATSAM3X8E.Word; + MDL7 : aliased ATSAM3X8E.UInt32; -- Mailbox Data High Register (MB = 7) - MDH7 : ATSAM3X8E.Word; + MDH7 : aliased ATSAM3X8E.UInt32; -- Mailbox Control Register (MB = 7) - MCR7 : MCR_Register; + MCR7 : aliased MCR_Register; + pragma Volatile_Full_Access (MCR7); end record with Volatile; for CAN_Peripheral use record - MR at 0 range 0 .. 31; - IER at 4 range 0 .. 31; - IDR at 8 range 0 .. 31; - IMR at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - BR at 20 range 0 .. 31; - TIM at 24 range 0 .. 31; - TIMESTP at 28 range 0 .. 31; - ECR at 32 range 0 .. 31; - TCR at 36 range 0 .. 31; - ACR at 40 range 0 .. 31; - WPMR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; - MMR0 at 512 range 0 .. 31; - MAM0 at 516 range 0 .. 31; - MID0 at 520 range 0 .. 31; - MFID0 at 524 range 0 .. 31; - MSR0 at 528 range 0 .. 31; - MDL0 at 532 range 0 .. 31; - MDH0 at 536 range 0 .. 31; - MCR0 at 540 range 0 .. 31; - MMR1 at 544 range 0 .. 31; - MAM1 at 548 range 0 .. 31; - MID1 at 552 range 0 .. 31; - MFID1 at 556 range 0 .. 31; - MSR1 at 560 range 0 .. 31; - MDL1 at 564 range 0 .. 31; - MDH1 at 568 range 0 .. 31; - MCR1 at 572 range 0 .. 31; - MMR2 at 576 range 0 .. 31; - MAM2 at 580 range 0 .. 31; - MID2 at 584 range 0 .. 31; - MFID2 at 588 range 0 .. 31; - MSR2 at 592 range 0 .. 31; - MDL2 at 596 range 0 .. 31; - MDH2 at 600 range 0 .. 31; - MCR2 at 604 range 0 .. 31; - MMR3 at 608 range 0 .. 31; - MAM3 at 612 range 0 .. 31; - MID3 at 616 range 0 .. 31; - MFID3 at 620 range 0 .. 31; - MSR3 at 624 range 0 .. 31; - MDL3 at 628 range 0 .. 31; - MDH3 at 632 range 0 .. 31; - MCR3 at 636 range 0 .. 31; - MMR4 at 640 range 0 .. 31; - MAM4 at 644 range 0 .. 31; - MID4 at 648 range 0 .. 31; - MFID4 at 652 range 0 .. 31; - MSR4 at 656 range 0 .. 31; - MDL4 at 660 range 0 .. 31; - MDH4 at 664 range 0 .. 31; - MCR4 at 668 range 0 .. 31; - MMR5 at 672 range 0 .. 31; - MAM5 at 676 range 0 .. 31; - MID5 at 680 range 0 .. 31; - MFID5 at 684 range 0 .. 31; - MSR5 at 688 range 0 .. 31; - MDL5 at 692 range 0 .. 31; - MDH5 at 696 range 0 .. 31; - MCR5 at 700 range 0 .. 31; - MMR6 at 704 range 0 .. 31; - MAM6 at 708 range 0 .. 31; - MID6 at 712 range 0 .. 31; - MFID6 at 716 range 0 .. 31; - MSR6 at 720 range 0 .. 31; - MDL6 at 724 range 0 .. 31; - MDH6 at 728 range 0 .. 31; - MCR6 at 732 range 0 .. 31; - MMR7 at 736 range 0 .. 31; - MAM7 at 740 range 0 .. 31; - MID7 at 744 range 0 .. 31; - MFID7 at 748 range 0 .. 31; - MSR7 at 752 range 0 .. 31; - MDL7 at 756 range 0 .. 31; - MDH7 at 760 range 0 .. 31; - MCR7 at 764 range 0 .. 31; + MR at 16#0# range 0 .. 31; + IER at 16#4# range 0 .. 31; + IDR at 16#8# range 0 .. 31; + IMR at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + BR at 16#14# range 0 .. 31; + TIM at 16#18# range 0 .. 31; + TIMESTP at 16#1C# range 0 .. 31; + ECR at 16#20# range 0 .. 31; + TCR at 16#24# range 0 .. 31; + ACR at 16#28# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; + MMR0 at 16#200# range 0 .. 31; + MAM0 at 16#204# range 0 .. 31; + MID0 at 16#208# range 0 .. 31; + MFID0 at 16#20C# range 0 .. 31; + MSR0 at 16#210# range 0 .. 31; + MDL0 at 16#214# range 0 .. 31; + MDH0 at 16#218# range 0 .. 31; + MCR0 at 16#21C# range 0 .. 31; + MMR1 at 16#220# range 0 .. 31; + MAM1 at 16#224# range 0 .. 31; + MID1 at 16#228# range 0 .. 31; + MFID1 at 16#22C# range 0 .. 31; + MSR1 at 16#230# range 0 .. 31; + MDL1 at 16#234# range 0 .. 31; + MDH1 at 16#238# range 0 .. 31; + MCR1 at 16#23C# range 0 .. 31; + MMR2 at 16#240# range 0 .. 31; + MAM2 at 16#244# range 0 .. 31; + MID2 at 16#248# range 0 .. 31; + MFID2 at 16#24C# range 0 .. 31; + MSR2 at 16#250# range 0 .. 31; + MDL2 at 16#254# range 0 .. 31; + MDH2 at 16#258# range 0 .. 31; + MCR2 at 16#25C# range 0 .. 31; + MMR3 at 16#260# range 0 .. 31; + MAM3 at 16#264# range 0 .. 31; + MID3 at 16#268# range 0 .. 31; + MFID3 at 16#26C# range 0 .. 31; + MSR3 at 16#270# range 0 .. 31; + MDL3 at 16#274# range 0 .. 31; + MDH3 at 16#278# range 0 .. 31; + MCR3 at 16#27C# range 0 .. 31; + MMR4 at 16#280# range 0 .. 31; + MAM4 at 16#284# range 0 .. 31; + MID4 at 16#288# range 0 .. 31; + MFID4 at 16#28C# range 0 .. 31; + MSR4 at 16#290# range 0 .. 31; + MDL4 at 16#294# range 0 .. 31; + MDH4 at 16#298# range 0 .. 31; + MCR4 at 16#29C# range 0 .. 31; + MMR5 at 16#2A0# range 0 .. 31; + MAM5 at 16#2A4# range 0 .. 31; + MID5 at 16#2A8# range 0 .. 31; + MFID5 at 16#2AC# range 0 .. 31; + MSR5 at 16#2B0# range 0 .. 31; + MDL5 at 16#2B4# range 0 .. 31; + MDH5 at 16#2B8# range 0 .. 31; + MCR5 at 16#2BC# range 0 .. 31; + MMR6 at 16#2C0# range 0 .. 31; + MAM6 at 16#2C4# range 0 .. 31; + MID6 at 16#2C8# range 0 .. 31; + MFID6 at 16#2CC# range 0 .. 31; + MSR6 at 16#2D0# range 0 .. 31; + MDL6 at 16#2D4# range 0 .. 31; + MDH6 at 16#2D8# range 0 .. 31; + MCR6 at 16#2DC# range 0 .. 31; + MMR7 at 16#2E0# range 0 .. 31; + MAM7 at 16#2E4# range 0 .. 31; + MID7 at 16#2E8# range 0 .. 31; + MFID7 at 16#2EC# range 0 .. 31; + MSR7 at 16#2F0# range 0 .. 31; + MDL7 at 16#2F4# range 0 .. 31; + MDH7 at 16#2F8# range 0 .. 31; + MCR7 at 16#2FC# range 0 .. 31; end record; -- Controller Area Network 0 diff --git a/arduino-due/atsam3x8e/atsam3x8e-chipid.ads b/arduino-due/atsam3x8e/atsam3x8e-chipid.ads index 136da49..749c8e8 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-chipid.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-chipid.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,18 +15,11 @@ package ATSAM3X8E.CHIPID is -- Registers -- --------------- - ------------------- - -- CIDR_Register -- - ------------------- - - subtype CIDR_VERSION_Field is ATSAM3X8E.UInt5; + subtype CHIPID_CIDR_VERSION_Field is ATSAM3X8E.UInt5; -- Embedded Processor - type EPROC_Field is - ( - -- Reset value for the field - Eproc_Field_Reset, - -- ARM946ES + type CIDR_EPROC_Field is + (-- ARM946ES Arm946Es, -- ARM7TDMI Arm7Tdmi, @@ -40,9 +34,8 @@ package ATSAM3X8E.CHIPID is -- Cortex-M4 Cm4) with Size => 3; - for EPROC_Field use - (Eproc_Field_Reset => 0, - Arm946Es => 1, + for CIDR_EPROC_Field use + (Arm946Es => 1, Arm7Tdmi => 2, Cm3 => 3, Arm920T => 4, @@ -51,51 +44,46 @@ package ATSAM3X8E.CHIPID is Cm4 => 7); -- Nonvolatile Program Memory Size - type NVPSIZ_Field is - ( - -- None + type CIDR_NVPSIZ_Field is + (-- None None, -- 8K bytes - NVPSIZ_Field_8K, + Val_8K, -- 16K bytes - NVPSIZ_Field_16K, + Val_16K, -- 32K bytes - NVPSIZ_Field_32K, + Val_32K, -- 64K bytes - NVPSIZ_Field_64K, + Val_64K, -- 128K bytes - NVPSIZ_Field_128K, + Val_128K, -- 256K bytes - NVPSIZ_Field_256K, + Val_256K, -- 512K bytes - NVPSIZ_Field_512K, + Val_512K, -- 1024K bytes - NVPSIZ_Field_1024K, + Val_1024K, -- 2048K bytes - NVPSIZ_Field_2048K) + Val_2048K) with Size => 4; - for NVPSIZ_Field use + for CIDR_NVPSIZ_Field use (None => 0, - NVPSIZ_Field_8K => 1, - NVPSIZ_Field_16K => 2, - NVPSIZ_Field_32K => 3, - NVPSIZ_Field_64K => 5, - NVPSIZ_Field_128K => 7, - NVPSIZ_Field_256K => 9, - NVPSIZ_Field_512K => 10, - NVPSIZ_Field_1024K => 12, - NVPSIZ_Field_2048K => 14); - - ----------------- - -- CIDR.NVPSIZ -- - ----------------- + Val_8K => 1, + Val_16K => 2, + Val_32K => 3, + Val_64K => 5, + Val_128K => 7, + Val_256K => 9, + Val_512K => 10, + Val_1024K => 12, + Val_2048K => 14); - -- CIDR_NVPSIZ array - type CIDR_NVPSIZ_Field_Array is array (0 .. 1) of NVPSIZ_Field + -- CHIPID_CIDR_NVPSIZ array + type CHIPID_CIDR_NVPSIZ_Field_Array is array (1 .. 2) of CIDR_NVPSIZ_Field with Component_Size => 4, Size => 8; - -- Type definition for CIDR_NVPSIZ - type CIDR_NVPSIZ_Field + -- Type definition for CHIPID_CIDR_NVPSIZ + type CHIPID_CIDR_NVPSIZ_Field (As_Array : Boolean := False) is record case As_Array is @@ -104,76 +92,72 @@ package ATSAM3X8E.CHIPID is Val : ATSAM3X8E.Byte; when True => -- NVPSIZ as an array - Arr : CIDR_NVPSIZ_Field_Array; + Arr : CHIPID_CIDR_NVPSIZ_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for CIDR_NVPSIZ_Field use record + for CHIPID_CIDR_NVPSIZ_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- Internal SRAM Size - type SRAMSIZ_Field is - ( - -- 48K bytes - SRAMSIZ_Field_48K, + type CIDR_SRAMSIZ_Field is + (-- 48K bytes + Val_48K, -- 1K bytes - SRAMSIZ_Field_1K, + Val_1K, -- 2K bytes - SRAMSIZ_Field_2K, + Val_2K, -- 6K bytes - SRAMSIZ_Field_6K, + Val_6K, -- 24K bytes - SRAMSIZ_Field_24K, + Val_24K, -- 4K bytes - SRAMSIZ_Field_4K, + Val_4K, -- 80K bytes - SRAMSIZ_Field_80K, + Val_80K, -- 160K bytes - SRAMSIZ_Field_160K, + Val_160K, -- 8K bytes - SRAMSIZ_Field_8K, + Val_8K, -- 16K bytes - SRAMSIZ_Field_16K, + Val_16K, -- 32K bytes - SRAMSIZ_Field_32K, + Val_32K, -- 64K bytes - SRAMSIZ_Field_64K, + Val_64K, -- 128K bytes - SRAMSIZ_Field_128K, + Val_128K, -- 256K bytes - SRAMSIZ_Field_256K, + Val_256K, -- 96K bytes - SRAMSIZ_Field_96K, + Val_96K, -- 512K bytes - SRAMSIZ_Field_512K) + Val_512K) with Size => 4; - for SRAMSIZ_Field use - (SRAMSIZ_Field_48K => 0, - SRAMSIZ_Field_1K => 1, - SRAMSIZ_Field_2K => 2, - SRAMSIZ_Field_6K => 3, - SRAMSIZ_Field_24K => 4, - SRAMSIZ_Field_4K => 5, - SRAMSIZ_Field_80K => 6, - SRAMSIZ_Field_160K => 7, - SRAMSIZ_Field_8K => 8, - SRAMSIZ_Field_16K => 9, - SRAMSIZ_Field_32K => 10, - SRAMSIZ_Field_64K => 11, - SRAMSIZ_Field_128K => 12, - SRAMSIZ_Field_256K => 13, - SRAMSIZ_Field_96K => 14, - SRAMSIZ_Field_512K => 15); + for CIDR_SRAMSIZ_Field use + (Val_48K => 0, + Val_1K => 1, + Val_2K => 2, + Val_6K => 3, + Val_24K => 4, + Val_4K => 5, + Val_80K => 6, + Val_160K => 7, + Val_8K => 8, + Val_16K => 9, + Val_32K => 10, + Val_64K => 11, + Val_128K => 12, + Val_256K => 13, + Val_96K => 14, + Val_512K => 15); -- Architecture Identifier - type ARCH_Field is - ( - -- Reset value for the field - Arch_Field_Reset, - -- AT91SAM9xx Series + type CIDR_ARCH_Field is + (-- AT91SAM9xx Series At91Sam9XX, -- AT91SAM9XExx Series At91Sam9Xexx, @@ -244,9 +228,8 @@ package ATSAM3X8E.CHIPID is -- AT75Cxx Series At75Cxx) with Size => 8; - for ARCH_Field use - (Arch_Field_Reset => 0, - At91Sam9XX => 25, + for CIDR_ARCH_Field use + (At91Sam9XX => 25, At91Sam9Xexx => 41, At91X34 => 52, Cap7 => 55, @@ -283,9 +266,8 @@ package ATSAM3X8E.CHIPID is At75Cxx => 240); -- Nonvolatile Program Memory Type - type NVPTYP_Field is - ( - -- ROM + type CIDR_NVPTYP_Field is + (-- ROM Rom, -- ROMless or on-chip Flash Romless, @@ -296,35 +278,35 @@ package ATSAM3X8E.CHIPID is -- SRAM emulating ROM Sram) with Size => 3; - for NVPTYP_Field use + for CIDR_NVPTYP_Field use (Rom => 0, Romless => 1, Flash => 2, Rom_Flash => 3, Sram => 4); - subtype CIDR_EXT_Field is ATSAM3X8E.Bit; + subtype CHIPID_CIDR_EXT_Field is ATSAM3X8E.Bit; -- Chip ID Register - type CIDR_Register is record + type CHIPID_CIDR_Register is record -- Read-only. Version of the Device - VERSION : CIDR_VERSION_Field := 16#0#; + VERSION : CHIPID_CIDR_VERSION_Field; -- Read-only. Embedded Processor - EPROC : EPROC_Field := Eproc_Field_Reset; + EPROC : CIDR_EPROC_Field; -- Read-only. Nonvolatile Program Memory Size - NVPSIZ : CIDR_NVPSIZ_Field := (As_Array => False, Val => 16#0#); + NVPSIZ : CHIPID_CIDR_NVPSIZ_Field; -- Read-only. Internal SRAM Size - SRAMSIZ : SRAMSIZ_Field := SRAMSIZ_Field_48K; + SRAMSIZ : CIDR_SRAMSIZ_Field; -- Read-only. Architecture Identifier - ARCH : ARCH_Field := Arch_Field_Reset; + ARCH : CIDR_ARCH_Field; -- Read-only. Nonvolatile Program Memory Type - NVPTYP : NVPTYP_Field := Rom; + NVPTYP : CIDR_NVPTYP_Field; -- Read-only. Extension Flag - EXT : CIDR_EXT_Field := 16#0#; + EXT : CHIPID_CIDR_EXT_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CIDR_Register use record + for CHIPID_CIDR_Register use record VERSION at 0 range 0 .. 4; EPROC at 0 range 5 .. 7; NVPSIZ at 0 range 8 .. 15; @@ -341,15 +323,16 @@ package ATSAM3X8E.CHIPID is -- Chip Identifier type CHIPID_Peripheral is record -- Chip ID Register - CIDR : CIDR_Register; + CIDR : aliased CHIPID_CIDR_Register; + pragma Volatile_Full_Access (CIDR); -- Chip ID Extension Register - EXID : ATSAM3X8E.Word; + EXID : aliased ATSAM3X8E.UInt32; end record with Volatile; for CHIPID_Peripheral use record - CIDR at 0 range 0 .. 31; - EXID at 4 range 0 .. 31; + CIDR at 16#0# range 0 .. 31; + EXID at 16#4# range 0 .. 31; end record; -- Chip Identifier diff --git a/arduino-due/atsam3x8e/atsam3x8e-dacc.ads b/arduino-due/atsam3x8e/atsam3x8e-dacc.ads index 9ba4fc9..bf905f3 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-dacc.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-dacc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,233 +15,219 @@ package ATSAM3X8E.DACC is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_SWRST_Field is ATSAM3X8E.Bit; + subtype DACC_CR_SWRST_Field is ATSAM3X8E.Bit; -- Control Register - type CR_Register is record + type DACC_CR_Register is record -- Write-only. Software Reset - SWRST : CR_SWRST_Field := 16#0#; + SWRST : DACC_CR_SWRST_Field := 16#0#; -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for DACC_CR_Register use record SWRST at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------- - -- MR_Register -- - ----------------- - -- Trigger Enable - type TRGEN_Field is - ( - -- External trigger mode disabled. DACC in free running mode. + type MR_TRGEN_Field is + (-- External trigger mode disabled. DACC in free running mode. Dis, -- External trigger mode enabled. En) with Size => 1; - for TRGEN_Field use + for MR_TRGEN_Field use (Dis => 0, En => 1); - subtype MR_TRGSEL_Field is ATSAM3X8E.UInt3; + subtype DACC_MR_TRGSEL_Field is ATSAM3X8E.UInt3; -- Word Transfer - type WORD_Field is - ( - -- Half-Word transfer + type MR_WORD_Field is + (-- Half-Word transfer Half, -- Word Transfer Word) with Size => 1; - for WORD_Field use + for MR_WORD_Field use (Half => 0, Word => 1); - subtype MR_SLEEP_Field is ATSAM3X8E.Bit; - subtype MR_FASTWKUP_Field is ATSAM3X8E.Bit; - subtype MR_REFRESH_Field is ATSAM3X8E.Byte; + subtype DACC_MR_SLEEP_Field is ATSAM3X8E.Bit; + subtype DACC_MR_FASTWKUP_Field is ATSAM3X8E.Bit; + subtype DACC_MR_REFRESH_Field is ATSAM3X8E.Byte; -- User Channel Selection - type USER_SEL_Field is - ( - -- Channel 0 + type MR_USER_SEL_Field is + (-- Channel 0 Channel0, -- Channel 1 Channel1) with Size => 2; - for USER_SEL_Field use + for MR_USER_SEL_Field use (Channel0 => 0, Channel1 => 1); -- Tag Selection Mode - type TAG_Field is - ( - -- Tag selection mode disabled. Using USER_SEL to select the channel for - -- the conversion. + type MR_TAG_Field is + (-- Tag selection mode disabled. Using USER_SEL to select the channel for the +-- conversion. Dis, -- Tag selection mode enabled En) with Size => 1; - for TAG_Field use + for MR_TAG_Field use (Dis => 0, En => 1); -- Max Speed Mode - type MAXS_Field is - ( - -- Normal Mode + type MR_MAXS_Field is + (-- Normal Mode Normal, -- Max Speed Mode enabled Maximum) with Size => 1; - for MAXS_Field use + for MR_MAXS_Field use (Normal => 0, Maximum => 1); -- Startup Time Selection - type STARTUP_Field is - ( - -- 0 periods of DACClock - STARTUP_Field_0, + type MR_STARTUP_Field is + (-- 0 periods of DACClock + Val_0, -- 8 periods of DACClock - STARTUP_Field_8, + Val_8, -- 16 periods of DACClock - STARTUP_Field_16, + Val_16, -- 24 periods of DACClock - STARTUP_Field_24, + Val_24, -- 64 periods of DACClock - STARTUP_Field_64, + Val_64, -- 80 periods of DACClock - STARTUP_Field_80, + Val_80, -- 96 periods of DACClock - STARTUP_Field_96, + Val_96, -- 112 periods of DACClock - STARTUP_Field_112, + Val_112, -- 512 periods of DACClock - STARTUP_Field_512, + Val_512, -- 576 periods of DACClock - STARTUP_Field_576, + Val_576, -- 640 periods of DACClock - STARTUP_Field_640, + Val_640, -- 704 periods of DACClock - STARTUP_Field_704, + Val_704, -- 768 periods of DACClock - STARTUP_Field_768, + Val_768, -- 832 periods of DACClock - STARTUP_Field_832, + Val_832, -- 896 periods of DACClock - STARTUP_Field_896, + Val_896, -- 960 periods of DACClock - STARTUP_Field_960, + Val_960, -- 1024 periods of DACClock - STARTUP_Field_1024, + Val_1024, -- 1088 periods of DACClock - STARTUP_Field_1088, + Val_1088, -- 1152 periods of DACClock - STARTUP_Field_1152, + Val_1152, -- 1216 periods of DACClock - STARTUP_Field_1216, + Val_1216, -- 1280 periods of DACClock - STARTUP_Field_1280, + Val_1280, -- 1344 periods of DACClock - STARTUP_Field_1344, + Val_1344, -- 1408 periods of DACClock - STARTUP_Field_1408, + Val_1408, -- 1472 periods of DACClock - STARTUP_Field_1472, + Val_1472, -- 1536 periods of DACClock - STARTUP_Field_1536, + Val_1536, -- 1600 periods of DACClock - STARTUP_Field_1600, + Val_1600, -- 1664 periods of DACClock - STARTUP_Field_1664, + Val_1664, -- 1728 periods of DACClock - STARTUP_Field_1728, + Val_1728, -- 1792 periods of DACClock - STARTUP_Field_1792, + Val_1792, -- 1856 periods of DACClock - STARTUP_Field_1856, + Val_1856, -- 1920 periods of DACClock - STARTUP_Field_1920, + Val_1920, -- 1984 periods of DACClock - STARTUP_Field_1984) + Val_1984) with Size => 6; - for STARTUP_Field use - (STARTUP_Field_0 => 0, - STARTUP_Field_8 => 1, - STARTUP_Field_16 => 2, - STARTUP_Field_24 => 3, - STARTUP_Field_64 => 4, - STARTUP_Field_80 => 5, - STARTUP_Field_96 => 6, - STARTUP_Field_112 => 7, - STARTUP_Field_512 => 8, - STARTUP_Field_576 => 9, - STARTUP_Field_640 => 10, - STARTUP_Field_704 => 11, - STARTUP_Field_768 => 12, - STARTUP_Field_832 => 13, - STARTUP_Field_896 => 14, - STARTUP_Field_960 => 15, - STARTUP_Field_1024 => 16, - STARTUP_Field_1088 => 17, - STARTUP_Field_1152 => 18, - STARTUP_Field_1216 => 19, - STARTUP_Field_1280 => 20, - STARTUP_Field_1344 => 21, - STARTUP_Field_1408 => 22, - STARTUP_Field_1472 => 23, - STARTUP_Field_1536 => 24, - STARTUP_Field_1600 => 25, - STARTUP_Field_1664 => 26, - STARTUP_Field_1728 => 27, - STARTUP_Field_1792 => 28, - STARTUP_Field_1856 => 29, - STARTUP_Field_1920 => 30, - STARTUP_Field_1984 => 31); + for MR_STARTUP_Field use + (Val_0 => 0, + Val_8 => 1, + Val_16 => 2, + Val_24 => 3, + Val_64 => 4, + Val_80 => 5, + Val_96 => 6, + Val_112 => 7, + Val_512 => 8, + Val_576 => 9, + Val_640 => 10, + Val_704 => 11, + Val_768 => 12, + Val_832 => 13, + Val_896 => 14, + Val_960 => 15, + Val_1024 => 16, + Val_1088 => 17, + Val_1152 => 18, + Val_1216 => 19, + Val_1280 => 20, + Val_1344 => 21, + Val_1408 => 22, + Val_1472 => 23, + Val_1536 => 24, + Val_1600 => 25, + Val_1664 => 26, + Val_1728 => 27, + Val_1792 => 28, + Val_1856 => 29, + Val_1920 => 30, + Val_1984 => 31); -- Mode Register - type MR_Register is record + type DACC_MR_Register is record -- Trigger Enable - TRGEN : TRGEN_Field := Dis; + TRGEN : MR_TRGEN_Field := ATSAM3X8E.DACC.Dis; -- Trigger Selection - TRGSEL : MR_TRGSEL_Field := 16#0#; + TRGSEL : DACC_MR_TRGSEL_Field := 16#0#; -- Word Transfer - WORD : WORD_Field := Half; + WORD : MR_WORD_Field := ATSAM3X8E.DACC.Half; -- Sleep Mode - SLEEP : MR_SLEEP_Field := 16#0#; + SLEEP : DACC_MR_SLEEP_Field := 16#0#; -- Fast Wake up Mode - FASTWKUP : MR_FASTWKUP_Field := 16#0#; + FASTWKUP : DACC_MR_FASTWKUP_Field := 16#0#; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Refresh Period - REFRESH : MR_REFRESH_Field := 16#0#; + REFRESH : DACC_MR_REFRESH_Field := 16#0#; -- User Channel Selection - USER_SEL : USER_SEL_Field := Channel0; + USER_SEL : MR_USER_SEL_Field := ATSAM3X8E.DACC.Channel0; -- unspecified Reserved_18_19 : ATSAM3X8E.UInt2 := 16#0#; -- Tag Selection Mode - TAG : TAG_Field := Dis; + TAG : MR_TAG_Field := ATSAM3X8E.DACC.Dis; -- Max Speed Mode - MAXS : MAXS_Field := Normal; + MAXS : MR_MAXS_Field := ATSAM3X8E.DACC.Normal; -- unspecified Reserved_22_23 : ATSAM3X8E.UInt2 := 16#0#; -- Startup Time Selection - STARTUP : STARTUP_Field := STARTUP_Field_0; + STARTUP : MR_STARTUP_Field := ATSAM3X8E.DACC.Val_0; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_Register use record + for DACC_MR_Register use record TRGEN at 0 range 0 .. 0; TRGSEL at 0 range 1 .. 3; WORD at 0 range 4 .. 4; @@ -257,23 +244,15 @@ package ATSAM3X8E.DACC is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- CHER_Register -- - ------------------- - - ------------- - -- CHER.CH -- - ------------- + -- DACC_CHER_CH array element + subtype DACC_CHER_CH_Element is ATSAM3X8E.Bit; - -- CHER_CH array element - subtype CHER_CH_Element is ATSAM3X8E.Bit; - - -- CHER_CH array - type CHER_CH_Field_Array is array (0 .. 1) of CHER_CH_Element + -- DACC_CHER_CH array + type DACC_CHER_CH_Field_Array is array (0 .. 1) of DACC_CHER_CH_Element with Component_Size => 1, Size => 2; - -- Type definition for CHER_CH - type CHER_CH_Field + -- Type definition for DACC_CHER_CH + type DACC_CHER_CH_Field (As_Array : Boolean := False) is record case As_Array is @@ -282,47 +261,39 @@ package ATSAM3X8E.DACC is Val : ATSAM3X8E.UInt2; when True => -- CH as an array - Arr : CHER_CH_Field_Array; + Arr : DACC_CHER_CH_Field_Array; end case; end record with Unchecked_Union, Size => 2; - for CHER_CH_Field use record + for DACC_CHER_CH_Field use record Val at 0 range 0 .. 1; Arr at 0 range 0 .. 1; end record; -- Channel Enable Register - type CHER_Register is record + type DACC_CHER_Register is record -- Write-only. Channel 0 Enable - CH : CHER_CH_Field := (As_Array => False, Val => 16#0#); + CH : DACC_CHER_CH_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHER_Register use record + for DACC_CHER_Register use record CH at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- CHDR_Register -- - ------------------- - - ------------- - -- CHDR.CH -- - ------------- + -- DACC_CHDR_CH array element + subtype DACC_CHDR_CH_Element is ATSAM3X8E.Bit; - -- CHDR_CH array element - subtype CHDR_CH_Element is ATSAM3X8E.Bit; - - -- CHDR_CH array - type CHDR_CH_Field_Array is array (0 .. 1) of CHDR_CH_Element + -- DACC_CHDR_CH array + type DACC_CHDR_CH_Field_Array is array (0 .. 1) of DACC_CHDR_CH_Element with Component_Size => 1, Size => 2; - -- Type definition for CHDR_CH - type CHDR_CH_Field + -- Type definition for DACC_CHDR_CH + type DACC_CHDR_CH_Field (As_Array : Boolean := False) is record case As_Array is @@ -331,47 +302,39 @@ package ATSAM3X8E.DACC is Val : ATSAM3X8E.UInt2; when True => -- CH as an array - Arr : CHDR_CH_Field_Array; + Arr : DACC_CHDR_CH_Field_Array; end case; end record with Unchecked_Union, Size => 2; - for CHDR_CH_Field use record + for DACC_CHDR_CH_Field use record Val at 0 range 0 .. 1; Arr at 0 range 0 .. 1; end record; -- Channel Disable Register - type CHDR_Register is record + type DACC_CHDR_Register is record -- Write-only. Channel 0 Disable - CH : CHDR_CH_Field := (As_Array => False, Val => 16#0#); + CH : DACC_CHDR_CH_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHDR_Register use record + for DACC_CHDR_Register use record CH at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- CHSR_Register -- - ------------------- - - ------------- - -- CHSR.CH -- - ------------- - - -- CHSR_CH array element - subtype CHSR_CH_Element is ATSAM3X8E.Bit; + -- DACC_CHSR_CH array element + subtype DACC_CHSR_CH_Element is ATSAM3X8E.Bit; - -- CHSR_CH array - type CHSR_CH_Field_Array is array (0 .. 1) of CHSR_CH_Element + -- DACC_CHSR_CH array + type DACC_CHSR_CH_Field_Array is array (0 .. 1) of DACC_CHSR_CH_Element with Component_Size => 1, Size => 2; - -- Type definition for CHSR_CH - type CHSR_CH_Field + -- Type definition for DACC_CHSR_CH + type DACC_CHSR_CH_Field (As_Array : Boolean := False) is record case As_Array is @@ -380,55 +343,51 @@ package ATSAM3X8E.DACC is Val : ATSAM3X8E.UInt2; when True => -- CH as an array - Arr : CHSR_CH_Field_Array; + Arr : DACC_CHSR_CH_Field_Array; end case; end record with Unchecked_Union, Size => 2; - for CHSR_CH_Field use record + for DACC_CHSR_CH_Field use record Val at 0 range 0 .. 1; Arr at 0 range 0 .. 1; end record; -- Channel Status Register - type CHSR_Register is record + type DACC_CHSR_Register is record -- Read-only. Channel 0 Status - CH : CHSR_CH_Field := (As_Array => False, Val => 16#0#); + CH : DACC_CHSR_CH_Field; -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHSR_Register use record + for DACC_CHSR_Register use record CH at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_TXRDY_Field is ATSAM3X8E.Bit; - subtype IER_EOC_Field is ATSAM3X8E.Bit; - subtype IER_ENDTX_Field is ATSAM3X8E.Bit; - subtype IER_TXBUFE_Field is ATSAM3X8E.Bit; + subtype DACC_IER_TXRDY_Field is ATSAM3X8E.Bit; + subtype DACC_IER_EOC_Field is ATSAM3X8E.Bit; + subtype DACC_IER_ENDTX_Field is ATSAM3X8E.Bit; + subtype DACC_IER_TXBUFE_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type DACC_IER_Register is record -- Write-only. Transmit Ready Interrupt Enable - TXRDY : IER_TXRDY_Field := 16#0#; + TXRDY : DACC_IER_TXRDY_Field := 16#0#; -- Write-only. End of Conversion Interrupt Enable - EOC : IER_EOC_Field := 16#0#; + EOC : DACC_IER_EOC_Field := 16#0#; -- Write-only. End of Transmit Buffer Interrupt Enable - ENDTX : IER_ENDTX_Field := 16#0#; + ENDTX : DACC_IER_ENDTX_Field := 16#0#; -- Write-only. Transmit Buffer Empty Interrupt Enable - TXBUFE : IER_TXBUFE_Field := 16#0#; + TXBUFE : DACC_IER_TXBUFE_Field := 16#0#; -- unspecified Reserved_4_31 : ATSAM3X8E.UInt28 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for DACC_IER_Register use record TXRDY at 0 range 0 .. 0; EOC at 0 range 1 .. 1; ENDTX at 0 range 2 .. 2; @@ -436,31 +395,27 @@ package ATSAM3X8E.DACC is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_EOC_Field is ATSAM3X8E.Bit; - subtype IDR_ENDTX_Field is ATSAM3X8E.Bit; - subtype IDR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype DACC_IDR_TXRDY_Field is ATSAM3X8E.Bit; + subtype DACC_IDR_EOC_Field is ATSAM3X8E.Bit; + subtype DACC_IDR_ENDTX_Field is ATSAM3X8E.Bit; + subtype DACC_IDR_TXBUFE_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type DACC_IDR_Register is record -- Write-only. Transmit Ready Interrupt Disable. - TXRDY : IDR_TXRDY_Field := 16#0#; + TXRDY : DACC_IDR_TXRDY_Field := 16#0#; -- Write-only. End of Conversion Interrupt Disable - EOC : IDR_EOC_Field := 16#0#; + EOC : DACC_IDR_EOC_Field := 16#0#; -- Write-only. End of Transmit Buffer Interrupt Disable - ENDTX : IDR_ENDTX_Field := 16#0#; + ENDTX : DACC_IDR_ENDTX_Field := 16#0#; -- Write-only. Transmit Buffer Empty Interrupt Disable - TXBUFE : IDR_TXBUFE_Field := 16#0#; + TXBUFE : DACC_IDR_TXBUFE_Field := 16#0#; -- unspecified Reserved_4_31 : ATSAM3X8E.UInt28 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for DACC_IDR_Register use record TXRDY at 0 range 0 .. 0; EOC at 0 range 1 .. 1; ENDTX at 0 range 2 .. 2; @@ -468,31 +423,27 @@ package ATSAM3X8E.DACC is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_EOC_Field is ATSAM3X8E.Bit; - subtype IMR_ENDTX_Field is ATSAM3X8E.Bit; - subtype IMR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype DACC_IMR_TXRDY_Field is ATSAM3X8E.Bit; + subtype DACC_IMR_EOC_Field is ATSAM3X8E.Bit; + subtype DACC_IMR_ENDTX_Field is ATSAM3X8E.Bit; + subtype DACC_IMR_TXBUFE_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type DACC_IMR_Register is record -- Read-only. Transmit Ready Interrupt Mask - TXRDY : IMR_TXRDY_Field := 16#0#; + TXRDY : DACC_IMR_TXRDY_Field; -- Read-only. End of Conversion Interrupt Mask - EOC : IMR_EOC_Field := 16#0#; + EOC : DACC_IMR_EOC_Field; -- Read-only. End of Transmit Buffer Interrupt Mask - ENDTX : IMR_ENDTX_Field := 16#0#; + ENDTX : DACC_IMR_ENDTX_Field; -- Read-only. Transmit Buffer Empty Interrupt Mask - TXBUFE : IMR_TXBUFE_Field := 16#0#; + TXBUFE : DACC_IMR_TXBUFE_Field; -- unspecified Reserved_4_31 : ATSAM3X8E.UInt28; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for DACC_IMR_Register use record TXRDY at 0 range 0 .. 0; EOC at 0 range 1 .. 1; ENDTX at 0 range 2 .. 2; @@ -500,31 +451,27 @@ package ATSAM3X8E.DACC is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ - - subtype ISR_TXRDY_Field is ATSAM3X8E.Bit; - subtype ISR_EOC_Field is ATSAM3X8E.Bit; - subtype ISR_ENDTX_Field is ATSAM3X8E.Bit; - subtype ISR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype DACC_ISR_TXRDY_Field is ATSAM3X8E.Bit; + subtype DACC_ISR_EOC_Field is ATSAM3X8E.Bit; + subtype DACC_ISR_ENDTX_Field is ATSAM3X8E.Bit; + subtype DACC_ISR_TXBUFE_Field is ATSAM3X8E.Bit; -- Interrupt Status Register - type ISR_Register is record + type DACC_ISR_Register is record -- Read-only. Transmit Ready Interrupt Flag - TXRDY : ISR_TXRDY_Field := 16#0#; + TXRDY : DACC_ISR_TXRDY_Field; -- Read-only. End of Conversion Interrupt Flag - EOC : ISR_EOC_Field := 16#0#; + EOC : DACC_ISR_EOC_Field; -- Read-only. End of DMA Interrupt Flag - ENDTX : ISR_ENDTX_Field := 16#0#; + ENDTX : DACC_ISR_ENDTX_Field; -- Read-only. Transmit Buffer Empty - TXBUFE : ISR_TXBUFE_Field := 16#0#; + TXBUFE : DACC_ISR_TXBUFE_Field; -- unspecified Reserved_4_31 : ATSAM3X8E.UInt28; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ISR_Register use record + for DACC_ISR_Register use record TXRDY at 0 range 0 .. 0; EOC at 0 range 1 .. 1; ENDTX at 0 range 2 .. 2; @@ -532,23 +479,16 @@ package ATSAM3X8E.DACC is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------ - -- ACR_Register -- - ------------------ - - ----------------- - -- ACR.IBCTLCH -- - ----------------- - - -- ACR_IBCTLCH array element - subtype ACR_IBCTLCH_Element is ATSAM3X8E.UInt2; + -- DACC_ACR_IBCTLCH array element + subtype DACC_ACR_IBCTLCH_Element is ATSAM3X8E.UInt2; - -- ACR_IBCTLCH array - type ACR_IBCTLCH_Field_Array is array (0 .. 1) of ACR_IBCTLCH_Element + -- DACC_ACR_IBCTLCH array + type DACC_ACR_IBCTLCH_Field_Array is array (0 .. 1) + of DACC_ACR_IBCTLCH_Element with Component_Size => 2, Size => 4; - -- Type definition for ACR_IBCTLCH - type ACR_IBCTLCH_Field + -- Type definition for DACC_ACR_IBCTLCH + type DACC_ACR_IBCTLCH_Field (As_Array : Boolean := False) is record case As_Array is @@ -557,156 +497,137 @@ package ATSAM3X8E.DACC is Val : ATSAM3X8E.UInt4; when True => -- IBCTLCH as an array - Arr : ACR_IBCTLCH_Field_Array; + Arr : DACC_ACR_IBCTLCH_Field_Array; end case; end record with Unchecked_Union, Size => 4; - for ACR_IBCTLCH_Field use record + for DACC_ACR_IBCTLCH_Field use record Val at 0 range 0 .. 3; Arr at 0 range 0 .. 3; end record; - subtype ACR_IBCTLDACCORE_Field is ATSAM3X8E.UInt2; + subtype DACC_ACR_IBCTLDACCORE_Field is ATSAM3X8E.UInt2; -- Analog Current Register - type ACR_Register is record + type DACC_ACR_Register is record -- Analog Output Current Control - IBCTLCH : ACR_IBCTLCH_Field := (As_Array => False, Val => 16#0#); + IBCTLCH : DACC_ACR_IBCTLCH_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; -- Bias Current Control for DAC Core - IBCTLDACCORE : ACR_IBCTLDACCORE_Field := 16#0#; + IBCTLDACCORE : DACC_ACR_IBCTLDACCORE_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ACR_Register use record + for DACC_ACR_Register use record IBCTLCH at 0 range 0 .. 3; Reserved_4_7 at 0 range 4 .. 7; IBCTLDACCORE at 0 range 8 .. 9; Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype DACC_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype DACC_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- Write Protect Mode register - type WPMR_Register is record + type DACC_WPMR_Register is record -- Write Protect Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : DACC_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protect KEY - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : DACC_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for DACC_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WPROTERR_Field is ATSAM3X8E.Bit; - subtype WPSR_WPROTADDR_Field is ATSAM3X8E.Byte; + subtype DACC_WPSR_WPROTERR_Field is ATSAM3X8E.Bit; + subtype DACC_WPSR_WPROTADDR_Field is ATSAM3X8E.Byte; -- Write Protect Status register - type WPSR_Register is record + type DACC_WPSR_Register is record -- Read-only. Write protection error - WPROTERR : WPSR_WPROTERR_Field := 16#0#; + WPROTERR : DACC_WPSR_WPROTERR_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write protection error address - WPROTADDR : WPSR_WPROTADDR_Field := 16#0#; + WPROTADDR : DACC_WPSR_WPROTADDR_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for DACC_WPSR_Register use record WPROTERR at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPROTADDR at 0 range 8 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- TCR_Register -- - ------------------ - - subtype TCR_TXCTR_Field is ATSAM3X8E.Short; + subtype DACC_TCR_TXCTR_Field is ATSAM3X8E.UInt16; -- Transmit Counter Register - type TCR_Register is record + type DACC_TCR_Register is record -- Transmit Counter Register - TXCTR : TCR_TXCTR_Field := 16#0#; + TXCTR : DACC_TCR_TXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TCR_Register use record + for DACC_TCR_Register use record TXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- TNCR_Register -- - ------------------- - - subtype TNCR_TXNCTR_Field is ATSAM3X8E.Short; + subtype DACC_TNCR_TXNCTR_Field is ATSAM3X8E.UInt16; -- Transmit Next Counter Register - type TNCR_Register is record + type DACC_TNCR_Register is record -- Transmit Counter Next - TXNCTR : TNCR_TXNCTR_Field := 16#0#; + TXNCTR : DACC_TNCR_TXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TNCR_Register use record + for DACC_TNCR_Register use record TXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- PTCR_Register -- - ------------------- - - subtype PTCR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_RXTDIS_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTDIS_Field is ATSAM3X8E.Bit; + subtype DACC_PTCR_RXTEN_Field is ATSAM3X8E.Bit; + subtype DACC_PTCR_RXTDIS_Field is ATSAM3X8E.Bit; + subtype DACC_PTCR_TXTEN_Field is ATSAM3X8E.Bit; + subtype DACC_PTCR_TXTDIS_Field is ATSAM3X8E.Bit; -- Transfer Control Register - type PTCR_Register is record + type DACC_PTCR_Register is record -- Write-only. Receiver Transfer Enable - RXTEN : PTCR_RXTEN_Field := 16#0#; + RXTEN : DACC_PTCR_RXTEN_Field := 16#0#; -- Write-only. Receiver Transfer Disable - RXTDIS : PTCR_RXTDIS_Field := 16#0#; + RXTDIS : DACC_PTCR_RXTDIS_Field := 16#0#; -- unspecified Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; -- Write-only. Transmitter Transfer Enable - TXTEN : PTCR_TXTEN_Field := 16#0#; + TXTEN : DACC_PTCR_TXTEN_Field := 16#0#; -- Write-only. Transmitter Transfer Disable - TXTDIS : PTCR_TXTDIS_Field := 16#0#; + TXTDIS : DACC_PTCR_TXTDIS_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTCR_Register use record + for DACC_PTCR_Register use record RXTEN at 0 range 0 .. 0; RXTDIS at 0 range 1 .. 1; Reserved_2_7 at 0 range 2 .. 7; @@ -715,27 +636,23 @@ package ATSAM3X8E.DACC is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- PTSR_Register -- - ------------------- - - subtype PTSR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTSR_TXTEN_Field is ATSAM3X8E.Bit; + subtype DACC_PTSR_RXTEN_Field is ATSAM3X8E.Bit; + subtype DACC_PTSR_TXTEN_Field is ATSAM3X8E.Bit; -- Transfer Status Register - type PTSR_Register is record + type DACC_PTSR_Register is record -- Read-only. Receiver Transfer Enable - RXTEN : PTSR_RXTEN_Field := 16#0#; + RXTEN : DACC_PTSR_RXTEN_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Transmitter Transfer Enable - TXTEN : PTSR_TXTEN_Field := 16#0#; + TXTEN : DACC_PTSR_TXTEN_Field; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTSR_Register use record + for DACC_PTSR_Register use record RXTEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; TXTEN at 0 range 8 .. 8; @@ -749,66 +666,82 @@ package ATSAM3X8E.DACC is -- Digital-to-Analog Converter Controller type DACC_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased DACC_CR_Register; + pragma Volatile_Full_Access (CR); -- Mode Register - MR : MR_Register; + MR : aliased DACC_MR_Register; + pragma Volatile_Full_Access (MR); -- Channel Enable Register - CHER : CHER_Register; + CHER : aliased DACC_CHER_Register; + pragma Volatile_Full_Access (CHER); -- Channel Disable Register - CHDR : CHDR_Register; + CHDR : aliased DACC_CHDR_Register; + pragma Volatile_Full_Access (CHDR); -- Channel Status Register - CHSR : CHSR_Register; + CHSR : aliased DACC_CHSR_Register; + pragma Volatile_Full_Access (CHSR); -- Conversion Data Register - CDR : ATSAM3X8E.Word; + CDR : aliased ATSAM3X8E.UInt32; -- Interrupt Enable Register - IER : IER_Register; + IER : aliased DACC_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased DACC_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased DACC_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Interrupt Status Register - ISR : ISR_Register; + ISR : aliased DACC_ISR_Register; + pragma Volatile_Full_Access (ISR); -- Analog Current Register - ACR : ACR_Register; + ACR : aliased DACC_ACR_Register; + pragma Volatile_Full_Access (ACR); -- Write Protect Mode register - WPMR : WPMR_Register; + WPMR : aliased DACC_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- Write Protect Status register - WPSR : WPSR_Register; + WPSR : aliased DACC_WPSR_Register; + pragma Volatile_Full_Access (WPSR); -- Transmit Pointer Register - TPR : ATSAM3X8E.Word; + TPR : aliased ATSAM3X8E.UInt32; -- Transmit Counter Register - TCR : TCR_Register; + TCR : aliased DACC_TCR_Register; + pragma Volatile_Full_Access (TCR); -- Transmit Next Pointer Register - TNPR : ATSAM3X8E.Word; + TNPR : aliased ATSAM3X8E.UInt32; -- Transmit Next Counter Register - TNCR : TNCR_Register; + TNCR : aliased DACC_TNCR_Register; + pragma Volatile_Full_Access (TNCR); -- Transfer Control Register - PTCR : PTCR_Register; + PTCR : aliased DACC_PTCR_Register; + pragma Volatile_Full_Access (PTCR); -- Transfer Status Register - PTSR : PTSR_Register; + PTSR : aliased DACC_PTSR_Register; + pragma Volatile_Full_Access (PTSR); end record with Volatile; for DACC_Peripheral use record - CR at 0 range 0 .. 31; - MR at 4 range 0 .. 31; - CHER at 16 range 0 .. 31; - CHDR at 20 range 0 .. 31; - CHSR at 24 range 0 .. 31; - CDR at 32 range 0 .. 31; - IER at 36 range 0 .. 31; - IDR at 40 range 0 .. 31; - IMR at 44 range 0 .. 31; - ISR at 48 range 0 .. 31; - ACR at 148 range 0 .. 31; - WPMR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; - TPR at 264 range 0 .. 31; - TCR at 268 range 0 .. 31; - TNPR at 280 range 0 .. 31; - TNCR at 284 range 0 .. 31; - PTCR at 288 range 0 .. 31; - PTSR at 292 range 0 .. 31; + CR at 16#0# range 0 .. 31; + MR at 16#4# range 0 .. 31; + CHER at 16#10# range 0 .. 31; + CHDR at 16#14# range 0 .. 31; + CHSR at 16#18# range 0 .. 31; + CDR at 16#20# range 0 .. 31; + IER at 16#24# range 0 .. 31; + IDR at 16#28# range 0 .. 31; + IMR at 16#2C# range 0 .. 31; + ISR at 16#30# range 0 .. 31; + ACR at 16#94# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; + TPR at 16#108# range 0 .. 31; + TCR at 16#10C# range 0 .. 31; + TNPR at 16#118# range 0 .. 31; + TNCR at 16#11C# range 0 .. 31; + PTCR at 16#120# range 0 .. 31; + PTSR at 16#124# range 0 .. 31; end record; -- Digital-to-Analog Converter Controller diff --git a/arduino-due/atsam3x8e/atsam3x8e-dmac.ads b/arduino-due/atsam3x8e/atsam3x8e-dmac.ads index 490a8e9..f89733b 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-dmac.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-dmac.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,107 +15,94 @@ package ATSAM3X8E.DMAC is -- Registers -- --------------- - ------------------- - -- GCFG_Register -- - ------------------- - -- Arbiter Configuration - type ARB_CFG_Field is - ( - -- Fixed priority arbiter. + type GCFG_ARB_CFG_Field is + (-- Fixed priority arbiter. Fixed, -- Modified round robin arbiter. Round_Robin) with Size => 1; - for ARB_CFG_Field use + for GCFG_ARB_CFG_Field use (Fixed => 0, Round_Robin => 1); -- DMAC Global Configuration Register - type GCFG_Register is record + type DMAC_GCFG_Register is record -- unspecified Reserved_0_3 : ATSAM3X8E.UInt4 := 16#0#; -- Arbiter Configuration - ARB_CFG : ARB_CFG_Field := Round_Robin; + ARB_CFG : GCFG_ARB_CFG_Field := ATSAM3X8E.DMAC.Round_Robin; -- unspecified Reserved_5_31 : ATSAM3X8E.UInt27 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for GCFG_Register use record + for DMAC_GCFG_Register use record Reserved_0_3 at 0 range 0 .. 3; ARB_CFG at 0 range 4 .. 4; Reserved_5_31 at 0 range 5 .. 31; end record; - ----------------- - -- EN_Register -- - ----------------- - - subtype EN_ENABLE_Field is ATSAM3X8E.Bit; + subtype DMAC_EN_ENABLE_Field is ATSAM3X8E.Bit; -- DMAC Enable Register - type EN_Register is record - ENABLE : EN_ENABLE_Field := 16#0#; + type DMAC_EN_Register is record + ENABLE : DMAC_EN_ENABLE_Field := 16#0#; -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EN_Register use record + for DMAC_EN_Register use record ENABLE at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------- - -- SREQ_Register -- - ------------------- - - subtype SREQ_SSREQ0_Field is ATSAM3X8E.Bit; - subtype SREQ_DSREQ0_Field is ATSAM3X8E.Bit; - subtype SREQ_SSREQ1_Field is ATSAM3X8E.Bit; - subtype SREQ_DSREQ1_Field is ATSAM3X8E.Bit; - subtype SREQ_SSREQ2_Field is ATSAM3X8E.Bit; - subtype SREQ_DSREQ2_Field is ATSAM3X8E.Bit; - subtype SREQ_SSREQ3_Field is ATSAM3X8E.Bit; - subtype SREQ_DSREQ3_Field is ATSAM3X8E.Bit; - subtype SREQ_SSREQ4_Field is ATSAM3X8E.Bit; - subtype SREQ_DSREQ4_Field is ATSAM3X8E.Bit; - subtype SREQ_SSREQ5_Field is ATSAM3X8E.Bit; - subtype SREQ_DSREQ5_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_SSREQ0_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_DSREQ0_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_SSREQ1_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_DSREQ1_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_SSREQ2_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_DSREQ2_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_SSREQ3_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_DSREQ3_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_SSREQ4_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_DSREQ4_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_SSREQ5_Field is ATSAM3X8E.Bit; + subtype DMAC_SREQ_DSREQ5_Field is ATSAM3X8E.Bit; -- DMAC Software Single Request Register - type SREQ_Register is record + type DMAC_SREQ_Register is record -- Source Request - SSREQ0 : SREQ_SSREQ0_Field := 16#0#; + SSREQ0 : DMAC_SREQ_SSREQ0_Field := 16#0#; -- Destination Request - DSREQ0 : SREQ_DSREQ0_Field := 16#0#; + DSREQ0 : DMAC_SREQ_DSREQ0_Field := 16#0#; -- Source Request - SSREQ1 : SREQ_SSREQ1_Field := 16#0#; + SSREQ1 : DMAC_SREQ_SSREQ1_Field := 16#0#; -- Destination Request - DSREQ1 : SREQ_DSREQ1_Field := 16#0#; + DSREQ1 : DMAC_SREQ_DSREQ1_Field := 16#0#; -- Source Request - SSREQ2 : SREQ_SSREQ2_Field := 16#0#; + SSREQ2 : DMAC_SREQ_SSREQ2_Field := 16#0#; -- Destination Request - DSREQ2 : SREQ_DSREQ2_Field := 16#0#; + DSREQ2 : DMAC_SREQ_DSREQ2_Field := 16#0#; -- Source Request - SSREQ3 : SREQ_SSREQ3_Field := 16#0#; + SSREQ3 : DMAC_SREQ_SSREQ3_Field := 16#0#; -- Destination Request - DSREQ3 : SREQ_DSREQ3_Field := 16#0#; + DSREQ3 : DMAC_SREQ_DSREQ3_Field := 16#0#; -- Source Request - SSREQ4 : SREQ_SSREQ4_Field := 16#0#; + SSREQ4 : DMAC_SREQ_SSREQ4_Field := 16#0#; -- Destination Request - DSREQ4 : SREQ_DSREQ4_Field := 16#0#; + DSREQ4 : DMAC_SREQ_DSREQ4_Field := 16#0#; -- Source Request - SSREQ5 : SREQ_SSREQ5_Field := 16#0#; + SSREQ5 : DMAC_SREQ_SSREQ5_Field := 16#0#; -- Destination Request - DSREQ5 : SREQ_DSREQ5_Field := 16#0#; + DSREQ5 : DMAC_SREQ_DSREQ5_Field := 16#0#; -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SREQ_Register use record + for DMAC_SREQ_Register use record SSREQ0 at 0 range 0 .. 0; DSREQ0 at 0 range 1 .. 1; SSREQ1 at 0 range 2 .. 2; @@ -130,55 +118,51 @@ package ATSAM3X8E.DMAC is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------- - -- CREQ_Register -- - ------------------- - - subtype CREQ_SCREQ0_Field is ATSAM3X8E.Bit; - subtype CREQ_DCREQ0_Field is ATSAM3X8E.Bit; - subtype CREQ_SCREQ1_Field is ATSAM3X8E.Bit; - subtype CREQ_DCREQ1_Field is ATSAM3X8E.Bit; - subtype CREQ_SCREQ2_Field is ATSAM3X8E.Bit; - subtype CREQ_DCREQ2_Field is ATSAM3X8E.Bit; - subtype CREQ_SCREQ3_Field is ATSAM3X8E.Bit; - subtype CREQ_DCREQ3_Field is ATSAM3X8E.Bit; - subtype CREQ_SCREQ4_Field is ATSAM3X8E.Bit; - subtype CREQ_DCREQ4_Field is ATSAM3X8E.Bit; - subtype CREQ_SCREQ5_Field is ATSAM3X8E.Bit; - subtype CREQ_DCREQ5_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_SCREQ0_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_DCREQ0_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_SCREQ1_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_DCREQ1_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_SCREQ2_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_DCREQ2_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_SCREQ3_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_DCREQ3_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_SCREQ4_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_DCREQ4_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_SCREQ5_Field is ATSAM3X8E.Bit; + subtype DMAC_CREQ_DCREQ5_Field is ATSAM3X8E.Bit; -- DMAC Software Chunk Transfer Request Register - type CREQ_Register is record + type DMAC_CREQ_Register is record -- Source Chunk Request - SCREQ0 : CREQ_SCREQ0_Field := 16#0#; + SCREQ0 : DMAC_CREQ_SCREQ0_Field := 16#0#; -- Destination Chunk Request - DCREQ0 : CREQ_DCREQ0_Field := 16#0#; + DCREQ0 : DMAC_CREQ_DCREQ0_Field := 16#0#; -- Source Chunk Request - SCREQ1 : CREQ_SCREQ1_Field := 16#0#; + SCREQ1 : DMAC_CREQ_SCREQ1_Field := 16#0#; -- Destination Chunk Request - DCREQ1 : CREQ_DCREQ1_Field := 16#0#; + DCREQ1 : DMAC_CREQ_DCREQ1_Field := 16#0#; -- Source Chunk Request - SCREQ2 : CREQ_SCREQ2_Field := 16#0#; + SCREQ2 : DMAC_CREQ_SCREQ2_Field := 16#0#; -- Destination Chunk Request - DCREQ2 : CREQ_DCREQ2_Field := 16#0#; + DCREQ2 : DMAC_CREQ_DCREQ2_Field := 16#0#; -- Source Chunk Request - SCREQ3 : CREQ_SCREQ3_Field := 16#0#; + SCREQ3 : DMAC_CREQ_SCREQ3_Field := 16#0#; -- Destination Chunk Request - DCREQ3 : CREQ_DCREQ3_Field := 16#0#; + DCREQ3 : DMAC_CREQ_DCREQ3_Field := 16#0#; -- Source Chunk Request - SCREQ4 : CREQ_SCREQ4_Field := 16#0#; + SCREQ4 : DMAC_CREQ_SCREQ4_Field := 16#0#; -- Destination Chunk Request - DCREQ4 : CREQ_DCREQ4_Field := 16#0#; + DCREQ4 : DMAC_CREQ_DCREQ4_Field := 16#0#; -- Source Chunk Request - SCREQ5 : CREQ_SCREQ5_Field := 16#0#; + SCREQ5 : DMAC_CREQ_SCREQ5_Field := 16#0#; -- Destination Chunk Request - DCREQ5 : CREQ_DCREQ5_Field := 16#0#; + DCREQ5 : DMAC_CREQ_DCREQ5_Field := 16#0#; -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CREQ_Register use record + for DMAC_CREQ_Register use record SCREQ0 at 0 range 0 .. 0; DCREQ0 at 0 range 1 .. 1; SCREQ1 at 0 range 2 .. 2; @@ -194,55 +178,51 @@ package ATSAM3X8E.DMAC is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------- - -- LAST_Register -- - ------------------- - - subtype LAST_SLAST0_Field is ATSAM3X8E.Bit; - subtype LAST_DLAST0_Field is ATSAM3X8E.Bit; - subtype LAST_SLAST1_Field is ATSAM3X8E.Bit; - subtype LAST_DLAST1_Field is ATSAM3X8E.Bit; - subtype LAST_SLAST2_Field is ATSAM3X8E.Bit; - subtype LAST_DLAST2_Field is ATSAM3X8E.Bit; - subtype LAST_SLAST3_Field is ATSAM3X8E.Bit; - subtype LAST_DLAST3_Field is ATSAM3X8E.Bit; - subtype LAST_SLAST4_Field is ATSAM3X8E.Bit; - subtype LAST_DLAST4_Field is ATSAM3X8E.Bit; - subtype LAST_SLAST5_Field is ATSAM3X8E.Bit; - subtype LAST_DLAST5_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_SLAST0_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_DLAST0_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_SLAST1_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_DLAST1_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_SLAST2_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_DLAST2_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_SLAST3_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_DLAST3_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_SLAST4_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_DLAST4_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_SLAST5_Field is ATSAM3X8E.Bit; + subtype DMAC_LAST_DLAST5_Field is ATSAM3X8E.Bit; -- DMAC Software Last Transfer Flag Register - type LAST_Register is record + type DMAC_LAST_Register is record -- Source Last - SLAST0 : LAST_SLAST0_Field := 16#0#; + SLAST0 : DMAC_LAST_SLAST0_Field := 16#0#; -- Destination Last - DLAST0 : LAST_DLAST0_Field := 16#0#; + DLAST0 : DMAC_LAST_DLAST0_Field := 16#0#; -- Source Last - SLAST1 : LAST_SLAST1_Field := 16#0#; + SLAST1 : DMAC_LAST_SLAST1_Field := 16#0#; -- Destination Last - DLAST1 : LAST_DLAST1_Field := 16#0#; + DLAST1 : DMAC_LAST_DLAST1_Field := 16#0#; -- Source Last - SLAST2 : LAST_SLAST2_Field := 16#0#; + SLAST2 : DMAC_LAST_SLAST2_Field := 16#0#; -- Destination Last - DLAST2 : LAST_DLAST2_Field := 16#0#; + DLAST2 : DMAC_LAST_DLAST2_Field := 16#0#; -- Source Last - SLAST3 : LAST_SLAST3_Field := 16#0#; + SLAST3 : DMAC_LAST_SLAST3_Field := 16#0#; -- Destination Last - DLAST3 : LAST_DLAST3_Field := 16#0#; + DLAST3 : DMAC_LAST_DLAST3_Field := 16#0#; -- Source Last - SLAST4 : LAST_SLAST4_Field := 16#0#; + SLAST4 : DMAC_LAST_SLAST4_Field := 16#0#; -- Destination Last - DLAST4 : LAST_DLAST4_Field := 16#0#; + DLAST4 : DMAC_LAST_DLAST4_Field := 16#0#; -- Source Last - SLAST5 : LAST_SLAST5_Field := 16#0#; + SLAST5 : DMAC_LAST_SLAST5_Field := 16#0#; -- Destination Last - DLAST5 : LAST_DLAST5_Field := 16#0#; + DLAST5 : DMAC_LAST_DLAST5_Field := 16#0#; -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for LAST_Register use record + for DMAC_LAST_Register use record SLAST0 at 0 range 0 .. 0; DLAST0 at 0 range 1 .. 1; SLAST1 at 0 range 2 .. 2; @@ -258,23 +238,16 @@ package ATSAM3X8E.DMAC is Reserved_12_31 at 0 range 12 .. 31; end record; - --------------------- - -- EBCIER_Register -- - --------------------- - - ---------------- - -- EBCIER.BTC -- - ---------------- + -- DMAC_EBCIER_BTC array element + subtype DMAC_EBCIER_BTC_Element is ATSAM3X8E.Bit; - -- EBCIER_BTC array element - subtype EBCIER_BTC_Element is ATSAM3X8E.Bit; - - -- EBCIER_BTC array - type EBCIER_BTC_Field_Array is array (0 .. 5) of EBCIER_BTC_Element + -- DMAC_EBCIER_BTC array + type DMAC_EBCIER_BTC_Field_Array is array (0 .. 5) + of DMAC_EBCIER_BTC_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIER_BTC - type EBCIER_BTC_Field + -- Type definition for DMAC_EBCIER_BTC + type DMAC_EBCIER_BTC_Field (As_Array : Boolean := False) is record case As_Array is @@ -283,29 +256,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- BTC as an array - Arr : EBCIER_BTC_Field_Array; + Arr : DMAC_EBCIER_BTC_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIER_BTC_Field use record + for DMAC_EBCIER_BTC_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - ----------------- - -- EBCIER.CBTC -- - ----------------- - - -- EBCIER_CBTC array element - subtype EBCIER_CBTC_Element is ATSAM3X8E.Bit; + -- DMAC_EBCIER_CBTC array element + subtype DMAC_EBCIER_CBTC_Element is ATSAM3X8E.Bit; - -- EBCIER_CBTC array - type EBCIER_CBTC_Field_Array is array (0 .. 5) of EBCIER_CBTC_Element + -- DMAC_EBCIER_CBTC array + type DMAC_EBCIER_CBTC_Field_Array is array (0 .. 5) + of DMAC_EBCIER_CBTC_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIER_CBTC - type EBCIER_CBTC_Field + -- Type definition for DMAC_EBCIER_CBTC + type DMAC_EBCIER_CBTC_Field (As_Array : Boolean := False) is record case As_Array is @@ -314,29 +284,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- CBTC as an array - Arr : EBCIER_CBTC_Field_Array; + Arr : DMAC_EBCIER_CBTC_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIER_CBTC_Field use record + for DMAC_EBCIER_CBTC_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - ---------------- - -- EBCIER.ERR -- - ---------------- + -- DMAC_EBCIER_ERR array element + subtype DMAC_EBCIER_ERR_Element is ATSAM3X8E.Bit; - -- EBCIER_ERR array element - subtype EBCIER_ERR_Element is ATSAM3X8E.Bit; - - -- EBCIER_ERR array - type EBCIER_ERR_Field_Array is array (0 .. 5) of EBCIER_ERR_Element + -- DMAC_EBCIER_ERR array + type DMAC_EBCIER_ERR_Field_Array is array (0 .. 5) + of DMAC_EBCIER_ERR_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIER_ERR - type EBCIER_ERR_Field + -- Type definition for DMAC_EBCIER_ERR + type DMAC_EBCIER_ERR_Field (As_Array : Boolean := False) is record case As_Array is @@ -345,35 +312,38 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- ERR as an array - Arr : EBCIER_ERR_Field_Array; + Arr : DMAC_EBCIER_ERR_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIER_ERR_Field use record + for DMAC_EBCIER_ERR_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; -- DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer -- Transfer Completed Interrupt Enable register. - type EBCIER_Register is record + type DMAC_EBCIER_Register is record -- Write-only. Buffer Transfer Completed [5:0] - BTC : EBCIER_BTC_Field := (As_Array => False, Val => 16#0#); + BTC : DMAC_EBCIER_BTC_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Chained Buffer Transfer Completed [5:0] - CBTC : EBCIER_CBTC_Field := (As_Array => False, Val => 16#0#); + CBTC : DMAC_EBCIER_CBTC_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Access Error [5:0] - ERR : EBCIER_ERR_Field := (As_Array => False, Val => 16#0#); + ERR : DMAC_EBCIER_ERR_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_22_31 : ATSAM3X8E.UInt10 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EBCIER_Register use record + for DMAC_EBCIER_Register use record BTC at 0 range 0 .. 5; Reserved_6_7 at 0 range 6 .. 7; CBTC at 0 range 8 .. 13; @@ -382,23 +352,16 @@ package ATSAM3X8E.DMAC is Reserved_22_31 at 0 range 22 .. 31; end record; - --------------------- - -- EBCIDR_Register -- - --------------------- - - ---------------- - -- EBCIDR.BTC -- - ---------------- - - -- EBCIDR_BTC array element - subtype EBCIDR_BTC_Element is ATSAM3X8E.Bit; + -- DMAC_EBCIDR_BTC array element + subtype DMAC_EBCIDR_BTC_Element is ATSAM3X8E.Bit; - -- EBCIDR_BTC array - type EBCIDR_BTC_Field_Array is array (0 .. 5) of EBCIDR_BTC_Element + -- DMAC_EBCIDR_BTC array + type DMAC_EBCIDR_BTC_Field_Array is array (0 .. 5) + of DMAC_EBCIDR_BTC_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIDR_BTC - type EBCIDR_BTC_Field + -- Type definition for DMAC_EBCIDR_BTC + type DMAC_EBCIDR_BTC_Field (As_Array : Boolean := False) is record case As_Array is @@ -407,29 +370,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- BTC as an array - Arr : EBCIDR_BTC_Field_Array; + Arr : DMAC_EBCIDR_BTC_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIDR_BTC_Field use record + for DMAC_EBCIDR_BTC_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - ----------------- - -- EBCIDR.CBTC -- - ----------------- + -- DMAC_EBCIDR_CBTC array element + subtype DMAC_EBCIDR_CBTC_Element is ATSAM3X8E.Bit; - -- EBCIDR_CBTC array element - subtype EBCIDR_CBTC_Element is ATSAM3X8E.Bit; - - -- EBCIDR_CBTC array - type EBCIDR_CBTC_Field_Array is array (0 .. 5) of EBCIDR_CBTC_Element + -- DMAC_EBCIDR_CBTC array + type DMAC_EBCIDR_CBTC_Field_Array is array (0 .. 5) + of DMAC_EBCIDR_CBTC_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIDR_CBTC - type EBCIDR_CBTC_Field + -- Type definition for DMAC_EBCIDR_CBTC + type DMAC_EBCIDR_CBTC_Field (As_Array : Boolean := False) is record case As_Array is @@ -438,29 +398,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- CBTC as an array - Arr : EBCIDR_CBTC_Field_Array; + Arr : DMAC_EBCIDR_CBTC_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIDR_CBTC_Field use record + for DMAC_EBCIDR_CBTC_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - ---------------- - -- EBCIDR.ERR -- - ---------------- - - -- EBCIDR_ERR array element - subtype EBCIDR_ERR_Element is ATSAM3X8E.Bit; + -- DMAC_EBCIDR_ERR array element + subtype DMAC_EBCIDR_ERR_Element is ATSAM3X8E.Bit; - -- EBCIDR_ERR array - type EBCIDR_ERR_Field_Array is array (0 .. 5) of EBCIDR_ERR_Element + -- DMAC_EBCIDR_ERR array + type DMAC_EBCIDR_ERR_Field_Array is array (0 .. 5) + of DMAC_EBCIDR_ERR_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIDR_ERR - type EBCIDR_ERR_Field + -- Type definition for DMAC_EBCIDR_ERR + type DMAC_EBCIDR_ERR_Field (As_Array : Boolean := False) is record case As_Array is @@ -469,35 +426,38 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- ERR as an array - Arr : EBCIDR_ERR_Field_Array; + Arr : DMAC_EBCIDR_ERR_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIDR_ERR_Field use record + for DMAC_EBCIDR_ERR_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; -- DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer -- Transfer Completed Interrupt Disable register. - type EBCIDR_Register is record + type DMAC_EBCIDR_Register is record -- Write-only. Buffer Transfer Completed [5:0] - BTC : EBCIDR_BTC_Field := (As_Array => False, Val => 16#0#); + BTC : DMAC_EBCIDR_BTC_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Chained Buffer Transfer Completed [5:0] - CBTC : EBCIDR_CBTC_Field := (As_Array => False, Val => 16#0#); + CBTC : DMAC_EBCIDR_CBTC_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Access Error [5:0] - ERR : EBCIDR_ERR_Field := (As_Array => False, Val => 16#0#); + ERR : DMAC_EBCIDR_ERR_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_22_31 : ATSAM3X8E.UInt10 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EBCIDR_Register use record + for DMAC_EBCIDR_Register use record BTC at 0 range 0 .. 5; Reserved_6_7 at 0 range 6 .. 7; CBTC at 0 range 8 .. 13; @@ -506,23 +466,16 @@ package ATSAM3X8E.DMAC is Reserved_22_31 at 0 range 22 .. 31; end record; - --------------------- - -- EBCIMR_Register -- - --------------------- + -- DMAC_EBCIMR_BTC array element + subtype DMAC_EBCIMR_BTC_Element is ATSAM3X8E.Bit; - ---------------- - -- EBCIMR.BTC -- - ---------------- - - -- EBCIMR_BTC array element - subtype EBCIMR_BTC_Element is ATSAM3X8E.Bit; - - -- EBCIMR_BTC array - type EBCIMR_BTC_Field_Array is array (0 .. 5) of EBCIMR_BTC_Element + -- DMAC_EBCIMR_BTC array + type DMAC_EBCIMR_BTC_Field_Array is array (0 .. 5) + of DMAC_EBCIMR_BTC_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIMR_BTC - type EBCIMR_BTC_Field + -- Type definition for DMAC_EBCIMR_BTC + type DMAC_EBCIMR_BTC_Field (As_Array : Boolean := False) is record case As_Array is @@ -531,29 +484,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- BTC as an array - Arr : EBCIMR_BTC_Field_Array; + Arr : DMAC_EBCIMR_BTC_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIMR_BTC_Field use record + for DMAC_EBCIMR_BTC_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - ----------------- - -- EBCIMR.CBTC -- - ----------------- + -- DMAC_EBCIMR_CBTC array element + subtype DMAC_EBCIMR_CBTC_Element is ATSAM3X8E.Bit; - -- EBCIMR_CBTC array element - subtype EBCIMR_CBTC_Element is ATSAM3X8E.Bit; - - -- EBCIMR_CBTC array - type EBCIMR_CBTC_Field_Array is array (0 .. 5) of EBCIMR_CBTC_Element + -- DMAC_EBCIMR_CBTC array + type DMAC_EBCIMR_CBTC_Field_Array is array (0 .. 5) + of DMAC_EBCIMR_CBTC_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIMR_CBTC - type EBCIMR_CBTC_Field + -- Type definition for DMAC_EBCIMR_CBTC + type DMAC_EBCIMR_CBTC_Field (As_Array : Boolean := False) is record case As_Array is @@ -562,29 +512,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- CBTC as an array - Arr : EBCIMR_CBTC_Field_Array; + Arr : DMAC_EBCIMR_CBTC_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIMR_CBTC_Field use record + for DMAC_EBCIMR_CBTC_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - ---------------- - -- EBCIMR.ERR -- - ---------------- - - -- EBCIMR_ERR array element - subtype EBCIMR_ERR_Element is ATSAM3X8E.Bit; + -- DMAC_EBCIMR_ERR array element + subtype DMAC_EBCIMR_ERR_Element is ATSAM3X8E.Bit; - -- EBCIMR_ERR array - type EBCIMR_ERR_Field_Array is array (0 .. 5) of EBCIMR_ERR_Element + -- DMAC_EBCIMR_ERR array + type DMAC_EBCIMR_ERR_Field_Array is array (0 .. 5) + of DMAC_EBCIMR_ERR_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCIMR_ERR - type EBCIMR_ERR_Field + -- Type definition for DMAC_EBCIMR_ERR + type DMAC_EBCIMR_ERR_Field (As_Array : Boolean := False) is record case As_Array is @@ -593,35 +540,35 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- ERR as an array - Arr : EBCIMR_ERR_Field_Array; + Arr : DMAC_EBCIMR_ERR_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCIMR_ERR_Field use record + for DMAC_EBCIMR_ERR_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; -- DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer -- transfer completed Mask Register. - type EBCIMR_Register is record + type DMAC_EBCIMR_Register is record -- Read-only. Buffer Transfer Completed [5:0] - BTC : EBCIMR_BTC_Field := (As_Array => False, Val => 16#0#); + BTC : DMAC_EBCIMR_BTC_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. Chained Buffer Transfer Completed [5:0] - CBTC : EBCIMR_CBTC_Field := (As_Array => False, Val => 16#0#); + CBTC : DMAC_EBCIMR_CBTC_Field; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2; -- Read-only. Access Error [5:0] - ERR : EBCIMR_ERR_Field := (As_Array => False, Val => 16#0#); + ERR : DMAC_EBCIMR_ERR_Field; -- unspecified Reserved_22_31 : ATSAM3X8E.UInt10; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EBCIMR_Register use record + for DMAC_EBCIMR_Register use record BTC at 0 range 0 .. 5; Reserved_6_7 at 0 range 6 .. 7; CBTC at 0 range 8 .. 13; @@ -630,23 +577,16 @@ package ATSAM3X8E.DMAC is Reserved_22_31 at 0 range 22 .. 31; end record; - --------------------- - -- EBCISR_Register -- - --------------------- - - ---------------- - -- EBCISR.BTC -- - ---------------- - - -- EBCISR_BTC array element - subtype EBCISR_BTC_Element is ATSAM3X8E.Bit; + -- DMAC_EBCISR_BTC array element + subtype DMAC_EBCISR_BTC_Element is ATSAM3X8E.Bit; - -- EBCISR_BTC array - type EBCISR_BTC_Field_Array is array (0 .. 5) of EBCISR_BTC_Element + -- DMAC_EBCISR_BTC array + type DMAC_EBCISR_BTC_Field_Array is array (0 .. 5) + of DMAC_EBCISR_BTC_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCISR_BTC - type EBCISR_BTC_Field + -- Type definition for DMAC_EBCISR_BTC + type DMAC_EBCISR_BTC_Field (As_Array : Boolean := False) is record case As_Array is @@ -655,29 +595,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- BTC as an array - Arr : EBCISR_BTC_Field_Array; + Arr : DMAC_EBCISR_BTC_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCISR_BTC_Field use record + for DMAC_EBCISR_BTC_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - ----------------- - -- EBCISR.CBTC -- - ----------------- - - -- EBCISR_CBTC array element - subtype EBCISR_CBTC_Element is ATSAM3X8E.Bit; + -- DMAC_EBCISR_CBTC array element + subtype DMAC_EBCISR_CBTC_Element is ATSAM3X8E.Bit; - -- EBCISR_CBTC array - type EBCISR_CBTC_Field_Array is array (0 .. 5) of EBCISR_CBTC_Element + -- DMAC_EBCISR_CBTC array + type DMAC_EBCISR_CBTC_Field_Array is array (0 .. 5) + of DMAC_EBCISR_CBTC_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCISR_CBTC - type EBCISR_CBTC_Field + -- Type definition for DMAC_EBCISR_CBTC + type DMAC_EBCISR_CBTC_Field (As_Array : Boolean := False) is record case As_Array is @@ -686,29 +623,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- CBTC as an array - Arr : EBCISR_CBTC_Field_Array; + Arr : DMAC_EBCISR_CBTC_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCISR_CBTC_Field use record + for DMAC_EBCISR_CBTC_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - ---------------- - -- EBCISR.ERR -- - ---------------- + -- DMAC_EBCISR_ERR array element + subtype DMAC_EBCISR_ERR_Element is ATSAM3X8E.Bit; - -- EBCISR_ERR array element - subtype EBCISR_ERR_Element is ATSAM3X8E.Bit; - - -- EBCISR_ERR array - type EBCISR_ERR_Field_Array is array (0 .. 5) of EBCISR_ERR_Element + -- DMAC_EBCISR_ERR array + type DMAC_EBCISR_ERR_Field_Array is array (0 .. 5) + of DMAC_EBCISR_ERR_Element with Component_Size => 1, Size => 6; - -- Type definition for EBCISR_ERR - type EBCISR_ERR_Field + -- Type definition for DMAC_EBCISR_ERR + type DMAC_EBCISR_ERR_Field (As_Array : Boolean := False) is record case As_Array is @@ -717,35 +651,35 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- ERR as an array - Arr : EBCISR_ERR_Field_Array; + Arr : DMAC_EBCISR_ERR_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for EBCISR_ERR_Field use record + for DMAC_EBCISR_ERR_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; -- DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer -- transfer completed Status Register. - type EBCISR_Register is record + type DMAC_EBCISR_Register is record -- Read-only. Buffer Transfer Completed [5:0] - BTC : EBCISR_BTC_Field := (As_Array => False, Val => 16#0#); + BTC : DMAC_EBCISR_BTC_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. Chained Buffer Transfer Completed [5:0] - CBTC : EBCISR_CBTC_Field := (As_Array => False, Val => 16#0#); + CBTC : DMAC_EBCISR_CBTC_Field; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2; -- Read-only. Access Error [5:0] - ERR : EBCISR_ERR_Field := (As_Array => False, Val => 16#0#); + ERR : DMAC_EBCISR_ERR_Field; -- unspecified Reserved_22_31 : ATSAM3X8E.UInt10; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EBCISR_Register use record + for DMAC_EBCISR_Register use record BTC at 0 range 0 .. 5; Reserved_6_7 at 0 range 6 .. 7; CBTC at 0 range 8 .. 13; @@ -754,23 +688,15 @@ package ATSAM3X8E.DMAC is Reserved_22_31 at 0 range 22 .. 31; end record; - ------------------- - -- CHER_Register -- - ------------------- - - -------------- - -- CHER.ENA -- - -------------- + -- DMAC_CHER_ENA array element + subtype DMAC_CHER_ENA_Element is ATSAM3X8E.Bit; - -- CHER_ENA array element - subtype CHER_ENA_Element is ATSAM3X8E.Bit; - - -- CHER_ENA array - type CHER_ENA_Field_Array is array (0 .. 5) of CHER_ENA_Element + -- DMAC_CHER_ENA array + type DMAC_CHER_ENA_Field_Array is array (0 .. 5) of DMAC_CHER_ENA_Element with Component_Size => 1, Size => 6; - -- Type definition for CHER_ENA - type CHER_ENA_Field + -- Type definition for DMAC_CHER_ENA + type DMAC_CHER_ENA_Field (As_Array : Boolean := False) is record case As_Array is @@ -779,29 +705,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- ENA as an array - Arr : CHER_ENA_Field_Array; + Arr : DMAC_CHER_ENA_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHER_ENA_Field use record + for DMAC_CHER_ENA_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - --------------- - -- CHER.SUSP -- - --------------- - - -- CHER_SUSP array element - subtype CHER_SUSP_Element is ATSAM3X8E.Bit; + -- DMAC_CHER_SUSP array element + subtype DMAC_CHER_SUSP_Element is ATSAM3X8E.Bit; - -- CHER_SUSP array - type CHER_SUSP_Field_Array is array (0 .. 5) of CHER_SUSP_Element + -- DMAC_CHER_SUSP array + type DMAC_CHER_SUSP_Field_Array is array (0 .. 5) + of DMAC_CHER_SUSP_Element with Component_Size => 1, Size => 6; - -- Type definition for CHER_SUSP - type CHER_SUSP_Field + -- Type definition for DMAC_CHER_SUSP + type DMAC_CHER_SUSP_Field (As_Array : Boolean := False) is record case As_Array is @@ -810,29 +733,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- SUSP as an array - Arr : CHER_SUSP_Field_Array; + Arr : DMAC_CHER_SUSP_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHER_SUSP_Field use record + for DMAC_CHER_SUSP_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - --------------- - -- CHER.KEEP -- - --------------- + -- DMAC_CHER_KEEP array element + subtype DMAC_CHER_KEEP_Element is ATSAM3X8E.Bit; - -- CHER_KEEP array element - subtype CHER_KEEP_Element is ATSAM3X8E.Bit; - - -- CHER_KEEP array - type CHER_KEEP_Field_Array is array (0 .. 5) of CHER_KEEP_Element + -- DMAC_CHER_KEEP array + type DMAC_CHER_KEEP_Field_Array is array (0 .. 5) + of DMAC_CHER_KEEP_Element with Component_Size => 1, Size => 6; - -- Type definition for CHER_KEEP - type CHER_KEEP_Field + -- Type definition for DMAC_CHER_KEEP + type DMAC_CHER_KEEP_Field (As_Array : Boolean := False) is record case As_Array is @@ -841,34 +761,37 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- KEEP as an array - Arr : CHER_KEEP_Field_Array; + Arr : DMAC_CHER_KEEP_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHER_KEEP_Field use record + for DMAC_CHER_KEEP_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; -- DMAC Channel Handler Enable Register - type CHER_Register is record + type DMAC_CHER_Register is record -- Write-only. Enable [5:0] - ENA : CHER_ENA_Field := (As_Array => False, Val => 16#0#); + ENA : DMAC_CHER_ENA_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Suspend [5:0] - SUSP : CHER_SUSP_Field := (As_Array => False, Val => 16#0#); + SUSP : DMAC_CHER_SUSP_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_14_23 : ATSAM3X8E.UInt10 := 16#0#; -- Write-only. Keep on [5:0] - KEEP : CHER_KEEP_Field := (As_Array => False, Val => 16#0#); + KEEP : DMAC_CHER_KEEP_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHER_Register use record + for DMAC_CHER_Register use record ENA at 0 range 0 .. 5; Reserved_6_7 at 0 range 6 .. 7; SUSP at 0 range 8 .. 13; @@ -877,23 +800,15 @@ package ATSAM3X8E.DMAC is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- CHDR_Register -- - ------------------- - - -------------- - -- CHDR.DIS -- - -------------- + -- DMAC_CHDR_DIS array element + subtype DMAC_CHDR_DIS_Element is ATSAM3X8E.Bit; - -- CHDR_DIS array element - subtype CHDR_DIS_Element is ATSAM3X8E.Bit; - - -- CHDR_DIS array - type CHDR_DIS_Field_Array is array (0 .. 5) of CHDR_DIS_Element + -- DMAC_CHDR_DIS array + type DMAC_CHDR_DIS_Field_Array is array (0 .. 5) of DMAC_CHDR_DIS_Element with Component_Size => 1, Size => 6; - -- Type definition for CHDR_DIS - type CHDR_DIS_Field + -- Type definition for DMAC_CHDR_DIS + type DMAC_CHDR_DIS_Field (As_Array : Boolean := False) is record case As_Array is @@ -902,29 +817,25 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- DIS as an array - Arr : CHDR_DIS_Field_Array; + Arr : DMAC_CHDR_DIS_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHDR_DIS_Field use record + for DMAC_CHDR_DIS_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - -------------- - -- CHDR.RES -- - -------------- - - -- CHDR_RES array element - subtype CHDR_RES_Element is ATSAM3X8E.Bit; + -- DMAC_CHDR_RES array element + subtype DMAC_CHDR_RES_Element is ATSAM3X8E.Bit; - -- CHDR_RES array - type CHDR_RES_Field_Array is array (0 .. 5) of CHDR_RES_Element + -- DMAC_CHDR_RES array + type DMAC_CHDR_RES_Field_Array is array (0 .. 5) of DMAC_CHDR_RES_Element with Component_Size => 1, Size => 6; - -- Type definition for CHDR_RES - type CHDR_RES_Field + -- Type definition for DMAC_CHDR_RES + type DMAC_CHDR_RES_Field (As_Array : Boolean := False) is record case As_Array is @@ -933,53 +844,47 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- RES as an array - Arr : CHDR_RES_Field_Array; + Arr : DMAC_CHDR_RES_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHDR_RES_Field use record + for DMAC_CHDR_RES_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; -- DMAC Channel Handler Disable Register - type CHDR_Register is record + type DMAC_CHDR_Register is record -- Write-only. Disable [5:0] - DIS : CHDR_DIS_Field := (As_Array => False, Val => 16#0#); + DIS : DMAC_CHDR_DIS_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Resume [5:0] - RES : CHDR_RES_Field := (As_Array => False, Val => 16#0#); + RES : DMAC_CHDR_RES_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHDR_Register use record + for DMAC_CHDR_Register use record DIS at 0 range 0 .. 5; Reserved_6_7 at 0 range 6 .. 7; RES at 0 range 8 .. 13; Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------- - -- CHSR_Register -- - ------------------- + -- DMAC_CHSR_ENA array element + subtype DMAC_CHSR_ENA_Element is ATSAM3X8E.Bit; - -------------- - -- CHSR.ENA -- - -------------- - - -- CHSR_ENA array element - subtype CHSR_ENA_Element is ATSAM3X8E.Bit; - - -- CHSR_ENA array - type CHSR_ENA_Field_Array is array (0 .. 5) of CHSR_ENA_Element + -- DMAC_CHSR_ENA array + type DMAC_CHSR_ENA_Field_Array is array (0 .. 5) of DMAC_CHSR_ENA_Element with Component_Size => 1, Size => 6; - -- Type definition for CHSR_ENA - type CHSR_ENA_Field + -- Type definition for DMAC_CHSR_ENA + type DMAC_CHSR_ENA_Field (As_Array : Boolean := False) is record case As_Array is @@ -988,29 +893,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- ENA as an array - Arr : CHSR_ENA_Field_Array; + Arr : DMAC_CHSR_ENA_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHSR_ENA_Field use record + for DMAC_CHSR_ENA_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - --------------- - -- CHSR.SUSP -- - --------------- - - -- CHSR_SUSP array element - subtype CHSR_SUSP_Element is ATSAM3X8E.Bit; + -- DMAC_CHSR_SUSP array element + subtype DMAC_CHSR_SUSP_Element is ATSAM3X8E.Bit; - -- CHSR_SUSP array - type CHSR_SUSP_Field_Array is array (0 .. 5) of CHSR_SUSP_Element + -- DMAC_CHSR_SUSP array + type DMAC_CHSR_SUSP_Field_Array is array (0 .. 5) + of DMAC_CHSR_SUSP_Element with Component_Size => 1, Size => 6; - -- Type definition for CHSR_SUSP - type CHSR_SUSP_Field + -- Type definition for DMAC_CHSR_SUSP + type DMAC_CHSR_SUSP_Field (As_Array : Boolean := False) is record case As_Array is @@ -1019,29 +921,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- SUSP as an array - Arr : CHSR_SUSP_Field_Array; + Arr : DMAC_CHSR_SUSP_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHSR_SUSP_Field use record + for DMAC_CHSR_SUSP_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - --------------- - -- CHSR.EMPT -- - --------------- + -- DMAC_CHSR_EMPT array element + subtype DMAC_CHSR_EMPT_Element is ATSAM3X8E.Bit; - -- CHSR_EMPT array element - subtype CHSR_EMPT_Element is ATSAM3X8E.Bit; - - -- CHSR_EMPT array - type CHSR_EMPT_Field_Array is array (0 .. 5) of CHSR_EMPT_Element + -- DMAC_CHSR_EMPT array + type DMAC_CHSR_EMPT_Field_Array is array (0 .. 5) + of DMAC_CHSR_EMPT_Element with Component_Size => 1, Size => 6; - -- Type definition for CHSR_EMPT - type CHSR_EMPT_Field + -- Type definition for DMAC_CHSR_EMPT + type DMAC_CHSR_EMPT_Field (As_Array : Boolean := False) is record case As_Array is @@ -1050,29 +949,26 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- EMPT as an array - Arr : CHSR_EMPT_Field_Array; + Arr : DMAC_CHSR_EMPT_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHSR_EMPT_Field use record + for DMAC_CHSR_EMPT_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - --------------- - -- CHSR.STAL -- - --------------- - - -- CHSR_STAL array element - subtype CHSR_STAL_Element is ATSAM3X8E.Bit; + -- DMAC_CHSR_STAL array element + subtype DMAC_CHSR_STAL_Element is ATSAM3X8E.Bit; - -- CHSR_STAL array - type CHSR_STAL_Field_Array is array (0 .. 5) of CHSR_STAL_Element + -- DMAC_CHSR_STAL array + type DMAC_CHSR_STAL_Field_Array is array (0 .. 5) + of DMAC_CHSR_STAL_Element with Component_Size => 1, Size => 6; - -- Type definition for CHSR_STAL - type CHSR_STAL_Field + -- Type definition for DMAC_CHSR_STAL + type DMAC_CHSR_STAL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1081,38 +977,38 @@ package ATSAM3X8E.DMAC is Val : ATSAM3X8E.UInt6; when True => -- STAL as an array - Arr : CHSR_STAL_Field_Array; + Arr : DMAC_CHSR_STAL_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for CHSR_STAL_Field use record + for DMAC_CHSR_STAL_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; -- DMAC Channel Handler Status Register - type CHSR_Register is record + type DMAC_CHSR_Register is record -- Read-only. Enable [5:0] - ENA : CHSR_ENA_Field := (As_Array => False, Val => 16#0#); + ENA : DMAC_CHSR_ENA_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. Suspend [5:0] - SUSP : CHSR_SUSP_Field := (As_Array => False, Val => 16#0#); + SUSP : DMAC_CHSR_SUSP_Field; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2; -- Read-only. Empty [5:0] - EMPT : CHSR_EMPT_Field := (As_Array => False, Val => 16#1#); + EMPT : DMAC_CHSR_EMPT_Field; -- unspecified Reserved_22_23 : ATSAM3X8E.UInt2; -- Read-only. Stalled [5:0] - STAL : CHSR_STAL_Field := (As_Array => False, Val => 16#0#); + STAL : DMAC_CHSR_STAL_Field; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CHSR_Register use record + for DMAC_CHSR_Register use record ENA at 0 range 0 .. 5; Reserved_6_7 at 0 range 6 .. 7; SUSP at 0 range 8 .. 13; @@ -1123,36 +1019,27 @@ package ATSAM3X8E.DMAC is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- DSCR_Register -- - ------------------- - - subtype DSCR0_DSCR_Field is ATSAM3X8E.UInt30; + subtype DSCR_DSCR_Field is ATSAM3X8E.UInt30; -- DMAC Channel Descriptor Address Register (ch_num = 0) type DSCR_Register is record -- unspecified Reserved_0_1 : ATSAM3X8E.UInt2 := 16#0#; -- Buffer Transfer Descriptor Address - DSCR : DSCR0_DSCR_Field := 16#0#; + DSCR : DSCR_DSCR_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DSCR_Register use record Reserved_0_1 at 0 range 0 .. 1; DSCR at 0 range 2 .. 31; end record; - -------------------- - -- CTRLA_Register -- - -------------------- - - subtype CTRLA0_BTSIZE_Field is ATSAM3X8E.Short; + subtype CTRLA_BTSIZE_Field is ATSAM3X8E.UInt16; -- Source Chunk Transfer Size. - type SCSIZE_Field is - ( - -- 1 data transferred + type CTRLA0_SCSIZE_Field is + (-- 1 data transferred Chk_1, -- 4 data transferred Chk_4, @@ -1169,7 +1056,7 @@ package ATSAM3X8E.DMAC is -- 256 data transferred Chk_256) with Size => 3; - for SCSIZE_Field use + for CTRLA0_SCSIZE_Field use (Chk_1 => 0, Chk_4 => 1, Chk_8 => 2, @@ -1180,9 +1067,8 @@ package ATSAM3X8E.DMAC is Chk_256 => 7); -- Destination Chunk Transfer Size - type DCSIZE_Field is - ( - -- 1 data transferred + type CTRLA0_DCSIZE_Field is + (-- 1 data transferred Chk_1, -- 4 data transferred Chk_4, @@ -1199,7 +1085,7 @@ package ATSAM3X8E.DMAC is -- 256 data transferred Chk_256) with Size => 3; - for DCSIZE_Field use + for CTRLA0_DCSIZE_Field use (Chk_1 => 0, Chk_4 => 1, Chk_8 => 2, @@ -1210,60 +1096,58 @@ package ATSAM3X8E.DMAC is Chk_256 => 7); -- Transfer Width for the Source - type SRC_WIDTH_Field is - ( - -- the transfer size is set to 8-bit width + type CTRLA0_SRC_WIDTH_Field is + (-- the transfer size is set to 8-bit width Byte, -- the transfer size is set to 16-bit width Half_Word, -- the transfer size is set to 32-bit width Word) with Size => 2; - for SRC_WIDTH_Field use + for CTRLA0_SRC_WIDTH_Field use (Byte => 0, Half_Word => 1, Word => 2); -- Transfer Width for the Destination - type DST_WIDTH_Field is - ( - -- the transfer size is set to 8-bit width + type CTRLA0_DST_WIDTH_Field is + (-- the transfer size is set to 8-bit width Byte, -- the transfer size is set to 16-bit width Half_Word, -- the transfer size is set to 32-bit width Word) with Size => 2; - for DST_WIDTH_Field use + for CTRLA0_DST_WIDTH_Field use (Byte => 0, Half_Word => 1, Word => 2); - subtype CTRLA0_DONE_Field is ATSAM3X8E.Bit; + subtype CTRLA_DONE_Field is ATSAM3X8E.Bit; -- DMAC Channel Control A Register (ch_num = 0) type CTRLA_Register is record -- Buffer Transfer Size - BTSIZE : CTRLA0_BTSIZE_Field := 16#0#; + BTSIZE : CTRLA_BTSIZE_Field := 16#0#; -- Source Chunk Transfer Size. - SCSIZE : SCSIZE_Field := Chk_1; + SCSIZE : CTRLA0_SCSIZE_Field := ATSAM3X8E.DMAC.Chk_1; -- unspecified Reserved_19_19 : ATSAM3X8E.Bit := 16#0#; -- Destination Chunk Transfer Size - DCSIZE : DCSIZE_Field := Chk_1; + DCSIZE : CTRLA0_DCSIZE_Field := ATSAM3X8E.DMAC.Chk_1; -- unspecified Reserved_23_23 : ATSAM3X8E.Bit := 16#0#; -- Transfer Width for the Source - SRC_WIDTH : SRC_WIDTH_Field := Byte; + SRC_WIDTH : CTRLA0_SRC_WIDTH_Field := ATSAM3X8E.DMAC.Byte; -- unspecified Reserved_26_27 : ATSAM3X8E.UInt2 := 16#0#; -- Transfer Width for the Destination - DST_WIDTH : DST_WIDTH_Field := Byte; + DST_WIDTH : CTRLA0_DST_WIDTH_Field := ATSAM3X8E.DMAC.Byte; -- unspecified Reserved_30_30 : ATSAM3X8E.Bit := 16#0#; - DONE : CTRLA0_DONE_Field := 16#0#; + DONE : CTRLA_DONE_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CTRLA_Register use record BTSIZE at 0 range 0 .. 15; @@ -1278,40 +1162,32 @@ package ATSAM3X8E.DMAC is DONE at 0 range 31 .. 31; end record; - -------------------- - -- CTRLB_Register -- - -------------------- - -- Source Address Descriptor - type SRC_DSCR_Field is - ( - -- Source address is updated when the descriptor is fetched from the - -- memory. + type CTRLB0_SRC_DSCR_Field is + (-- Source address is updated when the descriptor is fetched from the memory. Fetch_From_Mem, -- Buffer Descriptor Fetch operation is disabled for the source. Fetch_Disable) with Size => 1; - for SRC_DSCR_Field use + for CTRLB0_SRC_DSCR_Field use (Fetch_From_Mem => 0, Fetch_Disable => 1); -- Destination Address Descriptor - type DST_DSCR_Field is - ( - -- Destination address is updated when the descriptor is fetched from - -- the memory. + type CTRLB0_DST_DSCR_Field is + (-- Destination address is updated when the descriptor is fetched from the +-- memory. Fetch_From_Mem, -- Buffer Descriptor Fetch operation is disabled for the destination. Fetch_Disable) with Size => 1; - for DST_DSCR_Field use + for CTRLB0_DST_DSCR_Field use (Fetch_From_Mem => 0, Fetch_Disable => 1); -- Flow Control - type FC_Field is - ( - -- Memory-to-Memory Transfer DMAC is flow controller + type CTRLB0_FC_Field is + (-- Memory-to-Memory Transfer DMAC is flow controller Mem2Mem_Dma_Fc, -- Memory-to-Peripheral Transfer DMAC is flow controller Mem2Per_Dma_Fc, @@ -1320,67 +1196,65 @@ package ATSAM3X8E.DMAC is -- Peripheral-to-Peripheral Transfer DMAC is flow controller Per2Per_Dma_Fc) with Size => 3; - for FC_Field use + for CTRLB0_FC_Field use (Mem2Mem_Dma_Fc => 0, Mem2Per_Dma_Fc => 1, Per2Mem_Dma_Fc => 2, Per2Per_Dma_Fc => 3); -- Incrementing, Decrementing or Fixed Address for the Source - type SRC_INCR_Field is - ( - -- The source address is incremented + type CTRLB0_SRC_INCR_Field is + (-- The source address is incremented Incrementing, -- The source address is decremented Decrementing, -- The source address remains unchanged Fixed) with Size => 2; - for SRC_INCR_Field use + for CTRLB0_SRC_INCR_Field use (Incrementing => 0, Decrementing => 1, Fixed => 2); -- Incrementing, Decrementing or Fixed Address for the Destination - type DST_INCR_Field is - ( - -- The destination address is incremented + type CTRLB0_DST_INCR_Field is + (-- The destination address is incremented Incrementing, -- The destination address is decremented Decrementing, -- The destination address remains unchanged Fixed) with Size => 2; - for DST_INCR_Field use + for CTRLB0_DST_INCR_Field use (Incrementing => 0, Decrementing => 1, Fixed => 2); - subtype CTRLB0_IEN_Field is ATSAM3X8E.Bit; + subtype CTRLB_IEN_Field is ATSAM3X8E.Bit; -- DMAC Channel Control B Register (ch_num = 0) type CTRLB_Register is record -- unspecified - Reserved_0_15 : ATSAM3X8E.Short := 16#0#; + Reserved_0_15 : ATSAM3X8E.UInt16 := 16#0#; -- Source Address Descriptor - SRC_DSCR : SRC_DSCR_Field := Fetch_From_Mem; + SRC_DSCR : CTRLB0_SRC_DSCR_Field := ATSAM3X8E.DMAC.Fetch_From_Mem; -- unspecified Reserved_17_19 : ATSAM3X8E.UInt3 := 16#0#; -- Destination Address Descriptor - DST_DSCR : DST_DSCR_Field := Fetch_From_Mem; + DST_DSCR : CTRLB0_DST_DSCR_Field := ATSAM3X8E.DMAC.Fetch_From_Mem; -- Flow Control - FC : FC_Field := Mem2Mem_Dma_Fc; + FC : CTRLB0_FC_Field := ATSAM3X8E.DMAC.Mem2Mem_Dma_Fc; -- Incrementing, Decrementing or Fixed Address for the Source - SRC_INCR : SRC_INCR_Field := Incrementing; + SRC_INCR : CTRLB0_SRC_INCR_Field := ATSAM3X8E.DMAC.Incrementing; -- unspecified Reserved_26_27 : ATSAM3X8E.UInt2 := 16#0#; -- Incrementing, Decrementing or Fixed Address for the Destination - DST_INCR : DST_INCR_Field := Incrementing; - IEN : CTRLB0_IEN_Field := 16#0#; + DST_INCR : CTRLB0_DST_INCR_Field := ATSAM3X8E.DMAC.Incrementing; + IEN : CTRLB_IEN_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CTRLB_Register use record Reserved_0_15 at 0 range 0 .. 15; @@ -1395,102 +1269,91 @@ package ATSAM3X8E.DMAC is Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------ - -- CFG_Register -- - ------------------ - - subtype CFG0_SRC_PER_Field is ATSAM3X8E.UInt4; - subtype CFG0_DST_PER_Field is ATSAM3X8E.UInt4; + subtype CFG_SRC_PER_Field is ATSAM3X8E.UInt4; + subtype CFG_DST_PER_Field is ATSAM3X8E.UInt4; -- Software or Hardware Selection for the Source - type SRC_H2SEL_Field is - ( - -- Software handshaking interface is used to trigger a transfer request. + type CFG0_SRC_H2SEL_Field is + (-- Software handshaking interface is used to trigger a transfer request. Sw, -- Hardware handshaking interface is used to trigger a transfer request. Hw) with Size => 1; - for SRC_H2SEL_Field use + for CFG0_SRC_H2SEL_Field use (Sw => 0, Hw => 1); -- Software or Hardware Selection for the Destination - type DST_H2SEL_Field is - ( - -- Software handshaking interface is used to trigger a transfer request. + type CFG0_DST_H2SEL_Field is + (-- Software handshaking interface is used to trigger a transfer request. Sw, -- Hardware handshaking interface is used to trigger a transfer request. Hw) with Size => 1; - for DST_H2SEL_Field use + for CFG0_DST_H2SEL_Field use (Sw => 0, Hw => 1); -- Stop On Done - type SOD_Field is - ( - -- STOP ON DONE disabled, the descriptor fetch operation ignores DONE - -- Field of CTRLA register. + type CFG0_SOD_Field is + (-- STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of +-- CTRLA register. Disable, - -- STOP ON DONE activated, the DMAC module is automatically disabled if - -- DONE FIELD is set to 1. + -- STOP ON DONE activated, the DMAC module is automatically disabled if DONE +-- FIELD is set to 1. Enable) with Size => 1; - for SOD_Field use + for CFG0_SOD_Field use (Disable => 0, Enable => 1); -- Interface Lock - type LOCK_IF_Field is - ( - -- Interface Lock capability is disabled + type CFG0_LOCK_IF_Field is + (-- Interface Lock capability is disabled Disable, -- Interface Lock capability is enabled Enable) with Size => 1; - for LOCK_IF_Field use + for CFG0_LOCK_IF_Field use (Disable => 0, Enable => 1); -- Bus Lock - type LOCK_B_Field is - ( - -- AHB Bus Locking capability is disabled. + type CFG0_LOCK_B_Field is + (-- AHB Bus Locking capability is disabled. Disable) with Size => 1; - for LOCK_B_Field use + for CFG0_LOCK_B_Field use (Disable => 0); -- Master Interface Arbiter Lock - type LOCK_IF_L_Field is - ( - -- The Master Interface Arbiter is locked by the channel x for a chunk - -- transfer. + type CFG0_LOCK_IF_L_Field is + (-- The Master Interface Arbiter is locked by the channel x for a chunk +-- transfer. Chunk, -- The Master Interface Arbiter is locked by the channel x for a buffer - -- transfer. +-- transfer. Buffer) with Size => 1; - for LOCK_IF_L_Field use + for CFG0_LOCK_IF_L_Field use (Chunk => 0, Buffer => 1); - subtype CFG0_AHB_PROT_Field is ATSAM3X8E.UInt3; + subtype CFG_AHB_PROT_Field is ATSAM3X8E.UInt3; -- FIFO Configuration - type FIFOCFG_Field is - ( - -- The largest defined length AHB burst is performed on the destination - -- AHB interface. + type CFG0_FIFOCFG_Field is + (-- The largest defined length AHB burst is performed on the destination AHB +-- interface. Alap_Cfg, - -- When half FIFO size is available/filled, a source/destination request - -- is serviced. + -- When half FIFO size is available/filled, a source/destination request is +-- serviced. Half_Cfg, - -- When there is enough space/data available to perform a single AHB - -- access, then the request is serviced. + -- When there is enough space/data available to perform a single AHB access, +-- then the request is serviced. Asap_Cfg) with Size => 2; - for FIFOCFG_Field use + for CFG0_FIFOCFG_Field use (Alap_Cfg => 0, Half_Cfg => 1, Asap_Cfg => 2); @@ -1498,41 +1361,41 @@ package ATSAM3X8E.DMAC is -- DMAC Channel Configuration Register (ch_num = 0) type CFG_Register is record -- Source with Peripheral identifier - SRC_PER : CFG0_SRC_PER_Field := 16#0#; + SRC_PER : CFG_SRC_PER_Field := 16#0#; -- Destination with Peripheral identifier - DST_PER : CFG0_DST_PER_Field := 16#0#; + DST_PER : CFG_DST_PER_Field := 16#0#; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit := 16#0#; -- Software or Hardware Selection for the Source - SRC_H2SEL : SRC_H2SEL_Field := Sw; + SRC_H2SEL : CFG0_SRC_H2SEL_Field := ATSAM3X8E.DMAC.Sw; -- unspecified Reserved_10_12 : ATSAM3X8E.UInt3 := 16#0#; -- Software or Hardware Selection for the Destination - DST_H2SEL : DST_H2SEL_Field := Sw; + DST_H2SEL : CFG0_DST_H2SEL_Field := ATSAM3X8E.DMAC.Sw; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Stop On Done - SOD : SOD_Field := Disable; + SOD : CFG0_SOD_Field := ATSAM3X8E.DMAC.Disable; -- unspecified Reserved_17_19 : ATSAM3X8E.UInt3 := 16#0#; -- Interface Lock - LOCK_IF : LOCK_IF_Field := Disable; + LOCK_IF : CFG0_LOCK_IF_Field := ATSAM3X8E.DMAC.Disable; -- Bus Lock - LOCK_B : LOCK_B_Field := Disable; + LOCK_B : CFG0_LOCK_B_Field := ATSAM3X8E.DMAC.Disable; -- Master Interface Arbiter Lock - LOCK_IF_L : LOCK_IF_L_Field := Chunk; + LOCK_IF_L : CFG0_LOCK_IF_L_Field := ATSAM3X8E.DMAC.Chunk; -- unspecified Reserved_23_23 : ATSAM3X8E.Bit := 16#0#; -- AHB Protection - AHB_PROT : CFG0_AHB_PROT_Field := 16#1#; + AHB_PROT : CFG_AHB_PROT_Field := 16#1#; -- unspecified Reserved_27_27 : ATSAM3X8E.Bit := 16#0#; -- FIFO Configuration - FIFOCFG : FIFOCFG_Field := Alap_Cfg; + FIFOCFG : CFG0_FIFOCFG_Field := ATSAM3X8E.DMAC.Alap_Cfg; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CFG_Register use record SRC_PER at 0 range 0 .. 3; @@ -1554,51 +1417,43 @@ package ATSAM3X8E.DMAC is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype DMAC_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype DMAC_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- DMAC Write Protect Mode Register - type WPMR_Register is record + type DMAC_WPMR_Register is record -- Write Protect Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : DMAC_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protect KEY - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : DMAC_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for DMAC_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype WPSR_WPVSRC_Field is ATSAM3X8E.Short; + subtype DMAC_WPSR_WPVS_Field is ATSAM3X8E.Bit; + subtype DMAC_WPSR_WPVSRC_Field is ATSAM3X8E.UInt16; -- DMAC Write Protect Status Register - type WPSR_Register is record + type DMAC_WPSR_Register is record -- Read-only. Write Protect Violation Status - WPVS : WPSR_WPVS_Field := 16#0#; + WPVS : DMAC_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protect Violation Source - WPVSRC : WPSR_WPVSRC_Field := 16#0#; + WPVSRC : DMAC_WPSR_WPVSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for DMAC_WPSR_Register use record WPVS at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPVSRC at 0 range 8 .. 23; @@ -1612,163 +1467,201 @@ package ATSAM3X8E.DMAC is -- DMA Controller type DMAC_Peripheral is record -- DMAC Global Configuration Register - GCFG : GCFG_Register; + GCFG : aliased DMAC_GCFG_Register; + pragma Volatile_Full_Access (GCFG); -- DMAC Enable Register - EN : EN_Register; + EN : aliased DMAC_EN_Register; + pragma Volatile_Full_Access (EN); -- DMAC Software Single Request Register - SREQ : SREQ_Register; + SREQ : aliased DMAC_SREQ_Register; + pragma Volatile_Full_Access (SREQ); -- DMAC Software Chunk Transfer Request Register - CREQ : CREQ_Register; + CREQ : aliased DMAC_CREQ_Register; + pragma Volatile_Full_Access (CREQ); -- DMAC Software Last Transfer Flag Register - LAST : LAST_Register; + LAST : aliased DMAC_LAST_Register; + pragma Volatile_Full_Access (LAST); -- DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer -- Transfer Completed Interrupt Enable register. - EBCIER : EBCIER_Register; + EBCIER : aliased DMAC_EBCIER_Register; + pragma Volatile_Full_Access (EBCIER); -- DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer -- Transfer Completed Interrupt Disable register. - EBCIDR : EBCIDR_Register; + EBCIDR : aliased DMAC_EBCIDR_Register; + pragma Volatile_Full_Access (EBCIDR); -- DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer -- transfer completed Mask Register. - EBCIMR : EBCIMR_Register; + EBCIMR : aliased DMAC_EBCIMR_Register; + pragma Volatile_Full_Access (EBCIMR); -- DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer -- transfer completed Status Register. - EBCISR : EBCISR_Register; + EBCISR : aliased DMAC_EBCISR_Register; + pragma Volatile_Full_Access (EBCISR); -- DMAC Channel Handler Enable Register - CHER : CHER_Register; + CHER : aliased DMAC_CHER_Register; + pragma Volatile_Full_Access (CHER); -- DMAC Channel Handler Disable Register - CHDR : CHDR_Register; + CHDR : aliased DMAC_CHDR_Register; + pragma Volatile_Full_Access (CHDR); -- DMAC Channel Handler Status Register - CHSR : CHSR_Register; + CHSR : aliased DMAC_CHSR_Register; + pragma Volatile_Full_Access (CHSR); -- DMAC Channel Source Address Register (ch_num = 0) - SADDR0 : ATSAM3X8E.Word; + SADDR0 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Destination Address Register (ch_num = 0) - DADDR0 : ATSAM3X8E.Word; + DADDR0 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Descriptor Address Register (ch_num = 0) - DSCR0 : DSCR_Register; + DSCR0 : aliased DSCR_Register; + pragma Volatile_Full_Access (DSCR0); -- DMAC Channel Control A Register (ch_num = 0) - CTRLA0 : CTRLA_Register; + CTRLA0 : aliased CTRLA_Register; + pragma Volatile_Full_Access (CTRLA0); -- DMAC Channel Control B Register (ch_num = 0) - CTRLB0 : CTRLB_Register; + CTRLB0 : aliased CTRLB_Register; + pragma Volatile_Full_Access (CTRLB0); -- DMAC Channel Configuration Register (ch_num = 0) - CFG0 : CFG_Register; + CFG0 : aliased CFG_Register; + pragma Volatile_Full_Access (CFG0); -- DMAC Channel Source Address Register (ch_num = 1) - SADDR1 : ATSAM3X8E.Word; + SADDR1 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Destination Address Register (ch_num = 1) - DADDR1 : ATSAM3X8E.Word; + DADDR1 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Descriptor Address Register (ch_num = 1) - DSCR1 : DSCR_Register; + DSCR1 : aliased DSCR_Register; + pragma Volatile_Full_Access (DSCR1); -- DMAC Channel Control A Register (ch_num = 1) - CTRLA1 : CTRLA_Register; + CTRLA1 : aliased CTRLA_Register; + pragma Volatile_Full_Access (CTRLA1); -- DMAC Channel Control B Register (ch_num = 1) - CTRLB1 : CTRLB_Register; + CTRLB1 : aliased CTRLB_Register; + pragma Volatile_Full_Access (CTRLB1); -- DMAC Channel Configuration Register (ch_num = 1) - CFG1 : CFG_Register; + CFG1 : aliased CFG_Register; + pragma Volatile_Full_Access (CFG1); -- DMAC Channel Source Address Register (ch_num = 2) - SADDR2 : ATSAM3X8E.Word; + SADDR2 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Destination Address Register (ch_num = 2) - DADDR2 : ATSAM3X8E.Word; + DADDR2 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Descriptor Address Register (ch_num = 2) - DSCR2 : DSCR_Register; + DSCR2 : aliased DSCR_Register; + pragma Volatile_Full_Access (DSCR2); -- DMAC Channel Control A Register (ch_num = 2) - CTRLA2 : CTRLA_Register; + CTRLA2 : aliased CTRLA_Register; + pragma Volatile_Full_Access (CTRLA2); -- DMAC Channel Control B Register (ch_num = 2) - CTRLB2 : CTRLB_Register; + CTRLB2 : aliased CTRLB_Register; + pragma Volatile_Full_Access (CTRLB2); -- DMAC Channel Configuration Register (ch_num = 2) - CFG2 : CFG_Register; + CFG2 : aliased CFG_Register; + pragma Volatile_Full_Access (CFG2); -- DMAC Channel Source Address Register (ch_num = 3) - SADDR3 : ATSAM3X8E.Word; + SADDR3 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Destination Address Register (ch_num = 3) - DADDR3 : ATSAM3X8E.Word; + DADDR3 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Descriptor Address Register (ch_num = 3) - DSCR3 : DSCR_Register; + DSCR3 : aliased DSCR_Register; + pragma Volatile_Full_Access (DSCR3); -- DMAC Channel Control A Register (ch_num = 3) - CTRLA3 : CTRLA_Register; + CTRLA3 : aliased CTRLA_Register; + pragma Volatile_Full_Access (CTRLA3); -- DMAC Channel Control B Register (ch_num = 3) - CTRLB3 : CTRLB_Register; + CTRLB3 : aliased CTRLB_Register; + pragma Volatile_Full_Access (CTRLB3); -- DMAC Channel Configuration Register (ch_num = 3) - CFG3 : CFG_Register; + CFG3 : aliased CFG_Register; + pragma Volatile_Full_Access (CFG3); -- DMAC Channel Source Address Register (ch_num = 4) - SADDR4 : ATSAM3X8E.Word; + SADDR4 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Destination Address Register (ch_num = 4) - DADDR4 : ATSAM3X8E.Word; + DADDR4 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Descriptor Address Register (ch_num = 4) - DSCR4 : DSCR_Register; + DSCR4 : aliased DSCR_Register; + pragma Volatile_Full_Access (DSCR4); -- DMAC Channel Control A Register (ch_num = 4) - CTRLA4 : CTRLA_Register; + CTRLA4 : aliased CTRLA_Register; + pragma Volatile_Full_Access (CTRLA4); -- DMAC Channel Control B Register (ch_num = 4) - CTRLB4 : CTRLB_Register; + CTRLB4 : aliased CTRLB_Register; + pragma Volatile_Full_Access (CTRLB4); -- DMAC Channel Configuration Register (ch_num = 4) - CFG4 : CFG_Register; + CFG4 : aliased CFG_Register; + pragma Volatile_Full_Access (CFG4); -- DMAC Channel Source Address Register (ch_num = 5) - SADDR5 : ATSAM3X8E.Word; + SADDR5 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Destination Address Register (ch_num = 5) - DADDR5 : ATSAM3X8E.Word; + DADDR5 : aliased ATSAM3X8E.UInt32; -- DMAC Channel Descriptor Address Register (ch_num = 5) - DSCR5 : DSCR_Register; + DSCR5 : aliased DSCR_Register; + pragma Volatile_Full_Access (DSCR5); -- DMAC Channel Control A Register (ch_num = 5) - CTRLA5 : CTRLA_Register; + CTRLA5 : aliased CTRLA_Register; + pragma Volatile_Full_Access (CTRLA5); -- DMAC Channel Control B Register (ch_num = 5) - CTRLB5 : CTRLB_Register; + CTRLB5 : aliased CTRLB_Register; + pragma Volatile_Full_Access (CTRLB5); -- DMAC Channel Configuration Register (ch_num = 5) - CFG5 : CFG_Register; + CFG5 : aliased CFG_Register; + pragma Volatile_Full_Access (CFG5); -- DMAC Write Protect Mode Register - WPMR : WPMR_Register; + WPMR : aliased DMAC_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- DMAC Write Protect Status Register - WPSR : WPSR_Register; + WPSR : aliased DMAC_WPSR_Register; + pragma Volatile_Full_Access (WPSR); end record with Volatile; for DMAC_Peripheral use record - GCFG at 0 range 0 .. 31; - EN at 4 range 0 .. 31; - SREQ at 8 range 0 .. 31; - CREQ at 12 range 0 .. 31; - LAST at 16 range 0 .. 31; - EBCIER at 24 range 0 .. 31; - EBCIDR at 28 range 0 .. 31; - EBCIMR at 32 range 0 .. 31; - EBCISR at 36 range 0 .. 31; - CHER at 40 range 0 .. 31; - CHDR at 44 range 0 .. 31; - CHSR at 48 range 0 .. 31; - SADDR0 at 60 range 0 .. 31; - DADDR0 at 64 range 0 .. 31; - DSCR0 at 68 range 0 .. 31; - CTRLA0 at 72 range 0 .. 31; - CTRLB0 at 76 range 0 .. 31; - CFG0 at 80 range 0 .. 31; - SADDR1 at 100 range 0 .. 31; - DADDR1 at 104 range 0 .. 31; - DSCR1 at 108 range 0 .. 31; - CTRLA1 at 112 range 0 .. 31; - CTRLB1 at 116 range 0 .. 31; - CFG1 at 120 range 0 .. 31; - SADDR2 at 140 range 0 .. 31; - DADDR2 at 144 range 0 .. 31; - DSCR2 at 148 range 0 .. 31; - CTRLA2 at 152 range 0 .. 31; - CTRLB2 at 156 range 0 .. 31; - CFG2 at 160 range 0 .. 31; - SADDR3 at 180 range 0 .. 31; - DADDR3 at 184 range 0 .. 31; - DSCR3 at 188 range 0 .. 31; - CTRLA3 at 192 range 0 .. 31; - CTRLB3 at 196 range 0 .. 31; - CFG3 at 200 range 0 .. 31; - SADDR4 at 220 range 0 .. 31; - DADDR4 at 224 range 0 .. 31; - DSCR4 at 228 range 0 .. 31; - CTRLA4 at 232 range 0 .. 31; - CTRLB4 at 236 range 0 .. 31; - CFG4 at 240 range 0 .. 31; - SADDR5 at 260 range 0 .. 31; - DADDR5 at 264 range 0 .. 31; - DSCR5 at 268 range 0 .. 31; - CTRLA5 at 272 range 0 .. 31; - CTRLB5 at 276 range 0 .. 31; - CFG5 at 280 range 0 .. 31; - WPMR at 484 range 0 .. 31; - WPSR at 488 range 0 .. 31; + GCFG at 16#0# range 0 .. 31; + EN at 16#4# range 0 .. 31; + SREQ at 16#8# range 0 .. 31; + CREQ at 16#C# range 0 .. 31; + LAST at 16#10# range 0 .. 31; + EBCIER at 16#18# range 0 .. 31; + EBCIDR at 16#1C# range 0 .. 31; + EBCIMR at 16#20# range 0 .. 31; + EBCISR at 16#24# range 0 .. 31; + CHER at 16#28# range 0 .. 31; + CHDR at 16#2C# range 0 .. 31; + CHSR at 16#30# range 0 .. 31; + SADDR0 at 16#3C# range 0 .. 31; + DADDR0 at 16#40# range 0 .. 31; + DSCR0 at 16#44# range 0 .. 31; + CTRLA0 at 16#48# range 0 .. 31; + CTRLB0 at 16#4C# range 0 .. 31; + CFG0 at 16#50# range 0 .. 31; + SADDR1 at 16#64# range 0 .. 31; + DADDR1 at 16#68# range 0 .. 31; + DSCR1 at 16#6C# range 0 .. 31; + CTRLA1 at 16#70# range 0 .. 31; + CTRLB1 at 16#74# range 0 .. 31; + CFG1 at 16#78# range 0 .. 31; + SADDR2 at 16#8C# range 0 .. 31; + DADDR2 at 16#90# range 0 .. 31; + DSCR2 at 16#94# range 0 .. 31; + CTRLA2 at 16#98# range 0 .. 31; + CTRLB2 at 16#9C# range 0 .. 31; + CFG2 at 16#A0# range 0 .. 31; + SADDR3 at 16#B4# range 0 .. 31; + DADDR3 at 16#B8# range 0 .. 31; + DSCR3 at 16#BC# range 0 .. 31; + CTRLA3 at 16#C0# range 0 .. 31; + CTRLB3 at 16#C4# range 0 .. 31; + CFG3 at 16#C8# range 0 .. 31; + SADDR4 at 16#DC# range 0 .. 31; + DADDR4 at 16#E0# range 0 .. 31; + DSCR4 at 16#E4# range 0 .. 31; + CTRLA4 at 16#E8# range 0 .. 31; + CTRLB4 at 16#EC# range 0 .. 31; + CFG4 at 16#F0# range 0 .. 31; + SADDR5 at 16#104# range 0 .. 31; + DADDR5 at 16#108# range 0 .. 31; + DSCR5 at 16#10C# range 0 .. 31; + CTRLA5 at 16#110# range 0 .. 31; + CTRLB5 at 16#114# range 0 .. 31; + CFG5 at 16#118# range 0 .. 31; + WPMR at 16#1E4# range 0 .. 31; + WPSR at 16#1E8# range 0 .. 31; end record; -- DMA Controller diff --git a/arduino-due/atsam3x8e/atsam3x8e-ebi.ads b/arduino-due/atsam3x8e/atsam3x8e-ebi.ads index 8b208a8..3012413 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-ebi.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-ebi.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,13 +14,8 @@ package ATSAM3X8E.EBI is -- Registers -- --------------- - ------------------ - -- CFG_Register -- - ------------------ - - type PAGESIZE_Field is - ( - -- Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes + type CFG_PAGESIZE_Field is + (-- Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes Ps512_16, -- Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes Ps1024_32, @@ -28,22 +24,21 @@ package ATSAM3X8E.EBI is -- Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes Ps4096_128) with Size => 2; - for PAGESIZE_Field use + for CFG_PAGESIZE_Field use (Ps512_16 => 0, Ps1024_32 => 1, Ps2048_64 => 2, Ps4096_128 => 3); - subtype CFG_WSPARE_Field is ATSAM3X8E.Bit; - subtype CFG_RSPARE_Field is ATSAM3X8E.Bit; - subtype CFG_EDGECTRL_Field is ATSAM3X8E.Bit; - subtype CFG_RBEDGE_Field is ATSAM3X8E.Bit; - subtype CFG_DTOCYC_Field is ATSAM3X8E.UInt4; + subtype SMC_CFG_WSPARE_Field is ATSAM3X8E.Bit; + subtype SMC_CFG_RSPARE_Field is ATSAM3X8E.Bit; + subtype SMC_CFG_EDGECTRL_Field is ATSAM3X8E.Bit; + subtype SMC_CFG_RBEDGE_Field is ATSAM3X8E.Bit; + subtype SMC_CFG_DTOCYC_Field is ATSAM3X8E.UInt4; -- Data Timeout Multiplier - type DTOMUL_Field is - ( - -- DTOCYC + type CFG_DTOMUL_Field is + (-- DTOCYC X1, -- DTOCYC x 16 X16, @@ -60,7 +55,7 @@ package ATSAM3X8E.EBI is -- DTOCYC x 1048576 X1048576) with Size => 3; - for DTOMUL_Field use + for CFG_DTOMUL_Field use (X1 => 0, X16 => 1, X128 => 2, @@ -71,32 +66,32 @@ package ATSAM3X8E.EBI is X1048576 => 7); -- SMC NFC Configuration Register - type CFG_Register is record - PAGESIZE : PAGESIZE_Field := Ps512_16; + type SMC_CFG_Register is record + PAGESIZE : CFG_PAGESIZE_Field := ATSAM3X8E.EBI.Ps512_16; -- unspecified Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; -- Write Spare Area - WSPARE : CFG_WSPARE_Field := 16#0#; + WSPARE : SMC_CFG_WSPARE_Field := 16#0#; -- Read Spare Area - RSPARE : CFG_RSPARE_Field := 16#0#; + RSPARE : SMC_CFG_RSPARE_Field := 16#0#; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2 := 16#0#; -- Rising/Falling Edge Detection Control - EDGECTRL : CFG_EDGECTRL_Field := 16#0#; + EDGECTRL : SMC_CFG_EDGECTRL_Field := 16#0#; -- Ready/Busy Signal Edge Detection - RBEDGE : CFG_RBEDGE_Field := 16#0#; + RBEDGE : SMC_CFG_RBEDGE_Field := 16#0#; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Data Timeout Cycle Number - DTOCYC : CFG_DTOCYC_Field := 16#0#; + DTOCYC : SMC_CFG_DTOCYC_Field := 16#0#; -- Data Timeout Multiplier - DTOMUL : DTOMUL_Field := X1; + DTOMUL : CFG_DTOMUL_Field := ATSAM3X8E.EBI.X1; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CFG_Register use record + for SMC_CFG_Register use record PAGESIZE at 0 range 0 .. 1; Reserved_2_7 at 0 range 2 .. 7; WSPARE at 0 range 8 .. 8; @@ -110,92 +105,84 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- CTRL_Register -- - ------------------- - - subtype CTRL_NFCEN_Field is ATSAM3X8E.Bit; - subtype CTRL_NFCDIS_Field is ATSAM3X8E.Bit; + subtype SMC_CTRL_NFCEN_Field is ATSAM3X8E.Bit; + subtype SMC_CTRL_NFCDIS_Field is ATSAM3X8E.Bit; -- SMC NFC Control Register - type CTRL_Register is record + type SMC_CTRL_Register is record -- Write-only. NAND Flash Controller Enable - NFCEN : CTRL_NFCEN_Field := 16#0#; + NFCEN : SMC_CTRL_NFCEN_Field := 16#0#; -- Write-only. NAND Flash Controller Disable - NFCDIS : CTRL_NFCDIS_Field := 16#0#; + NFCDIS : SMC_CTRL_NFCDIS_Field := 16#0#; -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CTRL_Register use record + for SMC_CTRL_Register use record NFCEN at 0 range 0 .. 0; NFCDIS at 0 range 1 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_SMCSTS_Field is ATSAM3X8E.Bit; - subtype SR_RB_RISE_Field is ATSAM3X8E.Bit; - subtype SR_RB_FALL_Field is ATSAM3X8E.Bit; - subtype SR_NFCBUSY_Field is ATSAM3X8E.Bit; - subtype SR_NFCWR_Field is ATSAM3X8E.Bit; - subtype SR_NFCSID_Field is ATSAM3X8E.UInt3; - subtype SR_XFRDONE_Field is ATSAM3X8E.Bit; - subtype SR_CMDDONE_Field is ATSAM3X8E.Bit; - subtype SR_DTOE_Field is ATSAM3X8E.Bit; - subtype SR_UNDEF_Field is ATSAM3X8E.Bit; - subtype SR_AWB_Field is ATSAM3X8E.Bit; - subtype SR_NFCASE_Field is ATSAM3X8E.Bit; - subtype SR_RB_EDGE0_Field is ATSAM3X8E.Bit; + subtype SMC_SR_SMCSTS_Field is ATSAM3X8E.Bit; + subtype SMC_SR_RB_RISE_Field is ATSAM3X8E.Bit; + subtype SMC_SR_RB_FALL_Field is ATSAM3X8E.Bit; + subtype SMC_SR_NFCBUSY_Field is ATSAM3X8E.Bit; + subtype SMC_SR_NFCWR_Field is ATSAM3X8E.Bit; + subtype SMC_SR_NFCSID_Field is ATSAM3X8E.UInt3; + subtype SMC_SR_XFRDONE_Field is ATSAM3X8E.Bit; + subtype SMC_SR_CMDDONE_Field is ATSAM3X8E.Bit; + subtype SMC_SR_DTOE_Field is ATSAM3X8E.Bit; + subtype SMC_SR_UNDEF_Field is ATSAM3X8E.Bit; + subtype SMC_SR_AWB_Field is ATSAM3X8E.Bit; + subtype SMC_SR_NFCASE_Field is ATSAM3X8E.Bit; + subtype SMC_SR_RB_EDGE0_Field is ATSAM3X8E.Bit; -- SMC NFC Status Register - type SR_Register is record + type SMC_SR_Register is record -- Read-only. NAND Flash Controller status (this field cannot be reset) - SMCSTS : SR_SMCSTS_Field := 16#0#; + SMCSTS : SMC_SR_SMCSTS_Field; -- unspecified Reserved_1_3 : ATSAM3X8E.UInt3; -- Read-only. Selected Ready Busy Rising Edge Detected - RB_RISE : SR_RB_RISE_Field := 16#0#; + RB_RISE : SMC_SR_RB_RISE_Field; -- Read-only. Selected Ready Busy Falling Edge Detected - RB_FALL : SR_RB_FALL_Field := 16#0#; + RB_FALL : SMC_SR_RB_FALL_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. NFC Busy (this field cannot be reset) - NFCBUSY : SR_NFCBUSY_Field := 16#0#; + NFCBUSY : SMC_SR_NFCBUSY_Field; -- unspecified Reserved_9_10 : ATSAM3X8E.UInt2; -- Read-only. NFC Write/Read Operation (this field cannot be reset) - NFCWR : SR_NFCWR_Field := 16#0#; + NFCWR : SMC_SR_NFCWR_Field; -- Read-only. NFC Chip Select ID (this field cannot be reset) - NFCSID : SR_NFCSID_Field := 16#0#; + NFCSID : SMC_SR_NFCSID_Field; -- unspecified Reserved_15_15 : ATSAM3X8E.Bit; -- Read-only. NFC Data Transfer Terminated - XFRDONE : SR_XFRDONE_Field := 16#0#; + XFRDONE : SMC_SR_XFRDONE_Field; -- Read-only. Command Done - CMDDONE : SR_CMDDONE_Field := 16#0#; + CMDDONE : SMC_SR_CMDDONE_Field; -- unspecified Reserved_18_19 : ATSAM3X8E.UInt2; -- Read-only. Data Timeout Error - DTOE : SR_DTOE_Field := 16#0#; + DTOE : SMC_SR_DTOE_Field; -- Read-only. Undefined Area Error - UNDEF : SR_UNDEF_Field := 16#0#; + UNDEF : SMC_SR_UNDEF_Field; -- Read-only. Accessing While Busy - AWB : SR_AWB_Field := 16#0#; + AWB : SMC_SR_AWB_Field; -- Read-only. NFC Access Size Error - NFCASE : SR_NFCASE_Field := 16#0#; + NFCASE : SMC_SR_NFCASE_Field; -- Read-only. Ready/Busy Line 0 Edge Detected - RB_EDGE0 : SR_RB_EDGE0_Field := 16#0#; + RB_EDGE0 : SMC_SR_RB_EDGE0_Field; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for SMC_SR_Register use record SMCSTS at 0 range 0 .. 0; Reserved_1_3 at 0 range 1 .. 3; RB_RISE at 0 range 4 .. 4; @@ -217,52 +204,48 @@ package ATSAM3X8E.EBI is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_RB_RISE_Field is ATSAM3X8E.Bit; - subtype IER_RB_FALL_Field is ATSAM3X8E.Bit; - subtype IER_XFRDONE_Field is ATSAM3X8E.Bit; - subtype IER_CMDDONE_Field is ATSAM3X8E.Bit; - subtype IER_DTOE_Field is ATSAM3X8E.Bit; - subtype IER_UNDEF_Field is ATSAM3X8E.Bit; - subtype IER_AWB_Field is ATSAM3X8E.Bit; - subtype IER_NFCASE_Field is ATSAM3X8E.Bit; - subtype IER_RB_EDGE0_Field is ATSAM3X8E.Bit; + subtype SMC_IER_RB_RISE_Field is ATSAM3X8E.Bit; + subtype SMC_IER_RB_FALL_Field is ATSAM3X8E.Bit; + subtype SMC_IER_XFRDONE_Field is ATSAM3X8E.Bit; + subtype SMC_IER_CMDDONE_Field is ATSAM3X8E.Bit; + subtype SMC_IER_DTOE_Field is ATSAM3X8E.Bit; + subtype SMC_IER_UNDEF_Field is ATSAM3X8E.Bit; + subtype SMC_IER_AWB_Field is ATSAM3X8E.Bit; + subtype SMC_IER_NFCASE_Field is ATSAM3X8E.Bit; + subtype SMC_IER_RB_EDGE0_Field is ATSAM3X8E.Bit; -- SMC NFC Interrupt Enable Register - type IER_Register is record + type SMC_IER_Register is record -- unspecified Reserved_0_3 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Ready Busy Rising Edge Detection Interrupt Enable - RB_RISE : IER_RB_RISE_Field := 16#0#; + RB_RISE : SMC_IER_RB_RISE_Field := 16#0#; -- Write-only. Ready Busy Falling Edge Detection Interrupt Enable - RB_FALL : IER_RB_FALL_Field := 16#0#; + RB_FALL : SMC_IER_RB_FALL_Field := 16#0#; -- unspecified Reserved_6_15 : ATSAM3X8E.UInt10 := 16#0#; -- Write-only. Transfer Done Interrupt Enable - XFRDONE : IER_XFRDONE_Field := 16#0#; + XFRDONE : SMC_IER_XFRDONE_Field := 16#0#; -- Write-only. Command Done Interrupt Enable - CMDDONE : IER_CMDDONE_Field := 16#0#; + CMDDONE : SMC_IER_CMDDONE_Field := 16#0#; -- unspecified Reserved_18_19 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Data Timeout Error Interrupt Enable - DTOE : IER_DTOE_Field := 16#0#; + DTOE : SMC_IER_DTOE_Field := 16#0#; -- Write-only. Undefined Area Access Interrupt Enable - UNDEF : IER_UNDEF_Field := 16#0#; + UNDEF : SMC_IER_UNDEF_Field := 16#0#; -- Write-only. Accessing While Busy Interrupt Enable - AWB : IER_AWB_Field := 16#0#; + AWB : SMC_IER_AWB_Field := 16#0#; -- Write-only. NFC Access Size Error Interrupt Enable - NFCASE : IER_NFCASE_Field := 16#0#; + NFCASE : SMC_IER_NFCASE_Field := 16#0#; -- Write-only. Ready/Busy Line 0 Interrupt Enable - RB_EDGE0 : IER_RB_EDGE0_Field := 16#0#; + RB_EDGE0 : SMC_IER_RB_EDGE0_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for SMC_IER_Register use record Reserved_0_3 at 0 range 0 .. 3; RB_RISE at 0 range 4 .. 4; RB_FALL at 0 range 5 .. 5; @@ -278,52 +261,48 @@ package ATSAM3X8E.EBI is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_RB_RISE_Field is ATSAM3X8E.Bit; - subtype IDR_RB_FALL_Field is ATSAM3X8E.Bit; - subtype IDR_XFRDONE_Field is ATSAM3X8E.Bit; - subtype IDR_CMDDONE_Field is ATSAM3X8E.Bit; - subtype IDR_DTOE_Field is ATSAM3X8E.Bit; - subtype IDR_UNDEF_Field is ATSAM3X8E.Bit; - subtype IDR_AWB_Field is ATSAM3X8E.Bit; - subtype IDR_NFCASE_Field is ATSAM3X8E.Bit; - subtype IDR_RB_EDGE0_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_RB_RISE_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_RB_FALL_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_XFRDONE_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_CMDDONE_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_DTOE_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_UNDEF_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_AWB_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_NFCASE_Field is ATSAM3X8E.Bit; + subtype SMC_IDR_RB_EDGE0_Field is ATSAM3X8E.Bit; -- SMC NFC Interrupt Disable Register - type IDR_Register is record + type SMC_IDR_Register is record -- unspecified Reserved_0_3 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Ready Busy Rising Edge Detection Interrupt Disable - RB_RISE : IDR_RB_RISE_Field := 16#0#; + RB_RISE : SMC_IDR_RB_RISE_Field := 16#0#; -- Write-only. Ready Busy Falling Edge Detection Interrupt Disable - RB_FALL : IDR_RB_FALL_Field := 16#0#; + RB_FALL : SMC_IDR_RB_FALL_Field := 16#0#; -- unspecified Reserved_6_15 : ATSAM3X8E.UInt10 := 16#0#; -- Write-only. Transfer Done Interrupt Disable - XFRDONE : IDR_XFRDONE_Field := 16#0#; + XFRDONE : SMC_IDR_XFRDONE_Field := 16#0#; -- Write-only. Command Done Interrupt Disable - CMDDONE : IDR_CMDDONE_Field := 16#0#; + CMDDONE : SMC_IDR_CMDDONE_Field := 16#0#; -- unspecified Reserved_18_19 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Data Timeout Error Interrupt Disable - DTOE : IDR_DTOE_Field := 16#0#; + DTOE : SMC_IDR_DTOE_Field := 16#0#; -- Write-only. Undefined Area Access Interrupt Disable - UNDEF : IDR_UNDEF_Field := 16#0#; + UNDEF : SMC_IDR_UNDEF_Field := 16#0#; -- Write-only. Accessing While Busy Interrupt Disable - AWB : IDR_AWB_Field := 16#0#; + AWB : SMC_IDR_AWB_Field := 16#0#; -- Write-only. NFC Access Size Error Interrupt Disable - NFCASE : IDR_NFCASE_Field := 16#0#; + NFCASE : SMC_IDR_NFCASE_Field := 16#0#; -- Write-only. Ready/Busy Line 0 Interrupt Disable - RB_EDGE0 : IDR_RB_EDGE0_Field := 16#0#; + RB_EDGE0 : SMC_IDR_RB_EDGE0_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for SMC_IDR_Register use record Reserved_0_3 at 0 range 0 .. 3; RB_RISE at 0 range 4 .. 4; RB_FALL at 0 range 5 .. 5; @@ -339,52 +318,48 @@ package ATSAM3X8E.EBI is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_RB_RISE_Field is ATSAM3X8E.Bit; - subtype IMR_RB_FALL_Field is ATSAM3X8E.Bit; - subtype IMR_XFRDONE_Field is ATSAM3X8E.Bit; - subtype IMR_CMDDONE_Field is ATSAM3X8E.Bit; - subtype IMR_DTOE_Field is ATSAM3X8E.Bit; - subtype IMR_UNDEF_Field is ATSAM3X8E.Bit; - subtype IMR_AWB_Field is ATSAM3X8E.Bit; - subtype IMR_NFCASE_Field is ATSAM3X8E.Bit; - subtype IMR_RB_EDGE0_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_RB_RISE_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_RB_FALL_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_XFRDONE_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_CMDDONE_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_DTOE_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_UNDEF_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_AWB_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_NFCASE_Field is ATSAM3X8E.Bit; + subtype SMC_IMR_RB_EDGE0_Field is ATSAM3X8E.Bit; -- SMC NFC Interrupt Mask Register - type IMR_Register is record + type SMC_IMR_Register is record -- unspecified Reserved_0_3 : ATSAM3X8E.UInt4; -- Read-only. Ready Busy Rising Edge Detection Interrupt Mask - RB_RISE : IMR_RB_RISE_Field := 16#0#; + RB_RISE : SMC_IMR_RB_RISE_Field; -- Read-only. Ready Busy Falling Edge Detection Interrupt Mask - RB_FALL : IMR_RB_FALL_Field := 16#0#; + RB_FALL : SMC_IMR_RB_FALL_Field; -- unspecified Reserved_6_15 : ATSAM3X8E.UInt10; -- Read-only. Transfer Done Interrupt Mask - XFRDONE : IMR_XFRDONE_Field := 16#0#; + XFRDONE : SMC_IMR_XFRDONE_Field; -- Read-only. Command Done Interrupt Mask - CMDDONE : IMR_CMDDONE_Field := 16#0#; + CMDDONE : SMC_IMR_CMDDONE_Field; -- unspecified Reserved_18_19 : ATSAM3X8E.UInt2; -- Read-only. Data Timeout Error Interrupt Mask - DTOE : IMR_DTOE_Field := 16#0#; + DTOE : SMC_IMR_DTOE_Field; -- Read-only. Undefined Area Access Interrupt Mask5 - UNDEF : IMR_UNDEF_Field := 16#0#; + UNDEF : SMC_IMR_UNDEF_Field; -- Read-only. Accessing While Busy Interrupt Mask - AWB : IMR_AWB_Field := 16#0#; + AWB : SMC_IMR_AWB_Field; -- Read-only. NFC Access Size Error Interrupt Mask - NFCASE : IMR_NFCASE_Field := 16#0#; + NFCASE : SMC_IMR_NFCASE_Field; -- Read-only. Ready/Busy Line 0 Interrupt Mask - RB_EDGE0 : IMR_RB_EDGE0_Field := 16#0#; + RB_EDGE0 : SMC_IMR_RB_EDGE0_Field; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for SMC_IMR_Register use record Reserved_0_3 at 0 range 0 .. 3; RB_RISE at 0 range 4 .. 4; RB_FALL at 0 range 5 .. 5; @@ -400,78 +375,61 @@ package ATSAM3X8E.EBI is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------- - -- ADDR_Register -- - ------------------- - - subtype ADDR_ADDR_CYCLE0_Field is ATSAM3X8E.Byte; + subtype SMC_ADDR_ADDR_CYCLE0_Field is ATSAM3X8E.Byte; -- SMC NFC Address Cycle Zero Register - type ADDR_Register is record + type SMC_ADDR_Register is record -- NAND Flash Array Address cycle 0 - ADDR_CYCLE0 : ADDR_ADDR_CYCLE0_Field := 16#0#; + ADDR_CYCLE0 : SMC_ADDR_ADDR_CYCLE0_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ADDR_Register use record + for SMC_ADDR_Register use record ADDR_CYCLE0 at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- BANK_Register -- - ------------------- - - subtype BANK_BANK_Field is ATSAM3X8E.UInt3; + subtype SMC_BANK_BANK_Field is ATSAM3X8E.UInt3; -- SMC Bank Address Register - type BANK_Register is record + type SMC_BANK_Register is record -- Bank Identifier - BANK : BANK_BANK_Field := 16#0#; + BANK : SMC_BANK_BANK_Field := 16#0#; -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for BANK_Register use record + for SMC_BANK_Register use record BANK at 0 range 0 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------- - -- ECC_CTRL_Register -- - ----------------------- - - subtype ECC_CTRL_RST_Field is ATSAM3X8E.Bit; - subtype ECC_CTRL_SWRST_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_CTRL_RST_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_CTRL_SWRST_Field is ATSAM3X8E.Bit; -- SMC ECC Control Register - type ECC_CTRL_Register is record + type SMC_ECC_CTRL_Register is record -- Write-only. Reset ECC - RST : ECC_CTRL_RST_Field := 16#0#; + RST : SMC_ECC_CTRL_RST_Field := 16#0#; -- Write-only. Software Reset - SWRST : ECC_CTRL_SWRST_Field := 16#0#; + SWRST : SMC_ECC_CTRL_SWRST_Field := 16#0#; -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_CTRL_Register use record + for SMC_ECC_CTRL_Register use record RST at 0 range 0 .. 0; SWRST at 0 range 1 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - --------------------- - -- ECC_MD_Register -- - --------------------- - -- ECC Page Size - type ECC_PAGESIZE_Field is - ( - -- Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes + type ECC_MD_ECC_PAGESIZE_Field is + (-- Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes Ps512_16, -- Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes Ps1024_32, @@ -480,151 +438,146 @@ package ATSAM3X8E.EBI is -- Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes Ps4096_128) with Size => 2; - for ECC_PAGESIZE_Field use + for ECC_MD_ECC_PAGESIZE_Field use (Ps512_16 => 0, Ps1024_32 => 1, Ps2048_64 => 2, Ps4096_128 => 3); -- Type of Correction - type TYPCORREC_Field is - ( - -- 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or - -- 16-bit NAND Flash) + type ECC_MD_TYPCORREC_Field is + (-- 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit +-- NAND Flash) Cpage, - -- 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 - -- bytes (for 8-bit NAND Flash only) + -- 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes +-- (for 8-bit NAND Flash only) C256B, - -- 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 - -- bytes (for 8-bit NAND Flash only) + -- 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes +-- (for 8-bit NAND Flash only) C512B) with Size => 2; - for TYPCORREC_Field use + for ECC_MD_TYPCORREC_Field use (Cpage => 0, C256B => 1, C512B => 2); -- SMC ECC Mode Register - type ECC_MD_Register is record + type SMC_ECC_MD_Register is record -- ECC Page Size - ECC_PAGESIZE : ECC_PAGESIZE_Field := Ps512_16; + ECC_PAGESIZE : ECC_MD_ECC_PAGESIZE_Field := ATSAM3X8E.EBI.Ps512_16; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- Type of Correction - TYPCORREC : TYPCORREC_Field := Cpage; + TYPCORREC : ECC_MD_TYPCORREC_Field := ATSAM3X8E.EBI.Cpage; -- unspecified Reserved_6_31 : ATSAM3X8E.UInt26 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_MD_Register use record + for SMC_ECC_MD_Register use record ECC_PAGESIZE at 0 range 0 .. 1; Reserved_2_3 at 0 range 2 .. 3; TYPCORREC at 0 range 4 .. 5; Reserved_6_31 at 0 range 6 .. 31; end record; - --------------------- - -- ECC_SR_Register -- - --------------------- - - subtype ECC_SR1_RECERR0_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_ECCERR0_Field is ATSAM3X8E.UInt2; - subtype ECC_SR1_RECERR1_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_ECCERR1_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_MULERR1_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_RECERR2_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_ECCERR2_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_MULERR2_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_RECERR3_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_ECCERR3_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_MULERR3_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_RECERR4_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_ECCERR4_Field is ATSAM3X8E.UInt2; - subtype ECC_SR1_RECERR5_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_ECCERR5_Field is ATSAM3X8E.UInt2; - subtype ECC_SR1_RECERR6_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_ECCERR6_Field is ATSAM3X8E.UInt2; - subtype ECC_SR1_RECERR7_Field is ATSAM3X8E.Bit; - subtype ECC_SR1_ECCERR7_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR1_RECERR0_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_ECCERR0_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR1_RECERR1_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_ECCERR1_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_MULERR1_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_RECERR2_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_ECCERR2_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_MULERR2_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_RECERR3_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_ECCERR3_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_MULERR3_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_RECERR4_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_ECCERR4_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR1_RECERR5_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_ECCERR5_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR1_RECERR6_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_ECCERR6_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR1_RECERR7_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR1_ECCERR7_Field is ATSAM3X8E.UInt2; -- SMC ECC Status 1 Register - type ECC_SR_Register is record + type SMC_ECC_SR1_Register is record -- Read-only. Recoverable Error - RECERR0 : ECC_SR1_RECERR0_Field := 16#0#; + RECERR0 : SMC_ECC_SR1_RECERR0_Field; -- Read-only. ECC Error - ECCERR0 : ECC_SR1_ECCERR0_Field := 16#0#; + ECCERR0 : SMC_ECC_SR1_ECCERR0_Field; -- unspecified Reserved_3_3 : ATSAM3X8E.Bit; -- Read-only. Recoverable Error in the page between the 256th and the -- 511th bytes or the 512nd and the 1023rd bytes - RECERR1 : ECC_SR1_RECERR1_Field := 16#0#; + RECERR1 : SMC_ECC_SR1_RECERR1_Field; -- Read-only. ECC Error in the page between the 256th and the 511th -- bytes or between the 512nd and the 1023rd bytes - ECCERR1 : ECC_SR1_ECCERR1_Field := 16#0#; + ECCERR1 : SMC_ECC_SR1_ECCERR1_Field; -- Read-only. Multiple Error in the page between the 256th and the 511th -- bytes or between the 512nd and the 1023rd bytes - MULERR1 : ECC_SR1_MULERR1_Field := 16#0#; + MULERR1 : SMC_ECC_SR1_MULERR1_Field; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit; -- Read-only. Recoverable Error in the page between the 512nd and the -- 767th bytes or between the 1024th and the 1535th bytes - RECERR2 : ECC_SR1_RECERR2_Field := 16#0#; + RECERR2 : SMC_ECC_SR1_RECERR2_Field; -- Read-only. ECC Error in the page between the 512nd and the 767th -- bytes or between the 1024th and the 1535th bytes - ECCERR2 : ECC_SR1_ECCERR2_Field := 16#0#; + ECCERR2 : SMC_ECC_SR1_ECCERR2_Field; -- Read-only. Multiple Error in the page between the 512nd and the 767th -- bytes or between the 1024th and the 1535th bytes - MULERR2 : ECC_SR1_MULERR2_Field := 16#0#; + MULERR2 : SMC_ECC_SR1_MULERR2_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Recoverable Error in the page between the 768th and the -- 1023rd bytes or between the 1536th and the 2047th bytes - RECERR3 : ECC_SR1_RECERR3_Field := 16#0#; + RECERR3 : SMC_ECC_SR1_RECERR3_Field; -- Read-only. ECC Error in the page between the 768th and the 1023rd -- bytes or between the 1536th and the 2047th bytes - ECCERR3 : ECC_SR1_ECCERR3_Field := 16#0#; + ECCERR3 : SMC_ECC_SR1_ECCERR3_Field; -- Read-only. Multiple Error in the page between the 768th and the -- 1023rd bytes or between the 1536th and the 2047th bytes - MULERR3 : ECC_SR1_MULERR3_Field := 16#0#; + MULERR3 : SMC_ECC_SR1_MULERR3_Field; -- unspecified Reserved_15_15 : ATSAM3X8E.Bit; -- Read-only. Recoverable Error in the page between the 1024th and the -- 1279th bytes or between the 2048th and the 2559th bytes - RECERR4 : ECC_SR1_RECERR4_Field := 16#0#; + RECERR4 : SMC_ECC_SR1_RECERR4_Field; -- Read-only. ECC Error in the page between the 1024th and the 1279th -- bytes or between the 2048th and the 2559th bytes - ECCERR4 : ECC_SR1_ECCERR4_Field := 16#0#; + ECCERR4 : SMC_ECC_SR1_ECCERR4_Field; -- unspecified Reserved_19_19 : ATSAM3X8E.Bit; -- Read-only. Recoverable Error in the page between the 1280th and the -- 1535th bytes or between the 2560th and the 3071st bytes - RECERR5 : ECC_SR1_RECERR5_Field := 16#0#; + RECERR5 : SMC_ECC_SR1_RECERR5_Field; -- Read-only. ECC Error in the page between the 1280th and the 1535th -- bytes or between the 2560th and the 3071st bytes - ECCERR5 : ECC_SR1_ECCERR5_Field := 16#0#; + ECCERR5 : SMC_ECC_SR1_ECCERR5_Field; -- unspecified Reserved_23_23 : ATSAM3X8E.Bit; -- Read-only. Recoverable Error in the page between the 1536th and the -- 1791st bytes or between the 3072nd and the 3583rd bytes - RECERR6 : ECC_SR1_RECERR6_Field := 16#0#; + RECERR6 : SMC_ECC_SR1_RECERR6_Field; -- Read-only. ECC Error in the page between the 1536th and the 1791st -- bytes or between the 3072nd and the 3583rd bytes - ECCERR6 : ECC_SR1_ECCERR6_Field := 16#0#; + ECCERR6 : SMC_ECC_SR1_ECCERR6_Field; -- unspecified Reserved_27_27 : ATSAM3X8E.Bit; -- Read-only. Recoverable Error in the page between the 1792nd and the -- 2047th bytes or between the 3584th and the 4095th bytes - RECERR7 : ECC_SR1_RECERR7_Field := 16#0#; + RECERR7 : SMC_ECC_SR1_RECERR7_Field; -- Read-only. ECC Error in the page between the 1792nd and the 2047th -- bytes or between the 3584th and the 4095th bytes - ECCERR7 : ECC_SR1_ECCERR7_Field := 16#0#; + ECCERR7 : SMC_ECC_SR1_ECCERR7_Field; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_SR_Register use record + for SMC_ECC_SR1_Register use record RECERR0 at 0 range 0 .. 0; ECCERR0 at 0 range 1 .. 2; Reserved_3_3 at 0 range 3 .. 3; @@ -654,86 +607,74 @@ package ATSAM3X8E.EBI is Reserved_31_31 at 0 range 31 .. 31; end record; - ---------------------- - -- ECC_PR0_Register -- - ---------------------- - - subtype ECC_PR0_BITADDR_Field is ATSAM3X8E.UInt4; - subtype ECC_PR0_WORDADDR_Field is ATSAM3X8E.UInt12; + subtype SMC_ECC_PR0_BITADDR_Field is ATSAM3X8E.UInt4; + subtype SMC_ECC_PR0_WORDADDR_Field is ATSAM3X8E.UInt12; -- SMC ECC Parity 0 Register - type ECC_PR0_Register is record + type SMC_ECC_PR0_Register is record -- Read-only. Bit Address - BITADDR : ECC_PR0_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR0_BITADDR_Field; -- Read-only. Word Address - WORDADDR : ECC_PR0_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR0_WORDADDR_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR0_Register use record + for SMC_ECC_PR0_Register use record BITADDR at 0 range 0 .. 3; WORDADDR at 0 range 4 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------------- - -- ECC_PR0_W9BIT_Register -- - ---------------------------- - - subtype ECC_PR0_W9BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR0_W9BIT_WORDADDR_Field is ATSAM3X8E.UInt9; - subtype ECC_PR0_W9BIT_NPARITY_Field is ATSAM3X8E.UInt12; + subtype SMC_ECC_PR0_W9BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR0_W9BIT_WORDADDR_Field is ATSAM3X8E.UInt9; + subtype SMC_ECC_PR0_W9BIT_NPARITY_Field is ATSAM3X8E.UInt12; -- SMC ECC Parity 0 Register - type ECC_PR0_W9BIT_Register is record + type SMC_ECC_PR0_W9BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 512) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR0_W9BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR0_W9BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 512) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR0_W9BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR0_W9BIT_WORDADDR_Field; -- Read-only. Parity N - NPARITY : ECC_PR0_W9BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR0_W9BIT_NPARITY_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR0_W9BIT_Register use record + for SMC_ECC_PR0_W9BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 11; NPARITY at 0 range 12 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------------- - -- ECC_PR0_W8BIT_Register -- - ---------------------------- - - subtype ECC_PR0_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR0_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR0_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; + subtype SMC_ECC_PR0_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR0_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; + subtype SMC_ECC_PR0_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; -- SMC ECC Parity 0 Register - type ECC_PR0_W8BIT_Register is record + type SMC_ECC_PR0_W8BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR0_W8BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR0_W8BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR0_W8BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR0_W8BIT_WORDADDR_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR0_W8BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR0_W8BIT_NPARITY_Field; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR0_W8BIT_Register use record + for SMC_ECC_PR0_W8BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 10; Reserved_11_11 at 0 range 11 .. 11; @@ -741,82 +682,70 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - ---------------------- - -- ECC_PR1_Register -- - ---------------------- - - subtype ECC_PR1_NPARITY_Field is ATSAM3X8E.Short; + subtype SMC_ECC_PR1_NPARITY_Field is ATSAM3X8E.UInt16; -- SMC ECC parity 1 Register - type ECC_PR1_Register is record + type SMC_ECC_PR1_Register is record -- Read-only. Parity N - NPARITY : ECC_PR1_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR1_NPARITY_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR1_Register use record + for SMC_ECC_PR1_Register use record NPARITY at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------------- - -- ECC_PR1_W9BIT_Register -- - ---------------------------- - - subtype ECC_PR1_W9BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR1_W9BIT_WORDADDR_Field is ATSAM3X8E.UInt9; - subtype ECC_PR1_W9BIT_NPARITY_Field is ATSAM3X8E.UInt12; + subtype SMC_ECC_PR1_W9BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR1_W9BIT_WORDADDR_Field is ATSAM3X8E.UInt9; + subtype SMC_ECC_PR1_W9BIT_NPARITY_Field is ATSAM3X8E.UInt12; -- SMC ECC parity 1 Register - type ECC_PR1_W9BIT_Register is record + type SMC_ECC_PR1_W9BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 512) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR1_W9BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR1_W9BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 512) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR1_W9BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR1_W9BIT_WORDADDR_Field; -- Read-only. Parity N - NPARITY : ECC_PR1_W9BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR1_W9BIT_NPARITY_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR1_W9BIT_Register use record + for SMC_ECC_PR1_W9BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 11; NPARITY at 0 range 12 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------------- - -- ECC_PR1_W8BIT_Register -- - ---------------------------- - - subtype ECC_PR1_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR1_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR1_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; + subtype SMC_ECC_PR1_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR1_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; + subtype SMC_ECC_PR1_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; -- SMC ECC parity 1 Register - type ECC_PR1_W8BIT_Register is record + type SMC_ECC_PR1_W8BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR1_W8BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR1_W8BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR1_W8BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR1_W8BIT_WORDADDR_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR1_W8BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR1_W8BIT_NPARITY_Field; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR1_W8BIT_Register use record + for SMC_ECC_PR1_W8BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 10; Reserved_11_11 at 0 range 11 .. 11; @@ -824,28 +753,152 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - --------------------- - -- ECC_PR_Register -- - --------------------- + subtype SMC_ECC_SR2_RECERR8_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_ECCERR8_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR2_RECERR9_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_ECCERR9_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_MULERR9_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_RECERR10_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_ECCERR10_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_MULERR10_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_RECERR11_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_ECCERR11_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_MULERR11_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_RECERR12_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_ECCERR12_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR2_RECERR13_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_ECCERR13_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR2_RECERR14_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_ECCERR14_Field is ATSAM3X8E.UInt2; + subtype SMC_ECC_SR2_RECERR15_Field is ATSAM3X8E.Bit; + subtype SMC_ECC_SR2_ECCERR15_Field is ATSAM3X8E.UInt2; + + -- SMC ECC status 2 Register + type SMC_ECC_SR2_Register is record + -- Read-only. Recoverable Error in the page between the 2048th and the + -- 2303rd bytes + RECERR8 : SMC_ECC_SR2_RECERR8_Field; + -- Read-only. ECC Error in the page between the 2048th and the 2303rd + -- bytes + ECCERR8 : SMC_ECC_SR2_ECCERR8_Field; + -- unspecified + Reserved_3_3 : ATSAM3X8E.Bit; + -- Read-only. Recoverable Error in the page between the 2304th and the + -- 2559th bytes + RECERR9 : SMC_ECC_SR2_RECERR9_Field; + -- Read-only. ECC Error in the page between the 2304th and the 2559th + -- bytes + ECCERR9 : SMC_ECC_SR2_ECCERR9_Field; + -- Read-only. Multiple Error in the page between the 2304th and the + -- 2559th bytes + MULERR9 : SMC_ECC_SR2_MULERR9_Field; + -- unspecified + Reserved_7_7 : ATSAM3X8E.Bit; + -- Read-only. Recoverable Error in the page between the 2560th and the + -- 2815th bytes + RECERR10 : SMC_ECC_SR2_RECERR10_Field; + -- Read-only. ECC Error in the page between the 2560th and the 2815th + -- bytes + ECCERR10 : SMC_ECC_SR2_ECCERR10_Field; + -- Read-only. Multiple Error in the page between the 2560th and the + -- 2815th bytes + MULERR10 : SMC_ECC_SR2_MULERR10_Field; + -- unspecified + Reserved_11_11 : ATSAM3X8E.Bit; + -- Read-only. Recoverable Error in the page between the 2816th and the + -- 3071st bytes + RECERR11 : SMC_ECC_SR2_RECERR11_Field; + -- Read-only. ECC Error in the page between the 2816th and the 3071st + -- bytes + ECCERR11 : SMC_ECC_SR2_ECCERR11_Field; + -- Read-only. Multiple Error in the page between the 2816th and the + -- 3071st bytes + MULERR11 : SMC_ECC_SR2_MULERR11_Field; + -- unspecified + Reserved_15_15 : ATSAM3X8E.Bit; + -- Read-only. Recoverable Error in the page between the 3072nd and the + -- 3327th bytes + RECERR12 : SMC_ECC_SR2_RECERR12_Field; + -- Read-only. ECC Error in the page between the 3072nd and the 3327th + -- bytes + ECCERR12 : SMC_ECC_SR2_ECCERR12_Field; + -- unspecified + Reserved_19_19 : ATSAM3X8E.Bit; + -- Read-only. Recoverable Error in the page between the 3328th and the + -- 3583rd bytes + RECERR13 : SMC_ECC_SR2_RECERR13_Field; + -- Read-only. ECC Error in the page between the 3328th and the 3583rd + -- bytes + ECCERR13 : SMC_ECC_SR2_ECCERR13_Field; + -- unspecified + Reserved_23_23 : ATSAM3X8E.Bit; + -- Read-only. Recoverable Error in the page between the 3584th and the + -- 3839th bytes + RECERR14 : SMC_ECC_SR2_RECERR14_Field; + -- Read-only. ECC Error in the page between the 3584th and the 3839th + -- bytes + ECCERR14 : SMC_ECC_SR2_ECCERR14_Field; + -- unspecified + Reserved_27_27 : ATSAM3X8E.Bit; + -- Read-only. Recoverable Error in the page between the 3840th and the + -- 4095th bytes + RECERR15 : SMC_ECC_SR2_RECERR15_Field; + -- Read-only. ECC Error in the page between the 3840th and the 4095th + -- bytes + ECCERR15 : SMC_ECC_SR2_ECCERR15_Field; + -- unspecified + Reserved_31_31 : ATSAM3X8E.Bit; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SMC_ECC_SR2_Register use record + RECERR8 at 0 range 0 .. 0; + ECCERR8 at 0 range 1 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + RECERR9 at 0 range 4 .. 4; + ECCERR9 at 0 range 5 .. 5; + MULERR9 at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + RECERR10 at 0 range 8 .. 8; + ECCERR10 at 0 range 9 .. 9; + MULERR10 at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + RECERR11 at 0 range 12 .. 12; + ECCERR11 at 0 range 13 .. 13; + MULERR11 at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + RECERR12 at 0 range 16 .. 16; + ECCERR12 at 0 range 17 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + RECERR13 at 0 range 20 .. 20; + ECCERR13 at 0 range 21 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + RECERR14 at 0 range 24 .. 24; + ECCERR14 at 0 range 25 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + RECERR15 at 0 range 28 .. 28; + ECCERR15 at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; - subtype ECC_PR2_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR2_WORDADDR_Field is ATSAM3X8E.UInt9; - subtype ECC_PR2_NPARITY_Field is ATSAM3X8E.UInt12; + subtype ECC_PR_BITADDR_Field is ATSAM3X8E.UInt3; + subtype ECC_PR_WORDADDR_Field is ATSAM3X8E.UInt9; + subtype ECC_PR_NPARITY_Field is ATSAM3X8E.UInt12; -- SMC ECC parity 2 Register type ECC_PR_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 512) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR2_BITADDR_Field := 16#0#; + BITADDR : ECC_PR_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 512) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR2_WORDADDR_Field := 16#0#; + WORDADDR : ECC_PR_WORDADDR_Field; -- Read-only. Parity N - NPARITY : ECC_PR2_NPARITY_Field := 16#0#; + NPARITY : ECC_PR_NPARITY_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ECC_PR_Register use record BITADDR at 0 range 0 .. 2; @@ -854,32 +907,28 @@ package ATSAM3X8E.EBI is Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------------- - -- ECC_PR2_W8BIT_Register -- - ---------------------------- - - subtype ECC_PR2_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR2_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR2_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; + subtype SMC_ECC_PR2_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR2_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; + subtype SMC_ECC_PR2_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; -- SMC ECC parity 2 Register - type ECC_PR2_W8BIT_Register is record + type SMC_ECC_PR2_W8BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR2_W8BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR2_W8BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR2_W8BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR2_W8BIT_WORDADDR_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR2_W8BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR2_W8BIT_NPARITY_Field; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR2_W8BIT_Register use record + for SMC_ECC_PR2_W8BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 10; Reserved_11_11 at 0 range 11 .. 11; @@ -887,32 +936,28 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - ---------------------------- - -- ECC_PR3_W8BIT_Register -- - ---------------------------- - - subtype ECC_PR3_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR3_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR3_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; + subtype SMC_ECC_PR3_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR3_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; + subtype SMC_ECC_PR3_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; -- SMC ECC parity 3 Register - type ECC_PR3_W8BIT_Register is record + type SMC_ECC_PR3_W8BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR3_W8BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR3_W8BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR3_W8BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR3_W8BIT_WORDADDR_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR3_W8BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR3_W8BIT_NPARITY_Field; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR3_W8BIT_Register use record + for SMC_ECC_PR3_W8BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 10; Reserved_11_11 at 0 range 11 .. 11; @@ -920,32 +965,28 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - ---------------------------- - -- ECC_PR4_W8BIT_Register -- - ---------------------------- - - subtype ECC_PR4_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR4_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR4_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; + subtype SMC_ECC_PR4_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR4_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; + subtype SMC_ECC_PR4_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; -- SMC ECC parity 4 Register - type ECC_PR4_W8BIT_Register is record + type SMC_ECC_PR4_W8BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR4_W8BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR4_W8BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR4_W8BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR4_W8BIT_WORDADDR_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR4_W8BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR4_W8BIT_NPARITY_Field; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR4_W8BIT_Register use record + for SMC_ECC_PR4_W8BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 10; Reserved_11_11 at 0 range 11 .. 11; @@ -953,32 +994,28 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - ---------------------------- - -- ECC_PR5_W8BIT_Register -- - ---------------------------- - - subtype ECC_PR5_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR5_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR5_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; + subtype SMC_ECC_PR5_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR5_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; + subtype SMC_ECC_PR5_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; -- SMC ECC parity 5 Register - type ECC_PR5_W8BIT_Register is record + type SMC_ECC_PR5_W8BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR5_W8BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR5_W8BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR5_W8BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR5_W8BIT_WORDADDR_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR5_W8BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR5_W8BIT_NPARITY_Field; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR5_W8BIT_Register use record + for SMC_ECC_PR5_W8BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 10; Reserved_11_11 at 0 range 11 .. 11; @@ -986,32 +1023,28 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - ---------------------------- - -- ECC_PR6_W8BIT_Register -- - ---------------------------- - - subtype ECC_PR6_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR6_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR6_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; + subtype SMC_ECC_PR6_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR6_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; + subtype SMC_ECC_PR6_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; -- SMC ECC parity 6 Register - type ECC_PR6_W8BIT_Register is record + type SMC_ECC_PR6_W8BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR6_W8BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR6_W8BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR6_W8BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR6_W8BIT_WORDADDR_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR6_W8BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR6_W8BIT_NPARITY_Field; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR6_W8BIT_Register use record + for SMC_ECC_PR6_W8BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 10; Reserved_11_11 at 0 range 11 .. 11; @@ -1019,32 +1052,28 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - ---------------------------- - -- ECC_PR7_W8BIT_Register -- - ---------------------------- - - subtype ECC_PR7_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR7_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR7_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; + subtype SMC_ECC_PR7_W8BIT_BITADDR_Field is ATSAM3X8E.UInt3; + subtype SMC_ECC_PR7_W8BIT_WORDADDR_Field is ATSAM3X8E.Byte; + subtype SMC_ECC_PR7_W8BIT_NPARITY_Field is ATSAM3X8E.UInt11; -- SMC ECC parity 7 Register - type ECC_PR7_W8BIT_Register is record + type SMC_ECC_PR7_W8BIT_Register is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR7_W8BIT_BITADDR_Field := 16#0#; + BITADDR : SMC_ECC_PR7_W8BIT_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR7_W8BIT_WORDADDR_Field := 16#0#; + WORDADDR : SMC_ECC_PR7_W8BIT_WORDADDR_Field; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR7_W8BIT_NPARITY_Field := 16#0#; + NPARITY : SMC_ECC_PR7_W8BIT_NPARITY_Field; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECC_PR7_W8BIT_Register use record + for SMC_ECC_PR7_W8BIT_Register use record BITADDR at 0 range 0 .. 2; WORDADDR at 0 range 3 .. 10; Reserved_11_11 at 0 range 11 .. 11; @@ -1052,30 +1081,25 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - --------------------- - -- ECC_PR_Register -- - --------------------- - - subtype ECC_PR8_BITADDR_Field is ATSAM3X8E.UInt3; - subtype ECC_PR8_WORDADDR_Field is ATSAM3X8E.Byte; - subtype ECC_PR8_NPARITY_Field is ATSAM3X8E.UInt11; + subtype ECC_PR_WORDADDR_Field_1 is ATSAM3X8E.Byte; + subtype ECC_PR_NPARITY_Field_1 is ATSAM3X8E.UInt11; -- SMC ECC parity 8 Register type ECC_PR_Register_1 is record -- Read-only. Corrupted Bit Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - BITADDR : ECC_PR8_BITADDR_Field := 16#0#; + BITADDR : ECC_PR_BITADDR_Field; -- Read-only. Corrupted Word Address in the Page between (i x 256) and -- ((i + 1) x 512) - 1) Bytes - WORDADDR : ECC_PR8_WORDADDR_Field := 16#0#; + WORDADDR : ECC_PR_WORDADDR_Field_1; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit; -- Read-only. Parity N - NPARITY : ECC_PR8_NPARITY_Field := 16#0#; + NPARITY : ECC_PR_NPARITY_Field_1; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ECC_PR_Register_1 use record BITADDR at 0 range 0 .. 2; @@ -1085,35 +1109,31 @@ package ATSAM3X8E.EBI is Reserved_23_31 at 0 range 23 .. 31; end record; - -------------------- - -- SETUP_Register -- - -------------------- - - subtype SETUP0_NWE_SETUP_Field is ATSAM3X8E.UInt6; - subtype SETUP0_NCS_WR_SETUP_Field is ATSAM3X8E.UInt6; - subtype SETUP0_NRD_SETUP_Field is ATSAM3X8E.UInt6; - subtype SETUP0_NCS_RD_SETUP_Field is ATSAM3X8E.UInt6; + subtype SETUP_NWE_SETUP_Field is ATSAM3X8E.UInt6; + subtype SETUP_NCS_WR_SETUP_Field is ATSAM3X8E.UInt6; + subtype SETUP_NRD_SETUP_Field is ATSAM3X8E.UInt6; + subtype SETUP_NCS_RD_SETUP_Field is ATSAM3X8E.UInt6; -- SMC Setup Register (CS_number = 0) type SETUP_Register is record -- NWE Setup Length - NWE_SETUP : SETUP0_NWE_SETUP_Field := 16#1#; + NWE_SETUP : SETUP_NWE_SETUP_Field := 16#1#; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- NCS Setup Length in Write Access - NCS_WR_SETUP : SETUP0_NCS_WR_SETUP_Field := 16#1#; + NCS_WR_SETUP : SETUP_NCS_WR_SETUP_Field := 16#1#; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- NRD Setup Length - NRD_SETUP : SETUP0_NRD_SETUP_Field := 16#1#; + NRD_SETUP : SETUP_NRD_SETUP_Field := 16#1#; -- unspecified Reserved_22_23 : ATSAM3X8E.UInt2 := 16#0#; -- NCS Setup Length in Read Access - NCS_RD_SETUP : SETUP0_NCS_RD_SETUP_Field := 16#1#; + NCS_RD_SETUP : SETUP_NCS_RD_SETUP_Field := 16#1#; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SETUP_Register use record NWE_SETUP at 0 range 0 .. 5; @@ -1126,35 +1146,31 @@ package ATSAM3X8E.EBI is Reserved_30_31 at 0 range 30 .. 31; end record; - -------------------- - -- PULSE_Register -- - -------------------- - - subtype PULSE0_NWE_PULSE_Field is ATSAM3X8E.UInt6; - subtype PULSE0_NCS_WR_PULSE_Field is ATSAM3X8E.UInt6; - subtype PULSE0_NRD_PULSE_Field is ATSAM3X8E.UInt6; - subtype PULSE0_NCS_RD_PULSE_Field is ATSAM3X8E.UInt6; + subtype PULSE_NWE_PULSE_Field is ATSAM3X8E.UInt6; + subtype PULSE_NCS_WR_PULSE_Field is ATSAM3X8E.UInt6; + subtype PULSE_NRD_PULSE_Field is ATSAM3X8E.UInt6; + subtype PULSE_NCS_RD_PULSE_Field is ATSAM3X8E.UInt6; -- SMC Pulse Register (CS_number = 0) type PULSE_Register is record -- NWE Pulse Length - NWE_PULSE : PULSE0_NWE_PULSE_Field := 16#1#; + NWE_PULSE : PULSE_NWE_PULSE_Field := 16#1#; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- NCS Pulse Length in WRITE Access - NCS_WR_PULSE : PULSE0_NCS_WR_PULSE_Field := 16#1#; + NCS_WR_PULSE : PULSE_NCS_WR_PULSE_Field := 16#1#; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- NRD Pulse Length - NRD_PULSE : PULSE0_NRD_PULSE_Field := 16#1#; + NRD_PULSE : PULSE_NRD_PULSE_Field := 16#1#; -- unspecified Reserved_22_23 : ATSAM3X8E.UInt2 := 16#0#; -- NCS Pulse Length in READ Access - NCS_RD_PULSE : PULSE0_NCS_RD_PULSE_Field := 16#1#; + NCS_RD_PULSE : PULSE_NCS_RD_PULSE_Field := 16#1#; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PULSE_Register use record NWE_PULSE at 0 range 0 .. 5; @@ -1167,25 +1183,21 @@ package ATSAM3X8E.EBI is Reserved_30_31 at 0 range 30 .. 31; end record; - -------------------- - -- CYCLE_Register -- - -------------------- - - subtype CYCLE0_NWE_CYCLE_Field is ATSAM3X8E.UInt9; - subtype CYCLE0_NRD_CYCLE_Field is ATSAM3X8E.UInt9; + subtype CYCLE_NWE_CYCLE_Field is ATSAM3X8E.UInt9; + subtype CYCLE_NRD_CYCLE_Field is ATSAM3X8E.UInt9; -- SMC Cycle Register (CS_number = 0) type CYCLE_Register is record -- Total Write Cycle Length - NWE_CYCLE : CYCLE0_NWE_CYCLE_Field := 16#3#; + NWE_CYCLE : CYCLE_NWE_CYCLE_Field := 16#3#; -- unspecified Reserved_9_15 : ATSAM3X8E.UInt7 := 16#0#; -- Total Read Cycle Length - NRD_CYCLE : CYCLE0_NRD_CYCLE_Field := 16#3#; + NRD_CYCLE : CYCLE_NRD_CYCLE_Field := 16#3#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CYCLE_Register use record NWE_CYCLE at 0 range 0 .. 8; @@ -1194,43 +1206,39 @@ package ATSAM3X8E.EBI is Reserved_25_31 at 0 range 25 .. 31; end record; - ---------------------- - -- TIMINGS_Register -- - ---------------------- - - subtype TIMINGS0_TCLR_Field is ATSAM3X8E.UInt4; - subtype TIMINGS0_TADL_Field is ATSAM3X8E.UInt4; - subtype TIMINGS0_TAR_Field is ATSAM3X8E.UInt4; - subtype TIMINGS0_OCMS_Field is ATSAM3X8E.Bit; - subtype TIMINGS0_TRR_Field is ATSAM3X8E.UInt4; - subtype TIMINGS0_TWB_Field is ATSAM3X8E.UInt4; - subtype TIMINGS0_RBNSEL_Field is ATSAM3X8E.UInt3; - subtype TIMINGS0_NFSEL_Field is ATSAM3X8E.Bit; + subtype TIMINGS_TCLR_Field is ATSAM3X8E.UInt4; + subtype TIMINGS_TADL_Field is ATSAM3X8E.UInt4; + subtype TIMINGS_TAR_Field is ATSAM3X8E.UInt4; + subtype TIMINGS_OCMS_Field is ATSAM3X8E.Bit; + subtype TIMINGS_TRR_Field is ATSAM3X8E.UInt4; + subtype TIMINGS_TWB_Field is ATSAM3X8E.UInt4; + subtype TIMINGS_RBNSEL_Field is ATSAM3X8E.UInt3; + subtype TIMINGS_NFSEL_Field is ATSAM3X8E.Bit; -- SMC Timings Register (CS_number = 0) type TIMINGS_Register is record -- CLE to REN Low Delay - TCLR : TIMINGS0_TCLR_Field := 16#0#; + TCLR : TIMINGS_TCLR_Field := 16#0#; -- ALE to Data Start - TADL : TIMINGS0_TADL_Field := 16#0#; + TADL : TIMINGS_TADL_Field := 16#0#; -- ALE to REN Low Delay - TAR : TIMINGS0_TAR_Field := 16#0#; + TAR : TIMINGS_TAR_Field := 16#0#; -- Off Chip Memory Scrambling Enable - OCMS : TIMINGS0_OCMS_Field := 16#0#; + OCMS : TIMINGS_OCMS_Field := 16#0#; -- unspecified Reserved_13_15 : ATSAM3X8E.UInt3 := 16#0#; -- Ready to REN Low Delay - TRR : TIMINGS0_TRR_Field := 16#0#; + TRR : TIMINGS_TRR_Field := 16#0#; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4 := 16#0#; -- WEN High to REN to Busy - TWB : TIMINGS0_TWB_Field := 16#0#; + TWB : TIMINGS_TWB_Field := 16#0#; -- Ready/Busy Line Selection - RBNSEL : TIMINGS0_RBNSEL_Field := 16#0#; + RBNSEL : TIMINGS_RBNSEL_Field := 16#0#; -- NAND Flash Selection - NFSEL : TIMINGS0_NFSEL_Field := 16#0#; + NFSEL : TIMINGS_NFSEL_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TIMINGS_Register use record TCLR at 0 range 0 .. 3; @@ -1245,90 +1253,82 @@ package ATSAM3X8E.EBI is NFSEL at 0 range 31 .. 31; end record; - ------------------- - -- MODE_Register -- - ------------------- - - type READ_MODE_Field is - ( - -- The Read operation is controlled by the NCS signal. + type MODE0_READ_MODE_Field is + (-- The Read operation is controlled by the NCS signal. Ncs_Ctrl, -- The Read operation is controlled by the NRD signal. Nrd_Ctrl) with Size => 1; - for READ_MODE_Field use + for MODE0_READ_MODE_Field use (Ncs_Ctrl => 0, Nrd_Ctrl => 1); - type WRITE_MODE_Field is - ( - -- The Write operation is controller by the NCS signal. + type MODE0_WRITE_MODE_Field is + (-- The Write operation is controller by the NCS signal. Ncs_Ctrl, -- The Write operation is controlled by the NWE signal. Nwe_Ctrl) with Size => 1; - for WRITE_MODE_Field use + for MODE0_WRITE_MODE_Field use (Ncs_Ctrl => 0, Nwe_Ctrl => 1); -- NWAIT Mode - type EXNW_MODE_Field is - ( - -- Disabled + type MODE0_EXNW_MODE_Field is + (-- Disabled Disabled, -- Frozen Mode Frozen, -- Ready Mode Ready) with Size => 2; - for EXNW_MODE_Field use + for MODE0_EXNW_MODE_Field use (Disabled => 0, Frozen => 2, Ready => 3); - subtype MODE0_BAT_Field is ATSAM3X8E.Bit; + subtype MODE_BAT_Field is ATSAM3X8E.Bit; -- Data Bus Width - type DBW_Field is - ( - -- 8-bit bus + type MODE0_DBW_Field is + (-- 8-bit bus Bit_8, -- 16-bit bus Bit_16) with Size => 1; - for DBW_Field use + for MODE0_DBW_Field use (Bit_8 => 0, Bit_16 => 1); - subtype MODE0_TDF_CYCLES_Field is ATSAM3X8E.UInt4; - subtype MODE0_TDF_MODE_Field is ATSAM3X8E.Bit; + subtype MODE_TDF_CYCLES_Field is ATSAM3X8E.UInt4; + subtype MODE_TDF_MODE_Field is ATSAM3X8E.Bit; -- SMC Mode Register (CS_number = 0) type MODE_Register is record - READ_MODE : READ_MODE_Field := Nrd_Ctrl; - WRITE_MODE : WRITE_MODE_Field := Nwe_Ctrl; + READ_MODE : MODE0_READ_MODE_Field := ATSAM3X8E.EBI.Nrd_Ctrl; + WRITE_MODE : MODE0_WRITE_MODE_Field := ATSAM3X8E.EBI.Nwe_Ctrl; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- NWAIT Mode - EXNW_MODE : EXNW_MODE_Field := Disabled; + EXNW_MODE : MODE0_EXNW_MODE_Field := ATSAM3X8E.EBI.Disabled; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Byte Access Type - BAT : MODE0_BAT_Field := 16#0#; + BAT : MODE_BAT_Field := 16#0#; -- unspecified Reserved_9_11 : ATSAM3X8E.UInt3 := 16#0#; -- Data Bus Width - DBW : DBW_Field := Bit_8; + DBW : MODE0_DBW_Field := ATSAM3X8E.EBI.Bit_8; -- unspecified Reserved_13_15 : ATSAM3X8E.UInt3 := 16#0#; -- Data Float Time - TDF_CYCLES : MODE0_TDF_CYCLES_Field := 16#0#; + TDF_CYCLES : MODE_TDF_CYCLES_Field := 16#0#; -- TDF Optimization - TDF_MODE : MODE0_TDF_MODE_Field := 16#0#; + TDF_MODE : MODE_TDF_MODE_Field := 16#0#; -- unspecified Reserved_21_31 : ATSAM3X8E.UInt11 := 16#80#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MODE_Register use record READ_MODE at 0 range 0 .. 0; @@ -1345,75 +1345,63 @@ package ATSAM3X8E.EBI is Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------- - -- OCMS_Register -- - ------------------- - - subtype OCMS_SMSE_Field is ATSAM3X8E.Bit; - subtype OCMS_SRSE_Field is ATSAM3X8E.Bit; + subtype SMC_OCMS_SMSE_Field is ATSAM3X8E.Bit; + subtype SMC_OCMS_SRSE_Field is ATSAM3X8E.Bit; -- SMC OCMS Register - type OCMS_Register is record + type SMC_OCMS_Register is record -- Static Memory Controller Scrambling Enable - SMSE : OCMS_SMSE_Field := 16#0#; + SMSE : SMC_OCMS_SMSE_Field := 16#0#; -- SRAM Scrambling Enable - SRSE : OCMS_SRSE_Field := 16#0#; + SRSE : SMC_OCMS_SRSE_Field := 16#0#; -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OCMS_Register use record + for SMC_OCMS_Register use record SMSE at 0 range 0 .. 0; SRSE at 0 range 1 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- WPCR_Register -- - ------------------- - - subtype WPCR_WP_EN_Field is ATSAM3X8E.Bit; - subtype WPCR_WP_KEY_Field is ATSAM3X8E.UInt24; + subtype SMC_WPCR_WP_EN_Field is ATSAM3X8E.Bit; + subtype SMC_WPCR_WP_KEY_Field is ATSAM3X8E.UInt24; -- Write Protection Control Register - type WPCR_Register is record + type SMC_WPCR_Register is record -- Write-only. Write Protection Enable - WP_EN : WPCR_WP_EN_Field := 16#0#; + WP_EN : SMC_WPCR_WP_EN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write-only. Write Protection KEY password - WP_KEY : WPCR_WP_KEY_Field := 16#0#; + WP_KEY : SMC_WPCR_WP_KEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPCR_Register use record + for SMC_WPCR_Register use record WP_EN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WP_KEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WP_VS_Field is ATSAM3X8E.UInt4; - subtype WPSR_WP_VSRC_Field is ATSAM3X8E.Short; + subtype SMC_WPSR_WP_VS_Field is ATSAM3X8E.UInt4; + subtype SMC_WPSR_WP_VSRC_Field is ATSAM3X8E.UInt16; -- Write Protection Status Register - type WPSR_Register is record + type SMC_WPSR_Register is record -- Read-only. Write Protection Violation Status - WP_VS : WPSR_WP_VS_Field := 16#0#; + WP_VS : SMC_WPSR_WP_VS_Field; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4; -- Read-only. Write Protection Violation Source - WP_VSRC : WPSR_WP_VSRC_Field := 16#0#; + WP_VSRC : SMC_WPSR_WP_VSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for SMC_WPSR_Register use record WP_VS at 0 range 0 .. 3; Reserved_4_7 at 0 range 4 .. 7; WP_VSRC at 0 range 8 .. 23; @@ -1424,231 +1412,354 @@ package ATSAM3X8E.EBI is -- Peripherals -- ----------------- + type SMC_Disc is + (Default, + W9Bit, + W8Bit); + -- Static Memory Controller - type SMC_Peripheral is record + type SMC_Peripheral + (Discriminent : SMC_Disc := Default) + is record -- SMC NFC Configuration Register - CFG : CFG_Register; + CFG : aliased SMC_CFG_Register; + pragma Volatile_Full_Access (CFG); -- SMC NFC Control Register - CTRL : CTRL_Register; + CTRL : aliased SMC_CTRL_Register; + pragma Volatile_Full_Access (CTRL); -- SMC NFC Status Register - SR : SR_Register; + SR : aliased SMC_SR_Register; + pragma Volatile_Full_Access (SR); -- SMC NFC Interrupt Enable Register - IER : IER_Register; + IER : aliased SMC_IER_Register; + pragma Volatile_Full_Access (IER); -- SMC NFC Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased SMC_IDR_Register; + pragma Volatile_Full_Access (IDR); -- SMC NFC Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased SMC_IMR_Register; + pragma Volatile_Full_Access (IMR); -- SMC NFC Address Cycle Zero Register - ADDR : ADDR_Register; + ADDR : aliased SMC_ADDR_Register; + pragma Volatile_Full_Access (ADDR); -- SMC Bank Address Register - BANK : BANK_Register; + BANK : aliased SMC_BANK_Register; + pragma Volatile_Full_Access (BANK); -- SMC ECC Control Register - ECC_CTRL : ECC_CTRL_Register; + ECC_CTRL : aliased SMC_ECC_CTRL_Register; + pragma Volatile_Full_Access (ECC_CTRL); -- SMC ECC Mode Register - ECC_MD : ECC_MD_Register; + ECC_MD : aliased SMC_ECC_MD_Register; + pragma Volatile_Full_Access (ECC_MD); -- SMC ECC Status 1 Register - ECC_SR1 : ECC_SR_Register; - -- SMC ECC Parity 0 Register - ECC_PR0 : ECC_PR0_Register; - -- SMC ECC parity 1 Register - ECC_PR1 : ECC_PR1_Register; + ECC_SR1 : aliased SMC_ECC_SR1_Register; + pragma Volatile_Full_Access (ECC_SR1); -- SMC ECC status 2 Register - ECC_SR2 : ECC_SR_Register; - -- SMC ECC parity 2 Register - ECC_PR2 : ECC_PR_Register; - -- SMC ECC parity 3 Register - ECC_PR3 : ECC_PR_Register; - -- SMC ECC parity 4 Register - ECC_PR4 : ECC_PR_Register; - -- SMC ECC parity 5 Register - ECC_PR5 : ECC_PR_Register; - -- SMC ECC parity 6 Register - ECC_PR6 : ECC_PR_Register; - -- SMC ECC parity 7 Register - ECC_PR7 : ECC_PR_Register; + ECC_SR2 : aliased SMC_ECC_SR2_Register; + pragma Volatile_Full_Access (ECC_SR2); -- SMC ECC parity 8 Register - ECC_PR8 : ECC_PR_Register_1; + ECC_PR8 : aliased ECC_PR_Register_1; + pragma Volatile_Full_Access (ECC_PR8); -- SMC ECC parity 9 Register - ECC_PR9 : ECC_PR_Register_1; + ECC_PR9 : aliased ECC_PR_Register_1; + pragma Volatile_Full_Access (ECC_PR9); -- SMC ECC parity 10 Register - ECC_PR10 : ECC_PR_Register_1; + ECC_PR10 : aliased ECC_PR_Register_1; + pragma Volatile_Full_Access (ECC_PR10); -- SMC ECC parity 11 Register - ECC_PR11 : ECC_PR_Register_1; + ECC_PR11 : aliased ECC_PR_Register_1; + pragma Volatile_Full_Access (ECC_PR11); -- SMC ECC parity 12 Register - ECC_PR12 : ECC_PR_Register_1; + ECC_PR12 : aliased ECC_PR_Register_1; + pragma Volatile_Full_Access (ECC_PR12); -- SMC ECC parity 13 Register - ECC_PR13 : ECC_PR_Register_1; + ECC_PR13 : aliased ECC_PR_Register_1; + pragma Volatile_Full_Access (ECC_PR13); -- SMC ECC parity 14 Register - ECC_PR14 : ECC_PR_Register_1; + ECC_PR14 : aliased ECC_PR_Register_1; + pragma Volatile_Full_Access (ECC_PR14); -- SMC ECC parity 15 Register - ECC_PR15 : ECC_PR_Register_1; + ECC_PR15 : aliased ECC_PR_Register_1; + pragma Volatile_Full_Access (ECC_PR15); -- SMC Setup Register (CS_number = 0) - SETUP0 : SETUP_Register; + SETUP0 : aliased SETUP_Register; + pragma Volatile_Full_Access (SETUP0); -- SMC Pulse Register (CS_number = 0) - PULSE0 : PULSE_Register; + PULSE0 : aliased PULSE_Register; + pragma Volatile_Full_Access (PULSE0); -- SMC Cycle Register (CS_number = 0) - CYCLE0 : CYCLE_Register; + CYCLE0 : aliased CYCLE_Register; + pragma Volatile_Full_Access (CYCLE0); -- SMC Timings Register (CS_number = 0) - TIMINGS0 : TIMINGS_Register; + TIMINGS0 : aliased TIMINGS_Register; + pragma Volatile_Full_Access (TIMINGS0); -- SMC Mode Register (CS_number = 0) - MODE0 : MODE_Register; + MODE0 : aliased MODE_Register; + pragma Volatile_Full_Access (MODE0); -- SMC Setup Register (CS_number = 1) - SETUP1 : SETUP_Register; + SETUP1 : aliased SETUP_Register; + pragma Volatile_Full_Access (SETUP1); -- SMC Pulse Register (CS_number = 1) - PULSE1 : PULSE_Register; + PULSE1 : aliased PULSE_Register; + pragma Volatile_Full_Access (PULSE1); -- SMC Cycle Register (CS_number = 1) - CYCLE1 : CYCLE_Register; + CYCLE1 : aliased CYCLE_Register; + pragma Volatile_Full_Access (CYCLE1); -- SMC Timings Register (CS_number = 1) - TIMINGS1 : TIMINGS_Register; + TIMINGS1 : aliased TIMINGS_Register; + pragma Volatile_Full_Access (TIMINGS1); -- SMC Mode Register (CS_number = 1) - MODE1 : MODE_Register; + MODE1 : aliased MODE_Register; + pragma Volatile_Full_Access (MODE1); -- SMC Setup Register (CS_number = 2) - SETUP2 : SETUP_Register; + SETUP2 : aliased SETUP_Register; + pragma Volatile_Full_Access (SETUP2); -- SMC Pulse Register (CS_number = 2) - PULSE2 : PULSE_Register; + PULSE2 : aliased PULSE_Register; + pragma Volatile_Full_Access (PULSE2); -- SMC Cycle Register (CS_number = 2) - CYCLE2 : CYCLE_Register; + CYCLE2 : aliased CYCLE_Register; + pragma Volatile_Full_Access (CYCLE2); -- SMC Timings Register (CS_number = 2) - TIMINGS2 : TIMINGS_Register; + TIMINGS2 : aliased TIMINGS_Register; + pragma Volatile_Full_Access (TIMINGS2); -- SMC Mode Register (CS_number = 2) - MODE2 : MODE_Register; + MODE2 : aliased MODE_Register; + pragma Volatile_Full_Access (MODE2); -- SMC Setup Register (CS_number = 3) - SETUP3 : SETUP_Register; + SETUP3 : aliased SETUP_Register; + pragma Volatile_Full_Access (SETUP3); -- SMC Pulse Register (CS_number = 3) - PULSE3 : PULSE_Register; + PULSE3 : aliased PULSE_Register; + pragma Volatile_Full_Access (PULSE3); -- SMC Cycle Register (CS_number = 3) - CYCLE3 : CYCLE_Register; + CYCLE3 : aliased CYCLE_Register; + pragma Volatile_Full_Access (CYCLE3); -- SMC Timings Register (CS_number = 3) - TIMINGS3 : TIMINGS_Register; + TIMINGS3 : aliased TIMINGS_Register; + pragma Volatile_Full_Access (TIMINGS3); -- SMC Mode Register (CS_number = 3) - MODE3 : MODE_Register; + MODE3 : aliased MODE_Register; + pragma Volatile_Full_Access (MODE3); -- SMC Setup Register (CS_number = 4) - SETUP4 : SETUP_Register; + SETUP4 : aliased SETUP_Register; + pragma Volatile_Full_Access (SETUP4); -- SMC Pulse Register (CS_number = 4) - PULSE4 : PULSE_Register; + PULSE4 : aliased PULSE_Register; + pragma Volatile_Full_Access (PULSE4); -- SMC Cycle Register (CS_number = 4) - CYCLE4 : CYCLE_Register; + CYCLE4 : aliased CYCLE_Register; + pragma Volatile_Full_Access (CYCLE4); -- SMC Timings Register (CS_number = 4) - TIMINGS4 : TIMINGS_Register; + TIMINGS4 : aliased TIMINGS_Register; + pragma Volatile_Full_Access (TIMINGS4); -- SMC Mode Register (CS_number = 4) - MODE4 : MODE_Register; + MODE4 : aliased MODE_Register; + pragma Volatile_Full_Access (MODE4); -- SMC Setup Register (CS_number = 5) - SETUP5 : SETUP_Register; + SETUP5 : aliased SETUP_Register; + pragma Volatile_Full_Access (SETUP5); -- SMC Pulse Register (CS_number = 5) - PULSE5 : PULSE_Register; + PULSE5 : aliased PULSE_Register; + pragma Volatile_Full_Access (PULSE5); -- SMC Cycle Register (CS_number = 5) - CYCLE5 : CYCLE_Register; + CYCLE5 : aliased CYCLE_Register; + pragma Volatile_Full_Access (CYCLE5); -- SMC Timings Register (CS_number = 5) - TIMINGS5 : TIMINGS_Register; + TIMINGS5 : aliased TIMINGS_Register; + pragma Volatile_Full_Access (TIMINGS5); -- SMC Mode Register (CS_number = 5) - MODE5 : MODE_Register; + MODE5 : aliased MODE_Register; + pragma Volatile_Full_Access (MODE5); -- SMC Setup Register (CS_number = 6) - SETUP6 : SETUP_Register; + SETUP6 : aliased SETUP_Register; + pragma Volatile_Full_Access (SETUP6); -- SMC Pulse Register (CS_number = 6) - PULSE6 : PULSE_Register; + PULSE6 : aliased PULSE_Register; + pragma Volatile_Full_Access (PULSE6); -- SMC Cycle Register (CS_number = 6) - CYCLE6 : CYCLE_Register; + CYCLE6 : aliased CYCLE_Register; + pragma Volatile_Full_Access (CYCLE6); -- SMC Timings Register (CS_number = 6) - TIMINGS6 : TIMINGS_Register; + TIMINGS6 : aliased TIMINGS_Register; + pragma Volatile_Full_Access (TIMINGS6); -- SMC Mode Register (CS_number = 6) - MODE6 : MODE_Register; + MODE6 : aliased MODE_Register; + pragma Volatile_Full_Access (MODE6); -- SMC Setup Register (CS_number = 7) - SETUP7 : SETUP_Register; + SETUP7 : aliased SETUP_Register; + pragma Volatile_Full_Access (SETUP7); -- SMC Pulse Register (CS_number = 7) - PULSE7 : PULSE_Register; + PULSE7 : aliased PULSE_Register; + pragma Volatile_Full_Access (PULSE7); -- SMC Cycle Register (CS_number = 7) - CYCLE7 : CYCLE_Register; + CYCLE7 : aliased CYCLE_Register; + pragma Volatile_Full_Access (CYCLE7); -- SMC Timings Register (CS_number = 7) - TIMINGS7 : TIMINGS_Register; + TIMINGS7 : aliased TIMINGS_Register; + pragma Volatile_Full_Access (TIMINGS7); -- SMC Mode Register (CS_number = 7) - MODE7 : MODE_Register; + MODE7 : aliased MODE_Register; + pragma Volatile_Full_Access (MODE7); -- SMC OCMS Register - OCMS : OCMS_Register; + OCMS : aliased SMC_OCMS_Register; + pragma Volatile_Full_Access (OCMS); -- SMC OCMS KEY1 Register - KEY1 : ATSAM3X8E.Word; + KEY1 : aliased ATSAM3X8E.UInt32; -- SMC OCMS KEY2 Register - KEY2 : ATSAM3X8E.Word; + KEY2 : aliased ATSAM3X8E.UInt32; -- Write Protection Control Register - WPCR : WPCR_Register; + WPCR : aliased SMC_WPCR_Register; + pragma Volatile_Full_Access (WPCR); -- Write Protection Status Register - WPSR : WPSR_Register; + WPSR : aliased SMC_WPSR_Register; + pragma Volatile_Full_Access (WPSR); + case Discriminent is + when Default => + -- SMC ECC Parity 0 Register + ECC_PR0 : aliased SMC_ECC_PR0_Register; + pragma Volatile_Full_Access (ECC_PR0); + -- SMC ECC parity 1 Register + ECC_PR1 : aliased SMC_ECC_PR1_Register; + pragma Volatile_Full_Access (ECC_PR1); + -- SMC ECC parity 2 Register + ECC_PR2 : aliased ECC_PR_Register; + pragma Volatile_Full_Access (ECC_PR2); + -- SMC ECC parity 3 Register + ECC_PR3 : aliased ECC_PR_Register; + pragma Volatile_Full_Access (ECC_PR3); + -- SMC ECC parity 4 Register + ECC_PR4 : aliased ECC_PR_Register; + pragma Volatile_Full_Access (ECC_PR4); + -- SMC ECC parity 5 Register + ECC_PR5 : aliased ECC_PR_Register; + pragma Volatile_Full_Access (ECC_PR5); + -- SMC ECC parity 6 Register + ECC_PR6 : aliased ECC_PR_Register; + pragma Volatile_Full_Access (ECC_PR6); + -- SMC ECC parity 7 Register + ECC_PR7 : aliased ECC_PR_Register; + pragma Volatile_Full_Access (ECC_PR7); + when W9Bit => + -- SMC ECC Parity 0 Register + ECC_PR0_W9BIT : aliased SMC_ECC_PR0_W9BIT_Register; + pragma Volatile_Full_Access (ECC_PR0_W9BIT); + -- SMC ECC parity 1 Register + ECC_PR1_W9BIT : aliased SMC_ECC_PR1_W9BIT_Register; + pragma Volatile_Full_Access (ECC_PR1_W9BIT); + when W8Bit => + -- SMC ECC Parity 0 Register + ECC_PR0_W8BIT : aliased SMC_ECC_PR0_W8BIT_Register; + pragma Volatile_Full_Access (ECC_PR0_W8BIT); + -- SMC ECC parity 1 Register + ECC_PR1_W8BIT : aliased SMC_ECC_PR1_W8BIT_Register; + pragma Volatile_Full_Access (ECC_PR1_W8BIT); + -- SMC ECC parity 2 Register + ECC_PR2_W8BIT : aliased SMC_ECC_PR2_W8BIT_Register; + pragma Volatile_Full_Access (ECC_PR2_W8BIT); + -- SMC ECC parity 3 Register + ECC_PR3_W8BIT : aliased SMC_ECC_PR3_W8BIT_Register; + pragma Volatile_Full_Access (ECC_PR3_W8BIT); + -- SMC ECC parity 4 Register + ECC_PR4_W8BIT : aliased SMC_ECC_PR4_W8BIT_Register; + pragma Volatile_Full_Access (ECC_PR4_W8BIT); + -- SMC ECC parity 5 Register + ECC_PR5_W8BIT : aliased SMC_ECC_PR5_W8BIT_Register; + pragma Volatile_Full_Access (ECC_PR5_W8BIT); + -- SMC ECC parity 6 Register + ECC_PR6_W8BIT : aliased SMC_ECC_PR6_W8BIT_Register; + pragma Volatile_Full_Access (ECC_PR6_W8BIT); + -- SMC ECC parity 7 Register + ECC_PR7_W8BIT : aliased SMC_ECC_PR7_W8BIT_Register; + pragma Volatile_Full_Access (ECC_PR7_W8BIT); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for SMC_Peripheral use record - CFG at 0 range 0 .. 31; - CTRL at 4 range 0 .. 31; - SR at 8 range 0 .. 31; - IER at 12 range 0 .. 31; - IDR at 16 range 0 .. 31; - IMR at 20 range 0 .. 31; - ADDR at 24 range 0 .. 31; - BANK at 28 range 0 .. 31; - ECC_CTRL at 32 range 0 .. 31; - ECC_MD at 36 range 0 .. 31; - ECC_SR1 at 40 range 0 .. 31; - ECC_PR0 at 44 range 0 .. 31; - ECC_PR1 at 48 range 0 .. 31; - ECC_SR2 at 52 range 0 .. 31; - ECC_PR2 at 56 range 0 .. 31; - ECC_PR3 at 60 range 0 .. 31; - ECC_PR4 at 64 range 0 .. 31; - ECC_PR5 at 68 range 0 .. 31; - ECC_PR6 at 72 range 0 .. 31; - ECC_PR7 at 76 range 0 .. 31; - ECC_PR8 at 80 range 0 .. 31; - ECC_PR9 at 84 range 0 .. 31; - ECC_PR10 at 88 range 0 .. 31; - ECC_PR11 at 92 range 0 .. 31; - ECC_PR12 at 96 range 0 .. 31; - ECC_PR13 at 100 range 0 .. 31; - ECC_PR14 at 104 range 0 .. 31; - ECC_PR15 at 108 range 0 .. 31; - SETUP0 at 112 range 0 .. 31; - PULSE0 at 116 range 0 .. 31; - CYCLE0 at 120 range 0 .. 31; - TIMINGS0 at 124 range 0 .. 31; - MODE0 at 128 range 0 .. 31; - SETUP1 at 132 range 0 .. 31; - PULSE1 at 136 range 0 .. 31; - CYCLE1 at 140 range 0 .. 31; - TIMINGS1 at 144 range 0 .. 31; - MODE1 at 148 range 0 .. 31; - SETUP2 at 152 range 0 .. 31; - PULSE2 at 156 range 0 .. 31; - CYCLE2 at 160 range 0 .. 31; - TIMINGS2 at 164 range 0 .. 31; - MODE2 at 168 range 0 .. 31; - SETUP3 at 172 range 0 .. 31; - PULSE3 at 176 range 0 .. 31; - CYCLE3 at 180 range 0 .. 31; - TIMINGS3 at 184 range 0 .. 31; - MODE3 at 188 range 0 .. 31; - SETUP4 at 192 range 0 .. 31; - PULSE4 at 196 range 0 .. 31; - CYCLE4 at 200 range 0 .. 31; - TIMINGS4 at 204 range 0 .. 31; - MODE4 at 208 range 0 .. 31; - SETUP5 at 212 range 0 .. 31; - PULSE5 at 216 range 0 .. 31; - CYCLE5 at 220 range 0 .. 31; - TIMINGS5 at 224 range 0 .. 31; - MODE5 at 228 range 0 .. 31; - SETUP6 at 232 range 0 .. 31; - PULSE6 at 236 range 0 .. 31; - CYCLE6 at 240 range 0 .. 31; - TIMINGS6 at 244 range 0 .. 31; - MODE6 at 248 range 0 .. 31; - SETUP7 at 252 range 0 .. 31; - PULSE7 at 256 range 0 .. 31; - CYCLE7 at 260 range 0 .. 31; - TIMINGS7 at 264 range 0 .. 31; - MODE7 at 268 range 0 .. 31; - OCMS at 272 range 0 .. 31; - KEY1 at 276 range 0 .. 31; - KEY2 at 280 range 0 .. 31; - WPCR at 484 range 0 .. 31; - WPSR at 488 range 0 .. 31; + CFG at 16#0# range 0 .. 31; + CTRL at 16#4# range 0 .. 31; + SR at 16#8# range 0 .. 31; + IER at 16#C# range 0 .. 31; + IDR at 16#10# range 0 .. 31; + IMR at 16#14# range 0 .. 31; + ADDR at 16#18# range 0 .. 31; + BANK at 16#1C# range 0 .. 31; + ECC_CTRL at 16#20# range 0 .. 31; + ECC_MD at 16#24# range 0 .. 31; + ECC_SR1 at 16#28# range 0 .. 31; + ECC_SR2 at 16#34# range 0 .. 31; + ECC_PR8 at 16#50# range 0 .. 31; + ECC_PR9 at 16#54# range 0 .. 31; + ECC_PR10 at 16#58# range 0 .. 31; + ECC_PR11 at 16#5C# range 0 .. 31; + ECC_PR12 at 16#60# range 0 .. 31; + ECC_PR13 at 16#64# range 0 .. 31; + ECC_PR14 at 16#68# range 0 .. 31; + ECC_PR15 at 16#6C# range 0 .. 31; + SETUP0 at 16#70# range 0 .. 31; + PULSE0 at 16#74# range 0 .. 31; + CYCLE0 at 16#78# range 0 .. 31; + TIMINGS0 at 16#7C# range 0 .. 31; + MODE0 at 16#80# range 0 .. 31; + SETUP1 at 16#84# range 0 .. 31; + PULSE1 at 16#88# range 0 .. 31; + CYCLE1 at 16#8C# range 0 .. 31; + TIMINGS1 at 16#90# range 0 .. 31; + MODE1 at 16#94# range 0 .. 31; + SETUP2 at 16#98# range 0 .. 31; + PULSE2 at 16#9C# range 0 .. 31; + CYCLE2 at 16#A0# range 0 .. 31; + TIMINGS2 at 16#A4# range 0 .. 31; + MODE2 at 16#A8# range 0 .. 31; + SETUP3 at 16#AC# range 0 .. 31; + PULSE3 at 16#B0# range 0 .. 31; + CYCLE3 at 16#B4# range 0 .. 31; + TIMINGS3 at 16#B8# range 0 .. 31; + MODE3 at 16#BC# range 0 .. 31; + SETUP4 at 16#C0# range 0 .. 31; + PULSE4 at 16#C4# range 0 .. 31; + CYCLE4 at 16#C8# range 0 .. 31; + TIMINGS4 at 16#CC# range 0 .. 31; + MODE4 at 16#D0# range 0 .. 31; + SETUP5 at 16#D4# range 0 .. 31; + PULSE5 at 16#D8# range 0 .. 31; + CYCLE5 at 16#DC# range 0 .. 31; + TIMINGS5 at 16#E0# range 0 .. 31; + MODE5 at 16#E4# range 0 .. 31; + SETUP6 at 16#E8# range 0 .. 31; + PULSE6 at 16#EC# range 0 .. 31; + CYCLE6 at 16#F0# range 0 .. 31; + TIMINGS6 at 16#F4# range 0 .. 31; + MODE6 at 16#F8# range 0 .. 31; + SETUP7 at 16#FC# range 0 .. 31; + PULSE7 at 16#100# range 0 .. 31; + CYCLE7 at 16#104# range 0 .. 31; + TIMINGS7 at 16#108# range 0 .. 31; + MODE7 at 16#10C# range 0 .. 31; + OCMS at 16#110# range 0 .. 31; + KEY1 at 16#114# range 0 .. 31; + KEY2 at 16#118# range 0 .. 31; + WPCR at 16#1E4# range 0 .. 31; + WPSR at 16#1E8# range 0 .. 31; + ECC_PR0 at 16#2C# range 0 .. 31; + ECC_PR1 at 16#30# range 0 .. 31; + ECC_PR2 at 16#38# range 0 .. 31; + ECC_PR3 at 16#3C# range 0 .. 31; + ECC_PR4 at 16#40# range 0 .. 31; + ECC_PR5 at 16#44# range 0 .. 31; + ECC_PR6 at 16#48# range 0 .. 31; + ECC_PR7 at 16#4C# range 0 .. 31; + ECC_PR0_W9BIT at 16#2C# range 0 .. 31; + ECC_PR1_W9BIT at 16#30# range 0 .. 31; + ECC_PR0_W8BIT at 16#2C# range 0 .. 31; + ECC_PR1_W8BIT at 16#30# range 0 .. 31; + ECC_PR2_W8BIT at 16#38# range 0 .. 31; + ECC_PR3_W8BIT at 16#3C# range 0 .. 31; + ECC_PR4_W8BIT at 16#40# range 0 .. 31; + ECC_PR5_W8BIT at 16#44# range 0 .. 31; + ECC_PR6_W8BIT at 16#48# range 0 .. 31; + ECC_PR7_W8BIT at 16#4C# range 0 .. 31; end record; -- Static Memory Controller diff --git a/arduino-due/atsam3x8e/atsam3x8e-efc.ads b/arduino-due/atsam3x8e/atsam3x8e-efc.ads index b4445ec..677e4e9 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-efc.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-efc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,37 +14,33 @@ package ATSAM3X8E.EFC is -- Registers -- --------------- - ------------------ - -- FMR_Register -- - ------------------ - - subtype FMR_FRDY_Field is ATSAM3X8E.Bit; - subtype FMR_FWS_Field is ATSAM3X8E.UInt4; - subtype FMR_SCOD_Field is ATSAM3X8E.Bit; - subtype FMR_FAM_Field is ATSAM3X8E.Bit; + subtype EFC0_FMR_FRDY_Field is ATSAM3X8E.Bit; + subtype EFC0_FMR_FWS_Field is ATSAM3X8E.UInt4; + subtype EFC0_FMR_SCOD_Field is ATSAM3X8E.Bit; + subtype EFC0_FMR_FAM_Field is ATSAM3X8E.Bit; -- EEFC Flash Mode Register - type FMR_Register is record + type EFC0_FMR_Register is record -- Ready Interrupt Enable - FRDY : FMR_FRDY_Field := 16#0#; + FRDY : EFC0_FMR_FRDY_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Flash Wait State - FWS : FMR_FWS_Field := 16#0#; + FWS : EFC0_FMR_FWS_Field := 16#0#; -- unspecified Reserved_12_15 : ATSAM3X8E.UInt4 := 16#0#; -- Sequential Code Optimization Disable - SCOD : FMR_SCOD_Field := 16#0#; + SCOD : EFC0_FMR_SCOD_Field := 16#0#; -- unspecified Reserved_17_23 : ATSAM3X8E.UInt7 := 16#0#; -- Flash Access Mode - FAM : FMR_FAM_Field := 16#0#; + FAM : EFC0_FMR_FAM_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FMR_Register use record + for EFC0_FMR_Register use record FRDY at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; FWS at 0 range 8 .. 11; @@ -54,14 +51,9 @@ package ATSAM3X8E.EFC is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- FCR_Register -- - ------------------ - -- Flash Command - type FCMD_Field is - ( - -- Get Flash Descriptor + type FCR_FCMD_Field is + (-- Get Flash Descriptor Getd, -- Write page Wp, @@ -92,7 +84,7 @@ package ATSAM3X8E.EFC is -- Get CALIB Bit Gcalb) with Size => 8; - for FCMD_Field use + for FCR_FCMD_Field use (Getd => 0, Wp => 1, Wpl => 2, @@ -109,61 +101,56 @@ package ATSAM3X8E.EFC is Spui => 15, Gcalb => 16); - subtype FCR_FARG_Field is ATSAM3X8E.Short; + subtype EFC0_FCR_FARG_Field is ATSAM3X8E.UInt16; -- Flash Writing Protection Key - type FKEY_Field is - ( - -- Reset value for the field - Fkey_Field_Reset, - -- The 0x5A value enables the command defined by the bits of the - -- register. If the field is written with a different value, the write - -- is not performed and no action is started. + type FCR_FKEY_Field is + (-- Reset value for the field + Fcr_Fkey_Field_Reset, + -- The 0x5A value enables the command defined by the bits of the register. If +-- the field is written with a different value, the write is not performed and +-- no action is started. Passwd) with Size => 8; - for FKEY_Field use - (Fkey_Field_Reset => 0, + for FCR_FKEY_Field use + (Fcr_Fkey_Field_Reset => 0, Passwd => 90); -- EEFC Flash Command Register - type FCR_Register is record + type EFC0_FCR_Register is record -- Write-only. Flash Command - FCMD : FCMD_Field := Getd; + FCMD : FCR_FCMD_Field := ATSAM3X8E.EFC.Getd; -- Write-only. Flash Command Argument - FARG : FCR_FARG_Field := 16#0#; + FARG : EFC0_FCR_FARG_Field := 16#0#; -- Write-only. Flash Writing Protection Key - FKEY : FKEY_Field := Fkey_Field_Reset; + FKEY : FCR_FKEY_Field := Fcr_Fkey_Field_Reset; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FCR_Register use record + for EFC0_FCR_Register use record FCMD at 0 range 0 .. 7; FARG at 0 range 8 .. 23; FKEY at 0 range 24 .. 31; end record; - ------------------ - -- FSR_Register -- - ------------------ - - subtype FSR_FRDY_Field is ATSAM3X8E.Bit; - subtype FSR_FCMDE_Field is ATSAM3X8E.Bit; - subtype FSR_FLOCKE_Field is ATSAM3X8E.Bit; + subtype EFC0_FSR_FRDY_Field is ATSAM3X8E.Bit; + subtype EFC0_FSR_FCMDE_Field is ATSAM3X8E.Bit; + subtype EFC0_FSR_FLOCKE_Field is ATSAM3X8E.Bit; -- EEFC Flash Status Register - type FSR_Register is record + type EFC0_FSR_Register is record -- Read-only. Flash Ready Status - FRDY : FSR_FRDY_Field := 16#1#; + FRDY : EFC0_FSR_FRDY_Field; -- Read-only. Flash Command Error Status - FCMDE : FSR_FCMDE_Field := 16#0#; + FCMDE : EFC0_FSR_FCMDE_Field; -- Read-only. Flash Lock Error Status - FLOCKE : FSR_FLOCKE_Field := 16#0#; + FLOCKE : EFC0_FSR_FLOCKE_Field; -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FSR_Register use record + for EFC0_FSR_Register use record FRDY at 0 range 0 .. 0; FCMDE at 0 range 1 .. 1; FLOCKE at 0 range 2 .. 2; @@ -177,21 +164,24 @@ package ATSAM3X8E.EFC is -- Embedded Flash Controller 0 type EFC_Peripheral is record -- EEFC Flash Mode Register - FMR : FMR_Register; + FMR : aliased EFC0_FMR_Register; + pragma Volatile_Full_Access (FMR); -- EEFC Flash Command Register - FCR : FCR_Register; + FCR : aliased EFC0_FCR_Register; + pragma Volatile_Full_Access (FCR); -- EEFC Flash Status Register - FSR : FSR_Register; + FSR : aliased EFC0_FSR_Register; + pragma Volatile_Full_Access (FSR); -- EEFC Flash Result Register - FRR : ATSAM3X8E.Word; + FRR : aliased ATSAM3X8E.UInt32; end record with Volatile; for EFC_Peripheral use record - FMR at 0 range 0 .. 31; - FCR at 4 range 0 .. 31; - FSR at 8 range 0 .. 31; - FRR at 12 range 0 .. 31; + FMR at 16#0# range 0 .. 31; + FCR at 16#4# range 0 .. 31; + FSR at 16#8# range 0 .. 31; + FRR at 16#C# range 0 .. 31; end record; -- Embedded Flash Controller 0 diff --git a/arduino-due/atsam3x8e/atsam3x8e-emac.ads b/arduino-due/atsam3x8e/atsam3x8e-emac.ads index 86a9830..c3c695c 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-emac.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-emac.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,52 +15,48 @@ package ATSAM3X8E.EMAC is -- Registers -- --------------- - ------------------ - -- NCR_Register -- - ------------------ - - subtype NCR_LB_Field is ATSAM3X8E.Bit; - subtype NCR_LLB_Field is ATSAM3X8E.Bit; - subtype NCR_RE_Field is ATSAM3X8E.Bit; - subtype NCR_TE_Field is ATSAM3X8E.Bit; - subtype NCR_MPE_Field is ATSAM3X8E.Bit; - subtype NCR_CLRSTAT_Field is ATSAM3X8E.Bit; - subtype NCR_INCSTAT_Field is ATSAM3X8E.Bit; - subtype NCR_WESTAT_Field is ATSAM3X8E.Bit; - subtype NCR_BP_Field is ATSAM3X8E.Bit; - subtype NCR_TSTART_Field is ATSAM3X8E.Bit; - subtype NCR_THALT_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_LB_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_LLB_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_RE_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_TE_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_MPE_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_CLRSTAT_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_INCSTAT_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_WESTAT_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_BP_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_TSTART_Field is ATSAM3X8E.Bit; + subtype EMAC_NCR_THALT_Field is ATSAM3X8E.Bit; -- Network Control Register - type NCR_Register is record + type EMAC_NCR_Register is record -- LoopBack - LB : NCR_LB_Field := 16#0#; + LB : EMAC_NCR_LB_Field := 16#0#; -- Loopback local - LLB : NCR_LLB_Field := 16#0#; + LLB : EMAC_NCR_LLB_Field := 16#0#; -- Receive enable - RE : NCR_RE_Field := 16#0#; + RE : EMAC_NCR_RE_Field := 16#0#; -- Transmit enable - TE : NCR_TE_Field := 16#0#; + TE : EMAC_NCR_TE_Field := 16#0#; -- Management port enable - MPE : NCR_MPE_Field := 16#0#; + MPE : EMAC_NCR_MPE_Field := 16#0#; -- Clear statistics registers - CLRSTAT : NCR_CLRSTAT_Field := 16#0#; + CLRSTAT : EMAC_NCR_CLRSTAT_Field := 16#0#; -- Increment statistics registers - INCSTAT : NCR_INCSTAT_Field := 16#0#; + INCSTAT : EMAC_NCR_INCSTAT_Field := 16#0#; -- Write enable for statistics registers - WESTAT : NCR_WESTAT_Field := 16#0#; + WESTAT : EMAC_NCR_WESTAT_Field := 16#0#; -- Back pressure - BP : NCR_BP_Field := 16#0#; + BP : EMAC_NCR_BP_Field := 16#0#; -- Start transmission - TSTART : NCR_TSTART_Field := 16#0#; + TSTART : EMAC_NCR_TSTART_Field := 16#0#; -- Transmit halt - THALT : NCR_THALT_Field := 16#0#; + THALT : EMAC_NCR_THALT_Field := 16#0#; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for NCR_Register use record + for EMAC_NCR_Register use record LB at 0 range 0 .. 0; LLB at 0 range 1 .. 1; RE at 0 range 2 .. 2; @@ -74,23 +71,18 @@ package ATSAM3X8E.EMAC is Reserved_11_31 at 0 range 11 .. 31; end record; - -------------------- - -- NCFGR_Register -- - -------------------- - - subtype NCFGR_SPD_Field is ATSAM3X8E.Bit; - subtype NCFGR_FD_Field is ATSAM3X8E.Bit; - subtype NCFGR_JFRAME_Field is ATSAM3X8E.Bit; - subtype NCFGR_CAF_Field is ATSAM3X8E.Bit; - subtype NCFGR_NBC_Field is ATSAM3X8E.Bit; - subtype NCFGR_MTI_Field is ATSAM3X8E.Bit; - subtype NCFGR_UNI_Field is ATSAM3X8E.Bit; - subtype NCFGR_BIG_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_SPD_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_FD_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_JFRAME_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_CAF_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_NBC_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_MTI_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_UNI_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_BIG_Field is ATSAM3X8E.Bit; -- MDC clock divider - type CLK_Field is - ( - -- MCK divided by 8 (MCK up to 20 MHz). + type NCFGR_CLK_Field is + (-- MCK divided by 8 (MCK up to 20 MHz). Mck_8, -- MCK divided by 16 (MCK up to 40 MHz). Mck_16, @@ -99,19 +91,18 @@ package ATSAM3X8E.EMAC is -- MCK divided by 64 (MCK up to 160 MHz). Mck_64) with Size => 2; - for CLK_Field use + for NCFGR_CLK_Field use (Mck_8 => 0, Mck_16 => 1, Mck_32 => 2, Mck_64 => 3); - subtype NCFGR_RTY_Field is ATSAM3X8E.Bit; - subtype NCFGR_PAE_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_RTY_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_PAE_Field is ATSAM3X8E.Bit; -- Receive Buffer Offset - type RBOF_Field is - ( - -- No offset from start of receive buffer. + type NCFGR_RBOF_Field is + (-- No offset from start of receive buffer. Offset_0, -- One-byte offset from start of receive buffer. Offset_1, @@ -120,60 +111,60 @@ package ATSAM3X8E.EMAC is -- Three-byte offset from start of receive buffer. Offset_3) with Size => 2; - for RBOF_Field use + for NCFGR_RBOF_Field use (Offset_0 => 0, Offset_1 => 1, Offset_2 => 2, Offset_3 => 3); - subtype NCFGR_RLCE_Field is ATSAM3X8E.Bit; - subtype NCFGR_DRFCS_Field is ATSAM3X8E.Bit; - subtype NCFGR_EFRHD_Field is ATSAM3X8E.Bit; - subtype NCFGR_IRXFCS_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_RLCE_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_DRFCS_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_EFRHD_Field is ATSAM3X8E.Bit; + subtype EMAC_NCFGR_IRXFCS_Field is ATSAM3X8E.Bit; -- Network Configuration Register - type NCFGR_Register is record + type EMAC_NCFGR_Register is record -- Speed - SPD : NCFGR_SPD_Field := 16#0#; + SPD : EMAC_NCFGR_SPD_Field := 16#0#; -- Full Duplex - FD : NCFGR_FD_Field := 16#0#; + FD : EMAC_NCFGR_FD_Field := 16#0#; -- unspecified Reserved_2_2 : ATSAM3X8E.Bit := 16#0#; -- Jumbo Frames - JFRAME : NCFGR_JFRAME_Field := 16#0#; + JFRAME : EMAC_NCFGR_JFRAME_Field := 16#0#; -- Copy All Frames - CAF : NCFGR_CAF_Field := 16#0#; + CAF : EMAC_NCFGR_CAF_Field := 16#0#; -- No Broadcast - NBC : NCFGR_NBC_Field := 16#0#; + NBC : EMAC_NCFGR_NBC_Field := 16#0#; -- Multicast Hash Enable - MTI : NCFGR_MTI_Field := 16#0#; + MTI : EMAC_NCFGR_MTI_Field := 16#0#; -- Unicast Hash Enable - UNI : NCFGR_UNI_Field := 16#0#; + UNI : EMAC_NCFGR_UNI_Field := 16#0#; -- Receive 1536 bytes frames - BIG : NCFGR_BIG_Field := 16#0#; + BIG : EMAC_NCFGR_BIG_Field := 16#0#; -- unspecified Reserved_9_9 : ATSAM3X8E.Bit := 16#0#; -- MDC clock divider - CLK : CLK_Field := Mck_32; + CLK : NCFGR_CLK_Field := ATSAM3X8E.EMAC.Mck_32; -- Retry test - RTY : NCFGR_RTY_Field := 16#0#; + RTY : EMAC_NCFGR_RTY_Field := 16#0#; -- Pause Enable - PAE : NCFGR_PAE_Field := 16#0#; + PAE : EMAC_NCFGR_PAE_Field := 16#0#; -- Receive Buffer Offset - RBOF : RBOF_Field := Offset_0; + RBOF : NCFGR_RBOF_Field := ATSAM3X8E.EMAC.Offset_0; -- Receive Length field Checking Enable - RLCE : NCFGR_RLCE_Field := 16#0#; + RLCE : EMAC_NCFGR_RLCE_Field := 16#0#; -- Discard Receive FCS - DRFCS : NCFGR_DRFCS_Field := 16#0#; - EFRHD : NCFGR_EFRHD_Field := 16#0#; + DRFCS : EMAC_NCFGR_DRFCS_Field := 16#0#; + EFRHD : EMAC_NCFGR_EFRHD_Field := 16#0#; -- Ignore RX FCS - IRXFCS : NCFGR_IRXFCS_Field := 16#0#; + IRXFCS : EMAC_NCFGR_IRXFCS_Field := 16#0#; -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for NCFGR_Register use record + for EMAC_NCFGR_Register use record SPD at 0 range 0 .. 0; FD at 0 range 1 .. 1; Reserved_2_2 at 0 range 2 .. 2; @@ -195,67 +186,59 @@ package ATSAM3X8E.EMAC is Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------ - -- NSR_Register -- - ------------------ - - subtype NSR_MDIO_Field is ATSAM3X8E.Bit; - subtype NSR_IDLE_Field is ATSAM3X8E.Bit; + subtype EMAC_NSR_MDIO_Field is ATSAM3X8E.Bit; + subtype EMAC_NSR_IDLE_Field is ATSAM3X8E.Bit; -- Network Status Register - type NSR_Register is record + type EMAC_NSR_Register is record -- unspecified Reserved_0_0 : ATSAM3X8E.Bit; -- Read-only. - MDIO : NSR_MDIO_Field := 16#0#; + MDIO : EMAC_NSR_MDIO_Field; -- Read-only. - IDLE : NSR_IDLE_Field := 16#0#; + IDLE : EMAC_NSR_IDLE_Field; -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for NSR_Register use record + for EMAC_NSR_Register use record Reserved_0_0 at 0 range 0 .. 0; MDIO at 0 range 1 .. 1; IDLE at 0 range 2 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- TSR_Register -- - ------------------ - - subtype TSR_UBR_Field is ATSAM3X8E.Bit; - subtype TSR_COL_Field is ATSAM3X8E.Bit; - subtype TSR_RLES_Field is ATSAM3X8E.Bit; - subtype TSR_TGO_Field is ATSAM3X8E.Bit; - subtype TSR_BEX_Field is ATSAM3X8E.Bit; - subtype TSR_COMP_Field is ATSAM3X8E.Bit; - subtype TSR_UND_Field is ATSAM3X8E.Bit; + subtype EMAC_TSR_UBR_Field is ATSAM3X8E.Bit; + subtype EMAC_TSR_COL_Field is ATSAM3X8E.Bit; + subtype EMAC_TSR_RLES_Field is ATSAM3X8E.Bit; + subtype EMAC_TSR_TGO_Field is ATSAM3X8E.Bit; + subtype EMAC_TSR_BEX_Field is ATSAM3X8E.Bit; + subtype EMAC_TSR_COMP_Field is ATSAM3X8E.Bit; + subtype EMAC_TSR_UND_Field is ATSAM3X8E.Bit; -- Transmit Status Register - type TSR_Register is record + type EMAC_TSR_Register is record -- Used Bit Read - UBR : TSR_UBR_Field := 16#0#; + UBR : EMAC_TSR_UBR_Field := 16#0#; -- Collision Occurred - COL : TSR_COL_Field := 16#0#; + COL : EMAC_TSR_COL_Field := 16#0#; -- Retry Limit exceeded - RLES : TSR_RLES_Field := 16#0#; + RLES : EMAC_TSR_RLES_Field := 16#0#; -- Transmit Go - TGO : TSR_TGO_Field := 16#0#; + TGO : EMAC_TSR_TGO_Field := 16#0#; -- Buffers exhausted mid frame - BEX : TSR_BEX_Field := 16#0#; + BEX : EMAC_TSR_BEX_Field := 16#0#; -- Transmit Complete - COMP : TSR_COMP_Field := 16#0#; + COMP : EMAC_TSR_COMP_Field := 16#0#; -- Transmit Underrun - UND : TSR_UND_Field := 16#0#; + UND : EMAC_TSR_UND_Field := 16#0#; -- unspecified Reserved_7_31 : ATSAM3X8E.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TSR_Register use record + for EMAC_TSR_Register use record UBR at 0 range 0 .. 0; COL at 0 range 1 .. 1; RLES at 0 range 2 .. 2; @@ -266,125 +249,109 @@ package ATSAM3X8E.EMAC is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------- - -- RBQP_Register -- - ------------------- - - subtype RBQP_ADDR_Field is ATSAM3X8E.UInt30; + subtype EMAC_RBQP_ADDR_Field is ATSAM3X8E.UInt30; -- Receive Buffer Queue Pointer Register - type RBQP_Register is record + type EMAC_RBQP_Register is record -- unspecified Reserved_0_1 : ATSAM3X8E.UInt2 := 16#0#; -- Receive buffer queue pointer address - ADDR : RBQP_ADDR_Field := 16#0#; + ADDR : EMAC_RBQP_ADDR_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RBQP_Register use record + for EMAC_RBQP_Register use record Reserved_0_1 at 0 range 0 .. 1; ADDR at 0 range 2 .. 31; end record; - ------------------- - -- TBQP_Register -- - ------------------- - - subtype TBQP_ADDR_Field is ATSAM3X8E.UInt30; + subtype EMAC_TBQP_ADDR_Field is ATSAM3X8E.UInt30; -- Transmit Buffer Queue Pointer Register - type TBQP_Register is record + type EMAC_TBQP_Register is record -- unspecified Reserved_0_1 : ATSAM3X8E.UInt2 := 16#0#; -- Transmit buffer queue pointer address - ADDR : TBQP_ADDR_Field := 16#0#; + ADDR : EMAC_TBQP_ADDR_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TBQP_Register use record + for EMAC_TBQP_Register use record Reserved_0_1 at 0 range 0 .. 1; ADDR at 0 range 2 .. 31; end record; - ------------------ - -- RSR_Register -- - ------------------ - - subtype RSR_BNA_Field is ATSAM3X8E.Bit; - subtype RSR_REC_Field is ATSAM3X8E.Bit; - subtype RSR_OVR_Field is ATSAM3X8E.Bit; + subtype EMAC_RSR_BNA_Field is ATSAM3X8E.Bit; + subtype EMAC_RSR_REC_Field is ATSAM3X8E.Bit; + subtype EMAC_RSR_OVR_Field is ATSAM3X8E.Bit; -- Receive Status Register - type RSR_Register is record + type EMAC_RSR_Register is record -- Buffer Not Available - BNA : RSR_BNA_Field := 16#0#; + BNA : EMAC_RSR_BNA_Field := 16#0#; -- Frame Received - REC : RSR_REC_Field := 16#0#; + REC : EMAC_RSR_REC_Field := 16#0#; -- Receive Overrun - OVR : RSR_OVR_Field := 16#0#; + OVR : EMAC_RSR_OVR_Field := 16#0#; -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RSR_Register use record + for EMAC_RSR_Register use record BNA at 0 range 0 .. 0; REC at 0 range 1 .. 1; OVR at 0 range 2 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ - - subtype ISR_MFD_Field is ATSAM3X8E.Bit; - subtype ISR_RCOMP_Field is ATSAM3X8E.Bit; - subtype ISR_RXUBR_Field is ATSAM3X8E.Bit; - subtype ISR_TXUBR_Field is ATSAM3X8E.Bit; - subtype ISR_TUND_Field is ATSAM3X8E.Bit; - subtype ISR_RLEX_Field is ATSAM3X8E.Bit; - subtype ISR_TXERR_Field is ATSAM3X8E.Bit; - subtype ISR_TCOMP_Field is ATSAM3X8E.Bit; - subtype ISR_ROVR_Field is ATSAM3X8E.Bit; - subtype ISR_HRESP_Field is ATSAM3X8E.Bit; - subtype ISR_PFRE_Field is ATSAM3X8E.Bit; - subtype ISR_PTZ_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_MFD_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_RCOMP_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_RXUBR_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_TXUBR_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_TUND_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_RLEX_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_TXERR_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_TCOMP_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_ROVR_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_HRESP_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_PFRE_Field is ATSAM3X8E.Bit; + subtype EMAC_ISR_PTZ_Field is ATSAM3X8E.Bit; -- Interrupt Status Register - type ISR_Register is record + type EMAC_ISR_Register is record -- Management Frame Done - MFD : ISR_MFD_Field := 16#0#; + MFD : EMAC_ISR_MFD_Field := 16#0#; -- Receive Complete - RCOMP : ISR_RCOMP_Field := 16#0#; + RCOMP : EMAC_ISR_RCOMP_Field := 16#0#; -- Receive Used Bit Read - RXUBR : ISR_RXUBR_Field := 16#0#; + RXUBR : EMAC_ISR_RXUBR_Field := 16#0#; -- Transmit Used Bit Read - TXUBR : ISR_TXUBR_Field := 16#0#; + TXUBR : EMAC_ISR_TXUBR_Field := 16#0#; -- Ethernet Transmit Buffer Underrun - TUND : ISR_TUND_Field := 16#0#; + TUND : EMAC_ISR_TUND_Field := 16#0#; -- Retry Limit Exceeded - RLEX : ISR_RLEX_Field := 16#0#; + RLEX : EMAC_ISR_RLEX_Field := 16#0#; -- Transmit Error - TXERR : ISR_TXERR_Field := 16#0#; + TXERR : EMAC_ISR_TXERR_Field := 16#0#; -- Transmit Complete - TCOMP : ISR_TCOMP_Field := 16#0#; + TCOMP : EMAC_ISR_TCOMP_Field := 16#0#; -- unspecified Reserved_8_9 : ATSAM3X8E.UInt2 := 16#0#; -- Receive Overrun - ROVR : ISR_ROVR_Field := 16#0#; + ROVR : EMAC_ISR_ROVR_Field := 16#0#; -- Hresp not OK - HRESP : ISR_HRESP_Field := 16#0#; + HRESP : EMAC_ISR_HRESP_Field := 16#0#; -- Pause Frame Received - PFRE : ISR_PFRE_Field := 16#0#; + PFRE : EMAC_ISR_PFRE_Field := 16#0#; -- Pause Time Zero - PTZ : ISR_PTZ_Field := 16#0#; + PTZ : EMAC_ISR_PTZ_Field := 16#0#; -- unspecified Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ISR_Register use record + for EMAC_ISR_Register use record MFD at 0 range 0 .. 0; RCOMP at 0 range 1 .. 1; RXUBR at 0 range 2 .. 2; @@ -401,57 +368,53 @@ package ATSAM3X8E.EMAC is Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_MFD_Field is ATSAM3X8E.Bit; - subtype IER_RCOMP_Field is ATSAM3X8E.Bit; - subtype IER_RXUBR_Field is ATSAM3X8E.Bit; - subtype IER_TXUBR_Field is ATSAM3X8E.Bit; - subtype IER_TUND_Field is ATSAM3X8E.Bit; - subtype IER_RLE_Field is ATSAM3X8E.Bit; - subtype IER_TXERR_Field is ATSAM3X8E.Bit; - subtype IER_TCOMP_Field is ATSAM3X8E.Bit; - subtype IER_ROVR_Field is ATSAM3X8E.Bit; - subtype IER_HRESP_Field is ATSAM3X8E.Bit; - subtype IER_PFR_Field is ATSAM3X8E.Bit; - subtype IER_PTZ_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_MFD_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_RCOMP_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_RXUBR_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_TXUBR_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_TUND_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_RLE_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_TXERR_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_TCOMP_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_ROVR_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_HRESP_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_PFR_Field is ATSAM3X8E.Bit; + subtype EMAC_IER_PTZ_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type EMAC_IER_Register is record -- Write-only. Management Frame sent - MFD : IER_MFD_Field := 16#0#; + MFD : EMAC_IER_MFD_Field := 16#0#; -- Write-only. Receive Complete - RCOMP : IER_RCOMP_Field := 16#0#; + RCOMP : EMAC_IER_RCOMP_Field := 16#0#; -- Write-only. Receive Used Bit Read - RXUBR : IER_RXUBR_Field := 16#0#; + RXUBR : EMAC_IER_RXUBR_Field := 16#0#; -- Write-only. Transmit Used Bit Read - TXUBR : IER_TXUBR_Field := 16#0#; + TXUBR : EMAC_IER_TXUBR_Field := 16#0#; -- Write-only. Ethernet Transmit Buffer Underrun - TUND : IER_TUND_Field := 16#0#; + TUND : EMAC_IER_TUND_Field := 16#0#; -- Write-only. Retry Limit Exceeded - RLE : IER_RLE_Field := 16#0#; + RLE : EMAC_IER_RLE_Field := 16#0#; -- Write-only. - TXERR : IER_TXERR_Field := 16#0#; + TXERR : EMAC_IER_TXERR_Field := 16#0#; -- Write-only. Transmit Complete - TCOMP : IER_TCOMP_Field := 16#0#; + TCOMP : EMAC_IER_TCOMP_Field := 16#0#; -- unspecified Reserved_8_9 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Receive Overrun - ROVR : IER_ROVR_Field := 16#0#; + ROVR : EMAC_IER_ROVR_Field := 16#0#; -- Write-only. Hresp not OK - HRESP : IER_HRESP_Field := 16#0#; + HRESP : EMAC_IER_HRESP_Field := 16#0#; -- Write-only. Pause Frame Received - PFR : IER_PFR_Field := 16#0#; + PFR : EMAC_IER_PFR_Field := 16#0#; -- Write-only. Pause Time Zero - PTZ : IER_PTZ_Field := 16#0#; + PTZ : EMAC_IER_PTZ_Field := 16#0#; -- unspecified Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for EMAC_IER_Register use record MFD at 0 range 0 .. 0; RCOMP at 0 range 1 .. 1; RXUBR at 0 range 2 .. 2; @@ -468,57 +431,53 @@ package ATSAM3X8E.EMAC is Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_MFD_Field is ATSAM3X8E.Bit; - subtype IDR_RCOMP_Field is ATSAM3X8E.Bit; - subtype IDR_RXUBR_Field is ATSAM3X8E.Bit; - subtype IDR_TXUBR_Field is ATSAM3X8E.Bit; - subtype IDR_TUND_Field is ATSAM3X8E.Bit; - subtype IDR_RLE_Field is ATSAM3X8E.Bit; - subtype IDR_TXERR_Field is ATSAM3X8E.Bit; - subtype IDR_TCOMP_Field is ATSAM3X8E.Bit; - subtype IDR_ROVR_Field is ATSAM3X8E.Bit; - subtype IDR_HRESP_Field is ATSAM3X8E.Bit; - subtype IDR_PFR_Field is ATSAM3X8E.Bit; - subtype IDR_PTZ_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_MFD_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_RCOMP_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_RXUBR_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_TXUBR_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_TUND_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_RLE_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_TXERR_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_TCOMP_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_ROVR_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_HRESP_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_PFR_Field is ATSAM3X8E.Bit; + subtype EMAC_IDR_PTZ_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type EMAC_IDR_Register is record -- Write-only. Management Frame sent - MFD : IDR_MFD_Field := 16#0#; + MFD : EMAC_IDR_MFD_Field := 16#0#; -- Write-only. Receive Complete - RCOMP : IDR_RCOMP_Field := 16#0#; + RCOMP : EMAC_IDR_RCOMP_Field := 16#0#; -- Write-only. Receive Used Bit Read - RXUBR : IDR_RXUBR_Field := 16#0#; + RXUBR : EMAC_IDR_RXUBR_Field := 16#0#; -- Write-only. Transmit Used Bit Read - TXUBR : IDR_TXUBR_Field := 16#0#; + TXUBR : EMAC_IDR_TXUBR_Field := 16#0#; -- Write-only. Ethernet Transmit Buffer Underrun - TUND : IDR_TUND_Field := 16#0#; + TUND : EMAC_IDR_TUND_Field := 16#0#; -- Write-only. Retry Limit Exceeded - RLE : IDR_RLE_Field := 16#0#; + RLE : EMAC_IDR_RLE_Field := 16#0#; -- Write-only. - TXERR : IDR_TXERR_Field := 16#0#; + TXERR : EMAC_IDR_TXERR_Field := 16#0#; -- Write-only. Transmit Complete - TCOMP : IDR_TCOMP_Field := 16#0#; + TCOMP : EMAC_IDR_TCOMP_Field := 16#0#; -- unspecified Reserved_8_9 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Receive Overrun - ROVR : IDR_ROVR_Field := 16#0#; + ROVR : EMAC_IDR_ROVR_Field := 16#0#; -- Write-only. Hresp not OK - HRESP : IDR_HRESP_Field := 16#0#; + HRESP : EMAC_IDR_HRESP_Field := 16#0#; -- Write-only. Pause Frame Received - PFR : IDR_PFR_Field := 16#0#; + PFR : EMAC_IDR_PFR_Field := 16#0#; -- Write-only. Pause Time Zero - PTZ : IDR_PTZ_Field := 16#0#; + PTZ : EMAC_IDR_PTZ_Field := 16#0#; -- unspecified Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for EMAC_IDR_Register use record MFD at 0 range 0 .. 0; RCOMP at 0 range 1 .. 1; RXUBR at 0 range 2 .. 2; @@ -535,57 +494,53 @@ package ATSAM3X8E.EMAC is Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_MFD_Field is ATSAM3X8E.Bit; - subtype IMR_RCOMP_Field is ATSAM3X8E.Bit; - subtype IMR_RXUBR_Field is ATSAM3X8E.Bit; - subtype IMR_TXUBR_Field is ATSAM3X8E.Bit; - subtype IMR_TUND_Field is ATSAM3X8E.Bit; - subtype IMR_RLE_Field is ATSAM3X8E.Bit; - subtype IMR_TXERR_Field is ATSAM3X8E.Bit; - subtype IMR_TCOMP_Field is ATSAM3X8E.Bit; - subtype IMR_ROVR_Field is ATSAM3X8E.Bit; - subtype IMR_HRESP_Field is ATSAM3X8E.Bit; - subtype IMR_PFR_Field is ATSAM3X8E.Bit; - subtype IMR_PTZ_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_MFD_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_RCOMP_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_RXUBR_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_TXUBR_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_TUND_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_RLE_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_TXERR_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_TCOMP_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_ROVR_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_HRESP_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_PFR_Field is ATSAM3X8E.Bit; + subtype EMAC_IMR_PTZ_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type EMAC_IMR_Register is record -- Read-only. Management Frame sent - MFD : IMR_MFD_Field := 16#1#; + MFD : EMAC_IMR_MFD_Field; -- Read-only. Receive Complete - RCOMP : IMR_RCOMP_Field := 16#1#; + RCOMP : EMAC_IMR_RCOMP_Field; -- Read-only. Receive Used Bit Read - RXUBR : IMR_RXUBR_Field := 16#1#; + RXUBR : EMAC_IMR_RXUBR_Field; -- Read-only. Transmit Used Bit Read - TXUBR : IMR_TXUBR_Field := 16#1#; + TXUBR : EMAC_IMR_TXUBR_Field; -- Read-only. Ethernet Transmit Buffer Underrun - TUND : IMR_TUND_Field := 16#1#; + TUND : EMAC_IMR_TUND_Field; -- Read-only. Retry Limit Exceeded - RLE : IMR_RLE_Field := 16#1#; + RLE : EMAC_IMR_RLE_Field; -- Read-only. - TXERR : IMR_TXERR_Field := 16#1#; + TXERR : EMAC_IMR_TXERR_Field; -- Read-only. Transmit Complete - TCOMP : IMR_TCOMP_Field := 16#1#; + TCOMP : EMAC_IMR_TCOMP_Field; -- unspecified Reserved_8_9 : ATSAM3X8E.UInt2; -- Read-only. Receive Overrun - ROVR : IMR_ROVR_Field := 16#1#; + ROVR : EMAC_IMR_ROVR_Field; -- Read-only. Hresp not OK - HRESP : IMR_HRESP_Field := 16#1#; + HRESP : EMAC_IMR_HRESP_Field; -- Read-only. Pause Frame Received - PFR : IMR_PFR_Field := 16#1#; + PFR : EMAC_IMR_PFR_Field; -- Read-only. Pause Time Zero - PTZ : IMR_PTZ_Field := 16#1#; + PTZ : EMAC_IMR_PTZ_Field; -- unspecified Reserved_14_31 : ATSAM3X8E.UInt18; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for EMAC_IMR_Register use record MFD at 0 range 0 .. 0; RCOMP at 0 range 1 .. 1; RXUBR at 0 range 2 .. 2; @@ -602,33 +557,29 @@ package ATSAM3X8E.EMAC is Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------ - -- MAN_Register -- - ------------------ - - subtype MAN_DATA_Field is ATSAM3X8E.Short; - subtype MAN_CODE_Field is ATSAM3X8E.UInt2; - subtype MAN_REGA_Field is ATSAM3X8E.UInt5; - subtype MAN_PHYA_Field is ATSAM3X8E.UInt5; - subtype MAN_RW_Field is ATSAM3X8E.UInt2; - subtype MAN_SOF_Field is ATSAM3X8E.UInt2; + subtype EMAC_MAN_DATA_Field is ATSAM3X8E.UInt16; + subtype EMAC_MAN_CODE_Field is ATSAM3X8E.UInt2; + subtype EMAC_MAN_REGA_Field is ATSAM3X8E.UInt5; + subtype EMAC_MAN_PHYA_Field is ATSAM3X8E.UInt5; + subtype EMAC_MAN_RW_Field is ATSAM3X8E.UInt2; + subtype EMAC_MAN_SOF_Field is ATSAM3X8E.UInt2; -- Phy Maintenance Register - type MAN_Register is record - DATA : MAN_DATA_Field := 16#0#; - CODE : MAN_CODE_Field := 16#0#; + type EMAC_MAN_Register is record + DATA : EMAC_MAN_DATA_Field := 16#0#; + CODE : EMAC_MAN_CODE_Field := 16#0#; -- Register Address - REGA : MAN_REGA_Field := 16#0#; + REGA : EMAC_MAN_REGA_Field := 16#0#; -- PHY Address - PHYA : MAN_PHYA_Field := 16#0#; + PHYA : EMAC_MAN_PHYA_Field := 16#0#; -- Read-write - RW : MAN_RW_Field := 16#0#; + RW : EMAC_MAN_RW_Field := 16#0#; -- Start of frame - SOF : MAN_SOF_Field := 16#0#; + SOF : EMAC_MAN_SOF_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MAN_Register use record + for EMAC_MAN_Register use record DATA at 0 range 0 .. 15; CODE at 0 range 16 .. 17; REGA at 0 range 18 .. 22; @@ -637,541 +588,433 @@ package ATSAM3X8E.EMAC is SOF at 0 range 30 .. 31; end record; - ------------------ - -- PTR_Register -- - ------------------ - - subtype PTR_PTIME_Field is ATSAM3X8E.Short; + subtype EMAC_PTR_PTIME_Field is ATSAM3X8E.UInt16; -- Pause Time Register - type PTR_Register is record + type EMAC_PTR_Register is record -- Pause Time - PTIME : PTR_PTIME_Field := 16#0#; + PTIME : EMAC_PTR_PTIME_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTR_Register use record + for EMAC_PTR_Register use record PTIME at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- PFR_Register -- - ------------------ - - subtype PFR_FROK_Field is ATSAM3X8E.Short; + subtype EMAC_PFR_FROK_Field is ATSAM3X8E.UInt16; -- Pause Frames Received Register - type PFR_Register is record + type EMAC_PFR_Register is record -- Pause Frames received OK - FROK : PFR_FROK_Field := 16#0#; + FROK : EMAC_PFR_FROK_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PFR_Register use record + for EMAC_PFR_Register use record FROK at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- FTO_Register -- - ------------------ - - subtype FTO_FTOK_Field is ATSAM3X8E.UInt24; + subtype EMAC_FTO_FTOK_Field is ATSAM3X8E.UInt24; -- Frames Transmitted Ok Register - type FTO_Register is record + type EMAC_FTO_Register is record -- Frames Transmitted OK - FTOK : FTO_FTOK_Field := 16#0#; + FTOK : EMAC_FTO_FTOK_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FTO_Register use record + for EMAC_FTO_Register use record FTOK at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- SCF_Register -- - ------------------ - - subtype SCF_SCF_Field is ATSAM3X8E.Short; + subtype EMAC_SCF_SCF_Field is ATSAM3X8E.UInt16; -- Single Collision Frames Register - type SCF_Register is record + type EMAC_SCF_Register is record -- Single Collision Frames - SCF : SCF_SCF_Field := 16#0#; + SCF : EMAC_SCF_SCF_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SCF_Register use record + for EMAC_SCF_Register use record SCF at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- MCF_Register -- - ------------------ - - subtype MCF_MCF_Field is ATSAM3X8E.Short; + subtype EMAC_MCF_MCF_Field is ATSAM3X8E.UInt16; -- Multiple Collision Frames Register - type MCF_Register is record + type EMAC_MCF_Register is record -- Multicollision Frames - MCF : MCF_MCF_Field := 16#0#; + MCF : EMAC_MCF_MCF_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MCF_Register use record + for EMAC_MCF_Register use record MCF at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- FRO_Register -- - ------------------ - - subtype FRO_FROK_Field is ATSAM3X8E.UInt24; + subtype EMAC_FRO_FROK_Field is ATSAM3X8E.UInt24; -- Frames Received Ok Register - type FRO_Register is record + type EMAC_FRO_Register is record -- Frames Received OK - FROK : FRO_FROK_Field := 16#0#; + FROK : EMAC_FRO_FROK_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FRO_Register use record + for EMAC_FRO_Register use record FROK at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- FCSE_Register -- - ------------------- - - subtype FCSE_FCSE_Field is ATSAM3X8E.Byte; + subtype EMAC_FCSE_FCSE_Field is ATSAM3X8E.Byte; -- Frame Check Sequence Errors Register - type FCSE_Register is record + type EMAC_FCSE_Register is record -- Frame Check Sequence Errors - FCSE : FCSE_FCSE_Field := 16#0#; + FCSE : EMAC_FCSE_FCSE_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FCSE_Register use record + for EMAC_FCSE_Register use record FCSE at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- ALE_Register -- - ------------------ - - subtype ALE_ALE_Field is ATSAM3X8E.Byte; + subtype EMAC_ALE_ALE_Field is ATSAM3X8E.Byte; -- Alignment Errors Register - type ALE_Register is record + type EMAC_ALE_Register is record -- Alignment Errors - ALE : ALE_ALE_Field := 16#0#; + ALE : EMAC_ALE_ALE_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ALE_Register use record + for EMAC_ALE_Register use record ALE at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- DTF_Register -- - ------------------ - - subtype DTF_DTF_Field is ATSAM3X8E.Short; + subtype EMAC_DTF_DTF_Field is ATSAM3X8E.UInt16; -- Deferred Transmission Frames Register - type DTF_Register is record + type EMAC_DTF_Register is record -- Deferred Transmission Frames - DTF : DTF_DTF_Field := 16#0#; + DTF : EMAC_DTF_DTF_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DTF_Register use record + for EMAC_DTF_Register use record DTF at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- LCOL_Register -- - ------------------- - - subtype LCOL_LCOL_Field is ATSAM3X8E.Byte; + subtype EMAC_LCOL_LCOL_Field is ATSAM3X8E.Byte; -- Late Collisions Register - type LCOL_Register is record + type EMAC_LCOL_Register is record -- Late Collisions - LCOL : LCOL_LCOL_Field := 16#0#; + LCOL : EMAC_LCOL_LCOL_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for LCOL_Register use record + for EMAC_LCOL_Register use record LCOL at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- ECOL_Register -- - ------------------- - - subtype ECOL_EXCOL_Field is ATSAM3X8E.Byte; + subtype EMAC_ECOL_EXCOL_Field is ATSAM3X8E.Byte; -- Excessive Collisions Register - type ECOL_Register is record + type EMAC_ECOL_Register is record -- Excessive Collisions - EXCOL : ECOL_EXCOL_Field := 16#0#; + EXCOL : EMAC_ECOL_EXCOL_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ECOL_Register use record + for EMAC_ECOL_Register use record EXCOL at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- TUND_Register -- - ------------------- - - subtype TUND_TUND_Field is ATSAM3X8E.Byte; + subtype EMAC_TUND_TUND_Field is ATSAM3X8E.Byte; -- Transmit Underrun Errors Register - type TUND_Register is record + type EMAC_TUND_Register is record -- Transmit Underruns - TUND : TUND_TUND_Field := 16#0#; + TUND : EMAC_TUND_TUND_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TUND_Register use record + for EMAC_TUND_Register use record TUND at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- CSE_Register -- - ------------------ - - subtype CSE_CSE_Field is ATSAM3X8E.Byte; + subtype EMAC_CSE_CSE_Field is ATSAM3X8E.Byte; -- Carrier Sense Errors Register - type CSE_Register is record + type EMAC_CSE_Register is record -- Carrier Sense Errors - CSE : CSE_CSE_Field := 16#0#; + CSE : EMAC_CSE_CSE_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CSE_Register use record + for EMAC_CSE_Register use record CSE at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- RRE_Register -- - ------------------ - - subtype RRE_RRE_Field is ATSAM3X8E.Short; + subtype EMAC_RRE_RRE_Field is ATSAM3X8E.UInt16; -- Receive Resource Errors Register - type RRE_Register is record + type EMAC_RRE_Register is record -- Receive Resource Errors - RRE : RRE_RRE_Field := 16#0#; + RRE : EMAC_RRE_RRE_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RRE_Register use record + for EMAC_RRE_Register use record RRE at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- ROV_Register -- - ------------------ - - subtype ROV_ROVR_Field is ATSAM3X8E.Byte; + subtype EMAC_ROV_ROVR_Field is ATSAM3X8E.Byte; -- Receive Overrun Errors Register - type ROV_Register is record + type EMAC_ROV_Register is record -- Receive Overrun - ROVR : ROV_ROVR_Field := 16#0#; + ROVR : EMAC_ROV_ROVR_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ROV_Register use record + for EMAC_ROV_Register use record ROVR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- RSE_Register -- - ------------------ - - subtype RSE_RSE_Field is ATSAM3X8E.Byte; + subtype EMAC_RSE_RSE_Field is ATSAM3X8E.Byte; -- Receive Symbol Errors Register - type RSE_Register is record + type EMAC_RSE_Register is record -- Receive Symbol Errors - RSE : RSE_RSE_Field := 16#0#; + RSE : EMAC_RSE_RSE_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RSE_Register use record + for EMAC_RSE_Register use record RSE at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- ELE_Register -- - ------------------ - - subtype ELE_EXL_Field is ATSAM3X8E.Byte; + subtype EMAC_ELE_EXL_Field is ATSAM3X8E.Byte; -- Excessive Length Errors Register - type ELE_Register is record + type EMAC_ELE_Register is record -- Excessive Length Errors - EXL : ELE_EXL_Field := 16#0#; + EXL : EMAC_ELE_EXL_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ELE_Register use record + for EMAC_ELE_Register use record EXL at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- RJA_Register -- - ------------------ - - subtype RJA_RJB_Field is ATSAM3X8E.Byte; + subtype EMAC_RJA_RJB_Field is ATSAM3X8E.Byte; -- Receive Jabbers Register - type RJA_Register is record + type EMAC_RJA_Register is record -- Receive Jabbers - RJB : RJA_RJB_Field := 16#0#; + RJB : EMAC_RJA_RJB_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RJA_Register use record + for EMAC_RJA_Register use record RJB at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- USF_Register -- - ------------------ - - subtype USF_USF_Field is ATSAM3X8E.Byte; + subtype EMAC_USF_USF_Field is ATSAM3X8E.Byte; -- Undersize Frames Register - type USF_Register is record + type EMAC_USF_Register is record -- Undersize frames - USF : USF_USF_Field := 16#0#; + USF : EMAC_USF_USF_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for USF_Register use record + for EMAC_USF_Register use record USF at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- STE_Register -- - ------------------ - - subtype STE_SQER_Field is ATSAM3X8E.Byte; + subtype EMAC_STE_SQER_Field is ATSAM3X8E.Byte; -- SQE Test Errors Register - type STE_Register is record + type EMAC_STE_Register is record -- SQE test errors - SQER : STE_SQER_Field := 16#0#; + SQER : EMAC_STE_SQER_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for STE_Register use record + for EMAC_STE_Register use record SQER at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- RLE_Register -- - ------------------ - - subtype RLE_RLFM_Field is ATSAM3X8E.Byte; + subtype EMAC_RLE_RLFM_Field is ATSAM3X8E.Byte; -- Received Length Field Mismatch Register - type RLE_Register is record + type EMAC_RLE_Register is record -- Receive Length Field Mismatch - RLFM : RLE_RLFM_Field := 16#0#; + RLFM : EMAC_RLE_RLFM_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RLE_Register use record + for EMAC_RLE_Register use record RLFM at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- SA1T_Register -- - ------------------- - - subtype SA1T_ADDR_Field is ATSAM3X8E.Short; + subtype EMAC_SA1T_ADDR_Field is ATSAM3X8E.UInt16; -- Specific Address 1 Top Register - type SA1T_Register is record - ADDR : SA1T_ADDR_Field := 16#0#; + type EMAC_SA1T_Register is record + ADDR : EMAC_SA1T_ADDR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SA1T_Register use record + for EMAC_SA1T_Register use record ADDR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- SA2T_Register -- - ------------------- - - subtype SA2T_ADDR_Field is ATSAM3X8E.Short; + subtype EMAC_SA2T_ADDR_Field is ATSAM3X8E.UInt16; -- Specific Address 2 Top Register - type SA2T_Register is record - ADDR : SA2T_ADDR_Field := 16#0#; + type EMAC_SA2T_Register is record + ADDR : EMAC_SA2T_ADDR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SA2T_Register use record + for EMAC_SA2T_Register use record ADDR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- SA3T_Register -- - ------------------- - - subtype SA3T_ADDR_Field is ATSAM3X8E.Short; + subtype EMAC_SA3T_ADDR_Field is ATSAM3X8E.UInt16; -- Specific Address 3 Top Register - type SA3T_Register is record - ADDR : SA3T_ADDR_Field := 16#0#; + type EMAC_SA3T_Register is record + ADDR : EMAC_SA3T_ADDR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SA3T_Register use record + for EMAC_SA3T_Register use record ADDR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- SA4T_Register -- - ------------------- - - subtype SA4T_ADDR_Field is ATSAM3X8E.Short; + subtype EMAC_SA4T_ADDR_Field is ATSAM3X8E.UInt16; -- Specific Address 4 Top Register - type SA4T_Register is record - ADDR : SA4T_ADDR_Field := 16#0#; + type EMAC_SA4T_Register is record + ADDR : EMAC_SA4T_ADDR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SA4T_Register use record + for EMAC_SA4T_Register use record ADDR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- TID_Register -- - ------------------ - - subtype TID_TID_Field is ATSAM3X8E.Short; + subtype EMAC_TID_TID_Field is ATSAM3X8E.UInt16; -- Type ID Checking Register - type TID_Register is record + type EMAC_TID_Register is record -- Type ID checking - TID : TID_TID_Field := 16#0#; + TID : EMAC_TID_TID_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TID_Register use record + for EMAC_TID_Register use record TID at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- USRIO_Register -- - -------------------- - - subtype USRIO_RMII_Field is ATSAM3X8E.Bit; - subtype USRIO_CLKEN_Field is ATSAM3X8E.Bit; + subtype EMAC_USRIO_RMII_Field is ATSAM3X8E.Bit; + subtype EMAC_USRIO_CLKEN_Field is ATSAM3X8E.Bit; -- User Input/Output Register - type USRIO_Register is record + type EMAC_USRIO_Register is record -- Reduce MII - RMII : USRIO_RMII_Field := 16#0#; + RMII : EMAC_USRIO_RMII_Field := 16#0#; -- Clock Enable - CLKEN : USRIO_CLKEN_Field := 16#0#; + CLKEN : EMAC_USRIO_CLKEN_Field := 16#0#; -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for USRIO_Register use record + for EMAC_USRIO_Register use record RMII at 0 range 0 .. 0; CLKEN at 0 range 1 .. 1; Reserved_2_31 at 0 range 2 .. 31; @@ -1184,144 +1027,183 @@ package ATSAM3X8E.EMAC is -- Ethernet MAC 10/100 type EMAC_Peripheral is record -- Network Control Register - NCR : NCR_Register; + NCR : aliased EMAC_NCR_Register; + pragma Volatile_Full_Access (NCR); -- Network Configuration Register - NCFGR : NCFGR_Register; + NCFGR : aliased EMAC_NCFGR_Register; + pragma Volatile_Full_Access (NCFGR); -- Network Status Register - NSR : NSR_Register; + NSR : aliased EMAC_NSR_Register; + pragma Volatile_Full_Access (NSR); -- Transmit Status Register - TSR : TSR_Register; + TSR : aliased EMAC_TSR_Register; + pragma Volatile_Full_Access (TSR); -- Receive Buffer Queue Pointer Register - RBQP : RBQP_Register; + RBQP : aliased EMAC_RBQP_Register; + pragma Volatile_Full_Access (RBQP); -- Transmit Buffer Queue Pointer Register - TBQP : TBQP_Register; + TBQP : aliased EMAC_TBQP_Register; + pragma Volatile_Full_Access (TBQP); -- Receive Status Register - RSR : RSR_Register; + RSR : aliased EMAC_RSR_Register; + pragma Volatile_Full_Access (RSR); -- Interrupt Status Register - ISR : ISR_Register; + ISR : aliased EMAC_ISR_Register; + pragma Volatile_Full_Access (ISR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased EMAC_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased EMAC_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased EMAC_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Phy Maintenance Register - MAN : MAN_Register; + MAN : aliased EMAC_MAN_Register; + pragma Volatile_Full_Access (MAN); -- Pause Time Register - PTR : PTR_Register; + PTR : aliased EMAC_PTR_Register; + pragma Volatile_Full_Access (PTR); -- Pause Frames Received Register - PFR : PFR_Register; + PFR : aliased EMAC_PFR_Register; + pragma Volatile_Full_Access (PFR); -- Frames Transmitted Ok Register - FTO : FTO_Register; + FTO : aliased EMAC_FTO_Register; + pragma Volatile_Full_Access (FTO); -- Single Collision Frames Register - SCF : SCF_Register; + SCF : aliased EMAC_SCF_Register; + pragma Volatile_Full_Access (SCF); -- Multiple Collision Frames Register - MCF : MCF_Register; + MCF : aliased EMAC_MCF_Register; + pragma Volatile_Full_Access (MCF); -- Frames Received Ok Register - FRO : FRO_Register; + FRO : aliased EMAC_FRO_Register; + pragma Volatile_Full_Access (FRO); -- Frame Check Sequence Errors Register - FCSE : FCSE_Register; + FCSE : aliased EMAC_FCSE_Register; + pragma Volatile_Full_Access (FCSE); -- Alignment Errors Register - ALE : ALE_Register; + ALE : aliased EMAC_ALE_Register; + pragma Volatile_Full_Access (ALE); -- Deferred Transmission Frames Register - DTF : DTF_Register; + DTF : aliased EMAC_DTF_Register; + pragma Volatile_Full_Access (DTF); -- Late Collisions Register - LCOL : LCOL_Register; + LCOL : aliased EMAC_LCOL_Register; + pragma Volatile_Full_Access (LCOL); -- Excessive Collisions Register - ECOL : ECOL_Register; + ECOL : aliased EMAC_ECOL_Register; + pragma Volatile_Full_Access (ECOL); -- Transmit Underrun Errors Register - TUND : TUND_Register; + TUND : aliased EMAC_TUND_Register; + pragma Volatile_Full_Access (TUND); -- Carrier Sense Errors Register - CSE : CSE_Register; + CSE : aliased EMAC_CSE_Register; + pragma Volatile_Full_Access (CSE); -- Receive Resource Errors Register - RRE : RRE_Register; + RRE : aliased EMAC_RRE_Register; + pragma Volatile_Full_Access (RRE); -- Receive Overrun Errors Register - ROV : ROV_Register; + ROV : aliased EMAC_ROV_Register; + pragma Volatile_Full_Access (ROV); -- Receive Symbol Errors Register - RSE : RSE_Register; + RSE : aliased EMAC_RSE_Register; + pragma Volatile_Full_Access (RSE); -- Excessive Length Errors Register - ELE : ELE_Register; + ELE : aliased EMAC_ELE_Register; + pragma Volatile_Full_Access (ELE); -- Receive Jabbers Register - RJA : RJA_Register; + RJA : aliased EMAC_RJA_Register; + pragma Volatile_Full_Access (RJA); -- Undersize Frames Register - USF : USF_Register; + USF : aliased EMAC_USF_Register; + pragma Volatile_Full_Access (USF); -- SQE Test Errors Register - STE : STE_Register; + STE : aliased EMAC_STE_Register; + pragma Volatile_Full_Access (STE); -- Received Length Field Mismatch Register - RLE : RLE_Register; + RLE : aliased EMAC_RLE_Register; + pragma Volatile_Full_Access (RLE); -- Hash Register Bottom [31:0] Register - HRB : ATSAM3X8E.Word; + HRB : aliased ATSAM3X8E.UInt32; -- Hash Register Top [63:32] Register - HRT : ATSAM3X8E.Word; + HRT : aliased ATSAM3X8E.UInt32; -- Specific Address 1 Bottom Register - SA1B : ATSAM3X8E.Word; + SA1B : aliased ATSAM3X8E.UInt32; -- Specific Address 1 Top Register - SA1T : SA1T_Register; + SA1T : aliased EMAC_SA1T_Register; + pragma Volatile_Full_Access (SA1T); -- Specific Address 2 Bottom Register - SA2B : ATSAM3X8E.Word; + SA2B : aliased ATSAM3X8E.UInt32; -- Specific Address 2 Top Register - SA2T : SA2T_Register; + SA2T : aliased EMAC_SA2T_Register; + pragma Volatile_Full_Access (SA2T); -- Specific Address 3 Bottom Register - SA3B : ATSAM3X8E.Word; + SA3B : aliased ATSAM3X8E.UInt32; -- Specific Address 3 Top Register - SA3T : SA3T_Register; + SA3T : aliased EMAC_SA3T_Register; + pragma Volatile_Full_Access (SA3T); -- Specific Address 4 Bottom Register - SA4B : ATSAM3X8E.Word; + SA4B : aliased ATSAM3X8E.UInt32; -- Specific Address 4 Top Register - SA4T : SA4T_Register; + SA4T : aliased EMAC_SA4T_Register; + pragma Volatile_Full_Access (SA4T); -- Type ID Checking Register - TID : TID_Register; + TID : aliased EMAC_TID_Register; + pragma Volatile_Full_Access (TID); -- User Input/Output Register - USRIO : USRIO_Register; + USRIO : aliased EMAC_USRIO_Register; + pragma Volatile_Full_Access (USRIO); end record with Volatile; for EMAC_Peripheral use record - NCR at 0 range 0 .. 31; - NCFGR at 4 range 0 .. 31; - NSR at 8 range 0 .. 31; - TSR at 20 range 0 .. 31; - RBQP at 24 range 0 .. 31; - TBQP at 28 range 0 .. 31; - RSR at 32 range 0 .. 31; - ISR at 36 range 0 .. 31; - IER at 40 range 0 .. 31; - IDR at 44 range 0 .. 31; - IMR at 48 range 0 .. 31; - MAN at 52 range 0 .. 31; - PTR at 56 range 0 .. 31; - PFR at 60 range 0 .. 31; - FTO at 64 range 0 .. 31; - SCF at 68 range 0 .. 31; - MCF at 72 range 0 .. 31; - FRO at 76 range 0 .. 31; - FCSE at 80 range 0 .. 31; - ALE at 84 range 0 .. 31; - DTF at 88 range 0 .. 31; - LCOL at 92 range 0 .. 31; - ECOL at 96 range 0 .. 31; - TUND at 100 range 0 .. 31; - CSE at 104 range 0 .. 31; - RRE at 108 range 0 .. 31; - ROV at 112 range 0 .. 31; - RSE at 116 range 0 .. 31; - ELE at 120 range 0 .. 31; - RJA at 124 range 0 .. 31; - USF at 128 range 0 .. 31; - STE at 132 range 0 .. 31; - RLE at 136 range 0 .. 31; - HRB at 144 range 0 .. 31; - HRT at 148 range 0 .. 31; - SA1B at 152 range 0 .. 31; - SA1T at 156 range 0 .. 31; - SA2B at 160 range 0 .. 31; - SA2T at 164 range 0 .. 31; - SA3B at 168 range 0 .. 31; - SA3T at 172 range 0 .. 31; - SA4B at 176 range 0 .. 31; - SA4T at 180 range 0 .. 31; - TID at 184 range 0 .. 31; - USRIO at 192 range 0 .. 31; + NCR at 16#0# range 0 .. 31; + NCFGR at 16#4# range 0 .. 31; + NSR at 16#8# range 0 .. 31; + TSR at 16#14# range 0 .. 31; + RBQP at 16#18# range 0 .. 31; + TBQP at 16#1C# range 0 .. 31; + RSR at 16#20# range 0 .. 31; + ISR at 16#24# range 0 .. 31; + IER at 16#28# range 0 .. 31; + IDR at 16#2C# range 0 .. 31; + IMR at 16#30# range 0 .. 31; + MAN at 16#34# range 0 .. 31; + PTR at 16#38# range 0 .. 31; + PFR at 16#3C# range 0 .. 31; + FTO at 16#40# range 0 .. 31; + SCF at 16#44# range 0 .. 31; + MCF at 16#48# range 0 .. 31; + FRO at 16#4C# range 0 .. 31; + FCSE at 16#50# range 0 .. 31; + ALE at 16#54# range 0 .. 31; + DTF at 16#58# range 0 .. 31; + LCOL at 16#5C# range 0 .. 31; + ECOL at 16#60# range 0 .. 31; + TUND at 16#64# range 0 .. 31; + CSE at 16#68# range 0 .. 31; + RRE at 16#6C# range 0 .. 31; + ROV at 16#70# range 0 .. 31; + RSE at 16#74# range 0 .. 31; + ELE at 16#78# range 0 .. 31; + RJA at 16#7C# range 0 .. 31; + USF at 16#80# range 0 .. 31; + STE at 16#84# range 0 .. 31; + RLE at 16#88# range 0 .. 31; + HRB at 16#90# range 0 .. 31; + HRT at 16#94# range 0 .. 31; + SA1B at 16#98# range 0 .. 31; + SA1T at 16#9C# range 0 .. 31; + SA2B at 16#A0# range 0 .. 31; + SA2T at 16#A4# range 0 .. 31; + SA3B at 16#A8# range 0 .. 31; + SA3T at 16#AC# range 0 .. 31; + SA4B at 16#B0# range 0 .. 31; + SA4T at 16#B4# range 0 .. 31; + TID at 16#B8# range 0 .. 31; + USRIO at 16#C0# range 0 .. 31; end record; -- Ethernet MAC 10/100 diff --git a/arduino-due/atsam3x8e/atsam3x8e-hsmci.ads b/arduino-due/atsam3x8e/atsam3x8e-hsmci.ads index 18d9c3d..d5d3fb5 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-hsmci.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-hsmci.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,36 +15,32 @@ package ATSAM3X8E.HSMCI is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_MCIEN_Field is ATSAM3X8E.Bit; - subtype CR_MCIDIS_Field is ATSAM3X8E.Bit; - subtype CR_PWSEN_Field is ATSAM3X8E.Bit; - subtype CR_PWSDIS_Field is ATSAM3X8E.Bit; - subtype CR_SWRST_Field is ATSAM3X8E.Bit; + subtype HSMCI_CR_MCIEN_Field is ATSAM3X8E.Bit; + subtype HSMCI_CR_MCIDIS_Field is ATSAM3X8E.Bit; + subtype HSMCI_CR_PWSEN_Field is ATSAM3X8E.Bit; + subtype HSMCI_CR_PWSDIS_Field is ATSAM3X8E.Bit; + subtype HSMCI_CR_SWRST_Field is ATSAM3X8E.Bit; -- Control Register - type CR_Register is record + type HSMCI_CR_Register is record -- Write-only. Multi-Media Interface Enable - MCIEN : CR_MCIEN_Field := 16#0#; + MCIEN : HSMCI_CR_MCIEN_Field := 16#0#; -- Write-only. Multi-Media Interface Disable - MCIDIS : CR_MCIDIS_Field := 16#0#; + MCIDIS : HSMCI_CR_MCIDIS_Field := 16#0#; -- Write-only. Power Save Mode Enable - PWSEN : CR_PWSEN_Field := 16#0#; + PWSEN : HSMCI_CR_PWSEN_Field := 16#0#; -- Write-only. Power Save Mode Disable - PWSDIS : CR_PWSDIS_Field := 16#0#; + PWSDIS : HSMCI_CR_PWSDIS_Field := 16#0#; -- unspecified Reserved_4_6 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. Software Reset - SWRST : CR_SWRST_Field := 16#0#; + SWRST : HSMCI_CR_SWRST_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for HSMCI_CR_Register use record MCIEN at 0 range 0 .. 0; MCIDIS at 0 range 1 .. 1; PWSEN at 0 range 2 .. 2; @@ -53,35 +50,31 @@ package ATSAM3X8E.HSMCI is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- MR_Register -- - ----------------- - - subtype MR_CLKDIV_Field is ATSAM3X8E.Byte; - subtype MR_PWSDIV_Field is ATSAM3X8E.UInt3; - subtype MR_RDPROOF_Field is ATSAM3X8E.Bit; - subtype MR_WRPROOF_Field is ATSAM3X8E.Bit; - subtype MR_FBYTE_Field is ATSAM3X8E.Bit; - subtype MR_PADV_Field is ATSAM3X8E.Bit; + subtype HSMCI_MR_CLKDIV_Field is ATSAM3X8E.Byte; + subtype HSMCI_MR_PWSDIV_Field is ATSAM3X8E.UInt3; + subtype HSMCI_MR_RDPROOF_Field is ATSAM3X8E.Bit; + subtype HSMCI_MR_WRPROOF_Field is ATSAM3X8E.Bit; + subtype HSMCI_MR_FBYTE_Field is ATSAM3X8E.Bit; + subtype HSMCI_MR_PADV_Field is ATSAM3X8E.Bit; -- Mode Register - type MR_Register is record + type HSMCI_MR_Register is record -- Clock Divider - CLKDIV : MR_CLKDIV_Field := 16#0#; + CLKDIV : HSMCI_MR_CLKDIV_Field := 16#0#; -- Power Saving Divider - PWSDIV : MR_PWSDIV_Field := 16#0#; - RDPROOF : MR_RDPROOF_Field := 16#0#; - WRPROOF : MR_WRPROOF_Field := 16#0#; + PWSDIV : HSMCI_MR_PWSDIV_Field := 16#0#; + RDPROOF : HSMCI_MR_RDPROOF_Field := 16#0#; + WRPROOF : HSMCI_MR_WRPROOF_Field := 16#0#; -- Force Byte Transfer - FBYTE : MR_FBYTE_Field := 16#0#; + FBYTE : HSMCI_MR_FBYTE_Field := 16#0#; -- Padding Value - PADV : MR_PADV_Field := 16#0#; + PADV : HSMCI_MR_PADV_Field := 16#0#; -- unspecified Reserved_15_31 : ATSAM3X8E.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_Register use record + for HSMCI_MR_Register use record CLKDIV at 0 range 0 .. 7; PWSDIV at 0 range 8 .. 10; RDPROOF at 0 range 11 .. 11; @@ -91,67 +84,57 @@ package ATSAM3X8E.HSMCI is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------- - -- DTOR_Register -- - ------------------- - - subtype DTOR_DTOCYC_Field is ATSAM3X8E.UInt4; + subtype HSMCI_DTOR_DTOCYC_Field is ATSAM3X8E.UInt4; -- Data Timeout Multiplier - type DTOMUL_Field is - ( - -- DTOCYC - DTOMUL_Field_1, + type DTOR_DTOMUL_Field is + (-- DTOCYC + Val_1, -- DTOCYC x 16 - DTOMUL_Field_16, + Val_16, -- DTOCYC x 128 - DTOMUL_Field_128, + Val_128, -- DTOCYC x 256 - DTOMUL_Field_256, + Val_256, -- DTOCYC x 1024 - DTOMUL_Field_1024, + Val_1024, -- DTOCYC x 4096 - DTOMUL_Field_4096, + Val_4096, -- DTOCYC x 65536 - DTOMUL_Field_65536, + Val_65536, -- DTOCYC x 1048576 - DTOMUL_Field_1048576) + Val_1048576) with Size => 3; - for DTOMUL_Field use - (DTOMUL_Field_1 => 0, - DTOMUL_Field_16 => 1, - DTOMUL_Field_128 => 2, - DTOMUL_Field_256 => 3, - DTOMUL_Field_1024 => 4, - DTOMUL_Field_4096 => 5, - DTOMUL_Field_65536 => 6, - DTOMUL_Field_1048576 => 7); + for DTOR_DTOMUL_Field use + (Val_1 => 0, + Val_16 => 1, + Val_128 => 2, + Val_256 => 3, + Val_1024 => 4, + Val_4096 => 5, + Val_65536 => 6, + Val_1048576 => 7); -- Data Timeout Register - type DTOR_Register is record + type HSMCI_DTOR_Register is record -- Data Timeout Cycle Number - DTOCYC : DTOR_DTOCYC_Field := 16#0#; + DTOCYC : HSMCI_DTOR_DTOCYC_Field := 16#0#; -- Data Timeout Multiplier - DTOMUL : DTOMUL_Field := DTOMUL_Field_1; + DTOMUL : DTOR_DTOMUL_Field := ATSAM3X8E.HSMCI.Val_1; -- unspecified Reserved_7_31 : ATSAM3X8E.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DTOR_Register use record + for HSMCI_DTOR_Register use record DTOCYC at 0 range 0 .. 3; DTOMUL at 0 range 4 .. 6; Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------- - -- SDCR_Register -- - ------------------- - -- SDCard/SDIO Slot - type SDCSEL_Field is - ( - -- Slot A is selected. + type SDCR_SDCSEL_Field is + (-- Slot A is selected. Slota, -- SDCARD/SDIO Slot B selected Slotb, @@ -160,97 +143,89 @@ package ATSAM3X8E.HSMCI is -- - Slotd) with Size => 2; - for SDCSEL_Field use + for SDCR_SDCSEL_Field use (Slota => 0, Slotb => 1, Slotc => 2, Slotd => 3); -- SDCard/SDIO Bus Width - type SDCBUS_Field is - ( - -- 1 bit - SDCBUS_Field_1, + type SDCR_SDCBUS_Field is + (-- 1 bit + Val_1, -- 4 bit - SDCBUS_Field_4, + Val_4, -- 8 bit - SDCBUS_Field_8) + Val_8) with Size => 2; - for SDCBUS_Field use - (SDCBUS_Field_1 => 0, - SDCBUS_Field_4 => 2, - SDCBUS_Field_8 => 3); + for SDCR_SDCBUS_Field use + (Val_1 => 0, + Val_4 => 2, + Val_8 => 3); -- SD/SDIO Card Register - type SDCR_Register is record + type HSMCI_SDCR_Register is record -- SDCard/SDIO Slot - SDCSEL : SDCSEL_Field := Slota; + SDCSEL : SDCR_SDCSEL_Field := ATSAM3X8E.HSMCI.Slota; -- unspecified Reserved_2_5 : ATSAM3X8E.UInt4 := 16#0#; -- SDCard/SDIO Bus Width - SDCBUS : SDCBUS_Field := SDCBUS_Field_1; + SDCBUS : SDCR_SDCBUS_Field := ATSAM3X8E.HSMCI.Val_1; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SDCR_Register use record + for HSMCI_SDCR_Register use record SDCSEL at 0 range 0 .. 1; Reserved_2_5 at 0 range 2 .. 5; SDCBUS at 0 range 6 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- CMDR_Register -- - ------------------- - - subtype CMDR_CMDNB_Field is ATSAM3X8E.UInt6; + subtype HSMCI_CMDR_CMDNB_Field is ATSAM3X8E.UInt6; -- Response Type - type RSPTYP_Field is - ( - -- No response. + type CMDR_RSPTYP_Field is + (-- No response. Noresp, -- 48-bit response. - RSPTYP_Field_48_Bit, + Val_48_Bit, -- 136-bit response. - RSPTYP_Field_136_Bit, + Val_136_Bit, -- R1b response type R1B) with Size => 2; - for RSPTYP_Field use + for CMDR_RSPTYP_Field use (Noresp => 0, - RSPTYP_Field_48_Bit => 1, - RSPTYP_Field_136_Bit => 2, + Val_48_Bit => 1, + Val_136_Bit => 2, R1B => 3); -- Special Command - type SPCMD_Field is - ( - -- Not a special CMD. + type CMDR_SPCMD_Field is + (-- Not a special CMD. Std, -- Initialization CMD: 74 clock cycles for initialization sequence. Init, -- Synchronized CMD: Wait for the end of the current data block transfer - -- before sending the pending command. +-- before sending the pending command. Sync, - -- CE-ATA Completion Signal disable Command. The host cancels the - -- ability for the device to return a command completion signal on the - -- command line. + -- CE-ATA Completion Signal disable Command. The host cancels the ability for +-- the device to return a command completion signal on the command line. Ce_Ata, -- Interrupt command: Corresponds to the Interrupt Mode (CMD40). It_Cmd, -- Interrupt response: Corresponds to the Interrupt Mode (CMD40). It_Resp, - -- Boot Operation Request. Start a boot operation mode, the host - -- processor can read boot data from the MMC device directly. + -- Boot Operation Request. Start a boot operation mode, the host processor can +-- read boot data from the MMC device directly. Bor, - -- End Boot Operation. This command allows the host processor to - -- terminate the boot operation mode. + -- End Boot Operation. This command allows the host processor to terminate the +-- boot operation mode. Ebo) with Size => 3; - for SPCMD_Field use + for CMDR_SPCMD_Field use (Std => 0, Init => 1, Sync => 2, @@ -261,60 +236,55 @@ package ATSAM3X8E.HSMCI is Ebo => 7); -- Open Drain Command - type OPDCMD_Field is - ( - -- Push pull command. + type CMDR_OPDCMD_Field is + (-- Push pull command. Pushpull, -- Open drain command. Opendrain) with Size => 1; - for OPDCMD_Field use + for CMDR_OPDCMD_Field use (Pushpull => 0, Opendrain => 1); -- Max Latency for Command to Response - type MAXLAT_Field is - ( - -- 5-cycle max latency. - MAXLAT_Field_5, + type CMDR_MAXLAT_Field is + (-- 5-cycle max latency. + Val_5, -- 64-cycle max latency. - MAXLAT_Field_64) + Val_64) with Size => 1; - for MAXLAT_Field use - (MAXLAT_Field_5 => 0, - MAXLAT_Field_64 => 1); + for CMDR_MAXLAT_Field use + (Val_5 => 0, + Val_64 => 1); -- Transfer Command - type TRCMD_Field is - ( - -- No data transfer + type CMDR_TRCMD_Field is + (-- No data transfer No_Data, -- Start data transfer Start_Data, -- Stop data transfer Stop_Data) with Size => 2; - for TRCMD_Field use + for CMDR_TRCMD_Field use (No_Data => 0, Start_Data => 1, Stop_Data => 2); -- Transfer Direction - type TRDIR_Field is - ( - -- Write. + type CMDR_TRDIR_Field is + (-- Write. Write, -- Read. Read) with Size => 1; - for TRDIR_Field use + for CMDR_TRDIR_Field use (Write => 0, Read => 1); -- Transfer Type - type TRTYP_Field is - ( - -- MMC/SDCard Single Block + type CMDR_TRTYP_Field is + (-- MMC/SDCard Single Block Single, -- MMC/SDCard Multiple Block Multiple, @@ -325,7 +295,7 @@ package ATSAM3X8E.HSMCI is -- SDIO Block Block) with Size => 3; - for TRTYP_Field use + for CMDR_TRTYP_Field use (Single => 0, Multiple => 1, Stream => 2, @@ -333,69 +303,67 @@ package ATSAM3X8E.HSMCI is Block => 5); -- SDIO Special Command - type IOSPCMD_Field is - ( - -- Not an SDIO Special Command + type CMDR_IOSPCMD_Field is + (-- Not an SDIO Special Command Std, -- SDIO Suspend Command Suspend, -- SDIO Resume Command Resume) with Size => 2; - for IOSPCMD_Field use + for CMDR_IOSPCMD_Field use (Std => 0, Suspend => 1, Resume => 2); -- ATA with Command Completion Signal - type ATACS_Field is - ( - -- Normal operation mode. + type CMDR_ATACS_Field is + (-- Normal operation mode. Normal, - -- This bit indicates that a completion signal is expected within a - -- programmed amount of time (HSMCI_CSTOR). + -- This bit indicates that a completion signal is expected within a programmed +-- amount of time (HSMCI_CSTOR). Completion) with Size => 1; - for ATACS_Field use + for CMDR_ATACS_Field use (Normal => 0, Completion => 1); - subtype CMDR_BOOT_ACK_Field is ATSAM3X8E.Bit; + subtype HSMCI_CMDR_BOOT_ACK_Field is ATSAM3X8E.Bit; -- Command Register - type CMDR_Register is record + type HSMCI_CMDR_Register is record -- Write-only. Command Number - CMDNB : CMDR_CMDNB_Field := 16#0#; + CMDNB : HSMCI_CMDR_CMDNB_Field := 16#0#; -- Write-only. Response Type - RSPTYP : RSPTYP_Field := Noresp; + RSPTYP : CMDR_RSPTYP_Field := ATSAM3X8E.HSMCI.Noresp; -- Write-only. Special Command - SPCMD : SPCMD_Field := Std; + SPCMD : CMDR_SPCMD_Field := ATSAM3X8E.HSMCI.Std; -- Write-only. Open Drain Command - OPDCMD : OPDCMD_Field := Pushpull; + OPDCMD : CMDR_OPDCMD_Field := ATSAM3X8E.HSMCI.Pushpull; -- Write-only. Max Latency for Command to Response - MAXLAT : MAXLAT_Field := MAXLAT_Field_5; + MAXLAT : CMDR_MAXLAT_Field := ATSAM3X8E.HSMCI.Val_5; -- unspecified Reserved_13_15 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. Transfer Command - TRCMD : TRCMD_Field := No_Data; + TRCMD : CMDR_TRCMD_Field := ATSAM3X8E.HSMCI.No_Data; -- Write-only. Transfer Direction - TRDIR : TRDIR_Field := Write; + TRDIR : CMDR_TRDIR_Field := ATSAM3X8E.HSMCI.Write; -- Write-only. Transfer Type - TRTYP : TRTYP_Field := Single; + TRTYP : CMDR_TRTYP_Field := ATSAM3X8E.HSMCI.Single; -- unspecified Reserved_22_23 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. SDIO Special Command - IOSPCMD : IOSPCMD_Field := Std; + IOSPCMD : CMDR_IOSPCMD_Field := ATSAM3X8E.HSMCI.Std; -- Write-only. ATA with Command Completion Signal - ATACS : ATACS_Field := Normal; + ATACS : CMDR_ATACS_Field := ATSAM3X8E.HSMCI.Normal; -- Write-only. Boot Operation Acknowledge. - BOOT_ACK : CMDR_BOOT_ACK_Field := 16#0#; + BOOT_ACK : HSMCI_CMDR_BOOT_ACK_Field := 16#0#; -- unspecified Reserved_28_31 : ATSAM3X8E.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CMDR_Register use record + for HSMCI_CMDR_Register use record CMDNB at 0 range 0 .. 5; RSPTYP at 0 range 6 .. 7; SPCMD at 0 range 8 .. 10; @@ -412,197 +380,179 @@ package ATSAM3X8E.HSMCI is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- BLKR_Register -- - ------------------- - -- MMC/SDIO Block Count - SDIO Byte Count - type BCNT_Field is - ( - -- MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an - -- infinite block transfer. + type BLKR_BCNT_Field is + (-- MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an +-- infinite block transfer. Multiple, -- SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte - -- transfer.Values from 0x200 to 0xFFFF are forbidden. +-- transfer.Values from 0x200 to 0xFFFF are forbidden. Byte, - -- SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite - -- block transfer.Values from 0x200 to 0xFFFF are forbidden. + -- SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block +-- transfer.Values from 0x200 to 0xFFFF are forbidden. Block) with Size => 16; - for BCNT_Field use + for BLKR_BCNT_Field use (Multiple => 0, Byte => 4, Block => 5); - subtype BLKR_BLKLEN_Field is ATSAM3X8E.Short; + subtype HSMCI_BLKR_BLKLEN_Field is ATSAM3X8E.UInt16; -- Block Register - type BLKR_Register is record + type HSMCI_BLKR_Register is record -- MMC/SDIO Block Count - SDIO Byte Count - BCNT : BCNT_Field := Multiple; + BCNT : BLKR_BCNT_Field := ATSAM3X8E.HSMCI.Multiple; -- Data Block Length - BLKLEN : BLKR_BLKLEN_Field := 16#0#; + BLKLEN : HSMCI_BLKR_BLKLEN_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for BLKR_Register use record + for HSMCI_BLKR_Register use record BCNT at 0 range 0 .. 15; BLKLEN at 0 range 16 .. 31; end record; - -------------------- - -- CSTOR_Register -- - -------------------- - - subtype CSTOR_CSTOCYC_Field is ATSAM3X8E.UInt4; + subtype HSMCI_CSTOR_CSTOCYC_Field is ATSAM3X8E.UInt4; -- Completion Signal Timeout Multiplier - type CSTOMUL_Field is - ( - -- CSTOCYC x 1 - CSTOMUL_Field_1, + type CSTOR_CSTOMUL_Field is + (-- CSTOCYC x 1 + Val_1, -- CSTOCYC x 16 - CSTOMUL_Field_16, + Val_16, -- CSTOCYC x 128 - CSTOMUL_Field_128, + Val_128, -- CSTOCYC x 256 - CSTOMUL_Field_256, + Val_256, -- CSTOCYC x 1024 - CSTOMUL_Field_1024, + Val_1024, -- CSTOCYC x 4096 - CSTOMUL_Field_4096, + Val_4096, -- CSTOCYC x 65536 - CSTOMUL_Field_65536, + Val_65536, -- CSTOCYC x 1048576 - CSTOMUL_Field_1048576) + Val_1048576) with Size => 3; - for CSTOMUL_Field use - (CSTOMUL_Field_1 => 0, - CSTOMUL_Field_16 => 1, - CSTOMUL_Field_128 => 2, - CSTOMUL_Field_256 => 3, - CSTOMUL_Field_1024 => 4, - CSTOMUL_Field_4096 => 5, - CSTOMUL_Field_65536 => 6, - CSTOMUL_Field_1048576 => 7); + for CSTOR_CSTOMUL_Field use + (Val_1 => 0, + Val_16 => 1, + Val_128 => 2, + Val_256 => 3, + Val_1024 => 4, + Val_4096 => 5, + Val_65536 => 6, + Val_1048576 => 7); -- Completion Signal Timeout Register - type CSTOR_Register is record + type HSMCI_CSTOR_Register is record -- Completion Signal Timeout Cycle Number - CSTOCYC : CSTOR_CSTOCYC_Field := 16#0#; + CSTOCYC : HSMCI_CSTOR_CSTOCYC_Field := 16#0#; -- Completion Signal Timeout Multiplier - CSTOMUL : CSTOMUL_Field := CSTOMUL_Field_1; + CSTOMUL : CSTOR_CSTOMUL_Field := ATSAM3X8E.HSMCI.Val_1; -- unspecified Reserved_7_31 : ATSAM3X8E.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CSTOR_Register use record + for HSMCI_CSTOR_Register use record CSTOCYC at 0 range 0 .. 3; CSTOMUL at 0 range 4 .. 6; Reserved_7_31 at 0 range 7 .. 31; end record; -- Response Register - - -- Response Register - type RSPR_Registers is array (0 .. 3) of ATSAM3X8E.Word; - - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_CMDRDY_Field is ATSAM3X8E.Bit; - subtype SR_RXRDY_Field is ATSAM3X8E.Bit; - subtype SR_TXRDY_Field is ATSAM3X8E.Bit; - subtype SR_BLKE_Field is ATSAM3X8E.Bit; - subtype SR_DTIP_Field is ATSAM3X8E.Bit; - subtype SR_NOTBUSY_Field is ATSAM3X8E.Bit; - subtype SR_SDIOIRQforSlotA_Field is ATSAM3X8E.Bit; - subtype SR_SDIOIRQforSlotB_Field is ATSAM3X8E.Bit; - subtype SR_SDIOWAIT_Field is ATSAM3X8E.Bit; - subtype SR_CSRCV_Field is ATSAM3X8E.Bit; - subtype SR_RINDE_Field is ATSAM3X8E.Bit; - subtype SR_RDIRE_Field is ATSAM3X8E.Bit; - subtype SR_RCRCE_Field is ATSAM3X8E.Bit; - subtype SR_RENDE_Field is ATSAM3X8E.Bit; - subtype SR_RTOE_Field is ATSAM3X8E.Bit; - subtype SR_DCRCE_Field is ATSAM3X8E.Bit; - subtype SR_DTOE_Field is ATSAM3X8E.Bit; - subtype SR_CSTOE_Field is ATSAM3X8E.Bit; - subtype SR_BLKOVRE_Field is ATSAM3X8E.Bit; - subtype SR_DMADONE_Field is ATSAM3X8E.Bit; - subtype SR_FIFOEMPTY_Field is ATSAM3X8E.Bit; - subtype SR_XFRDONE_Field is ATSAM3X8E.Bit; - subtype SR_ACKRCV_Field is ATSAM3X8E.Bit; - subtype SR_ACKRCVE_Field is ATSAM3X8E.Bit; - subtype SR_OVRE_Field is ATSAM3X8E.Bit; - subtype SR_UNRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_CMDRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_RXRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_TXRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_BLKE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_DTIP_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_NOTBUSY_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_SDIOIRQforSlotA_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_SDIOIRQforSlotB_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_SDIOWAIT_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_CSRCV_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_RINDE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_RDIRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_RCRCE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_RENDE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_RTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_DCRCE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_DTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_CSTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_BLKOVRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_DMADONE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_FIFOEMPTY_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_XFRDONE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_ACKRCV_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_ACKRCVE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_OVRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_SR_UNRE_Field is ATSAM3X8E.Bit; -- Status Register - type SR_Register is record + type HSMCI_SR_Register is record -- Read-only. Command Ready - CMDRDY : SR_CMDRDY_Field := 16#1#; + CMDRDY : HSMCI_SR_CMDRDY_Field; -- Read-only. Receiver Ready - RXRDY : SR_RXRDY_Field := 16#0#; + RXRDY : HSMCI_SR_RXRDY_Field; -- Read-only. Transmit Ready - TXRDY : SR_TXRDY_Field := 16#1#; + TXRDY : HSMCI_SR_TXRDY_Field; -- Read-only. Data Block Ended - BLKE : SR_BLKE_Field := 16#0#; + BLKE : HSMCI_SR_BLKE_Field; -- Read-only. Data Transfer in Progress - DTIP : SR_DTIP_Field := 16#0#; + DTIP : HSMCI_SR_DTIP_Field; -- Read-only. HSMCI Not Busy - NOTBUSY : SR_NOTBUSY_Field := 16#1#; + NOTBUSY : HSMCI_SR_NOTBUSY_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. - SDIOIRQforSlotA : SR_SDIOIRQforSlotA_Field := 16#0#; + SDIOIRQforSlotA : HSMCI_SR_SDIOIRQforSlotA_Field; -- Read-only. - SDIOIRQforSlotB : SR_SDIOIRQforSlotB_Field := 16#0#; + SDIOIRQforSlotB : HSMCI_SR_SDIOIRQforSlotB_Field; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2; -- Read-only. SDIO Read Wait Operation Status - SDIOWAIT : SR_SDIOWAIT_Field := 16#0#; + SDIOWAIT : HSMCI_SR_SDIOWAIT_Field; -- Read-only. CE-ATA Completion Signal Received - CSRCV : SR_CSRCV_Field := 16#0#; + CSRCV : HSMCI_SR_CSRCV_Field; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2; -- Read-only. Response Index Error - RINDE : SR_RINDE_Field := 16#0#; + RINDE : HSMCI_SR_RINDE_Field; -- Read-only. Response Direction Error - RDIRE : SR_RDIRE_Field := 16#0#; + RDIRE : HSMCI_SR_RDIRE_Field; -- Read-only. Response CRC Error - RCRCE : SR_RCRCE_Field := 16#0#; + RCRCE : HSMCI_SR_RCRCE_Field; -- Read-only. Response End Bit Error - RENDE : SR_RENDE_Field := 16#0#; + RENDE : HSMCI_SR_RENDE_Field; -- Read-only. Response Time-out Error - RTOE : SR_RTOE_Field := 16#0#; + RTOE : HSMCI_SR_RTOE_Field; -- Read-only. Data CRC Error - DCRCE : SR_DCRCE_Field := 16#0#; + DCRCE : HSMCI_SR_DCRCE_Field; -- Read-only. Data Time-out Error - DTOE : SR_DTOE_Field := 16#0#; + DTOE : HSMCI_SR_DTOE_Field; -- Read-only. Completion Signal Time-out Error - CSTOE : SR_CSTOE_Field := 16#0#; + CSTOE : HSMCI_SR_CSTOE_Field; -- Read-only. DMA Block Overrun Error - BLKOVRE : SR_BLKOVRE_Field := 16#0#; + BLKOVRE : HSMCI_SR_BLKOVRE_Field; -- Read-only. DMA Transfer done - DMADONE : SR_DMADONE_Field := 16#0#; + DMADONE : HSMCI_SR_DMADONE_Field; -- Read-only. FIFO empty flag - FIFOEMPTY : SR_FIFOEMPTY_Field := 16#0#; + FIFOEMPTY : HSMCI_SR_FIFOEMPTY_Field; -- Read-only. Transfer Done flag - XFRDONE : SR_XFRDONE_Field := 16#0#; + XFRDONE : HSMCI_SR_XFRDONE_Field; -- Read-only. Boot Operation Acknowledge Received - ACKRCV : SR_ACKRCV_Field := 16#0#; + ACKRCV : HSMCI_SR_ACKRCV_Field; -- Read-only. Boot Operation Acknowledge Error - ACKRCVE : SR_ACKRCVE_Field := 16#0#; + ACKRCVE : HSMCI_SR_ACKRCVE_Field; -- Read-only. Overrun - OVRE : SR_OVRE_Field := 16#0#; + OVRE : HSMCI_SR_OVRE_Field; -- Read-only. Underrun - UNRE : SR_UNRE_Field := 16#0#; + UNRE : HSMCI_SR_UNRE_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for HSMCI_SR_Register use record CMDRDY at 0 range 0 .. 0; RXRDY at 0 range 1 .. 1; TXRDY at 0 range 2 .. 2; @@ -634,101 +584,97 @@ package ATSAM3X8E.HSMCI is UNRE at 0 range 31 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_CMDRDY_Field is ATSAM3X8E.Bit; - subtype IER_RXRDY_Field is ATSAM3X8E.Bit; - subtype IER_TXRDY_Field is ATSAM3X8E.Bit; - subtype IER_BLKE_Field is ATSAM3X8E.Bit; - subtype IER_DTIP_Field is ATSAM3X8E.Bit; - subtype IER_NOTBUSY_Field is ATSAM3X8E.Bit; - subtype IER_SDIOIRQforSlotA_Field is ATSAM3X8E.Bit; - subtype IER_SDIOIRQforSlotB_Field is ATSAM3X8E.Bit; - subtype IER_SDIOWAIT_Field is ATSAM3X8E.Bit; - subtype IER_CSRCV_Field is ATSAM3X8E.Bit; - subtype IER_RINDE_Field is ATSAM3X8E.Bit; - subtype IER_RDIRE_Field is ATSAM3X8E.Bit; - subtype IER_RCRCE_Field is ATSAM3X8E.Bit; - subtype IER_RENDE_Field is ATSAM3X8E.Bit; - subtype IER_RTOE_Field is ATSAM3X8E.Bit; - subtype IER_DCRCE_Field is ATSAM3X8E.Bit; - subtype IER_DTOE_Field is ATSAM3X8E.Bit; - subtype IER_CSTOE_Field is ATSAM3X8E.Bit; - subtype IER_BLKOVRE_Field is ATSAM3X8E.Bit; - subtype IER_DMADONE_Field is ATSAM3X8E.Bit; - subtype IER_FIFOEMPTY_Field is ATSAM3X8E.Bit; - subtype IER_XFRDONE_Field is ATSAM3X8E.Bit; - subtype IER_ACKRCV_Field is ATSAM3X8E.Bit; - subtype IER_ACKRCVE_Field is ATSAM3X8E.Bit; - subtype IER_OVRE_Field is ATSAM3X8E.Bit; - subtype IER_UNRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_CMDRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_RXRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_TXRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_BLKE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_DTIP_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_NOTBUSY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_SDIOIRQforSlotA_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_SDIOIRQforSlotB_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_SDIOWAIT_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_CSRCV_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_RINDE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_RDIRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_RCRCE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_RENDE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_RTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_DCRCE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_DTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_CSTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_BLKOVRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_DMADONE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_FIFOEMPTY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_XFRDONE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_ACKRCV_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_ACKRCVE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_OVRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IER_UNRE_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type HSMCI_IER_Register is record -- Write-only. Command Ready Interrupt Enable - CMDRDY : IER_CMDRDY_Field := 16#0#; + CMDRDY : HSMCI_IER_CMDRDY_Field := 16#0#; -- Write-only. Receiver Ready Interrupt Enable - RXRDY : IER_RXRDY_Field := 16#0#; + RXRDY : HSMCI_IER_RXRDY_Field := 16#0#; -- Write-only. Transmit Ready Interrupt Enable - TXRDY : IER_TXRDY_Field := 16#0#; + TXRDY : HSMCI_IER_TXRDY_Field := 16#0#; -- Write-only. Data Block Ended Interrupt Enable - BLKE : IER_BLKE_Field := 16#0#; + BLKE : HSMCI_IER_BLKE_Field := 16#0#; -- Write-only. Data Transfer in Progress Interrupt Enable - DTIP : IER_DTIP_Field := 16#0#; + DTIP : HSMCI_IER_DTIP_Field := 16#0#; -- Write-only. Data Not Busy Interrupt Enable - NOTBUSY : IER_NOTBUSY_Field := 16#0#; + NOTBUSY : HSMCI_IER_NOTBUSY_Field := 16#0#; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. - SDIOIRQforSlotA : IER_SDIOIRQforSlotA_Field := 16#0#; + SDIOIRQforSlotA : HSMCI_IER_SDIOIRQforSlotA_Field := 16#0#; -- Write-only. - SDIOIRQforSlotB : IER_SDIOIRQforSlotB_Field := 16#0#; + SDIOIRQforSlotB : HSMCI_IER_SDIOIRQforSlotB_Field := 16#0#; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. SDIO Read Wait Operation Status Interrupt Enable - SDIOWAIT : IER_SDIOWAIT_Field := 16#0#; + SDIOWAIT : HSMCI_IER_SDIOWAIT_Field := 16#0#; -- Write-only. Completion Signal Received Interrupt Enable - CSRCV : IER_CSRCV_Field := 16#0#; + CSRCV : HSMCI_IER_CSRCV_Field := 16#0#; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Response Index Error Interrupt Enable - RINDE : IER_RINDE_Field := 16#0#; + RINDE : HSMCI_IER_RINDE_Field := 16#0#; -- Write-only. Response Direction Error Interrupt Enable - RDIRE : IER_RDIRE_Field := 16#0#; + RDIRE : HSMCI_IER_RDIRE_Field := 16#0#; -- Write-only. Response CRC Error Interrupt Enable - RCRCE : IER_RCRCE_Field := 16#0#; + RCRCE : HSMCI_IER_RCRCE_Field := 16#0#; -- Write-only. Response End Bit Error Interrupt Enable - RENDE : IER_RENDE_Field := 16#0#; + RENDE : HSMCI_IER_RENDE_Field := 16#0#; -- Write-only. Response Time-out Error Interrupt Enable - RTOE : IER_RTOE_Field := 16#0#; + RTOE : HSMCI_IER_RTOE_Field := 16#0#; -- Write-only. Data CRC Error Interrupt Enable - DCRCE : IER_DCRCE_Field := 16#0#; + DCRCE : HSMCI_IER_DCRCE_Field := 16#0#; -- Write-only. Data Time-out Error Interrupt Enable - DTOE : IER_DTOE_Field := 16#0#; + DTOE : HSMCI_IER_DTOE_Field := 16#0#; -- Write-only. Completion Signal Timeout Error Interrupt Enable - CSTOE : IER_CSTOE_Field := 16#0#; + CSTOE : HSMCI_IER_CSTOE_Field := 16#0#; -- Write-only. DMA Block Overrun Error Interrupt Enable - BLKOVRE : IER_BLKOVRE_Field := 16#0#; + BLKOVRE : HSMCI_IER_BLKOVRE_Field := 16#0#; -- Write-only. DMA Transfer completed Interrupt Enable - DMADONE : IER_DMADONE_Field := 16#0#; + DMADONE : HSMCI_IER_DMADONE_Field := 16#0#; -- Write-only. FIFO empty Interrupt enable - FIFOEMPTY : IER_FIFOEMPTY_Field := 16#0#; + FIFOEMPTY : HSMCI_IER_FIFOEMPTY_Field := 16#0#; -- Write-only. Transfer Done Interrupt enable - XFRDONE : IER_XFRDONE_Field := 16#0#; + XFRDONE : HSMCI_IER_XFRDONE_Field := 16#0#; -- Write-only. Boot Acknowledge Interrupt Enable - ACKRCV : IER_ACKRCV_Field := 16#0#; + ACKRCV : HSMCI_IER_ACKRCV_Field := 16#0#; -- Write-only. Boot Acknowledge Error Interrupt Enable - ACKRCVE : IER_ACKRCVE_Field := 16#0#; + ACKRCVE : HSMCI_IER_ACKRCVE_Field := 16#0#; -- Write-only. Overrun Interrupt Enable - OVRE : IER_OVRE_Field := 16#0#; + OVRE : HSMCI_IER_OVRE_Field := 16#0#; -- Write-only. Underrun Interrupt Enable - UNRE : IER_UNRE_Field := 16#0#; + UNRE : HSMCI_IER_UNRE_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for HSMCI_IER_Register use record CMDRDY at 0 range 0 .. 0; RXRDY at 0 range 1 .. 1; TXRDY at 0 range 2 .. 2; @@ -760,101 +706,97 @@ package ATSAM3X8E.HSMCI is UNRE at 0 range 31 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_CMDRDY_Field is ATSAM3X8E.Bit; - subtype IDR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_BLKE_Field is ATSAM3X8E.Bit; - subtype IDR_DTIP_Field is ATSAM3X8E.Bit; - subtype IDR_NOTBUSY_Field is ATSAM3X8E.Bit; - subtype IDR_SDIOIRQforSlotA_Field is ATSAM3X8E.Bit; - subtype IDR_SDIOIRQforSlotB_Field is ATSAM3X8E.Bit; - subtype IDR_SDIOWAIT_Field is ATSAM3X8E.Bit; - subtype IDR_CSRCV_Field is ATSAM3X8E.Bit; - subtype IDR_RINDE_Field is ATSAM3X8E.Bit; - subtype IDR_RDIRE_Field is ATSAM3X8E.Bit; - subtype IDR_RCRCE_Field is ATSAM3X8E.Bit; - subtype IDR_RENDE_Field is ATSAM3X8E.Bit; - subtype IDR_RTOE_Field is ATSAM3X8E.Bit; - subtype IDR_DCRCE_Field is ATSAM3X8E.Bit; - subtype IDR_DTOE_Field is ATSAM3X8E.Bit; - subtype IDR_CSTOE_Field is ATSAM3X8E.Bit; - subtype IDR_BLKOVRE_Field is ATSAM3X8E.Bit; - subtype IDR_DMADONE_Field is ATSAM3X8E.Bit; - subtype IDR_FIFOEMPTY_Field is ATSAM3X8E.Bit; - subtype IDR_XFRDONE_Field is ATSAM3X8E.Bit; - subtype IDR_ACKRCV_Field is ATSAM3X8E.Bit; - subtype IDR_ACKRCVE_Field is ATSAM3X8E.Bit; - subtype IDR_OVRE_Field is ATSAM3X8E.Bit; - subtype IDR_UNRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_CMDRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_RXRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_TXRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_BLKE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_DTIP_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_NOTBUSY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_SDIOIRQforSlotA_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_SDIOIRQforSlotB_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_SDIOWAIT_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_CSRCV_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_RINDE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_RDIRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_RCRCE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_RENDE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_RTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_DCRCE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_DTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_CSTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_BLKOVRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_DMADONE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_FIFOEMPTY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_XFRDONE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_ACKRCV_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_ACKRCVE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_OVRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IDR_UNRE_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type HSMCI_IDR_Register is record -- Write-only. Command Ready Interrupt Disable - CMDRDY : IDR_CMDRDY_Field := 16#0#; + CMDRDY : HSMCI_IDR_CMDRDY_Field := 16#0#; -- Write-only. Receiver Ready Interrupt Disable - RXRDY : IDR_RXRDY_Field := 16#0#; + RXRDY : HSMCI_IDR_RXRDY_Field := 16#0#; -- Write-only. Transmit Ready Interrupt Disable - TXRDY : IDR_TXRDY_Field := 16#0#; + TXRDY : HSMCI_IDR_TXRDY_Field := 16#0#; -- Write-only. Data Block Ended Interrupt Disable - BLKE : IDR_BLKE_Field := 16#0#; + BLKE : HSMCI_IDR_BLKE_Field := 16#0#; -- Write-only. Data Transfer in Progress Interrupt Disable - DTIP : IDR_DTIP_Field := 16#0#; + DTIP : HSMCI_IDR_DTIP_Field := 16#0#; -- Write-only. Data Not Busy Interrupt Disable - NOTBUSY : IDR_NOTBUSY_Field := 16#0#; + NOTBUSY : HSMCI_IDR_NOTBUSY_Field := 16#0#; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. - SDIOIRQforSlotA : IDR_SDIOIRQforSlotA_Field := 16#0#; + SDIOIRQforSlotA : HSMCI_IDR_SDIOIRQforSlotA_Field := 16#0#; -- Write-only. - SDIOIRQforSlotB : IDR_SDIOIRQforSlotB_Field := 16#0#; + SDIOIRQforSlotB : HSMCI_IDR_SDIOIRQforSlotB_Field := 16#0#; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. SDIO Read Wait Operation Status Interrupt Disable - SDIOWAIT : IDR_SDIOWAIT_Field := 16#0#; + SDIOWAIT : HSMCI_IDR_SDIOWAIT_Field := 16#0#; -- Write-only. Completion Signal received interrupt Disable - CSRCV : IDR_CSRCV_Field := 16#0#; + CSRCV : HSMCI_IDR_CSRCV_Field := 16#0#; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Response Index Error Interrupt Disable - RINDE : IDR_RINDE_Field := 16#0#; + RINDE : HSMCI_IDR_RINDE_Field := 16#0#; -- Write-only. Response Direction Error Interrupt Disable - RDIRE : IDR_RDIRE_Field := 16#0#; + RDIRE : HSMCI_IDR_RDIRE_Field := 16#0#; -- Write-only. Response CRC Error Interrupt Disable - RCRCE : IDR_RCRCE_Field := 16#0#; + RCRCE : HSMCI_IDR_RCRCE_Field := 16#0#; -- Write-only. Response End Bit Error Interrupt Disable - RENDE : IDR_RENDE_Field := 16#0#; + RENDE : HSMCI_IDR_RENDE_Field := 16#0#; -- Write-only. Response Time-out Error Interrupt Disable - RTOE : IDR_RTOE_Field := 16#0#; + RTOE : HSMCI_IDR_RTOE_Field := 16#0#; -- Write-only. Data CRC Error Interrupt Disable - DCRCE : IDR_DCRCE_Field := 16#0#; + DCRCE : HSMCI_IDR_DCRCE_Field := 16#0#; -- Write-only. Data Time-out Error Interrupt Disable - DTOE : IDR_DTOE_Field := 16#0#; + DTOE : HSMCI_IDR_DTOE_Field := 16#0#; -- Write-only. Completion Signal Time out Error Interrupt Disable - CSTOE : IDR_CSTOE_Field := 16#0#; + CSTOE : HSMCI_IDR_CSTOE_Field := 16#0#; -- Write-only. DMA Block Overrun Error Interrupt Disable - BLKOVRE : IDR_BLKOVRE_Field := 16#0#; + BLKOVRE : HSMCI_IDR_BLKOVRE_Field := 16#0#; -- Write-only. DMA Transfer completed Interrupt Disable - DMADONE : IDR_DMADONE_Field := 16#0#; + DMADONE : HSMCI_IDR_DMADONE_Field := 16#0#; -- Write-only. FIFO empty Interrupt Disable - FIFOEMPTY : IDR_FIFOEMPTY_Field := 16#0#; + FIFOEMPTY : HSMCI_IDR_FIFOEMPTY_Field := 16#0#; -- Write-only. Transfer Done Interrupt Disable - XFRDONE : IDR_XFRDONE_Field := 16#0#; + XFRDONE : HSMCI_IDR_XFRDONE_Field := 16#0#; -- Write-only. Boot Acknowledge Interrupt Disable - ACKRCV : IDR_ACKRCV_Field := 16#0#; + ACKRCV : HSMCI_IDR_ACKRCV_Field := 16#0#; -- Write-only. Boot Acknowledge Error Interrupt Disable - ACKRCVE : IDR_ACKRCVE_Field := 16#0#; + ACKRCVE : HSMCI_IDR_ACKRCVE_Field := 16#0#; -- Write-only. Overrun Interrupt Disable - OVRE : IDR_OVRE_Field := 16#0#; + OVRE : HSMCI_IDR_OVRE_Field := 16#0#; -- Write-only. Underrun Interrupt Disable - UNRE : IDR_UNRE_Field := 16#0#; + UNRE : HSMCI_IDR_UNRE_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for HSMCI_IDR_Register use record CMDRDY at 0 range 0 .. 0; RXRDY at 0 range 1 .. 1; TXRDY at 0 range 2 .. 2; @@ -886,101 +828,97 @@ package ATSAM3X8E.HSMCI is UNRE at 0 range 31 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_CMDRDY_Field is ATSAM3X8E.Bit; - subtype IMR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_BLKE_Field is ATSAM3X8E.Bit; - subtype IMR_DTIP_Field is ATSAM3X8E.Bit; - subtype IMR_NOTBUSY_Field is ATSAM3X8E.Bit; - subtype IMR_SDIOIRQforSlotA_Field is ATSAM3X8E.Bit; - subtype IMR_SDIOIRQforSlotB_Field is ATSAM3X8E.Bit; - subtype IMR_SDIOWAIT_Field is ATSAM3X8E.Bit; - subtype IMR_CSRCV_Field is ATSAM3X8E.Bit; - subtype IMR_RINDE_Field is ATSAM3X8E.Bit; - subtype IMR_RDIRE_Field is ATSAM3X8E.Bit; - subtype IMR_RCRCE_Field is ATSAM3X8E.Bit; - subtype IMR_RENDE_Field is ATSAM3X8E.Bit; - subtype IMR_RTOE_Field is ATSAM3X8E.Bit; - subtype IMR_DCRCE_Field is ATSAM3X8E.Bit; - subtype IMR_DTOE_Field is ATSAM3X8E.Bit; - subtype IMR_CSTOE_Field is ATSAM3X8E.Bit; - subtype IMR_BLKOVRE_Field is ATSAM3X8E.Bit; - subtype IMR_DMADONE_Field is ATSAM3X8E.Bit; - subtype IMR_FIFOEMPTY_Field is ATSAM3X8E.Bit; - subtype IMR_XFRDONE_Field is ATSAM3X8E.Bit; - subtype IMR_ACKRCV_Field is ATSAM3X8E.Bit; - subtype IMR_ACKRCVE_Field is ATSAM3X8E.Bit; - subtype IMR_OVRE_Field is ATSAM3X8E.Bit; - subtype IMR_UNRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_CMDRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_RXRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_TXRDY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_BLKE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_DTIP_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_NOTBUSY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_SDIOIRQforSlotA_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_SDIOIRQforSlotB_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_SDIOWAIT_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_CSRCV_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_RINDE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_RDIRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_RCRCE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_RENDE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_RTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_DCRCE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_DTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_CSTOE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_BLKOVRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_DMADONE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_FIFOEMPTY_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_XFRDONE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_ACKRCV_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_ACKRCVE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_OVRE_Field is ATSAM3X8E.Bit; + subtype HSMCI_IMR_UNRE_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type HSMCI_IMR_Register is record -- Read-only. Command Ready Interrupt Mask - CMDRDY : IMR_CMDRDY_Field := 16#0#; + CMDRDY : HSMCI_IMR_CMDRDY_Field; -- Read-only. Receiver Ready Interrupt Mask - RXRDY : IMR_RXRDY_Field := 16#0#; + RXRDY : HSMCI_IMR_RXRDY_Field; -- Read-only. Transmit Ready Interrupt Mask - TXRDY : IMR_TXRDY_Field := 16#0#; + TXRDY : HSMCI_IMR_TXRDY_Field; -- Read-only. Data Block Ended Interrupt Mask - BLKE : IMR_BLKE_Field := 16#0#; + BLKE : HSMCI_IMR_BLKE_Field; -- Read-only. Data Transfer in Progress Interrupt Mask - DTIP : IMR_DTIP_Field := 16#0#; + DTIP : HSMCI_IMR_DTIP_Field; -- Read-only. Data Not Busy Interrupt Mask - NOTBUSY : IMR_NOTBUSY_Field := 16#0#; + NOTBUSY : HSMCI_IMR_NOTBUSY_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. - SDIOIRQforSlotA : IMR_SDIOIRQforSlotA_Field := 16#0#; + SDIOIRQforSlotA : HSMCI_IMR_SDIOIRQforSlotA_Field; -- Read-only. - SDIOIRQforSlotB : IMR_SDIOIRQforSlotB_Field := 16#0#; + SDIOIRQforSlotB : HSMCI_IMR_SDIOIRQforSlotB_Field; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2; -- Read-only. SDIO Read Wait Operation Status Interrupt Mask - SDIOWAIT : IMR_SDIOWAIT_Field := 16#0#; + SDIOWAIT : HSMCI_IMR_SDIOWAIT_Field; -- Read-only. Completion Signal Received Interrupt Mask - CSRCV : IMR_CSRCV_Field := 16#0#; + CSRCV : HSMCI_IMR_CSRCV_Field; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2; -- Read-only. Response Index Error Interrupt Mask - RINDE : IMR_RINDE_Field := 16#0#; + RINDE : HSMCI_IMR_RINDE_Field; -- Read-only. Response Direction Error Interrupt Mask - RDIRE : IMR_RDIRE_Field := 16#0#; + RDIRE : HSMCI_IMR_RDIRE_Field; -- Read-only. Response CRC Error Interrupt Mask - RCRCE : IMR_RCRCE_Field := 16#0#; + RCRCE : HSMCI_IMR_RCRCE_Field; -- Read-only. Response End Bit Error Interrupt Mask - RENDE : IMR_RENDE_Field := 16#0#; + RENDE : HSMCI_IMR_RENDE_Field; -- Read-only. Response Time-out Error Interrupt Mask - RTOE : IMR_RTOE_Field := 16#0#; + RTOE : HSMCI_IMR_RTOE_Field; -- Read-only. Data CRC Error Interrupt Mask - DCRCE : IMR_DCRCE_Field := 16#0#; + DCRCE : HSMCI_IMR_DCRCE_Field; -- Read-only. Data Time-out Error Interrupt Mask - DTOE : IMR_DTOE_Field := 16#0#; + DTOE : HSMCI_IMR_DTOE_Field; -- Read-only. Completion Signal Time-out Error Interrupt Mask - CSTOE : IMR_CSTOE_Field := 16#0#; + CSTOE : HSMCI_IMR_CSTOE_Field; -- Read-only. DMA Block Overrun Error Interrupt Mask - BLKOVRE : IMR_BLKOVRE_Field := 16#0#; + BLKOVRE : HSMCI_IMR_BLKOVRE_Field; -- Read-only. DMA Transfer Completed Interrupt Mask - DMADONE : IMR_DMADONE_Field := 16#0#; + DMADONE : HSMCI_IMR_DMADONE_Field; -- Read-only. FIFO Empty Interrupt Mask - FIFOEMPTY : IMR_FIFOEMPTY_Field := 16#0#; + FIFOEMPTY : HSMCI_IMR_FIFOEMPTY_Field; -- Read-only. Transfer Done Interrupt Mask - XFRDONE : IMR_XFRDONE_Field := 16#0#; + XFRDONE : HSMCI_IMR_XFRDONE_Field; -- Read-only. Boot Operation Acknowledge Received Interrupt Mask - ACKRCV : IMR_ACKRCV_Field := 16#0#; + ACKRCV : HSMCI_IMR_ACKRCV_Field; -- Read-only. Boot Operation Acknowledge Error Interrupt Mask - ACKRCVE : IMR_ACKRCVE_Field := 16#0#; + ACKRCVE : HSMCI_IMR_ACKRCVE_Field; -- Read-only. Overrun Interrupt Mask - OVRE : IMR_OVRE_Field := 16#0#; + OVRE : HSMCI_IMR_OVRE_Field; -- Read-only. Underrun Interrupt Mask - UNRE : IMR_UNRE_Field := 16#0#; + UNRE : HSMCI_IMR_UNRE_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for HSMCI_IMR_Register use record CMDRDY at 0 range 0 .. 0; RXRDY at 0 range 1 .. 1; TXRDY at 0 range 2 .. 2; @@ -1012,49 +950,44 @@ package ATSAM3X8E.HSMCI is UNRE at 0 range 31 .. 31; end record; - ------------------ - -- DMA_Register -- - ------------------ - - subtype DMA_OFFSET_Field is ATSAM3X8E.UInt2; + subtype HSMCI_DMA_OFFSET_Field is ATSAM3X8E.UInt2; -- DMA Channel Read and Write Chunk Size - type CHKSIZE_Field is - ( - -- 1 data available - CHKSIZE_Field_1, + type DMA_CHKSIZE_Field is + (-- 1 data available + Val_1, -- 4 data available - CHKSIZE_Field_4) + Val_4) with Size => 1; - for CHKSIZE_Field use - (CHKSIZE_Field_1 => 0, - CHKSIZE_Field_4 => 1); + for DMA_CHKSIZE_Field use + (Val_1 => 0, + Val_4 => 1); - subtype DMA_DMAEN_Field is ATSAM3X8E.Bit; - subtype DMA_ROPT_Field is ATSAM3X8E.Bit; + subtype HSMCI_DMA_DMAEN_Field is ATSAM3X8E.Bit; + subtype HSMCI_DMA_ROPT_Field is ATSAM3X8E.Bit; -- DMA Configuration Register - type DMA_Register is record + type HSMCI_DMA_Register is record -- DMA Write Buffer Offset - OFFSET : DMA_OFFSET_Field := 16#0#; + OFFSET : HSMCI_DMA_OFFSET_Field := 16#0#; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- DMA Channel Read and Write Chunk Size - CHKSIZE : CHKSIZE_Field := CHKSIZE_Field_1; + CHKSIZE : DMA_CHKSIZE_Field := ATSAM3X8E.HSMCI.Val_1; -- unspecified Reserved_5_7 : ATSAM3X8E.UInt3 := 16#0#; -- DMA Hardware Handshaking Enable - DMAEN : DMA_DMAEN_Field := 16#0#; + DMAEN : HSMCI_DMA_DMAEN_Field := 16#0#; -- unspecified Reserved_9_11 : ATSAM3X8E.UInt3 := 16#0#; -- Read Optimization with padding - ROPT : DMA_ROPT_Field := 16#0#; + ROPT : HSMCI_DMA_ROPT_Field := 16#0#; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMA_Register use record + for HSMCI_DMA_Register use record OFFSET at 0 range 0 .. 1; Reserved_2_3 at 0 range 2 .. 3; CHKSIZE at 0 range 4 .. 4; @@ -1065,37 +998,33 @@ package ATSAM3X8E.HSMCI is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------ - -- CFG_Register -- - ------------------ - - subtype CFG_FIFOMODE_Field is ATSAM3X8E.Bit; - subtype CFG_FERRCTRL_Field is ATSAM3X8E.Bit; - subtype CFG_HSMODE_Field is ATSAM3X8E.Bit; - subtype CFG_LSYNC_Field is ATSAM3X8E.Bit; + subtype HSMCI_CFG_FIFOMODE_Field is ATSAM3X8E.Bit; + subtype HSMCI_CFG_FERRCTRL_Field is ATSAM3X8E.Bit; + subtype HSMCI_CFG_HSMODE_Field is ATSAM3X8E.Bit; + subtype HSMCI_CFG_LSYNC_Field is ATSAM3X8E.Bit; -- Configuration Register - type CFG_Register is record + type HSMCI_CFG_Register is record -- HSMCI Internal FIFO control mode - FIFOMODE : CFG_FIFOMODE_Field := 16#0#; + FIFOMODE : HSMCI_CFG_FIFOMODE_Field := 16#0#; -- unspecified Reserved_1_3 : ATSAM3X8E.UInt3 := 16#0#; -- Flow Error flag reset control mode - FERRCTRL : CFG_FERRCTRL_Field := 16#0#; + FERRCTRL : HSMCI_CFG_FERRCTRL_Field := 16#0#; -- unspecified Reserved_5_7 : ATSAM3X8E.UInt3 := 16#0#; -- High Speed Mode - HSMODE : CFG_HSMODE_Field := 16#0#; + HSMODE : HSMCI_CFG_HSMODE_Field := 16#0#; -- unspecified Reserved_9_11 : ATSAM3X8E.UInt3 := 16#0#; -- Synchronize on the last block - LSYNC : CFG_LSYNC_Field := 16#0#; + LSYNC : HSMCI_CFG_LSYNC_Field := 16#0#; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CFG_Register use record + for HSMCI_CFG_Register use record FIFOMODE at 0 range 0 .. 0; Reserved_1_3 at 0 range 1 .. 3; FERRCTRL at 0 range 4 .. 4; @@ -1106,72 +1035,63 @@ package ATSAM3X8E.HSMCI is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WP_EN_Field is ATSAM3X8E.Bit; - subtype WPMR_WP_KEY_Field is ATSAM3X8E.UInt24; + subtype HSMCI_WPMR_WP_EN_Field is ATSAM3X8E.Bit; + subtype HSMCI_WPMR_WP_KEY_Field is ATSAM3X8E.UInt24; -- Write Protection Mode Register - type WPMR_Register is record + type HSMCI_WPMR_Register is record -- Write Protection Enable - WP_EN : WPMR_WP_EN_Field := 16#0#; + WP_EN : HSMCI_WPMR_WP_EN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protection Key password - WP_KEY : WPMR_WP_KEY_Field := 16#0#; + WP_KEY : HSMCI_WPMR_WP_KEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for HSMCI_WPMR_Register use record WP_EN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WP_KEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - -- Write Protection Violation Status - type WP_VS_Field is - ( - -- No Write Protection Violation occurred since the last read of this - -- register (WP_SR) + type WPSR_WP_VS_Field is + (-- No Write Protection Violation occurred since the last read of this register +-- (WP_SR) None, - -- Write Protection detected unauthorized attempt to write a control - -- register had occurred (since the last read.) + -- Write Protection detected unauthorized attempt to write a control register +-- had occurred (since the last read.) Write, - -- Software reset had been performed while Write Protection was enabled - -- (since the last read). + -- Software reset had been performed while Write Protection was enabled (since +-- the last read). Reset, - -- Both Write Protection violation and software reset with Write - -- Protection enabled have occurred since the last read. + -- Both Write Protection violation and software reset with Write Protection +-- enabled have occurred since the last read. Both) with Size => 4; - for WP_VS_Field use + for WPSR_WP_VS_Field use (None => 0, Write => 1, Reset => 2, Both => 3); - subtype WPSR_WP_VSRC_Field is ATSAM3X8E.Short; + subtype HSMCI_WPSR_WP_VSRC_Field is ATSAM3X8E.UInt16; -- Write Protection Status Register - type WPSR_Register is record + type HSMCI_WPSR_Register is record -- Read-only. Write Protection Violation Status - WP_VS : WP_VS_Field := None; + WP_VS : WPSR_WP_VS_Field; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4; -- Read-only. Write Protection Violation SouRCe - WP_VSRC : WPSR_WP_VSRC_Field := 16#0#; + WP_VSRC : HSMCI_WPSR_WP_VSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for HSMCI_WPSR_Register use record WP_VS at 0 range 0 .. 3; Reserved_4_7 at 0 range 4 .. 7; WP_VSRC at 0 range 8 .. 23; @@ -1180,9 +1100,6 @@ package ATSAM3X8E.HSMCI is -- FIFO Memory Aperture0 - -- FIFO Memory Aperture0 - type FIFO_Registers is array (0 .. 255) of ATSAM3X8E.Word; - ----------------- -- Peripherals -- ----------------- @@ -1190,69 +1107,858 @@ package ATSAM3X8E.HSMCI is -- High Speed MultiMedia Card Interface type HSMCI_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased HSMCI_CR_Register; + pragma Volatile_Full_Access (CR); -- Mode Register - MR : MR_Register; + MR : aliased HSMCI_MR_Register; + pragma Volatile_Full_Access (MR); -- Data Timeout Register - DTOR : DTOR_Register; + DTOR : aliased HSMCI_DTOR_Register; + pragma Volatile_Full_Access (DTOR); -- SD/SDIO Card Register - SDCR : SDCR_Register; + SDCR : aliased HSMCI_SDCR_Register; + pragma Volatile_Full_Access (SDCR); -- Argument Register - ARGR : ATSAM3X8E.Word; + ARGR : aliased ATSAM3X8E.UInt32; -- Command Register - CMDR : CMDR_Register; + CMDR : aliased HSMCI_CMDR_Register; + pragma Volatile_Full_Access (CMDR); -- Block Register - BLKR : BLKR_Register; + BLKR : aliased HSMCI_BLKR_Register; + pragma Volatile_Full_Access (BLKR); -- Completion Signal Timeout Register - CSTOR : CSTOR_Register; + CSTOR : aliased HSMCI_CSTOR_Register; + pragma Volatile_Full_Access (CSTOR); + -- Response Register + RSPR_0 : aliased ATSAM3X8E.UInt32; -- Response Register - RSPR : RSPR_Registers; + RSPR_1 : aliased ATSAM3X8E.UInt32; + -- Response Register + RSPR_2 : aliased ATSAM3X8E.UInt32; + -- Response Register + RSPR_3 : aliased ATSAM3X8E.UInt32; -- Receive Data Register - RDR : ATSAM3X8E.Word; + RDR : aliased ATSAM3X8E.UInt32; -- Transmit Data Register - TDR : ATSAM3X8E.Word; + TDR : aliased ATSAM3X8E.UInt32; -- Status Register - SR : SR_Register; + SR : aliased HSMCI_SR_Register; + pragma Volatile_Full_Access (SR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased HSMCI_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased HSMCI_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased HSMCI_IMR_Register; + pragma Volatile_Full_Access (IMR); -- DMA Configuration Register - DMA : DMA_Register; + DMA : aliased HSMCI_DMA_Register; + pragma Volatile_Full_Access (DMA); -- Configuration Register - CFG : CFG_Register; + CFG : aliased HSMCI_CFG_Register; + pragma Volatile_Full_Access (CFG); -- Write Protection Mode Register - WPMR : WPMR_Register; + WPMR : aliased HSMCI_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- Write Protection Status Register - WPSR : WPSR_Register; + WPSR : aliased HSMCI_WPSR_Register; + pragma Volatile_Full_Access (WPSR); + -- FIFO Memory Aperture0 + FIFO_0 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_1 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_2 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_3 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_4 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_5 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_6 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_7 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_8 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_9 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_10 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_11 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_12 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_13 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_14 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_15 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_16 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_17 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_18 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_19 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_20 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_21 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_22 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_23 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_24 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_25 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_26 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_27 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_28 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_29 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_30 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_31 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_32 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_33 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_34 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_35 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_36 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_37 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_38 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_39 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_40 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_41 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_42 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_43 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_44 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_45 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_46 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_47 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_48 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_49 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_50 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_51 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_52 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_53 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_54 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_55 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_56 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_57 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_58 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_59 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_60 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_61 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_62 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_63 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_64 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_65 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_66 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_67 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_68 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_69 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_70 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_71 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_72 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_73 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_74 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_75 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_76 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_77 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_78 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_79 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_80 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_81 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_82 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_83 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_84 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_85 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_86 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_87 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_88 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_89 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_90 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_91 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_92 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_93 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_94 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_95 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_96 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_97 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_98 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_99 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_100 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_101 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_102 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_103 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_104 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_105 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_106 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_107 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_108 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_109 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_110 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_111 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_112 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_113 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_114 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_115 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_116 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_117 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_118 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_119 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_120 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_121 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_122 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_123 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_124 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_125 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_126 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_127 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_128 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_129 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_130 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_131 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_132 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_133 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_134 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_135 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_136 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_137 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_138 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_139 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_140 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_141 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_142 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_143 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_144 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_145 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_146 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_147 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_148 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_149 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_150 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_151 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_152 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_153 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_154 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_155 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_156 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_157 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_158 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_159 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_160 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_161 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_162 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_163 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_164 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_165 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_166 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_167 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_168 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_169 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_170 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_171 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_172 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_173 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_174 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_175 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_176 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_177 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_178 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_179 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_180 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_181 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_182 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_183 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_184 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_185 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_186 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_187 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_188 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_189 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_190 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_191 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_192 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_193 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_194 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_195 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_196 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_197 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_198 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_199 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_200 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_201 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_202 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_203 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_204 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_205 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_206 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_207 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_208 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_209 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_210 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_211 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_212 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_213 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_214 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_215 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_216 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_217 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_218 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_219 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_220 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_221 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_222 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_223 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_224 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_225 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_226 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_227 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_228 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_229 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_230 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_231 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_232 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_233 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_234 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_235 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_236 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_237 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_238 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_239 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_240 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_241 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_242 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_243 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_244 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_245 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_246 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_247 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_248 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_249 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_250 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_251 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_252 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_253 : aliased ATSAM3X8E.UInt32; + -- FIFO Memory Aperture0 + FIFO_254 : aliased ATSAM3X8E.UInt32; -- FIFO Memory Aperture0 - FIFO : FIFO_Registers; + FIFO_255 : aliased ATSAM3X8E.UInt32; end record with Volatile; for HSMCI_Peripheral use record - CR at 0 range 0 .. 31; - MR at 4 range 0 .. 31; - DTOR at 8 range 0 .. 31; - SDCR at 12 range 0 .. 31; - ARGR at 16 range 0 .. 31; - CMDR at 20 range 0 .. 31; - BLKR at 24 range 0 .. 31; - CSTOR at 28 range 0 .. 31; - RSPR at 32 range 0 .. 127; - RDR at 48 range 0 .. 31; - TDR at 52 range 0 .. 31; - SR at 64 range 0 .. 31; - IER at 68 range 0 .. 31; - IDR at 72 range 0 .. 31; - IMR at 76 range 0 .. 31; - DMA at 80 range 0 .. 31; - CFG at 84 range 0 .. 31; - WPMR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; - FIFO at 512 range 0 .. 8191; + CR at 16#0# range 0 .. 31; + MR at 16#4# range 0 .. 31; + DTOR at 16#8# range 0 .. 31; + SDCR at 16#C# range 0 .. 31; + ARGR at 16#10# range 0 .. 31; + CMDR at 16#14# range 0 .. 31; + BLKR at 16#18# range 0 .. 31; + CSTOR at 16#1C# range 0 .. 31; + RSPR_0 at 16#20# range 0 .. 31; + RSPR_1 at 16#24# range 0 .. 31; + RSPR_2 at 16#28# range 0 .. 31; + RSPR_3 at 16#2C# range 0 .. 31; + RDR at 16#30# range 0 .. 31; + TDR at 16#34# range 0 .. 31; + SR at 16#40# range 0 .. 31; + IER at 16#44# range 0 .. 31; + IDR at 16#48# range 0 .. 31; + IMR at 16#4C# range 0 .. 31; + DMA at 16#50# range 0 .. 31; + CFG at 16#54# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; + FIFO_0 at 16#200# range 0 .. 31; + FIFO_1 at 16#204# range 0 .. 31; + FIFO_2 at 16#208# range 0 .. 31; + FIFO_3 at 16#20C# range 0 .. 31; + FIFO_4 at 16#210# range 0 .. 31; + FIFO_5 at 16#214# range 0 .. 31; + FIFO_6 at 16#218# range 0 .. 31; + FIFO_7 at 16#21C# range 0 .. 31; + FIFO_8 at 16#220# range 0 .. 31; + FIFO_9 at 16#224# range 0 .. 31; + FIFO_10 at 16#228# range 0 .. 31; + FIFO_11 at 16#22C# range 0 .. 31; + FIFO_12 at 16#230# range 0 .. 31; + FIFO_13 at 16#234# range 0 .. 31; + FIFO_14 at 16#238# range 0 .. 31; + FIFO_15 at 16#23C# range 0 .. 31; + FIFO_16 at 16#240# range 0 .. 31; + FIFO_17 at 16#244# range 0 .. 31; + FIFO_18 at 16#248# range 0 .. 31; + FIFO_19 at 16#24C# range 0 .. 31; + FIFO_20 at 16#250# range 0 .. 31; + FIFO_21 at 16#254# range 0 .. 31; + FIFO_22 at 16#258# range 0 .. 31; + FIFO_23 at 16#25C# range 0 .. 31; + FIFO_24 at 16#260# range 0 .. 31; + FIFO_25 at 16#264# range 0 .. 31; + FIFO_26 at 16#268# range 0 .. 31; + FIFO_27 at 16#26C# range 0 .. 31; + FIFO_28 at 16#270# range 0 .. 31; + FIFO_29 at 16#274# range 0 .. 31; + FIFO_30 at 16#278# range 0 .. 31; + FIFO_31 at 16#27C# range 0 .. 31; + FIFO_32 at 16#280# range 0 .. 31; + FIFO_33 at 16#284# range 0 .. 31; + FIFO_34 at 16#288# range 0 .. 31; + FIFO_35 at 16#28C# range 0 .. 31; + FIFO_36 at 16#290# range 0 .. 31; + FIFO_37 at 16#294# range 0 .. 31; + FIFO_38 at 16#298# range 0 .. 31; + FIFO_39 at 16#29C# range 0 .. 31; + FIFO_40 at 16#2A0# range 0 .. 31; + FIFO_41 at 16#2A4# range 0 .. 31; + FIFO_42 at 16#2A8# range 0 .. 31; + FIFO_43 at 16#2AC# range 0 .. 31; + FIFO_44 at 16#2B0# range 0 .. 31; + FIFO_45 at 16#2B4# range 0 .. 31; + FIFO_46 at 16#2B8# range 0 .. 31; + FIFO_47 at 16#2BC# range 0 .. 31; + FIFO_48 at 16#2C0# range 0 .. 31; + FIFO_49 at 16#2C4# range 0 .. 31; + FIFO_50 at 16#2C8# range 0 .. 31; + FIFO_51 at 16#2CC# range 0 .. 31; + FIFO_52 at 16#2D0# range 0 .. 31; + FIFO_53 at 16#2D4# range 0 .. 31; + FIFO_54 at 16#2D8# range 0 .. 31; + FIFO_55 at 16#2DC# range 0 .. 31; + FIFO_56 at 16#2E0# range 0 .. 31; + FIFO_57 at 16#2E4# range 0 .. 31; + FIFO_58 at 16#2E8# range 0 .. 31; + FIFO_59 at 16#2EC# range 0 .. 31; + FIFO_60 at 16#2F0# range 0 .. 31; + FIFO_61 at 16#2F4# range 0 .. 31; + FIFO_62 at 16#2F8# range 0 .. 31; + FIFO_63 at 16#2FC# range 0 .. 31; + FIFO_64 at 16#300# range 0 .. 31; + FIFO_65 at 16#304# range 0 .. 31; + FIFO_66 at 16#308# range 0 .. 31; + FIFO_67 at 16#30C# range 0 .. 31; + FIFO_68 at 16#310# range 0 .. 31; + FIFO_69 at 16#314# range 0 .. 31; + FIFO_70 at 16#318# range 0 .. 31; + FIFO_71 at 16#31C# range 0 .. 31; + FIFO_72 at 16#320# range 0 .. 31; + FIFO_73 at 16#324# range 0 .. 31; + FIFO_74 at 16#328# range 0 .. 31; + FIFO_75 at 16#32C# range 0 .. 31; + FIFO_76 at 16#330# range 0 .. 31; + FIFO_77 at 16#334# range 0 .. 31; + FIFO_78 at 16#338# range 0 .. 31; + FIFO_79 at 16#33C# range 0 .. 31; + FIFO_80 at 16#340# range 0 .. 31; + FIFO_81 at 16#344# range 0 .. 31; + FIFO_82 at 16#348# range 0 .. 31; + FIFO_83 at 16#34C# range 0 .. 31; + FIFO_84 at 16#350# range 0 .. 31; + FIFO_85 at 16#354# range 0 .. 31; + FIFO_86 at 16#358# range 0 .. 31; + FIFO_87 at 16#35C# range 0 .. 31; + FIFO_88 at 16#360# range 0 .. 31; + FIFO_89 at 16#364# range 0 .. 31; + FIFO_90 at 16#368# range 0 .. 31; + FIFO_91 at 16#36C# range 0 .. 31; + FIFO_92 at 16#370# range 0 .. 31; + FIFO_93 at 16#374# range 0 .. 31; + FIFO_94 at 16#378# range 0 .. 31; + FIFO_95 at 16#37C# range 0 .. 31; + FIFO_96 at 16#380# range 0 .. 31; + FIFO_97 at 16#384# range 0 .. 31; + FIFO_98 at 16#388# range 0 .. 31; + FIFO_99 at 16#38C# range 0 .. 31; + FIFO_100 at 16#390# range 0 .. 31; + FIFO_101 at 16#394# range 0 .. 31; + FIFO_102 at 16#398# range 0 .. 31; + FIFO_103 at 16#39C# range 0 .. 31; + FIFO_104 at 16#3A0# range 0 .. 31; + FIFO_105 at 16#3A4# range 0 .. 31; + FIFO_106 at 16#3A8# range 0 .. 31; + FIFO_107 at 16#3AC# range 0 .. 31; + FIFO_108 at 16#3B0# range 0 .. 31; + FIFO_109 at 16#3B4# range 0 .. 31; + FIFO_110 at 16#3B8# range 0 .. 31; + FIFO_111 at 16#3BC# range 0 .. 31; + FIFO_112 at 16#3C0# range 0 .. 31; + FIFO_113 at 16#3C4# range 0 .. 31; + FIFO_114 at 16#3C8# range 0 .. 31; + FIFO_115 at 16#3CC# range 0 .. 31; + FIFO_116 at 16#3D0# range 0 .. 31; + FIFO_117 at 16#3D4# range 0 .. 31; + FIFO_118 at 16#3D8# range 0 .. 31; + FIFO_119 at 16#3DC# range 0 .. 31; + FIFO_120 at 16#3E0# range 0 .. 31; + FIFO_121 at 16#3E4# range 0 .. 31; + FIFO_122 at 16#3E8# range 0 .. 31; + FIFO_123 at 16#3EC# range 0 .. 31; + FIFO_124 at 16#3F0# range 0 .. 31; + FIFO_125 at 16#3F4# range 0 .. 31; + FIFO_126 at 16#3F8# range 0 .. 31; + FIFO_127 at 16#3FC# range 0 .. 31; + FIFO_128 at 16#400# range 0 .. 31; + FIFO_129 at 16#404# range 0 .. 31; + FIFO_130 at 16#408# range 0 .. 31; + FIFO_131 at 16#40C# range 0 .. 31; + FIFO_132 at 16#410# range 0 .. 31; + FIFO_133 at 16#414# range 0 .. 31; + FIFO_134 at 16#418# range 0 .. 31; + FIFO_135 at 16#41C# range 0 .. 31; + FIFO_136 at 16#420# range 0 .. 31; + FIFO_137 at 16#424# range 0 .. 31; + FIFO_138 at 16#428# range 0 .. 31; + FIFO_139 at 16#42C# range 0 .. 31; + FIFO_140 at 16#430# range 0 .. 31; + FIFO_141 at 16#434# range 0 .. 31; + FIFO_142 at 16#438# range 0 .. 31; + FIFO_143 at 16#43C# range 0 .. 31; + FIFO_144 at 16#440# range 0 .. 31; + FIFO_145 at 16#444# range 0 .. 31; + FIFO_146 at 16#448# range 0 .. 31; + FIFO_147 at 16#44C# range 0 .. 31; + FIFO_148 at 16#450# range 0 .. 31; + FIFO_149 at 16#454# range 0 .. 31; + FIFO_150 at 16#458# range 0 .. 31; + FIFO_151 at 16#45C# range 0 .. 31; + FIFO_152 at 16#460# range 0 .. 31; + FIFO_153 at 16#464# range 0 .. 31; + FIFO_154 at 16#468# range 0 .. 31; + FIFO_155 at 16#46C# range 0 .. 31; + FIFO_156 at 16#470# range 0 .. 31; + FIFO_157 at 16#474# range 0 .. 31; + FIFO_158 at 16#478# range 0 .. 31; + FIFO_159 at 16#47C# range 0 .. 31; + FIFO_160 at 16#480# range 0 .. 31; + FIFO_161 at 16#484# range 0 .. 31; + FIFO_162 at 16#488# range 0 .. 31; + FIFO_163 at 16#48C# range 0 .. 31; + FIFO_164 at 16#490# range 0 .. 31; + FIFO_165 at 16#494# range 0 .. 31; + FIFO_166 at 16#498# range 0 .. 31; + FIFO_167 at 16#49C# range 0 .. 31; + FIFO_168 at 16#4A0# range 0 .. 31; + FIFO_169 at 16#4A4# range 0 .. 31; + FIFO_170 at 16#4A8# range 0 .. 31; + FIFO_171 at 16#4AC# range 0 .. 31; + FIFO_172 at 16#4B0# range 0 .. 31; + FIFO_173 at 16#4B4# range 0 .. 31; + FIFO_174 at 16#4B8# range 0 .. 31; + FIFO_175 at 16#4BC# range 0 .. 31; + FIFO_176 at 16#4C0# range 0 .. 31; + FIFO_177 at 16#4C4# range 0 .. 31; + FIFO_178 at 16#4C8# range 0 .. 31; + FIFO_179 at 16#4CC# range 0 .. 31; + FIFO_180 at 16#4D0# range 0 .. 31; + FIFO_181 at 16#4D4# range 0 .. 31; + FIFO_182 at 16#4D8# range 0 .. 31; + FIFO_183 at 16#4DC# range 0 .. 31; + FIFO_184 at 16#4E0# range 0 .. 31; + FIFO_185 at 16#4E4# range 0 .. 31; + FIFO_186 at 16#4E8# range 0 .. 31; + FIFO_187 at 16#4EC# range 0 .. 31; + FIFO_188 at 16#4F0# range 0 .. 31; + FIFO_189 at 16#4F4# range 0 .. 31; + FIFO_190 at 16#4F8# range 0 .. 31; + FIFO_191 at 16#4FC# range 0 .. 31; + FIFO_192 at 16#500# range 0 .. 31; + FIFO_193 at 16#504# range 0 .. 31; + FIFO_194 at 16#508# range 0 .. 31; + FIFO_195 at 16#50C# range 0 .. 31; + FIFO_196 at 16#510# range 0 .. 31; + FIFO_197 at 16#514# range 0 .. 31; + FIFO_198 at 16#518# range 0 .. 31; + FIFO_199 at 16#51C# range 0 .. 31; + FIFO_200 at 16#520# range 0 .. 31; + FIFO_201 at 16#524# range 0 .. 31; + FIFO_202 at 16#528# range 0 .. 31; + FIFO_203 at 16#52C# range 0 .. 31; + FIFO_204 at 16#530# range 0 .. 31; + FIFO_205 at 16#534# range 0 .. 31; + FIFO_206 at 16#538# range 0 .. 31; + FIFO_207 at 16#53C# range 0 .. 31; + FIFO_208 at 16#540# range 0 .. 31; + FIFO_209 at 16#544# range 0 .. 31; + FIFO_210 at 16#548# range 0 .. 31; + FIFO_211 at 16#54C# range 0 .. 31; + FIFO_212 at 16#550# range 0 .. 31; + FIFO_213 at 16#554# range 0 .. 31; + FIFO_214 at 16#558# range 0 .. 31; + FIFO_215 at 16#55C# range 0 .. 31; + FIFO_216 at 16#560# range 0 .. 31; + FIFO_217 at 16#564# range 0 .. 31; + FIFO_218 at 16#568# range 0 .. 31; + FIFO_219 at 16#56C# range 0 .. 31; + FIFO_220 at 16#570# range 0 .. 31; + FIFO_221 at 16#574# range 0 .. 31; + FIFO_222 at 16#578# range 0 .. 31; + FIFO_223 at 16#57C# range 0 .. 31; + FIFO_224 at 16#580# range 0 .. 31; + FIFO_225 at 16#584# range 0 .. 31; + FIFO_226 at 16#588# range 0 .. 31; + FIFO_227 at 16#58C# range 0 .. 31; + FIFO_228 at 16#590# range 0 .. 31; + FIFO_229 at 16#594# range 0 .. 31; + FIFO_230 at 16#598# range 0 .. 31; + FIFO_231 at 16#59C# range 0 .. 31; + FIFO_232 at 16#5A0# range 0 .. 31; + FIFO_233 at 16#5A4# range 0 .. 31; + FIFO_234 at 16#5A8# range 0 .. 31; + FIFO_235 at 16#5AC# range 0 .. 31; + FIFO_236 at 16#5B0# range 0 .. 31; + FIFO_237 at 16#5B4# range 0 .. 31; + FIFO_238 at 16#5B8# range 0 .. 31; + FIFO_239 at 16#5BC# range 0 .. 31; + FIFO_240 at 16#5C0# range 0 .. 31; + FIFO_241 at 16#5C4# range 0 .. 31; + FIFO_242 at 16#5C8# range 0 .. 31; + FIFO_243 at 16#5CC# range 0 .. 31; + FIFO_244 at 16#5D0# range 0 .. 31; + FIFO_245 at 16#5D4# range 0 .. 31; + FIFO_246 at 16#5D8# range 0 .. 31; + FIFO_247 at 16#5DC# range 0 .. 31; + FIFO_248 at 16#5E0# range 0 .. 31; + FIFO_249 at 16#5E4# range 0 .. 31; + FIFO_250 at 16#5E8# range 0 .. 31; + FIFO_251 at 16#5EC# range 0 .. 31; + FIFO_252 at 16#5F0# range 0 .. 31; + FIFO_253 at 16#5F4# range 0 .. 31; + FIFO_254 at 16#5F8# range 0 .. 31; + FIFO_255 at 16#5FC# range 0 .. 31; end record; -- High Speed MultiMedia Card Interface diff --git a/arduino-due/atsam3x8e/atsam3x8e-matrix.ads b/arduino-due/atsam3x8e/atsam3x8e-matrix.ads index fe58e1f..5ac8a1d 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-matrix.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-matrix.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,10 +15,6 @@ package ATSAM3X8E.MATRIX is -- Registers -- --------------- - -------------------------- - -- MATRIX_MCFG_Register -- - -------------------------- - subtype MATRIX_MCFG_ULBT_Field is ATSAM3X8E.UInt3; -- Master Configuration Register @@ -27,20 +24,13 @@ package ATSAM3X8E.MATRIX is -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MATRIX_MCFG_Register use record ULBT at 0 range 0 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - -- Master Configuration Register - type MATRIX_MCFG_Registers is array (0 .. 5) of MATRIX_MCFG_Register; - - -------------------------- - -- MATRIX_SCFG_Register -- - -------------------------- - subtype MATRIX_SCFG_SLOT_CYCLE_Field is ATSAM3X8E.Byte; subtype MATRIX_SCFG_DEFMSTR_TYPE_Field is ATSAM3X8E.UInt2; subtype MATRIX_SCFG_FIXED_DEFMSTR_Field is ATSAM3X8E.UInt3; @@ -63,7 +53,7 @@ package ATSAM3X8E.MATRIX is -- unspecified Reserved_26_31 : ATSAM3X8E.UInt6 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MATRIX_SCFG_Register use record SLOT_CYCLE at 0 range 0 .. 7; @@ -75,48 +65,41 @@ package ATSAM3X8E.MATRIX is Reserved_26_31 at 0 range 26 .. 31; end record; - -- Slave Configuration Register - type MATRIX_SCFG_Registers is array (0 .. 8) of MATRIX_SCFG_Register; - - -------------------------- - -- MATRIX_PRAS_Register -- - -------------------------- - - subtype MATRIX_PRAS0_M0PR_Field is ATSAM3X8E.UInt2; - subtype MATRIX_PRAS0_M1PR_Field is ATSAM3X8E.UInt2; - subtype MATRIX_PRAS0_M2PR_Field is ATSAM3X8E.UInt2; - subtype MATRIX_PRAS0_M3PR_Field is ATSAM3X8E.UInt2; - subtype MATRIX_PRAS0_M4PR_Field is ATSAM3X8E.UInt2; - subtype MATRIX_PRAS0_M5PR_Field is ATSAM3X8E.UInt2; + subtype MATRIX_PRAS_M0PR_Field is ATSAM3X8E.UInt2; + subtype MATRIX_PRAS_M1PR_Field is ATSAM3X8E.UInt2; + subtype MATRIX_PRAS_M2PR_Field is ATSAM3X8E.UInt2; + subtype MATRIX_PRAS_M3PR_Field is ATSAM3X8E.UInt2; + subtype MATRIX_PRAS_M4PR_Field is ATSAM3X8E.UInt2; + subtype MATRIX_PRAS_M5PR_Field is ATSAM3X8E.UInt2; -- Priority Register A for Slave 0 type MATRIX_PRAS_Register is record -- Master 0 Priority - M0PR : MATRIX_PRAS0_M0PR_Field := 16#0#; + M0PR : MATRIX_PRAS_M0PR_Field := 16#0#; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- Master 1 Priority - M1PR : MATRIX_PRAS0_M1PR_Field := 16#0#; + M1PR : MATRIX_PRAS_M1PR_Field := 16#0#; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Master 2 Priority - M2PR : MATRIX_PRAS0_M2PR_Field := 16#0#; + M2PR : MATRIX_PRAS_M2PR_Field := 16#0#; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2 := 16#0#; -- Master 3 Priority - M3PR : MATRIX_PRAS0_M3PR_Field := 16#0#; + M3PR : MATRIX_PRAS_M3PR_Field := 16#0#; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Master 4 Priority - M4PR : MATRIX_PRAS0_M4PR_Field := 16#0#; + M4PR : MATRIX_PRAS_M4PR_Field := 16#0#; -- unspecified Reserved_18_19 : ATSAM3X8E.UInt2 := 16#0#; -- Master 5 Priority - M5PR : MATRIX_PRAS0_M5PR_Field := 16#0#; + M5PR : MATRIX_PRAS_M5PR_Field := 16#0#; -- unspecified Reserved_22_31 : ATSAM3X8E.UInt10 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MATRIX_PRAS_Register use record M0PR at 0 range 0 .. 1; @@ -133,14 +116,6 @@ package ATSAM3X8E.MATRIX is Reserved_22_31 at 0 range 22 .. 31; end record; - -------------------------- - -- MATRIX_MRCR_Register -- - -------------------------- - - --------------------- - -- MATRIX_MRCR.RCB -- - --------------------- - -- MATRIX_MRCR_RCB array element subtype MATRIX_MRCR_RCB_Element is ATSAM3X8E.Bit; @@ -184,7 +159,7 @@ package ATSAM3X8E.MATRIX is -- unspecified Reserved_7_31 : ATSAM3X8E.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MATRIX_MRCR_Register use record RCB at 0 range 0 .. 3; @@ -193,10 +168,6 @@ package ATSAM3X8E.MATRIX is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------------- - -- CCFG_SYSIO_Register -- - ------------------------- - subtype CCFG_SYSIO_SYSIO12_Field is ATSAM3X8E.Bit; -- System I/O Configuration register @@ -208,7 +179,7 @@ package ATSAM3X8E.MATRIX is -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCFG_SYSIO_Register use record Reserved_0_11 at 0 range 0 .. 11; @@ -216,10 +187,6 @@ package ATSAM3X8E.MATRIX is Reserved_13_31 at 0 range 13 .. 31; end record; - -------------------------- - -- MATRIX_WPMR_Register -- - -------------------------- - subtype MATRIX_WPMR_WPEN_Field is ATSAM3X8E.Bit; subtype MATRIX_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; @@ -232,7 +199,7 @@ package ATSAM3X8E.MATRIX is -- Write Protect KEY (Write-only) WPKEY : MATRIX_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MATRIX_WPMR_Register use record WPEN at 0 range 0 .. 0; @@ -240,25 +207,21 @@ package ATSAM3X8E.MATRIX is WPKEY at 0 range 8 .. 31; end record; - -------------------------- - -- MATRIX_WPSR_Register -- - -------------------------- - subtype MATRIX_WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype MATRIX_WPSR_WPVSRC_Field is ATSAM3X8E.Short; + subtype MATRIX_WPSR_WPVSRC_Field is ATSAM3X8E.UInt16; -- Write Protect Status Register type MATRIX_WPSR_Register is record -- Read-only. Write Protect Violation Status - WPVS : MATRIX_WPSR_WPVS_Field := 16#0#; + WPVS : MATRIX_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protect Violation Source - WPVSRC : MATRIX_WPSR_WPVSRC_Field := 16#0#; + WPVSRC : MATRIX_WPSR_WPVSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MATRIX_WPSR_Register use record WPVS at 0 range 0 .. 0; @@ -274,54 +237,121 @@ package ATSAM3X8E.MATRIX is -- AHB Bus Matrix type MATRIX_Peripheral is record -- Master Configuration Register - MATRIX_MCFG : MATRIX_MCFG_Registers; + MATRIX_MCFG_0 : aliased MATRIX_MCFG_Register; + pragma Volatile_Full_Access (MATRIX_MCFG_0); + -- Master Configuration Register + MATRIX_MCFG_1 : aliased MATRIX_MCFG_Register; + pragma Volatile_Full_Access (MATRIX_MCFG_1); + -- Master Configuration Register + MATRIX_MCFG_2 : aliased MATRIX_MCFG_Register; + pragma Volatile_Full_Access (MATRIX_MCFG_2); + -- Master Configuration Register + MATRIX_MCFG_3 : aliased MATRIX_MCFG_Register; + pragma Volatile_Full_Access (MATRIX_MCFG_3); + -- Master Configuration Register + MATRIX_MCFG_4 : aliased MATRIX_MCFG_Register; + pragma Volatile_Full_Access (MATRIX_MCFG_4); + -- Master Configuration Register + MATRIX_MCFG_5 : aliased MATRIX_MCFG_Register; + pragma Volatile_Full_Access (MATRIX_MCFG_5); + -- Slave Configuration Register + MATRIX_SCFG_0 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_0); + -- Slave Configuration Register + MATRIX_SCFG_1 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_1); + -- Slave Configuration Register + MATRIX_SCFG_2 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_2); + -- Slave Configuration Register + MATRIX_SCFG_3 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_3); + -- Slave Configuration Register + MATRIX_SCFG_4 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_4); + -- Slave Configuration Register + MATRIX_SCFG_5 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_5); + -- Slave Configuration Register + MATRIX_SCFG_6 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_6); + -- Slave Configuration Register + MATRIX_SCFG_7 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_7); -- Slave Configuration Register - MATRIX_SCFG : MATRIX_SCFG_Registers; + MATRIX_SCFG_8 : aliased MATRIX_SCFG_Register; + pragma Volatile_Full_Access (MATRIX_SCFG_8); -- Priority Register A for Slave 0 - MATRIX_PRAS0 : MATRIX_PRAS_Register; + MATRIX_PRAS0 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS0); -- Priority Register A for Slave 1 - MATRIX_PRAS1 : MATRIX_PRAS_Register; + MATRIX_PRAS1 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS1); -- Priority Register A for Slave 2 - MATRIX_PRAS2 : MATRIX_PRAS_Register; + MATRIX_PRAS2 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS2); -- Priority Register A for Slave 3 - MATRIX_PRAS3 : MATRIX_PRAS_Register; + MATRIX_PRAS3 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS3); -- Priority Register A for Slave 4 - MATRIX_PRAS4 : MATRIX_PRAS_Register; + MATRIX_PRAS4 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS4); -- Priority Register A for Slave 5 - MATRIX_PRAS5 : MATRIX_PRAS_Register; + MATRIX_PRAS5 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS5); -- Priority Register A for Slave 6 - MATRIX_PRAS6 : MATRIX_PRAS_Register; + MATRIX_PRAS6 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS6); -- Priority Register A for Slave 7 - MATRIX_PRAS7 : MATRIX_PRAS_Register; + MATRIX_PRAS7 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS7); -- Priority Register A for Slave 8 - MATRIX_PRAS8 : MATRIX_PRAS_Register; + MATRIX_PRAS8 : aliased MATRIX_PRAS_Register; + pragma Volatile_Full_Access (MATRIX_PRAS8); -- Master Remap Control Register - MATRIX_MRCR : MATRIX_MRCR_Register; + MATRIX_MRCR : aliased MATRIX_MRCR_Register; + pragma Volatile_Full_Access (MATRIX_MRCR); -- System I/O Configuration register - CCFG_SYSIO : CCFG_SYSIO_Register; + CCFG_SYSIO : aliased CCFG_SYSIO_Register; + pragma Volatile_Full_Access (CCFG_SYSIO); -- Write Protect Mode Register - MATRIX_WPMR : MATRIX_WPMR_Register; + MATRIX_WPMR : aliased MATRIX_WPMR_Register; + pragma Volatile_Full_Access (MATRIX_WPMR); -- Write Protect Status Register - MATRIX_WPSR : MATRIX_WPSR_Register; + MATRIX_WPSR : aliased MATRIX_WPSR_Register; + pragma Volatile_Full_Access (MATRIX_WPSR); end record with Volatile; for MATRIX_Peripheral use record - MATRIX_MCFG at 0 range 0 .. 191; - MATRIX_SCFG at 64 range 0 .. 287; - MATRIX_PRAS0 at 128 range 0 .. 31; - MATRIX_PRAS1 at 136 range 0 .. 31; - MATRIX_PRAS2 at 144 range 0 .. 31; - MATRIX_PRAS3 at 152 range 0 .. 31; - MATRIX_PRAS4 at 160 range 0 .. 31; - MATRIX_PRAS5 at 168 range 0 .. 31; - MATRIX_PRAS6 at 176 range 0 .. 31; - MATRIX_PRAS7 at 184 range 0 .. 31; - MATRIX_PRAS8 at 192 range 0 .. 31; - MATRIX_MRCR at 256 range 0 .. 31; - CCFG_SYSIO at 276 range 0 .. 31; - MATRIX_WPMR at 484 range 0 .. 31; - MATRIX_WPSR at 488 range 0 .. 31; + MATRIX_MCFG_0 at 16#0# range 0 .. 31; + MATRIX_MCFG_1 at 16#4# range 0 .. 31; + MATRIX_MCFG_2 at 16#8# range 0 .. 31; + MATRIX_MCFG_3 at 16#C# range 0 .. 31; + MATRIX_MCFG_4 at 16#10# range 0 .. 31; + MATRIX_MCFG_5 at 16#14# range 0 .. 31; + MATRIX_SCFG_0 at 16#40# range 0 .. 31; + MATRIX_SCFG_1 at 16#44# range 0 .. 31; + MATRIX_SCFG_2 at 16#48# range 0 .. 31; + MATRIX_SCFG_3 at 16#4C# range 0 .. 31; + MATRIX_SCFG_4 at 16#50# range 0 .. 31; + MATRIX_SCFG_5 at 16#54# range 0 .. 31; + MATRIX_SCFG_6 at 16#58# range 0 .. 31; + MATRIX_SCFG_7 at 16#5C# range 0 .. 31; + MATRIX_SCFG_8 at 16#60# range 0 .. 31; + MATRIX_PRAS0 at 16#80# range 0 .. 31; + MATRIX_PRAS1 at 16#88# range 0 .. 31; + MATRIX_PRAS2 at 16#90# range 0 .. 31; + MATRIX_PRAS3 at 16#98# range 0 .. 31; + MATRIX_PRAS4 at 16#A0# range 0 .. 31; + MATRIX_PRAS5 at 16#A8# range 0 .. 31; + MATRIX_PRAS6 at 16#B0# range 0 .. 31; + MATRIX_PRAS7 at 16#B8# range 0 .. 31; + MATRIX_PRAS8 at 16#C0# range 0 .. 31; + MATRIX_MRCR at 16#100# range 0 .. 31; + CCFG_SYSIO at 16#114# range 0 .. 31; + MATRIX_WPMR at 16#1E4# range 0 .. 31; + MATRIX_WPSR at 16#1E8# range 0 .. 31; end record; -- AHB Bus Matrix diff --git a/arduino-due/atsam3x8e/atsam3x8e-pio.ads b/arduino-due/atsam3x8e/atsam3x8e-pio.ads index 67cdecb..49eb9b4 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-pio.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-pio.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,1351 +14,1179 @@ package ATSAM3X8E.PIO is -- Registers -- --------------- - ------------------ - -- PER_Register -- - ------------------ + -- PIOA_PER_P array element + subtype PIOA_PER_P_Element is ATSAM3X8E.Bit; - -- PER_P array element - subtype PER_P_Element is ATSAM3X8E.Bit; - - -- PER_P array - type PER_P_Field_Array is array (0 .. 31) of PER_P_Element + -- PIOA_PER_P array + type PIOA_PER_P_Field_Array is array (0 .. 31) of PIOA_PER_P_Element with Component_Size => 1, Size => 32; -- PIO Enable Register - type PER_Register + type PIOA_PER_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : PER_P_Field_Array; + Arr : PIOA_PER_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for PER_Register use record + for PIOA_PER_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- PDR_Register -- - ------------------ - - -- PDR_P array element - subtype PDR_P_Element is ATSAM3X8E.Bit; + -- PIOA_PDR_P array element + subtype PIOA_PDR_P_Element is ATSAM3X8E.Bit; - -- PDR_P array - type PDR_P_Field_Array is array (0 .. 31) of PDR_P_Element + -- PIOA_PDR_P array + type PIOA_PDR_P_Field_Array is array (0 .. 31) of PIOA_PDR_P_Element with Component_Size => 1, Size => 32; -- PIO Disable Register - type PDR_Register + type PIOA_PDR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : PDR_P_Field_Array; + Arr : PIOA_PDR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for PDR_Register use record + for PIOA_PDR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- PSR_Register -- - ------------------ - - -- PSR_P array element - subtype PSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_PSR_P array element + subtype PIOA_PSR_P_Element is ATSAM3X8E.Bit; - -- PSR_P array - type PSR_P_Field_Array is array (0 .. 31) of PSR_P_Element + -- PIOA_PSR_P array + type PIOA_PSR_P_Field_Array is array (0 .. 31) of PIOA_PSR_P_Element with Component_Size => 1, Size => 32; -- PIO Status Register - type PSR_Register + type PIOA_PSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : PSR_P_Field_Array; + Arr : PIOA_PSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for PSR_Register use record + for PIOA_PSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- OER_Register -- - ------------------ + -- PIOA_OER_P array element + subtype PIOA_OER_P_Element is ATSAM3X8E.Bit; - -- OER_P array element - subtype OER_P_Element is ATSAM3X8E.Bit; - - -- OER_P array - type OER_P_Field_Array is array (0 .. 31) of OER_P_Element + -- PIOA_OER_P array + type PIOA_OER_P_Field_Array is array (0 .. 31) of PIOA_OER_P_Element with Component_Size => 1, Size => 32; -- Output Enable Register - type OER_Register + type PIOA_OER_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : OER_P_Field_Array; + Arr : PIOA_OER_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for OER_Register use record + for PIOA_OER_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- ODR_Register -- - ------------------ - - -- ODR_P array element - subtype ODR_P_Element is ATSAM3X8E.Bit; + -- PIOA_ODR_P array element + subtype PIOA_ODR_P_Element is ATSAM3X8E.Bit; - -- ODR_P array - type ODR_P_Field_Array is array (0 .. 31) of ODR_P_Element + -- PIOA_ODR_P array + type PIOA_ODR_P_Field_Array is array (0 .. 31) of PIOA_ODR_P_Element with Component_Size => 1, Size => 32; -- Output Disable Register - type ODR_Register + type PIOA_ODR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : ODR_P_Field_Array; + Arr : PIOA_ODR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for ODR_Register use record + for PIOA_ODR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- OSR_Register -- - ------------------ - - -- OSR_P array element - subtype OSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_OSR_P array element + subtype PIOA_OSR_P_Element is ATSAM3X8E.Bit; - -- OSR_P array - type OSR_P_Field_Array is array (0 .. 31) of OSR_P_Element + -- PIOA_OSR_P array + type PIOA_OSR_P_Field_Array is array (0 .. 31) of PIOA_OSR_P_Element with Component_Size => 1, Size => 32; -- Output Status Register - type OSR_Register + type PIOA_OSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : OSR_P_Field_Array; + Arr : PIOA_OSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for OSR_Register use record + for PIOA_OSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- IFER_Register -- - ------------------- + -- PIOA_IFER_P array element + subtype PIOA_IFER_P_Element is ATSAM3X8E.Bit; - -- IFER_P array element - subtype IFER_P_Element is ATSAM3X8E.Bit; - - -- IFER_P array - type IFER_P_Field_Array is array (0 .. 31) of IFER_P_Element + -- PIOA_IFER_P array + type PIOA_IFER_P_Field_Array is array (0 .. 31) of PIOA_IFER_P_Element with Component_Size => 1, Size => 32; -- Glitch Input Filter Enable Register - type IFER_Register + type PIOA_IFER_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : IFER_P_Field_Array; + Arr : PIOA_IFER_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for IFER_Register use record + for PIOA_IFER_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- IFDR_Register -- - ------------------- - - -- IFDR_P array element - subtype IFDR_P_Element is ATSAM3X8E.Bit; + -- PIOA_IFDR_P array element + subtype PIOA_IFDR_P_Element is ATSAM3X8E.Bit; - -- IFDR_P array - type IFDR_P_Field_Array is array (0 .. 31) of IFDR_P_Element + -- PIOA_IFDR_P array + type PIOA_IFDR_P_Field_Array is array (0 .. 31) of PIOA_IFDR_P_Element with Component_Size => 1, Size => 32; -- Glitch Input Filter Disable Register - type IFDR_Register + type PIOA_IFDR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : IFDR_P_Field_Array; + Arr : PIOA_IFDR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for IFDR_Register use record + for PIOA_IFDR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- IFSR_Register -- - ------------------- - - -- IFSR_P array element - subtype IFSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_IFSR_P array element + subtype PIOA_IFSR_P_Element is ATSAM3X8E.Bit; - -- IFSR_P array - type IFSR_P_Field_Array is array (0 .. 31) of IFSR_P_Element + -- PIOA_IFSR_P array + type PIOA_IFSR_P_Field_Array is array (0 .. 31) of PIOA_IFSR_P_Element with Component_Size => 1, Size => 32; -- Glitch Input Filter Status Register - type IFSR_Register + type PIOA_IFSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : IFSR_P_Field_Array; + Arr : PIOA_IFSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for IFSR_Register use record + for PIOA_IFSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- SODR_Register -- - ------------------- + -- PIOA_SODR_P array element + subtype PIOA_SODR_P_Element is ATSAM3X8E.Bit; - -- SODR_P array element - subtype SODR_P_Element is ATSAM3X8E.Bit; - - -- SODR_P array - type SODR_P_Field_Array is array (0 .. 31) of SODR_P_Element + -- PIOA_SODR_P array + type PIOA_SODR_P_Field_Array is array (0 .. 31) of PIOA_SODR_P_Element with Component_Size => 1, Size => 32; -- Set Output Data Register - type SODR_Register + type PIOA_SODR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : SODR_P_Field_Array; + Arr : PIOA_SODR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for SODR_Register use record + for PIOA_SODR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- CODR_Register -- - ------------------- - - -- CODR_P array element - subtype CODR_P_Element is ATSAM3X8E.Bit; + -- PIOA_CODR_P array element + subtype PIOA_CODR_P_Element is ATSAM3X8E.Bit; - -- CODR_P array - type CODR_P_Field_Array is array (0 .. 31) of CODR_P_Element + -- PIOA_CODR_P array + type PIOA_CODR_P_Field_Array is array (0 .. 31) of PIOA_CODR_P_Element with Component_Size => 1, Size => 32; -- Clear Output Data Register - type CODR_Register + type PIOA_CODR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : CODR_P_Field_Array; + Arr : PIOA_CODR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for CODR_Register use record + for PIOA_CODR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- ODSR_Register -- - ------------------- - - -- ODSR_P array element - subtype ODSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_ODSR_P array element + subtype PIOA_ODSR_P_Element is ATSAM3X8E.Bit; - -- ODSR_P array - type ODSR_P_Field_Array is array (0 .. 31) of ODSR_P_Element + -- PIOA_ODSR_P array + type PIOA_ODSR_P_Field_Array is array (0 .. 31) of PIOA_ODSR_P_Element with Component_Size => 1, Size => 32; -- Output Data Status Register - type ODSR_Register + type PIOA_ODSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : ODSR_P_Field_Array; + Arr : PIOA_ODSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for ODSR_Register use record + for PIOA_ODSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- PDSR_Register -- - ------------------- + -- PIOA_PDSR_P array element + subtype PIOA_PDSR_P_Element is ATSAM3X8E.Bit; - -- PDSR_P array element - subtype PDSR_P_Element is ATSAM3X8E.Bit; - - -- PDSR_P array - type PDSR_P_Field_Array is array (0 .. 31) of PDSR_P_Element + -- PIOA_PDSR_P array + type PIOA_PDSR_P_Field_Array is array (0 .. 31) of PIOA_PDSR_P_Element with Component_Size => 1, Size => 32; -- Pin Data Status Register - type PDSR_Register + type PIOA_PDSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : PDSR_P_Field_Array; + Arr : PIOA_PDSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for PDSR_Register use record + for PIOA_PDSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - -- IER_P array element - subtype IER_P_Element is ATSAM3X8E.Bit; + -- PIOA_IER_P array element + subtype PIOA_IER_P_Element is ATSAM3X8E.Bit; - -- IER_P array - type IER_P_Field_Array is array (0 .. 31) of IER_P_Element + -- PIOA_IER_P array + type PIOA_IER_P_Field_Array is array (0 .. 31) of PIOA_IER_P_Element with Component_Size => 1, Size => 32; -- Interrupt Enable Register - type IER_Register + type PIOA_IER_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : IER_P_Field_Array; + Arr : PIOA_IER_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for PIOA_IER_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - -- IDR_P array element - subtype IDR_P_Element is ATSAM3X8E.Bit; + -- PIOA_IDR_P array element + subtype PIOA_IDR_P_Element is ATSAM3X8E.Bit; - -- IDR_P array - type IDR_P_Field_Array is array (0 .. 31) of IDR_P_Element + -- PIOA_IDR_P array + type PIOA_IDR_P_Field_Array is array (0 .. 31) of PIOA_IDR_P_Element with Component_Size => 1, Size => 32; -- Interrupt Disable Register - type IDR_Register + type PIOA_IDR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : IDR_P_Field_Array; + Arr : PIOA_IDR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for PIOA_IDR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ + -- PIOA_IMR_P array element + subtype PIOA_IMR_P_Element is ATSAM3X8E.Bit; - -- IMR_P array element - subtype IMR_P_Element is ATSAM3X8E.Bit; - - -- IMR_P array - type IMR_P_Field_Array is array (0 .. 31) of IMR_P_Element + -- PIOA_IMR_P array + type PIOA_IMR_P_Field_Array is array (0 .. 31) of PIOA_IMR_P_Element with Component_Size => 1, Size => 32; -- Interrupt Mask Register - type IMR_Register + type PIOA_IMR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : IMR_P_Field_Array; + Arr : PIOA_IMR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for PIOA_IMR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ - - -- ISR_P array element - subtype ISR_P_Element is ATSAM3X8E.Bit; + -- PIOA_ISR_P array element + subtype PIOA_ISR_P_Element is ATSAM3X8E.Bit; - -- ISR_P array - type ISR_P_Field_Array is array (0 .. 31) of ISR_P_Element + -- PIOA_ISR_P array + type PIOA_ISR_P_Field_Array is array (0 .. 31) of PIOA_ISR_P_Element with Component_Size => 1, Size => 32; -- Interrupt Status Register - type ISR_Register + type PIOA_ISR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : ISR_P_Field_Array; + Arr : PIOA_ISR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for ISR_Register use record + for PIOA_ISR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- MDER_Register -- - ------------------- - - -- MDER_P array element - subtype MDER_P_Element is ATSAM3X8E.Bit; + -- PIOA_MDER_P array element + subtype PIOA_MDER_P_Element is ATSAM3X8E.Bit; - -- MDER_P array - type MDER_P_Field_Array is array (0 .. 31) of MDER_P_Element + -- PIOA_MDER_P array + type PIOA_MDER_P_Field_Array is array (0 .. 31) of PIOA_MDER_P_Element with Component_Size => 1, Size => 32; -- Multi-driver Enable Register - type MDER_Register + type PIOA_MDER_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : MDER_P_Field_Array; + Arr : PIOA_MDER_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for MDER_Register use record + for PIOA_MDER_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- MDDR_Register -- - ------------------- + -- PIOA_MDDR_P array element + subtype PIOA_MDDR_P_Element is ATSAM3X8E.Bit; - -- MDDR_P array element - subtype MDDR_P_Element is ATSAM3X8E.Bit; - - -- MDDR_P array - type MDDR_P_Field_Array is array (0 .. 31) of MDDR_P_Element + -- PIOA_MDDR_P array + type PIOA_MDDR_P_Field_Array is array (0 .. 31) of PIOA_MDDR_P_Element with Component_Size => 1, Size => 32; -- Multi-driver Disable Register - type MDDR_Register + type PIOA_MDDR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : MDDR_P_Field_Array; + Arr : PIOA_MDDR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for MDDR_Register use record + for PIOA_MDDR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- MDSR_Register -- - ------------------- - - -- MDSR_P array element - subtype MDSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_MDSR_P array element + subtype PIOA_MDSR_P_Element is ATSAM3X8E.Bit; - -- MDSR_P array - type MDSR_P_Field_Array is array (0 .. 31) of MDSR_P_Element + -- PIOA_MDSR_P array + type PIOA_MDSR_P_Field_Array is array (0 .. 31) of PIOA_MDSR_P_Element with Component_Size => 1, Size => 32; -- Multi-driver Status Register - type MDSR_Register + type PIOA_MDSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : MDSR_P_Field_Array; + Arr : PIOA_MDSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for MDSR_Register use record + for PIOA_MDSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- PUDR_Register -- - ------------------- + -- PIOA_PUDR_P array element + subtype PIOA_PUDR_P_Element is ATSAM3X8E.Bit; - -- PUDR_P array element - subtype PUDR_P_Element is ATSAM3X8E.Bit; - - -- PUDR_P array - type PUDR_P_Field_Array is array (0 .. 31) of PUDR_P_Element + -- PIOA_PUDR_P array + type PIOA_PUDR_P_Field_Array is array (0 .. 31) of PIOA_PUDR_P_Element with Component_Size => 1, Size => 32; -- Pull-up Disable Register - type PUDR_Register + type PIOA_PUDR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : PUDR_P_Field_Array; + Arr : PIOA_PUDR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for PUDR_Register use record + for PIOA_PUDR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- PUER_Register -- - ------------------- - - -- PUER_P array element - subtype PUER_P_Element is ATSAM3X8E.Bit; + -- PIOA_PUER_P array element + subtype PIOA_PUER_P_Element is ATSAM3X8E.Bit; - -- PUER_P array - type PUER_P_Field_Array is array (0 .. 31) of PUER_P_Element + -- PIOA_PUER_P array + type PIOA_PUER_P_Field_Array is array (0 .. 31) of PIOA_PUER_P_Element with Component_Size => 1, Size => 32; -- Pull-up Enable Register - type PUER_Register + type PIOA_PUER_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : PUER_P_Field_Array; + Arr : PIOA_PUER_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for PUER_Register use record + for PIOA_PUER_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- PUSR_Register -- - ------------------- - - -- PUSR_P array element - subtype PUSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_PUSR_P array element + subtype PIOA_PUSR_P_Element is ATSAM3X8E.Bit; - -- PUSR_P array - type PUSR_P_Field_Array is array (0 .. 31) of PUSR_P_Element + -- PIOA_PUSR_P array + type PIOA_PUSR_P_Field_Array is array (0 .. 31) of PIOA_PUSR_P_Element with Component_Size => 1, Size => 32; -- Pad Pull-up Status Register - type PUSR_Register + type PIOA_PUSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : PUSR_P_Field_Array; + Arr : PIOA_PUSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for PUSR_Register use record + for PIOA_PUSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- ABSR_Register -- - ------------------- + -- PIOA_ABSR_P array element + subtype PIOA_ABSR_P_Element is ATSAM3X8E.Bit; - -- ABSR_P array element - subtype ABSR_P_Element is ATSAM3X8E.Bit; - - -- ABSR_P array - type ABSR_P_Field_Array is array (0 .. 31) of ABSR_P_Element + -- PIOA_ABSR_P array + type PIOA_ABSR_P_Field_Array is array (0 .. 31) of PIOA_ABSR_P_Element with Component_Size => 1, Size => 32; -- Peripheral AB Select Register - type ABSR_Register + type PIOA_ABSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : ABSR_P_Field_Array; + Arr : PIOA_ABSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for ABSR_Register use record + for PIOA_ABSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - --------------------- - -- SCIFSR_Register -- - --------------------- - - -- SCIFSR_P array element - subtype SCIFSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_SCIFSR_P array element + subtype PIOA_SCIFSR_P_Element is ATSAM3X8E.Bit; - -- SCIFSR_P array - type SCIFSR_P_Field_Array is array (0 .. 31) of SCIFSR_P_Element + -- PIOA_SCIFSR_P array + type PIOA_SCIFSR_P_Field_Array is array (0 .. 31) of PIOA_SCIFSR_P_Element with Component_Size => 1, Size => 32; -- System Clock Glitch Input Filter Select Register - type SCIFSR_Register + type PIOA_SCIFSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : SCIFSR_P_Field_Array; + Arr : PIOA_SCIFSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for SCIFSR_Register use record + for PIOA_SCIFSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - -------------------- - -- DIFSR_Register -- - -------------------- - - -- DIFSR_P array element - subtype DIFSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_DIFSR_P array element + subtype PIOA_DIFSR_P_Element is ATSAM3X8E.Bit; - -- DIFSR_P array - type DIFSR_P_Field_Array is array (0 .. 31) of DIFSR_P_Element + -- PIOA_DIFSR_P array + type PIOA_DIFSR_P_Field_Array is array (0 .. 31) of PIOA_DIFSR_P_Element with Component_Size => 1, Size => 32; -- Debouncing Input Filter Select Register - type DIFSR_Register + type PIOA_DIFSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : DIFSR_P_Field_Array; + Arr : PIOA_DIFSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIFSR_Register use record + for PIOA_DIFSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - --------------------- - -- IFDGSR_Register -- - --------------------- + -- PIOA_IFDGSR_P array element + subtype PIOA_IFDGSR_P_Element is ATSAM3X8E.Bit; - -- IFDGSR_P array element - subtype IFDGSR_P_Element is ATSAM3X8E.Bit; - - -- IFDGSR_P array - type IFDGSR_P_Field_Array is array (0 .. 31) of IFDGSR_P_Element + -- PIOA_IFDGSR_P array + type PIOA_IFDGSR_P_Field_Array is array (0 .. 31) of PIOA_IFDGSR_P_Element with Component_Size => 1, Size => 32; -- Glitch or Debouncing Input Filter Clock Selection Status Register - type IFDGSR_Register + type PIOA_IFDGSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : IFDGSR_P_Field_Array; + Arr : PIOA_IFDGSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for IFDGSR_Register use record + for PIOA_IFDGSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- SCDR_Register -- - ------------------- - - subtype SCDR_DIV_Field is ATSAM3X8E.UInt14; + subtype PIOA_SCDR_DIV_Field is ATSAM3X8E.UInt14; -- Slow Clock Divider Debouncing Register - type SCDR_Register is record + type PIOA_SCDR_Register is record -- Slow Clock Divider Selection for Debouncing - DIV : SCDR_DIV_Field := 16#0#; + DIV : PIOA_SCDR_DIV_Field := 16#0#; -- unspecified Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SCDR_Register use record + for PIOA_SCDR_Register use record DIV at 0 range 0 .. 13; Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------- - -- OWER_Register -- - ------------------- - - -- OWER_P array element - subtype OWER_P_Element is ATSAM3X8E.Bit; + -- PIOA_OWER_P array element + subtype PIOA_OWER_P_Element is ATSAM3X8E.Bit; - -- OWER_P array - type OWER_P_Field_Array is array (0 .. 31) of OWER_P_Element + -- PIOA_OWER_P array + type PIOA_OWER_P_Field_Array is array (0 .. 31) of PIOA_OWER_P_Element with Component_Size => 1, Size => 32; -- Output Write Enable - type OWER_Register + type PIOA_OWER_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : OWER_P_Field_Array; + Arr : PIOA_OWER_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for OWER_Register use record + for PIOA_OWER_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- OWDR_Register -- - ------------------- + -- PIOA_OWDR_P array element + subtype PIOA_OWDR_P_Element is ATSAM3X8E.Bit; - -- OWDR_P array element - subtype OWDR_P_Element is ATSAM3X8E.Bit; - - -- OWDR_P array - type OWDR_P_Field_Array is array (0 .. 31) of OWDR_P_Element + -- PIOA_OWDR_P array + type PIOA_OWDR_P_Field_Array is array (0 .. 31) of PIOA_OWDR_P_Element with Component_Size => 1, Size => 32; -- Output Write Disable - type OWDR_Register + type PIOA_OWDR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : OWDR_P_Field_Array; + Arr : PIOA_OWDR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for OWDR_Register use record + for PIOA_OWDR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- OWSR_Register -- - ------------------- - - -- OWSR_P array element - subtype OWSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_OWSR_P array element + subtype PIOA_OWSR_P_Element is ATSAM3X8E.Bit; - -- OWSR_P array - type OWSR_P_Field_Array is array (0 .. 31) of OWSR_P_Element + -- PIOA_OWSR_P array + type PIOA_OWSR_P_Field_Array is array (0 .. 31) of PIOA_OWSR_P_Element with Component_Size => 1, Size => 32; -- Output Write Status Register - type OWSR_Register + type PIOA_OWSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : OWSR_P_Field_Array; + Arr : PIOA_OWSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for OWSR_Register use record + for PIOA_OWSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - -------------------- - -- AIMER_Register -- - -------------------- - - -- AIMER_P array element - subtype AIMER_P_Element is ATSAM3X8E.Bit; + -- PIOA_AIMER_P array element + subtype PIOA_AIMER_P_Element is ATSAM3X8E.Bit; - -- AIMER_P array - type AIMER_P_Field_Array is array (0 .. 31) of AIMER_P_Element + -- PIOA_AIMER_P array + type PIOA_AIMER_P_Field_Array is array (0 .. 31) of PIOA_AIMER_P_Element with Component_Size => 1, Size => 32; -- Additional Interrupt Modes Enable Register - type AIMER_Register + type PIOA_AIMER_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : AIMER_P_Field_Array; + Arr : PIOA_AIMER_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for AIMER_Register use record + for PIOA_AIMER_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - -------------------- - -- AIMDR_Register -- - -------------------- + -- PIOA_AIMDR_P array element + subtype PIOA_AIMDR_P_Element is ATSAM3X8E.Bit; - -- AIMDR_P array element - subtype AIMDR_P_Element is ATSAM3X8E.Bit; - - -- AIMDR_P array - type AIMDR_P_Field_Array is array (0 .. 31) of AIMDR_P_Element + -- PIOA_AIMDR_P array + type PIOA_AIMDR_P_Field_Array is array (0 .. 31) of PIOA_AIMDR_P_Element with Component_Size => 1, Size => 32; -- Additional Interrupt Modes Disables Register - type AIMDR_Register + type PIOA_AIMDR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : AIMDR_P_Field_Array; + Arr : PIOA_AIMDR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for AIMDR_Register use record + for PIOA_AIMDR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - -------------------- - -- AIMMR_Register -- - -------------------- - - -- AIMMR_P array element - subtype AIMMR_P_Element is ATSAM3X8E.Bit; + -- PIOA_AIMMR_P array element + subtype PIOA_AIMMR_P_Element is ATSAM3X8E.Bit; - -- AIMMR_P array - type AIMMR_P_Field_Array is array (0 .. 31) of AIMMR_P_Element + -- PIOA_AIMMR_P array + type PIOA_AIMMR_P_Field_Array is array (0 .. 31) of PIOA_AIMMR_P_Element with Component_Size => 1, Size => 32; -- Additional Interrupt Modes Mask Register - type AIMMR_Register + type PIOA_AIMMR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : AIMMR_P_Field_Array; + Arr : PIOA_AIMMR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for AIMMR_Register use record + for PIOA_AIMMR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- ESR_Register -- - ------------------ - - -- ESR_P array element - subtype ESR_P_Element is ATSAM3X8E.Bit; + -- PIOA_ESR_P array element + subtype PIOA_ESR_P_Element is ATSAM3X8E.Bit; - -- ESR_P array - type ESR_P_Field_Array is array (0 .. 31) of ESR_P_Element + -- PIOA_ESR_P array + type PIOA_ESR_P_Field_Array is array (0 .. 31) of PIOA_ESR_P_Element with Component_Size => 1, Size => 32; -- Edge Select Register - type ESR_Register + type PIOA_ESR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : ESR_P_Field_Array; + Arr : PIOA_ESR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for ESR_Register use record + for PIOA_ESR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------ - -- LSR_Register -- - ------------------ + -- PIOA_LSR_P array element + subtype PIOA_LSR_P_Element is ATSAM3X8E.Bit; - -- LSR_P array element - subtype LSR_P_Element is ATSAM3X8E.Bit; - - -- LSR_P array - type LSR_P_Field_Array is array (0 .. 31) of LSR_P_Element + -- PIOA_LSR_P array + type PIOA_LSR_P_Field_Array is array (0 .. 31) of PIOA_LSR_P_Element with Component_Size => 1, Size => 32; -- Level Select Register - type LSR_Register + type PIOA_LSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : LSR_P_Field_Array; + Arr : PIOA_LSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for LSR_Register use record + for PIOA_LSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- ELSR_Register -- - ------------------- - - -- ELSR_P array element - subtype ELSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_ELSR_P array element + subtype PIOA_ELSR_P_Element is ATSAM3X8E.Bit; - -- ELSR_P array - type ELSR_P_Field_Array is array (0 .. 31) of ELSR_P_Element + -- PIOA_ELSR_P array + type PIOA_ELSR_P_Field_Array is array (0 .. 31) of PIOA_ELSR_P_Element with Component_Size => 1, Size => 32; -- Edge/Level Status Register - type ELSR_Register + type PIOA_ELSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : ELSR_P_Field_Array; + Arr : PIOA_ELSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for ELSR_Register use record + for PIOA_ELSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - --------------------- - -- FELLSR_Register -- - --------------------- - - -- FELLSR_P array element - subtype FELLSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_FELLSR_P array element + subtype PIOA_FELLSR_P_Element is ATSAM3X8E.Bit; - -- FELLSR_P array - type FELLSR_P_Field_Array is array (0 .. 31) of FELLSR_P_Element + -- PIOA_FELLSR_P array + type PIOA_FELLSR_P_Field_Array is array (0 .. 31) of PIOA_FELLSR_P_Element with Component_Size => 1, Size => 32; -- Falling Edge/Low Level Select Register - type FELLSR_Register + type PIOA_FELLSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : FELLSR_P_Field_Array; + Arr : PIOA_FELLSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for FELLSR_Register use record + for PIOA_FELLSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - --------------------- - -- REHLSR_Register -- - --------------------- + -- PIOA_REHLSR_P array element + subtype PIOA_REHLSR_P_Element is ATSAM3X8E.Bit; - -- REHLSR_P array element - subtype REHLSR_P_Element is ATSAM3X8E.Bit; - - -- REHLSR_P array - type REHLSR_P_Field_Array is array (0 .. 31) of REHLSR_P_Element + -- PIOA_REHLSR_P array + type PIOA_REHLSR_P_Field_Array is array (0 .. 31) of PIOA_REHLSR_P_Element with Component_Size => 1, Size => 32; -- Rising Edge/ High Level Select Register - type REHLSR_Register + type PIOA_REHLSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : REHLSR_P_Field_Array; + Arr : PIOA_REHLSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for REHLSR_Register use record + for PIOA_REHLSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - --------------------- - -- FRLHSR_Register -- - --------------------- - - -- FRLHSR_P array element - subtype FRLHSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_FRLHSR_P array element + subtype PIOA_FRLHSR_P_Element is ATSAM3X8E.Bit; - -- FRLHSR_P array - type FRLHSR_P_Field_Array is array (0 .. 31) of FRLHSR_P_Element + -- PIOA_FRLHSR_P array + type PIOA_FRLHSR_P_Field_Array is array (0 .. 31) of PIOA_FRLHSR_P_Element with Component_Size => 1, Size => 32; -- Fall/Rise - Low/High Status Register - type FRLHSR_Register + type PIOA_FRLHSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : FRLHSR_P_Field_Array; + Arr : PIOA_FRLHSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for FRLHSR_Register use record + for PIOA_FRLHSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - --------------------- - -- LOCKSR_Register -- - --------------------- - - -- LOCKSR_P array element - subtype LOCKSR_P_Element is ATSAM3X8E.Bit; + -- PIOA_LOCKSR_P array element + subtype PIOA_LOCKSR_P_Element is ATSAM3X8E.Bit; - -- LOCKSR_P array - type LOCKSR_P_Field_Array is array (0 .. 31) of LOCKSR_P_Element + -- PIOA_LOCKSR_P array + type PIOA_LOCKSR_P_Field_Array is array (0 .. 31) of PIOA_LOCKSR_P_Element with Component_Size => 1, Size => 32; -- Lock Status - type LOCKSR_Register + type PIOA_LOCKSR_Register (As_Array : Boolean := False) is record case As_Array is when False => -- P as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- P as an array - Arr : LOCKSR_P_Field_Array; + Arr : PIOA_LOCKSR_P_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for LOCKSR_Register use record + for PIOA_LOCKSR_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype PIOA_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype PIOA_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- Write Protect Mode Register - type WPMR_Register is record + type PIOA_WPMR_Register is record -- Write Protect Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : PIOA_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protect KEY - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : PIOA_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for PIOA_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype WPSR_WPVSRC_Field is ATSAM3X8E.Short; + subtype PIOA_WPSR_WPVS_Field is ATSAM3X8E.Bit; + subtype PIOA_WPSR_WPVSRC_Field is ATSAM3X8E.UInt16; -- Write Protect Status Register - type WPSR_Register is record + type PIOA_WPSR_Register is record -- Read-only. Write Protect Violation Status - WPVS : WPSR_WPVS_Field := 16#0#; + WPVS : PIOA_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protect Violation Source - WPVSRC : WPSR_WPVSRC_Field := 16#0#; + WPVSRC : PIOA_WPSR_WPVSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for PIOA_WPSR_Register use record WPVS at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPVSRC at 0 range 8 .. 23; @@ -1371,138 +1200,181 @@ package ATSAM3X8E.PIO is -- Parallel Input/Output Controller A type PIO_Peripheral is record -- PIO Enable Register - PER : PER_Register; + PER : aliased PIOA_PER_Register; + pragma Volatile_Full_Access (PER); -- PIO Disable Register - PDR : PDR_Register; + PDR : aliased PIOA_PDR_Register; + pragma Volatile_Full_Access (PDR); -- PIO Status Register - PSR : PSR_Register; + PSR : aliased PIOA_PSR_Register; + pragma Volatile_Full_Access (PSR); -- Output Enable Register - OER : OER_Register; + OER : aliased PIOA_OER_Register; + pragma Volatile_Full_Access (OER); -- Output Disable Register - ODR : ODR_Register; + ODR : aliased PIOA_ODR_Register; + pragma Volatile_Full_Access (ODR); -- Output Status Register - OSR : OSR_Register; + OSR : aliased PIOA_OSR_Register; + pragma Volatile_Full_Access (OSR); -- Glitch Input Filter Enable Register - IFER : IFER_Register; + IFER : aliased PIOA_IFER_Register; + pragma Volatile_Full_Access (IFER); -- Glitch Input Filter Disable Register - IFDR : IFDR_Register; + IFDR : aliased PIOA_IFDR_Register; + pragma Volatile_Full_Access (IFDR); -- Glitch Input Filter Status Register - IFSR : IFSR_Register; + IFSR : aliased PIOA_IFSR_Register; + pragma Volatile_Full_Access (IFSR); -- Set Output Data Register - SODR : SODR_Register; + SODR : aliased PIOA_SODR_Register; + pragma Volatile_Full_Access (SODR); -- Clear Output Data Register - CODR : CODR_Register; + CODR : aliased PIOA_CODR_Register; + pragma Volatile_Full_Access (CODR); -- Output Data Status Register - ODSR : ODSR_Register; + ODSR : aliased PIOA_ODSR_Register; + pragma Volatile_Full_Access (ODSR); -- Pin Data Status Register - PDSR : PDSR_Register; + PDSR : aliased PIOA_PDSR_Register; + pragma Volatile_Full_Access (PDSR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased PIOA_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased PIOA_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased PIOA_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Interrupt Status Register - ISR : ISR_Register; + ISR : aliased PIOA_ISR_Register; + pragma Volatile_Full_Access (ISR); -- Multi-driver Enable Register - MDER : MDER_Register; + MDER : aliased PIOA_MDER_Register; + pragma Volatile_Full_Access (MDER); -- Multi-driver Disable Register - MDDR : MDDR_Register; + MDDR : aliased PIOA_MDDR_Register; + pragma Volatile_Full_Access (MDDR); -- Multi-driver Status Register - MDSR : MDSR_Register; + MDSR : aliased PIOA_MDSR_Register; + pragma Volatile_Full_Access (MDSR); -- Pull-up Disable Register - PUDR : PUDR_Register; + PUDR : aliased PIOA_PUDR_Register; + pragma Volatile_Full_Access (PUDR); -- Pull-up Enable Register - PUER : PUER_Register; + PUER : aliased PIOA_PUER_Register; + pragma Volatile_Full_Access (PUER); -- Pad Pull-up Status Register - PUSR : PUSR_Register; + PUSR : aliased PIOA_PUSR_Register; + pragma Volatile_Full_Access (PUSR); -- Peripheral AB Select Register - ABSR : ABSR_Register; + ABSR : aliased PIOA_ABSR_Register; + pragma Volatile_Full_Access (ABSR); -- System Clock Glitch Input Filter Select Register - SCIFSR : SCIFSR_Register; + SCIFSR : aliased PIOA_SCIFSR_Register; + pragma Volatile_Full_Access (SCIFSR); -- Debouncing Input Filter Select Register - DIFSR : DIFSR_Register; + DIFSR : aliased PIOA_DIFSR_Register; + pragma Volatile_Full_Access (DIFSR); -- Glitch or Debouncing Input Filter Clock Selection Status Register - IFDGSR : IFDGSR_Register; + IFDGSR : aliased PIOA_IFDGSR_Register; + pragma Volatile_Full_Access (IFDGSR); -- Slow Clock Divider Debouncing Register - SCDR : SCDR_Register; + SCDR : aliased PIOA_SCDR_Register; + pragma Volatile_Full_Access (SCDR); -- Output Write Enable - OWER : OWER_Register; + OWER : aliased PIOA_OWER_Register; + pragma Volatile_Full_Access (OWER); -- Output Write Disable - OWDR : OWDR_Register; + OWDR : aliased PIOA_OWDR_Register; + pragma Volatile_Full_Access (OWDR); -- Output Write Status Register - OWSR : OWSR_Register; + OWSR : aliased PIOA_OWSR_Register; + pragma Volatile_Full_Access (OWSR); -- Additional Interrupt Modes Enable Register - AIMER : AIMER_Register; + AIMER : aliased PIOA_AIMER_Register; + pragma Volatile_Full_Access (AIMER); -- Additional Interrupt Modes Disables Register - AIMDR : AIMDR_Register; + AIMDR : aliased PIOA_AIMDR_Register; + pragma Volatile_Full_Access (AIMDR); -- Additional Interrupt Modes Mask Register - AIMMR : AIMMR_Register; + AIMMR : aliased PIOA_AIMMR_Register; + pragma Volatile_Full_Access (AIMMR); -- Edge Select Register - ESR : ESR_Register; + ESR : aliased PIOA_ESR_Register; + pragma Volatile_Full_Access (ESR); -- Level Select Register - LSR : LSR_Register; + LSR : aliased PIOA_LSR_Register; + pragma Volatile_Full_Access (LSR); -- Edge/Level Status Register - ELSR : ELSR_Register; + ELSR : aliased PIOA_ELSR_Register; + pragma Volatile_Full_Access (ELSR); -- Falling Edge/Low Level Select Register - FELLSR : FELLSR_Register; + FELLSR : aliased PIOA_FELLSR_Register; + pragma Volatile_Full_Access (FELLSR); -- Rising Edge/ High Level Select Register - REHLSR : REHLSR_Register; + REHLSR : aliased PIOA_REHLSR_Register; + pragma Volatile_Full_Access (REHLSR); -- Fall/Rise - Low/High Status Register - FRLHSR : FRLHSR_Register; + FRLHSR : aliased PIOA_FRLHSR_Register; + pragma Volatile_Full_Access (FRLHSR); -- Lock Status - LOCKSR : LOCKSR_Register; + LOCKSR : aliased PIOA_LOCKSR_Register; + pragma Volatile_Full_Access (LOCKSR); -- Write Protect Mode Register - WPMR : WPMR_Register; + WPMR : aliased PIOA_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- Write Protect Status Register - WPSR : WPSR_Register; + WPSR : aliased PIOA_WPSR_Register; + pragma Volatile_Full_Access (WPSR); end record with Volatile; for PIO_Peripheral use record - PER at 0 range 0 .. 31; - PDR at 4 range 0 .. 31; - PSR at 8 range 0 .. 31; - OER at 16 range 0 .. 31; - ODR at 20 range 0 .. 31; - OSR at 24 range 0 .. 31; - IFER at 32 range 0 .. 31; - IFDR at 36 range 0 .. 31; - IFSR at 40 range 0 .. 31; - SODR at 48 range 0 .. 31; - CODR at 52 range 0 .. 31; - ODSR at 56 range 0 .. 31; - PDSR at 60 range 0 .. 31; - IER at 64 range 0 .. 31; - IDR at 68 range 0 .. 31; - IMR at 72 range 0 .. 31; - ISR at 76 range 0 .. 31; - MDER at 80 range 0 .. 31; - MDDR at 84 range 0 .. 31; - MDSR at 88 range 0 .. 31; - PUDR at 96 range 0 .. 31; - PUER at 100 range 0 .. 31; - PUSR at 104 range 0 .. 31; - ABSR at 112 range 0 .. 31; - SCIFSR at 128 range 0 .. 31; - DIFSR at 132 range 0 .. 31; - IFDGSR at 136 range 0 .. 31; - SCDR at 140 range 0 .. 31; - OWER at 160 range 0 .. 31; - OWDR at 164 range 0 .. 31; - OWSR at 168 range 0 .. 31; - AIMER at 176 range 0 .. 31; - AIMDR at 180 range 0 .. 31; - AIMMR at 184 range 0 .. 31; - ESR at 192 range 0 .. 31; - LSR at 196 range 0 .. 31; - ELSR at 200 range 0 .. 31; - FELLSR at 208 range 0 .. 31; - REHLSR at 212 range 0 .. 31; - FRLHSR at 216 range 0 .. 31; - LOCKSR at 224 range 0 .. 31; - WPMR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; + PER at 16#0# range 0 .. 31; + PDR at 16#4# range 0 .. 31; + PSR at 16#8# range 0 .. 31; + OER at 16#10# range 0 .. 31; + ODR at 16#14# range 0 .. 31; + OSR at 16#18# range 0 .. 31; + IFER at 16#20# range 0 .. 31; + IFDR at 16#24# range 0 .. 31; + IFSR at 16#28# range 0 .. 31; + SODR at 16#30# range 0 .. 31; + CODR at 16#34# range 0 .. 31; + ODSR at 16#38# range 0 .. 31; + PDSR at 16#3C# range 0 .. 31; + IER at 16#40# range 0 .. 31; + IDR at 16#44# range 0 .. 31; + IMR at 16#48# range 0 .. 31; + ISR at 16#4C# range 0 .. 31; + MDER at 16#50# range 0 .. 31; + MDDR at 16#54# range 0 .. 31; + MDSR at 16#58# range 0 .. 31; + PUDR at 16#60# range 0 .. 31; + PUER at 16#64# range 0 .. 31; + PUSR at 16#68# range 0 .. 31; + ABSR at 16#70# range 0 .. 31; + SCIFSR at 16#80# range 0 .. 31; + DIFSR at 16#84# range 0 .. 31; + IFDGSR at 16#88# range 0 .. 31; + SCDR at 16#8C# range 0 .. 31; + OWER at 16#A0# range 0 .. 31; + OWDR at 16#A4# range 0 .. 31; + OWSR at 16#A8# range 0 .. 31; + AIMER at 16#B0# range 0 .. 31; + AIMDR at 16#B4# range 0 .. 31; + AIMMR at 16#B8# range 0 .. 31; + ESR at 16#C0# range 0 .. 31; + LSR at 16#C4# range 0 .. 31; + ELSR at 16#C8# range 0 .. 31; + FELLSR at 16#D0# range 0 .. 31; + REHLSR at 16#D4# range 0 .. 31; + FRLHSR at 16#D8# range 0 .. 31; + LOCKSR at 16#E0# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; end record; -- Parallel Input/Output Controller A diff --git a/arduino-due/atsam3x8e/atsam3x8e-pmc.ads b/arduino-due/atsam3x8e/atsam3x8e-pmc.ads index eba866e..c4670c8 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-pmc.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-pmc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,16 +15,7 @@ package ATSAM3X8E.PMC is -- Registers -- --------------- - ----------------------- - -- PMC_SCER_Register -- - ----------------------- - subtype PMC_SCER_UOTGCLK_Field is ATSAM3X8E.Bit; - - ------------------ - -- PMC_SCER.PCK -- - ------------------ - -- PMC_SCER_PCK array element subtype PMC_SCER_PCK_Element is ATSAM3X8E.Bit; @@ -65,7 +57,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_SCER_Register use record Reserved_0_4 at 0 range 0 .. 4; @@ -75,16 +67,7 @@ package ATSAM3X8E.PMC is Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------- - -- PMC_SCDR_Register -- - ----------------------- - subtype PMC_SCDR_UOTGCLK_Field is ATSAM3X8E.Bit; - - ------------------ - -- PMC_SCDR.PCK -- - ------------------ - -- PMC_SCDR_PCK array element subtype PMC_SCDR_PCK_Element is ATSAM3X8E.Bit; @@ -126,7 +109,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_SCDR_Register use record Reserved_0_4 at 0 range 0 .. 4; @@ -136,16 +119,7 @@ package ATSAM3X8E.PMC is Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------- - -- PMC_SCSR_Register -- - ----------------------- - subtype PMC_SCSR_UOTGCLK_Field is ATSAM3X8E.Bit; - - ------------------ - -- PMC_SCSR.PCK -- - ------------------ - -- PMC_SCSR_PCK array element subtype PMC_SCSR_PCK_Element is ATSAM3X8E.Bit; @@ -178,16 +152,15 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_0_4 : ATSAM3X8E.UInt5; -- Read-only. USB OTG Clock (48 MHz, USB_48M) Clock Status - UOTGCLK : PMC_SCSR_UOTGCLK_Field := 16#0#; + UOTGCLK : PMC_SCSR_UOTGCLK_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. Programmable Clock 0 Output Status - PCK : PMC_SCSR_PCK_Field := - (As_Array => False, Val => 16#0#); + PCK : PMC_SCSR_PCK_Field; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_SCSR_Register use record Reserved_0_4 at 0 range 0 .. 4; @@ -197,14 +170,6 @@ package ATSAM3X8E.PMC is Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------------ - -- PMC_PCER0_Register -- - ------------------------ - - ------------------- - -- PMC_PCER0.PID -- - ------------------- - -- PMC_PCER0_PID array element subtype PMC_PCER0_PID_Element is ATSAM3X8E.Bit; @@ -239,21 +204,13 @@ package ATSAM3X8E.PMC is -- Write-only. Peripheral Clock 2 Enable PID : PMC_PCER0_PID_Field := (As_Array => False, Val => 16#0#); end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_PCER0_Register use record Reserved_0_1 at 0 range 0 .. 1; PID at 0 range 2 .. 31; end record; - ------------------------ - -- PMC_PCDR0_Register -- - ------------------------ - - ------------------- - -- PMC_PCDR0.PID -- - ------------------- - -- PMC_PCDR0_PID array element subtype PMC_PCDR0_PID_Element is ATSAM3X8E.Bit; @@ -288,21 +245,13 @@ package ATSAM3X8E.PMC is -- Write-only. Peripheral Clock 2 Disable PID : PMC_PCDR0_PID_Field := (As_Array => False, Val => 16#0#); end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_PCDR0_Register use record Reserved_0_1 at 0 range 0 .. 1; PID at 0 range 2 .. 31; end record; - ------------------------ - -- PMC_PCSR0_Register -- - ------------------------ - - ------------------- - -- PMC_PCSR0.PID -- - ------------------- - -- PMC_PCSR0_PID array element subtype PMC_PCSR0_PID_Element is ATSAM3X8E.Bit; @@ -335,26 +284,22 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_0_1 : ATSAM3X8E.UInt2; -- Read-only. Peripheral Clock 2 Status - PID : PMC_PCSR0_PID_Field := (As_Array => False, Val => 16#0#); + PID : PMC_PCSR0_PID_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_PCSR0_Register use record Reserved_0_1 at 0 range 0 .. 1; PID at 0 range 2 .. 31; end record; - ------------------------ - -- CKGR_UCKR_Register -- - ------------------------ - subtype CKGR_UCKR_UPLLEN_Field is ATSAM3X8E.Bit; subtype CKGR_UCKR_UPLLCOUNT_Field is ATSAM3X8E.UInt4; -- UTMI Clock Register type CKGR_UCKR_Register is record -- unspecified - Reserved_0_15 : ATSAM3X8E.Short := 16#800#; + Reserved_0_15 : ATSAM3X8E.UInt16 := 16#800#; -- UTMI PLL Enable UPLLEN : CKGR_UCKR_UPLLEN_Field := 16#0#; -- unspecified @@ -364,7 +309,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#10#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CKGR_UCKR_Register use record Reserved_0_15 at 0 range 0 .. 15; @@ -374,28 +319,23 @@ package ATSAM3X8E.PMC is Reserved_24_31 at 0 range 24 .. 31; end record; - ----------------------- - -- CKGR_MOR_Register -- - ----------------------- - subtype CKGR_MOR_MOSCXTEN_Field is ATSAM3X8E.Bit; subtype CKGR_MOR_MOSCXTBY_Field is ATSAM3X8E.Bit; subtype CKGR_MOR_MOSCRCEN_Field is ATSAM3X8E.Bit; -- Main On-Chip RC Oscillator Frequency Selection - type MOSCRCF_Field is - ( - -- The Fast RC Oscillator Frequency is at 4 MHz (default) - MOSCRCF_Field_4_Mhz, + type CKGR_MOR_MOSCRCF_Field is + (-- The Fast RC Oscillator Frequency is at 4 MHz (default) + Val_4_Mhz, -- The Fast RC Oscillator Frequency is at 8 MHz - MOSCRCF_Field_8_Mhz, + Val_8_Mhz, -- The Fast RC Oscillator Frequency is at 12 MHz - MOSCRCF_Field_12_Mhz) + Val_12_Mhz) with Size => 3; - for MOSCRCF_Field use - (MOSCRCF_Field_4_Mhz => 0, - MOSCRCF_Field_8_Mhz => 1, - MOSCRCF_Field_12_Mhz => 2); + for CKGR_MOR_MOSCRCF_Field use + (Val_4_Mhz => 0, + Val_8_Mhz => 1, + Val_12_Mhz => 2); subtype CKGR_MOR_MOSCXTST_Field is ATSAM3X8E.Byte; subtype CKGR_MOR_KEY_Field is ATSAM3X8E.Byte; @@ -413,7 +353,7 @@ package ATSAM3X8E.PMC is -- Main On-Chip RC Oscillator Enable MOSCRCEN : CKGR_MOR_MOSCRCEN_Field := 16#0#; -- Main On-Chip RC Oscillator Frequency Selection - MOSCRCF : MOSCRCF_Field := MOSCRCF_Field_4_Mhz; + MOSCRCF : CKGR_MOR_MOSCRCF_Field := ATSAM3X8E.PMC.Val_4_Mhz; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Main Crystal Oscillator Start-up Time @@ -427,7 +367,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_26_31 : ATSAM3X8E.UInt6 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CKGR_MOR_Register use record MOSCXTEN at 0 range 0 .. 0; @@ -443,23 +383,19 @@ package ATSAM3X8E.PMC is Reserved_26_31 at 0 range 26 .. 31; end record; - ------------------------ - -- CKGR_MCFR_Register -- - ------------------------ - - subtype CKGR_MCFR_MAINF_Field is ATSAM3X8E.Short; + subtype CKGR_MCFR_MAINF_Field is ATSAM3X8E.UInt16; subtype CKGR_MCFR_MAINFRDY_Field is ATSAM3X8E.Bit; -- Main Clock Frequency Register type CKGR_MCFR_Register is record -- Read-only. Main Clock Frequency - MAINF : CKGR_MCFR_MAINF_Field := 16#0#; + MAINF : CKGR_MCFR_MAINF_Field; -- Read-only. Main Clock Ready - MAINFRDY : CKGR_MCFR_MAINFRDY_Field := 16#0#; + MAINFRDY : CKGR_MCFR_MAINFRDY_Field; -- unspecified Reserved_17_31 : ATSAM3X8E.UInt15; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CKGR_MCFR_Register use record MAINF at 0 range 0 .. 15; @@ -467,10 +403,6 @@ package ATSAM3X8E.PMC is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------------- - -- CKGR_PLLAR_Register -- - ------------------------- - subtype CKGR_PLLAR_DIVA_Field is ATSAM3X8E.Byte; subtype CKGR_PLLAR_PLLACOUNT_Field is ATSAM3X8E.UInt6; subtype CKGR_PLLAR_MULA_Field is ATSAM3X8E.UInt11; @@ -493,7 +425,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CKGR_PLLAR_Register use record DIVA at 0 range 0 .. 7; @@ -505,14 +437,9 @@ package ATSAM3X8E.PMC is Reserved_30_31 at 0 range 30 .. 31; end record; - ----------------------- - -- PMC_MCKR_Register -- - ----------------------- - -- Master Clock Source Selection - type CSS_Field is - ( - -- Slow Clock is selected + type PMC_MCKR_CSS_Field is + (-- Slow Clock is selected Slow_Clk, -- Main Clock is selected Main_Clk, @@ -521,16 +448,15 @@ package ATSAM3X8E.PMC is -- UPLL Clock is selected Upll_Clk) with Size => 2; - for CSS_Field use + for PMC_MCKR_CSS_Field use (Slow_Clk => 0, Main_Clk => 1, Plla_Clk => 2, Upll_Clk => 3); -- Processor Clock Prescaler - type PRES_Field is - ( - -- Selected clock + type PMC_MCKR_PRES_Field is + (-- Selected clock Clk_1, -- Selected clock divided by 2 Clk_2, @@ -547,7 +473,7 @@ package ATSAM3X8E.PMC is -- Selected clock divided by 3 Clk_3) with Size => 3; - for PRES_Field use + for PMC_MCKR_PRES_Field use (Clk_1 => 0, Clk_2 => 1, Clk_4 => 2, @@ -563,11 +489,11 @@ package ATSAM3X8E.PMC is -- Master Clock Register type PMC_MCKR_Register is record -- Master Clock Source Selection - CSS : CSS_Field := Main_Clk; + CSS : PMC_MCKR_CSS_Field := ATSAM3X8E.PMC.Main_Clk; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- Processor Clock Prescaler - PRES : PRES_Field := Clk_1; + PRES : PMC_MCKR_PRES_Field := ATSAM3X8E.PMC.Clk_1; -- unspecified Reserved_7_11 : ATSAM3X8E.UInt5 := 16#0#; -- PLLA Divisor by 2 @@ -576,7 +502,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_MCKR_Register use record CSS at 0 range 0 .. 1; @@ -588,10 +514,6 @@ package ATSAM3X8E.PMC is Reserved_14_31 at 0 range 14 .. 31; end record; - ---------------------- - -- PMC_USB_Register -- - ---------------------- - subtype PMC_USB_USBS_Field is ATSAM3X8E.Bit; subtype PMC_USB_USBDIV_Field is ATSAM3X8E.UInt4; @@ -606,7 +528,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_USB_Register use record USBS at 0 range 0 .. 0; @@ -615,14 +537,9 @@ package ATSAM3X8E.PMC is Reserved_12_31 at 0 range 12 .. 31; end record; - ---------------------- - -- PMC_PCK_Register -- - ---------------------- - -- Master Clock Source Selection - type CSS_Field_1 is - ( - -- Slow Clock is selected + type PMC_PCK_CSS_Field is + (-- Slow Clock is selected Slow_Clk, -- Main Clock is selected Main_Clk, @@ -633,7 +550,7 @@ package ATSAM3X8E.PMC is -- Master Clock is selected Mck) with Size => 3; - for CSS_Field_1 use + for PMC_PCK_CSS_Field use (Slow_Clk => 0, Main_Clk => 1, Plla_Clk => 2, @@ -641,9 +558,8 @@ package ATSAM3X8E.PMC is Mck => 4); -- Programmable Clock Prescaler - type PRES_Field_1 is - ( - -- Selected clock + type PMC_PCK_PRES_Field is + (-- Selected clock Clk_1, -- Selected clock divided by 2 Clk_2, @@ -658,7 +574,7 @@ package ATSAM3X8E.PMC is -- Selected clock divided by 64 Clk_64) with Size => 3; - for PRES_Field_1 use + for PMC_PCK_PRES_Field use (Clk_1 => 0, Clk_2 => 1, Clk_4 => 2, @@ -670,15 +586,15 @@ package ATSAM3X8E.PMC is -- Programmable Clock 0 Register type PMC_PCK_Register is record -- Master Clock Source Selection - CSS : CSS_Field_1 := Slow_Clk; + CSS : PMC_PCK_CSS_Field := ATSAM3X8E.PMC.Slow_Clk; -- unspecified Reserved_3_3 : ATSAM3X8E.Bit := 16#0#; -- Programmable Clock Prescaler - PRES : PRES_Field_1 := Clk_1; + PRES : PMC_PCK_PRES_Field := ATSAM3X8E.PMC.Clk_1; -- unspecified Reserved_7_31 : ATSAM3X8E.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_PCK_Register use record CSS at 0 range 0 .. 2; @@ -687,22 +603,10 @@ package ATSAM3X8E.PMC is Reserved_7_31 at 0 range 7 .. 31; end record; - -- Programmable Clock 0 Register - type PMC_PCK_Registers is array (0 .. 2) of PMC_PCK_Register; - - ---------------------- - -- PMC_IER_Register -- - ---------------------- - subtype PMC_IER_MOSCXTS_Field is ATSAM3X8E.Bit; subtype PMC_IER_LOCKA_Field is ATSAM3X8E.Bit; subtype PMC_IER_MCKRDY_Field is ATSAM3X8E.Bit; subtype PMC_IER_LOCKU_Field is ATSAM3X8E.Bit; - - -------------------- - -- PMC_IER.PCKRDY -- - -------------------- - -- PMC_IER_PCKRDY array element subtype PMC_IER_PCKRDY_Element is ATSAM3X8E.Bit; @@ -765,7 +669,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_IER_Register use record MOSCXTS at 0 range 0 .. 0; @@ -783,19 +687,10 @@ package ATSAM3X8E.PMC is Reserved_19_31 at 0 range 19 .. 31; end record; - ---------------------- - -- PMC_IDR_Register -- - ---------------------- - subtype PMC_IDR_MOSCXTS_Field is ATSAM3X8E.Bit; subtype PMC_IDR_LOCKA_Field is ATSAM3X8E.Bit; subtype PMC_IDR_MCKRDY_Field is ATSAM3X8E.Bit; subtype PMC_IDR_LOCKU_Field is ATSAM3X8E.Bit; - - -------------------- - -- PMC_IDR.PCKRDY -- - -------------------- - -- PMC_IDR_PCKRDY array element subtype PMC_IDR_PCKRDY_Element is ATSAM3X8E.Bit; @@ -858,7 +753,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_IDR_Register use record MOSCXTS at 0 range 0 .. 0; @@ -876,20 +771,11 @@ package ATSAM3X8E.PMC is Reserved_19_31 at 0 range 19 .. 31; end record; - --------------------- - -- PMC_SR_Register -- - --------------------- - subtype PMC_SR_MOSCXTS_Field is ATSAM3X8E.Bit; subtype PMC_SR_LOCKA_Field is ATSAM3X8E.Bit; subtype PMC_SR_MCKRDY_Field is ATSAM3X8E.Bit; subtype PMC_SR_LOCKU_Field is ATSAM3X8E.Bit; subtype PMC_SR_OSCSELS_Field is ATSAM3X8E.Bit; - - ------------------- - -- PMC_SR.PCKRDY -- - ------------------- - -- PMC_SR_PCKRDY array element subtype PMC_SR_PCKRDY_Element is ATSAM3X8E.Bit; @@ -926,38 +812,37 @@ package ATSAM3X8E.PMC is -- Status Register type PMC_SR_Register is record -- Read-only. Main XTAL Oscillator Status - MOSCXTS : PMC_SR_MOSCXTS_Field := 16#0#; + MOSCXTS : PMC_SR_MOSCXTS_Field; -- Read-only. PLLA Lock Status - LOCKA : PMC_SR_LOCKA_Field := 16#0#; + LOCKA : PMC_SR_LOCKA_Field; -- unspecified Reserved_2_2 : ATSAM3X8E.Bit; -- Read-only. Master Clock Status - MCKRDY : PMC_SR_MCKRDY_Field := 16#1#; + MCKRDY : PMC_SR_MCKRDY_Field; -- unspecified Reserved_4_5 : ATSAM3X8E.UInt2; -- Read-only. UTMI PLL Lock Status - LOCKU : PMC_SR_LOCKU_Field := 16#0#; + LOCKU : PMC_SR_LOCKU_Field; -- Read-only. Slow Clock Oscillator Selection - OSCSELS : PMC_SR_OSCSELS_Field := 16#0#; + OSCSELS : PMC_SR_OSCSELS_Field; -- Read-only. Programmable Clock Ready Status - PCKRDY : PMC_SR_PCKRDY_Field := - (As_Array => False, Val => 16#0#); + PCKRDY : PMC_SR_PCKRDY_Field; -- unspecified Reserved_11_15 : ATSAM3X8E.UInt5; -- Read-only. Main Oscillator Selection Status - MOSCSELS : PMC_SR_MOSCSELS_Field := 16#1#; + MOSCSELS : PMC_SR_MOSCSELS_Field; -- Read-only. Main On-Chip RC Oscillator Status - MOSCRCS : PMC_SR_MOSCRCS_Field := 16#0#; + MOSCRCS : PMC_SR_MOSCRCS_Field; -- Read-only. Clock Failure Detector Event - CFDEV : PMC_SR_CFDEV_Field := 16#0#; + CFDEV : PMC_SR_CFDEV_Field; -- Read-only. Clock Failure Detector Status - CFDS : PMC_SR_CFDS_Field := 16#0#; + CFDS : PMC_SR_CFDS_Field; -- Read-only. Clock Failure Detector Fault Output Status - FOS : PMC_SR_FOS_Field := 16#0#; + FOS : PMC_SR_FOS_Field; -- unspecified Reserved_21_31 : ATSAM3X8E.UInt11; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_SR_Register use record MOSCXTS at 0 range 0 .. 0; @@ -977,19 +862,10 @@ package ATSAM3X8E.PMC is Reserved_21_31 at 0 range 21 .. 31; end record; - ---------------------- - -- PMC_IMR_Register -- - ---------------------- - subtype PMC_IMR_MOSCXTS_Field is ATSAM3X8E.Bit; subtype PMC_IMR_LOCKA_Field is ATSAM3X8E.Bit; subtype PMC_IMR_MCKRDY_Field is ATSAM3X8E.Bit; subtype PMC_IMR_LOCKU_Field is ATSAM3X8E.Bit; - - -------------------- - -- PMC_IMR.PCKRDY -- - -------------------- - -- PMC_IMR_PCKRDY array element subtype PMC_IMR_PCKRDY_Element is ATSAM3X8E.Bit; @@ -1025,34 +901,33 @@ package ATSAM3X8E.PMC is -- Interrupt Mask Register type PMC_IMR_Register is record -- Read-only. Main Crystal Oscillator Status Interrupt Mask - MOSCXTS : PMC_IMR_MOSCXTS_Field := 16#0#; + MOSCXTS : PMC_IMR_MOSCXTS_Field; -- Read-only. PLLA Lock Interrupt Mask - LOCKA : PMC_IMR_LOCKA_Field := 16#0#; + LOCKA : PMC_IMR_LOCKA_Field; -- unspecified Reserved_2_2 : ATSAM3X8E.Bit; -- Read-only. Master Clock Ready Interrupt Mask - MCKRDY : PMC_IMR_MCKRDY_Field := 16#0#; + MCKRDY : PMC_IMR_MCKRDY_Field; -- unspecified Reserved_4_5 : ATSAM3X8E.UInt2; -- Read-only. UTMI PLL Lock Interrupt Mask - LOCKU : PMC_IMR_LOCKU_Field := 16#0#; + LOCKU : PMC_IMR_LOCKU_Field; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit; -- Read-only. Programmable Clock Ready 0 Interrupt Mask - PCKRDY : PMC_IMR_PCKRDY_Field := - (As_Array => False, Val => 16#0#); + PCKRDY : PMC_IMR_PCKRDY_Field; -- unspecified Reserved_11_15 : ATSAM3X8E.UInt5; -- Read-only. Main Oscillator Selection Status Interrupt Mask - MOSCSELS : PMC_IMR_MOSCSELS_Field := 16#0#; + MOSCSELS : PMC_IMR_MOSCSELS_Field; -- Read-only. Main On-Chip RC Status Interrupt Mask - MOSCRCS : PMC_IMR_MOSCRCS_Field := 16#0#; + MOSCRCS : PMC_IMR_MOSCRCS_Field; -- Read-only. Clock Failure Detector Event Interrupt Mask - CFDEV : PMC_IMR_CFDEV_Field := 16#0#; + CFDEV : PMC_IMR_CFDEV_Field; -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_IMR_Register use record MOSCXTS at 0 range 0 .. 0; @@ -1070,14 +945,6 @@ package ATSAM3X8E.PMC is Reserved_19_31 at 0 range 19 .. 31; end record; - ----------------------- - -- PMC_FSMR_Register -- - ----------------------- - - ------------------- - -- PMC_FSMR.FSTT -- - ------------------- - -- PMC_FSMR_FSTT array element subtype PMC_FSMR_FSTT_Element is ATSAM3X8E.Bit; @@ -1092,7 +959,7 @@ package ATSAM3X8E.PMC is case As_Array is when False => -- FSTT as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- FSTT as an array Arr : PMC_FSMR_FSTT_Field_Array; @@ -1128,7 +995,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_21_31 : ATSAM3X8E.UInt11 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_FSMR_Register use record FSTT at 0 range 0 .. 15; @@ -1140,14 +1007,6 @@ package ATSAM3X8E.PMC is Reserved_21_31 at 0 range 21 .. 31; end record; - ----------------------- - -- PMC_FSPR_Register -- - ----------------------- - - ------------------- - -- PMC_FSPR.FSTP -- - ------------------- - -- PMC_FSPR_FSTP array element subtype PMC_FSPR_FSTP_Element is ATSAM3X8E.Bit; @@ -1162,7 +1021,7 @@ package ATSAM3X8E.PMC is case As_Array is when False => -- FSTP as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- FSTP as an array Arr : PMC_FSPR_FSTP_Field_Array; @@ -1181,19 +1040,15 @@ package ATSAM3X8E.PMC is FSTP : PMC_FSPR_FSTP_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_FSPR_Register use record FSTP at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------- - -- PMC_FOCR_Register -- - ----------------------- - subtype PMC_FOCR_FOCLR_Field is ATSAM3X8E.Bit; -- Fault Output Clear Register @@ -1203,17 +1058,13 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_FOCR_Register use record FOCLR at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- PMC_WPMR_Register -- - ----------------------- - subtype PMC_WPMR_WPEN_Field is ATSAM3X8E.Bit; subtype PMC_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; @@ -1226,7 +1077,7 @@ package ATSAM3X8E.PMC is -- Write Protect KEY WPKEY : PMC_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_WPMR_Register use record WPEN at 0 range 0 .. 0; @@ -1234,25 +1085,21 @@ package ATSAM3X8E.PMC is WPKEY at 0 range 8 .. 31; end record; - ----------------------- - -- PMC_WPSR_Register -- - ----------------------- - subtype PMC_WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype PMC_WPSR_WPVSRC_Field is ATSAM3X8E.Short; + subtype PMC_WPSR_WPVSRC_Field is ATSAM3X8E.UInt16; -- Write Protect Status Register type PMC_WPSR_Register is record -- Read-only. Write Protect Violation Status - WPVS : PMC_WPSR_WPVS_Field := 16#0#; + WPVS : PMC_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protect Violation Source - WPVSRC : PMC_WPSR_WPVSRC_Field := 16#0#; + WPVSRC : PMC_WPSR_WPVSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_WPSR_Register use record WPVS at 0 range 0 .. 0; @@ -1261,19 +1108,12 @@ package ATSAM3X8E.PMC is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------------ - -- PMC_PCER1_Register -- - ------------------------ - - ------------------- - -- PMC_PCER1.PID -- - ------------------- - -- PMC_PCER1_PID array element subtype PMC_PCER1_PID_Element is ATSAM3X8E.Bit; -- PMC_PCER1_PID array - type PMC_PCER1_PID_Field_Array is array (0 .. 12) of PMC_PCER1_PID_Element + type PMC_PCER1_PID_Field_Array is array (32 .. 44) + of PMC_PCER1_PID_Element with Component_Size => 1, Size => 13; -- Type definition for PMC_PCER1_PID @@ -1304,26 +1144,19 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_PCER1_Register use record PID at 0 range 0 .. 12; Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------------ - -- PMC_PCDR1_Register -- - ------------------------ - - ------------------- - -- PMC_PCDR1.PID -- - ------------------- - -- PMC_PCDR1_PID array element subtype PMC_PCDR1_PID_Element is ATSAM3X8E.Bit; -- PMC_PCDR1_PID array - type PMC_PCDR1_PID_Field_Array is array (0 .. 12) of PMC_PCDR1_PID_Element + type PMC_PCDR1_PID_Field_Array is array (32 .. 44) + of PMC_PCDR1_PID_Element with Component_Size => 1, Size => 13; -- Type definition for PMC_PCDR1_PID @@ -1354,26 +1187,19 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_PCDR1_Register use record PID at 0 range 0 .. 12; Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------------ - -- PMC_PCSR1_Register -- - ------------------------ - - ------------------- - -- PMC_PCSR1.PID -- - ------------------- - -- PMC_PCSR1_PID array element subtype PMC_PCSR1_PID_Element is ATSAM3X8E.Bit; -- PMC_PCSR1_PID array - type PMC_PCSR1_PID_Field_Array is array (0 .. 12) of PMC_PCSR1_PID_Element + type PMC_PCSR1_PID_Field_Array is array (32 .. 44) + of PMC_PCSR1_PID_Element with Component_Size => 1, Size => 13; -- Type definition for PMC_PCSR1_PID @@ -1399,36 +1225,30 @@ package ATSAM3X8E.PMC is -- Peripheral Clock Status Register 1 type PMC_PCSR1_Register is record -- Read-only. Peripheral Clock 32 Status - PID : PMC_PCSR1_PID_Field := - (As_Array => False, Val => 16#0#); + PID : PMC_PCSR1_PID_Field; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_PCSR1_Register use record PID at 0 range 0 .. 12; Reserved_13_31 at 0 range 13 .. 31; end record; - ---------------------- - -- PMC_PCR_Register -- - ---------------------- - subtype PMC_PCR_PID_Field is ATSAM3X8E.UInt6; subtype PMC_PCR_CMD_Field is ATSAM3X8E.Bit; -- Divisor Value - type DIV_Field is - ( - -- Peripheral clock is MCK + type PMC_PCR_DIV_Field is + (-- Peripheral clock is MCK Periph_Div_Mck, -- Peripheral clock is MCK/2 Periph_Div2_Mck, -- Peripheral clock is MCK/4 Periph_Div4_Mck) with Size => 2; - for DIV_Field use + for PMC_PCR_DIV_Field use (Periph_Div_Mck => 0, Periph_Div2_Mck => 1, Periph_Div4_Mck => 2); @@ -1446,7 +1266,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_13_15 : ATSAM3X8E.UInt3 := 16#0#; -- Divisor Value - DIV : DIV_Field := Periph_Div_Mck; + DIV : PMC_PCR_DIV_Field := ATSAM3X8E.PMC.Periph_Div_Mck; -- unspecified Reserved_18_27 : ATSAM3X8E.UInt10 := 16#0#; -- Enable @@ -1454,7 +1274,7 @@ package ATSAM3X8E.PMC is -- unspecified Reserved_29_31 : ATSAM3X8E.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_PCR_Register use record PID at 0 range 0 .. 5; @@ -1474,87 +1294,121 @@ package ATSAM3X8E.PMC is -- Power Management Controller type PMC_Peripheral is record -- System Clock Enable Register - PMC_SCER : PMC_SCER_Register; + PMC_SCER : aliased PMC_SCER_Register; + pragma Volatile_Full_Access (PMC_SCER); -- System Clock Disable Register - PMC_SCDR : PMC_SCDR_Register; + PMC_SCDR : aliased PMC_SCDR_Register; + pragma Volatile_Full_Access (PMC_SCDR); -- System Clock Status Register - PMC_SCSR : PMC_SCSR_Register; + PMC_SCSR : aliased PMC_SCSR_Register; + pragma Volatile_Full_Access (PMC_SCSR); -- Peripheral Clock Enable Register 0 - PMC_PCER0 : PMC_PCER0_Register; + PMC_PCER0 : aliased PMC_PCER0_Register; + pragma Volatile_Full_Access (PMC_PCER0); -- Peripheral Clock Disable Register 0 - PMC_PCDR0 : PMC_PCDR0_Register; + PMC_PCDR0 : aliased PMC_PCDR0_Register; + pragma Volatile_Full_Access (PMC_PCDR0); -- Peripheral Clock Status Register 0 - PMC_PCSR0 : PMC_PCSR0_Register; + PMC_PCSR0 : aliased PMC_PCSR0_Register; + pragma Volatile_Full_Access (PMC_PCSR0); -- UTMI Clock Register - CKGR_UCKR : CKGR_UCKR_Register; + CKGR_UCKR : aliased CKGR_UCKR_Register; + pragma Volatile_Full_Access (CKGR_UCKR); -- Main Oscillator Register - CKGR_MOR : CKGR_MOR_Register; + CKGR_MOR : aliased CKGR_MOR_Register; + pragma Volatile_Full_Access (CKGR_MOR); -- Main Clock Frequency Register - CKGR_MCFR : CKGR_MCFR_Register; + CKGR_MCFR : aliased CKGR_MCFR_Register; + pragma Volatile_Full_Access (CKGR_MCFR); -- PLLA Register - CKGR_PLLAR : CKGR_PLLAR_Register; + CKGR_PLLAR : aliased CKGR_PLLAR_Register; + pragma Volatile_Full_Access (CKGR_PLLAR); -- Master Clock Register - PMC_MCKR : PMC_MCKR_Register; + PMC_MCKR : aliased PMC_MCKR_Register; + pragma Volatile_Full_Access (PMC_MCKR); -- USB Clock Register - PMC_USB : PMC_USB_Register; + PMC_USB : aliased PMC_USB_Register; + pragma Volatile_Full_Access (PMC_USB); + -- Programmable Clock 0 Register + PMC_PCK_0 : aliased PMC_PCK_Register; + pragma Volatile_Full_Access (PMC_PCK_0); + -- Programmable Clock 0 Register + PMC_PCK_1 : aliased PMC_PCK_Register; + pragma Volatile_Full_Access (PMC_PCK_1); -- Programmable Clock 0 Register - PMC_PCK : PMC_PCK_Registers; + PMC_PCK_2 : aliased PMC_PCK_Register; + pragma Volatile_Full_Access (PMC_PCK_2); -- Interrupt Enable Register - PMC_IER : PMC_IER_Register; + PMC_IER : aliased PMC_IER_Register; + pragma Volatile_Full_Access (PMC_IER); -- Interrupt Disable Register - PMC_IDR : PMC_IDR_Register; + PMC_IDR : aliased PMC_IDR_Register; + pragma Volatile_Full_Access (PMC_IDR); -- Status Register - PMC_SR : PMC_SR_Register; + PMC_SR : aliased PMC_SR_Register; + pragma Volatile_Full_Access (PMC_SR); -- Interrupt Mask Register - PMC_IMR : PMC_IMR_Register; + PMC_IMR : aliased PMC_IMR_Register; + pragma Volatile_Full_Access (PMC_IMR); -- Fast Startup Mode Register - PMC_FSMR : PMC_FSMR_Register; + PMC_FSMR : aliased PMC_FSMR_Register; + pragma Volatile_Full_Access (PMC_FSMR); -- Fast Startup Polarity Register - PMC_FSPR : PMC_FSPR_Register; + PMC_FSPR : aliased PMC_FSPR_Register; + pragma Volatile_Full_Access (PMC_FSPR); -- Fault Output Clear Register - PMC_FOCR : PMC_FOCR_Register; + PMC_FOCR : aliased PMC_FOCR_Register; + pragma Volatile_Full_Access (PMC_FOCR); -- Write Protect Mode Register - PMC_WPMR : PMC_WPMR_Register; + PMC_WPMR : aliased PMC_WPMR_Register; + pragma Volatile_Full_Access (PMC_WPMR); -- Write Protect Status Register - PMC_WPSR : PMC_WPSR_Register; + PMC_WPSR : aliased PMC_WPSR_Register; + pragma Volatile_Full_Access (PMC_WPSR); -- Peripheral Clock Enable Register 1 - PMC_PCER1 : PMC_PCER1_Register; + PMC_PCER1 : aliased PMC_PCER1_Register; + pragma Volatile_Full_Access (PMC_PCER1); -- Peripheral Clock Disable Register 1 - PMC_PCDR1 : PMC_PCDR1_Register; + PMC_PCDR1 : aliased PMC_PCDR1_Register; + pragma Volatile_Full_Access (PMC_PCDR1); -- Peripheral Clock Status Register 1 - PMC_PCSR1 : PMC_PCSR1_Register; + PMC_PCSR1 : aliased PMC_PCSR1_Register; + pragma Volatile_Full_Access (PMC_PCSR1); -- Peripheral Control Register - PMC_PCR : PMC_PCR_Register; + PMC_PCR : aliased PMC_PCR_Register; + pragma Volatile_Full_Access (PMC_PCR); end record with Volatile; for PMC_Peripheral use record - PMC_SCER at 0 range 0 .. 31; - PMC_SCDR at 4 range 0 .. 31; - PMC_SCSR at 8 range 0 .. 31; - PMC_PCER0 at 16 range 0 .. 31; - PMC_PCDR0 at 20 range 0 .. 31; - PMC_PCSR0 at 24 range 0 .. 31; - CKGR_UCKR at 28 range 0 .. 31; - CKGR_MOR at 32 range 0 .. 31; - CKGR_MCFR at 36 range 0 .. 31; - CKGR_PLLAR at 40 range 0 .. 31; - PMC_MCKR at 48 range 0 .. 31; - PMC_USB at 56 range 0 .. 31; - PMC_PCK at 64 range 0 .. 95; - PMC_IER at 96 range 0 .. 31; - PMC_IDR at 100 range 0 .. 31; - PMC_SR at 104 range 0 .. 31; - PMC_IMR at 108 range 0 .. 31; - PMC_FSMR at 112 range 0 .. 31; - PMC_FSPR at 116 range 0 .. 31; - PMC_FOCR at 120 range 0 .. 31; - PMC_WPMR at 228 range 0 .. 31; - PMC_WPSR at 232 range 0 .. 31; - PMC_PCER1 at 256 range 0 .. 31; - PMC_PCDR1 at 260 range 0 .. 31; - PMC_PCSR1 at 264 range 0 .. 31; - PMC_PCR at 268 range 0 .. 31; + PMC_SCER at 16#0# range 0 .. 31; + PMC_SCDR at 16#4# range 0 .. 31; + PMC_SCSR at 16#8# range 0 .. 31; + PMC_PCER0 at 16#10# range 0 .. 31; + PMC_PCDR0 at 16#14# range 0 .. 31; + PMC_PCSR0 at 16#18# range 0 .. 31; + CKGR_UCKR at 16#1C# range 0 .. 31; + CKGR_MOR at 16#20# range 0 .. 31; + CKGR_MCFR at 16#24# range 0 .. 31; + CKGR_PLLAR at 16#28# range 0 .. 31; + PMC_MCKR at 16#30# range 0 .. 31; + PMC_USB at 16#38# range 0 .. 31; + PMC_PCK_0 at 16#40# range 0 .. 31; + PMC_PCK_1 at 16#44# range 0 .. 31; + PMC_PCK_2 at 16#48# range 0 .. 31; + PMC_IER at 16#60# range 0 .. 31; + PMC_IDR at 16#64# range 0 .. 31; + PMC_SR at 16#68# range 0 .. 31; + PMC_IMR at 16#6C# range 0 .. 31; + PMC_FSMR at 16#70# range 0 .. 31; + PMC_FSPR at 16#74# range 0 .. 31; + PMC_FOCR at 16#78# range 0 .. 31; + PMC_WPMR at 16#E4# range 0 .. 31; + PMC_WPSR at 16#E8# range 0 .. 31; + PMC_PCER1 at 16#100# range 0 .. 31; + PMC_PCDR1 at 16#104# range 0 .. 31; + PMC_PCSR1 at 16#108# range 0 .. 31; + PMC_PCR at 16#10C# range 0 .. 31; end record; -- Power Management Controller diff --git a/arduino-due/atsam3x8e/atsam3x8e-pwm.ads b/arduino-due/atsam3x8e/atsam3x8e-pwm.ads index 5aaac40..6535c45 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-pwm.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-pwm.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,33 +15,29 @@ package ATSAM3X8E.PWM is -- Registers -- --------------- - ------------------ - -- CLK_Register -- - ------------------ - - subtype CLK_DIVA_Field is ATSAM3X8E.Byte; - subtype CLK_PREA_Field is ATSAM3X8E.UInt4; - subtype CLK_DIVB_Field is ATSAM3X8E.Byte; - subtype CLK_PREB_Field is ATSAM3X8E.UInt4; + subtype PWM_CLK_DIVA_Field is ATSAM3X8E.Byte; + subtype PWM_CLK_PREA_Field is ATSAM3X8E.UInt4; + subtype PWM_CLK_DIVB_Field is ATSAM3X8E.Byte; + subtype PWM_CLK_PREB_Field is ATSAM3X8E.UInt4; -- PWM Clock Register - type CLK_Register is record + type PWM_CLK_Register is record -- CLKA, CLKB Divide Factor - DIVA : CLK_DIVA_Field := 16#0#; + DIVA : PWM_CLK_DIVA_Field := 16#0#; -- CLKA, CLKB Source Clock Selection - PREA : CLK_PREA_Field := 16#0#; + PREA : PWM_CLK_PREA_Field := 16#0#; -- unspecified Reserved_12_15 : ATSAM3X8E.UInt4 := 16#0#; -- CLKA, CLKB Divide Factor - DIVB : CLK_DIVB_Field := 16#0#; + DIVB : PWM_CLK_DIVB_Field := 16#0#; -- CLKA, CLKB Source Clock Selection - PREB : CLK_PREB_Field := 16#0#; + PREB : PWM_CLK_PREB_Field := 16#0#; -- unspecified Reserved_28_31 : ATSAM3X8E.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CLK_Register use record + for PWM_CLK_Register use record DIVA at 0 range 0 .. 7; PREA at 0 range 8 .. 11; Reserved_12_15 at 0 range 12 .. 15; @@ -49,23 +46,15 @@ package ATSAM3X8E.PWM is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------ - -- ENA_Register -- - ------------------ - - -------------- - -- ENA.CHID -- - -------------- - - -- ENA_CHID array element - subtype ENA_CHID_Element is ATSAM3X8E.Bit; + -- PWM_ENA_CHID array element + subtype PWM_ENA_CHID_Element is ATSAM3X8E.Bit; - -- ENA_CHID array - type ENA_CHID_Field_Array is array (0 .. 7) of ENA_CHID_Element + -- PWM_ENA_CHID array + type PWM_ENA_CHID_Field_Array is array (0 .. 7) of PWM_ENA_CHID_Element with Component_Size => 1, Size => 8; - -- Type definition for ENA_CHID - type ENA_CHID_Field + -- Type definition for PWM_ENA_CHID + type PWM_ENA_CHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -74,47 +63,39 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CHID as an array - Arr : ENA_CHID_Field_Array; + Arr : PWM_ENA_CHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for ENA_CHID_Field use record + for PWM_ENA_CHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Enable Register - type ENA_Register is record + type PWM_ENA_Register is record -- Write-only. Channel ID - CHID : ENA_CHID_Field := (As_Array => False, Val => 16#0#); + CHID : PWM_ENA_CHID_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ENA_Register use record + for PWM_ENA_Register use record CHID at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- DIS_Register -- - ------------------ + -- PWM_DIS_CHID array element + subtype PWM_DIS_CHID_Element is ATSAM3X8E.Bit; - -------------- - -- DIS.CHID -- - -------------- - - -- DIS_CHID array element - subtype DIS_CHID_Element is ATSAM3X8E.Bit; - - -- DIS_CHID array - type DIS_CHID_Field_Array is array (0 .. 7) of DIS_CHID_Element + -- PWM_DIS_CHID array + type PWM_DIS_CHID_Field_Array is array (0 .. 7) of PWM_DIS_CHID_Element with Component_Size => 1, Size => 8; - -- Type definition for DIS_CHID - type DIS_CHID_Field + -- Type definition for PWM_DIS_CHID + type PWM_DIS_CHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -123,47 +104,39 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CHID as an array - Arr : DIS_CHID_Field_Array; + Arr : PWM_DIS_CHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for DIS_CHID_Field use record + for PWM_DIS_CHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Disable Register - type DIS_Register is record + type PWM_DIS_Register is record -- Write-only. Channel ID - CHID : DIS_CHID_Field := (As_Array => False, Val => 16#0#); + CHID : PWM_DIS_CHID_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIS_Register use record + for PWM_DIS_Register use record CHID at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - ------------- - -- SR.CHID -- - ------------- + -- PWM_SR_CHID array element + subtype PWM_SR_CHID_Element is ATSAM3X8E.Bit; - -- SR_CHID array element - subtype SR_CHID_Element is ATSAM3X8E.Bit; - - -- SR_CHID array - type SR_CHID_Field_Array is array (0 .. 7) of SR_CHID_Element + -- PWM_SR_CHID array + type PWM_SR_CHID_Field_Array is array (0 .. 7) of PWM_SR_CHID_Element with Component_Size => 1, Size => 8; - -- Type definition for SR_CHID - type SR_CHID_Field + -- Type definition for PWM_SR_CHID + type PWM_SR_CHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -172,47 +145,39 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CHID as an array - Arr : SR_CHID_Field_Array; + Arr : PWM_SR_CHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for SR_CHID_Field use record + for PWM_SR_CHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Status Register - type SR_Register is record + type PWM_SR_Register is record -- Read-only. Channel ID - CHID : SR_CHID_Field := (As_Array => False, Val => 16#0#); + CHID : PWM_SR_CHID_Field; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for PWM_SR_Register use record CHID at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- IER1_Register -- - ------------------- - - --------------- - -- IER1.CHID -- - --------------- - - -- IER1_CHID array element - subtype IER1_CHID_Element is ATSAM3X8E.Bit; + -- PWM_IER1_CHID array element + subtype PWM_IER1_CHID_Element is ATSAM3X8E.Bit; - -- IER1_CHID array - type IER1_CHID_Field_Array is array (0 .. 7) of IER1_CHID_Element + -- PWM_IER1_CHID array + type PWM_IER1_CHID_Field_Array is array (0 .. 7) of PWM_IER1_CHID_Element with Component_Size => 1, Size => 8; - -- Type definition for IER1_CHID - type IER1_CHID_Field + -- Type definition for PWM_IER1_CHID + type PWM_IER1_CHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -221,29 +186,26 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CHID as an array - Arr : IER1_CHID_Field_Array; + Arr : PWM_IER1_CHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IER1_CHID_Field use record + for PWM_IER1_CHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - ---------------- - -- IER1.FCHID -- - ---------------- - - -- IER1_FCHID array element - subtype IER1_FCHID_Element is ATSAM3X8E.Bit; + -- PWM_IER1_FCHID array element + subtype PWM_IER1_FCHID_Element is ATSAM3X8E.Bit; - -- IER1_FCHID array - type IER1_FCHID_Field_Array is array (0 .. 7) of IER1_FCHID_Element + -- PWM_IER1_FCHID array + type PWM_IER1_FCHID_Field_Array is array (0 .. 7) + of PWM_IER1_FCHID_Element with Component_Size => 1, Size => 8; - -- Type definition for IER1_FCHID - type IER1_FCHID_Field + -- Type definition for PWM_IER1_FCHID + type PWM_IER1_FCHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -252,53 +214,47 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- FCHID as an array - Arr : IER1_FCHID_Field_Array; + Arr : PWM_IER1_FCHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IER1_FCHID_Field use record + for PWM_IER1_FCHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Interrupt Enable Register 1 - type IER1_Register is record + type PWM_IER1_Register is record -- Write-only. Counter Event on Channel 0 Interrupt Enable - CHID : IER1_CHID_Field := (As_Array => False, Val => 16#0#); + CHID : PWM_IER1_CHID_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Fault Protection Trigger on Channel 0 Interrupt Enable - FCHID : IER1_FCHID_Field := (As_Array => False, Val => 16#0#); + FCHID : PWM_IER1_FCHID_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER1_Register use record + for PWM_IER1_Register use record CHID at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; FCHID at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- IDR1_Register -- - ------------------- - - --------------- - -- IDR1.CHID -- - --------------- + -- PWM_IDR1_CHID array element + subtype PWM_IDR1_CHID_Element is ATSAM3X8E.Bit; - -- IDR1_CHID array element - subtype IDR1_CHID_Element is ATSAM3X8E.Bit; - - -- IDR1_CHID array - type IDR1_CHID_Field_Array is array (0 .. 7) of IDR1_CHID_Element + -- PWM_IDR1_CHID array + type PWM_IDR1_CHID_Field_Array is array (0 .. 7) of PWM_IDR1_CHID_Element with Component_Size => 1, Size => 8; - -- Type definition for IDR1_CHID - type IDR1_CHID_Field + -- Type definition for PWM_IDR1_CHID + type PWM_IDR1_CHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -307,29 +263,26 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CHID as an array - Arr : IDR1_CHID_Field_Array; + Arr : PWM_IDR1_CHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IDR1_CHID_Field use record + for PWM_IDR1_CHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - ---------------- - -- IDR1.FCHID -- - ---------------- - - -- IDR1_FCHID array element - subtype IDR1_FCHID_Element is ATSAM3X8E.Bit; + -- PWM_IDR1_FCHID array element + subtype PWM_IDR1_FCHID_Element is ATSAM3X8E.Bit; - -- IDR1_FCHID array - type IDR1_FCHID_Field_Array is array (0 .. 7) of IDR1_FCHID_Element + -- PWM_IDR1_FCHID array + type PWM_IDR1_FCHID_Field_Array is array (0 .. 7) + of PWM_IDR1_FCHID_Element with Component_Size => 1, Size => 8; - -- Type definition for IDR1_FCHID - type IDR1_FCHID_Field + -- Type definition for PWM_IDR1_FCHID + type PWM_IDR1_FCHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -338,53 +291,47 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- FCHID as an array - Arr : IDR1_FCHID_Field_Array; + Arr : PWM_IDR1_FCHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IDR1_FCHID_Field use record + for PWM_IDR1_FCHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Interrupt Disable Register 1 - type IDR1_Register is record + type PWM_IDR1_Register is record -- Write-only. Counter Event on Channel 0 Interrupt Disable - CHID : IDR1_CHID_Field := (As_Array => False, Val => 16#0#); + CHID : PWM_IDR1_CHID_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Fault Protection Trigger on Channel 0 Interrupt Disable - FCHID : IDR1_FCHID_Field := (As_Array => False, Val => 16#0#); + FCHID : PWM_IDR1_FCHID_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR1_Register use record + for PWM_IDR1_Register use record CHID at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; FCHID at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- IMR1_Register -- - ------------------- + -- PWM_IMR1_CHID array element + subtype PWM_IMR1_CHID_Element is ATSAM3X8E.Bit; - --------------- - -- IMR1.CHID -- - --------------- - - -- IMR1_CHID array element - subtype IMR1_CHID_Element is ATSAM3X8E.Bit; - - -- IMR1_CHID array - type IMR1_CHID_Field_Array is array (0 .. 7) of IMR1_CHID_Element + -- PWM_IMR1_CHID array + type PWM_IMR1_CHID_Field_Array is array (0 .. 7) of PWM_IMR1_CHID_Element with Component_Size => 1, Size => 8; - -- Type definition for IMR1_CHID - type IMR1_CHID_Field + -- Type definition for PWM_IMR1_CHID + type PWM_IMR1_CHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -393,29 +340,26 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CHID as an array - Arr : IMR1_CHID_Field_Array; + Arr : PWM_IMR1_CHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IMR1_CHID_Field use record + for PWM_IMR1_CHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - ---------------- - -- IMR1.FCHID -- - ---------------- - - -- IMR1_FCHID array element - subtype IMR1_FCHID_Element is ATSAM3X8E.Bit; + -- PWM_IMR1_FCHID array element + subtype PWM_IMR1_FCHID_Element is ATSAM3X8E.Bit; - -- IMR1_FCHID array - type IMR1_FCHID_Field_Array is array (0 .. 7) of IMR1_FCHID_Element + -- PWM_IMR1_FCHID array + type PWM_IMR1_FCHID_Field_Array is array (0 .. 7) + of PWM_IMR1_FCHID_Element with Component_Size => 1, Size => 8; - -- Type definition for IMR1_FCHID - type IMR1_FCHID_Field + -- Type definition for PWM_IMR1_FCHID + type PWM_IMR1_FCHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -424,53 +368,45 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- FCHID as an array - Arr : IMR1_FCHID_Field_Array; + Arr : PWM_IMR1_FCHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IMR1_FCHID_Field use record + for PWM_IMR1_FCHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Interrupt Mask Register 1 - type IMR1_Register is record + type PWM_IMR1_Register is record -- Read-only. Counter Event on Channel 0 Interrupt Mask - CHID : IMR1_CHID_Field := (As_Array => False, Val => 16#0#); + CHID : PWM_IMR1_CHID_Field; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte; -- Read-only. Fault Protection Trigger on Channel 0 Interrupt Mask - FCHID : IMR1_FCHID_Field := (As_Array => False, Val => 16#0#); + FCHID : PWM_IMR1_FCHID_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR1_Register use record + for PWM_IMR1_Register use record CHID at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; FCHID at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- ISR1_Register -- - ------------------- + -- PWM_ISR1_CHID array element + subtype PWM_ISR1_CHID_Element is ATSAM3X8E.Bit; - --------------- - -- ISR1.CHID -- - --------------- - - -- ISR1_CHID array element - subtype ISR1_CHID_Element is ATSAM3X8E.Bit; - - -- ISR1_CHID array - type ISR1_CHID_Field_Array is array (0 .. 7) of ISR1_CHID_Element + -- PWM_ISR1_CHID array + type PWM_ISR1_CHID_Field_Array is array (0 .. 7) of PWM_ISR1_CHID_Element with Component_Size => 1, Size => 8; - -- Type definition for ISR1_CHID - type ISR1_CHID_Field + -- Type definition for PWM_ISR1_CHID + type PWM_ISR1_CHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -479,29 +415,26 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CHID as an array - Arr : ISR1_CHID_Field_Array; + Arr : PWM_ISR1_CHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for ISR1_CHID_Field use record + for PWM_ISR1_CHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - ---------------- - -- ISR1.FCHID -- - ---------------- - - -- ISR1_FCHID array element - subtype ISR1_FCHID_Element is ATSAM3X8E.Bit; + -- PWM_ISR1_FCHID array element + subtype PWM_ISR1_FCHID_Element is ATSAM3X8E.Bit; - -- ISR1_FCHID array - type ISR1_FCHID_Field_Array is array (0 .. 7) of ISR1_FCHID_Element + -- PWM_ISR1_FCHID array + type PWM_ISR1_FCHID_Field_Array is array (0 .. 7) + of PWM_ISR1_FCHID_Element with Component_Size => 1, Size => 8; - -- Type definition for ISR1_FCHID - type ISR1_FCHID_Field + -- Type definition for PWM_ISR1_FCHID + type PWM_ISR1_FCHID_Field (As_Array : Boolean := False) is record case As_Array is @@ -510,53 +443,45 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- FCHID as an array - Arr : ISR1_FCHID_Field_Array; + Arr : PWM_ISR1_FCHID_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for ISR1_FCHID_Field use record + for PWM_ISR1_FCHID_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Interrupt Status Register 1 - type ISR1_Register is record + type PWM_ISR1_Register is record -- Read-only. Counter Event on Channel 0 - CHID : ISR1_CHID_Field := (As_Array => False, Val => 16#0#); + CHID : PWM_ISR1_CHID_Field; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte; -- Read-only. Fault Protection Trigger on Channel 0 - FCHID : ISR1_FCHID_Field := (As_Array => False, Val => 16#0#); + FCHID : PWM_ISR1_FCHID_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ISR1_Register use record + for PWM_ISR1_Register use record CHID at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; FCHID at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- SCM_Register -- - ------------------ - - -------------- - -- SCM.SYNC -- - -------------- - - -- SCM_SYNC array element - subtype SCM_SYNC_Element is ATSAM3X8E.Bit; + -- PWM_SCM_SYNC array element + subtype PWM_SCM_SYNC_Element is ATSAM3X8E.Bit; - -- SCM_SYNC array - type SCM_SYNC_Field_Array is array (0 .. 7) of SCM_SYNC_Element + -- PWM_SCM_SYNC array + type PWM_SCM_SYNC_Field_Array is array (0 .. 7) of PWM_SCM_SYNC_Element with Component_Size => 1, Size => 8; - -- Type definition for SCM_SYNC - type SCM_SYNC_Field + -- Type definition for PWM_SCM_SYNC + type PWM_SCM_SYNC_Field (As_Array : Boolean := False) is record case As_Array is @@ -565,57 +490,57 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- SYNC as an array - Arr : SCM_SYNC_Field_Array; + Arr : PWM_SCM_SYNC_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for SCM_SYNC_Field use record + for PWM_SCM_SYNC_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- Synchronous Channels Update Mode - type UPDM_Field is - ( - -- Manual write of double buffer registers and manual update of - -- synchronous channels + type SCM_UPDM_Field is + (-- Manual write of double buffer registers and manual update of synchronous +-- channels Mode0, - -- Manual write of double buffer registers and automatic update of - -- synchronous channels + -- Manual write of double buffer registers and automatic update of synchronous +-- channels Mode1, - -- Automatic write of duty-cycle update registers by the PDC and - -- automatic update of synchronous channels + -- Automatic write of duty-cycle update registers by the PDC and automatic +-- update of synchronous channels Mode2) with Size => 2; - for UPDM_Field use + for SCM_UPDM_Field use (Mode0 => 0, Mode1 => 1, Mode2 => 2); - subtype SCM_PTRM_Field is ATSAM3X8E.Bit; - subtype SCM_PTRCS_Field is ATSAM3X8E.UInt3; + subtype PWM_SCM_PTRM_Field is ATSAM3X8E.Bit; + subtype PWM_SCM_PTRCS_Field is ATSAM3X8E.UInt3; -- PWM Sync Channels Mode Register - type SCM_Register is record + type PWM_SCM_Register is record -- Synchronous Channel 0 - SYNC : SCM_SYNC_Field := (As_Array => False, Val => 16#0#); + SYNC : PWM_SCM_SYNC_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Synchronous Channels Update Mode - UPDM : UPDM_Field := Mode0; + UPDM : SCM_UPDM_Field := ATSAM3X8E.PWM.Mode0; -- unspecified Reserved_18_19 : ATSAM3X8E.UInt2 := 16#0#; -- PDC Transfer Request Mode - PTRM : SCM_PTRM_Field := 16#0#; + PTRM : PWM_SCM_PTRM_Field := 16#0#; -- PDC Transfer Request Comparison Selection - PTRCS : SCM_PTRCS_Field := 16#0#; + PTRCS : PWM_SCM_PTRCS_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SCM_Register use record + for PWM_SCM_Register use record SYNC at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; UPDM at 0 range 16 .. 17; @@ -625,92 +550,71 @@ package ATSAM3X8E.PWM is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- SCUC_Register -- - ------------------- - - subtype SCUC_UPDULOCK_Field is ATSAM3X8E.Bit; + subtype PWM_SCUC_UPDULOCK_Field is ATSAM3X8E.Bit; -- PWM Sync Channels Update Control Register - type SCUC_Register is record + type PWM_SCUC_Register is record -- Synchronous Channels Update Unlock - UPDULOCK : SCUC_UPDULOCK_Field := 16#0#; + UPDULOCK : PWM_SCUC_UPDULOCK_Field := 16#0#; -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SCUC_Register use record + for PWM_SCUC_Register use record UPDULOCK at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------- - -- SCUP_Register -- - ------------------- - - subtype SCUP_UPR_Field is ATSAM3X8E.UInt4; - subtype SCUP_UPRCNT_Field is ATSAM3X8E.UInt4; + subtype PWM_SCUP_UPR_Field is ATSAM3X8E.UInt4; + subtype PWM_SCUP_UPRCNT_Field is ATSAM3X8E.UInt4; -- PWM Sync Channels Update Period Register - type SCUP_Register is record + type PWM_SCUP_Register is record -- Update Period - UPR : SCUP_UPR_Field := 16#0#; + UPR : PWM_SCUP_UPR_Field := 16#0#; -- Update Period Counter - UPRCNT : SCUP_UPRCNT_Field := 16#0#; + UPRCNT : PWM_SCUP_UPRCNT_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SCUP_Register use record + for PWM_SCUP_Register use record UPR at 0 range 0 .. 3; UPRCNT at 0 range 4 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ---------------------- - -- SCUPUPD_Register -- - ---------------------- - - subtype SCUPUPD_UPRUPD_Field is ATSAM3X8E.UInt4; + subtype PWM_SCUPUPD_UPRUPD_Field is ATSAM3X8E.UInt4; -- PWM Sync Channels Update Period Update Register - type SCUPUPD_Register is record + type PWM_SCUPUPD_Register is record -- Write-only. Update Period Update - UPRUPD : SCUPUPD_UPRUPD_Field := 16#0#; + UPRUPD : PWM_SCUPUPD_UPRUPD_Field := 16#0#; -- unspecified Reserved_4_31 : ATSAM3X8E.UInt28 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SCUPUPD_Register use record + for PWM_SCUPUPD_Register use record UPRUPD at 0 range 0 .. 3; Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------- - -- IER2_Register -- - ------------------- - - subtype IER2_WRDY_Field is ATSAM3X8E.Bit; - subtype IER2_ENDTX_Field is ATSAM3X8E.Bit; - subtype IER2_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IER2_UNRE_Field is ATSAM3X8E.Bit; + subtype PWM_IER2_WRDY_Field is ATSAM3X8E.Bit; + subtype PWM_IER2_ENDTX_Field is ATSAM3X8E.Bit; + subtype PWM_IER2_TXBUFE_Field is ATSAM3X8E.Bit; + subtype PWM_IER2_UNRE_Field is ATSAM3X8E.Bit; + -- PWM_IER2_CMPM array element + subtype PWM_IER2_CMPM_Element is ATSAM3X8E.Bit; - --------------- - -- IER2.CMPM -- - --------------- - - -- IER2_CMPM array element - subtype IER2_CMPM_Element is ATSAM3X8E.Bit; - - -- IER2_CMPM array - type IER2_CMPM_Field_Array is array (0 .. 7) of IER2_CMPM_Element + -- PWM_IER2_CMPM array + type PWM_IER2_CMPM_Field_Array is array (0 .. 7) of PWM_IER2_CMPM_Element with Component_Size => 1, Size => 8; - -- Type definition for IER2_CMPM - type IER2_CMPM_Field + -- Type definition for PWM_IER2_CMPM + type PWM_IER2_CMPM_Field (As_Array : Boolean := False) is record case As_Array is @@ -719,29 +623,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CMPM as an array - Arr : IER2_CMPM_Field_Array; + Arr : PWM_IER2_CMPM_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IER2_CMPM_Field use record + for PWM_IER2_CMPM_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - --------------- - -- IER2.CMPU -- - --------------- + -- PWM_IER2_CMPU array element + subtype PWM_IER2_CMPU_Element is ATSAM3X8E.Bit; - -- IER2_CMPU array element - subtype IER2_CMPU_Element is ATSAM3X8E.Bit; - - -- IER2_CMPU array - type IER2_CMPU_Field_Array is array (0 .. 7) of IER2_CMPU_Element + -- PWM_IER2_CMPU array + type PWM_IER2_CMPU_Field_Array is array (0 .. 7) of PWM_IER2_CMPU_Element with Component_Size => 1, Size => 8; - -- Type definition for IER2_CMPU - type IER2_CMPU_Field + -- Type definition for PWM_IER2_CMPU + type PWM_IER2_CMPU_Field (As_Array : Boolean := False) is record case As_Array is @@ -750,40 +650,42 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CMPU as an array - Arr : IER2_CMPU_Field_Array; + Arr : PWM_IER2_CMPU_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IER2_CMPU_Field use record + for PWM_IER2_CMPU_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Interrupt Enable Register 2 - type IER2_Register is record + type PWM_IER2_Register is record -- Write-only. Write Ready for Synchronous Channels Update Interrupt -- Enable - WRDY : IER2_WRDY_Field := 16#0#; + WRDY : PWM_IER2_WRDY_Field := 16#0#; -- Write-only. PDC End of TX Buffer Interrupt Enable - ENDTX : IER2_ENDTX_Field := 16#0#; + ENDTX : PWM_IER2_ENDTX_Field := 16#0#; -- Write-only. PDC TX Buffer Empty Interrupt Enable - TXBUFE : IER2_TXBUFE_Field := 16#0#; + TXBUFE : PWM_IER2_TXBUFE_Field := 16#0#; -- Write-only. Synchronous Channels Update Underrun Error Interrupt -- Enable - UNRE : IER2_UNRE_Field := 16#0#; + UNRE : PWM_IER2_UNRE_Field := 16#0#; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Comparison 0 Match Interrupt Enable - CMPM : IER2_CMPM_Field := (As_Array => False, Val => 16#0#); + CMPM : PWM_IER2_CMPM_Field := + (As_Array => False, Val => 16#0#); -- Write-only. Comparison 0 Update Interrupt Enable - CMPU : IER2_CMPU_Field := (As_Array => False, Val => 16#0#); + CMPU : PWM_IER2_CMPU_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER2_Register use record + for PWM_IER2_Register use record WRDY at 0 range 0 .. 0; ENDTX at 0 range 1 .. 1; TXBUFE at 0 range 2 .. 2; @@ -794,28 +696,19 @@ package ATSAM3X8E.PWM is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- IDR2_Register -- - ------------------- + subtype PWM_IDR2_WRDY_Field is ATSAM3X8E.Bit; + subtype PWM_IDR2_ENDTX_Field is ATSAM3X8E.Bit; + subtype PWM_IDR2_TXBUFE_Field is ATSAM3X8E.Bit; + subtype PWM_IDR2_UNRE_Field is ATSAM3X8E.Bit; + -- PWM_IDR2_CMPM array element + subtype PWM_IDR2_CMPM_Element is ATSAM3X8E.Bit; - subtype IDR2_WRDY_Field is ATSAM3X8E.Bit; - subtype IDR2_ENDTX_Field is ATSAM3X8E.Bit; - subtype IDR2_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IDR2_UNRE_Field is ATSAM3X8E.Bit; - - --------------- - -- IDR2.CMPM -- - --------------- - - -- IDR2_CMPM array element - subtype IDR2_CMPM_Element is ATSAM3X8E.Bit; - - -- IDR2_CMPM array - type IDR2_CMPM_Field_Array is array (0 .. 7) of IDR2_CMPM_Element + -- PWM_IDR2_CMPM array + type PWM_IDR2_CMPM_Field_Array is array (0 .. 7) of PWM_IDR2_CMPM_Element with Component_Size => 1, Size => 8; - -- Type definition for IDR2_CMPM - type IDR2_CMPM_Field + -- Type definition for PWM_IDR2_CMPM + type PWM_IDR2_CMPM_Field (As_Array : Boolean := False) is record case As_Array is @@ -824,29 +717,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CMPM as an array - Arr : IDR2_CMPM_Field_Array; + Arr : PWM_IDR2_CMPM_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IDR2_CMPM_Field use record + for PWM_IDR2_CMPM_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - --------------- - -- IDR2.CMPU -- - --------------- - - -- IDR2_CMPU array element - subtype IDR2_CMPU_Element is ATSAM3X8E.Bit; + -- PWM_IDR2_CMPU array element + subtype PWM_IDR2_CMPU_Element is ATSAM3X8E.Bit; - -- IDR2_CMPU array - type IDR2_CMPU_Field_Array is array (0 .. 7) of IDR2_CMPU_Element + -- PWM_IDR2_CMPU array + type PWM_IDR2_CMPU_Field_Array is array (0 .. 7) of PWM_IDR2_CMPU_Element with Component_Size => 1, Size => 8; - -- Type definition for IDR2_CMPU - type IDR2_CMPU_Field + -- Type definition for PWM_IDR2_CMPU + type PWM_IDR2_CMPU_Field (As_Array : Boolean := False) is record case As_Array is @@ -855,40 +744,42 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CMPU as an array - Arr : IDR2_CMPU_Field_Array; + Arr : PWM_IDR2_CMPU_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IDR2_CMPU_Field use record + for PWM_IDR2_CMPU_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Interrupt Disable Register 2 - type IDR2_Register is record + type PWM_IDR2_Register is record -- Write-only. Write Ready for Synchronous Channels Update Interrupt -- Disable - WRDY : IDR2_WRDY_Field := 16#0#; + WRDY : PWM_IDR2_WRDY_Field := 16#0#; -- Write-only. PDC End of TX Buffer Interrupt Disable - ENDTX : IDR2_ENDTX_Field := 16#0#; + ENDTX : PWM_IDR2_ENDTX_Field := 16#0#; -- Write-only. PDC TX Buffer Empty Interrupt Disable - TXBUFE : IDR2_TXBUFE_Field := 16#0#; + TXBUFE : PWM_IDR2_TXBUFE_Field := 16#0#; -- Write-only. Synchronous Channels Update Underrun Error Interrupt -- Disable - UNRE : IDR2_UNRE_Field := 16#0#; + UNRE : PWM_IDR2_UNRE_Field := 16#0#; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Comparison 0 Match Interrupt Disable - CMPM : IDR2_CMPM_Field := (As_Array => False, Val => 16#0#); + CMPM : PWM_IDR2_CMPM_Field := + (As_Array => False, Val => 16#0#); -- Write-only. Comparison 0 Update Interrupt Disable - CMPU : IDR2_CMPU_Field := (As_Array => False, Val => 16#0#); + CMPU : PWM_IDR2_CMPU_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR2_Register use record + for PWM_IDR2_Register use record WRDY at 0 range 0 .. 0; ENDTX at 0 range 1 .. 1; TXBUFE at 0 range 2 .. 2; @@ -899,28 +790,19 @@ package ATSAM3X8E.PWM is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- IMR2_Register -- - ------------------- - - subtype IMR2_WRDY_Field is ATSAM3X8E.Bit; - subtype IMR2_ENDTX_Field is ATSAM3X8E.Bit; - subtype IMR2_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IMR2_UNRE_Field is ATSAM3X8E.Bit; - - --------------- - -- IMR2.CMPM -- - --------------- - - -- IMR2_CMPM array element - subtype IMR2_CMPM_Element is ATSAM3X8E.Bit; + subtype PWM_IMR2_WRDY_Field is ATSAM3X8E.Bit; + subtype PWM_IMR2_ENDTX_Field is ATSAM3X8E.Bit; + subtype PWM_IMR2_TXBUFE_Field is ATSAM3X8E.Bit; + subtype PWM_IMR2_UNRE_Field is ATSAM3X8E.Bit; + -- PWM_IMR2_CMPM array element + subtype PWM_IMR2_CMPM_Element is ATSAM3X8E.Bit; - -- IMR2_CMPM array - type IMR2_CMPM_Field_Array is array (0 .. 7) of IMR2_CMPM_Element + -- PWM_IMR2_CMPM array + type PWM_IMR2_CMPM_Field_Array is array (0 .. 7) of PWM_IMR2_CMPM_Element with Component_Size => 1, Size => 8; - -- Type definition for IMR2_CMPM - type IMR2_CMPM_Field + -- Type definition for PWM_IMR2_CMPM + type PWM_IMR2_CMPM_Field (As_Array : Boolean := False) is record case As_Array is @@ -929,29 +811,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CMPM as an array - Arr : IMR2_CMPM_Field_Array; + Arr : PWM_IMR2_CMPM_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IMR2_CMPM_Field use record + for PWM_IMR2_CMPM_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - --------------- - -- IMR2.CMPU -- - --------------- - - -- IMR2_CMPU array element - subtype IMR2_CMPU_Element is ATSAM3X8E.Bit; + -- PWM_IMR2_CMPU array element + subtype PWM_IMR2_CMPU_Element is ATSAM3X8E.Bit; - -- IMR2_CMPU array - type IMR2_CMPU_Field_Array is array (0 .. 7) of IMR2_CMPU_Element + -- PWM_IMR2_CMPU array + type PWM_IMR2_CMPU_Field_Array is array (0 .. 7) of PWM_IMR2_CMPU_Element with Component_Size => 1, Size => 8; - -- Type definition for IMR2_CMPU - type IMR2_CMPU_Field + -- Type definition for PWM_IMR2_CMPU + type PWM_IMR2_CMPU_Field (As_Array : Boolean := False) is record case As_Array is @@ -960,38 +838,38 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CMPU as an array - Arr : IMR2_CMPU_Field_Array; + Arr : PWM_IMR2_CMPU_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for IMR2_CMPU_Field use record + for PWM_IMR2_CMPU_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Interrupt Mask Register 2 - type IMR2_Register is record + type PWM_IMR2_Register is record -- Read-only. Write Ready for Synchronous Channels Update Interrupt Mask - WRDY : IMR2_WRDY_Field := 16#0#; + WRDY : PWM_IMR2_WRDY_Field; -- Read-only. PDC End of TX Buffer Interrupt Mask - ENDTX : IMR2_ENDTX_Field := 16#0#; + ENDTX : PWM_IMR2_ENDTX_Field; -- Read-only. PDC TX Buffer Empty Interrupt Mask - TXBUFE : IMR2_TXBUFE_Field := 16#0#; + TXBUFE : PWM_IMR2_TXBUFE_Field; -- Read-only. Synchronous Channels Update Underrun Error Interrupt Mask - UNRE : IMR2_UNRE_Field := 16#0#; + UNRE : PWM_IMR2_UNRE_Field; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4; -- Read-only. Comparison 0 Match Interrupt Mask - CMPM : IMR2_CMPM_Field := (As_Array => False, Val => 16#0#); + CMPM : PWM_IMR2_CMPM_Field; -- Read-only. Comparison 0 Update Interrupt Mask - CMPU : IMR2_CMPU_Field := (As_Array => False, Val => 16#0#); + CMPU : PWM_IMR2_CMPU_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR2_Register use record + for PWM_IMR2_Register use record WRDY at 0 range 0 .. 0; ENDTX at 0 range 1 .. 1; TXBUFE at 0 range 2 .. 2; @@ -1002,28 +880,19 @@ package ATSAM3X8E.PWM is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- ISR2_Register -- - ------------------- - - subtype ISR2_WRDY_Field is ATSAM3X8E.Bit; - subtype ISR2_ENDTX_Field is ATSAM3X8E.Bit; - subtype ISR2_TXBUFE_Field is ATSAM3X8E.Bit; - subtype ISR2_UNRE_Field is ATSAM3X8E.Bit; - - --------------- - -- ISR2.CMPM -- - --------------- - - -- ISR2_CMPM array element - subtype ISR2_CMPM_Element is ATSAM3X8E.Bit; + subtype PWM_ISR2_WRDY_Field is ATSAM3X8E.Bit; + subtype PWM_ISR2_ENDTX_Field is ATSAM3X8E.Bit; + subtype PWM_ISR2_TXBUFE_Field is ATSAM3X8E.Bit; + subtype PWM_ISR2_UNRE_Field is ATSAM3X8E.Bit; + -- PWM_ISR2_CMPM array element + subtype PWM_ISR2_CMPM_Element is ATSAM3X8E.Bit; - -- ISR2_CMPM array - type ISR2_CMPM_Field_Array is array (0 .. 7) of ISR2_CMPM_Element + -- PWM_ISR2_CMPM array + type PWM_ISR2_CMPM_Field_Array is array (0 .. 7) of PWM_ISR2_CMPM_Element with Component_Size => 1, Size => 8; - -- Type definition for ISR2_CMPM - type ISR2_CMPM_Field + -- Type definition for PWM_ISR2_CMPM + type PWM_ISR2_CMPM_Field (As_Array : Boolean := False) is record case As_Array is @@ -1032,29 +901,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CMPM as an array - Arr : ISR2_CMPM_Field_Array; + Arr : PWM_ISR2_CMPM_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for ISR2_CMPM_Field use record + for PWM_ISR2_CMPM_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - --------------- - -- ISR2.CMPU -- - --------------- - - -- ISR2_CMPU array element - subtype ISR2_CMPU_Element is ATSAM3X8E.Bit; + -- PWM_ISR2_CMPU array element + subtype PWM_ISR2_CMPU_Element is ATSAM3X8E.Bit; - -- ISR2_CMPU array - type ISR2_CMPU_Field_Array is array (0 .. 7) of ISR2_CMPU_Element + -- PWM_ISR2_CMPU array + type PWM_ISR2_CMPU_Field_Array is array (0 .. 7) of PWM_ISR2_CMPU_Element with Component_Size => 1, Size => 8; - -- Type definition for ISR2_CMPU - type ISR2_CMPU_Field + -- Type definition for PWM_ISR2_CMPU + type PWM_ISR2_CMPU_Field (As_Array : Boolean := False) is record case As_Array is @@ -1063,38 +928,38 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CMPU as an array - Arr : ISR2_CMPU_Field_Array; + Arr : PWM_ISR2_CMPU_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for ISR2_CMPU_Field use record + for PWM_ISR2_CMPU_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Interrupt Status Register 2 - type ISR2_Register is record + type PWM_ISR2_Register is record -- Read-only. Write Ready for Synchronous Channels Update - WRDY : ISR2_WRDY_Field := 16#0#; + WRDY : PWM_ISR2_WRDY_Field; -- Read-only. PDC End of TX Buffer - ENDTX : ISR2_ENDTX_Field := 16#0#; + ENDTX : PWM_ISR2_ENDTX_Field; -- Read-only. PDC TX Buffer Empty - TXBUFE : ISR2_TXBUFE_Field := 16#0#; + TXBUFE : PWM_ISR2_TXBUFE_Field; -- Read-only. Synchronous Channels Update Underrun Error - UNRE : ISR2_UNRE_Field := 16#0#; + UNRE : PWM_ISR2_UNRE_Field; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4; -- Read-only. Comparison 0 Match - CMPM : ISR2_CMPM_Field := (As_Array => False, Val => 16#0#); + CMPM : PWM_ISR2_CMPM_Field; -- Read-only. Comparison 0 Update - CMPU : ISR2_CMPU_Field := (As_Array => False, Val => 16#0#); + CMPU : PWM_ISR2_CMPU_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ISR2_Register use record + for PWM_ISR2_Register use record WRDY at 0 range 0 .. 0; ENDTX at 0 range 1 .. 1; TXBUFE at 0 range 2 .. 2; @@ -1105,23 +970,15 @@ package ATSAM3X8E.PWM is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- OOV_Register -- - ------------------ - - -------------- - -- OOV.OOVH -- - -------------- - - -- OOV_OOVH array element - subtype OOV_OOVH_Element is ATSAM3X8E.Bit; + -- PWM_OOV_OOVH array element + subtype PWM_OOV_OOVH_Element is ATSAM3X8E.Bit; - -- OOV_OOVH array - type OOV_OOVH_Field_Array is array (0 .. 7) of OOV_OOVH_Element + -- PWM_OOV_OOVH array + type PWM_OOV_OOVH_Field_Array is array (0 .. 7) of PWM_OOV_OOVH_Element with Component_Size => 1, Size => 8; - -- Type definition for OOV_OOVH - type OOV_OOVH_Field + -- Type definition for PWM_OOV_OOVH + type PWM_OOV_OOVH_Field (As_Array : Boolean := False) is record case As_Array is @@ -1130,29 +987,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OOVH as an array - Arr : OOV_OOVH_Field_Array; + Arr : PWM_OOV_OOVH_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OOV_OOVH_Field use record + for PWM_OOV_OOVH_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - -------------- - -- OOV.OOVL -- - -------------- + -- PWM_OOV_OOVL array element + subtype PWM_OOV_OOVL_Element is ATSAM3X8E.Bit; - -- OOV_OOVL array element - subtype OOV_OOVL_Element is ATSAM3X8E.Bit; - - -- OOV_OOVL array - type OOV_OOVL_Field_Array is array (0 .. 7) of OOV_OOVL_Element + -- PWM_OOV_OOVL array + type PWM_OOV_OOVL_Field_Array is array (0 .. 7) of PWM_OOV_OOVL_Element with Component_Size => 1, Size => 8; - -- Type definition for OOV_OOVL - type OOV_OOVL_Field + -- Type definition for PWM_OOV_OOVL + type PWM_OOV_OOVL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1161,53 +1014,47 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OOVL as an array - Arr : OOV_OOVL_Field_Array; + Arr : PWM_OOV_OOVL_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OOV_OOVL_Field use record + for PWM_OOV_OOVL_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Output Override Value Register - type OOV_Register is record + type PWM_OOV_Register is record -- Output Override Value for PWMH output of the channel 0 - OOVH : OOV_OOVH_Field := (As_Array => False, Val => 16#0#); + OOVH : PWM_OOV_OOVH_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Output Override Value for PWML output of the channel 0 - OOVL : OOV_OOVL_Field := (As_Array => False, Val => 16#0#); + OOVL : PWM_OOV_OOVL_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OOV_Register use record + for PWM_OOV_Register use record OOVH at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; OOVL at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ----------------- - -- OS_Register -- - ----------------- - - ------------ - -- OS.OSH -- - ------------ - - -- OS_OSH array element - subtype OS_OSH_Element is ATSAM3X8E.Bit; + -- PWM_OS_OSH array element + subtype PWM_OS_OSH_Element is ATSAM3X8E.Bit; - -- OS_OSH array - type OS_OSH_Field_Array is array (0 .. 7) of OS_OSH_Element + -- PWM_OS_OSH array + type PWM_OS_OSH_Field_Array is array (0 .. 7) of PWM_OS_OSH_Element with Component_Size => 1, Size => 8; - -- Type definition for OS_OSH - type OS_OSH_Field + -- Type definition for PWM_OS_OSH + type PWM_OS_OSH_Field (As_Array : Boolean := False) is record case As_Array is @@ -1216,29 +1063,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSH as an array - Arr : OS_OSH_Field_Array; + Arr : PWM_OS_OSH_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OS_OSH_Field use record + for PWM_OS_OSH_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - ------------ - -- OS.OSL -- - ------------ - - -- OS_OSL array element - subtype OS_OSL_Element is ATSAM3X8E.Bit; + -- PWM_OS_OSL array element + subtype PWM_OS_OSL_Element is ATSAM3X8E.Bit; - -- OS_OSL array - type OS_OSL_Field_Array is array (0 .. 7) of OS_OSL_Element + -- PWM_OS_OSL array + type PWM_OS_OSL_Field_Array is array (0 .. 7) of PWM_OS_OSL_Element with Component_Size => 1, Size => 8; - -- Type definition for OS_OSL - type OS_OSL_Field + -- Type definition for PWM_OS_OSL + type PWM_OS_OSL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1247,53 +1090,45 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSL as an array - Arr : OS_OSL_Field_Array; + Arr : PWM_OS_OSL_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OS_OSL_Field use record + for PWM_OS_OSL_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Output Selection Register - type OS_Register is record + type PWM_OS_Register is record -- Output Selection for PWMH output of the channel 0 - OSH : OS_OSH_Field := (As_Array => False, Val => 16#0#); + OSH : PWM_OS_OSH_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Output Selection for PWML output of the channel 0 - OSL : OS_OSL_Field := (As_Array => False, Val => 16#0#); + OSL : PWM_OS_OSL_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OS_Register use record + for PWM_OS_Register use record OSH at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; OSL at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- OSS_Register -- - ------------------ + -- PWM_OSS_OSSH array element + subtype PWM_OSS_OSSH_Element is ATSAM3X8E.Bit; - -------------- - -- OSS.OSSH -- - -------------- - - -- OSS_OSSH array element - subtype OSS_OSSH_Element is ATSAM3X8E.Bit; - - -- OSS_OSSH array - type OSS_OSSH_Field_Array is array (0 .. 7) of OSS_OSSH_Element + -- PWM_OSS_OSSH array + type PWM_OSS_OSSH_Field_Array is array (0 .. 7) of PWM_OSS_OSSH_Element with Component_Size => 1, Size => 8; - -- Type definition for OSS_OSSH - type OSS_OSSH_Field + -- Type definition for PWM_OSS_OSSH + type PWM_OSS_OSSH_Field (As_Array : Boolean := False) is record case As_Array is @@ -1302,29 +1137,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSSH as an array - Arr : OSS_OSSH_Field_Array; + Arr : PWM_OSS_OSSH_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OSS_OSSH_Field use record + for PWM_OSS_OSSH_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - -------------- - -- OSS.OSSL -- - -------------- - - -- OSS_OSSL array element - subtype OSS_OSSL_Element is ATSAM3X8E.Bit; + -- PWM_OSS_OSSL array element + subtype PWM_OSS_OSSL_Element is ATSAM3X8E.Bit; - -- OSS_OSSL array - type OSS_OSSL_Field_Array is array (0 .. 7) of OSS_OSSL_Element + -- PWM_OSS_OSSL array + type PWM_OSS_OSSL_Field_Array is array (0 .. 7) of PWM_OSS_OSSL_Element with Component_Size => 1, Size => 8; - -- Type definition for OSS_OSSL - type OSS_OSSL_Field + -- Type definition for PWM_OSS_OSSL + type PWM_OSS_OSSL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1333,53 +1164,47 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSSL as an array - Arr : OSS_OSSL_Field_Array; + Arr : PWM_OSS_OSSL_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OSS_OSSL_Field use record + for PWM_OSS_OSSL_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Output Selection Set Register - type OSS_Register is record + type PWM_OSS_Register is record -- Write-only. Output Selection Set for PWMH output of the channel 0 - OSSH : OSS_OSSH_Field := (As_Array => False, Val => 16#0#); + OSSH : PWM_OSS_OSSH_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Output Selection Set for PWML output of the channel 0 - OSSL : OSS_OSSL_Field := (As_Array => False, Val => 16#0#); + OSSL : PWM_OSS_OSSL_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OSS_Register use record + for PWM_OSS_Register use record OSSH at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; OSSL at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- OSC_Register -- - ------------------ - - -------------- - -- OSC.OSCH -- - -------------- + -- PWM_OSC_OSCH array element + subtype PWM_OSC_OSCH_Element is ATSAM3X8E.Bit; - -- OSC_OSCH array element - subtype OSC_OSCH_Element is ATSAM3X8E.Bit; - - -- OSC_OSCH array - type OSC_OSCH_Field_Array is array (0 .. 7) of OSC_OSCH_Element + -- PWM_OSC_OSCH array + type PWM_OSC_OSCH_Field_Array is array (0 .. 7) of PWM_OSC_OSCH_Element with Component_Size => 1, Size => 8; - -- Type definition for OSC_OSCH - type OSC_OSCH_Field + -- Type definition for PWM_OSC_OSCH + type PWM_OSC_OSCH_Field (As_Array : Boolean := False) is record case As_Array is @@ -1388,29 +1213,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSCH as an array - Arr : OSC_OSCH_Field_Array; + Arr : PWM_OSC_OSCH_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OSC_OSCH_Field use record + for PWM_OSC_OSCH_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - -------------- - -- OSC.OSCL -- - -------------- - - -- OSC_OSCL array element - subtype OSC_OSCL_Element is ATSAM3X8E.Bit; + -- PWM_OSC_OSCL array element + subtype PWM_OSC_OSCL_Element is ATSAM3X8E.Bit; - -- OSC_OSCL array - type OSC_OSCL_Field_Array is array (0 .. 7) of OSC_OSCL_Element + -- PWM_OSC_OSCL array + type PWM_OSC_OSCL_Field_Array is array (0 .. 7) of PWM_OSC_OSCL_Element with Component_Size => 1, Size => 8; - -- Type definition for OSC_OSCL - type OSC_OSCL_Field + -- Type definition for PWM_OSC_OSCL + type PWM_OSC_OSCL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1419,53 +1240,48 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSCL as an array - Arr : OSC_OSCL_Field_Array; + Arr : PWM_OSC_OSCL_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OSC_OSCL_Field use record + for PWM_OSC_OSCL_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Output Selection Clear Register - type OSC_Register is record + type PWM_OSC_Register is record -- Write-only. Output Selection Clear for PWMH output of the channel 0 - OSCH : OSC_OSCH_Field := (As_Array => False, Val => 16#0#); + OSCH : PWM_OSC_OSCH_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Output Selection Clear for PWML output of the channel 0 - OSCL : OSC_OSCL_Field := (As_Array => False, Val => 16#0#); + OSCL : PWM_OSC_OSCL_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OSC_Register use record + for PWM_OSC_Register use record OSCH at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; OSCL at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - --------------------- - -- OSSUPD_Register -- - --------------------- - - ------------------- - -- OSSUPD.OSSUPH -- - ------------------- + -- PWM_OSSUPD_OSSUPH array element + subtype PWM_OSSUPD_OSSUPH_Element is ATSAM3X8E.Bit; - -- OSSUPD_OSSUPH array element - subtype OSSUPD_OSSUPH_Element is ATSAM3X8E.Bit; - - -- OSSUPD_OSSUPH array - type OSSUPD_OSSUPH_Field_Array is array (0 .. 7) of OSSUPD_OSSUPH_Element + -- PWM_OSSUPD_OSSUPH array + type PWM_OSSUPD_OSSUPH_Field_Array is array (0 .. 7) + of PWM_OSSUPD_OSSUPH_Element with Component_Size => 1, Size => 8; - -- Type definition for OSSUPD_OSSUPH - type OSSUPD_OSSUPH_Field + -- Type definition for PWM_OSSUPD_OSSUPH + type PWM_OSSUPD_OSSUPH_Field (As_Array : Boolean := False) is record case As_Array is @@ -1474,29 +1290,26 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSSUPH as an array - Arr : OSSUPD_OSSUPH_Field_Array; + Arr : PWM_OSSUPD_OSSUPH_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OSSUPD_OSSUPH_Field use record + for PWM_OSSUPD_OSSUPH_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - ------------------- - -- OSSUPD.OSSUPL -- - ------------------- - - -- OSSUPD_OSSUPL array element - subtype OSSUPD_OSSUPL_Element is ATSAM3X8E.Bit; + -- PWM_OSSUPD_OSSUPL array element + subtype PWM_OSSUPD_OSSUPL_Element is ATSAM3X8E.Bit; - -- OSSUPD_OSSUPL array - type OSSUPD_OSSUPL_Field_Array is array (0 .. 7) of OSSUPD_OSSUPL_Element + -- PWM_OSSUPD_OSSUPL array + type PWM_OSSUPD_OSSUPL_Field_Array is array (0 .. 7) + of PWM_OSSUPD_OSSUPL_Element with Component_Size => 1, Size => 8; - -- Type definition for OSSUPD_OSSUPL - type OSSUPD_OSSUPL_Field + -- Type definition for PWM_OSSUPD_OSSUPL + type PWM_OSSUPD_OSSUPL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1505,55 +1318,48 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSSUPL as an array - Arr : OSSUPD_OSSUPL_Field_Array; + Arr : PWM_OSSUPD_OSSUPL_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OSSUPD_OSSUPL_Field use record + for PWM_OSSUPD_OSSUPL_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Output Selection Set Update Register - type OSSUPD_Register is record + type PWM_OSSUPD_Register is record -- Write-only. Output Selection Set for PWMH output of the channel 0 - OSSUPH : OSSUPD_OSSUPH_Field := + OSSUPH : PWM_OSSUPD_OSSUPH_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Output Selection Set for PWML output of the channel 0 - OSSUPL : OSSUPD_OSSUPL_Field := + OSSUPL : PWM_OSSUPD_OSSUPL_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OSSUPD_Register use record + for PWM_OSSUPD_Register use record OSSUPH at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; OSSUPL at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - --------------------- - -- OSCUPD_Register -- - --------------------- - - ------------------- - -- OSCUPD.OSCUPH -- - ------------------- + -- PWM_OSCUPD_OSCUPH array element + subtype PWM_OSCUPD_OSCUPH_Element is ATSAM3X8E.Bit; - -- OSCUPD_OSCUPH array element - subtype OSCUPD_OSCUPH_Element is ATSAM3X8E.Bit; - - -- OSCUPD_OSCUPH array - type OSCUPD_OSCUPH_Field_Array is array (0 .. 7) of OSCUPD_OSCUPH_Element + -- PWM_OSCUPD_OSCUPH array + type PWM_OSCUPD_OSCUPH_Field_Array is array (0 .. 7) + of PWM_OSCUPD_OSCUPH_Element with Component_Size => 1, Size => 8; - -- Type definition for OSCUPD_OSCUPH - type OSCUPD_OSCUPH_Field + -- Type definition for PWM_OSCUPD_OSCUPH + type PWM_OSCUPD_OSCUPH_Field (As_Array : Boolean := False) is record case As_Array is @@ -1562,29 +1368,26 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- OSCUPH as an array - Arr : OSCUPD_OSCUPH_Field_Array; + Arr : PWM_OSCUPD_OSCUPH_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for OSCUPD_OSCUPH_Field use record + for PWM_OSCUPD_OSCUPH_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - ------------------- - -- OSCUPD.OSCUPL -- - ------------------- - - -- OSCUPD_OSCUPL array element - subtype OSCUPD_OSCUPL_Element is ATSAM3X8E.Bit; + -- PWM_OSCUPD_OSCUPL array element + subtype PWM_OSCUPD_OSCUPL_Element is ATSAM3X8E.Bit; - -- OSCUPD_OSCUPL array - type OSCUPD_OSCUPL_Field_Array is array (0 .. 5) of OSCUPD_OSCUPL_Element + -- PWM_OSCUPD_OSCUPL array + type PWM_OSCUPD_OSCUPL_Field_Array is array (0 .. 5) + of PWM_OSCUPD_OSCUPL_Element with Component_Size => 1, Size => 6; - -- Type definition for OSCUPD_OSCUPL - type OSCUPD_OSCUPL_Field + -- Type definition for PWM_OSCUPD_OSCUPL + type PWM_OSCUPD_OSCUPL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1593,39 +1396,39 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.UInt6; when True => -- OSCUPL as an array - Arr : OSCUPD_OSCUPL_Field_Array; + Arr : PWM_OSCUPD_OSCUPL_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for OSCUPD_OSCUPL_Field use record + for PWM_OSCUPD_OSCUPL_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - subtype OSCUPD_OSCUPDL6_Field is ATSAM3X8E.Bit; - subtype OSCUPD_OSCUPL7_Field is ATSAM3X8E.Bit; + subtype PWM_OSCUPD_OSCUPDL6_Field is ATSAM3X8E.Bit; + subtype PWM_OSCUPD_OSCUPL7_Field is ATSAM3X8E.Bit; -- PWM Output Selection Clear Update Register - type OSCUPD_Register is record + type PWM_OSCUPD_Register is record -- Write-only. Output Selection Clear for PWMH output of the channel 0 - OSCUPH : OSCUPD_OSCUPH_Field := + OSCUPH : PWM_OSCUPD_OSCUPH_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Write-only. Output Selection Clear for PWML output of the channel 0 - OSCUPL : OSCUPD_OSCUPL_Field := + OSCUPL : PWM_OSCUPD_OSCUPL_Field := (As_Array => False, Val => 16#0#); -- Write-only. - OSCUPDL6 : OSCUPD_OSCUPDL6_Field := 16#0#; + OSCUPDL6 : PWM_OSCUPD_OSCUPDL6_Field := 16#0#; -- Write-only. Output Selection Clear for PWML output of the channel 7 - OSCUPL7 : OSCUPD_OSCUPL7_Field := 16#0#; + OSCUPL7 : PWM_OSCUPD_OSCUPL7_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OSCUPD_Register use record + for PWM_OSCUPD_Register use record OSCUPH at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; OSCUPL at 0 range 16 .. 21; @@ -1634,95 +1437,75 @@ package ATSAM3X8E.PWM is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- FMR_Register -- - ------------------ - - subtype FMR_FPOL_Field is ATSAM3X8E.Byte; - subtype FMR_FMOD_Field is ATSAM3X8E.Byte; - subtype FMR_FFIL_Field is ATSAM3X8E.Byte; + subtype PWM_FMR_FPOL_Field is ATSAM3X8E.Byte; + subtype PWM_FMR_FMOD_Field is ATSAM3X8E.Byte; + subtype PWM_FMR_FFIL_Field is ATSAM3X8E.Byte; -- PWM Fault Mode Register - type FMR_Register is record + type PWM_FMR_Register is record -- Fault Polarity (fault input bit varies from 0 to 5) - FPOL : FMR_FPOL_Field := 16#0#; + FPOL : PWM_FMR_FPOL_Field := 16#0#; -- Fault Activation Mode (fault input bit varies from 0 to 5) - FMOD : FMR_FMOD_Field := 16#0#; + FMOD : PWM_FMR_FMOD_Field := 16#0#; -- Fault Filtering (fault input bit varies from 0 to 5) - FFIL : FMR_FFIL_Field := 16#0#; + FFIL : PWM_FMR_FFIL_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FMR_Register use record + for PWM_FMR_Register use record FPOL at 0 range 0 .. 7; FMOD at 0 range 8 .. 15; FFIL at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- FSR_Register -- - ------------------ - - subtype FSR_FIV_Field is ATSAM3X8E.Byte; - subtype FSR_FS_Field is ATSAM3X8E.Byte; + subtype PWM_FSR_FIV_Field is ATSAM3X8E.Byte; + subtype PWM_FSR_FS_Field is ATSAM3X8E.Byte; -- PWM Fault Status Register - type FSR_Register is record + type PWM_FSR_Register is record -- Read-only. Fault Input Value (fault input bit varies from 0 to 5) - FIV : FSR_FIV_Field := 16#0#; + FIV : PWM_FSR_FIV_Field; -- Read-only. Fault Status (fault input bit varies from 0 to 5) - FS : FSR_FS_Field := 16#0#; + FS : PWM_FSR_FS_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FSR_Register use record + for PWM_FSR_Register use record FIV at 0 range 0 .. 7; FS at 0 range 8 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- FCR_Register -- - ------------------ - - subtype FCR_FCLR_Field is ATSAM3X8E.Byte; + subtype PWM_FCR_FCLR_Field is ATSAM3X8E.Byte; -- PWM Fault Clear Register - type FCR_Register is record + type PWM_FCR_Register is record -- Write-only. Fault Clear (fault input bit varies from 0 to 5) - FCLR : FCR_FCLR_Field := 16#0#; + FCLR : PWM_FCR_FCLR_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FCR_Register use record + for PWM_FCR_Register use record FCLR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- FPV_Register -- - ------------------ + -- PWM_FPV_FPVH array element + subtype PWM_FPV_FPVH_Element is ATSAM3X8E.Bit; - -------------- - -- FPV.FPVH -- - -------------- - - -- FPV_FPVH array element - subtype FPV_FPVH_Element is ATSAM3X8E.Bit; - - -- FPV_FPVH array - type FPV_FPVH_Field_Array is array (0 .. 7) of FPV_FPVH_Element + -- PWM_FPV_FPVH array + type PWM_FPV_FPVH_Field_Array is array (0 .. 7) of PWM_FPV_FPVH_Element with Component_Size => 1, Size => 8; - -- Type definition for FPV_FPVH - type FPV_FPVH_Field + -- Type definition for PWM_FPV_FPVH + type PWM_FPV_FPVH_Field (As_Array : Boolean := False) is record case As_Array is @@ -1731,29 +1514,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- FPVH as an array - Arr : FPV_FPVH_Field_Array; + Arr : PWM_FPV_FPVH_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for FPV_FPVH_Field use record + for PWM_FPV_FPVH_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; - -------------- - -- FPV.FPVL -- - -------------- - - -- FPV_FPVL array element - subtype FPV_FPVL_Element is ATSAM3X8E.Bit; + -- PWM_FPV_FPVL array element + subtype PWM_FPV_FPVL_Element is ATSAM3X8E.Bit; - -- FPV_FPVL array - type FPV_FPVL_Field_Array is array (0 .. 7) of FPV_FPVL_Element + -- PWM_FPV_FPVL array + type PWM_FPV_FPVL_Field_Array is array (0 .. 7) of PWM_FPV_FPVL_Element with Component_Size => 1, Size => 8; - -- Type definition for FPV_FPVL - type FPV_FPVL_Field + -- Type definition for PWM_FPV_FPVL + type PWM_FPV_FPVL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1762,85 +1541,103 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- FPVL as an array - Arr : FPV_FPVL_Field_Array; + Arr : PWM_FPV_FPVL_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for FPV_FPVL_Field use record + for PWM_FPV_FPVL_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Fault Protection Value Register - type FPV_Register is record + type PWM_FPV_Register is record -- Fault Protection Value for PWMH output on channel 0 - FPVH : FPV_FPVH_Field := (As_Array => False, Val => 16#0#); + FPVH : PWM_FPV_FPVH_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Fault Protection Value for PWML output on channel 0 - FPVL : FPV_FPVL_Field := (As_Array => False, Val => 16#0#); + FPVL : PWM_FPV_FPVL_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FPV_Register use record + for PWM_FPV_Register use record FPVH at 0 range 0 .. 7; Reserved_8_15 at 0 range 8 .. 15; FPVL at 0 range 16 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- FPE_Register -- - ------------------ - - -- FPE1_FPE array element - subtype FPE1_FPE_Element is ATSAM3X8E.Byte; + -- PWM_FPE1_FPE array element + subtype PWM_FPE1_FPE_Element is ATSAM3X8E.Byte; - -- FPE1_FPE array - type FPE1_FPE_Field_Array is array (0 .. 3) of FPE1_FPE_Element + -- PWM_FPE1_FPE array + type PWM_FPE1_FPE_Field_Array is array (0 .. 3) of PWM_FPE1_FPE_Element with Component_Size => 8, Size => 32; -- PWM Fault Protection Enable Register 1 - type FPE_Register + type PWM_FPE1_Register (As_Array : Boolean := False) is record case As_Array is when False => -- FPE as a value - Val : ATSAM3X8E.Word; + Val : ATSAM3X8E.UInt32; when True => -- FPE as an array - Arr : FPE1_FPE_Field_Array; + Arr : PWM_FPE1_FPE_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; - for FPE_Register use record + for PWM_FPE1_Register use record Val at 0 range 0 .. 31; Arr at 0 range 0 .. 31; end record; - ------------------- - -- ELMR_Register -- - ------------------- + -- PWM_FPE2_FPE array element + subtype PWM_FPE2_FPE_Element is ATSAM3X8E.Byte; - --------------- - -- ELMR.CSEL -- - --------------- + -- PWM_FPE2_FPE array + type PWM_FPE2_FPE_Field_Array is array (4 .. 7) of PWM_FPE2_FPE_Element + with Component_Size => 8, Size => 32; - -- ELMR_CSEL array element - subtype ELMR_CSEL_Element is ATSAM3X8E.Bit; + -- PWM Fault Protection Enable Register 2 + type PWM_FPE2_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FPE as a value + Val : ATSAM3X8E.UInt32; + when True => + -- FPE as an array + Arr : PWM_FPE2_FPE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Object_Size => 32, + Bit_Order => System.Low_Order_First; - -- ELMR_CSEL array - type ELMR_CSEL_Field_Array is array (0 .. 7) of ELMR_CSEL_Element + for PWM_FPE2_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PWM_ELMR_CSEL array element + subtype PWM_ELMR_CSEL_Element is ATSAM3X8E.Bit; + + -- PWM_ELMR_CSEL array + type PWM_ELMR_CSEL_Field_Array is array (0 .. 7) of PWM_ELMR_CSEL_Element with Component_Size => 1, Size => 8; - -- Type definition for ELMR_CSEL - type ELMR_CSEL_Field + -- Type definition for PWM_ELMR_CSEL + type PWM_ELMR_CSEL_Field (As_Array : Boolean := False) is record case As_Array is @@ -1849,50 +1646,40 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.Byte; when True => -- CSEL as an array - Arr : ELMR_CSEL_Field_Array; + Arr : PWM_ELMR_CSEL_Field_Array; end case; end record with Unchecked_Union, Size => 8; - for ELMR_CSEL_Field use record + for PWM_ELMR_CSEL_Field use record Val at 0 range 0 .. 7; Arr at 0 range 0 .. 7; end record; -- PWM Event Line 0 Mode Register - type ELMR_Register is record + type PWM_ELMR_Register is record -- Comparison 0 Selection - CSEL : ELMR_CSEL_Field := (As_Array => False, Val => 16#0#); + CSEL : PWM_ELMR_CSEL_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ELMR_Register use record + for PWM_ELMR_Register use record CSEL at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - -- PWM Event Line 0 Mode Register - type ELMR_Registers is array (0 .. 1) of ELMR_Register; - - ------------------- - -- SMMR_Register -- - ------------------- + -- PWM_SMMR_GCEN array element + subtype PWM_SMMR_GCEN_Element is ATSAM3X8E.Bit; - --------------- - -- SMMR.GCEN -- - --------------- - - -- SMMR_GCEN array element - subtype SMMR_GCEN_Element is ATSAM3X8E.Bit; - - -- SMMR_GCEN array - type SMMR_GCEN_Field_Array is array (0 .. 3) of SMMR_GCEN_Element + -- PWM_SMMR_GCEN array + type PWM_SMMR_GCEN_Field_Array is array (0 .. 3) of PWM_SMMR_GCEN_Element with Component_Size => 1, Size => 4; - -- Type definition for SMMR_GCEN - type SMMR_GCEN_Field + -- Type definition for PWM_SMMR_GCEN + type PWM_SMMR_GCEN_Field (As_Array : Boolean := False) is record case As_Array is @@ -1901,29 +1688,25 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.UInt4; when True => -- GCEN as an array - Arr : SMMR_GCEN_Field_Array; + Arr : PWM_SMMR_GCEN_Field_Array; end case; end record with Unchecked_Union, Size => 4; - for SMMR_GCEN_Field use record + for PWM_SMMR_GCEN_Field use record Val at 0 range 0 .. 3; Arr at 0 range 0 .. 3; end record; - --------------- - -- SMMR.DOWN -- - --------------- + -- PWM_SMMR_DOWN array element + subtype PWM_SMMR_DOWN_Element is ATSAM3X8E.Bit; - -- SMMR_DOWN array element - subtype SMMR_DOWN_Element is ATSAM3X8E.Bit; - - -- SMMR_DOWN array - type SMMR_DOWN_Field_Array is array (0 .. 3) of SMMR_DOWN_Element + -- PWM_SMMR_DOWN array + type PWM_SMMR_DOWN_Field_Array is array (0 .. 3) of PWM_SMMR_DOWN_Element with Component_Size => 1, Size => 4; - -- Type definition for SMMR_DOWN - type SMMR_DOWN_Field + -- Type definition for PWM_SMMR_DOWN + type PWM_SMMR_DOWN_Field (As_Array : Boolean := False) is record case As_Array is @@ -1932,55 +1715,48 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.UInt4; when True => -- DOWN as an array - Arr : SMMR_DOWN_Field_Array; + Arr : PWM_SMMR_DOWN_Field_Array; end case; end record with Unchecked_Union, Size => 4; - for SMMR_DOWN_Field use record + for PWM_SMMR_DOWN_Field use record Val at 0 range 0 .. 3; Arr at 0 range 0 .. 3; end record; -- PWM Stepper Motor Mode Register - type SMMR_Register is record + type PWM_SMMR_Register is record -- Gray Count ENable - GCEN : SMMR_GCEN_Field := (As_Array => False, Val => 16#0#); + GCEN : PWM_SMMR_GCEN_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_4_15 : ATSAM3X8E.UInt12 := 16#0#; -- DOWN Count - DOWN : SMMR_DOWN_Field := (As_Array => False, Val => 16#0#); + DOWN : PWM_SMMR_DOWN_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SMMR_Register use record + for PWM_SMMR_Register use record GCEN at 0 range 0 .. 3; Reserved_4_15 at 0 range 4 .. 15; DOWN at 0 range 16 .. 19; Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------- - -- WPCR_Register -- - ------------------- - - subtype WPCR_WPCMD_Field is ATSAM3X8E.UInt2; - - --------------- - -- WPCR.WPRG -- - --------------- - - -- WPCR_WPRG array element - subtype WPCR_WPRG_Element is ATSAM3X8E.Bit; + subtype PWM_WPCR_WPCMD_Field is ATSAM3X8E.UInt2; + -- PWM_WPCR_WPRG array element + subtype PWM_WPCR_WPRG_Element is ATSAM3X8E.Bit; - -- WPCR_WPRG array - type WPCR_WPRG_Field_Array is array (0 .. 5) of WPCR_WPRG_Element + -- PWM_WPCR_WPRG array + type PWM_WPCR_WPRG_Field_Array is array (0 .. 5) of PWM_WPCR_WPRG_Element with Component_Size => 1, Size => 6; - -- Type definition for WPCR_WPRG - type WPCR_WPRG_Field + -- Type definition for PWM_WPCR_WPRG + type PWM_WPCR_WPRG_Field (As_Array : Boolean := False) is record case As_Array is @@ -1989,52 +1765,45 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.UInt6; when True => -- WPRG as an array - Arr : WPCR_WPRG_Field_Array; + Arr : PWM_WPCR_WPRG_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for WPCR_WPRG_Field use record + for PWM_WPCR_WPRG_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - subtype WPCR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype PWM_WPCR_WPKEY_Field is ATSAM3X8E.UInt24; -- PWM Write Protect Control Register - type WPCR_Register is record + type PWM_WPCR_Register is record -- Write-only. Write Protect Command - WPCMD : WPCR_WPCMD_Field := 16#0#; + WPCMD : PWM_WPCR_WPCMD_Field := 16#0#; -- Write-only. Write Protect Register Group 0 - WPRG : WPCR_WPRG_Field := (As_Array => False, Val => 16#0#); + WPRG : PWM_WPCR_WPRG_Field := (As_Array => False, Val => 16#0#); -- Write-only. Write Protect Key - WPKEY : WPCR_WPKEY_Field := 16#0#; + WPKEY : PWM_WPCR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPCR_Register use record + for PWM_WPCR_Register use record WPCMD at 0 range 0 .. 1; WPRG at 0 range 2 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - ---------------- - -- WPSR.WPSWS -- - ---------------- - - -- WPSR_WPSWS array element - subtype WPSR_WPSWS_Element is ATSAM3X8E.Bit; + -- PWM_WPSR_WPSWS array element + subtype PWM_WPSR_WPSWS_Element is ATSAM3X8E.Bit; - -- WPSR_WPSWS array - type WPSR_WPSWS_Field_Array is array (0 .. 5) of WPSR_WPSWS_Element + -- PWM_WPSR_WPSWS array + type PWM_WPSR_WPSWS_Field_Array is array (0 .. 5) + of PWM_WPSR_WPSWS_Element with Component_Size => 1, Size => 6; - -- Type definition for WPSR_WPSWS - type WPSR_WPSWS_Field + -- Type definition for PWM_WPSR_WPSWS + type PWM_WPSR_WPSWS_Field (As_Array : Boolean := False) is record case As_Array is @@ -2043,31 +1812,27 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.UInt6; when True => -- WPSWS as an array - Arr : WPSR_WPSWS_Field_Array; + Arr : PWM_WPSR_WPSWS_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for WPSR_WPSWS_Field use record + for PWM_WPSR_WPSWS_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - subtype WPSR_WPVS_Field is ATSAM3X8E.Bit; + subtype PWM_WPSR_WPVS_Field is ATSAM3X8E.Bit; + -- PWM_WPSR_WPHWS array element + subtype PWM_WPSR_WPHWS_Element is ATSAM3X8E.Bit; - ---------------- - -- WPSR.WPHWS -- - ---------------- - - -- WPSR_WPHWS array element - subtype WPSR_WPHWS_Element is ATSAM3X8E.Bit; - - -- WPSR_WPHWS array - type WPSR_WPHWS_Field_Array is array (0 .. 5) of WPSR_WPHWS_Element + -- PWM_WPSR_WPHWS array + type PWM_WPSR_WPHWS_Field_Array is array (0 .. 5) + of PWM_WPSR_WPHWS_Element with Component_Size => 1, Size => 6; - -- Type definition for WPSR_WPHWS - type WPSR_WPHWS_Field + -- Type definition for PWM_WPSR_WPHWS + type PWM_WPSR_WPHWS_Field (As_Array : Boolean := False) is record case As_Array is @@ -2076,36 +1841,36 @@ package ATSAM3X8E.PWM is Val : ATSAM3X8E.UInt6; when True => -- WPHWS as an array - Arr : WPSR_WPHWS_Field_Array; + Arr : PWM_WPSR_WPHWS_Field_Array; end case; end record with Unchecked_Union, Size => 6; - for WPSR_WPHWS_Field use record + for PWM_WPSR_WPHWS_Field use record Val at 0 range 0 .. 5; Arr at 0 range 0 .. 5; end record; - subtype WPSR_WPVSRC_Field is ATSAM3X8E.Short; + subtype PWM_WPSR_WPVSRC_Field is ATSAM3X8E.UInt16; -- PWM Write Protect Status Register - type WPSR_Register is record + type PWM_WPSR_Register is record -- Read-only. Write Protect SW Status - WPSWS : WPSR_WPSWS_Field := (As_Array => False, Val => 16#0#); + WPSWS : PWM_WPSR_WPSWS_Field; -- unspecified Reserved_6_6 : ATSAM3X8E.Bit; -- Read-only. Write Protect Violation Status - WPVS : WPSR_WPVS_Field := 16#0#; + WPVS : PWM_WPSR_WPVS_Field; -- Read-only. Write Protect HW Status - WPHWS : WPSR_WPHWS_Field := (As_Array => False, Val => 16#0#); + WPHWS : PWM_WPSR_WPHWS_Field; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2; -- Read-only. Write Protect Violation Source - WPVSRC : WPSR_WPVSRC_Field := 16#0#; + WPVSRC : PWM_WPSR_WPVSRC_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for PWM_WPSR_Register use record WPSWS at 0 range 0 .. 5; Reserved_6_6 at 0 range 6 .. 6; WPVS at 0 range 7 .. 7; @@ -2114,73 +1879,61 @@ package ATSAM3X8E.PWM is WPVSRC at 0 range 16 .. 31; end record; - ------------------ - -- TCR_Register -- - ------------------ - - subtype TCR_TXCTR_Field is ATSAM3X8E.Short; + subtype PWM_TCR_TXCTR_Field is ATSAM3X8E.UInt16; -- Transmit Counter Register - type TCR_Register is record + type PWM_TCR_Register is record -- Transmit Counter Register - TXCTR : TCR_TXCTR_Field := 16#0#; + TXCTR : PWM_TCR_TXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TCR_Register use record + for PWM_TCR_Register use record TXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- TNCR_Register -- - ------------------- - - subtype TNCR_TXNCTR_Field is ATSAM3X8E.Short; + subtype PWM_TNCR_TXNCTR_Field is ATSAM3X8E.UInt16; -- Transmit Next Counter Register - type TNCR_Register is record + type PWM_TNCR_Register is record -- Transmit Counter Next - TXNCTR : TNCR_TXNCTR_Field := 16#0#; + TXNCTR : PWM_TNCR_TXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TNCR_Register use record + for PWM_TNCR_Register use record TXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- PTCR_Register -- - ------------------- - - subtype PTCR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_RXTDIS_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTDIS_Field is ATSAM3X8E.Bit; + subtype PWM_PTCR_RXTEN_Field is ATSAM3X8E.Bit; + subtype PWM_PTCR_RXTDIS_Field is ATSAM3X8E.Bit; + subtype PWM_PTCR_TXTEN_Field is ATSAM3X8E.Bit; + subtype PWM_PTCR_TXTDIS_Field is ATSAM3X8E.Bit; -- Transfer Control Register - type PTCR_Register is record + type PWM_PTCR_Register is record -- Write-only. Receiver Transfer Enable - RXTEN : PTCR_RXTEN_Field := 16#0#; + RXTEN : PWM_PTCR_RXTEN_Field := 16#0#; -- Write-only. Receiver Transfer Disable - RXTDIS : PTCR_RXTDIS_Field := 16#0#; + RXTDIS : PWM_PTCR_RXTDIS_Field := 16#0#; -- unspecified Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; -- Write-only. Transmitter Transfer Enable - TXTEN : PTCR_TXTEN_Field := 16#0#; + TXTEN : PWM_PTCR_TXTEN_Field := 16#0#; -- Write-only. Transmitter Transfer Disable - TXTDIS : PTCR_TXTDIS_Field := 16#0#; + TXTDIS : PWM_PTCR_TXTDIS_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTCR_Register use record + for PWM_PTCR_Register use record RXTEN at 0 range 0 .. 0; RXTDIS at 0 range 1 .. 1; Reserved_2_7 at 0 range 2 .. 7; @@ -2189,50 +1942,42 @@ package ATSAM3X8E.PWM is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- PTSR_Register -- - ------------------- - - subtype PTSR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTSR_TXTEN_Field is ATSAM3X8E.Bit; + subtype PWM_PTSR_RXTEN_Field is ATSAM3X8E.Bit; + subtype PWM_PTSR_TXTEN_Field is ATSAM3X8E.Bit; -- Transfer Status Register - type PTSR_Register is record + type PWM_PTSR_Register is record -- Read-only. Receiver Transfer Enable - RXTEN : PTSR_RXTEN_Field := 16#0#; + RXTEN : PWM_PTSR_RXTEN_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Transmitter Transfer Enable - TXTEN : PTSR_TXTEN_Field := 16#0#; + TXTEN : PWM_PTSR_TXTEN_Field; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTSR_Register use record + for PWM_PTSR_Register use record RXTEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; TXTEN at 0 range 8 .. 8; Reserved_9_31 at 0 range 9 .. 31; end record; - ------------------- - -- CMPV_Register -- - ------------------- - - subtype CMPV0_CV_Field is ATSAM3X8E.UInt24; - subtype CMPV0_CVM_Field is ATSAM3X8E.Bit; + subtype CMPV_CV_Field is ATSAM3X8E.UInt24; + subtype CMPV_CVM_Field is ATSAM3X8E.Bit; -- PWM Comparison 0 Value Register type CMPV_Register is record -- Comparison x Value - CV : CMPV0_CV_Field := 16#0#; + CV : CMPV_CV_Field := 16#0#; -- Comparison x Value Mode - CVM : CMPV0_CVM_Field := 16#0#; + CVM : CMPV_CVM_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMPV_Register use record CV at 0 range 0 .. 23; @@ -2240,23 +1985,19 @@ package ATSAM3X8E.PWM is Reserved_25_31 at 0 range 25 .. 31; end record; - ---------------------- - -- CMPVUPD_Register -- - ---------------------- - - subtype CMPVUPD0_CVUPD_Field is ATSAM3X8E.UInt24; - subtype CMPVUPD0_CVMUPD_Field is ATSAM3X8E.Bit; + subtype CMPVUPD_CVUPD_Field is ATSAM3X8E.UInt24; + subtype CMPVUPD_CVMUPD_Field is ATSAM3X8E.Bit; -- PWM Comparison 0 Value Update Register type CMPVUPD_Register is record -- Write-only. Comparison x Value Update - CVUPD : CMPVUPD0_CVUPD_Field := 16#0#; + CVUPD : CMPVUPD_CVUPD_Field := 16#0#; -- Write-only. Comparison x Value Mode Update - CVMUPD : CMPVUPD0_CVMUPD_Field := 16#0#; + CVMUPD : CMPVUPD_CVMUPD_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMPVUPD_Register use record CVUPD at 0 range 0 .. 23; @@ -2264,37 +2005,33 @@ package ATSAM3X8E.PWM is Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------- - -- CMPM_Register -- - ------------------- - - subtype CMPM0_CEN_Field is ATSAM3X8E.Bit; - subtype CMPM0_CTR_Field is ATSAM3X8E.UInt4; - subtype CMPM0_CPR_Field is ATSAM3X8E.UInt4; - subtype CMPM0_CPRCNT_Field is ATSAM3X8E.UInt4; - subtype CMPM0_CUPR_Field is ATSAM3X8E.UInt4; - subtype CMPM0_CUPRCNT_Field is ATSAM3X8E.UInt4; + subtype CMPM_CEN_Field is ATSAM3X8E.Bit; + subtype CMPM_CTR_Field is ATSAM3X8E.UInt4; + subtype CMPM_CPR_Field is ATSAM3X8E.UInt4; + subtype CMPM_CPRCNT_Field is ATSAM3X8E.UInt4; + subtype CMPM_CUPR_Field is ATSAM3X8E.UInt4; + subtype CMPM_CUPRCNT_Field is ATSAM3X8E.UInt4; -- PWM Comparison 0 Mode Register type CMPM_Register is record -- Comparison x Enable - CEN : CMPM0_CEN_Field := 16#0#; + CEN : CMPM_CEN_Field := 16#0#; -- unspecified Reserved_1_3 : ATSAM3X8E.UInt3 := 16#0#; -- Comparison x Trigger - CTR : CMPM0_CTR_Field := 16#0#; + CTR : CMPM_CTR_Field := 16#0#; -- Comparison x Period - CPR : CMPM0_CPR_Field := 16#0#; + CPR : CMPM_CPR_Field := 16#0#; -- Comparison x Period Counter - CPRCNT : CMPM0_CPRCNT_Field := 16#0#; + CPRCNT : CMPM_CPRCNT_Field := 16#0#; -- Comparison x Update Period - CUPR : CMPM0_CUPR_Field := 16#0#; + CUPR : CMPM_CUPR_Field := 16#0#; -- Comparison x Update Period Counter - CUPRCNT : CMPM0_CUPRCNT_Field := 16#0#; + CUPRCNT : CMPM_CUPRCNT_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMPM_Register use record CEN at 0 range 0 .. 0; @@ -2307,33 +2044,29 @@ package ATSAM3X8E.PWM is Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------- - -- CMPMUPD_Register -- - ---------------------- - - subtype CMPMUPD0_CENUPD_Field is ATSAM3X8E.Bit; - subtype CMPMUPD0_CTRUPD_Field is ATSAM3X8E.UInt4; - subtype CMPMUPD0_CPRUPD_Field is ATSAM3X8E.UInt4; - subtype CMPMUPD0_CUPRUPD_Field is ATSAM3X8E.UInt4; + subtype CMPMUPD_CENUPD_Field is ATSAM3X8E.Bit; + subtype CMPMUPD_CTRUPD_Field is ATSAM3X8E.UInt4; + subtype CMPMUPD_CPRUPD_Field is ATSAM3X8E.UInt4; + subtype CMPMUPD_CUPRUPD_Field is ATSAM3X8E.UInt4; -- PWM Comparison 0 Mode Update Register type CMPMUPD_Register is record -- Write-only. Comparison x Enable Update - CENUPD : CMPMUPD0_CENUPD_Field := 16#0#; + CENUPD : CMPMUPD_CENUPD_Field := 16#0#; -- unspecified Reserved_1_3 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. Comparison x Trigger Update - CTRUPD : CMPMUPD0_CTRUPD_Field := 16#0#; + CTRUPD : CMPMUPD_CTRUPD_Field := 16#0#; -- Write-only. Comparison x Period Update - CPRUPD : CMPMUPD0_CPRUPD_Field := 16#0#; + CPRUPD : CMPMUPD_CPRUPD_Field := 16#0#; -- unspecified Reserved_12_15 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Comparison x Update Period Update - CUPRUPD : CMPMUPD0_CUPRUPD_Field := 16#0#; + CUPRUPD : CMPMUPD_CUPRUPD_Field := 16#0#; -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMPMUPD_Register use record CENUPD at 0 range 0 .. 0; @@ -2345,14 +2078,9 @@ package ATSAM3X8E.PWM is Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------ - -- CMR_Register -- - ------------------ - -- Channel Pre-scaler - type CPRE_Field is - ( - -- Master clock + type CMR0_CPRE_Field is + (-- Master clock Mck, -- Master clock/2 Mck_Div_2, @@ -2379,7 +2107,7 @@ package ATSAM3X8E.PWM is -- Clock B Clkb) with Size => 4; - for CPRE_Field use + for CMR0_CPRE_Field use (Mck => 0, Mck_Div_2 => 1, Mck_Div_4 => 2, @@ -2394,37 +2122,37 @@ package ATSAM3X8E.PWM is Clka => 11, Clkb => 12); - subtype CMR0_CALG_Field is ATSAM3X8E.Bit; - subtype CMR0_CPOL_Field is ATSAM3X8E.Bit; - subtype CMR0_CES_Field is ATSAM3X8E.Bit; - subtype CMR0_DTE_Field is ATSAM3X8E.Bit; - subtype CMR0_DTHI_Field is ATSAM3X8E.Bit; - subtype CMR0_DTLI_Field is ATSAM3X8E.Bit; + subtype CMR_CALG_Field is ATSAM3X8E.Bit; + subtype CMR_CPOL_Field is ATSAM3X8E.Bit; + subtype CMR_CES_Field is ATSAM3X8E.Bit; + subtype CMR_DTE_Field is ATSAM3X8E.Bit; + subtype CMR_DTHI_Field is ATSAM3X8E.Bit; + subtype CMR_DTLI_Field is ATSAM3X8E.Bit; -- PWM Channel Mode Register (ch_num = 0) type CMR_Register is record -- Channel Pre-scaler - CPRE : CPRE_Field := Mck; + CPRE : CMR0_CPRE_Field := ATSAM3X8E.PWM.Mck; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; -- Channel Alignment - CALG : CMR0_CALG_Field := 16#0#; + CALG : CMR_CALG_Field := 16#0#; -- Channel Polarity - CPOL : CMR0_CPOL_Field := 16#0#; + CPOL : CMR_CPOL_Field := 16#0#; -- Counter Event Selection - CES : CMR0_CES_Field := 16#0#; + CES : CMR_CES_Field := 16#0#; -- unspecified Reserved_11_15 : ATSAM3X8E.UInt5 := 16#0#; -- Dead-Time Generator Enable - DTE : CMR0_DTE_Field := 16#0#; + DTE : CMR_DTE_Field := 16#0#; -- Dead-Time PWMHx Output Inverted - DTHI : CMR0_DTHI_Field := 16#0#; + DTHI : CMR_DTHI_Field := 16#0#; -- Dead-Time PWMLx Output Inverted - DTLI : CMR0_DTLI_Field := 16#0#; + DTLI : CMR_DTLI_Field := 16#0#; -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMR_Register use record CPRE at 0 range 0 .. 3; @@ -2439,142 +2167,114 @@ package ATSAM3X8E.PWM is Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------- - -- CDTY_Register -- - ------------------- - - subtype CDTY0_CDTY_Field is ATSAM3X8E.UInt24; + subtype CDTY_CDTY_Field is ATSAM3X8E.UInt24; -- PWM Channel Duty Cycle Register (ch_num = 0) type CDTY_Register is record -- Channel Duty-Cycle - CDTY : CDTY0_CDTY_Field := 16#0#; + CDTY : CDTY_CDTY_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CDTY_Register use record CDTY at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------- - -- CDTYUPD_Register -- - ---------------------- - - subtype CDTYUPD0_CDTYUPD_Field is ATSAM3X8E.UInt24; + subtype CDTYUPD_CDTYUPD_Field is ATSAM3X8E.UInt24; -- PWM Channel Duty Cycle Update Register (ch_num = 0) type CDTYUPD_Register is record -- Write-only. Channel Duty-Cycle Update - CDTYUPD : CDTYUPD0_CDTYUPD_Field := 16#0#; + CDTYUPD : CDTYUPD_CDTYUPD_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CDTYUPD_Register use record CDTYUPD at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- CPRD_Register -- - ------------------- - - subtype CPRD0_CPRD_Field is ATSAM3X8E.UInt24; + subtype CPRD_CPRD_Field is ATSAM3X8E.UInt24; -- PWM Channel Period Register (ch_num = 0) type CPRD_Register is record -- Channel Period - CPRD : CPRD0_CPRD_Field := 16#0#; + CPRD : CPRD_CPRD_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CPRD_Register use record CPRD at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------- - -- CPRDUPD_Register -- - ---------------------- - - subtype CPRDUPD0_CPRDUPD_Field is ATSAM3X8E.UInt24; + subtype CPRDUPD_CPRDUPD_Field is ATSAM3X8E.UInt24; -- PWM Channel Period Update Register (ch_num = 0) type CPRDUPD_Register is record -- Write-only. Channel Period Update - CPRDUPD : CPRDUPD0_CPRDUPD_Field := 16#0#; + CPRDUPD : CPRDUPD_CPRDUPD_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CPRDUPD_Register use record CPRDUPD at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- CCNT_Register -- - ------------------- - - subtype CCNT0_CNT_Field is ATSAM3X8E.UInt24; + subtype CCNT_CNT_Field is ATSAM3X8E.UInt24; -- PWM Channel Counter Register (ch_num = 0) type CCNT_Register is record -- Read-only. Channel Counter Register - CNT : CCNT0_CNT_Field := 16#0#; + CNT : CCNT_CNT_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCNT_Register use record CNT at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ----------------- - -- DT_Register -- - ----------------- - - subtype DT0_DTH_Field is ATSAM3X8E.Short; - subtype DT0_DTL_Field is ATSAM3X8E.Short; + subtype DT_DTH_Field is ATSAM3X8E.UInt16; + subtype DT_DTL_Field is ATSAM3X8E.UInt16; -- PWM Channel Dead Time Register (ch_num = 0) type DT_Register is record -- Dead-Time Value for PWMHx Output - DTH : DT0_DTH_Field := 16#0#; + DTH : DT_DTH_Field := 16#0#; -- Dead-Time Value for PWMLx Output - DTL : DT0_DTL_Field := 16#0#; + DTL : DT_DTL_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DT_Register use record DTH at 0 range 0 .. 15; DTL at 0 range 16 .. 31; end record; - -------------------- - -- DTUPD_Register -- - -------------------- - - subtype DTUPD0_DTHUPD_Field is ATSAM3X8E.Short; - subtype DTUPD0_DTLUPD_Field is ATSAM3X8E.Short; + subtype DTUPD_DTHUPD_Field is ATSAM3X8E.UInt16; + subtype DTUPD_DTLUPD_Field is ATSAM3X8E.UInt16; -- PWM Channel Dead Time Update Register (ch_num = 0) type DTUPD_Register is record -- Write-only. Dead-Time Value Update for PWMHx Output - DTHUPD : DTUPD0_DTHUPD_Field := 16#0#; + DTHUPD : DTUPD_DTHUPD_Field := 16#0#; -- Write-only. Dead-Time Value Update for PWMLx Output - DTLUPD : DTUPD0_DTLUPD_Field := 16#0#; + DTLUPD : DTUPD_DTLUPD_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DTUPD_Register use record DTHUPD at 0 range 0 .. 15; @@ -2588,411 +2288,547 @@ package ATSAM3X8E.PWM is -- Pulse Width Modulation Controller type PWM_Peripheral is record -- PWM Clock Register - CLK : CLK_Register; + CLK : aliased PWM_CLK_Register; + pragma Volatile_Full_Access (CLK); -- PWM Enable Register - ENA : ENA_Register; + ENA : aliased PWM_ENA_Register; + pragma Volatile_Full_Access (ENA); -- PWM Disable Register - DIS : DIS_Register; + DIS : aliased PWM_DIS_Register; + pragma Volatile_Full_Access (DIS); -- PWM Status Register - SR : SR_Register; + SR : aliased PWM_SR_Register; + pragma Volatile_Full_Access (SR); -- PWM Interrupt Enable Register 1 - IER1 : IER1_Register; + IER1 : aliased PWM_IER1_Register; + pragma Volatile_Full_Access (IER1); -- PWM Interrupt Disable Register 1 - IDR1 : IDR1_Register; + IDR1 : aliased PWM_IDR1_Register; + pragma Volatile_Full_Access (IDR1); -- PWM Interrupt Mask Register 1 - IMR1 : IMR1_Register; + IMR1 : aliased PWM_IMR1_Register; + pragma Volatile_Full_Access (IMR1); -- PWM Interrupt Status Register 1 - ISR1 : ISR1_Register; + ISR1 : aliased PWM_ISR1_Register; + pragma Volatile_Full_Access (ISR1); -- PWM Sync Channels Mode Register - SCM : SCM_Register; + SCM : aliased PWM_SCM_Register; + pragma Volatile_Full_Access (SCM); -- PWM Sync Channels Update Control Register - SCUC : SCUC_Register; + SCUC : aliased PWM_SCUC_Register; + pragma Volatile_Full_Access (SCUC); -- PWM Sync Channels Update Period Register - SCUP : SCUP_Register; + SCUP : aliased PWM_SCUP_Register; + pragma Volatile_Full_Access (SCUP); -- PWM Sync Channels Update Period Update Register - SCUPUPD : SCUPUPD_Register; + SCUPUPD : aliased PWM_SCUPUPD_Register; + pragma Volatile_Full_Access (SCUPUPD); -- PWM Interrupt Enable Register 2 - IER2 : IER2_Register; + IER2 : aliased PWM_IER2_Register; + pragma Volatile_Full_Access (IER2); -- PWM Interrupt Disable Register 2 - IDR2 : IDR2_Register; + IDR2 : aliased PWM_IDR2_Register; + pragma Volatile_Full_Access (IDR2); -- PWM Interrupt Mask Register 2 - IMR2 : IMR2_Register; + IMR2 : aliased PWM_IMR2_Register; + pragma Volatile_Full_Access (IMR2); -- PWM Interrupt Status Register 2 - ISR2 : ISR2_Register; + ISR2 : aliased PWM_ISR2_Register; + pragma Volatile_Full_Access (ISR2); -- PWM Output Override Value Register - OOV : OOV_Register; + OOV : aliased PWM_OOV_Register; + pragma Volatile_Full_Access (OOV); -- PWM Output Selection Register - OS : OS_Register; + OS : aliased PWM_OS_Register; + pragma Volatile_Full_Access (OS); -- PWM Output Selection Set Register - OSS : OSS_Register; + OSS : aliased PWM_OSS_Register; + pragma Volatile_Full_Access (OSS); -- PWM Output Selection Clear Register - OSC : OSC_Register; + OSC : aliased PWM_OSC_Register; + pragma Volatile_Full_Access (OSC); -- PWM Output Selection Set Update Register - OSSUPD : OSSUPD_Register; + OSSUPD : aliased PWM_OSSUPD_Register; + pragma Volatile_Full_Access (OSSUPD); -- PWM Output Selection Clear Update Register - OSCUPD : OSCUPD_Register; + OSCUPD : aliased PWM_OSCUPD_Register; + pragma Volatile_Full_Access (OSCUPD); -- PWM Fault Mode Register - FMR : FMR_Register; + FMR : aliased PWM_FMR_Register; + pragma Volatile_Full_Access (FMR); -- PWM Fault Status Register - FSR : FSR_Register; + FSR : aliased PWM_FSR_Register; + pragma Volatile_Full_Access (FSR); -- PWM Fault Clear Register - FCR : FCR_Register; + FCR : aliased PWM_FCR_Register; + pragma Volatile_Full_Access (FCR); -- PWM Fault Protection Value Register - FPV : FPV_Register; + FPV : aliased PWM_FPV_Register; + pragma Volatile_Full_Access (FPV); -- PWM Fault Protection Enable Register 1 - FPE1 : FPE_Register; + FPE1 : aliased PWM_FPE1_Register; + pragma Volatile_Full_Access (FPE1); -- PWM Fault Protection Enable Register 2 - FPE2 : FPE_Register; + FPE2 : aliased PWM_FPE2_Register; + pragma Volatile_Full_Access (FPE2); + -- PWM Event Line 0 Mode Register + ELMR_0 : aliased PWM_ELMR_Register; + pragma Volatile_Full_Access (ELMR_0); -- PWM Event Line 0 Mode Register - ELMR : ELMR_Registers; + ELMR_1 : aliased PWM_ELMR_Register; + pragma Volatile_Full_Access (ELMR_1); -- PWM Stepper Motor Mode Register - SMMR : SMMR_Register; + SMMR : aliased PWM_SMMR_Register; + pragma Volatile_Full_Access (SMMR); -- PWM Write Protect Control Register - WPCR : WPCR_Register; + WPCR : aliased PWM_WPCR_Register; + pragma Volatile_Full_Access (WPCR); -- PWM Write Protect Status Register - WPSR : WPSR_Register; + WPSR : aliased PWM_WPSR_Register; + pragma Volatile_Full_Access (WPSR); -- Transmit Pointer Register - TPR : ATSAM3X8E.Word; + TPR : aliased ATSAM3X8E.UInt32; -- Transmit Counter Register - TCR : TCR_Register; + TCR : aliased PWM_TCR_Register; + pragma Volatile_Full_Access (TCR); -- Transmit Next Pointer Register - TNPR : ATSAM3X8E.Word; + TNPR : aliased ATSAM3X8E.UInt32; -- Transmit Next Counter Register - TNCR : TNCR_Register; + TNCR : aliased PWM_TNCR_Register; + pragma Volatile_Full_Access (TNCR); -- Transfer Control Register - PTCR : PTCR_Register; + PTCR : aliased PWM_PTCR_Register; + pragma Volatile_Full_Access (PTCR); -- Transfer Status Register - PTSR : PTSR_Register; + PTSR : aliased PWM_PTSR_Register; + pragma Volatile_Full_Access (PTSR); -- PWM Comparison 0 Value Register - CMPV0 : CMPV_Register; + CMPV0 : aliased CMPV_Register; + pragma Volatile_Full_Access (CMPV0); -- PWM Comparison 0 Value Update Register - CMPVUPD0 : CMPVUPD_Register; + CMPVUPD0 : aliased CMPVUPD_Register; + pragma Volatile_Full_Access (CMPVUPD0); -- PWM Comparison 0 Mode Register - CMPM0 : CMPM_Register; + CMPM0 : aliased CMPM_Register; + pragma Volatile_Full_Access (CMPM0); -- PWM Comparison 0 Mode Update Register - CMPMUPD0 : CMPMUPD_Register; + CMPMUPD0 : aliased CMPMUPD_Register; + pragma Volatile_Full_Access (CMPMUPD0); -- PWM Comparison 1 Value Register - CMPV1 : CMPV_Register; + CMPV1 : aliased CMPV_Register; + pragma Volatile_Full_Access (CMPV1); -- PWM Comparison 1 Value Update Register - CMPVUPD1 : CMPVUPD_Register; + CMPVUPD1 : aliased CMPVUPD_Register; + pragma Volatile_Full_Access (CMPVUPD1); -- PWM Comparison 1 Mode Register - CMPM1 : CMPM_Register; + CMPM1 : aliased CMPM_Register; + pragma Volatile_Full_Access (CMPM1); -- PWM Comparison 1 Mode Update Register - CMPMUPD1 : CMPMUPD_Register; + CMPMUPD1 : aliased CMPMUPD_Register; + pragma Volatile_Full_Access (CMPMUPD1); -- PWM Comparison 2 Value Register - CMPV2 : CMPV_Register; + CMPV2 : aliased CMPV_Register; + pragma Volatile_Full_Access (CMPV2); -- PWM Comparison 2 Value Update Register - CMPVUPD2 : CMPVUPD_Register; + CMPVUPD2 : aliased CMPVUPD_Register; + pragma Volatile_Full_Access (CMPVUPD2); -- PWM Comparison 2 Mode Register - CMPM2 : CMPM_Register; + CMPM2 : aliased CMPM_Register; + pragma Volatile_Full_Access (CMPM2); -- PWM Comparison 2 Mode Update Register - CMPMUPD2 : CMPMUPD_Register; + CMPMUPD2 : aliased CMPMUPD_Register; + pragma Volatile_Full_Access (CMPMUPD2); -- PWM Comparison 3 Value Register - CMPV3 : CMPV_Register; + CMPV3 : aliased CMPV_Register; + pragma Volatile_Full_Access (CMPV3); -- PWM Comparison 3 Value Update Register - CMPVUPD3 : CMPVUPD_Register; + CMPVUPD3 : aliased CMPVUPD_Register; + pragma Volatile_Full_Access (CMPVUPD3); -- PWM Comparison 3 Mode Register - CMPM3 : CMPM_Register; + CMPM3 : aliased CMPM_Register; + pragma Volatile_Full_Access (CMPM3); -- PWM Comparison 3 Mode Update Register - CMPMUPD3 : CMPMUPD_Register; + CMPMUPD3 : aliased CMPMUPD_Register; + pragma Volatile_Full_Access (CMPMUPD3); -- PWM Comparison 4 Value Register - CMPV4 : CMPV_Register; + CMPV4 : aliased CMPV_Register; + pragma Volatile_Full_Access (CMPV4); -- PWM Comparison 4 Value Update Register - CMPVUPD4 : CMPVUPD_Register; + CMPVUPD4 : aliased CMPVUPD_Register; + pragma Volatile_Full_Access (CMPVUPD4); -- PWM Comparison 4 Mode Register - CMPM4 : CMPM_Register; + CMPM4 : aliased CMPM_Register; + pragma Volatile_Full_Access (CMPM4); -- PWM Comparison 4 Mode Update Register - CMPMUPD4 : CMPMUPD_Register; + CMPMUPD4 : aliased CMPMUPD_Register; + pragma Volatile_Full_Access (CMPMUPD4); -- PWM Comparison 5 Value Register - CMPV5 : CMPV_Register; + CMPV5 : aliased CMPV_Register; + pragma Volatile_Full_Access (CMPV5); -- PWM Comparison 5 Value Update Register - CMPVUPD5 : CMPVUPD_Register; + CMPVUPD5 : aliased CMPVUPD_Register; + pragma Volatile_Full_Access (CMPVUPD5); -- PWM Comparison 5 Mode Register - CMPM5 : CMPM_Register; + CMPM5 : aliased CMPM_Register; + pragma Volatile_Full_Access (CMPM5); -- PWM Comparison 5 Mode Update Register - CMPMUPD5 : CMPMUPD_Register; + CMPMUPD5 : aliased CMPMUPD_Register; + pragma Volatile_Full_Access (CMPMUPD5); -- PWM Comparison 6 Value Register - CMPV6 : CMPV_Register; + CMPV6 : aliased CMPV_Register; + pragma Volatile_Full_Access (CMPV6); -- PWM Comparison 6 Value Update Register - CMPVUPD6 : CMPVUPD_Register; + CMPVUPD6 : aliased CMPVUPD_Register; + pragma Volatile_Full_Access (CMPVUPD6); -- PWM Comparison 6 Mode Register - CMPM6 : CMPM_Register; + CMPM6 : aliased CMPM_Register; + pragma Volatile_Full_Access (CMPM6); -- PWM Comparison 6 Mode Update Register - CMPMUPD6 : CMPMUPD_Register; + CMPMUPD6 : aliased CMPMUPD_Register; + pragma Volatile_Full_Access (CMPMUPD6); -- PWM Comparison 7 Value Register - CMPV7 : CMPV_Register; + CMPV7 : aliased CMPV_Register; + pragma Volatile_Full_Access (CMPV7); -- PWM Comparison 7 Value Update Register - CMPVUPD7 : CMPVUPD_Register; + CMPVUPD7 : aliased CMPVUPD_Register; + pragma Volatile_Full_Access (CMPVUPD7); -- PWM Comparison 7 Mode Register - CMPM7 : CMPM_Register; + CMPM7 : aliased CMPM_Register; + pragma Volatile_Full_Access (CMPM7); -- PWM Comparison 7 Mode Update Register - CMPMUPD7 : CMPMUPD_Register; + CMPMUPD7 : aliased CMPMUPD_Register; + pragma Volatile_Full_Access (CMPMUPD7); -- PWM Channel Mode Register (ch_num = 0) - CMR0 : CMR_Register; + CMR0 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR0); -- PWM Channel Duty Cycle Register (ch_num = 0) - CDTY0 : CDTY_Register; + CDTY0 : aliased CDTY_Register; + pragma Volatile_Full_Access (CDTY0); -- PWM Channel Duty Cycle Update Register (ch_num = 0) - CDTYUPD0 : CDTYUPD_Register; + CDTYUPD0 : aliased CDTYUPD_Register; + pragma Volatile_Full_Access (CDTYUPD0); -- PWM Channel Period Register (ch_num = 0) - CPRD0 : CPRD_Register; + CPRD0 : aliased CPRD_Register; + pragma Volatile_Full_Access (CPRD0); -- PWM Channel Period Update Register (ch_num = 0) - CPRDUPD0 : CPRDUPD_Register; + CPRDUPD0 : aliased CPRDUPD_Register; + pragma Volatile_Full_Access (CPRDUPD0); -- PWM Channel Counter Register (ch_num = 0) - CCNT0 : CCNT_Register; + CCNT0 : aliased CCNT_Register; + pragma Volatile_Full_Access (CCNT0); -- PWM Channel Dead Time Register (ch_num = 0) - DT0 : DT_Register; + DT0 : aliased DT_Register; + pragma Volatile_Full_Access (DT0); -- PWM Channel Dead Time Update Register (ch_num = 0) - DTUPD0 : DTUPD_Register; + DTUPD0 : aliased DTUPD_Register; + pragma Volatile_Full_Access (DTUPD0); -- PWM Channel Mode Register (ch_num = 1) - CMR1 : CMR_Register; + CMR1 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR1); -- PWM Channel Duty Cycle Register (ch_num = 1) - CDTY1 : CDTY_Register; + CDTY1 : aliased CDTY_Register; + pragma Volatile_Full_Access (CDTY1); -- PWM Channel Duty Cycle Update Register (ch_num = 1) - CDTYUPD1 : CDTYUPD_Register; + CDTYUPD1 : aliased CDTYUPD_Register; + pragma Volatile_Full_Access (CDTYUPD1); -- PWM Channel Period Register (ch_num = 1) - CPRD1 : CPRD_Register; + CPRD1 : aliased CPRD_Register; + pragma Volatile_Full_Access (CPRD1); -- PWM Channel Period Update Register (ch_num = 1) - CPRDUPD1 : CPRDUPD_Register; + CPRDUPD1 : aliased CPRDUPD_Register; + pragma Volatile_Full_Access (CPRDUPD1); -- PWM Channel Counter Register (ch_num = 1) - CCNT1 : CCNT_Register; + CCNT1 : aliased CCNT_Register; + pragma Volatile_Full_Access (CCNT1); -- PWM Channel Dead Time Register (ch_num = 1) - DT1 : DT_Register; + DT1 : aliased DT_Register; + pragma Volatile_Full_Access (DT1); -- PWM Channel Dead Time Update Register (ch_num = 1) - DTUPD1 : DTUPD_Register; + DTUPD1 : aliased DTUPD_Register; + pragma Volatile_Full_Access (DTUPD1); -- PWM Channel Mode Register (ch_num = 2) - CMR2 : CMR_Register; + CMR2 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR2); -- PWM Channel Duty Cycle Register (ch_num = 2) - CDTY2 : CDTY_Register; + CDTY2 : aliased CDTY_Register; + pragma Volatile_Full_Access (CDTY2); -- PWM Channel Duty Cycle Update Register (ch_num = 2) - CDTYUPD2 : CDTYUPD_Register; + CDTYUPD2 : aliased CDTYUPD_Register; + pragma Volatile_Full_Access (CDTYUPD2); -- PWM Channel Period Register (ch_num = 2) - CPRD2 : CPRD_Register; + CPRD2 : aliased CPRD_Register; + pragma Volatile_Full_Access (CPRD2); -- PWM Channel Period Update Register (ch_num = 2) - CPRDUPD2 : CPRDUPD_Register; + CPRDUPD2 : aliased CPRDUPD_Register; + pragma Volatile_Full_Access (CPRDUPD2); -- PWM Channel Counter Register (ch_num = 2) - CCNT2 : CCNT_Register; + CCNT2 : aliased CCNT_Register; + pragma Volatile_Full_Access (CCNT2); -- PWM Channel Dead Time Register (ch_num = 2) - DT2 : DT_Register; + DT2 : aliased DT_Register; + pragma Volatile_Full_Access (DT2); -- PWM Channel Dead Time Update Register (ch_num = 2) - DTUPD2 : DTUPD_Register; + DTUPD2 : aliased DTUPD_Register; + pragma Volatile_Full_Access (DTUPD2); -- PWM Channel Mode Register (ch_num = 3) - CMR3 : CMR_Register; + CMR3 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR3); -- PWM Channel Duty Cycle Register (ch_num = 3) - CDTY3 : CDTY_Register; + CDTY3 : aliased CDTY_Register; + pragma Volatile_Full_Access (CDTY3); -- PWM Channel Duty Cycle Update Register (ch_num = 3) - CDTYUPD3 : CDTYUPD_Register; + CDTYUPD3 : aliased CDTYUPD_Register; + pragma Volatile_Full_Access (CDTYUPD3); -- PWM Channel Period Register (ch_num = 3) - CPRD3 : CPRD_Register; + CPRD3 : aliased CPRD_Register; + pragma Volatile_Full_Access (CPRD3); -- PWM Channel Period Update Register (ch_num = 3) - CPRDUPD3 : CPRDUPD_Register; + CPRDUPD3 : aliased CPRDUPD_Register; + pragma Volatile_Full_Access (CPRDUPD3); -- PWM Channel Counter Register (ch_num = 3) - CCNT3 : CCNT_Register; + CCNT3 : aliased CCNT_Register; + pragma Volatile_Full_Access (CCNT3); -- PWM Channel Dead Time Register (ch_num = 3) - DT3 : DT_Register; + DT3 : aliased DT_Register; + pragma Volatile_Full_Access (DT3); -- PWM Channel Dead Time Update Register (ch_num = 3) - DTUPD3 : DTUPD_Register; + DTUPD3 : aliased DTUPD_Register; + pragma Volatile_Full_Access (DTUPD3); -- PWM Channel Mode Register (ch_num = 4) - CMR4 : CMR_Register; + CMR4 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR4); -- PWM Channel Duty Cycle Register (ch_num = 4) - CDTY4 : CDTY_Register; + CDTY4 : aliased CDTY_Register; + pragma Volatile_Full_Access (CDTY4); -- PWM Channel Duty Cycle Update Register (ch_num = 4) - CDTYUPD4 : CDTYUPD_Register; + CDTYUPD4 : aliased CDTYUPD_Register; + pragma Volatile_Full_Access (CDTYUPD4); -- PWM Channel Period Register (ch_num = 4) - CPRD4 : CPRD_Register; + CPRD4 : aliased CPRD_Register; + pragma Volatile_Full_Access (CPRD4); -- PWM Channel Period Update Register (ch_num = 4) - CPRDUPD4 : CPRDUPD_Register; + CPRDUPD4 : aliased CPRDUPD_Register; + pragma Volatile_Full_Access (CPRDUPD4); -- PWM Channel Counter Register (ch_num = 4) - CCNT4 : CCNT_Register; + CCNT4 : aliased CCNT_Register; + pragma Volatile_Full_Access (CCNT4); -- PWM Channel Dead Time Register (ch_num = 4) - DT4 : DT_Register; + DT4 : aliased DT_Register; + pragma Volatile_Full_Access (DT4); -- PWM Channel Dead Time Update Register (ch_num = 4) - DTUPD4 : DTUPD_Register; + DTUPD4 : aliased DTUPD_Register; + pragma Volatile_Full_Access (DTUPD4); -- PWM Channel Mode Register (ch_num = 5) - CMR5 : CMR_Register; + CMR5 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR5); -- PWM Channel Duty Cycle Register (ch_num = 5) - CDTY5 : CDTY_Register; + CDTY5 : aliased CDTY_Register; + pragma Volatile_Full_Access (CDTY5); -- PWM Channel Duty Cycle Update Register (ch_num = 5) - CDTYUPD5 : CDTYUPD_Register; + CDTYUPD5 : aliased CDTYUPD_Register; + pragma Volatile_Full_Access (CDTYUPD5); -- PWM Channel Period Register (ch_num = 5) - CPRD5 : CPRD_Register; + CPRD5 : aliased CPRD_Register; + pragma Volatile_Full_Access (CPRD5); -- PWM Channel Period Update Register (ch_num = 5) - CPRDUPD5 : CPRDUPD_Register; + CPRDUPD5 : aliased CPRDUPD_Register; + pragma Volatile_Full_Access (CPRDUPD5); -- PWM Channel Counter Register (ch_num = 5) - CCNT5 : CCNT_Register; + CCNT5 : aliased CCNT_Register; + pragma Volatile_Full_Access (CCNT5); -- PWM Channel Dead Time Register (ch_num = 5) - DT5 : DT_Register; + DT5 : aliased DT_Register; + pragma Volatile_Full_Access (DT5); -- PWM Channel Dead Time Update Register (ch_num = 5) - DTUPD5 : DTUPD_Register; + DTUPD5 : aliased DTUPD_Register; + pragma Volatile_Full_Access (DTUPD5); -- PWM Channel Mode Register (ch_num = 6) - CMR6 : CMR_Register; + CMR6 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR6); -- PWM Channel Duty Cycle Register (ch_num = 6) - CDTY6 : CDTY_Register; + CDTY6 : aliased CDTY_Register; + pragma Volatile_Full_Access (CDTY6); -- PWM Channel Duty Cycle Update Register (ch_num = 6) - CDTYUPD6 : CDTYUPD_Register; + CDTYUPD6 : aliased CDTYUPD_Register; + pragma Volatile_Full_Access (CDTYUPD6); -- PWM Channel Period Register (ch_num = 6) - CPRD6 : CPRD_Register; + CPRD6 : aliased CPRD_Register; + pragma Volatile_Full_Access (CPRD6); -- PWM Channel Period Update Register (ch_num = 6) - CPRDUPD6 : CPRDUPD_Register; + CPRDUPD6 : aliased CPRDUPD_Register; + pragma Volatile_Full_Access (CPRDUPD6); -- PWM Channel Counter Register (ch_num = 6) - CCNT6 : CCNT_Register; + CCNT6 : aliased CCNT_Register; + pragma Volatile_Full_Access (CCNT6); -- PWM Channel Dead Time Register (ch_num = 6) - DT6 : DT_Register; + DT6 : aliased DT_Register; + pragma Volatile_Full_Access (DT6); -- PWM Channel Dead Time Update Register (ch_num = 6) - DTUPD6 : DTUPD_Register; + DTUPD6 : aliased DTUPD_Register; + pragma Volatile_Full_Access (DTUPD6); -- PWM Channel Mode Register (ch_num = 7) - CMR7 : CMR_Register; + CMR7 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR7); -- PWM Channel Duty Cycle Register (ch_num = 7) - CDTY7 : CDTY_Register; + CDTY7 : aliased CDTY_Register; + pragma Volatile_Full_Access (CDTY7); -- PWM Channel Duty Cycle Update Register (ch_num = 7) - CDTYUPD7 : CDTYUPD_Register; + CDTYUPD7 : aliased CDTYUPD_Register; + pragma Volatile_Full_Access (CDTYUPD7); -- PWM Channel Period Register (ch_num = 7) - CPRD7 : CPRD_Register; + CPRD7 : aliased CPRD_Register; + pragma Volatile_Full_Access (CPRD7); -- PWM Channel Period Update Register (ch_num = 7) - CPRDUPD7 : CPRDUPD_Register; + CPRDUPD7 : aliased CPRDUPD_Register; + pragma Volatile_Full_Access (CPRDUPD7); -- PWM Channel Counter Register (ch_num = 7) - CCNT7 : CCNT_Register; + CCNT7 : aliased CCNT_Register; + pragma Volatile_Full_Access (CCNT7); -- PWM Channel Dead Time Register (ch_num = 7) - DT7 : DT_Register; + DT7 : aliased DT_Register; + pragma Volatile_Full_Access (DT7); -- PWM Channel Dead Time Update Register (ch_num = 7) - DTUPD7 : DTUPD_Register; + DTUPD7 : aliased DTUPD_Register; + pragma Volatile_Full_Access (DTUPD7); end record with Volatile; for PWM_Peripheral use record - CLK at 0 range 0 .. 31; - ENA at 4 range 0 .. 31; - DIS at 8 range 0 .. 31; - SR at 12 range 0 .. 31; - IER1 at 16 range 0 .. 31; - IDR1 at 20 range 0 .. 31; - IMR1 at 24 range 0 .. 31; - ISR1 at 28 range 0 .. 31; - SCM at 32 range 0 .. 31; - SCUC at 40 range 0 .. 31; - SCUP at 44 range 0 .. 31; - SCUPUPD at 48 range 0 .. 31; - IER2 at 52 range 0 .. 31; - IDR2 at 56 range 0 .. 31; - IMR2 at 60 range 0 .. 31; - ISR2 at 64 range 0 .. 31; - OOV at 68 range 0 .. 31; - OS at 72 range 0 .. 31; - OSS at 76 range 0 .. 31; - OSC at 80 range 0 .. 31; - OSSUPD at 84 range 0 .. 31; - OSCUPD at 88 range 0 .. 31; - FMR at 92 range 0 .. 31; - FSR at 96 range 0 .. 31; - FCR at 100 range 0 .. 31; - FPV at 104 range 0 .. 31; - FPE1 at 108 range 0 .. 31; - FPE2 at 112 range 0 .. 31; - ELMR at 124 range 0 .. 63; - SMMR at 176 range 0 .. 31; - WPCR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; - TPR at 264 range 0 .. 31; - TCR at 268 range 0 .. 31; - TNPR at 280 range 0 .. 31; - TNCR at 284 range 0 .. 31; - PTCR at 288 range 0 .. 31; - PTSR at 292 range 0 .. 31; - CMPV0 at 304 range 0 .. 31; - CMPVUPD0 at 308 range 0 .. 31; - CMPM0 at 312 range 0 .. 31; - CMPMUPD0 at 316 range 0 .. 31; - CMPV1 at 320 range 0 .. 31; - CMPVUPD1 at 324 range 0 .. 31; - CMPM1 at 328 range 0 .. 31; - CMPMUPD1 at 332 range 0 .. 31; - CMPV2 at 336 range 0 .. 31; - CMPVUPD2 at 340 range 0 .. 31; - CMPM2 at 344 range 0 .. 31; - CMPMUPD2 at 348 range 0 .. 31; - CMPV3 at 352 range 0 .. 31; - CMPVUPD3 at 356 range 0 .. 31; - CMPM3 at 360 range 0 .. 31; - CMPMUPD3 at 364 range 0 .. 31; - CMPV4 at 368 range 0 .. 31; - CMPVUPD4 at 372 range 0 .. 31; - CMPM4 at 376 range 0 .. 31; - CMPMUPD4 at 380 range 0 .. 31; - CMPV5 at 384 range 0 .. 31; - CMPVUPD5 at 388 range 0 .. 31; - CMPM5 at 392 range 0 .. 31; - CMPMUPD5 at 396 range 0 .. 31; - CMPV6 at 400 range 0 .. 31; - CMPVUPD6 at 404 range 0 .. 31; - CMPM6 at 408 range 0 .. 31; - CMPMUPD6 at 412 range 0 .. 31; - CMPV7 at 416 range 0 .. 31; - CMPVUPD7 at 420 range 0 .. 31; - CMPM7 at 424 range 0 .. 31; - CMPMUPD7 at 428 range 0 .. 31; - CMR0 at 512 range 0 .. 31; - CDTY0 at 516 range 0 .. 31; - CDTYUPD0 at 520 range 0 .. 31; - CPRD0 at 524 range 0 .. 31; - CPRDUPD0 at 528 range 0 .. 31; - CCNT0 at 532 range 0 .. 31; - DT0 at 536 range 0 .. 31; - DTUPD0 at 540 range 0 .. 31; - CMR1 at 544 range 0 .. 31; - CDTY1 at 548 range 0 .. 31; - CDTYUPD1 at 552 range 0 .. 31; - CPRD1 at 556 range 0 .. 31; - CPRDUPD1 at 560 range 0 .. 31; - CCNT1 at 564 range 0 .. 31; - DT1 at 568 range 0 .. 31; - DTUPD1 at 572 range 0 .. 31; - CMR2 at 576 range 0 .. 31; - CDTY2 at 580 range 0 .. 31; - CDTYUPD2 at 584 range 0 .. 31; - CPRD2 at 588 range 0 .. 31; - CPRDUPD2 at 592 range 0 .. 31; - CCNT2 at 596 range 0 .. 31; - DT2 at 600 range 0 .. 31; - DTUPD2 at 604 range 0 .. 31; - CMR3 at 608 range 0 .. 31; - CDTY3 at 612 range 0 .. 31; - CDTYUPD3 at 616 range 0 .. 31; - CPRD3 at 620 range 0 .. 31; - CPRDUPD3 at 624 range 0 .. 31; - CCNT3 at 628 range 0 .. 31; - DT3 at 632 range 0 .. 31; - DTUPD3 at 636 range 0 .. 31; - CMR4 at 640 range 0 .. 31; - CDTY4 at 644 range 0 .. 31; - CDTYUPD4 at 648 range 0 .. 31; - CPRD4 at 652 range 0 .. 31; - CPRDUPD4 at 656 range 0 .. 31; - CCNT4 at 660 range 0 .. 31; - DT4 at 664 range 0 .. 31; - DTUPD4 at 668 range 0 .. 31; - CMR5 at 672 range 0 .. 31; - CDTY5 at 676 range 0 .. 31; - CDTYUPD5 at 680 range 0 .. 31; - CPRD5 at 684 range 0 .. 31; - CPRDUPD5 at 688 range 0 .. 31; - CCNT5 at 692 range 0 .. 31; - DT5 at 696 range 0 .. 31; - DTUPD5 at 700 range 0 .. 31; - CMR6 at 704 range 0 .. 31; - CDTY6 at 708 range 0 .. 31; - CDTYUPD6 at 712 range 0 .. 31; - CPRD6 at 716 range 0 .. 31; - CPRDUPD6 at 720 range 0 .. 31; - CCNT6 at 724 range 0 .. 31; - DT6 at 728 range 0 .. 31; - DTUPD6 at 732 range 0 .. 31; - CMR7 at 736 range 0 .. 31; - CDTY7 at 740 range 0 .. 31; - CDTYUPD7 at 744 range 0 .. 31; - CPRD7 at 748 range 0 .. 31; - CPRDUPD7 at 752 range 0 .. 31; - CCNT7 at 756 range 0 .. 31; - DT7 at 760 range 0 .. 31; - DTUPD7 at 764 range 0 .. 31; + CLK at 16#0# range 0 .. 31; + ENA at 16#4# range 0 .. 31; + DIS at 16#8# range 0 .. 31; + SR at 16#C# range 0 .. 31; + IER1 at 16#10# range 0 .. 31; + IDR1 at 16#14# range 0 .. 31; + IMR1 at 16#18# range 0 .. 31; + ISR1 at 16#1C# range 0 .. 31; + SCM at 16#20# range 0 .. 31; + SCUC at 16#28# range 0 .. 31; + SCUP at 16#2C# range 0 .. 31; + SCUPUPD at 16#30# range 0 .. 31; + IER2 at 16#34# range 0 .. 31; + IDR2 at 16#38# range 0 .. 31; + IMR2 at 16#3C# range 0 .. 31; + ISR2 at 16#40# range 0 .. 31; + OOV at 16#44# range 0 .. 31; + OS at 16#48# range 0 .. 31; + OSS at 16#4C# range 0 .. 31; + OSC at 16#50# range 0 .. 31; + OSSUPD at 16#54# range 0 .. 31; + OSCUPD at 16#58# range 0 .. 31; + FMR at 16#5C# range 0 .. 31; + FSR at 16#60# range 0 .. 31; + FCR at 16#64# range 0 .. 31; + FPV at 16#68# range 0 .. 31; + FPE1 at 16#6C# range 0 .. 31; + FPE2 at 16#70# range 0 .. 31; + ELMR_0 at 16#7C# range 0 .. 31; + ELMR_1 at 16#80# range 0 .. 31; + SMMR at 16#B0# range 0 .. 31; + WPCR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; + TPR at 16#108# range 0 .. 31; + TCR at 16#10C# range 0 .. 31; + TNPR at 16#118# range 0 .. 31; + TNCR at 16#11C# range 0 .. 31; + PTCR at 16#120# range 0 .. 31; + PTSR at 16#124# range 0 .. 31; + CMPV0 at 16#130# range 0 .. 31; + CMPVUPD0 at 16#134# range 0 .. 31; + CMPM0 at 16#138# range 0 .. 31; + CMPMUPD0 at 16#13C# range 0 .. 31; + CMPV1 at 16#140# range 0 .. 31; + CMPVUPD1 at 16#144# range 0 .. 31; + CMPM1 at 16#148# range 0 .. 31; + CMPMUPD1 at 16#14C# range 0 .. 31; + CMPV2 at 16#150# range 0 .. 31; + CMPVUPD2 at 16#154# range 0 .. 31; + CMPM2 at 16#158# range 0 .. 31; + CMPMUPD2 at 16#15C# range 0 .. 31; + CMPV3 at 16#160# range 0 .. 31; + CMPVUPD3 at 16#164# range 0 .. 31; + CMPM3 at 16#168# range 0 .. 31; + CMPMUPD3 at 16#16C# range 0 .. 31; + CMPV4 at 16#170# range 0 .. 31; + CMPVUPD4 at 16#174# range 0 .. 31; + CMPM4 at 16#178# range 0 .. 31; + CMPMUPD4 at 16#17C# range 0 .. 31; + CMPV5 at 16#180# range 0 .. 31; + CMPVUPD5 at 16#184# range 0 .. 31; + CMPM5 at 16#188# range 0 .. 31; + CMPMUPD5 at 16#18C# range 0 .. 31; + CMPV6 at 16#190# range 0 .. 31; + CMPVUPD6 at 16#194# range 0 .. 31; + CMPM6 at 16#198# range 0 .. 31; + CMPMUPD6 at 16#19C# range 0 .. 31; + CMPV7 at 16#1A0# range 0 .. 31; + CMPVUPD7 at 16#1A4# range 0 .. 31; + CMPM7 at 16#1A8# range 0 .. 31; + CMPMUPD7 at 16#1AC# range 0 .. 31; + CMR0 at 16#200# range 0 .. 31; + CDTY0 at 16#204# range 0 .. 31; + CDTYUPD0 at 16#208# range 0 .. 31; + CPRD0 at 16#20C# range 0 .. 31; + CPRDUPD0 at 16#210# range 0 .. 31; + CCNT0 at 16#214# range 0 .. 31; + DT0 at 16#218# range 0 .. 31; + DTUPD0 at 16#21C# range 0 .. 31; + CMR1 at 16#220# range 0 .. 31; + CDTY1 at 16#224# range 0 .. 31; + CDTYUPD1 at 16#228# range 0 .. 31; + CPRD1 at 16#22C# range 0 .. 31; + CPRDUPD1 at 16#230# range 0 .. 31; + CCNT1 at 16#234# range 0 .. 31; + DT1 at 16#238# range 0 .. 31; + DTUPD1 at 16#23C# range 0 .. 31; + CMR2 at 16#240# range 0 .. 31; + CDTY2 at 16#244# range 0 .. 31; + CDTYUPD2 at 16#248# range 0 .. 31; + CPRD2 at 16#24C# range 0 .. 31; + CPRDUPD2 at 16#250# range 0 .. 31; + CCNT2 at 16#254# range 0 .. 31; + DT2 at 16#258# range 0 .. 31; + DTUPD2 at 16#25C# range 0 .. 31; + CMR3 at 16#260# range 0 .. 31; + CDTY3 at 16#264# range 0 .. 31; + CDTYUPD3 at 16#268# range 0 .. 31; + CPRD3 at 16#26C# range 0 .. 31; + CPRDUPD3 at 16#270# range 0 .. 31; + CCNT3 at 16#274# range 0 .. 31; + DT3 at 16#278# range 0 .. 31; + DTUPD3 at 16#27C# range 0 .. 31; + CMR4 at 16#280# range 0 .. 31; + CDTY4 at 16#284# range 0 .. 31; + CDTYUPD4 at 16#288# range 0 .. 31; + CPRD4 at 16#28C# range 0 .. 31; + CPRDUPD4 at 16#290# range 0 .. 31; + CCNT4 at 16#294# range 0 .. 31; + DT4 at 16#298# range 0 .. 31; + DTUPD4 at 16#29C# range 0 .. 31; + CMR5 at 16#2A0# range 0 .. 31; + CDTY5 at 16#2A4# range 0 .. 31; + CDTYUPD5 at 16#2A8# range 0 .. 31; + CPRD5 at 16#2AC# range 0 .. 31; + CPRDUPD5 at 16#2B0# range 0 .. 31; + CCNT5 at 16#2B4# range 0 .. 31; + DT5 at 16#2B8# range 0 .. 31; + DTUPD5 at 16#2BC# range 0 .. 31; + CMR6 at 16#2C0# range 0 .. 31; + CDTY6 at 16#2C4# range 0 .. 31; + CDTYUPD6 at 16#2C8# range 0 .. 31; + CPRD6 at 16#2CC# range 0 .. 31; + CPRDUPD6 at 16#2D0# range 0 .. 31; + CCNT6 at 16#2D4# range 0 .. 31; + DT6 at 16#2D8# range 0 .. 31; + DTUPD6 at 16#2DC# range 0 .. 31; + CMR7 at 16#2E0# range 0 .. 31; + CDTY7 at 16#2E4# range 0 .. 31; + CDTYUPD7 at 16#2E8# range 0 .. 31; + CPRD7 at 16#2EC# range 0 .. 31; + CPRDUPD7 at 16#2F0# range 0 .. 31; + CCNT7 at 16#2F4# range 0 .. 31; + DT7 at 16#2F8# range 0 .. 31; + DTUPD7 at 16#2FC# range 0 .. 31; end record; -- Pulse Width Modulation Controller diff --git a/arduino-due/atsam3x8e/atsam3x8e-spi.ads b/arduino-due/atsam3x8e/atsam3x8e-spi.ads index 37b83ef..d362bb0 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-spi.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-spi.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,35 +14,31 @@ package ATSAM3X8E.SPI is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_SPIEN_Field is ATSAM3X8E.Bit; - subtype CR_SPIDIS_Field is ATSAM3X8E.Bit; - subtype CR_SWRST_Field is ATSAM3X8E.Bit; - subtype CR_LASTXFER_Field is ATSAM3X8E.Bit; + subtype SPI0_CR_SPIEN_Field is ATSAM3X8E.Bit; + subtype SPI0_CR_SPIDIS_Field is ATSAM3X8E.Bit; + subtype SPI0_CR_SWRST_Field is ATSAM3X8E.Bit; + subtype SPI0_CR_LASTXFER_Field is ATSAM3X8E.Bit; -- Control Register - type CR_Register is record + type SPI0_CR_Register is record -- Write-only. SPI Enable - SPIEN : CR_SPIEN_Field := 16#0#; + SPIEN : SPI0_CR_SPIEN_Field := 16#0#; -- Write-only. SPI Disable - SPIDIS : CR_SPIDIS_Field := 16#0#; + SPIDIS : SPI0_CR_SPIDIS_Field := 16#0#; -- unspecified Reserved_2_6 : ATSAM3X8E.UInt5 := 16#0#; -- Write-only. SPI Software Reset - SWRST : CR_SWRST_Field := 16#0#; + SWRST : SPI0_CR_SWRST_Field := 16#0#; -- unspecified - Reserved_8_23 : ATSAM3X8E.Short := 16#0#; + Reserved_8_23 : ATSAM3X8E.UInt16 := 16#0#; -- Write-only. Last Transfer - LASTXFER : CR_LASTXFER_Field := 16#0#; + LASTXFER : SPI0_CR_LASTXFER_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for SPI0_CR_Register use record SPIEN at 0 range 0 .. 0; SPIDIS at 0 range 1 .. 1; Reserved_2_6 at 0 range 2 .. 6; @@ -51,49 +48,45 @@ package ATSAM3X8E.SPI is Reserved_25_31 at 0 range 25 .. 31; end record; - ----------------- - -- MR_Register -- - ----------------- - - subtype MR_MSTR_Field is ATSAM3X8E.Bit; - subtype MR_PS_Field is ATSAM3X8E.Bit; - subtype MR_PCSDEC_Field is ATSAM3X8E.Bit; - subtype MR_MODFDIS_Field is ATSAM3X8E.Bit; - subtype MR_WDRBT_Field is ATSAM3X8E.Bit; - subtype MR_LLB_Field is ATSAM3X8E.Bit; - subtype MR_PCS_Field is ATSAM3X8E.UInt4; - subtype MR_DLYBCS_Field is ATSAM3X8E.Byte; + subtype SPI0_MR_MSTR_Field is ATSAM3X8E.Bit; + subtype SPI0_MR_PS_Field is ATSAM3X8E.Bit; + subtype SPI0_MR_PCSDEC_Field is ATSAM3X8E.Bit; + subtype SPI0_MR_MODFDIS_Field is ATSAM3X8E.Bit; + subtype SPI0_MR_WDRBT_Field is ATSAM3X8E.Bit; + subtype SPI0_MR_LLB_Field is ATSAM3X8E.Bit; + subtype SPI0_MR_PCS_Field is ATSAM3X8E.UInt4; + subtype SPI0_MR_DLYBCS_Field is ATSAM3X8E.Byte; -- Mode Register - type MR_Register is record + type SPI0_MR_Register is record -- Master/Slave Mode - MSTR : MR_MSTR_Field := 16#0#; + MSTR : SPI0_MR_MSTR_Field := 16#0#; -- Peripheral Select - PS : MR_PS_Field := 16#0#; + PS : SPI0_MR_PS_Field := 16#0#; -- Chip Select Decode - PCSDEC : MR_PCSDEC_Field := 16#0#; + PCSDEC : SPI0_MR_PCSDEC_Field := 16#0#; -- unspecified Reserved_3_3 : ATSAM3X8E.Bit := 16#0#; -- Mode Fault Detection - MODFDIS : MR_MODFDIS_Field := 16#0#; + MODFDIS : SPI0_MR_MODFDIS_Field := 16#0#; -- Wait Data Read Before Transfer - WDRBT : MR_WDRBT_Field := 16#0#; + WDRBT : SPI0_MR_WDRBT_Field := 16#0#; -- unspecified Reserved_6_6 : ATSAM3X8E.Bit := 16#0#; -- Local Loopback Enable - LLB : MR_LLB_Field := 16#0#; + LLB : SPI0_MR_LLB_Field := 16#0#; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Peripheral Chip Select - PCS : MR_PCS_Field := 16#0#; + PCS : SPI0_MR_PCS_Field := 16#0#; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4 := 16#0#; -- Delay Between Chip Selects - DLYBCS : MR_DLYBCS_Field := 16#0#; + DLYBCS : SPI0_MR_DLYBCS_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_Register use record + for SPI0_MR_Register use record MSTR at 0 range 0 .. 0; PS at 0 range 1 .. 1; PCSDEC at 0 range 2 .. 2; @@ -108,54 +101,46 @@ package ATSAM3X8E.SPI is DLYBCS at 0 range 24 .. 31; end record; - ------------------ - -- RDR_Register -- - ------------------ - - subtype RDR_RD_Field is ATSAM3X8E.Short; - subtype RDR_PCS_Field is ATSAM3X8E.UInt4; + subtype SPI0_RDR_RD_Field is ATSAM3X8E.UInt16; + subtype SPI0_RDR_PCS_Field is ATSAM3X8E.UInt4; -- Receive Data Register - type RDR_Register is record + type SPI0_RDR_Register is record -- Read-only. Receive Data - RD : RDR_RD_Field := 16#0#; + RD : SPI0_RDR_RD_Field; -- Read-only. Peripheral Chip Select - PCS : RDR_PCS_Field := 16#0#; + PCS : SPI0_RDR_PCS_Field; -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RDR_Register use record + for SPI0_RDR_Register use record RD at 0 range 0 .. 15; PCS at 0 range 16 .. 19; Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------ - -- TDR_Register -- - ------------------ - - subtype TDR_TD_Field is ATSAM3X8E.Short; - subtype TDR_PCS_Field is ATSAM3X8E.UInt4; - subtype TDR_LASTXFER_Field is ATSAM3X8E.Bit; + subtype SPI0_TDR_TD_Field is ATSAM3X8E.UInt16; + subtype SPI0_TDR_PCS_Field is ATSAM3X8E.UInt4; + subtype SPI0_TDR_LASTXFER_Field is ATSAM3X8E.Bit; -- Transmit Data Register - type TDR_Register is record + type SPI0_TDR_Register is record -- Write-only. Transmit Data - TD : TDR_TD_Field := 16#0#; + TD : SPI0_TDR_TD_Field := 16#0#; -- Write-only. Peripheral Chip Select - PCS : TDR_PCS_Field := 16#0#; + PCS : SPI0_TDR_PCS_Field := 16#0#; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Last Transfer - LASTXFER : TDR_LASTXFER_Field := 16#0#; + LASTXFER : SPI0_TDR_LASTXFER_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TDR_Register use record + for SPI0_TDR_Register use record TD at 0 range 0 .. 15; PCS at 0 range 16 .. 19; Reserved_20_23 at 0 range 20 .. 23; @@ -163,47 +148,43 @@ package ATSAM3X8E.SPI is Reserved_25_31 at 0 range 25 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_RDRF_Field is ATSAM3X8E.Bit; - subtype SR_TDRE_Field is ATSAM3X8E.Bit; - subtype SR_MODF_Field is ATSAM3X8E.Bit; - subtype SR_OVRES_Field is ATSAM3X8E.Bit; - subtype SR_NSSR_Field is ATSAM3X8E.Bit; - subtype SR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype SR_UNDES_Field is ATSAM3X8E.Bit; - subtype SR_SPIENS_Field is ATSAM3X8E.Bit; + subtype SPI0_SR_RDRF_Field is ATSAM3X8E.Bit; + subtype SPI0_SR_TDRE_Field is ATSAM3X8E.Bit; + subtype SPI0_SR_MODF_Field is ATSAM3X8E.Bit; + subtype SPI0_SR_OVRES_Field is ATSAM3X8E.Bit; + subtype SPI0_SR_NSSR_Field is ATSAM3X8E.Bit; + subtype SPI0_SR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype SPI0_SR_UNDES_Field is ATSAM3X8E.Bit; + subtype SPI0_SR_SPIENS_Field is ATSAM3X8E.Bit; -- Status Register - type SR_Register is record + type SPI0_SR_Register is record -- Read-only. Receive Data Register Full - RDRF : SR_RDRF_Field := 16#0#; + RDRF : SPI0_SR_RDRF_Field; -- Read-only. Transmit Data Register Empty - TDRE : SR_TDRE_Field := 16#0#; + TDRE : SPI0_SR_TDRE_Field; -- Read-only. Mode Fault Error - MODF : SR_MODF_Field := 16#0#; + MODF : SPI0_SR_MODF_Field; -- Read-only. Overrun Error Status - OVRES : SR_OVRES_Field := 16#0#; + OVRES : SPI0_SR_OVRES_Field; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4; -- Read-only. NSS Rising - NSSR : SR_NSSR_Field := 16#0#; + NSSR : SPI0_SR_NSSR_Field; -- Read-only. Transmission Registers Empty - TXEMPTY : SR_TXEMPTY_Field := 16#0#; + TXEMPTY : SPI0_SR_TXEMPTY_Field; -- Read-only. Underrun Error Status (Slave Mode Only) - UNDES : SR_UNDES_Field := 16#0#; + UNDES : SPI0_SR_UNDES_Field; -- unspecified Reserved_11_15 : ATSAM3X8E.UInt5; -- Read-only. SPI Enable Status - SPIENS : SR_SPIENS_Field := 16#0#; + SPIENS : SPI0_SR_SPIENS_Field; -- unspecified Reserved_17_31 : ATSAM3X8E.UInt15; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for SPI0_SR_Register use record RDRF at 0 range 0 .. 0; TDRE at 0 range 1 .. 1; MODF at 0 range 2 .. 2; @@ -217,42 +198,38 @@ package ATSAM3X8E.SPI is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_RDRF_Field is ATSAM3X8E.Bit; - subtype IER_TDRE_Field is ATSAM3X8E.Bit; - subtype IER_MODF_Field is ATSAM3X8E.Bit; - subtype IER_OVRES_Field is ATSAM3X8E.Bit; - subtype IER_NSSR_Field is ATSAM3X8E.Bit; - subtype IER_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IER_UNDES_Field is ATSAM3X8E.Bit; + subtype SPI0_IER_RDRF_Field is ATSAM3X8E.Bit; + subtype SPI0_IER_TDRE_Field is ATSAM3X8E.Bit; + subtype SPI0_IER_MODF_Field is ATSAM3X8E.Bit; + subtype SPI0_IER_OVRES_Field is ATSAM3X8E.Bit; + subtype SPI0_IER_NSSR_Field is ATSAM3X8E.Bit; + subtype SPI0_IER_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype SPI0_IER_UNDES_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type SPI0_IER_Register is record -- Write-only. Receive Data Register Full Interrupt Enable - RDRF : IER_RDRF_Field := 16#0#; + RDRF : SPI0_IER_RDRF_Field := 16#0#; -- Write-only. SPI Transmit Data Register Empty Interrupt Enable - TDRE : IER_TDRE_Field := 16#0#; + TDRE : SPI0_IER_TDRE_Field := 16#0#; -- Write-only. Mode Fault Error Interrupt Enable - MODF : IER_MODF_Field := 16#0#; + MODF : SPI0_IER_MODF_Field := 16#0#; -- Write-only. Overrun Error Interrupt Enable - OVRES : IER_OVRES_Field := 16#0#; + OVRES : SPI0_IER_OVRES_Field := 16#0#; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. NSS Rising Interrupt Enable - NSSR : IER_NSSR_Field := 16#0#; + NSSR : SPI0_IER_NSSR_Field := 16#0#; -- Write-only. Transmission Registers Empty Enable - TXEMPTY : IER_TXEMPTY_Field := 16#0#; + TXEMPTY : SPI0_IER_TXEMPTY_Field := 16#0#; -- Write-only. Underrun Error Interrupt Enable - UNDES : IER_UNDES_Field := 16#0#; + UNDES : SPI0_IER_UNDES_Field := 16#0#; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for SPI0_IER_Register use record RDRF at 0 range 0 .. 0; TDRE at 0 range 1 .. 1; MODF at 0 range 2 .. 2; @@ -264,42 +241,38 @@ package ATSAM3X8E.SPI is Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_RDRF_Field is ATSAM3X8E.Bit; - subtype IDR_TDRE_Field is ATSAM3X8E.Bit; - subtype IDR_MODF_Field is ATSAM3X8E.Bit; - subtype IDR_OVRES_Field is ATSAM3X8E.Bit; - subtype IDR_NSSR_Field is ATSAM3X8E.Bit; - subtype IDR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IDR_UNDES_Field is ATSAM3X8E.Bit; + subtype SPI0_IDR_RDRF_Field is ATSAM3X8E.Bit; + subtype SPI0_IDR_TDRE_Field is ATSAM3X8E.Bit; + subtype SPI0_IDR_MODF_Field is ATSAM3X8E.Bit; + subtype SPI0_IDR_OVRES_Field is ATSAM3X8E.Bit; + subtype SPI0_IDR_NSSR_Field is ATSAM3X8E.Bit; + subtype SPI0_IDR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype SPI0_IDR_UNDES_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type SPI0_IDR_Register is record -- Write-only. Receive Data Register Full Interrupt Disable - RDRF : IDR_RDRF_Field := 16#0#; + RDRF : SPI0_IDR_RDRF_Field := 16#0#; -- Write-only. SPI Transmit Data Register Empty Interrupt Disable - TDRE : IDR_TDRE_Field := 16#0#; + TDRE : SPI0_IDR_TDRE_Field := 16#0#; -- Write-only. Mode Fault Error Interrupt Disable - MODF : IDR_MODF_Field := 16#0#; + MODF : SPI0_IDR_MODF_Field := 16#0#; -- Write-only. Overrun Error Interrupt Disable - OVRES : IDR_OVRES_Field := 16#0#; + OVRES : SPI0_IDR_OVRES_Field := 16#0#; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. NSS Rising Interrupt Disable - NSSR : IDR_NSSR_Field := 16#0#; + NSSR : SPI0_IDR_NSSR_Field := 16#0#; -- Write-only. Transmission Registers Empty Disable - TXEMPTY : IDR_TXEMPTY_Field := 16#0#; + TXEMPTY : SPI0_IDR_TXEMPTY_Field := 16#0#; -- Write-only. Underrun Error Interrupt Disable - UNDES : IDR_UNDES_Field := 16#0#; + UNDES : SPI0_IDR_UNDES_Field := 16#0#; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for SPI0_IDR_Register use record RDRF at 0 range 0 .. 0; TDRE at 0 range 1 .. 1; MODF at 0 range 2 .. 2; @@ -311,42 +284,38 @@ package ATSAM3X8E.SPI is Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_RDRF_Field is ATSAM3X8E.Bit; - subtype IMR_TDRE_Field is ATSAM3X8E.Bit; - subtype IMR_MODF_Field is ATSAM3X8E.Bit; - subtype IMR_OVRES_Field is ATSAM3X8E.Bit; - subtype IMR_NSSR_Field is ATSAM3X8E.Bit; - subtype IMR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IMR_UNDES_Field is ATSAM3X8E.Bit; + subtype SPI0_IMR_RDRF_Field is ATSAM3X8E.Bit; + subtype SPI0_IMR_TDRE_Field is ATSAM3X8E.Bit; + subtype SPI0_IMR_MODF_Field is ATSAM3X8E.Bit; + subtype SPI0_IMR_OVRES_Field is ATSAM3X8E.Bit; + subtype SPI0_IMR_NSSR_Field is ATSAM3X8E.Bit; + subtype SPI0_IMR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype SPI0_IMR_UNDES_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type SPI0_IMR_Register is record -- Read-only. Receive Data Register Full Interrupt Mask - RDRF : IMR_RDRF_Field := 16#0#; + RDRF : SPI0_IMR_RDRF_Field; -- Read-only. SPI Transmit Data Register Empty Interrupt Mask - TDRE : IMR_TDRE_Field := 16#0#; + TDRE : SPI0_IMR_TDRE_Field; -- Read-only. Mode Fault Error Interrupt Mask - MODF : IMR_MODF_Field := 16#0#; + MODF : SPI0_IMR_MODF_Field; -- Read-only. Overrun Error Interrupt Mask - OVRES : IMR_OVRES_Field := 16#0#; + OVRES : SPI0_IMR_OVRES_Field; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4; -- Read-only. NSS Rising Interrupt Mask - NSSR : IMR_NSSR_Field := 16#0#; + NSSR : SPI0_IMR_NSSR_Field; -- Read-only. Transmission Registers Empty Mask - TXEMPTY : IMR_TXEMPTY_Field := 16#0#; + TXEMPTY : SPI0_IMR_TXEMPTY_Field; -- Read-only. Underrun Error Interrupt Mask - UNDES : IMR_UNDES_Field := 16#0#; + UNDES : SPI0_IMR_UNDES_Field; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for SPI0_IMR_Register use record RDRF at 0 range 0 .. 0; TDRE at 0 range 1 .. 1; MODF at 0 range 2 .. 2; @@ -358,74 +327,69 @@ package ATSAM3X8E.SPI is Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------ - -- CSR_Register -- - ------------------ - - subtype CSR_CPOL_Field is ATSAM3X8E.Bit; - subtype CSR_NCPHA_Field is ATSAM3X8E.Bit; - subtype CSR_CSNAAT_Field is ATSAM3X8E.Bit; - subtype CSR_CSAAT_Field is ATSAM3X8E.Bit; + subtype SPI0_CSR_CPOL_Field is ATSAM3X8E.Bit; + subtype SPI0_CSR_NCPHA_Field is ATSAM3X8E.Bit; + subtype SPI0_CSR_CSNAAT_Field is ATSAM3X8E.Bit; + subtype SPI0_CSR_CSAAT_Field is ATSAM3X8E.Bit; -- Bits Per Transfer - type BITS_Field is - ( - -- 8 bits for transfer - BITS_Field_8_Bit, + type CSR_BITS_Field is + (-- 8 bits for transfer + Val_8_Bit, -- 9 bits for transfer - BITS_Field_9_Bit, + Val_9_Bit, -- 10 bits for transfer - BITS_Field_10_Bit, + Val_10_Bit, -- 11 bits for transfer - BITS_Field_11_Bit, + Val_11_Bit, -- 12 bits for transfer - BITS_Field_12_Bit, + Val_12_Bit, -- 13 bits for transfer - BITS_Field_13_Bit, + Val_13_Bit, -- 14 bits for transfer - BITS_Field_14_Bit, + Val_14_Bit, -- 15 bits for transfer - BITS_Field_15_Bit, + Val_15_Bit, -- 16 bits for transfer - BITS_Field_16_Bit) + Val_16_Bit) with Size => 4; - for BITS_Field use - (BITS_Field_8_Bit => 0, - BITS_Field_9_Bit => 1, - BITS_Field_10_Bit => 2, - BITS_Field_11_Bit => 3, - BITS_Field_12_Bit => 4, - BITS_Field_13_Bit => 5, - BITS_Field_14_Bit => 6, - BITS_Field_15_Bit => 7, - BITS_Field_16_Bit => 8); - - subtype CSR_SCBR_Field is ATSAM3X8E.Byte; - subtype CSR_DLYBS_Field is ATSAM3X8E.Byte; - subtype CSR_DLYBCT_Field is ATSAM3X8E.Byte; + for CSR_BITS_Field use + (Val_8_Bit => 0, + Val_9_Bit => 1, + Val_10_Bit => 2, + Val_11_Bit => 3, + Val_12_Bit => 4, + Val_13_Bit => 5, + Val_14_Bit => 6, + Val_15_Bit => 7, + Val_16_Bit => 8); + + subtype SPI0_CSR_SCBR_Field is ATSAM3X8E.Byte; + subtype SPI0_CSR_DLYBS_Field is ATSAM3X8E.Byte; + subtype SPI0_CSR_DLYBCT_Field is ATSAM3X8E.Byte; -- Chip Select Register - type CSR_Register is record + type SPI0_CSR_Register is record -- Clock Polarity - CPOL : CSR_CPOL_Field := 16#0#; + CPOL : SPI0_CSR_CPOL_Field := 16#0#; -- Clock Phase - NCPHA : CSR_NCPHA_Field := 16#0#; + NCPHA : SPI0_CSR_NCPHA_Field := 16#0#; -- Chip Select Not Active After Transfer (Ignored if CSAAT = 1) - CSNAAT : CSR_CSNAAT_Field := 16#0#; + CSNAAT : SPI0_CSR_CSNAAT_Field := 16#0#; -- Chip Select Active After Transfer - CSAAT : CSR_CSAAT_Field := 16#0#; + CSAAT : SPI0_CSR_CSAAT_Field := 16#0#; -- Bits Per Transfer - BITS : BITS_Field := BITS_Field_8_Bit; + BITS : CSR_BITS_Field := ATSAM3X8E.SPI.Val_8_Bit; -- Serial Clock Baud Rate - SCBR : CSR_SCBR_Field := 16#0#; + SCBR : SPI0_CSR_SCBR_Field := 16#0#; -- Delay Before SPCK - DLYBS : CSR_DLYBS_Field := 16#0#; + DLYBS : SPI0_CSR_DLYBS_Field := 16#0#; -- Delay Between Consecutive Transfers - DLYBCT : CSR_DLYBCT_Field := 16#0#; + DLYBCT : SPI0_CSR_DLYBCT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CSR_Register use record + for SPI0_CSR_Register use record CPOL at 0 range 0 .. 0; NCPHA at 0 range 1 .. 1; CSNAAT at 0 range 2 .. 2; @@ -436,54 +400,43 @@ package ATSAM3X8E.SPI is DLYBCT at 0 range 24 .. 31; end record; - -- Chip Select Register - type CSR_Registers is array (0 .. 3) of CSR_Register; - - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype SPI0_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype SPI0_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- Write Protection Control Register - type WPMR_Register is record + type SPI0_WPMR_Register is record -- Write Protection Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : SPI0_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protection Key Password - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : SPI0_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for SPI0_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype WPSR_WPVSRC_Field is ATSAM3X8E.Byte; + subtype SPI0_WPSR_WPVS_Field is ATSAM3X8E.Bit; + subtype SPI0_WPSR_WPVSRC_Field is ATSAM3X8E.Byte; -- Write Protection Status Register - type WPSR_Register is record + type SPI0_WPSR_Register is record -- Read-only. Write Protection Violation Status - WPVS : WPSR_WPVS_Field := 16#0#; + WPVS : SPI0_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protection Violation Source - WPVSRC : WPSR_WPVSRC_Field := 16#0#; + WPVSRC : SPI0_WPSR_WPVSRC_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for SPI0_WPSR_Register use record WPVS at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPVSRC at 0 range 8 .. 15; @@ -497,42 +450,65 @@ package ATSAM3X8E.SPI is -- Serial Peripheral Interface 0 type SPI0_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased SPI0_CR_Register; + pragma Volatile_Full_Access (CR); -- Mode Register - MR : MR_Register; + MR : aliased SPI0_MR_Register; + pragma Volatile_Full_Access (MR); -- Receive Data Register - RDR : RDR_Register; + RDR : aliased SPI0_RDR_Register; + pragma Volatile_Full_Access (RDR); -- Transmit Data Register - TDR : TDR_Register; + TDR : aliased SPI0_TDR_Register; + pragma Volatile_Full_Access (TDR); -- Status Register - SR : SR_Register; + SR : aliased SPI0_SR_Register; + pragma Volatile_Full_Access (SR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased SPI0_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased SPI0_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased SPI0_IMR_Register; + pragma Volatile_Full_Access (IMR); + -- Chip Select Register + CSR_0 : aliased SPI0_CSR_Register; + pragma Volatile_Full_Access (CSR_0); + -- Chip Select Register + CSR_1 : aliased SPI0_CSR_Register; + pragma Volatile_Full_Access (CSR_1); + -- Chip Select Register + CSR_2 : aliased SPI0_CSR_Register; + pragma Volatile_Full_Access (CSR_2); -- Chip Select Register - CSR : CSR_Registers; + CSR_3 : aliased SPI0_CSR_Register; + pragma Volatile_Full_Access (CSR_3); -- Write Protection Control Register - WPMR : WPMR_Register; + WPMR : aliased SPI0_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- Write Protection Status Register - WPSR : WPSR_Register; + WPSR : aliased SPI0_WPSR_Register; + pragma Volatile_Full_Access (WPSR); end record with Volatile; for SPI0_Peripheral use record - CR at 0 range 0 .. 31; - MR at 4 range 0 .. 31; - RDR at 8 range 0 .. 31; - TDR at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - IER at 20 range 0 .. 31; - IDR at 24 range 0 .. 31; - IMR at 28 range 0 .. 31; - CSR at 48 range 0 .. 127; - WPMR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; + CR at 16#0# range 0 .. 31; + MR at 16#4# range 0 .. 31; + RDR at 16#8# range 0 .. 31; + TDR at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + IER at 16#14# range 0 .. 31; + IDR at 16#18# range 0 .. 31; + IMR at 16#1C# range 0 .. 31; + CSR_0 at 16#30# range 0 .. 31; + CSR_1 at 16#34# range 0 .. 31; + CSR_2 at 16#38# range 0 .. 31; + CSR_3 at 16#3C# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; end record; -- Serial Peripheral Interface 0 diff --git a/arduino-due/atsam3x8e/atsam3x8e-ssc.ads b/arduino-due/atsam3x8e/atsam3x8e-ssc.ads index 77f5a61..7a80e56 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-ssc.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-ssc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,38 +15,34 @@ package ATSAM3X8E.SSC is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_RXEN_Field is ATSAM3X8E.Bit; - subtype CR_RXDIS_Field is ATSAM3X8E.Bit; - subtype CR_TXEN_Field is ATSAM3X8E.Bit; - subtype CR_TXDIS_Field is ATSAM3X8E.Bit; - subtype CR_SWRST_Field is ATSAM3X8E.Bit; + subtype SSC_CR_RXEN_Field is ATSAM3X8E.Bit; + subtype SSC_CR_RXDIS_Field is ATSAM3X8E.Bit; + subtype SSC_CR_TXEN_Field is ATSAM3X8E.Bit; + subtype SSC_CR_TXDIS_Field is ATSAM3X8E.Bit; + subtype SSC_CR_SWRST_Field is ATSAM3X8E.Bit; -- Control Register - type CR_Register is record + type SSC_CR_Register is record -- Write-only. Receive Enable - RXEN : CR_RXEN_Field := 16#0#; + RXEN : SSC_CR_RXEN_Field := 16#0#; -- Write-only. Receive Disable - RXDIS : CR_RXDIS_Field := 16#0#; + RXDIS : SSC_CR_RXDIS_Field := 16#0#; -- unspecified Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; -- Write-only. Transmit Enable - TXEN : CR_TXEN_Field := 16#0#; + TXEN : SSC_CR_TXEN_Field := 16#0#; -- Write-only. Transmit Disable - TXDIS : CR_TXDIS_Field := 16#0#; + TXDIS : SSC_CR_TXDIS_Field := 16#0#; -- unspecified Reserved_10_14 : ATSAM3X8E.UInt5 := 16#0#; -- Write-only. Software Reset - SWRST : CR_SWRST_Field := 16#0#; + SWRST : SSC_CR_SWRST_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for SSC_CR_Register use record RXEN at 0 range 0 .. 0; RXDIS at 0 range 1 .. 1; Reserved_2_7 at 0 range 2 .. 7; @@ -56,82 +53,70 @@ package ATSAM3X8E.SSC is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CMR_Register -- - ------------------ - - subtype CMR_DIV_Field is ATSAM3X8E.UInt12; + subtype SSC_CMR_DIV_Field is ATSAM3X8E.UInt12; -- Clock Mode Register - type CMR_Register is record + type SSC_CMR_Register is record -- Clock Divider - DIV : CMR_DIV_Field := 16#0#; + DIV : SSC_CMR_DIV_Field := 16#0#; -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CMR_Register use record + for SSC_CMR_Register use record DIV at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------- - -- RCMR_Register -- - ------------------- - -- Receive Clock Selection - type CKS_Field is - ( - -- Divided Clock + type RCMR_CKS_Field is + (-- Divided Clock Mck, -- TK Clock signal Tk, -- RK pin Rk) with Size => 2; - for CKS_Field use + for RCMR_CKS_Field use (Mck => 0, Tk => 1, Rk => 2); -- Receive Clock Output Mode Selection - type CKO_Field is - ( - -- None + type RCMR_CKO_Field is + (-- None None, -- Continuous Receive Clock Continuous, -- Receive Clock only during data transfers Transfer) with Size => 3; - for CKO_Field use + for RCMR_CKO_Field use (None => 0, Continuous => 1, Transfer => 2); - subtype RCMR_CKI_Field is ATSAM3X8E.Bit; + subtype SSC_RCMR_CKI_Field is ATSAM3X8E.Bit; -- Receive Clock Gating Selection - type CKG_Field is - ( - -- None + type RCMR_CKG_Field is + (-- None None, -- Continuous Receive Clock Continuous, -- Receive Clock only during data transfers Transfer) with Size => 2; - for CKG_Field use + for RCMR_CKG_Field use (None => 0, Continuous => 1, Transfer => 2); -- Receive Start Selection - type START_Field is - ( - -- Continuous, as soon as the receiver is enabled, and immediately after - -- the end of transfer of the previous data. + type RCMR_START_Field is + (-- Continuous, as soon as the receiver is enabled, and immediately after the +-- end of transfer of the previous data. Continuous, -- Transmit start Transmit, @@ -150,7 +135,7 @@ package ATSAM3X8E.SSC is -- Compare 0 Cmp_0) with Size => 4; - for START_Field use + for RCMR_START_Field use (Continuous => 0, Transmit => 1, Rf_Low => 2, @@ -161,34 +146,34 @@ package ATSAM3X8E.SSC is Rf_Edge => 7, Cmp_0 => 8); - subtype RCMR_STOP_Field is ATSAM3X8E.Bit; - subtype RCMR_STTDLY_Field is ATSAM3X8E.Byte; - subtype RCMR_PERIOD_Field is ATSAM3X8E.Byte; + subtype SSC_RCMR_STOP_Field is ATSAM3X8E.Bit; + subtype SSC_RCMR_STTDLY_Field is ATSAM3X8E.Byte; + subtype SSC_RCMR_PERIOD_Field is ATSAM3X8E.Byte; -- Receive Clock Mode Register - type RCMR_Register is record + type SSC_RCMR_Register is record -- Receive Clock Selection - CKS : CKS_Field := Mck; + CKS : RCMR_CKS_Field := ATSAM3X8E.SSC.Mck; -- Receive Clock Output Mode Selection - CKO : CKO_Field := None; + CKO : RCMR_CKO_Field := ATSAM3X8E.SSC.None; -- Receive Clock Inversion - CKI : RCMR_CKI_Field := 16#0#; + CKI : SSC_RCMR_CKI_Field := 16#0#; -- Receive Clock Gating Selection - CKG : CKG_Field := None; + CKG : RCMR_CKG_Field := ATSAM3X8E.SSC.None; -- Receive Start Selection - START : START_Field := Continuous; + START : RCMR_START_Field := ATSAM3X8E.SSC.Continuous; -- Receive Stop Selection - STOP : RCMR_STOP_Field := 16#0#; + STOP : SSC_RCMR_STOP_Field := 16#0#; -- unspecified Reserved_13_15 : ATSAM3X8E.UInt3 := 16#0#; -- Receive Start Delay - STTDLY : RCMR_STTDLY_Field := 16#0#; + STTDLY : SSC_RCMR_STTDLY_Field := 16#0#; -- Receive Period Divider Selection - PERIOD : RCMR_PERIOD_Field := 16#0#; + PERIOD : SSC_RCMR_PERIOD_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RCMR_Register use record + for SSC_RCMR_Register use record CKS at 0 range 0 .. 1; CKO at 0 range 2 .. 4; CKI at 0 range 5 .. 5; @@ -200,20 +185,15 @@ package ATSAM3X8E.SSC is PERIOD at 0 range 24 .. 31; end record; - ------------------- - -- RFMR_Register -- - ------------------- - - subtype RFMR_DATLEN_Field is ATSAM3X8E.UInt5; - subtype RFMR_LOOP_Field is ATSAM3X8E.Bit; - subtype RFMR_MSBF_Field is ATSAM3X8E.Bit; - subtype RFMR_DATNB_Field is ATSAM3X8E.UInt4; - subtype RFMR_FSLEN_Field is ATSAM3X8E.UInt4; + subtype SSC_RFMR_DATLEN_Field is ATSAM3X8E.UInt5; + subtype SSC_RFMR_LOOP_Field is ATSAM3X8E.Bit; + subtype SSC_RFMR_MSBF_Field is ATSAM3X8E.Bit; + subtype SSC_RFMR_DATNB_Field is ATSAM3X8E.UInt4; + subtype SSC_RFMR_FSLEN_Field is ATSAM3X8E.UInt4; -- Receive Frame Sync Output Selection - type FSOS_Field is - ( - -- None + type RFMR_FSOS_Field is + (-- None None, -- Negative Pulse Negative, @@ -226,7 +206,7 @@ package ATSAM3X8E.SSC is -- Toggling at each start of data transfer Toggling) with Size => 3; - for FSOS_Field use + for RFMR_FSOS_Field use (None => 0, Negative => 1, Positive => 2, @@ -235,49 +215,48 @@ package ATSAM3X8E.SSC is Toggling => 5); -- Frame Sync Edge Detection - type FSEDGE_Field is - ( - -- Positive Edge Detection + type RFMR_FSEDGE_Field is + (-- Positive Edge Detection Positive, -- Negative Edge Detection Negative) with Size => 1; - for FSEDGE_Field use + for RFMR_FSEDGE_Field use (Positive => 0, Negative => 1); - subtype RFMR_FSLEN_EXT_Field is ATSAM3X8E.UInt4; + subtype SSC_RFMR_FSLEN_EXT_Field is ATSAM3X8E.UInt4; -- Receive Frame Mode Register - type RFMR_Register is record + type SSC_RFMR_Register is record -- Data Length - DATLEN : RFMR_DATLEN_Field := 16#0#; + DATLEN : SSC_RFMR_DATLEN_Field := 16#0#; -- Loop Mode - LOOP_k : RFMR_LOOP_Field := 16#0#; + LOOP_k : SSC_RFMR_LOOP_Field := 16#0#; -- unspecified Reserved_6_6 : ATSAM3X8E.Bit := 16#0#; -- Most Significant Bit First - MSBF : RFMR_MSBF_Field := 16#0#; + MSBF : SSC_RFMR_MSBF_Field := 16#0#; -- Data Number per Frame - DATNB : RFMR_DATNB_Field := 16#0#; + DATNB : SSC_RFMR_DATNB_Field := 16#0#; -- unspecified Reserved_12_15 : ATSAM3X8E.UInt4 := 16#0#; -- Receive Frame Sync Length - FSLEN : RFMR_FSLEN_Field := 16#0#; + FSLEN : SSC_RFMR_FSLEN_Field := 16#0#; -- Receive Frame Sync Output Selection - FSOS : FSOS_Field := None; + FSOS : RFMR_FSOS_Field := ATSAM3X8E.SSC.None; -- unspecified Reserved_23_23 : ATSAM3X8E.Bit := 16#0#; -- Frame Sync Edge Detection - FSEDGE : FSEDGE_Field := Positive; + FSEDGE : RFMR_FSEDGE_Field := ATSAM3X8E.SSC.Positive; -- unspecified Reserved_25_27 : ATSAM3X8E.UInt3 := 16#0#; -- FSLEN Field Extension - FSLEN_EXT : RFMR_FSLEN_EXT_Field := 16#0#; + FSLEN_EXT : SSC_RFMR_FSLEN_EXT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RFMR_Register use record + for SSC_RFMR_Register use record DATLEN at 0 range 0 .. 4; LOOP_k at 0 range 5 .. 5; Reserved_6_6 at 0 range 6 .. 6; @@ -292,18 +271,55 @@ package ATSAM3X8E.SSC is FSLEN_EXT at 0 range 28 .. 31; end record; - ------------------- - -- TCMR_Register -- - ------------------- + -- Transmit Clock Selection + type TCMR_CKS_Field is + (-- Divided Clock + Mck, + -- TK Clock signal + Tk, + -- RK pin + Rk) + with Size => 2; + for TCMR_CKS_Field use + (Mck => 0, + Tk => 1, + Rk => 2); + + -- Transmit Clock Output Mode Selection + type TCMR_CKO_Field is + (-- None + None, + -- Continuous Receive Clock + Continuous, + -- Transmit Clock only during data transfers + Transfer) + with Size => 3; + for TCMR_CKO_Field use + (None => 0, + Continuous => 1, + Transfer => 2); + + subtype SSC_TCMR_CKI_Field is ATSAM3X8E.Bit; - subtype TCMR_CKI_Field is ATSAM3X8E.Bit; + -- Transmit Clock Gating Selection + type TCMR_CKG_Field is + (-- None + None, + -- Transmit Clock enabled only if TF Low + Continuous, + -- Transmit Clock enabled only if TF High + Transfer) + with Size => 2; + for TCMR_CKG_Field use + (None => 0, + Continuous => 1, + Transfer => 2); -- Transmit Start Selection - type START_Field_1 is - ( - -- Continuous, as soon as a word is written in the SSC_THR Register (if - -- Transmit is enabled), and immediately after the end of transfer of - -- the previous data. + type TCMR_START_Field is + (-- Continuous, as soon as a word is written in the SSC_THR Register (if +-- Transmit is enabled), and immediately after the end of transfer of the +-- previous data. Continuous, -- Receive start Receive, @@ -322,7 +338,7 @@ package ATSAM3X8E.SSC is -- Compare 0 Cmp_0) with Size => 4; - for START_Field_1 use + for TCMR_START_Field use (Continuous => 0, Receive => 1, Rf_Low => 2, @@ -333,31 +349,31 @@ package ATSAM3X8E.SSC is Rf_Edge => 7, Cmp_0 => 8); - subtype TCMR_STTDLY_Field is ATSAM3X8E.Byte; - subtype TCMR_PERIOD_Field is ATSAM3X8E.Byte; + subtype SSC_TCMR_STTDLY_Field is ATSAM3X8E.Byte; + subtype SSC_TCMR_PERIOD_Field is ATSAM3X8E.Byte; -- Transmit Clock Mode Register - type TCMR_Register is record + type SSC_TCMR_Register is record -- Transmit Clock Selection - CKS : CKS_Field := Mck; + CKS : TCMR_CKS_Field := ATSAM3X8E.SSC.Mck; -- Transmit Clock Output Mode Selection - CKO : CKO_Field := None; + CKO : TCMR_CKO_Field := ATSAM3X8E.SSC.None; -- Transmit Clock Inversion - CKI : TCMR_CKI_Field := 16#0#; + CKI : SSC_TCMR_CKI_Field := 16#0#; -- Transmit Clock Gating Selection - CKG : CKG_Field := None; + CKG : TCMR_CKG_Field := ATSAM3X8E.SSC.None; -- Transmit Start Selection - START : START_Field_1 := Continuous; + START : TCMR_START_Field := ATSAM3X8E.SSC.Continuous; -- unspecified Reserved_12_15 : ATSAM3X8E.UInt4 := 16#0#; -- Transmit Start Delay - STTDLY : TCMR_STTDLY_Field := 16#0#; + STTDLY : SSC_TCMR_STTDLY_Field := 16#0#; -- Transmit Period Divider Selection - PERIOD : TCMR_PERIOD_Field := 16#0#; + PERIOD : SSC_TCMR_PERIOD_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TCMR_Register use record + for SSC_TCMR_Register use record CKS at 0 range 0 .. 1; CKO at 0 range 2 .. 4; CKI at 0 range 5 .. 5; @@ -368,48 +384,80 @@ package ATSAM3X8E.SSC is PERIOD at 0 range 24 .. 31; end record; - ------------------- - -- TFMR_Register -- - ------------------- + subtype SSC_TFMR_DATLEN_Field is ATSAM3X8E.UInt5; + subtype SSC_TFMR_DATDEF_Field is ATSAM3X8E.Bit; + subtype SSC_TFMR_MSBF_Field is ATSAM3X8E.Bit; + subtype SSC_TFMR_DATNB_Field is ATSAM3X8E.UInt4; + subtype SSC_TFMR_FSLEN_Field is ATSAM3X8E.UInt4; - subtype TFMR_DATLEN_Field is ATSAM3X8E.UInt5; - subtype TFMR_DATDEF_Field is ATSAM3X8E.Bit; - subtype TFMR_MSBF_Field is ATSAM3X8E.Bit; - subtype TFMR_DATNB_Field is ATSAM3X8E.UInt4; - subtype TFMR_FSLEN_Field is ATSAM3X8E.UInt4; - subtype TFMR_FSDEN_Field is ATSAM3X8E.Bit; - subtype TFMR_FSLEN_EXT_Field is ATSAM3X8E.UInt4; + -- Transmit Frame Sync Output Selection + type TFMR_FSOS_Field is + (-- None + None, + -- Negative Pulse + Negative, + -- Positive Pulse + Positive, + -- Driven Low during data transfer + Low, + -- Driven High during data transfer + High, + -- Toggling at each start of data transfer + Toggling) + with Size => 3; + for TFMR_FSOS_Field use + (None => 0, + Negative => 1, + Positive => 2, + Low => 3, + High => 4, + Toggling => 5); + + subtype SSC_TFMR_FSDEN_Field is ATSAM3X8E.Bit; + + -- Frame Sync Edge Detection + type TFMR_FSEDGE_Field is + (-- Positive Edge Detection + Positive, + -- Negative Edge Detection + Negative) + with Size => 1; + for TFMR_FSEDGE_Field use + (Positive => 0, + Negative => 1); + + subtype SSC_TFMR_FSLEN_EXT_Field is ATSAM3X8E.UInt4; -- Transmit Frame Mode Register - type TFMR_Register is record + type SSC_TFMR_Register is record -- Data Length - DATLEN : TFMR_DATLEN_Field := 16#0#; + DATLEN : SSC_TFMR_DATLEN_Field := 16#0#; -- Data Default Value - DATDEF : TFMR_DATDEF_Field := 16#0#; + DATDEF : SSC_TFMR_DATDEF_Field := 16#0#; -- unspecified Reserved_6_6 : ATSAM3X8E.Bit := 16#0#; -- Most Significant Bit First - MSBF : TFMR_MSBF_Field := 16#0#; + MSBF : SSC_TFMR_MSBF_Field := 16#0#; -- Data Number per frame - DATNB : TFMR_DATNB_Field := 16#0#; + DATNB : SSC_TFMR_DATNB_Field := 16#0#; -- unspecified Reserved_12_15 : ATSAM3X8E.UInt4 := 16#0#; -- Transmit Frame Sync Length - FSLEN : TFMR_FSLEN_Field := 16#0#; + FSLEN : SSC_TFMR_FSLEN_Field := 16#0#; -- Transmit Frame Sync Output Selection - FSOS : FSOS_Field := None; + FSOS : TFMR_FSOS_Field := ATSAM3X8E.SSC.None; -- Frame Sync Data Enable - FSDEN : TFMR_FSDEN_Field := 16#0#; + FSDEN : SSC_TFMR_FSDEN_Field := 16#0#; -- Frame Sync Edge Detection - FSEDGE : FSEDGE_Field := Positive; + FSEDGE : TFMR_FSEDGE_Field := ATSAM3X8E.SSC.Positive; -- unspecified Reserved_25_27 : ATSAM3X8E.UInt3 := 16#0#; -- FSLEN Field Extension - FSLEN_EXT : TFMR_FSLEN_EXT_Field := 16#0#; + FSLEN_EXT : SSC_TFMR_FSLEN_EXT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TFMR_Register use record + for SSC_TFMR_Register use record DATLEN at 0 range 0 .. 4; DATDEF at 0 range 5 .. 5; Reserved_6_6 at 0 range 6 .. 6; @@ -424,108 +472,83 @@ package ATSAM3X8E.SSC is FSLEN_EXT at 0 range 28 .. 31; end record; - ------------------- - -- RSHR_Register -- - ------------------- - - subtype RSHR_RSDAT_Field is ATSAM3X8E.Short; + subtype SSC_RSHR_RSDAT_Field is ATSAM3X8E.UInt16; -- Receive Sync. Holding Register - type RSHR_Register is record + type SSC_RSHR_Register is record -- Read-only. Receive Synchronization Data - RSDAT : RSHR_RSDAT_Field := 16#0#; + RSDAT : SSC_RSHR_RSDAT_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RSHR_Register use record + for SSC_RSHR_Register use record RSDAT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- TSHR_Register -- - ------------------- - - subtype TSHR_TSDAT_Field is ATSAM3X8E.Short; + subtype SSC_TSHR_TSDAT_Field is ATSAM3X8E.UInt16; -- Transmit Sync. Holding Register - type TSHR_Register is record + type SSC_TSHR_Register is record -- Transmit Synchronization Data - TSDAT : TSHR_TSDAT_Field := 16#0#; + TSDAT : SSC_TSHR_TSDAT_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TSHR_Register use record + for SSC_TSHR_Register use record TSDAT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- RC0R_Register -- - ------------------- - - subtype RC0R_CP0_Field is ATSAM3X8E.Short; + subtype SSC_RC0R_CP0_Field is ATSAM3X8E.UInt16; -- Receive Compare 0 Register - type RC0R_Register is record + type SSC_RC0R_Register is record -- Receive Compare Data 0 - CP0 : RC0R_CP0_Field := 16#0#; + CP0 : SSC_RC0R_CP0_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RC0R_Register use record + for SSC_RC0R_Register use record CP0 at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- RC1R_Register -- - ------------------- - - subtype RC1R_CP1_Field is ATSAM3X8E.Short; + subtype SSC_RC1R_CP1_Field is ATSAM3X8E.UInt16; -- Receive Compare 1 Register - type RC1R_Register is record + type SSC_RC1R_Register is record -- Receive Compare Data 1 - CP1 : RC1R_CP1_Field := 16#0#; + CP1 : SSC_RC1R_CP1_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RC1R_Register use record + for SSC_RC1R_Register use record CP1 at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_TXRDY_Field is ATSAM3X8E.Bit; - subtype SR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype SR_RXRDY_Field is ATSAM3X8E.Bit; - subtype SR_OVRUN_Field is ATSAM3X8E.Bit; - - ----------- - -- SR.CP -- - ----------- + subtype SSC_SR_TXRDY_Field is ATSAM3X8E.Bit; + subtype SSC_SR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype SSC_SR_RXRDY_Field is ATSAM3X8E.Bit; + subtype SSC_SR_OVRUN_Field is ATSAM3X8E.Bit; + -- SSC_SR_CP array element + subtype SSC_SR_CP_Element is ATSAM3X8E.Bit; - -- SR_CP array element - subtype SR_CP_Element is ATSAM3X8E.Bit; - - -- SR_CP array - type SR_CP_Field_Array is array (0 .. 1) of SR_CP_Element + -- SSC_SR_CP array + type SSC_SR_CP_Field_Array is array (0 .. 1) of SSC_SR_CP_Element with Component_Size => 1, Size => 2; - -- Type definition for SR_CP - type SR_CP_Field + -- Type definition for SSC_SR_CP + type SSC_SR_CP_Field (As_Array : Boolean := False) is record case As_Array is @@ -534,53 +557,53 @@ package ATSAM3X8E.SSC is Val : ATSAM3X8E.UInt2; when True => -- CP as an array - Arr : SR_CP_Field_Array; + Arr : SSC_SR_CP_Field_Array; end case; end record with Unchecked_Union, Size => 2; - for SR_CP_Field use record + for SSC_SR_CP_Field use record Val at 0 range 0 .. 1; Arr at 0 range 0 .. 1; end record; - subtype SR_TXSYN_Field is ATSAM3X8E.Bit; - subtype SR_RXSYN_Field is ATSAM3X8E.Bit; - subtype SR_TXEN_Field is ATSAM3X8E.Bit; - subtype SR_RXEN_Field is ATSAM3X8E.Bit; + subtype SSC_SR_TXSYN_Field is ATSAM3X8E.Bit; + subtype SSC_SR_RXSYN_Field is ATSAM3X8E.Bit; + subtype SSC_SR_TXEN_Field is ATSAM3X8E.Bit; + subtype SSC_SR_RXEN_Field is ATSAM3X8E.Bit; -- Status Register - type SR_Register is record + type SSC_SR_Register is record -- Read-only. Transmit Ready - TXRDY : SR_TXRDY_Field := 16#0#; + TXRDY : SSC_SR_TXRDY_Field; -- Read-only. Transmit Empty - TXEMPTY : SR_TXEMPTY_Field := 16#0#; + TXEMPTY : SSC_SR_TXEMPTY_Field; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2; -- Read-only. Receive Ready - RXRDY : SR_RXRDY_Field := 16#0#; + RXRDY : SSC_SR_RXRDY_Field; -- Read-only. Receive Overrun - OVRUN : SR_OVRUN_Field := 16#0#; + OVRUN : SSC_SR_OVRUN_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. Compare 0 - CP : SR_CP_Field := (As_Array => False, Val => 16#0#); + CP : SSC_SR_CP_Field; -- Read-only. Transmit Sync - TXSYN : SR_TXSYN_Field := 16#0#; + TXSYN : SSC_SR_TXSYN_Field; -- Read-only. Receive Sync - RXSYN : SR_RXSYN_Field := 16#0#; + RXSYN : SSC_SR_RXSYN_Field; -- unspecified Reserved_12_15 : ATSAM3X8E.UInt4; -- Read-only. Transmit Enable - TXEN : SR_TXEN_Field := 16#0#; + TXEN : SSC_SR_TXEN_Field; -- Read-only. Receive Enable - RXEN : SR_RXEN_Field := 16#0#; + RXEN : SSC_SR_RXEN_Field; -- unspecified Reserved_18_31 : ATSAM3X8E.UInt14; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for SSC_SR_Register use record TXRDY at 0 range 0 .. 0; TXEMPTY at 0 range 1 .. 1; Reserved_2_3 at 0 range 2 .. 3; @@ -596,28 +619,19 @@ package ATSAM3X8E.SSC is Reserved_18_31 at 0 range 18 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_TXRDY_Field is ATSAM3X8E.Bit; - subtype IER_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IER_RXRDY_Field is ATSAM3X8E.Bit; - subtype IER_OVRUN_Field is ATSAM3X8E.Bit; + subtype SSC_IER_TXRDY_Field is ATSAM3X8E.Bit; + subtype SSC_IER_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype SSC_IER_RXRDY_Field is ATSAM3X8E.Bit; + subtype SSC_IER_OVRUN_Field is ATSAM3X8E.Bit; + -- SSC_IER_CP array element + subtype SSC_IER_CP_Element is ATSAM3X8E.Bit; - ------------ - -- IER.CP -- - ------------ - - -- IER_CP array element - subtype IER_CP_Element is ATSAM3X8E.Bit; - - -- IER_CP array - type IER_CP_Field_Array is array (0 .. 1) of IER_CP_Element + -- SSC_IER_CP array + type SSC_IER_CP_Field_Array is array (0 .. 1) of SSC_IER_CP_Element with Component_Size => 1, Size => 2; - -- Type definition for IER_CP - type IER_CP_Field + -- Type definition for SSC_IER_CP + type SSC_IER_CP_Field (As_Array : Boolean := False) is record case As_Array is @@ -626,45 +640,45 @@ package ATSAM3X8E.SSC is Val : ATSAM3X8E.UInt2; when True => -- CP as an array - Arr : IER_CP_Field_Array; + Arr : SSC_IER_CP_Field_Array; end case; end record with Unchecked_Union, Size => 2; - for IER_CP_Field use record + for SSC_IER_CP_Field use record Val at 0 range 0 .. 1; Arr at 0 range 0 .. 1; end record; - subtype IER_TXSYN_Field is ATSAM3X8E.Bit; - subtype IER_RXSYN_Field is ATSAM3X8E.Bit; + subtype SSC_IER_TXSYN_Field is ATSAM3X8E.Bit; + subtype SSC_IER_RXSYN_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type SSC_IER_Register is record -- Write-only. Transmit Ready Interrupt Enable - TXRDY : IER_TXRDY_Field := 16#0#; + TXRDY : SSC_IER_TXRDY_Field := 16#0#; -- Write-only. Transmit Empty Interrupt Enable - TXEMPTY : IER_TXEMPTY_Field := 16#0#; + TXEMPTY : SSC_IER_TXEMPTY_Field := 16#0#; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Receive Ready Interrupt Enable - RXRDY : IER_RXRDY_Field := 16#0#; + RXRDY : SSC_IER_RXRDY_Field := 16#0#; -- Write-only. Receive Overrun Interrupt Enable - OVRUN : IER_OVRUN_Field := 16#0#; + OVRUN : SSC_IER_OVRUN_Field := 16#0#; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Compare 0 Interrupt Enable - CP : IER_CP_Field := (As_Array => False, Val => 16#0#); + CP : SSC_IER_CP_Field := (As_Array => False, Val => 16#0#); -- Write-only. Tx Sync Interrupt Enable - TXSYN : IER_TXSYN_Field := 16#0#; + TXSYN : SSC_IER_TXSYN_Field := 16#0#; -- Write-only. Rx Sync Interrupt Enable - RXSYN : IER_RXSYN_Field := 16#0#; + RXSYN : SSC_IER_RXSYN_Field := 16#0#; -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for SSC_IER_Register use record TXRDY at 0 range 0 .. 0; TXEMPTY at 0 range 1 .. 1; Reserved_2_3 at 0 range 2 .. 3; @@ -677,28 +691,19 @@ package ATSAM3X8E.SSC is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IDR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_OVRUN_Field is ATSAM3X8E.Bit; - - ------------ - -- IDR.CP -- - ------------ - - -- IDR_CP array element - subtype IDR_CP_Element is ATSAM3X8E.Bit; + subtype SSC_IDR_TXRDY_Field is ATSAM3X8E.Bit; + subtype SSC_IDR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype SSC_IDR_RXRDY_Field is ATSAM3X8E.Bit; + subtype SSC_IDR_OVRUN_Field is ATSAM3X8E.Bit; + -- SSC_IDR_CP array element + subtype SSC_IDR_CP_Element is ATSAM3X8E.Bit; - -- IDR_CP array - type IDR_CP_Field_Array is array (0 .. 1) of IDR_CP_Element + -- SSC_IDR_CP array + type SSC_IDR_CP_Field_Array is array (0 .. 1) of SSC_IDR_CP_Element with Component_Size => 1, Size => 2; - -- Type definition for IDR_CP - type IDR_CP_Field + -- Type definition for SSC_IDR_CP + type SSC_IDR_CP_Field (As_Array : Boolean := False) is record case As_Array is @@ -707,45 +712,45 @@ package ATSAM3X8E.SSC is Val : ATSAM3X8E.UInt2; when True => -- CP as an array - Arr : IDR_CP_Field_Array; + Arr : SSC_IDR_CP_Field_Array; end case; end record with Unchecked_Union, Size => 2; - for IDR_CP_Field use record + for SSC_IDR_CP_Field use record Val at 0 range 0 .. 1; Arr at 0 range 0 .. 1; end record; - subtype IDR_TXSYN_Field is ATSAM3X8E.Bit; - subtype IDR_RXSYN_Field is ATSAM3X8E.Bit; + subtype SSC_IDR_TXSYN_Field is ATSAM3X8E.Bit; + subtype SSC_IDR_RXSYN_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type SSC_IDR_Register is record -- Write-only. Transmit Ready Interrupt Disable - TXRDY : IDR_TXRDY_Field := 16#0#; + TXRDY : SSC_IDR_TXRDY_Field := 16#0#; -- Write-only. Transmit Empty Interrupt Disable - TXEMPTY : IDR_TXEMPTY_Field := 16#0#; + TXEMPTY : SSC_IDR_TXEMPTY_Field := 16#0#; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Receive Ready Interrupt Disable - RXRDY : IDR_RXRDY_Field := 16#0#; + RXRDY : SSC_IDR_RXRDY_Field := 16#0#; -- Write-only. Receive Overrun Interrupt Disable - OVRUN : IDR_OVRUN_Field := 16#0#; + OVRUN : SSC_IDR_OVRUN_Field := 16#0#; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Compare 0 Interrupt Disable - CP : IDR_CP_Field := (As_Array => False, Val => 16#0#); + CP : SSC_IDR_CP_Field := (As_Array => False, Val => 16#0#); -- Write-only. Tx Sync Interrupt Enable - TXSYN : IDR_TXSYN_Field := 16#0#; + TXSYN : SSC_IDR_TXSYN_Field := 16#0#; -- Write-only. Rx Sync Interrupt Enable - RXSYN : IDR_RXSYN_Field := 16#0#; + RXSYN : SSC_IDR_RXSYN_Field := 16#0#; -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for SSC_IDR_Register use record TXRDY at 0 range 0 .. 0; TXEMPTY at 0 range 1 .. 1; Reserved_2_3 at 0 range 2 .. 3; @@ -758,28 +763,19 @@ package ATSAM3X8E.SSC is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ + subtype SSC_IMR_TXRDY_Field is ATSAM3X8E.Bit; + subtype SSC_IMR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype SSC_IMR_RXRDY_Field is ATSAM3X8E.Bit; + subtype SSC_IMR_OVRUN_Field is ATSAM3X8E.Bit; + -- SSC_IMR_CP array element + subtype SSC_IMR_CP_Element is ATSAM3X8E.Bit; - subtype IMR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IMR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_OVRUN_Field is ATSAM3X8E.Bit; - - ------------ - -- IMR.CP -- - ------------ - - -- IMR_CP array element - subtype IMR_CP_Element is ATSAM3X8E.Bit; - - -- IMR_CP array - type IMR_CP_Field_Array is array (0 .. 1) of IMR_CP_Element + -- SSC_IMR_CP array + type SSC_IMR_CP_Field_Array is array (0 .. 1) of SSC_IMR_CP_Element with Component_Size => 1, Size => 2; - -- Type definition for IMR_CP - type IMR_CP_Field + -- Type definition for SSC_IMR_CP + type SSC_IMR_CP_Field (As_Array : Boolean := False) is record case As_Array is @@ -788,45 +784,45 @@ package ATSAM3X8E.SSC is Val : ATSAM3X8E.UInt2; when True => -- CP as an array - Arr : IMR_CP_Field_Array; + Arr : SSC_IMR_CP_Field_Array; end case; end record with Unchecked_Union, Size => 2; - for IMR_CP_Field use record + for SSC_IMR_CP_Field use record Val at 0 range 0 .. 1; Arr at 0 range 0 .. 1; end record; - subtype IMR_TXSYN_Field is ATSAM3X8E.Bit; - subtype IMR_RXSYN_Field is ATSAM3X8E.Bit; + subtype SSC_IMR_TXSYN_Field is ATSAM3X8E.Bit; + subtype SSC_IMR_RXSYN_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type SSC_IMR_Register is record -- Read-only. Transmit Ready Interrupt Mask - TXRDY : IMR_TXRDY_Field := 16#0#; + TXRDY : SSC_IMR_TXRDY_Field; -- Read-only. Transmit Empty Interrupt Mask - TXEMPTY : IMR_TXEMPTY_Field := 16#0#; + TXEMPTY : SSC_IMR_TXEMPTY_Field; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2; -- Read-only. Receive Ready Interrupt Mask - RXRDY : IMR_RXRDY_Field := 16#0#; + RXRDY : SSC_IMR_RXRDY_Field; -- Read-only. Receive Overrun Interrupt Mask - OVRUN : IMR_OVRUN_Field := 16#0#; + OVRUN : SSC_IMR_OVRUN_Field; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2; -- Read-only. Compare 0 Interrupt Mask - CP : IMR_CP_Field := (As_Array => False, Val => 16#0#); + CP : SSC_IMR_CP_Field; -- Read-only. Tx Sync Interrupt Mask - TXSYN : IMR_TXSYN_Field := 16#0#; + TXSYN : SSC_IMR_TXSYN_Field; -- Read-only. Rx Sync Interrupt Mask - RXSYN : IMR_RXSYN_Field := 16#0#; + RXSYN : SSC_IMR_RXSYN_Field; -- unspecified Reserved_12_31 : ATSAM3X8E.UInt20; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for SSC_IMR_Register use record TXRDY at 0 range 0 .. 0; TXEMPTY at 0 range 1 .. 1; Reserved_2_3 at 0 range 2 .. 3; @@ -839,51 +835,43 @@ package ATSAM3X8E.SSC is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype SSC_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype SSC_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- Write Protect Mode Register - type WPMR_Register is record + type SSC_WPMR_Register is record -- Write Protect Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : SSC_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protect KEY - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : SSC_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for SSC_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype WPSR_WPVSRC_Field is ATSAM3X8E.Short; + subtype SSC_WPSR_WPVS_Field is ATSAM3X8E.Bit; + subtype SSC_WPSR_WPVSRC_Field is ATSAM3X8E.UInt16; -- Write Protect Status Register - type WPSR_Register is record + type SSC_WPSR_Register is record -- Read-only. Write Protect Violation Status - WPVS : WPSR_WPVS_Field := 16#0#; + WPVS : SSC_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protect Violation Source - WPVSRC : WPSR_WPVSRC_Field := 16#0#; + WPVSRC : SSC_WPSR_WPVSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for SSC_WPSR_Register use record WPVS at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPVSRC at 0 range 8 .. 23; @@ -897,63 +885,79 @@ package ATSAM3X8E.SSC is -- Synchronous Serial Controller type SSC_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased SSC_CR_Register; + pragma Volatile_Full_Access (CR); -- Clock Mode Register - CMR : CMR_Register; + CMR : aliased SSC_CMR_Register; + pragma Volatile_Full_Access (CMR); -- Receive Clock Mode Register - RCMR : RCMR_Register; + RCMR : aliased SSC_RCMR_Register; + pragma Volatile_Full_Access (RCMR); -- Receive Frame Mode Register - RFMR : RFMR_Register; + RFMR : aliased SSC_RFMR_Register; + pragma Volatile_Full_Access (RFMR); -- Transmit Clock Mode Register - TCMR : TCMR_Register; + TCMR : aliased SSC_TCMR_Register; + pragma Volatile_Full_Access (TCMR); -- Transmit Frame Mode Register - TFMR : TFMR_Register; + TFMR : aliased SSC_TFMR_Register; + pragma Volatile_Full_Access (TFMR); -- Receive Holding Register - RHR : ATSAM3X8E.Word; + RHR : aliased ATSAM3X8E.UInt32; -- Transmit Holding Register - THR : ATSAM3X8E.Word; + THR : aliased ATSAM3X8E.UInt32; -- Receive Sync. Holding Register - RSHR : RSHR_Register; + RSHR : aliased SSC_RSHR_Register; + pragma Volatile_Full_Access (RSHR); -- Transmit Sync. Holding Register - TSHR : TSHR_Register; + TSHR : aliased SSC_TSHR_Register; + pragma Volatile_Full_Access (TSHR); -- Receive Compare 0 Register - RC0R : RC0R_Register; + RC0R : aliased SSC_RC0R_Register; + pragma Volatile_Full_Access (RC0R); -- Receive Compare 1 Register - RC1R : RC1R_Register; + RC1R : aliased SSC_RC1R_Register; + pragma Volatile_Full_Access (RC1R); -- Status Register - SR : SR_Register; + SR : aliased SSC_SR_Register; + pragma Volatile_Full_Access (SR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased SSC_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased SSC_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased SSC_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Write Protect Mode Register - WPMR : WPMR_Register; + WPMR : aliased SSC_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- Write Protect Status Register - WPSR : WPSR_Register; + WPSR : aliased SSC_WPSR_Register; + pragma Volatile_Full_Access (WPSR); end record with Volatile; for SSC_Peripheral use record - CR at 0 range 0 .. 31; - CMR at 4 range 0 .. 31; - RCMR at 16 range 0 .. 31; - RFMR at 20 range 0 .. 31; - TCMR at 24 range 0 .. 31; - TFMR at 28 range 0 .. 31; - RHR at 32 range 0 .. 31; - THR at 36 range 0 .. 31; - RSHR at 48 range 0 .. 31; - TSHR at 52 range 0 .. 31; - RC0R at 56 range 0 .. 31; - RC1R at 60 range 0 .. 31; - SR at 64 range 0 .. 31; - IER at 68 range 0 .. 31; - IDR at 72 range 0 .. 31; - IMR at 76 range 0 .. 31; - WPMR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; + CR at 16#0# range 0 .. 31; + CMR at 16#4# range 0 .. 31; + RCMR at 16#10# range 0 .. 31; + RFMR at 16#14# range 0 .. 31; + TCMR at 16#18# range 0 .. 31; + TFMR at 16#1C# range 0 .. 31; + RHR at 16#20# range 0 .. 31; + THR at 16#24# range 0 .. 31; + RSHR at 16#30# range 0 .. 31; + TSHR at 16#34# range 0 .. 31; + RC0R at 16#38# range 0 .. 31; + RC1R at 16#3C# range 0 .. 31; + SR at 16#40# range 0 .. 31; + IER at 16#44# range 0 .. 31; + IDR at 16#48# range 0 .. 31; + IMR at 16#4C# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; end record; -- Synchronous Serial Controller diff --git a/arduino-due/atsam3x8e/atsam3x8e-sysc.ads b/arduino-due/atsam3x8e/atsam3x8e-sysc.ads index 2b732ad..51b83f8 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-sysc.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-sysc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,33 +14,30 @@ package ATSAM3X8E.SYSC is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_PROCRST_Field is ATSAM3X8E.Bit; - subtype CR_PERRST_Field is ATSAM3X8E.Bit; - subtype CR_EXTRST_Field is ATSAM3X8E.Bit; - subtype CR_KEY_Field is ATSAM3X8E.Byte; + -- General Purpose Backup Register + subtype RSTC_CR_PROCRST_Field is ATSAM3X8E.Bit; + subtype RSTC_CR_PERRST_Field is ATSAM3X8E.Bit; + subtype RSTC_CR_EXTRST_Field is ATSAM3X8E.Bit; + subtype RSTC_CR_KEY_Field is ATSAM3X8E.Byte; -- Control Register - type CR_Register is record + type RSTC_CR_Register is record -- Write-only. Processor Reset - PROCRST : CR_PROCRST_Field := 16#0#; + PROCRST : RSTC_CR_PROCRST_Field := 16#0#; -- unspecified Reserved_1_1 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Peripheral Reset - PERRST : CR_PERRST_Field := 16#0#; + PERRST : RSTC_CR_PERRST_Field := 16#0#; -- Write-only. External Reset - EXTRST : CR_EXTRST_Field := 16#0#; + EXTRST : RSTC_CR_EXTRST_Field := 16#0#; -- unspecified Reserved_4_23 : ATSAM3X8E.UInt20 := 16#0#; -- Write-only. System Reset Key - KEY : CR_KEY_Field := 16#0#; + KEY : RSTC_CR_KEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for RSTC_CR_Register use record PROCRST at 0 range 0 .. 0; Reserved_1_1 at 0 range 1 .. 1; PERRST at 0 range 2 .. 2; @@ -48,35 +46,31 @@ package ATSAM3X8E.SYSC is KEY at 0 range 24 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_URSTS_Field is ATSAM3X8E.Bit; - subtype SR_RSTTYP_Field is ATSAM3X8E.UInt3; - subtype SR_NRSTL_Field is ATSAM3X8E.Bit; - subtype SR_SRCMP_Field is ATSAM3X8E.Bit; + subtype RSTC_SR_URSTS_Field is ATSAM3X8E.Bit; + subtype RSTC_SR_RSTTYP_Field is ATSAM3X8E.UInt3; + subtype RSTC_SR_NRSTL_Field is ATSAM3X8E.Bit; + subtype RSTC_SR_SRCMP_Field is ATSAM3X8E.Bit; -- Status Register - type SR_Register is record + type RSTC_SR_Register is record -- Read-only. User Reset Status - URSTS : SR_URSTS_Field := 16#0#; + URSTS : RSTC_SR_URSTS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Reset Type - RSTTYP : SR_RSTTYP_Field := 16#0#; + RSTTYP : RSTC_SR_RSTTYP_Field; -- unspecified Reserved_11_15 : ATSAM3X8E.UInt5; -- Read-only. NRST Pin Level - NRSTL : SR_NRSTL_Field := 16#0#; + NRSTL : RSTC_SR_NRSTL_Field; -- Read-only. Software Reset Command in Progress - SRCMP : SR_SRCMP_Field := 16#0#; + SRCMP : RSTC_SR_SRCMP_Field; -- unspecified Reserved_18_31 : ATSAM3X8E.UInt14; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for RSTC_SR_Register use record URSTS at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; RSTTYP at 0 range 8 .. 10; @@ -86,35 +80,31 @@ package ATSAM3X8E.SYSC is Reserved_18_31 at 0 range 18 .. 31; end record; - ----------------- - -- MR_Register -- - ----------------- - - subtype MR_URSTEN_Field is ATSAM3X8E.Bit; - subtype MR_URSTIEN_Field is ATSAM3X8E.Bit; - subtype MR_ERSTL_Field is ATSAM3X8E.UInt4; - subtype MR_KEY_Field is ATSAM3X8E.Byte; + subtype RSTC_MR_URSTEN_Field is ATSAM3X8E.Bit; + subtype RSTC_MR_URSTIEN_Field is ATSAM3X8E.Bit; + subtype RSTC_MR_ERSTL_Field is ATSAM3X8E.UInt4; + subtype RSTC_MR_KEY_Field is ATSAM3X8E.Byte; -- Mode Register - type MR_Register is record + type RSTC_MR_Register is record -- User Reset Enable - URSTEN : MR_URSTEN_Field := 16#1#; + URSTEN : RSTC_MR_URSTEN_Field := 16#1#; -- unspecified Reserved_1_3 : ATSAM3X8E.UInt3 := 16#0#; -- User Reset Interrupt Enable - URSTIEN : MR_URSTIEN_Field := 16#0#; + URSTIEN : RSTC_MR_URSTIEN_Field := 16#0#; -- unspecified Reserved_5_7 : ATSAM3X8E.UInt3 := 16#0#; -- External Reset Length - ERSTL : MR_ERSTL_Field := 16#0#; + ERSTL : RSTC_MR_ERSTL_Field := 16#0#; -- unspecified Reserved_12_23 : ATSAM3X8E.UInt12 := 16#0#; -- Password - KEY : MR_KEY_Field := 16#0#; + KEY : RSTC_MR_KEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_Register use record + for RSTC_MR_Register use record URSTEN at 0 range 0 .. 0; Reserved_1_3 at 0 range 1 .. 3; URSTIEN at 0 range 4 .. 4; @@ -124,1262 +114,1429 @@ package ATSAM3X8E.SYSC is KEY at 0 range 24 .. 31; end record; - ------------------- - -- SMMR_Register -- - ------------------- + subtype RTC_CR_UPDTIM_Field is ATSAM3X8E.Bit; + subtype RTC_CR_UPDCAL_Field is ATSAM3X8E.Bit; + + -- Time Event Selection + type CR_TIMEVSEL_Field is + (-- Minute change + Minute, + -- Hour change + Hour, + -- Every day at midnight + Midnight, + -- Every day at noon + Noon) + with Size => 2; + for CR_TIMEVSEL_Field use + (Minute => 0, + Hour => 1, + Midnight => 2, + Noon => 3); + + -- Calendar Event Selection + type CR_CALEVSEL_Field is + (-- Week change (every Monday at time 00:00:00) + Week, + -- Month change (every 01 of each month at time 00:00:00) + Month, + -- Year change (every January 1 at time 00:00:00) + Year) + with Size => 2; + for CR_CALEVSEL_Field use + (Week => 0, + Month => 1, + Year => 2); - -- Supply Monitor Threshold - type SMTH_Field is - ( - -- 1.9 V - SMTH_Field_1_9V, - -- 2.0 V - SMTH_Field_2_0V, - -- 2.1 V - SMTH_Field_2_1V, - -- 2.2 V - SMTH_Field_2_2V, - -- 2.3 V - SMTH_Field_2_3V, - -- 2.4 V - SMTH_Field_2_4V, - -- 2.5 V - SMTH_Field_2_5V, - -- 2.6 V - SMTH_Field_2_6V, - -- 2.7 V - SMTH_Field_2_7V, - -- 2.8 V - SMTH_Field_2_8V, - -- 2.9 V - SMTH_Field_2_9V, - -- 3.0 V - SMTH_Field_3_0V, - -- 3.1 V - SMTH_Field_3_1V, - -- 3.2 V - SMTH_Field_3_2V, - -- 3.3 V - SMTH_Field_3_3V, - -- 3.4 V - SMTH_Field_3_4V) - with Size => 4; - for SMTH_Field use - (SMTH_Field_1_9V => 0, - SMTH_Field_2_0V => 1, - SMTH_Field_2_1V => 2, - SMTH_Field_2_2V => 3, - SMTH_Field_2_3V => 4, - SMTH_Field_2_4V => 5, - SMTH_Field_2_5V => 6, - SMTH_Field_2_6V => 7, - SMTH_Field_2_7V => 8, - SMTH_Field_2_8V => 9, - SMTH_Field_2_9V => 10, - SMTH_Field_3_0V => 11, - SMTH_Field_3_1V => 12, - SMTH_Field_3_2V => 13, - SMTH_Field_3_3V => 14, - SMTH_Field_3_4V => 15); + -- Control Register + type RTC_CR_Register is record + -- Update Request Time Register + UPDTIM : RTC_CR_UPDTIM_Field := 16#0#; + -- Update Request Calendar Register + UPDCAL : RTC_CR_UPDCAL_Field := 16#0#; + -- unspecified + Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; + -- Time Event Selection + TIMEVSEL : CR_TIMEVSEL_Field := ATSAM3X8E.SYSC.Minute; + -- unspecified + Reserved_10_15 : ATSAM3X8E.UInt6 := 16#0#; + -- Calendar Event Selection + CALEVSEL : CR_CALEVSEL_Field := ATSAM3X8E.SYSC.Week; + -- unspecified + Reserved_18_31 : ATSAM3X8E.UInt14 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTC_CR_Register use record + UPDTIM at 0 range 0 .. 0; + UPDCAL at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + TIMEVSEL at 0 range 8 .. 9; + Reserved_10_15 at 0 range 10 .. 15; + CALEVSEL at 0 range 16 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; - -- Supply Monitor Sampling Period - type SMSMPL_Field is - ( - -- Supply Monitor disabled - Smd, - -- Continuous Supply Monitor - Csm, - -- Supply Monitor enabled one SLCK period every 32 SLCK periods - SMSMPL_Field_32Slck, - -- Supply Monitor enabled one SLCK period every 256 SLCK periods - SMSMPL_Field_256Slck, - -- Supply Monitor enabled one SLCK period every 2,048 SLCK periods - SMSMPL_Field_2048Slck) - with Size => 3; - for SMSMPL_Field use - (Smd => 0, - Csm => 1, - SMSMPL_Field_32Slck => 2, - SMSMPL_Field_256Slck => 3, - SMSMPL_Field_2048Slck => 4); + subtype RTC_MR_HRMOD_Field is ATSAM3X8E.Bit; - -- Supply Monitor Reset Enable - type SMRSTEN_Field is - ( - -- the core reset signal "vddcore_nreset" is not affected when a supply - -- monitor detection occurs. - Not_Enable, - -- the core reset signal, vddcore_nreset is asserted when a supply - -- monitor detection occurs. - Enable) - with Size => 1; - for SMRSTEN_Field use - (Not_Enable => 0, - Enable => 1); + -- Mode Register + type RTC_MR_Register is record + -- 12-/24-hour Mode + HRMOD : RTC_MR_HRMOD_Field := 16#0#; + -- unspecified + Reserved_1_31 : ATSAM3X8E.UInt31 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- Supply Monitor Interrupt Enable - type SMIEN_Field is - ( - -- the SUPC interrupt signal is not affected when a supply monitor - -- detection occurs. - Not_Enable, - -- the SUPC interrupt signal is asserted when a supply monitor detection - -- occurs. - Enable) - with Size => 1; - for SMIEN_Field use - (Not_Enable => 0, - Enable => 1); + for RTC_MR_Register use record + HRMOD at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; - -- Supply Controller Supply Monitor Mode Register - type SMMR_Register is record - -- Supply Monitor Threshold - SMTH : SMTH_Field := SMTH_Field_1_9V; + subtype RTC_TIMR_SEC_Field is ATSAM3X8E.UInt7; + subtype RTC_TIMR_MIN_Field is ATSAM3X8E.UInt7; + subtype RTC_TIMR_HOUR_Field is ATSAM3X8E.UInt6; + subtype RTC_TIMR_AMPM_Field is ATSAM3X8E.Bit; + + -- Time Register + type RTC_TIMR_Register is record + -- Current Second + SEC : RTC_TIMR_SEC_Field := 16#0#; -- unspecified - Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; - -- Supply Monitor Sampling Period - SMSMPL : SMSMPL_Field := Smd; + Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; + -- Current Minute + MIN : RTC_TIMR_MIN_Field := 16#0#; -- unspecified - Reserved_11_11 : ATSAM3X8E.Bit := 16#0#; - -- Supply Monitor Reset Enable - SMRSTEN : SMRSTEN_Field := Not_Enable; - -- Supply Monitor Interrupt Enable - SMIEN : SMIEN_Field := Not_Enable; + Reserved_15_15 : ATSAM3X8E.Bit := 16#0#; + -- Current Hour + HOUR : RTC_TIMR_HOUR_Field := 16#0#; + -- Ante Meridiem Post Meridiem Indicator + AMPM : RTC_TIMR_AMPM_Field := 16#0#; -- unspecified - Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; + Reserved_23_31 : ATSAM3X8E.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SMMR_Register use record - SMTH at 0 range 0 .. 3; - Reserved_4_7 at 0 range 4 .. 7; - SMSMPL at 0 range 8 .. 10; - Reserved_11_11 at 0 range 11 .. 11; - SMRSTEN at 0 range 12 .. 12; - SMIEN at 0 range 13 .. 13; - Reserved_14_31 at 0 range 14 .. 31; + for RTC_TIMR_Register use record + SEC at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MIN at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + HOUR at 0 range 16 .. 21; + AMPM at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- WUMR_Register -- - ------------------- + subtype RTC_CALR_CENT_Field is ATSAM3X8E.UInt7; + subtype RTC_CALR_YEAR_Field is ATSAM3X8E.Byte; + subtype RTC_CALR_MONTH_Field is ATSAM3X8E.UInt5; + subtype RTC_CALR_DAY_Field is ATSAM3X8E.UInt3; + subtype RTC_CALR_DATE_Field is ATSAM3X8E.UInt6; - -- Force Wake Up Enable - type FWUPEN_Field is - ( - -- the Force Wake Up pin has no wake up effect. - Not_Enable, - -- the Force Wake Up pin low forces the wake up of the core power - -- supply. - Enable) - with Size => 1; - for FWUPEN_Field use - (Not_Enable => 0, - Enable => 1); + -- Calendar Register + type RTC_CALR_Register is record + -- Current Century + CENT : RTC_CALR_CENT_Field := 16#20#; + -- unspecified + Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; + -- Current Year + YEAR : RTC_CALR_YEAR_Field := 16#7#; + -- Current Month + MONTH : RTC_CALR_MONTH_Field := 16#1#; + -- Current Day in Current Week + DAY : RTC_CALR_DAY_Field := 16#1#; + -- Current Day in Current Month + DATE : RTC_CALR_DATE_Field := 16#1#; + -- unspecified + Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- Supply Monitor Wake Up Enable - type SMEN_Field is - ( - -- the supply monitor detection has no wake up effect. - Not_Enable, - -- the supply monitor detection forces the wake up of the core power - -- supply. - Enable) - with Size => 1; - for SMEN_Field use - (Not_Enable => 0, - Enable => 1); + for RTC_CALR_Register use record + CENT at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + YEAR at 0 range 8 .. 15; + MONTH at 0 range 16 .. 20; + DAY at 0 range 21 .. 23; + DATE at 0 range 24 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; - -- Real Time Timer Wake Up Enable - type RTTEN_Field is - ( - -- the RTT alarm signal has no wake up effect. - Not_Enable, - -- the RTT alarm signal forces the wake up of the core power supply. - Enable) - with Size => 1; - for RTTEN_Field use - (Not_Enable => 0, - Enable => 1); + subtype RTC_TIMALR_SEC_Field is ATSAM3X8E.UInt7; + subtype RTC_TIMALR_SECEN_Field is ATSAM3X8E.Bit; + subtype RTC_TIMALR_MIN_Field is ATSAM3X8E.UInt7; + subtype RTC_TIMALR_MINEN_Field is ATSAM3X8E.Bit; + subtype RTC_TIMALR_HOUR_Field is ATSAM3X8E.UInt6; + subtype RTC_TIMALR_AMPM_Field is ATSAM3X8E.Bit; + subtype RTC_TIMALR_HOUREN_Field is ATSAM3X8E.Bit; - -- Real Time Clock Wake Up Enable - type RTCEN_Field is - ( - -- the RTC alarm signal has no wake up effect. - Not_Enable, - -- the RTC alarm signal forces the wake up of the core power supply. - Enable) - with Size => 1; - for RTCEN_Field use - (Not_Enable => 0, - Enable => 1); + -- Time Alarm Register + type RTC_TIMALR_Register is record + -- Second Alarm + SEC : RTC_TIMALR_SEC_Field := 16#0#; + -- Second Alarm Enable + SECEN : RTC_TIMALR_SECEN_Field := 16#0#; + -- Minute Alarm + MIN : RTC_TIMALR_MIN_Field := 16#0#; + -- Minute Alarm Enable + MINEN : RTC_TIMALR_MINEN_Field := 16#0#; + -- Hour Alarm + HOUR : RTC_TIMALR_HOUR_Field := 16#0#; + -- AM/PM Indicator + AMPM : RTC_TIMALR_AMPM_Field := 16#0#; + -- Hour Alarm Enable + HOUREN : RTC_TIMALR_HOUREN_Field := 16#0#; + -- unspecified + Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- Force Wake Up Debouncer Period - type FWUPDBC_Field is - ( - -- Immediate, no debouncing, detected active at least on one Slow Clock - -- edge. - Immediate, - -- FWUP shall be low for at least 3 SLCK periods - FWUPDBC_Field_3_Sclk, - -- FWUP shall be low for at least 32 SLCK periods - FWUPDBC_Field_32_Sclk, - -- FWUP shall be low for at least 512 SLCK periods - FWUPDBC_Field_512_Sclk, - -- FWUP shall be low for at least 4,096 SLCK periods - FWUPDBC_Field_4096_Sclk, - -- FWUP shall be low for at least 32,768 SLCK periods - FWUPDBC_Field_32768_Sclk) - with Size => 3; - for FWUPDBC_Field use - (Immediate => 0, - FWUPDBC_Field_3_Sclk => 1, - FWUPDBC_Field_32_Sclk => 2, - FWUPDBC_Field_512_Sclk => 3, - FWUPDBC_Field_4096_Sclk => 4, - FWUPDBC_Field_32768_Sclk => 5); + for RTC_TIMALR_Register use record + SEC at 0 range 0 .. 6; + SECEN at 0 range 7 .. 7; + MIN at 0 range 8 .. 14; + MINEN at 0 range 15 .. 15; + HOUR at 0 range 16 .. 21; + AMPM at 0 range 22 .. 22; + HOUREN at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; - -- Wake Up Inputs Debouncer Period - type WKUPDBC_Field is - ( - -- Immediate, no debouncing, detected active at least on one Slow Clock - -- edge. - Immediate, - -- WKUPx shall be in its active state for at least 3 SLCK periods - WKUPDBC_Field_3_Sclk, - -- WKUPx shall be in its active state for at least 32 SLCK periods - WKUPDBC_Field_32_Sclk, - -- WKUPx shall be in its active state for at least 512 SLCK periods - WKUPDBC_Field_512_Sclk, - -- WKUPx shall be in its active state for at least 4,096 SLCK periods - WKUPDBC_Field_4096_Sclk, - -- WKUPx shall be in its active state for at least 32,768 SLCK periods - WKUPDBC_Field_32768_Sclk) - with Size => 3; - for WKUPDBC_Field use - (Immediate => 0, - WKUPDBC_Field_3_Sclk => 1, - WKUPDBC_Field_32_Sclk => 2, - WKUPDBC_Field_512_Sclk => 3, - WKUPDBC_Field_4096_Sclk => 4, - WKUPDBC_Field_32768_Sclk => 5); + subtype RTC_CALALR_MONTH_Field is ATSAM3X8E.UInt5; + subtype RTC_CALALR_MTHEN_Field is ATSAM3X8E.Bit; + subtype RTC_CALALR_DATE_Field is ATSAM3X8E.UInt6; + subtype RTC_CALALR_DATEEN_Field is ATSAM3X8E.Bit; - -- Supply Controller Wake Up Mode Register - type WUMR_Register is record - -- Force Wake Up Enable - FWUPEN : FWUPEN_Field := Not_Enable; - -- Supply Monitor Wake Up Enable - SMEN : SMEN_Field := Not_Enable; - -- Real Time Timer Wake Up Enable - RTTEN : RTTEN_Field := Not_Enable; - -- Real Time Clock Wake Up Enable - RTCEN : RTCEN_Field := Not_Enable; + -- Calendar Alarm Register + type RTC_CALALR_Register is record -- unspecified - Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; - -- Force Wake Up Debouncer Period - FWUPDBC : FWUPDBC_Field := Immediate; + Reserved_0_15 : ATSAM3X8E.UInt16 := 16#0#; + -- Month Alarm + MONTH : RTC_CALALR_MONTH_Field := 16#1#; -- unspecified - Reserved_11_11 : ATSAM3X8E.Bit := 16#0#; - -- Wake Up Inputs Debouncer Period - WKUPDBC : WKUPDBC_Field := Immediate; + Reserved_21_22 : ATSAM3X8E.UInt2 := 16#0#; + -- Month Alarm Enable + MTHEN : RTC_CALALR_MTHEN_Field := 16#0#; + -- Date Alarm + DATE : RTC_CALALR_DATE_Field := 16#1#; -- unspecified - Reserved_15_31 : ATSAM3X8E.UInt17 := 16#0#; + Reserved_30_30 : ATSAM3X8E.Bit := 16#0#; + -- Date Alarm Enable + DATEEN : RTC_CALALR_DATEEN_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WUMR_Register use record - FWUPEN at 0 range 0 .. 0; - SMEN at 0 range 1 .. 1; - RTTEN at 0 range 2 .. 2; - RTCEN at 0 range 3 .. 3; - Reserved_4_7 at 0 range 4 .. 7; - FWUPDBC at 0 range 8 .. 10; - Reserved_11_11 at 0 range 11 .. 11; - WKUPDBC at 0 range 12 .. 14; - Reserved_15_31 at 0 range 15 .. 31; + for RTC_CALALR_Register use record + Reserved_0_15 at 0 range 0 .. 15; + MONTH at 0 range 16 .. 20; + Reserved_21_22 at 0 range 21 .. 22; + MTHEN at 0 range 23 .. 23; + DATE at 0 range 24 .. 29; + Reserved_30_30 at 0 range 30 .. 30; + DATEEN at 0 range 31 .. 31; end record; - ------------------- - -- WUIR_Register -- - ------------------- - - -- Wake Up Input Enable 0 - type WKUPEN0_Field is - ( - -- the corresponding wake-up input has no wake up effect. - Disable, - -- the corresponding wake-up input forces the wake up of the core power - -- supply. - Enable) - with Size => 1; - for WKUPEN0_Field use - (Disable => 0, - Enable => 1); - - ----------------- - -- WUIR.WKUPEN -- - ----------------- - - -- WUIR_WKUPEN array - type WUIR_WKUPEN_Field_Array is array (0 .. 15) of WKUPEN0_Field - with Component_Size => 1, Size => 16; + subtype RTC_SR_ACKUPD_Field is ATSAM3X8E.Bit; + subtype RTC_SR_ALARM_Field is ATSAM3X8E.Bit; + subtype RTC_SR_SEC_Field is ATSAM3X8E.Bit; + subtype RTC_SR_TIMEV_Field is ATSAM3X8E.Bit; + subtype RTC_SR_CALEV_Field is ATSAM3X8E.Bit; - -- Type definition for WUIR_WKUPEN - type WUIR_WKUPEN_Field - (As_Array : Boolean := False) - is record - case As_Array is - when False => - -- WKUPEN as a value - Val : ATSAM3X8E.Short; - when True => - -- WKUPEN as an array - Arr : WUIR_WKUPEN_Field_Array; - end case; + -- Status Register + type RTC_SR_Register is record + -- Read-only. Acknowledge for Update + ACKUPD : RTC_SR_ACKUPD_Field; + -- Read-only. Alarm Flag + ALARM : RTC_SR_ALARM_Field; + -- Read-only. Second Event + SEC : RTC_SR_SEC_Field; + -- Read-only. Time Event + TIMEV : RTC_SR_TIMEV_Field; + -- Read-only. Calendar Event + CALEV : RTC_SR_CALEV_Field; + -- unspecified + Reserved_5_31 : ATSAM3X8E.UInt27; end record - with Unchecked_Union, Size => 16; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WUIR_WKUPEN_Field use record - Val at 0 range 0 .. 15; - Arr at 0 range 0 .. 15; + for RTC_SR_Register use record + ACKUPD at 0 range 0 .. 0; + ALARM at 0 range 1 .. 1; + SEC at 0 range 2 .. 2; + TIMEV at 0 range 3 .. 3; + CALEV at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; end record; - -- Wake Up Input Type 0 - type WKUPT0_Field is - ( - -- a high to low level transition for a period defined by WKUPDBC on the - -- corresponding wake-up input forces the wake up of the core power - -- supply. - High_To_Low, - -- a low to high level transition for a period defined by WKUPDBC on the - -- correspond-ing wake-up input forces the wake up of the core power - -- supply. - Low_To_High) - with Size => 1; - for WKUPT0_Field use - (High_To_Low => 0, - Low_To_High => 1); + subtype RTC_SCCR_ACKCLR_Field is ATSAM3X8E.Bit; + subtype RTC_SCCR_ALRCLR_Field is ATSAM3X8E.Bit; + subtype RTC_SCCR_SECCLR_Field is ATSAM3X8E.Bit; + subtype RTC_SCCR_TIMCLR_Field is ATSAM3X8E.Bit; + subtype RTC_SCCR_CALCLR_Field is ATSAM3X8E.Bit; - ---------------- - -- WUIR.WKUPT -- - ---------------- + -- Status Clear Command Register + type RTC_SCCR_Register is record + -- Write-only. Acknowledge Clear + ACKCLR : RTC_SCCR_ACKCLR_Field := 16#0#; + -- Write-only. Alarm Clear + ALRCLR : RTC_SCCR_ALRCLR_Field := 16#0#; + -- Write-only. Second Clear + SECCLR : RTC_SCCR_SECCLR_Field := 16#0#; + -- Write-only. Time Clear + TIMCLR : RTC_SCCR_TIMCLR_Field := 16#0#; + -- Write-only. Calendar Clear + CALCLR : RTC_SCCR_CALCLR_Field := 16#0#; + -- unspecified + Reserved_5_31 : ATSAM3X8E.UInt27 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTC_SCCR_Register use record + ACKCLR at 0 range 0 .. 0; + ALRCLR at 0 range 1 .. 1; + SECCLR at 0 range 2 .. 2; + TIMCLR at 0 range 3 .. 3; + CALCLR at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype RTC_IER_ACKEN_Field is ATSAM3X8E.Bit; + subtype RTC_IER_ALREN_Field is ATSAM3X8E.Bit; + subtype RTC_IER_SECEN_Field is ATSAM3X8E.Bit; + subtype RTC_IER_TIMEN_Field is ATSAM3X8E.Bit; + subtype RTC_IER_CALEN_Field is ATSAM3X8E.Bit; + + -- Interrupt Enable Register + type RTC_IER_Register is record + -- Write-only. Acknowledge Update Interrupt Enable + ACKEN : RTC_IER_ACKEN_Field := 16#0#; + -- Write-only. Alarm Interrupt Enable + ALREN : RTC_IER_ALREN_Field := 16#0#; + -- Write-only. Second Event Interrupt Enable + SECEN : RTC_IER_SECEN_Field := 16#0#; + -- Write-only. Time Event Interrupt Enable + TIMEN : RTC_IER_TIMEN_Field := 16#0#; + -- Write-only. Calendar Event Interrupt Enable + CALEN : RTC_IER_CALEN_Field := 16#0#; + -- unspecified + Reserved_5_31 : ATSAM3X8E.UInt27 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTC_IER_Register use record + ACKEN at 0 range 0 .. 0; + ALREN at 0 range 1 .. 1; + SECEN at 0 range 2 .. 2; + TIMEN at 0 range 3 .. 3; + CALEN at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype RTC_IDR_ACKDIS_Field is ATSAM3X8E.Bit; + subtype RTC_IDR_ALRDIS_Field is ATSAM3X8E.Bit; + subtype RTC_IDR_SECDIS_Field is ATSAM3X8E.Bit; + subtype RTC_IDR_TIMDIS_Field is ATSAM3X8E.Bit; + subtype RTC_IDR_CALDIS_Field is ATSAM3X8E.Bit; + + -- Interrupt Disable Register + type RTC_IDR_Register is record + -- Write-only. Acknowledge Update Interrupt Disable + ACKDIS : RTC_IDR_ACKDIS_Field := 16#0#; + -- Write-only. Alarm Interrupt Disable + ALRDIS : RTC_IDR_ALRDIS_Field := 16#0#; + -- Write-only. Second Event Interrupt Disable + SECDIS : RTC_IDR_SECDIS_Field := 16#0#; + -- Write-only. Time Event Interrupt Disable + TIMDIS : RTC_IDR_TIMDIS_Field := 16#0#; + -- Write-only. Calendar Event Interrupt Disable + CALDIS : RTC_IDR_CALDIS_Field := 16#0#; + -- unspecified + Reserved_5_31 : ATSAM3X8E.UInt27 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTC_IDR_Register use record + ACKDIS at 0 range 0 .. 0; + ALRDIS at 0 range 1 .. 1; + SECDIS at 0 range 2 .. 2; + TIMDIS at 0 range 3 .. 3; + CALDIS at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype RTC_IMR_ACK_Field is ATSAM3X8E.Bit; + subtype RTC_IMR_ALR_Field is ATSAM3X8E.Bit; + subtype RTC_IMR_SEC_Field is ATSAM3X8E.Bit; + subtype RTC_IMR_TIM_Field is ATSAM3X8E.Bit; + subtype RTC_IMR_CAL_Field is ATSAM3X8E.Bit; + + -- Interrupt Mask Register + type RTC_IMR_Register is record + -- Read-only. Acknowledge Update Interrupt Mask + ACK : RTC_IMR_ACK_Field; + -- Read-only. Alarm Interrupt Mask + ALR : RTC_IMR_ALR_Field; + -- Read-only. Second Event Interrupt Mask + SEC : RTC_IMR_SEC_Field; + -- Read-only. Time Event Interrupt Mask + TIM : RTC_IMR_TIM_Field; + -- Read-only. Calendar Event Interrupt Mask + CAL : RTC_IMR_CAL_Field; + -- unspecified + Reserved_5_31 : ATSAM3X8E.UInt27; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTC_IMR_Register use record + ACK at 0 range 0 .. 0; + ALR at 0 range 1 .. 1; + SEC at 0 range 2 .. 2; + TIM at 0 range 3 .. 3; + CAL at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype RTC_VER_NVTIM_Field is ATSAM3X8E.Bit; + subtype RTC_VER_NVCAL_Field is ATSAM3X8E.Bit; + subtype RTC_VER_NVTIMALR_Field is ATSAM3X8E.Bit; + subtype RTC_VER_NVCALALR_Field is ATSAM3X8E.Bit; + + -- Valid Entry Register + type RTC_VER_Register is record + -- Read-only. Non-valid Time + NVTIM : RTC_VER_NVTIM_Field; + -- Read-only. Non-valid Calendar + NVCAL : RTC_VER_NVCAL_Field; + -- Read-only. Non-valid Time Alarm + NVTIMALR : RTC_VER_NVTIMALR_Field; + -- Read-only. Non-valid Calendar Alarm + NVCALALR : RTC_VER_NVCALALR_Field; + -- unspecified + Reserved_4_31 : ATSAM3X8E.UInt28; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTC_VER_Register use record + NVTIM at 0 range 0 .. 0; + NVCAL at 0 range 1 .. 1; + NVTIMALR at 0 range 2 .. 2; + NVCALALR at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype RTC_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype RTC_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + + -- Write Protect Mode Register + type RTC_WPMR_Register is record + -- Write Protect Enable + WPEN : RTC_WPMR_WPEN_Field := 16#0#; + -- unspecified + Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; + WPKEY : RTC_WPMR_WPKEY_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype RTT_MR_RTPRES_Field is ATSAM3X8E.UInt16; + subtype RTT_MR_ALMIEN_Field is ATSAM3X8E.Bit; + subtype RTT_MR_RTTINCIEN_Field is ATSAM3X8E.Bit; + subtype RTT_MR_RTTRST_Field is ATSAM3X8E.Bit; + + -- Mode Register + type RTT_MR_Register is record + -- Real-time Timer Prescaler Value + RTPRES : RTT_MR_RTPRES_Field := 16#8000#; + -- Alarm Interrupt Enable + ALMIEN : RTT_MR_ALMIEN_Field := 16#0#; + -- Real-time Timer Increment Interrupt Enable + RTTINCIEN : RTT_MR_RTTINCIEN_Field := 16#0#; + -- Real-time Timer Restart + RTTRST : RTT_MR_RTTRST_Field := 16#0#; + -- unspecified + Reserved_19_31 : ATSAM3X8E.UInt13 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTT_MR_Register use record + RTPRES at 0 range 0 .. 15; + ALMIEN at 0 range 16 .. 16; + RTTINCIEN at 0 range 17 .. 17; + RTTRST at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype RTT_SR_ALMS_Field is ATSAM3X8E.Bit; + subtype RTT_SR_RTTINC_Field is ATSAM3X8E.Bit; + + -- Status Register + type RTT_SR_Register is record + -- Read-only. Real-time Alarm Status + ALMS : RTT_SR_ALMS_Field; + -- Read-only. Real-time Timer Increment + RTTINC : RTT_SR_RTTINC_Field; + -- unspecified + Reserved_2_31 : ATSAM3X8E.UInt30; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for RTT_SR_Register use record + ALMS at 0 range 0 .. 0; + RTTINC at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Voltage Regulator Off + type CR_VROFF_Field is + (-- no effect. + No_Effect, + -- if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. + Stop_Vreg) + with Size => 1; + for CR_VROFF_Field use + (No_Effect => 0, + Stop_Vreg => 1); + + -- Crystal Oscillator Select + type CR_XTALSEL_Field is + (-- no effect. + No_Effect, + -- if KEY is correct, switches the slow clock on the crystal oscillator +-- output. + Crystal_Sel) + with Size => 1; + for CR_XTALSEL_Field use + (No_Effect => 0, + Crystal_Sel => 1); + + subtype SUPC_CR_KEY_Field is ATSAM3X8E.Byte; + + -- Supply Controller Control Register + type SUPC_CR_Register is record + -- unspecified + Reserved_0_1 : ATSAM3X8E.UInt2 := 16#0#; + -- Write-only. Voltage Regulator Off + VROFF : CR_VROFF_Field := ATSAM3X8E.SYSC.No_Effect; + -- Write-only. Crystal Oscillator Select + XTALSEL : CR_XTALSEL_Field := ATSAM3X8E.SYSC.No_Effect; + -- unspecified + Reserved_4_23 : ATSAM3X8E.UInt20 := 16#0#; + -- Write-only. Password + KEY : SUPC_CR_KEY_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SUPC_CR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + VROFF at 0 range 2 .. 2; + XTALSEL at 0 range 3 .. 3; + Reserved_4_23 at 0 range 4 .. 23; + KEY at 0 range 24 .. 31; + end record; + + -- Supply Monitor Threshold + type SMMR_SMTH_Field is + (-- 1.9 V + Val_1_9V, + -- 2.0 V + Val_2_0V, + -- 2.1 V + Val_2_1V, + -- 2.2 V + Val_2_2V, + -- 2.3 V + Val_2_3V, + -- 2.4 V + Val_2_4V, + -- 2.5 V + Val_2_5V, + -- 2.6 V + Val_2_6V, + -- 2.7 V + Val_2_7V, + -- 2.8 V + Val_2_8V, + -- 2.9 V + Val_2_9V, + -- 3.0 V + Val_3_0V, + -- 3.1 V + Val_3_1V, + -- 3.2 V + Val_3_2V, + -- 3.3 V + Val_3_3V, + -- 3.4 V + Val_3_4V) + with Size => 4; + for SMMR_SMTH_Field use + (Val_1_9V => 0, + Val_2_0V => 1, + Val_2_1V => 2, + Val_2_2V => 3, + Val_2_3V => 4, + Val_2_4V => 5, + Val_2_5V => 6, + Val_2_6V => 7, + Val_2_7V => 8, + Val_2_8V => 9, + Val_2_9V => 10, + Val_3_0V => 11, + Val_3_1V => 12, + Val_3_2V => 13, + Val_3_3V => 14, + Val_3_4V => 15); + + -- Supply Monitor Sampling Period + type SMMR_SMSMPL_Field is + (-- Supply Monitor disabled + Smd, + -- Continuous Supply Monitor + Csm, + -- Supply Monitor enabled one SLCK period every 32 SLCK periods + Val_32Slck, + -- Supply Monitor enabled one SLCK period every 256 SLCK periods + Val_256Slck, + -- Supply Monitor enabled one SLCK period every 2,048 SLCK periods + Val_2048Slck) + with Size => 3; + for SMMR_SMSMPL_Field use + (Smd => 0, + Csm => 1, + Val_32Slck => 2, + Val_256Slck => 3, + Val_2048Slck => 4); + + -- Supply Monitor Reset Enable + type SMMR_SMRSTEN_Field is + (-- the core reset signal "vddcore_nreset" is not affected when a supply +-- monitor detection occurs. + Not_Enable, + -- the core reset signal, vddcore_nreset is asserted when a supply monitor +-- detection occurs. + Enable) + with Size => 1; + for SMMR_SMRSTEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Supply Monitor Interrupt Enable + type SMMR_SMIEN_Field is + (-- the SUPC interrupt signal is not affected when a supply monitor detection +-- occurs. + Not_Enable, + -- the SUPC interrupt signal is asserted when a supply monitor detection +-- occurs. + Enable) + with Size => 1; + for SMMR_SMIEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Supply Controller Supply Monitor Mode Register + type SUPC_SMMR_Register is record + -- Supply Monitor Threshold + SMTH : SMMR_SMTH_Field := ATSAM3X8E.SYSC.Val_1_9V; + -- unspecified + Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; + -- Supply Monitor Sampling Period + SMSMPL : SMMR_SMSMPL_Field := ATSAM3X8E.SYSC.Smd; + -- unspecified + Reserved_11_11 : ATSAM3X8E.Bit := 16#0#; + -- Supply Monitor Reset Enable + SMRSTEN : SMMR_SMRSTEN_Field := ATSAM3X8E.SYSC.Not_Enable; + -- Supply Monitor Interrupt Enable + SMIEN : SMMR_SMIEN_Field := ATSAM3X8E.SYSC.Not_Enable; + -- unspecified + Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SUPC_SMMR_Register use record + SMTH at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + SMSMPL at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + SMRSTEN at 0 range 12 .. 12; + SMIEN at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Brownout Detector Reset Enable + type MR_BODRSTEN_Field is + (-- the core reset signal "vddcore_nreset" is not affected when a brownout +-- detection occurs. + Not_Enable, + -- the core reset signal, vddcore_nreset is asserted when a brownout detection +-- occurs. + Enable) + with Size => 1; + for MR_BODRSTEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Brownout Detector Disable + type MR_BODDIS_Field is + (-- the core brownout detector is enabled. + Enable, + -- the core brownout detector is disabled. + Disable) + with Size => 1; + for MR_BODDIS_Field use + (Enable => 0, + Disable => 1); + + subtype SUPC_MR_VDDIORDYONREG_Field is ATSAM3X8E.Bit; + + -- Oscillator Bypass + type MR_OSCBYPASS_Field is + (-- no effect. Clock selection depends on XTALSEL value. + No_Effect, + -- the 32-KHz XTAL oscillator is selected and is put in bypass mode. + Bypass) + with Size => 1; + for MR_OSCBYPASS_Field use + (No_Effect => 0, + Bypass => 1); + + subtype SUPC_MR_KEY_Field is ATSAM3X8E.Byte; + + -- Supply Controller Mode Register + type SUPC_MR_Register is record + -- unspecified + Reserved_0_11 : ATSAM3X8E.UInt12 := 16#A00#; + -- Brownout Detector Reset Enable + BODRSTEN : MR_BODRSTEN_Field := ATSAM3X8E.SYSC.Enable; + -- Brownout Detector Disable + BODDIS : MR_BODDIS_Field := ATSAM3X8E.SYSC.Enable; + VDDIORDYONREG : SUPC_MR_VDDIORDYONREG_Field := 16#1#; + -- unspecified + Reserved_15_19 : ATSAM3X8E.UInt5 := 16#0#; + -- Oscillator Bypass + OSCBYPASS : MR_OSCBYPASS_Field := ATSAM3X8E.SYSC.No_Effect; + -- unspecified + Reserved_21_23 : ATSAM3X8E.UInt3 := 16#0#; + -- Password Key + KEY : SUPC_MR_KEY_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SUPC_MR_Register use record + Reserved_0_11 at 0 range 0 .. 11; + BODRSTEN at 0 range 12 .. 12; + BODDIS at 0 range 13 .. 13; + VDDIORDYONREG at 0 range 14 .. 14; + Reserved_15_19 at 0 range 15 .. 19; + OSCBYPASS at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + KEY at 0 range 24 .. 31; + end record; + + -- Force Wake Up Enable + type WUMR_FWUPEN_Field is + (-- the Force Wake Up pin has no wake up effect. + Not_Enable, + -- the Force Wake Up pin low forces the wake up of the core power supply. + Enable) + with Size => 1; + for WUMR_FWUPEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Supply Monitor Wake Up Enable + type WUMR_SMEN_Field is + (-- the supply monitor detection has no wake up effect. + Not_Enable, + -- the supply monitor detection forces the wake up of the core power supply. + Enable) + with Size => 1; + for WUMR_SMEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Real Time Timer Wake Up Enable + type WUMR_RTTEN_Field is + (-- the RTT alarm signal has no wake up effect. + Not_Enable, + -- the RTT alarm signal forces the wake up of the core power supply. + Enable) + with Size => 1; + for WUMR_RTTEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Real Time Clock Wake Up Enable + type WUMR_RTCEN_Field is + (-- the RTC alarm signal has no wake up effect. + Not_Enable, + -- the RTC alarm signal forces the wake up of the core power supply. + Enable) + with Size => 1; + for WUMR_RTCEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Force Wake Up Debouncer Period + type WUMR_FWUPDBC_Field is + (-- Immediate, no debouncing, detected active at least on one Slow Clock edge. + Immediate, + -- FWUP shall be low for at least 3 SLCK periods + Val_3_Sclk, + -- FWUP shall be low for at least 32 SLCK periods + Val_32_Sclk, + -- FWUP shall be low for at least 512 SLCK periods + Val_512_Sclk, + -- FWUP shall be low for at least 4,096 SLCK periods + Val_4096_Sclk, + -- FWUP shall be low for at least 32,768 SLCK periods + Val_32768_Sclk) + with Size => 3; + for WUMR_FWUPDBC_Field use + (Immediate => 0, + Val_3_Sclk => 1, + Val_32_Sclk => 2, + Val_512_Sclk => 3, + Val_4096_Sclk => 4, + Val_32768_Sclk => 5); + + -- Wake Up Inputs Debouncer Period + type WUMR_WKUPDBC_Field is + (-- Immediate, no debouncing, detected active at least on one Slow Clock edge. + Immediate, + -- WKUPx shall be in its active state for at least 3 SLCK periods + Val_3_Sclk, + -- WKUPx shall be in its active state for at least 32 SLCK periods + Val_32_Sclk, + -- WKUPx shall be in its active state for at least 512 SLCK periods + Val_512_Sclk, + -- WKUPx shall be in its active state for at least 4,096 SLCK periods + Val_4096_Sclk, + -- WKUPx shall be in its active state for at least 32,768 SLCK periods + Val_32768_Sclk) + with Size => 3; + for WUMR_WKUPDBC_Field use + (Immediate => 0, + Val_3_Sclk => 1, + Val_32_Sclk => 2, + Val_512_Sclk => 3, + Val_4096_Sclk => 4, + Val_32768_Sclk => 5); + + -- Supply Controller Wake Up Mode Register + type SUPC_WUMR_Register is record + -- Force Wake Up Enable + FWUPEN : WUMR_FWUPEN_Field := ATSAM3X8E.SYSC.Not_Enable; + -- Supply Monitor Wake Up Enable + SMEN : WUMR_SMEN_Field := ATSAM3X8E.SYSC.Not_Enable; + -- Real Time Timer Wake Up Enable + RTTEN : WUMR_RTTEN_Field := ATSAM3X8E.SYSC.Not_Enable; + -- Real Time Clock Wake Up Enable + RTCEN : WUMR_RTCEN_Field := ATSAM3X8E.SYSC.Not_Enable; + -- unspecified + Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; + -- Force Wake Up Debouncer Period + FWUPDBC : WUMR_FWUPDBC_Field := ATSAM3X8E.SYSC.Immediate; + -- unspecified + Reserved_11_11 : ATSAM3X8E.Bit := 16#0#; + -- Wake Up Inputs Debouncer Period + WKUPDBC : WUMR_WKUPDBC_Field := ATSAM3X8E.SYSC.Immediate; + -- unspecified + Reserved_15_31 : ATSAM3X8E.UInt17 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SUPC_WUMR_Register use record + FWUPEN at 0 range 0 .. 0; + SMEN at 0 range 1 .. 1; + RTTEN at 0 range 2 .. 2; + RTCEN at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + FWUPDBC at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + WKUPDBC at 0 range 12 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Wake Up Input Enable 0 + type WUIR_WKUPEN0_Field is + (-- the corresponding wake-up input has no wake up effect. + Disable, + -- the corresponding wake-up input forces the wake up of the core power +-- supply. + Enable) + with Size => 1; + for WUIR_WKUPEN0_Field use + (Disable => 0, + Enable => 1); + + -- SUPC_WUIR_WKUPEN array + type SUPC_WUIR_WKUPEN_Field_Array is array (0 .. 15) of WUIR_WKUPEN0_Field + with Component_Size => 1, Size => 16; + + -- Type definition for SUPC_WUIR_WKUPEN + type SUPC_WUIR_WKUPEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WKUPEN as a value + Val : ATSAM3X8E.UInt16; + when True => + -- WKUPEN as an array + Arr : SUPC_WUIR_WKUPEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for SUPC_WUIR_WKUPEN_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Wake Up Input Type 0 + type WUIR_WKUPT0_Field is + (-- a high to low level transition for a period defined by WKUPDBC on the +-- corresponding wake-up input forces the wake up of the core power supply. + High_To_Low, + -- a low to high level transition for a period defined by WKUPDBC on the +-- correspond-ing wake-up input forces the wake up of the core power supply. + Low_To_High) + with Size => 1; + for WUIR_WKUPT0_Field use + (High_To_Low => 0, + Low_To_High => 1); - -- WUIR_WKUPT array - type WUIR_WKUPT_Field_Array is array (0 .. 15) of WKUPT0_Field + -- SUPC_WUIR_WKUPT array + type SUPC_WUIR_WKUPT_Field_Array is array (0 .. 15) of WUIR_WKUPT0_Field with Component_Size => 1, Size => 16; - -- Type definition for WUIR_WKUPT - type WUIR_WKUPT_Field + -- Type definition for SUPC_WUIR_WKUPT + type SUPC_WUIR_WKUPT_Field (As_Array : Boolean := False) is record case As_Array is when False => -- WKUPT as a value - Val : ATSAM3X8E.Short; + Val : ATSAM3X8E.UInt16; when True => -- WKUPT as an array - Arr : WUIR_WKUPT_Field_Array; + Arr : SUPC_WUIR_WKUPT_Field_Array; end case; end record with Unchecked_Union, Size => 16; - for WUIR_WKUPT_Field use record + for SUPC_WUIR_WKUPT_Field use record Val at 0 range 0 .. 15; Arr at 0 range 0 .. 15; end record; -- Supply Controller Wake Up Inputs Register - type WUIR_Register is record + type SUPC_WUIR_Register is record -- Wake Up Input Enable 0 - WKUPEN : WUIR_WKUPEN_Field := (As_Array => False, Val => 16#0#); + WKUPEN : SUPC_WUIR_WKUPEN_Field := (As_Array => False, Val => 16#0#); -- Wake Up Input Type 0 - WKUPT : WUIR_WKUPT_Field := (As_Array => False, Val => 16#0#); + WKUPT : SUPC_WUIR_WKUPT_Field := (As_Array => False, Val => 16#0#); end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WUIR_Register use record + for SUPC_WUIR_Register use record WKUPEN at 0 range 0 .. 15; WKUPT at 0 range 16 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - -- FWUP Wake Up Status - type FWUPS_Field is - ( - -- no wake up due to the assertion of the FWUP pin has occurred since - -- the last read of SUPC_SR. + type SR_FWUPS_Field is + (-- no wake up due to the assertion of the FWUP pin has occurred since the last +-- read of SUPC_SR. No, - -- at least one wake up due to the assertion of the FWUP pin has - -- occurred since the last read of SUPC_SR. + -- at least one wake up due to the assertion of the FWUP pin has occurred +-- since the last read of SUPC_SR. Present) with Size => 1; - for FWUPS_Field use + for SR_FWUPS_Field use (No => 0, Present => 1); -- WKUP Wake Up Status - type WKUPS_Field is - ( - -- no wake up due to the assertion of the WKUP pins has occurred since - -- the last read of SUPC_SR. + type SR_WKUPS_Field is + (-- no wake up due to the assertion of the WKUP pins has occurred since the +-- last read of SUPC_SR. No, - -- at least one wake up due to the assertion of the WKUP pins has - -- occurred since the last read of SUPC_SR. + -- at least one wake up due to the assertion of the WKUP pins has occurred +-- since the last read of SUPC_SR. Present) with Size => 1; - for WKUPS_Field use + for SR_WKUPS_Field use (No => 0, Present => 1); -- Supply Monitor Detection Wake Up Status - type SMWS_Field is - ( - -- no wake up due to a supply monitor detection has occurred since the - -- last read of SUPC_SR. + type SR_SMWS_Field is + (-- no wake up due to a supply monitor detection has occurred since the last +-- read of SUPC_SR. No, - -- at least one wake up due to a supply monitor detection has occurred - -- since the last read of SUPC_SR. + -- at least one wake up due to a supply monitor detection has occurred since +-- the last read of SUPC_SR. Present) with Size => 1; - for SMWS_Field use + for SR_SMWS_Field use (No => 0, Present => 1); -- Brownout Detector Reset Status - type BODRSTS_Field is - ( - -- no core brownout rising edge event has been detected since the last - -- read of the SUPC_SR. + type SR_BODRSTS_Field is + (-- no core brownout rising edge event has been detected since the last read of +-- the SUPC_SR. No, - -- at least one brownout output rising edge event has been detected - -- since the last read of the SUPC_SR. + -- at least one brownout output rising edge event has been detected since the +-- last read of the SUPC_SR. Present) with Size => 1; - for BODRSTS_Field use + for SR_BODRSTS_Field use (No => 0, Present => 1); -- Supply Monitor Reset Status - type SMRSTS_Field is - ( - -- no supply monitor detection has generated a core reset since the last - -- read of the SUPC_SR. + type SR_SMRSTS_Field is + (-- no supply monitor detection has generated a core reset since the last read +-- of the SUPC_SR. No, - -- at least one supply monitor detection has generated a core reset - -- since the last read of the SUPC_SR. + -- at least one supply monitor detection has generated a core reset since the +-- last read of the SUPC_SR. Present) with Size => 1; - for SMRSTS_Field use + for SR_SMRSTS_Field use (No => 0, Present => 1); -- Supply Monitor Status - type SMS_Field is - ( - -- no supply monitor detection since the last read of SUPC_SR. + type SR_SMS_Field is + (-- no supply monitor detection since the last read of SUPC_SR. No, -- at least one supply monitor detection since the last read of SUPC_SR. Present) with Size => 1; - for SMS_Field use + for SR_SMS_Field use (No => 0, Present => 1); -- Supply Monitor Output Status - type SMOS_Field is - ( - -- the supply monitor detected VDDUTMI higher than its threshold at its - -- last measurement. + type SR_SMOS_Field is + (-- the supply monitor detected VDDUTMI higher than its threshold at its last +-- measurement. High, - -- the supply monitor detected VDDUTMI lower than its threshold at its - -- last measurement. + -- the supply monitor detected VDDUTMI lower than its threshold at its last +-- measurement. Low) with Size => 1; - for SMOS_Field use + for SR_SMOS_Field use (High => 0, Low => 1); -- 32-kHz Oscillator Selection Status - type OSCSEL_Field is - ( - -- the slow clock, SLCK is generated by the embedded 32-kHz RC - -- oscillator. + type SR_OSCSEL_Field is + (-- the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. Rc, -- the slow clock, SLCK is generated by the 32-kHz crystal oscillator. Cryst) with Size => 1; - for OSCSEL_Field use + for SR_OSCSEL_Field use (Rc => 0, Cryst => 1); -- FWUP Input Status - type FWUPIS_Field is - ( - -- FWUP input is tied low. + type SR_FWUPIS_Field is + (-- FWUP input is tied low. Low, -- FWUP input is tied high. High) with Size => 1; - for FWUPIS_Field use + for SR_FWUPIS_Field use (Low => 0, High => 1); - -- WKUP Input Status 0 - type WKUPIS0_Field is - ( - -- the corresponding wake-up input is disabled, or was inactive at the - -- time the debouncer triggered a wake up event. - Dis, - -- the corresponding wake-up input was active at the time the debouncer - -- triggered a wake up event. - En) - with Size => 1; - for WKUPIS0_Field use - (Dis => 0, - En => 1); - - --------------- - -- SR.WKUPIS -- - --------------- - - -- SR_WKUPIS array - type SR_WKUPIS_Field_Array is array (0 .. 15) of WKUPIS0_Field - with Component_Size => 1, Size => 16; - - -- Type definition for SR_WKUPIS - type SR_WKUPIS_Field - (As_Array : Boolean := False) - is record - case As_Array is - when False => - -- WKUPIS as a value - Val : ATSAM3X8E.Short; - when True => - -- WKUPIS as an array - Arr : SR_WKUPIS_Field_Array; - end case; - end record - with Unchecked_Union, Size => 16; - - for SR_WKUPIS_Field use record - Val at 0 range 0 .. 15; - Arr at 0 range 0 .. 15; - end record; - - -- Supply Controller Status Register - type SR_Register_1 is record - -- Read-only. FWUP Wake Up Status - FWUPS : FWUPS_Field := No; - -- Read-only. WKUP Wake Up Status - WKUPS : WKUPS_Field := No; - -- Read-only. Supply Monitor Detection Wake Up Status - SMWS : SMWS_Field := No; - -- Read-only. Brownout Detector Reset Status - BODRSTS : BODRSTS_Field := No; - -- Read-only. Supply Monitor Reset Status - SMRSTS : SMRSTS_Field := No; - -- Read-only. Supply Monitor Status - SMS : SMS_Field := No; - -- Read-only. Supply Monitor Output Status - SMOS : SMOS_Field := High; - -- Read-only. 32-kHz Oscillator Selection Status - OSCSEL : OSCSEL_Field := Rc; - -- unspecified - Reserved_8_11 : ATSAM3X8E.UInt4; - -- Read-only. FWUP Input Status - FWUPIS : FWUPIS_Field := Low; - -- unspecified - Reserved_13_15 : ATSAM3X8E.UInt3; - -- Read-only. WKUP Input Status 0 - WKUPIS : SR_WKUPIS_Field := (As_Array => False, Val => 16#0#); - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for SR_Register_1 use record - FWUPS at 0 range 0 .. 0; - WKUPS at 0 range 1 .. 1; - SMWS at 0 range 2 .. 2; - BODRSTS at 0 range 3 .. 3; - SMRSTS at 0 range 4 .. 4; - SMS at 0 range 5 .. 5; - SMOS at 0 range 6 .. 6; - OSCSEL at 0 range 7 .. 7; - Reserved_8_11 at 0 range 8 .. 11; - FWUPIS at 0 range 12 .. 12; - Reserved_13_15 at 0 range 13 .. 15; - WKUPIS at 0 range 16 .. 31; - end record; - - ----------------- - -- MR_Register -- - ----------------- - - subtype MR_RTPRES_Field is ATSAM3X8E.Short; - subtype MR_ALMIEN_Field is ATSAM3X8E.Bit; - subtype MR_RTTINCIEN_Field is ATSAM3X8E.Bit; - subtype MR_RTTRST_Field is ATSAM3X8E.Bit; - - -- Mode Register - type MR_Register_1 is record - -- Real-time Timer Prescaler Value - RTPRES : MR_RTPRES_Field := 16#8000#; - -- Alarm Interrupt Enable - ALMIEN : MR_ALMIEN_Field := 16#0#; - -- Real-time Timer Increment Interrupt Enable - RTTINCIEN : MR_RTTINCIEN_Field := 16#0#; - -- Real-time Timer Restart - RTTRST : MR_RTTRST_Field := 16#0#; - -- unspecified - Reserved_19_31 : ATSAM3X8E.UInt13 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for MR_Register_1 use record - RTPRES at 0 range 0 .. 15; - ALMIEN at 0 range 16 .. 16; - RTTINCIEN at 0 range 17 .. 17; - RTTRST at 0 range 18 .. 18; - Reserved_19_31 at 0 range 19 .. 31; - end record; - - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_ALMS_Field is ATSAM3X8E.Bit; - subtype SR_RTTINC_Field is ATSAM3X8E.Bit; - - -- Status Register - type SR_Register_2 is record - -- Read-only. Real-time Alarm Status - ALMS : SR_ALMS_Field := 16#0#; - -- Read-only. Real-time Timer Increment - RTTINC : SR_RTTINC_Field := 16#0#; - -- unspecified - Reserved_2_31 : ATSAM3X8E.UInt30; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for SR_Register_2 use record - ALMS at 0 range 0 .. 0; - RTTINC at 0 range 1 .. 1; - Reserved_2_31 at 0 range 2 .. 31; - end record; - - ----------------- - -- MR_Register -- - ----------------- - - subtype MR_WDV_Field is ATSAM3X8E.UInt12; - subtype MR_WDFIEN_Field is ATSAM3X8E.Bit; - subtype MR_WDRSTEN_Field is ATSAM3X8E.Bit; - subtype MR_WDRPROC_Field is ATSAM3X8E.Bit; - subtype MR_WDDIS_Field is ATSAM3X8E.Bit; - subtype MR_WDD_Field is ATSAM3X8E.UInt12; - subtype MR_WDDBGHLT_Field is ATSAM3X8E.Bit; - subtype MR_WDIDLEHLT_Field is ATSAM3X8E.Bit; - - -- Mode Register - type MR_Register_2 is record - -- Watchdog Counter Value - WDV : MR_WDV_Field := 16#FFF#; - -- Watchdog Fault Interrupt Enable - WDFIEN : MR_WDFIEN_Field := 16#0#; - -- Watchdog Reset Enable - WDRSTEN : MR_WDRSTEN_Field := 16#1#; - -- Watchdog Reset Processor - WDRPROC : MR_WDRPROC_Field := 16#0#; - -- Watchdog Disable - WDDIS : MR_WDDIS_Field := 16#0#; - -- Watchdog Delta Value - WDD : MR_WDD_Field := 16#FFF#; - -- Watchdog Debug Halt - WDDBGHLT : MR_WDDBGHLT_Field := 16#1#; - -- Watchdog Idle Halt - WDIDLEHLT : MR_WDIDLEHLT_Field := 16#1#; - -- unspecified - Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for MR_Register_2 use record - WDV at 0 range 0 .. 11; - WDFIEN at 0 range 12 .. 12; - WDRSTEN at 0 range 13 .. 13; - WDRPROC at 0 range 14 .. 14; - WDDIS at 0 range 15 .. 15; - WDD at 0 range 16 .. 27; - WDDBGHLT at 0 range 28 .. 28; - WDIDLEHLT at 0 range 29 .. 29; - Reserved_30_31 at 0 range 30 .. 31; - end record; - - ------------------- - -- TIMR_Register -- - ------------------- - - subtype TIMR_SEC_Field is ATSAM3X8E.UInt7; - subtype TIMR_MIN_Field is ATSAM3X8E.UInt7; - subtype TIMR_HOUR_Field is ATSAM3X8E.UInt6; - subtype TIMR_AMPM_Field is ATSAM3X8E.Bit; - - -- Time Register - type TIMR_Register is record - -- Current Second - SEC : TIMR_SEC_Field := 16#0#; - -- unspecified - Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; - -- Current Minute - MIN : TIMR_MIN_Field := 16#0#; - -- unspecified - Reserved_15_15 : ATSAM3X8E.Bit := 16#0#; - -- Current Hour - HOUR : TIMR_HOUR_Field := 16#0#; - -- Ante Meridiem Post Meridiem Indicator - AMPM : TIMR_AMPM_Field := 16#0#; - -- unspecified - Reserved_23_31 : ATSAM3X8E.UInt9 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for TIMR_Register use record - SEC at 0 range 0 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - MIN at 0 range 8 .. 14; - Reserved_15_15 at 0 range 15 .. 15; - HOUR at 0 range 16 .. 21; - AMPM at 0 range 22 .. 22; - Reserved_23_31 at 0 range 23 .. 31; - end record; - - ------------------- - -- CALR_Register -- - ------------------- - - subtype CALR_CENT_Field is ATSAM3X8E.UInt7; - subtype CALR_YEAR_Field is ATSAM3X8E.Byte; - subtype CALR_MONTH_Field is ATSAM3X8E.UInt5; - subtype CALR_DAY_Field is ATSAM3X8E.UInt3; - subtype CALR_DATE_Field is ATSAM3X8E.UInt6; - - -- Calendar Register - type CALR_Register is record - -- Current Century - CENT : CALR_CENT_Field := 16#20#; - -- unspecified - Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; - -- Current Year - YEAR : CALR_YEAR_Field := 16#7#; - -- Current Month - MONTH : CALR_MONTH_Field := 16#1#; - -- Current Day in Current Week - DAY : CALR_DAY_Field := 16#1#; - -- Current Day in Current Month - DATE : CALR_DATE_Field := 16#1#; - -- unspecified - Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for CALR_Register use record - CENT at 0 range 0 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - YEAR at 0 range 8 .. 15; - MONTH at 0 range 16 .. 20; - DAY at 0 range 21 .. 23; - DATE at 0 range 24 .. 29; - Reserved_30_31 at 0 range 30 .. 31; - end record; - - --------------------- - -- TIMALR_Register -- - --------------------- - - subtype TIMALR_SEC_Field is ATSAM3X8E.UInt7; - subtype TIMALR_SECEN_Field is ATSAM3X8E.Bit; - subtype TIMALR_MIN_Field is ATSAM3X8E.UInt7; - subtype TIMALR_MINEN_Field is ATSAM3X8E.Bit; - subtype TIMALR_HOUR_Field is ATSAM3X8E.UInt6; - subtype TIMALR_AMPM_Field is ATSAM3X8E.Bit; - subtype TIMALR_HOUREN_Field is ATSAM3X8E.Bit; - - -- Time Alarm Register - type TIMALR_Register is record - -- Second Alarm - SEC : TIMALR_SEC_Field := 16#0#; - -- Second Alarm Enable - SECEN : TIMALR_SECEN_Field := 16#0#; - -- Minute Alarm - MIN : TIMALR_MIN_Field := 16#0#; - -- Minute Alarm Enable - MINEN : TIMALR_MINEN_Field := 16#0#; - -- Hour Alarm - HOUR : TIMALR_HOUR_Field := 16#0#; - -- AM/PM Indicator - AMPM : TIMALR_AMPM_Field := 16#0#; - -- Hour Alarm Enable - HOUREN : TIMALR_HOUREN_Field := 16#0#; - -- unspecified - Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for TIMALR_Register use record - SEC at 0 range 0 .. 6; - SECEN at 0 range 7 .. 7; - MIN at 0 range 8 .. 14; - MINEN at 0 range 15 .. 15; - HOUR at 0 range 16 .. 21; - AMPM at 0 range 22 .. 22; - HOUREN at 0 range 23 .. 23; - Reserved_24_31 at 0 range 24 .. 31; - end record; - - --------------------- - -- CALALR_Register -- - --------------------- - - subtype CALALR_MONTH_Field is ATSAM3X8E.UInt5; - subtype CALALR_MTHEN_Field is ATSAM3X8E.Bit; - subtype CALALR_DATE_Field is ATSAM3X8E.UInt6; - subtype CALALR_DATEEN_Field is ATSAM3X8E.Bit; - - -- Calendar Alarm Register - type CALALR_Register is record - -- unspecified - Reserved_0_15 : ATSAM3X8E.Short := 16#0#; - -- Month Alarm - MONTH : CALALR_MONTH_Field := 16#1#; - -- unspecified - Reserved_21_22 : ATSAM3X8E.UInt2 := 16#0#; - -- Month Alarm Enable - MTHEN : CALALR_MTHEN_Field := 16#0#; - -- Date Alarm - DATE : CALALR_DATE_Field := 16#1#; - -- unspecified - Reserved_30_30 : ATSAM3X8E.Bit := 16#0#; - -- Date Alarm Enable - DATEEN : CALALR_DATEEN_Field := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for CALALR_Register use record - Reserved_0_15 at 0 range 0 .. 15; - MONTH at 0 range 16 .. 20; - Reserved_21_22 at 0 range 21 .. 22; - MTHEN at 0 range 23 .. 23; - DATE at 0 range 24 .. 29; - Reserved_30_30 at 0 range 30 .. 30; - DATEEN at 0 range 31 .. 31; - end record; - - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_ACKUPD_Field is ATSAM3X8E.Bit; - subtype SR_ALARM_Field is ATSAM3X8E.Bit; - subtype SR_SEC_Field is ATSAM3X8E.Bit; - subtype SR_TIMEV_Field is ATSAM3X8E.Bit; - subtype SR_CALEV_Field is ATSAM3X8E.Bit; - - -- Status Register - type SR_Register_3 is record - -- Read-only. Acknowledge for Update - ACKUPD : SR_ACKUPD_Field := 16#0#; - -- Read-only. Alarm Flag - ALARM : SR_ALARM_Field := 16#0#; - -- Read-only. Second Event - SEC : SR_SEC_Field := 16#0#; - -- Read-only. Time Event - TIMEV : SR_TIMEV_Field := 16#0#; - -- Read-only. Calendar Event - CALEV : SR_CALEV_Field := 16#0#; - -- unspecified - Reserved_5_31 : ATSAM3X8E.UInt27; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for SR_Register_3 use record - ACKUPD at 0 range 0 .. 0; - ALARM at 0 range 1 .. 1; - SEC at 0 range 2 .. 2; - TIMEV at 0 range 3 .. 3; - CALEV at 0 range 4 .. 4; - Reserved_5_31 at 0 range 5 .. 31; - end record; - - ------------------- - -- SCCR_Register -- - ------------------- + -- WKUP Input Status 0 + type SR_WKUPIS0_Field is + (-- the corresponding wake-up input is disabled, or was inactive at the time +-- the debouncer triggered a wake up event. + Dis, + -- the corresponding wake-up input was active at the time the debouncer +-- triggered a wake up event. + En) + with Size => 1; + for SR_WKUPIS0_Field use + (Dis => 0, + En => 1); - subtype SCCR_ACKCLR_Field is ATSAM3X8E.Bit; - subtype SCCR_ALRCLR_Field is ATSAM3X8E.Bit; - subtype SCCR_SECCLR_Field is ATSAM3X8E.Bit; - subtype SCCR_TIMCLR_Field is ATSAM3X8E.Bit; - subtype SCCR_CALCLR_Field is ATSAM3X8E.Bit; + -- SUPC_SR_WKUPIS array + type SUPC_SR_WKUPIS_Field_Array is array (0 .. 15) of SR_WKUPIS0_Field + with Component_Size => 1, Size => 16; - -- Status Clear Command Register - type SCCR_Register is record - -- Write-only. Acknowledge Clear - ACKCLR : SCCR_ACKCLR_Field := 16#0#; - -- Write-only. Alarm Clear - ALRCLR : SCCR_ALRCLR_Field := 16#0#; - -- Write-only. Second Clear - SECCLR : SCCR_SECCLR_Field := 16#0#; - -- Write-only. Time Clear - TIMCLR : SCCR_TIMCLR_Field := 16#0#; - -- Write-only. Calendar Clear - CALCLR : SCCR_CALCLR_Field := 16#0#; - -- unspecified - Reserved_5_31 : ATSAM3X8E.UInt27 := 16#0#; + -- Type definition for SUPC_SR_WKUPIS + type SUPC_SR_WKUPIS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WKUPIS as a value + Val : ATSAM3X8E.UInt16; + when True => + -- WKUPIS as an array + Arr : SUPC_SR_WKUPIS_Field_Array; + end case; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Unchecked_Union, Size => 16; - for SCCR_Register use record - ACKCLR at 0 range 0 .. 0; - ALRCLR at 0 range 1 .. 1; - SECCLR at 0 range 2 .. 2; - TIMCLR at 0 range 3 .. 3; - CALCLR at 0 range 4 .. 4; - Reserved_5_31 at 0 range 5 .. 31; + for SUPC_SR_WKUPIS_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_ACKEN_Field is ATSAM3X8E.Bit; - subtype IER_ALREN_Field is ATSAM3X8E.Bit; - subtype IER_SECEN_Field is ATSAM3X8E.Bit; - subtype IER_TIMEN_Field is ATSAM3X8E.Bit; - subtype IER_CALEN_Field is ATSAM3X8E.Bit; - - -- Interrupt Enable Register - type IER_Register is record - -- Write-only. Acknowledge Update Interrupt Enable - ACKEN : IER_ACKEN_Field := 16#0#; - -- Write-only. Alarm Interrupt Enable - ALREN : IER_ALREN_Field := 16#0#; - -- Write-only. Second Event Interrupt Enable - SECEN : IER_SECEN_Field := 16#0#; - -- Write-only. Time Event Interrupt Enable - TIMEN : IER_TIMEN_Field := 16#0#; - -- Write-only. Calendar Event Interrupt Enable - CALEN : IER_CALEN_Field := 16#0#; + -- Supply Controller Status Register + type SUPC_SR_Register is record + -- Read-only. FWUP Wake Up Status + FWUPS : SR_FWUPS_Field; + -- Read-only. WKUP Wake Up Status + WKUPS : SR_WKUPS_Field; + -- Read-only. Supply Monitor Detection Wake Up Status + SMWS : SR_SMWS_Field; + -- Read-only. Brownout Detector Reset Status + BODRSTS : SR_BODRSTS_Field; + -- Read-only. Supply Monitor Reset Status + SMRSTS : SR_SMRSTS_Field; + -- Read-only. Supply Monitor Status + SMS : SR_SMS_Field; + -- Read-only. Supply Monitor Output Status + SMOS : SR_SMOS_Field; + -- Read-only. 32-kHz Oscillator Selection Status + OSCSEL : SR_OSCSEL_Field; -- unspecified - Reserved_5_31 : ATSAM3X8E.UInt27 := 16#0#; + Reserved_8_11 : ATSAM3X8E.UInt4; + -- Read-only. FWUP Input Status + FWUPIS : SR_FWUPIS_Field; + -- unspecified + Reserved_13_15 : ATSAM3X8E.UInt3; + -- Read-only. WKUP Input Status 0 + WKUPIS : SUPC_SR_WKUPIS_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record - ACKEN at 0 range 0 .. 0; - ALREN at 0 range 1 .. 1; - SECEN at 0 range 2 .. 2; - TIMEN at 0 range 3 .. 3; - CALEN at 0 range 4 .. 4; - Reserved_5_31 at 0 range 5 .. 31; + for SUPC_SR_Register use record + FWUPS at 0 range 0 .. 0; + WKUPS at 0 range 1 .. 1; + SMWS at 0 range 2 .. 2; + BODRSTS at 0 range 3 .. 3; + SMRSTS at 0 range 4 .. 4; + SMS at 0 range 5 .. 5; + SMOS at 0 range 6 .. 6; + OSCSEL at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + FWUPIS at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + WKUPIS at 0 range 16 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ + subtype WDT_CR_WDRSTT_Field is ATSAM3X8E.Bit; + subtype WDT_CR_KEY_Field is ATSAM3X8E.Byte; - subtype IDR_ACKDIS_Field is ATSAM3X8E.Bit; - subtype IDR_ALRDIS_Field is ATSAM3X8E.Bit; - subtype IDR_SECDIS_Field is ATSAM3X8E.Bit; - subtype IDR_TIMDIS_Field is ATSAM3X8E.Bit; - subtype IDR_CALDIS_Field is ATSAM3X8E.Bit; - - -- Interrupt Disable Register - type IDR_Register is record - -- Write-only. Acknowledge Update Interrupt Disable - ACKDIS : IDR_ACKDIS_Field := 16#0#; - -- Write-only. Alarm Interrupt Disable - ALRDIS : IDR_ALRDIS_Field := 16#0#; - -- Write-only. Second Event Interrupt Disable - SECDIS : IDR_SECDIS_Field := 16#0#; - -- Write-only. Time Event Interrupt Disable - TIMDIS : IDR_TIMDIS_Field := 16#0#; - -- Write-only. Calendar Event Interrupt Disable - CALDIS : IDR_CALDIS_Field := 16#0#; + -- Control Register + type WDT_CR_Register is record + -- Write-only. Watchdog Restart + WDRSTT : WDT_CR_WDRSTT_Field := 16#0#; -- unspecified - Reserved_5_31 : ATSAM3X8E.UInt27 := 16#0#; + Reserved_1_23 : ATSAM3X8E.UInt23 := 16#0#; + -- Write-only. Password + KEY : WDT_CR_KEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record - ACKDIS at 0 range 0 .. 0; - ALRDIS at 0 range 1 .. 1; - SECDIS at 0 range 2 .. 2; - TIMDIS at 0 range 3 .. 3; - CALDIS at 0 range 4 .. 4; - Reserved_5_31 at 0 range 5 .. 31; + for WDT_CR_Register use record + WDRSTT at 0 range 0 .. 0; + Reserved_1_23 at 0 range 1 .. 23; + KEY at 0 range 24 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ + subtype WDT_MR_WDV_Field is ATSAM3X8E.UInt12; + subtype WDT_MR_WDFIEN_Field is ATSAM3X8E.Bit; + subtype WDT_MR_WDRSTEN_Field is ATSAM3X8E.Bit; + subtype WDT_MR_WDRPROC_Field is ATSAM3X8E.Bit; + subtype WDT_MR_WDDIS_Field is ATSAM3X8E.Bit; + subtype WDT_MR_WDD_Field is ATSAM3X8E.UInt12; + subtype WDT_MR_WDDBGHLT_Field is ATSAM3X8E.Bit; + subtype WDT_MR_WDIDLEHLT_Field is ATSAM3X8E.Bit; - subtype IMR_ACK_Field is ATSAM3X8E.Bit; - subtype IMR_ALR_Field is ATSAM3X8E.Bit; - subtype IMR_SEC_Field is ATSAM3X8E.Bit; - subtype IMR_TIM_Field is ATSAM3X8E.Bit; - subtype IMR_CAL_Field is ATSAM3X8E.Bit; - - -- Interrupt Mask Register - type IMR_Register is record - -- Read-only. Acknowledge Update Interrupt Mask - ACK : IMR_ACK_Field := 16#0#; - -- Read-only. Alarm Interrupt Mask - ALR : IMR_ALR_Field := 16#0#; - -- Read-only. Second Event Interrupt Mask - SEC : IMR_SEC_Field := 16#0#; - -- Read-only. Time Event Interrupt Mask - TIM : IMR_TIM_Field := 16#0#; - -- Read-only. Calendar Event Interrupt Mask - CAL : IMR_CAL_Field := 16#0#; + -- Mode Register + type WDT_MR_Register is record + -- Watchdog Counter Value + WDV : WDT_MR_WDV_Field := 16#FFF#; + -- Watchdog Fault Interrupt Enable + WDFIEN : WDT_MR_WDFIEN_Field := 16#0#; + -- Watchdog Reset Enable + WDRSTEN : WDT_MR_WDRSTEN_Field := 16#1#; + -- Watchdog Reset Processor + WDRPROC : WDT_MR_WDRPROC_Field := 16#0#; + -- Watchdog Disable + WDDIS : WDT_MR_WDDIS_Field := 16#0#; + -- Watchdog Delta Value + WDD : WDT_MR_WDD_Field := 16#FFF#; + -- Watchdog Debug Halt + WDDBGHLT : WDT_MR_WDDBGHLT_Field := 16#1#; + -- Watchdog Idle Halt + WDIDLEHLT : WDT_MR_WDIDLEHLT_Field := 16#1#; -- unspecified - Reserved_5_31 : ATSAM3X8E.UInt27; + Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record - ACK at 0 range 0 .. 0; - ALR at 0 range 1 .. 1; - SEC at 0 range 2 .. 2; - TIM at 0 range 3 .. 3; - CAL at 0 range 4 .. 4; - Reserved_5_31 at 0 range 5 .. 31; + for WDT_MR_Register use record + WDV at 0 range 0 .. 11; + WDFIEN at 0 range 12 .. 12; + WDRSTEN at 0 range 13 .. 13; + WDRPROC at 0 range 14 .. 14; + WDDIS at 0 range 15 .. 15; + WDD at 0 range 16 .. 27; + WDDBGHLT at 0 range 28 .. 28; + WDIDLEHLT at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- VER_Register -- - ------------------ - - subtype VER_NVTIM_Field is ATSAM3X8E.Bit; - subtype VER_NVCAL_Field is ATSAM3X8E.Bit; - subtype VER_NVTIMALR_Field is ATSAM3X8E.Bit; - subtype VER_NVCALALR_Field is ATSAM3X8E.Bit; + subtype WDT_SR_WDUNF_Field is ATSAM3X8E.Bit; + subtype WDT_SR_WDERR_Field is ATSAM3X8E.Bit; - -- Valid Entry Register - type VER_Register is record - -- Read-only. Non-valid Time - NVTIM : VER_NVTIM_Field := 16#0#; - -- Read-only. Non-valid Calendar - NVCAL : VER_NVCAL_Field := 16#0#; - -- Read-only. Non-valid Time Alarm - NVTIMALR : VER_NVTIMALR_Field := 16#0#; - -- Read-only. Non-valid Calendar Alarm - NVCALALR : VER_NVCALALR_Field := 16#0#; + -- Status Register + type WDT_SR_Register is record + -- Read-only. Watchdog Underflow + WDUNF : WDT_SR_WDUNF_Field; + -- Read-only. Watchdog Error + WDERR : WDT_SR_WDERR_Field; -- unspecified - Reserved_4_31 : ATSAM3X8E.UInt28; + Reserved_2_31 : ATSAM3X8E.UInt30; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for VER_Register use record - NVTIM at 0 range 0 .. 0; - NVCAL at 0 range 1 .. 1; - NVTIMALR at 0 range 2 .. 2; - NVCALALR at 0 range 3 .. 3; - Reserved_4_31 at 0 range 4 .. 31; + for WDT_SR_Register use record + WDUNF at 0 range 0 .. 0; + WDERR at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + ----------------- + -- Peripherals -- + ----------------- - -- Write Protect Mode Register - type WPMR_Register is record - -- Write Protect Enable - WPEN : WPMR_WPEN_Field := 16#0#; - -- unspecified - Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; - WPKEY : WPMR_WPKEY_Field := 16#0#; + -- General Purpose Backup Register + type GPBR_Peripheral is record + -- General Purpose Backup Register + GPBR_0 : aliased ATSAM3X8E.UInt32; + -- General Purpose Backup Register + GPBR_1 : aliased ATSAM3X8E.UInt32; + -- General Purpose Backup Register + GPBR_2 : aliased ATSAM3X8E.UInt32; + -- General Purpose Backup Register + GPBR_3 : aliased ATSAM3X8E.UInt32; + -- General Purpose Backup Register + GPBR_4 : aliased ATSAM3X8E.UInt32; + -- General Purpose Backup Register + GPBR_5 : aliased ATSAM3X8E.UInt32; + -- General Purpose Backup Register + GPBR_6 : aliased ATSAM3X8E.UInt32; + -- General Purpose Backup Register + GPBR_7 : aliased ATSAM3X8E.UInt32; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Volatile; - for WPMR_Register use record - WPEN at 0 range 0 .. 0; - Reserved_1_7 at 0 range 1 .. 7; - WPKEY at 0 range 8 .. 31; + for GPBR_Peripheral use record + GPBR_0 at 16#0# range 0 .. 31; + GPBR_1 at 16#4# range 0 .. 31; + GPBR_2 at 16#8# range 0 .. 31; + GPBR_3 at 16#C# range 0 .. 31; + GPBR_4 at 16#10# range 0 .. 31; + GPBR_5 at 16#14# range 0 .. 31; + GPBR_6 at 16#18# range 0 .. 31; + GPBR_7 at 16#1C# range 0 .. 31; end record; -- General Purpose Backup Register - - -- General Purpose Backup Register - type GPBR_Registers is array (0 .. 7) of ATSAM3X8E.Word; - - ----------------- - -- Peripherals -- - ----------------- + GPBR_Periph : aliased GPBR_Peripheral + with Import, Address => GPBR_Base; -- Reset Controller type RSTC_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased RSTC_CR_Register; + pragma Volatile_Full_Access (CR); -- Status Register - SR : SR_Register; + SR : aliased RSTC_SR_Register; + pragma Volatile_Full_Access (SR); -- Mode Register - MR : MR_Register; + MR : aliased RSTC_MR_Register; + pragma Volatile_Full_Access (MR); end record with Volatile; for RSTC_Peripheral use record - CR at 0 range 0 .. 31; - SR at 4 range 0 .. 31; - MR at 8 range 0 .. 31; + CR at 16#0# range 0 .. 31; + SR at 16#4# range 0 .. 31; + MR at 16#8# range 0 .. 31; end record; -- Reset Controller RSTC_Periph : aliased RSTC_Peripheral with Import, Address => RSTC_Base; - -- Supply Controller - type SUPC_Peripheral is record - -- Supply Controller Control Register - CR : CR_Register; - -- Supply Controller Supply Monitor Mode Register - SMMR : SMMR_Register; - -- Supply Controller Mode Register - MR : MR_Register; - -- Supply Controller Wake Up Mode Register - WUMR : WUMR_Register; - -- Supply Controller Wake Up Inputs Register - WUIR : WUIR_Register; - -- Supply Controller Status Register - SR : SR_Register_1; + -- Real-time Clock + type RTC_Peripheral is record + -- Control Register + CR : aliased RTC_CR_Register; + pragma Volatile_Full_Access (CR); + -- Mode Register + MR : aliased RTC_MR_Register; + pragma Volatile_Full_Access (MR); + -- Time Register + TIMR : aliased RTC_TIMR_Register; + pragma Volatile_Full_Access (TIMR); + -- Calendar Register + CALR : aliased RTC_CALR_Register; + pragma Volatile_Full_Access (CALR); + -- Time Alarm Register + TIMALR : aliased RTC_TIMALR_Register; + pragma Volatile_Full_Access (TIMALR); + -- Calendar Alarm Register + CALALR : aliased RTC_CALALR_Register; + pragma Volatile_Full_Access (CALALR); + -- Status Register + SR : aliased RTC_SR_Register; + pragma Volatile_Full_Access (SR); + -- Status Clear Command Register + SCCR : aliased RTC_SCCR_Register; + pragma Volatile_Full_Access (SCCR); + -- Interrupt Enable Register + IER : aliased RTC_IER_Register; + pragma Volatile_Full_Access (IER); + -- Interrupt Disable Register + IDR : aliased RTC_IDR_Register; + pragma Volatile_Full_Access (IDR); + -- Interrupt Mask Register + IMR : aliased RTC_IMR_Register; + pragma Volatile_Full_Access (IMR); + -- Valid Entry Register + VER : aliased RTC_VER_Register; + pragma Volatile_Full_Access (VER); + -- Write Protect Mode Register + WPMR : aliased RTC_WPMR_Register; + pragma Volatile_Full_Access (WPMR); end record with Volatile; - for SUPC_Peripheral use record - CR at 0 range 0 .. 31; - SMMR at 4 range 0 .. 31; - MR at 8 range 0 .. 31; - WUMR at 12 range 0 .. 31; - WUIR at 16 range 0 .. 31; - SR at 20 range 0 .. 31; + for RTC_Peripheral use record + CR at 16#0# range 0 .. 31; + MR at 16#4# range 0 .. 31; + TIMR at 16#8# range 0 .. 31; + CALR at 16#C# range 0 .. 31; + TIMALR at 16#10# range 0 .. 31; + CALALR at 16#14# range 0 .. 31; + SR at 16#18# range 0 .. 31; + SCCR at 16#1C# range 0 .. 31; + IER at 16#20# range 0 .. 31; + IDR at 16#24# range 0 .. 31; + IMR at 16#28# range 0 .. 31; + VER at 16#2C# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; end record; - -- Supply Controller - SUPC_Periph : aliased SUPC_Peripheral - with Import, Address => SUPC_Base; + -- Real-time Clock + RTC_Periph : aliased RTC_Peripheral + with Import, Address => RTC_Base; -- Real-time Timer type RTT_Peripheral is record -- Mode Register - MR : MR_Register_1; + MR : aliased RTT_MR_Register; + pragma Volatile_Full_Access (MR); -- Alarm Register - AR : ATSAM3X8E.Word; + AR : aliased ATSAM3X8E.UInt32; -- Value Register - VR : ATSAM3X8E.Word; + VR : aliased ATSAM3X8E.UInt32; -- Status Register - SR : SR_Register_2; + SR : aliased RTT_SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; for RTT_Peripheral use record - MR at 0 range 0 .. 31; - AR at 4 range 0 .. 31; - VR at 8 range 0 .. 31; - SR at 12 range 0 .. 31; + MR at 16#0# range 0 .. 31; + AR at 16#4# range 0 .. 31; + VR at 16#8# range 0 .. 31; + SR at 16#C# range 0 .. 31; end record; -- Real-time Timer RTT_Periph : aliased RTT_Peripheral with Import, Address => RTT_Base; - -- Watchdog Timer - type WDT_Peripheral is record - -- Control Register - CR : CR_Register; - -- Mode Register - MR : MR_Register_2; - -- Status Register - SR : SR_Register_2; + -- Supply Controller + type SUPC_Peripheral is record + -- Supply Controller Control Register + CR : aliased SUPC_CR_Register; + pragma Volatile_Full_Access (CR); + -- Supply Controller Supply Monitor Mode Register + SMMR : aliased SUPC_SMMR_Register; + pragma Volatile_Full_Access (SMMR); + -- Supply Controller Mode Register + MR : aliased SUPC_MR_Register; + pragma Volatile_Full_Access (MR); + -- Supply Controller Wake Up Mode Register + WUMR : aliased SUPC_WUMR_Register; + pragma Volatile_Full_Access (WUMR); + -- Supply Controller Wake Up Inputs Register + WUIR : aliased SUPC_WUIR_Register; + pragma Volatile_Full_Access (WUIR); + -- Supply Controller Status Register + SR : aliased SUPC_SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; - for WDT_Peripheral use record - CR at 0 range 0 .. 31; - MR at 4 range 0 .. 31; - SR at 8 range 0 .. 31; + for SUPC_Peripheral use record + CR at 16#0# range 0 .. 31; + SMMR at 16#4# range 0 .. 31; + MR at 16#8# range 0 .. 31; + WUMR at 16#C# range 0 .. 31; + WUIR at 16#10# range 0 .. 31; + SR at 16#14# range 0 .. 31; end record; - -- Watchdog Timer - WDT_Periph : aliased WDT_Peripheral - with Import, Address => WDT_Base; + -- Supply Controller + SUPC_Periph : aliased SUPC_Peripheral + with Import, Address => SUPC_Base; - -- Real-time Clock - type RTC_Peripheral is record + -- Watchdog Timer + type WDT_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased WDT_CR_Register; + pragma Volatile_Full_Access (CR); -- Mode Register - MR : MR_Register_2; - -- Time Register - TIMR : TIMR_Register; - -- Calendar Register - CALR : CALR_Register; - -- Time Alarm Register - TIMALR : TIMALR_Register; - -- Calendar Alarm Register - CALALR : CALALR_Register; + MR : aliased WDT_MR_Register; + pragma Volatile_Full_Access (MR); -- Status Register - SR : SR_Register_3; - -- Status Clear Command Register - SCCR : SCCR_Register; - -- Interrupt Enable Register - IER : IER_Register; - -- Interrupt Disable Register - IDR : IDR_Register; - -- Interrupt Mask Register - IMR : IMR_Register; - -- Valid Entry Register - VER : VER_Register; - -- Write Protect Mode Register - WPMR : WPMR_Register; - end record - with Volatile; - - for RTC_Peripheral use record - CR at 0 range 0 .. 31; - MR at 4 range 0 .. 31; - TIMR at 8 range 0 .. 31; - CALR at 12 range 0 .. 31; - TIMALR at 16 range 0 .. 31; - CALALR at 20 range 0 .. 31; - SR at 24 range 0 .. 31; - SCCR at 28 range 0 .. 31; - IER at 32 range 0 .. 31; - IDR at 36 range 0 .. 31; - IMR at 40 range 0 .. 31; - VER at 44 range 0 .. 31; - WPMR at 228 range 0 .. 31; - end record; - - -- Real-time Clock - RTC_Periph : aliased RTC_Peripheral - with Import, Address => RTC_Base; - - -- General Purpose Backup Register - type GPBR_Peripheral is record - -- General Purpose Backup Register - GPBR : GPBR_Registers; + SR : aliased WDT_SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; - for GPBR_Peripheral use record - GPBR at 0 range 0 .. 255; + for WDT_Peripheral use record + CR at 16#0# range 0 .. 31; + MR at 16#4# range 0 .. 31; + SR at 16#8# range 0 .. 31; end record; - -- General Purpose Backup Register - GPBR_Periph : aliased GPBR_Peripheral - with Import, Address => GPBR_Base; + -- Watchdog Timer + WDT_Periph : aliased WDT_Peripheral + with Import, Address => WDT_Base; end ATSAM3X8E.SYSC; diff --git a/arduino-due/atsam3x8e/atsam3x8e-tc.ads b/arduino-due/atsam3x8e/atsam3x8e-tc.ads index 5275349..c44b439 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-tc.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-tc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,26 +14,22 @@ package ATSAM3X8E.TC is -- Registers -- --------------- - ------------------ - -- CCR_Register -- - ------------------ - - subtype CCR0_CLKEN_Field is ATSAM3X8E.Bit; - subtype CCR0_CLKDIS_Field is ATSAM3X8E.Bit; - subtype CCR0_SWTRG_Field is ATSAM3X8E.Bit; + subtype CCR_CLKEN_Field is ATSAM3X8E.Bit; + subtype CCR_CLKDIS_Field is ATSAM3X8E.Bit; + subtype CCR_SWTRG_Field is ATSAM3X8E.Bit; -- Channel Control Register (channel = 0) type CCR_Register is record -- Write-only. Counter Clock Enable Command - CLKEN : CCR0_CLKEN_Field := 16#0#; + CLKEN : CCR_CLKEN_Field := 16#0#; -- Write-only. Counter Clock Disable Command - CLKDIS : CCR0_CLKDIS_Field := 16#0#; + CLKDIS : CCR_CLKDIS_Field := 16#0#; -- Write-only. Software Trigger Command - SWTRG : CCR0_SWTRG_Field := 16#0#; + SWTRG : CCR_SWTRG_Field := 16#0#; -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCR_Register use record CLKEN at 0 range 0 .. 0; @@ -41,14 +38,9 @@ package ATSAM3X8E.TC is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- CMR_Register -- - ------------------ - -- Clock Selection - type TCCLKS_Field is - ( - -- Clock selected: TCLK1 + type CMR0_TCCLKS_Field is + (-- Clock selected: TCLK1 Timer_Clock1, -- Clock selected: TCLK2 Timer_Clock2, @@ -65,7 +57,7 @@ package ATSAM3X8E.TC is -- Clock selected: XC2 Xc2) with Size => 3; - for TCCLKS_Field use + for CMR0_TCCLKS_Field use (Timer_Clock1 => 0, Timer_Clock2 => 1, Timer_Clock3 => 2, @@ -75,12 +67,11 @@ package ATSAM3X8E.TC is Xc1 => 6, Xc2 => 7); - subtype CMR0_CLKI_Field is ATSAM3X8E.Bit; + subtype CMR_CLKI_Field is ATSAM3X8E.Bit; -- Burst Signal Selection - type BURST_Field is - ( - -- The clock is not gated by an external signal. + type CMR0_BURST_Field is + (-- The clock is not gated by an external signal. None, -- XC0 is ANDed with the selected clock. Xc0, @@ -89,19 +80,18 @@ package ATSAM3X8E.TC is -- XC2 is ANDed with the selected clock. Xc2) with Size => 2; - for BURST_Field use + for CMR0_BURST_Field use (None => 0, Xc0 => 1, Xc1 => 2, Xc2 => 3); - subtype CMR0_LDBSTOP_Field is ATSAM3X8E.Bit; - subtype CMR0_LDBDIS_Field is ATSAM3X8E.Bit; + subtype CMR_LDBSTOP_Field is ATSAM3X8E.Bit; + subtype CMR_LDBDIS_Field is ATSAM3X8E.Bit; -- External Trigger Edge Selection - type ETRGEDG_Field is - ( - -- The clock is not gated by an external signal. + type CMR0_ETRGEDG_Field is + (-- The clock is not gated by an external signal. None, -- Rising edge Rising, @@ -110,20 +100,19 @@ package ATSAM3X8E.TC is -- Each edge Edge) with Size => 2; - for ETRGEDG_Field use + for CMR0_ETRGEDG_Field use (None => 0, Rising => 1, Falling => 2, Edge => 3); - subtype CMR0_ABETRG_Field is ATSAM3X8E.Bit; - subtype CMR0_CPCTRG_Field is ATSAM3X8E.Bit; - subtype CMR0_WAVE_Field is ATSAM3X8E.Bit; + subtype CMR_ABETRG_Field is ATSAM3X8E.Bit; + subtype CMR_CPCTRG_Field is ATSAM3X8E.Bit; + subtype CMR_WAVE_Field is ATSAM3X8E.Bit; -- RA Loading Edge Selection - type LDRA_Field is - ( - -- None + type CMR0_LDRA_Field is + (-- None None, -- Rising edge of TIOA Rising, @@ -132,16 +121,15 @@ package ATSAM3X8E.TC is -- Each edge of TIOA Edge) with Size => 2; - for LDRA_Field use + for CMR0_LDRA_Field use (None => 0, Rising => 1, Falling => 2, Edge => 3); -- RB Loading Edge Selection - type LDRB_Field is - ( - -- None + type CMR0_LDRB_Field is + (-- None None, -- Rising edge of TIOA Rising, @@ -150,7 +138,7 @@ package ATSAM3X8E.TC is -- Each edge of TIOA Edge) with Size => 2; - for LDRB_Field use + for CMR0_LDRB_Field use (None => 0, Rising => 1, Falling => 2, @@ -159,33 +147,33 @@ package ATSAM3X8E.TC is -- Channel Mode Register (channel = 0) type CMR_Register is record -- Clock Selection - TCCLKS : TCCLKS_Field := Timer_Clock1; + TCCLKS : CMR0_TCCLKS_Field := ATSAM3X8E.TC.Timer_Clock1; -- Clock Invert - CLKI : CMR0_CLKI_Field := 16#0#; + CLKI : CMR_CLKI_Field := 16#0#; -- Burst Signal Selection - BURST : BURST_Field := None; + BURST : CMR0_BURST_Field := ATSAM3X8E.TC.None; -- Counter Clock Stopped with RB Loading - LDBSTOP : CMR0_LDBSTOP_Field := 16#0#; + LDBSTOP : CMR_LDBSTOP_Field := 16#0#; -- Counter Clock Disable with RB Loading - LDBDIS : CMR0_LDBDIS_Field := 16#0#; + LDBDIS : CMR_LDBDIS_Field := 16#0#; -- External Trigger Edge Selection - ETRGEDG : ETRGEDG_Field := None; + ETRGEDG : CMR0_ETRGEDG_Field := ATSAM3X8E.TC.None; -- TIOA or TIOB External Trigger Selection - ABETRG : CMR0_ABETRG_Field := 16#0#; + ABETRG : CMR_ABETRG_Field := 16#0#; -- unspecified Reserved_11_13 : ATSAM3X8E.UInt3 := 16#0#; -- RC Compare Trigger Enable - CPCTRG : CMR0_CPCTRG_Field := 16#0#; + CPCTRG : CMR_CPCTRG_Field := 16#0#; -- Waveform Mode - WAVE : CMR0_WAVE_Field := 16#0#; + WAVE : CMR_WAVE_Field := 16#0#; -- RA Loading Edge Selection - LDRA : LDRA_Field := None; + LDRA : CMR0_LDRA_Field := ATSAM3X8E.TC.None; -- RB Loading Edge Selection - LDRB : LDRB_Field := None; + LDRB : CMR0_LDRB_Field := ATSAM3X8E.TC.None; -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMR_Register use record TCCLKS at 0 range 0 .. 2; @@ -203,18 +191,60 @@ package ATSAM3X8E.TC is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------------------- - -- CMR0_WAVE_EQ_1_Register -- - ----------------------------- + -- Clock Selection + type CMR0_WAVE_EQ_1_TCCLKS_Field is + (-- Clock selected: TCLK1 + Timer_Clock1, + -- Clock selected: TCLK2 + Timer_Clock2, + -- Clock selected: TCLK3 + Timer_Clock3, + -- Clock selected: TCLK4 + Timer_Clock4, + -- Clock selected: TCLK5 + Timer_Clock5, + -- Clock selected: XC0 + Xc0, + -- Clock selected: XC1 + Xc1, + -- Clock selected: XC2 + Xc2) + with Size => 3; + for CMR0_WAVE_EQ_1_TCCLKS_Field use + (Timer_Clock1 => 0, + Timer_Clock2 => 1, + Timer_Clock3 => 2, + Timer_Clock4 => 3, + Timer_Clock5 => 4, + Xc0 => 5, + Xc1 => 6, + Xc2 => 7); + + subtype TC0_CMR0_WAVE_EQ_1_CLKI_Field is ATSAM3X8E.Bit; + + -- Burst Signal Selection + type CMR0_WAVE_EQ_1_BURST_Field is + (-- The clock is not gated by an external signal. + None, + -- XC0 is ANDed with the selected clock. + Xc0, + -- XC1 is ANDed with the selected clock. + Xc1, + -- XC2 is ANDed with the selected clock. + Xc2) + with Size => 2; + for CMR0_WAVE_EQ_1_BURST_Field use + (None => 0, + Xc0 => 1, + Xc1 => 2, + Xc2 => 3); - subtype CMR0_WAVE_EQ_1_CLKI_Field is ATSAM3X8E.Bit; - subtype CMR0_WAVE_EQ_1_CPCSTOP_Field is ATSAM3X8E.Bit; - subtype CMR0_WAVE_EQ_1_CPCDIS_Field is ATSAM3X8E.Bit; + subtype TC0_CMR0_WAVE_EQ_1_CPCSTOP_Field is ATSAM3X8E.Bit; + subtype TC0_CMR0_WAVE_EQ_1_CPCDIS_Field is ATSAM3X8E.Bit; -- External Event Edge Selection - type EEVTEDG_Field is - ( - -- None + type CMR0_WAVE_EQ_1_EEVTEDG_Field is + (-- None None, -- Rising edge Rising, @@ -223,16 +253,15 @@ package ATSAM3X8E.TC is -- Each edge Edge) with Size => 2; - for EEVTEDG_Field use + for CMR0_WAVE_EQ_1_EEVTEDG_Field use (None => 0, Rising => 1, Falling => 2, Edge => 3); -- External Event Selection - type EEVT_Field is - ( - -- TIOB + type CMR0_WAVE_EQ_1_EEVT_Field is + (-- TIOB Tiob, -- XC0 Xc0, @@ -241,18 +270,17 @@ package ATSAM3X8E.TC is -- XC2 Xc2) with Size => 2; - for EEVT_Field use + for CMR0_WAVE_EQ_1_EEVT_Field use (Tiob => 0, Xc0 => 1, Xc1 => 2, Xc2 => 3); - subtype CMR0_WAVE_EQ_1_ENETRG_Field is ATSAM3X8E.Bit; + subtype TC0_CMR0_WAVE_EQ_1_ENETRG_Field is ATSAM3X8E.Bit; -- Waveform Selection - type WAVSEL_Field is - ( - -- UP mode without automatic trigger on RC Compare + type CMR0_WAVE_EQ_1_WAVSEL_Field is + (-- UP mode without automatic trigger on RC Compare Up, -- UPDOWN mode without automatic trigger on RC Compare Updown, @@ -261,18 +289,17 @@ package ATSAM3X8E.TC is -- UPDOWN mode with automatic trigger on RC Compare Updown_Rc) with Size => 2; - for WAVSEL_Field use + for CMR0_WAVE_EQ_1_WAVSEL_Field use (Up => 0, Updown => 1, Up_Rc => 2, Updown_Rc => 3); - subtype CMR0_WAVE_EQ_1_WAVE_Field is ATSAM3X8E.Bit; + subtype TC0_CMR0_WAVE_EQ_1_WAVE_Field is ATSAM3X8E.Bit; -- RA Compare Effect on TIOA - type ACPA_Field is - ( - -- None + type CMR0_WAVE_EQ_1_ACPA_Field is + (-- None None, -- Set Set, @@ -281,16 +308,15 @@ package ATSAM3X8E.TC is -- Toggle Toggle) with Size => 2; - for ACPA_Field use + for CMR0_WAVE_EQ_1_ACPA_Field use (None => 0, Set => 1, Clear => 2, Toggle => 3); -- RC Compare Effect on TIOA - type ACPC_Field is - ( - -- None + type CMR0_WAVE_EQ_1_ACPC_Field is + (-- None None, -- Set Set, @@ -299,16 +325,15 @@ package ATSAM3X8E.TC is -- Toggle Toggle) with Size => 2; - for ACPC_Field use + for CMR0_WAVE_EQ_1_ACPC_Field use (None => 0, Set => 1, Clear => 2, Toggle => 3); -- External Event Effect on TIOA - type AEEVT_Field is - ( - -- None + type CMR0_WAVE_EQ_1_AEEVT_Field is + (-- None None, -- Set Set, @@ -317,16 +342,15 @@ package ATSAM3X8E.TC is -- Toggle Toggle) with Size => 2; - for AEEVT_Field use + for CMR0_WAVE_EQ_1_AEEVT_Field use (None => 0, Set => 1, Clear => 2, Toggle => 3); -- Software Trigger Effect on TIOA - type ASWTRG_Field is - ( - -- None + type CMR0_WAVE_EQ_1_ASWTRG_Field is + (-- None None, -- Set Set, @@ -335,16 +359,15 @@ package ATSAM3X8E.TC is -- Toggle Toggle) with Size => 2; - for ASWTRG_Field use + for CMR0_WAVE_EQ_1_ASWTRG_Field use (None => 0, Set => 1, Clear => 2, Toggle => 3); -- RB Compare Effect on TIOB - type BCPB_Field is - ( - -- None + type CMR0_WAVE_EQ_1_BCPB_Field is + (-- None None, -- Set Set, @@ -353,16 +376,15 @@ package ATSAM3X8E.TC is -- Toggle Toggle) with Size => 2; - for BCPB_Field use + for CMR0_WAVE_EQ_1_BCPB_Field use (None => 0, Set => 1, Clear => 2, Toggle => 3); -- RC Compare Effect on TIOB - type BCPC_Field is - ( - -- None + type CMR0_WAVE_EQ_1_BCPC_Field is + (-- None None, -- Set Set, @@ -371,16 +393,15 @@ package ATSAM3X8E.TC is -- Toggle Toggle) with Size => 2; - for BCPC_Field use + for CMR0_WAVE_EQ_1_BCPC_Field use (None => 0, Set => 1, Clear => 2, Toggle => 3); -- External Event Effect on TIOB - type BEEVT_Field is - ( - -- None + type CMR0_WAVE_EQ_1_BEEVT_Field is + (-- None None, -- Set Set, @@ -389,16 +410,15 @@ package ATSAM3X8E.TC is -- Toggle Toggle) with Size => 2; - for BEEVT_Field use + for CMR0_WAVE_EQ_1_BEEVT_Field use (None => 0, Set => 1, Clear => 2, Toggle => 3); -- Software Trigger Effect on TIOB - type BSWTRG_Field is - ( - -- None + type CMR0_WAVE_EQ_1_BSWTRG_Field is + (-- None None, -- Set Set, @@ -407,54 +427,54 @@ package ATSAM3X8E.TC is -- Toggle Toggle) with Size => 2; - for BSWTRG_Field use + for CMR0_WAVE_EQ_1_BSWTRG_Field use (None => 0, Set => 1, Clear => 2, Toggle => 3); -- Channel Mode Register (channel = 0) - type CMR0_WAVE_EQ_1_Register is record + type TC0_CMR0_WAVE_EQ_1_Register is record -- Clock Selection - TCCLKS : TCCLKS_Field := Timer_Clock1; + TCCLKS : CMR0_WAVE_EQ_1_TCCLKS_Field := ATSAM3X8E.TC.Timer_Clock1; -- Clock Invert - CLKI : CMR0_WAVE_EQ_1_CLKI_Field := 16#0#; + CLKI : TC0_CMR0_WAVE_EQ_1_CLKI_Field := 16#0#; -- Burst Signal Selection - BURST : BURST_Field := None; + BURST : CMR0_WAVE_EQ_1_BURST_Field := ATSAM3X8E.TC.None; -- Counter Clock Stopped with RC Compare - CPCSTOP : CMR0_WAVE_EQ_1_CPCSTOP_Field := 16#0#; + CPCSTOP : TC0_CMR0_WAVE_EQ_1_CPCSTOP_Field := 16#0#; -- Counter Clock Disable with RC Compare - CPCDIS : CMR0_WAVE_EQ_1_CPCDIS_Field := 16#0#; + CPCDIS : TC0_CMR0_WAVE_EQ_1_CPCDIS_Field := 16#0#; -- External Event Edge Selection - EEVTEDG : EEVTEDG_Field := None; + EEVTEDG : CMR0_WAVE_EQ_1_EEVTEDG_Field := ATSAM3X8E.TC.None; -- External Event Selection - EEVT : EEVT_Field := Tiob; + EEVT : CMR0_WAVE_EQ_1_EEVT_Field := ATSAM3X8E.TC.Tiob; -- External Event Trigger Enable - ENETRG : CMR0_WAVE_EQ_1_ENETRG_Field := 16#0#; + ENETRG : TC0_CMR0_WAVE_EQ_1_ENETRG_Field := 16#0#; -- Waveform Selection - WAVSEL : WAVSEL_Field := Up; + WAVSEL : CMR0_WAVE_EQ_1_WAVSEL_Field := ATSAM3X8E.TC.Up; -- Waveform Mode - WAVE : CMR0_WAVE_EQ_1_WAVE_Field := 16#0#; + WAVE : TC0_CMR0_WAVE_EQ_1_WAVE_Field := 16#0#; -- RA Compare Effect on TIOA - ACPA : ACPA_Field := None; + ACPA : CMR0_WAVE_EQ_1_ACPA_Field := ATSAM3X8E.TC.None; -- RC Compare Effect on TIOA - ACPC : ACPC_Field := None; + ACPC : CMR0_WAVE_EQ_1_ACPC_Field := ATSAM3X8E.TC.None; -- External Event Effect on TIOA - AEEVT : AEEVT_Field := None; + AEEVT : CMR0_WAVE_EQ_1_AEEVT_Field := ATSAM3X8E.TC.None; -- Software Trigger Effect on TIOA - ASWTRG : ASWTRG_Field := None; + ASWTRG : CMR0_WAVE_EQ_1_ASWTRG_Field := ATSAM3X8E.TC.None; -- RB Compare Effect on TIOB - BCPB : BCPB_Field := None; + BCPB : CMR0_WAVE_EQ_1_BCPB_Field := ATSAM3X8E.TC.None; -- RC Compare Effect on TIOB - BCPC : BCPC_Field := None; + BCPC : CMR0_WAVE_EQ_1_BCPC_Field := ATSAM3X8E.TC.None; -- External Event Effect on TIOB - BEEVT : BEEVT_Field := None; + BEEVT : CMR0_WAVE_EQ_1_BEEVT_Field := ATSAM3X8E.TC.None; -- Software Trigger Effect on TIOB - BSWTRG : BSWTRG_Field := None; + BSWTRG : CMR0_WAVE_EQ_1_BSWTRG_Field := ATSAM3X8E.TC.None; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CMR0_WAVE_EQ_1_Register use record + for TC0_CMR0_WAVE_EQ_1_Register use record TCCLKS at 0 range 0 .. 2; CLKI at 0 range 3 .. 3; BURST at 0 range 4 .. 5; @@ -475,23 +495,19 @@ package ATSAM3X8E.TC is BSWTRG at 0 range 30 .. 31; end record; - ------------------- - -- SMMR_Register -- - ------------------- - - subtype SMMR0_GCEN_Field is ATSAM3X8E.Bit; - subtype SMMR0_DOWN_Field is ATSAM3X8E.Bit; + subtype SMMR_GCEN_Field is ATSAM3X8E.Bit; + subtype SMMR_DOWN_Field is ATSAM3X8E.Bit; -- Stepper Motor Mode Register (channel = 0) type SMMR_Register is record -- Gray Count Enable - GCEN : SMMR0_GCEN_Field := 16#0#; + GCEN : SMMR_GCEN_Field := 16#0#; -- DOWN Count - DOWN : SMMR0_DOWN_Field := 16#0#; + DOWN : SMMR_DOWN_Field := 16#0#; -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SMMR_Register use record GCEN at 0 range 0 .. 0; @@ -499,52 +515,48 @@ package ATSAM3X8E.TC is Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR0_COVFS_Field is ATSAM3X8E.Bit; - subtype SR0_LOVRS_Field is ATSAM3X8E.Bit; - subtype SR0_CPAS_Field is ATSAM3X8E.Bit; - subtype SR0_CPBS_Field is ATSAM3X8E.Bit; - subtype SR0_CPCS_Field is ATSAM3X8E.Bit; - subtype SR0_LDRAS_Field is ATSAM3X8E.Bit; - subtype SR0_LDRBS_Field is ATSAM3X8E.Bit; - subtype SR0_ETRGS_Field is ATSAM3X8E.Bit; - subtype SR0_CLKSTA_Field is ATSAM3X8E.Bit; - subtype SR0_MTIOA_Field is ATSAM3X8E.Bit; - subtype SR0_MTIOB_Field is ATSAM3X8E.Bit; + subtype SR_COVFS_Field is ATSAM3X8E.Bit; + subtype SR_LOVRS_Field is ATSAM3X8E.Bit; + subtype SR_CPAS_Field is ATSAM3X8E.Bit; + subtype SR_CPBS_Field is ATSAM3X8E.Bit; + subtype SR_CPCS_Field is ATSAM3X8E.Bit; + subtype SR_LDRAS_Field is ATSAM3X8E.Bit; + subtype SR_LDRBS_Field is ATSAM3X8E.Bit; + subtype SR_ETRGS_Field is ATSAM3X8E.Bit; + subtype SR_CLKSTA_Field is ATSAM3X8E.Bit; + subtype SR_MTIOA_Field is ATSAM3X8E.Bit; + subtype SR_MTIOB_Field is ATSAM3X8E.Bit; -- Status Register (channel = 0) type SR_Register is record -- Read-only. Counter Overflow Status - COVFS : SR0_COVFS_Field := 16#0#; + COVFS : SR_COVFS_Field; -- Read-only. Load Overrun Status - LOVRS : SR0_LOVRS_Field := 16#0#; + LOVRS : SR_LOVRS_Field; -- Read-only. RA Compare Status - CPAS : SR0_CPAS_Field := 16#0#; + CPAS : SR_CPAS_Field; -- Read-only. RB Compare Status - CPBS : SR0_CPBS_Field := 16#0#; + CPBS : SR_CPBS_Field; -- Read-only. RC Compare Status - CPCS : SR0_CPCS_Field := 16#0#; + CPCS : SR_CPCS_Field; -- Read-only. RA Loading Status - LDRAS : SR0_LDRAS_Field := 16#0#; + LDRAS : SR_LDRAS_Field; -- Read-only. RB Loading Status - LDRBS : SR0_LDRBS_Field := 16#0#; + LDRBS : SR_LDRBS_Field; -- Read-only. External Trigger Status - ETRGS : SR0_ETRGS_Field := 16#0#; + ETRGS : SR_ETRGS_Field; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte; -- Read-only. Clock Enabling Status - CLKSTA : SR0_CLKSTA_Field := 16#0#; + CLKSTA : SR_CLKSTA_Field; -- Read-only. TIOA Mirror - MTIOA : SR0_MTIOA_Field := 16#0#; + MTIOA : SR_MTIOA_Field; -- Read-only. TIOB Mirror - MTIOB : SR0_MTIOB_Field := 16#0#; + MTIOB : SR_MTIOB_Field; -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record COVFS at 0 range 0 .. 0; @@ -562,41 +574,37 @@ package ATSAM3X8E.TC is Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER0_COVFS_Field is ATSAM3X8E.Bit; - subtype IER0_LOVRS_Field is ATSAM3X8E.Bit; - subtype IER0_CPAS_Field is ATSAM3X8E.Bit; - subtype IER0_CPBS_Field is ATSAM3X8E.Bit; - subtype IER0_CPCS_Field is ATSAM3X8E.Bit; - subtype IER0_LDRAS_Field is ATSAM3X8E.Bit; - subtype IER0_LDRBS_Field is ATSAM3X8E.Bit; - subtype IER0_ETRGS_Field is ATSAM3X8E.Bit; + subtype IER_COVFS_Field is ATSAM3X8E.Bit; + subtype IER_LOVRS_Field is ATSAM3X8E.Bit; + subtype IER_CPAS_Field is ATSAM3X8E.Bit; + subtype IER_CPBS_Field is ATSAM3X8E.Bit; + subtype IER_CPCS_Field is ATSAM3X8E.Bit; + subtype IER_LDRAS_Field is ATSAM3X8E.Bit; + subtype IER_LDRBS_Field is ATSAM3X8E.Bit; + subtype IER_ETRGS_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register (channel = 0) type IER_Register is record -- Write-only. Counter Overflow - COVFS : IER0_COVFS_Field := 16#0#; + COVFS : IER_COVFS_Field := 16#0#; -- Write-only. Load Overrun - LOVRS : IER0_LOVRS_Field := 16#0#; + LOVRS : IER_LOVRS_Field := 16#0#; -- Write-only. RA Compare - CPAS : IER0_CPAS_Field := 16#0#; + CPAS : IER_CPAS_Field := 16#0#; -- Write-only. RB Compare - CPBS : IER0_CPBS_Field := 16#0#; + CPBS : IER_CPBS_Field := 16#0#; -- Write-only. RC Compare - CPCS : IER0_CPCS_Field := 16#0#; + CPCS : IER_CPCS_Field := 16#0#; -- Write-only. RA Loading - LDRAS : IER0_LDRAS_Field := 16#0#; + LDRAS : IER_LDRAS_Field := 16#0#; -- Write-only. RB Loading - LDRBS : IER0_LDRBS_Field := 16#0#; + LDRBS : IER_LDRBS_Field := 16#0#; -- Write-only. External Trigger - ETRGS : IER0_ETRGS_Field := 16#0#; + ETRGS : IER_ETRGS_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IER_Register use record COVFS at 0 range 0 .. 0; @@ -610,41 +618,37 @@ package ATSAM3X8E.TC is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR0_COVFS_Field is ATSAM3X8E.Bit; - subtype IDR0_LOVRS_Field is ATSAM3X8E.Bit; - subtype IDR0_CPAS_Field is ATSAM3X8E.Bit; - subtype IDR0_CPBS_Field is ATSAM3X8E.Bit; - subtype IDR0_CPCS_Field is ATSAM3X8E.Bit; - subtype IDR0_LDRAS_Field is ATSAM3X8E.Bit; - subtype IDR0_LDRBS_Field is ATSAM3X8E.Bit; - subtype IDR0_ETRGS_Field is ATSAM3X8E.Bit; + subtype IDR_COVFS_Field is ATSAM3X8E.Bit; + subtype IDR_LOVRS_Field is ATSAM3X8E.Bit; + subtype IDR_CPAS_Field is ATSAM3X8E.Bit; + subtype IDR_CPBS_Field is ATSAM3X8E.Bit; + subtype IDR_CPCS_Field is ATSAM3X8E.Bit; + subtype IDR_LDRAS_Field is ATSAM3X8E.Bit; + subtype IDR_LDRBS_Field is ATSAM3X8E.Bit; + subtype IDR_ETRGS_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register (channel = 0) type IDR_Register is record -- Write-only. Counter Overflow - COVFS : IDR0_COVFS_Field := 16#0#; + COVFS : IDR_COVFS_Field := 16#0#; -- Write-only. Load Overrun - LOVRS : IDR0_LOVRS_Field := 16#0#; + LOVRS : IDR_LOVRS_Field := 16#0#; -- Write-only. RA Compare - CPAS : IDR0_CPAS_Field := 16#0#; + CPAS : IDR_CPAS_Field := 16#0#; -- Write-only. RB Compare - CPBS : IDR0_CPBS_Field := 16#0#; + CPBS : IDR_CPBS_Field := 16#0#; -- Write-only. RC Compare - CPCS : IDR0_CPCS_Field := 16#0#; + CPCS : IDR_CPCS_Field := 16#0#; -- Write-only. RA Loading - LDRAS : IDR0_LDRAS_Field := 16#0#; + LDRAS : IDR_LDRAS_Field := 16#0#; -- Write-only. RB Loading - LDRBS : IDR0_LDRBS_Field := 16#0#; + LDRBS : IDR_LDRBS_Field := 16#0#; -- Write-only. External Trigger - ETRGS : IDR0_ETRGS_Field := 16#0#; + ETRGS : IDR_ETRGS_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IDR_Register use record COVFS at 0 range 0 .. 0; @@ -658,41 +662,37 @@ package ATSAM3X8E.TC is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR0_COVFS_Field is ATSAM3X8E.Bit; - subtype IMR0_LOVRS_Field is ATSAM3X8E.Bit; - subtype IMR0_CPAS_Field is ATSAM3X8E.Bit; - subtype IMR0_CPBS_Field is ATSAM3X8E.Bit; - subtype IMR0_CPCS_Field is ATSAM3X8E.Bit; - subtype IMR0_LDRAS_Field is ATSAM3X8E.Bit; - subtype IMR0_LDRBS_Field is ATSAM3X8E.Bit; - subtype IMR0_ETRGS_Field is ATSAM3X8E.Bit; + subtype IMR_COVFS_Field is ATSAM3X8E.Bit; + subtype IMR_LOVRS_Field is ATSAM3X8E.Bit; + subtype IMR_CPAS_Field is ATSAM3X8E.Bit; + subtype IMR_CPBS_Field is ATSAM3X8E.Bit; + subtype IMR_CPCS_Field is ATSAM3X8E.Bit; + subtype IMR_LDRAS_Field is ATSAM3X8E.Bit; + subtype IMR_LDRBS_Field is ATSAM3X8E.Bit; + subtype IMR_ETRGS_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register (channel = 0) type IMR_Register is record -- Read-only. Counter Overflow - COVFS : IMR0_COVFS_Field := 16#0#; + COVFS : IMR_COVFS_Field; -- Read-only. Load Overrun - LOVRS : IMR0_LOVRS_Field := 16#0#; + LOVRS : IMR_LOVRS_Field; -- Read-only. RA Compare - CPAS : IMR0_CPAS_Field := 16#0#; + CPAS : IMR_CPAS_Field; -- Read-only. RB Compare - CPBS : IMR0_CPBS_Field := 16#0#; + CPBS : IMR_CPBS_Field; -- Read-only. RC Compare - CPCS : IMR0_CPCS_Field := 16#0#; + CPCS : IMR_CPCS_Field; -- Read-only. RA Loading - LDRAS : IMR0_LDRAS_Field := 16#0#; + LDRAS : IMR_LDRAS_Field; -- Read-only. RB Loading - LDRBS : IMR0_LDRBS_Field := 16#0#; + LDRBS : IMR_LDRBS_Field; -- Read-only. External Trigger - ETRGS : IMR0_ETRGS_Field := 16#0#; + ETRGS : IMR_ETRGS_Field; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IMR_Register use record COVFS at 0 range 0 .. 0; @@ -706,58 +706,290 @@ package ATSAM3X8E.TC is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------------------- - -- CMR1_WAVE_EQ_1_Register -- - ----------------------------- + -- Clock Selection + type CMR1_WAVE_EQ_1_TCCLKS_Field is + (-- Clock selected: TCLK1 + Timer_Clock1, + -- Clock selected: TCLK2 + Timer_Clock2, + -- Clock selected: TCLK3 + Timer_Clock3, + -- Clock selected: TCLK4 + Timer_Clock4, + -- Clock selected: TCLK5 + Timer_Clock5, + -- Clock selected: XC0 + Xc0, + -- Clock selected: XC1 + Xc1, + -- Clock selected: XC2 + Xc2) + with Size => 3; + for CMR1_WAVE_EQ_1_TCCLKS_Field use + (Timer_Clock1 => 0, + Timer_Clock2 => 1, + Timer_Clock3 => 2, + Timer_Clock4 => 3, + Timer_Clock5 => 4, + Xc0 => 5, + Xc1 => 6, + Xc2 => 7); + + subtype TC0_CMR1_WAVE_EQ_1_CLKI_Field is ATSAM3X8E.Bit; + + -- Burst Signal Selection + type CMR1_WAVE_EQ_1_BURST_Field is + (-- The clock is not gated by an external signal. + None, + -- XC0 is ANDed with the selected clock. + Xc0, + -- XC1 is ANDed with the selected clock. + Xc1, + -- XC2 is ANDed with the selected clock. + Xc2) + with Size => 2; + for CMR1_WAVE_EQ_1_BURST_Field use + (None => 0, + Xc0 => 1, + Xc1 => 2, + Xc2 => 3); + + subtype TC0_CMR1_WAVE_EQ_1_CPCSTOP_Field is ATSAM3X8E.Bit; + subtype TC0_CMR1_WAVE_EQ_1_CPCDIS_Field is ATSAM3X8E.Bit; + + -- External Event Edge Selection + type CMR1_WAVE_EQ_1_EEVTEDG_Field is + (-- None + None, + -- Rising edge + Rising, + -- Falling edge + Falling, + -- Each edge + Edge) + with Size => 2; + for CMR1_WAVE_EQ_1_EEVTEDG_Field use + (None => 0, + Rising => 1, + Falling => 2, + Edge => 3); + + -- External Event Selection + type CMR1_WAVE_EQ_1_EEVT_Field is + (-- TIOB + Tiob, + -- XC0 + Xc0, + -- XC1 + Xc1, + -- XC2 + Xc2) + with Size => 2; + for CMR1_WAVE_EQ_1_EEVT_Field use + (Tiob => 0, + Xc0 => 1, + Xc1 => 2, + Xc2 => 3); + + subtype TC0_CMR1_WAVE_EQ_1_ENETRG_Field is ATSAM3X8E.Bit; + + -- Waveform Selection + type CMR1_WAVE_EQ_1_WAVSEL_Field is + (-- UP mode without automatic trigger on RC Compare + Up, + -- UPDOWN mode without automatic trigger on RC Compare + Updown, + -- UP mode with automatic trigger on RC Compare + Up_Rc, + -- UPDOWN mode with automatic trigger on RC Compare + Updown_Rc) + with Size => 2; + for CMR1_WAVE_EQ_1_WAVSEL_Field use + (Up => 0, + Updown => 1, + Up_Rc => 2, + Updown_Rc => 3); + + subtype TC0_CMR1_WAVE_EQ_1_WAVE_Field is ATSAM3X8E.Bit; + + -- RA Compare Effect on TIOA + type CMR1_WAVE_EQ_1_ACPA_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR1_WAVE_EQ_1_ACPA_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- RC Compare Effect on TIOA + type CMR1_WAVE_EQ_1_ACPC_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR1_WAVE_EQ_1_ACPC_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- External Event Effect on TIOA + type CMR1_WAVE_EQ_1_AEEVT_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR1_WAVE_EQ_1_AEEVT_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- Software Trigger Effect on TIOA + type CMR1_WAVE_EQ_1_ASWTRG_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR1_WAVE_EQ_1_ASWTRG_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- RB Compare Effect on TIOB + type CMR1_WAVE_EQ_1_BCPB_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR1_WAVE_EQ_1_BCPB_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- RC Compare Effect on TIOB + type CMR1_WAVE_EQ_1_BCPC_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR1_WAVE_EQ_1_BCPC_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- External Event Effect on TIOB + type CMR1_WAVE_EQ_1_BEEVT_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR1_WAVE_EQ_1_BEEVT_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); - subtype CMR1_WAVE_EQ_1_CLKI_Field is ATSAM3X8E.Bit; - subtype CMR1_WAVE_EQ_1_CPCSTOP_Field is ATSAM3X8E.Bit; - subtype CMR1_WAVE_EQ_1_CPCDIS_Field is ATSAM3X8E.Bit; - subtype CMR1_WAVE_EQ_1_ENETRG_Field is ATSAM3X8E.Bit; - subtype CMR1_WAVE_EQ_1_WAVE_Field is ATSAM3X8E.Bit; + -- Software Trigger Effect on TIOB + type CMR1_WAVE_EQ_1_BSWTRG_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR1_WAVE_EQ_1_BSWTRG_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); -- Channel Mode Register (channel = 1) - type CMR1_WAVE_EQ_1_Register is record + type TC0_CMR1_WAVE_EQ_1_Register is record -- Clock Selection - TCCLKS : TCCLKS_Field := Timer_Clock1; + TCCLKS : CMR1_WAVE_EQ_1_TCCLKS_Field := ATSAM3X8E.TC.Timer_Clock1; -- Clock Invert - CLKI : CMR1_WAVE_EQ_1_CLKI_Field := 16#0#; + CLKI : TC0_CMR1_WAVE_EQ_1_CLKI_Field := 16#0#; -- Burst Signal Selection - BURST : BURST_Field := None; + BURST : CMR1_WAVE_EQ_1_BURST_Field := ATSAM3X8E.TC.None; -- Counter Clock Stopped with RC Compare - CPCSTOP : CMR1_WAVE_EQ_1_CPCSTOP_Field := 16#0#; + CPCSTOP : TC0_CMR1_WAVE_EQ_1_CPCSTOP_Field := 16#0#; -- Counter Clock Disable with RC Compare - CPCDIS : CMR1_WAVE_EQ_1_CPCDIS_Field := 16#0#; + CPCDIS : TC0_CMR1_WAVE_EQ_1_CPCDIS_Field := 16#0#; -- External Event Edge Selection - EEVTEDG : EEVTEDG_Field := None; + EEVTEDG : CMR1_WAVE_EQ_1_EEVTEDG_Field := ATSAM3X8E.TC.None; -- External Event Selection - EEVT : EEVT_Field := Tiob; + EEVT : CMR1_WAVE_EQ_1_EEVT_Field := ATSAM3X8E.TC.Tiob; -- External Event Trigger Enable - ENETRG : CMR1_WAVE_EQ_1_ENETRG_Field := 16#0#; + ENETRG : TC0_CMR1_WAVE_EQ_1_ENETRG_Field := 16#0#; -- Waveform Selection - WAVSEL : WAVSEL_Field := Up; + WAVSEL : CMR1_WAVE_EQ_1_WAVSEL_Field := ATSAM3X8E.TC.Up; -- Waveform Mode - WAVE : CMR1_WAVE_EQ_1_WAVE_Field := 16#0#; + WAVE : TC0_CMR1_WAVE_EQ_1_WAVE_Field := 16#0#; -- RA Compare Effect on TIOA - ACPA : ACPA_Field := None; + ACPA : CMR1_WAVE_EQ_1_ACPA_Field := ATSAM3X8E.TC.None; -- RC Compare Effect on TIOA - ACPC : ACPC_Field := None; + ACPC : CMR1_WAVE_EQ_1_ACPC_Field := ATSAM3X8E.TC.None; -- External Event Effect on TIOA - AEEVT : AEEVT_Field := None; + AEEVT : CMR1_WAVE_EQ_1_AEEVT_Field := ATSAM3X8E.TC.None; -- Software Trigger Effect on TIOA - ASWTRG : ASWTRG_Field := None; + ASWTRG : CMR1_WAVE_EQ_1_ASWTRG_Field := ATSAM3X8E.TC.None; -- RB Compare Effect on TIOB - BCPB : BCPB_Field := None; + BCPB : CMR1_WAVE_EQ_1_BCPB_Field := ATSAM3X8E.TC.None; -- RC Compare Effect on TIOB - BCPC : BCPC_Field := None; + BCPC : CMR1_WAVE_EQ_1_BCPC_Field := ATSAM3X8E.TC.None; -- External Event Effect on TIOB - BEEVT : BEEVT_Field := None; + BEEVT : CMR1_WAVE_EQ_1_BEEVT_Field := ATSAM3X8E.TC.None; -- Software Trigger Effect on TIOB - BSWTRG : BSWTRG_Field := None; + BSWTRG : CMR1_WAVE_EQ_1_BSWTRG_Field := ATSAM3X8E.TC.None; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CMR1_WAVE_EQ_1_Register use record + for TC0_CMR1_WAVE_EQ_1_Register use record TCCLKS at 0 range 0 .. 2; CLKI at 0 range 3 .. 3; BURST at 0 range 4 .. 5; @@ -778,58 +1010,290 @@ package ATSAM3X8E.TC is BSWTRG at 0 range 30 .. 31; end record; - ----------------------------- - -- CMR2_WAVE_EQ_1_Register -- - ----------------------------- + -- Clock Selection + type CMR2_WAVE_EQ_1_TCCLKS_Field is + (-- Clock selected: TCLK1 + Timer_Clock1, + -- Clock selected: TCLK2 + Timer_Clock2, + -- Clock selected: TCLK3 + Timer_Clock3, + -- Clock selected: TCLK4 + Timer_Clock4, + -- Clock selected: TCLK5 + Timer_Clock5, + -- Clock selected: XC0 + Xc0, + -- Clock selected: XC1 + Xc1, + -- Clock selected: XC2 + Xc2) + with Size => 3; + for CMR2_WAVE_EQ_1_TCCLKS_Field use + (Timer_Clock1 => 0, + Timer_Clock2 => 1, + Timer_Clock3 => 2, + Timer_Clock4 => 3, + Timer_Clock5 => 4, + Xc0 => 5, + Xc1 => 6, + Xc2 => 7); + + subtype TC0_CMR2_WAVE_EQ_1_CLKI_Field is ATSAM3X8E.Bit; + + -- Burst Signal Selection + type CMR2_WAVE_EQ_1_BURST_Field is + (-- The clock is not gated by an external signal. + None, + -- XC0 is ANDed with the selected clock. + Xc0, + -- XC1 is ANDed with the selected clock. + Xc1, + -- XC2 is ANDed with the selected clock. + Xc2) + with Size => 2; + for CMR2_WAVE_EQ_1_BURST_Field use + (None => 0, + Xc0 => 1, + Xc1 => 2, + Xc2 => 3); + + subtype TC0_CMR2_WAVE_EQ_1_CPCSTOP_Field is ATSAM3X8E.Bit; + subtype TC0_CMR2_WAVE_EQ_1_CPCDIS_Field is ATSAM3X8E.Bit; + + -- External Event Edge Selection + type CMR2_WAVE_EQ_1_EEVTEDG_Field is + (-- None + None, + -- Rising edge + Rising, + -- Falling edge + Falling, + -- Each edge + Edge) + with Size => 2; + for CMR2_WAVE_EQ_1_EEVTEDG_Field use + (None => 0, + Rising => 1, + Falling => 2, + Edge => 3); + + -- External Event Selection + type CMR2_WAVE_EQ_1_EEVT_Field is + (-- TIOB + Tiob, + -- XC0 + Xc0, + -- XC1 + Xc1, + -- XC2 + Xc2) + with Size => 2; + for CMR2_WAVE_EQ_1_EEVT_Field use + (Tiob => 0, + Xc0 => 1, + Xc1 => 2, + Xc2 => 3); + + subtype TC0_CMR2_WAVE_EQ_1_ENETRG_Field is ATSAM3X8E.Bit; + + -- Waveform Selection + type CMR2_WAVE_EQ_1_WAVSEL_Field is + (-- UP mode without automatic trigger on RC Compare + Up, + -- UPDOWN mode without automatic trigger on RC Compare + Updown, + -- UP mode with automatic trigger on RC Compare + Up_Rc, + -- UPDOWN mode with automatic trigger on RC Compare + Updown_Rc) + with Size => 2; + for CMR2_WAVE_EQ_1_WAVSEL_Field use + (Up => 0, + Updown => 1, + Up_Rc => 2, + Updown_Rc => 3); + + subtype TC0_CMR2_WAVE_EQ_1_WAVE_Field is ATSAM3X8E.Bit; + + -- RA Compare Effect on TIOA + type CMR2_WAVE_EQ_1_ACPA_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR2_WAVE_EQ_1_ACPA_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- RC Compare Effect on TIOA + type CMR2_WAVE_EQ_1_ACPC_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR2_WAVE_EQ_1_ACPC_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- External Event Effect on TIOA + type CMR2_WAVE_EQ_1_AEEVT_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR2_WAVE_EQ_1_AEEVT_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- Software Trigger Effect on TIOA + type CMR2_WAVE_EQ_1_ASWTRG_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR2_WAVE_EQ_1_ASWTRG_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- RB Compare Effect on TIOB + type CMR2_WAVE_EQ_1_BCPB_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR2_WAVE_EQ_1_BCPB_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- RC Compare Effect on TIOB + type CMR2_WAVE_EQ_1_BCPC_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR2_WAVE_EQ_1_BCPC_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); - subtype CMR2_WAVE_EQ_1_CLKI_Field is ATSAM3X8E.Bit; - subtype CMR2_WAVE_EQ_1_CPCSTOP_Field is ATSAM3X8E.Bit; - subtype CMR2_WAVE_EQ_1_CPCDIS_Field is ATSAM3X8E.Bit; - subtype CMR2_WAVE_EQ_1_ENETRG_Field is ATSAM3X8E.Bit; - subtype CMR2_WAVE_EQ_1_WAVE_Field is ATSAM3X8E.Bit; + -- External Event Effect on TIOB + type CMR2_WAVE_EQ_1_BEEVT_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR2_WAVE_EQ_1_BEEVT_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); + + -- Software Trigger Effect on TIOB + type CMR2_WAVE_EQ_1_BSWTRG_Field is + (-- None + None, + -- Set + Set, + -- Clear + Clear, + -- Toggle + Toggle) + with Size => 2; + for CMR2_WAVE_EQ_1_BSWTRG_Field use + (None => 0, + Set => 1, + Clear => 2, + Toggle => 3); -- Channel Mode Register (channel = 2) - type CMR2_WAVE_EQ_1_Register is record + type TC0_CMR2_WAVE_EQ_1_Register is record -- Clock Selection - TCCLKS : TCCLKS_Field := Timer_Clock1; + TCCLKS : CMR2_WAVE_EQ_1_TCCLKS_Field := ATSAM3X8E.TC.Timer_Clock1; -- Clock Invert - CLKI : CMR2_WAVE_EQ_1_CLKI_Field := 16#0#; + CLKI : TC0_CMR2_WAVE_EQ_1_CLKI_Field := 16#0#; -- Burst Signal Selection - BURST : BURST_Field := None; + BURST : CMR2_WAVE_EQ_1_BURST_Field := ATSAM3X8E.TC.None; -- Counter Clock Stopped with RC Compare - CPCSTOP : CMR2_WAVE_EQ_1_CPCSTOP_Field := 16#0#; + CPCSTOP : TC0_CMR2_WAVE_EQ_1_CPCSTOP_Field := 16#0#; -- Counter Clock Disable with RC Compare - CPCDIS : CMR2_WAVE_EQ_1_CPCDIS_Field := 16#0#; + CPCDIS : TC0_CMR2_WAVE_EQ_1_CPCDIS_Field := 16#0#; -- External Event Edge Selection - EEVTEDG : EEVTEDG_Field := None; + EEVTEDG : CMR2_WAVE_EQ_1_EEVTEDG_Field := ATSAM3X8E.TC.None; -- External Event Selection - EEVT : EEVT_Field := Tiob; + EEVT : CMR2_WAVE_EQ_1_EEVT_Field := ATSAM3X8E.TC.Tiob; -- External Event Trigger Enable - ENETRG : CMR2_WAVE_EQ_1_ENETRG_Field := 16#0#; + ENETRG : TC0_CMR2_WAVE_EQ_1_ENETRG_Field := 16#0#; -- Waveform Selection - WAVSEL : WAVSEL_Field := Up; + WAVSEL : CMR2_WAVE_EQ_1_WAVSEL_Field := ATSAM3X8E.TC.Up; -- Waveform Mode - WAVE : CMR2_WAVE_EQ_1_WAVE_Field := 16#0#; + WAVE : TC0_CMR2_WAVE_EQ_1_WAVE_Field := 16#0#; -- RA Compare Effect on TIOA - ACPA : ACPA_Field := None; + ACPA : CMR2_WAVE_EQ_1_ACPA_Field := ATSAM3X8E.TC.None; -- RC Compare Effect on TIOA - ACPC : ACPC_Field := None; + ACPC : CMR2_WAVE_EQ_1_ACPC_Field := ATSAM3X8E.TC.None; -- External Event Effect on TIOA - AEEVT : AEEVT_Field := None; + AEEVT : CMR2_WAVE_EQ_1_AEEVT_Field := ATSAM3X8E.TC.None; -- Software Trigger Effect on TIOA - ASWTRG : ASWTRG_Field := None; + ASWTRG : CMR2_WAVE_EQ_1_ASWTRG_Field := ATSAM3X8E.TC.None; -- RB Compare Effect on TIOB - BCPB : BCPB_Field := None; + BCPB : CMR2_WAVE_EQ_1_BCPB_Field := ATSAM3X8E.TC.None; -- RC Compare Effect on TIOB - BCPC : BCPC_Field := None; + BCPC : CMR2_WAVE_EQ_1_BCPC_Field := ATSAM3X8E.TC.None; -- External Event Effect on TIOB - BEEVT : BEEVT_Field := None; + BEEVT : CMR2_WAVE_EQ_1_BEEVT_Field := ATSAM3X8E.TC.None; -- Software Trigger Effect on TIOB - BSWTRG : BSWTRG_Field := None; + BSWTRG : CMR2_WAVE_EQ_1_BSWTRG_Field := ATSAM3X8E.TC.None; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CMR2_WAVE_EQ_1_Register use record + for TC0_CMR2_WAVE_EQ_1_Register use record TCCLKS at 0 range 0 .. 2; CLKI at 0 range 3 .. 3; BURST at 0 range 4 .. 5; @@ -850,129 +1314,118 @@ package ATSAM3X8E.TC is BSWTRG at 0 range 30 .. 31; end record; - ------------------ - -- BCR_Register -- - ------------------ - - subtype BCR_SYNC_Field is ATSAM3X8E.Bit; + subtype TC0_BCR_SYNC_Field is ATSAM3X8E.Bit; -- Block Control Register - type BCR_Register is record + type TC0_BCR_Register is record -- Write-only. Synchro Command - SYNC : BCR_SYNC_Field := 16#0#; + SYNC : TC0_BCR_SYNC_Field := 16#0#; -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for BCR_Register use record + for TC0_BCR_Register use record SYNC at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------ - -- BMR_Register -- - ------------------ - -- External Clock Signal 0 Selection - type TC0XC0S_Field is - ( - -- Signal connected to XC0: TCLK0 + type BMR_TC0XC0S_Field is + (-- Signal connected to XC0: TCLK0 Tclk0, -- Signal connected to XC0: TIOA1 Tioa1, -- Signal connected to XC0: TIOA2 Tioa2) with Size => 2; - for TC0XC0S_Field use + for BMR_TC0XC0S_Field use (Tclk0 => 0, Tioa1 => 2, Tioa2 => 3); -- External Clock Signal 1 Selection - type TC1XC1S_Field is - ( - -- Signal connected to XC1: TCLK1 + type BMR_TC1XC1S_Field is + (-- Signal connected to XC1: TCLK1 Tclk1, -- Signal connected to XC1: TIOA0 Tioa0, -- Signal connected to XC1: TIOA2 Tioa2) with Size => 2; - for TC1XC1S_Field use + for BMR_TC1XC1S_Field use (Tclk1 => 0, Tioa0 => 2, Tioa2 => 3); -- External Clock Signal 2 Selection - type TC2XC2S_Field is - ( - -- Signal connected to XC2: TCLK2 + type BMR_TC2XC2S_Field is + (-- Signal connected to XC2: TCLK2 Tclk2, -- Signal connected to XC2: TIOA1 Tioa1, -- Signal connected to XC2: TIOA2 Tioa2) with Size => 2; - for TC2XC2S_Field use + for BMR_TC2XC2S_Field use (Tclk2 => 0, Tioa1 => 2, Tioa2 => 3); - subtype BMR_QDEN_Field is ATSAM3X8E.Bit; - subtype BMR_POSEN_Field is ATSAM3X8E.Bit; - subtype BMR_SPEEDEN_Field is ATSAM3X8E.Bit; - subtype BMR_QDTRANS_Field is ATSAM3X8E.Bit; - subtype BMR_EDGPHA_Field is ATSAM3X8E.Bit; - subtype BMR_INVA_Field is ATSAM3X8E.Bit; - subtype BMR_INVB_Field is ATSAM3X8E.Bit; - subtype BMR_INVIDX_Field is ATSAM3X8E.Bit; - subtype BMR_SWAP_Field is ATSAM3X8E.Bit; - subtype BMR_IDXPHB_Field is ATSAM3X8E.Bit; - subtype BMR_FILTER_Field is ATSAM3X8E.Bit; - subtype BMR_MAXFILT_Field is ATSAM3X8E.UInt6; + subtype TC0_BMR_QDEN_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_POSEN_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_SPEEDEN_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_QDTRANS_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_EDGPHA_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_INVA_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_INVB_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_INVIDX_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_SWAP_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_IDXPHB_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_FILTER_Field is ATSAM3X8E.Bit; + subtype TC0_BMR_MAXFILT_Field is ATSAM3X8E.UInt6; -- Block Mode Register - type BMR_Register is record + type TC0_BMR_Register is record -- External Clock Signal 0 Selection - TC0XC0S : TC0XC0S_Field := Tclk0; + TC0XC0S : BMR_TC0XC0S_Field := ATSAM3X8E.TC.Tclk0; -- External Clock Signal 1 Selection - TC1XC1S : TC1XC1S_Field := Tclk1; + TC1XC1S : BMR_TC1XC1S_Field := ATSAM3X8E.TC.Tclk1; -- External Clock Signal 2 Selection - TC2XC2S : TC2XC2S_Field := Tclk2; + TC2XC2S : BMR_TC2XC2S_Field := ATSAM3X8E.TC.Tclk2; -- unspecified Reserved_6_7 : ATSAM3X8E.UInt2 := 16#0#; -- Quadrature Decoder ENabled - QDEN : BMR_QDEN_Field := 16#0#; + QDEN : TC0_BMR_QDEN_Field := 16#0#; -- POSition ENabled - POSEN : BMR_POSEN_Field := 16#0#; + POSEN : TC0_BMR_POSEN_Field := 16#0#; -- SPEED ENabled - SPEEDEN : BMR_SPEEDEN_Field := 16#0#; + SPEEDEN : TC0_BMR_SPEEDEN_Field := 16#0#; -- Quadrature Decoding TRANSparent - QDTRANS : BMR_QDTRANS_Field := 16#0#; + QDTRANS : TC0_BMR_QDTRANS_Field := 16#0#; -- EDGe on PHA count mode - EDGPHA : BMR_EDGPHA_Field := 16#0#; + EDGPHA : TC0_BMR_EDGPHA_Field := 16#0#; -- INVerted phA - INVA : BMR_INVA_Field := 16#0#; + INVA : TC0_BMR_INVA_Field := 16#0#; -- INVerted phB - INVB : BMR_INVB_Field := 16#0#; + INVB : TC0_BMR_INVB_Field := 16#0#; -- INVerted InDeX - INVIDX : BMR_INVIDX_Field := 16#0#; + INVIDX : TC0_BMR_INVIDX_Field := 16#0#; -- SWAP PHA and PHB - SWAP : BMR_SWAP_Field := 16#0#; + SWAP : TC0_BMR_SWAP_Field := 16#0#; -- InDeX pin is PHB pin - IDXPHB : BMR_IDXPHB_Field := 16#0#; + IDXPHB : TC0_BMR_IDXPHB_Field := 16#0#; -- unspecified Reserved_18_18 : ATSAM3X8E.Bit := 16#0#; - FILTER : BMR_FILTER_Field := 16#0#; + FILTER : TC0_BMR_FILTER_Field := 16#0#; -- MAXimum FILTer - MAXFILT : BMR_MAXFILT_Field := 16#0#; + MAXFILT : TC0_BMR_MAXFILT_Field := 16#0#; -- unspecified Reserved_26_31 : ATSAM3X8E.UInt6 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for BMR_Register use record + for TC0_BMR_Register use record TC0XC0S at 0 range 0 .. 1; TC1XC1S at 0 range 2 .. 3; TC2XC2S at 0 range 4 .. 5; @@ -993,117 +1446,101 @@ package ATSAM3X8E.TC is Reserved_26_31 at 0 range 26 .. 31; end record; - ------------------- - -- QIER_Register -- - ------------------- - - subtype QIER_IDX_Field is ATSAM3X8E.Bit; - subtype QIER_DIRCHG_Field is ATSAM3X8E.Bit; - subtype QIER_QERR_Field is ATSAM3X8E.Bit; + subtype TC0_QIER_IDX_Field is ATSAM3X8E.Bit; + subtype TC0_QIER_DIRCHG_Field is ATSAM3X8E.Bit; + subtype TC0_QIER_QERR_Field is ATSAM3X8E.Bit; -- QDEC Interrupt Enable Register - type QIER_Register is record + type TC0_QIER_Register is record -- Write-only. InDeX - IDX : QIER_IDX_Field := 16#0#; + IDX : TC0_QIER_IDX_Field := 16#0#; -- Write-only. DIRection CHanGe - DIRCHG : QIER_DIRCHG_Field := 16#0#; + DIRCHG : TC0_QIER_DIRCHG_Field := 16#0#; -- Write-only. Quadrature ERRor - QERR : QIER_QERR_Field := 16#0#; + QERR : TC0_QIER_QERR_Field := 16#0#; -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for QIER_Register use record + for TC0_QIER_Register use record IDX at 0 range 0 .. 0; DIRCHG at 0 range 1 .. 1; QERR at 0 range 2 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------- - -- QIDR_Register -- - ------------------- - - subtype QIDR_IDX_Field is ATSAM3X8E.Bit; - subtype QIDR_DIRCHG_Field is ATSAM3X8E.Bit; - subtype QIDR_QERR_Field is ATSAM3X8E.Bit; + subtype TC0_QIDR_IDX_Field is ATSAM3X8E.Bit; + subtype TC0_QIDR_DIRCHG_Field is ATSAM3X8E.Bit; + subtype TC0_QIDR_QERR_Field is ATSAM3X8E.Bit; -- QDEC Interrupt Disable Register - type QIDR_Register is record + type TC0_QIDR_Register is record -- Write-only. InDeX - IDX : QIDR_IDX_Field := 16#0#; + IDX : TC0_QIDR_IDX_Field := 16#0#; -- Write-only. DIRection CHanGe - DIRCHG : QIDR_DIRCHG_Field := 16#0#; + DIRCHG : TC0_QIDR_DIRCHG_Field := 16#0#; -- Write-only. Quadrature ERRor - QERR : QIDR_QERR_Field := 16#0#; + QERR : TC0_QIDR_QERR_Field := 16#0#; -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for QIDR_Register use record + for TC0_QIDR_Register use record IDX at 0 range 0 .. 0; DIRCHG at 0 range 1 .. 1; QERR at 0 range 2 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------- - -- QIMR_Register -- - ------------------- - - subtype QIMR_IDX_Field is ATSAM3X8E.Bit; - subtype QIMR_DIRCHG_Field is ATSAM3X8E.Bit; - subtype QIMR_QERR_Field is ATSAM3X8E.Bit; + subtype TC0_QIMR_IDX_Field is ATSAM3X8E.Bit; + subtype TC0_QIMR_DIRCHG_Field is ATSAM3X8E.Bit; + subtype TC0_QIMR_QERR_Field is ATSAM3X8E.Bit; -- QDEC Interrupt Mask Register - type QIMR_Register is record + type TC0_QIMR_Register is record -- Read-only. InDeX - IDX : QIMR_IDX_Field := 16#0#; + IDX : TC0_QIMR_IDX_Field; -- Read-only. DIRection CHanGe - DIRCHG : QIMR_DIRCHG_Field := 16#0#; + DIRCHG : TC0_QIMR_DIRCHG_Field; -- Read-only. Quadrature ERRor - QERR : QIMR_QERR_Field := 16#0#; + QERR : TC0_QIMR_QERR_Field; -- unspecified Reserved_3_31 : ATSAM3X8E.UInt29; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for QIMR_Register use record + for TC0_QIMR_Register use record IDX at 0 range 0 .. 0; DIRCHG at 0 range 1 .. 1; QERR at 0 range 2 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------- - -- QISR_Register -- - ------------------- - - subtype QISR_IDX_Field is ATSAM3X8E.Bit; - subtype QISR_DIRCHG_Field is ATSAM3X8E.Bit; - subtype QISR_QERR_Field is ATSAM3X8E.Bit; - subtype QISR_DIR_Field is ATSAM3X8E.Bit; + subtype TC0_QISR_IDX_Field is ATSAM3X8E.Bit; + subtype TC0_QISR_DIRCHG_Field is ATSAM3X8E.Bit; + subtype TC0_QISR_QERR_Field is ATSAM3X8E.Bit; + subtype TC0_QISR_DIR_Field is ATSAM3X8E.Bit; -- QDEC Interrupt Status Register - type QISR_Register is record + type TC0_QISR_Register is record -- Read-only. InDeX - IDX : QISR_IDX_Field := 16#0#; + IDX : TC0_QISR_IDX_Field; -- Read-only. DIRection CHanGe - DIRCHG : QISR_DIRCHG_Field := 16#0#; + DIRCHG : TC0_QISR_DIRCHG_Field; -- Read-only. Quadrature ERRor - QERR : QISR_QERR_Field := 16#0#; + QERR : TC0_QISR_QERR_Field; -- unspecified Reserved_3_7 : ATSAM3X8E.UInt5; -- Read-only. DIRection - DIR : QISR_DIR_Field := 16#0#; + DIR : TC0_QISR_DIR_Field; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for QISR_Register use record + for TC0_QISR_Register use record IDX at 0 range 0 .. 0; DIRCHG at 0 range 1 .. 1; QERR at 0 range 2 .. 2; @@ -1112,23 +1549,15 @@ package ATSAM3X8E.TC is Reserved_9_31 at 0 range 9 .. 31; end record; - ------------------ - -- FMR_Register -- - ------------------ - - -------------- - -- FMR.ENCF -- - -------------- + -- TC0_FMR_ENCF array element + subtype TC0_FMR_ENCF_Element is ATSAM3X8E.Bit; - -- FMR_ENCF array element - subtype FMR_ENCF_Element is ATSAM3X8E.Bit; - - -- FMR_ENCF array - type FMR_ENCF_Field_Array is array (0 .. 1) of FMR_ENCF_Element + -- TC0_FMR_ENCF array + type TC0_FMR_ENCF_Field_Array is array (0 .. 1) of TC0_FMR_ENCF_Element with Component_Size => 1, Size => 2; - -- Type definition for FMR_ENCF - type FMR_ENCF_Field + -- Type definition for TC0_FMR_ENCF + type TC0_FMR_ENCF_Field (As_Array : Boolean := False) is record case As_Array is @@ -1137,49 +1566,45 @@ package ATSAM3X8E.TC is Val : ATSAM3X8E.UInt2; when True => -- ENCF as an array - Arr : FMR_ENCF_Field_Array; + Arr : TC0_FMR_ENCF_Field_Array; end case; end record with Unchecked_Union, Size => 2; - for FMR_ENCF_Field use record + for TC0_FMR_ENCF_Field use record Val at 0 range 0 .. 1; Arr at 0 range 0 .. 1; end record; -- Fault Mode Register - type FMR_Register is record + type TC0_FMR_Register is record -- ENable Compare Fault Channel 0 - ENCF : FMR_ENCF_Field := (As_Array => False, Val => 16#0#); + ENCF : TC0_FMR_ENCF_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_2_31 : ATSAM3X8E.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FMR_Register use record + for TC0_FMR_Register use record ENCF at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype TC0_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype TC0_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- Write Protect Mode Register - type WPMR_Register is record + type TC0_WPMR_Register is record -- Write Protect Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : TC0_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protect KEY - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : TC0_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for TC0_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; @@ -1189,135 +1614,186 @@ package ATSAM3X8E.TC is -- Peripherals -- ----------------- + type TC0_Disc is + (Default, + Wave_Eq_1); + -- Timer Counter 0 - type TC_Peripheral is record + type TC_Peripheral + (Discriminent : TC0_Disc := Default) + is record -- Channel Control Register (channel = 0) - CCR0 : CCR_Register; - -- Channel Mode Register (channel = 0) - CMR0 : CMR_Register; + CCR0 : aliased CCR_Register; + pragma Volatile_Full_Access (CCR0); -- Stepper Motor Mode Register (channel = 0) - SMMR0 : SMMR_Register; + SMMR0 : aliased SMMR_Register; + pragma Volatile_Full_Access (SMMR0); -- Counter Value (channel = 0) - CV0 : ATSAM3X8E.Word; + CV0 : aliased ATSAM3X8E.UInt32; -- Register A (channel = 0) - RA0 : ATSAM3X8E.Word; + RA0 : aliased ATSAM3X8E.UInt32; -- Register B (channel = 0) - RB0 : ATSAM3X8E.Word; + RB0 : aliased ATSAM3X8E.UInt32; -- Register C (channel = 0) - RC0 : ATSAM3X8E.Word; + RC0 : aliased ATSAM3X8E.UInt32; -- Status Register (channel = 0) - SR0 : SR_Register; + SR0 : aliased SR_Register; + pragma Volatile_Full_Access (SR0); -- Interrupt Enable Register (channel = 0) - IER0 : IER_Register; + IER0 : aliased IER_Register; + pragma Volatile_Full_Access (IER0); -- Interrupt Disable Register (channel = 0) - IDR0 : IDR_Register; + IDR0 : aliased IDR_Register; + pragma Volatile_Full_Access (IDR0); -- Interrupt Mask Register (channel = 0) - IMR0 : IMR_Register; + IMR0 : aliased IMR_Register; + pragma Volatile_Full_Access (IMR0); -- Channel Control Register (channel = 1) - CCR1 : CCR_Register; - -- Channel Mode Register (channel = 1) - CMR1 : CMR_Register; + CCR1 : aliased CCR_Register; + pragma Volatile_Full_Access (CCR1); -- Stepper Motor Mode Register (channel = 1) - SMMR1 : SMMR_Register; + SMMR1 : aliased SMMR_Register; + pragma Volatile_Full_Access (SMMR1); -- Counter Value (channel = 1) - CV1 : ATSAM3X8E.Word; + CV1 : aliased ATSAM3X8E.UInt32; -- Register A (channel = 1) - RA1 : ATSAM3X8E.Word; + RA1 : aliased ATSAM3X8E.UInt32; -- Register B (channel = 1) - RB1 : ATSAM3X8E.Word; + RB1 : aliased ATSAM3X8E.UInt32; -- Register C (channel = 1) - RC1 : ATSAM3X8E.Word; + RC1 : aliased ATSAM3X8E.UInt32; -- Status Register (channel = 1) - SR1 : SR_Register; + SR1 : aliased SR_Register; + pragma Volatile_Full_Access (SR1); -- Interrupt Enable Register (channel = 1) - IER1 : IER_Register; + IER1 : aliased IER_Register; + pragma Volatile_Full_Access (IER1); -- Interrupt Disable Register (channel = 1) - IDR1 : IDR_Register; + IDR1 : aliased IDR_Register; + pragma Volatile_Full_Access (IDR1); -- Interrupt Mask Register (channel = 1) - IMR1 : IMR_Register; + IMR1 : aliased IMR_Register; + pragma Volatile_Full_Access (IMR1); -- Channel Control Register (channel = 2) - CCR2 : CCR_Register; - -- Channel Mode Register (channel = 2) - CMR2 : CMR_Register; + CCR2 : aliased CCR_Register; + pragma Volatile_Full_Access (CCR2); -- Stepper Motor Mode Register (channel = 2) - SMMR2 : SMMR_Register; + SMMR2 : aliased SMMR_Register; + pragma Volatile_Full_Access (SMMR2); -- Counter Value (channel = 2) - CV2 : ATSAM3X8E.Word; + CV2 : aliased ATSAM3X8E.UInt32; -- Register A (channel = 2) - RA2 : ATSAM3X8E.Word; + RA2 : aliased ATSAM3X8E.UInt32; -- Register B (channel = 2) - RB2 : ATSAM3X8E.Word; + RB2 : aliased ATSAM3X8E.UInt32; -- Register C (channel = 2) - RC2 : ATSAM3X8E.Word; + RC2 : aliased ATSAM3X8E.UInt32; -- Status Register (channel = 2) - SR2 : SR_Register; + SR2 : aliased SR_Register; + pragma Volatile_Full_Access (SR2); -- Interrupt Enable Register (channel = 2) - IER2 : IER_Register; + IER2 : aliased IER_Register; + pragma Volatile_Full_Access (IER2); -- Interrupt Disable Register (channel = 2) - IDR2 : IDR_Register; + IDR2 : aliased IDR_Register; + pragma Volatile_Full_Access (IDR2); -- Interrupt Mask Register (channel = 2) - IMR2 : IMR_Register; + IMR2 : aliased IMR_Register; + pragma Volatile_Full_Access (IMR2); -- Block Control Register - BCR : BCR_Register; + BCR : aliased TC0_BCR_Register; + pragma Volatile_Full_Access (BCR); -- Block Mode Register - BMR : BMR_Register; + BMR : aliased TC0_BMR_Register; + pragma Volatile_Full_Access (BMR); -- QDEC Interrupt Enable Register - QIER : QIER_Register; + QIER : aliased TC0_QIER_Register; + pragma Volatile_Full_Access (QIER); -- QDEC Interrupt Disable Register - QIDR : QIDR_Register; + QIDR : aliased TC0_QIDR_Register; + pragma Volatile_Full_Access (QIDR); -- QDEC Interrupt Mask Register - QIMR : QIMR_Register; + QIMR : aliased TC0_QIMR_Register; + pragma Volatile_Full_Access (QIMR); -- QDEC Interrupt Status Register - QISR : QISR_Register; + QISR : aliased TC0_QISR_Register; + pragma Volatile_Full_Access (QISR); -- Fault Mode Register - FMR : FMR_Register; + FMR : aliased TC0_FMR_Register; + pragma Volatile_Full_Access (FMR); -- Write Protect Mode Register - WPMR : WPMR_Register; + WPMR : aliased TC0_WPMR_Register; + pragma Volatile_Full_Access (WPMR); + case Discriminent is + when Default => + -- Channel Mode Register (channel = 0) + CMR0 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR0); + -- Channel Mode Register (channel = 1) + CMR1 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR1); + -- Channel Mode Register (channel = 2) + CMR2 : aliased CMR_Register; + pragma Volatile_Full_Access (CMR2); + when Wave_Eq_1 => + -- Channel Mode Register (channel = 0) + CMR0_WAVE_EQ_1 : aliased TC0_CMR0_WAVE_EQ_1_Register; + pragma Volatile_Full_Access (CMR0_WAVE_EQ_1); + -- Channel Mode Register (channel = 1) + CMR1_WAVE_EQ_1 : aliased TC0_CMR1_WAVE_EQ_1_Register; + pragma Volatile_Full_Access (CMR1_WAVE_EQ_1); + -- Channel Mode Register (channel = 2) + CMR2_WAVE_EQ_1 : aliased TC0_CMR2_WAVE_EQ_1_Register; + pragma Volatile_Full_Access (CMR2_WAVE_EQ_1); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for TC_Peripheral use record - CCR0 at 0 range 0 .. 31; - CMR0 at 4 range 0 .. 31; - SMMR0 at 8 range 0 .. 31; - CV0 at 16 range 0 .. 31; - RA0 at 20 range 0 .. 31; - RB0 at 24 range 0 .. 31; - RC0 at 28 range 0 .. 31; - SR0 at 32 range 0 .. 31; - IER0 at 36 range 0 .. 31; - IDR0 at 40 range 0 .. 31; - IMR0 at 44 range 0 .. 31; - CCR1 at 64 range 0 .. 31; - CMR1 at 68 range 0 .. 31; - SMMR1 at 72 range 0 .. 31; - CV1 at 80 range 0 .. 31; - RA1 at 84 range 0 .. 31; - RB1 at 88 range 0 .. 31; - RC1 at 92 range 0 .. 31; - SR1 at 96 range 0 .. 31; - IER1 at 100 range 0 .. 31; - IDR1 at 104 range 0 .. 31; - IMR1 at 108 range 0 .. 31; - CCR2 at 128 range 0 .. 31; - CMR2 at 132 range 0 .. 31; - SMMR2 at 136 range 0 .. 31; - CV2 at 144 range 0 .. 31; - RA2 at 148 range 0 .. 31; - RB2 at 152 range 0 .. 31; - RC2 at 156 range 0 .. 31; - SR2 at 160 range 0 .. 31; - IER2 at 164 range 0 .. 31; - IDR2 at 168 range 0 .. 31; - IMR2 at 172 range 0 .. 31; - BCR at 192 range 0 .. 31; - BMR at 196 range 0 .. 31; - QIER at 200 range 0 .. 31; - QIDR at 204 range 0 .. 31; - QIMR at 208 range 0 .. 31; - QISR at 212 range 0 .. 31; - FMR at 216 range 0 .. 31; - WPMR at 228 range 0 .. 31; + CCR0 at 16#0# range 0 .. 31; + SMMR0 at 16#8# range 0 .. 31; + CV0 at 16#10# range 0 .. 31; + RA0 at 16#14# range 0 .. 31; + RB0 at 16#18# range 0 .. 31; + RC0 at 16#1C# range 0 .. 31; + SR0 at 16#20# range 0 .. 31; + IER0 at 16#24# range 0 .. 31; + IDR0 at 16#28# range 0 .. 31; + IMR0 at 16#2C# range 0 .. 31; + CCR1 at 16#40# range 0 .. 31; + SMMR1 at 16#48# range 0 .. 31; + CV1 at 16#50# range 0 .. 31; + RA1 at 16#54# range 0 .. 31; + RB1 at 16#58# range 0 .. 31; + RC1 at 16#5C# range 0 .. 31; + SR1 at 16#60# range 0 .. 31; + IER1 at 16#64# range 0 .. 31; + IDR1 at 16#68# range 0 .. 31; + IMR1 at 16#6C# range 0 .. 31; + CCR2 at 16#80# range 0 .. 31; + SMMR2 at 16#88# range 0 .. 31; + CV2 at 16#90# range 0 .. 31; + RA2 at 16#94# range 0 .. 31; + RB2 at 16#98# range 0 .. 31; + RC2 at 16#9C# range 0 .. 31; + SR2 at 16#A0# range 0 .. 31; + IER2 at 16#A4# range 0 .. 31; + IDR2 at 16#A8# range 0 .. 31; + IMR2 at 16#AC# range 0 .. 31; + BCR at 16#C0# range 0 .. 31; + BMR at 16#C4# range 0 .. 31; + QIER at 16#C8# range 0 .. 31; + QIDR at 16#CC# range 0 .. 31; + QIMR at 16#D0# range 0 .. 31; + QISR at 16#D4# range 0 .. 31; + FMR at 16#D8# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + CMR0 at 16#4# range 0 .. 31; + CMR1 at 16#44# range 0 .. 31; + CMR2 at 16#84# range 0 .. 31; + CMR0_WAVE_EQ_1 at 16#4# range 0 .. 31; + CMR1_WAVE_EQ_1 at 16#44# range 0 .. 31; + CMR2_WAVE_EQ_1 at 16#84# range 0 .. 31; end record; -- Timer Counter 0 diff --git a/arduino-due/atsam3x8e/atsam3x8e-trng.ads b/arduino-due/atsam3x8e/atsam3x8e-trng.ads index f87646b..9cda455 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-trng.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-trng.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,106 +15,86 @@ package ATSAM3X8E.TRNG is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_ENABLE_Field is ATSAM3X8E.Bit; - subtype CR_KEY_Field is ATSAM3X8E.UInt24; + subtype TRNG_CR_ENABLE_Field is ATSAM3X8E.Bit; + subtype TRNG_CR_KEY_Field is ATSAM3X8E.UInt24; -- Control Register - type CR_Register is record + type TRNG_CR_Register is record -- Write-only. Enables the TRNG to provide random values - ENABLE : CR_ENABLE_Field := 16#0#; + ENABLE : TRNG_CR_ENABLE_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write-only. Security Key - KEY : CR_KEY_Field := 16#0#; + KEY : TRNG_CR_KEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for TRNG_CR_Register use record ENABLE at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; KEY at 0 range 8 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_DATRDY_Field is ATSAM3X8E.Bit; + subtype TRNG_IER_DATRDY_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type TRNG_IER_Register is record -- Write-only. Data Ready Interrupt Enable - DATRDY : IER_DATRDY_Field := 16#0#; + DATRDY : TRNG_IER_DATRDY_Field := 16#0#; -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for TRNG_IER_Register use record DATRDY at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_DATRDY_Field is ATSAM3X8E.Bit; + subtype TRNG_IDR_DATRDY_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type TRNG_IDR_Register is record -- Write-only. Data Ready Interrupt Disable - DATRDY : IDR_DATRDY_Field := 16#0#; + DATRDY : TRNG_IDR_DATRDY_Field := 16#0#; -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for TRNG_IDR_Register use record DATRDY at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_DATRDY_Field is ATSAM3X8E.Bit; + subtype TRNG_IMR_DATRDY_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type TRNG_IMR_Register is record -- Read-only. Data Ready Interrupt Mask - DATRDY : IMR_DATRDY_Field := 16#0#; + DATRDY : TRNG_IMR_DATRDY_Field; -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for TRNG_IMR_Register use record DATRDY at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ - - subtype ISR_DATRDY_Field is ATSAM3X8E.Bit; + subtype TRNG_ISR_DATRDY_Field is ATSAM3X8E.Bit; -- Interrupt Status Register - type ISR_Register is record + type TRNG_ISR_Register is record -- Read-only. Data Ready - DATRDY : ISR_DATRDY_Field := 16#0#; + DATRDY : TRNG_ISR_DATRDY_Field; -- unspecified Reserved_1_31 : ATSAM3X8E.UInt31; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for ISR_Register use record + for TRNG_ISR_Register use record DATRDY at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; @@ -125,27 +106,32 @@ package ATSAM3X8E.TRNG is -- True Random Number Generator type TRNG_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased TRNG_CR_Register; + pragma Volatile_Full_Access (CR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased TRNG_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased TRNG_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased TRNG_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Interrupt Status Register - ISR : ISR_Register; + ISR : aliased TRNG_ISR_Register; + pragma Volatile_Full_Access (ISR); -- Output Data Register - ODATA : ATSAM3X8E.Word; + ODATA : aliased ATSAM3X8E.UInt32; end record with Volatile; for TRNG_Peripheral use record - CR at 0 range 0 .. 31; - IER at 16 range 0 .. 31; - IDR at 20 range 0 .. 31; - IMR at 24 range 0 .. 31; - ISR at 28 range 0 .. 31; - ODATA at 80 range 0 .. 31; + CR at 16#0# range 0 .. 31; + IER at 16#10# range 0 .. 31; + IDR at 16#14# range 0 .. 31; + IMR at 16#18# range 0 .. 31; + ISR at 16#1C# range 0 .. 31; + ODATA at 16#50# range 0 .. 31; end record; -- True Random Number Generator diff --git a/arduino-due/atsam3x8e/atsam3x8e-twi.ads b/arduino-due/atsam3x8e/atsam3x8e-twi.ads index fe9d540..f3fda91 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-twi.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-twi.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,43 +14,39 @@ package ATSAM3X8E.TWI is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_START_Field is ATSAM3X8E.Bit; - subtype CR_STOP_Field is ATSAM3X8E.Bit; - subtype CR_MSEN_Field is ATSAM3X8E.Bit; - subtype CR_MSDIS_Field is ATSAM3X8E.Bit; - subtype CR_SVEN_Field is ATSAM3X8E.Bit; - subtype CR_SVDIS_Field is ATSAM3X8E.Bit; - subtype CR_QUICK_Field is ATSAM3X8E.Bit; - subtype CR_SWRST_Field is ATSAM3X8E.Bit; + subtype TWI0_CR_START_Field is ATSAM3X8E.Bit; + subtype TWI0_CR_STOP_Field is ATSAM3X8E.Bit; + subtype TWI0_CR_MSEN_Field is ATSAM3X8E.Bit; + subtype TWI0_CR_MSDIS_Field is ATSAM3X8E.Bit; + subtype TWI0_CR_SVEN_Field is ATSAM3X8E.Bit; + subtype TWI0_CR_SVDIS_Field is ATSAM3X8E.Bit; + subtype TWI0_CR_QUICK_Field is ATSAM3X8E.Bit; + subtype TWI0_CR_SWRST_Field is ATSAM3X8E.Bit; -- Control Register - type CR_Register is record + type TWI0_CR_Register is record -- Write-only. Send a START Condition - START : CR_START_Field := 16#0#; + START : TWI0_CR_START_Field := 16#0#; -- Write-only. Send a STOP Condition - STOP : CR_STOP_Field := 16#0#; + STOP : TWI0_CR_STOP_Field := 16#0#; -- Write-only. TWI Master Mode Enabled - MSEN : CR_MSEN_Field := 16#0#; + MSEN : TWI0_CR_MSEN_Field := 16#0#; -- Write-only. TWI Master Mode Disabled - MSDIS : CR_MSDIS_Field := 16#0#; + MSDIS : TWI0_CR_MSDIS_Field := 16#0#; -- Write-only. TWI Slave Mode Enabled - SVEN : CR_SVEN_Field := 16#0#; + SVEN : TWI0_CR_SVEN_Field := 16#0#; -- Write-only. TWI Slave Mode Disabled - SVDIS : CR_SVDIS_Field := 16#0#; + SVDIS : TWI0_CR_SVDIS_Field := 16#0#; -- Write-only. SMBUS Quick Command - QUICK : CR_QUICK_Field := 16#0#; + QUICK : TWI0_CR_QUICK_Field := 16#0#; -- Write-only. Software Reset - SWRST : CR_SWRST_Field := 16#0#; + SWRST : TWI0_CR_SWRST_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for TWI0_CR_Register use record START at 0 range 0 .. 0; STOP at 0 range 1 .. 1; MSEN at 0 range 2 .. 2; @@ -61,51 +58,46 @@ package ATSAM3X8E.TWI is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- MMR_Register -- - ------------------ - -- Internal Device Address Size - type IADRSZ_Field is - ( - -- No internal device address + type MMR_IADRSZ_Field is + (-- No internal device address None, -- One-byte internal device address - IADRSZ_Field_1_Byte, + Val_1_Byte, -- Two-byte internal device address - IADRSZ_Field_2_Byte, + Val_2_Byte, -- Three-byte internal device address - IADRSZ_Field_3_Byte) + Val_3_Byte) with Size => 2; - for IADRSZ_Field use + for MMR_IADRSZ_Field use (None => 0, - IADRSZ_Field_1_Byte => 1, - IADRSZ_Field_2_Byte => 2, - IADRSZ_Field_3_Byte => 3); + Val_1_Byte => 1, + Val_2_Byte => 2, + Val_3_Byte => 3); - subtype MMR_MREAD_Field is ATSAM3X8E.Bit; - subtype MMR_DADR_Field is ATSAM3X8E.UInt7; + subtype TWI0_MMR_MREAD_Field is ATSAM3X8E.Bit; + subtype TWI0_MMR_DADR_Field is ATSAM3X8E.UInt7; -- Master Mode Register - type MMR_Register is record + type TWI0_MMR_Register is record -- unspecified Reserved_0_7 : ATSAM3X8E.Byte := 16#0#; -- Internal Device Address Size - IADRSZ : IADRSZ_Field := None; + IADRSZ : MMR_IADRSZ_Field := ATSAM3X8E.TWI.None; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2 := 16#0#; -- Master Read Direction - MREAD : MMR_MREAD_Field := 16#0#; + MREAD : TWI0_MMR_MREAD_Field := 16#0#; -- unspecified Reserved_13_15 : ATSAM3X8E.UInt3 := 16#0#; -- Device Address - DADR : MMR_DADR_Field := 16#0#; + DADR : TWI0_MMR_DADR_Field := 16#0#; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MMR_Register use record + for TWI0_MMR_Register use record Reserved_0_7 at 0 range 0 .. 7; IADRSZ at 0 range 8 .. 9; Reserved_10_11 at 0 range 10 .. 11; @@ -115,138 +107,122 @@ package ATSAM3X8E.TWI is Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------ - -- SMR_Register -- - ------------------ - - subtype SMR_SADR_Field is ATSAM3X8E.UInt7; + subtype TWI0_SMR_SADR_Field is ATSAM3X8E.UInt7; -- Slave Mode Register - type SMR_Register is record + type TWI0_SMR_Register is record -- unspecified - Reserved_0_15 : ATSAM3X8E.Short := 16#0#; + Reserved_0_15 : ATSAM3X8E.UInt16 := 16#0#; -- Slave Address - SADR : SMR_SADR_Field := 16#0#; + SADR : TWI0_SMR_SADR_Field := 16#0#; -- unspecified Reserved_23_31 : ATSAM3X8E.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SMR_Register use record + for TWI0_SMR_Register use record Reserved_0_15 at 0 range 0 .. 15; SADR at 0 range 16 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- IADR_Register -- - ------------------- - - subtype IADR_IADR_Field is ATSAM3X8E.UInt24; + subtype TWI0_IADR_IADR_Field is ATSAM3X8E.UInt24; -- Internal Address Register - type IADR_Register is record + type TWI0_IADR_Register is record -- Internal Address - IADR : IADR_IADR_Field := 16#0#; + IADR : TWI0_IADR_IADR_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IADR_Register use record + for TWI0_IADR_Register use record IADR at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- CWGR_Register -- - ------------------- - - subtype CWGR_CLDIV_Field is ATSAM3X8E.Byte; - subtype CWGR_CHDIV_Field is ATSAM3X8E.Byte; - subtype CWGR_CKDIV_Field is ATSAM3X8E.UInt3; + subtype TWI0_CWGR_CLDIV_Field is ATSAM3X8E.Byte; + subtype TWI0_CWGR_CHDIV_Field is ATSAM3X8E.Byte; + subtype TWI0_CWGR_CKDIV_Field is ATSAM3X8E.UInt3; -- Clock Waveform Generator Register - type CWGR_Register is record + type TWI0_CWGR_Register is record -- Clock Low Divider - CLDIV : CWGR_CLDIV_Field := 16#0#; + CLDIV : TWI0_CWGR_CLDIV_Field := 16#0#; -- Clock High Divider - CHDIV : CWGR_CHDIV_Field := 16#0#; + CHDIV : TWI0_CWGR_CHDIV_Field := 16#0#; -- Clock Divider - CKDIV : CWGR_CKDIV_Field := 16#0#; + CKDIV : TWI0_CWGR_CKDIV_Field := 16#0#; -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CWGR_Register use record + for TWI0_CWGR_Register use record CLDIV at 0 range 0 .. 7; CHDIV at 0 range 8 .. 15; CKDIV at 0 range 16 .. 18; Reserved_19_31 at 0 range 19 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_TXCOMP_Field is ATSAM3X8E.Bit; - subtype SR_RXRDY_Field is ATSAM3X8E.Bit; - subtype SR_TXRDY_Field is ATSAM3X8E.Bit; - subtype SR_SVREAD_Field is ATSAM3X8E.Bit; - subtype SR_SVACC_Field is ATSAM3X8E.Bit; - subtype SR_GACC_Field is ATSAM3X8E.Bit; - subtype SR_OVRE_Field is ATSAM3X8E.Bit; - subtype SR_NACK_Field is ATSAM3X8E.Bit; - subtype SR_ARBLST_Field is ATSAM3X8E.Bit; - subtype SR_SCLWS_Field is ATSAM3X8E.Bit; - subtype SR_EOSACC_Field is ATSAM3X8E.Bit; - subtype SR_ENDRX_Field is ATSAM3X8E.Bit; - subtype SR_ENDTX_Field is ATSAM3X8E.Bit; - subtype SR_RXBUFF_Field is ATSAM3X8E.Bit; - subtype SR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_TXCOMP_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_RXRDY_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_TXRDY_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_SVREAD_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_SVACC_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_GACC_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_OVRE_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_NACK_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_ARBLST_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_SCLWS_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_EOSACC_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_ENDRX_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_ENDTX_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype TWI0_SR_TXBUFE_Field is ATSAM3X8E.Bit; -- Status Register - type SR_Register is record + type TWI0_SR_Register is record -- Read-only. Transmission Completed (automatically set / reset) - TXCOMP : SR_TXCOMP_Field := 16#1#; + TXCOMP : TWI0_SR_TXCOMP_Field; -- Read-only. Receive Holding Register Ready (automatically set / reset) - RXRDY : SR_RXRDY_Field := 16#0#; + RXRDY : TWI0_SR_RXRDY_Field; -- Read-only. Transmit Holding Register Ready (automatically set / -- reset) - TXRDY : SR_TXRDY_Field := 16#0#; + TXRDY : TWI0_SR_TXRDY_Field; -- Read-only. Slave Read (automatically set / reset) - SVREAD : SR_SVREAD_Field := 16#1#; + SVREAD : TWI0_SR_SVREAD_Field; -- Read-only. Slave Access (automatically set / reset) - SVACC : SR_SVACC_Field := 16#0#; + SVACC : TWI0_SR_SVACC_Field; -- Read-only. General Call Access (clear on read) - GACC : SR_GACC_Field := 16#0#; + GACC : TWI0_SR_GACC_Field; -- Read-only. Overrun Error (clear on read) - OVRE : SR_OVRE_Field := 16#0#; + OVRE : TWI0_SR_OVRE_Field; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit; -- Read-only. Not Acknowledged (clear on read) - NACK : SR_NACK_Field := 16#0#; + NACK : TWI0_SR_NACK_Field; -- Read-only. Arbitration Lost (clear on read) - ARBLST : SR_ARBLST_Field := 16#0#; + ARBLST : TWI0_SR_ARBLST_Field; -- Read-only. Clock Wait State (automatically set / reset) - SCLWS : SR_SCLWS_Field := 16#0#; + SCLWS : TWI0_SR_SCLWS_Field; -- Read-only. End Of Slave Access (clear on read) - EOSACC : SR_EOSACC_Field := 16#0#; + EOSACC : TWI0_SR_EOSACC_Field; -- Read-only. End of RX buffer - ENDRX : SR_ENDRX_Field := 16#1#; + ENDRX : TWI0_SR_ENDRX_Field; -- Read-only. End of TX buffer - ENDTX : SR_ENDTX_Field := 16#1#; + ENDTX : TWI0_SR_ENDTX_Field; -- Read-only. RX Buffer Full - RXBUFF : SR_RXBUFF_Field := 16#1#; + RXBUFF : TWI0_SR_RXBUFF_Field; -- Read-only. TX Buffer Empty - TXBUFE : SR_TXBUFE_Field := 16#1#; + TXBUFE : TWI0_SR_TXBUFE_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for TWI0_SR_Register use record TXCOMP at 0 range 0 .. 0; RXRDY at 0 range 1 .. 1; TXRDY at 0 range 2 .. 2; @@ -266,65 +242,61 @@ package ATSAM3X8E.TWI is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_TXCOMP_Field is ATSAM3X8E.Bit; - subtype IER_RXRDY_Field is ATSAM3X8E.Bit; - subtype IER_TXRDY_Field is ATSAM3X8E.Bit; - subtype IER_SVACC_Field is ATSAM3X8E.Bit; - subtype IER_GACC_Field is ATSAM3X8E.Bit; - subtype IER_OVRE_Field is ATSAM3X8E.Bit; - subtype IER_NACK_Field is ATSAM3X8E.Bit; - subtype IER_ARBLST_Field is ATSAM3X8E.Bit; - subtype IER_SCL_WS_Field is ATSAM3X8E.Bit; - subtype IER_EOSACC_Field is ATSAM3X8E.Bit; - subtype IER_ENDRX_Field is ATSAM3X8E.Bit; - subtype IER_ENDTX_Field is ATSAM3X8E.Bit; - subtype IER_RXBUFF_Field is ATSAM3X8E.Bit; - subtype IER_TXBUFE_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_TXCOMP_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_RXRDY_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_TXRDY_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_SVACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_GACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_OVRE_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_NACK_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_ARBLST_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_SCL_WS_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_EOSACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_ENDRX_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_ENDTX_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_RXBUFF_Field is ATSAM3X8E.Bit; + subtype TWI0_IER_TXBUFE_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type TWI0_IER_Register is record -- Write-only. Transmission Completed Interrupt Enable - TXCOMP : IER_TXCOMP_Field := 16#0#; + TXCOMP : TWI0_IER_TXCOMP_Field := 16#0#; -- Write-only. Receive Holding Register Ready Interrupt Enable - RXRDY : IER_RXRDY_Field := 16#0#; + RXRDY : TWI0_IER_RXRDY_Field := 16#0#; -- Write-only. Transmit Holding Register Ready Interrupt Enable - TXRDY : IER_TXRDY_Field := 16#0#; + TXRDY : TWI0_IER_TXRDY_Field := 16#0#; -- unspecified Reserved_3_3 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Slave Access Interrupt Enable - SVACC : IER_SVACC_Field := 16#0#; + SVACC : TWI0_IER_SVACC_Field := 16#0#; -- Write-only. General Call Access Interrupt Enable - GACC : IER_GACC_Field := 16#0#; + GACC : TWI0_IER_GACC_Field := 16#0#; -- Write-only. Overrun Error Interrupt Enable - OVRE : IER_OVRE_Field := 16#0#; + OVRE : TWI0_IER_OVRE_Field := 16#0#; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Not Acknowledge Interrupt Enable - NACK : IER_NACK_Field := 16#0#; + NACK : TWI0_IER_NACK_Field := 16#0#; -- Write-only. Arbitration Lost Interrupt Enable - ARBLST : IER_ARBLST_Field := 16#0#; + ARBLST : TWI0_IER_ARBLST_Field := 16#0#; -- Write-only. Clock Wait State Interrupt Enable - SCL_WS : IER_SCL_WS_Field := 16#0#; + SCL_WS : TWI0_IER_SCL_WS_Field := 16#0#; -- Write-only. End Of Slave Access Interrupt Enable - EOSACC : IER_EOSACC_Field := 16#0#; + EOSACC : TWI0_IER_EOSACC_Field := 16#0#; -- Write-only. End of Receive Buffer Interrupt Enable - ENDRX : IER_ENDRX_Field := 16#0#; + ENDRX : TWI0_IER_ENDRX_Field := 16#0#; -- Write-only. End of Transmit Buffer Interrupt Enable - ENDTX : IER_ENDTX_Field := 16#0#; + ENDTX : TWI0_IER_ENDTX_Field := 16#0#; -- Write-only. Receive Buffer Full Interrupt Enable - RXBUFF : IER_RXBUFF_Field := 16#0#; + RXBUFF : TWI0_IER_RXBUFF_Field := 16#0#; -- Write-only. Transmit Buffer Empty Interrupt Enable - TXBUFE : IER_TXBUFE_Field := 16#0#; + TXBUFE : TWI0_IER_TXBUFE_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for TWI0_IER_Register use record TXCOMP at 0 range 0 .. 0; RXRDY at 0 range 1 .. 1; TXRDY at 0 range 2 .. 2; @@ -344,65 +316,61 @@ package ATSAM3X8E.TWI is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_TXCOMP_Field is ATSAM3X8E.Bit; - subtype IDR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_SVACC_Field is ATSAM3X8E.Bit; - subtype IDR_GACC_Field is ATSAM3X8E.Bit; - subtype IDR_OVRE_Field is ATSAM3X8E.Bit; - subtype IDR_NACK_Field is ATSAM3X8E.Bit; - subtype IDR_ARBLST_Field is ATSAM3X8E.Bit; - subtype IDR_SCL_WS_Field is ATSAM3X8E.Bit; - subtype IDR_EOSACC_Field is ATSAM3X8E.Bit; - subtype IDR_ENDRX_Field is ATSAM3X8E.Bit; - subtype IDR_ENDTX_Field is ATSAM3X8E.Bit; - subtype IDR_RXBUFF_Field is ATSAM3X8E.Bit; - subtype IDR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_TXCOMP_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_RXRDY_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_TXRDY_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_SVACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_GACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_OVRE_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_NACK_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_ARBLST_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_SCL_WS_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_EOSACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_ENDRX_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_ENDTX_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype TWI0_IDR_TXBUFE_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type TWI0_IDR_Register is record -- Write-only. Transmission Completed Interrupt Disable - TXCOMP : IDR_TXCOMP_Field := 16#0#; + TXCOMP : TWI0_IDR_TXCOMP_Field := 16#0#; -- Write-only. Receive Holding Register Ready Interrupt Disable - RXRDY : IDR_RXRDY_Field := 16#0#; + RXRDY : TWI0_IDR_RXRDY_Field := 16#0#; -- Write-only. Transmit Holding Register Ready Interrupt Disable - TXRDY : IDR_TXRDY_Field := 16#0#; + TXRDY : TWI0_IDR_TXRDY_Field := 16#0#; -- unspecified Reserved_3_3 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Slave Access Interrupt Disable - SVACC : IDR_SVACC_Field := 16#0#; + SVACC : TWI0_IDR_SVACC_Field := 16#0#; -- Write-only. General Call Access Interrupt Disable - GACC : IDR_GACC_Field := 16#0#; + GACC : TWI0_IDR_GACC_Field := 16#0#; -- Write-only. Overrun Error Interrupt Disable - OVRE : IDR_OVRE_Field := 16#0#; + OVRE : TWI0_IDR_OVRE_Field := 16#0#; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Not Acknowledge Interrupt Disable - NACK : IDR_NACK_Field := 16#0#; + NACK : TWI0_IDR_NACK_Field := 16#0#; -- Write-only. Arbitration Lost Interrupt Disable - ARBLST : IDR_ARBLST_Field := 16#0#; + ARBLST : TWI0_IDR_ARBLST_Field := 16#0#; -- Write-only. Clock Wait State Interrupt Disable - SCL_WS : IDR_SCL_WS_Field := 16#0#; + SCL_WS : TWI0_IDR_SCL_WS_Field := 16#0#; -- Write-only. End Of Slave Access Interrupt Disable - EOSACC : IDR_EOSACC_Field := 16#0#; + EOSACC : TWI0_IDR_EOSACC_Field := 16#0#; -- Write-only. End of Receive Buffer Interrupt Disable - ENDRX : IDR_ENDRX_Field := 16#0#; + ENDRX : TWI0_IDR_ENDRX_Field := 16#0#; -- Write-only. End of Transmit Buffer Interrupt Disable - ENDTX : IDR_ENDTX_Field := 16#0#; + ENDTX : TWI0_IDR_ENDTX_Field := 16#0#; -- Write-only. Receive Buffer Full Interrupt Disable - RXBUFF : IDR_RXBUFF_Field := 16#0#; + RXBUFF : TWI0_IDR_RXBUFF_Field := 16#0#; -- Write-only. Transmit Buffer Empty Interrupt Disable - TXBUFE : IDR_TXBUFE_Field := 16#0#; + TXBUFE : TWI0_IDR_TXBUFE_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for TWI0_IDR_Register use record TXCOMP at 0 range 0 .. 0; RXRDY at 0 range 1 .. 1; TXRDY at 0 range 2 .. 2; @@ -422,65 +390,61 @@ package ATSAM3X8E.TWI is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_TXCOMP_Field is ATSAM3X8E.Bit; - subtype IMR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_SVACC_Field is ATSAM3X8E.Bit; - subtype IMR_GACC_Field is ATSAM3X8E.Bit; - subtype IMR_OVRE_Field is ATSAM3X8E.Bit; - subtype IMR_NACK_Field is ATSAM3X8E.Bit; - subtype IMR_ARBLST_Field is ATSAM3X8E.Bit; - subtype IMR_SCL_WS_Field is ATSAM3X8E.Bit; - subtype IMR_EOSACC_Field is ATSAM3X8E.Bit; - subtype IMR_ENDRX_Field is ATSAM3X8E.Bit; - subtype IMR_ENDTX_Field is ATSAM3X8E.Bit; - subtype IMR_RXBUFF_Field is ATSAM3X8E.Bit; - subtype IMR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_TXCOMP_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_RXRDY_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_TXRDY_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_SVACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_GACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_OVRE_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_NACK_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_ARBLST_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_SCL_WS_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_EOSACC_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_ENDRX_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_ENDTX_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype TWI0_IMR_TXBUFE_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type TWI0_IMR_Register is record -- Read-only. Transmission Completed Interrupt Mask - TXCOMP : IMR_TXCOMP_Field := 16#0#; + TXCOMP : TWI0_IMR_TXCOMP_Field; -- Read-only. Receive Holding Register Ready Interrupt Mask - RXRDY : IMR_RXRDY_Field := 16#0#; + RXRDY : TWI0_IMR_RXRDY_Field; -- Read-only. Transmit Holding Register Ready Interrupt Mask - TXRDY : IMR_TXRDY_Field := 16#0#; + TXRDY : TWI0_IMR_TXRDY_Field; -- unspecified Reserved_3_3 : ATSAM3X8E.Bit; -- Read-only. Slave Access Interrupt Mask - SVACC : IMR_SVACC_Field := 16#0#; + SVACC : TWI0_IMR_SVACC_Field; -- Read-only. General Call Access Interrupt Mask - GACC : IMR_GACC_Field := 16#0#; + GACC : TWI0_IMR_GACC_Field; -- Read-only. Overrun Error Interrupt Mask - OVRE : IMR_OVRE_Field := 16#0#; + OVRE : TWI0_IMR_OVRE_Field; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit; -- Read-only. Not Acknowledge Interrupt Mask - NACK : IMR_NACK_Field := 16#0#; + NACK : TWI0_IMR_NACK_Field; -- Read-only. Arbitration Lost Interrupt Mask - ARBLST : IMR_ARBLST_Field := 16#0#; + ARBLST : TWI0_IMR_ARBLST_Field; -- Read-only. Clock Wait State Interrupt Mask - SCL_WS : IMR_SCL_WS_Field := 16#0#; + SCL_WS : TWI0_IMR_SCL_WS_Field; -- Read-only. End Of Slave Access Interrupt Mask - EOSACC : IMR_EOSACC_Field := 16#0#; + EOSACC : TWI0_IMR_EOSACC_Field; -- Read-only. End of Receive Buffer Interrupt Mask - ENDRX : IMR_ENDRX_Field := 16#0#; + ENDRX : TWI0_IMR_ENDRX_Field; -- Read-only. End of Transmit Buffer Interrupt Mask - ENDTX : IMR_ENDTX_Field := 16#0#; + ENDTX : TWI0_IMR_ENDTX_Field; -- Read-only. Receive Buffer Full Interrupt Mask - RXBUFF : IMR_RXBUFF_Field := 16#0#; + RXBUFF : TWI0_IMR_RXBUFF_Field; -- Read-only. Transmit Buffer Empty Interrupt Mask - TXBUFE : IMR_TXBUFE_Field := 16#0#; + TXBUFE : TWI0_IMR_TXBUFE_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for TWI0_IMR_Register use record TXCOMP at 0 range 0 .. 0; RXRDY at 0 range 1 .. 1; TXRDY at 0 range 2 .. 2; @@ -500,153 +464,125 @@ package ATSAM3X8E.TWI is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- RHR_Register -- - ------------------ - - subtype RHR_RXDATA_Field is ATSAM3X8E.Byte; + subtype TWI0_RHR_RXDATA_Field is ATSAM3X8E.Byte; -- Receive Holding Register - type RHR_Register is record + type TWI0_RHR_Register is record -- Read-only. Master or Slave Receive Holding Data - RXDATA : RHR_RXDATA_Field := 16#0#; + RXDATA : TWI0_RHR_RXDATA_Field; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RHR_Register use record + for TWI0_RHR_Register use record RXDATA at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- THR_Register -- - ------------------ - - subtype THR_TXDATA_Field is ATSAM3X8E.Byte; + subtype TWI0_THR_TXDATA_Field is ATSAM3X8E.Byte; -- Transmit Holding Register - type THR_Register is record + type TWI0_THR_Register is record -- Write-only. Master or Slave Transmit Holding Data - TXDATA : THR_TXDATA_Field := 16#0#; + TXDATA : TWI0_THR_TXDATA_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for THR_Register use record + for TWI0_THR_Register use record TXDATA at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- RCR_Register -- - ------------------ - - subtype RCR_RXCTR_Field is ATSAM3X8E.Short; + subtype TWI0_RCR_RXCTR_Field is ATSAM3X8E.UInt16; -- Receive Counter Register - type RCR_Register is record + type TWI0_RCR_Register is record -- Receive Counter Register - RXCTR : RCR_RXCTR_Field := 16#0#; + RXCTR : TWI0_RCR_RXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RCR_Register use record + for TWI0_RCR_Register use record RXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- TCR_Register -- - ------------------ - - subtype TCR_TXCTR_Field is ATSAM3X8E.Short; + subtype TWI0_TCR_TXCTR_Field is ATSAM3X8E.UInt16; -- Transmit Counter Register - type TCR_Register is record + type TWI0_TCR_Register is record -- Transmit Counter Register - TXCTR : TCR_TXCTR_Field := 16#0#; + TXCTR : TWI0_TCR_TXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TCR_Register use record + for TWI0_TCR_Register use record TXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- RNCR_Register -- - ------------------- - - subtype RNCR_RXNCTR_Field is ATSAM3X8E.Short; + subtype TWI0_RNCR_RXNCTR_Field is ATSAM3X8E.UInt16; -- Receive Next Counter Register - type RNCR_Register is record + type TWI0_RNCR_Register is record -- Receive Next Counter - RXNCTR : RNCR_RXNCTR_Field := 16#0#; + RXNCTR : TWI0_RNCR_RXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RNCR_Register use record + for TWI0_RNCR_Register use record RXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- TNCR_Register -- - ------------------- - - subtype TNCR_TXNCTR_Field is ATSAM3X8E.Short; + subtype TWI0_TNCR_TXNCTR_Field is ATSAM3X8E.UInt16; -- Transmit Next Counter Register - type TNCR_Register is record + type TWI0_TNCR_Register is record -- Transmit Counter Next - TXNCTR : TNCR_TXNCTR_Field := 16#0#; + TXNCTR : TWI0_TNCR_TXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TNCR_Register use record + for TWI0_TNCR_Register use record TXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- PTCR_Register -- - ------------------- - - subtype PTCR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_RXTDIS_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTDIS_Field is ATSAM3X8E.Bit; + subtype TWI0_PTCR_RXTEN_Field is ATSAM3X8E.Bit; + subtype TWI0_PTCR_RXTDIS_Field is ATSAM3X8E.Bit; + subtype TWI0_PTCR_TXTEN_Field is ATSAM3X8E.Bit; + subtype TWI0_PTCR_TXTDIS_Field is ATSAM3X8E.Bit; -- Transfer Control Register - type PTCR_Register is record + type TWI0_PTCR_Register is record -- Write-only. Receiver Transfer Enable - RXTEN : PTCR_RXTEN_Field := 16#0#; + RXTEN : TWI0_PTCR_RXTEN_Field := 16#0#; -- Write-only. Receiver Transfer Disable - RXTDIS : PTCR_RXTDIS_Field := 16#0#; + RXTDIS : TWI0_PTCR_RXTDIS_Field := 16#0#; -- unspecified Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; -- Write-only. Transmitter Transfer Enable - TXTEN : PTCR_TXTEN_Field := 16#0#; + TXTEN : TWI0_PTCR_TXTEN_Field := 16#0#; -- Write-only. Transmitter Transfer Disable - TXTDIS : PTCR_TXTDIS_Field := 16#0#; + TXTDIS : TWI0_PTCR_TXTDIS_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTCR_Register use record + for TWI0_PTCR_Register use record RXTEN at 0 range 0 .. 0; RXTDIS at 0 range 1 .. 1; Reserved_2_7 at 0 range 2 .. 7; @@ -655,27 +591,23 @@ package ATSAM3X8E.TWI is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- PTSR_Register -- - ------------------- - - subtype PTSR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTSR_TXTEN_Field is ATSAM3X8E.Bit; + subtype TWI0_PTSR_RXTEN_Field is ATSAM3X8E.Bit; + subtype TWI0_PTSR_TXTEN_Field is ATSAM3X8E.Bit; -- Transfer Status Register - type PTSR_Register is record + type TWI0_PTSR_Register is record -- Read-only. Receiver Transfer Enable - RXTEN : PTSR_RXTEN_Field := 16#0#; + RXTEN : TWI0_PTSR_RXTEN_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Transmitter Transfer Enable - TXTEN : PTSR_TXTEN_Field := 16#0#; + TXTEN : TWI0_PTSR_TXTEN_Field; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTSR_Register use record + for TWI0_PTSR_Register use record RXTEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; TXTEN at 0 range 8 .. 8; @@ -689,72 +621,89 @@ package ATSAM3X8E.TWI is -- Two-wire Interface 0 type TWI_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased TWI0_CR_Register; + pragma Volatile_Full_Access (CR); -- Master Mode Register - MMR : MMR_Register; + MMR : aliased TWI0_MMR_Register; + pragma Volatile_Full_Access (MMR); -- Slave Mode Register - SMR : SMR_Register; + SMR : aliased TWI0_SMR_Register; + pragma Volatile_Full_Access (SMR); -- Internal Address Register - IADR : IADR_Register; + IADR : aliased TWI0_IADR_Register; + pragma Volatile_Full_Access (IADR); -- Clock Waveform Generator Register - CWGR : CWGR_Register; + CWGR : aliased TWI0_CWGR_Register; + pragma Volatile_Full_Access (CWGR); -- Status Register - SR : SR_Register; + SR : aliased TWI0_SR_Register; + pragma Volatile_Full_Access (SR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased TWI0_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased TWI0_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased TWI0_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Receive Holding Register - RHR : RHR_Register; + RHR : aliased TWI0_RHR_Register; + pragma Volatile_Full_Access (RHR); -- Transmit Holding Register - THR : THR_Register; + THR : aliased TWI0_THR_Register; + pragma Volatile_Full_Access (THR); -- Receive Pointer Register - RPR : ATSAM3X8E.Word; + RPR : aliased ATSAM3X8E.UInt32; -- Receive Counter Register - RCR : RCR_Register; + RCR : aliased TWI0_RCR_Register; + pragma Volatile_Full_Access (RCR); -- Transmit Pointer Register - TPR : ATSAM3X8E.Word; + TPR : aliased ATSAM3X8E.UInt32; -- Transmit Counter Register - TCR : TCR_Register; + TCR : aliased TWI0_TCR_Register; + pragma Volatile_Full_Access (TCR); -- Receive Next Pointer Register - RNPR : ATSAM3X8E.Word; + RNPR : aliased ATSAM3X8E.UInt32; -- Receive Next Counter Register - RNCR : RNCR_Register; + RNCR : aliased TWI0_RNCR_Register; + pragma Volatile_Full_Access (RNCR); -- Transmit Next Pointer Register - TNPR : ATSAM3X8E.Word; + TNPR : aliased ATSAM3X8E.UInt32; -- Transmit Next Counter Register - TNCR : TNCR_Register; + TNCR : aliased TWI0_TNCR_Register; + pragma Volatile_Full_Access (TNCR); -- Transfer Control Register - PTCR : PTCR_Register; + PTCR : aliased TWI0_PTCR_Register; + pragma Volatile_Full_Access (PTCR); -- Transfer Status Register - PTSR : PTSR_Register; + PTSR : aliased TWI0_PTSR_Register; + pragma Volatile_Full_Access (PTSR); end record with Volatile; for TWI_Peripheral use record - CR at 0 range 0 .. 31; - MMR at 4 range 0 .. 31; - SMR at 8 range 0 .. 31; - IADR at 12 range 0 .. 31; - CWGR at 16 range 0 .. 31; - SR at 32 range 0 .. 31; - IER at 36 range 0 .. 31; - IDR at 40 range 0 .. 31; - IMR at 44 range 0 .. 31; - RHR at 48 range 0 .. 31; - THR at 52 range 0 .. 31; - RPR at 256 range 0 .. 31; - RCR at 260 range 0 .. 31; - TPR at 264 range 0 .. 31; - TCR at 268 range 0 .. 31; - RNPR at 272 range 0 .. 31; - RNCR at 276 range 0 .. 31; - TNPR at 280 range 0 .. 31; - TNCR at 284 range 0 .. 31; - PTCR at 288 range 0 .. 31; - PTSR at 292 range 0 .. 31; + CR at 16#0# range 0 .. 31; + MMR at 16#4# range 0 .. 31; + SMR at 16#8# range 0 .. 31; + IADR at 16#C# range 0 .. 31; + CWGR at 16#10# range 0 .. 31; + SR at 16#20# range 0 .. 31; + IER at 16#24# range 0 .. 31; + IDR at 16#28# range 0 .. 31; + IMR at 16#2C# range 0 .. 31; + RHR at 16#30# range 0 .. 31; + THR at 16#34# range 0 .. 31; + RPR at 16#100# range 0 .. 31; + RCR at 16#104# range 0 .. 31; + TPR at 16#108# range 0 .. 31; + TCR at 16#10C# range 0 .. 31; + RNPR at 16#110# range 0 .. 31; + RNCR at 16#114# range 0 .. 31; + TNPR at 16#118# range 0 .. 31; + TNCR at 16#11C# range 0 .. 31; + PTCR at 16#120# range 0 .. 31; + PTSR at 16#124# range 0 .. 31; end record; -- Two-wire Interface 0 diff --git a/arduino-due/atsam3x8e/atsam3x8e-uart.ads b/arduino-due/atsam3x8e/atsam3x8e-uart.ads index b0edcf8..7f009bc 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-uart.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-uart.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,42 +15,38 @@ package ATSAM3X8E.UART is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_RSTRX_Field is ATSAM3X8E.Bit; - subtype CR_RSTTX_Field is ATSAM3X8E.Bit; - subtype CR_RXEN_Field is ATSAM3X8E.Bit; - subtype CR_RXDIS_Field is ATSAM3X8E.Bit; - subtype CR_TXEN_Field is ATSAM3X8E.Bit; - subtype CR_TXDIS_Field is ATSAM3X8E.Bit; - subtype CR_RSTSTA_Field is ATSAM3X8E.Bit; + subtype UART_CR_RSTRX_Field is ATSAM3X8E.Bit; + subtype UART_CR_RSTTX_Field is ATSAM3X8E.Bit; + subtype UART_CR_RXEN_Field is ATSAM3X8E.Bit; + subtype UART_CR_RXDIS_Field is ATSAM3X8E.Bit; + subtype UART_CR_TXEN_Field is ATSAM3X8E.Bit; + subtype UART_CR_TXDIS_Field is ATSAM3X8E.Bit; + subtype UART_CR_RSTSTA_Field is ATSAM3X8E.Bit; -- Control Register - type CR_Register is record + type UART_CR_Register is record -- unspecified Reserved_0_1 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Reset Receiver - RSTRX : CR_RSTRX_Field := 16#0#; + RSTRX : UART_CR_RSTRX_Field := 16#0#; -- Write-only. Reset Transmitter - RSTTX : CR_RSTTX_Field := 16#0#; + RSTTX : UART_CR_RSTTX_Field := 16#0#; -- Write-only. Receiver Enable - RXEN : CR_RXEN_Field := 16#0#; + RXEN : UART_CR_RXEN_Field := 16#0#; -- Write-only. Receiver Disable - RXDIS : CR_RXDIS_Field := 16#0#; + RXDIS : UART_CR_RXDIS_Field := 16#0#; -- Write-only. Transmitter Enable - TXEN : CR_TXEN_Field := 16#0#; + TXEN : UART_CR_TXEN_Field := 16#0#; -- Write-only. Transmitter Disable - TXDIS : CR_TXDIS_Field := 16#0#; + TXDIS : UART_CR_TXDIS_Field := 16#0#; -- Write-only. Reset Status Bits - RSTSTA : CR_RSTSTA_Field := 16#0#; + RSTSTA : UART_CR_RSTSTA_Field := 16#0#; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for UART_CR_Register use record Reserved_0_1 at 0 range 0 .. 1; RSTRX at 0 range 2 .. 2; RSTTX at 0 range 3 .. 3; @@ -61,14 +58,9 @@ package ATSAM3X8E.UART is Reserved_9_31 at 0 range 9 .. 31; end record; - ----------------- - -- MR_Register -- - ----------------- - -- Parity Type - type PAR_Field is - ( - -- Even parity + type MR_PAR_Field is + (-- Even parity Even, -- Odd parity Odd, @@ -79,7 +71,7 @@ package ATSAM3X8E.UART is -- No parity No) with Size => 3; - for PAR_Field use + for MR_PAR_Field use (Even => 0, Odd => 1, Space => 2, @@ -87,9 +79,8 @@ package ATSAM3X8E.UART is No => 4); -- Channel Mode - type CHMODE_Field is - ( - -- Normal Mode + type MR_CHMODE_Field is + (-- Normal Mode Normal, -- Automatic Echo Automatic, @@ -98,28 +89,28 @@ package ATSAM3X8E.UART is -- Remote Loopback Remote_Loopback) with Size => 2; - for CHMODE_Field use + for MR_CHMODE_Field use (Normal => 0, Automatic => 1, Local_Loopback => 2, Remote_Loopback => 3); -- Mode Register - type MR_Register is record + type UART_MR_Register is record -- unspecified Reserved_0_8 : ATSAM3X8E.UInt9 := 16#0#; -- Parity Type - PAR : PAR_Field := Even; + PAR : MR_PAR_Field := ATSAM3X8E.UART.Even; -- unspecified Reserved_12_13 : ATSAM3X8E.UInt2 := 16#0#; -- Channel Mode - CHMODE : CHMODE_Field := Normal; + CHMODE : MR_CHMODE_Field := ATSAM3X8E.UART.Normal; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_Register use record + for UART_MR_Register use record Reserved_0_8 at 0 range 0 .. 8; PAR at 0 range 9 .. 11; Reserved_12_13 at 0 range 12 .. 13; @@ -127,55 +118,51 @@ package ATSAM3X8E.UART is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_RXRDY_Field is ATSAM3X8E.Bit; - subtype IER_TXRDY_Field is ATSAM3X8E.Bit; - subtype IER_ENDRX_Field is ATSAM3X8E.Bit; - subtype IER_ENDTX_Field is ATSAM3X8E.Bit; - subtype IER_OVRE_Field is ATSAM3X8E.Bit; - subtype IER_FRAME_Field is ATSAM3X8E.Bit; - subtype IER_PARE_Field is ATSAM3X8E.Bit; - subtype IER_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IER_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IER_RXBUFF_Field is ATSAM3X8E.Bit; + subtype UART_IER_RXRDY_Field is ATSAM3X8E.Bit; + subtype UART_IER_TXRDY_Field is ATSAM3X8E.Bit; + subtype UART_IER_ENDRX_Field is ATSAM3X8E.Bit; + subtype UART_IER_ENDTX_Field is ATSAM3X8E.Bit; + subtype UART_IER_OVRE_Field is ATSAM3X8E.Bit; + subtype UART_IER_FRAME_Field is ATSAM3X8E.Bit; + subtype UART_IER_PARE_Field is ATSAM3X8E.Bit; + subtype UART_IER_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype UART_IER_TXBUFE_Field is ATSAM3X8E.Bit; + subtype UART_IER_RXBUFF_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type UART_IER_Register is record -- Write-only. Enable RXRDY Interrupt - RXRDY : IER_RXRDY_Field := 16#0#; + RXRDY : UART_IER_RXRDY_Field := 16#0#; -- Write-only. Enable TXRDY Interrupt - TXRDY : IER_TXRDY_Field := 16#0#; + TXRDY : UART_IER_TXRDY_Field := 16#0#; -- unspecified Reserved_2_2 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Enable End of Receive Transfer Interrupt - ENDRX : IER_ENDRX_Field := 16#0#; + ENDRX : UART_IER_ENDRX_Field := 16#0#; -- Write-only. Enable End of Transmit Interrupt - ENDTX : IER_ENDTX_Field := 16#0#; + ENDTX : UART_IER_ENDTX_Field := 16#0#; -- Write-only. Enable Overrun Error Interrupt - OVRE : IER_OVRE_Field := 16#0#; + OVRE : UART_IER_OVRE_Field := 16#0#; -- Write-only. Enable Framing Error Interrupt - FRAME : IER_FRAME_Field := 16#0#; + FRAME : UART_IER_FRAME_Field := 16#0#; -- Write-only. Enable Parity Error Interrupt - PARE : IER_PARE_Field := 16#0#; + PARE : UART_IER_PARE_Field := 16#0#; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Enable TXEMPTY Interrupt - TXEMPTY : IER_TXEMPTY_Field := 16#0#; + TXEMPTY : UART_IER_TXEMPTY_Field := 16#0#; -- unspecified Reserved_10_10 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Enable Buffer Empty Interrupt - TXBUFE : IER_TXBUFE_Field := 16#0#; + TXBUFE : UART_IER_TXBUFE_Field := 16#0#; -- Write-only. Enable Buffer Full Interrupt - RXBUFF : IER_RXBUFF_Field := 16#0#; + RXBUFF : UART_IER_RXBUFF_Field := 16#0#; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for UART_IER_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_2 at 0 range 2 .. 2; @@ -192,55 +179,51 @@ package ATSAM3X8E.UART is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_ENDRX_Field is ATSAM3X8E.Bit; - subtype IDR_ENDTX_Field is ATSAM3X8E.Bit; - subtype IDR_OVRE_Field is ATSAM3X8E.Bit; - subtype IDR_FRAME_Field is ATSAM3X8E.Bit; - subtype IDR_PARE_Field is ATSAM3X8E.Bit; - subtype IDR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IDR_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IDR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype UART_IDR_RXRDY_Field is ATSAM3X8E.Bit; + subtype UART_IDR_TXRDY_Field is ATSAM3X8E.Bit; + subtype UART_IDR_ENDRX_Field is ATSAM3X8E.Bit; + subtype UART_IDR_ENDTX_Field is ATSAM3X8E.Bit; + subtype UART_IDR_OVRE_Field is ATSAM3X8E.Bit; + subtype UART_IDR_FRAME_Field is ATSAM3X8E.Bit; + subtype UART_IDR_PARE_Field is ATSAM3X8E.Bit; + subtype UART_IDR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype UART_IDR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype UART_IDR_RXBUFF_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type UART_IDR_Register is record -- Write-only. Disable RXRDY Interrupt - RXRDY : IDR_RXRDY_Field := 16#0#; + RXRDY : UART_IDR_RXRDY_Field := 16#0#; -- Write-only. Disable TXRDY Interrupt - TXRDY : IDR_TXRDY_Field := 16#0#; + TXRDY : UART_IDR_TXRDY_Field := 16#0#; -- unspecified Reserved_2_2 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Disable End of Receive Transfer Interrupt - ENDRX : IDR_ENDRX_Field := 16#0#; + ENDRX : UART_IDR_ENDRX_Field := 16#0#; -- Write-only. Disable End of Transmit Interrupt - ENDTX : IDR_ENDTX_Field := 16#0#; + ENDTX : UART_IDR_ENDTX_Field := 16#0#; -- Write-only. Disable Overrun Error Interrupt - OVRE : IDR_OVRE_Field := 16#0#; + OVRE : UART_IDR_OVRE_Field := 16#0#; -- Write-only. Disable Framing Error Interrupt - FRAME : IDR_FRAME_Field := 16#0#; + FRAME : UART_IDR_FRAME_Field := 16#0#; -- Write-only. Disable Parity Error Interrupt - PARE : IDR_PARE_Field := 16#0#; + PARE : UART_IDR_PARE_Field := 16#0#; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Disable TXEMPTY Interrupt - TXEMPTY : IDR_TXEMPTY_Field := 16#0#; + TXEMPTY : UART_IDR_TXEMPTY_Field := 16#0#; -- unspecified Reserved_10_10 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Disable Buffer Empty Interrupt - TXBUFE : IDR_TXBUFE_Field := 16#0#; + TXBUFE : UART_IDR_TXBUFE_Field := 16#0#; -- Write-only. Disable Buffer Full Interrupt - RXBUFF : IDR_RXBUFF_Field := 16#0#; + RXBUFF : UART_IDR_RXBUFF_Field := 16#0#; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for UART_IDR_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_2 at 0 range 2 .. 2; @@ -257,55 +240,51 @@ package ATSAM3X8E.UART is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_ENDRX_Field is ATSAM3X8E.Bit; - subtype IMR_ENDTX_Field is ATSAM3X8E.Bit; - subtype IMR_OVRE_Field is ATSAM3X8E.Bit; - subtype IMR_FRAME_Field is ATSAM3X8E.Bit; - subtype IMR_PARE_Field is ATSAM3X8E.Bit; - subtype IMR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IMR_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IMR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype UART_IMR_RXRDY_Field is ATSAM3X8E.Bit; + subtype UART_IMR_TXRDY_Field is ATSAM3X8E.Bit; + subtype UART_IMR_ENDRX_Field is ATSAM3X8E.Bit; + subtype UART_IMR_ENDTX_Field is ATSAM3X8E.Bit; + subtype UART_IMR_OVRE_Field is ATSAM3X8E.Bit; + subtype UART_IMR_FRAME_Field is ATSAM3X8E.Bit; + subtype UART_IMR_PARE_Field is ATSAM3X8E.Bit; + subtype UART_IMR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype UART_IMR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype UART_IMR_RXBUFF_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type UART_IMR_Register is record -- Read-only. Mask RXRDY Interrupt - RXRDY : IMR_RXRDY_Field := 16#0#; + RXRDY : UART_IMR_RXRDY_Field; -- Read-only. Disable TXRDY Interrupt - TXRDY : IMR_TXRDY_Field := 16#0#; + TXRDY : UART_IMR_TXRDY_Field; -- unspecified Reserved_2_2 : ATSAM3X8E.Bit; -- Read-only. Mask End of Receive Transfer Interrupt - ENDRX : IMR_ENDRX_Field := 16#0#; + ENDRX : UART_IMR_ENDRX_Field; -- Read-only. Mask End of Transmit Interrupt - ENDTX : IMR_ENDTX_Field := 16#0#; + ENDTX : UART_IMR_ENDTX_Field; -- Read-only. Mask Overrun Error Interrupt - OVRE : IMR_OVRE_Field := 16#0#; + OVRE : UART_IMR_OVRE_Field; -- Read-only. Mask Framing Error Interrupt - FRAME : IMR_FRAME_Field := 16#0#; + FRAME : UART_IMR_FRAME_Field; -- Read-only. Mask Parity Error Interrupt - PARE : IMR_PARE_Field := 16#0#; + PARE : UART_IMR_PARE_Field; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit; -- Read-only. Mask TXEMPTY Interrupt - TXEMPTY : IMR_TXEMPTY_Field := 16#0#; + TXEMPTY : UART_IMR_TXEMPTY_Field; -- unspecified Reserved_10_10 : ATSAM3X8E.Bit; -- Read-only. Mask TXBUFE Interrupt - TXBUFE : IMR_TXBUFE_Field := 16#0#; + TXBUFE : UART_IMR_TXBUFE_Field; -- Read-only. Mask RXBUFF Interrupt - RXBUFF : IMR_RXBUFF_Field := 16#0#; + RXBUFF : UART_IMR_RXBUFF_Field; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for UART_IMR_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_2 at 0 range 2 .. 2; @@ -322,55 +301,51 @@ package ATSAM3X8E.UART is Reserved_13_31 at 0 range 13 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_RXRDY_Field is ATSAM3X8E.Bit; - subtype SR_TXRDY_Field is ATSAM3X8E.Bit; - subtype SR_ENDRX_Field is ATSAM3X8E.Bit; - subtype SR_ENDTX_Field is ATSAM3X8E.Bit; - subtype SR_OVRE_Field is ATSAM3X8E.Bit; - subtype SR_FRAME_Field is ATSAM3X8E.Bit; - subtype SR_PARE_Field is ATSAM3X8E.Bit; - subtype SR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype SR_TXBUFE_Field is ATSAM3X8E.Bit; - subtype SR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype UART_SR_RXRDY_Field is ATSAM3X8E.Bit; + subtype UART_SR_TXRDY_Field is ATSAM3X8E.Bit; + subtype UART_SR_ENDRX_Field is ATSAM3X8E.Bit; + subtype UART_SR_ENDTX_Field is ATSAM3X8E.Bit; + subtype UART_SR_OVRE_Field is ATSAM3X8E.Bit; + subtype UART_SR_FRAME_Field is ATSAM3X8E.Bit; + subtype UART_SR_PARE_Field is ATSAM3X8E.Bit; + subtype UART_SR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype UART_SR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype UART_SR_RXBUFF_Field is ATSAM3X8E.Bit; -- Status Register - type SR_Register is record + type UART_SR_Register is record -- Read-only. Receiver Ready - RXRDY : SR_RXRDY_Field := 16#0#; + RXRDY : UART_SR_RXRDY_Field; -- Read-only. Transmitter Ready - TXRDY : SR_TXRDY_Field := 16#0#; + TXRDY : UART_SR_TXRDY_Field; -- unspecified Reserved_2_2 : ATSAM3X8E.Bit; -- Read-only. End of Receiver Transfer - ENDRX : SR_ENDRX_Field := 16#0#; + ENDRX : UART_SR_ENDRX_Field; -- Read-only. End of Transmitter Transfer - ENDTX : SR_ENDTX_Field := 16#0#; + ENDTX : UART_SR_ENDTX_Field; -- Read-only. Overrun Error - OVRE : SR_OVRE_Field := 16#0#; + OVRE : UART_SR_OVRE_Field; -- Read-only. Framing Error - FRAME : SR_FRAME_Field := 16#0#; + FRAME : UART_SR_FRAME_Field; -- Read-only. Parity Error - PARE : SR_PARE_Field := 16#0#; + PARE : UART_SR_PARE_Field; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit; -- Read-only. Transmitter Empty - TXEMPTY : SR_TXEMPTY_Field := 16#0#; + TXEMPTY : UART_SR_TXEMPTY_Field; -- unspecified Reserved_10_10 : ATSAM3X8E.Bit; -- Read-only. Transmission Buffer Empty - TXBUFE : SR_TXBUFE_Field := 16#0#; + TXBUFE : UART_SR_TXBUFE_Field; -- Read-only. Receive Buffer Full - RXBUFF : SR_RXBUFF_Field := 16#0#; + RXBUFF : UART_SR_RXBUFF_Field; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for UART_SR_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_2 at 0 range 2 .. 2; @@ -387,173 +362,141 @@ package ATSAM3X8E.UART is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------ - -- RHR_Register -- - ------------------ - - subtype RHR_RXCHR_Field is ATSAM3X8E.Byte; + subtype UART_RHR_RXCHR_Field is ATSAM3X8E.Byte; -- Receive Holding Register - type RHR_Register is record + type UART_RHR_Register is record -- Read-only. Received Character - RXCHR : RHR_RXCHR_Field := 16#0#; + RXCHR : UART_RHR_RXCHR_Field; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RHR_Register use record + for UART_RHR_Register use record RXCHR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- THR_Register -- - ------------------ - - subtype THR_TXCHR_Field is ATSAM3X8E.Byte; + subtype UART_THR_TXCHR_Field is ATSAM3X8E.Byte; -- Transmit Holding Register - type THR_Register is record + type UART_THR_Register is record -- Write-only. Character to be Transmitted - TXCHR : THR_TXCHR_Field := 16#0#; + TXCHR : UART_THR_TXCHR_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for THR_Register use record + for UART_THR_Register use record TXCHR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- BRGR_Register -- - ------------------- - - subtype BRGR_CD_Field is ATSAM3X8E.Short; + subtype UART_BRGR_CD_Field is ATSAM3X8E.UInt16; -- Baud Rate Generator Register - type BRGR_Register is record + type UART_BRGR_Register is record -- Clock Divisor - CD : BRGR_CD_Field := 16#0#; + CD : UART_BRGR_CD_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for BRGR_Register use record + for UART_BRGR_Register use record CD at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- RCR_Register -- - ------------------ - - subtype RCR_RXCTR_Field is ATSAM3X8E.Short; + subtype UART_RCR_RXCTR_Field is ATSAM3X8E.UInt16; -- Receive Counter Register - type RCR_Register is record + type UART_RCR_Register is record -- Receive Counter Register - RXCTR : RCR_RXCTR_Field := 16#0#; + RXCTR : UART_RCR_RXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RCR_Register use record + for UART_RCR_Register use record RXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- TCR_Register -- - ------------------ - - subtype TCR_TXCTR_Field is ATSAM3X8E.Short; + subtype UART_TCR_TXCTR_Field is ATSAM3X8E.UInt16; -- Transmit Counter Register - type TCR_Register is record + type UART_TCR_Register is record -- Transmit Counter Register - TXCTR : TCR_TXCTR_Field := 16#0#; + TXCTR : UART_TCR_TXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TCR_Register use record + for UART_TCR_Register use record TXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- RNCR_Register -- - ------------------- - - subtype RNCR_RXNCTR_Field is ATSAM3X8E.Short; + subtype UART_RNCR_RXNCTR_Field is ATSAM3X8E.UInt16; -- Receive Next Counter Register - type RNCR_Register is record + type UART_RNCR_Register is record -- Receive Next Counter - RXNCTR : RNCR_RXNCTR_Field := 16#0#; + RXNCTR : UART_RNCR_RXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RNCR_Register use record + for UART_RNCR_Register use record RXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- TNCR_Register -- - ------------------- - - subtype TNCR_TXNCTR_Field is ATSAM3X8E.Short; + subtype UART_TNCR_TXNCTR_Field is ATSAM3X8E.UInt16; -- Transmit Next Counter Register - type TNCR_Register is record + type UART_TNCR_Register is record -- Transmit Counter Next - TXNCTR : TNCR_TXNCTR_Field := 16#0#; + TXNCTR : UART_TNCR_TXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TNCR_Register use record + for UART_TNCR_Register use record TXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- PTCR_Register -- - ------------------- - - subtype PTCR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_RXTDIS_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTDIS_Field is ATSAM3X8E.Bit; + subtype UART_PTCR_RXTEN_Field is ATSAM3X8E.Bit; + subtype UART_PTCR_RXTDIS_Field is ATSAM3X8E.Bit; + subtype UART_PTCR_TXTEN_Field is ATSAM3X8E.Bit; + subtype UART_PTCR_TXTDIS_Field is ATSAM3X8E.Bit; -- Transfer Control Register - type PTCR_Register is record + type UART_PTCR_Register is record -- Write-only. Receiver Transfer Enable - RXTEN : PTCR_RXTEN_Field := 16#0#; + RXTEN : UART_PTCR_RXTEN_Field := 16#0#; -- Write-only. Receiver Transfer Disable - RXTDIS : PTCR_RXTDIS_Field := 16#0#; + RXTDIS : UART_PTCR_RXTDIS_Field := 16#0#; -- unspecified Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; -- Write-only. Transmitter Transfer Enable - TXTEN : PTCR_TXTEN_Field := 16#0#; + TXTEN : UART_PTCR_TXTEN_Field := 16#0#; -- Write-only. Transmitter Transfer Disable - TXTDIS : PTCR_TXTDIS_Field := 16#0#; + TXTDIS : UART_PTCR_TXTDIS_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTCR_Register use record + for UART_PTCR_Register use record RXTEN at 0 range 0 .. 0; RXTDIS at 0 range 1 .. 1; Reserved_2_7 at 0 range 2 .. 7; @@ -562,27 +505,23 @@ package ATSAM3X8E.UART is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- PTSR_Register -- - ------------------- - - subtype PTSR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTSR_TXTEN_Field is ATSAM3X8E.Bit; + subtype UART_PTSR_RXTEN_Field is ATSAM3X8E.Bit; + subtype UART_PTSR_TXTEN_Field is ATSAM3X8E.Bit; -- Transfer Status Register - type PTSR_Register is record + type UART_PTSR_Register is record -- Read-only. Receiver Transfer Enable - RXTEN : PTSR_RXTEN_Field := 16#0#; + RXTEN : UART_PTSR_RXTEN_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Transmitter Transfer Enable - TXTEN : PTSR_TXTEN_Field := 16#0#; + TXTEN : UART_PTSR_TXTEN_Field; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTSR_Register use record + for UART_PTSR_Register use record RXTEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; TXTEN at 0 range 8 .. 8; @@ -596,66 +535,81 @@ package ATSAM3X8E.UART is -- Universal Asynchronous Receiver Transmitter type UART_Peripheral is record -- Control Register - CR : CR_Register; + CR : aliased UART_CR_Register; + pragma Volatile_Full_Access (CR); -- Mode Register - MR : MR_Register; + MR : aliased UART_MR_Register; + pragma Volatile_Full_Access (MR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased UART_IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Disable Register - IDR : IDR_Register; + IDR : aliased UART_IDR_Register; + pragma Volatile_Full_Access (IDR); -- Interrupt Mask Register - IMR : IMR_Register; + IMR : aliased UART_IMR_Register; + pragma Volatile_Full_Access (IMR); -- Status Register - SR : SR_Register; + SR : aliased UART_SR_Register; + pragma Volatile_Full_Access (SR); -- Receive Holding Register - RHR : RHR_Register; + RHR : aliased UART_RHR_Register; + pragma Volatile_Full_Access (RHR); -- Transmit Holding Register - THR : THR_Register; + THR : aliased UART_THR_Register; + pragma Volatile_Full_Access (THR); -- Baud Rate Generator Register - BRGR : BRGR_Register; + BRGR : aliased UART_BRGR_Register; + pragma Volatile_Full_Access (BRGR); -- Receive Pointer Register - RPR : ATSAM3X8E.Word; + RPR : aliased ATSAM3X8E.UInt32; -- Receive Counter Register - RCR : RCR_Register; + RCR : aliased UART_RCR_Register; + pragma Volatile_Full_Access (RCR); -- Transmit Pointer Register - TPR : ATSAM3X8E.Word; + TPR : aliased ATSAM3X8E.UInt32; -- Transmit Counter Register - TCR : TCR_Register; + TCR : aliased UART_TCR_Register; + pragma Volatile_Full_Access (TCR); -- Receive Next Pointer Register - RNPR : ATSAM3X8E.Word; + RNPR : aliased ATSAM3X8E.UInt32; -- Receive Next Counter Register - RNCR : RNCR_Register; + RNCR : aliased UART_RNCR_Register; + pragma Volatile_Full_Access (RNCR); -- Transmit Next Pointer Register - TNPR : ATSAM3X8E.Word; + TNPR : aliased ATSAM3X8E.UInt32; -- Transmit Next Counter Register - TNCR : TNCR_Register; + TNCR : aliased UART_TNCR_Register; + pragma Volatile_Full_Access (TNCR); -- Transfer Control Register - PTCR : PTCR_Register; + PTCR : aliased UART_PTCR_Register; + pragma Volatile_Full_Access (PTCR); -- Transfer Status Register - PTSR : PTSR_Register; + PTSR : aliased UART_PTSR_Register; + pragma Volatile_Full_Access (PTSR); end record with Volatile; for UART_Peripheral use record - CR at 0 range 0 .. 31; - MR at 4 range 0 .. 31; - IER at 8 range 0 .. 31; - IDR at 12 range 0 .. 31; - IMR at 16 range 0 .. 31; - SR at 20 range 0 .. 31; - RHR at 24 range 0 .. 31; - THR at 28 range 0 .. 31; - BRGR at 32 range 0 .. 31; - RPR at 256 range 0 .. 31; - RCR at 260 range 0 .. 31; - TPR at 264 range 0 .. 31; - TCR at 268 range 0 .. 31; - RNPR at 272 range 0 .. 31; - RNCR at 276 range 0 .. 31; - TNPR at 280 range 0 .. 31; - TNCR at 284 range 0 .. 31; - PTCR at 288 range 0 .. 31; - PTSR at 292 range 0 .. 31; + CR at 16#0# range 0 .. 31; + MR at 16#4# range 0 .. 31; + IER at 16#8# range 0 .. 31; + IDR at 16#C# range 0 .. 31; + IMR at 16#10# range 0 .. 31; + SR at 16#14# range 0 .. 31; + RHR at 16#18# range 0 .. 31; + THR at 16#1C# range 0 .. 31; + BRGR at 16#20# range 0 .. 31; + RPR at 16#100# range 0 .. 31; + RCR at 16#104# range 0 .. 31; + TPR at 16#108# range 0 .. 31; + TCR at 16#10C# range 0 .. 31; + RNPR at 16#110# range 0 .. 31; + RNCR at 16#114# range 0 .. 31; + TNPR at 16#118# range 0 .. 31; + TNCR at 16#11C# range 0 .. 31; + PTCR at 16#120# range 0 .. 31; + PTSR at 16#124# range 0 .. 31; end record; -- Universal Asynchronous Receiver Transmitter diff --git a/arduino-due/atsam3x8e/atsam3x8e-uotghs.ads b/arduino-due/atsam3x8e/atsam3x8e-uotghs.ads index 85c89d8..947025a 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-uotghs.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-uotghs.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -14,70 +15,64 @@ package ATSAM3X8E.UOTGHS is -- Registers -- --------------- - ---------------------- - -- DEVCTRL_Register -- - ---------------------- - - subtype DEVCTRL_UADD_Field is ATSAM3X8E.UInt7; - subtype DEVCTRL_ADDEN_Field is ATSAM3X8E.Bit; - subtype DEVCTRL_DETACH_Field is ATSAM3X8E.Bit; - subtype DEVCTRL_RMWKUP_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVCTRL_UADD_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_DEVCTRL_ADDEN_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVCTRL_DETACH_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVCTRL_RMWKUP_Field is ATSAM3X8E.Bit; -- Mode Configuration - type SPDCONF_Field is - ( - -- The peripheral starts in full-speed mode and performs a high-speed - -- reset to switch to the high-speed mode if the host is high-speed - -- capable. + type DEVCTRL_SPDCONF_Field is + (-- The peripheral starts in full-speed mode and performs a high-speed reset to +-- switch to the high-speed mode if the host is high-speed capable. Normal, -- For a better consumption, if high-speed is not needed. Low_Power, -- Forced high speed. High_Speed, -- The peripheral remains in full-speed mode whatever the host speed - -- capability. +-- capability. Forced_Fs) with Size => 2; - for SPDCONF_Field use + for DEVCTRL_SPDCONF_Field use (Normal => 0, Low_Power => 1, High_Speed => 2, Forced_Fs => 3); - subtype DEVCTRL_LS_Field is ATSAM3X8E.Bit; - subtype DEVCTRL_TSTJ_Field is ATSAM3X8E.Bit; - subtype DEVCTRL_TSTK_Field is ATSAM3X8E.Bit; - subtype DEVCTRL_TSTPCKT_Field is ATSAM3X8E.Bit; - subtype DEVCTRL_OPMODE2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVCTRL_LS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVCTRL_TSTJ_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVCTRL_TSTK_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVCTRL_TSTPCKT_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVCTRL_OPMODE2_Field is ATSAM3X8E.Bit; -- Device General Control Register - type DEVCTRL_Register is record + type UOTGHS_DEVCTRL_Register is record -- USB Address - UADD : DEVCTRL_UADD_Field := 16#0#; + UADD : UOTGHS_DEVCTRL_UADD_Field := 16#0#; -- Address Enable - ADDEN : DEVCTRL_ADDEN_Field := 16#0#; + ADDEN : UOTGHS_DEVCTRL_ADDEN_Field := 16#0#; -- Detach - DETACH : DEVCTRL_DETACH_Field := 16#1#; + DETACH : UOTGHS_DEVCTRL_DETACH_Field := 16#1#; -- Remote Wake-Up - RMWKUP : DEVCTRL_RMWKUP_Field := 16#0#; + RMWKUP : UOTGHS_DEVCTRL_RMWKUP_Field := 16#0#; -- Mode Configuration - SPDCONF : SPDCONF_Field := Normal; + SPDCONF : DEVCTRL_SPDCONF_Field := ATSAM3X8E.UOTGHS.Normal; -- Low-Speed Mode Force - LS : DEVCTRL_LS_Field := 16#0#; + LS : UOTGHS_DEVCTRL_LS_Field := 16#0#; -- Test mode J - TSTJ : DEVCTRL_TSTJ_Field := 16#0#; + TSTJ : UOTGHS_DEVCTRL_TSTJ_Field := 16#0#; -- Test mode K - TSTK : DEVCTRL_TSTK_Field := 16#0#; + TSTK : UOTGHS_DEVCTRL_TSTK_Field := 16#0#; -- Test packet mode - TSTPCKT : DEVCTRL_TSTPCKT_Field := 16#0#; + TSTPCKT : UOTGHS_DEVCTRL_TSTPCKT_Field := 16#0#; -- Specific Operational mode - OPMODE2 : DEVCTRL_OPMODE2_Field := 16#0#; + OPMODE2 : UOTGHS_DEVCTRL_OPMODE2_Field := 16#0#; -- unspecified Reserved_17_31 : ATSAM3X8E.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVCTRL_Register use record + for UOTGHS_DEVCTRL_Register use record UADD at 0 range 0 .. 6; ADDEN at 0 range 7 .. 7; DETACH at 0 range 8 .. 8; @@ -91,92 +86,88 @@ package ATSAM3X8E.UOTGHS is Reserved_17_31 at 0 range 17 .. 31; end record; - --------------------- - -- DEVISR_Register -- - --------------------- - - subtype DEVISR_SUSP_Field is ATSAM3X8E.Bit; - subtype DEVISR_MSOF_Field is ATSAM3X8E.Bit; - subtype DEVISR_SOF_Field is ATSAM3X8E.Bit; - subtype DEVISR_EORST_Field is ATSAM3X8E.Bit; - subtype DEVISR_WAKEUP_Field is ATSAM3X8E.Bit; - subtype DEVISR_EORSM_Field is ATSAM3X8E.Bit; - subtype DEVISR_UPRSM_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_0_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_1_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_2_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_3_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_4_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_5_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_6_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_7_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_8_Field is ATSAM3X8E.Bit; - subtype DEVISR_PEP_9_Field is ATSAM3X8E.Bit; - subtype DEVISR_DMA_1_Field is ATSAM3X8E.Bit; - subtype DEVISR_DMA_2_Field is ATSAM3X8E.Bit; - subtype DEVISR_DMA_3_Field is ATSAM3X8E.Bit; - subtype DEVISR_DMA_4_Field is ATSAM3X8E.Bit; - subtype DEVISR_DMA_5_Field is ATSAM3X8E.Bit; - subtype DEVISR_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_SUSP_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_MSOF_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_SOF_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_EORST_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_WAKEUP_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_EORSM_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_UPRSM_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_0_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_7_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_8_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_PEP_9_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVISR_DMA_6_Field is ATSAM3X8E.Bit; -- Device Global Interrupt Status Register - type DEVISR_Register is record + type UOTGHS_DEVISR_Register is record -- Read-only. Suspend Interrupt - SUSP : DEVISR_SUSP_Field := 16#0#; + SUSP : UOTGHS_DEVISR_SUSP_Field; -- Read-only. Micro Start of Frame Interrupt - MSOF : DEVISR_MSOF_Field := 16#0#; + MSOF : UOTGHS_DEVISR_MSOF_Field; -- Read-only. Start of Frame Interrupt - SOF : DEVISR_SOF_Field := 16#0#; + SOF : UOTGHS_DEVISR_SOF_Field; -- Read-only. End of Reset Interrupt - EORST : DEVISR_EORST_Field := 16#0#; + EORST : UOTGHS_DEVISR_EORST_Field; -- Read-only. Wake-Up Interrupt - WAKEUP : DEVISR_WAKEUP_Field := 16#0#; + WAKEUP : UOTGHS_DEVISR_WAKEUP_Field; -- Read-only. End of Resume Interrupt - EORSM : DEVISR_EORSM_Field := 16#0#; + EORSM : UOTGHS_DEVISR_EORSM_Field; -- Read-only. Upstream Resume Interrupt - UPRSM : DEVISR_UPRSM_Field := 16#0#; + UPRSM : UOTGHS_DEVISR_UPRSM_Field; -- unspecified Reserved_7_11 : ATSAM3X8E.UInt5; -- Read-only. Endpoint 0 Interrupt - PEP_0 : DEVISR_PEP_0_Field := 16#0#; + PEP_0 : UOTGHS_DEVISR_PEP_0_Field; -- Read-only. Endpoint 1 Interrupt - PEP_1 : DEVISR_PEP_1_Field := 16#0#; + PEP_1 : UOTGHS_DEVISR_PEP_1_Field; -- Read-only. Endpoint 2 Interrupt - PEP_2 : DEVISR_PEP_2_Field := 16#0#; + PEP_2 : UOTGHS_DEVISR_PEP_2_Field; -- Read-only. Endpoint 3 Interrupt - PEP_3 : DEVISR_PEP_3_Field := 16#0#; + PEP_3 : UOTGHS_DEVISR_PEP_3_Field; -- Read-only. Endpoint 4 Interrupt - PEP_4 : DEVISR_PEP_4_Field := 16#0#; + PEP_4 : UOTGHS_DEVISR_PEP_4_Field; -- Read-only. Endpoint 5 Interrupt - PEP_5 : DEVISR_PEP_5_Field := 16#0#; + PEP_5 : UOTGHS_DEVISR_PEP_5_Field; -- Read-only. Endpoint 6 Interrupt - PEP_6 : DEVISR_PEP_6_Field := 16#0#; + PEP_6 : UOTGHS_DEVISR_PEP_6_Field; -- Read-only. Endpoint 7 Interrupt - PEP_7 : DEVISR_PEP_7_Field := 16#0#; + PEP_7 : UOTGHS_DEVISR_PEP_7_Field; -- Read-only. Endpoint 8 Interrupt - PEP_8 : DEVISR_PEP_8_Field := 16#0#; + PEP_8 : UOTGHS_DEVISR_PEP_8_Field; -- Read-only. Endpoint 9 Interrupt - PEP_9 : DEVISR_PEP_9_Field := 16#0#; + PEP_9 : UOTGHS_DEVISR_PEP_9_Field; -- unspecified Reserved_22_24 : ATSAM3X8E.UInt3; -- Read-only. DMA Channel 1 Interrupt - DMA_1 : DEVISR_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_DEVISR_DMA_1_Field; -- Read-only. DMA Channel 2 Interrupt - DMA_2 : DEVISR_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_DEVISR_DMA_2_Field; -- Read-only. DMA Channel 3 Interrupt - DMA_3 : DEVISR_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_DEVISR_DMA_3_Field; -- Read-only. DMA Channel 4 Interrupt - DMA_4 : DEVISR_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_DEVISR_DMA_4_Field; -- Read-only. DMA Channel 5 Interrupt - DMA_5 : DEVISR_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_DEVISR_DMA_5_Field; -- Read-only. DMA Channel 6 Interrupt - DMA_6 : DEVISR_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_DEVISR_DMA_6_Field; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVISR_Register use record + for UOTGHS_DEVISR_Register use record SUSP at 0 range 0 .. 0; MSOF at 0 range 1 .. 1; SOF at 0 range 2 .. 2; @@ -205,40 +196,36 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- DEVICR_Register -- - --------------------- - - subtype DEVICR_SUSPC_Field is ATSAM3X8E.Bit; - subtype DEVICR_MSOFC_Field is ATSAM3X8E.Bit; - subtype DEVICR_SOFC_Field is ATSAM3X8E.Bit; - subtype DEVICR_EORSTC_Field is ATSAM3X8E.Bit; - subtype DEVICR_WAKEUPC_Field is ATSAM3X8E.Bit; - subtype DEVICR_EORSMC_Field is ATSAM3X8E.Bit; - subtype DEVICR_UPRSMC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVICR_SUSPC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVICR_MSOFC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVICR_SOFC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVICR_EORSTC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVICR_WAKEUPC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVICR_EORSMC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVICR_UPRSMC_Field is ATSAM3X8E.Bit; -- Device Global Interrupt Clear Register - type DEVICR_Register is record + type UOTGHS_DEVICR_Register is record -- Write-only. Suspend Interrupt Clear - SUSPC : DEVICR_SUSPC_Field := 16#0#; + SUSPC : UOTGHS_DEVICR_SUSPC_Field := 16#0#; -- Write-only. Micro Start of Frame Interrupt Clear - MSOFC : DEVICR_MSOFC_Field := 16#0#; + MSOFC : UOTGHS_DEVICR_MSOFC_Field := 16#0#; -- Write-only. Start of Frame Interrupt Clear - SOFC : DEVICR_SOFC_Field := 16#0#; + SOFC : UOTGHS_DEVICR_SOFC_Field := 16#0#; -- Write-only. End of Reset Interrupt Clear - EORSTC : DEVICR_EORSTC_Field := 16#0#; + EORSTC : UOTGHS_DEVICR_EORSTC_Field := 16#0#; -- Write-only. Wake-Up Interrupt Clear - WAKEUPC : DEVICR_WAKEUPC_Field := 16#0#; + WAKEUPC : UOTGHS_DEVICR_WAKEUPC_Field := 16#0#; -- Write-only. End of Resume Interrupt Clear - EORSMC : DEVICR_EORSMC_Field := 16#0#; + EORSMC : UOTGHS_DEVICR_EORSMC_Field := 16#0#; -- Write-only. Upstream Resume Interrupt Clear - UPRSMC : DEVICR_UPRSMC_Field := 16#0#; + UPRSMC : UOTGHS_DEVICR_UPRSMC_Field := 16#0#; -- unspecified Reserved_7_31 : ATSAM3X8E.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVICR_Register use record + for UOTGHS_DEVICR_Register use record SUSPC at 0 range 0 .. 0; MSOFC at 0 range 1 .. 1; SOFC at 0 range 2 .. 2; @@ -249,60 +236,56 @@ package ATSAM3X8E.UOTGHS is Reserved_7_31 at 0 range 7 .. 31; end record; - --------------------- - -- DEVIFR_Register -- - --------------------- - - subtype DEVIFR_SUSPS_Field is ATSAM3X8E.Bit; - subtype DEVIFR_MSOFS_Field is ATSAM3X8E.Bit; - subtype DEVIFR_SOFS_Field is ATSAM3X8E.Bit; - subtype DEVIFR_EORSTS_Field is ATSAM3X8E.Bit; - subtype DEVIFR_WAKEUPS_Field is ATSAM3X8E.Bit; - subtype DEVIFR_EORSMS_Field is ATSAM3X8E.Bit; - subtype DEVIFR_UPRSMS_Field is ATSAM3X8E.Bit; - subtype DEVIFR_DMA_1_Field is ATSAM3X8E.Bit; - subtype DEVIFR_DMA_2_Field is ATSAM3X8E.Bit; - subtype DEVIFR_DMA_3_Field is ATSAM3X8E.Bit; - subtype DEVIFR_DMA_4_Field is ATSAM3X8E.Bit; - subtype DEVIFR_DMA_5_Field is ATSAM3X8E.Bit; - subtype DEVIFR_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_SUSPS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_MSOFS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_SOFS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_EORSTS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_WAKEUPS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_EORSMS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_UPRSMS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIFR_DMA_6_Field is ATSAM3X8E.Bit; -- Device Global Interrupt Set Register - type DEVIFR_Register is record + type UOTGHS_DEVIFR_Register is record -- Write-only. Suspend Interrupt Set - SUSPS : DEVIFR_SUSPS_Field := 16#0#; + SUSPS : UOTGHS_DEVIFR_SUSPS_Field := 16#0#; -- Write-only. Micro Start of Frame Interrupt Set - MSOFS : DEVIFR_MSOFS_Field := 16#0#; + MSOFS : UOTGHS_DEVIFR_MSOFS_Field := 16#0#; -- Write-only. Start of Frame Interrupt Set - SOFS : DEVIFR_SOFS_Field := 16#0#; + SOFS : UOTGHS_DEVIFR_SOFS_Field := 16#0#; -- Write-only. End of Reset Interrupt Set - EORSTS : DEVIFR_EORSTS_Field := 16#0#; + EORSTS : UOTGHS_DEVIFR_EORSTS_Field := 16#0#; -- Write-only. Wake-Up Interrupt Set - WAKEUPS : DEVIFR_WAKEUPS_Field := 16#0#; + WAKEUPS : UOTGHS_DEVIFR_WAKEUPS_Field := 16#0#; -- Write-only. End of Resume Interrupt Set - EORSMS : DEVIFR_EORSMS_Field := 16#0#; + EORSMS : UOTGHS_DEVIFR_EORSMS_Field := 16#0#; -- Write-only. Upstream Resume Interrupt Set - UPRSMS : DEVIFR_UPRSMS_Field := 16#0#; + UPRSMS : UOTGHS_DEVIFR_UPRSMS_Field := 16#0#; -- unspecified Reserved_7_24 : ATSAM3X8E.UInt18 := 16#0#; -- Write-only. DMA Channel 1 Interrupt Set - DMA_1 : DEVIFR_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_DEVIFR_DMA_1_Field := 16#0#; -- Write-only. DMA Channel 2 Interrupt Set - DMA_2 : DEVIFR_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_DEVIFR_DMA_2_Field := 16#0#; -- Write-only. DMA Channel 3 Interrupt Set - DMA_3 : DEVIFR_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_DEVIFR_DMA_3_Field := 16#0#; -- Write-only. DMA Channel 4 Interrupt Set - DMA_4 : DEVIFR_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_DEVIFR_DMA_4_Field := 16#0#; -- Write-only. DMA Channel 5 Interrupt Set - DMA_5 : DEVIFR_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_DEVIFR_DMA_5_Field := 16#0#; -- Write-only. DMA Channel 6 Interrupt Set - DMA_6 : DEVIFR_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_DEVIFR_DMA_6_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVIFR_Register use record + for UOTGHS_DEVIFR_Register use record SUSPS at 0 range 0 .. 0; MSOFS at 0 range 1 .. 1; SOFS at 0 range 2 .. 2; @@ -320,92 +303,88 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- DEVIMR_Register -- - --------------------- - - subtype DEVIMR_SUSPE_Field is ATSAM3X8E.Bit; - subtype DEVIMR_MSOFE_Field is ATSAM3X8E.Bit; - subtype DEVIMR_SOFE_Field is ATSAM3X8E.Bit; - subtype DEVIMR_EORSTE_Field is ATSAM3X8E.Bit; - subtype DEVIMR_WAKEUPE_Field is ATSAM3X8E.Bit; - subtype DEVIMR_EORSME_Field is ATSAM3X8E.Bit; - subtype DEVIMR_UPRSME_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_0_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_1_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_2_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_3_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_4_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_5_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_6_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_7_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_8_Field is ATSAM3X8E.Bit; - subtype DEVIMR_PEP_9_Field is ATSAM3X8E.Bit; - subtype DEVIMR_DMA_1_Field is ATSAM3X8E.Bit; - subtype DEVIMR_DMA_2_Field is ATSAM3X8E.Bit; - subtype DEVIMR_DMA_3_Field is ATSAM3X8E.Bit; - subtype DEVIMR_DMA_4_Field is ATSAM3X8E.Bit; - subtype DEVIMR_DMA_5_Field is ATSAM3X8E.Bit; - subtype DEVIMR_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_SUSPE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_MSOFE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_SOFE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_EORSTE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_WAKEUPE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_EORSME_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_UPRSME_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_0_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_7_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_8_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_PEP_9_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIMR_DMA_6_Field is ATSAM3X8E.Bit; -- Device Global Interrupt Mask Register - type DEVIMR_Register is record + type UOTGHS_DEVIMR_Register is record -- Read-only. Suspend Interrupt Mask - SUSPE : DEVIMR_SUSPE_Field := 16#0#; + SUSPE : UOTGHS_DEVIMR_SUSPE_Field; -- Read-only. Micro Start of Frame Interrupt Mask - MSOFE : DEVIMR_MSOFE_Field := 16#0#; + MSOFE : UOTGHS_DEVIMR_MSOFE_Field; -- Read-only. Start of Frame Interrupt Mask - SOFE : DEVIMR_SOFE_Field := 16#0#; + SOFE : UOTGHS_DEVIMR_SOFE_Field; -- Read-only. End of Reset Interrupt Mask - EORSTE : DEVIMR_EORSTE_Field := 16#0#; + EORSTE : UOTGHS_DEVIMR_EORSTE_Field; -- Read-only. Wake-Up Interrupt Mask - WAKEUPE : DEVIMR_WAKEUPE_Field := 16#0#; + WAKEUPE : UOTGHS_DEVIMR_WAKEUPE_Field; -- Read-only. End of Resume Interrupt Mask - EORSME : DEVIMR_EORSME_Field := 16#0#; + EORSME : UOTGHS_DEVIMR_EORSME_Field; -- Read-only. Upstream Resume Interrupt Mask - UPRSME : DEVIMR_UPRSME_Field := 16#0#; + UPRSME : UOTGHS_DEVIMR_UPRSME_Field; -- unspecified Reserved_7_11 : ATSAM3X8E.UInt5; -- Read-only. Endpoint 0 Interrupt Mask - PEP_0 : DEVIMR_PEP_0_Field := 16#0#; + PEP_0 : UOTGHS_DEVIMR_PEP_0_Field; -- Read-only. Endpoint 1 Interrupt Mask - PEP_1 : DEVIMR_PEP_1_Field := 16#0#; + PEP_1 : UOTGHS_DEVIMR_PEP_1_Field; -- Read-only. Endpoint 2 Interrupt Mask - PEP_2 : DEVIMR_PEP_2_Field := 16#0#; + PEP_2 : UOTGHS_DEVIMR_PEP_2_Field; -- Read-only. Endpoint 3 Interrupt Mask - PEP_3 : DEVIMR_PEP_3_Field := 16#0#; + PEP_3 : UOTGHS_DEVIMR_PEP_3_Field; -- Read-only. Endpoint 4 Interrupt Mask - PEP_4 : DEVIMR_PEP_4_Field := 16#0#; + PEP_4 : UOTGHS_DEVIMR_PEP_4_Field; -- Read-only. Endpoint 5 Interrupt Mask - PEP_5 : DEVIMR_PEP_5_Field := 16#0#; + PEP_5 : UOTGHS_DEVIMR_PEP_5_Field; -- Read-only. Endpoint 6 Interrupt Mask - PEP_6 : DEVIMR_PEP_6_Field := 16#0#; + PEP_6 : UOTGHS_DEVIMR_PEP_6_Field; -- Read-only. Endpoint 7 Interrupt Mask - PEP_7 : DEVIMR_PEP_7_Field := 16#0#; + PEP_7 : UOTGHS_DEVIMR_PEP_7_Field; -- Read-only. Endpoint 8 Interrupt Mask - PEP_8 : DEVIMR_PEP_8_Field := 16#0#; + PEP_8 : UOTGHS_DEVIMR_PEP_8_Field; -- Read-only. Endpoint 9 Interrupt Mask - PEP_9 : DEVIMR_PEP_9_Field := 16#0#; + PEP_9 : UOTGHS_DEVIMR_PEP_9_Field; -- unspecified Reserved_22_24 : ATSAM3X8E.UInt3; -- Read-only. DMA Channel 1 Interrupt Mask - DMA_1 : DEVIMR_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_DEVIMR_DMA_1_Field; -- Read-only. DMA Channel 2 Interrupt Mask - DMA_2 : DEVIMR_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_DEVIMR_DMA_2_Field; -- Read-only. DMA Channel 3 Interrupt Mask - DMA_3 : DEVIMR_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_DEVIMR_DMA_3_Field; -- Read-only. DMA Channel 4 Interrupt Mask - DMA_4 : DEVIMR_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_DEVIMR_DMA_4_Field; -- Read-only. DMA Channel 5 Interrupt Mask - DMA_5 : DEVIMR_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_DEVIMR_DMA_5_Field; -- Read-only. DMA Channel 6 Interrupt Mask - DMA_6 : DEVIMR_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_DEVIMR_DMA_6_Field; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVIMR_Register use record + for UOTGHS_DEVIMR_Register use record SUSPE at 0 range 0 .. 0; MSOFE at 0 range 1 .. 1; SOFE at 0 range 2 .. 2; @@ -434,92 +413,88 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- DEVIDR_Register -- - --------------------- - - subtype DEVIDR_SUSPEC_Field is ATSAM3X8E.Bit; - subtype DEVIDR_MSOFEC_Field is ATSAM3X8E.Bit; - subtype DEVIDR_SOFEC_Field is ATSAM3X8E.Bit; - subtype DEVIDR_EORSTEC_Field is ATSAM3X8E.Bit; - subtype DEVIDR_WAKEUPEC_Field is ATSAM3X8E.Bit; - subtype DEVIDR_EORSMEC_Field is ATSAM3X8E.Bit; - subtype DEVIDR_UPRSMEC_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_0_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_1_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_2_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_3_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_4_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_5_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_6_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_7_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_8_Field is ATSAM3X8E.Bit; - subtype DEVIDR_PEP_9_Field is ATSAM3X8E.Bit; - subtype DEVIDR_DMA_1_Field is ATSAM3X8E.Bit; - subtype DEVIDR_DMA_2_Field is ATSAM3X8E.Bit; - subtype DEVIDR_DMA_3_Field is ATSAM3X8E.Bit; - subtype DEVIDR_DMA_4_Field is ATSAM3X8E.Bit; - subtype DEVIDR_DMA_5_Field is ATSAM3X8E.Bit; - subtype DEVIDR_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_SUSPEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_MSOFEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_SOFEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_EORSTEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_WAKEUPEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_EORSMEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_UPRSMEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_0_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_7_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_8_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_PEP_9_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIDR_DMA_6_Field is ATSAM3X8E.Bit; -- Device Global Interrupt Disable Register - type DEVIDR_Register is record + type UOTGHS_DEVIDR_Register is record -- Write-only. Suspend Interrupt Disable - SUSPEC : DEVIDR_SUSPEC_Field := 16#0#; + SUSPEC : UOTGHS_DEVIDR_SUSPEC_Field := 16#0#; -- Write-only. Micro Start of Frame Interrupt Disable - MSOFEC : DEVIDR_MSOFEC_Field := 16#0#; + MSOFEC : UOTGHS_DEVIDR_MSOFEC_Field := 16#0#; -- Write-only. Start of Frame Interrupt Disable - SOFEC : DEVIDR_SOFEC_Field := 16#0#; + SOFEC : UOTGHS_DEVIDR_SOFEC_Field := 16#0#; -- Write-only. End of Reset Interrupt Disable - EORSTEC : DEVIDR_EORSTEC_Field := 16#0#; + EORSTEC : UOTGHS_DEVIDR_EORSTEC_Field := 16#0#; -- Write-only. Wake-Up Interrupt Disable - WAKEUPEC : DEVIDR_WAKEUPEC_Field := 16#0#; + WAKEUPEC : UOTGHS_DEVIDR_WAKEUPEC_Field := 16#0#; -- Write-only. End of Resume Interrupt Disable - EORSMEC : DEVIDR_EORSMEC_Field := 16#0#; + EORSMEC : UOTGHS_DEVIDR_EORSMEC_Field := 16#0#; -- Write-only. Upstream Resume Interrupt Disable - UPRSMEC : DEVIDR_UPRSMEC_Field := 16#0#; + UPRSMEC : UOTGHS_DEVIDR_UPRSMEC_Field := 16#0#; -- unspecified Reserved_7_11 : ATSAM3X8E.UInt5 := 16#0#; -- Write-only. Endpoint 0 Interrupt Disable - PEP_0 : DEVIDR_PEP_0_Field := 16#0#; + PEP_0 : UOTGHS_DEVIDR_PEP_0_Field := 16#0#; -- Write-only. Endpoint 1 Interrupt Disable - PEP_1 : DEVIDR_PEP_1_Field := 16#0#; + PEP_1 : UOTGHS_DEVIDR_PEP_1_Field := 16#0#; -- Write-only. Endpoint 2 Interrupt Disable - PEP_2 : DEVIDR_PEP_2_Field := 16#0#; + PEP_2 : UOTGHS_DEVIDR_PEP_2_Field := 16#0#; -- Write-only. Endpoint 3 Interrupt Disable - PEP_3 : DEVIDR_PEP_3_Field := 16#0#; + PEP_3 : UOTGHS_DEVIDR_PEP_3_Field := 16#0#; -- Write-only. Endpoint 4 Interrupt Disable - PEP_4 : DEVIDR_PEP_4_Field := 16#0#; + PEP_4 : UOTGHS_DEVIDR_PEP_4_Field := 16#0#; -- Write-only. Endpoint 5 Interrupt Disable - PEP_5 : DEVIDR_PEP_5_Field := 16#0#; + PEP_5 : UOTGHS_DEVIDR_PEP_5_Field := 16#0#; -- Write-only. Endpoint 6 Interrupt Disable - PEP_6 : DEVIDR_PEP_6_Field := 16#0#; + PEP_6 : UOTGHS_DEVIDR_PEP_6_Field := 16#0#; -- Write-only. Endpoint 7 Interrupt Disable - PEP_7 : DEVIDR_PEP_7_Field := 16#0#; + PEP_7 : UOTGHS_DEVIDR_PEP_7_Field := 16#0#; -- Write-only. Endpoint 8 Interrupt Disable - PEP_8 : DEVIDR_PEP_8_Field := 16#0#; + PEP_8 : UOTGHS_DEVIDR_PEP_8_Field := 16#0#; -- Write-only. Endpoint 9 Interrupt Disable - PEP_9 : DEVIDR_PEP_9_Field := 16#0#; + PEP_9 : UOTGHS_DEVIDR_PEP_9_Field := 16#0#; -- unspecified Reserved_22_24 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. DMA Channel 1 Interrupt Disable - DMA_1 : DEVIDR_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_DEVIDR_DMA_1_Field := 16#0#; -- Write-only. DMA Channel 2 Interrupt Disable - DMA_2 : DEVIDR_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_DEVIDR_DMA_2_Field := 16#0#; -- Write-only. DMA Channel 3 Interrupt Disable - DMA_3 : DEVIDR_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_DEVIDR_DMA_3_Field := 16#0#; -- Write-only. DMA Channel 4 Interrupt Disable - DMA_4 : DEVIDR_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_DEVIDR_DMA_4_Field := 16#0#; -- Write-only. DMA Channel 5 Interrupt Disable - DMA_5 : DEVIDR_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_DEVIDR_DMA_5_Field := 16#0#; -- Write-only. DMA Channel 6 Interrupt Disable - DMA_6 : DEVIDR_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_DEVIDR_DMA_6_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVIDR_Register use record + for UOTGHS_DEVIDR_Register use record SUSPEC at 0 range 0 .. 0; MSOFEC at 0 range 1 .. 1; SOFEC at 0 range 2 .. 2; @@ -548,92 +523,88 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- DEVIER_Register -- - --------------------- - - subtype DEVIER_SUSPES_Field is ATSAM3X8E.Bit; - subtype DEVIER_MSOFES_Field is ATSAM3X8E.Bit; - subtype DEVIER_SOFES_Field is ATSAM3X8E.Bit; - subtype DEVIER_EORSTES_Field is ATSAM3X8E.Bit; - subtype DEVIER_WAKEUPES_Field is ATSAM3X8E.Bit; - subtype DEVIER_EORSMES_Field is ATSAM3X8E.Bit; - subtype DEVIER_UPRSMES_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_0_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_1_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_2_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_3_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_4_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_5_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_6_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_7_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_8_Field is ATSAM3X8E.Bit; - subtype DEVIER_PEP_9_Field is ATSAM3X8E.Bit; - subtype DEVIER_DMA_1_Field is ATSAM3X8E.Bit; - subtype DEVIER_DMA_2_Field is ATSAM3X8E.Bit; - subtype DEVIER_DMA_3_Field is ATSAM3X8E.Bit; - subtype DEVIER_DMA_4_Field is ATSAM3X8E.Bit; - subtype DEVIER_DMA_5_Field is ATSAM3X8E.Bit; - subtype DEVIER_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_SUSPES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_MSOFES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_SOFES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_EORSTES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_WAKEUPES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_EORSMES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_UPRSMES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_0_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_7_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_8_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_PEP_9_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVIER_DMA_6_Field is ATSAM3X8E.Bit; -- Device Global Interrupt Enable Register - type DEVIER_Register is record + type UOTGHS_DEVIER_Register is record -- Write-only. Suspend Interrupt Enable - SUSPES : DEVIER_SUSPES_Field := 16#0#; + SUSPES : UOTGHS_DEVIER_SUSPES_Field := 16#0#; -- Write-only. Micro Start of Frame Interrupt Enable - MSOFES : DEVIER_MSOFES_Field := 16#0#; + MSOFES : UOTGHS_DEVIER_MSOFES_Field := 16#0#; -- Write-only. Start of Frame Interrupt Enable - SOFES : DEVIER_SOFES_Field := 16#0#; + SOFES : UOTGHS_DEVIER_SOFES_Field := 16#0#; -- Write-only. End of Reset Interrupt Enable - EORSTES : DEVIER_EORSTES_Field := 16#0#; + EORSTES : UOTGHS_DEVIER_EORSTES_Field := 16#0#; -- Write-only. Wake-Up Interrupt Enable - WAKEUPES : DEVIER_WAKEUPES_Field := 16#0#; + WAKEUPES : UOTGHS_DEVIER_WAKEUPES_Field := 16#0#; -- Write-only. End of Resume Interrupt Enable - EORSMES : DEVIER_EORSMES_Field := 16#0#; + EORSMES : UOTGHS_DEVIER_EORSMES_Field := 16#0#; -- Write-only. Upstream Resume Interrupt Enable - UPRSMES : DEVIER_UPRSMES_Field := 16#0#; + UPRSMES : UOTGHS_DEVIER_UPRSMES_Field := 16#0#; -- unspecified Reserved_7_11 : ATSAM3X8E.UInt5 := 16#0#; -- Write-only. Endpoint 0 Interrupt Enable - PEP_0 : DEVIER_PEP_0_Field := 16#0#; + PEP_0 : UOTGHS_DEVIER_PEP_0_Field := 16#0#; -- Write-only. Endpoint 1 Interrupt Enable - PEP_1 : DEVIER_PEP_1_Field := 16#0#; + PEP_1 : UOTGHS_DEVIER_PEP_1_Field := 16#0#; -- Write-only. Endpoint 2 Interrupt Enable - PEP_2 : DEVIER_PEP_2_Field := 16#0#; + PEP_2 : UOTGHS_DEVIER_PEP_2_Field := 16#0#; -- Write-only. Endpoint 3 Interrupt Enable - PEP_3 : DEVIER_PEP_3_Field := 16#0#; + PEP_3 : UOTGHS_DEVIER_PEP_3_Field := 16#0#; -- Write-only. Endpoint 4 Interrupt Enable - PEP_4 : DEVIER_PEP_4_Field := 16#0#; + PEP_4 : UOTGHS_DEVIER_PEP_4_Field := 16#0#; -- Write-only. Endpoint 5 Interrupt Enable - PEP_5 : DEVIER_PEP_5_Field := 16#0#; + PEP_5 : UOTGHS_DEVIER_PEP_5_Field := 16#0#; -- Write-only. Endpoint 6 Interrupt Enable - PEP_6 : DEVIER_PEP_6_Field := 16#0#; + PEP_6 : UOTGHS_DEVIER_PEP_6_Field := 16#0#; -- Write-only. Endpoint 7 Interrupt Enable - PEP_7 : DEVIER_PEP_7_Field := 16#0#; + PEP_7 : UOTGHS_DEVIER_PEP_7_Field := 16#0#; -- Write-only. Endpoint 8 Interrupt Enable - PEP_8 : DEVIER_PEP_8_Field := 16#0#; + PEP_8 : UOTGHS_DEVIER_PEP_8_Field := 16#0#; -- Write-only. Endpoint 9 Interrupt Enable - PEP_9 : DEVIER_PEP_9_Field := 16#0#; + PEP_9 : UOTGHS_DEVIER_PEP_9_Field := 16#0#; -- unspecified Reserved_22_24 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. DMA Channel 1 Interrupt Enable - DMA_1 : DEVIER_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_DEVIER_DMA_1_Field := 16#0#; -- Write-only. DMA Channel 2 Interrupt Enable - DMA_2 : DEVIER_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_DEVIER_DMA_2_Field := 16#0#; -- Write-only. DMA Channel 3 Interrupt Enable - DMA_3 : DEVIER_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_DEVIER_DMA_3_Field := 16#0#; -- Write-only. DMA Channel 4 Interrupt Enable - DMA_4 : DEVIER_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_DEVIER_DMA_4_Field := 16#0#; -- Write-only. DMA Channel 5 Interrupt Enable - DMA_5 : DEVIER_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_DEVIER_DMA_5_Field := 16#0#; -- Write-only. DMA Channel 6 Interrupt Enable - DMA_6 : DEVIER_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_DEVIER_DMA_6_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVIER_Register use record + for UOTGHS_DEVIER_Register use record SUSPES at 0 range 0 .. 0; MSOFES at 0 range 1 .. 1; SOFES at 0 range 2 .. 2; @@ -662,23 +633,16 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- DEVEPT_Register -- - --------------------- - - ----------------- - -- DEVEPT.EPEN -- - ----------------- - - -- DEVEPT_EPEN array element - subtype DEVEPT_EPEN_Element is ATSAM3X8E.Bit; + -- UOTGHS_DEVEPT_EPEN array element + subtype UOTGHS_DEVEPT_EPEN_Element is ATSAM3X8E.Bit; - -- DEVEPT_EPEN array - type DEVEPT_EPEN_Field_Array is array (0 .. 8) of DEVEPT_EPEN_Element + -- UOTGHS_DEVEPT_EPEN array + type UOTGHS_DEVEPT_EPEN_Field_Array is array (0 .. 8) + of UOTGHS_DEVEPT_EPEN_Element with Component_Size => 1, Size => 9; - -- Type definition for DEVEPT_EPEN - type DEVEPT_EPEN_Field + -- Type definition for UOTGHS_DEVEPT_EPEN + type UOTGHS_DEVEPT_EPEN_Field (As_Array : Boolean := False) is record case As_Array is @@ -687,29 +651,26 @@ package ATSAM3X8E.UOTGHS is Val : ATSAM3X8E.UInt9; when True => -- EPEN as an array - Arr : DEVEPT_EPEN_Field_Array; + Arr : UOTGHS_DEVEPT_EPEN_Field_Array; end case; end record with Unchecked_Union, Size => 9; - for DEVEPT_EPEN_Field use record + for UOTGHS_DEVEPT_EPEN_Field use record Val at 0 range 0 .. 8; Arr at 0 range 0 .. 8; end record; - ------------------ - -- DEVEPT.EPRST -- - ------------------ - - -- DEVEPT_EPRST array element - subtype DEVEPT_EPRST_Element is ATSAM3X8E.Bit; + -- UOTGHS_DEVEPT_EPRST array element + subtype UOTGHS_DEVEPT_EPRST_Element is ATSAM3X8E.Bit; - -- DEVEPT_EPRST array - type DEVEPT_EPRST_Field_Array is array (0 .. 8) of DEVEPT_EPRST_Element + -- UOTGHS_DEVEPT_EPRST array + type UOTGHS_DEVEPT_EPRST_Field_Array is array (0 .. 8) + of UOTGHS_DEVEPT_EPRST_Element with Component_Size => 1, Size => 9; - -- Type definition for DEVEPT_EPRST - type DEVEPT_EPRST_Field + -- Type definition for UOTGHS_DEVEPT_EPRST + type UOTGHS_DEVEPT_EPRST_Field (As_Array : Boolean := False) is record case As_Array is @@ -718,61 +679,58 @@ package ATSAM3X8E.UOTGHS is Val : ATSAM3X8E.UInt9; when True => -- EPRST as an array - Arr : DEVEPT_EPRST_Field_Array; + Arr : UOTGHS_DEVEPT_EPRST_Field_Array; end case; end record with Unchecked_Union, Size => 9; - for DEVEPT_EPRST_Field use record + for UOTGHS_DEVEPT_EPRST_Field use record Val at 0 range 0 .. 8; Arr at 0 range 0 .. 8; end record; -- Device Endpoint Register - type DEVEPT_Register is record + type UOTGHS_DEVEPT_Register is record -- Endpoint 0 Enable - EPEN : DEVEPT_EPEN_Field := (As_Array => False, Val => 16#0#); + EPEN : UOTGHS_DEVEPT_EPEN_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_9_15 : ATSAM3X8E.UInt7 := 16#0#; -- Endpoint 0 Reset - EPRST : DEVEPT_EPRST_Field := + EPRST : UOTGHS_DEVEPT_EPRST_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVEPT_Register use record + for UOTGHS_DEVEPT_Register use record EPEN at 0 range 0 .. 8; Reserved_9_15 at 0 range 9 .. 15; EPRST at 0 range 16 .. 24; Reserved_25_31 at 0 range 25 .. 31; end record; - ---------------------- - -- DEVFNUM_Register -- - ---------------------- - - subtype DEVFNUM_MFNUM_Field is ATSAM3X8E.UInt3; - subtype DEVFNUM_FNUM_Field is ATSAM3X8E.UInt11; - subtype DEVFNUM_FNCERR_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVFNUM_MFNUM_Field is ATSAM3X8E.UInt3; + subtype UOTGHS_DEVFNUM_FNUM_Field is ATSAM3X8E.UInt11; + subtype UOTGHS_DEVFNUM_FNCERR_Field is ATSAM3X8E.Bit; -- Device Frame Number Register - type DEVFNUM_Register is record + type UOTGHS_DEVFNUM_Register is record -- Read-only. Micro Frame Number - MFNUM : DEVFNUM_MFNUM_Field := 16#0#; + MFNUM : UOTGHS_DEVFNUM_MFNUM_Field; -- Read-only. Frame Number - FNUM : DEVFNUM_FNUM_Field := 16#0#; + FNUM : UOTGHS_DEVFNUM_FNUM_Field; -- unspecified Reserved_14_14 : ATSAM3X8E.Bit; -- Read-only. Frame Number CRC Error - FNCERR : DEVFNUM_FNCERR_Field := 16#0#; + FNCERR : UOTGHS_DEVFNUM_FNCERR_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVFNUM_Register use record + for UOTGHS_DEVFNUM_Register use record MFNUM at 0 range 0 .. 2; FNUM at 0 range 3 .. 13; Reserved_14_14 at 0 range 14 .. 14; @@ -780,75 +738,67 @@ package ATSAM3X8E.UOTGHS is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------------ - -- DEVEPTCFG_Register -- - ------------------------ - - subtype DEVEPTCFG_ALLOC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTCFG_ALLOC_Field is ATSAM3X8E.Bit; -- Endpoint Banks - type EPBK_Field is - ( - -- Single-bank endpoint - EPBK_Field_1_Bank, + type DEVEPTCFG_EPBK_Field is + (-- Single-bank endpoint + Val_1_Bank, -- Double-bank endpoint - EPBK_Field_2_Bank, + Val_2_Bank, -- Triple-bank endpoint - EPBK_Field_3_Bank) + Val_3_Bank) with Size => 2; - for EPBK_Field use - (EPBK_Field_1_Bank => 0, - EPBK_Field_2_Bank => 1, - EPBK_Field_3_Bank => 2); + for DEVEPTCFG_EPBK_Field use + (Val_1_Bank => 0, + Val_2_Bank => 1, + Val_3_Bank => 2); -- Endpoint Size - type EPSIZE_Field is - ( - -- 8 bytes - EPSIZE_Field_8_Byte, + type DEVEPTCFG_EPSIZE_Field is + (-- 8 bytes + Val_8_Byte, -- 16 bytes - EPSIZE_Field_16_Byte, + Val_16_Byte, -- 32 bytes - EPSIZE_Field_32_Byte, + Val_32_Byte, -- 64 bytes - EPSIZE_Field_64_Byte, + Val_64_Byte, -- 128 bytes - EPSIZE_Field_128_Byte, + Val_128_Byte, -- 256 bytes - EPSIZE_Field_256_Byte, + Val_256_Byte, -- 512 bytes - EPSIZE_Field_512_Byte, + Val_512_Byte, -- 1024 bytes - EPSIZE_Field_1024_Byte) + Val_1024_Byte) with Size => 3; - for EPSIZE_Field use - (EPSIZE_Field_8_Byte => 0, - EPSIZE_Field_16_Byte => 1, - EPSIZE_Field_32_Byte => 2, - EPSIZE_Field_64_Byte => 3, - EPSIZE_Field_128_Byte => 4, - EPSIZE_Field_256_Byte => 5, - EPSIZE_Field_512_Byte => 6, - EPSIZE_Field_1024_Byte => 7); + for DEVEPTCFG_EPSIZE_Field use + (Val_8_Byte => 0, + Val_16_Byte => 1, + Val_32_Byte => 2, + Val_64_Byte => 3, + Val_128_Byte => 4, + Val_256_Byte => 5, + Val_512_Byte => 6, + Val_1024_Byte => 7); -- Endpoint Direction - type EPDIR_Field is - ( - -- The endpoint direction is OUT. + type DEVEPTCFG_EPDIR_Field is + (-- The endpoint direction is OUT. Out_k, -- The endpoint direction is IN (nor for control endpoints). In_k) with Size => 1; - for EPDIR_Field use + for DEVEPTCFG_EPDIR_Field use (Out_k => 0, In_k => 1); - subtype DEVEPTCFG_AUTOSW_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTCFG_AUTOSW_Field is ATSAM3X8E.Bit; -- Endpoint Type - type EPTYPE_Field is - ( - -- Control + type DEVEPTCFG_EPTYPE_Field is + (-- Control Ctrl, -- Isochronous Iso, @@ -857,61 +807,61 @@ package ATSAM3X8E.UOTGHS is -- Interrupt Intrpt) with Size => 2; - for EPTYPE_Field use + for DEVEPTCFG_EPTYPE_Field use (Ctrl => 0, Iso => 1, Blk => 2, Intrpt => 3); -- Number of transaction per microframe for isochronous endpoint - type NBTRANS_Field is - ( - -- reserved to endpoint that does not have the high-bandwidth - -- isochronous capability. - NBTRANS_Field_0_Trans, + type DEVEPTCFG_NBTRANS_Field is + (-- reserved to endpoint that does not have the high-bandwidth isochronous +-- capability. + Val_0_Trans, -- default value: one transaction per micro-frame. - NBTRANS_Field_1_Trans, + Val_1_Trans, -- 2 transactions per micro-frame. This endpoint should be configured as - -- double-bank. - NBTRANS_Field_2_Trans, +-- double-bank. + Val_2_Trans, -- 3 transactions per micro-frame. This endpoint should be configured as - -- triple-bank. - NBTRANS_Field_3_Trans) +-- triple-bank. + Val_3_Trans) with Size => 2; - for NBTRANS_Field use - (NBTRANS_Field_0_Trans => 0, - NBTRANS_Field_1_Trans => 1, - NBTRANS_Field_2_Trans => 2, - NBTRANS_Field_3_Trans => 3); + for DEVEPTCFG_NBTRANS_Field use + (Val_0_Trans => 0, + Val_1_Trans => 1, + Val_2_Trans => 2, + Val_3_Trans => 3); -- Device Endpoint Configuration Register (n = 0) - type DEVEPTCFG_Register is record + type UOTGHS_DEVEPTCFG_Register is record -- unspecified Reserved_0_0 : ATSAM3X8E.Bit := 16#0#; -- Endpoint Memory Allocate - ALLOC : DEVEPTCFG_ALLOC_Field := 16#0#; + ALLOC : UOTGHS_DEVEPTCFG_ALLOC_Field := 16#0#; -- Endpoint Banks - EPBK : EPBK_Field := EPBK_Field_1_Bank; + EPBK : DEVEPTCFG_EPBK_Field := ATSAM3X8E.UOTGHS.Val_1_Bank; -- Endpoint Size - EPSIZE : EPSIZE_Field := EPSIZE_Field_8_Byte; + EPSIZE : DEVEPTCFG_EPSIZE_Field := ATSAM3X8E.UOTGHS.Val_8_Byte; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Endpoint Direction - EPDIR : EPDIR_Field := Out_k; + EPDIR : DEVEPTCFG_EPDIR_Field := ATSAM3X8E.UOTGHS.Out_k; -- Automatic Switch - AUTOSW : DEVEPTCFG_AUTOSW_Field := 16#0#; + AUTOSW : UOTGHS_DEVEPTCFG_AUTOSW_Field := 16#0#; -- unspecified Reserved_10_10 : ATSAM3X8E.Bit := 16#0#; -- Endpoint Type - EPTYPE : EPTYPE_Field := Ctrl; + EPTYPE : DEVEPTCFG_EPTYPE_Field := ATSAM3X8E.UOTGHS.Ctrl; -- Number of transaction per microframe for isochronous endpoint - NBTRANS : NBTRANS_Field := NBTRANS_Field_0_Trans; + NBTRANS : DEVEPTCFG_NBTRANS_Field := + ATSAM3X8E.UOTGHS.Val_0_Trans; -- unspecified Reserved_15_31 : ATSAM3X8E.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVEPTCFG_Register use record + for UOTGHS_DEVEPTCFG_Register use record Reserved_0_0 at 0 range 0 .. 0; ALLOC at 0 range 1 .. 1; EPBK at 0 range 2 .. 3; @@ -925,26 +875,18 @@ package ATSAM3X8E.UOTGHS is Reserved_15_31 at 0 range 15 .. 31; end record; - -- Device Endpoint Configuration Register (n = 0) - type DEVEPTCFG_Registers is array (0 .. 9) of DEVEPTCFG_Register; - - ------------------------ - -- DEVEPTISR_Register -- - ------------------------ - - subtype DEVEPTISR_TXINI_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_RXOUTI_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_RXSTPI_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_NAKOUTI_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_NAKINI_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_OVERFI_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_STALLEDI_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_SHORTPACKET_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_TXINI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_RXOUTI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_RXSTPI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_NAKOUTI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_NAKINI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_OVERFI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_STALLEDI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_SHORTPACKET_Field is ATSAM3X8E.Bit; -- Data Toggle Sequence - type DTSEQ_Field is - ( - -- Data0 toggle sequence + type DEVEPTISR_DTSEQ_Field is + (-- Data0 toggle sequence Data0, -- Data1 toggle sequence Data1, @@ -953,92 +895,90 @@ package ATSAM3X8E.UOTGHS is -- Reserved for high-bandwidth isochronous endpoint Mdata) with Size => 2; - for DTSEQ_Field use + for DEVEPTISR_DTSEQ_Field use (Data0 => 0, Data1 => 1, Data2 => 2, Mdata => 3); -- Number of Busy Banks - type NBUSYBK_Field is - ( - -- 0 busy bank (all banks free) - NBUSYBK_Field_0_Busy, + type DEVEPTISR_NBUSYBK_Field is + (-- 0 busy bank (all banks free) + Val_0_Busy, -- 1 busy bank - NBUSYBK_Field_1_Busy, + Val_1_Busy, -- 2 busy banks - NBUSYBK_Field_2_Busy, + Val_2_Busy, -- 3 busy banks - NBUSYBK_Field_3_Busy) + Val_3_Busy) with Size => 2; - for NBUSYBK_Field use - (NBUSYBK_Field_0_Busy => 0, - NBUSYBK_Field_1_Busy => 1, - NBUSYBK_Field_2_Busy => 2, - NBUSYBK_Field_3_Busy => 3); + for DEVEPTISR_NBUSYBK_Field use + (Val_0_Busy => 0, + Val_1_Busy => 1, + Val_2_Busy => 2, + Val_3_Busy => 3); -- Current Bank - type CURRBK_Field is - ( - -- Current bank is bank0 + type DEVEPTISR_CURRBK_Field is + (-- Current bank is bank0 Bank0, -- Current bank is bank1 Bank1, -- Current bank is bank2 Bank2) with Size => 2; - for CURRBK_Field use + for DEVEPTISR_CURRBK_Field use (Bank0 => 0, Bank1 => 1, Bank2 => 2); - subtype DEVEPTISR_RWALL_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_CTRLDIR_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_CFGOK_Field is ATSAM3X8E.Bit; - subtype DEVEPTISR_BYCT_Field is ATSAM3X8E.UInt11; + subtype UOTGHS_DEVEPTISR_RWALL_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_CTRLDIR_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_CFGOK_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTISR_BYCT_Field is ATSAM3X8E.UInt11; -- Device Endpoint Status Register (n = 0) - type DEVEPTISR_Register is record + type UOTGHS_DEVEPTISR_Register is record -- Read-only. Transmitted IN Data Interrupt - TXINI : DEVEPTISR_TXINI_Field := 16#0#; + TXINI : UOTGHS_DEVEPTISR_TXINI_Field; -- Read-only. Received OUT Data Interrupt - RXOUTI : DEVEPTISR_RXOUTI_Field := 16#0#; + RXOUTI : UOTGHS_DEVEPTISR_RXOUTI_Field; -- Read-only. Received SETUP Interrupt - RXSTPI : DEVEPTISR_RXSTPI_Field := 16#0#; + RXSTPI : UOTGHS_DEVEPTISR_RXSTPI_Field; -- Read-only. NAKed OUT Interrupt - NAKOUTI : DEVEPTISR_NAKOUTI_Field := 16#0#; + NAKOUTI : UOTGHS_DEVEPTISR_NAKOUTI_Field; -- Read-only. NAKed IN Interrupt - NAKINI : DEVEPTISR_NAKINI_Field := 16#0#; + NAKINI : UOTGHS_DEVEPTISR_NAKINI_Field; -- Read-only. Overflow Interrupt - OVERFI : DEVEPTISR_OVERFI_Field := 16#0#; + OVERFI : UOTGHS_DEVEPTISR_OVERFI_Field; -- Read-only. STALLed Interrupt - STALLEDI : DEVEPTISR_STALLEDI_Field := 16#0#; + STALLEDI : UOTGHS_DEVEPTISR_STALLEDI_Field; -- Read-only. Short Packet Interrupt - SHORTPACKET : DEVEPTISR_SHORTPACKET_Field := 16#0#; + SHORTPACKET : UOTGHS_DEVEPTISR_SHORTPACKET_Field; -- Read-only. Data Toggle Sequence - DTSEQ : DTSEQ_Field := Data0; + DTSEQ : DEVEPTISR_DTSEQ_Field; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2; -- Read-only. Number of Busy Banks - NBUSYBK : NBUSYBK_Field := NBUSYBK_Field_0_Busy; + NBUSYBK : DEVEPTISR_NBUSYBK_Field; -- Read-only. Current Bank - CURRBK : CURRBK_Field := Bank0; + CURRBK : DEVEPTISR_CURRBK_Field; -- Read-only. Read-write Allowed - RWALL : DEVEPTISR_RWALL_Field := 16#0#; + RWALL : UOTGHS_DEVEPTISR_RWALL_Field; -- Read-only. Control Direction - CTRLDIR : DEVEPTISR_CTRLDIR_Field := 16#0#; + CTRLDIR : UOTGHS_DEVEPTISR_CTRLDIR_Field; -- Read-only. Configuration OK Status - CFGOK : DEVEPTISR_CFGOK_Field := 16#0#; + CFGOK : UOTGHS_DEVEPTISR_CFGOK_Field; -- unspecified Reserved_19_19 : ATSAM3X8E.Bit; -- Read-only. Byte Count - BYCT : DEVEPTISR_BYCT_Field := 16#0#; + BYCT : UOTGHS_DEVEPTISR_BYCT_Field; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVEPTISR_Register use record + for UOTGHS_DEVEPTISR_Register use record TXINI at 0 range 0 .. 0; RXOUTI at 0 range 1 .. 1; RXSTPI at 0 range 2 .. 2; @@ -1059,46 +999,39 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - -- Device Endpoint Status Register (n = 0) - type DEVEPTISR_Registers is array (0 .. 9) of DEVEPTISR_Register; - - ------------------------ - -- DEVEPTICR_Register -- - ------------------------ - - subtype DEVEPTICR_TXINIC_Field is ATSAM3X8E.Bit; - subtype DEVEPTICR_RXOUTIC_Field is ATSAM3X8E.Bit; - subtype DEVEPTICR_RXSTPIC_Field is ATSAM3X8E.Bit; - subtype DEVEPTICR_NAKOUTIC_Field is ATSAM3X8E.Bit; - subtype DEVEPTICR_NAKINIC_Field is ATSAM3X8E.Bit; - subtype DEVEPTICR_OVERFIC_Field is ATSAM3X8E.Bit; - subtype DEVEPTICR_STALLEDIC_Field is ATSAM3X8E.Bit; - subtype DEVEPTICR_SHORTPACKETC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTICR_TXINIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTICR_RXOUTIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTICR_RXSTPIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTICR_NAKOUTIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTICR_NAKINIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTICR_OVERFIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTICR_STALLEDIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTICR_SHORTPACKETC_Field is ATSAM3X8E.Bit; -- Device Endpoint Clear Register (n = 0) - type DEVEPTICR_Register is record + type UOTGHS_DEVEPTICR_Register is record -- Write-only. Transmitted IN Data Interrupt Clear - TXINIC : DEVEPTICR_TXINIC_Field := 16#0#; + TXINIC : UOTGHS_DEVEPTICR_TXINIC_Field := 16#0#; -- Write-only. Received OUT Data Interrupt Clear - RXOUTIC : DEVEPTICR_RXOUTIC_Field := 16#0#; + RXOUTIC : UOTGHS_DEVEPTICR_RXOUTIC_Field := 16#0#; -- Write-only. Received SETUP Interrupt Clear - RXSTPIC : DEVEPTICR_RXSTPIC_Field := 16#0#; + RXSTPIC : UOTGHS_DEVEPTICR_RXSTPIC_Field := 16#0#; -- Write-only. NAKed OUT Interrupt Clear - NAKOUTIC : DEVEPTICR_NAKOUTIC_Field := 16#0#; + NAKOUTIC : UOTGHS_DEVEPTICR_NAKOUTIC_Field := 16#0#; -- Write-only. NAKed IN Interrupt Clear - NAKINIC : DEVEPTICR_NAKINIC_Field := 16#0#; + NAKINIC : UOTGHS_DEVEPTICR_NAKINIC_Field := 16#0#; -- Write-only. Overflow Interrupt Clear - OVERFIC : DEVEPTICR_OVERFIC_Field := 16#0#; + OVERFIC : UOTGHS_DEVEPTICR_OVERFIC_Field := 16#0#; -- Write-only. STALLed Interrupt Clear - STALLEDIC : DEVEPTICR_STALLEDIC_Field := 16#0#; + STALLEDIC : UOTGHS_DEVEPTICR_STALLEDIC_Field := 16#0#; -- Write-only. Short Packet Interrupt Clear - SHORTPACKETC : DEVEPTICR_SHORTPACKETC_Field := 16#0#; + SHORTPACKETC : UOTGHS_DEVEPTICR_SHORTPACKETC_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVEPTICR_Register use record + for UOTGHS_DEVEPTICR_Register use record TXINIC at 0 range 0 .. 0; RXOUTIC at 0 range 1 .. 1; RXSTPIC at 0 range 2 .. 2; @@ -1110,51 +1043,44 @@ package ATSAM3X8E.UOTGHS is Reserved_8_31 at 0 range 8 .. 31; end record; - -- Device Endpoint Clear Register (n = 0) - type DEVEPTICR_Registers is array (0 .. 9) of DEVEPTICR_Register; - - ------------------------ - -- DEVEPTIFR_Register -- - ------------------------ - - subtype DEVEPTIFR_TXINIS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIFR_RXOUTIS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIFR_RXSTPIS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIFR_NAKOUTIS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIFR_NAKINIS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIFR_OVERFIS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIFR_STALLEDIS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIFR_SHORTPACKETS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIFR_NBUSYBKS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_TXINIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_RXOUTIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_RXSTPIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_NAKOUTIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_NAKINIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_OVERFIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_STALLEDIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_SHORTPACKETS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIFR_NBUSYBKS_Field is ATSAM3X8E.Bit; -- Device Endpoint Set Register (n = 0) - type DEVEPTIFR_Register is record + type UOTGHS_DEVEPTIFR_Register is record -- Write-only. Transmitted IN Data Interrupt Set - TXINIS : DEVEPTIFR_TXINIS_Field := 16#0#; + TXINIS : UOTGHS_DEVEPTIFR_TXINIS_Field := 16#0#; -- Write-only. Received OUT Data Interrupt Set - RXOUTIS : DEVEPTIFR_RXOUTIS_Field := 16#0#; + RXOUTIS : UOTGHS_DEVEPTIFR_RXOUTIS_Field := 16#0#; -- Write-only. Received SETUP Interrupt Set - RXSTPIS : DEVEPTIFR_RXSTPIS_Field := 16#0#; + RXSTPIS : UOTGHS_DEVEPTIFR_RXSTPIS_Field := 16#0#; -- Write-only. NAKed OUT Interrupt Set - NAKOUTIS : DEVEPTIFR_NAKOUTIS_Field := 16#0#; + NAKOUTIS : UOTGHS_DEVEPTIFR_NAKOUTIS_Field := 16#0#; -- Write-only. NAKed IN Interrupt Set - NAKINIS : DEVEPTIFR_NAKINIS_Field := 16#0#; + NAKINIS : UOTGHS_DEVEPTIFR_NAKINIS_Field := 16#0#; -- Write-only. Overflow Interrupt Set - OVERFIS : DEVEPTIFR_OVERFIS_Field := 16#0#; + OVERFIS : UOTGHS_DEVEPTIFR_OVERFIS_Field := 16#0#; -- Write-only. STALLed Interrupt Set - STALLEDIS : DEVEPTIFR_STALLEDIS_Field := 16#0#; + STALLEDIS : UOTGHS_DEVEPTIFR_STALLEDIS_Field := 16#0#; -- Write-only. Short Packet Interrupt Set - SHORTPACKETS : DEVEPTIFR_SHORTPACKETS_Field := 16#0#; + SHORTPACKETS : UOTGHS_DEVEPTIFR_SHORTPACKETS_Field := 16#0#; -- unspecified Reserved_8_11 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Number of Busy Banks Interrupt Set - NBUSYBKS : DEVEPTIFR_NBUSYBKS_Field := 16#0#; + NBUSYBKS : UOTGHS_DEVEPTIFR_NBUSYBKS_Field := 16#0#; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVEPTIFR_Register use record + for UOTGHS_DEVEPTIFR_Register use record TXINIS at 0 range 0 .. 0; RXOUTIS at 0 range 1 .. 1; RXSTPIS at 0 range 2 .. 2; @@ -1168,71 +1094,64 @@ package ATSAM3X8E.UOTGHS is Reserved_13_31 at 0 range 13 .. 31; end record; - -- Device Endpoint Set Register (n = 0) - type DEVEPTIFR_Registers is array (0 .. 9) of DEVEPTIFR_Register; - - ------------------------ - -- DEVEPTIMR_Register -- - ------------------------ - - subtype DEVEPTIMR_TXINE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_RXOUTE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_RXSTPE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_NAKOUTE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_NAKINE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_OVERFE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_STALLEDE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_SHORTPACKETE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_NBUSYBKE_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_KILLBK_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_FIFOCON_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_EPDISHDMA_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_NYETDIS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_RSTDT_Field is ATSAM3X8E.Bit; - subtype DEVEPTIMR_STALLRQ_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_TXINE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_RXOUTE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_RXSTPE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_NAKOUTE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_NAKINE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_OVERFE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_STALLEDE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_SHORTPACKETE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_NBUSYBKE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_KILLBK_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_FIFOCON_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_EPDISHDMA_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_NYETDIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_RSTDT_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIMR_STALLRQ_Field is ATSAM3X8E.Bit; -- Device Endpoint Mask Register (n = 0) - type DEVEPTIMR_Register is record + type UOTGHS_DEVEPTIMR_Register is record -- Read-only. Transmitted IN Data Interrupt - TXINE : DEVEPTIMR_TXINE_Field := 16#0#; + TXINE : UOTGHS_DEVEPTIMR_TXINE_Field; -- Read-only. Received OUT Data Interrupt - RXOUTE : DEVEPTIMR_RXOUTE_Field := 16#0#; + RXOUTE : UOTGHS_DEVEPTIMR_RXOUTE_Field; -- Read-only. Received SETUP Interrupt - RXSTPE : DEVEPTIMR_RXSTPE_Field := 16#0#; + RXSTPE : UOTGHS_DEVEPTIMR_RXSTPE_Field; -- Read-only. NAKed OUT Interrupt - NAKOUTE : DEVEPTIMR_NAKOUTE_Field := 16#0#; + NAKOUTE : UOTGHS_DEVEPTIMR_NAKOUTE_Field; -- Read-only. NAKed IN Interrupt - NAKINE : DEVEPTIMR_NAKINE_Field := 16#0#; + NAKINE : UOTGHS_DEVEPTIMR_NAKINE_Field; -- Read-only. Overflow Interrupt - OVERFE : DEVEPTIMR_OVERFE_Field := 16#0#; + OVERFE : UOTGHS_DEVEPTIMR_OVERFE_Field; -- Read-only. STALLed Interrupt - STALLEDE : DEVEPTIMR_STALLEDE_Field := 16#0#; + STALLEDE : UOTGHS_DEVEPTIMR_STALLEDE_Field; -- Read-only. Short Packet Interrupt - SHORTPACKETE : DEVEPTIMR_SHORTPACKETE_Field := 16#0#; + SHORTPACKETE : UOTGHS_DEVEPTIMR_SHORTPACKETE_Field; -- unspecified Reserved_8_11 : ATSAM3X8E.UInt4; -- Read-only. Number of Busy Banks Interrupt - NBUSYBKE : DEVEPTIMR_NBUSYBKE_Field := 16#0#; + NBUSYBKE : UOTGHS_DEVEPTIMR_NBUSYBKE_Field; -- Read-only. Kill IN Bank - KILLBK : DEVEPTIMR_KILLBK_Field := 16#0#; + KILLBK : UOTGHS_DEVEPTIMR_KILLBK_Field; -- Read-only. FIFO Control - FIFOCON : DEVEPTIMR_FIFOCON_Field := 16#0#; + FIFOCON : UOTGHS_DEVEPTIMR_FIFOCON_Field; -- unspecified Reserved_15_15 : ATSAM3X8E.Bit; -- Read-only. Endpoint Interrupts Disable HDMA Request - EPDISHDMA : DEVEPTIMR_EPDISHDMA_Field := 16#0#; + EPDISHDMA : UOTGHS_DEVEPTIMR_EPDISHDMA_Field; -- Read-only. NYET Token Disable - NYETDIS : DEVEPTIMR_NYETDIS_Field := 16#0#; + NYETDIS : UOTGHS_DEVEPTIMR_NYETDIS_Field; -- Read-only. Reset Data Toggle - RSTDT : DEVEPTIMR_RSTDT_Field := 16#0#; + RSTDT : UOTGHS_DEVEPTIMR_RSTDT_Field; -- Read-only. STALL Request - STALLRQ : DEVEPTIMR_STALLRQ_Field := 16#0#; + STALLRQ : UOTGHS_DEVEPTIMR_STALLRQ_Field; -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVEPTIMR_Register use record + for UOTGHS_DEVEPTIMR_Register use record TXINE at 0 range 0 .. 0; RXOUTE at 0 range 1 .. 1; RXSTPE at 0 range 2 .. 2; @@ -1253,71 +1172,64 @@ package ATSAM3X8E.UOTGHS is Reserved_20_31 at 0 range 20 .. 31; end record; - -- Device Endpoint Mask Register (n = 0) - type DEVEPTIMR_Registers is array (0 .. 9) of DEVEPTIMR_Register; - - ------------------------ - -- DEVEPTIER_Register -- - ------------------------ - - subtype DEVEPTIER_TXINES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_RXOUTES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_RXSTPES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_NAKOUTES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_NAKINES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_OVERFES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_STALLEDES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_SHORTPACKETES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_NBUSYBKES_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_KILLBKS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_FIFOCONS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_EPDISHDMAS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_NYETDISS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_RSTDTS_Field is ATSAM3X8E.Bit; - subtype DEVEPTIER_STALLRQS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_TXINES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_RXOUTES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_RXSTPES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_NAKOUTES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_NAKINES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_OVERFES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_STALLEDES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_SHORTPACKETES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_NBUSYBKES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_KILLBKS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_FIFOCONS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_EPDISHDMAS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_NYETDISS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_RSTDTS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIER_STALLRQS_Field is ATSAM3X8E.Bit; -- Device Endpoint Enable Register (n = 0) - type DEVEPTIER_Register is record + type UOTGHS_DEVEPTIER_Register is record -- Write-only. Transmitted IN Data Interrupt Enable - TXINES : DEVEPTIER_TXINES_Field := 16#0#; + TXINES : UOTGHS_DEVEPTIER_TXINES_Field := 16#0#; -- Write-only. Received OUT Data Interrupt Enable - RXOUTES : DEVEPTIER_RXOUTES_Field := 16#0#; + RXOUTES : UOTGHS_DEVEPTIER_RXOUTES_Field := 16#0#; -- Write-only. Received SETUP Interrupt Enable - RXSTPES : DEVEPTIER_RXSTPES_Field := 16#0#; + RXSTPES : UOTGHS_DEVEPTIER_RXSTPES_Field := 16#0#; -- Write-only. NAKed OUT Interrupt Enable - NAKOUTES : DEVEPTIER_NAKOUTES_Field := 16#0#; + NAKOUTES : UOTGHS_DEVEPTIER_NAKOUTES_Field := 16#0#; -- Write-only. NAKed IN Interrupt Enable - NAKINES : DEVEPTIER_NAKINES_Field := 16#0#; + NAKINES : UOTGHS_DEVEPTIER_NAKINES_Field := 16#0#; -- Write-only. Overflow Interrupt Enable - OVERFES : DEVEPTIER_OVERFES_Field := 16#0#; + OVERFES : UOTGHS_DEVEPTIER_OVERFES_Field := 16#0#; -- Write-only. STALLed Interrupt Enable - STALLEDES : DEVEPTIER_STALLEDES_Field := 16#0#; + STALLEDES : UOTGHS_DEVEPTIER_STALLEDES_Field := 16#0#; -- Write-only. Short Packet Interrupt Enable - SHORTPACKETES : DEVEPTIER_SHORTPACKETES_Field := 16#0#; + SHORTPACKETES : UOTGHS_DEVEPTIER_SHORTPACKETES_Field := 16#0#; -- unspecified Reserved_8_11 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Number of Busy Banks Interrupt Enable - NBUSYBKES : DEVEPTIER_NBUSYBKES_Field := 16#0#; + NBUSYBKES : UOTGHS_DEVEPTIER_NBUSYBKES_Field := 16#0#; -- Write-only. Kill IN Bank - KILLBKS : DEVEPTIER_KILLBKS_Field := 16#0#; + KILLBKS : UOTGHS_DEVEPTIER_KILLBKS_Field := 16#0#; -- Write-only. FIFO Control - FIFOCONS : DEVEPTIER_FIFOCONS_Field := 16#0#; + FIFOCONS : UOTGHS_DEVEPTIER_FIFOCONS_Field := 16#0#; -- unspecified Reserved_15_15 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Endpoint Interrupts Disable HDMA Request Enable - EPDISHDMAS : DEVEPTIER_EPDISHDMAS_Field := 16#0#; + EPDISHDMAS : UOTGHS_DEVEPTIER_EPDISHDMAS_Field := 16#0#; -- Write-only. NYET Token Disable Enable - NYETDISS : DEVEPTIER_NYETDISS_Field := 16#0#; + NYETDISS : UOTGHS_DEVEPTIER_NYETDISS_Field := 16#0#; -- Write-only. Reset Data Toggle Enable - RSTDTS : DEVEPTIER_RSTDTS_Field := 16#0#; + RSTDTS : UOTGHS_DEVEPTIER_RSTDTS_Field := 16#0#; -- Write-only. STALL Request Enable - STALLRQS : DEVEPTIER_STALLRQS_Field := 16#0#; + STALLRQS : UOTGHS_DEVEPTIER_STALLRQS_Field := 16#0#; -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVEPTIER_Register use record + for UOTGHS_DEVEPTIER_Register use record TXINES at 0 range 0 .. 0; RXOUTES at 0 range 1 .. 1; RXSTPES at 0 range 2 .. 2; @@ -1338,69 +1250,62 @@ package ATSAM3X8E.UOTGHS is Reserved_20_31 at 0 range 20 .. 31; end record; - -- Device Endpoint Enable Register (n = 0) - type DEVEPTIER_Registers is array (0 .. 9) of DEVEPTIER_Register; - - ------------------------ - -- DEVEPTIDR_Register -- - ------------------------ - - subtype DEVEPTIDR_TXINEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_RXOUTEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_RXSTPEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_NAKOUTEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_NAKINEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_OVERFEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_STALLEDEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_SHORTPACKETEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_NBUSYBKEC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_FIFOCONC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_EPDISHDMAC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_NYETDISC_Field is ATSAM3X8E.Bit; - subtype DEVEPTIDR_STALLRQC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_TXINEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_RXOUTEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_RXSTPEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_NAKOUTEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_NAKINEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_OVERFEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_STALLEDEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_SHORTPACKETEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_NBUSYBKEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_FIFOCONC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_EPDISHDMAC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_NYETDISC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_DEVEPTIDR_STALLRQC_Field is ATSAM3X8E.Bit; -- Device Endpoint Disable Register (n = 0) - type DEVEPTIDR_Register is record + type UOTGHS_DEVEPTIDR_Register is record -- Write-only. Transmitted IN Interrupt Clear - TXINEC : DEVEPTIDR_TXINEC_Field := 16#0#; + TXINEC : UOTGHS_DEVEPTIDR_TXINEC_Field := 16#0#; -- Write-only. Received OUT Data Interrupt Clear - RXOUTEC : DEVEPTIDR_RXOUTEC_Field := 16#0#; + RXOUTEC : UOTGHS_DEVEPTIDR_RXOUTEC_Field := 16#0#; -- Write-only. Received SETUP Interrupt Clear - RXSTPEC : DEVEPTIDR_RXSTPEC_Field := 16#0#; + RXSTPEC : UOTGHS_DEVEPTIDR_RXSTPEC_Field := 16#0#; -- Write-only. NAKed OUT Interrupt Clear - NAKOUTEC : DEVEPTIDR_NAKOUTEC_Field := 16#0#; + NAKOUTEC : UOTGHS_DEVEPTIDR_NAKOUTEC_Field := 16#0#; -- Write-only. NAKed IN Interrupt Clear - NAKINEC : DEVEPTIDR_NAKINEC_Field := 16#0#; + NAKINEC : UOTGHS_DEVEPTIDR_NAKINEC_Field := 16#0#; -- Write-only. Overflow Interrupt Clear - OVERFEC : DEVEPTIDR_OVERFEC_Field := 16#0#; + OVERFEC : UOTGHS_DEVEPTIDR_OVERFEC_Field := 16#0#; -- Write-only. STALLed Interrupt Clear - STALLEDEC : DEVEPTIDR_STALLEDEC_Field := 16#0#; + STALLEDEC : UOTGHS_DEVEPTIDR_STALLEDEC_Field := 16#0#; -- Write-only. Shortpacket Interrupt Clear - SHORTPACKETEC : DEVEPTIDR_SHORTPACKETEC_Field := 16#0#; + SHORTPACKETEC : UOTGHS_DEVEPTIDR_SHORTPACKETEC_Field := 16#0#; -- unspecified Reserved_8_11 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Number of Busy Banks Interrupt Clear - NBUSYBKEC : DEVEPTIDR_NBUSYBKEC_Field := 16#0#; + NBUSYBKEC : UOTGHS_DEVEPTIDR_NBUSYBKEC_Field := 16#0#; -- unspecified Reserved_13_13 : ATSAM3X8E.Bit := 16#0#; -- Write-only. FIFO Control Clear - FIFOCONC : DEVEPTIDR_FIFOCONC_Field := 16#0#; + FIFOCONC : UOTGHS_DEVEPTIDR_FIFOCONC_Field := 16#0#; -- unspecified Reserved_15_15 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Endpoint Interrupts Disable HDMA Request Clear - EPDISHDMAC : DEVEPTIDR_EPDISHDMAC_Field := 16#0#; + EPDISHDMAC : UOTGHS_DEVEPTIDR_EPDISHDMAC_Field := 16#0#; -- Write-only. NYET Token Disable Clear - NYETDISC : DEVEPTIDR_NYETDISC_Field := 16#0#; + NYETDISC : UOTGHS_DEVEPTIDR_NYETDISC_Field := 16#0#; -- unspecified Reserved_18_18 : ATSAM3X8E.Bit := 16#0#; -- Write-only. STALL Request Clear - STALLRQC : DEVEPTIDR_STALLRQC_Field := 16#0#; + STALLRQC : UOTGHS_DEVEPTIDR_STALLRQC_Field := 16#0#; -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DEVEPTIDR_Register use record + for UOTGHS_DEVEPTIDR_Register use record TXINEC at 0 range 0 .. 0; RXOUTEC at 0 range 1 .. 1; RXSTPEC at 0 range 2 .. 2; @@ -1421,47 +1326,40 @@ package ATSAM3X8E.UOTGHS is Reserved_20_31 at 0 range 20 .. 31; end record; - -- Device Endpoint Disable Register (n = 0) - type DEVEPTIDR_Registers is array (0 .. 9) of DEVEPTIDR_Register; - - ---------------------------- - -- DEVDMACONTROL_Register -- - ---------------------------- - - subtype DEVDMACONTROL1_CHANN_ENB_Field is ATSAM3X8E.Bit; - subtype DEVDMACONTROL1_LDNXT_DSC_Field is ATSAM3X8E.Bit; - subtype DEVDMACONTROL1_END_TR_EN_Field is ATSAM3X8E.Bit; - subtype DEVDMACONTROL1_END_B_EN_Field is ATSAM3X8E.Bit; - subtype DEVDMACONTROL1_END_TR_IT_Field is ATSAM3X8E.Bit; - subtype DEVDMACONTROL1_END_BUFFIT_Field is ATSAM3X8E.Bit; - subtype DEVDMACONTROL1_DESC_LD_IT_Field is ATSAM3X8E.Bit; - subtype DEVDMACONTROL1_BURST_LCK_Field is ATSAM3X8E.Bit; - subtype DEVDMACONTROL1_BUFF_LENGTH_Field is ATSAM3X8E.Short; + subtype DEVDMACONTROL_CHANN_ENB_Field is ATSAM3X8E.Bit; + subtype DEVDMACONTROL_LDNXT_DSC_Field is ATSAM3X8E.Bit; + subtype DEVDMACONTROL_END_TR_EN_Field is ATSAM3X8E.Bit; + subtype DEVDMACONTROL_END_B_EN_Field is ATSAM3X8E.Bit; + subtype DEVDMACONTROL_END_TR_IT_Field is ATSAM3X8E.Bit; + subtype DEVDMACONTROL_END_BUFFIT_Field is ATSAM3X8E.Bit; + subtype DEVDMACONTROL_DESC_LD_IT_Field is ATSAM3X8E.Bit; + subtype DEVDMACONTROL_BURST_LCK_Field is ATSAM3X8E.Bit; + subtype DEVDMACONTROL_BUFF_LENGTH_Field is ATSAM3X8E.UInt16; -- Device DMA Channel Control Register (n = 1) type DEVDMACONTROL_Register is record -- Channel Enable Command - CHANN_ENB : DEVDMACONTROL1_CHANN_ENB_Field := 16#0#; + CHANN_ENB : DEVDMACONTROL_CHANN_ENB_Field := 16#0#; -- Load Next Channel Transfer Descriptor Enable Command - LDNXT_DSC : DEVDMACONTROL1_LDNXT_DSC_Field := 16#0#; + LDNXT_DSC : DEVDMACONTROL_LDNXT_DSC_Field := 16#0#; -- End of Transfer Enable Control - END_TR_EN : DEVDMACONTROL1_END_TR_EN_Field := 16#0#; + END_TR_EN : DEVDMACONTROL_END_TR_EN_Field := 16#0#; -- End of Buffer Enable Control - END_B_EN : DEVDMACONTROL1_END_B_EN_Field := 16#0#; + END_B_EN : DEVDMACONTROL_END_B_EN_Field := 16#0#; -- End of Transfer Interrupt Enable - END_TR_IT : DEVDMACONTROL1_END_TR_IT_Field := 16#0#; + END_TR_IT : DEVDMACONTROL_END_TR_IT_Field := 16#0#; -- End of Buffer Interrupt Enable - END_BUFFIT : DEVDMACONTROL1_END_BUFFIT_Field := 16#0#; + END_BUFFIT : DEVDMACONTROL_END_BUFFIT_Field := 16#0#; -- Descriptor Loaded Interrupt Enable - DESC_LD_IT : DEVDMACONTROL1_DESC_LD_IT_Field := 16#0#; + DESC_LD_IT : DEVDMACONTROL_DESC_LD_IT_Field := 16#0#; -- Burst Lock Enable - BURST_LCK : DEVDMACONTROL1_BURST_LCK_Field := 16#0#; + BURST_LCK : DEVDMACONTROL_BURST_LCK_Field := 16#0#; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Buffer Byte Length (Write-only) - BUFF_LENGTH : DEVDMACONTROL1_BUFF_LENGTH_Field := 16#0#; + BUFF_LENGTH : DEVDMACONTROL_BUFF_LENGTH_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DEVDMACONTROL_Register use record CHANN_ENB at 0 range 0 .. 0; @@ -1476,37 +1374,33 @@ package ATSAM3X8E.UOTGHS is BUFF_LENGTH at 0 range 16 .. 31; end record; - --------------------------- - -- DEVDMASTATUS_Register -- - --------------------------- - - subtype DEVDMASTATUS1_CHANN_ENB_Field is ATSAM3X8E.Bit; - subtype DEVDMASTATUS1_CHANN_ACT_Field is ATSAM3X8E.Bit; - subtype DEVDMASTATUS1_END_TR_ST_Field is ATSAM3X8E.Bit; - subtype DEVDMASTATUS1_END_BF_ST_Field is ATSAM3X8E.Bit; - subtype DEVDMASTATUS1_DESC_LDST_Field is ATSAM3X8E.Bit; - subtype DEVDMASTATUS1_BUFF_COUNT_Field is ATSAM3X8E.Short; + subtype DEVDMASTATUS_CHANN_ENB_Field is ATSAM3X8E.Bit; + subtype DEVDMASTATUS_CHANN_ACT_Field is ATSAM3X8E.Bit; + subtype DEVDMASTATUS_END_TR_ST_Field is ATSAM3X8E.Bit; + subtype DEVDMASTATUS_END_BF_ST_Field is ATSAM3X8E.Bit; + subtype DEVDMASTATUS_DESC_LDST_Field is ATSAM3X8E.Bit; + subtype DEVDMASTATUS_BUFF_COUNT_Field is ATSAM3X8E.UInt16; -- Device DMA Channel Status Register (n = 1) type DEVDMASTATUS_Register is record -- Channel Enable Status - CHANN_ENB : DEVDMASTATUS1_CHANN_ENB_Field := 16#0#; + CHANN_ENB : DEVDMASTATUS_CHANN_ENB_Field := 16#0#; -- Channel Active Status - CHANN_ACT : DEVDMASTATUS1_CHANN_ACT_Field := 16#0#; + CHANN_ACT : DEVDMASTATUS_CHANN_ACT_Field := 16#0#; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- End of Channel Transfer Status - END_TR_ST : DEVDMASTATUS1_END_TR_ST_Field := 16#0#; + END_TR_ST : DEVDMASTATUS_END_TR_ST_Field := 16#0#; -- End of Channel Buffer Status - END_BF_ST : DEVDMASTATUS1_END_BF_ST_Field := 16#0#; + END_BF_ST : DEVDMASTATUS_END_BF_ST_Field := 16#0#; -- Descriptor Loaded Status - DESC_LDST : DEVDMASTATUS1_DESC_LDST_Field := 16#0#; + DESC_LDST : DEVDMASTATUS_DESC_LDST_Field := 16#0#; -- unspecified Reserved_7_15 : ATSAM3X8E.UInt9 := 16#0#; -- Buffer Byte Count - BUFF_COUNT : DEVDMASTATUS1_BUFF_COUNT_Field := 16#0#; + BUFF_COUNT : DEVDMASTATUS_BUFF_COUNT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DEVDMASTATUS_Register use record CHANN_ENB at 0 range 0 .. 0; @@ -1519,34 +1413,50 @@ package ATSAM3X8E.UOTGHS is BUFF_COUNT at 0 range 16 .. 31; end record; - ---------------------- - -- HSTCTRL_Register -- - ---------------------- + subtype UOTGHS_HSTCTRL_SOFE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTCTRL_RESET_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTCTRL_RESUME_Field is ATSAM3X8E.Bit; - subtype HSTCTRL_SOFE_Field is ATSAM3X8E.Bit; - subtype HSTCTRL_RESET_Field is ATSAM3X8E.Bit; - subtype HSTCTRL_RESUME_Field is ATSAM3X8E.Bit; + -- Mode Configuration + type HSTCTRL_SPDCONF_Field is + (-- The host starts in full-speed mode and performs a high-speed reset to +-- switch to the high-speed mode if the downstream peripheral is high-speed +-- capable. + Normal, + -- For a better consumption, if high-speed is not needed. + Low_Power, + -- Forced high speed. + High_Speed, + -- The host remains to full-speed mode whatever the peripheral speed +-- capability. + Forced_Fs) + with Size => 2; + for HSTCTRL_SPDCONF_Field use + (Normal => 0, + Low_Power => 1, + High_Speed => 2, + Forced_Fs => 3); -- Host General Control Register - type HSTCTRL_Register is record + type UOTGHS_HSTCTRL_Register is record -- unspecified Reserved_0_7 : ATSAM3X8E.Byte := 16#0#; -- Start of Frame Generation Enable - SOFE : HSTCTRL_SOFE_Field := 16#0#; + SOFE : UOTGHS_HSTCTRL_SOFE_Field := 16#0#; -- Send USB Reset - RESET : HSTCTRL_RESET_Field := 16#0#; + RESET : UOTGHS_HSTCTRL_RESET_Field := 16#0#; -- Send USB Resume - RESUME : HSTCTRL_RESUME_Field := 16#0#; + RESUME : UOTGHS_HSTCTRL_RESUME_Field := 16#0#; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit := 16#0#; -- Mode Configuration - SPDCONF : SPDCONF_Field := Normal; + SPDCONF : HSTCTRL_SPDCONF_Field := ATSAM3X8E.UOTGHS.Normal; -- unspecified Reserved_14_31 : ATSAM3X8E.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTCTRL_Register use record + for UOTGHS_HSTCTRL_Register use record Reserved_0_7 at 0 range 0 .. 7; SOFE at 0 range 8 .. 8; RESET at 0 range 9 .. 9; @@ -1556,92 +1466,88 @@ package ATSAM3X8E.UOTGHS is Reserved_14_31 at 0 range 14 .. 31; end record; - --------------------- - -- HSTISR_Register -- - --------------------- - - subtype HSTISR_DCONNI_Field is ATSAM3X8E.Bit; - subtype HSTISR_DDISCI_Field is ATSAM3X8E.Bit; - subtype HSTISR_RSTI_Field is ATSAM3X8E.Bit; - subtype HSTISR_RSMEDI_Field is ATSAM3X8E.Bit; - subtype HSTISR_RXRSMI_Field is ATSAM3X8E.Bit; - subtype HSTISR_HSOFI_Field is ATSAM3X8E.Bit; - subtype HSTISR_HWUPI_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_0_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_1_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_2_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_3_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_4_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_5_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_6_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_7_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_8_Field is ATSAM3X8E.Bit; - subtype HSTISR_PEP_9_Field is ATSAM3X8E.Bit; - subtype HSTISR_DMA_1_Field is ATSAM3X8E.Bit; - subtype HSTISR_DMA_2_Field is ATSAM3X8E.Bit; - subtype HSTISR_DMA_3_Field is ATSAM3X8E.Bit; - subtype HSTISR_DMA_4_Field is ATSAM3X8E.Bit; - subtype HSTISR_DMA_5_Field is ATSAM3X8E.Bit; - subtype HSTISR_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_DCONNI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_DDISCI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_RSTI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_RSMEDI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_RXRSMI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_HSOFI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_HWUPI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_0_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_7_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_8_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_PEP_9_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTISR_DMA_6_Field is ATSAM3X8E.Bit; -- Host Global Interrupt Status Register - type HSTISR_Register is record + type UOTGHS_HSTISR_Register is record -- Read-only. Device Connection Interrupt - DCONNI : HSTISR_DCONNI_Field := 16#0#; + DCONNI : UOTGHS_HSTISR_DCONNI_Field; -- Read-only. Device Disconnection Interrupt - DDISCI : HSTISR_DDISCI_Field := 16#0#; + DDISCI : UOTGHS_HSTISR_DDISCI_Field; -- Read-only. USB Reset Sent Interrupt - RSTI : HSTISR_RSTI_Field := 16#0#; + RSTI : UOTGHS_HSTISR_RSTI_Field; -- Read-only. Downstream Resume Sent Interrupt - RSMEDI : HSTISR_RSMEDI_Field := 16#0#; + RSMEDI : UOTGHS_HSTISR_RSMEDI_Field; -- Read-only. Upstream Resume Received Interrupt - RXRSMI : HSTISR_RXRSMI_Field := 16#0#; + RXRSMI : UOTGHS_HSTISR_RXRSMI_Field; -- Read-only. Host Start of Frame Interrupt - HSOFI : HSTISR_HSOFI_Field := 16#0#; + HSOFI : UOTGHS_HSTISR_HSOFI_Field; -- Read-only. Host Wake-Up Interrupt - HWUPI : HSTISR_HWUPI_Field := 16#0#; + HWUPI : UOTGHS_HSTISR_HWUPI_Field; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit; -- Read-only. Pipe 0 Interrupt - PEP_0 : HSTISR_PEP_0_Field := 16#0#; + PEP_0 : UOTGHS_HSTISR_PEP_0_Field; -- Read-only. Pipe 1 Interrupt - PEP_1 : HSTISR_PEP_1_Field := 16#0#; + PEP_1 : UOTGHS_HSTISR_PEP_1_Field; -- Read-only. Pipe 2 Interrupt - PEP_2 : HSTISR_PEP_2_Field := 16#0#; + PEP_2 : UOTGHS_HSTISR_PEP_2_Field; -- Read-only. Pipe 3 Interrupt - PEP_3 : HSTISR_PEP_3_Field := 16#0#; + PEP_3 : UOTGHS_HSTISR_PEP_3_Field; -- Read-only. Pipe 4 Interrupt - PEP_4 : HSTISR_PEP_4_Field := 16#0#; + PEP_4 : UOTGHS_HSTISR_PEP_4_Field; -- Read-only. Pipe 5 Interrupt - PEP_5 : HSTISR_PEP_5_Field := 16#0#; + PEP_5 : UOTGHS_HSTISR_PEP_5_Field; -- Read-only. Pipe 6 Interrupt - PEP_6 : HSTISR_PEP_6_Field := 16#0#; + PEP_6 : UOTGHS_HSTISR_PEP_6_Field; -- Read-only. Pipe 7 Interrupt - PEP_7 : HSTISR_PEP_7_Field := 16#0#; + PEP_7 : UOTGHS_HSTISR_PEP_7_Field; -- Read-only. Pipe 8 Interrupt - PEP_8 : HSTISR_PEP_8_Field := 16#0#; + PEP_8 : UOTGHS_HSTISR_PEP_8_Field; -- Read-only. Pipe 9 Interrupt - PEP_9 : HSTISR_PEP_9_Field := 16#0#; + PEP_9 : UOTGHS_HSTISR_PEP_9_Field; -- unspecified Reserved_18_24 : ATSAM3X8E.UInt7; -- Read-only. DMA Channel 1 Interrupt - DMA_1 : HSTISR_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_HSTISR_DMA_1_Field; -- Read-only. DMA Channel 2 Interrupt - DMA_2 : HSTISR_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_HSTISR_DMA_2_Field; -- Read-only. DMA Channel 3 Interrupt - DMA_3 : HSTISR_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_HSTISR_DMA_3_Field; -- Read-only. DMA Channel 4 Interrupt - DMA_4 : HSTISR_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_HSTISR_DMA_4_Field; -- Read-only. DMA Channel 5 Interrupt - DMA_5 : HSTISR_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_HSTISR_DMA_5_Field; -- Read-only. DMA Channel 6 Interrupt - DMA_6 : HSTISR_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_HSTISR_DMA_6_Field; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTISR_Register use record + for UOTGHS_HSTISR_Register use record DCONNI at 0 range 0 .. 0; DDISCI at 0 range 1 .. 1; RSTI at 0 range 2 .. 2; @@ -1670,40 +1576,36 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- HSTICR_Register -- - --------------------- - - subtype HSTICR_DCONNIC_Field is ATSAM3X8E.Bit; - subtype HSTICR_DDISCIC_Field is ATSAM3X8E.Bit; - subtype HSTICR_RSTIC_Field is ATSAM3X8E.Bit; - subtype HSTICR_RSMEDIC_Field is ATSAM3X8E.Bit; - subtype HSTICR_RXRSMIC_Field is ATSAM3X8E.Bit; - subtype HSTICR_HSOFIC_Field is ATSAM3X8E.Bit; - subtype HSTICR_HWUPIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTICR_DCONNIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTICR_DDISCIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTICR_RSTIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTICR_RSMEDIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTICR_RXRSMIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTICR_HSOFIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTICR_HWUPIC_Field is ATSAM3X8E.Bit; -- Host Global Interrupt Clear Register - type HSTICR_Register is record + type UOTGHS_HSTICR_Register is record -- Write-only. Device Connection Interrupt Clear - DCONNIC : HSTICR_DCONNIC_Field := 16#0#; + DCONNIC : UOTGHS_HSTICR_DCONNIC_Field := 16#0#; -- Write-only. Device Disconnection Interrupt Clear - DDISCIC : HSTICR_DDISCIC_Field := 16#0#; + DDISCIC : UOTGHS_HSTICR_DDISCIC_Field := 16#0#; -- Write-only. USB Reset Sent Interrupt Clear - RSTIC : HSTICR_RSTIC_Field := 16#0#; + RSTIC : UOTGHS_HSTICR_RSTIC_Field := 16#0#; -- Write-only. Downstream Resume Sent Interrupt Clear - RSMEDIC : HSTICR_RSMEDIC_Field := 16#0#; + RSMEDIC : UOTGHS_HSTICR_RSMEDIC_Field := 16#0#; -- Write-only. Upstream Resume Received Interrupt Clear - RXRSMIC : HSTICR_RXRSMIC_Field := 16#0#; + RXRSMIC : UOTGHS_HSTICR_RXRSMIC_Field := 16#0#; -- Write-only. Host Start of Frame Interrupt Clear - HSOFIC : HSTICR_HSOFIC_Field := 16#0#; + HSOFIC : UOTGHS_HSTICR_HSOFIC_Field := 16#0#; -- Write-only. Host Wake-Up Interrupt Clear - HWUPIC : HSTICR_HWUPIC_Field := 16#0#; + HWUPIC : UOTGHS_HSTICR_HWUPIC_Field := 16#0#; -- unspecified Reserved_7_31 : ATSAM3X8E.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTICR_Register use record + for UOTGHS_HSTICR_Register use record DCONNIC at 0 range 0 .. 0; DDISCIC at 0 range 1 .. 1; RSTIC at 0 range 2 .. 2; @@ -1714,60 +1616,56 @@ package ATSAM3X8E.UOTGHS is Reserved_7_31 at 0 range 7 .. 31; end record; - --------------------- - -- HSTIFR_Register -- - --------------------- - - subtype HSTIFR_DCONNIS_Field is ATSAM3X8E.Bit; - subtype HSTIFR_DDISCIS_Field is ATSAM3X8E.Bit; - subtype HSTIFR_RSTIS_Field is ATSAM3X8E.Bit; - subtype HSTIFR_RSMEDIS_Field is ATSAM3X8E.Bit; - subtype HSTIFR_RXRSMIS_Field is ATSAM3X8E.Bit; - subtype HSTIFR_HSOFIS_Field is ATSAM3X8E.Bit; - subtype HSTIFR_HWUPIS_Field is ATSAM3X8E.Bit; - subtype HSTIFR_DMA_1_Field is ATSAM3X8E.Bit; - subtype HSTIFR_DMA_2_Field is ATSAM3X8E.Bit; - subtype HSTIFR_DMA_3_Field is ATSAM3X8E.Bit; - subtype HSTIFR_DMA_4_Field is ATSAM3X8E.Bit; - subtype HSTIFR_DMA_5_Field is ATSAM3X8E.Bit; - subtype HSTIFR_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_DCONNIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_DDISCIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_RSTIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_RSMEDIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_RXRSMIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_HSOFIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_HWUPIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIFR_DMA_6_Field is ATSAM3X8E.Bit; -- Host Global Interrupt Set Register - type HSTIFR_Register is record + type UOTGHS_HSTIFR_Register is record -- Write-only. Device Connection Interrupt Set - DCONNIS : HSTIFR_DCONNIS_Field := 16#0#; + DCONNIS : UOTGHS_HSTIFR_DCONNIS_Field := 16#0#; -- Write-only. Device Disconnection Interrupt Set - DDISCIS : HSTIFR_DDISCIS_Field := 16#0#; + DDISCIS : UOTGHS_HSTIFR_DDISCIS_Field := 16#0#; -- Write-only. USB Reset Sent Interrupt Set - RSTIS : HSTIFR_RSTIS_Field := 16#0#; + RSTIS : UOTGHS_HSTIFR_RSTIS_Field := 16#0#; -- Write-only. Downstream Resume Sent Interrupt Set - RSMEDIS : HSTIFR_RSMEDIS_Field := 16#0#; + RSMEDIS : UOTGHS_HSTIFR_RSMEDIS_Field := 16#0#; -- Write-only. Upstream Resume Received Interrupt Set - RXRSMIS : HSTIFR_RXRSMIS_Field := 16#0#; + RXRSMIS : UOTGHS_HSTIFR_RXRSMIS_Field := 16#0#; -- Write-only. Host Start of Frame Interrupt Set - HSOFIS : HSTIFR_HSOFIS_Field := 16#0#; + HSOFIS : UOTGHS_HSTIFR_HSOFIS_Field := 16#0#; -- Write-only. Host Wake-Up Interrupt Set - HWUPIS : HSTIFR_HWUPIS_Field := 16#0#; + HWUPIS : UOTGHS_HSTIFR_HWUPIS_Field := 16#0#; -- unspecified Reserved_7_24 : ATSAM3X8E.UInt18 := 16#0#; -- Write-only. DMA Channel 1 Interrupt Set - DMA_1 : HSTIFR_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_HSTIFR_DMA_1_Field := 16#0#; -- Write-only. DMA Channel 2 Interrupt Set - DMA_2 : HSTIFR_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_HSTIFR_DMA_2_Field := 16#0#; -- Write-only. DMA Channel 3 Interrupt Set - DMA_3 : HSTIFR_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_HSTIFR_DMA_3_Field := 16#0#; -- Write-only. DMA Channel 4 Interrupt Set - DMA_4 : HSTIFR_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_HSTIFR_DMA_4_Field := 16#0#; -- Write-only. DMA Channel 5 Interrupt Set - DMA_5 : HSTIFR_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_HSTIFR_DMA_5_Field := 16#0#; -- Write-only. DMA Channel 6 Interrupt Set - DMA_6 : HSTIFR_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_HSTIFR_DMA_6_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTIFR_Register use record + for UOTGHS_HSTIFR_Register use record DCONNIS at 0 range 0 .. 0; DDISCIS at 0 range 1 .. 1; RSTIS at 0 range 2 .. 2; @@ -1785,92 +1683,88 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- HSTIMR_Register -- - --------------------- - - subtype HSTIMR_DCONNIE_Field is ATSAM3X8E.Bit; - subtype HSTIMR_DDISCIE_Field is ATSAM3X8E.Bit; - subtype HSTIMR_RSTIE_Field is ATSAM3X8E.Bit; - subtype HSTIMR_RSMEDIE_Field is ATSAM3X8E.Bit; - subtype HSTIMR_RXRSMIE_Field is ATSAM3X8E.Bit; - subtype HSTIMR_HSOFIE_Field is ATSAM3X8E.Bit; - subtype HSTIMR_HWUPIE_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_0_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_1_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_2_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_3_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_4_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_5_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_6_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_7_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_8_Field is ATSAM3X8E.Bit; - subtype HSTIMR_PEP_9_Field is ATSAM3X8E.Bit; - subtype HSTIMR_DMA_1_Field is ATSAM3X8E.Bit; - subtype HSTIMR_DMA_2_Field is ATSAM3X8E.Bit; - subtype HSTIMR_DMA_3_Field is ATSAM3X8E.Bit; - subtype HSTIMR_DMA_4_Field is ATSAM3X8E.Bit; - subtype HSTIMR_DMA_5_Field is ATSAM3X8E.Bit; - subtype HSTIMR_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_DCONNIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_DDISCIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_RSTIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_RSMEDIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_RXRSMIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_HSOFIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_HWUPIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_0_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_7_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_8_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_PEP_9_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIMR_DMA_6_Field is ATSAM3X8E.Bit; -- Host Global Interrupt Mask Register - type HSTIMR_Register is record + type UOTGHS_HSTIMR_Register is record -- Read-only. Device Connection Interrupt Enable - DCONNIE : HSTIMR_DCONNIE_Field := 16#0#; + DCONNIE : UOTGHS_HSTIMR_DCONNIE_Field; -- Read-only. Device Disconnection Interrupt Enable - DDISCIE : HSTIMR_DDISCIE_Field := 16#0#; + DDISCIE : UOTGHS_HSTIMR_DDISCIE_Field; -- Read-only. USB Reset Sent Interrupt Enable - RSTIE : HSTIMR_RSTIE_Field := 16#0#; + RSTIE : UOTGHS_HSTIMR_RSTIE_Field; -- Read-only. Downstream Resume Sent Interrupt Enable - RSMEDIE : HSTIMR_RSMEDIE_Field := 16#0#; + RSMEDIE : UOTGHS_HSTIMR_RSMEDIE_Field; -- Read-only. Upstream Resume Received Interrupt Enable - RXRSMIE : HSTIMR_RXRSMIE_Field := 16#0#; + RXRSMIE : UOTGHS_HSTIMR_RXRSMIE_Field; -- Read-only. Host Start of Frame Interrupt Enable - HSOFIE : HSTIMR_HSOFIE_Field := 16#0#; + HSOFIE : UOTGHS_HSTIMR_HSOFIE_Field; -- Read-only. Host Wake-Up Interrupt Enable - HWUPIE : HSTIMR_HWUPIE_Field := 16#0#; + HWUPIE : UOTGHS_HSTIMR_HWUPIE_Field; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit; -- Read-only. Pipe 0 Interrupt Enable - PEP_0 : HSTIMR_PEP_0_Field := 16#0#; + PEP_0 : UOTGHS_HSTIMR_PEP_0_Field; -- Read-only. Pipe 1 Interrupt Enable - PEP_1 : HSTIMR_PEP_1_Field := 16#0#; + PEP_1 : UOTGHS_HSTIMR_PEP_1_Field; -- Read-only. Pipe 2 Interrupt Enable - PEP_2 : HSTIMR_PEP_2_Field := 16#0#; + PEP_2 : UOTGHS_HSTIMR_PEP_2_Field; -- Read-only. Pipe 3 Interrupt Enable - PEP_3 : HSTIMR_PEP_3_Field := 16#0#; + PEP_3 : UOTGHS_HSTIMR_PEP_3_Field; -- Read-only. Pipe 4 Interrupt Enable - PEP_4 : HSTIMR_PEP_4_Field := 16#0#; + PEP_4 : UOTGHS_HSTIMR_PEP_4_Field; -- Read-only. Pipe 5 Interrupt Enable - PEP_5 : HSTIMR_PEP_5_Field := 16#0#; + PEP_5 : UOTGHS_HSTIMR_PEP_5_Field; -- Read-only. Pipe 6 Interrupt Enable - PEP_6 : HSTIMR_PEP_6_Field := 16#0#; + PEP_6 : UOTGHS_HSTIMR_PEP_6_Field; -- Read-only. Pipe 7 Interrupt Enable - PEP_7 : HSTIMR_PEP_7_Field := 16#0#; + PEP_7 : UOTGHS_HSTIMR_PEP_7_Field; -- Read-only. Pipe 8 Interrupt Enable - PEP_8 : HSTIMR_PEP_8_Field := 16#0#; + PEP_8 : UOTGHS_HSTIMR_PEP_8_Field; -- Read-only. Pipe 9 Interrupt Enable - PEP_9 : HSTIMR_PEP_9_Field := 16#0#; + PEP_9 : UOTGHS_HSTIMR_PEP_9_Field; -- unspecified Reserved_18_24 : ATSAM3X8E.UInt7; -- Read-only. DMA Channel 1 Interrupt Enable - DMA_1 : HSTIMR_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_HSTIMR_DMA_1_Field; -- Read-only. DMA Channel 2 Interrupt Enable - DMA_2 : HSTIMR_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_HSTIMR_DMA_2_Field; -- Read-only. DMA Channel 3 Interrupt Enable - DMA_3 : HSTIMR_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_HSTIMR_DMA_3_Field; -- Read-only. DMA Channel 4 Interrupt Enable - DMA_4 : HSTIMR_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_HSTIMR_DMA_4_Field; -- Read-only. DMA Channel 5 Interrupt Enable - DMA_5 : HSTIMR_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_HSTIMR_DMA_5_Field; -- Read-only. DMA Channel 6 Interrupt Enable - DMA_6 : HSTIMR_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_HSTIMR_DMA_6_Field; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTIMR_Register use record + for UOTGHS_HSTIMR_Register use record DCONNIE at 0 range 0 .. 0; DDISCIE at 0 range 1 .. 1; RSTIE at 0 range 2 .. 2; @@ -1899,92 +1793,88 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- HSTIDR_Register -- - --------------------- - - subtype HSTIDR_DCONNIEC_Field is ATSAM3X8E.Bit; - subtype HSTIDR_DDISCIEC_Field is ATSAM3X8E.Bit; - subtype HSTIDR_RSTIEC_Field is ATSAM3X8E.Bit; - subtype HSTIDR_RSMEDIEC_Field is ATSAM3X8E.Bit; - subtype HSTIDR_RXRSMIEC_Field is ATSAM3X8E.Bit; - subtype HSTIDR_HSOFIEC_Field is ATSAM3X8E.Bit; - subtype HSTIDR_HWUPIEC_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_0_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_1_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_2_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_3_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_4_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_5_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_6_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_7_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_8_Field is ATSAM3X8E.Bit; - subtype HSTIDR_PEP_9_Field is ATSAM3X8E.Bit; - subtype HSTIDR_DMA_1_Field is ATSAM3X8E.Bit; - subtype HSTIDR_DMA_2_Field is ATSAM3X8E.Bit; - subtype HSTIDR_DMA_3_Field is ATSAM3X8E.Bit; - subtype HSTIDR_DMA_4_Field is ATSAM3X8E.Bit; - subtype HSTIDR_DMA_5_Field is ATSAM3X8E.Bit; - subtype HSTIDR_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_DCONNIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_DDISCIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_RSTIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_RSMEDIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_RXRSMIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_HSOFIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_HWUPIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_0_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_7_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_8_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_PEP_9_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIDR_DMA_6_Field is ATSAM3X8E.Bit; -- Host Global Interrupt Disable Register - type HSTIDR_Register is record + type UOTGHS_HSTIDR_Register is record -- Write-only. Device Connection Interrupt Disable - DCONNIEC : HSTIDR_DCONNIEC_Field := 16#0#; + DCONNIEC : UOTGHS_HSTIDR_DCONNIEC_Field := 16#0#; -- Write-only. Device Disconnection Interrupt Disable - DDISCIEC : HSTIDR_DDISCIEC_Field := 16#0#; + DDISCIEC : UOTGHS_HSTIDR_DDISCIEC_Field := 16#0#; -- Write-only. USB Reset Sent Interrupt Disable - RSTIEC : HSTIDR_RSTIEC_Field := 16#0#; + RSTIEC : UOTGHS_HSTIDR_RSTIEC_Field := 16#0#; -- Write-only. Downstream Resume Sent Interrupt Disable - RSMEDIEC : HSTIDR_RSMEDIEC_Field := 16#0#; + RSMEDIEC : UOTGHS_HSTIDR_RSMEDIEC_Field := 16#0#; -- Write-only. Upstream Resume Received Interrupt Disable - RXRSMIEC : HSTIDR_RXRSMIEC_Field := 16#0#; + RXRSMIEC : UOTGHS_HSTIDR_RXRSMIEC_Field := 16#0#; -- Write-only. Host Start of Frame Interrupt Disable - HSOFIEC : HSTIDR_HSOFIEC_Field := 16#0#; + HSOFIEC : UOTGHS_HSTIDR_HSOFIEC_Field := 16#0#; -- Write-only. Host Wake-Up Interrupt Disable - HWUPIEC : HSTIDR_HWUPIEC_Field := 16#0#; + HWUPIEC : UOTGHS_HSTIDR_HWUPIEC_Field := 16#0#; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Pipe 0 Interrupt Disable - PEP_0 : HSTIDR_PEP_0_Field := 16#0#; + PEP_0 : UOTGHS_HSTIDR_PEP_0_Field := 16#0#; -- Write-only. Pipe 1 Interrupt Disable - PEP_1 : HSTIDR_PEP_1_Field := 16#0#; + PEP_1 : UOTGHS_HSTIDR_PEP_1_Field := 16#0#; -- Write-only. Pipe 2 Interrupt Disable - PEP_2 : HSTIDR_PEP_2_Field := 16#0#; + PEP_2 : UOTGHS_HSTIDR_PEP_2_Field := 16#0#; -- Write-only. Pipe 3 Interrupt Disable - PEP_3 : HSTIDR_PEP_3_Field := 16#0#; + PEP_3 : UOTGHS_HSTIDR_PEP_3_Field := 16#0#; -- Write-only. Pipe 4 Interrupt Disable - PEP_4 : HSTIDR_PEP_4_Field := 16#0#; + PEP_4 : UOTGHS_HSTIDR_PEP_4_Field := 16#0#; -- Write-only. Pipe 5 Interrupt Disable - PEP_5 : HSTIDR_PEP_5_Field := 16#0#; + PEP_5 : UOTGHS_HSTIDR_PEP_5_Field := 16#0#; -- Write-only. Pipe 6 Interrupt Disable - PEP_6 : HSTIDR_PEP_6_Field := 16#0#; + PEP_6 : UOTGHS_HSTIDR_PEP_6_Field := 16#0#; -- Write-only. Pipe 7 Interrupt Disable - PEP_7 : HSTIDR_PEP_7_Field := 16#0#; + PEP_7 : UOTGHS_HSTIDR_PEP_7_Field := 16#0#; -- Write-only. Pipe 8 Interrupt Disable - PEP_8 : HSTIDR_PEP_8_Field := 16#0#; + PEP_8 : UOTGHS_HSTIDR_PEP_8_Field := 16#0#; -- Write-only. Pipe 9 Interrupt Disable - PEP_9 : HSTIDR_PEP_9_Field := 16#0#; + PEP_9 : UOTGHS_HSTIDR_PEP_9_Field := 16#0#; -- unspecified Reserved_18_24 : ATSAM3X8E.UInt7 := 16#0#; -- Write-only. DMA Channel 1 Interrupt Disable - DMA_1 : HSTIDR_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_HSTIDR_DMA_1_Field := 16#0#; -- Write-only. DMA Channel 2 Interrupt Disable - DMA_2 : HSTIDR_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_HSTIDR_DMA_2_Field := 16#0#; -- Write-only. DMA Channel 3 Interrupt Disable - DMA_3 : HSTIDR_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_HSTIDR_DMA_3_Field := 16#0#; -- Write-only. DMA Channel 4 Interrupt Disable - DMA_4 : HSTIDR_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_HSTIDR_DMA_4_Field := 16#0#; -- Write-only. DMA Channel 5 Interrupt Disable - DMA_5 : HSTIDR_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_HSTIDR_DMA_5_Field := 16#0#; -- Write-only. DMA Channel 6 Interrupt Disable - DMA_6 : HSTIDR_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_HSTIDR_DMA_6_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTIDR_Register use record + for UOTGHS_HSTIDR_Register use record DCONNIEC at 0 range 0 .. 0; DDISCIEC at 0 range 1 .. 1; RSTIEC at 0 range 2 .. 2; @@ -2013,92 +1903,88 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- HSTIER_Register -- - --------------------- - - subtype HSTIER_DCONNIES_Field is ATSAM3X8E.Bit; - subtype HSTIER_DDISCIES_Field is ATSAM3X8E.Bit; - subtype HSTIER_RSTIES_Field is ATSAM3X8E.Bit; - subtype HSTIER_RSMEDIES_Field is ATSAM3X8E.Bit; - subtype HSTIER_RXRSMIES_Field is ATSAM3X8E.Bit; - subtype HSTIER_HSOFIES_Field is ATSAM3X8E.Bit; - subtype HSTIER_HWUPIES_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_0_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_1_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_2_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_3_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_4_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_5_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_6_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_7_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_8_Field is ATSAM3X8E.Bit; - subtype HSTIER_PEP_9_Field is ATSAM3X8E.Bit; - subtype HSTIER_DMA_1_Field is ATSAM3X8E.Bit; - subtype HSTIER_DMA_2_Field is ATSAM3X8E.Bit; - subtype HSTIER_DMA_3_Field is ATSAM3X8E.Bit; - subtype HSTIER_DMA_4_Field is ATSAM3X8E.Bit; - subtype HSTIER_DMA_5_Field is ATSAM3X8E.Bit; - subtype HSTIER_DMA_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_DCONNIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_DDISCIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_RSTIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_RSMEDIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_RXRSMIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_HSOFIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_HWUPIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_0_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_6_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_7_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_8_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_PEP_9_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_DMA_1_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_DMA_2_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_DMA_3_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_DMA_4_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_DMA_5_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTIER_DMA_6_Field is ATSAM3X8E.Bit; -- Host Global Interrupt Enable Register - type HSTIER_Register is record + type UOTGHS_HSTIER_Register is record -- Write-only. Device Connection Interrupt Enable - DCONNIES : HSTIER_DCONNIES_Field := 16#0#; + DCONNIES : UOTGHS_HSTIER_DCONNIES_Field := 16#0#; -- Write-only. Device Disconnection Interrupt Enable - DDISCIES : HSTIER_DDISCIES_Field := 16#0#; + DDISCIES : UOTGHS_HSTIER_DDISCIES_Field := 16#0#; -- Write-only. USB Reset Sent Interrupt Enable - RSTIES : HSTIER_RSTIES_Field := 16#0#; + RSTIES : UOTGHS_HSTIER_RSTIES_Field := 16#0#; -- Write-only. Downstream Resume Sent Interrupt Enable - RSMEDIES : HSTIER_RSMEDIES_Field := 16#0#; + RSMEDIES : UOTGHS_HSTIER_RSMEDIES_Field := 16#0#; -- Write-only. Upstream Resume Received Interrupt Enable - RXRSMIES : HSTIER_RXRSMIES_Field := 16#0#; + RXRSMIES : UOTGHS_HSTIER_RXRSMIES_Field := 16#0#; -- Write-only. Host Start of Frame Interrupt Enable - HSOFIES : HSTIER_HSOFIES_Field := 16#0#; + HSOFIES : UOTGHS_HSTIER_HSOFIES_Field := 16#0#; -- Write-only. Host Wake-Up Interrupt Enable - HWUPIES : HSTIER_HWUPIES_Field := 16#0#; + HWUPIES : UOTGHS_HSTIER_HWUPIES_Field := 16#0#; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Pipe 0 Interrupt Enable - PEP_0 : HSTIER_PEP_0_Field := 16#0#; + PEP_0 : UOTGHS_HSTIER_PEP_0_Field := 16#0#; -- Write-only. Pipe 1 Interrupt Enable - PEP_1 : HSTIER_PEP_1_Field := 16#0#; + PEP_1 : UOTGHS_HSTIER_PEP_1_Field := 16#0#; -- Write-only. Pipe 2 Interrupt Enable - PEP_2 : HSTIER_PEP_2_Field := 16#0#; + PEP_2 : UOTGHS_HSTIER_PEP_2_Field := 16#0#; -- Write-only. Pipe 3 Interrupt Enable - PEP_3 : HSTIER_PEP_3_Field := 16#0#; + PEP_3 : UOTGHS_HSTIER_PEP_3_Field := 16#0#; -- Write-only. Pipe 4 Interrupt Enable - PEP_4 : HSTIER_PEP_4_Field := 16#0#; + PEP_4 : UOTGHS_HSTIER_PEP_4_Field := 16#0#; -- Write-only. Pipe 5 Interrupt Enable - PEP_5 : HSTIER_PEP_5_Field := 16#0#; + PEP_5 : UOTGHS_HSTIER_PEP_5_Field := 16#0#; -- Write-only. Pipe 6 Interrupt Enable - PEP_6 : HSTIER_PEP_6_Field := 16#0#; + PEP_6 : UOTGHS_HSTIER_PEP_6_Field := 16#0#; -- Write-only. Pipe 7 Interrupt Enable - PEP_7 : HSTIER_PEP_7_Field := 16#0#; + PEP_7 : UOTGHS_HSTIER_PEP_7_Field := 16#0#; -- Write-only. Pipe 8 Interrupt Enable - PEP_8 : HSTIER_PEP_8_Field := 16#0#; + PEP_8 : UOTGHS_HSTIER_PEP_8_Field := 16#0#; -- Write-only. Pipe 9 Interrupt Enable - PEP_9 : HSTIER_PEP_9_Field := 16#0#; + PEP_9 : UOTGHS_HSTIER_PEP_9_Field := 16#0#; -- unspecified Reserved_18_24 : ATSAM3X8E.UInt7 := 16#0#; -- Write-only. DMA Channel 1 Interrupt Enable - DMA_1 : HSTIER_DMA_1_Field := 16#0#; + DMA_1 : UOTGHS_HSTIER_DMA_1_Field := 16#0#; -- Write-only. DMA Channel 2 Interrupt Enable - DMA_2 : HSTIER_DMA_2_Field := 16#0#; + DMA_2 : UOTGHS_HSTIER_DMA_2_Field := 16#0#; -- Write-only. DMA Channel 3 Interrupt Enable - DMA_3 : HSTIER_DMA_3_Field := 16#0#; + DMA_3 : UOTGHS_HSTIER_DMA_3_Field := 16#0#; -- Write-only. DMA Channel 4 Interrupt Enable - DMA_4 : HSTIER_DMA_4_Field := 16#0#; + DMA_4 : UOTGHS_HSTIER_DMA_4_Field := 16#0#; -- Write-only. DMA Channel 5 Interrupt Enable - DMA_5 : HSTIER_DMA_5_Field := 16#0#; + DMA_5 : UOTGHS_HSTIER_DMA_5_Field := 16#0#; -- Write-only. DMA Channel 6 Interrupt Enable - DMA_6 : HSTIER_DMA_6_Field := 16#0#; + DMA_6 : UOTGHS_HSTIER_DMA_6_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTIER_Register use record + for UOTGHS_HSTIER_Register use record DCONNIES at 0 range 0 .. 0; DDISCIES at 0 range 1 .. 1; RSTIES at 0 range 2 .. 2; @@ -2127,23 +2013,16 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------- - -- HSTPIP_Register -- - --------------------- - - ---------------- - -- HSTPIP.PEN -- - ---------------- - - -- HSTPIP_PEN array element - subtype HSTPIP_PEN_Element is ATSAM3X8E.Bit; + -- UOTGHS_HSTPIP_PEN array element + subtype UOTGHS_HSTPIP_PEN_Element is ATSAM3X8E.Bit; - -- HSTPIP_PEN array - type HSTPIP_PEN_Field_Array is array (0 .. 8) of HSTPIP_PEN_Element + -- UOTGHS_HSTPIP_PEN array + type UOTGHS_HSTPIP_PEN_Field_Array is array (0 .. 8) + of UOTGHS_HSTPIP_PEN_Element with Component_Size => 1, Size => 9; - -- Type definition for HSTPIP_PEN - type HSTPIP_PEN_Field + -- Type definition for UOTGHS_HSTPIP_PEN + type UOTGHS_HSTPIP_PEN_Field (As_Array : Boolean := False) is record case As_Array is @@ -2152,29 +2031,26 @@ package ATSAM3X8E.UOTGHS is Val : ATSAM3X8E.UInt9; when True => -- PEN as an array - Arr : HSTPIP_PEN_Field_Array; + Arr : UOTGHS_HSTPIP_PEN_Field_Array; end case; end record with Unchecked_Union, Size => 9; - for HSTPIP_PEN_Field use record + for UOTGHS_HSTPIP_PEN_Field use record Val at 0 range 0 .. 8; Arr at 0 range 0 .. 8; end record; - ----------------- - -- HSTPIP.PRST -- - ----------------- + -- UOTGHS_HSTPIP_PRST array element + subtype UOTGHS_HSTPIP_PRST_Element is ATSAM3X8E.Bit; - -- HSTPIP_PRST array element - subtype HSTPIP_PRST_Element is ATSAM3X8E.Bit; - - -- HSTPIP_PRST array - type HSTPIP_PRST_Field_Array is array (0 .. 8) of HSTPIP_PRST_Element + -- UOTGHS_HSTPIP_PRST array + type UOTGHS_HSTPIP_PRST_Field_Array is array (0 .. 8) + of UOTGHS_HSTPIP_PRST_Element with Component_Size => 1, Size => 9; - -- Type definition for HSTPIP_PRST - type HSTPIP_PRST_Field + -- Type definition for UOTGHS_HSTPIP_PRST + type UOTGHS_HSTPIP_PRST_Field (As_Array : Boolean := False) is record case As_Array is @@ -2183,60 +2059,58 @@ package ATSAM3X8E.UOTGHS is Val : ATSAM3X8E.UInt9; when True => -- PRST as an array - Arr : HSTPIP_PRST_Field_Array; + Arr : UOTGHS_HSTPIP_PRST_Field_Array; end case; end record with Unchecked_Union, Size => 9; - for HSTPIP_PRST_Field use record + for UOTGHS_HSTPIP_PRST_Field use record Val at 0 range 0 .. 8; Arr at 0 range 0 .. 8; end record; -- Host Pipe Register - type HSTPIP_Register is record + type UOTGHS_HSTPIP_Register is record -- Pipe 0 Enable - PEN : HSTPIP_PEN_Field := (As_Array => False, Val => 16#0#); + PEN : UOTGHS_HSTPIP_PEN_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_9_15 : ATSAM3X8E.UInt7 := 16#0#; -- Pipe 0 Reset - PRST : HSTPIP_PRST_Field := (As_Array => False, Val => 16#0#); + PRST : UOTGHS_HSTPIP_PRST_Field := + (As_Array => False, Val => 16#0#); -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIP_Register use record + for UOTGHS_HSTPIP_Register use record PEN at 0 range 0 .. 8; Reserved_9_15 at 0 range 9 .. 15; PRST at 0 range 16 .. 24; Reserved_25_31 at 0 range 25 .. 31; end record; - ---------------------- - -- HSTFNUM_Register -- - ---------------------- - - subtype HSTFNUM_MFNUM_Field is ATSAM3X8E.UInt3; - subtype HSTFNUM_FNUM_Field is ATSAM3X8E.UInt11; - subtype HSTFNUM_FLENHIGH_Field is ATSAM3X8E.Byte; + subtype UOTGHS_HSTFNUM_MFNUM_Field is ATSAM3X8E.UInt3; + subtype UOTGHS_HSTFNUM_FNUM_Field is ATSAM3X8E.UInt11; + subtype UOTGHS_HSTFNUM_FLENHIGH_Field is ATSAM3X8E.Byte; -- Host Frame Number Register - type HSTFNUM_Register is record + type UOTGHS_HSTFNUM_Register is record -- Micro Frame Number - MFNUM : HSTFNUM_MFNUM_Field := 16#0#; + MFNUM : UOTGHS_HSTFNUM_MFNUM_Field := 16#0#; -- Frame Number - FNUM : HSTFNUM_FNUM_Field := 16#0#; + FNUM : UOTGHS_HSTFNUM_FNUM_Field := 16#0#; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Frame Length - FLENHIGH : HSTFNUM_FLENHIGH_Field := 16#0#; + FLENHIGH : UOTGHS_HSTFNUM_FLENHIGH_Field := 16#0#; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTFNUM_Register use record + for UOTGHS_HSTFNUM_Register use record MFNUM at 0 range 0 .. 2; FNUM at 0 range 3 .. 13; Reserved_14_15 at 0 range 14 .. 15; @@ -2244,37 +2118,33 @@ package ATSAM3X8E.UOTGHS is Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------- - -- HSTADDR_Register -- - ---------------------- - - subtype HSTADDR1_HSTADDRP0_Field is ATSAM3X8E.UInt7; - subtype HSTADDR1_HSTADDRP1_Field is ATSAM3X8E.UInt7; - subtype HSTADDR1_HSTADDRP2_Field is ATSAM3X8E.UInt7; - subtype HSTADDR1_HSTADDRP3_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_HSTADDR1_HSTADDRP0_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_HSTADDR1_HSTADDRP1_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_HSTADDR1_HSTADDRP2_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_HSTADDR1_HSTADDRP3_Field is ATSAM3X8E.UInt7; -- Host Address 1 Register - type HSTADDR_Register is record + type UOTGHS_HSTADDR1_Register is record -- USB Host Address - HSTADDRP0 : HSTADDR1_HSTADDRP0_Field := 16#0#; + HSTADDRP0 : UOTGHS_HSTADDR1_HSTADDRP0_Field := 16#0#; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- USB Host Address - HSTADDRP1 : HSTADDR1_HSTADDRP1_Field := 16#0#; + HSTADDRP1 : UOTGHS_HSTADDR1_HSTADDRP1_Field := 16#0#; -- unspecified Reserved_15_15 : ATSAM3X8E.Bit := 16#0#; -- USB Host Address - HSTADDRP2 : HSTADDR1_HSTADDRP2_Field := 16#0#; + HSTADDRP2 : UOTGHS_HSTADDR1_HSTADDRP2_Field := 16#0#; -- unspecified Reserved_23_23 : ATSAM3X8E.Bit := 16#0#; -- USB Host Address - HSTADDRP3 : HSTADDR1_HSTADDRP3_Field := 16#0#; + HSTADDRP3 : UOTGHS_HSTADDR1_HSTADDRP3_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTADDR_Register use record + for UOTGHS_HSTADDR1_Register use record HSTADDRP0 at 0 range 0 .. 6; Reserved_7_7 at 0 range 7 .. 7; HSTADDRP1 at 0 range 8 .. 14; @@ -2285,105 +2155,130 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - ----------------------- - -- HSTADDR3_Register -- - ----------------------- + subtype UOTGHS_HSTADDR2_HSTADDRP4_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_HSTADDR2_HSTADDRP5_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_HSTADDR2_HSTADDRP6_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_HSTADDR2_HSTADDRP7_Field is ATSAM3X8E.UInt7; - subtype HSTADDR3_HSTADDRP8_Field is ATSAM3X8E.UInt7; - subtype HSTADDR3_HSTADDRP9_Field is ATSAM3X8E.UInt7; + -- Host Address 2 Register + type UOTGHS_HSTADDR2_Register is record + -- USB Host Address + HSTADDRP4 : UOTGHS_HSTADDR2_HSTADDRP4_Field := 16#0#; + -- unspecified + Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; + -- USB Host Address + HSTADDRP5 : UOTGHS_HSTADDR2_HSTADDRP5_Field := 16#0#; + -- unspecified + Reserved_15_15 : ATSAM3X8E.Bit := 16#0#; + -- USB Host Address + HSTADDRP6 : UOTGHS_HSTADDR2_HSTADDRP6_Field := 16#0#; + -- unspecified + Reserved_23_23 : ATSAM3X8E.Bit := 16#0#; + -- USB Host Address + HSTADDRP7 : UOTGHS_HSTADDR2_HSTADDRP7_Field := 16#0#; + -- unspecified + Reserved_31_31 : ATSAM3X8E.Bit := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for UOTGHS_HSTADDR2_Register use record + HSTADDRP4 at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + HSTADDRP5 at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + HSTADDRP6 at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + HSTADDRP7 at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype UOTGHS_HSTADDR3_HSTADDRP8_Field is ATSAM3X8E.UInt7; + subtype UOTGHS_HSTADDR3_HSTADDRP9_Field is ATSAM3X8E.UInt7; -- Host Address 3 Register - type HSTADDR3_Register is record + type UOTGHS_HSTADDR3_Register is record -- USB Host Address - HSTADDRP8 : HSTADDR3_HSTADDRP8_Field := 16#0#; + HSTADDRP8 : UOTGHS_HSTADDR3_HSTADDRP8_Field := 16#0#; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- USB Host Address - HSTADDRP9 : HSTADDR3_HSTADDRP9_Field := 16#0#; + HSTADDRP9 : UOTGHS_HSTADDR3_HSTADDRP9_Field := 16#0#; -- unspecified Reserved_15_31 : ATSAM3X8E.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTADDR3_Register use record + for UOTGHS_HSTADDR3_Register use record HSTADDRP8 at 0 range 0 .. 6; Reserved_7_7 at 0 range 7 .. 7; HSTADDRP9 at 0 range 8 .. 14; Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------------ - -- HSTPIPCFG_Register -- - ------------------------ - - subtype HSTPIPCFG_ALLOC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPCFG_ALLOC_Field is ATSAM3X8E.Bit; -- Pipe Banks - type PBK_Field is - ( - -- Single-bank pipe - PBK_Field_1_Bank, + type HSTPIPCFG_PBK_Field is + (-- Single-bank pipe + Val_1_Bank, -- Double-bank pipe - PBK_Field_2_Bank, + Val_2_Bank, -- Triple-bank pipe - PBK_Field_3_Bank) + Val_3_Bank) with Size => 2; - for PBK_Field use - (PBK_Field_1_Bank => 0, - PBK_Field_2_Bank => 1, - PBK_Field_3_Bank => 2); + for HSTPIPCFG_PBK_Field use + (Val_1_Bank => 0, + Val_2_Bank => 1, + Val_3_Bank => 2); -- Pipe Size - type PSIZE_Field is - ( - -- 8 bytes - PSIZE_Field_8_Byte, + type HSTPIPCFG_PSIZE_Field is + (-- 8 bytes + Val_8_Byte, -- 16 bytes - PSIZE_Field_16_Byte, + Val_16_Byte, -- 32 bytes - PSIZE_Field_32_Byte, + Val_32_Byte, -- 64 bytes - PSIZE_Field_64_Byte, + Val_64_Byte, -- 128 bytes - PSIZE_Field_128_Byte, + Val_128_Byte, -- 256 bytes - PSIZE_Field_256_Byte, + Val_256_Byte, -- 512 bytes - PSIZE_Field_512_Byte, + Val_512_Byte, -- 1024 bytes - PSIZE_Field_1024_Byte) + Val_1024_Byte) with Size => 3; - for PSIZE_Field use - (PSIZE_Field_8_Byte => 0, - PSIZE_Field_16_Byte => 1, - PSIZE_Field_32_Byte => 2, - PSIZE_Field_64_Byte => 3, - PSIZE_Field_128_Byte => 4, - PSIZE_Field_256_Byte => 5, - PSIZE_Field_512_Byte => 6, - PSIZE_Field_1024_Byte => 7); + for HSTPIPCFG_PSIZE_Field use + (Val_8_Byte => 0, + Val_16_Byte => 1, + Val_32_Byte => 2, + Val_64_Byte => 3, + Val_128_Byte => 4, + Val_256_Byte => 5, + Val_512_Byte => 6, + Val_1024_Byte => 7); -- Pipe Token - type PTOKEN_Field is - ( - -- SETUP + type HSTPIPCFG_PTOKEN_Field is + (-- SETUP Setup, -- IN In_k, -- OUT Out_k) with Size => 2; - for PTOKEN_Field use + for HSTPIPCFG_PTOKEN_Field use (Setup => 0, In_k => 1, Out_k => 2); - subtype HSTPIPCFG_AUTOSW_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPCFG_AUTOSW_Field is ATSAM3X8E.Bit; -- Pipe Type - type PTYPE_Field is - ( - -- Control + type HSTPIPCFG_PTYPE_Field is + (-- Control Ctrl, -- Isochronous Iso, @@ -2392,47 +2287,47 @@ package ATSAM3X8E.UOTGHS is -- Interrupt Intrpt) with Size => 2; - for PTYPE_Field use + for HSTPIPCFG_PTYPE_Field use (Ctrl => 0, Iso => 1, Blk => 2, Intrpt => 3); - subtype HSTPIPCFG_PEPNUM_Field is ATSAM3X8E.UInt4; - subtype HSTPIPCFG_INTFRQ_Field is ATSAM3X8E.Byte; + subtype UOTGHS_HSTPIPCFG_PEPNUM_Field is ATSAM3X8E.UInt4; + subtype UOTGHS_HSTPIPCFG_INTFRQ_Field is ATSAM3X8E.Byte; -- Host Pipe Configuration Register (n = 0) - type HSTPIPCFG_Register is record + type UOTGHS_HSTPIPCFG_Register is record -- unspecified Reserved_0_0 : ATSAM3X8E.Bit := 16#0#; -- Pipe Memory Allocate - ALLOC : HSTPIPCFG_ALLOC_Field := 16#0#; + ALLOC : UOTGHS_HSTPIPCFG_ALLOC_Field := 16#0#; -- Pipe Banks - PBK : PBK_Field := PBK_Field_1_Bank; + PBK : HSTPIPCFG_PBK_Field := ATSAM3X8E.UOTGHS.Val_1_Bank; -- Pipe Size - PSIZE : PSIZE_Field := PSIZE_Field_8_Byte; + PSIZE : HSTPIPCFG_PSIZE_Field := ATSAM3X8E.UOTGHS.Val_8_Byte; -- unspecified Reserved_7_7 : ATSAM3X8E.Bit := 16#0#; -- Pipe Token - PTOKEN : PTOKEN_Field := Setup; + PTOKEN : HSTPIPCFG_PTOKEN_Field := ATSAM3X8E.UOTGHS.Setup; -- Automatic Switch - AUTOSW : HSTPIPCFG_AUTOSW_Field := 16#0#; + AUTOSW : UOTGHS_HSTPIPCFG_AUTOSW_Field := 16#0#; -- unspecified Reserved_11_11 : ATSAM3X8E.Bit := 16#0#; -- Pipe Type - PTYPE : PTYPE_Field := Ctrl; + PTYPE : HSTPIPCFG_PTYPE_Field := ATSAM3X8E.UOTGHS.Ctrl; -- unspecified Reserved_14_15 : ATSAM3X8E.UInt2 := 16#0#; -- Pipe Endpoint Number - PEPNUM : HSTPIPCFG_PEPNUM_Field := 16#0#; + PEPNUM : UOTGHS_HSTPIPCFG_PEPNUM_Field := 16#0#; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4 := 16#0#; -- Pipe Interrupt Request Frequency - INTFRQ : HSTPIPCFG_INTFRQ_Field := 16#0#; + INTFRQ : UOTGHS_HSTPIPCFG_INTFRQ_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPCFG_Register use record + for UOTGHS_HSTPIPCFG_Register use record Reserved_0_0 at 0 range 0 .. 0; ALLOC at 0 range 1 .. 1; PBK at 0 range 2 .. 3; @@ -2448,80 +2343,103 @@ package ATSAM3X8E.UOTGHS is INTFRQ at 0 range 24 .. 31; end record; - -- Host Pipe Configuration Register (n = 0) - type HSTPIPCFG_Registers is array (0 .. 9) of HSTPIPCFG_Register; - - ------------------------ - -- HSTPIPISR_Register -- - ------------------------ - - subtype HSTPIPISR_RXINI_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_TXOUTI_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_TXSTPI_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_PERRI_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_NAKEDI_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_OVERFI_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_RXSTALLDI_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_SHORTPACKETI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_RXINI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_TXOUTI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_TXSTPI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_PERRI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_NAKEDI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_OVERFI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_RXSTALLDI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_SHORTPACKETI_Field is ATSAM3X8E.Bit; -- Data Toggle Sequence - type DTSEQ_Field_1 is - ( - -- Data0 toggle sequence + type HSTPIPISR_DTSEQ_Field is + (-- Data0 toggle sequence Data0, -- Data1 toggle sequence Data1) with Size => 2; - for DTSEQ_Field_1 use + for HSTPIPISR_DTSEQ_Field use (Data0 => 0, Data1 => 1); - subtype HSTPIPISR_RWALL_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_CFGOK_Field is ATSAM3X8E.Bit; - subtype HSTPIPISR_PBYCT_Field is ATSAM3X8E.UInt11; + -- Number of Busy Banks + type HSTPIPISR_NBUSYBK_Field is + (-- 0 busy bank (all banks free) + Val_0_Busy, + -- 1 busy bank + Val_1_Busy, + -- 2 busy banks + Val_2_Busy, + -- 3 busy banks + Val_3_Busy) + with Size => 2; + for HSTPIPISR_NBUSYBK_Field use + (Val_0_Busy => 0, + Val_1_Busy => 1, + Val_2_Busy => 2, + Val_3_Busy => 3); + + -- Current Bank + type HSTPIPISR_CURRBK_Field is + (-- Current bank is bank0 + Bank0, + -- Current bank is bank1 + Bank1, + -- Current bank is bank2 + Bank2) + with Size => 2; + for HSTPIPISR_CURRBK_Field use + (Bank0 => 0, + Bank1 => 1, + Bank2 => 2); + + subtype UOTGHS_HSTPIPISR_RWALL_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_CFGOK_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPISR_PBYCT_Field is ATSAM3X8E.UInt11; -- Host Pipe Status Register (n = 0) - type HSTPIPISR_Register is record + type UOTGHS_HSTPIPISR_Register is record -- Read-only. Received IN Data Interrupt - RXINI : HSTPIPISR_RXINI_Field := 16#0#; + RXINI : UOTGHS_HSTPIPISR_RXINI_Field; -- Read-only. Transmitted OUT Data Interrupt - TXOUTI : HSTPIPISR_TXOUTI_Field := 16#0#; + TXOUTI : UOTGHS_HSTPIPISR_TXOUTI_Field; -- Read-only. Transmitted SETUP Interrupt - TXSTPI : HSTPIPISR_TXSTPI_Field := 16#0#; + TXSTPI : UOTGHS_HSTPIPISR_TXSTPI_Field; -- Read-only. Pipe Error Interrupt - PERRI : HSTPIPISR_PERRI_Field := 16#0#; + PERRI : UOTGHS_HSTPIPISR_PERRI_Field; -- Read-only. NAKed Interrupt - NAKEDI : HSTPIPISR_NAKEDI_Field := 16#0#; + NAKEDI : UOTGHS_HSTPIPISR_NAKEDI_Field; -- Read-only. Overflow Interrupt - OVERFI : HSTPIPISR_OVERFI_Field := 16#0#; + OVERFI : UOTGHS_HSTPIPISR_OVERFI_Field; -- Read-only. Received STALLed Interrupt - RXSTALLDI : HSTPIPISR_RXSTALLDI_Field := 16#0#; + RXSTALLDI : UOTGHS_HSTPIPISR_RXSTALLDI_Field; -- Read-only. Short Packet Interrupt - SHORTPACKETI : HSTPIPISR_SHORTPACKETI_Field := 16#0#; + SHORTPACKETI : UOTGHS_HSTPIPISR_SHORTPACKETI_Field; -- Read-only. Data Toggle Sequence - DTSEQ : DTSEQ_Field_1 := Data0; + DTSEQ : HSTPIPISR_DTSEQ_Field; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2; -- Read-only. Number of Busy Banks - NBUSYBK : NBUSYBK_Field := NBUSYBK_Field_0_Busy; + NBUSYBK : HSTPIPISR_NBUSYBK_Field; -- Read-only. Current Bank - CURRBK : CURRBK_Field := Bank0; + CURRBK : HSTPIPISR_CURRBK_Field; -- Read-only. Read-write Allowed - RWALL : HSTPIPISR_RWALL_Field := 16#0#; + RWALL : UOTGHS_HSTPIPISR_RWALL_Field; -- unspecified Reserved_17_17 : ATSAM3X8E.Bit; -- Read-only. Configuration OK Status - CFGOK : HSTPIPISR_CFGOK_Field := 16#0#; + CFGOK : UOTGHS_HSTPIPISR_CFGOK_Field; -- unspecified Reserved_19_19 : ATSAM3X8E.Bit; -- Read-only. Pipe Byte Count - PBYCT : HSTPIPISR_PBYCT_Field := 16#0#; + PBYCT : UOTGHS_HSTPIPISR_PBYCT_Field; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPISR_Register use record + for UOTGHS_HSTPIPISR_Register use record RXINI at 0 range 0 .. 0; TXOUTI at 0 range 1 .. 1; TXSTPI at 0 range 2 .. 2; @@ -2542,45 +2460,38 @@ package ATSAM3X8E.UOTGHS is Reserved_31_31 at 0 range 31 .. 31; end record; - -- Host Pipe Status Register (n = 0) - type HSTPIPISR_Registers is array (0 .. 9) of HSTPIPISR_Register; - - ------------------------ - -- HSTPIPICR_Register -- - ------------------------ - - subtype HSTPIPICR_RXINIC_Field is ATSAM3X8E.Bit; - subtype HSTPIPICR_TXOUTIC_Field is ATSAM3X8E.Bit; - subtype HSTPIPICR_TXSTPIC_Field is ATSAM3X8E.Bit; - subtype HSTPIPICR_NAKEDIC_Field is ATSAM3X8E.Bit; - subtype HSTPIPICR_OVERFIC_Field is ATSAM3X8E.Bit; - subtype HSTPIPICR_RXSTALLDIC_Field is ATSAM3X8E.Bit; - subtype HSTPIPICR_SHORTPACKETIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPICR_RXINIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPICR_TXOUTIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPICR_TXSTPIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPICR_NAKEDIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPICR_OVERFIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPICR_RXSTALLDIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPICR_SHORTPACKETIC_Field is ATSAM3X8E.Bit; -- Host Pipe Clear Register (n = 0) - type HSTPIPICR_Register is record + type UOTGHS_HSTPIPICR_Register is record -- Write-only. Received IN Data Interrupt Clear - RXINIC : HSTPIPICR_RXINIC_Field := 16#0#; + RXINIC : UOTGHS_HSTPIPICR_RXINIC_Field := 16#0#; -- Write-only. Transmitted OUT Data Interrupt Clear - TXOUTIC : HSTPIPICR_TXOUTIC_Field := 16#0#; + TXOUTIC : UOTGHS_HSTPIPICR_TXOUTIC_Field := 16#0#; -- Write-only. Transmitted SETUP Interrupt Clear - TXSTPIC : HSTPIPICR_TXSTPIC_Field := 16#0#; + TXSTPIC : UOTGHS_HSTPIPICR_TXSTPIC_Field := 16#0#; -- unspecified Reserved_3_3 : ATSAM3X8E.Bit := 16#0#; -- Write-only. NAKed Interrupt Clear - NAKEDIC : HSTPIPICR_NAKEDIC_Field := 16#0#; + NAKEDIC : UOTGHS_HSTPIPICR_NAKEDIC_Field := 16#0#; -- Write-only. Overflow Interrupt Clear - OVERFIC : HSTPIPICR_OVERFIC_Field := 16#0#; + OVERFIC : UOTGHS_HSTPIPICR_OVERFIC_Field := 16#0#; -- Write-only. Received STALLed Interrupt Clear - RXSTALLDIC : HSTPIPICR_RXSTALLDIC_Field := 16#0#; + RXSTALLDIC : UOTGHS_HSTPIPICR_RXSTALLDIC_Field := 16#0#; -- Write-only. Short Packet Interrupt Clear - SHORTPACKETIC : HSTPIPICR_SHORTPACKETIC_Field := 16#0#; + SHORTPACKETIC : UOTGHS_HSTPIPICR_SHORTPACKETIC_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPICR_Register use record + for UOTGHS_HSTPIPICR_Register use record RXINIC at 0 range 0 .. 0; TXOUTIC at 0 range 1 .. 1; TXSTPIC at 0 range 2 .. 2; @@ -2592,51 +2503,44 @@ package ATSAM3X8E.UOTGHS is Reserved_8_31 at 0 range 8 .. 31; end record; - -- Host Pipe Clear Register (n = 0) - type HSTPIPICR_Registers is array (0 .. 9) of HSTPIPICR_Register; - - ------------------------ - -- HSTPIPIFR_Register -- - ------------------------ - - subtype HSTPIPIFR_RXINIS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIFR_TXOUTIS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIFR_TXSTPIS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIFR_PERRIS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIFR_NAKEDIS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIFR_OVERFIS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIFR_RXSTALLDIS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIFR_SHORTPACKETIS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIFR_NBUSYBKS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_RXINIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_TXOUTIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_TXSTPIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_PERRIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_NAKEDIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_OVERFIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_RXSTALLDIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_SHORTPACKETIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIFR_NBUSYBKS_Field is ATSAM3X8E.Bit; -- Host Pipe Set Register (n = 0) - type HSTPIPIFR_Register is record + type UOTGHS_HSTPIPIFR_Register is record -- Write-only. Received IN Data Interrupt Set - RXINIS : HSTPIPIFR_RXINIS_Field := 16#0#; + RXINIS : UOTGHS_HSTPIPIFR_RXINIS_Field := 16#0#; -- Write-only. Transmitted OUT Data Interrupt Set - TXOUTIS : HSTPIPIFR_TXOUTIS_Field := 16#0#; + TXOUTIS : UOTGHS_HSTPIPIFR_TXOUTIS_Field := 16#0#; -- Write-only. Transmitted SETUP Interrupt Set - TXSTPIS : HSTPIPIFR_TXSTPIS_Field := 16#0#; + TXSTPIS : UOTGHS_HSTPIPIFR_TXSTPIS_Field := 16#0#; -- Write-only. Pipe Error Interrupt Set - PERRIS : HSTPIPIFR_PERRIS_Field := 16#0#; + PERRIS : UOTGHS_HSTPIPIFR_PERRIS_Field := 16#0#; -- Write-only. NAKed Interrupt Set - NAKEDIS : HSTPIPIFR_NAKEDIS_Field := 16#0#; + NAKEDIS : UOTGHS_HSTPIPIFR_NAKEDIS_Field := 16#0#; -- Write-only. Overflow Interrupt Set - OVERFIS : HSTPIPIFR_OVERFIS_Field := 16#0#; + OVERFIS : UOTGHS_HSTPIPIFR_OVERFIS_Field := 16#0#; -- Write-only. Received STALLed Interrupt Set - RXSTALLDIS : HSTPIPIFR_RXSTALLDIS_Field := 16#0#; + RXSTALLDIS : UOTGHS_HSTPIPIFR_RXSTALLDIS_Field := 16#0#; -- Write-only. Short Packet Interrupt Set - SHORTPACKETIS : HSTPIPIFR_SHORTPACKETIS_Field := 16#0#; + SHORTPACKETIS : UOTGHS_HSTPIPIFR_SHORTPACKETIS_Field := 16#0#; -- unspecified Reserved_8_11 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Number of Busy Banks Set - NBUSYBKS : HSTPIPIFR_NBUSYBKS_Field := 16#0#; + NBUSYBKS : UOTGHS_HSTPIPIFR_NBUSYBKS_Field := 16#0#; -- unspecified Reserved_13_31 : ATSAM3X8E.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPIFR_Register use record + for UOTGHS_HSTPIPIFR_Register use record RXINIS at 0 range 0 .. 0; TXOUTIS at 0 range 1 .. 1; TXSTPIS at 0 range 2 .. 2; @@ -2650,67 +2554,60 @@ package ATSAM3X8E.UOTGHS is Reserved_13_31 at 0 range 13 .. 31; end record; - -- Host Pipe Set Register (n = 0) - type HSTPIPIFR_Registers is array (0 .. 9) of HSTPIPIFR_Register; - - ------------------------ - -- HSTPIPIMR_Register -- - ------------------------ - - subtype HSTPIPIMR_RXINE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_TXOUTE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_TXSTPE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_PERRE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_NAKEDE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_OVERFIE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_RXSTALLDE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_SHORTPACKETIE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_NBUSYBKE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_FIFOCON_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_PDISHDMA_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_PFREEZE_Field is ATSAM3X8E.Bit; - subtype HSTPIPIMR_RSTDT_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_RXINE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_TXOUTE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_TXSTPE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_PERRE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_NAKEDE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_OVERFIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_RXSTALLDE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_SHORTPACKETIE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_NBUSYBKE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_FIFOCON_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_PDISHDMA_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_PFREEZE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIMR_RSTDT_Field is ATSAM3X8E.Bit; -- Host Pipe Mask Register (n = 0) - type HSTPIPIMR_Register is record + type UOTGHS_HSTPIPIMR_Register is record -- Read-only. Received IN Data Interrupt Enable - RXINE : HSTPIPIMR_RXINE_Field := 16#0#; + RXINE : UOTGHS_HSTPIPIMR_RXINE_Field; -- Read-only. Transmitted OUT Data Interrupt Enable - TXOUTE : HSTPIPIMR_TXOUTE_Field := 16#0#; + TXOUTE : UOTGHS_HSTPIPIMR_TXOUTE_Field; -- Read-only. Transmitted SETUP Interrupt Enable - TXSTPE : HSTPIPIMR_TXSTPE_Field := 16#0#; + TXSTPE : UOTGHS_HSTPIPIMR_TXSTPE_Field; -- Read-only. Pipe Error Interrupt Enable - PERRE : HSTPIPIMR_PERRE_Field := 16#0#; + PERRE : UOTGHS_HSTPIPIMR_PERRE_Field; -- Read-only. NAKed Interrupt Enable - NAKEDE : HSTPIPIMR_NAKEDE_Field := 16#0#; + NAKEDE : UOTGHS_HSTPIPIMR_NAKEDE_Field; -- Read-only. Overflow Interrupt Enable - OVERFIE : HSTPIPIMR_OVERFIE_Field := 16#0#; + OVERFIE : UOTGHS_HSTPIPIMR_OVERFIE_Field; -- Read-only. Received STALLed Interrupt Enable - RXSTALLDE : HSTPIPIMR_RXSTALLDE_Field := 16#0#; + RXSTALLDE : UOTGHS_HSTPIPIMR_RXSTALLDE_Field; -- Read-only. Short Packet Interrupt Enable - SHORTPACKETIE : HSTPIPIMR_SHORTPACKETIE_Field := 16#0#; + SHORTPACKETIE : UOTGHS_HSTPIPIMR_SHORTPACKETIE_Field; -- unspecified Reserved_8_11 : ATSAM3X8E.UInt4; -- Read-only. Number of Busy Banks Interrupt Enable - NBUSYBKE : HSTPIPIMR_NBUSYBKE_Field := 16#0#; + NBUSYBKE : UOTGHS_HSTPIPIMR_NBUSYBKE_Field; -- unspecified Reserved_13_13 : ATSAM3X8E.Bit; -- Read-only. FIFO Control - FIFOCON : HSTPIPIMR_FIFOCON_Field := 16#0#; + FIFOCON : UOTGHS_HSTPIPIMR_FIFOCON_Field; -- unspecified Reserved_15_15 : ATSAM3X8E.Bit; -- Read-only. Pipe Interrupts Disable HDMA Request Enable - PDISHDMA : HSTPIPIMR_PDISHDMA_Field := 16#0#; + PDISHDMA : UOTGHS_HSTPIPIMR_PDISHDMA_Field; -- Read-only. Pipe Freeze - PFREEZE : HSTPIPIMR_PFREEZE_Field := 16#0#; + PFREEZE : UOTGHS_HSTPIPIMR_PFREEZE_Field; -- Read-only. Reset Data Toggle - RSTDT : HSTPIPIMR_RSTDT_Field := 16#0#; + RSTDT : UOTGHS_HSTPIPIMR_RSTDT_Field; -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPIMR_Register use record + for UOTGHS_HSTPIPIMR_Register use record RXINE at 0 range 0 .. 0; TXOUTE at 0 range 1 .. 1; TXSTPE at 0 range 2 .. 2; @@ -2730,62 +2627,55 @@ package ATSAM3X8E.UOTGHS is Reserved_19_31 at 0 range 19 .. 31; end record; - -- Host Pipe Mask Register (n = 0) - type HSTPIPIMR_Registers is array (0 .. 9) of HSTPIPIMR_Register; - - ------------------------ - -- HSTPIPIER_Register -- - ------------------------ - - subtype HSTPIPIER_RXINES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_TXOUTES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_TXSTPES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_PERRES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_NAKEDES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_OVERFIES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_RXSTALLDES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_SHORTPACKETIES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_NBUSYBKES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_PDISHDMAS_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_PFREEZES_Field is ATSAM3X8E.Bit; - subtype HSTPIPIER_RSTDTS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_RXINES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_TXOUTES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_TXSTPES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_PERRES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_NAKEDES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_OVERFIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_RXSTALLDES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_SHORTPACKETIES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_NBUSYBKES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_PDISHDMAS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_PFREEZES_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIER_RSTDTS_Field is ATSAM3X8E.Bit; -- Host Pipe Enable Register (n = 0) - type HSTPIPIER_Register is record + type UOTGHS_HSTPIPIER_Register is record -- Write-only. Received IN Data Interrupt Enable - RXINES : HSTPIPIER_RXINES_Field := 16#0#; + RXINES : UOTGHS_HSTPIPIER_RXINES_Field := 16#0#; -- Write-only. Transmitted OUT Data Interrupt Enable - TXOUTES : HSTPIPIER_TXOUTES_Field := 16#0#; + TXOUTES : UOTGHS_HSTPIPIER_TXOUTES_Field := 16#0#; -- Write-only. Transmitted SETUP Interrupt Enable - TXSTPES : HSTPIPIER_TXSTPES_Field := 16#0#; + TXSTPES : UOTGHS_HSTPIPIER_TXSTPES_Field := 16#0#; -- Write-only. Pipe Error Interrupt Enable - PERRES : HSTPIPIER_PERRES_Field := 16#0#; + PERRES : UOTGHS_HSTPIPIER_PERRES_Field := 16#0#; -- Write-only. NAKed Interrupt Enable - NAKEDES : HSTPIPIER_NAKEDES_Field := 16#0#; + NAKEDES : UOTGHS_HSTPIPIER_NAKEDES_Field := 16#0#; -- Write-only. Overflow Interrupt Enable - OVERFIES : HSTPIPIER_OVERFIES_Field := 16#0#; + OVERFIES : UOTGHS_HSTPIPIER_OVERFIES_Field := 16#0#; -- Write-only. Received STALLed Interrupt Enable - RXSTALLDES : HSTPIPIER_RXSTALLDES_Field := 16#0#; + RXSTALLDES : UOTGHS_HSTPIPIER_RXSTALLDES_Field := 16#0#; -- Write-only. Short Packet Interrupt Enable - SHORTPACKETIES : HSTPIPIER_SHORTPACKETIES_Field := 16#0#; + SHORTPACKETIES : UOTGHS_HSTPIPIER_SHORTPACKETIES_Field := 16#0#; -- unspecified Reserved_8_11 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Number of Busy Banks Enable - NBUSYBKES : HSTPIPIER_NBUSYBKES_Field := 16#0#; + NBUSYBKES : UOTGHS_HSTPIPIER_NBUSYBKES_Field := 16#0#; -- unspecified Reserved_13_15 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. Pipe Interrupts Disable HDMA Request Enable - PDISHDMAS : HSTPIPIER_PDISHDMAS_Field := 16#0#; + PDISHDMAS : UOTGHS_HSTPIPIER_PDISHDMAS_Field := 16#0#; -- Write-only. Pipe Freeze Enable - PFREEZES : HSTPIPIER_PFREEZES_Field := 16#0#; + PFREEZES : UOTGHS_HSTPIPIER_PFREEZES_Field := 16#0#; -- Write-only. Reset Data Toggle Enable - RSTDTS : HSTPIPIER_RSTDTS_Field := 16#0#; + RSTDTS : UOTGHS_HSTPIPIER_RSTDTS_Field := 16#0#; -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPIER_Register use record + for UOTGHS_HSTPIPIER_Register use record RXINES at 0 range 0 .. 0; TXOUTES at 0 range 1 .. 1; TXSTPES at 0 range 2 .. 2; @@ -2803,64 +2693,57 @@ package ATSAM3X8E.UOTGHS is Reserved_19_31 at 0 range 19 .. 31; end record; - -- Host Pipe Enable Register (n = 0) - type HSTPIPIER_Registers is array (0 .. 9) of HSTPIPIER_Register; - - ------------------------ - -- HSTPIPIDR_Register -- - ------------------------ - - subtype HSTPIPIDR_RXINEC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_TXOUTEC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_TXSTPEC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_PERREC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_NAKEDEC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_OVERFIEC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_RXSTALLDEC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_SHORTPACKETIEC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_NBUSYBKEC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_FIFOCONC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_PDISHDMAC_Field is ATSAM3X8E.Bit; - subtype HSTPIPIDR_PFREEZEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_RXINEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_TXOUTEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_TXSTPEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_PERREC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_NAKEDEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_OVERFIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_RXSTALLDEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_SHORTPACKETIEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_NBUSYBKEC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_FIFOCONC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_PDISHDMAC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPIDR_PFREEZEC_Field is ATSAM3X8E.Bit; -- Host Pipe Disable Register (n = 0) - type HSTPIPIDR_Register is record + type UOTGHS_HSTPIPIDR_Register is record -- Write-only. Received IN Data Interrupt Disable - RXINEC : HSTPIPIDR_RXINEC_Field := 16#0#; + RXINEC : UOTGHS_HSTPIPIDR_RXINEC_Field := 16#0#; -- Write-only. Transmitted OUT Data Interrupt Disable - TXOUTEC : HSTPIPIDR_TXOUTEC_Field := 16#0#; + TXOUTEC : UOTGHS_HSTPIPIDR_TXOUTEC_Field := 16#0#; -- Write-only. Transmitted SETUP Interrupt Disable - TXSTPEC : HSTPIPIDR_TXSTPEC_Field := 16#0#; + TXSTPEC : UOTGHS_HSTPIPIDR_TXSTPEC_Field := 16#0#; -- Write-only. Pipe Error Interrupt Disable - PERREC : HSTPIPIDR_PERREC_Field := 16#0#; + PERREC : UOTGHS_HSTPIPIDR_PERREC_Field := 16#0#; -- Write-only. NAKed Interrupt Disable - NAKEDEC : HSTPIPIDR_NAKEDEC_Field := 16#0#; + NAKEDEC : UOTGHS_HSTPIPIDR_NAKEDEC_Field := 16#0#; -- Write-only. Overflow Interrupt Disable - OVERFIEC : HSTPIPIDR_OVERFIEC_Field := 16#0#; + OVERFIEC : UOTGHS_HSTPIPIDR_OVERFIEC_Field := 16#0#; -- Write-only. Received STALLed Interrupt Disable - RXSTALLDEC : HSTPIPIDR_RXSTALLDEC_Field := 16#0#; + RXSTALLDEC : UOTGHS_HSTPIPIDR_RXSTALLDEC_Field := 16#0#; -- Write-only. Short Packet Interrupt Disable - SHORTPACKETIEC : HSTPIPIDR_SHORTPACKETIEC_Field := 16#0#; + SHORTPACKETIEC : UOTGHS_HSTPIPIDR_SHORTPACKETIEC_Field := 16#0#; -- unspecified Reserved_8_11 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Number of Busy Banks Disable - NBUSYBKEC : HSTPIPIDR_NBUSYBKEC_Field := 16#0#; + NBUSYBKEC : UOTGHS_HSTPIPIDR_NBUSYBKEC_Field := 16#0#; -- unspecified Reserved_13_13 : ATSAM3X8E.Bit := 16#0#; -- Write-only. FIFO Control Disable - FIFOCONC : HSTPIPIDR_FIFOCONC_Field := 16#0#; + FIFOCONC : UOTGHS_HSTPIPIDR_FIFOCONC_Field := 16#0#; -- unspecified Reserved_15_15 : ATSAM3X8E.Bit := 16#0#; -- Write-only. Pipe Interrupts Disable HDMA Request Disable - PDISHDMAC : HSTPIPIDR_PDISHDMAC_Field := 16#0#; + PDISHDMAC : UOTGHS_HSTPIPIDR_PDISHDMAC_Field := 16#0#; -- Write-only. Pipe Freeze Disable - PFREEZEC : HSTPIPIDR_PFREEZEC_Field := 16#0#; + PFREEZEC : UOTGHS_HSTPIPIDR_PFREEZEC_Field := 16#0#; -- unspecified Reserved_18_31 : ATSAM3X8E.UInt14 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPIDR_Register use record + for UOTGHS_HSTPIPIDR_Register use record RXINEC at 0 range 0 .. 0; TXOUTEC at 0 range 1 .. 1; TXSTPEC at 0 range 2 .. 2; @@ -2879,67 +2762,53 @@ package ATSAM3X8E.UOTGHS is Reserved_18_31 at 0 range 18 .. 31; end record; - -- Host Pipe Disable Register (n = 0) - type HSTPIPIDR_Registers is array (0 .. 9) of HSTPIPIDR_Register; - - ------------------------- - -- HSTPIPINRQ_Register -- - ------------------------- - - subtype HSTPIPINRQ_INRQ_Field is ATSAM3X8E.Byte; - subtype HSTPIPINRQ_INMODE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPINRQ_INRQ_Field is ATSAM3X8E.Byte; + subtype UOTGHS_HSTPIPINRQ_INMODE_Field is ATSAM3X8E.Bit; -- Host Pipe IN Request Register (n = 0) - type HSTPIPINRQ_Register is record + type UOTGHS_HSTPIPINRQ_Register is record -- IN Request Number before Freeze - INRQ : HSTPIPINRQ_INRQ_Field := 16#0#; + INRQ : UOTGHS_HSTPIPINRQ_INRQ_Field := 16#0#; -- IN Request Mode - INMODE : HSTPIPINRQ_INMODE_Field := 16#0#; + INMODE : UOTGHS_HSTPIPINRQ_INMODE_Field := 16#0#; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPINRQ_Register use record + for UOTGHS_HSTPIPINRQ_Register use record INRQ at 0 range 0 .. 7; INMODE at 0 range 8 .. 8; Reserved_9_31 at 0 range 9 .. 31; end record; - -- Host Pipe IN Request Register (n = 0) - type HSTPIPINRQ_Registers is array (0 .. 9) of HSTPIPINRQ_Register; - - ------------------------ - -- HSTPIPERR_Register -- - ------------------------ - - subtype HSTPIPERR_DATATGL_Field is ATSAM3X8E.Bit; - subtype HSTPIPERR_DATAPID_Field is ATSAM3X8E.Bit; - subtype HSTPIPERR_PID_Field is ATSAM3X8E.Bit; - subtype HSTPIPERR_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype HSTPIPERR_CRC16_Field is ATSAM3X8E.Bit; - subtype HSTPIPERR_COUNTER_Field is ATSAM3X8E.UInt2; + subtype UOTGHS_HSTPIPERR_DATATGL_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPERR_DATAPID_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPERR_PID_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPERR_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPERR_CRC16_Field is ATSAM3X8E.Bit; + subtype UOTGHS_HSTPIPERR_COUNTER_Field is ATSAM3X8E.UInt2; -- Host Pipe Error Register (n = 0) - type HSTPIPERR_Register is record + type UOTGHS_HSTPIPERR_Register is record -- Data Toggle Error - DATATGL : HSTPIPERR_DATATGL_Field := 16#0#; + DATATGL : UOTGHS_HSTPIPERR_DATATGL_Field := 16#0#; -- Data PID Error - DATAPID : HSTPIPERR_DATAPID_Field := 16#0#; + DATAPID : UOTGHS_HSTPIPERR_DATAPID_Field := 16#0#; -- PID Error - PID : HSTPIPERR_PID_Field := 16#0#; + PID : UOTGHS_HSTPIPERR_PID_Field := 16#0#; -- Time-Out Error - TIMEOUT : HSTPIPERR_TIMEOUT_Field := 16#0#; + TIMEOUT : UOTGHS_HSTPIPERR_TIMEOUT_Field := 16#0#; -- CRC16 Error - CRC16 : HSTPIPERR_CRC16_Field := 16#0#; + CRC16 : UOTGHS_HSTPIPERR_CRC16_Field := 16#0#; -- Error Counter - COUNTER : HSTPIPERR_COUNTER_Field := 16#0#; + COUNTER : UOTGHS_HSTPIPERR_COUNTER_Field := 16#0#; -- unspecified Reserved_7_31 : ATSAM3X8E.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HSTPIPERR_Register use record + for UOTGHS_HSTPIPERR_Register use record DATATGL at 0 range 0 .. 0; DATAPID at 0 range 1 .. 1; PID at 0 range 2 .. 2; @@ -2949,47 +2818,40 @@ package ATSAM3X8E.UOTGHS is Reserved_7_31 at 0 range 7 .. 31; end record; - -- Host Pipe Error Register (n = 0) - type HSTPIPERR_Registers is array (0 .. 9) of HSTPIPERR_Register; - - ---------------------------- - -- HSTDMACONTROL_Register -- - ---------------------------- - - subtype HSTDMACONTROL1_CHANN_ENB_Field is ATSAM3X8E.Bit; - subtype HSTDMACONTROL1_LDNXT_DSC_Field is ATSAM3X8E.Bit; - subtype HSTDMACONTROL1_END_TR_EN_Field is ATSAM3X8E.Bit; - subtype HSTDMACONTROL1_END_B_EN_Field is ATSAM3X8E.Bit; - subtype HSTDMACONTROL1_END_TR_IT_Field is ATSAM3X8E.Bit; - subtype HSTDMACONTROL1_END_BUFFIT_Field is ATSAM3X8E.Bit; - subtype HSTDMACONTROL1_DESC_LD_IT_Field is ATSAM3X8E.Bit; - subtype HSTDMACONTROL1_BURST_LCK_Field is ATSAM3X8E.Bit; - subtype HSTDMACONTROL1_BUFF_LENGTH_Field is ATSAM3X8E.Short; + subtype HSTDMACONTROL_CHANN_ENB_Field is ATSAM3X8E.Bit; + subtype HSTDMACONTROL_LDNXT_DSC_Field is ATSAM3X8E.Bit; + subtype HSTDMACONTROL_END_TR_EN_Field is ATSAM3X8E.Bit; + subtype HSTDMACONTROL_END_B_EN_Field is ATSAM3X8E.Bit; + subtype HSTDMACONTROL_END_TR_IT_Field is ATSAM3X8E.Bit; + subtype HSTDMACONTROL_END_BUFFIT_Field is ATSAM3X8E.Bit; + subtype HSTDMACONTROL_DESC_LD_IT_Field is ATSAM3X8E.Bit; + subtype HSTDMACONTROL_BURST_LCK_Field is ATSAM3X8E.Bit; + subtype HSTDMACONTROL_BUFF_LENGTH_Field is ATSAM3X8E.UInt16; -- Host DMA Channel Control Register (n = 1) type HSTDMACONTROL_Register is record -- Channel Enable Command - CHANN_ENB : HSTDMACONTROL1_CHANN_ENB_Field := 16#0#; + CHANN_ENB : HSTDMACONTROL_CHANN_ENB_Field := 16#0#; -- Load Next Channel Transfer Descriptor Enable Command - LDNXT_DSC : HSTDMACONTROL1_LDNXT_DSC_Field := 16#0#; + LDNXT_DSC : HSTDMACONTROL_LDNXT_DSC_Field := 16#0#; -- End of Transfer Enable (Control) - END_TR_EN : HSTDMACONTROL1_END_TR_EN_Field := 16#0#; + END_TR_EN : HSTDMACONTROL_END_TR_EN_Field := 16#0#; -- End of Buffer Enable Control - END_B_EN : HSTDMACONTROL1_END_B_EN_Field := 16#0#; + END_B_EN : HSTDMACONTROL_END_B_EN_Field := 16#0#; -- End of Transfer Interrupt Enable - END_TR_IT : HSTDMACONTROL1_END_TR_IT_Field := 16#0#; + END_TR_IT : HSTDMACONTROL_END_TR_IT_Field := 16#0#; -- End of Buffer Interrupt Enable - END_BUFFIT : HSTDMACONTROL1_END_BUFFIT_Field := 16#0#; + END_BUFFIT : HSTDMACONTROL_END_BUFFIT_Field := 16#0#; -- Descriptor Loaded Interrupt Enable - DESC_LD_IT : HSTDMACONTROL1_DESC_LD_IT_Field := 16#0#; + DESC_LD_IT : HSTDMACONTROL_DESC_LD_IT_Field := 16#0#; -- Burst Lock Enable - BURST_LCK : HSTDMACONTROL1_BURST_LCK_Field := 16#0#; + BURST_LCK : HSTDMACONTROL_BURST_LCK_Field := 16#0#; -- unspecified Reserved_8_15 : ATSAM3X8E.Byte := 16#0#; -- Buffer Byte Length (Write-only) - BUFF_LENGTH : HSTDMACONTROL1_BUFF_LENGTH_Field := 16#0#; + BUFF_LENGTH : HSTDMACONTROL_BUFF_LENGTH_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for HSTDMACONTROL_Register use record CHANN_ENB at 0 range 0 .. 0; @@ -3004,37 +2866,33 @@ package ATSAM3X8E.UOTGHS is BUFF_LENGTH at 0 range 16 .. 31; end record; - --------------------------- - -- HSTDMASTATUS_Register -- - --------------------------- - - subtype HSTDMASTATUS1_CHANN_ENB_Field is ATSAM3X8E.Bit; - subtype HSTDMASTATUS1_CHANN_ACT_Field is ATSAM3X8E.Bit; - subtype HSTDMASTATUS1_END_TR_ST_Field is ATSAM3X8E.Bit; - subtype HSTDMASTATUS1_END_BF_ST_Field is ATSAM3X8E.Bit; - subtype HSTDMASTATUS1_DESC_LDST_Field is ATSAM3X8E.Bit; - subtype HSTDMASTATUS1_BUFF_COUNT_Field is ATSAM3X8E.Short; + subtype HSTDMASTATUS_CHANN_ENB_Field is ATSAM3X8E.Bit; + subtype HSTDMASTATUS_CHANN_ACT_Field is ATSAM3X8E.Bit; + subtype HSTDMASTATUS_END_TR_ST_Field is ATSAM3X8E.Bit; + subtype HSTDMASTATUS_END_BF_ST_Field is ATSAM3X8E.Bit; + subtype HSTDMASTATUS_DESC_LDST_Field is ATSAM3X8E.Bit; + subtype HSTDMASTATUS_BUFF_COUNT_Field is ATSAM3X8E.UInt16; -- Host DMA Channel Status Register (n = 1) type HSTDMASTATUS_Register is record -- Channel Enable Status - CHANN_ENB : HSTDMASTATUS1_CHANN_ENB_Field := 16#0#; + CHANN_ENB : HSTDMASTATUS_CHANN_ENB_Field := 16#0#; -- Channel Active Status - CHANN_ACT : HSTDMASTATUS1_CHANN_ACT_Field := 16#0#; + CHANN_ACT : HSTDMASTATUS_CHANN_ACT_Field := 16#0#; -- unspecified Reserved_2_3 : ATSAM3X8E.UInt2 := 16#0#; -- End of Channel Transfer Status - END_TR_ST : HSTDMASTATUS1_END_TR_ST_Field := 16#0#; + END_TR_ST : HSTDMASTATUS_END_TR_ST_Field := 16#0#; -- End of Channel Buffer Status - END_BF_ST : HSTDMASTATUS1_END_BF_ST_Field := 16#0#; + END_BF_ST : HSTDMASTATUS_END_BF_ST_Field := 16#0#; -- Descriptor Loaded Status - DESC_LDST : HSTDMASTATUS1_DESC_LDST_Field := 16#0#; + DESC_LDST : HSTDMASTATUS_DESC_LDST_Field := 16#0#; -- unspecified Reserved_7_15 : ATSAM3X8E.UInt9 := 16#0#; -- Buffer Byte Count - BUFF_COUNT : HSTDMASTATUS1_BUFF_COUNT_Field := 16#0#; + BUFF_COUNT : HSTDMASTATUS_BUFF_COUNT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for HSTDMASTATUS_Register use record CHANN_ENB at 0 range 0 .. 0; @@ -3047,108 +2905,102 @@ package ATSAM3X8E.UOTGHS is BUFF_COUNT at 0 range 16 .. 31; end record; - ------------------- - -- CTRL_Register -- - ------------------- - - subtype CTRL_IDTE_Field is ATSAM3X8E.Bit; - subtype CTRL_VBUSTE_Field is ATSAM3X8E.Bit; - subtype CTRL_SRPE_Field is ATSAM3X8E.Bit; - subtype CTRL_VBERRE_Field is ATSAM3X8E.Bit; - subtype CTRL_BCERRE_Field is ATSAM3X8E.Bit; - subtype CTRL_ROLEEXE_Field is ATSAM3X8E.Bit; - subtype CTRL_HNPERRE_Field is ATSAM3X8E.Bit; - subtype CTRL_STOE_Field is ATSAM3X8E.Bit; - subtype CTRL_VBUSHWC_Field is ATSAM3X8E.Bit; - subtype CTRL_SRPSEL_Field is ATSAM3X8E.Bit; - subtype CTRL_SRPREQ_Field is ATSAM3X8E.Bit; - subtype CTRL_HNPREQ_Field is ATSAM3X8E.Bit; - subtype CTRL_OTGPADE_Field is ATSAM3X8E.Bit; - subtype CTRL_VBUSPO_Field is ATSAM3X8E.Bit; - subtype CTRL_FRZCLK_Field is ATSAM3X8E.Bit; - subtype CTRL_USBE_Field is ATSAM3X8E.Bit; - subtype CTRL_TIMVALUE_Field is ATSAM3X8E.UInt2; - subtype CTRL_TIMPAGE_Field is ATSAM3X8E.UInt2; - subtype CTRL_UNLOCK_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_IDTE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_VBUSTE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_SRPE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_VBERRE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_BCERRE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_ROLEEXE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_HNPERRE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_STOE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_VBUSHWC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_SRPSEL_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_SRPREQ_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_HNPREQ_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_OTGPADE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_VBUSPO_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_FRZCLK_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_USBE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_CTRL_TIMVALUE_Field is ATSAM3X8E.UInt2; + subtype UOTGHS_CTRL_TIMPAGE_Field is ATSAM3X8E.UInt2; + subtype UOTGHS_CTRL_UNLOCK_Field is ATSAM3X8E.Bit; -- UOTGID Pin Enable - type UIDE_Field is - ( - -- The USB mode (device/host) is selected from the UIMOD bit. + type CTRL_UIDE_Field is + (-- The USB mode (device/host) is selected from the UIMOD bit. Uimod, -- The USB mode (device/host) is selected from the UOTGID input pin. Uotgid) with Size => 1; - for UIDE_Field use + for CTRL_UIDE_Field use (Uimod => 0, Uotgid => 1); -- UOTGHS Mode - type UIMOD_Field is - ( - -- The module is in USB host mode. + type CTRL_UIMOD_Field is + (-- The module is in USB host mode. Host, -- The module is in USB device mode. Device) with Size => 1; - for UIMOD_Field use + for CTRL_UIMOD_Field use (Host => 0, Device => 1); -- General Control Register - type CTRL_Register is record + type UOTGHS_CTRL_Register is record -- ID Transition Interrupt Enable - IDTE : CTRL_IDTE_Field := 16#0#; + IDTE : UOTGHS_CTRL_IDTE_Field := 16#0#; -- VBus Transition Interrupt Enable - VBUSTE : CTRL_VBUSTE_Field := 16#0#; + VBUSTE : UOTGHS_CTRL_VBUSTE_Field := 16#0#; -- SRP Interrupt Enable - SRPE : CTRL_SRPE_Field := 16#0#; + SRPE : UOTGHS_CTRL_SRPE_Field := 16#0#; -- VBus Error Interrupt Enable - VBERRE : CTRL_VBERRE_Field := 16#0#; + VBERRE : UOTGHS_CTRL_VBERRE_Field := 16#0#; -- B-Connection Error Interrupt Enable - BCERRE : CTRL_BCERRE_Field := 16#0#; + BCERRE : UOTGHS_CTRL_BCERRE_Field := 16#0#; -- Role Exchange Interrupt Enable - ROLEEXE : CTRL_ROLEEXE_Field := 16#0#; + ROLEEXE : UOTGHS_CTRL_ROLEEXE_Field := 16#0#; -- HNP Error Interrupt Enable - HNPERRE : CTRL_HNPERRE_Field := 16#0#; + HNPERRE : UOTGHS_CTRL_HNPERRE_Field := 16#0#; -- Suspend Time-Out Interrupt Enable - STOE : CTRL_STOE_Field := 16#0#; + STOE : UOTGHS_CTRL_STOE_Field := 16#0#; -- VBus Hardware Control - VBUSHWC : CTRL_VBUSHWC_Field := 16#0#; + VBUSHWC : UOTGHS_CTRL_VBUSHWC_Field := 16#0#; -- SRP Selection - SRPSEL : CTRL_SRPSEL_Field := 16#0#; + SRPSEL : UOTGHS_CTRL_SRPSEL_Field := 16#0#; -- SRP Request - SRPREQ : CTRL_SRPREQ_Field := 16#0#; + SRPREQ : UOTGHS_CTRL_SRPREQ_Field := 16#0#; -- HNP Request - HNPREQ : CTRL_HNPREQ_Field := 16#0#; + HNPREQ : UOTGHS_CTRL_HNPREQ_Field := 16#0#; -- OTG Pad Enable - OTGPADE : CTRL_OTGPADE_Field := 16#0#; + OTGPADE : UOTGHS_CTRL_OTGPADE_Field := 16#0#; -- VBus Polarity Off - VBUSPO : CTRL_VBUSPO_Field := 16#0#; + VBUSPO : UOTGHS_CTRL_VBUSPO_Field := 16#0#; -- Freeze USB Clock - FRZCLK : CTRL_FRZCLK_Field := 16#1#; + FRZCLK : UOTGHS_CTRL_FRZCLK_Field := 16#1#; -- UOTGHS Enable - USBE : CTRL_USBE_Field := 16#0#; + USBE : UOTGHS_CTRL_USBE_Field := 16#0#; -- Timer Value - TIMVALUE : CTRL_TIMVALUE_Field := 16#0#; + TIMVALUE : UOTGHS_CTRL_TIMVALUE_Field := 16#0#; -- unspecified Reserved_18_19 : ATSAM3X8E.UInt2 := 16#0#; -- Timer Page - TIMPAGE : CTRL_TIMPAGE_Field := 16#0#; + TIMPAGE : UOTGHS_CTRL_TIMPAGE_Field := 16#0#; -- Timer Access Unlock - UNLOCK : CTRL_UNLOCK_Field := 16#0#; + UNLOCK : UOTGHS_CTRL_UNLOCK_Field := 16#0#; -- unspecified Reserved_23_23 : ATSAM3X8E.Bit := 16#0#; -- UOTGID Pin Enable - UIDE : UIDE_Field := Uotgid; + UIDE : CTRL_UIDE_Field := ATSAM3X8E.UOTGHS.Uotgid; -- UOTGHS Mode - UIMOD : UIMOD_Field := Device; + UIMOD : CTRL_UIMOD_Field := ATSAM3X8E.UOTGHS.Device; -- unspecified Reserved_26_31 : ATSAM3X8E.UInt6 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CTRL_Register use record + for UOTGHS_CTRL_Register use record IDTE at 0 range 0 .. 0; VBUSTE at 0 range 1 .. 1; SRPE at 0 range 2 .. 2; @@ -3175,75 +3027,70 @@ package ATSAM3X8E.UOTGHS is Reserved_26_31 at 0 range 26 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR_IDTI_Field is ATSAM3X8E.Bit; - subtype SR_VBUSTI_Field is ATSAM3X8E.Bit; - subtype SR_SRPI_Field is ATSAM3X8E.Bit; - subtype SR_VBERRI_Field is ATSAM3X8E.Bit; - subtype SR_BCERRI_Field is ATSAM3X8E.Bit; - subtype SR_ROLEEXI_Field is ATSAM3X8E.Bit; - subtype SR_HNPERRI_Field is ATSAM3X8E.Bit; - subtype SR_STOI_Field is ATSAM3X8E.Bit; - subtype SR_VBUSRQ_Field is ATSAM3X8E.Bit; - subtype SR_ID_Field is ATSAM3X8E.Bit; - subtype SR_VBUS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_IDTI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_VBUSTI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_SRPI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_VBERRI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_BCERRI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_ROLEEXI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_HNPERRI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_STOI_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_VBUSRQ_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_ID_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_VBUS_Field is ATSAM3X8E.Bit; -- Speed Status - type SPEED_Field is - ( - -- Full-Speed mode + type SR_SPEED_Field is + (-- Full-Speed mode Full_Speed, -- High-Speed mode High_Speed, -- Low-Speed mode Low_Speed) with Size => 2; - for SPEED_Field use + for SR_SPEED_Field use (Full_Speed => 0, High_Speed => 1, Low_Speed => 2); - subtype SR_CLKUSABLE_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SR_CLKUSABLE_Field is ATSAM3X8E.Bit; -- General Status Register - type SR_Register is record + type UOTGHS_SR_Register is record -- Read-only. ID Transition Interrupt - IDTI : SR_IDTI_Field := 16#0#; + IDTI : UOTGHS_SR_IDTI_Field; -- Read-only. VBus Transition Interrupt - VBUSTI : SR_VBUSTI_Field := 16#0#; + VBUSTI : UOTGHS_SR_VBUSTI_Field; -- Read-only. SRP Interrupt - SRPI : SR_SRPI_Field := 16#0#; + SRPI : UOTGHS_SR_SRPI_Field; -- Read-only. VBus Error Interrupt - VBERRI : SR_VBERRI_Field := 16#0#; + VBERRI : UOTGHS_SR_VBERRI_Field; -- Read-only. B-Connection Error Interrupt - BCERRI : SR_BCERRI_Field := 16#0#; + BCERRI : UOTGHS_SR_BCERRI_Field; -- Read-only. Role Exchange Interrupt - ROLEEXI : SR_ROLEEXI_Field := 16#0#; + ROLEEXI : UOTGHS_SR_ROLEEXI_Field; -- Read-only. HNP Error Interrupt - HNPERRI : SR_HNPERRI_Field := 16#0#; + HNPERRI : UOTGHS_SR_HNPERRI_Field; -- Read-only. Suspend Time-Out Interrupt - STOI : SR_STOI_Field := 16#0#; + STOI : UOTGHS_SR_STOI_Field; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit; -- Read-only. VBus Request - VBUSRQ : SR_VBUSRQ_Field := 16#0#; + VBUSRQ : UOTGHS_SR_VBUSRQ_Field; -- Read-only. UOTGID Pin State - ID : SR_ID_Field := 16#1#; + ID : UOTGHS_SR_ID_Field; -- Read-only. VBus Level - VBUS : SR_VBUS_Field := 16#0#; + VBUS : UOTGHS_SR_VBUS_Field; -- Read-only. Speed Status - SPEED : SPEED_Field := Full_Speed; + SPEED : SR_SPEED_Field; -- Read-only. UTMI Clock Usable - CLKUSABLE : SR_CLKUSABLE_Field := 16#0#; + CLKUSABLE : UOTGHS_SR_CLKUSABLE_Field; -- unspecified Reserved_15_31 : ATSAM3X8E.UInt17; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register use record + for UOTGHS_SR_Register use record IDTI at 0 range 0 .. 0; VBUSTI at 0 range 1 .. 1; SRPI at 0 range 2 .. 2; @@ -3261,48 +3108,44 @@ package ATSAM3X8E.UOTGHS is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------ - -- SCR_Register -- - ------------------ - - subtype SCR_IDTIC_Field is ATSAM3X8E.Bit; - subtype SCR_VBUSTIC_Field is ATSAM3X8E.Bit; - subtype SCR_SRPIC_Field is ATSAM3X8E.Bit; - subtype SCR_VBERRIC_Field is ATSAM3X8E.Bit; - subtype SCR_BCERRIC_Field is ATSAM3X8E.Bit; - subtype SCR_ROLEEXIC_Field is ATSAM3X8E.Bit; - subtype SCR_HNPERRIC_Field is ATSAM3X8E.Bit; - subtype SCR_STOIC_Field is ATSAM3X8E.Bit; - subtype SCR_VBUSRQC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_IDTIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_VBUSTIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_SRPIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_VBERRIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_BCERRIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_ROLEEXIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_HNPERRIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_STOIC_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SCR_VBUSRQC_Field is ATSAM3X8E.Bit; -- General Status Clear Register - type SCR_Register is record + type UOTGHS_SCR_Register is record -- Write-only. ID Transition Interrupt Clear - IDTIC : SCR_IDTIC_Field := 16#0#; + IDTIC : UOTGHS_SCR_IDTIC_Field := 16#0#; -- Write-only. VBus Transition Interrupt Clear - VBUSTIC : SCR_VBUSTIC_Field := 16#0#; + VBUSTIC : UOTGHS_SCR_VBUSTIC_Field := 16#0#; -- Write-only. SRP Interrupt Clear - SRPIC : SCR_SRPIC_Field := 16#0#; + SRPIC : UOTGHS_SCR_SRPIC_Field := 16#0#; -- Write-only. VBus Error Interrupt Clear - VBERRIC : SCR_VBERRIC_Field := 16#0#; + VBERRIC : UOTGHS_SCR_VBERRIC_Field := 16#0#; -- Write-only. B-Connection Error Interrupt Clear - BCERRIC : SCR_BCERRIC_Field := 16#0#; + BCERRIC : UOTGHS_SCR_BCERRIC_Field := 16#0#; -- Write-only. Role Exchange Interrupt Clear - ROLEEXIC : SCR_ROLEEXIC_Field := 16#0#; + ROLEEXIC : UOTGHS_SCR_ROLEEXIC_Field := 16#0#; -- Write-only. HNP Error Interrupt Clear - HNPERRIC : SCR_HNPERRIC_Field := 16#0#; + HNPERRIC : UOTGHS_SCR_HNPERRIC_Field := 16#0#; -- Write-only. Suspend Time-Out Interrupt Clear - STOIC : SCR_STOIC_Field := 16#0#; + STOIC : UOTGHS_SCR_STOIC_Field := 16#0#; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit := 16#0#; -- Write-only. VBus Request Clear - VBUSRQC : SCR_VBUSRQC_Field := 16#0#; + VBUSRQC : UOTGHS_SCR_VBUSRQC_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SCR_Register use record + for UOTGHS_SCR_Register use record IDTIC at 0 range 0 .. 0; VBUSTIC at 0 range 1 .. 1; SRPIC at 0 range 2 .. 2; @@ -3316,48 +3159,44 @@ package ATSAM3X8E.UOTGHS is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------ - -- SFR_Register -- - ------------------ - - subtype SFR_IDTIS_Field is ATSAM3X8E.Bit; - subtype SFR_VBUSTIS_Field is ATSAM3X8E.Bit; - subtype SFR_SRPIS_Field is ATSAM3X8E.Bit; - subtype SFR_VBERRIS_Field is ATSAM3X8E.Bit; - subtype SFR_BCERRIS_Field is ATSAM3X8E.Bit; - subtype SFR_ROLEEXIS_Field is ATSAM3X8E.Bit; - subtype SFR_HNPERRIS_Field is ATSAM3X8E.Bit; - subtype SFR_STOIS_Field is ATSAM3X8E.Bit; - subtype SFR_VBUSRQS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_IDTIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_VBUSTIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_SRPIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_VBERRIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_BCERRIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_ROLEEXIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_HNPERRIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_STOIS_Field is ATSAM3X8E.Bit; + subtype UOTGHS_SFR_VBUSRQS_Field is ATSAM3X8E.Bit; -- General Status Set Register - type SFR_Register is record + type UOTGHS_SFR_Register is record -- Write-only. ID Transition Interrupt Set - IDTIS : SFR_IDTIS_Field := 16#0#; + IDTIS : UOTGHS_SFR_IDTIS_Field := 16#0#; -- Write-only. VBus Transition Interrupt Set - VBUSTIS : SFR_VBUSTIS_Field := 16#0#; + VBUSTIS : UOTGHS_SFR_VBUSTIS_Field := 16#0#; -- Write-only. SRP Interrupt Set - SRPIS : SFR_SRPIS_Field := 16#0#; + SRPIS : UOTGHS_SFR_SRPIS_Field := 16#0#; -- Write-only. VBus Error Interrupt Set - VBERRIS : SFR_VBERRIS_Field := 16#0#; + VBERRIS : UOTGHS_SFR_VBERRIS_Field := 16#0#; -- Write-only. B-Connection Error Interrupt Set - BCERRIS : SFR_BCERRIS_Field := 16#0#; + BCERRIS : UOTGHS_SFR_BCERRIS_Field := 16#0#; -- Write-only. Role Exchange Interrupt Set - ROLEEXIS : SFR_ROLEEXIS_Field := 16#0#; + ROLEEXIS : UOTGHS_SFR_ROLEEXIS_Field := 16#0#; -- Write-only. HNP Error Interrupt Set - HNPERRIS : SFR_HNPERRIS_Field := 16#0#; + HNPERRIS : UOTGHS_SFR_HNPERRIS_Field := 16#0#; -- Write-only. Suspend Time-Out Interrupt Set - STOIS : SFR_STOIS_Field := 16#0#; + STOIS : UOTGHS_SFR_STOIS_Field := 16#0#; -- unspecified Reserved_8_8 : ATSAM3X8E.Bit := 16#0#; -- Write-only. VBus Request Set - VBUSRQS : SFR_VBUSRQS_Field := 16#0#; + VBUSRQS : UOTGHS_SFR_VBUSRQS_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SFR_Register use record + for UOTGHS_SFR_Register use record IDTIS at 0 range 0 .. 0; VBUSTIS at 0 range 1 .. 1; SRPIS at 0 range 2 .. 2; @@ -3371,57 +3210,50 @@ package ATSAM3X8E.UOTGHS is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------ - -- FSM_Register -- - ------------------ - -- Dual Role Device State - type DRDSTATE_Field is - ( - -- This is the start state for A-devices (when the ID pin is 0) + type FSM_DRDSTATE_Field is + (-- This is the start state for A-devices (when the ID pin is 0) A_Idlestate, - -- In this state, the A-device waits for the voltage on VBus to rise - -- above the A-device VBus Valid threshold (4.4 V). + -- In this state, the A-device waits for the voltage on VBus to rise above the +-- A-device VBus Valid threshold (4.4 V). A_Wait_Vrise, - -- In this state, the A-device waits for the B-device to signal a - -- connection. + -- In this state, the A-device waits for the B-device to signal a connection. A_Wait_Bcon, - -- In this state, the A-device that operates in Host mode is - -- operational. + -- In this state, the A-device that operates in Host mode is operational. A_Host, -- The A-device operating as a host is in the suspend mode. A_Suspend, -- The A-device operates as a peripheral. A_Peripheral, - -- In this state, the A-device waits for the voltage on VBus to drop - -- below the A-device Session Valid threshold (1.4 V). + -- In this state, the A-device waits for the voltage on VBus to drop below the +-- A-device Session Valid threshold (1.4 V). A_Wait_Vfall, -- In this state, the A-device waits for recovery of the over-current - -- condition that caused it to enter this state. +-- condition that caused it to enter this state. A_Vbus_Err, - -- In this state, the A-device waits for the data USB line to discharge - -- (100 us). + -- In this state, the A-device waits for the data USB line to discharge (100 +-- us). A_Wait_Discharge, -- This is the start state for B-device (when the ID pin is 1). B_Idle, -- In this state, the B-device acts as the peripheral. B_Peripheral, - -- In this state, the B-device is in suspend mode and waits until 3 ms - -- before initiating the HNP protocol if requested. + -- In this state, the B-device is in suspend mode and waits until 3 ms before +-- initiating the HNP protocol if requested. B_Wait_Begin_Hnp, - -- In this state, the B-device waits for the data USB line to discharge - -- (100 us) before becoming Host. + -- In this state, the B-device waits for the data USB line to discharge (100 +-- us) before becoming Host. B_Wait_Discharge, - -- In this state, the B-device waits for the A-device to signal a - -- connect before becoming B-Host. + -- In this state, the B-device waits for the A-device to signal a connect +-- before becoming B-Host. B_Wait_Acon, -- In this state, the B-device acts as the Host. B_Host, -- In this state, the B-device attempts to start a session using the SRP - -- protocol. +-- protocol. B_Srp_Init) with Size => 4; - for DRDSTATE_Field use + for FSM_DRDSTATE_Field use (A_Idlestate => 0, A_Wait_Vrise => 1, A_Wait_Bcon => 2, @@ -3440,15 +3272,15 @@ package ATSAM3X8E.UOTGHS is B_Srp_Init => 15); -- General Finite State Machine Register - type FSM_Register is record + type UOTGHS_FSM_Register is record -- Read-only. Dual Role Device State - DRDSTATE : DRDSTATE_Field := B_Idle; + DRDSTATE : FSM_DRDSTATE_Field; -- unspecified Reserved_4_31 : ATSAM3X8E.UInt28; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FSM_Register use record + for UOTGHS_FSM_Register use record DRDSTATE at 0 range 0 .. 3; Reserved_4_31 at 0 range 4 .. 31; end record; @@ -3460,303 +3292,949 @@ package ATSAM3X8E.UOTGHS is -- USB On-The-Go Interface type UOTGHS_Peripheral is record -- Device General Control Register - DEVCTRL : DEVCTRL_Register; + DEVCTRL : aliased UOTGHS_DEVCTRL_Register; + pragma Volatile_Full_Access (DEVCTRL); -- Device Global Interrupt Status Register - DEVISR : DEVISR_Register; + DEVISR : aliased UOTGHS_DEVISR_Register; + pragma Volatile_Full_Access (DEVISR); -- Device Global Interrupt Clear Register - DEVICR : DEVICR_Register; + DEVICR : aliased UOTGHS_DEVICR_Register; + pragma Volatile_Full_Access (DEVICR); -- Device Global Interrupt Set Register - DEVIFR : DEVIFR_Register; + DEVIFR : aliased UOTGHS_DEVIFR_Register; + pragma Volatile_Full_Access (DEVIFR); -- Device Global Interrupt Mask Register - DEVIMR : DEVIMR_Register; + DEVIMR : aliased UOTGHS_DEVIMR_Register; + pragma Volatile_Full_Access (DEVIMR); -- Device Global Interrupt Disable Register - DEVIDR : DEVIDR_Register; + DEVIDR : aliased UOTGHS_DEVIDR_Register; + pragma Volatile_Full_Access (DEVIDR); -- Device Global Interrupt Enable Register - DEVIER : DEVIER_Register; + DEVIER : aliased UOTGHS_DEVIER_Register; + pragma Volatile_Full_Access (DEVIER); -- Device Endpoint Register - DEVEPT : DEVEPT_Register; + DEVEPT : aliased UOTGHS_DEVEPT_Register; + pragma Volatile_Full_Access (DEVEPT); -- Device Frame Number Register - DEVFNUM : DEVFNUM_Register; + DEVFNUM : aliased UOTGHS_DEVFNUM_Register; + pragma Volatile_Full_Access (DEVFNUM); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_0 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_0); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_1 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_1); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_2 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_2); -- Device Endpoint Configuration Register (n = 0) - DEVEPTCFG : DEVEPTCFG_Registers; + DEVEPTCFG_3 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_3); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_4 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_4); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_5 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_5); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_6 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_6); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_7 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_7); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_8 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_8); + -- Device Endpoint Configuration Register (n = 0) + DEVEPTCFG_9 : aliased UOTGHS_DEVEPTCFG_Register; + pragma Volatile_Full_Access (DEVEPTCFG_9); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_0 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_0); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_1 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_1); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_2 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_2); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_3 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_3); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_4 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_4); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_5 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_5); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_6 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_6); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_7 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_7); + -- Device Endpoint Status Register (n = 0) + DEVEPTISR_8 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_8); -- Device Endpoint Status Register (n = 0) - DEVEPTISR : DEVEPTISR_Registers; + DEVEPTISR_9 : aliased UOTGHS_DEVEPTISR_Register; + pragma Volatile_Full_Access (DEVEPTISR_9); -- Device Endpoint Clear Register (n = 0) - DEVEPTICR : DEVEPTICR_Registers; + DEVEPTICR_0 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_0); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_1 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_1); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_2 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_2); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_3 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_3); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_4 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_4); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_5 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_5); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_6 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_6); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_7 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_7); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_8 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_8); + -- Device Endpoint Clear Register (n = 0) + DEVEPTICR_9 : aliased UOTGHS_DEVEPTICR_Register; + pragma Volatile_Full_Access (DEVEPTICR_9); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_0 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_0); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_1 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_1); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_2 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_2); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_3 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_3); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_4 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_4); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_5 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_5); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_6 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_6); -- Device Endpoint Set Register (n = 0) - DEVEPTIFR : DEVEPTIFR_Registers; + DEVEPTIFR_7 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_7); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_8 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_8); + -- Device Endpoint Set Register (n = 0) + DEVEPTIFR_9 : aliased UOTGHS_DEVEPTIFR_Register; + pragma Volatile_Full_Access (DEVEPTIFR_9); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_0 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_0); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_1 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_1); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_2 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_2); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_3 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_3); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_4 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_4); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_5 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_5); -- Device Endpoint Mask Register (n = 0) - DEVEPTIMR : DEVEPTIMR_Registers; + DEVEPTIMR_6 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_6); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_7 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_7); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_8 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_8); + -- Device Endpoint Mask Register (n = 0) + DEVEPTIMR_9 : aliased UOTGHS_DEVEPTIMR_Register; + pragma Volatile_Full_Access (DEVEPTIMR_9); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_0 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_0); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_1 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_1); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_2 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_2); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_3 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_3); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_4 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_4); -- Device Endpoint Enable Register (n = 0) - DEVEPTIER : DEVEPTIER_Registers; + DEVEPTIER_5 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_5); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_6 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_6); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_7 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_7); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_8 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_8); + -- Device Endpoint Enable Register (n = 0) + DEVEPTIER_9 : aliased UOTGHS_DEVEPTIER_Register; + pragma Volatile_Full_Access (DEVEPTIER_9); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_0 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_0); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_1 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_1); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_2 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_2); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_3 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_3); -- Device Endpoint Disable Register (n = 0) - DEVEPTIDR : DEVEPTIDR_Registers; + DEVEPTIDR_4 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_4); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_5 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_5); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_6 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_6); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_7 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_7); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_8 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_8); + -- Device Endpoint Disable Register (n = 0) + DEVEPTIDR_9 : aliased UOTGHS_DEVEPTIDR_Register; + pragma Volatile_Full_Access (DEVEPTIDR_9); -- Device DMA Channel Next Descriptor Address Register (n = 1) - DEVDMANXTDSC1 : ATSAM3X8E.Word; + DEVDMANXTDSC1 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Address Register (n = 1) - DEVDMAADDRESS1 : ATSAM3X8E.Word; + DEVDMAADDRESS1 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Control Register (n = 1) - DEVDMACONTROL1 : DEVDMACONTROL_Register; + DEVDMACONTROL1 : aliased DEVDMACONTROL_Register; + pragma Volatile_Full_Access (DEVDMACONTROL1); -- Device DMA Channel Status Register (n = 1) - DEVDMASTATUS1 : DEVDMASTATUS_Register; + DEVDMASTATUS1 : aliased DEVDMASTATUS_Register; + pragma Volatile_Full_Access (DEVDMASTATUS1); -- Device DMA Channel Next Descriptor Address Register (n = 2) - DEVDMANXTDSC2 : ATSAM3X8E.Word; + DEVDMANXTDSC2 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Address Register (n = 2) - DEVDMAADDRESS2 : ATSAM3X8E.Word; + DEVDMAADDRESS2 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Control Register (n = 2) - DEVDMACONTROL2 : DEVDMACONTROL_Register; + DEVDMACONTROL2 : aliased DEVDMACONTROL_Register; + pragma Volatile_Full_Access (DEVDMACONTROL2); -- Device DMA Channel Status Register (n = 2) - DEVDMASTATUS2 : DEVDMASTATUS_Register; + DEVDMASTATUS2 : aliased DEVDMASTATUS_Register; + pragma Volatile_Full_Access (DEVDMASTATUS2); -- Device DMA Channel Next Descriptor Address Register (n = 3) - DEVDMANXTDSC3 : ATSAM3X8E.Word; + DEVDMANXTDSC3 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Address Register (n = 3) - DEVDMAADDRESS3 : ATSAM3X8E.Word; + DEVDMAADDRESS3 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Control Register (n = 3) - DEVDMACONTROL3 : DEVDMACONTROL_Register; + DEVDMACONTROL3 : aliased DEVDMACONTROL_Register; + pragma Volatile_Full_Access (DEVDMACONTROL3); -- Device DMA Channel Status Register (n = 3) - DEVDMASTATUS3 : DEVDMASTATUS_Register; + DEVDMASTATUS3 : aliased DEVDMASTATUS_Register; + pragma Volatile_Full_Access (DEVDMASTATUS3); -- Device DMA Channel Next Descriptor Address Register (n = 4) - DEVDMANXTDSC4 : ATSAM3X8E.Word; + DEVDMANXTDSC4 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Address Register (n = 4) - DEVDMAADDRESS4 : ATSAM3X8E.Word; + DEVDMAADDRESS4 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Control Register (n = 4) - DEVDMACONTROL4 : DEVDMACONTROL_Register; + DEVDMACONTROL4 : aliased DEVDMACONTROL_Register; + pragma Volatile_Full_Access (DEVDMACONTROL4); -- Device DMA Channel Status Register (n = 4) - DEVDMASTATUS4 : DEVDMASTATUS_Register; + DEVDMASTATUS4 : aliased DEVDMASTATUS_Register; + pragma Volatile_Full_Access (DEVDMASTATUS4); -- Device DMA Channel Next Descriptor Address Register (n = 5) - DEVDMANXTDSC5 : ATSAM3X8E.Word; + DEVDMANXTDSC5 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Address Register (n = 5) - DEVDMAADDRESS5 : ATSAM3X8E.Word; + DEVDMAADDRESS5 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Control Register (n = 5) - DEVDMACONTROL5 : DEVDMACONTROL_Register; + DEVDMACONTROL5 : aliased DEVDMACONTROL_Register; + pragma Volatile_Full_Access (DEVDMACONTROL5); -- Device DMA Channel Status Register (n = 5) - DEVDMASTATUS5 : DEVDMASTATUS_Register; + DEVDMASTATUS5 : aliased DEVDMASTATUS_Register; + pragma Volatile_Full_Access (DEVDMASTATUS5); -- Device DMA Channel Next Descriptor Address Register (n = 6) - DEVDMANXTDSC6 : ATSAM3X8E.Word; + DEVDMANXTDSC6 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Address Register (n = 6) - DEVDMAADDRESS6 : ATSAM3X8E.Word; + DEVDMAADDRESS6 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Control Register (n = 6) - DEVDMACONTROL6 : DEVDMACONTROL_Register; + DEVDMACONTROL6 : aliased DEVDMACONTROL_Register; + pragma Volatile_Full_Access (DEVDMACONTROL6); -- Device DMA Channel Status Register (n = 6) - DEVDMASTATUS6 : DEVDMASTATUS_Register; + DEVDMASTATUS6 : aliased DEVDMASTATUS_Register; + pragma Volatile_Full_Access (DEVDMASTATUS6); -- Device DMA Channel Next Descriptor Address Register (n = 7) - DEVDMANXTDSC7 : ATSAM3X8E.Word; + DEVDMANXTDSC7 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Address Register (n = 7) - DEVDMAADDRESS7 : ATSAM3X8E.Word; + DEVDMAADDRESS7 : aliased ATSAM3X8E.UInt32; -- Device DMA Channel Control Register (n = 7) - DEVDMACONTROL7 : DEVDMACONTROL_Register; + DEVDMACONTROL7 : aliased DEVDMACONTROL_Register; + pragma Volatile_Full_Access (DEVDMACONTROL7); -- Device DMA Channel Status Register (n = 7) - DEVDMASTATUS7 : DEVDMASTATUS_Register; + DEVDMASTATUS7 : aliased DEVDMASTATUS_Register; + pragma Volatile_Full_Access (DEVDMASTATUS7); -- Host General Control Register - HSTCTRL : HSTCTRL_Register; + HSTCTRL : aliased UOTGHS_HSTCTRL_Register; + pragma Volatile_Full_Access (HSTCTRL); -- Host Global Interrupt Status Register - HSTISR : HSTISR_Register; + HSTISR : aliased UOTGHS_HSTISR_Register; + pragma Volatile_Full_Access (HSTISR); -- Host Global Interrupt Clear Register - HSTICR : HSTICR_Register; + HSTICR : aliased UOTGHS_HSTICR_Register; + pragma Volatile_Full_Access (HSTICR); -- Host Global Interrupt Set Register - HSTIFR : HSTIFR_Register; + HSTIFR : aliased UOTGHS_HSTIFR_Register; + pragma Volatile_Full_Access (HSTIFR); -- Host Global Interrupt Mask Register - HSTIMR : HSTIMR_Register; + HSTIMR : aliased UOTGHS_HSTIMR_Register; + pragma Volatile_Full_Access (HSTIMR); -- Host Global Interrupt Disable Register - HSTIDR : HSTIDR_Register; + HSTIDR : aliased UOTGHS_HSTIDR_Register; + pragma Volatile_Full_Access (HSTIDR); -- Host Global Interrupt Enable Register - HSTIER : HSTIER_Register; + HSTIER : aliased UOTGHS_HSTIER_Register; + pragma Volatile_Full_Access (HSTIER); -- Host Pipe Register - HSTPIP : HSTPIP_Register; + HSTPIP : aliased UOTGHS_HSTPIP_Register; + pragma Volatile_Full_Access (HSTPIP); -- Host Frame Number Register - HSTFNUM : HSTFNUM_Register; + HSTFNUM : aliased UOTGHS_HSTFNUM_Register; + pragma Volatile_Full_Access (HSTFNUM); -- Host Address 1 Register - HSTADDR1 : HSTADDR_Register; + HSTADDR1 : aliased UOTGHS_HSTADDR1_Register; + pragma Volatile_Full_Access (HSTADDR1); -- Host Address 2 Register - HSTADDR2 : HSTADDR_Register; + HSTADDR2 : aliased UOTGHS_HSTADDR2_Register; + pragma Volatile_Full_Access (HSTADDR2); -- Host Address 3 Register - HSTADDR3 : HSTADDR3_Register; + HSTADDR3 : aliased UOTGHS_HSTADDR3_Register; + pragma Volatile_Full_Access (HSTADDR3); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_0 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_0); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_1 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_1); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_2 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_2); -- Host Pipe Configuration Register (n = 0) - HSTPIPCFG : HSTPIPCFG_Registers; + HSTPIPCFG_3 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_3); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_4 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_4); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_5 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_5); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_6 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_6); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_7 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_7); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_8 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_8); + -- Host Pipe Configuration Register (n = 0) + HSTPIPCFG_9 : aliased UOTGHS_HSTPIPCFG_Register; + pragma Volatile_Full_Access (HSTPIPCFG_9); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_0 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_0); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_1 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_1); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_2 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_2); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_3 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_3); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_4 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_4); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_5 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_5); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_6 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_6); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_7 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_7); + -- Host Pipe Status Register (n = 0) + HSTPIPISR_8 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_8); -- Host Pipe Status Register (n = 0) - HSTPIPISR : HSTPIPISR_Registers; + HSTPIPISR_9 : aliased UOTGHS_HSTPIPISR_Register; + pragma Volatile_Full_Access (HSTPIPISR_9); -- Host Pipe Clear Register (n = 0) - HSTPIPICR : HSTPIPICR_Registers; + HSTPIPICR_0 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_0); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_1 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_1); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_2 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_2); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_3 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_3); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_4 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_4); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_5 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_5); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_6 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_6); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_7 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_7); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_8 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_8); + -- Host Pipe Clear Register (n = 0) + HSTPIPICR_9 : aliased UOTGHS_HSTPIPICR_Register; + pragma Volatile_Full_Access (HSTPIPICR_9); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_0 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_0); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_1 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_1); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_2 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_2); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_3 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_3); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_4 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_4); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_5 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_5); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_6 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_6); -- Host Pipe Set Register (n = 0) - HSTPIPIFR : HSTPIPIFR_Registers; + HSTPIPIFR_7 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_7); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_8 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_8); + -- Host Pipe Set Register (n = 0) + HSTPIPIFR_9 : aliased UOTGHS_HSTPIPIFR_Register; + pragma Volatile_Full_Access (HSTPIPIFR_9); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_0 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_0); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_1 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_1); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_2 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_2); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_3 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_3); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_4 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_4); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_5 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_5); -- Host Pipe Mask Register (n = 0) - HSTPIPIMR : HSTPIPIMR_Registers; + HSTPIPIMR_6 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_6); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_7 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_7); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_8 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_8); + -- Host Pipe Mask Register (n = 0) + HSTPIPIMR_9 : aliased UOTGHS_HSTPIPIMR_Register; + pragma Volatile_Full_Access (HSTPIPIMR_9); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_0 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_0); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_1 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_1); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_2 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_2); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_3 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_3); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_4 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_4); -- Host Pipe Enable Register (n = 0) - HSTPIPIER : HSTPIPIER_Registers; + HSTPIPIER_5 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_5); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_6 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_6); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_7 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_7); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_8 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_8); + -- Host Pipe Enable Register (n = 0) + HSTPIPIER_9 : aliased UOTGHS_HSTPIPIER_Register; + pragma Volatile_Full_Access (HSTPIPIER_9); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_0 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_0); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_1 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_1); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_2 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_2); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_3 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_3); -- Host Pipe Disable Register (n = 0) - HSTPIPIDR : HSTPIPIDR_Registers; + HSTPIPIDR_4 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_4); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_5 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_5); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_6 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_6); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_7 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_7); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_8 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_8); + -- Host Pipe Disable Register (n = 0) + HSTPIPIDR_9 : aliased UOTGHS_HSTPIPIDR_Register; + pragma Volatile_Full_Access (HSTPIPIDR_9); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_0 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_0); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_1 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_1); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_2 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_2); -- Host Pipe IN Request Register (n = 0) - HSTPIPINRQ : HSTPIPINRQ_Registers; + HSTPIPINRQ_3 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_3); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_4 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_4); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_5 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_5); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_6 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_6); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_7 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_7); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_8 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_8); + -- Host Pipe IN Request Register (n = 0) + HSTPIPINRQ_9 : aliased UOTGHS_HSTPIPINRQ_Register; + pragma Volatile_Full_Access (HSTPIPINRQ_9); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_0 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_0); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_1 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_1); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_2 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_2); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_3 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_3); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_4 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_4); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_5 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_5); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_6 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_6); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_7 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_7); + -- Host Pipe Error Register (n = 0) + HSTPIPERR_8 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_8); -- Host Pipe Error Register (n = 0) - HSTPIPERR : HSTPIPERR_Registers; + HSTPIPERR_9 : aliased UOTGHS_HSTPIPERR_Register; + pragma Volatile_Full_Access (HSTPIPERR_9); -- Host DMA Channel Next Descriptor Address Register (n = 1) - HSTDMANXTDSC1 : ATSAM3X8E.Word; + HSTDMANXTDSC1 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Address Register (n = 1) - HSTDMAADDRESS1 : ATSAM3X8E.Word; + HSTDMAADDRESS1 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Control Register (n = 1) - HSTDMACONTROL1 : HSTDMACONTROL_Register; + HSTDMACONTROL1 : aliased HSTDMACONTROL_Register; + pragma Volatile_Full_Access (HSTDMACONTROL1); -- Host DMA Channel Status Register (n = 1) - HSTDMASTATUS1 : HSTDMASTATUS_Register; + HSTDMASTATUS1 : aliased HSTDMASTATUS_Register; + pragma Volatile_Full_Access (HSTDMASTATUS1); -- Host DMA Channel Next Descriptor Address Register (n = 2) - HSTDMANXTDSC2 : ATSAM3X8E.Word; + HSTDMANXTDSC2 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Address Register (n = 2) - HSTDMAADDRESS2 : ATSAM3X8E.Word; + HSTDMAADDRESS2 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Control Register (n = 2) - HSTDMACONTROL2 : HSTDMACONTROL_Register; + HSTDMACONTROL2 : aliased HSTDMACONTROL_Register; + pragma Volatile_Full_Access (HSTDMACONTROL2); -- Host DMA Channel Status Register (n = 2) - HSTDMASTATUS2 : HSTDMASTATUS_Register; + HSTDMASTATUS2 : aliased HSTDMASTATUS_Register; + pragma Volatile_Full_Access (HSTDMASTATUS2); -- Host DMA Channel Next Descriptor Address Register (n = 3) - HSTDMANXTDSC3 : ATSAM3X8E.Word; + HSTDMANXTDSC3 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Address Register (n = 3) - HSTDMAADDRESS3 : ATSAM3X8E.Word; + HSTDMAADDRESS3 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Control Register (n = 3) - HSTDMACONTROL3 : HSTDMACONTROL_Register; + HSTDMACONTROL3 : aliased HSTDMACONTROL_Register; + pragma Volatile_Full_Access (HSTDMACONTROL3); -- Host DMA Channel Status Register (n = 3) - HSTDMASTATUS3 : HSTDMASTATUS_Register; + HSTDMASTATUS3 : aliased HSTDMASTATUS_Register; + pragma Volatile_Full_Access (HSTDMASTATUS3); -- Host DMA Channel Next Descriptor Address Register (n = 4) - HSTDMANXTDSC4 : ATSAM3X8E.Word; + HSTDMANXTDSC4 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Address Register (n = 4) - HSTDMAADDRESS4 : ATSAM3X8E.Word; + HSTDMAADDRESS4 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Control Register (n = 4) - HSTDMACONTROL4 : HSTDMACONTROL_Register; + HSTDMACONTROL4 : aliased HSTDMACONTROL_Register; + pragma Volatile_Full_Access (HSTDMACONTROL4); -- Host DMA Channel Status Register (n = 4) - HSTDMASTATUS4 : HSTDMASTATUS_Register; + HSTDMASTATUS4 : aliased HSTDMASTATUS_Register; + pragma Volatile_Full_Access (HSTDMASTATUS4); -- Host DMA Channel Next Descriptor Address Register (n = 5) - HSTDMANXTDSC5 : ATSAM3X8E.Word; + HSTDMANXTDSC5 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Address Register (n = 5) - HSTDMAADDRESS5 : ATSAM3X8E.Word; + HSTDMAADDRESS5 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Control Register (n = 5) - HSTDMACONTROL5 : HSTDMACONTROL_Register; + HSTDMACONTROL5 : aliased HSTDMACONTROL_Register; + pragma Volatile_Full_Access (HSTDMACONTROL5); -- Host DMA Channel Status Register (n = 5) - HSTDMASTATUS5 : HSTDMASTATUS_Register; + HSTDMASTATUS5 : aliased HSTDMASTATUS_Register; + pragma Volatile_Full_Access (HSTDMASTATUS5); -- Host DMA Channel Next Descriptor Address Register (n = 6) - HSTDMANXTDSC6 : ATSAM3X8E.Word; + HSTDMANXTDSC6 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Address Register (n = 6) - HSTDMAADDRESS6 : ATSAM3X8E.Word; + HSTDMAADDRESS6 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Control Register (n = 6) - HSTDMACONTROL6 : HSTDMACONTROL_Register; + HSTDMACONTROL6 : aliased HSTDMACONTROL_Register; + pragma Volatile_Full_Access (HSTDMACONTROL6); -- Host DMA Channel Status Register (n = 6) - HSTDMASTATUS6 : HSTDMASTATUS_Register; + HSTDMASTATUS6 : aliased HSTDMASTATUS_Register; + pragma Volatile_Full_Access (HSTDMASTATUS6); -- Host DMA Channel Next Descriptor Address Register (n = 7) - HSTDMANXTDSC7 : ATSAM3X8E.Word; + HSTDMANXTDSC7 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Address Register (n = 7) - HSTDMAADDRESS7 : ATSAM3X8E.Word; + HSTDMAADDRESS7 : aliased ATSAM3X8E.UInt32; -- Host DMA Channel Control Register (n = 7) - HSTDMACONTROL7 : HSTDMACONTROL_Register; + HSTDMACONTROL7 : aliased HSTDMACONTROL_Register; + pragma Volatile_Full_Access (HSTDMACONTROL7); -- Host DMA Channel Status Register (n = 7) - HSTDMASTATUS7 : HSTDMASTATUS_Register; + HSTDMASTATUS7 : aliased HSTDMASTATUS_Register; + pragma Volatile_Full_Access (HSTDMASTATUS7); -- General Control Register - CTRL : CTRL_Register; + CTRL : aliased UOTGHS_CTRL_Register; + pragma Volatile_Full_Access (CTRL); -- General Status Register - SR : SR_Register; + SR : aliased UOTGHS_SR_Register; + pragma Volatile_Full_Access (SR); -- General Status Clear Register - SCR : SCR_Register; + SCR : aliased UOTGHS_SCR_Register; + pragma Volatile_Full_Access (SCR); -- General Status Set Register - SFR : SFR_Register; + SFR : aliased UOTGHS_SFR_Register; + pragma Volatile_Full_Access (SFR); -- General Finite State Machine Register - FSM : FSM_Register; + FSM : aliased UOTGHS_FSM_Register; + pragma Volatile_Full_Access (FSM); end record with Volatile; for UOTGHS_Peripheral use record - DEVCTRL at 0 range 0 .. 31; - DEVISR at 4 range 0 .. 31; - DEVICR at 8 range 0 .. 31; - DEVIFR at 12 range 0 .. 31; - DEVIMR at 16 range 0 .. 31; - DEVIDR at 20 range 0 .. 31; - DEVIER at 24 range 0 .. 31; - DEVEPT at 28 range 0 .. 31; - DEVFNUM at 32 range 0 .. 31; - DEVEPTCFG at 256 range 0 .. 319; - DEVEPTISR at 304 range 0 .. 319; - DEVEPTICR at 352 range 0 .. 319; - DEVEPTIFR at 400 range 0 .. 319; - DEVEPTIMR at 448 range 0 .. 319; - DEVEPTIER at 496 range 0 .. 319; - DEVEPTIDR at 544 range 0 .. 319; - DEVDMANXTDSC1 at 784 range 0 .. 31; - DEVDMAADDRESS1 at 788 range 0 .. 31; - DEVDMACONTROL1 at 792 range 0 .. 31; - DEVDMASTATUS1 at 796 range 0 .. 31; - DEVDMANXTDSC2 at 800 range 0 .. 31; - DEVDMAADDRESS2 at 804 range 0 .. 31; - DEVDMACONTROL2 at 808 range 0 .. 31; - DEVDMASTATUS2 at 812 range 0 .. 31; - DEVDMANXTDSC3 at 816 range 0 .. 31; - DEVDMAADDRESS3 at 820 range 0 .. 31; - DEVDMACONTROL3 at 824 range 0 .. 31; - DEVDMASTATUS3 at 828 range 0 .. 31; - DEVDMANXTDSC4 at 832 range 0 .. 31; - DEVDMAADDRESS4 at 836 range 0 .. 31; - DEVDMACONTROL4 at 840 range 0 .. 31; - DEVDMASTATUS4 at 844 range 0 .. 31; - DEVDMANXTDSC5 at 848 range 0 .. 31; - DEVDMAADDRESS5 at 852 range 0 .. 31; - DEVDMACONTROL5 at 856 range 0 .. 31; - DEVDMASTATUS5 at 860 range 0 .. 31; - DEVDMANXTDSC6 at 864 range 0 .. 31; - DEVDMAADDRESS6 at 868 range 0 .. 31; - DEVDMACONTROL6 at 872 range 0 .. 31; - DEVDMASTATUS6 at 876 range 0 .. 31; - DEVDMANXTDSC7 at 880 range 0 .. 31; - DEVDMAADDRESS7 at 884 range 0 .. 31; - DEVDMACONTROL7 at 888 range 0 .. 31; - DEVDMASTATUS7 at 892 range 0 .. 31; - HSTCTRL at 1024 range 0 .. 31; - HSTISR at 1028 range 0 .. 31; - HSTICR at 1032 range 0 .. 31; - HSTIFR at 1036 range 0 .. 31; - HSTIMR at 1040 range 0 .. 31; - HSTIDR at 1044 range 0 .. 31; - HSTIER at 1048 range 0 .. 31; - HSTPIP at 1052 range 0 .. 31; - HSTFNUM at 1056 range 0 .. 31; - HSTADDR1 at 1060 range 0 .. 31; - HSTADDR2 at 1064 range 0 .. 31; - HSTADDR3 at 1068 range 0 .. 31; - HSTPIPCFG at 1280 range 0 .. 319; - HSTPIPISR at 1328 range 0 .. 319; - HSTPIPICR at 1376 range 0 .. 319; - HSTPIPIFR at 1424 range 0 .. 319; - HSTPIPIMR at 1472 range 0 .. 319; - HSTPIPIER at 1520 range 0 .. 319; - HSTPIPIDR at 1568 range 0 .. 319; - HSTPIPINRQ at 1616 range 0 .. 319; - HSTPIPERR at 1664 range 0 .. 319; - HSTDMANXTDSC1 at 1808 range 0 .. 31; - HSTDMAADDRESS1 at 1812 range 0 .. 31; - HSTDMACONTROL1 at 1816 range 0 .. 31; - HSTDMASTATUS1 at 1820 range 0 .. 31; - HSTDMANXTDSC2 at 1824 range 0 .. 31; - HSTDMAADDRESS2 at 1828 range 0 .. 31; - HSTDMACONTROL2 at 1832 range 0 .. 31; - HSTDMASTATUS2 at 1836 range 0 .. 31; - HSTDMANXTDSC3 at 1840 range 0 .. 31; - HSTDMAADDRESS3 at 1844 range 0 .. 31; - HSTDMACONTROL3 at 1848 range 0 .. 31; - HSTDMASTATUS3 at 1852 range 0 .. 31; - HSTDMANXTDSC4 at 1856 range 0 .. 31; - HSTDMAADDRESS4 at 1860 range 0 .. 31; - HSTDMACONTROL4 at 1864 range 0 .. 31; - HSTDMASTATUS4 at 1868 range 0 .. 31; - HSTDMANXTDSC5 at 1872 range 0 .. 31; - HSTDMAADDRESS5 at 1876 range 0 .. 31; - HSTDMACONTROL5 at 1880 range 0 .. 31; - HSTDMASTATUS5 at 1884 range 0 .. 31; - HSTDMANXTDSC6 at 1888 range 0 .. 31; - HSTDMAADDRESS6 at 1892 range 0 .. 31; - HSTDMACONTROL6 at 1896 range 0 .. 31; - HSTDMASTATUS6 at 1900 range 0 .. 31; - HSTDMANXTDSC7 at 1904 range 0 .. 31; - HSTDMAADDRESS7 at 1908 range 0 .. 31; - HSTDMACONTROL7 at 1912 range 0 .. 31; - HSTDMASTATUS7 at 1916 range 0 .. 31; - CTRL at 2048 range 0 .. 31; - SR at 2052 range 0 .. 31; - SCR at 2056 range 0 .. 31; - SFR at 2060 range 0 .. 31; - FSM at 2092 range 0 .. 31; + DEVCTRL at 16#0# range 0 .. 31; + DEVISR at 16#4# range 0 .. 31; + DEVICR at 16#8# range 0 .. 31; + DEVIFR at 16#C# range 0 .. 31; + DEVIMR at 16#10# range 0 .. 31; + DEVIDR at 16#14# range 0 .. 31; + DEVIER at 16#18# range 0 .. 31; + DEVEPT at 16#1C# range 0 .. 31; + DEVFNUM at 16#20# range 0 .. 31; + DEVEPTCFG_0 at 16#100# range 0 .. 31; + DEVEPTCFG_1 at 16#104# range 0 .. 31; + DEVEPTCFG_2 at 16#108# range 0 .. 31; + DEVEPTCFG_3 at 16#10C# range 0 .. 31; + DEVEPTCFG_4 at 16#110# range 0 .. 31; + DEVEPTCFG_5 at 16#114# range 0 .. 31; + DEVEPTCFG_6 at 16#118# range 0 .. 31; + DEVEPTCFG_7 at 16#11C# range 0 .. 31; + DEVEPTCFG_8 at 16#120# range 0 .. 31; + DEVEPTCFG_9 at 16#124# range 0 .. 31; + DEVEPTISR_0 at 16#130# range 0 .. 31; + DEVEPTISR_1 at 16#134# range 0 .. 31; + DEVEPTISR_2 at 16#138# range 0 .. 31; + DEVEPTISR_3 at 16#13C# range 0 .. 31; + DEVEPTISR_4 at 16#140# range 0 .. 31; + DEVEPTISR_5 at 16#144# range 0 .. 31; + DEVEPTISR_6 at 16#148# range 0 .. 31; + DEVEPTISR_7 at 16#14C# range 0 .. 31; + DEVEPTISR_8 at 16#150# range 0 .. 31; + DEVEPTISR_9 at 16#154# range 0 .. 31; + DEVEPTICR_0 at 16#160# range 0 .. 31; + DEVEPTICR_1 at 16#164# range 0 .. 31; + DEVEPTICR_2 at 16#168# range 0 .. 31; + DEVEPTICR_3 at 16#16C# range 0 .. 31; + DEVEPTICR_4 at 16#170# range 0 .. 31; + DEVEPTICR_5 at 16#174# range 0 .. 31; + DEVEPTICR_6 at 16#178# range 0 .. 31; + DEVEPTICR_7 at 16#17C# range 0 .. 31; + DEVEPTICR_8 at 16#180# range 0 .. 31; + DEVEPTICR_9 at 16#184# range 0 .. 31; + DEVEPTIFR_0 at 16#190# range 0 .. 31; + DEVEPTIFR_1 at 16#194# range 0 .. 31; + DEVEPTIFR_2 at 16#198# range 0 .. 31; + DEVEPTIFR_3 at 16#19C# range 0 .. 31; + DEVEPTIFR_4 at 16#1A0# range 0 .. 31; + DEVEPTIFR_5 at 16#1A4# range 0 .. 31; + DEVEPTIFR_6 at 16#1A8# range 0 .. 31; + DEVEPTIFR_7 at 16#1AC# range 0 .. 31; + DEVEPTIFR_8 at 16#1B0# range 0 .. 31; + DEVEPTIFR_9 at 16#1B4# range 0 .. 31; + DEVEPTIMR_0 at 16#1C0# range 0 .. 31; + DEVEPTIMR_1 at 16#1C4# range 0 .. 31; + DEVEPTIMR_2 at 16#1C8# range 0 .. 31; + DEVEPTIMR_3 at 16#1CC# range 0 .. 31; + DEVEPTIMR_4 at 16#1D0# range 0 .. 31; + DEVEPTIMR_5 at 16#1D4# range 0 .. 31; + DEVEPTIMR_6 at 16#1D8# range 0 .. 31; + DEVEPTIMR_7 at 16#1DC# range 0 .. 31; + DEVEPTIMR_8 at 16#1E0# range 0 .. 31; + DEVEPTIMR_9 at 16#1E4# range 0 .. 31; + DEVEPTIER_0 at 16#1F0# range 0 .. 31; + DEVEPTIER_1 at 16#1F4# range 0 .. 31; + DEVEPTIER_2 at 16#1F8# range 0 .. 31; + DEVEPTIER_3 at 16#1FC# range 0 .. 31; + DEVEPTIER_4 at 16#200# range 0 .. 31; + DEVEPTIER_5 at 16#204# range 0 .. 31; + DEVEPTIER_6 at 16#208# range 0 .. 31; + DEVEPTIER_7 at 16#20C# range 0 .. 31; + DEVEPTIER_8 at 16#210# range 0 .. 31; + DEVEPTIER_9 at 16#214# range 0 .. 31; + DEVEPTIDR_0 at 16#220# range 0 .. 31; + DEVEPTIDR_1 at 16#224# range 0 .. 31; + DEVEPTIDR_2 at 16#228# range 0 .. 31; + DEVEPTIDR_3 at 16#22C# range 0 .. 31; + DEVEPTIDR_4 at 16#230# range 0 .. 31; + DEVEPTIDR_5 at 16#234# range 0 .. 31; + DEVEPTIDR_6 at 16#238# range 0 .. 31; + DEVEPTIDR_7 at 16#23C# range 0 .. 31; + DEVEPTIDR_8 at 16#240# range 0 .. 31; + DEVEPTIDR_9 at 16#244# range 0 .. 31; + DEVDMANXTDSC1 at 16#310# range 0 .. 31; + DEVDMAADDRESS1 at 16#314# range 0 .. 31; + DEVDMACONTROL1 at 16#318# range 0 .. 31; + DEVDMASTATUS1 at 16#31C# range 0 .. 31; + DEVDMANXTDSC2 at 16#320# range 0 .. 31; + DEVDMAADDRESS2 at 16#324# range 0 .. 31; + DEVDMACONTROL2 at 16#328# range 0 .. 31; + DEVDMASTATUS2 at 16#32C# range 0 .. 31; + DEVDMANXTDSC3 at 16#330# range 0 .. 31; + DEVDMAADDRESS3 at 16#334# range 0 .. 31; + DEVDMACONTROL3 at 16#338# range 0 .. 31; + DEVDMASTATUS3 at 16#33C# range 0 .. 31; + DEVDMANXTDSC4 at 16#340# range 0 .. 31; + DEVDMAADDRESS4 at 16#344# range 0 .. 31; + DEVDMACONTROL4 at 16#348# range 0 .. 31; + DEVDMASTATUS4 at 16#34C# range 0 .. 31; + DEVDMANXTDSC5 at 16#350# range 0 .. 31; + DEVDMAADDRESS5 at 16#354# range 0 .. 31; + DEVDMACONTROL5 at 16#358# range 0 .. 31; + DEVDMASTATUS5 at 16#35C# range 0 .. 31; + DEVDMANXTDSC6 at 16#360# range 0 .. 31; + DEVDMAADDRESS6 at 16#364# range 0 .. 31; + DEVDMACONTROL6 at 16#368# range 0 .. 31; + DEVDMASTATUS6 at 16#36C# range 0 .. 31; + DEVDMANXTDSC7 at 16#370# range 0 .. 31; + DEVDMAADDRESS7 at 16#374# range 0 .. 31; + DEVDMACONTROL7 at 16#378# range 0 .. 31; + DEVDMASTATUS7 at 16#37C# range 0 .. 31; + HSTCTRL at 16#400# range 0 .. 31; + HSTISR at 16#404# range 0 .. 31; + HSTICR at 16#408# range 0 .. 31; + HSTIFR at 16#40C# range 0 .. 31; + HSTIMR at 16#410# range 0 .. 31; + HSTIDR at 16#414# range 0 .. 31; + HSTIER at 16#418# range 0 .. 31; + HSTPIP at 16#41C# range 0 .. 31; + HSTFNUM at 16#420# range 0 .. 31; + HSTADDR1 at 16#424# range 0 .. 31; + HSTADDR2 at 16#428# range 0 .. 31; + HSTADDR3 at 16#42C# range 0 .. 31; + HSTPIPCFG_0 at 16#500# range 0 .. 31; + HSTPIPCFG_1 at 16#504# range 0 .. 31; + HSTPIPCFG_2 at 16#508# range 0 .. 31; + HSTPIPCFG_3 at 16#50C# range 0 .. 31; + HSTPIPCFG_4 at 16#510# range 0 .. 31; + HSTPIPCFG_5 at 16#514# range 0 .. 31; + HSTPIPCFG_6 at 16#518# range 0 .. 31; + HSTPIPCFG_7 at 16#51C# range 0 .. 31; + HSTPIPCFG_8 at 16#520# range 0 .. 31; + HSTPIPCFG_9 at 16#524# range 0 .. 31; + HSTPIPISR_0 at 16#530# range 0 .. 31; + HSTPIPISR_1 at 16#534# range 0 .. 31; + HSTPIPISR_2 at 16#538# range 0 .. 31; + HSTPIPISR_3 at 16#53C# range 0 .. 31; + HSTPIPISR_4 at 16#540# range 0 .. 31; + HSTPIPISR_5 at 16#544# range 0 .. 31; + HSTPIPISR_6 at 16#548# range 0 .. 31; + HSTPIPISR_7 at 16#54C# range 0 .. 31; + HSTPIPISR_8 at 16#550# range 0 .. 31; + HSTPIPISR_9 at 16#554# range 0 .. 31; + HSTPIPICR_0 at 16#560# range 0 .. 31; + HSTPIPICR_1 at 16#564# range 0 .. 31; + HSTPIPICR_2 at 16#568# range 0 .. 31; + HSTPIPICR_3 at 16#56C# range 0 .. 31; + HSTPIPICR_4 at 16#570# range 0 .. 31; + HSTPIPICR_5 at 16#574# range 0 .. 31; + HSTPIPICR_6 at 16#578# range 0 .. 31; + HSTPIPICR_7 at 16#57C# range 0 .. 31; + HSTPIPICR_8 at 16#580# range 0 .. 31; + HSTPIPICR_9 at 16#584# range 0 .. 31; + HSTPIPIFR_0 at 16#590# range 0 .. 31; + HSTPIPIFR_1 at 16#594# range 0 .. 31; + HSTPIPIFR_2 at 16#598# range 0 .. 31; + HSTPIPIFR_3 at 16#59C# range 0 .. 31; + HSTPIPIFR_4 at 16#5A0# range 0 .. 31; + HSTPIPIFR_5 at 16#5A4# range 0 .. 31; + HSTPIPIFR_6 at 16#5A8# range 0 .. 31; + HSTPIPIFR_7 at 16#5AC# range 0 .. 31; + HSTPIPIFR_8 at 16#5B0# range 0 .. 31; + HSTPIPIFR_9 at 16#5B4# range 0 .. 31; + HSTPIPIMR_0 at 16#5C0# range 0 .. 31; + HSTPIPIMR_1 at 16#5C4# range 0 .. 31; + HSTPIPIMR_2 at 16#5C8# range 0 .. 31; + HSTPIPIMR_3 at 16#5CC# range 0 .. 31; + HSTPIPIMR_4 at 16#5D0# range 0 .. 31; + HSTPIPIMR_5 at 16#5D4# range 0 .. 31; + HSTPIPIMR_6 at 16#5D8# range 0 .. 31; + HSTPIPIMR_7 at 16#5DC# range 0 .. 31; + HSTPIPIMR_8 at 16#5E0# range 0 .. 31; + HSTPIPIMR_9 at 16#5E4# range 0 .. 31; + HSTPIPIER_0 at 16#5F0# range 0 .. 31; + HSTPIPIER_1 at 16#5F4# range 0 .. 31; + HSTPIPIER_2 at 16#5F8# range 0 .. 31; + HSTPIPIER_3 at 16#5FC# range 0 .. 31; + HSTPIPIER_4 at 16#600# range 0 .. 31; + HSTPIPIER_5 at 16#604# range 0 .. 31; + HSTPIPIER_6 at 16#608# range 0 .. 31; + HSTPIPIER_7 at 16#60C# range 0 .. 31; + HSTPIPIER_8 at 16#610# range 0 .. 31; + HSTPIPIER_9 at 16#614# range 0 .. 31; + HSTPIPIDR_0 at 16#620# range 0 .. 31; + HSTPIPIDR_1 at 16#624# range 0 .. 31; + HSTPIPIDR_2 at 16#628# range 0 .. 31; + HSTPIPIDR_3 at 16#62C# range 0 .. 31; + HSTPIPIDR_4 at 16#630# range 0 .. 31; + HSTPIPIDR_5 at 16#634# range 0 .. 31; + HSTPIPIDR_6 at 16#638# range 0 .. 31; + HSTPIPIDR_7 at 16#63C# range 0 .. 31; + HSTPIPIDR_8 at 16#640# range 0 .. 31; + HSTPIPIDR_9 at 16#644# range 0 .. 31; + HSTPIPINRQ_0 at 16#650# range 0 .. 31; + HSTPIPINRQ_1 at 16#654# range 0 .. 31; + HSTPIPINRQ_2 at 16#658# range 0 .. 31; + HSTPIPINRQ_3 at 16#65C# range 0 .. 31; + HSTPIPINRQ_4 at 16#660# range 0 .. 31; + HSTPIPINRQ_5 at 16#664# range 0 .. 31; + HSTPIPINRQ_6 at 16#668# range 0 .. 31; + HSTPIPINRQ_7 at 16#66C# range 0 .. 31; + HSTPIPINRQ_8 at 16#670# range 0 .. 31; + HSTPIPINRQ_9 at 16#674# range 0 .. 31; + HSTPIPERR_0 at 16#680# range 0 .. 31; + HSTPIPERR_1 at 16#684# range 0 .. 31; + HSTPIPERR_2 at 16#688# range 0 .. 31; + HSTPIPERR_3 at 16#68C# range 0 .. 31; + HSTPIPERR_4 at 16#690# range 0 .. 31; + HSTPIPERR_5 at 16#694# range 0 .. 31; + HSTPIPERR_6 at 16#698# range 0 .. 31; + HSTPIPERR_7 at 16#69C# range 0 .. 31; + HSTPIPERR_8 at 16#6A0# range 0 .. 31; + HSTPIPERR_9 at 16#6A4# range 0 .. 31; + HSTDMANXTDSC1 at 16#710# range 0 .. 31; + HSTDMAADDRESS1 at 16#714# range 0 .. 31; + HSTDMACONTROL1 at 16#718# range 0 .. 31; + HSTDMASTATUS1 at 16#71C# range 0 .. 31; + HSTDMANXTDSC2 at 16#720# range 0 .. 31; + HSTDMAADDRESS2 at 16#724# range 0 .. 31; + HSTDMACONTROL2 at 16#728# range 0 .. 31; + HSTDMASTATUS2 at 16#72C# range 0 .. 31; + HSTDMANXTDSC3 at 16#730# range 0 .. 31; + HSTDMAADDRESS3 at 16#734# range 0 .. 31; + HSTDMACONTROL3 at 16#738# range 0 .. 31; + HSTDMASTATUS3 at 16#73C# range 0 .. 31; + HSTDMANXTDSC4 at 16#740# range 0 .. 31; + HSTDMAADDRESS4 at 16#744# range 0 .. 31; + HSTDMACONTROL4 at 16#748# range 0 .. 31; + HSTDMASTATUS4 at 16#74C# range 0 .. 31; + HSTDMANXTDSC5 at 16#750# range 0 .. 31; + HSTDMAADDRESS5 at 16#754# range 0 .. 31; + HSTDMACONTROL5 at 16#758# range 0 .. 31; + HSTDMASTATUS5 at 16#75C# range 0 .. 31; + HSTDMANXTDSC6 at 16#760# range 0 .. 31; + HSTDMAADDRESS6 at 16#764# range 0 .. 31; + HSTDMACONTROL6 at 16#768# range 0 .. 31; + HSTDMASTATUS6 at 16#76C# range 0 .. 31; + HSTDMANXTDSC7 at 16#770# range 0 .. 31; + HSTDMAADDRESS7 at 16#774# range 0 .. 31; + HSTDMACONTROL7 at 16#778# range 0 .. 31; + HSTDMASTATUS7 at 16#77C# range 0 .. 31; + CTRL at 16#800# range 0 .. 31; + SR at 16#804# range 0 .. 31; + SCR at 16#808# range 0 .. 31; + SFR at 16#80C# range 0 .. 31; + FSM at 16#82C# range 0 .. 31; end record; -- USB On-The-Go Interface diff --git a/arduino-due/atsam3x8e/atsam3x8e-usart.ads b/arduino-due/atsam3x8e/atsam3x8e-usart.ads index 919200b..8379af3 100644 --- a/arduino-due/atsam3x8e/atsam3x8e-usart.ads +++ b/arduino-due/atsam3x8e/atsam3x8e-usart.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,77 +14,73 @@ package ATSAM3X8E.USART is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - - subtype CR_RSTRX_Field is ATSAM3X8E.Bit; - subtype CR_RSTTX_Field is ATSAM3X8E.Bit; - subtype CR_RXEN_Field is ATSAM3X8E.Bit; - subtype CR_RXDIS_Field is ATSAM3X8E.Bit; - subtype CR_TXEN_Field is ATSAM3X8E.Bit; - subtype CR_TXDIS_Field is ATSAM3X8E.Bit; - subtype CR_RSTSTA_Field is ATSAM3X8E.Bit; - subtype CR_STTBRK_Field is ATSAM3X8E.Bit; - subtype CR_STPBRK_Field is ATSAM3X8E.Bit; - subtype CR_STTTO_Field is ATSAM3X8E.Bit; - subtype CR_SENDA_Field is ATSAM3X8E.Bit; - subtype CR_RSTIT_Field is ATSAM3X8E.Bit; - subtype CR_RSTNACK_Field is ATSAM3X8E.Bit; - subtype CR_RETTO_Field is ATSAM3X8E.Bit; - subtype CR_RTSEN_Field is ATSAM3X8E.Bit; - subtype CR_RTSDIS_Field is ATSAM3X8E.Bit; - subtype CR_LINABT_Field is ATSAM3X8E.Bit; - subtype CR_LINWKUP_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RSTRX_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RSTTX_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RXEN_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RXDIS_Field is ATSAM3X8E.Bit; + subtype USART0_CR_TXEN_Field is ATSAM3X8E.Bit; + subtype USART0_CR_TXDIS_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RSTSTA_Field is ATSAM3X8E.Bit; + subtype USART0_CR_STTBRK_Field is ATSAM3X8E.Bit; + subtype USART0_CR_STPBRK_Field is ATSAM3X8E.Bit; + subtype USART0_CR_STTTO_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SENDA_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RSTIT_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RSTNACK_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RETTO_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RTSEN_Field is ATSAM3X8E.Bit; + subtype USART0_CR_RTSDIS_Field is ATSAM3X8E.Bit; + subtype USART0_CR_LINABT_Field is ATSAM3X8E.Bit; + subtype USART0_CR_LINWKUP_Field is ATSAM3X8E.Bit; -- Control Register - type CR_Register is record + type USART0_CR_Register is record -- unspecified Reserved_0_1 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Reset Receiver - RSTRX : CR_RSTRX_Field := 16#0#; + RSTRX : USART0_CR_RSTRX_Field := 16#0#; -- Write-only. Reset Transmitter - RSTTX : CR_RSTTX_Field := 16#0#; + RSTTX : USART0_CR_RSTTX_Field := 16#0#; -- Write-only. Receiver Enable - RXEN : CR_RXEN_Field := 16#0#; + RXEN : USART0_CR_RXEN_Field := 16#0#; -- Write-only. Receiver Disable - RXDIS : CR_RXDIS_Field := 16#0#; + RXDIS : USART0_CR_RXDIS_Field := 16#0#; -- Write-only. Transmitter Enable - TXEN : CR_TXEN_Field := 16#0#; + TXEN : USART0_CR_TXEN_Field := 16#0#; -- Write-only. Transmitter Disable - TXDIS : CR_TXDIS_Field := 16#0#; + TXDIS : USART0_CR_TXDIS_Field := 16#0#; -- Write-only. Reset Status Bits - RSTSTA : CR_RSTSTA_Field := 16#0#; + RSTSTA : USART0_CR_RSTSTA_Field := 16#0#; -- Write-only. Start Break - STTBRK : CR_STTBRK_Field := 16#0#; + STTBRK : USART0_CR_STTBRK_Field := 16#0#; -- Write-only. Stop Break - STPBRK : CR_STPBRK_Field := 16#0#; + STPBRK : USART0_CR_STPBRK_Field := 16#0#; -- Write-only. Start Time-out - STTTO : CR_STTTO_Field := 16#0#; + STTTO : USART0_CR_STTTO_Field := 16#0#; -- Write-only. Send Address - SENDA : CR_SENDA_Field := 16#0#; + SENDA : USART0_CR_SENDA_Field := 16#0#; -- Write-only. Reset Iterations - RSTIT : CR_RSTIT_Field := 16#0#; + RSTIT : USART0_CR_RSTIT_Field := 16#0#; -- Write-only. Reset Non Acknowledge - RSTNACK : CR_RSTNACK_Field := 16#0#; + RSTNACK : USART0_CR_RSTNACK_Field := 16#0#; -- Write-only. Rearm Time-out - RETTO : CR_RETTO_Field := 16#0#; + RETTO : USART0_CR_RETTO_Field := 16#0#; -- unspecified Reserved_16_17 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Request to Send Enable - RTSEN : CR_RTSEN_Field := 16#0#; + RTSEN : USART0_CR_RTSEN_Field := 16#0#; -- Write-only. Request to Send Disable - RTSDIS : CR_RTSDIS_Field := 16#0#; + RTSDIS : USART0_CR_RTSDIS_Field := 16#0#; -- Write-only. Abort LIN Transmission - LINABT : CR_LINABT_Field := 16#0#; + LINABT : USART0_CR_LINABT_Field := 16#0#; -- Write-only. Send LIN Wakeup Signal - LINWKUP : CR_LINWKUP_Field := 16#0#; + LINWKUP : USART0_CR_LINWKUP_Field := 16#0#; -- unspecified Reserved_22_31 : ATSAM3X8E.UInt10 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_Register use record + for USART0_CR_Register use record Reserved_0_1 at 0 range 0 .. 1; RSTRX at 0 range 2 .. 2; RSTTX at 0 range 3 .. 3; @@ -107,50 +104,46 @@ package ATSAM3X8E.USART is Reserved_22_31 at 0 range 22 .. 31; end record; - -------------------------- - -- CR_SPI_MODE_Register -- - -------------------------- - - subtype CR_SPI_MODE_RSTRX_Field is ATSAM3X8E.Bit; - subtype CR_SPI_MODE_RSTTX_Field is ATSAM3X8E.Bit; - subtype CR_SPI_MODE_RXEN_Field is ATSAM3X8E.Bit; - subtype CR_SPI_MODE_RXDIS_Field is ATSAM3X8E.Bit; - subtype CR_SPI_MODE_TXEN_Field is ATSAM3X8E.Bit; - subtype CR_SPI_MODE_TXDIS_Field is ATSAM3X8E.Bit; - subtype CR_SPI_MODE_RSTSTA_Field is ATSAM3X8E.Bit; - subtype CR_SPI_MODE_FCS_Field is ATSAM3X8E.Bit; - subtype CR_SPI_MODE_RCS_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_RSTRX_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_RSTTX_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_RXEN_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_RXDIS_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_TXEN_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_TXDIS_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_RSTSTA_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_FCS_Field is ATSAM3X8E.Bit; + subtype USART0_CR_SPI_MODE_RCS_Field is ATSAM3X8E.Bit; -- Control Register - type CR_SPI_MODE_Register is record + type USART0_CR_SPI_MODE_Register is record -- unspecified Reserved_0_1 : ATSAM3X8E.UInt2 := 16#0#; -- Write-only. Reset Receiver - RSTRX : CR_SPI_MODE_RSTRX_Field := 16#0#; + RSTRX : USART0_CR_SPI_MODE_RSTRX_Field := 16#0#; -- Write-only. Reset Transmitter - RSTTX : CR_SPI_MODE_RSTTX_Field := 16#0#; + RSTTX : USART0_CR_SPI_MODE_RSTTX_Field := 16#0#; -- Write-only. Receiver Enable - RXEN : CR_SPI_MODE_RXEN_Field := 16#0#; + RXEN : USART0_CR_SPI_MODE_RXEN_Field := 16#0#; -- Write-only. Receiver Disable - RXDIS : CR_SPI_MODE_RXDIS_Field := 16#0#; + RXDIS : USART0_CR_SPI_MODE_RXDIS_Field := 16#0#; -- Write-only. Transmitter Enable - TXEN : CR_SPI_MODE_TXEN_Field := 16#0#; + TXEN : USART0_CR_SPI_MODE_TXEN_Field := 16#0#; -- Write-only. Transmitter Disable - TXDIS : CR_SPI_MODE_TXDIS_Field := 16#0#; + TXDIS : USART0_CR_SPI_MODE_TXDIS_Field := 16#0#; -- Write-only. Reset Status Bits - RSTSTA : CR_SPI_MODE_RSTSTA_Field := 16#0#; + RSTSTA : USART0_CR_SPI_MODE_RSTSTA_Field := 16#0#; -- unspecified Reserved_9_17 : ATSAM3X8E.UInt9 := 16#0#; -- Write-only. Force SPI Chip Select - FCS : CR_SPI_MODE_FCS_Field := 16#0#; + FCS : USART0_CR_SPI_MODE_FCS_Field := 16#0#; -- Write-only. Release SPI Chip Select - RCS : CR_SPI_MODE_RCS_Field := 16#0#; + RCS : USART0_CR_SPI_MODE_RCS_Field := 16#0#; -- unspecified Reserved_20_31 : ATSAM3X8E.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR_SPI_MODE_Register use record + for USART0_CR_SPI_MODE_Register use record Reserved_0_1 at 0 range 0 .. 1; RSTRX at 0 range 2 .. 2; RSTTX at 0 range 3 .. 3; @@ -165,14 +158,9 @@ package ATSAM3X8E.USART is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------- - -- MR_Register -- - ----------------- - -- USART Mode of Operation - type USART_MODE_Field is - ( - -- Normal mode + type MR_USART_MODE_Field is + (-- Normal mode Normal, -- RS485 Rs485, @@ -193,7 +181,7 @@ package ATSAM3X8E.USART is -- SPI Slave Spi_Slave) with Size => 4; - for USART_MODE_Field use + for MR_USART_MODE_Field use (Normal => 0, Rs485 => 1, Hw_Handshaking => 2, @@ -206,44 +194,41 @@ package ATSAM3X8E.USART is Spi_Slave => 15); -- Clock Selection - type USCLKS_Field is - ( - -- Master Clock MCK is selected + type MR_USCLKS_Field is + (-- Master Clock MCK is selected Mck, -- Internal Clock Divided MCK/DIV (DIV=8) is selected Div, -- Serial Clock SLK is selected Sck) with Size => 2; - for USCLKS_Field use + for MR_USCLKS_Field use (Mck => 0, Div => 1, Sck => 3); -- Character Length. - type CHRL_Field is - ( - -- Character length is 5 bits - CHRL_Field_5_Bit, + type MR_CHRL_Field is + (-- Character length is 5 bits + Val_5_Bit, -- Character length is 6 bits - CHRL_Field_6_Bit, + Val_6_Bit, -- Character length is 7 bits - CHRL_Field_7_Bit, + Val_7_Bit, -- Character length is 8 bits - CHRL_Field_8_Bit) + Val_8_Bit) with Size => 2; - for CHRL_Field use - (CHRL_Field_5_Bit => 0, - CHRL_Field_6_Bit => 1, - CHRL_Field_7_Bit => 2, - CHRL_Field_8_Bit => 3); + for MR_CHRL_Field use + (Val_5_Bit => 0, + Val_6_Bit => 1, + Val_7_Bit => 2, + Val_8_Bit => 3); - subtype MR_SYNC_Field is ATSAM3X8E.Bit; + subtype USART0_MR_SYNC_Field is ATSAM3X8E.Bit; -- Parity Type - type PAR_Field is - ( - -- Even parity + type MR_PAR_Field is + (-- Even parity Even, -- Odd parity Odd, @@ -256,7 +241,7 @@ package ATSAM3X8E.USART is -- Multidrop mode Multidrop) with Size => 3; - for PAR_Field use + for MR_PAR_Field use (Even => 0, Odd => 1, Space => 2, @@ -265,101 +250,98 @@ package ATSAM3X8E.USART is Multidrop => 6); -- Number of Stop Bits - type NBSTOP_Field is - ( - -- 1 stop bit - NBSTOP_Field_1_Bit, + type MR_NBSTOP_Field is + (-- 1 stop bit + Val_1_Bit, -- 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) - NBSTOP_Field_1_5_Bit, + Val_1_5_Bit, -- 2 stop bits - NBSTOP_Field_2_Bit) + Val_2_Bit) with Size => 2; - for NBSTOP_Field use - (NBSTOP_Field_1_Bit => 0, - NBSTOP_Field_1_5_Bit => 1, - NBSTOP_Field_2_Bit => 2); + for MR_NBSTOP_Field use + (Val_1_Bit => 0, + Val_1_5_Bit => 1, + Val_2_Bit => 2); -- Channel Mode - type CHMODE_Field is - ( - -- Normal Mode + type MR_CHMODE_Field is + (-- Normal Mode Normal, -- Automatic Echo. Receiver input is connected to the TXD pin. Automatic, - -- Local Loopback. Transmitter output is connected to the Receiver - -- Input. + -- Local Loopback. Transmitter output is connected to the Receiver Input. Local_Loopback, -- Remote Loopback. RXD pin is internally connected to the TXD pin. Remote_Loopback) with Size => 2; - for CHMODE_Field use + for MR_CHMODE_Field use (Normal => 0, Automatic => 1, Local_Loopback => 2, Remote_Loopback => 3); - subtype MR_MSBF_Field is ATSAM3X8E.Bit; - subtype MR_MODE9_Field is ATSAM3X8E.Bit; - subtype MR_CLKO_Field is ATSAM3X8E.Bit; - subtype MR_OVER_Field is ATSAM3X8E.Bit; - subtype MR_INACK_Field is ATSAM3X8E.Bit; - subtype MR_DSNACK_Field is ATSAM3X8E.Bit; - subtype MR_VAR_SYNC_Field is ATSAM3X8E.Bit; - subtype MR_INVDATA_Field is ATSAM3X8E.Bit; - subtype MR_MAX_ITERATION_Field is ATSAM3X8E.UInt3; - subtype MR_FILTER_Field is ATSAM3X8E.Bit; - subtype MR_MAN_Field is ATSAM3X8E.Bit; - subtype MR_MODSYNC_Field is ATSAM3X8E.Bit; - subtype MR_ONEBIT_Field is ATSAM3X8E.Bit; + subtype USART0_MR_MSBF_Field is ATSAM3X8E.Bit; + subtype USART0_MR_MODE9_Field is ATSAM3X8E.Bit; + subtype USART0_MR_CLKO_Field is ATSAM3X8E.Bit; + subtype USART0_MR_OVER_Field is ATSAM3X8E.Bit; + subtype USART0_MR_INACK_Field is ATSAM3X8E.Bit; + subtype USART0_MR_DSNACK_Field is ATSAM3X8E.Bit; + subtype USART0_MR_VAR_SYNC_Field is ATSAM3X8E.Bit; + subtype USART0_MR_INVDATA_Field is ATSAM3X8E.Bit; + subtype USART0_MR_MAX_ITERATION_Field is ATSAM3X8E.UInt3; + subtype USART0_MR_FILTER_Field is ATSAM3X8E.Bit; + subtype USART0_MR_MAN_Field is ATSAM3X8E.Bit; + subtype USART0_MR_MODSYNC_Field is ATSAM3X8E.Bit; + subtype USART0_MR_ONEBIT_Field is ATSAM3X8E.Bit; -- Mode Register - type MR_Register is record + type USART0_MR_Register is record -- USART Mode of Operation - USART_MODE : USART_MODE_Field := Normal; + USART_MODE : MR_USART_MODE_Field := ATSAM3X8E.USART.Normal; -- Clock Selection - USCLKS : USCLKS_Field := Mck; + USCLKS : MR_USCLKS_Field := ATSAM3X8E.USART.Mck; -- Character Length. - CHRL : CHRL_Field := CHRL_Field_5_Bit; + CHRL : MR_CHRL_Field := ATSAM3X8E.USART.Val_5_Bit; -- Synchronous Mode Select - SYNC : MR_SYNC_Field := 16#0#; + SYNC : USART0_MR_SYNC_Field := 16#0#; -- Parity Type - PAR : PAR_Field := Even; + PAR : MR_PAR_Field := ATSAM3X8E.USART.Even; -- Number of Stop Bits - NBSTOP : NBSTOP_Field := NBSTOP_Field_1_Bit; + NBSTOP : MR_NBSTOP_Field := ATSAM3X8E.USART.Val_1_Bit; -- Channel Mode - CHMODE : CHMODE_Field := Normal; + CHMODE : MR_CHMODE_Field := ATSAM3X8E.USART.Normal; -- Bit Order - MSBF : MR_MSBF_Field := 16#0#; + MSBF : USART0_MR_MSBF_Field := 16#0#; -- 9-bit Character Length - MODE9 : MR_MODE9_Field := 16#0#; + MODE9 : USART0_MR_MODE9_Field := 16#0#; -- Clock Output Select - CLKO : MR_CLKO_Field := 16#0#; + CLKO : USART0_MR_CLKO_Field := 16#0#; -- Oversampling Mode - OVER : MR_OVER_Field := 16#0#; + OVER : USART0_MR_OVER_Field := 16#0#; -- Inhibit Non Acknowledge - INACK : MR_INACK_Field := 16#0#; + INACK : USART0_MR_INACK_Field := 16#0#; -- Disable Successive NACK - DSNACK : MR_DSNACK_Field := 16#0#; + DSNACK : USART0_MR_DSNACK_Field := 16#0#; -- Variable Synchronization of Command/Data Sync Start Frame Delimiter - VAR_SYNC : MR_VAR_SYNC_Field := 16#0#; + VAR_SYNC : USART0_MR_VAR_SYNC_Field := 16#0#; -- INverted Data - INVDATA : MR_INVDATA_Field := 16#0#; + INVDATA : USART0_MR_INVDATA_Field := 16#0#; -- Maximum Number of Automatic Iteration - MAX_ITERATION : MR_MAX_ITERATION_Field := 16#0#; + MAX_ITERATION : USART0_MR_MAX_ITERATION_Field := 16#0#; -- unspecified Reserved_27_27 : ATSAM3X8E.Bit := 16#0#; -- Infrared Receive Line Filter - FILTER : MR_FILTER_Field := 16#0#; + FILTER : USART0_MR_FILTER_Field := 16#0#; -- Manchester Encoder/Decoder Enable - MAN : MR_MAN_Field := 16#0#; + MAN : USART0_MR_MAN_Field := 16#0#; -- Manchester Synchronization Mode - MODSYNC : MR_MODSYNC_Field := 16#0#; + MODSYNC : USART0_MR_MODSYNC_Field := 16#0#; -- Start Frame Delimiter Selector - ONEBIT : MR_ONEBIT_Field := 16#0#; + ONEBIT : USART0_MR_ONEBIT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_Register use record + for USART0_MR_Register use record USART_MODE at 0 range 0 .. 3; USCLKS at 0 range 4 .. 5; CHRL at 0 range 6 .. 7; @@ -383,65 +365,74 @@ package ATSAM3X8E.USART is ONEBIT at 0 range 31 .. 31; end record; - -------------------------- - -- MR_SPI_MODE_Register -- - -------------------------- - -- USART Mode of Operation - type USART_MODE_Field_1 is - ( - -- Reset value for the field - Usart_Mode_Field_Reset, + type MR_SPI_MODE_USART_MODE_Field is + (-- Reset value for the field + Mr_Spi_Mode_Usart_Mode_Field_Reset, -- SPI Master Spi_Master, -- SPI Slave Spi_Slave) with Size => 4; - for USART_MODE_Field_1 use - (Usart_Mode_Field_Reset => 0, + for MR_SPI_MODE_USART_MODE_Field use + (Mr_Spi_Mode_Usart_Mode_Field_Reset => 0, Spi_Master => 14, Spi_Slave => 15); + -- Clock Selection + type MR_SPI_MODE_USCLKS_Field is + (-- Master Clock MCK is selected + Mck, + -- Internal Clock Divided MCK/DIV (DIV=8) is selected + Div, + -- Serial Clock SLK is selected + Sck) + with Size => 2; + for MR_SPI_MODE_USCLKS_Field use + (Mck => 0, + Div => 1, + Sck => 3); + -- Character Length. - type CHRL_Field_1 is - ( - -- Reset value for the field - Chrl_Field_Reset, + type MR_SPI_MODE_CHRL_Field is + (-- Reset value for the field + Mr_Spi_Mode_Chrl_Field_Reset, -- Character length is 8 bits - CHRL_Field_8_Bit) + Val_8_Bit) with Size => 2; - for CHRL_Field_1 use - (Chrl_Field_Reset => 0, - CHRL_Field_8_Bit => 3); + for MR_SPI_MODE_CHRL_Field use + (Mr_Spi_Mode_Chrl_Field_Reset => 0, + Val_8_Bit => 3); - subtype MR_SPI_MODE_CPHA_Field is ATSAM3X8E.Bit; - subtype MR_SPI_MODE_CPOL_Field is ATSAM3X8E.Bit; - subtype MR_SPI_MODE_WRDBT_Field is ATSAM3X8E.Bit; + subtype USART0_MR_SPI_MODE_CPHA_Field is ATSAM3X8E.Bit; + subtype USART0_MR_SPI_MODE_CPOL_Field is ATSAM3X8E.Bit; + subtype USART0_MR_SPI_MODE_WRDBT_Field is ATSAM3X8E.Bit; -- Mode Register - type MR_SPI_MODE_Register is record + type USART0_MR_SPI_MODE_Register is record -- USART Mode of Operation - USART_MODE : USART_MODE_Field_1 := Usart_Mode_Field_Reset; + USART_MODE : MR_SPI_MODE_USART_MODE_Field := + Mr_Spi_Mode_Usart_Mode_Field_Reset; -- Clock Selection - USCLKS : USCLKS_Field := Mck; + USCLKS : MR_SPI_MODE_USCLKS_Field := ATSAM3X8E.USART.Mck; -- Character Length. - CHRL : CHRL_Field_1 := Chrl_Field_Reset; + CHRL : MR_SPI_MODE_CHRL_Field := Mr_Spi_Mode_Chrl_Field_Reset; -- SPI Clock Phase - CPHA : MR_SPI_MODE_CPHA_Field := 16#0#; + CPHA : USART0_MR_SPI_MODE_CPHA_Field := 16#0#; -- unspecified Reserved_9_15 : ATSAM3X8E.UInt7 := 16#0#; -- SPI Clock Polarity - CPOL : MR_SPI_MODE_CPOL_Field := 16#0#; + CPOL : USART0_MR_SPI_MODE_CPOL_Field := 16#0#; -- unspecified Reserved_17_19 : ATSAM3X8E.UInt3 := 16#0#; -- Wait Read Data Before Transfer - WRDBT : MR_SPI_MODE_WRDBT_Field := 16#0#; + WRDBT : USART0_MR_SPI_MODE_WRDBT_Field := 16#0#; -- unspecified Reserved_21_31 : ATSAM3X8E.UInt11 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MR_SPI_MODE_Register use record + for USART0_MR_SPI_MODE_Register use record USART_MODE at 0 range 0 .. 3; USCLKS at 0 range 4 .. 5; CHRL at 0 range 6 .. 7; @@ -453,75 +444,71 @@ package ATSAM3X8E.USART is Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - - subtype IER_RXRDY_Field is ATSAM3X8E.Bit; - subtype IER_TXRDY_Field is ATSAM3X8E.Bit; - subtype IER_RXBRK_Field is ATSAM3X8E.Bit; - subtype IER_ENDRX_Field is ATSAM3X8E.Bit; - subtype IER_ENDTX_Field is ATSAM3X8E.Bit; - subtype IER_OVRE_Field is ATSAM3X8E.Bit; - subtype IER_FRAME_Field is ATSAM3X8E.Bit; - subtype IER_PARE_Field is ATSAM3X8E.Bit; - subtype IER_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype IER_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IER_ITER_Field is ATSAM3X8E.Bit; - subtype IER_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IER_RXBUFF_Field is ATSAM3X8E.Bit; - subtype IER_NACK_Field is ATSAM3X8E.Bit; - subtype IER_CTSIC_Field is ATSAM3X8E.Bit; - subtype IER_MANE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_RXBRK_Field is ATSAM3X8E.Bit; + subtype USART0_IER_ENDRX_Field is ATSAM3X8E.Bit; + subtype USART0_IER_ENDTX_Field is ATSAM3X8E.Bit; + subtype USART0_IER_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_FRAME_Field is ATSAM3X8E.Bit; + subtype USART0_IER_PARE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype USART0_IER_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_ITER_Field is ATSAM3X8E.Bit; + subtype USART0_IER_TXBUFE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_RXBUFF_Field is ATSAM3X8E.Bit; + subtype USART0_IER_NACK_Field is ATSAM3X8E.Bit; + subtype USART0_IER_CTSIC_Field is ATSAM3X8E.Bit; + subtype USART0_IER_MANE_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_Register is record + type USART0_IER_Register is record -- Write-only. RXRDY Interrupt Enable - RXRDY : IER_RXRDY_Field := 16#0#; + RXRDY : USART0_IER_RXRDY_Field := 16#0#; -- Write-only. TXRDY Interrupt Enable - TXRDY : IER_TXRDY_Field := 16#0#; + TXRDY : USART0_IER_TXRDY_Field := 16#0#; -- Write-only. Receiver Break Interrupt Enable - RXBRK : IER_RXBRK_Field := 16#0#; + RXBRK : USART0_IER_RXBRK_Field := 16#0#; -- Write-only. End of Receive Transfer Interrupt Enable (available in -- all USART modes of operation) - ENDRX : IER_ENDRX_Field := 16#0#; + ENDRX : USART0_IER_ENDRX_Field := 16#0#; -- Write-only. End of Transmit Interrupt Enable (available in all USART -- modes of operation) - ENDTX : IER_ENDTX_Field := 16#0#; + ENDTX : USART0_IER_ENDTX_Field := 16#0#; -- Write-only. Overrun Error Interrupt Enable - OVRE : IER_OVRE_Field := 16#0#; + OVRE : USART0_IER_OVRE_Field := 16#0#; -- Write-only. Framing Error Interrupt Enable - FRAME : IER_FRAME_Field := 16#0#; + FRAME : USART0_IER_FRAME_Field := 16#0#; -- Write-only. Parity Error Interrupt Enable - PARE : IER_PARE_Field := 16#0#; + PARE : USART0_IER_PARE_Field := 16#0#; -- Write-only. Time-out Interrupt Enable - TIMEOUT : IER_TIMEOUT_Field := 16#0#; + TIMEOUT : USART0_IER_TIMEOUT_Field := 16#0#; -- Write-only. TXEMPTY Interrupt Enable - TXEMPTY : IER_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IER_TXEMPTY_Field := 16#0#; -- Write-only. Max number of Repetitions Reached Interrupt Enable - ITER : IER_ITER_Field := 16#0#; + ITER : USART0_IER_ITER_Field := 16#0#; -- Write-only. Buffer Empty Interrupt Enable (available in all USART -- modes of operation) - TXBUFE : IER_TXBUFE_Field := 16#0#; + TXBUFE : USART0_IER_TXBUFE_Field := 16#0#; -- Write-only. Buffer Full Interrupt Enable (available in all USART -- modes of operation) - RXBUFF : IER_RXBUFF_Field := 16#0#; + RXBUFF : USART0_IER_RXBUFF_Field := 16#0#; -- Write-only. Non Acknowledge Interrupt Enable - NACK : IER_NACK_Field := 16#0#; + NACK : USART0_IER_NACK_Field := 16#0#; -- unspecified Reserved_14_18 : ATSAM3X8E.UInt5 := 16#0#; -- Write-only. Clear to Send Input Change Interrupt Enable - CTSIC : IER_CTSIC_Field := 16#0#; + CTSIC : USART0_IER_CTSIC_Field := 16#0#; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Manchester Error Interrupt Enable - MANE : IER_MANE_Field := 16#0#; + MANE : USART0_IER_MANE_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_Register use record + for USART0_IER_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; RXBRK at 0 range 2 .. 2; @@ -543,38 +530,34 @@ package ATSAM3X8E.USART is Reserved_25_31 at 0 range 25 .. 31; end record; - --------------------------- - -- IER_SPI_MODE_Register -- - --------------------------- - - subtype IER_SPI_MODE_RXRDY_Field is ATSAM3X8E.Bit; - subtype IER_SPI_MODE_TXRDY_Field is ATSAM3X8E.Bit; - subtype IER_SPI_MODE_OVRE_Field is ATSAM3X8E.Bit; - subtype IER_SPI_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IER_SPI_MODE_UNRE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_SPI_MODE_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_SPI_MODE_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_SPI_MODE_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_SPI_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_SPI_MODE_UNRE_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_SPI_MODE_Register is record + type USART0_IER_SPI_MODE_Register is record -- Write-only. RXRDY Interrupt Enable - RXRDY : IER_SPI_MODE_RXRDY_Field := 16#0#; + RXRDY : USART0_IER_SPI_MODE_RXRDY_Field := 16#0#; -- Write-only. TXRDY Interrupt Enable - TXRDY : IER_SPI_MODE_TXRDY_Field := 16#0#; + TXRDY : USART0_IER_SPI_MODE_TXRDY_Field := 16#0#; -- unspecified Reserved_2_4 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. Overrun Error Interrupt Enable - OVRE : IER_SPI_MODE_OVRE_Field := 16#0#; + OVRE : USART0_IER_SPI_MODE_OVRE_Field := 16#0#; -- unspecified Reserved_6_8 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. TXEMPTY Interrupt Enable - TXEMPTY : IER_SPI_MODE_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IER_SPI_MODE_TXEMPTY_Field := 16#0#; -- Write-only. SPI Underrun Error Interrupt Enable - UNRE : IER_SPI_MODE_UNRE_Field := 16#0#; + UNRE : USART0_IER_SPI_MODE_UNRE_Field := 16#0#; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_SPI_MODE_Register use record + for USART0_IER_SPI_MODE_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_4 at 0 range 2 .. 4; @@ -585,71 +568,67 @@ package ATSAM3X8E.USART is Reserved_11_31 at 0 range 11 .. 31; end record; - --------------------------- - -- IER_LIN_MODE_Register -- - --------------------------- - - subtype IER_LIN_MODE_RXRDY_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_TXRDY_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_OVRE_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_FRAME_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_PARE_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_LINBK_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_LINID_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_LINTC_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_LINBE_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_LINISFE_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_LINIPE_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_LINCE_Field is ATSAM3X8E.Bit; - subtype IER_LIN_MODE_LINSNRE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_FRAME_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_PARE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_LINBK_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_LINID_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_LINTC_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_LINBE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_LINISFE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_LINIPE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_LINCE_Field is ATSAM3X8E.Bit; + subtype USART0_IER_LIN_MODE_LINSNRE_Field is ATSAM3X8E.Bit; -- Interrupt Enable Register - type IER_LIN_MODE_Register is record + type USART0_IER_LIN_MODE_Register is record -- Write-only. RXRDY Interrupt Enable - RXRDY : IER_LIN_MODE_RXRDY_Field := 16#0#; + RXRDY : USART0_IER_LIN_MODE_RXRDY_Field := 16#0#; -- Write-only. TXRDY Interrupt Enable - TXRDY : IER_LIN_MODE_TXRDY_Field := 16#0#; + TXRDY : USART0_IER_LIN_MODE_TXRDY_Field := 16#0#; -- unspecified Reserved_2_4 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. Overrun Error Interrupt Enable - OVRE : IER_LIN_MODE_OVRE_Field := 16#0#; + OVRE : USART0_IER_LIN_MODE_OVRE_Field := 16#0#; -- Write-only. Framing Error Interrupt Enable - FRAME : IER_LIN_MODE_FRAME_Field := 16#0#; + FRAME : USART0_IER_LIN_MODE_FRAME_Field := 16#0#; -- Write-only. Parity Error Interrupt Enable - PARE : IER_LIN_MODE_PARE_Field := 16#0#; + PARE : USART0_IER_LIN_MODE_PARE_Field := 16#0#; -- Write-only. Time-out Interrupt Enable - TIMEOUT : IER_LIN_MODE_TIMEOUT_Field := 16#0#; + TIMEOUT : USART0_IER_LIN_MODE_TIMEOUT_Field := 16#0#; -- Write-only. TXEMPTY Interrupt Enable - TXEMPTY : IER_LIN_MODE_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IER_LIN_MODE_TXEMPTY_Field := 16#0#; -- unspecified Reserved_10_12 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. LIN Break Sent or LIN Break Received Interrupt Enable - LINBK : IER_LIN_MODE_LINBK_Field := 16#0#; + LINBK : USART0_IER_LIN_MODE_LINBK_Field := 16#0#; -- Write-only. LIN Identifier Sent or LIN Identifier Received Interrupt -- Enable - LINID : IER_LIN_MODE_LINID_Field := 16#0#; + LINID : USART0_IER_LIN_MODE_LINID_Field := 16#0#; -- Write-only. LIN Transfer Completed Interrupt Enable - LINTC : IER_LIN_MODE_LINTC_Field := 16#0#; + LINTC : USART0_IER_LIN_MODE_LINTC_Field := 16#0#; -- unspecified Reserved_16_24 : ATSAM3X8E.UInt9 := 16#0#; -- Write-only. LIN Bus Error Interrupt Enable - LINBE : IER_LIN_MODE_LINBE_Field := 16#0#; + LINBE : USART0_IER_LIN_MODE_LINBE_Field := 16#0#; -- Write-only. LIN Inconsistent Synch Field Error Interrupt Enable - LINISFE : IER_LIN_MODE_LINISFE_Field := 16#0#; + LINISFE : USART0_IER_LIN_MODE_LINISFE_Field := 16#0#; -- Write-only. LIN Identifier Parity Interrupt Enable - LINIPE : IER_LIN_MODE_LINIPE_Field := 16#0#; + LINIPE : USART0_IER_LIN_MODE_LINIPE_Field := 16#0#; -- Write-only. LIN Checksum Error Interrupt Enable - LINCE : IER_LIN_MODE_LINCE_Field := 16#0#; + LINCE : USART0_IER_LIN_MODE_LINCE_Field := 16#0#; -- Write-only. LIN Slave Not Responding Error Interrupt Enable - LINSNRE : IER_LIN_MODE_LINSNRE_Field := 16#0#; + LINSNRE : USART0_IER_LIN_MODE_LINSNRE_Field := 16#0#; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IER_LIN_MODE_Register use record + for USART0_IER_LIN_MODE_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_4 at 0 range 2 .. 4; @@ -671,75 +650,71 @@ package ATSAM3X8E.USART is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - subtype IDR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_RXBRK_Field is ATSAM3X8E.Bit; - subtype IDR_ENDRX_Field is ATSAM3X8E.Bit; - subtype IDR_ENDTX_Field is ATSAM3X8E.Bit; - subtype IDR_OVRE_Field is ATSAM3X8E.Bit; - subtype IDR_FRAME_Field is ATSAM3X8E.Bit; - subtype IDR_PARE_Field is ATSAM3X8E.Bit; - subtype IDR_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype IDR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IDR_ITER_Field is ATSAM3X8E.Bit; - subtype IDR_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IDR_RXBUFF_Field is ATSAM3X8E.Bit; - subtype IDR_NACK_Field is ATSAM3X8E.Bit; - subtype IDR_CTSIC_Field is ATSAM3X8E.Bit; - subtype IDR_MANE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_RXBRK_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_ENDRX_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_ENDTX_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_FRAME_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_PARE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_ITER_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_NACK_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_CTSIC_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_MANE_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_Register is record + type USART0_IDR_Register is record -- Write-only. RXRDY Interrupt Disable - RXRDY : IDR_RXRDY_Field := 16#0#; + RXRDY : USART0_IDR_RXRDY_Field := 16#0#; -- Write-only. TXRDY Interrupt Disable - TXRDY : IDR_TXRDY_Field := 16#0#; + TXRDY : USART0_IDR_TXRDY_Field := 16#0#; -- Write-only. Receiver Break Interrupt Disable - RXBRK : IDR_RXBRK_Field := 16#0#; + RXBRK : USART0_IDR_RXBRK_Field := 16#0#; -- Write-only. End of Receive Transfer Interrupt Disable (available in -- all USART modes of operation) - ENDRX : IDR_ENDRX_Field := 16#0#; + ENDRX : USART0_IDR_ENDRX_Field := 16#0#; -- Write-only. End of Transmit Interrupt Disable (available in all USART -- modes of operation) - ENDTX : IDR_ENDTX_Field := 16#0#; + ENDTX : USART0_IDR_ENDTX_Field := 16#0#; -- Write-only. Overrun Error Interrupt Enable - OVRE : IDR_OVRE_Field := 16#0#; + OVRE : USART0_IDR_OVRE_Field := 16#0#; -- Write-only. Framing Error Interrupt Disable - FRAME : IDR_FRAME_Field := 16#0#; + FRAME : USART0_IDR_FRAME_Field := 16#0#; -- Write-only. Parity Error Interrupt Disable - PARE : IDR_PARE_Field := 16#0#; + PARE : USART0_IDR_PARE_Field := 16#0#; -- Write-only. Time-out Interrupt Disable - TIMEOUT : IDR_TIMEOUT_Field := 16#0#; + TIMEOUT : USART0_IDR_TIMEOUT_Field := 16#0#; -- Write-only. TXEMPTY Interrupt Disable - TXEMPTY : IDR_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IDR_TXEMPTY_Field := 16#0#; -- Write-only. Max number of Repetitions Reached Interrupt Disable - ITER : IDR_ITER_Field := 16#0#; + ITER : USART0_IDR_ITER_Field := 16#0#; -- Write-only. Buffer Empty Interrupt Disable (available in all USART -- modes of operation) - TXBUFE : IDR_TXBUFE_Field := 16#0#; + TXBUFE : USART0_IDR_TXBUFE_Field := 16#0#; -- Write-only. Buffer Full Interrupt Disable (available in all USART -- modes of operation) - RXBUFF : IDR_RXBUFF_Field := 16#0#; + RXBUFF : USART0_IDR_RXBUFF_Field := 16#0#; -- Write-only. Non Acknowledge Interrupt Disable - NACK : IDR_NACK_Field := 16#0#; + NACK : USART0_IDR_NACK_Field := 16#0#; -- unspecified Reserved_14_18 : ATSAM3X8E.UInt5 := 16#0#; -- Write-only. Clear to Send Input Change Interrupt Disable - CTSIC : IDR_CTSIC_Field := 16#0#; + CTSIC : USART0_IDR_CTSIC_Field := 16#0#; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4 := 16#0#; -- Write-only. Manchester Error Interrupt Disable - MANE : IDR_MANE_Field := 16#0#; + MANE : USART0_IDR_MANE_Field := 16#0#; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_Register use record + for USART0_IDR_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; RXBRK at 0 range 2 .. 2; @@ -761,38 +736,34 @@ package ATSAM3X8E.USART is Reserved_25_31 at 0 range 25 .. 31; end record; - --------------------------- - -- IDR_SPI_MODE_Register -- - --------------------------- - - subtype IDR_SPI_MODE_RXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_SPI_MODE_TXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_SPI_MODE_OVRE_Field is ATSAM3X8E.Bit; - subtype IDR_SPI_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IDR_SPI_MODE_UNRE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_SPI_MODE_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_SPI_MODE_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_SPI_MODE_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_SPI_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_SPI_MODE_UNRE_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_SPI_MODE_Register is record + type USART0_IDR_SPI_MODE_Register is record -- Write-only. RXRDY Interrupt Disable - RXRDY : IDR_SPI_MODE_RXRDY_Field := 16#0#; + RXRDY : USART0_IDR_SPI_MODE_RXRDY_Field := 16#0#; -- Write-only. TXRDY Interrupt Disable - TXRDY : IDR_SPI_MODE_TXRDY_Field := 16#0#; + TXRDY : USART0_IDR_SPI_MODE_TXRDY_Field := 16#0#; -- unspecified Reserved_2_4 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. Overrun Error Interrupt Disable - OVRE : IDR_SPI_MODE_OVRE_Field := 16#0#; + OVRE : USART0_IDR_SPI_MODE_OVRE_Field := 16#0#; -- unspecified Reserved_6_8 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. TXEMPTY Interrupt Disable - TXEMPTY : IDR_SPI_MODE_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IDR_SPI_MODE_TXEMPTY_Field := 16#0#; -- Write-only. SPI Underrun Error Interrupt Disable - UNRE : IDR_SPI_MODE_UNRE_Field := 16#0#; + UNRE : USART0_IDR_SPI_MODE_UNRE_Field := 16#0#; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_SPI_MODE_Register use record + for USART0_IDR_SPI_MODE_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_4 at 0 range 2 .. 4; @@ -803,71 +774,67 @@ package ATSAM3X8E.USART is Reserved_11_31 at 0 range 11 .. 31; end record; - --------------------------- - -- IDR_LIN_MODE_Register -- - --------------------------- - - subtype IDR_LIN_MODE_RXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_TXRDY_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_OVRE_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_FRAME_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_PARE_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_LINBK_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_LINID_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_LINTC_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_LINBE_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_LINISFE_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_LINIPE_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_LINCE_Field is ATSAM3X8E.Bit; - subtype IDR_LIN_MODE_LINSNRE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_FRAME_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_PARE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_LINBK_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_LINID_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_LINTC_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_LINBE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_LINISFE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_LINIPE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_LINCE_Field is ATSAM3X8E.Bit; + subtype USART0_IDR_LIN_MODE_LINSNRE_Field is ATSAM3X8E.Bit; -- Interrupt Disable Register - type IDR_LIN_MODE_Register is record + type USART0_IDR_LIN_MODE_Register is record -- Write-only. RXRDY Interrupt Disable - RXRDY : IDR_LIN_MODE_RXRDY_Field := 16#0#; + RXRDY : USART0_IDR_LIN_MODE_RXRDY_Field := 16#0#; -- Write-only. TXRDY Interrupt Disable - TXRDY : IDR_LIN_MODE_TXRDY_Field := 16#0#; + TXRDY : USART0_IDR_LIN_MODE_TXRDY_Field := 16#0#; -- unspecified Reserved_2_4 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. Overrun Error Interrupt Disable - OVRE : IDR_LIN_MODE_OVRE_Field := 16#0#; + OVRE : USART0_IDR_LIN_MODE_OVRE_Field := 16#0#; -- Write-only. Framing Error Interrupt Disable - FRAME : IDR_LIN_MODE_FRAME_Field := 16#0#; + FRAME : USART0_IDR_LIN_MODE_FRAME_Field := 16#0#; -- Write-only. Parity Error Interrupt Disable - PARE : IDR_LIN_MODE_PARE_Field := 16#0#; + PARE : USART0_IDR_LIN_MODE_PARE_Field := 16#0#; -- Write-only. Time-out Interrupt Disable - TIMEOUT : IDR_LIN_MODE_TIMEOUT_Field := 16#0#; + TIMEOUT : USART0_IDR_LIN_MODE_TIMEOUT_Field := 16#0#; -- Write-only. TXEMPTY Interrupt Disable - TXEMPTY : IDR_LIN_MODE_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IDR_LIN_MODE_TXEMPTY_Field := 16#0#; -- unspecified Reserved_10_12 : ATSAM3X8E.UInt3 := 16#0#; -- Write-only. LIN Break Sent or LIN Break Received Interrupt Disable - LINBK : IDR_LIN_MODE_LINBK_Field := 16#0#; + LINBK : USART0_IDR_LIN_MODE_LINBK_Field := 16#0#; -- Write-only. LIN Identifier Sent or LIN Identifier Received Interrupt -- Disable - LINID : IDR_LIN_MODE_LINID_Field := 16#0#; + LINID : USART0_IDR_LIN_MODE_LINID_Field := 16#0#; -- Write-only. LIN Transfer Completed Interrupt Disable - LINTC : IDR_LIN_MODE_LINTC_Field := 16#0#; + LINTC : USART0_IDR_LIN_MODE_LINTC_Field := 16#0#; -- unspecified Reserved_16_24 : ATSAM3X8E.UInt9 := 16#0#; -- Write-only. LIN Bus Error Interrupt Disable - LINBE : IDR_LIN_MODE_LINBE_Field := 16#0#; + LINBE : USART0_IDR_LIN_MODE_LINBE_Field := 16#0#; -- Write-only. LIN Inconsistent Synch Field Error Interrupt Disable - LINISFE : IDR_LIN_MODE_LINISFE_Field := 16#0#; + LINISFE : USART0_IDR_LIN_MODE_LINISFE_Field := 16#0#; -- Write-only. LIN Identifier Parity Interrupt Disable - LINIPE : IDR_LIN_MODE_LINIPE_Field := 16#0#; + LINIPE : USART0_IDR_LIN_MODE_LINIPE_Field := 16#0#; -- Write-only. LIN Checksum Error Interrupt Disable - LINCE : IDR_LIN_MODE_LINCE_Field := 16#0#; + LINCE : USART0_IDR_LIN_MODE_LINCE_Field := 16#0#; -- Write-only. LIN Slave Not Responding Error Interrupt Disable - LINSNRE : IDR_LIN_MODE_LINSNRE_Field := 16#0#; + LINSNRE : USART0_IDR_LIN_MODE_LINSNRE_Field := 16#0#; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IDR_LIN_MODE_Register use record + for USART0_IDR_LIN_MODE_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_4 at 0 range 2 .. 4; @@ -889,75 +856,71 @@ package ATSAM3X8E.USART is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- IMR_Register -- - ------------------ - - subtype IMR_RXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_TXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_RXBRK_Field is ATSAM3X8E.Bit; - subtype IMR_ENDRX_Field is ATSAM3X8E.Bit; - subtype IMR_ENDTX_Field is ATSAM3X8E.Bit; - subtype IMR_OVRE_Field is ATSAM3X8E.Bit; - subtype IMR_FRAME_Field is ATSAM3X8E.Bit; - subtype IMR_PARE_Field is ATSAM3X8E.Bit; - subtype IMR_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype IMR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IMR_ITER_Field is ATSAM3X8E.Bit; - subtype IMR_TXBUFE_Field is ATSAM3X8E.Bit; - subtype IMR_RXBUFF_Field is ATSAM3X8E.Bit; - subtype IMR_NACK_Field is ATSAM3X8E.Bit; - subtype IMR_CTSIC_Field is ATSAM3X8E.Bit; - subtype IMR_MANE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_RXBRK_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_ENDRX_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_ENDTX_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_FRAME_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_PARE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_ITER_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_NACK_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_CTSIC_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_MANE_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_Register is record + type USART0_IMR_Register is record -- Read-only. RXRDY Interrupt Mask - RXRDY : IMR_RXRDY_Field := 16#0#; + RXRDY : USART0_IMR_RXRDY_Field; -- Read-only. TXRDY Interrupt Mask - TXRDY : IMR_TXRDY_Field := 16#0#; + TXRDY : USART0_IMR_TXRDY_Field; -- Read-only. Receiver Break Interrupt Mask - RXBRK : IMR_RXBRK_Field := 16#0#; + RXBRK : USART0_IMR_RXBRK_Field; -- Read-only. End of Receive Transfer Interrupt Mask (available in all -- USART modes of operation) - ENDRX : IMR_ENDRX_Field := 16#0#; + ENDRX : USART0_IMR_ENDRX_Field; -- Read-only. End of Transmit Interrupt Mask (available in all USART -- modes of operation) - ENDTX : IMR_ENDTX_Field := 16#0#; + ENDTX : USART0_IMR_ENDTX_Field; -- Read-only. Overrun Error Interrupt Mask - OVRE : IMR_OVRE_Field := 16#0#; + OVRE : USART0_IMR_OVRE_Field; -- Read-only. Framing Error Interrupt Mask - FRAME : IMR_FRAME_Field := 16#0#; + FRAME : USART0_IMR_FRAME_Field; -- Read-only. Parity Error Interrupt Mask - PARE : IMR_PARE_Field := 16#0#; + PARE : USART0_IMR_PARE_Field; -- Read-only. Time-out Interrupt Mask - TIMEOUT : IMR_TIMEOUT_Field := 16#0#; + TIMEOUT : USART0_IMR_TIMEOUT_Field; -- Read-only. TXEMPTY Interrupt Mask - TXEMPTY : IMR_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IMR_TXEMPTY_Field; -- Read-only. Max number of Repetitions Reached Interrupt Mask - ITER : IMR_ITER_Field := 16#0#; + ITER : USART0_IMR_ITER_Field; -- Read-only. Buffer Empty Interrupt Mask (available in all USART modes -- of operation) - TXBUFE : IMR_TXBUFE_Field := 16#0#; + TXBUFE : USART0_IMR_TXBUFE_Field; -- Read-only. Buffer Full Interrupt Mask (available in all USART modes -- of operation) - RXBUFF : IMR_RXBUFF_Field := 16#0#; + RXBUFF : USART0_IMR_RXBUFF_Field; -- Read-only. Non Acknowledge Interrupt Mask - NACK : IMR_NACK_Field := 16#0#; + NACK : USART0_IMR_NACK_Field; -- unspecified Reserved_14_18 : ATSAM3X8E.UInt5; -- Read-only. Clear to Send Input Change Interrupt Mask - CTSIC : IMR_CTSIC_Field := 16#0#; + CTSIC : USART0_IMR_CTSIC_Field; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4; -- Read-only. Manchester Error Interrupt Mask - MANE : IMR_MANE_Field := 16#0#; + MANE : USART0_IMR_MANE_Field; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_Register use record + for USART0_IMR_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; RXBRK at 0 range 2 .. 2; @@ -979,38 +942,34 @@ package ATSAM3X8E.USART is Reserved_25_31 at 0 range 25 .. 31; end record; - --------------------------- - -- IMR_SPI_MODE_Register -- - --------------------------- - - subtype IMR_SPI_MODE_RXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_SPI_MODE_TXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_SPI_MODE_OVRE_Field is ATSAM3X8E.Bit; - subtype IMR_SPI_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IMR_SPI_MODE_UNRE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_SPI_MODE_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_SPI_MODE_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_SPI_MODE_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_SPI_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_SPI_MODE_UNRE_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_SPI_MODE_Register is record + type USART0_IMR_SPI_MODE_Register is record -- Read-only. RXRDY Interrupt Mask - RXRDY : IMR_SPI_MODE_RXRDY_Field := 16#0#; + RXRDY : USART0_IMR_SPI_MODE_RXRDY_Field; -- Read-only. TXRDY Interrupt Mask - TXRDY : IMR_SPI_MODE_TXRDY_Field := 16#0#; + TXRDY : USART0_IMR_SPI_MODE_TXRDY_Field; -- unspecified Reserved_2_4 : ATSAM3X8E.UInt3; -- Read-only. Overrun Error Interrupt Mask - OVRE : IMR_SPI_MODE_OVRE_Field := 16#0#; + OVRE : USART0_IMR_SPI_MODE_OVRE_Field; -- unspecified Reserved_6_8 : ATSAM3X8E.UInt3; -- Read-only. TXEMPTY Interrupt Mask - TXEMPTY : IMR_SPI_MODE_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IMR_SPI_MODE_TXEMPTY_Field; -- Read-only. SPI Underrun Error Interrupt Mask - UNRE : IMR_SPI_MODE_UNRE_Field := 16#0#; + UNRE : USART0_IMR_SPI_MODE_UNRE_Field; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_SPI_MODE_Register use record + for USART0_IMR_SPI_MODE_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_4 at 0 range 2 .. 4; @@ -1021,71 +980,67 @@ package ATSAM3X8E.USART is Reserved_11_31 at 0 range 11 .. 31; end record; - --------------------------- - -- IMR_LIN_MODE_Register -- - --------------------------- - - subtype IMR_LIN_MODE_RXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_TXRDY_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_OVRE_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_FRAME_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_PARE_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_LINBK_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_LINID_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_LINTC_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_LINBE_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_LINISFE_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_LINIPE_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_LINCE_Field is ATSAM3X8E.Bit; - subtype IMR_LIN_MODE_LINSNRE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_FRAME_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_PARE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_LINBK_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_LINID_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_LINTC_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_LINBE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_LINISFE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_LINIPE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_LINCE_Field is ATSAM3X8E.Bit; + subtype USART0_IMR_LIN_MODE_LINSNRE_Field is ATSAM3X8E.Bit; -- Interrupt Mask Register - type IMR_LIN_MODE_Register is record + type USART0_IMR_LIN_MODE_Register is record -- Read-only. RXRDY Interrupt Mask - RXRDY : IMR_LIN_MODE_RXRDY_Field := 16#0#; + RXRDY : USART0_IMR_LIN_MODE_RXRDY_Field; -- Read-only. TXRDY Interrupt Mask - TXRDY : IMR_LIN_MODE_TXRDY_Field := 16#0#; + TXRDY : USART0_IMR_LIN_MODE_TXRDY_Field; -- unspecified Reserved_2_4 : ATSAM3X8E.UInt3; -- Read-only. Overrun Error Interrupt Mask - OVRE : IMR_LIN_MODE_OVRE_Field := 16#0#; + OVRE : USART0_IMR_LIN_MODE_OVRE_Field; -- Read-only. Framing Error Interrupt Mask - FRAME : IMR_LIN_MODE_FRAME_Field := 16#0#; + FRAME : USART0_IMR_LIN_MODE_FRAME_Field; -- Read-only. Parity Error Interrupt Mask - PARE : IMR_LIN_MODE_PARE_Field := 16#0#; + PARE : USART0_IMR_LIN_MODE_PARE_Field; -- Read-only. Time-out Interrupt Mask - TIMEOUT : IMR_LIN_MODE_TIMEOUT_Field := 16#0#; + TIMEOUT : USART0_IMR_LIN_MODE_TIMEOUT_Field; -- Read-only. TXEMPTY Interrupt Mask - TXEMPTY : IMR_LIN_MODE_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_IMR_LIN_MODE_TXEMPTY_Field; -- unspecified Reserved_10_12 : ATSAM3X8E.UInt3; -- Read-only. LIN Break Sent or LIN Break Received Interrupt Mask - LINBK : IMR_LIN_MODE_LINBK_Field := 16#0#; + LINBK : USART0_IMR_LIN_MODE_LINBK_Field; -- Read-only. LIN Identifier Sent or LIN Identifier Received Interrupt -- Mask - LINID : IMR_LIN_MODE_LINID_Field := 16#0#; + LINID : USART0_IMR_LIN_MODE_LINID_Field; -- Read-only. LIN Transfer Completed Interrupt Mask - LINTC : IMR_LIN_MODE_LINTC_Field := 16#0#; + LINTC : USART0_IMR_LIN_MODE_LINTC_Field; -- unspecified Reserved_16_24 : ATSAM3X8E.UInt9; -- Read-only. LIN Bus Error Interrupt Mask - LINBE : IMR_LIN_MODE_LINBE_Field := 16#0#; + LINBE : USART0_IMR_LIN_MODE_LINBE_Field; -- Read-only. LIN Inconsistent Synch Field Error Interrupt Mask - LINISFE : IMR_LIN_MODE_LINISFE_Field := 16#0#; + LINISFE : USART0_IMR_LIN_MODE_LINISFE_Field; -- Read-only. LIN Identifier Parity Interrupt Mask - LINIPE : IMR_LIN_MODE_LINIPE_Field := 16#0#; + LINIPE : USART0_IMR_LIN_MODE_LINIPE_Field; -- Read-only. LIN Checksum Error Interrupt Mask - LINCE : IMR_LIN_MODE_LINCE_Field := 16#0#; + LINCE : USART0_IMR_LIN_MODE_LINCE_Field; -- Read-only. LIN Slave Not Responding Error Interrupt Mask - LINSNRE : IMR_LIN_MODE_LINSNRE_Field := 16#0#; + LINSNRE : USART0_IMR_LIN_MODE_LINSNRE_Field; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IMR_LIN_MODE_Register use record + for USART0_IMR_LIN_MODE_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_4 at 0 range 2 .. 4; @@ -1107,74 +1062,70 @@ package ATSAM3X8E.USART is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- CSR_Register -- - ------------------ - - subtype CSR_RXRDY_Field is ATSAM3X8E.Bit; - subtype CSR_TXRDY_Field is ATSAM3X8E.Bit; - subtype CSR_RXBRK_Field is ATSAM3X8E.Bit; - subtype CSR_ENDRX_Field is ATSAM3X8E.Bit; - subtype CSR_ENDTX_Field is ATSAM3X8E.Bit; - subtype CSR_OVRE_Field is ATSAM3X8E.Bit; - subtype CSR_FRAME_Field is ATSAM3X8E.Bit; - subtype CSR_PARE_Field is ATSAM3X8E.Bit; - subtype CSR_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype CSR_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype CSR_ITER_Field is ATSAM3X8E.Bit; - subtype CSR_TXBUFE_Field is ATSAM3X8E.Bit; - subtype CSR_RXBUFF_Field is ATSAM3X8E.Bit; - subtype CSR_NACK_Field is ATSAM3X8E.Bit; - subtype CSR_CTSIC_Field is ATSAM3X8E.Bit; - subtype CSR_CTS_Field is ATSAM3X8E.Bit; - subtype CSR_MANERR_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_RXBRK_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_ENDRX_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_ENDTX_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_FRAME_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_PARE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_ITER_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_TXBUFE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_RXBUFF_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_NACK_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_CTSIC_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_CTS_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_MANERR_Field is ATSAM3X8E.Bit; -- Channel Status Register - type CSR_Register is record + type USART0_CSR_Register is record -- Read-only. Receiver Ready - RXRDY : CSR_RXRDY_Field := 16#0#; + RXRDY : USART0_CSR_RXRDY_Field; -- Read-only. Transmitter Ready - TXRDY : CSR_TXRDY_Field := 16#0#; + TXRDY : USART0_CSR_TXRDY_Field; -- Read-only. Break Received/End of Break - RXBRK : CSR_RXBRK_Field := 16#0#; + RXBRK : USART0_CSR_RXBRK_Field; -- Read-only. End of Receiver Transfer - ENDRX : CSR_ENDRX_Field := 16#0#; + ENDRX : USART0_CSR_ENDRX_Field; -- Read-only. End of Transmitter Transfer - ENDTX : CSR_ENDTX_Field := 16#0#; + ENDTX : USART0_CSR_ENDTX_Field; -- Read-only. Overrun Error - OVRE : CSR_OVRE_Field := 16#0#; + OVRE : USART0_CSR_OVRE_Field; -- Read-only. Framing Error - FRAME : CSR_FRAME_Field := 16#0#; + FRAME : USART0_CSR_FRAME_Field; -- Read-only. Parity Error - PARE : CSR_PARE_Field := 16#0#; + PARE : USART0_CSR_PARE_Field; -- Read-only. Receiver Time-out - TIMEOUT : CSR_TIMEOUT_Field := 16#0#; + TIMEOUT : USART0_CSR_TIMEOUT_Field; -- Read-only. Transmitter Empty - TXEMPTY : CSR_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_CSR_TXEMPTY_Field; -- Read-only. Max number of Repetitions Reached - ITER : CSR_ITER_Field := 16#0#; + ITER : USART0_CSR_ITER_Field; -- Read-only. Transmission Buffer Empty - TXBUFE : CSR_TXBUFE_Field := 16#0#; + TXBUFE : USART0_CSR_TXBUFE_Field; -- Read-only. Reception Buffer Full - RXBUFF : CSR_RXBUFF_Field := 16#0#; + RXBUFF : USART0_CSR_RXBUFF_Field; -- Read-only. Non Acknowledge Interrupt - NACK : CSR_NACK_Field := 16#0#; + NACK : USART0_CSR_NACK_Field; -- unspecified Reserved_14_18 : ATSAM3X8E.UInt5; -- Read-only. Clear to Send Input Change Flag - CTSIC : CSR_CTSIC_Field := 16#0#; + CTSIC : USART0_CSR_CTSIC_Field; -- unspecified Reserved_20_22 : ATSAM3X8E.UInt3; -- Read-only. Image of CTS Input - CTS : CSR_CTS_Field := 16#0#; + CTS : USART0_CSR_CTS_Field; -- Read-only. Manchester Error - MANERR : CSR_MANERR_Field := 16#0#; + MANERR : USART0_CSR_MANERR_Field; -- unspecified Reserved_25_31 : ATSAM3X8E.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CSR_Register use record + for USART0_CSR_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; RXBRK at 0 range 2 .. 2; @@ -1197,38 +1148,34 @@ package ATSAM3X8E.USART is Reserved_25_31 at 0 range 25 .. 31; end record; - --------------------------- - -- CSR_SPI_MODE_Register -- - --------------------------- - - subtype CSR_SPI_MODE_RXRDY_Field is ATSAM3X8E.Bit; - subtype CSR_SPI_MODE_TXRDY_Field is ATSAM3X8E.Bit; - subtype CSR_SPI_MODE_OVRE_Field is ATSAM3X8E.Bit; - subtype CSR_SPI_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype CSR_SPI_MODE_UNRE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_SPI_MODE_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_SPI_MODE_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_SPI_MODE_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_SPI_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_SPI_MODE_UNRE_Field is ATSAM3X8E.Bit; -- Channel Status Register - type CSR_SPI_MODE_Register is record + type USART0_CSR_SPI_MODE_Register is record -- Read-only. Receiver Ready - RXRDY : CSR_SPI_MODE_RXRDY_Field := 16#0#; + RXRDY : USART0_CSR_SPI_MODE_RXRDY_Field; -- Read-only. Transmitter Ready - TXRDY : CSR_SPI_MODE_TXRDY_Field := 16#0#; + TXRDY : USART0_CSR_SPI_MODE_TXRDY_Field; -- unspecified Reserved_2_4 : ATSAM3X8E.UInt3; -- Read-only. Overrun Error - OVRE : CSR_SPI_MODE_OVRE_Field := 16#0#; + OVRE : USART0_CSR_SPI_MODE_OVRE_Field; -- unspecified Reserved_6_8 : ATSAM3X8E.UInt3; -- Read-only. Transmitter Empty - TXEMPTY : CSR_SPI_MODE_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_CSR_SPI_MODE_TXEMPTY_Field; -- Read-only. Underrun Error - UNRE : CSR_SPI_MODE_UNRE_Field := 16#0#; + UNRE : USART0_CSR_SPI_MODE_UNRE_Field; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CSR_SPI_MODE_Register use record + for USART0_CSR_SPI_MODE_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_4 at 0 range 2 .. 4; @@ -1239,75 +1186,71 @@ package ATSAM3X8E.USART is Reserved_11_31 at 0 range 11 .. 31; end record; - --------------------------- - -- CSR_LIN_MODE_Register -- - --------------------------- - - subtype CSR_LIN_MODE_RXRDY_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_TXRDY_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_OVRE_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_FRAME_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_PARE_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_TIMEOUT_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINBK_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINID_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINTC_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINBLS_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINBE_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINISFE_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINIPE_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINCE_Field is ATSAM3X8E.Bit; - subtype CSR_LIN_MODE_LINSNRE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_RXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_TXRDY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_OVRE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_FRAME_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_PARE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_TIMEOUT_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_TXEMPTY_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINBK_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINID_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINTC_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINBLS_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINBE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINISFE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINIPE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINCE_Field is ATSAM3X8E.Bit; + subtype USART0_CSR_LIN_MODE_LINSNRE_Field is ATSAM3X8E.Bit; -- Channel Status Register - type CSR_LIN_MODE_Register is record + type USART0_CSR_LIN_MODE_Register is record -- Read-only. Receiver Ready - RXRDY : CSR_LIN_MODE_RXRDY_Field := 16#0#; + RXRDY : USART0_CSR_LIN_MODE_RXRDY_Field; -- Read-only. Transmitter Ready - TXRDY : CSR_LIN_MODE_TXRDY_Field := 16#0#; + TXRDY : USART0_CSR_LIN_MODE_TXRDY_Field; -- unspecified Reserved_2_4 : ATSAM3X8E.UInt3; -- Read-only. Overrun Error - OVRE : CSR_LIN_MODE_OVRE_Field := 16#0#; + OVRE : USART0_CSR_LIN_MODE_OVRE_Field; -- Read-only. Framing Error - FRAME : CSR_LIN_MODE_FRAME_Field := 16#0#; + FRAME : USART0_CSR_LIN_MODE_FRAME_Field; -- Read-only. Parity Error - PARE : CSR_LIN_MODE_PARE_Field := 16#0#; + PARE : USART0_CSR_LIN_MODE_PARE_Field; -- Read-only. Receiver Time-out - TIMEOUT : CSR_LIN_MODE_TIMEOUT_Field := 16#0#; + TIMEOUT : USART0_CSR_LIN_MODE_TIMEOUT_Field; -- Read-only. Transmitter Empty - TXEMPTY : CSR_LIN_MODE_TXEMPTY_Field := 16#0#; + TXEMPTY : USART0_CSR_LIN_MODE_TXEMPTY_Field; -- unspecified Reserved_10_12 : ATSAM3X8E.UInt3; -- Read-only. LIN Break Sent or LIN Break Received - LINBK : CSR_LIN_MODE_LINBK_Field := 16#0#; + LINBK : USART0_CSR_LIN_MODE_LINBK_Field; -- Read-only. LIN Identifier Sent or LIN Identifier Received - LINID : CSR_LIN_MODE_LINID_Field := 16#0#; + LINID : USART0_CSR_LIN_MODE_LINID_Field; -- Read-only. LIN Transfer Completed - LINTC : CSR_LIN_MODE_LINTC_Field := 16#0#; + LINTC : USART0_CSR_LIN_MODE_LINTC_Field; -- unspecified Reserved_16_22 : ATSAM3X8E.UInt7; -- Read-only. LIN Bus Line Status - LINBLS : CSR_LIN_MODE_LINBLS_Field := 16#0#; + LINBLS : USART0_CSR_LIN_MODE_LINBLS_Field; -- unspecified Reserved_24_24 : ATSAM3X8E.Bit; -- Read-only. LIN Bit Error - LINBE : CSR_LIN_MODE_LINBE_Field := 16#0#; + LINBE : USART0_CSR_LIN_MODE_LINBE_Field; -- Read-only. LIN Inconsistent Synch Field Error - LINISFE : CSR_LIN_MODE_LINISFE_Field := 16#0#; + LINISFE : USART0_CSR_LIN_MODE_LINISFE_Field; -- Read-only. LIN Identifier Parity Error - LINIPE : CSR_LIN_MODE_LINIPE_Field := 16#0#; + LINIPE : USART0_CSR_LIN_MODE_LINIPE_Field; -- Read-only. LIN Checksum Error - LINCE : CSR_LIN_MODE_LINCE_Field := 16#0#; + LINCE : USART0_CSR_LIN_MODE_LINCE_Field; -- Read-only. LIN Slave Not Responding Error - LINSNRE : CSR_LIN_MODE_LINSNRE_Field := 16#0#; + LINSNRE : USART0_CSR_LIN_MODE_LINSNRE_Field; -- unspecified Reserved_30_31 : ATSAM3X8E.UInt2; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CSR_LIN_MODE_Register use record + for USART0_CSR_LIN_MODE_Register use record RXRDY at 0 range 0 .. 0; TXRDY at 0 range 1 .. 1; Reserved_2_4 at 0 range 2 .. 4; @@ -1331,194 +1274,157 @@ package ATSAM3X8E.USART is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- RHR_Register -- - ------------------ - - subtype RHR_RXCHR_Field is ATSAM3X8E.UInt9; - subtype RHR_RXSYNH_Field is ATSAM3X8E.Bit; + subtype USART0_RHR_RXCHR_Field is ATSAM3X8E.UInt9; + subtype USART0_RHR_RXSYNH_Field is ATSAM3X8E.Bit; -- Receiver Holding Register - type RHR_Register is record + type USART0_RHR_Register is record -- Read-only. Received Character - RXCHR : RHR_RXCHR_Field := 16#0#; + RXCHR : USART0_RHR_RXCHR_Field; -- unspecified Reserved_9_14 : ATSAM3X8E.UInt6; -- Read-only. Received Sync - RXSYNH : RHR_RXSYNH_Field := 16#0#; + RXSYNH : USART0_RHR_RXSYNH_Field; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short; + Reserved_16_31 : ATSAM3X8E.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RHR_Register use record + for USART0_RHR_Register use record RXCHR at 0 range 0 .. 8; Reserved_9_14 at 0 range 9 .. 14; RXSYNH at 0 range 15 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- THR_Register -- - ------------------ - - subtype THR_TXCHR_Field is ATSAM3X8E.UInt9; - subtype THR_TXSYNH_Field is ATSAM3X8E.Bit; + subtype USART0_THR_TXCHR_Field is ATSAM3X8E.UInt9; + subtype USART0_THR_TXSYNH_Field is ATSAM3X8E.Bit; -- Transmitter Holding Register - type THR_Register is record + type USART0_THR_Register is record -- Write-only. Character to be Transmitted - TXCHR : THR_TXCHR_Field := 16#0#; + TXCHR : USART0_THR_TXCHR_Field := 16#0#; -- unspecified Reserved_9_14 : ATSAM3X8E.UInt6 := 16#0#; -- Write-only. Sync Field to be transmitted - TXSYNH : THR_TXSYNH_Field := 16#0#; + TXSYNH : USART0_THR_TXSYNH_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for THR_Register use record + for USART0_THR_Register use record TXCHR at 0 range 0 .. 8; Reserved_9_14 at 0 range 9 .. 14; TXSYNH at 0 range 15 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- BRGR_Register -- - ------------------- - - subtype BRGR_CD_Field is ATSAM3X8E.Short; - subtype BRGR_FP_Field is ATSAM3X8E.UInt3; + subtype USART0_BRGR_CD_Field is ATSAM3X8E.UInt16; + subtype USART0_BRGR_FP_Field is ATSAM3X8E.UInt3; -- Baud Rate Generator Register - type BRGR_Register is record + type USART0_BRGR_Register is record -- Clock Divider - CD : BRGR_CD_Field := 16#0#; + CD : USART0_BRGR_CD_Field := 16#0#; -- Fractional Part - FP : BRGR_FP_Field := 16#0#; + FP : USART0_BRGR_FP_Field := 16#0#; -- unspecified Reserved_19_31 : ATSAM3X8E.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for BRGR_Register use record + for USART0_BRGR_Register use record CD at 0 range 0 .. 15; FP at 0 range 16 .. 18; Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------- - -- RTOR_Register -- - ------------------- - - subtype RTOR_TO_Field is ATSAM3X8E.UInt17; + subtype USART0_RTOR_TO_Field is ATSAM3X8E.UInt17; -- Receiver Time-out Register - type RTOR_Register is record + type USART0_RTOR_Register is record -- Time-out Value - TO : RTOR_TO_Field := 16#0#; + TO : USART0_RTOR_TO_Field := 16#0#; -- unspecified Reserved_17_31 : ATSAM3X8E.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RTOR_Register use record + for USART0_RTOR_Register use record TO at 0 range 0 .. 16; Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------- - -- TTGR_Register -- - ------------------- - - subtype TTGR_TG_Field is ATSAM3X8E.Byte; + subtype USART0_TTGR_TG_Field is ATSAM3X8E.Byte; -- Transmitter Timeguard Register - type TTGR_Register is record + type USART0_TTGR_Register is record -- Timeguard Value - TG : TTGR_TG_Field := 16#0#; + TG : USART0_TTGR_TG_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TTGR_Register use record + for USART0_TTGR_Register use record TG at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- FIDI_Register -- - ------------------- - - subtype FIDI_FI_DI_RATIO_Field is ATSAM3X8E.UInt11; + subtype USART0_FIDI_FI_DI_RATIO_Field is ATSAM3X8E.UInt11; -- FI DI Ratio Register - type FIDI_Register is record + type USART0_FIDI_Register is record -- FI Over DI Ratio Value - FI_DI_RATIO : FIDI_FI_DI_RATIO_Field := 16#174#; + FI_DI_RATIO : USART0_FIDI_FI_DI_RATIO_Field := 16#174#; -- unspecified Reserved_11_31 : ATSAM3X8E.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FIDI_Register use record + for USART0_FIDI_Register use record FI_DI_RATIO at 0 range 0 .. 10; Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------ - -- NER_Register -- - ------------------ - - subtype NER_NB_ERRORS_Field is ATSAM3X8E.Byte; + subtype USART0_NER_NB_ERRORS_Field is ATSAM3X8E.Byte; -- Number of Errors Register - type NER_Register is record + type USART0_NER_Register is record -- Read-only. Number of Errors - NB_ERRORS : NER_NB_ERRORS_Field := 16#0#; + NB_ERRORS : USART0_NER_NB_ERRORS_Field; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for NER_Register use record + for USART0_NER_Register use record NB_ERRORS at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- IF_Register -- - ----------------- - - subtype IF_IRDA_FILTER_Field is ATSAM3X8E.Byte; + subtype USART0_IF_IRDA_FILTER_Field is ATSAM3X8E.Byte; -- IrDA Filter Register - type IF_Register is record + type USART0_IF_Register is record -- IrDA Filter - IRDA_FILTER : IF_IRDA_FILTER_Field := 16#0#; + IRDA_FILTER : USART0_IF_IRDA_FILTER_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for IF_Register use record + for USART0_IF_Register use record IRDA_FILTER at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- MAN_Register -- - ------------------ - - subtype MAN_TX_PL_Field is ATSAM3X8E.UInt4; + subtype USART0_MAN_TX_PL_Field is ATSAM3X8E.UInt4; -- Transmitter Preamble Pattern - type TX_PP_Field is - ( - -- The preamble is composed of '1's + type MAN_TX_PP_Field is + (-- The preamble is composed of '1's All_One, -- The preamble is composed of '0's All_Zero, @@ -1527,19 +1433,18 @@ package ATSAM3X8E.USART is -- The preamble is composed of '10's One_Zero) with Size => 2; - for TX_PP_Field use + for MAN_TX_PP_Field use (All_One => 0, All_Zero => 1, Zero_One => 2, One_Zero => 3); - subtype MAN_TX_MPOL_Field is ATSAM3X8E.Bit; - subtype MAN_RX_PL_Field is ATSAM3X8E.UInt4; + subtype USART0_MAN_TX_MPOL_Field is ATSAM3X8E.Bit; + subtype USART0_MAN_RX_PL_Field is ATSAM3X8E.UInt4; -- Receiver Preamble Pattern detected - type RX_PP_Field is - ( - -- The preamble is composed of '1's + type MAN_RX_PP_Field is + (-- The preamble is composed of '1's All_One, -- The preamble is composed of '0's All_Zero, @@ -1548,50 +1453,50 @@ package ATSAM3X8E.USART is -- The preamble is composed of '10's One_Zero) with Size => 2; - for RX_PP_Field use + for MAN_RX_PP_Field use (All_One => 0, All_Zero => 1, Zero_One => 2, One_Zero => 3); - subtype MAN_RX_MPOL_Field is ATSAM3X8E.Bit; - subtype MAN_ONE_Field is ATSAM3X8E.Bit; - subtype MAN_DRIFT_Field is ATSAM3X8E.Bit; + subtype USART0_MAN_RX_MPOL_Field is ATSAM3X8E.Bit; + subtype USART0_MAN_ONE_Field is ATSAM3X8E.Bit; + subtype USART0_MAN_DRIFT_Field is ATSAM3X8E.Bit; -- Manchester Encoder Decoder Register - type MAN_Register is record + type USART0_MAN_Register is record -- Transmitter Preamble Length - TX_PL : MAN_TX_PL_Field := 16#4#; + TX_PL : USART0_MAN_TX_PL_Field := 16#4#; -- unspecified Reserved_4_7 : ATSAM3X8E.UInt4 := 16#0#; -- Transmitter Preamble Pattern - TX_PP : TX_PP_Field := All_One; + TX_PP : MAN_TX_PP_Field := ATSAM3X8E.USART.All_One; -- unspecified Reserved_10_11 : ATSAM3X8E.UInt2 := 16#0#; -- Transmitter Manchester Polarity - TX_MPOL : MAN_TX_MPOL_Field := 16#1#; + TX_MPOL : USART0_MAN_TX_MPOL_Field := 16#1#; -- unspecified Reserved_13_15 : ATSAM3X8E.UInt3 := 16#0#; -- Receiver Preamble Length - RX_PL : MAN_RX_PL_Field := 16#1#; + RX_PL : USART0_MAN_RX_PL_Field := 16#1#; -- unspecified Reserved_20_23 : ATSAM3X8E.UInt4 := 16#0#; -- Receiver Preamble Pattern detected - RX_PP : RX_PP_Field := All_One; + RX_PP : MAN_RX_PP_Field := ATSAM3X8E.USART.All_One; -- unspecified Reserved_26_27 : ATSAM3X8E.UInt2 := 16#0#; -- Receiver Manchester Polarity - RX_MPOL : MAN_RX_MPOL_Field := 16#1#; + RX_MPOL : USART0_MAN_RX_MPOL_Field := 16#1#; -- Must Be Set to 1 - ONE : MAN_ONE_Field := 16#1#; + ONE : USART0_MAN_ONE_Field := 16#1#; -- Drift compensation - DRIFT : MAN_DRIFT_Field := 16#0#; + DRIFT : USART0_MAN_DRIFT_Field := 16#0#; -- unspecified Reserved_31_31 : ATSAM3X8E.Bit := 16#1#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MAN_Register use record + for USART0_MAN_Register use record TX_PL at 0 range 0 .. 3; Reserved_4_7 at 0 range 4 .. 7; TX_PP at 0 range 8 .. 9; @@ -1608,60 +1513,55 @@ package ATSAM3X8E.USART is Reserved_31_31 at 0 range 31 .. 31; end record; - -------------------- - -- LINMR_Register -- - -------------------- - -- LIN Node Action - type NACT_Field is - ( - -- The USART transmits the response. + type LINMR_NACT_Field is + (-- The USART transmits the response. Publish, -- The USART receives the response. Subscribe, -- The USART does not transmit and does not receive the response. Ignore) with Size => 2; - for NACT_Field use + for LINMR_NACT_Field use (Publish => 0, Subscribe => 1, Ignore => 2); - subtype LINMR_PARDIS_Field is ATSAM3X8E.Bit; - subtype LINMR_CHKDIS_Field is ATSAM3X8E.Bit; - subtype LINMR_CHKTYP_Field is ATSAM3X8E.Bit; - subtype LINMR_DLM_Field is ATSAM3X8E.Bit; - subtype LINMR_FSDIS_Field is ATSAM3X8E.Bit; - subtype LINMR_WKUPTYP_Field is ATSAM3X8E.Bit; - subtype LINMR_DLC_Field is ATSAM3X8E.Byte; - subtype LINMR_PDCM_Field is ATSAM3X8E.Bit; + subtype USART0_LINMR_PARDIS_Field is ATSAM3X8E.Bit; + subtype USART0_LINMR_CHKDIS_Field is ATSAM3X8E.Bit; + subtype USART0_LINMR_CHKTYP_Field is ATSAM3X8E.Bit; + subtype USART0_LINMR_DLM_Field is ATSAM3X8E.Bit; + subtype USART0_LINMR_FSDIS_Field is ATSAM3X8E.Bit; + subtype USART0_LINMR_WKUPTYP_Field is ATSAM3X8E.Bit; + subtype USART0_LINMR_DLC_Field is ATSAM3X8E.Byte; + subtype USART0_LINMR_PDCM_Field is ATSAM3X8E.Bit; -- LIN Mode Register - type LINMR_Register is record + type USART0_LINMR_Register is record -- LIN Node Action - NACT : NACT_Field := Publish; + NACT : LINMR_NACT_Field := ATSAM3X8E.USART.Publish; -- Parity Disable - PARDIS : LINMR_PARDIS_Field := 16#0#; + PARDIS : USART0_LINMR_PARDIS_Field := 16#0#; -- Checksum Disable - CHKDIS : LINMR_CHKDIS_Field := 16#0#; + CHKDIS : USART0_LINMR_CHKDIS_Field := 16#0#; -- Checksum Type - CHKTYP : LINMR_CHKTYP_Field := 16#0#; + CHKTYP : USART0_LINMR_CHKTYP_Field := 16#0#; -- Data Length Mode - DLM : LINMR_DLM_Field := 16#0#; + DLM : USART0_LINMR_DLM_Field := 16#0#; -- Frame Slot Mode Disable - FSDIS : LINMR_FSDIS_Field := 16#0#; + FSDIS : USART0_LINMR_FSDIS_Field := 16#0#; -- Wakeup Signal Type - WKUPTYP : LINMR_WKUPTYP_Field := 16#0#; + WKUPTYP : USART0_LINMR_WKUPTYP_Field := 16#0#; -- Data Length Control - DLC : LINMR_DLC_Field := 16#0#; + DLC : USART0_LINMR_DLC_Field := 16#0#; -- PDC Mode - PDCM : LINMR_PDCM_Field := 16#0#; + PDCM : USART0_LINMR_PDCM_Field := 16#0#; -- unspecified Reserved_17_31 : ATSAM3X8E.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for LINMR_Register use record + for USART0_LINMR_Register use record NACT at 0 range 0 .. 1; PARDIS at 0 range 2 .. 2; CHKDIS at 0 range 3 .. 3; @@ -1674,184 +1574,152 @@ package ATSAM3X8E.USART is Reserved_17_31 at 0 range 17 .. 31; end record; - -------------------- - -- LINIR_Register -- - -------------------- - - subtype LINIR_IDCHR_Field is ATSAM3X8E.Byte; + subtype USART0_LINIR_IDCHR_Field is ATSAM3X8E.Byte; -- LIN Identifier Register - type LINIR_Register is record + type USART0_LINIR_Register is record -- Identifier Character - IDCHR : LINIR_IDCHR_Field := 16#0#; + IDCHR : USART0_LINIR_IDCHR_Field := 16#0#; -- unspecified Reserved_8_31 : ATSAM3X8E.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for LINIR_Register use record + for USART0_LINIR_Register use record IDCHR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- WPMR_Register -- - ------------------- - - subtype WPMR_WPEN_Field is ATSAM3X8E.Bit; - subtype WPMR_WPKEY_Field is ATSAM3X8E.UInt24; + subtype USART0_WPMR_WPEN_Field is ATSAM3X8E.Bit; + subtype USART0_WPMR_WPKEY_Field is ATSAM3X8E.UInt24; -- Write Protect Mode Register - type WPMR_Register is record + type USART0_WPMR_Register is record -- Write Protect Enable - WPEN : WPMR_WPEN_Field := 16#0#; + WPEN : USART0_WPMR_WPEN_Field := 16#0#; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7 := 16#0#; -- Write Protect KEY - WPKEY : WPMR_WPKEY_Field := 16#0#; + WPKEY : USART0_WPMR_WPKEY_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPMR_Register use record + for USART0_WPMR_Register use record WPEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPKEY at 0 range 8 .. 31; end record; - ------------------- - -- WPSR_Register -- - ------------------- - - subtype WPSR_WPVS_Field is ATSAM3X8E.Bit; - subtype WPSR_WPVSRC_Field is ATSAM3X8E.Short; + subtype USART0_WPSR_WPVS_Field is ATSAM3X8E.Bit; + subtype USART0_WPSR_WPVSRC_Field is ATSAM3X8E.UInt16; -- Write Protect Status Register - type WPSR_Register is record + type USART0_WPSR_Register is record -- Read-only. Write Protect Violation Status - WPVS : WPSR_WPVS_Field := 16#0#; + WPVS : USART0_WPSR_WPVS_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Write Protect Violation Source - WPVSRC : WPSR_WPVSRC_Field := 16#0#; + WPVSRC : USART0_WPSR_WPVSRC_Field; -- unspecified Reserved_24_31 : ATSAM3X8E.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for WPSR_Register use record + for USART0_WPSR_Register use record WPVS at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; WPVSRC at 0 range 8 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- RCR_Register -- - ------------------ - - subtype RCR_RXCTR_Field is ATSAM3X8E.Short; + subtype USART0_RCR_RXCTR_Field is ATSAM3X8E.UInt16; -- Receive Counter Register - type RCR_Register is record + type USART0_RCR_Register is record -- Receive Counter Register - RXCTR : RCR_RXCTR_Field := 16#0#; + RXCTR : USART0_RCR_RXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RCR_Register use record + for USART0_RCR_Register use record RXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- TCR_Register -- - ------------------ - - subtype TCR_TXCTR_Field is ATSAM3X8E.Short; + subtype USART0_TCR_TXCTR_Field is ATSAM3X8E.UInt16; -- Transmit Counter Register - type TCR_Register is record + type USART0_TCR_Register is record -- Transmit Counter Register - TXCTR : TCR_TXCTR_Field := 16#0#; + TXCTR : USART0_TCR_TXCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TCR_Register use record + for USART0_TCR_Register use record TXCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- RNCR_Register -- - ------------------- - - subtype RNCR_RXNCTR_Field is ATSAM3X8E.Short; + subtype USART0_RNCR_RXNCTR_Field is ATSAM3X8E.UInt16; -- Receive Next Counter Register - type RNCR_Register is record + type USART0_RNCR_Register is record -- Receive Next Counter - RXNCTR : RNCR_RXNCTR_Field := 16#0#; + RXNCTR : USART0_RNCR_RXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for RNCR_Register use record + for USART0_RNCR_Register use record RXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- TNCR_Register -- - ------------------- - - subtype TNCR_TXNCTR_Field is ATSAM3X8E.Short; + subtype USART0_TNCR_TXNCTR_Field is ATSAM3X8E.UInt16; -- Transmit Next Counter Register - type TNCR_Register is record + type USART0_TNCR_Register is record -- Transmit Counter Next - TXNCTR : TNCR_TXNCTR_Field := 16#0#; + TXNCTR : USART0_TNCR_TXNCTR_Field := 16#0#; -- unspecified - Reserved_16_31 : ATSAM3X8E.Short := 16#0#; + Reserved_16_31 : ATSAM3X8E.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TNCR_Register use record + for USART0_TNCR_Register use record TXNCTR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- PTCR_Register -- - ------------------- - - subtype PTCR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_RXTDIS_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTEN_Field is ATSAM3X8E.Bit; - subtype PTCR_TXTDIS_Field is ATSAM3X8E.Bit; + subtype USART0_PTCR_RXTEN_Field is ATSAM3X8E.Bit; + subtype USART0_PTCR_RXTDIS_Field is ATSAM3X8E.Bit; + subtype USART0_PTCR_TXTEN_Field is ATSAM3X8E.Bit; + subtype USART0_PTCR_TXTDIS_Field is ATSAM3X8E.Bit; -- Transfer Control Register - type PTCR_Register is record + type USART0_PTCR_Register is record -- Write-only. Receiver Transfer Enable - RXTEN : PTCR_RXTEN_Field := 16#0#; + RXTEN : USART0_PTCR_RXTEN_Field := 16#0#; -- Write-only. Receiver Transfer Disable - RXTDIS : PTCR_RXTDIS_Field := 16#0#; + RXTDIS : USART0_PTCR_RXTDIS_Field := 16#0#; -- unspecified Reserved_2_7 : ATSAM3X8E.UInt6 := 16#0#; -- Write-only. Transmitter Transfer Enable - TXTEN : PTCR_TXTEN_Field := 16#0#; + TXTEN : USART0_PTCR_TXTEN_Field := 16#0#; -- Write-only. Transmitter Transfer Disable - TXTDIS : PTCR_TXTDIS_Field := 16#0#; + TXTDIS : USART0_PTCR_TXTDIS_Field := 16#0#; -- unspecified Reserved_10_31 : ATSAM3X8E.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTCR_Register use record + for USART0_PTCR_Register use record RXTEN at 0 range 0 .. 0; RXTDIS at 0 range 1 .. 1; Reserved_2_7 at 0 range 2 .. 7; @@ -1860,27 +1728,23 @@ package ATSAM3X8E.USART is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- PTSR_Register -- - ------------------- - - subtype PTSR_RXTEN_Field is ATSAM3X8E.Bit; - subtype PTSR_TXTEN_Field is ATSAM3X8E.Bit; + subtype USART0_PTSR_RXTEN_Field is ATSAM3X8E.Bit; + subtype USART0_PTSR_TXTEN_Field is ATSAM3X8E.Bit; -- Transfer Status Register - type PTSR_Register is record + type USART0_PTSR_Register is record -- Read-only. Receiver Transfer Enable - RXTEN : PTSR_RXTEN_Field := 16#0#; + RXTEN : USART0_PTSR_RXTEN_Field; -- unspecified Reserved_1_7 : ATSAM3X8E.UInt7; -- Read-only. Transmitter Transfer Enable - TXTEN : PTSR_TXTEN_Field := 16#0#; + TXTEN : USART0_PTSR_TXTEN_Field; -- unspecified Reserved_9_31 : ATSAM3X8E.UInt23; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTSR_Register use record + for USART0_PTSR_Register use record RXTEN at 0 range 0 .. 0; Reserved_1_7 at 0 range 1 .. 7; TXTEN at 0 range 8 .. 8; @@ -1891,99 +1755,176 @@ package ATSAM3X8E.USART is -- Peripherals -- ----------------- + type USART0_Disc is + (Default, + Spi_Mode, + Lin_Mode); + -- Universal Synchronous Asynchronous Receiver Transmitter 0 - type USART_Peripheral is record - -- Control Register - CR : CR_Register; - -- Mode Register - MR : MR_Register; - -- Interrupt Enable Register - IER : IER_Register; - -- Interrupt Disable Register - IDR : IDR_Register; - -- Interrupt Mask Register - IMR : IMR_Register; - -- Channel Status Register - CSR : CSR_Register; + type USART_Peripheral + (Discriminent : USART0_Disc := Default) + is record -- Receiver Holding Register - RHR : RHR_Register; + RHR : aliased USART0_RHR_Register; + pragma Volatile_Full_Access (RHR); -- Transmitter Holding Register - THR : THR_Register; + THR : aliased USART0_THR_Register; + pragma Volatile_Full_Access (THR); -- Baud Rate Generator Register - BRGR : BRGR_Register; + BRGR : aliased USART0_BRGR_Register; + pragma Volatile_Full_Access (BRGR); -- Receiver Time-out Register - RTOR : RTOR_Register; + RTOR : aliased USART0_RTOR_Register; + pragma Volatile_Full_Access (RTOR); -- Transmitter Timeguard Register - TTGR : TTGR_Register; + TTGR : aliased USART0_TTGR_Register; + pragma Volatile_Full_Access (TTGR); -- FI DI Ratio Register - FIDI : FIDI_Register; + FIDI : aliased USART0_FIDI_Register; + pragma Volatile_Full_Access (FIDI); -- Number of Errors Register - NER : NER_Register; + NER : aliased USART0_NER_Register; + pragma Volatile_Full_Access (NER); -- IrDA Filter Register - IF_k : IF_Register; + IF_k : aliased USART0_IF_Register; + pragma Volatile_Full_Access (IF_k); -- Manchester Encoder Decoder Register - MAN : MAN_Register; + MAN : aliased USART0_MAN_Register; + pragma Volatile_Full_Access (MAN); -- LIN Mode Register - LINMR : LINMR_Register; + LINMR : aliased USART0_LINMR_Register; + pragma Volatile_Full_Access (LINMR); -- LIN Identifier Register - LINIR : LINIR_Register; + LINIR : aliased USART0_LINIR_Register; + pragma Volatile_Full_Access (LINIR); -- Write Protect Mode Register - WPMR : WPMR_Register; + WPMR : aliased USART0_WPMR_Register; + pragma Volatile_Full_Access (WPMR); -- Write Protect Status Register - WPSR : WPSR_Register; + WPSR : aliased USART0_WPSR_Register; + pragma Volatile_Full_Access (WPSR); -- Receive Pointer Register - RPR : ATSAM3X8E.Word; + RPR : aliased ATSAM3X8E.UInt32; -- Receive Counter Register - RCR : RCR_Register; + RCR : aliased USART0_RCR_Register; + pragma Volatile_Full_Access (RCR); -- Transmit Pointer Register - TPR : ATSAM3X8E.Word; + TPR : aliased ATSAM3X8E.UInt32; -- Transmit Counter Register - TCR : TCR_Register; + TCR : aliased USART0_TCR_Register; + pragma Volatile_Full_Access (TCR); -- Receive Next Pointer Register - RNPR : ATSAM3X8E.Word; + RNPR : aliased ATSAM3X8E.UInt32; -- Receive Next Counter Register - RNCR : RNCR_Register; + RNCR : aliased USART0_RNCR_Register; + pragma Volatile_Full_Access (RNCR); -- Transmit Next Pointer Register - TNPR : ATSAM3X8E.Word; + TNPR : aliased ATSAM3X8E.UInt32; -- Transmit Next Counter Register - TNCR : TNCR_Register; + TNCR : aliased USART0_TNCR_Register; + pragma Volatile_Full_Access (TNCR); -- Transfer Control Register - PTCR : PTCR_Register; + PTCR : aliased USART0_PTCR_Register; + pragma Volatile_Full_Access (PTCR); -- Transfer Status Register - PTSR : PTSR_Register; + PTSR : aliased USART0_PTSR_Register; + pragma Volatile_Full_Access (PTSR); + case Discriminent is + when Default => + -- Control Register + CR : aliased USART0_CR_Register; + pragma Volatile_Full_Access (CR); + -- Mode Register + MR : aliased USART0_MR_Register; + pragma Volatile_Full_Access (MR); + -- Interrupt Enable Register + IER : aliased USART0_IER_Register; + pragma Volatile_Full_Access (IER); + -- Interrupt Disable Register + IDR : aliased USART0_IDR_Register; + pragma Volatile_Full_Access (IDR); + -- Interrupt Mask Register + IMR : aliased USART0_IMR_Register; + pragma Volatile_Full_Access (IMR); + -- Channel Status Register + CSR : aliased USART0_CSR_Register; + pragma Volatile_Full_Access (CSR); + when Spi_Mode => + -- Control Register + CR_SPI_MODE : aliased USART0_CR_SPI_MODE_Register; + pragma Volatile_Full_Access (CR_SPI_MODE); + -- Mode Register + MR_SPI_MODE : aliased USART0_MR_SPI_MODE_Register; + pragma Volatile_Full_Access (MR_SPI_MODE); + -- Interrupt Enable Register + IER_SPI_MODE : aliased USART0_IER_SPI_MODE_Register; + pragma Volatile_Full_Access (IER_SPI_MODE); + -- Interrupt Disable Register + IDR_SPI_MODE : aliased USART0_IDR_SPI_MODE_Register; + pragma Volatile_Full_Access (IDR_SPI_MODE); + -- Interrupt Mask Register + IMR_SPI_MODE : aliased USART0_IMR_SPI_MODE_Register; + pragma Volatile_Full_Access (IMR_SPI_MODE); + -- Channel Status Register + CSR_SPI_MODE : aliased USART0_CSR_SPI_MODE_Register; + pragma Volatile_Full_Access (CSR_SPI_MODE); + when Lin_Mode => + -- Interrupt Enable Register + IER_LIN_MODE : aliased USART0_IER_LIN_MODE_Register; + pragma Volatile_Full_Access (IER_LIN_MODE); + -- Interrupt Disable Register + IDR_LIN_MODE : aliased USART0_IDR_LIN_MODE_Register; + pragma Volatile_Full_Access (IDR_LIN_MODE); + -- Interrupt Mask Register + IMR_LIN_MODE : aliased USART0_IMR_LIN_MODE_Register; + pragma Volatile_Full_Access (IMR_LIN_MODE); + -- Channel Status Register + CSR_LIN_MODE : aliased USART0_CSR_LIN_MODE_Register; + pragma Volatile_Full_Access (CSR_LIN_MODE); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for USART_Peripheral use record - CR at 0 range 0 .. 31; - MR at 4 range 0 .. 31; - IER at 8 range 0 .. 31; - IDR at 12 range 0 .. 31; - IMR at 16 range 0 .. 31; - CSR at 20 range 0 .. 31; - RHR at 24 range 0 .. 31; - THR at 28 range 0 .. 31; - BRGR at 32 range 0 .. 31; - RTOR at 36 range 0 .. 31; - TTGR at 40 range 0 .. 31; - FIDI at 64 range 0 .. 31; - NER at 68 range 0 .. 31; - IF_k at 76 range 0 .. 31; - MAN at 80 range 0 .. 31; - LINMR at 84 range 0 .. 31; - LINIR at 88 range 0 .. 31; - WPMR at 228 range 0 .. 31; - WPSR at 232 range 0 .. 31; - RPR at 256 range 0 .. 31; - RCR at 260 range 0 .. 31; - TPR at 264 range 0 .. 31; - TCR at 268 range 0 .. 31; - RNPR at 272 range 0 .. 31; - RNCR at 276 range 0 .. 31; - TNPR at 280 range 0 .. 31; - TNCR at 284 range 0 .. 31; - PTCR at 288 range 0 .. 31; - PTSR at 292 range 0 .. 31; + RHR at 16#18# range 0 .. 31; + THR at 16#1C# range 0 .. 31; + BRGR at 16#20# range 0 .. 31; + RTOR at 16#24# range 0 .. 31; + TTGR at 16#28# range 0 .. 31; + FIDI at 16#40# range 0 .. 31; + NER at 16#44# range 0 .. 31; + IF_k at 16#4C# range 0 .. 31; + MAN at 16#50# range 0 .. 31; + LINMR at 16#54# range 0 .. 31; + LINIR at 16#58# range 0 .. 31; + WPMR at 16#E4# range 0 .. 31; + WPSR at 16#E8# range 0 .. 31; + RPR at 16#100# range 0 .. 31; + RCR at 16#104# range 0 .. 31; + TPR at 16#108# range 0 .. 31; + TCR at 16#10C# range 0 .. 31; + RNPR at 16#110# range 0 .. 31; + RNCR at 16#114# range 0 .. 31; + TNPR at 16#118# range 0 .. 31; + TNCR at 16#11C# range 0 .. 31; + PTCR at 16#120# range 0 .. 31; + PTSR at 16#124# range 0 .. 31; + CR at 16#0# range 0 .. 31; + MR at 16#4# range 0 .. 31; + IER at 16#8# range 0 .. 31; + IDR at 16#C# range 0 .. 31; + IMR at 16#10# range 0 .. 31; + CSR at 16#14# range 0 .. 31; + CR_SPI_MODE at 16#0# range 0 .. 31; + MR_SPI_MODE at 16#4# range 0 .. 31; + IER_SPI_MODE at 16#8# range 0 .. 31; + IDR_SPI_MODE at 16#C# range 0 .. 31; + IMR_SPI_MODE at 16#10# range 0 .. 31; + CSR_SPI_MODE at 16#14# range 0 .. 31; + IER_LIN_MODE at 16#8# range 0 .. 31; + IDR_LIN_MODE at 16#C# range 0 .. 31; + IMR_LIN_MODE at 16#10# range 0 .. 31; + CSR_LIN_MODE at 16#14# range 0 .. 31; end record; -- Universal Synchronous Asynchronous Receiver Transmitter 0 diff --git a/arduino-due/atsam3x8e/atsam3x8e.ads b/arduino-due/atsam3x8e/atsam3x8e.ads index 501efde..44dd4ee 100644 --- a/arduino-due/atsam3x8e/atsam3x8e.ads +++ b/arduino-due/atsam3x8e/atsam3x8e.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from ATSAM3X8E.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with Interfaces; with System; @@ -16,9 +17,9 @@ package ATSAM3X8E is -- Base type -- --------------- - subtype Word is Interfaces.Unsigned_32; - subtype Short is Interfaces.Unsigned_16; - subtype Byte is Interfaces.Unsigned_8; + type UInt32 is new Interfaces.Unsigned_32; + type UInt16 is new Interfaces.Unsigned_16; + type Byte is new Interfaces.Unsigned_8; type Bit is mod 2**1 with Size => 1; type UInt2 is mod 2**2 @@ -82,81 +83,43 @@ package ATSAM3X8E is -- Base addresses -- -------------------- - HSMCI_Base : constant System.Address := - System'To_Address (16#40000000#); - SSC_Base : constant System.Address := - System'To_Address (16#40004000#); - SPI0_Base : constant System.Address := - System'To_Address (16#40008000#); - TC0_Base : constant System.Address := - System'To_Address (16#40080000#); - TC1_Base : constant System.Address := - System'To_Address (16#40084000#); - TC2_Base : constant System.Address := - System'To_Address (16#40088000#); - TWI0_Base : constant System.Address := - System'To_Address (16#4008C000#); - TWI1_Base : constant System.Address := - System'To_Address (16#40090000#); - PWM_Base : constant System.Address := - System'To_Address (16#40094000#); - USART0_Base : constant System.Address := - System'To_Address (16#40098000#); - USART1_Base : constant System.Address := - System'To_Address (16#4009C000#); - USART2_Base : constant System.Address := - System'To_Address (16#400A0000#); - USART3_Base : constant System.Address := - System'To_Address (16#400A4000#); - UOTGHS_Base : constant System.Address := - System'To_Address (16#400AC000#); - EMAC_Base : constant System.Address := - System'To_Address (16#400B0000#); - CAN0_Base : constant System.Address := - System'To_Address (16#400B4000#); - CAN1_Base : constant System.Address := - System'To_Address (16#400B8000#); - TRNG_Base : constant System.Address := - System'To_Address (16#400BC000#); - ADC_Base : constant System.Address := - System'To_Address (16#400C0000#); - DMAC_Base : constant System.Address := - System'To_Address (16#400C4000#); - DACC_Base : constant System.Address := - System'To_Address (16#400C8000#); - SMC_Base : constant System.Address := - System'To_Address (16#400E0000#); - MATRIX_Base : constant System.Address := - System'To_Address (16#400E0400#); - PMC_Base : constant System.Address := - System'To_Address (16#400E0600#); - UART_Base : constant System.Address := - System'To_Address (16#400E0800#); - CHIPID_Base : constant System.Address := - System'To_Address (16#400E0940#); - EFC0_Base : constant System.Address := - System'To_Address (16#400E0A00#); - EFC1_Base : constant System.Address := - System'To_Address (16#400E0C00#); - PIOA_Base : constant System.Address := - System'To_Address (16#400E0E00#); - PIOB_Base : constant System.Address := - System'To_Address (16#400E1000#); - PIOC_Base : constant System.Address := - System'To_Address (16#400E1200#); - PIOD_Base : constant System.Address := - System'To_Address (16#400E1400#); - RSTC_Base : constant System.Address := - System'To_Address (16#400E1A00#); - SUPC_Base : constant System.Address := - System'To_Address (16#400E1A10#); - RTT_Base : constant System.Address := - System'To_Address (16#400E1A30#); - WDT_Base : constant System.Address := - System'To_Address (16#400E1A50#); - RTC_Base : constant System.Address := - System'To_Address (16#400E1A60#); - GPBR_Base : constant System.Address := - System'To_Address (16#400E1A90#); + HSMCI_Base : constant System.Address := System'To_Address (16#40000000#); + SSC_Base : constant System.Address := System'To_Address (16#40004000#); + SPI0_Base : constant System.Address := System'To_Address (16#40008000#); + TC0_Base : constant System.Address := System'To_Address (16#40080000#); + TC1_Base : constant System.Address := System'To_Address (16#40084000#); + TC2_Base : constant System.Address := System'To_Address (16#40088000#); + TWI0_Base : constant System.Address := System'To_Address (16#4008C000#); + TWI1_Base : constant System.Address := System'To_Address (16#40090000#); + PWM_Base : constant System.Address := System'To_Address (16#40094000#); + USART0_Base : constant System.Address := System'To_Address (16#40098000#); + USART1_Base : constant System.Address := System'To_Address (16#4009C000#); + USART2_Base : constant System.Address := System'To_Address (16#400A0000#); + USART3_Base : constant System.Address := System'To_Address (16#400A4000#); + UOTGHS_Base : constant System.Address := System'To_Address (16#400AC000#); + EMAC_Base : constant System.Address := System'To_Address (16#400B0000#); + CAN0_Base : constant System.Address := System'To_Address (16#400B4000#); + CAN1_Base : constant System.Address := System'To_Address (16#400B8000#); + TRNG_Base : constant System.Address := System'To_Address (16#400BC000#); + ADC_Base : constant System.Address := System'To_Address (16#400C0000#); + DMAC_Base : constant System.Address := System'To_Address (16#400C4000#); + DACC_Base : constant System.Address := System'To_Address (16#400C8000#); + SMC_Base : constant System.Address := System'To_Address (16#400E0000#); + MATRIX_Base : constant System.Address := System'To_Address (16#400E0400#); + PMC_Base : constant System.Address := System'To_Address (16#400E0600#); + UART_Base : constant System.Address := System'To_Address (16#400E0800#); + CHIPID_Base : constant System.Address := System'To_Address (16#400E0940#); + EFC0_Base : constant System.Address := System'To_Address (16#400E0A00#); + EFC1_Base : constant System.Address := System'To_Address (16#400E0C00#); + PIOA_Base : constant System.Address := System'To_Address (16#400E0E00#); + PIOB_Base : constant System.Address := System'To_Address (16#400E1000#); + PIOC_Base : constant System.Address := System'To_Address (16#400E1200#); + PIOD_Base : constant System.Address := System'To_Address (16#400E1400#); + RSTC_Base : constant System.Address := System'To_Address (16#400E1A00#); + SUPC_Base : constant System.Address := System'To_Address (16#400E1A10#); + RTT_Base : constant System.Address := System'To_Address (16#400E1A30#); + WDT_Base : constant System.Address := System'To_Address (16#400E1A50#); + RTC_Base : constant System.Address := System'To_Address (16#400E1A60#); + GPBR_Base : constant System.Address := System'To_Address (16#400E1A90#); end ATSAM3X8E; diff --git a/microbit/Makefile b/microbit/Makefile index e9d0e16..75a0070 100644 --- a/microbit/Makefile +++ b/microbit/Makefile @@ -1,4 +1,4 @@ -# Copyright (C) 2016, 2018 Free Software Foundation, Inc. +# Copyright (C) 2016, 2018, 2020 Free Software Foundation, Inc. # # This file is part of the Cortex GNAT RTS package. # @@ -16,13 +16,23 @@ # along with this program; see the file COPYING3. If not, see # . -all: +SVD2ADA ?= ~/adacore/svd2ada + +all: nrf51 gprbuild -p -P build_runtime.gpr +nrf51: + $(SVD2ADA)/svd2ada \ + --output=nrf51 \ + $(SVD2ADA)/CMSIS-SVD/Nordic/nrf51.svd +# would have liked to specify --no-vfa-on-types but this suppresses the use +# of arrays. + install: all gprinstall -p -P build_runtime.gpr -f clean: - gprclean -P build_runtime.gpr + -gprclean -P build_runtime.gpr + rm -rf nrf51 .PHONY: all install clean diff --git a/microbit/adainclude/nrf51_clock.adb b/microbit/adainclude/nrf51_clock.adb index bc1173f..7ce60d1 100644 --- a/microbit/adainclude/nrf51_clock.adb +++ b/microbit/adainclude/nrf51_clock.adb @@ -43,7 +43,7 @@ with System; package body nRF51_Clock is procedure Start is - use type nrf51.CLOCK.STATE_Field; + use type nrf51.CLOCK.LFCLKSTAT_STATE_Field; begin -- Start the board low frequency clock, running off the high diff --git a/microbit/build_runtime.gpr b/microbit/build_runtime.gpr index f20ad45..4cd6dc1 100644 --- a/microbit/build_runtime.gpr +++ b/microbit/build_runtime.gpr @@ -96,6 +96,7 @@ library project Build_Runtime is for Switches ("a-tags.adb") use ALL_ADAFLAGS & ("-g"); for Switches ("last_chance_handler.c") use ALL_CFLAGS & ("-g", "-O0"); for Switches ("hardfault_handling.adb") use ALL_ADAFLAGS & ("-g", "-O0"); + for Switches ("nrf51-swi.ads") use ALL_ADAFLAGS & ("-gnatwU"); end Compiler; package Install is diff --git a/microbit/nrf51/nrf51-aar.ads b/microbit/nrf51/nrf51-aar.ads index b7d436e..bfd8cc1 100644 --- a/microbit/nrf51/nrf51-aar.ads +++ b/microbit/nrf51/nrf51-aar.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,94 +43,86 @@ package nrf51.AAR is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on END event. - type END_Field is - ( - -- Interrupt disabled. + type INTENSET_END_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for END_Field use + for INTENSET_END_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on END event. - type END_Field_1 is - ( - -- Reset value for the field - End_Field_Reset, + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for END_Field_1 use - (End_Field_Reset => 0, + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, Set => 1); -- Enable interrupt on RESOLVED event. - type RESOLVED_Field is - ( - -- Interrupt disabled. + type INTENSET_RESOLVED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for RESOLVED_Field use + for INTENSET_RESOLVED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on RESOLVED event. - type RESOLVED_Field_1 is - ( - -- Reset value for the field - Resolved_Field_Reset, + type INTENSET_RESOLVED_Field_1 is + (-- Reset value for the field + Intenset_Resolved_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for RESOLVED_Field_1 use - (Resolved_Field_Reset => 0, + for INTENSET_RESOLVED_Field_1 use + (Intenset_Resolved_Field_Reset => 0, Set => 1); -- Enable interrupt on NOTRESOLVED event. - type NOTRESOLVED_Field is - ( - -- Interrupt disabled. + type INTENSET_NOTRESOLVED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for NOTRESOLVED_Field use + for INTENSET_NOTRESOLVED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on NOTRESOLVED event. - type NOTRESOLVED_Field_1 is - ( - -- Reset value for the field - Notresolved_Field_Reset, + type INTENSET_NOTRESOLVED_Field_1 is + (-- Reset value for the field + Intenset_Notresolved_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for NOTRESOLVED_Field_1 use - (Notresolved_Field_Reset => 0, + for INTENSET_NOTRESOLVED_Field_1 use + (Intenset_Notresolved_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on END event. - END_k : END_Field_1 := End_Field_Reset; + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; -- Enable interrupt on RESOLVED event. - RESOLVED : RESOLVED_Field_1 := Resolved_Field_Reset; + RESOLVED : INTENSET_RESOLVED_Field_1 := + Intenset_Resolved_Field_Reset; -- Enable interrupt on NOTRESOLVED event. - NOTRESOLVED : NOTRESOLVED_Field_1 := Notresolved_Field_Reset; + NOTRESOLVED : INTENSET_NOTRESOLVED_Field_1 := + Intenset_Notresolved_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -109,58 +132,86 @@ package nrf51.AAR is Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on ENDKSGEN event. + type INTENCLR_END_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on ENDKSGEN event. - type END_Field_2 is - ( - -- Reset value for the field - End_Field_Reset, + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for END_Field_2 use - (End_Field_Reset => 0, + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, Clear => 1); -- Disable interrupt on RESOLVED event. - type RESOLVED_Field_2 is - ( - -- Reset value for the field - Resolved_Field_Reset, + type INTENCLR_RESOLVED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_RESOLVED_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on RESOLVED event. + type INTENCLR_RESOLVED_Field_1 is + (-- Reset value for the field + Intenclr_Resolved_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for RESOLVED_Field_2 use - (Resolved_Field_Reset => 0, + for INTENCLR_RESOLVED_Field_1 use + (Intenclr_Resolved_Field_Reset => 0, Clear => 1); -- Disable interrupt on NOTRESOLVED event. - type NOTRESOLVED_Field_2 is - ( - -- Reset value for the field - Notresolved_Field_Reset, + type INTENCLR_NOTRESOLVED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_NOTRESOLVED_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on NOTRESOLVED event. + type INTENCLR_NOTRESOLVED_Field_1 is + (-- Reset value for the field + Intenclr_Notresolved_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for NOTRESOLVED_Field_2 use - (Notresolved_Field_Reset => 0, + for INTENCLR_NOTRESOLVED_Field_1 use + (Intenclr_Notresolved_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on ENDKSGEN event. - END_k : END_Field_2 := End_Field_Reset; + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; -- Disable interrupt on RESOLVED event. - RESOLVED : RESOLVED_Field_2 := Resolved_Field_Reset; + RESOLVED : INTENCLR_RESOLVED_Field_1 := + Intenclr_Resolved_Field_Reset; -- Disable interrupt on NOTRESOLVED event. - NOTRESOLVED : NOTRESOLVED_Field_2 := Notresolved_Field_Reset; + NOTRESOLVED : INTENCLR_NOTRESOLVED_Field_1 := + Intenclr_Notresolved_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -170,10 +221,6 @@ package nrf51.AAR is Reserved_3_31 at 0 range 3 .. 31; end record; - --------------------- - -- STATUS_Register -- - --------------------- - subtype STATUS_STATUS_Field is nrf51.UInt4; -- Resolution status. @@ -183,7 +230,7 @@ package nrf51.AAR is -- unspecified Reserved_4_31 : nrf51.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for STATUS_Register use record @@ -191,30 +238,25 @@ package nrf51.AAR is Reserved_4_31 at 0 range 4 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- Enable AAR. - type ENABLE_Field is - ( - -- Disabled AAR. + type ENABLE_ENABLE_Field is + (-- Disabled AAR. Disabled, -- Enable AAR. Enabled) with Size => 2; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 3); -- Enable AAR. type ENABLE_Register is record -- Enable AAR. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.AAR.Disabled; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -222,10 +264,6 @@ package nrf51.AAR is Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- NIRK_Register -- - ------------------- - subtype NIRK_NIRK_Field is nrf51.UInt5; -- Number of Identity root Keys in the IRK data structure. @@ -235,7 +273,7 @@ package nrf51.AAR is -- unspecified Reserved_5_31 : nrf51.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for NIRK_Register use record @@ -243,30 +281,25 @@ package nrf51.AAR is Reserved_5_31 at 0 range 5 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.AAR.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -282,52 +315,52 @@ package nrf51.AAR is type AAR_Peripheral is record -- Start resolving addresses based on IRKs specified in the IRK data -- structure. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop resolving addresses. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Address resolution procedure completed. - EVENTS_END : nrf51.Word; + EVENTS_END : aliased nrf51.UInt32; -- Address resolved. - EVENTS_RESOLVED : nrf51.Word; + EVENTS_RESOLVED : aliased nrf51.UInt32; -- Address not resolved. - EVENTS_NOTRESOLVED : nrf51.Word; + EVENTS_NOTRESOLVED : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Resolution status. - STATUS : STATUS_Register; + STATUS : aliased STATUS_Register; -- Enable AAR. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- Number of Identity root Keys in the IRK data structure. - NIRK : NIRK_Register; + NIRK : aliased NIRK_Register; -- Pointer to the IRK data structure. - IRKPTR : nrf51.Word; + IRKPTR : aliased nrf51.UInt32; -- Pointer to the resolvable address (6 bytes). - ADDRPTR : nrf51.Word; + ADDRPTR : aliased nrf51.UInt32; -- Pointer to a "scratch" data area used for temporary storage during -- resolution. A minimum of 3 bytes must be reserved. - SCRATCHPTR : nrf51.Word; + SCRATCHPTR : aliased nrf51.UInt32; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for AAR_Peripheral use record - TASKS_START at 0 range 0 .. 31; - TASKS_STOP at 8 range 0 .. 31; - EVENTS_END at 256 range 0 .. 31; - EVENTS_RESOLVED at 260 range 0 .. 31; - EVENTS_NOTRESOLVED at 264 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - STATUS at 1024 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - NIRK at 1284 range 0 .. 31; - IRKPTR at 1288 range 0 .. 31; - ADDRPTR at 1296 range 0 .. 31; - SCRATCHPTR at 1300 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#8# range 0 .. 31; + EVENTS_END at 16#100# range 0 .. 31; + EVENTS_RESOLVED at 16#104# range 0 .. 31; + EVENTS_NOTRESOLVED at 16#108# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + STATUS at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + NIRK at 16#504# range 0 .. 31; + IRKPTR at 16#508# range 0 .. 31; + ADDRPTR at 16#510# range 0 .. 31; + SCRATCHPTR at 16#514# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- Accelerated Address Resolver. diff --git a/microbit/nrf51/nrf51-adc.ads b/microbit/nrf51/nrf51-adc.ads index acfc621..ff786d3 100644 --- a/microbit/nrf51/nrf51-adc.ads +++ b/microbit/nrf51/nrf51-adc.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,42 +43,36 @@ package nrf51.ADC is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on END event. - type END_Field is - ( - -- Interrupt disabled. + type INTENSET_END_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for END_Field use + for INTENSET_END_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on END event. - type END_Field_1 is - ( - -- Reset value for the field - End_Field_Reset, + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for END_Field_1 use - (End_Field_Reset => 0, + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on END event. - END_k : END_Field_1 := End_Field_Reset; + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -55,30 +80,36 @@ package nrf51.ADC is Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on END event. + type INTENCLR_END_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on END event. - type END_Field_2 is - ( - -- Reset value for the field - End_Field_Reset, + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for END_Field_2 use - (End_Field_Reset => 0, + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on END event. - END_k : END_Field_2 := End_Field_Reset; + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -86,30 +117,25 @@ package nrf51.ADC is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------- - -- BUSY_Register -- - ------------------- - -- ADC busy register. - type BUSY_Field is - ( - -- No ongoing ADC conversion is taking place. ADC is ready. + type BUSY_BUSY_Field is + (-- No ongoing ADC conversion is taking place. ADC is ready. Ready, -- An ADC conversion is taking place. ADC is busy. Busy) with Size => 1; - for BUSY_Field use + for BUSY_BUSY_Field use (Ready => 0, Busy => 1); -- ADC busy register. type BUSY_Register is record -- Read-only. ADC busy register. - BUSY : BUSY_Field; + BUSY : BUSY_BUSY_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for BUSY_Register use record @@ -117,31 +143,26 @@ package nrf51.ADC is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- ADC enable. - type ENABLE_Field is - ( - -- ADC is disabled. + type ENABLE_ENABLE_Field is + (-- ADC is disabled. Disabled, -- ADC is enabled. If an analog input pin is selected as source of the - -- conversion, the selected pin is configured as an analog input. +-- conversion, the selected pin is configured as an analog input. Enabled) with Size => 2; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 1); -- ADC enable. type ENABLE_Register is record -- ADC enable. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.ADC.Disabled; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -149,43 +170,37 @@ package nrf51.ADC is Reserved_2_31 at 0 range 2 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- - -- ADC resolution. - type RES_Field is - ( - -- 8bit ADC resolution. - RES_Field_8BIT, + type CONFIG_RES_Field is + (-- 8bit ADC resolution. + Val_8BIT, -- 9bit ADC resolution. - RES_Field_9BIT, + Val_9BIT, -- 10bit ADC resolution. - RES_Field_10BIT) + Val_10BIT) with Size => 2; - for RES_Field use - (RES_Field_8BIT => 0, - RES_Field_9BIT => 1, - RES_Field_10BIT => 2); + for CONFIG_RES_Field use + (Val_8BIT => 0, + Val_9BIT => 1, + Val_10BIT => 2); -- ADC input selection. - type INPSEL_Field is - ( - -- Analog input specified by PSEL with no prescaling used as input for - -- the conversion. + type CONFIG_INPSEL_Field is + (-- Analog input specified by PSEL with no prescaling used as input for the +-- conversion. Analoginputnoprescaling, - -- Analog input specified by PSEL with 2/3 prescaling used as input for - -- the conversion. + -- Analog input specified by PSEL with 2/3 prescaling used as input for the +-- conversion. Analoginputtwothirdsprescaling, - -- Analog input specified by PSEL with 1/3 prescaling used as input for - -- the conversion. + -- Analog input specified by PSEL with 1/3 prescaling used as input for the +-- conversion. Analoginputonethirdprescaling, -- Supply voltage with 2/3 prescaling used as input for the conversion. Supplytwothirdsprescaling, -- Supply voltage with 1/3 prescaling used as input for the conversion. Supplyonethirdprescaling) with Size => 3; - for INPSEL_Field use + for CONFIG_INPSEL_Field use (Analoginputnoprescaling => 0, Analoginputtwothirdsprescaling => 1, Analoginputonethirdprescaling => 2, @@ -193,30 +208,27 @@ package nrf51.ADC is Supplyonethirdprescaling => 6); -- ADC reference selection. - type REFSEL_Field is - ( - -- Use internal 1.2V bandgap voltage as reference for conversion. + type CONFIG_REFSEL_Field is + (-- Use internal 1.2V bandgap voltage as reference for conversion. Vbg, - -- Use external source configured by EXTREFSEL as reference for - -- conversion. + -- Use external source configured by EXTREFSEL as reference for conversion. External, - -- Use supply voltage with 1/2 prescaling as reference for conversion. - -- Only usable when supply voltage is between 1.7V and 2.6V. + -- Use supply voltage with 1/2 prescaling as reference for conversion. Only +-- usable when supply voltage is between 1.7V and 2.6V. Supplyonehalfprescaling, - -- Use supply voltage with 1/3 prescaling as reference for conversion. - -- Only usable when supply voltage is between 2.5V and 3.6V. + -- Use supply voltage with 1/3 prescaling as reference for conversion. Only +-- usable when supply voltage is between 2.5V and 3.6V. Supplyonethirdprescaling) with Size => 2; - for REFSEL_Field use + for CONFIG_REFSEL_Field use (Vbg => 0, External => 1, Supplyonehalfprescaling => 2, Supplyonethirdprescaling => 3); -- ADC analog pin selection. - type PSEL_Field is - ( - -- Analog input pins disabled. + type CONFIG_PSEL_Field is + (-- Analog input pins disabled. Disabled, -- Use analog input 0 as analog input. Analoginput0, @@ -235,7 +247,7 @@ package nrf51.ADC is -- Use analog input 7 as analog input. Analoginput7) with Size => 8; - for PSEL_Field use + for CONFIG_PSEL_Field use (Disabled => 0, Analoginput0 => 1, Analoginput1 => 2, @@ -247,16 +259,15 @@ package nrf51.ADC is Analoginput7 => 128); -- ADC external reference pin selection. - type EXTREFSEL_Field is - ( - -- Analog external reference inputs disabled. + type CONFIG_EXTREFSEL_Field is + (-- Analog external reference inputs disabled. None, -- Use analog reference 0 as reference. Analogreference0, -- Use analog reference 1 as reference. Analogreference1) with Size => 2; - for EXTREFSEL_Field use + for CONFIG_EXTREFSEL_Field use (None => 0, Analogreference0 => 1, Analogreference1 => 2); @@ -264,21 +275,22 @@ package nrf51.ADC is -- ADC configuration register. type CONFIG_Register is record -- ADC resolution. - RES : RES_Field := RES_Field_8BIT; + RES : CONFIG_RES_Field := nrf51.ADC.Val_8BIT; -- ADC input selection. - INPSEL : INPSEL_Field := Supplyonethirdprescaling; + INPSEL : CONFIG_INPSEL_Field := + nrf51.ADC.Supplyonethirdprescaling; -- ADC reference selection. - REFSEL : REFSEL_Field := Vbg; + REFSEL : CONFIG_REFSEL_Field := nrf51.ADC.Vbg; -- unspecified Reserved_7_7 : nrf51.Bit := 16#0#; -- ADC analog pin selection. - PSEL : PSEL_Field := Disabled; + PSEL : CONFIG_PSEL_Field := nrf51.ADC.Disabled; -- ADC external reference pin selection. - EXTREFSEL : EXTREFSEL_Field := None; + EXTREFSEL : CONFIG_EXTREFSEL_Field := nrf51.ADC.None; -- unspecified Reserved_18_31 : nrf51.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -291,10 +303,6 @@ package nrf51.ADC is Reserved_18_31 at 0 range 18 .. 31; end record; - --------------------- - -- RESULT_Register -- - --------------------- - subtype RESULT_RESULT_Field is nrf51.UInt10; -- Result of ADC conversion. @@ -304,7 +312,7 @@ package nrf51.ADC is -- unspecified Reserved_10_31 : nrf51.UInt22; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RESULT_Register use record @@ -312,30 +320,25 @@ package nrf51.ADC is Reserved_10_31 at 0 range 10 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.ADC.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -350,39 +353,39 @@ package nrf51.ADC is -- Analog to digital converter. type ADC_Peripheral is record -- Start an ADC conversion. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop ADC. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- ADC conversion complete. - EVENTS_END : nrf51.Word; + EVENTS_END : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- ADC busy register. - BUSY : BUSY_Register; + BUSY : aliased BUSY_Register; -- ADC enable. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- ADC configuration register. - CONFIG : CONFIG_Register; + CONFIG : aliased CONFIG_Register; -- Result of ADC conversion. - RESULT : RESULT_Register; + RESULT : aliased RESULT_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for ADC_Peripheral use record - TASKS_START at 0 range 0 .. 31; - TASKS_STOP at 4 range 0 .. 31; - EVENTS_END at 256 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - BUSY at 1024 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - CONFIG at 1284 range 0 .. 31; - RESULT at 1288 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + EVENTS_END at 16#100# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + BUSY at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + CONFIG at 16#504# range 0 .. 31; + RESULT at 16#508# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- Analog to digital converter. diff --git a/microbit/nrf51/nrf51-amli.ads b/microbit/nrf51/nrf51-amli.ads index 7d7be8d..a8542f4 100644 --- a/microbit/nrf51/nrf51-amli.ads +++ b/microbit/nrf51/nrf51-amli.ads @@ -1,9 +1,40 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; --- with System; +with System; package nrf51.AMLI is pragma Preelaborate; @@ -12,6 +43,360 @@ package nrf51.AMLI is -- Registers -- --------------- + ------------------------------------- + -- AMLI_RAMPRI cluster's Registers -- + ------------------------------------- + + -- Configuration field for RAM block 0. + type CPU0_RAM0_Field is + (-- Priority 0. + Pri0, + -- Priority 2. + Pri2, + -- Priority 4. + Pri4, + -- Priority 6. + Pri6, + -- Priority 8. + Pri8, + -- Priority 10. + Pri10, + -- Priority 12. + Pri12, + -- Priority 14. + Pri14) + with Size => 4; + for CPU0_RAM0_Field use + (Pri0 => 0, + Pri2 => 2, + Pri4 => 4, + Pri6 => 6, + Pri8 => 8, + Pri10 => 10, + Pri12 => 12, + Pri14 => 14); + + -- CPU0_RAMPRI_RAM array + type CPU0_RAMPRI_RAM_Field_Array is array (0 .. 7) of CPU0_RAM0_Field + with Component_Size => 4, Size => 32; + + -- Configurable priority configuration register for CPU0. + type CPU0_RAMPRI_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RAM as a value + Val : nrf51.UInt32; + when True => + -- RAM as an array + Arr : CPU0_RAMPRI_RAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CPU0_RAMPRI_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Configuration field for RAM block 0. + type SPIS1_RAM0_Field is + (-- Priority 0. + Pri0, + -- Priority 2. + Pri2, + -- Priority 4. + Pri4, + -- Priority 6. + Pri6, + -- Priority 8. + Pri8, + -- Priority 10. + Pri10, + -- Priority 12. + Pri12, + -- Priority 14. + Pri14) + with Size => 4; + for SPIS1_RAM0_Field use + (Pri0 => 0, + Pri2 => 2, + Pri4 => 4, + Pri6 => 6, + Pri8 => 8, + Pri10 => 10, + Pri12 => 12, + Pri14 => 14); + + -- SPIS1_RAMPRI_RAM array + type SPIS1_RAMPRI_RAM_Field_Array is array (0 .. 7) of SPIS1_RAM0_Field + with Component_Size => 4, Size => 32; + + -- Configurable priority configuration register for SPIS1. + type SPIS1_RAMPRI_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RAM as a value + Val : nrf51.UInt32; + when True => + -- RAM as an array + Arr : SPIS1_RAMPRI_RAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SPIS1_RAMPRI_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Configuration field for RAM block 0. + type RADIO_RAM0_Field is + (-- Priority 0. + Pri0, + -- Priority 2. + Pri2, + -- Priority 4. + Pri4, + -- Priority 6. + Pri6, + -- Priority 8. + Pri8, + -- Priority 10. + Pri10, + -- Priority 12. + Pri12, + -- Priority 14. + Pri14) + with Size => 4; + for RADIO_RAM0_Field use + (Pri0 => 0, + Pri2 => 2, + Pri4 => 4, + Pri6 => 6, + Pri8 => 8, + Pri10 => 10, + Pri12 => 12, + Pri14 => 14); + + -- RADIO_RAMPRI_RAM array + type RADIO_RAMPRI_RAM_Field_Array is array (0 .. 7) of RADIO_RAM0_Field + with Component_Size => 4, Size => 32; + + -- Configurable priority configuration register for RADIO. + type RADIO_RAMPRI_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RAM as a value + Val : nrf51.UInt32; + when True => + -- RAM as an array + Arr : RADIO_RAMPRI_RAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RADIO_RAMPRI_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Configuration field for RAM block 0. + type ECB_RAM0_Field is + (-- Priority 0. + Pri0, + -- Priority 2. + Pri2, + -- Priority 4. + Pri4, + -- Priority 6. + Pri6, + -- Priority 8. + Pri8, + -- Priority 10. + Pri10, + -- Priority 12. + Pri12, + -- Priority 14. + Pri14) + with Size => 4; + for ECB_RAM0_Field use + (Pri0 => 0, + Pri2 => 2, + Pri4 => 4, + Pri6 => 6, + Pri8 => 8, + Pri10 => 10, + Pri12 => 12, + Pri14 => 14); + + -- ECB_RAMPRI_RAM array + type ECB_RAMPRI_RAM_Field_Array is array (0 .. 7) of ECB_RAM0_Field + with Component_Size => 4, Size => 32; + + -- Configurable priority configuration register for ECB. + type ECB_RAMPRI_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RAM as a value + Val : nrf51.UInt32; + when True => + -- RAM as an array + Arr : ECB_RAMPRI_RAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ECB_RAMPRI_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Configuration field for RAM block 0. + type CCM_RAM0_Field is + (-- Priority 0. + Pri0, + -- Priority 2. + Pri2, + -- Priority 4. + Pri4, + -- Priority 6. + Pri6, + -- Priority 8. + Pri8, + -- Priority 10. + Pri10, + -- Priority 12. + Pri12, + -- Priority 14. + Pri14) + with Size => 4; + for CCM_RAM0_Field use + (Pri0 => 0, + Pri2 => 2, + Pri4 => 4, + Pri6 => 6, + Pri8 => 8, + Pri10 => 10, + Pri12 => 12, + Pri14 => 14); + + -- CCM_RAMPRI_RAM array + type CCM_RAMPRI_RAM_Field_Array is array (0 .. 7) of CCM_RAM0_Field + with Component_Size => 4, Size => 32; + + -- Configurable priority configuration register for CCM. + type CCM_RAMPRI_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RAM as a value + Val : nrf51.UInt32; + when True => + -- RAM as an array + Arr : CCM_RAMPRI_RAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCM_RAMPRI_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Configuration field for RAM block 0. + type AAR_RAM0_Field is + (-- Priority 0. + Pri0, + -- Priority 2. + Pri2, + -- Priority 4. + Pri4, + -- Priority 6. + Pri6, + -- Priority 8. + Pri8, + -- Priority 10. + Pri10, + -- Priority 12. + Pri12, + -- Priority 14. + Pri14) + with Size => 4; + for AAR_RAM0_Field use + (Pri0 => 0, + Pri2 => 2, + Pri4 => 4, + Pri6 => 6, + Pri8 => 8, + Pri10 => 10, + Pri12 => 12, + Pri14 => 14); + + -- AAR_RAMPRI_RAM array + type AAR_RAMPRI_RAM_Field_Array is array (0 .. 7) of AAR_RAM0_Field + with Component_Size => 4, Size => 32; + + -- Configurable priority configuration register for AAR. + type AAR_RAMPRI_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RAM as a value + Val : nrf51.UInt32; + when True => + -- RAM as an array + Arr : AAR_RAMPRI_RAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AAR_RAMPRI_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- RAM configurable priority configuration structure. + type AMLI_RAMPRI_Cluster is record + -- Configurable priority configuration register for CPU0. + CPU0 : aliased CPU0_RAMPRI_Register; + -- Configurable priority configuration register for SPIS1. + SPIS1 : aliased SPIS1_RAMPRI_Register; + -- Configurable priority configuration register for RADIO. + RADIO : aliased RADIO_RAMPRI_Register; + -- Configurable priority configuration register for ECB. + ECB : aliased ECB_RAMPRI_Register; + -- Configurable priority configuration register for CCM. + CCM : aliased CCM_RAMPRI_Register; + -- Configurable priority configuration register for AAR. + AAR : aliased AAR_RAMPRI_Register; + end record + with Size => 192; + + for AMLI_RAMPRI_Cluster use record + CPU0 at 16#0# range 0 .. 31; + SPIS1 at 16#4# range 0 .. 31; + RADIO at 16#8# range 0 .. 31; + ECB at 16#C# range 0 .. 31; + CCM at 16#10# range 0 .. 31; + AAR at 16#14# range 0 .. 31; + end record; + ----------------- -- Peripherals -- ----------------- @@ -19,12 +404,12 @@ package nrf51.AMLI is -- AHB Multi-Layer Interface. type AMLI_Peripheral is record -- RAM configurable priority configuration structure. - RAMPRI : nrf51.Word; + RAMPRI : aliased AMLI_RAMPRI_Cluster; end record with Volatile; for AMLI_Peripheral use record - RAMPRI at 3584 range 0 .. 31; + RAMPRI at 16#E00# range 0 .. 191; end record; -- AHB Multi-Layer Interface. diff --git a/microbit/nrf51/nrf51-ccm.ads b/microbit/nrf51/nrf51-ccm.ads index 28fe877..385b831 100644 --- a/microbit/nrf51/nrf51-ccm.ads +++ b/microbit/nrf51/nrf51-ccm.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,30 +43,25 @@ package nrf51.CCM is -- Registers -- --------------- - --------------------- - -- SHORTS_Register -- - --------------------- - -- Shortcut between ENDKSGEN event and CRYPT task. - type ENDKSGEN_CRYPT_Field is - ( - -- Shortcut disabled. + type SHORTS_ENDKSGEN_CRYPT_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for ENDKSGEN_CRYPT_Field use + for SHORTS_ENDKSGEN_CRYPT_Field use (Disabled => 0, Enabled => 1); -- Shortcuts for the CCM. type SHORTS_Register is record -- Shortcut between ENDKSGEN event and CRYPT task. - ENDKSGEN_CRYPT : ENDKSGEN_CRYPT_Field := Disabled; + ENDKSGEN_CRYPT : SHORTS_ENDKSGEN_CRYPT_Field := nrf51.CCM.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -43,94 +69,86 @@ package nrf51.CCM is Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on ENDKSGEN event. - type ENDKSGEN_Field is - ( - -- Interrupt disabled. + type INTENSET_ENDKSGEN_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ENDKSGEN_Field use + for INTENSET_ENDKSGEN_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ENDKSGEN event. - type ENDKSGEN_Field_1 is - ( - -- Reset value for the field - Endksgen_Field_Reset, + type INTENSET_ENDKSGEN_Field_1 is + (-- Reset value for the field + Intenset_Endksgen_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ENDKSGEN_Field_1 use - (Endksgen_Field_Reset => 0, + for INTENSET_ENDKSGEN_Field_1 use + (Intenset_Endksgen_Field_Reset => 0, Set => 1); -- Enable interrupt on ENDCRYPT event. - type ENDCRYPT_Field is - ( - -- Interrupt disabled. + type INTENSET_ENDCRYPT_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ENDCRYPT_Field use + for INTENSET_ENDCRYPT_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ENDCRYPT event. - type ENDCRYPT_Field_1 is - ( - -- Reset value for the field - Endcrypt_Field_Reset, + type INTENSET_ENDCRYPT_Field_1 is + (-- Reset value for the field + Intenset_Endcrypt_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ENDCRYPT_Field_1 use - (Endcrypt_Field_Reset => 0, + for INTENSET_ENDCRYPT_Field_1 use + (Intenset_Endcrypt_Field_Reset => 0, Set => 1); -- Enable interrupt on ERROR event. - type ERROR_Field is - ( - -- Interrupt disabled. + type INTENSET_ERROR_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ERROR_Field use + for INTENSET_ERROR_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ERROR event. - type ERROR_Field_1 is - ( - -- Reset value for the field - Error_Field_Reset, + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ERROR_Field_1 use - (Error_Field_Reset => 0, + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on ENDKSGEN event. - ENDKSGEN : ENDKSGEN_Field_1 := Endksgen_Field_Reset; + ENDKSGEN : INTENSET_ENDKSGEN_Field_1 := + Intenset_Endksgen_Field_Reset; -- Enable interrupt on ENDCRYPT event. - ENDCRYPT : ENDCRYPT_Field_1 := Endcrypt_Field_Reset; + ENDCRYPT : INTENSET_ENDCRYPT_Field_1 := + Intenset_Endcrypt_Field_Reset; -- Enable interrupt on ERROR event. - ERROR : ERROR_Field_1 := Error_Field_Reset; + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -140,58 +158,86 @@ package nrf51.CCM is Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on ENDKSGEN event. + type INTENCLR_ENDKSGEN_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ENDKSGEN_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on ENDKSGEN event. - type ENDKSGEN_Field_2 is - ( - -- Reset value for the field - Endksgen_Field_Reset, + type INTENCLR_ENDKSGEN_Field_1 is + (-- Reset value for the field + Intenclr_Endksgen_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ENDKSGEN_Field_2 use - (Endksgen_Field_Reset => 0, + for INTENCLR_ENDKSGEN_Field_1 use + (Intenclr_Endksgen_Field_Reset => 0, Clear => 1); -- Disable interrupt on ENDCRYPT event. - type ENDCRYPT_Field_2 is - ( - -- Reset value for the field - Endcrypt_Field_Reset, + type INTENCLR_ENDCRYPT_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ENDCRYPT_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ENDCRYPT event. + type INTENCLR_ENDCRYPT_Field_1 is + (-- Reset value for the field + Intenclr_Endcrypt_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ENDCRYPT_Field_2 use - (Endcrypt_Field_Reset => 0, + for INTENCLR_ENDCRYPT_Field_1 use + (Intenclr_Endcrypt_Field_Reset => 0, Clear => 1); -- Disable interrupt on ERROR event. - type ERROR_Field_2 is - ( - -- Reset value for the field - Error_Field_Reset, + type INTENCLR_ERROR_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ERROR event. + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ERROR_Field_2 use - (Error_Field_Reset => 0, + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on ENDKSGEN event. - ENDKSGEN : ENDKSGEN_Field_2 := Endksgen_Field_Reset; + ENDKSGEN : INTENCLR_ENDKSGEN_Field_1 := + Intenclr_Endksgen_Field_Reset; -- Disable interrupt on ENDCRYPT event. - ENDCRYPT : ENDCRYPT_Field_2 := Endcrypt_Field_Reset; + ENDCRYPT : INTENCLR_ENDCRYPT_Field_1 := + Intenclr_Endcrypt_Field_Reset; -- Disable interrupt on ERROR event. - ERROR : ERROR_Field_2 := Error_Field_Reset; + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -201,19 +247,14 @@ package nrf51.CCM is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------------ - -- MICSTATUS_Register -- - ------------------------ - -- Result of the MIC check performed during the previous CCM RX STARTCRYPT - type MICSTATUS_Field is - ( - -- MIC check failed. + type MICSTATUS_MICSTATUS_Field is + (-- MIC check failed. Checkfailed, -- MIC check passed. Checkpassed) with Size => 1; - for MICSTATUS_Field use + for MICSTATUS_MICSTATUS_Field use (Checkfailed => 0, Checkpassed => 1); @@ -221,11 +262,11 @@ package nrf51.CCM is type MICSTATUS_Register is record -- Read-only. Result of the MIC check performed during the previous CCM -- RX STARTCRYPT - MICSTATUS : MICSTATUS_Field; + MICSTATUS : MICSTATUS_MICSTATUS_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MICSTATUS_Register use record @@ -233,30 +274,25 @@ package nrf51.CCM is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- CCM enable. - type ENABLE_Field is - ( - -- CCM is disabled. + type ENABLE_ENABLE_Field is + (-- CCM is disabled. Disabled, -- CCM is enabled. Enabled) with Size => 2; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 2); -- CCM enable. type ENABLE_Register is record -- CCM enable. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.CCM.Disabled; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -264,30 +300,25 @@ package nrf51.CCM is Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- MODE_Register -- - ------------------- - -- CCM mode operation. - type MODE_Field is - ( - -- CCM mode TX + type MODE_MODE_Field is + (-- CCM mode TX Encryption, -- CCM mode TX Decryption) with Size => 1; - for MODE_Field use + for MODE_MODE_Field use (Encryption => 0, Decryption => 1); -- Operation mode. type MODE_Register is record -- CCM mode operation. - MODE : MODE_Field := Decryption; + MODE : MODE_MODE_Field := nrf51.CCM.Decryption; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MODE_Register use record @@ -295,30 +326,25 @@ package nrf51.CCM is Reserved_1_31 at 0 range 1 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.CCM.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -334,62 +360,62 @@ package nrf51.CCM is type CCM_Peripheral is record -- Start generation of key-stream. This operation will stop by itself -- when completed. - TASKS_KSGEN : nrf51.Word; + TASKS_KSGEN : aliased nrf51.UInt32; -- Start encrypt/decrypt. This operation will stop by itself when -- completed. - TASKS_CRYPT : nrf51.Word; + TASKS_CRYPT : aliased nrf51.UInt32; -- Stop encrypt/decrypt. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Keystream generation completed. - EVENTS_ENDKSGEN : nrf51.Word; + EVENTS_ENDKSGEN : aliased nrf51.UInt32; -- Encrypt/decrypt completed. - EVENTS_ENDCRYPT : nrf51.Word; + EVENTS_ENDCRYPT : aliased nrf51.UInt32; -- Error happened. - EVENTS_ERROR : nrf51.Word; + EVENTS_ERROR : aliased nrf51.UInt32; -- Shortcuts for the CCM. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- CCM RX MIC check result. - MICSTATUS : MICSTATUS_Register; + MICSTATUS : aliased MICSTATUS_Register; -- CCM enable. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- Operation mode. - MODE : MODE_Register; + MODE : aliased MODE_Register; -- Pointer to a data structure holding AES key and NONCE vector. - CNFPTR : nrf51.Word; + CNFPTR : aliased nrf51.UInt32; -- Pointer to the input packet. - INPTR : nrf51.Word; + INPTR : aliased nrf51.UInt32; -- Pointer to the output packet. - OUTPTR : nrf51.Word; + OUTPTR : aliased nrf51.UInt32; -- Pointer to a "scratch" data area used for temporary storage during -- resolution. A minimum of 43 bytes must be reserved. - SCRATCHPTR : nrf51.Word; + SCRATCHPTR : aliased nrf51.UInt32; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for CCM_Peripheral use record - TASKS_KSGEN at 0 range 0 .. 31; - TASKS_CRYPT at 4 range 0 .. 31; - TASKS_STOP at 8 range 0 .. 31; - EVENTS_ENDKSGEN at 256 range 0 .. 31; - EVENTS_ENDCRYPT at 260 range 0 .. 31; - EVENTS_ERROR at 264 range 0 .. 31; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - MICSTATUS at 1024 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - MODE at 1284 range 0 .. 31; - CNFPTR at 1288 range 0 .. 31; - INPTR at 1292 range 0 .. 31; - OUTPTR at 1296 range 0 .. 31; - SCRATCHPTR at 1300 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_KSGEN at 16#0# range 0 .. 31; + TASKS_CRYPT at 16#4# range 0 .. 31; + TASKS_STOP at 16#8# range 0 .. 31; + EVENTS_ENDKSGEN at 16#100# range 0 .. 31; + EVENTS_ENDCRYPT at 16#104# range 0 .. 31; + EVENTS_ERROR at 16#108# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + MICSTATUS at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + MODE at 16#504# range 0 .. 31; + CNFPTR at 16#508# range 0 .. 31; + INPTR at 16#50C# range 0 .. 31; + OUTPTR at 16#510# range 0 .. 31; + SCRATCHPTR at 16#514# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- AES CCM Mode Encryption. diff --git a/microbit/nrf51/nrf51-clock.ads b/microbit/nrf51/nrf51-clock.ads index c9112c5..77c8d05 100644 --- a/microbit/nrf51/nrf51-clock.ads +++ b/microbit/nrf51/nrf51-clock.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,122 +43,112 @@ package nrf51.CLOCK is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on HFCLKSTARTED event. - type HFCLKSTARTED_Field is - ( - -- Interrupt disabled. + type INTENSET_HFCLKSTARTED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for HFCLKSTARTED_Field use + for INTENSET_HFCLKSTARTED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on HFCLKSTARTED event. - type HFCLKSTARTED_Field_1 is - ( - -- Reset value for the field - Hfclkstarted_Field_Reset, + type INTENSET_HFCLKSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Hfclkstarted_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for HFCLKSTARTED_Field_1 use - (Hfclkstarted_Field_Reset => 0, + for INTENSET_HFCLKSTARTED_Field_1 use + (Intenset_Hfclkstarted_Field_Reset => 0, Set => 1); -- Enable interrupt on LFCLKSTARTED event. - type LFCLKSTARTED_Field is - ( - -- Interrupt disabled. + type INTENSET_LFCLKSTARTED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for LFCLKSTARTED_Field use + for INTENSET_LFCLKSTARTED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on LFCLKSTARTED event. - type LFCLKSTARTED_Field_1 is - ( - -- Reset value for the field - Lfclkstarted_Field_Reset, + type INTENSET_LFCLKSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Lfclkstarted_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for LFCLKSTARTED_Field_1 use - (Lfclkstarted_Field_Reset => 0, + for INTENSET_LFCLKSTARTED_Field_1 use + (Intenset_Lfclkstarted_Field_Reset => 0, Set => 1); -- Enable interrupt on DONE event. - type DONE_Field is - ( - -- Interrupt disabled. + type INTENSET_DONE_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for DONE_Field use + for INTENSET_DONE_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on DONE event. - type DONE_Field_1 is - ( - -- Reset value for the field - Done_Field_Reset, + type INTENSET_DONE_Field_1 is + (-- Reset value for the field + Intenset_Done_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for DONE_Field_1 use - (Done_Field_Reset => 0, + for INTENSET_DONE_Field_1 use + (Intenset_Done_Field_Reset => 0, Set => 1); -- Enable interrupt on CTTO event. - type CTTO_Field is - ( - -- Interrupt disabled. + type INTENSET_CTTO_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for CTTO_Field use + for INTENSET_CTTO_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on CTTO event. - type CTTO_Field_1 is - ( - -- Reset value for the field - Ctto_Field_Reset, + type INTENSET_CTTO_Field_1 is + (-- Reset value for the field + Intenset_Ctto_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for CTTO_Field_1 use - (Ctto_Field_Reset => 0, + for INTENSET_CTTO_Field_1 use + (Intenset_Ctto_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on HFCLKSTARTED event. - HFCLKSTARTED : HFCLKSTARTED_Field_1 := Hfclkstarted_Field_Reset; + HFCLKSTARTED : INTENSET_HFCLKSTARTED_Field_1 := + Intenset_Hfclkstarted_Field_Reset; -- Enable interrupt on LFCLKSTARTED event. - LFCLKSTARTED : LFCLKSTARTED_Field_1 := Lfclkstarted_Field_Reset; + LFCLKSTARTED : INTENSET_LFCLKSTARTED_Field_1 := + Intenset_Lfclkstarted_Field_Reset; -- unspecified Reserved_2_2 : nrf51.Bit := 16#0#; -- Enable interrupt on DONE event. - DONE : DONE_Field_1 := Done_Field_Reset; + DONE : INTENSET_DONE_Field_1 := Intenset_Done_Field_Reset; -- Enable interrupt on CTTO event. - CTTO : CTTO_Field_1 := Ctto_Field_Reset; + CTTO : INTENSET_CTTO_Field_1 := Intenset_Ctto_Field_Reset; -- unspecified Reserved_5_31 : nrf51.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -139,74 +160,112 @@ package nrf51.CLOCK is Reserved_5_31 at 0 range 5 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on HFCLKSTARTED event. + type INTENCLR_HFCLKSTARTED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_HFCLKSTARTED_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on HFCLKSTARTED event. - type HFCLKSTARTED_Field_2 is - ( - -- Reset value for the field - Hfclkstarted_Field_Reset, + type INTENCLR_HFCLKSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Hfclkstarted_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for HFCLKSTARTED_Field_2 use - (Hfclkstarted_Field_Reset => 0, + for INTENCLR_HFCLKSTARTED_Field_1 use + (Intenclr_Hfclkstarted_Field_Reset => 0, Clear => 1); -- Disable interrupt on LFCLKSTARTED event. - type LFCLKSTARTED_Field_2 is - ( - -- Reset value for the field - Lfclkstarted_Field_Reset, + type INTENCLR_LFCLKSTARTED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_LFCLKSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on LFCLKSTARTED event. + type INTENCLR_LFCLKSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Lfclkstarted_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for LFCLKSTARTED_Field_2 use - (Lfclkstarted_Field_Reset => 0, + for INTENCLR_LFCLKSTARTED_Field_1 use + (Intenclr_Lfclkstarted_Field_Reset => 0, Clear => 1); -- Disable interrupt on DONE event. - type DONE_Field_2 is - ( - -- Reset value for the field - Done_Field_Reset, + type INTENCLR_DONE_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_DONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on DONE event. + type INTENCLR_DONE_Field_1 is + (-- Reset value for the field + Intenclr_Done_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for DONE_Field_2 use - (Done_Field_Reset => 0, + for INTENCLR_DONE_Field_1 use + (Intenclr_Done_Field_Reset => 0, Clear => 1); -- Disable interrupt on CTTO event. - type CTTO_Field_2 is - ( - -- Reset value for the field - Ctto_Field_Reset, + type INTENCLR_CTTO_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_CTTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on CTTO event. + type INTENCLR_CTTO_Field_1 is + (-- Reset value for the field + Intenclr_Ctto_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for CTTO_Field_2 use - (Ctto_Field_Reset => 0, + for INTENCLR_CTTO_Field_1 use + (Intenclr_Ctto_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on HFCLKSTARTED event. - HFCLKSTARTED : HFCLKSTARTED_Field_2 := Hfclkstarted_Field_Reset; + HFCLKSTARTED : INTENCLR_HFCLKSTARTED_Field_1 := + Intenclr_Hfclkstarted_Field_Reset; -- Disable interrupt on LFCLKSTARTED event. - LFCLKSTARTED : LFCLKSTARTED_Field_2 := Lfclkstarted_Field_Reset; + LFCLKSTARTED : INTENCLR_LFCLKSTARTED_Field_1 := + Intenclr_Lfclkstarted_Field_Reset; -- unspecified Reserved_2_2 : nrf51.Bit := 16#0#; -- Disable interrupt on DONE event. - DONE : DONE_Field_2 := Done_Field_Reset; + DONE : INTENCLR_DONE_Field_1 := Intenclr_Done_Field_Reset; -- Disable interrupt on CTTO event. - CTTO : CTTO_Field_2 := Ctto_Field_Reset; + CTTO : INTENCLR_CTTO_Field_1 := Intenclr_Ctto_Field_Reset; -- unspecified Reserved_5_31 : nrf51.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -218,30 +277,25 @@ package nrf51.CLOCK is Reserved_5_31 at 0 range 5 .. 31; end record; - ----------------------- - -- HFCLKRUN_Register -- - ----------------------- - -- Task HFCLKSTART trigger status. - type STATUS_Field is - ( - -- Task HFCLKSTART has not been triggered. + type HFCLKRUN_STATUS_Field is + (-- Task HFCLKSTART has not been triggered. Nottriggered, -- Task HFCLKSTART has been triggered. Triggered) with Size => 1; - for STATUS_Field use + for HFCLKRUN_STATUS_Field use (Nottriggered => 0, Triggered => 1); -- Task HFCLKSTART trigger status. type HFCLKRUN_Register is record -- Read-only. Task HFCLKSTART trigger status. - STATUS : STATUS_Field; + STATUS : HFCLKRUN_STATUS_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for HFCLKRUN_Register use record @@ -249,47 +303,41 @@ package nrf51.CLOCK is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- HFCLKSTAT_Register -- - ------------------------ - -- Active clock source for the HF clock. - type SRC_Field is - ( - -- Internal 16MHz RC oscillator running and generating the HFCLK clock. + type HFCLKSTAT_SRC_Field is + (-- Internal 16MHz RC oscillator running and generating the HFCLK clock. Rc, - -- External 16MHz/32MHz crystal oscillator running and generating the - -- HFCLK clock. + -- External 16MHz/32MHz crystal oscillator running and generating the HFCLK +-- clock. Xtal) with Size => 1; - for SRC_Field use + for HFCLKSTAT_SRC_Field use (Rc => 0, Xtal => 1); -- State for the HFCLK. - type STATE_Field is - ( - -- HFCLK clock not running. + type HFCLKSTAT_STATE_Field is + (-- HFCLK clock not running. Notrunning, -- HFCLK clock running. Running) with Size => 1; - for STATE_Field use + for HFCLKSTAT_STATE_Field use (Notrunning => 0, Running => 1); -- High frequency clock status. type HFCLKSTAT_Register is record -- Read-only. Active clock source for the HF clock. - SRC : SRC_Field; + SRC : HFCLKSTAT_SRC_Field; -- unspecified Reserved_1_15 : nrf51.UInt15; -- Read-only. State for the HFCLK. - STATE : STATE_Field; + STATE : HFCLKSTAT_STATE_Field; -- unspecified Reserved_17_31 : nrf51.UInt15; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for HFCLKSTAT_Register use record @@ -299,18 +347,25 @@ package nrf51.CLOCK is Reserved_17_31 at 0 range 17 .. 31; end record; - ----------------------- - -- LFCLKRUN_Register -- - ----------------------- + -- Task LFCLKSTART triggered status. + type LFCLKRUN_STATUS_Field is + (-- Task LFCLKSTART has not been triggered. + Nottriggered, + -- Task LFCLKSTART has been triggered. + Triggered) + with Size => 1; + for LFCLKRUN_STATUS_Field use + (Nottriggered => 0, + Triggered => 1); -- Task LFCLKSTART triggered status. type LFCLKRUN_Register is record -- Read-only. Task LFCLKSTART triggered status. - STATUS : STATUS_Field; + STATUS : LFCLKRUN_STATUS_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LFCLKRUN_Register use record @@ -318,39 +373,44 @@ package nrf51.CLOCK is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- LFCLKSTAT_Register -- - ------------------------ - -- Active clock source for the LF clock. - type SRC_Field_1 is - ( - -- Internal 32KiHz RC oscillator running and generating the LFCLK clock. + type LFCLKSTAT_SRC_Field is + (-- Internal 32KiHz RC oscillator running and generating the LFCLK clock. Rc, - -- External 32KiHz crystal oscillator running and generating the LFCLK - -- clock. + -- External 32KiHz crystal oscillator running and generating the LFCLK clock. Xtal, - -- Internal 32KiHz synthesizer from the HFCLK running and generating the - -- LFCLK clock. + -- Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK +-- clock. Synth) with Size => 2; - for SRC_Field_1 use + for LFCLKSTAT_SRC_Field use (Rc => 0, Xtal => 1, Synth => 2); + -- State for the LF clock. + type LFCLKSTAT_STATE_Field is + (-- LFCLK clock not running. + Notrunning, + -- LFCLK clock running. + Running) + with Size => 1; + for LFCLKSTAT_STATE_Field use + (Notrunning => 0, + Running => 1); + -- Low frequency clock status. type LFCLKSTAT_Register is record -- Read-only. Active clock source for the LF clock. - SRC : SRC_Field_1; + SRC : LFCLKSTAT_SRC_Field; -- unspecified Reserved_2_15 : nrf51.UInt14; -- Read-only. State for the LF clock. - STATE : STATE_Field; + STATE : LFCLKSTAT_STATE_Field; -- unspecified Reserved_17_31 : nrf51.UInt15; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LFCLKSTAT_Register use record @@ -360,19 +420,29 @@ package nrf51.CLOCK is Reserved_17_31 at 0 range 17 .. 31; end record; - --------------------------- - -- LFCLKSRCCOPY_Register -- - --------------------------- + -- Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. + type LFCLKSRCCOPY_SRC_Field is + (-- Internal 32KiHz RC oscillator. + Rc, + -- External 32KiHz crystal. + Xtal, + -- Internal 32KiHz synthesizer from HFCLK system clock. + Synth) + with Size => 2; + for LFCLKSRCCOPY_SRC_Field use + (Rc => 0, + Xtal => 1, + Synth => 2); -- Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. type LFCLKSRCCOPY_Register is record -- Read-only. Clock source for the LFCLK clock, set when task LKCLKSTART -- is triggered. - SRC : SRC_Field_1; + SRC : LFCLKSRCCOPY_SRC_Field; -- unspecified Reserved_2_31 : nrf51.UInt30; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LFCLKSRCCOPY_Register use record @@ -380,18 +450,28 @@ package nrf51.CLOCK is Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------------- - -- LFCLKSRC_Register -- - ----------------------- + -- Clock source. + type LFCLKSRC_SRC_Field is + (-- Internal 32KiHz RC oscillator. + Rc, + -- External 32KiHz crystal. + Xtal, + -- Internal 32KiHz synthesizer from HFCLK system clock. + Synth) + with Size => 2; + for LFCLKSRC_SRC_Field use + (Rc => 0, + Xtal => 1, + Synth => 2); -- Clock source for the LFCLK clock. type LFCLKSRC_Register is record -- Clock source. - SRC : SRC_Field_1 := Rc; + SRC : LFCLKSRC_SRC_Field := nrf51.CLOCK.Rc; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LFCLKSRC_Register use record @@ -399,10 +479,6 @@ package nrf51.CLOCK is Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- CTIV_Register -- - ------------------- - subtype CTIV_CTIV_Field is nrf51.UInt7; -- Calibration timer interval. @@ -412,7 +488,7 @@ package nrf51.CLOCK is -- unspecified Reserved_7_31 : nrf51.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CTIV_Register use record @@ -420,30 +496,25 @@ package nrf51.CLOCK is Reserved_7_31 at 0 range 7 .. 31; end record; - ----------------------- - -- XTALFREQ_Register -- - ----------------------- - -- External Xtal frequency selection. - type XTALFREQ_Field is - ( - -- 32MHz xtal is used as source for the HFCLK oscillator. - XTALFREQ_Field_32Mhz, + type XTALFREQ_XTALFREQ_Field is + (-- 32MHz xtal is used as source for the HFCLK oscillator. + Val_32Mhz, -- 16MHz xtal is used as source for the HFCLK oscillator. - XTALFREQ_Field_16Mhz) + Val_16Mhz) with Size => 8; - for XTALFREQ_Field use - (XTALFREQ_Field_32Mhz => 0, - XTALFREQ_Field_16Mhz => 255); + for XTALFREQ_XTALFREQ_Field use + (Val_32Mhz => 0, + Val_16Mhz => 255); -- Crystal frequency. type XTALFREQ_Register is record -- External Xtal frequency selection. - XTALFREQ : XTALFREQ_Field := XTALFREQ_Field_16Mhz; + XTALFREQ : XTALFREQ_XTALFREQ_Field := nrf51.CLOCK.Val_16Mhz; -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#FFFFFF#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for XTALFREQ_Register use record @@ -458,73 +529,73 @@ package nrf51.CLOCK is -- Clock control. type CLOCK_Peripheral is record -- Start HFCLK clock source. - TASKS_HFCLKSTART : nrf51.Word; + TASKS_HFCLKSTART : aliased nrf51.UInt32; -- Stop HFCLK clock source. - TASKS_HFCLKSTOP : nrf51.Word; + TASKS_HFCLKSTOP : aliased nrf51.UInt32; -- Start LFCLK clock source. - TASKS_LFCLKSTART : nrf51.Word; + TASKS_LFCLKSTART : aliased nrf51.UInt32; -- Stop LFCLK clock source. - TASKS_LFCLKSTOP : nrf51.Word; + TASKS_LFCLKSTOP : aliased nrf51.UInt32; -- Start calibration of LFCLK RC oscillator. - TASKS_CAL : nrf51.Word; + TASKS_CAL : aliased nrf51.UInt32; -- Start calibration timer. - TASKS_CTSTART : nrf51.Word; + TASKS_CTSTART : aliased nrf51.UInt32; -- Stop calibration timer. - TASKS_CTSTOP : nrf51.Word; + TASKS_CTSTOP : aliased nrf51.UInt32; -- HFCLK oscillator started. - EVENTS_HFCLKSTARTED : nrf51.Word; + EVENTS_HFCLKSTARTED : aliased nrf51.UInt32; -- LFCLK oscillator started. - EVENTS_LFCLKSTARTED : nrf51.Word; + EVENTS_LFCLKSTARTED : aliased nrf51.UInt32; -- Calibration of LFCLK RC oscillator completed. - EVENTS_DONE : nrf51.Word; + EVENTS_DONE : aliased nrf51.UInt32; -- Calibration timer timeout. - EVENTS_CTTO : nrf51.Word; + EVENTS_CTTO : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Task HFCLKSTART trigger status. - HFCLKRUN : HFCLKRUN_Register; + HFCLKRUN : aliased HFCLKRUN_Register; -- High frequency clock status. - HFCLKSTAT : HFCLKSTAT_Register; + HFCLKSTAT : aliased HFCLKSTAT_Register; -- Task LFCLKSTART triggered status. - LFCLKRUN : LFCLKRUN_Register; + LFCLKRUN : aliased LFCLKRUN_Register; -- Low frequency clock status. - LFCLKSTAT : LFCLKSTAT_Register; + LFCLKSTAT : aliased LFCLKSTAT_Register; -- Clock source for the LFCLK clock, set when task LKCLKSTART is -- triggered. - LFCLKSRCCOPY : LFCLKSRCCOPY_Register; + LFCLKSRCCOPY : aliased LFCLKSRCCOPY_Register; -- Clock source for the LFCLK clock. - LFCLKSRC : LFCLKSRC_Register; + LFCLKSRC : aliased LFCLKSRC_Register; -- Calibration timer interval. - CTIV : CTIV_Register; + CTIV : aliased CTIV_Register; -- Crystal frequency. - XTALFREQ : XTALFREQ_Register; + XTALFREQ : aliased XTALFREQ_Register; end record with Volatile; for CLOCK_Peripheral use record - TASKS_HFCLKSTART at 0 range 0 .. 31; - TASKS_HFCLKSTOP at 4 range 0 .. 31; - TASKS_LFCLKSTART at 8 range 0 .. 31; - TASKS_LFCLKSTOP at 12 range 0 .. 31; - TASKS_CAL at 16 range 0 .. 31; - TASKS_CTSTART at 20 range 0 .. 31; - TASKS_CTSTOP at 24 range 0 .. 31; - EVENTS_HFCLKSTARTED at 256 range 0 .. 31; - EVENTS_LFCLKSTARTED at 260 range 0 .. 31; - EVENTS_DONE at 268 range 0 .. 31; - EVENTS_CTTO at 272 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - HFCLKRUN at 1032 range 0 .. 31; - HFCLKSTAT at 1036 range 0 .. 31; - LFCLKRUN at 1044 range 0 .. 31; - LFCLKSTAT at 1048 range 0 .. 31; - LFCLKSRCCOPY at 1052 range 0 .. 31; - LFCLKSRC at 1304 range 0 .. 31; - CTIV at 1336 range 0 .. 31; - XTALFREQ at 1360 range 0 .. 31; + TASKS_HFCLKSTART at 16#0# range 0 .. 31; + TASKS_HFCLKSTOP at 16#4# range 0 .. 31; + TASKS_LFCLKSTART at 16#8# range 0 .. 31; + TASKS_LFCLKSTOP at 16#C# range 0 .. 31; + TASKS_CAL at 16#10# range 0 .. 31; + TASKS_CTSTART at 16#14# range 0 .. 31; + TASKS_CTSTOP at 16#18# range 0 .. 31; + EVENTS_HFCLKSTARTED at 16#100# range 0 .. 31; + EVENTS_LFCLKSTARTED at 16#104# range 0 .. 31; + EVENTS_DONE at 16#10C# range 0 .. 31; + EVENTS_CTTO at 16#110# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + HFCLKRUN at 16#408# range 0 .. 31; + HFCLKSTAT at 16#40C# range 0 .. 31; + LFCLKRUN at 16#414# range 0 .. 31; + LFCLKSTAT at 16#418# range 0 .. 31; + LFCLKSRCCOPY at 16#41C# range 0 .. 31; + LFCLKSRC at 16#518# range 0 .. 31; + CTIV at 16#538# range 0 .. 31; + XTALFREQ at 16#550# range 0 .. 31; end record; -- Clock control. diff --git a/microbit/nrf51/nrf51-ecb.ads b/microbit/nrf51/nrf51-ecb.ads index 65fe645..a2a6c59 100644 --- a/microbit/nrf51/nrf51-ecb.ads +++ b/microbit/nrf51/nrf51-ecb.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,68 +43,61 @@ package nrf51.ECB is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on ENDECB event. - type ENDECB_Field is - ( - -- Interrupt disabled. + type INTENSET_ENDECB_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ENDECB_Field use + for INTENSET_ENDECB_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ENDECB event. - type ENDECB_Field_1 is - ( - -- Reset value for the field - Endecb_Field_Reset, + type INTENSET_ENDECB_Field_1 is + (-- Reset value for the field + Intenset_Endecb_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ENDECB_Field_1 use - (Endecb_Field_Reset => 0, + for INTENSET_ENDECB_Field_1 use + (Intenset_Endecb_Field_Reset => 0, Set => 1); -- Enable interrupt on ERRORECB event. - type ERRORECB_Field is - ( - -- Interrupt disabled. + type INTENSET_ERRORECB_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ERRORECB_Field use + for INTENSET_ERRORECB_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ERRORECB event. - type ERRORECB_Field_1 is - ( - -- Reset value for the field - Errorecb_Field_Reset, + type INTENSET_ERRORECB_Field_1 is + (-- Reset value for the field + Intenset_Errorecb_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ERRORECB_Field_1 use - (Errorecb_Field_Reset => 0, + for INTENSET_ERRORECB_Field_1 use + (Intenset_Errorecb_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on ENDECB event. - ENDECB : ENDECB_Field_1 := Endecb_Field_Reset; + ENDECB : INTENSET_ENDECB_Field_1 := Intenset_Endecb_Field_Reset; -- Enable interrupt on ERRORECB event. - ERRORECB : ERRORECB_Field_1 := Errorecb_Field_Reset; + ERRORECB : INTENSET_ERRORECB_Field_1 := + Intenset_Errorecb_Field_Reset; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -82,44 +106,61 @@ package nrf51.ECB is Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on ENDECB event. + type INTENCLR_ENDECB_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ENDECB_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on ENDECB event. - type ENDECB_Field_2 is - ( - -- Reset value for the field - Endecb_Field_Reset, + type INTENCLR_ENDECB_Field_1 is + (-- Reset value for the field + Intenclr_Endecb_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ENDECB_Field_2 use - (Endecb_Field_Reset => 0, + for INTENCLR_ENDECB_Field_1 use + (Intenclr_Endecb_Field_Reset => 0, Clear => 1); -- Disable interrupt on ERRORECB event. - type ERRORECB_Field_2 is - ( - -- Reset value for the field - Errorecb_Field_Reset, + type INTENCLR_ERRORECB_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ERRORECB_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ERRORECB event. + type INTENCLR_ERRORECB_Field_1 is + (-- Reset value for the field + Intenclr_Errorecb_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ERRORECB_Field_2 use - (Errorecb_Field_Reset => 0, + for INTENCLR_ERRORECB_Field_1 use + (Intenclr_Errorecb_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on ENDECB event. - ENDECB : ENDECB_Field_2 := Endecb_Field_Reset; + ENDECB : INTENCLR_ENDECB_Field_1 := Intenclr_Endecb_Field_Reset; -- Disable interrupt on ERRORECB event. - ERRORECB : ERRORECB_Field_2 := Errorecb_Field_Reset; + ERRORECB : INTENCLR_ERRORECB_Field_1 := + Intenclr_Errorecb_Field_Reset; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -128,30 +169,25 @@ package nrf51.ECB is Reserved_2_31 at 0 range 2 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.ECB.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -168,34 +204,34 @@ package nrf51.ECB is -- Start ECB block encrypt. If a crypto operation is running, this will -- not initiate a new encryption and the ERRORECB event will be -- triggered. - TASKS_STARTECB : nrf51.Word; + TASKS_STARTECB : aliased nrf51.UInt32; -- Stop current ECB encryption. If a crypto operation is running, this -- will will trigger the ERRORECB event. - TASKS_STOPECB : nrf51.Word; + TASKS_STOPECB : aliased nrf51.UInt32; -- ECB block encrypt complete. - EVENTS_ENDECB : nrf51.Word; + EVENTS_ENDECB : aliased nrf51.UInt32; -- ECB block encrypt aborted due to a STOPECB task or due to an error. - EVENTS_ERRORECB : nrf51.Word; + EVENTS_ERRORECB : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- ECB block encrypt memory pointer. - ECBDATAPTR : nrf51.Word; + ECBDATAPTR : aliased nrf51.UInt32; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for ECB_Peripheral use record - TASKS_STARTECB at 0 range 0 .. 31; - TASKS_STOPECB at 4 range 0 .. 31; - EVENTS_ENDECB at 256 range 0 .. 31; - EVENTS_ERRORECB at 260 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - ECBDATAPTR at 1284 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_STARTECB at 16#0# range 0 .. 31; + TASKS_STOPECB at 16#4# range 0 .. 31; + EVENTS_ENDECB at 16#100# range 0 .. 31; + EVENTS_ERRORECB at 16#104# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ECBDATAPTR at 16#504# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- AES ECB Mode Encryption. diff --git a/microbit/nrf51/nrf51-ficr.ads b/microbit/nrf51/nrf51-ficr.ads index f5f6a83..6a985d2 100644 --- a/microbit/nrf51/nrf51-ficr.ads +++ b/microbit/nrf51/nrf51-ficr.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,30 +43,25 @@ package nrf51.FICR is -- Registers -- --------------- - ------------------- - -- PPFC_Register -- - ------------------- - -- Pre-programmed factory code present. - type PPFC_Field is - ( - -- Present. + type PPFC_PPFC_Field is + (-- Present. Present, -- Not present. Notpresent) with Size => 8; - for PPFC_Field use + for PPFC_PPFC_Field use (Present => 0, Notpresent => 255); -- Pre-programmed factory code present. type PPFC_Register is record -- Read-only. Pre-programmed factory code present. - PPFC : PPFC_Field; + PPFC : PPFC_PPFC_Field; -- unspecified Reserved_8_31 : nrf51.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PPFC_Register use record @@ -43,12 +69,14 @@ package nrf51.FICR is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------------- - -- CONFIGID_Register -- - ----------------------- + -- Deprecated array of size of RAM block in bytes. This name is kept for backward compatinility purposes. Use SIZERAMBLOCKS instead. - subtype CONFIGID_HWID_Field is nrf51.Short; - subtype CONFIGID_FWID_Field is nrf51.Short; + -- Deprecated array of size of RAM block in bytes. This name is kept for + -- backward compatinility purposes. Use SIZERAMBLOCKS instead. + type SIZERAMBLOCK_Registers is array (0 .. 3) of nrf51.UInt32; + + subtype CONFIGID_HWID_Field is nrf51.UInt16; + subtype CONFIGID_FWID_Field is nrf51.UInt16; -- Configuration identifier. type CONFIGID_Register is record @@ -57,7 +85,7 @@ package nrf51.FICR is -- Read-only. Firmware Identification Number pre-loaded into the flash. FWID : CONFIGID_FWID_Field; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIGID_Register use record @@ -68,42 +96,37 @@ package nrf51.FICR is -- Device identifier. -- Device identifier. - type DEVICEID_Registers is array (0 .. 1) of nrf51.Word; + type DEVICEID_Registers is array (0 .. 1) of nrf51.UInt32; -- Encryption root. -- Encryption root. - type ER_Registers is array (0 .. 3) of nrf51.Word; + type ER_Registers is array (0 .. 3) of nrf51.UInt32; -- Identity root. -- Identity root. - type IR_Registers is array (0 .. 3) of nrf51.Word; - - ----------------------------- - -- DEVICEADDRTYPE_Register -- - ----------------------------- + type IR_Registers is array (0 .. 3) of nrf51.UInt32; -- Device address type. - type DEVICEADDRTYPE_Field is - ( - -- Public address. + type DEVICEADDRTYPE_DEVICEADDRTYPE_Field is + (-- Public address. Public, -- Random address. Random) with Size => 1; - for DEVICEADDRTYPE_Field use + for DEVICEADDRTYPE_DEVICEADDRTYPE_Field use (Public => 0, Random => 1); -- Device address type. type DEVICEADDRTYPE_Register is record -- Read-only. Device address type. - DEVICEADDRTYPE : DEVICEADDRTYPE_Field; + DEVICEADDRTYPE : DEVICEADDRTYPE_DEVICEADDRTYPE_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DEVICEADDRTYPE_Register use record @@ -114,48 +137,42 @@ package nrf51.FICR is -- Device address. -- Device address. - type DEVICEADDR_Registers is array (0 .. 1) of nrf51.Word; - - ------------------------- - -- OVERRIDEEN_Register -- - ------------------------- + type DEVICEADDR_Registers is array (0 .. 1) of nrf51.UInt32; -- Override default values for NRF_1Mbit mode. - type NRF_1MBIT_Field is - ( - -- Override the default values for NRF_1Mbit mode. + type OVERRIDEEN_NRF_1MBIT_Field is + (-- Override the default values for NRF_1Mbit mode. Override, -- Do not override the default values for NRF_1Mbit mode. Notoverride) with Size => 1; - for NRF_1MBIT_Field use + for OVERRIDEEN_NRF_1MBIT_Field use (Override => 0, Notoverride => 1); -- Override default values for BLE_1Mbit mode. - type BLE_1MBIT_Field is - ( - -- Override the default values for BLE_1Mbit mode. + type OVERRIDEEN_BLE_1MBIT_Field is + (-- Override the default values for BLE_1Mbit mode. Override, -- Do not override the default values for BLE_1Mbit mode. Notoverride) with Size => 1; - for BLE_1MBIT_Field use + for OVERRIDEEN_BLE_1MBIT_Field use (Override => 0, Notoverride => 1); -- Radio calibration override enable. type OVERRIDEEN_Register is record -- Read-only. Override default values for NRF_1Mbit mode. - NRF_1MBIT : NRF_1MBIT_Field; + NRF_1MBIT : OVERRIDEEN_NRF_1MBIT_Field; -- unspecified Reserved_1_2 : nrf51.UInt2; -- Read-only. Override default values for BLE_1Mbit mode. - BLE_1MBIT : BLE_1MBIT_Field; + BLE_1MBIT : OVERRIDEEN_BLE_1MBIT_Field; -- unspecified Reserved_4_31 : nrf51.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OVERRIDEEN_Register use record @@ -168,70 +185,85 @@ package nrf51.FICR is -- Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit mode. -- Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit mode. - type NRF_1MBIT_Registers is array (0 .. 4) of nrf51.Word; + type NRF_1MBIT_Registers is array (0 .. 4) of nrf51.UInt32; -- Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode. -- Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode. - type BLE_1MBIT_Registers is array (0 .. 4) of nrf51.Word; + type BLE_1MBIT_Registers is array (0 .. 4) of nrf51.UInt32; ----------------- -- Peripherals -- ----------------- + type FICR_Disc is + (S, + Default); + -- Factory Information Configuration. - type FICR_Peripheral is record + type FICR_Peripheral + (Discriminent : FICR_Disc := S) + is record -- Code memory page size in bytes. - CODEPAGESIZE : nrf51.Word; + CODEPAGESIZE : aliased nrf51.UInt32; -- Code memory size in pages. - CODESIZE : nrf51.Word; + CODESIZE : aliased nrf51.UInt32; -- Length of code region 0 in bytes. - CLENR0 : nrf51.Word; + CLENR0 : aliased nrf51.UInt32; -- Pre-programmed factory code present. - PPFC : PPFC_Register; + PPFC : aliased PPFC_Register; -- Number of individualy controllable RAM blocks. - NUMRAMBLOCK : nrf51.Word; - -- Size of RAM blocks in bytes. - SIZERAMBLOCKS : nrf51.Word; + NUMRAMBLOCK : aliased nrf51.UInt32; -- Configuration identifier. - CONFIGID : CONFIGID_Register; + CONFIGID : aliased CONFIGID_Register; -- Device identifier. - DEVICEID : DEVICEID_Registers; + DEVICEID : aliased DEVICEID_Registers; -- Encryption root. - ER : ER_Registers; + ER : aliased ER_Registers; -- Identity root. - IR : IR_Registers; + IR : aliased IR_Registers; -- Device address type. - DEVICEADDRTYPE : DEVICEADDRTYPE_Register; + DEVICEADDRTYPE : aliased DEVICEADDRTYPE_Register; -- Device address. - DEVICEADDR : DEVICEADDR_Registers; + DEVICEADDR : aliased DEVICEADDR_Registers; -- Radio calibration override enable. - OVERRIDEEN : OVERRIDEEN_Register; + OVERRIDEEN : aliased OVERRIDEEN_Register; -- Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit -- mode. - NRF_1MBIT : NRF_1MBIT_Registers; + NRF_1MBIT : aliased NRF_1MBIT_Registers; -- Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit -- mode. - BLE_1MBIT : BLE_1MBIT_Registers; + BLE_1MBIT : aliased BLE_1MBIT_Registers; + case Discriminent is + when S => + -- Size of RAM blocks in bytes. + SIZERAMBLOCKS : aliased nrf51.UInt32; + when Default => + -- Deprecated array of size of RAM block in bytes. This name is + -- kept for backward compatinility purposes. Use SIZERAMBLOCKS + -- instead. + SIZERAMBLOCK : aliased SIZERAMBLOCK_Registers; + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for FICR_Peripheral use record - CODEPAGESIZE at 16 range 0 .. 31; - CODESIZE at 20 range 0 .. 31; - CLENR0 at 40 range 0 .. 31; - PPFC at 44 range 0 .. 31; - NUMRAMBLOCK at 52 range 0 .. 31; - SIZERAMBLOCKS at 56 range 0 .. 31; - CONFIGID at 92 range 0 .. 31; - DEVICEID at 96 range 0 .. 63; - ER at 128 range 0 .. 127; - IR at 144 range 0 .. 127; - DEVICEADDRTYPE at 160 range 0 .. 31; - DEVICEADDR at 164 range 0 .. 63; - OVERRIDEEN at 172 range 0 .. 31; - NRF_1MBIT at 176 range 0 .. 159; - BLE_1MBIT at 236 range 0 .. 159; + CODEPAGESIZE at 16#10# range 0 .. 31; + CODESIZE at 16#14# range 0 .. 31; + CLENR0 at 16#28# range 0 .. 31; + PPFC at 16#2C# range 0 .. 31; + NUMRAMBLOCK at 16#34# range 0 .. 31; + CONFIGID at 16#5C# range 0 .. 31; + DEVICEID at 16#60# range 0 .. 63; + ER at 16#80# range 0 .. 127; + IR at 16#90# range 0 .. 127; + DEVICEADDRTYPE at 16#A0# range 0 .. 31; + DEVICEADDR at 16#A4# range 0 .. 63; + OVERRIDEEN at 16#AC# range 0 .. 31; + NRF_1MBIT at 16#B0# range 0 .. 159; + BLE_1MBIT at 16#EC# range 0 .. 159; + SIZERAMBLOCKS at 16#38# range 0 .. 31; + SIZERAMBLOCK at 16#38# range 0 .. 127; end record; -- Factory Information Configuration. diff --git a/microbit/nrf51/nrf51-gpio.ads b/microbit/nrf51/nrf51-gpio.ads index 7f8393a..1c34624 100644 --- a/microbit/nrf51/nrf51-gpio.ads +++ b/microbit/nrf51/nrf51-gpio.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,24 +43,19 @@ package nrf51.GPIO is -- Registers -- --------------- - ------------------ - -- OUT_Register -- - ------------------ - -- Pin 0. - type PIN0_Field is - ( - -- Pin driver is low. + type OUT_PIN0_Field is + (-- Pin driver is low. Low, -- Pin driver is high. High) with Size => 1; - for PIN0_Field use + for OUT_PIN0_Field use (Low => 0, High => 1); -- OUT_PIN array - type OUT_PIN_Field_Array is array (0 .. 31) of PIN0_Field + type OUT_PIN_Field_Array is array (0 .. 31) of OUT_PIN0_Field with Component_Size => 1, Size => 32; -- Write GPIO port. @@ -39,13 +65,13 @@ package nrf51.GPIO is case As_Array is when False => -- PIN as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PIN as an array Arr : OUT_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OUT_Register use record @@ -53,24 +79,30 @@ package nrf51.GPIO is Arr at 0 range 0 .. 31; end record; - --------------------- - -- OUTSET_Register -- - --------------------- + -- Pin 0. + type OUTSET_PIN0_Field is + (-- Pin driver is low. + Low, + -- Pin driver is high. + High) + with Size => 1; + for OUTSET_PIN0_Field use + (Low => 0, + High => 1); -- Pin 0. - type PIN0_Field_1 is - ( - -- Reset value for the field - Pin0_Field_Reset, + type OUTSET_PIN0_Field_1 is + (-- Reset value for the field + Outset_Pin0_Field_Reset, -- Set pin driver high. Set) with Size => 1; - for PIN0_Field_1 use - (Pin0_Field_Reset => 0, + for OUTSET_PIN0_Field_1 use + (Outset_Pin0_Field_Reset => 0, Set => 1); -- OUTSET_PIN array - type OUTSET_PIN_Field_Array is array (0 .. 31) of PIN0_Field_1 + type OUTSET_PIN_Field_Array is array (0 .. 31) of OUTSET_PIN0_Field_1 with Component_Size => 1, Size => 32; -- Set individual bits in GPIO port. @@ -80,13 +112,13 @@ package nrf51.GPIO is case As_Array is when False => -- PIN as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PIN as an array Arr : OUTSET_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OUTSET_Register use record @@ -94,24 +126,30 @@ package nrf51.GPIO is Arr at 0 range 0 .. 31; end record; - --------------------- - -- OUTCLR_Register -- - --------------------- + -- Pin 0. + type OUTCLR_PIN0_Field is + (-- Pin driver is low. + Low, + -- Pin driver is high. + High) + with Size => 1; + for OUTCLR_PIN0_Field use + (Low => 0, + High => 1); -- Pin 0. - type PIN0_Field_2 is - ( - -- Reset value for the field - Pin0_Field_Reset, + type OUTCLR_PIN0_Field_1 is + (-- Reset value for the field + Outclr_Pin0_Field_Reset, -- Set pin driver low. Clear) with Size => 1; - for PIN0_Field_2 use - (Pin0_Field_Reset => 0, + for OUTCLR_PIN0_Field_1 use + (Outclr_Pin0_Field_Reset => 0, Clear => 1); -- OUTCLR_PIN array - type OUTCLR_PIN_Field_Array is array (0 .. 31) of PIN0_Field_2 + type OUTCLR_PIN_Field_Array is array (0 .. 31) of OUTCLR_PIN0_Field_1 with Component_Size => 1, Size => 32; -- Clear individual bits in GPIO port. @@ -121,13 +159,13 @@ package nrf51.GPIO is case As_Array is when False => -- PIN as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PIN as an array Arr : OUTCLR_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OUTCLR_Register use record @@ -135,12 +173,19 @@ package nrf51.GPIO is Arr at 0 range 0 .. 31; end record; - ----------------- - -- IN_Register -- - ----------------- + -- Pin 0. + type IN_PIN0_Field is + (-- Pin input is low. + Low, + -- Pin input is high. + High) + with Size => 1; + for IN_PIN0_Field use + (Low => 0, + High => 1); -- IN_PIN array - type IN_PIN_Field_Array is array (0 .. 31) of PIN0_Field + type IN_PIN_Field_Array is array (0 .. 31) of IN_PIN0_Field with Component_Size => 1, Size => 32; -- Read GPIO port. @@ -150,13 +195,13 @@ package nrf51.GPIO is case As_Array is when False => -- PIN as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PIN as an array Arr : IN_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for IN_Register use record @@ -164,24 +209,19 @@ package nrf51.GPIO is Arr at 0 range 0 .. 31; end record; - ------------------ - -- DIR_Register -- - ------------------ - -- Pin 0. - type PIN0_Field_3 is - ( - -- Pin set as input. + type DIR_PIN0_Field is + (-- Pin set as input. Input, -- Pin set as output. Output) with Size => 1; - for PIN0_Field_3 use + for DIR_PIN0_Field use (Input => 0, Output => 1); -- DIR_PIN array - type DIR_PIN_Field_Array is array (0 .. 31) of PIN0_Field_3 + type DIR_PIN_Field_Array is array (0 .. 31) of DIR_PIN0_Field with Component_Size => 1, Size => 32; -- Direction of GPIO pins. @@ -191,13 +231,13 @@ package nrf51.GPIO is case As_Array is when False => -- PIN as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PIN as an array Arr : DIR_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DIR_Register use record @@ -205,12 +245,30 @@ package nrf51.GPIO is Arr at 0 range 0 .. 31; end record; - --------------------- - -- DIRSET_Register -- - --------------------- + -- Set as output pin 0. + type DIRSET_PIN0_Field is + (-- Pin set as input. + Input, + -- Pin set as output. + Output) + with Size => 1; + for DIRSET_PIN0_Field use + (Input => 0, + Output => 1); + + -- Set as output pin 0. + type DIRSET_PIN0_Field_1 is + (-- Reset value for the field + Dirset_Pin0_Field_Reset, + -- Set pin as output. + Set) + with Size => 1; + for DIRSET_PIN0_Field_1 use + (Dirset_Pin0_Field_Reset => 0, + Set => 1); -- DIRSET_PIN array - type DIRSET_PIN_Field_Array is array (0 .. 31) of PIN0_Field_1 + type DIRSET_PIN_Field_Array is array (0 .. 31) of DIRSET_PIN0_Field_1 with Component_Size => 1, Size => 32; -- DIR set register. @@ -220,13 +278,13 @@ package nrf51.GPIO is case As_Array is when False => -- PIN as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PIN as an array Arr : DIRSET_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DIRSET_Register use record @@ -234,12 +292,30 @@ package nrf51.GPIO is Arr at 0 range 0 .. 31; end record; - --------------------- - -- DIRCLR_Register -- - --------------------- + -- Set as input pin 0. + type DIRCLR_PIN0_Field is + (-- Pin set as input. + Input, + -- Pin set as output. + Output) + with Size => 1; + for DIRCLR_PIN0_Field use + (Input => 0, + Output => 1); + + -- Set as input pin 0. + type DIRCLR_PIN0_Field_1 is + (-- Reset value for the field + Dirclr_Pin0_Field_Reset, + -- Set pin as input. + Clear) + with Size => 1; + for DIRCLR_PIN0_Field_1 use + (Dirclr_Pin0_Field_Reset => 0, + Clear => 1); -- DIRCLR_PIN array - type DIRCLR_PIN_Field_Array is array (0 .. 31) of PIN0_Field_2 + type DIRCLR_PIN_Field_Array is array (0 .. 31) of DIRCLR_PIN0_Field_1 with Component_Size => 1, Size => 32; -- DIR clear register. @@ -249,13 +325,13 @@ package nrf51.GPIO is case As_Array is when False => -- PIN as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PIN as an array Arr : DIRCLR_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DIRCLR_Register use record @@ -263,53 +339,45 @@ package nrf51.GPIO is Arr at 0 range 0 .. 31; end record; - ---------------------- - -- PIN_CNF_Register -- - ---------------------- - -- Pin direction. - type DIR_Field is - ( - -- Configure pin as an input pin. + type PIN_CNF_DIR_Field is + (-- Configure pin as an input pin. Input, -- Configure pin as an output pin. Output) with Size => 1; - for DIR_Field use + for PIN_CNF_DIR_Field use (Input => 0, Output => 1); -- Connect or disconnect input path. - type INPUT_Field is - ( - -- Connect input pin. + type PIN_CNF_INPUT_Field is + (-- Connect input pin. Connect, -- Disconnect input pin. Disconnect) with Size => 1; - for INPUT_Field use + for PIN_CNF_INPUT_Field use (Connect => 0, Disconnect => 1); -- Pull-up or -down configuration. - type PULL_Field is - ( - -- No pull. + type PIN_CNF_PULL_Field is + (-- No pull. Disabled, -- Pulldown on pin. Pulldown, -- Pullup on pin. Pullup) with Size => 2; - for PULL_Field use + for PIN_CNF_PULL_Field use (Disabled => 0, Pulldown => 1, Pullup => 3); -- Drive configuration. - type DRIVE_Field is - ( - -- Standard '0', Standard '1'. + type PIN_CNF_DRIVE_Field is + (-- Standard '0', Standard '1'. S0S1, -- High '0', Standard '1'. H0S1, @@ -326,7 +394,7 @@ package nrf51.GPIO is -- High '0', Disconnected '1'. H0D1) with Size => 3; - for DRIVE_Field use + for PIN_CNF_DRIVE_Field use (S0S1 => 0, H0S1 => 1, S0H1 => 2, @@ -337,16 +405,15 @@ package nrf51.GPIO is H0D1 => 7); -- Pin sensing mechanism. - type SENSE_Field is - ( - -- Disabled. + type PIN_CNF_SENSE_Field is + (-- Disabled. Disabled, -- Wakeup on high level. High, -- Wakeup on low level. Low) with Size => 2; - for SENSE_Field use + for PIN_CNF_SENSE_Field use (Disabled => 0, High => 2, Low => 3); @@ -354,23 +421,23 @@ package nrf51.GPIO is -- Configuration of GPIO pins. type PIN_CNF_Register is record -- Pin direction. - DIR : DIR_Field := Input; + DIR : PIN_CNF_DIR_Field := nrf51.GPIO.Input; -- Connect or disconnect input path. - INPUT : INPUT_Field := Disconnect; + INPUT : PIN_CNF_INPUT_Field := nrf51.GPIO.Disconnect; -- Pull-up or -down configuration. - PULL : PULL_Field := Disabled; + PULL : PIN_CNF_PULL_Field := nrf51.GPIO.Disabled; -- unspecified Reserved_4_7 : nrf51.UInt4 := 16#0#; -- Drive configuration. - DRIVE : DRIVE_Field := S0S1; + DRIVE : PIN_CNF_DRIVE_Field := nrf51.GPIO.S0S1; -- unspecified Reserved_11_15 : nrf51.UInt5 := 16#0#; -- Pin sensing mechanism. - SENSE : SENSE_Field := Disabled; + SENSE : PIN_CNF_SENSE_Field := nrf51.GPIO.Disabled; -- unspecified Reserved_18_31 : nrf51.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PIN_CNF_Register use record @@ -394,33 +461,33 @@ package nrf51.GPIO is -- General purpose input and output. type GPIO_Peripheral is record -- Write GPIO port. - OUT_k : OUT_Register; + OUT_k : aliased OUT_Register; -- Set individual bits in GPIO port. - OUTSET : OUTSET_Register; + OUTSET : aliased OUTSET_Register; -- Clear individual bits in GPIO port. - OUTCLR : OUTCLR_Register; + OUTCLR : aliased OUTCLR_Register; -- Read GPIO port. - IN_k : IN_Register; + IN_k : aliased IN_Register; -- Direction of GPIO pins. - DIR : DIR_Register; + DIR : aliased DIR_Register; -- DIR set register. - DIRSET : DIRSET_Register; + DIRSET : aliased DIRSET_Register; -- DIR clear register. - DIRCLR : DIRCLR_Register; + DIRCLR : aliased DIRCLR_Register; -- Configuration of GPIO pins. - PIN_CNF : PIN_CNF_Registers; + PIN_CNF : aliased PIN_CNF_Registers; end record with Volatile; for GPIO_Peripheral use record - OUT_k at 1284 range 0 .. 31; - OUTSET at 1288 range 0 .. 31; - OUTCLR at 1292 range 0 .. 31; - IN_k at 1296 range 0 .. 31; - DIR at 1300 range 0 .. 31; - DIRSET at 1304 range 0 .. 31; - DIRCLR at 1308 range 0 .. 31; - PIN_CNF at 1792 range 0 .. 1023; + OUT_k at 16#504# range 0 .. 31; + OUTSET at 16#508# range 0 .. 31; + OUTCLR at 16#50C# range 0 .. 31; + IN_k at 16#510# range 0 .. 31; + DIR at 16#514# range 0 .. 31; + DIRSET at 16#518# range 0 .. 31; + DIRCLR at 16#51C# range 0 .. 31; + PIN_CNF at 16#700# range 0 .. 1023; end record; -- General purpose input and output. diff --git a/microbit/nrf51/nrf51-gpiote.ads b/microbit/nrf51/nrf51-gpiote.ads index 777bc1c..0097cfd 100644 --- a/microbit/nrf51/nrf51-gpiote.ads +++ b/microbit/nrf51/nrf51-gpiote.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -15,47 +46,37 @@ package nrf51.GPIOTE is -- Tasks asssociated with GPIOTE channels. -- Tasks asssociated with GPIOTE channels. - type TASKS_OUT_Registers is array (0 .. 3) of nrf51.Word; + type TASKS_OUT_Registers is array (0 .. 3) of nrf51.UInt32; -- Tasks asssociated with GPIOTE channels. -- Tasks asssociated with GPIOTE channels. - type EVENTS_IN_Registers is array (0 .. 3) of nrf51.Word; - - ----------------------- - -- INTENSET_Register -- - ----------------------- + type EVENTS_IN_Registers is array (0 .. 3) of nrf51.UInt32; -- Enable interrupt on IN[0] event. - type IN0_Field is - ( - -- Interrupt disabled. + type INTENSET_IN0_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for IN0_Field use + for INTENSET_IN0_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on IN[0] event. - type IN0_Field_1 is - ( - -- Reset value for the field - In0_Field_Reset, + type INTENSET_IN0_Field_1 is + (-- Reset value for the field + Intenset_In0_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for IN0_Field_1 use - (In0_Field_Reset => 0, + for INTENSET_IN0_Field_1 use + (Intenset_In0_Field_Reset => 0, Set => 1); - ----------------- - -- INTENSET.IN -- - ----------------- - -- INTENSET_IN array - type INTENSET_IN_Field_Array is array (0 .. 3) of IN0_Field_1 + type INTENSET_IN_Field_Array is array (0 .. 3) of INTENSET_IN0_Field_1 with Component_Size => 1, Size => 4; -- Type definition for INTENSET_IN @@ -79,27 +100,25 @@ package nrf51.GPIOTE is end record; -- Enable interrupt on PORT event. - type PORT_Field is - ( - -- Interrupt disabled. + type INTENSET_PORT_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for PORT_Field use + for INTENSET_PORT_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on PORT event. - type PORT_Field_1 is - ( - -- Reset value for the field - Port_Field_Reset, + type INTENSET_PORT_Field_1 is + (-- Reset value for the field + Intenset_Port_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for PORT_Field_1 use - (Port_Field_Reset => 0, + for INTENSET_PORT_Field_1 use + (Intenset_Port_Field_Reset => 0, Set => 1); -- Interrupt enable set register. @@ -109,9 +128,9 @@ package nrf51.GPIOTE is -- unspecified Reserved_4_30 : nrf51.UInt27 := 16#0#; -- Enable interrupt on PORT event. - PORT : PORT_Field_1 := Port_Field_Reset; + PORT : INTENSET_PORT_Field_1 := Intenset_Port_Field_Reset; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -120,28 +139,30 @@ package nrf51.GPIOTE is PORT at 0 range 31 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on IN[0] event. + type INTENCLR_IN0_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_IN0_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on IN[0] event. - type IN0_Field_2 is - ( - -- Reset value for the field - In0_Field_Reset, + type INTENCLR_IN0_Field_1 is + (-- Reset value for the field + Intenclr_In0_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for IN0_Field_2 use - (In0_Field_Reset => 0, + for INTENCLR_IN0_Field_1 use + (Intenclr_In0_Field_Reset => 0, Clear => 1); - ----------------- - -- INTENCLR.IN -- - ----------------- - -- INTENCLR_IN array - type INTENCLR_IN_Field_Array is array (0 .. 3) of IN0_Field_2 + type INTENCLR_IN_Field_Array is array (0 .. 3) of INTENCLR_IN0_Field_1 with Component_Size => 1, Size => 4; -- Type definition for INTENCLR_IN @@ -165,15 +186,25 @@ package nrf51.GPIOTE is end record; -- Disable interrupt on PORT event. - type PORT_Field_2 is - ( - -- Reset value for the field - Port_Field_Reset, + type INTENCLR_PORT_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_PORT_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on PORT event. + type INTENCLR_PORT_Field_1 is + (-- Reset value for the field + Intenclr_Port_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for PORT_Field_2 use - (Port_Field_Reset => 0, + for INTENCLR_PORT_Field_1 use + (Intenclr_Port_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. @@ -183,9 +214,9 @@ package nrf51.GPIOTE is -- unspecified Reserved_4_30 : nrf51.UInt27 := 16#0#; -- Disable interrupt on PORT event. - PORT : PORT_Field_2 := Port_Field_Reset; + PORT : INTENCLR_PORT_Field_1 := Intenclr_Port_Field_Reset; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -194,21 +225,16 @@ package nrf51.GPIOTE is PORT at 0 range 31 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- - -- Mode - type MODE_Field is - ( - -- Disabled. + type CONFIG_MODE_Field is + (-- Disabled. Disabled, -- Channel configure in event mode. Event, -- Channel configure in task mode. Task_k) with Size => 2; - for MODE_Field use + for CONFIG_MODE_Field use (Disabled => 0, Event => 1, Task_k => 3); @@ -217,9 +243,8 @@ package nrf51.GPIOTE is -- Effects on output when in Task mode, or events on input that generates -- an event. - type POLARITY_Field is - ( - -- No task or event. + type CONFIG_POLARITY_Field is + (-- No task or event. None, -- Low to high. Lotohi, @@ -228,7 +253,7 @@ package nrf51.GPIOTE is -- Toggle. Toggle) with Size => 2; - for POLARITY_Field use + for CONFIG_POLARITY_Field use (None => 0, Lotohi => 1, Hitolo => 2, @@ -236,21 +261,20 @@ package nrf51.GPIOTE is -- Initial value of the output when the GPIOTE channel is configured as a -- Task. - type OUTINIT_Field is - ( - -- Initial low output when in task mode. + type CONFIG_OUTINIT_Field is + (-- Initial low output when in task mode. Low, -- Initial high output when in task mode. High) with Size => 1; - for OUTINIT_Field use + for CONFIG_OUTINIT_Field use (Low => 0, High => 1); -- Channel configuration registers. type CONFIG_Register is record -- Mode - MODE : MODE_Field := Disabled; + MODE : CONFIG_MODE_Field := nrf51.GPIOTE.Disabled; -- unspecified Reserved_2_7 : nrf51.UInt6 := 16#0#; -- Pin select. @@ -259,16 +283,16 @@ package nrf51.GPIOTE is Reserved_13_15 : nrf51.UInt3 := 16#0#; -- Effects on output when in Task mode, or events on input that -- generates an event. - POLARITY : POLARITY_Field := None; + POLARITY : CONFIG_POLARITY_Field := nrf51.GPIOTE.None; -- unspecified Reserved_18_19 : nrf51.UInt2 := 16#0#; -- Initial value of the output when the GPIOTE channel is configured as -- a Task. - OUTINIT : OUTINIT_Field := Low; + OUTINIT : CONFIG_OUTINIT_Field := nrf51.GPIOTE.Low; -- unspecified Reserved_21_31 : nrf51.UInt11 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -285,30 +309,25 @@ package nrf51.GPIOTE is -- Channel configuration registers. type CONFIG_Registers is array (0 .. 3) of CONFIG_Register; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.GPIOTE.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -323,30 +342,30 @@ package nrf51.GPIOTE is -- GPIO tasks and events. type GPIOTE_Peripheral is record -- Tasks asssociated with GPIOTE channels. - TASKS_OUT : TASKS_OUT_Registers; + TASKS_OUT : aliased TASKS_OUT_Registers; -- Tasks asssociated with GPIOTE channels. - EVENTS_IN : EVENTS_IN_Registers; + EVENTS_IN : aliased EVENTS_IN_Registers; -- Event generated from multiple pins. - EVENTS_PORT : nrf51.Word; + EVENTS_PORT : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Channel configuration registers. - CONFIG : CONFIG_Registers; + CONFIG : aliased CONFIG_Registers; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for GPIOTE_Peripheral use record - TASKS_OUT at 0 range 0 .. 127; - EVENTS_IN at 256 range 0 .. 127; - EVENTS_PORT at 380 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - CONFIG at 1296 range 0 .. 127; - POWER at 4092 range 0 .. 31; + TASKS_OUT at 16#0# range 0 .. 127; + EVENTS_IN at 16#100# range 0 .. 127; + EVENTS_PORT at 16#17C# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + CONFIG at 16#510# range 0 .. 127; + POWER at 16#FFC# range 0 .. 31; end record; -- GPIO tasks and events. diff --git a/microbit/nrf51/nrf51-interrupts.adb b/microbit/nrf51/nrf51-interrupts.adb deleted file mode 100644 index 5f5d815..0000000 --- a/microbit/nrf51/nrf51-interrupts.adb +++ /dev/null @@ -1,39 +0,0 @@ -with Interfaces; use Interfaces; -with System; - -package body nrf51.Interrupts is - procedure Enable (I : Interrupt) is - ISER : Interfaces.Unsigned_32; - pragma Volatile (ISER); - for ISER'Address use System'To_Address (16#E000_E100#); - begin - ISER := Shift_Left (1, Interrupt'Pos (I)); - end Enable; - - procedure Disable (I : Interrupt) is - ICER : Interfaces.Unsigned_32; - pragma Volatile (ICER); - for ICER'Address use System'To_Address (16#E000_E180#); - begin - ICER := Shift_Left (1, Interrupt'Pos (I)); - end Disable; - - procedure Set_Priority (I : Interrupt; P : IRQ_Priority) is - IPR : array (0 .. 3) of Interfaces.Unsigned_32; - for IPR'Address use System'To_Address (16#E000_E400#); - pragma Volatile (IPR); - - subtype IPR_Reg_Number is Integer range 0 .. 3; - subtype IPR_Field_Number is Integer range 0 .. 3; - subtype Priority_Value is Unsigned_32 range 0 .. 192; - - Reg_Num : IPR_Reg_Number; - Field_Num : IPR_Field_Number; - Prio : Priority_Value; - begin - Reg_Num := Interrupt'Pos (I) / 4; - Field_Num := Interrupt'Pos (I) mod 4; - Prio := IRQ_Priority'Pos (P) * 64; - IPR (Reg_Num) := IPR (Reg_Num) or Shift_Left (Prio, Field_Num * 8); - end Set_Priority; -end nrf51.Interrupts; diff --git a/microbit/nrf51/nrf51-interrupts.ads b/microbit/nrf51/nrf51-interrupts.ads deleted file mode 100644 index 7315c1f..0000000 --- a/microbit/nrf51/nrf51-interrupts.ads +++ /dev/null @@ -1,19 +0,0 @@ --- Specs for Basic Interrupt management package --- Shawn Nock 1 Jul. 2016 - -package nrf51.Interrupts is - type Interrupt is (POWER_CLOCK_IRQ, RADIO_IRQ, UART0_IRQ, SPI0_TWI0_IRQ, - SPI1_TWI1_IRQ, Unused_IRQ0, GPIOTE_IRQ, ADC_IRQ, - TIMER0_IRQ, TIMER1_IRQ, TIMER2_IRQ, RTC0_IRQ, TEMP_IRQ, - RNG_IRQ, ECB_IRQ, CCM_AAR_IRQ, WDT_IRQ, RTC1_IRQ, - QDEC_IRQ, LPCOMP_IRQ, SWI0_IRQ, SWI1_IRQ, SWI2_IRQ, - SWI3_IRQ, SWI4_IRQ, SWI5_IRQ, Unused_IRQ1, Unused_IRQ2, - Unused_IRQ3, Unused_IRQ4, Unused_IRQ5, Unused_IRQ6); - - type IRQ_Priority is (IRQ_Prio_Highest, IRQ_Prio_High, IRQ_Prio_Med, - IRQ_Prio_Low); - - procedure Set_Priority (I : Interrupt; P : IRQ_Priority); - procedure Enable (I : Interrupt); - procedure Disable (I : Interrupt); -end nrf51.Interrupts; diff --git a/microbit/nrf51/nrf51-lpcomp.ads b/microbit/nrf51/nrf51-lpcomp.ads index 9a1bafd..a238a63 100644 --- a/microbit/nrf51/nrf51-lpcomp.ads +++ b/microbit/nrf51/nrf51-lpcomp.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,86 +43,77 @@ package nrf51.LPCOMP is -- Registers -- --------------- - --------------------- - -- SHORTS_Register -- - --------------------- - -- Shortcut between READY event and SAMPLE task. - type READY_SAMPLE_Field is - ( - -- Shortcut disabled. + type SHORTS_READY_SAMPLE_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for READY_SAMPLE_Field use + for SHORTS_READY_SAMPLE_Field use (Disabled => 0, Enabled => 1); -- Shortcut between RADY event and STOP task. - type READY_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_READY_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for READY_STOP_Field use + for SHORTS_READY_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcut between DOWN event and STOP task. - type DOWN_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_DOWN_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for DOWN_STOP_Field use + for SHORTS_DOWN_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcut between UP event and STOP task. - type UP_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_UP_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for UP_STOP_Field use + for SHORTS_UP_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcut between CROSS event and STOP task. - type CROSS_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_CROSS_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for CROSS_STOP_Field use + for SHORTS_CROSS_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcuts for the LPCOMP. type SHORTS_Register is record -- Shortcut between READY event and SAMPLE task. - READY_SAMPLE : READY_SAMPLE_Field := Disabled; + READY_SAMPLE : SHORTS_READY_SAMPLE_Field := nrf51.LPCOMP.Disabled; -- Shortcut between RADY event and STOP task. - READY_STOP : READY_STOP_Field := Disabled; + READY_STOP : SHORTS_READY_STOP_Field := nrf51.LPCOMP.Disabled; -- Shortcut between DOWN event and STOP task. - DOWN_STOP : DOWN_STOP_Field := Disabled; + DOWN_STOP : SHORTS_DOWN_STOP_Field := nrf51.LPCOMP.Disabled; -- Shortcut between UP event and STOP task. - UP_STOP : UP_STOP_Field := Disabled; + UP_STOP : SHORTS_UP_STOP_Field := nrf51.LPCOMP.Disabled; -- Shortcut between CROSS event and STOP task. - CROSS_STOP : CROSS_STOP_Field := Disabled; + CROSS_STOP : SHORTS_CROSS_STOP_Field := nrf51.LPCOMP.Disabled; -- unspecified Reserved_5_31 : nrf51.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -103,120 +125,108 @@ package nrf51.LPCOMP is Reserved_5_31 at 0 range 5 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on READY event. - type READY_Field is - ( - -- Interrupt disabled. + type INTENSET_READY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for READY_Field use + for INTENSET_READY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on READY event. - type READY_Field_1 is - ( - -- Reset value for the field - Ready_Field_Reset, + type INTENSET_READY_Field_1 is + (-- Reset value for the field + Intenset_Ready_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for READY_Field_1 use - (Ready_Field_Reset => 0, + for INTENSET_READY_Field_1 use + (Intenset_Ready_Field_Reset => 0, Set => 1); -- Enable interrupt on DOWN event. - type DOWN_Field is - ( - -- Interrupt disabled. + type INTENSET_DOWN_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for DOWN_Field use + for INTENSET_DOWN_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on DOWN event. - type DOWN_Field_1 is - ( - -- Reset value for the field - Down_Field_Reset, + type INTENSET_DOWN_Field_1 is + (-- Reset value for the field + Intenset_Down_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for DOWN_Field_1 use - (Down_Field_Reset => 0, + for INTENSET_DOWN_Field_1 use + (Intenset_Down_Field_Reset => 0, Set => 1); -- Enable interrupt on UP event. - type UP_Field is - ( - -- Interrupt disabled. + type INTENSET_UP_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for UP_Field use + for INTENSET_UP_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on UP event. - type UP_Field_1 is - ( - -- Reset value for the field - Up_Field_Reset, + type INTENSET_UP_Field_1 is + (-- Reset value for the field + Intenset_Up_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for UP_Field_1 use - (Up_Field_Reset => 0, + for INTENSET_UP_Field_1 use + (Intenset_Up_Field_Reset => 0, Set => 1); -- Enable interrupt on CROSS event. - type CROSS_Field is - ( - -- Interrupt disabled. + type INTENSET_CROSS_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for CROSS_Field use + for INTENSET_CROSS_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on CROSS event. - type CROSS_Field_1 is - ( - -- Reset value for the field - Cross_Field_Reset, + type INTENSET_CROSS_Field_1 is + (-- Reset value for the field + Intenset_Cross_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for CROSS_Field_1 use - (Cross_Field_Reset => 0, + for INTENSET_CROSS_Field_1 use + (Intenset_Cross_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on READY event. - READY : READY_Field_1 := Ready_Field_Reset; + READY : INTENSET_READY_Field_1 := Intenset_Ready_Field_Reset; -- Enable interrupt on DOWN event. - DOWN : DOWN_Field_1 := Down_Field_Reset; + DOWN : INTENSET_DOWN_Field_1 := Intenset_Down_Field_Reset; -- Enable interrupt on UP event. - UP : UP_Field_1 := Up_Field_Reset; + UP : INTENSET_UP_Field_1 := Intenset_Up_Field_Reset; -- Enable interrupt on CROSS event. - CROSS : CROSS_Field_1 := Cross_Field_Reset; + CROSS : INTENSET_CROSS_Field_1 := Intenset_Cross_Field_Reset; -- unspecified Reserved_4_31 : nrf51.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -227,72 +237,108 @@ package nrf51.LPCOMP is Reserved_4_31 at 0 range 4 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on READY event. + type INTENCLR_READY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_READY_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on READY event. - type READY_Field_2 is - ( - -- Reset value for the field - Ready_Field_Reset, + type INTENCLR_READY_Field_1 is + (-- Reset value for the field + Intenclr_Ready_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for READY_Field_2 use - (Ready_Field_Reset => 0, + for INTENCLR_READY_Field_1 use + (Intenclr_Ready_Field_Reset => 0, Clear => 1); -- Disable interrupt on DOWN event. - type DOWN_Field_2 is - ( - -- Reset value for the field - Down_Field_Reset, + type INTENCLR_DOWN_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_DOWN_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on DOWN event. + type INTENCLR_DOWN_Field_1 is + (-- Reset value for the field + Intenclr_Down_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for DOWN_Field_2 use - (Down_Field_Reset => 0, + for INTENCLR_DOWN_Field_1 use + (Intenclr_Down_Field_Reset => 0, Clear => 1); -- Disable interrupt on UP event. - type UP_Field_2 is - ( - -- Reset value for the field - Up_Field_Reset, + type INTENCLR_UP_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_UP_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on UP event. + type INTENCLR_UP_Field_1 is + (-- Reset value for the field + Intenclr_Up_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for UP_Field_2 use - (Up_Field_Reset => 0, + for INTENCLR_UP_Field_1 use + (Intenclr_Up_Field_Reset => 0, Clear => 1); -- Disable interrupt on CROSS event. - type CROSS_Field_2 is - ( - -- Reset value for the field - Cross_Field_Reset, + type INTENCLR_CROSS_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_CROSS_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on CROSS event. + type INTENCLR_CROSS_Field_1 is + (-- Reset value for the field + Intenclr_Cross_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for CROSS_Field_2 use - (Cross_Field_Reset => 0, + for INTENCLR_CROSS_Field_1 use + (Intenclr_Cross_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on READY event. - READY : READY_Field_2 := Ready_Field_Reset; + READY : INTENCLR_READY_Field_1 := Intenclr_Ready_Field_Reset; -- Disable interrupt on DOWN event. - DOWN : DOWN_Field_2 := Down_Field_Reset; + DOWN : INTENCLR_DOWN_Field_1 := Intenclr_Down_Field_Reset; -- Disable interrupt on UP event. - UP : UP_Field_2 := Up_Field_Reset; + UP : INTENCLR_UP_Field_1 := Intenclr_Up_Field_Reset; -- Disable interrupt on CROSS event. - CROSS : CROSS_Field_2 := Cross_Field_Reset; + CROSS : INTENCLR_CROSS_Field_1 := Intenclr_Cross_Field_Reset; -- unspecified Reserved_4_31 : nrf51.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -303,30 +349,25 @@ package nrf51.LPCOMP is Reserved_4_31 at 0 range 4 .. 31; end record; - --------------------- - -- RESULT_Register -- - --------------------- - -- Result of last compare. Decision point SAMPLE task. - type RESULT_Field is - ( - -- Input voltage is bellow the reference threshold. + type RESULT_RESULT_Field is + (-- Input voltage is bellow the reference threshold. Bellow, -- Input voltage is above the reference threshold. Above) with Size => 1; - for RESULT_Field use + for RESULT_RESULT_Field use (Bellow => 0, Above => 1); -- Result of last compare. type RESULT_Register is record -- Read-only. Result of last compare. Decision point SAMPLE task. - RESULT : RESULT_Field; + RESULT : RESULT_RESULT_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RESULT_Register use record @@ -334,30 +375,25 @@ package nrf51.LPCOMP is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- Enable or disable LPCOMP. - type ENABLE_Field is - ( - -- Disabled LPCOMP. + type ENABLE_ENABLE_Field is + (-- Disabled LPCOMP. Disabled, -- Enable LPCOMP. Enabled) with Size => 2; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 1); -- Enable the LPCOMP. type ENABLE_Register is record -- Enable or disable LPCOMP. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.LPCOMP.Disabled; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -365,14 +401,9 @@ package nrf51.LPCOMP is Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- PSEL_Register -- - ------------------- - -- Analog input pin select. - type PSEL_Field is - ( - -- Use analog input 0 as analog input. + type PSEL_PSEL_Field is + (-- Use analog input 0 as analog input. Analoginput0, -- Use analog input 1 as analog input. Analoginput1, @@ -389,7 +420,7 @@ package nrf51.LPCOMP is -- Use analog input 7 as analog input. Analoginput7) with Size => 3; - for PSEL_Field use + for PSEL_PSEL_Field use (Analoginput0 => 0, Analoginput1 => 1, Analoginput2 => 2, @@ -402,11 +433,11 @@ package nrf51.LPCOMP is -- Input pin select. type PSEL_Register is record -- Analog input pin select. - PSEL : PSEL_Field := Analoginput0; + PSEL : PSEL_PSEL_Field := nrf51.LPCOMP.Analoginput0; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PSEL_Register use record @@ -414,14 +445,9 @@ package nrf51.LPCOMP is Reserved_3_31 at 0 range 3 .. 31; end record; - --------------------- - -- REFSEL_Register -- - --------------------- - -- Reference select. - type REFSEL_Field is - ( - -- Use supply with a 1/8 prescaler as reference. + type REFSEL_REFSEL_Field is + (-- Use supply with a 1/8 prescaler as reference. Supplyoneeighthprescaling, -- Use supply with a 2/8 prescaler as reference. Supplytwoeighthsprescaling, @@ -438,7 +464,7 @@ package nrf51.LPCOMP is -- Use external analog reference as reference. Aref) with Size => 3; - for REFSEL_Field use + for REFSEL_REFSEL_Field use (Supplyoneeighthprescaling => 0, Supplytwoeighthsprescaling => 1, Supplythreeeighthsprescaling => 2, @@ -451,11 +477,12 @@ package nrf51.LPCOMP is -- Reference select. type REFSEL_Register is record -- Reference select. - REFSEL : REFSEL_Field := Supplyoneeighthprescaling; + REFSEL : REFSEL_REFSEL_Field := + nrf51.LPCOMP.Supplyoneeighthprescaling; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for REFSEL_Register use record @@ -463,30 +490,26 @@ package nrf51.LPCOMP is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------------ - -- EXTREFSEL_Register -- - ------------------------ - -- External analog reference pin selection. - type EXTREFSEL_Field is - ( - -- Use analog reference 0 as reference. + type EXTREFSEL_EXTREFSEL_Field is + (-- Use analog reference 0 as reference. Analogreference0, -- Use analog reference 1 as reference. Analogreference1) with Size => 1; - for EXTREFSEL_Field use + for EXTREFSEL_EXTREFSEL_Field use (Analogreference0 => 0, Analogreference1 => 1); -- External reference select. type EXTREFSEL_Register is record -- External analog reference pin selection. - EXTREFSEL : EXTREFSEL_Field := Analogreference0; + EXTREFSEL : EXTREFSEL_EXTREFSEL_Field := + nrf51.LPCOMP.Analogreference0; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for EXTREFSEL_Register use record @@ -494,21 +517,16 @@ package nrf51.LPCOMP is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- ANADETECT_Register -- - ------------------------ - -- Analog detect configuration. - type ANADETECT_Field is - ( - -- Generate ANADETEC on crossing, both upwards and downwards crossing. + type ANADETECT_ANADETECT_Field is + (-- Generate ANADETEC on crossing, both upwards and downwards crossing. Cross, -- Generate ANADETEC on upwards crossing only. Up, -- Generate ANADETEC on downwards crossing only. Down) with Size => 2; - for ANADETECT_Field use + for ANADETECT_ANADETECT_Field use (Cross => 0, Up => 1, Down => 2); @@ -516,11 +534,11 @@ package nrf51.LPCOMP is -- Analog detect configuration. type ANADETECT_Register is record -- Analog detect configuration. - ANADETECT : ANADETECT_Field := Cross; + ANADETECT : ANADETECT_ANADETECT_Field := nrf51.LPCOMP.Cross; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ANADETECT_Register use record @@ -528,30 +546,25 @@ package nrf51.LPCOMP is Reserved_2_31 at 0 range 2 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.LPCOMP.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -566,60 +579,60 @@ package nrf51.LPCOMP is -- Low power comparator. type LPCOMP_Peripheral is record -- Start the comparator. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop the comparator. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Sample comparator value. - TASKS_SAMPLE : nrf51.Word; + TASKS_SAMPLE : aliased nrf51.UInt32; -- LPCOMP is ready and output is valid. - EVENTS_READY : nrf51.Word; + EVENTS_READY : aliased nrf51.UInt32; -- Input voltage crossed the threshold going down. - EVENTS_DOWN : nrf51.Word; + EVENTS_DOWN : aliased nrf51.UInt32; -- Input voltage crossed the threshold going up. - EVENTS_UP : nrf51.Word; + EVENTS_UP : aliased nrf51.UInt32; -- Input voltage crossed the threshold in any direction. - EVENTS_CROSS : nrf51.Word; + EVENTS_CROSS : aliased nrf51.UInt32; -- Shortcuts for the LPCOMP. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Result of last compare. - RESULT : RESULT_Register; + RESULT : aliased RESULT_Register; -- Enable the LPCOMP. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- Input pin select. - PSEL : PSEL_Register; + PSEL : aliased PSEL_Register; -- Reference select. - REFSEL : REFSEL_Register; + REFSEL : aliased REFSEL_Register; -- External reference select. - EXTREFSEL : EXTREFSEL_Register; + EXTREFSEL : aliased EXTREFSEL_Register; -- Analog detect configuration. - ANADETECT : ANADETECT_Register; + ANADETECT : aliased ANADETECT_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for LPCOMP_Peripheral use record - TASKS_START at 0 range 0 .. 31; - TASKS_STOP at 4 range 0 .. 31; - TASKS_SAMPLE at 8 range 0 .. 31; - EVENTS_READY at 256 range 0 .. 31; - EVENTS_DOWN at 260 range 0 .. 31; - EVENTS_UP at 264 range 0 .. 31; - EVENTS_CROSS at 268 range 0 .. 31; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - RESULT at 1024 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - PSEL at 1284 range 0 .. 31; - REFSEL at 1288 range 0 .. 31; - EXTREFSEL at 1292 range 0 .. 31; - ANADETECT at 1312 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_SAMPLE at 16#8# range 0 .. 31; + EVENTS_READY at 16#100# range 0 .. 31; + EVENTS_DOWN at 16#104# range 0 .. 31; + EVENTS_UP at 16#108# range 0 .. 31; + EVENTS_CROSS at 16#10C# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + RESULT at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#504# range 0 .. 31; + REFSEL at 16#508# range 0 .. 31; + EXTREFSEL at 16#50C# range 0 .. 31; + ANADETECT at 16#520# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- Low power comparator. diff --git a/microbit/nrf51/nrf51-mpu.ads b/microbit/nrf51/nrf51-mpu.ads index 725e667..8e24a30 100644 --- a/microbit/nrf51/nrf51-mpu.ads +++ b/microbit/nrf51/nrf51-mpu.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,112 +43,96 @@ package nrf51.MPU is -- Registers -- --------------- - -------------------- - -- PERR0_Register -- - -------------------- - -- POWER_CLOCK region configuration. - type POWER_CLOCK_Field is - ( - -- Peripheral configured in region 1. + type PERR0_POWER_CLOCK_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for POWER_CLOCK_Field use + for PERR0_POWER_CLOCK_Field use (Inregion1 => 0, Inregion0 => 1); -- RADIO region configuration. - type RADIO_Field is - ( - -- Peripheral configured in region 1. + type PERR0_RADIO_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for RADIO_Field use + for PERR0_RADIO_Field use (Inregion1 => 0, Inregion0 => 1); -- UART0 region configuration. - type UART0_Field is - ( - -- Peripheral configured in region 1. + type PERR0_UART0_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for UART0_Field use + for PERR0_UART0_Field use (Inregion1 => 0, Inregion0 => 1); -- SPI0 and TWI0 region configuration. - type SPI0_TWI0_Field is - ( - -- Peripheral configured in region 1. + type PERR0_SPI0_TWI0_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for SPI0_TWI0_Field use + for PERR0_SPI0_TWI0_Field use (Inregion1 => 0, Inregion0 => 1); -- SPI1 and TWI1 region configuration. - type SPI1_TWI1_Field is - ( - -- Peripheral configured in region 1. + type PERR0_SPI1_TWI1_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for SPI1_TWI1_Field use + for PERR0_SPI1_TWI1_Field use (Inregion1 => 0, Inregion0 => 1); -- GPIOTE region configuration. - type GPIOTE_Field is - ( - -- Peripheral configured in region 1. + type PERR0_GPIOTE_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for GPIOTE_Field use + for PERR0_GPIOTE_Field use (Inregion1 => 0, Inregion0 => 1); -- ADC region configuration. - type ADC_Field is - ( - -- Peripheral configured in region 1. + type PERR0_ADC_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for ADC_Field use + for PERR0_ADC_Field use (Inregion1 => 0, Inregion0 => 1); -- TIMER0 region configuration. - type TIMER0_Field is - ( - -- Peripheral configured in region 1. + type PERR0_TIMER0_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for TIMER0_Field use + for PERR0_TIMER0_Field use (Inregion1 => 0, Inregion0 => 1); - ----------------- - -- PERR0.TIMER -- - ----------------- - -- PERR0_TIMER array - type PERR0_TIMER_Field_Array is array (0 .. 2) of TIMER0_Field + type PERR0_TIMER_Field_Array is array (0 .. 2) of PERR0_TIMER0_Field with Component_Size => 1, Size => 3; -- Type definition for PERR0_TIMER @@ -141,183 +156,172 @@ package nrf51.MPU is end record; -- RTC0 region configuration. - type RTC0_Field is - ( - -- Peripheral configured in region 1. + type PERR0_RTC0_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for RTC0_Field use + for PERR0_RTC0_Field use (Inregion1 => 0, Inregion0 => 1); -- TEMP region configuration. - type TEMP_Field is - ( - -- Peripheral configured in region 1. + type PERR0_TEMP_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for TEMP_Field use + for PERR0_TEMP_Field use (Inregion1 => 0, Inregion0 => 1); -- RNG region configuration. - type RNG_Field is - ( - -- Peripheral configured in region 1. + type PERR0_RNG_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for RNG_Field use + for PERR0_RNG_Field use (Inregion1 => 0, Inregion0 => 1); -- ECB region configuration. - type ECB_Field is - ( - -- Peripheral configured in region 1. + type PERR0_ECB_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for ECB_Field use + for PERR0_ECB_Field use (Inregion1 => 0, Inregion0 => 1); -- CCM and AAR region configuration. - type CCM_AAR_Field is - ( - -- Peripheral configured in region 1. + type PERR0_CCM_AAR_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for CCM_AAR_Field use + for PERR0_CCM_AAR_Field use (Inregion1 => 0, Inregion0 => 1); -- WDT region configuration. - type WDT_Field is - ( - -- Peripheral configured in region 1. + type PERR0_WDT_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for WDT_Field use + for PERR0_WDT_Field use (Inregion1 => 0, Inregion0 => 1); -- RTC1 region configuration. - type RTC1_Field is - ( - -- Peripheral configured in region 1. + type PERR0_RTC1_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for RTC1_Field use + for PERR0_RTC1_Field use (Inregion1 => 0, Inregion0 => 1); -- QDEC region configuration. - type QDEC_Field is - ( - -- Peripheral configured in region 1. + type PERR0_QDEC_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for QDEC_Field use + for PERR0_QDEC_Field use (Inregion1 => 0, Inregion0 => 1); -- LPCOMP region configuration. - type LPCOMP_Field is - ( - -- Peripheral configured in region 1. + type PERR0_LPCOMP_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for LPCOMP_Field use + for PERR0_LPCOMP_Field use (Inregion1 => 0, Inregion0 => 1); -- NVMC region configuration. - type NVMC_Field is - ( - -- Peripheral configured in region 1. + type PERR0_NVMC_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for NVMC_Field use + for PERR0_NVMC_Field use (Inregion1 => 0, Inregion0 => 1); -- PPI region configuration. - type PPI_Field is - ( - -- Peripheral configured in region 1. + type PERR0_PPI_Field is + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) with Size => 1; - for PPI_Field use + for PERR0_PPI_Field use (Inregion1 => 0, Inregion0 => 1); -- Configuration of peripherals in mpu regions. type PERR0_Register is record -- POWER_CLOCK region configuration. - POWER_CLOCK : POWER_CLOCK_Field := Inregion1; + POWER_CLOCK : PERR0_POWER_CLOCK_Field := nrf51.MPU.Inregion1; -- RADIO region configuration. - RADIO : RADIO_Field := Inregion1; + RADIO : PERR0_RADIO_Field := nrf51.MPU.Inregion1; -- UART0 region configuration. - UART0 : UART0_Field := Inregion1; + UART0 : PERR0_UART0_Field := nrf51.MPU.Inregion1; -- SPI0 and TWI0 region configuration. - SPI0_TWI0 : SPI0_TWI0_Field := Inregion1; + SPI0_TWI0 : PERR0_SPI0_TWI0_Field := nrf51.MPU.Inregion1; -- SPI1 and TWI1 region configuration. - SPI1_TWI1 : SPI1_TWI1_Field := Inregion1; + SPI1_TWI1 : PERR0_SPI1_TWI1_Field := nrf51.MPU.Inregion1; -- unspecified Reserved_5_5 : nrf51.Bit := 16#0#; -- GPIOTE region configuration. - GPIOTE : GPIOTE_Field := Inregion1; + GPIOTE : PERR0_GPIOTE_Field := nrf51.MPU.Inregion1; -- ADC region configuration. - ADC : ADC_Field := Inregion1; + ADC : PERR0_ADC_Field := nrf51.MPU.Inregion1; -- TIMER0 region configuration. TIMER : PERR0_TIMER_Field := (As_Array => False, Val => 16#0#); -- RTC0 region configuration. - RTC0 : RTC0_Field := Inregion1; + RTC0 : PERR0_RTC0_Field := nrf51.MPU.Inregion1; -- TEMP region configuration. - TEMP : TEMP_Field := Inregion1; + TEMP : PERR0_TEMP_Field := nrf51.MPU.Inregion1; -- RNG region configuration. - RNG : RNG_Field := Inregion1; + RNG : PERR0_RNG_Field := nrf51.MPU.Inregion1; -- ECB region configuration. - ECB : ECB_Field := Inregion1; + ECB : PERR0_ECB_Field := nrf51.MPU.Inregion1; -- CCM and AAR region configuration. - CCM_AAR : CCM_AAR_Field := Inregion1; + CCM_AAR : PERR0_CCM_AAR_Field := nrf51.MPU.Inregion1; -- WDT region configuration. - WDT : WDT_Field := Inregion1; + WDT : PERR0_WDT_Field := nrf51.MPU.Inregion1; -- RTC1 region configuration. - RTC1 : RTC1_Field := Inregion1; + RTC1 : PERR0_RTC1_Field := nrf51.MPU.Inregion1; -- QDEC region configuration. - QDEC : QDEC_Field := Inregion1; + QDEC : PERR0_QDEC_Field := nrf51.MPU.Inregion1; -- LPCOMP region configuration. - LPCOMP : LPCOMP_Field := Inregion1; + LPCOMP : PERR0_LPCOMP_Field := nrf51.MPU.Inregion1; -- unspecified Reserved_20_29 : nrf51.UInt10 := 16#0#; -- NVMC region configuration. - NVMC : NVMC_Field := Inregion1; + NVMC : PERR0_NVMC_Field := nrf51.MPU.Inregion1; -- PPI region configuration. - PPI : PPI_Field := Inregion1; + PPI : PERR0_PPI_Field := nrf51.MPU.Inregion1; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PERR0_Register use record @@ -344,36 +348,31 @@ package nrf51.MPU is PPI at 0 range 31 .. 31; end record; - ------------------------- - -- PROTENSET0_Register -- - ------------------------- - -- Protection enable for region 0. - type PROTREG0_Field is - ( - -- Protection disabled. + type PROTENSET0_PROTREG0_Field is + (-- Protection disabled. Disabled, -- Protection enabled. Enabled) with Size => 1; - for PROTREG0_Field use + for PROTENSET0_PROTREG0_Field use (Disabled => 0, Enabled => 1); -- Protection enable for region 0. - type PROTREG0_Field_1 is - ( - -- Reset value for the field - Protreg0_Field_Reset, + type PROTENSET0_PROTREG0_Field_1 is + (-- Reset value for the field + Protenset0_Protreg0_Field_Reset, -- Enable protection on write. Set) with Size => 1; - for PROTREG0_Field_1 use - (Protreg0_Field_Reset => 0, + for PROTENSET0_PROTREG0_Field_1 use + (Protenset0_Protreg0_Field_Reset => 0, Set => 1); -- PROTENSET0_PROTREG array - type PROTENSET0_PROTREG_Field_Array is array (0 .. 31) of PROTREG0_Field_1 + type PROTENSET0_PROTREG_Field_Array is array (0 .. 31) + of PROTENSET0_PROTREG0_Field_1 with Component_Size => 1, Size => 32; -- Erase and write protection bit enable set register. @@ -383,13 +382,13 @@ package nrf51.MPU is case As_Array is when False => -- PROTREG as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PROTREG as an array Arr : PROTENSET0_PROTREG_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PROTENSET0_Register use record @@ -397,37 +396,31 @@ package nrf51.MPU is Arr at 0 range 0 .. 31; end record; - ------------------------- - -- PROTENSET1_Register -- - ------------------------- - -- Protection enable for region 32. - type PROTREG32_Field is - ( - -- Protection disabled. + type PROTENSET1_PROTREG32_Field is + (-- Protection disabled. Disabled, -- Protection enabled. Enabled) with Size => 1; - for PROTREG32_Field use + for PROTENSET1_PROTREG32_Field use (Disabled => 0, Enabled => 1); -- Protection enable for region 32. - type PROTREG32_Field_1 is - ( - -- Reset value for the field - Protreg32_Field_Reset, + type PROTENSET1_PROTREG32_Field_1 is + (-- Reset value for the field + Protenset1_Protreg32_Field_Reset, -- Enable protection on write. Set) with Size => 1; - for PROTREG32_Field_1 use - (Protreg32_Field_Reset => 0, + for PROTENSET1_PROTREG32_Field_1 use + (Protenset1_Protreg32_Field_Reset => 0, Set => 1); -- PROTENSET1_PROTREG array type PROTENSET1_PROTREG_Field_Array is array (32 .. 63) - of PROTREG32_Field_1 + of PROTENSET1_PROTREG32_Field_1 with Component_Size => 1, Size => 32; -- Erase and write protection bit enable set register. @@ -437,13 +430,13 @@ package nrf51.MPU is case As_Array is when False => -- PROTREG as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- PROTREG as an array Arr : PROTENSET1_PROTREG_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PROTENSET1_Register use record @@ -451,30 +444,26 @@ package nrf51.MPU is Arr at 0 range 0 .. 31; end record; - ----------------------------- - -- DISABLEINDEBUG_Register -- - ----------------------------- - -- Disable protection mechanism in debug mode. - type DISABLEINDEBUG_Field is - ( - -- Protection enabled. + type DISABLEINDEBUG_DISABLEINDEBUG_Field is + (-- Protection enabled. Enabled, -- Protection disabled. Disabled) with Size => 1; - for DISABLEINDEBUG_Field use + for DISABLEINDEBUG_DISABLEINDEBUG_Field use (Enabled => 0, Disabled => 1); -- Disable erase and write protection mechanism in debug mode. type DISABLEINDEBUG_Register is record -- Disable protection mechanism in debug mode. - DISABLEINDEBUG : DISABLEINDEBUG_Field := Disabled; + DISABLEINDEBUG : DISABLEINDEBUG_DISABLEINDEBUG_Field := + nrf51.MPU.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DISABLEINDEBUG_Register use record @@ -482,27 +471,22 @@ package nrf51.MPU is Reserved_1_31 at 0 range 1 .. 31; end record; - ---------------------------- - -- PROTBLOCKSIZE_Register -- - ---------------------------- - -- Erase and write protection block size. - type PROTBLOCKSIZE_Field is - ( - -- Erase and write protection block size is 4k. - PROTBLOCKSIZE_Field_4K) + type PROTBLOCKSIZE_PROTBLOCKSIZE_Field is + (-- Erase and write protection block size is 4k. + Val_4K) with Size => 2; - for PROTBLOCKSIZE_Field use - (PROTBLOCKSIZE_Field_4K => 0); + for PROTBLOCKSIZE_PROTBLOCKSIZE_Field use + (Val_4K => 0); -- Erase and write protection block size. type PROTBLOCKSIZE_Register is record -- Erase and write protection block size. - PROTBLOCKSIZE : PROTBLOCKSIZE_Field := PROTBLOCKSIZE_Field_4K; + PROTBLOCKSIZE : PROTBLOCKSIZE_PROTBLOCKSIZE_Field := nrf51.MPU.Val_4K; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PROTBLOCKSIZE_Register use record @@ -517,27 +501,27 @@ package nrf51.MPU is -- Memory Protection Unit. type MPU_Peripheral is record -- Configuration of peripherals in mpu regions. - PERR0 : PERR0_Register; + PERR0 : aliased PERR0_Register; -- Length of RAM region 0. - RLENR0 : nrf51.Word; + RLENR0 : aliased nrf51.UInt32; -- Erase and write protection bit enable set register. - PROTENSET0 : PROTENSET0_Register; + PROTENSET0 : aliased PROTENSET0_Register; -- Erase and write protection bit enable set register. - PROTENSET1 : PROTENSET1_Register; + PROTENSET1 : aliased PROTENSET1_Register; -- Disable erase and write protection mechanism in debug mode. - DISABLEINDEBUG : DISABLEINDEBUG_Register; + DISABLEINDEBUG : aliased DISABLEINDEBUG_Register; -- Erase and write protection block size. - PROTBLOCKSIZE : PROTBLOCKSIZE_Register; + PROTBLOCKSIZE : aliased PROTBLOCKSIZE_Register; end record with Volatile; for MPU_Peripheral use record - PERR0 at 1320 range 0 .. 31; - RLENR0 at 1324 range 0 .. 31; - PROTENSET0 at 1536 range 0 .. 31; - PROTENSET1 at 1540 range 0 .. 31; - DISABLEINDEBUG at 1544 range 0 .. 31; - PROTBLOCKSIZE at 1548 range 0 .. 31; + PERR0 at 16#528# range 0 .. 31; + RLENR0 at 16#52C# range 0 .. 31; + PROTENSET0 at 16#600# range 0 .. 31; + PROTENSET1 at 16#604# range 0 .. 31; + DISABLEINDEBUG at 16#608# range 0 .. 31; + PROTBLOCKSIZE at 16#60C# range 0 .. 31; end record; -- Memory Protection Unit. diff --git a/microbit/nrf51/nrf51-nvmc.ads b/microbit/nrf51/nrf51-nvmc.ads index a8a7115..438097e 100644 --- a/microbit/nrf51/nrf51-nvmc.ads +++ b/microbit/nrf51/nrf51-nvmc.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,30 +43,25 @@ package nrf51.NVMC is -- Registers -- --------------- - -------------------- - -- READY_Register -- - -------------------- - -- NVMC ready. - type READY_Field is - ( - -- NVMC is busy (on-going write or erase operation). + type READY_READY_Field is + (-- NVMC is busy (on-going write or erase operation). Busy, -- NVMC is ready. Ready) with Size => 1; - for READY_Field use + for READY_READY_Field use (Busy => 0, Ready => 1); -- Ready flag. type READY_Register is record -- Read-only. NVMC ready. - READY : READY_Field; + READY : READY_READY_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for READY_Register use record @@ -43,21 +69,16 @@ package nrf51.NVMC is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- - -- Program write enable. - type WEN_Field is - ( - -- Read only access. + type CONFIG_WEN_Field is + (-- Read only access. Ren, -- Write enabled. Wen, -- Erase enabled. Een) with Size => 2; - for WEN_Field use + for CONFIG_WEN_Field use (Ren => 0, Wen => 1, Een => 2); @@ -65,11 +86,11 @@ package nrf51.NVMC is -- Configuration register. type CONFIG_Register is record -- Program write enable. - WEN : WEN_Field := Ren; + WEN : CONFIG_WEN_Field := nrf51.NVMC.Ren; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -77,19 +98,14 @@ package nrf51.NVMC is Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------------- - -- ERASEALL_Register -- - ----------------------- - -- Starts the erasing of all user NVM (code region 0/1 and UICR registers). - type ERASEALL_Field is - ( - -- No operation. + type ERASEALL_ERASEALL_Field is + (-- No operation. Nooperation, -- Start chip erase. Erase) with Size => 1; - for ERASEALL_Field use + for ERASEALL_ERASEALL_Field use (Nooperation => 0, Erase => 1); @@ -97,11 +113,11 @@ package nrf51.NVMC is type ERASEALL_Register is record -- Starts the erasing of all user NVM (code region 0/1 and UICR -- registers). - ERASEALL : ERASEALL_Field := Nooperation; + ERASEALL : ERASEALL_ERASEALL_Field := nrf51.NVMC.Nooperation; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ERASEALL_Register use record @@ -109,30 +125,25 @@ package nrf51.NVMC is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- ERASEUICR_Register -- - ------------------------ - -- It can only be used when all contents of code region 1 are erased. - type ERASEUICR_Field is - ( - -- No operation. + type ERASEUICR_ERASEUICR_Field is + (-- No operation. Nooperation, -- Start UICR erase. Erase) with Size => 1; - for ERASEUICR_Field use + for ERASEUICR_ERASEUICR_Field use (Nooperation => 0, Erase => 1); -- Register for start erasing User Information Congfiguration Registers. type ERASEUICR_Register is record -- It can only be used when all contents of code region 1 are erased. - ERASEUICR : ERASEUICR_Field := Nooperation; + ERASEUICR : ERASEUICR_ERASEUICR_Field := nrf51.NVMC.Nooperation; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ERASEUICR_Register use record @@ -145,8 +156,7 @@ package nrf51.NVMC is ----------------- type NVMC_Disc is - ( - Age, + (Age, Cr1); -- Non Volatile Memory Controller. @@ -154,34 +164,34 @@ package nrf51.NVMC is (Discriminent : NVMC_Disc := Age) is record -- Ready flag. - READY : READY_Register; + READY : aliased READY_Register; -- Configuration register. - CONFIG : CONFIG_Register; + CONFIG : aliased CONFIG_Register; -- Register for erasing all non-volatile user memory. - ERASEALL : ERASEALL_Register; + ERASEALL : aliased ERASEALL_Register; -- Register for erasing a protected non-volatile memory page. - ERASEPCR0 : nrf51.Word; + ERASEPCR0 : aliased nrf51.UInt32; -- Register for start erasing User Information Congfiguration Registers. - ERASEUICR : ERASEUICR_Register; + ERASEUICR : aliased ERASEUICR_Register; case Discriminent is when Age => -- Register for erasing a non-protected non-volatile memory page. - ERASEPAGE : nrf51.Word; + ERASEPAGE : aliased nrf51.UInt32; when Cr1 => -- Register for erasing a non-protected non-volatile memory page. - ERASEPCR1 : nrf51.Word; + ERASEPCR1 : aliased nrf51.UInt32; end case; end record with Unchecked_Union, Volatile; for NVMC_Peripheral use record - READY at 1024 range 0 .. 31; - CONFIG at 1284 range 0 .. 31; - ERASEALL at 1292 range 0 .. 31; - ERASEPCR0 at 1296 range 0 .. 31; - ERASEUICR at 1300 range 0 .. 31; - ERASEPAGE at 1288 range 0 .. 31; - ERASEPCR1 at 1288 range 0 .. 31; + READY at 16#400# range 0 .. 31; + CONFIG at 16#504# range 0 .. 31; + ERASEALL at 16#50C# range 0 .. 31; + ERASEPCR0 at 16#510# range 0 .. 31; + ERASEUICR at 16#514# range 0 .. 31; + ERASEPAGE at 16#508# range 0 .. 31; + ERASEPCR1 at 16#508# range 0 .. 31; end record; -- Non Volatile Memory Controller. diff --git a/microbit/nrf51/nrf51-power.ads b/microbit/nrf51/nrf51-power.ads index affbcaf..f2a2acf 100644 --- a/microbit/nrf51/nrf51-power.ads +++ b/microbit/nrf51/nrf51-power.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,32 +43,26 @@ package nrf51.POWER is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on POFWARN event. - type POFWARN_Field is - ( - -- Interrupt disabled. + type INTENSET_POFWARN_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for POFWARN_Field use + for INTENSET_POFWARN_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on POFWARN event. - type POFWARN_Field_1 is - ( - -- Reset value for the field - Pofwarn_Field_Reset, + type INTENSET_POFWARN_Field_1 is + (-- Reset value for the field + Intenset_Pofwarn_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for POFWARN_Field_1 use - (Pofwarn_Field_Reset => 0, + for INTENSET_POFWARN_Field_1 use + (Intenset_Pofwarn_Field_Reset => 0, Set => 1); -- Interrupt enable set register. @@ -45,11 +70,12 @@ package nrf51.POWER is -- unspecified Reserved_0_1 : nrf51.UInt2 := 16#0#; -- Enable interrupt on POFWARN event. - POFWARN : POFWARN_Field_1 := Pofwarn_Field_Reset; + POFWARN : INTENSET_POFWARN_Field_1 := + Intenset_Pofwarn_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -58,20 +84,26 @@ package nrf51.POWER is Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on POFWARN event. + type INTENCLR_POFWARN_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_POFWARN_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on POFWARN event. - type POFWARN_Field_2 is - ( - -- Reset value for the field - Pofwarn_Field_Reset, + type INTENCLR_POFWARN_Field_1 is + (-- Reset value for the field + Intenclr_Pofwarn_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for POFWARN_Field_2 use - (Pofwarn_Field_Reset => 0, + for INTENCLR_POFWARN_Field_1 use + (Intenclr_Pofwarn_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. @@ -79,11 +111,12 @@ package nrf51.POWER is -- unspecified Reserved_0_1 : nrf51.UInt2 := 16#0#; -- Disable interrupt on POFWARN event. - POFWARN : POFWARN_Field_2 := Pofwarn_Field_Reset; + POFWARN : INTENCLR_POFWARN_Field_1 := + Intenclr_Pofwarn_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -92,122 +125,111 @@ package nrf51.POWER is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------------ - -- RESETREAS_Register -- - ------------------------ - -- Reset from pin-reset detected. - type RESETPIN_Field is - ( - -- Reset not detected. + type RESETREAS_RESETPIN_Field is + (-- Reset not detected. Notdetected, -- Reset detected. Detected) with Size => 1; - for RESETPIN_Field use + for RESETREAS_RESETPIN_Field use (Notdetected => 0, Detected => 1); -- Reset from watchdog detected. - type DOG_Field is - ( - -- Reset not detected. + type RESETREAS_DOG_Field is + (-- Reset not detected. Notdetected, -- Reset detected. Detected) with Size => 1; - for DOG_Field use + for RESETREAS_DOG_Field use (Notdetected => 0, Detected => 1); -- Reset from AIRCR.SYSRESETREQ detected. - type SREQ_Field is - ( - -- Reset not detected. + type RESETREAS_SREQ_Field is + (-- Reset not detected. Notdetected, -- Reset detected. Detected) with Size => 1; - for SREQ_Field use + for RESETREAS_SREQ_Field use (Notdetected => 0, Detected => 1); -- Reset from CPU lock-up detected. - type LOCKUP_Field is - ( - -- Reset not detected. + type RESETREAS_LOCKUP_Field is + (-- Reset not detected. Notdetected, -- Reset detected. Detected) with Size => 1; - for LOCKUP_Field use + for RESETREAS_LOCKUP_Field use (Notdetected => 0, Detected => 1); -- Reset from wake-up from OFF mode detected by the use of DETECT signal -- from GPIO. - type OFF_Field is - ( - -- Reset not detected. + type RESETREAS_OFF_Field is + (-- Reset not detected. Notdetected, -- Reset detected. Detected) with Size => 1; - for OFF_Field use + for RESETREAS_OFF_Field use (Notdetected => 0, Detected => 1); -- Reset from wake-up from OFF mode detected by the use of ANADETECT signal -- from LPCOMP. - type LPCOMP_Field is - ( - -- Reset not detected. + type RESETREAS_LPCOMP_Field is + (-- Reset not detected. Notdetected, -- Reset detected. Detected) with Size => 1; - for LPCOMP_Field use + for RESETREAS_LPCOMP_Field use (Notdetected => 0, Detected => 1); -- Reset from wake-up from OFF mode detected by entering into debug -- interface mode. - type DIF_Field is - ( - -- Reset not detected. + type RESETREAS_DIF_Field is + (-- Reset not detected. Notdetected, -- Reset detected. Detected) with Size => 1; - for DIF_Field use + for RESETREAS_DIF_Field use (Notdetected => 0, Detected => 1); -- Reset reason. type RESETREAS_Register is record -- Reset from pin-reset detected. - RESETPIN : RESETPIN_Field := Notdetected; + RESETPIN : RESETREAS_RESETPIN_Field := nrf51.POWER.Notdetected; -- Reset from watchdog detected. - DOG : DOG_Field := Notdetected; + DOG : RESETREAS_DOG_Field := nrf51.POWER.Notdetected; -- Reset from AIRCR.SYSRESETREQ detected. - SREQ : SREQ_Field := Notdetected; + SREQ : RESETREAS_SREQ_Field := nrf51.POWER.Notdetected; -- Reset from CPU lock-up detected. - LOCKUP : LOCKUP_Field := Notdetected; + LOCKUP : RESETREAS_LOCKUP_Field := nrf51.POWER.Notdetected; -- unspecified Reserved_4_15 : nrf51.UInt12 := 16#0#; -- Reset from wake-up from OFF mode detected by the use of DETECT signal -- from GPIO. - OFF : OFF_Field := Notdetected; + OFF : RESETREAS_OFF_Field := nrf51.POWER.Notdetected; -- Reset from wake-up from OFF mode detected by the use of ANADETECT -- signal from LPCOMP. - LPCOMP : LPCOMP_Field := Notdetected; + LPCOMP : RESETREAS_LPCOMP_Field := nrf51.POWER.Notdetected; -- Reset from wake-up from OFF mode detected by entering into debug -- interface mode. - DIF : DIF_Field := Notdetected; + DIF : RESETREAS_DIF_Field := nrf51.POWER.Notdetected; -- unspecified Reserved_19_31 : nrf51.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RESETREAS_Register use record @@ -222,72 +244,64 @@ package nrf51.POWER is Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------------ - -- RAMSTATUS_Register -- - ------------------------ - -- RAM block 0 status. - type RAMBLOCK0_Field is - ( - -- RAM block 0 is off or powering up. + type RAMSTATUS_RAMBLOCK0_Field is + (-- RAM block 0 is off or powering up. Off, -- RAM block 0 is on. On) with Size => 1; - for RAMBLOCK0_Field use + for RAMSTATUS_RAMBLOCK0_Field use (Off => 0, On => 1); -- RAM block 1 status. - type RAMBLOCK1_Field is - ( - -- RAM block 1 is off or powering up. + type RAMSTATUS_RAMBLOCK1_Field is + (-- RAM block 1 is off or powering up. Off, -- RAM block 1 is on. On) with Size => 1; - for RAMBLOCK1_Field use + for RAMSTATUS_RAMBLOCK1_Field use (Off => 0, On => 1); -- RAM block 2 status. - type RAMBLOCK2_Field is - ( - -- RAM block 2 is off or powering up. + type RAMSTATUS_RAMBLOCK2_Field is + (-- RAM block 2 is off or powering up. Off, -- RAM block 2 is on. On) with Size => 1; - for RAMBLOCK2_Field use + for RAMSTATUS_RAMBLOCK2_Field use (Off => 0, On => 1); -- RAM block 3 status. - type RAMBLOCK3_Field is - ( - -- RAM block 3 is off or powering up. + type RAMSTATUS_RAMBLOCK3_Field is + (-- RAM block 3 is off or powering up. Off, -- RAM block 3 is on. On) with Size => 1; - for RAMBLOCK3_Field use + for RAMSTATUS_RAMBLOCK3_Field use (Off => 0, On => 1); -- Ram status register. type RAMSTATUS_Register is record -- Read-only. RAM block 0 status. - RAMBLOCK0 : RAMBLOCK0_Field; + RAMBLOCK0 : RAMSTATUS_RAMBLOCK0_Field; -- Read-only. RAM block 1 status. - RAMBLOCK1 : RAMBLOCK1_Field; + RAMBLOCK1 : RAMSTATUS_RAMBLOCK1_Field; -- Read-only. RAM block 2 status. - RAMBLOCK2 : RAMBLOCK2_Field; + RAMBLOCK2 : RAMSTATUS_RAMBLOCK2_Field; -- Read-only. RAM block 3 status. - RAMBLOCK3 : RAMBLOCK3_Field; + RAMBLOCK3 : RAMSTATUS_RAMBLOCK3_Field; -- unspecified Reserved_4_31 : nrf51.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RAMSTATUS_Register use record @@ -298,30 +312,26 @@ package nrf51.POWER is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------------ - -- SYSTEMOFF_Register -- - ------------------------ - -- Enter system off mode. - type SYSTEMOFF_Field is - ( - -- Reset value for the field - Systemoff_Field_Reset, + type SYSTEMOFF_SYSTEMOFF_Field is + (-- Reset value for the field + Systemoff_Systemoff_Field_Reset, -- Enter system off mode. Enter) with Size => 1; - for SYSTEMOFF_Field use - (Systemoff_Field_Reset => 0, + for SYSTEMOFF_SYSTEMOFF_Field use + (Systemoff_Systemoff_Field_Reset => 0, Enter => 1); -- System off register. type SYSTEMOFF_Register is record -- Write-only. Enter system off mode. - SYSTEMOFF : SYSTEMOFF_Field := Systemoff_Field_Reset; + SYSTEMOFF : SYSTEMOFF_SYSTEMOFF_Field := + Systemoff_Systemoff_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SYSTEMOFF_Register use record @@ -329,26 +339,20 @@ package nrf51.POWER is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- POFCON_Register -- - --------------------- - -- Power failure comparator enable. - type POF_Field is - ( - -- Disabled. + type POFCON_POF_Field is + (-- Disabled. Disabled, -- Enabled. Enabled) with Size => 1; - for POF_Field use + for POFCON_POF_Field use (Disabled => 0, Enabled => 1); -- Set threshold level. - type THRESHOLD_Field is - ( - -- Set threshold to 2.1Volts. + type POFCON_THRESHOLD_Field is + (-- Set threshold to 2.1Volts. V21, -- Set threshold to 2.3Volts. V23, @@ -357,7 +361,7 @@ package nrf51.POWER is -- Set threshold to 2.7Volts. V27) with Size => 2; - for THRESHOLD_Field use + for POFCON_THRESHOLD_Field use (V21 => 0, V23 => 1, V25 => 2, @@ -366,13 +370,13 @@ package nrf51.POWER is -- Power failure configuration. type POFCON_Register is record -- Power failure comparator enable. - POF : POF_Field := Disabled; + POF : POFCON_POF_Field := nrf51.POWER.Disabled; -- Set threshold level. - THRESHOLD : THRESHOLD_Field := V21; + THRESHOLD : POFCON_THRESHOLD_Field := nrf51.POWER.V21; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POFCON_Register use record @@ -381,10 +385,6 @@ package nrf51.POWER is Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------- - -- GPREGRET_Register -- - ----------------------- - subtype GPREGRET_GPREGRET_Field is nrf51.Byte; -- General purpose retention register. This register is a retained @@ -395,7 +395,7 @@ package nrf51.POWER is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for GPREGRET_Register use record @@ -403,74 +403,66 @@ package nrf51.POWER is Reserved_8_31 at 0 range 8 .. 31; end record; - -------------------- - -- RAMON_Register -- - -------------------- - -- RAM block 0 behaviour in ON mode. - type ONRAM0_Field is - ( - -- RAM block 0 OFF in ON mode. + type RAMON_ONRAM0_Field is + (-- RAM block 0 OFF in ON mode. Ram0Off, -- RAM block 0 ON in ON mode. Ram0On) with Size => 1; - for ONRAM0_Field use + for RAMON_ONRAM0_Field use (Ram0Off => 0, Ram0On => 1); -- RAM block 1 behaviour in ON mode. - type ONRAM1_Field is - ( - -- RAM block 1 OFF in ON mode. + type RAMON_ONRAM1_Field is + (-- RAM block 1 OFF in ON mode. Ram1Off, -- RAM block 1 ON in ON mode. Ram1On) with Size => 1; - for ONRAM1_Field use + for RAMON_ONRAM1_Field use (Ram1Off => 0, Ram1On => 1); -- RAM block 0 behaviour in OFF mode. - type OFFRAM0_Field is - ( - -- RAM block 0 OFF in OFF mode. + type RAMON_OFFRAM0_Field is + (-- RAM block 0 OFF in OFF mode. Ram0Off, -- RAM block 0 ON in OFF mode. Ram0On) with Size => 1; - for OFFRAM0_Field use + for RAMON_OFFRAM0_Field use (Ram0Off => 0, Ram0On => 1); -- RAM block 1 behaviour in OFF mode. - type OFFRAM1_Field is - ( - -- RAM block 1 OFF in OFF mode. + type RAMON_OFFRAM1_Field is + (-- RAM block 1 OFF in OFF mode. Ram1Off, -- RAM block 1 ON in OFF mode. Ram1On) with Size => 1; - for OFFRAM1_Field use + for RAMON_OFFRAM1_Field use (Ram1Off => 0, Ram1On => 1); -- Ram on/off. type RAMON_Register is record -- RAM block 0 behaviour in ON mode. - ONRAM0 : ONRAM0_Field := Ram0On; + ONRAM0 : RAMON_ONRAM0_Field := nrf51.POWER.Ram0On; -- RAM block 1 behaviour in ON mode. - ONRAM1 : ONRAM1_Field := Ram1On; + ONRAM1 : RAMON_ONRAM1_Field := nrf51.POWER.Ram1On; -- unspecified Reserved_2_15 : nrf51.UInt14 := 16#0#; -- RAM block 0 behaviour in OFF mode. - OFFRAM0 : OFFRAM0_Field := Ram0Off; + OFFRAM0 : RAMON_OFFRAM0_Field := nrf51.POWER.Ram0Off; -- RAM block 1 behaviour in OFF mode. - OFFRAM1 : OFFRAM1_Field := Ram1Off; + OFFRAM1 : RAMON_OFFRAM1_Field := nrf51.POWER.Ram1Off; -- unspecified Reserved_18_31 : nrf51.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RAMON_Register use record @@ -482,19 +474,14 @@ package nrf51.POWER is Reserved_18_31 at 0 range 18 .. 31; end record; - -------------------- - -- RESET_Register -- - -------------------- - -- Enable or disable pin reset in debug interface mode. - type RESET_Field is - ( - -- Pin reset in debug interface mode disabled. + type RESET_RESET_Field is + (-- Pin reset in debug interface mode disabled. Disabled, -- Pin reset in debug interface mode enabled. Enabled) with Size => 1; - for RESET_Field use + for RESET_RESET_Field use (Disabled => 0, Enabled => 1); @@ -502,11 +489,11 @@ package nrf51.POWER is -- retained register. type RESET_Register is record -- Enable or disable pin reset in debug interface mode. - RESET : RESET_Field := Disabled; + RESET : RESET_RESET_Field := nrf51.POWER.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RESET_Register use record @@ -514,74 +501,66 @@ package nrf51.POWER is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- RAMONB_Register -- - --------------------- - -- RAM block 2 behaviour in ON mode. - type ONRAM2_Field is - ( - -- RAM block 2 OFF in ON mode. + type RAMONB_ONRAM2_Field is + (-- RAM block 2 OFF in ON mode. Ram2Off, -- RAM block 2 ON in ON mode. Ram2On) with Size => 1; - for ONRAM2_Field use + for RAMONB_ONRAM2_Field use (Ram2Off => 0, Ram2On => 1); -- RAM block 3 behaviour in ON mode. - type ONRAM3_Field is - ( - -- RAM block 33 OFF in ON mode. + type RAMONB_ONRAM3_Field is + (-- RAM block 33 OFF in ON mode. Ram3Off, -- RAM block 3 ON in ON mode. Ram3On) with Size => 1; - for ONRAM3_Field use + for RAMONB_ONRAM3_Field use (Ram3Off => 0, Ram3On => 1); -- RAM block 2 behaviour in OFF mode. - type OFFRAM2_Field is - ( - -- RAM block 2 OFF in OFF mode. + type RAMONB_OFFRAM2_Field is + (-- RAM block 2 OFF in OFF mode. Ram2Off, -- RAM block 2 ON in OFF mode. Ram2On) with Size => 1; - for OFFRAM2_Field use + for RAMONB_OFFRAM2_Field use (Ram2Off => 0, Ram2On => 1); -- RAM block 3 behaviour in OFF mode. - type OFFRAM3_Field is - ( - -- RAM block 3 OFF in OFF mode. + type RAMONB_OFFRAM3_Field is + (-- RAM block 3 OFF in OFF mode. Ram3Off, -- RAM block 3 ON in OFF mode. Ram3On) with Size => 1; - for OFFRAM3_Field use + for RAMONB_OFFRAM3_Field use (Ram3Off => 0, Ram3On => 1); -- Ram on/off. type RAMONB_Register is record -- RAM block 2 behaviour in ON mode. - ONRAM2 : ONRAM2_Field := Ram2On; + ONRAM2 : RAMONB_ONRAM2_Field := nrf51.POWER.Ram2On; -- RAM block 3 behaviour in ON mode. - ONRAM3 : ONRAM3_Field := Ram3On; + ONRAM3 : RAMONB_ONRAM3_Field := nrf51.POWER.Ram3On; -- unspecified Reserved_2_15 : nrf51.UInt14 := 16#0#; -- RAM block 2 behaviour in OFF mode. - OFFRAM2 : OFFRAM2_Field := Ram2Off; + OFFRAM2 : RAMONB_OFFRAM2_Field := nrf51.POWER.Ram2Off; -- RAM block 3 behaviour in OFF mode. - OFFRAM3 : OFFRAM3_Field := Ram3Off; + OFFRAM3 : RAMONB_OFFRAM3_Field := nrf51.POWER.Ram3Off; -- unspecified Reserved_18_31 : nrf51.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RAMONB_Register use record @@ -593,30 +572,25 @@ package nrf51.POWER is Reserved_18_31 at 0 range 18 .. 31; end record; - --------------------- - -- DCDCEN_Register -- - --------------------- - -- Enable DCDC converter. - type DCDCEN_Field is - ( - -- DCDC converter disabled. + type DCDCEN_DCDCEN_Field is + (-- DCDC converter disabled. Disabled, -- DCDC converter enabled. Enabled) with Size => 1; - for DCDCEN_Field use + for DCDCEN_DCDCEN_Field use (Disabled => 0, Enabled => 1); -- DCDC converter enable configuration register. type DCDCEN_Register is record -- Enable DCDC converter. - DCDCEN : DCDCEN_Field := Disabled; + DCDCEN : DCDCEN_DCDCEN_Field := nrf51.POWER.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DCDCEN_Register use record @@ -624,44 +598,38 @@ package nrf51.POWER is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- DCDCFORCE_Register -- - ------------------------ - -- DCDC power-up force off. - type FORCEOFF_Field is - ( - -- No force. + type DCDCFORCE_FORCEOFF_Field is + (-- No force. Noforce, -- Force. Force) with Size => 1; - for FORCEOFF_Field use + for DCDCFORCE_FORCEOFF_Field use (Noforce => 0, Force => 1); -- DCDC power-up force on. - type FORCEON_Field is - ( - -- No force. + type DCDCFORCE_FORCEON_Field is + (-- No force. Noforce, -- Force. Force) with Size => 1; - for FORCEON_Field use + for DCDCFORCE_FORCEON_Field use (Noforce => 0, Force => 1); -- DCDC power-up force register. type DCDCFORCE_Register is record -- DCDC power-up force off. - FORCEOFF : FORCEOFF_Field := Noforce; + FORCEOFF : DCDCFORCE_FORCEOFF_Field := nrf51.POWER.Noforce; -- DCDC power-up force on. - FORCEON : FORCEON_Field := Noforce; + FORCEON : DCDCFORCE_FORCEON_Field := nrf51.POWER.Noforce; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DCDCFORCE_Register use record @@ -677,56 +645,56 @@ package nrf51.POWER is -- Power Control. type POWER_Peripheral is record -- Enable constant latency mode. - TASKS_CONSTLAT : nrf51.Word; + TASKS_CONSTLAT : aliased nrf51.UInt32; -- Enable low power mode (variable latency). - TASKS_LOWPWR : nrf51.Word; + TASKS_LOWPWR : aliased nrf51.UInt32; -- Power failure warning. - EVENTS_POFWARN : nrf51.Word; + EVENTS_POFWARN : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Reset reason. - RESETREAS : RESETREAS_Register; + RESETREAS : aliased RESETREAS_Register; -- Ram status register. - RAMSTATUS : RAMSTATUS_Register; + RAMSTATUS : aliased RAMSTATUS_Register; -- System off register. - SYSTEMOFF : SYSTEMOFF_Register; + SYSTEMOFF : aliased SYSTEMOFF_Register; -- Power failure configuration. - POFCON : POFCON_Register; + POFCON : aliased POFCON_Register; -- General purpose retention register. This register is a retained -- register. - GPREGRET : GPREGRET_Register; + GPREGRET : aliased GPREGRET_Register; -- Ram on/off. - RAMON : RAMON_Register; + RAMON : aliased RAMON_Register; -- Pin reset functionality configuration register. This register is a -- retained register. - RESET : RESET_Register; + RESET : aliased RESET_Register; -- Ram on/off. - RAMONB : RAMONB_Register; + RAMONB : aliased RAMONB_Register; -- DCDC converter enable configuration register. - DCDCEN : DCDCEN_Register; + DCDCEN : aliased DCDCEN_Register; -- DCDC power-up force register. - DCDCFORCE : DCDCFORCE_Register; + DCDCFORCE : aliased DCDCFORCE_Register; end record with Volatile; for POWER_Peripheral use record - TASKS_CONSTLAT at 120 range 0 .. 31; - TASKS_LOWPWR at 124 range 0 .. 31; - EVENTS_POFWARN at 264 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - RESETREAS at 1024 range 0 .. 31; - RAMSTATUS at 1064 range 0 .. 31; - SYSTEMOFF at 1280 range 0 .. 31; - POFCON at 1296 range 0 .. 31; - GPREGRET at 1308 range 0 .. 31; - RAMON at 1316 range 0 .. 31; - RESET at 1348 range 0 .. 31; - RAMONB at 1364 range 0 .. 31; - DCDCEN at 1400 range 0 .. 31; - DCDCFORCE at 2568 range 0 .. 31; + TASKS_CONSTLAT at 16#78# range 0 .. 31; + TASKS_LOWPWR at 16#7C# range 0 .. 31; + EVENTS_POFWARN at 16#108# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + RESETREAS at 16#400# range 0 .. 31; + RAMSTATUS at 16#428# range 0 .. 31; + SYSTEMOFF at 16#500# range 0 .. 31; + POFCON at 16#510# range 0 .. 31; + GPREGRET at 16#51C# range 0 .. 31; + RAMON at 16#524# range 0 .. 31; + RESET at 16#544# range 0 .. 31; + RAMONB at 16#554# range 0 .. 31; + DCDCEN at 16#578# range 0 .. 31; + DCDCFORCE at 16#A08# range 0 .. 31; end record; -- Power Control. diff --git a/microbit/nrf51/nrf51-ppi.ads b/microbit/nrf51/nrf51-ppi.ads index ca12cfb..d33ae67 100644 --- a/microbit/nrf51/nrf51-ppi.ads +++ b/microbit/nrf51/nrf51-ppi.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,33 +43,40 @@ package nrf51.PPI is -- Registers -- --------------- - -- Channel group tasks. + --------------------------------------- + -- PPI_TASKS_CHG cluster's Registers -- + --------------------------------------- -- Channel group tasks. - type TASKS_CHG_Registers is array (0 .. 3) of nrf51.Word; + type PPI_TASKS_CHG_Cluster is record + -- Enable channel group. + EN : aliased nrf51.UInt32; + -- Disable channel group. + DIS : aliased nrf51.UInt32; + end record + with Size => 64; - ------------------- - -- CHEN_Register -- - ------------------- + for PPI_TASKS_CHG_Cluster use record + EN at 16#0# range 0 .. 31; + DIS at 16#4# range 0 .. 31; + end record; + + -- Channel group tasks. + type PPI_TASKS_CHG_Clusters is array (0 .. 3) of PPI_TASKS_CHG_Cluster; -- Enable PPI channel 0. - type CH0_Field is - ( - -- Channel disabled. + type CHEN_CH0_Field is + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) with Size => 1; - for CH0_Field use + for CHEN_CH0_Field use (Disabled => 0, Enabled => 1); - ------------- - -- CHEN.CH -- - ------------- - -- CHEN_CH array - type CHEN_CH_Field_Array is array (0 .. 2) of CH0_Field + type CHEN_CH_Field_Array is array (0 .. 2) of CHEN_CH0_Field with Component_Size => 1, Size => 3; -- Type definition for CHEN_CH @@ -62,35 +100,29 @@ package nrf51.PPI is end record; -- Enable PPI channel 3. - type CH3_Field is - ( - -- Channel disabled + type CHEN_CH3_Field is + (-- Channel disabled Disabled, -- Channel enabled Enabled) with Size => 1; - for CH3_Field use + for CHEN_CH3_Field use (Disabled => 0, Enabled => 1); -- Enable PPI channel 4. - type CH4_Field is - ( - -- Channel disabled. + type CHEN_CH4_Field is + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) with Size => 1; - for CH4_Field use + for CHEN_CH4_Field use (Disabled => 0, Enabled => 1); - ------------- - -- CHEN.CH -- - ------------- - -- CHEN_CH array - type CHEN_CH_Field_Array_1 is array (4 .. 15) of CH4_Field + type CHEN_CH_Field_Array_1 is array (4 .. 15) of CHEN_CH4_Field with Component_Size => 1, Size => 12; -- Type definition for CHEN_CH @@ -114,23 +146,18 @@ package nrf51.PPI is end record; -- Enable PPI channel 20. - type CH20_Field is - ( - -- Channel disabled. + type CHEN_CH20_Field is + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) with Size => 1; - for CH20_Field use + for CHEN_CH20_Field use (Disabled => 0, Enabled => 1); - ------------- - -- CHEN.CH -- - ------------- - -- CHEN_CH array - type CHEN_CH_Field_Array_2 is array (20 .. 31) of CH20_Field + type CHEN_CH_Field_Array_2 is array (20 .. 31) of CHEN_CH20_Field with Component_Size => 1, Size => 12; -- Type definition for CHEN_CH @@ -156,49 +183,51 @@ package nrf51.PPI is -- Channel enable. type CHEN_Register is record -- Enable PPI channel 0. - CH0 : CHEN_CH_Field := (As_Array => False, Val => 16#0#); + CH : CHEN_CH_Field := (As_Array => False, Val => 16#0#); -- Enable PPI channel 3. - CH3 : CH3_Field := Disabled; + CH3 : CHEN_CH3_Field := nrf51.PPI.Disabled; -- Enable PPI channel 4. - CH4 : CHEN_CH_Field_1 := (As_Array => False, Val => 16#0#); + CH_1 : CHEN_CH_Field_1 := (As_Array => False, Val => 16#0#); -- unspecified Reserved_16_19 : nrf51.UInt4 := 16#0#; -- Enable PPI channel 20. - CH20 : CHEN_CH_Field_2 := (As_Array => False, Val => 16#0#); + CH_2 : CHEN_CH_Field_2 := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CHEN_Register use record - CH0 at 0 range 0 .. 2; + CH at 0 range 0 .. 2; CH3 at 0 range 3 .. 3; - CH4 at 0 range 4 .. 15; + CH_1 at 0 range 4 .. 15; Reserved_16_19 at 0 range 16 .. 19; - CH20 at 0 range 20 .. 31; + CH_2 at 0 range 20 .. 31; end record; - ---------------------- - -- CHENSET_Register -- - ---------------------- + -- Enable PPI channel 0. + type CHENSET_CH0_Field is + (-- Channel disabled. + Disabled, + -- Channel enabled. + Enabled) + with Size => 1; + for CHENSET_CH0_Field use + (Disabled => 0, + Enabled => 1); -- Enable PPI channel 0. - type CH0_Field_1 is - ( - -- Reset value for the field - Ch0_Field_Reset, + type CHENSET_CH0_Field_1 is + (-- Reset value for the field + Chenset_Ch0_Field_Reset, -- Enable channel on write. Set) with Size => 1; - for CH0_Field_1 use - (Ch0_Field_Reset => 0, + for CHENSET_CH0_Field_1 use + (Chenset_Ch0_Field_Reset => 0, Set => 1); - ---------------- - -- CHENSET.CH -- - ---------------- - -- CHENSET_CH array - type CHENSET_CH_Field_Array is array (0 .. 15) of CH0_Field_1 + type CHENSET_CH_Field_Array is array (0 .. 15) of CHENSET_CH0_Field_1 with Component_Size => 1, Size => 16; -- Type definition for CHENSET_CH @@ -208,7 +237,7 @@ package nrf51.PPI is case As_Array is when False => -- CH as a value - Val : nrf51.Short; + Val : nrf51.UInt16; when True => -- CH as an array Arr : CHENSET_CH_Field_Array; @@ -222,23 +251,29 @@ package nrf51.PPI is end record; -- Enable PPI channel 20. - type CH20_Field_1 is - ( - -- Reset value for the field - Ch20_Field_Reset, + type CHENSET_CH20_Field is + (-- Channel disabled. + Disabled, + -- Channel enabled. + Enabled) + with Size => 1; + for CHENSET_CH20_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable PPI channel 20. + type CHENSET_CH20_Field_1 is + (-- Reset value for the field + Chenset_Ch20_Field_Reset, -- Enable channel on write. Set) with Size => 1; - for CH20_Field_1 use - (Ch20_Field_Reset => 0, + for CHENSET_CH20_Field_1 use + (Chenset_Ch20_Field_Reset => 0, Set => 1); - ---------------- - -- CHENSET.CH -- - ---------------- - -- CHENSET_CH array - type CHENSET_CH_Field_Array_1 is array (20 .. 31) of CH20_Field_1 + type CHENSET_CH_Field_Array_1 is array (20 .. 31) of CHENSET_CH20_Field_1 with Component_Size => 1, Size => 12; -- Type definition for CHENSET_CH @@ -264,44 +299,46 @@ package nrf51.PPI is -- Channel enable set. type CHENSET_Register is record -- Enable PPI channel 0. - CH0 : CHENSET_CH_Field := (As_Array => False, Val => 16#0#); + CH : CHENSET_CH_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_16_19 : nrf51.UInt4 := 16#0#; -- Enable PPI channel 20. - CH20 : CHENSET_CH_Field_1 := + CH_1 : CHENSET_CH_Field_1 := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CHENSET_Register use record - CH0 at 0 range 0 .. 15; + CH at 0 range 0 .. 15; Reserved_16_19 at 0 range 16 .. 19; - CH20 at 0 range 20 .. 31; + CH_1 at 0 range 20 .. 31; end record; - ---------------------- - -- CHENCLR_Register -- - ---------------------- + -- Disable PPI channel 0. + type CHENCLR_CH0_Field is + (-- Channel disabled. + Disabled, + -- Channel enabled. + Enabled) + with Size => 1; + for CHENCLR_CH0_Field use + (Disabled => 0, + Enabled => 1); -- Disable PPI channel 0. - type CH0_Field_2 is - ( - -- Reset value for the field - Ch0_Field_Reset, + type CHENCLR_CH0_Field_1 is + (-- Reset value for the field + Chenclr_Ch0_Field_Reset, -- Disable channel on write. Clear) with Size => 1; - for CH0_Field_2 use - (Ch0_Field_Reset => 0, + for CHENCLR_CH0_Field_1 use + (Chenclr_Ch0_Field_Reset => 0, Clear => 1); - ---------------- - -- CHENCLR.CH -- - ---------------- - -- CHENCLR_CH array - type CHENCLR_CH_Field_Array is array (0 .. 15) of CH0_Field_2 + type CHENCLR_CH_Field_Array is array (0 .. 15) of CHENCLR_CH0_Field_1 with Component_Size => 1, Size => 16; -- Type definition for CHENCLR_CH @@ -311,7 +348,7 @@ package nrf51.PPI is case As_Array is when False => -- CH as a value - Val : nrf51.Short; + Val : nrf51.UInt16; when True => -- CH as an array Arr : CHENCLR_CH_Field_Array; @@ -325,23 +362,29 @@ package nrf51.PPI is end record; -- Disable PPI channel 20. - type CH20_Field_2 is - ( - -- Reset value for the field - Ch20_Field_Reset, + type CHENCLR_CH20_Field is + (-- Channel disabled. + Disabled, + -- Channel enabled. + Enabled) + with Size => 1; + for CHENCLR_CH20_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable PPI channel 20. + type CHENCLR_CH20_Field_1 is + (-- Reset value for the field + Chenclr_Ch20_Field_Reset, -- Disable channel on write. Clear) with Size => 1; - for CH20_Field_2 use - (Ch20_Field_Reset => 0, + for CHENCLR_CH20_Field_1 use + (Chenclr_Ch20_Field_Reset => 0, Clear => 1); - ---------------- - -- CHENCLR.CH -- - ---------------- - -- CHENCLR_CH array - type CHENCLR_CH_Field_Array_1 is array (20 .. 31) of CH20_Field_2 + type CHENCLR_CH_Field_Array_1 is array (20 .. 31) of CHENCLR_CH20_Field_1 with Component_Size => 1, Size => 12; -- Type definition for CHENCLR_CH @@ -367,49 +410,56 @@ package nrf51.PPI is -- Channel enable clear. type CHENCLR_Register is record -- Disable PPI channel 0. - CH0 : CHENCLR_CH_Field := (As_Array => False, Val => 16#0#); + CH : CHENCLR_CH_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_16_19 : nrf51.UInt4 := 16#0#; -- Disable PPI channel 20. - CH20 : CHENCLR_CH_Field_1 := + CH_1 : CHENCLR_CH_Field_1 := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CHENCLR_Register use record - CH0 at 0 range 0 .. 15; + CH at 0 range 0 .. 15; Reserved_16_19 at 0 range 16 .. 19; - CH20 at 0 range 20 .. 31; + CH_1 at 0 range 20 .. 31; end record; - -- PPI Channel. + -------------------------------- + -- PPI_CH cluster's Registers -- + -------------------------------- -- PPI Channel. - type CH_Registers is array (0 .. 15) of nrf51.Word; + type PPI_CH_Cluster is record + -- Channel event end-point. + EEP : aliased nrf51.UInt32; + -- Channel task end-point. + TEP : aliased nrf51.UInt32; + end record + with Size => 64; + + for PPI_CH_Cluster use record + EEP at 16#0# range 0 .. 31; + TEP at 16#4# range 0 .. 31; + end record; - ------------------ - -- CHG_Register -- - ------------------ + -- PPI Channel. + type PPI_CH_Clusters is array (0 .. 15) of PPI_CH_Cluster; -- Include CH0 in channel group. - type CH0_Field_3 is - ( - -- Channel excluded. + type CHG_CH0_Field is + (-- Channel excluded. Excluded, -- Channel included. Included) with Size => 1; - for CH0_Field_3 use + for CHG_CH0_Field use (Excluded => 0, Included => 1); - ------------ - -- CHG.CH -- - ------------ - -- CHG_CH array - type CHG_CH_Field_Array is array (0 .. 15) of CH0_Field_3 + type CHG_CH_Field_Array is array (0 .. 15) of CHG_CH0_Field with Component_Size => 1, Size => 16; -- Type definition for CHG_CH @@ -419,7 +469,7 @@ package nrf51.PPI is case As_Array is when False => -- CH as a value - Val : nrf51.Short; + Val : nrf51.UInt16; when True => -- CH as an array Arr : CHG_CH_Field_Array; @@ -433,23 +483,18 @@ package nrf51.PPI is end record; -- Include CH20 in channel group. - type CH20_Field_3 is - ( - -- Channel excluded. + type CHG_CH20_Field is + (-- Channel excluded. Excluded, -- Channel included. Included) with Size => 1; - for CH20_Field_3 use + for CHG_CH20_Field use (Excluded => 0, Included => 1); - ------------ - -- CHG.CH -- - ------------ - -- CHG_CH array - type CHG_CH_Field_Array_1 is array (20 .. 31) of CH20_Field_3 + type CHG_CH_Field_Array_1 is array (20 .. 31) of CHG_CH20_Field with Component_Size => 1, Size => 12; -- Type definition for CHG_CH @@ -475,19 +520,19 @@ package nrf51.PPI is -- Channel group configuration. type CHG_Register is record -- Include CH0 in channel group. - CH0 : CHG_CH_Field := (As_Array => False, Val => 16#0#); + CH : CHG_CH_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_16_19 : nrf51.UInt4 := 16#0#; -- Include CH20 in channel group. - CH20 : CHG_CH_Field_1 := (As_Array => False, Val => 16#0#); + CH_1 : CHG_CH_Field_1 := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CHG_Register use record - CH0 at 0 range 0 .. 15; + CH at 0 range 0 .. 15; Reserved_16_19 at 0 range 16 .. 19; - CH20 at 0 range 20 .. 31; + CH_1 at 0 range 20 .. 31; end record; -- Channel group configuration. @@ -500,29 +545,27 @@ package nrf51.PPI is -- PPI controller. type PPI_Peripheral is record -- Channel group tasks. - TASKS_CHG : TASKS_CHG_Registers; + TASKS_CHG : aliased PPI_TASKS_CHG_Clusters; -- Channel enable. - CHEN : CHEN_Register; + CHEN : aliased CHEN_Register; -- Channel enable set. - CHENSET : CHENSET_Register; + CHENSET : aliased CHENSET_Register; -- Channel enable clear. - CHENCLR : CHENCLR_Register; + CHENCLR : aliased CHENCLR_Register; -- PPI Channel. - CH : CH_Registers; + CH : aliased PPI_CH_Clusters; -- Channel group configuration. - CHG : CHG_Registers; + CHG : aliased CHG_Registers; end record with Volatile; for PPI_Peripheral use record - pragma Warnings (Off, "bits of*unused"); - TASKS_CHG at 0 range 0 .. 255; - CHEN at 1280 range 0 .. 31; - CHENSET at 1284 range 0 .. 31; - CHENCLR at 1288 range 0 .. 31; - CH at 1296 range 0 .. 1023; - CHG at 2048 range 0 .. 127; - pragma Warnings (On, "bits of*unused"); + TASKS_CHG at 16#0# range 0 .. 255; + CHEN at 16#500# range 0 .. 31; + CHENSET at 16#504# range 0 .. 31; + CHENCLR at 16#508# range 0 .. 31; + CH at 16#510# range 0 .. 1023; + CHG at 16#800# range 0 .. 127; end record; -- PPI controller. diff --git a/microbit/nrf51/nrf51-qdec.ads b/microbit/nrf51/nrf51-qdec.ads index 4baf682..1b7a57c 100644 --- a/microbit/nrf51/nrf51-qdec.ads +++ b/microbit/nrf51/nrf51-qdec.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,44 +43,40 @@ package nrf51.QDEC is -- Registers -- --------------- - --------------------- - -- SHORTS_Register -- - --------------------- - -- Shortcut between REPORTRDY event and READCLRACC task. - type REPORTRDY_READCLRACC_Field is - ( - -- Shortcut disabled. + type SHORTS_REPORTRDY_READCLRACC_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for REPORTRDY_READCLRACC_Field use + for SHORTS_REPORTRDY_READCLRACC_Field use (Disabled => 0, Enabled => 1); -- Shortcut between SAMPLERDY event and STOP task. - type SAMPLERDY_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_SAMPLERDY_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for SAMPLERDY_STOP_Field use + for SHORTS_SAMPLERDY_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcuts for the QDEC. type SHORTS_Register is record -- Shortcut between REPORTRDY event and READCLRACC task. - REPORTRDY_READCLRACC : REPORTRDY_READCLRACC_Field := Disabled; + REPORTRDY_READCLRACC : SHORTS_REPORTRDY_READCLRACC_Field := + nrf51.QDEC.Disabled; -- Shortcut between SAMPLERDY event and STOP task. - SAMPLERDY_STOP : SAMPLERDY_STOP_Field := Disabled; + SAMPLERDY_STOP : SHORTS_SAMPLERDY_STOP_Field := + nrf51.QDEC.Disabled; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -58,94 +85,86 @@ package nrf51.QDEC is Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on SAMPLERDY event. - type SAMPLERDY_Field is - ( - -- Interrupt disabled. + type INTENSET_SAMPLERDY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for SAMPLERDY_Field use + for INTENSET_SAMPLERDY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on SAMPLERDY event. - type SAMPLERDY_Field_1 is - ( - -- Reset value for the field - Samplerdy_Field_Reset, + type INTENSET_SAMPLERDY_Field_1 is + (-- Reset value for the field + Intenset_Samplerdy_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for SAMPLERDY_Field_1 use - (Samplerdy_Field_Reset => 0, + for INTENSET_SAMPLERDY_Field_1 use + (Intenset_Samplerdy_Field_Reset => 0, Set => 1); -- Enable interrupt on REPORTRDY event. - type REPORTRDY_Field is - ( - -- Interrupt disabled. + type INTENSET_REPORTRDY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for REPORTRDY_Field use + for INTENSET_REPORTRDY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on REPORTRDY event. - type REPORTRDY_Field_1 is - ( - -- Reset value for the field - Reportrdy_Field_Reset, + type INTENSET_REPORTRDY_Field_1 is + (-- Reset value for the field + Intenset_Reportrdy_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for REPORTRDY_Field_1 use - (Reportrdy_Field_Reset => 0, + for INTENSET_REPORTRDY_Field_1 use + (Intenset_Reportrdy_Field_Reset => 0, Set => 1); -- Enable interrupt on ACCOF event. - type ACCOF_Field is - ( - -- Interrupt disabled. + type INTENSET_ACCOF_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ACCOF_Field use + for INTENSET_ACCOF_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ACCOF event. - type ACCOF_Field_1 is - ( - -- Reset value for the field - Accof_Field_Reset, + type INTENSET_ACCOF_Field_1 is + (-- Reset value for the field + Intenset_Accof_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ACCOF_Field_1 use - (Accof_Field_Reset => 0, + for INTENSET_ACCOF_Field_1 use + (Intenset_Accof_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on SAMPLERDY event. - SAMPLERDY : SAMPLERDY_Field_1 := Samplerdy_Field_Reset; + SAMPLERDY : INTENSET_SAMPLERDY_Field_1 := + Intenset_Samplerdy_Field_Reset; -- Enable interrupt on REPORTRDY event. - REPORTRDY : REPORTRDY_Field_1 := Reportrdy_Field_Reset; + REPORTRDY : INTENSET_REPORTRDY_Field_1 := + Intenset_Reportrdy_Field_Reset; -- Enable interrupt on ACCOF event. - ACCOF : ACCOF_Field_1 := Accof_Field_Reset; + ACCOF : INTENSET_ACCOF_Field_1 := Intenset_Accof_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -155,58 +174,86 @@ package nrf51.QDEC is Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on SAMPLERDY event. + type INTENCLR_SAMPLERDY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_SAMPLERDY_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on SAMPLERDY event. - type SAMPLERDY_Field_2 is - ( - -- Reset value for the field - Samplerdy_Field_Reset, + type INTENCLR_SAMPLERDY_Field_1 is + (-- Reset value for the field + Intenclr_Samplerdy_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for SAMPLERDY_Field_2 use - (Samplerdy_Field_Reset => 0, + for INTENCLR_SAMPLERDY_Field_1 use + (Intenclr_Samplerdy_Field_Reset => 0, Clear => 1); -- Disable interrupt on REPORTRDY event. - type REPORTRDY_Field_2 is - ( - -- Reset value for the field - Reportrdy_Field_Reset, + type INTENCLR_REPORTRDY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_REPORTRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on REPORTRDY event. + type INTENCLR_REPORTRDY_Field_1 is + (-- Reset value for the field + Intenclr_Reportrdy_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for REPORTRDY_Field_2 use - (Reportrdy_Field_Reset => 0, + for INTENCLR_REPORTRDY_Field_1 use + (Intenclr_Reportrdy_Field_Reset => 0, Clear => 1); -- Disable interrupt on ACCOF event. - type ACCOF_Field_2 is - ( - -- Reset value for the field - Accof_Field_Reset, + type INTENCLR_ACCOF_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ACCOF_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ACCOF event. + type INTENCLR_ACCOF_Field_1 is + (-- Reset value for the field + Intenclr_Accof_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ACCOF_Field_2 use - (Accof_Field_Reset => 0, + for INTENCLR_ACCOF_Field_1 use + (Intenclr_Accof_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on SAMPLERDY event. - SAMPLERDY : SAMPLERDY_Field_2 := Samplerdy_Field_Reset; + SAMPLERDY : INTENCLR_SAMPLERDY_Field_1 := + Intenclr_Samplerdy_Field_Reset; -- Disable interrupt on REPORTRDY event. - REPORTRDY : REPORTRDY_Field_2 := Reportrdy_Field_Reset; + REPORTRDY : INTENCLR_REPORTRDY_Field_1 := + Intenclr_Reportrdy_Field_Reset; -- Disable interrupt on ACCOF event. - ACCOF : ACCOF_Field_2 := Accof_Field_Reset; + ACCOF : INTENCLR_ACCOF_Field_1 := Intenclr_Accof_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -216,30 +263,25 @@ package nrf51.QDEC is Reserved_3_31 at 0 range 3 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- Enable or disable QDEC. - type ENABLE_Field is - ( - -- Disabled QDEC. + type ENABLE_ENABLE_Field is + (-- Disabled QDEC. Disabled, -- Enable QDEC. Enabled) with Size => 1; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 1); -- Enable the QDEC. type ENABLE_Register is record -- Enable or disable QDEC. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.QDEC.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -247,30 +289,25 @@ package nrf51.QDEC is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- LEDPOL_Register -- - --------------------- - -- LED output pin polarity. - type LEDPOL_Field is - ( - -- LED output is active low. + type LEDPOL_LEDPOL_Field is + (-- LED output is active low. Activelow, -- LED output is active high. Activehigh) with Size => 1; - for LEDPOL_Field use + for LEDPOL_LEDPOL_Field use (Activelow => 0, Activehigh => 1); -- LED output pin polarity. type LEDPOL_Register is record -- LED output pin polarity. - LEDPOL : LEDPOL_Field := Activelow; + LEDPOL : LEDPOL_LEDPOL_Field := nrf51.QDEC.Activelow; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LEDPOL_Register use record @@ -278,48 +315,43 @@ package nrf51.QDEC is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- SAMPLEPER_Register -- - ------------------------ - -- Sample period. - type SAMPLEPER_Field is - ( - -- 128us sample period. - SAMPLEPER_Field_128US, + type SAMPLEPER_SAMPLEPER_Field is + (-- 128us sample period. + Val_128US, -- 256us sample period. - SAMPLEPER_Field_256US, + Val_256US, -- 512us sample period. - SAMPLEPER_Field_512US, + Val_512US, -- 1024us sample period. - SAMPLEPER_Field_1024US, + Val_1024US, -- 2048us sample period. - SAMPLEPER_Field_2048US, + Val_2048US, -- 4096us sample period. - SAMPLEPER_Field_4096US, + Val_4096US, -- 8192us sample period. - SAMPLEPER_Field_8192US, + Val_8192US, -- 16384us sample period. - SAMPLEPER_Field_16384US) + Val_16384US) with Size => 3; - for SAMPLEPER_Field use - (SAMPLEPER_Field_128US => 0, - SAMPLEPER_Field_256US => 1, - SAMPLEPER_Field_512US => 2, - SAMPLEPER_Field_1024US => 3, - SAMPLEPER_Field_2048US => 4, - SAMPLEPER_Field_4096US => 5, - SAMPLEPER_Field_8192US => 6, - SAMPLEPER_Field_16384US => 7); + for SAMPLEPER_SAMPLEPER_Field use + (Val_128US => 0, + Val_256US => 1, + Val_512US => 2, + Val_1024US => 3, + Val_2048US => 4, + Val_4096US => 5, + Val_8192US => 6, + Val_16384US => 7); -- Sample period. type SAMPLEPER_Register is record -- Sample period. - SAMPLEPER : SAMPLEPER_Field := SAMPLEPER_Field_128US; + SAMPLEPER : SAMPLEPER_SAMPLEPER_Field := nrf51.QDEC.Val_128US; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SAMPLEPER_Register use record @@ -327,48 +359,43 @@ package nrf51.QDEC is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------------ - -- REPORTPER_Register -- - ------------------------ - -- Number of samples to generate an EVENT_REPORTRDY. - type REPORTPER_Field is - ( - -- 10 samples per report. - REPORTPER_Field_10Smpl, + type REPORTPER_REPORTPER_Field is + (-- 10 samples per report. + Val_10Smpl, -- 40 samples per report. - REPORTPER_Field_40Smpl, + Val_40Smpl, -- 80 samples per report. - REPORTPER_Field_80Smpl, + Val_80Smpl, -- 120 samples per report. - REPORTPER_Field_120Smpl, + Val_120Smpl, -- 160 samples per report. - REPORTPER_Field_160Smpl, + Val_160Smpl, -- 200 samples per report. - REPORTPER_Field_200Smpl, + Val_200Smpl, -- 240 samples per report. - REPORTPER_Field_240Smpl, + Val_240Smpl, -- 280 samples per report. - REPORTPER_Field_280Smpl) + Val_280Smpl) with Size => 3; - for REPORTPER_Field use - (REPORTPER_Field_10Smpl => 0, - REPORTPER_Field_40Smpl => 1, - REPORTPER_Field_80Smpl => 2, - REPORTPER_Field_120Smpl => 3, - REPORTPER_Field_160Smpl => 4, - REPORTPER_Field_200Smpl => 5, - REPORTPER_Field_240Smpl => 6, - REPORTPER_Field_280Smpl => 7); + for REPORTPER_REPORTPER_Field use + (Val_10Smpl => 0, + Val_40Smpl => 1, + Val_80Smpl => 2, + Val_120Smpl => 3, + Val_160Smpl => 4, + Val_200Smpl => 5, + Val_240Smpl => 6, + Val_280Smpl => 7); -- Number of samples to generate an EVENT_REPORTRDY. type REPORTPER_Register is record -- Number of samples to generate an EVENT_REPORTRDY. - REPORTPER : REPORTPER_Field := REPORTPER_Field_10Smpl; + REPORTPER : REPORTPER_REPORTPER_Field := nrf51.QDEC.Val_10Smpl; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for REPORTPER_Register use record @@ -376,30 +403,25 @@ package nrf51.QDEC is Reserved_3_31 at 0 range 3 .. 31; end record; - -------------------- - -- DBFEN_Register -- - -------------------- - -- Enable debounce input filters. - type DBFEN_Field is - ( - -- Debounce input filters disabled. + type DBFEN_DBFEN_Field is + (-- Debounce input filters disabled. Disabled, -- Debounce input filters enabled. Enabled) with Size => 1; - for DBFEN_Field use + for DBFEN_DBFEN_Field use (Disabled => 0, Enabled => 1); -- Enable debouncer input filters. type DBFEN_Register is record -- Enable debounce input filters. - DBFEN : DBFEN_Field := Disabled; + DBFEN : DBFEN_DBFEN_Field := nrf51.QDEC.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DBFEN_Register use record @@ -407,10 +429,6 @@ package nrf51.QDEC is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- LEDPRE_Register -- - --------------------- - subtype LEDPRE_LEDPRE_Field is nrf51.UInt9; -- Time LED is switched ON before the sample. @@ -420,7 +438,7 @@ package nrf51.QDEC is -- unspecified Reserved_9_31 : nrf51.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LEDPRE_Register use record @@ -428,10 +446,6 @@ package nrf51.QDEC is Reserved_9_31 at 0 range 9 .. 31; end record; - --------------------- - -- ACCDBL_Register -- - --------------------- - subtype ACCDBL_ACCDBL_Field is nrf51.UInt4; -- Accumulated double (error) transitions register. @@ -441,7 +455,7 @@ package nrf51.QDEC is -- unspecified Reserved_4_31 : nrf51.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ACCDBL_Register use record @@ -449,10 +463,6 @@ package nrf51.QDEC is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------------- - -- ACCDBLREAD_Register -- - ------------------------- - subtype ACCDBLREAD_ACCDBLREAD_Field is nrf51.UInt4; -- Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC @@ -463,7 +473,7 @@ package nrf51.QDEC is -- unspecified Reserved_4_31 : nrf51.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ACCDBLREAD_Register use record @@ -471,30 +481,25 @@ package nrf51.QDEC is Reserved_4_31 at 0 range 4 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.QDEC.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -509,85 +514,85 @@ package nrf51.QDEC is -- Rotary decoder. type QDEC_Peripheral is record -- Start the quadrature decoder. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop the quadrature decoder. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Transfers the content from ACC registers to ACCREAD registers, and -- clears the ACC registers. - TASKS_READCLRACC : nrf51.Word; + TASKS_READCLRACC : aliased nrf51.UInt32; -- A new sample is written to the sample register. - EVENTS_SAMPLERDY : nrf51.Word; + EVENTS_SAMPLERDY : aliased nrf51.UInt32; -- REPORTPER number of samples accumulated in ACC register, and ACC -- register different than zero. - EVENTS_REPORTRDY : nrf51.Word; + EVENTS_REPORTRDY : aliased nrf51.UInt32; -- ACC or ACCDBL register overflow. - EVENTS_ACCOF : nrf51.Word; + EVENTS_ACCOF : aliased nrf51.UInt32; -- Shortcuts for the QDEC. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Enable the QDEC. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- LED output pin polarity. - LEDPOL : LEDPOL_Register; + LEDPOL : aliased LEDPOL_Register; -- Sample period. - SAMPLEPER : SAMPLEPER_Register; + SAMPLEPER : aliased SAMPLEPER_Register; -- Motion sample value. - SAMPLE : nrf51.Word; + SAMPLE : aliased nrf51.UInt32; -- Number of samples to generate an EVENT_REPORTRDY. - REPORTPER : REPORTPER_Register; + REPORTPER : aliased REPORTPER_Register; -- Accumulated valid transitions register. - ACC : nrf51.Word; + ACC : aliased nrf51.UInt32; -- Snapshot of ACC register. Value generated by the TASKS_READCLEACC -- task. - ACCREAD : nrf51.Word; + ACCREAD : aliased nrf51.UInt32; -- Pin select for LED output. - PSELLED : nrf51.Word; + PSELLED : aliased nrf51.UInt32; -- Pin select for phase A input. - PSELA : nrf51.Word; + PSELA : aliased nrf51.UInt32; -- Pin select for phase B input. - PSELB : nrf51.Word; + PSELB : aliased nrf51.UInt32; -- Enable debouncer input filters. - DBFEN : DBFEN_Register; + DBFEN : aliased DBFEN_Register; -- Time LED is switched ON before the sample. - LEDPRE : LEDPRE_Register; + LEDPRE : aliased LEDPRE_Register; -- Accumulated double (error) transitions register. - ACCDBL : ACCDBL_Register; + ACCDBL : aliased ACCDBL_Register; -- Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC -- task. - ACCDBLREAD : ACCDBLREAD_Register; + ACCDBLREAD : aliased ACCDBLREAD_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for QDEC_Peripheral use record - TASKS_START at 0 range 0 .. 31; - TASKS_STOP at 4 range 0 .. 31; - TASKS_READCLRACC at 8 range 0 .. 31; - EVENTS_SAMPLERDY at 256 range 0 .. 31; - EVENTS_REPORTRDY at 260 range 0 .. 31; - EVENTS_ACCOF at 264 range 0 .. 31; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - LEDPOL at 1284 range 0 .. 31; - SAMPLEPER at 1288 range 0 .. 31; - SAMPLE at 1292 range 0 .. 31; - REPORTPER at 1296 range 0 .. 31; - ACC at 1300 range 0 .. 31; - ACCREAD at 1304 range 0 .. 31; - PSELLED at 1308 range 0 .. 31; - PSELA at 1312 range 0 .. 31; - PSELB at 1316 range 0 .. 31; - DBFEN at 1320 range 0 .. 31; - LEDPRE at 1344 range 0 .. 31; - ACCDBL at 1348 range 0 .. 31; - ACCDBLREAD at 1352 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_READCLRACC at 16#8# range 0 .. 31; + EVENTS_SAMPLERDY at 16#100# range 0 .. 31; + EVENTS_REPORTRDY at 16#104# range 0 .. 31; + EVENTS_ACCOF at 16#108# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + LEDPOL at 16#504# range 0 .. 31; + SAMPLEPER at 16#508# range 0 .. 31; + SAMPLE at 16#50C# range 0 .. 31; + REPORTPER at 16#510# range 0 .. 31; + ACC at 16#514# range 0 .. 31; + ACCREAD at 16#518# range 0 .. 31; + PSELLED at 16#51C# range 0 .. 31; + PSELA at 16#520# range 0 .. 31; + PSELB at 16#524# range 0 .. 31; + DBFEN at 16#528# range 0 .. 31; + LEDPRE at 16#540# range 0 .. 31; + ACCDBL at 16#544# range 0 .. 31; + ACCDBLREAD at 16#548# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- Rotary decoder. diff --git a/microbit/nrf51/nrf51-radio.ads b/microbit/nrf51/nrf51-radio.ads index 7d0eb00..a4a5965 100644 --- a/microbit/nrf51/nrf51-radio.ads +++ b/microbit/nrf51/nrf51-radio.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,130 +43,121 @@ package nrf51.RADIO is -- Registers -- --------------- - --------------------- - -- SHORTS_Register -- - --------------------- - -- Shortcut between READY event and START task. - type READY_START_Field is - ( - -- Shortcut disabled. + type SHORTS_READY_START_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for READY_START_Field use + for SHORTS_READY_START_Field use (Disabled => 0, Enabled => 1); -- Shortcut between END event and DISABLE task. - type END_DISABLE_Field is - ( - -- Shortcut disabled. + type SHORTS_END_DISABLE_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for END_DISABLE_Field use + for SHORTS_END_DISABLE_Field use (Disabled => 0, Enabled => 1); -- Shortcut between DISABLED event and TXEN task. - type DISABLED_TXEN_Field is - ( - -- Shortcut disabled. + type SHORTS_DISABLED_TXEN_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for DISABLED_TXEN_Field use + for SHORTS_DISABLED_TXEN_Field use (Disabled => 0, Enabled => 1); -- Shortcut between DISABLED event and RXEN task. - type DISABLED_RXEN_Field is - ( - -- Shortcut disabled. + type SHORTS_DISABLED_RXEN_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for DISABLED_RXEN_Field use + for SHORTS_DISABLED_RXEN_Field use (Disabled => 0, Enabled => 1); -- Shortcut between ADDRESS event and RSSISTART task. - type ADDRESS_RSSISTART_Field is - ( - -- Shortcut disabled. + type SHORTS_ADDRESS_RSSISTART_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for ADDRESS_RSSISTART_Field use + for SHORTS_ADDRESS_RSSISTART_Field use (Disabled => 0, Enabled => 1); -- Shortcut between END event and START task. - type END_START_Field is - ( - -- Shortcut disabled. + type SHORTS_END_START_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for END_START_Field use + for SHORTS_END_START_Field use (Disabled => 0, Enabled => 1); -- Shortcut between ADDRESS event and BCSTART task. - type ADDRESS_BCSTART_Field is - ( - -- Shortcut disabled. + type SHORTS_ADDRESS_BCSTART_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for ADDRESS_BCSTART_Field use + for SHORTS_ADDRESS_BCSTART_Field use (Disabled => 0, Enabled => 1); -- Shortcut between DISABLED event and RSSISTOP task. - type DISABLED_RSSISTOP_Field is - ( - -- Shortcut disabled. + type SHORTS_DISABLED_RSSISTOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for DISABLED_RSSISTOP_Field use + for SHORTS_DISABLED_RSSISTOP_Field use (Disabled => 0, Enabled => 1); -- Shortcuts for the radio. type SHORTS_Register is record -- Shortcut between READY event and START task. - READY_START : READY_START_Field := Disabled; + READY_START : SHORTS_READY_START_Field := nrf51.RADIO.Disabled; -- Shortcut between END event and DISABLE task. - END_DISABLE : END_DISABLE_Field := Disabled; + END_DISABLE : SHORTS_END_DISABLE_Field := nrf51.RADIO.Disabled; -- Shortcut between DISABLED event and TXEN task. - DISABLED_TXEN : DISABLED_TXEN_Field := Disabled; + DISABLED_TXEN : SHORTS_DISABLED_TXEN_Field := nrf51.RADIO.Disabled; -- Shortcut between DISABLED event and RXEN task. - DISABLED_RXEN : DISABLED_RXEN_Field := Disabled; + DISABLED_RXEN : SHORTS_DISABLED_RXEN_Field := nrf51.RADIO.Disabled; -- Shortcut between ADDRESS event and RSSISTART task. - ADDRESS_RSSISTART : ADDRESS_RSSISTART_Field := Disabled; + ADDRESS_RSSISTART : SHORTS_ADDRESS_RSSISTART_Field := + nrf51.RADIO.Disabled; -- Shortcut between END event and START task. - END_START : END_START_Field := Disabled; + END_START : SHORTS_END_START_Field := nrf51.RADIO.Disabled; -- Shortcut between ADDRESS event and BCSTART task. - ADDRESS_BCSTART : ADDRESS_BCSTART_Field := Disabled; + ADDRESS_BCSTART : SHORTS_ADDRESS_BCSTART_Field := + nrf51.RADIO.Disabled; -- unspecified Reserved_7_7 : nrf51.Bit := 16#0#; -- Shortcut between DISABLED event and RSSISTOP task. - DISABLED_RSSISTOP : DISABLED_RSSISTOP_Field := Disabled; + DISABLED_RSSISTOP : SHORTS_DISABLED_RSSISTOP_Field := + nrf51.RADIO.Disabled; -- unspecified Reserved_9_31 : nrf51.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -151,252 +173,237 @@ package nrf51.RADIO is Reserved_9_31 at 0 range 9 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on READY event. - type READY_Field is - ( - -- Interrupt disabled. + type INTENSET_READY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for READY_Field use + for INTENSET_READY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on READY event. - type READY_Field_1 is - ( - -- Reset value for the field - Ready_Field_Reset, + type INTENSET_READY_Field_1 is + (-- Reset value for the field + Intenset_Ready_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for READY_Field_1 use - (Ready_Field_Reset => 0, + for INTENSET_READY_Field_1 use + (Intenset_Ready_Field_Reset => 0, Set => 1); -- Enable interrupt on ADDRESS event. - type ADDRESS_Field is - ( - -- Interrupt disabled. + type INTENSET_ADDRESS_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ADDRESS_Field use + for INTENSET_ADDRESS_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ADDRESS event. - type ADDRESS_Field_1 is - ( - -- Reset value for the field - Address_Field_Reset, + type INTENSET_ADDRESS_Field_1 is + (-- Reset value for the field + Intenset_Address_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ADDRESS_Field_1 use - (Address_Field_Reset => 0, + for INTENSET_ADDRESS_Field_1 use + (Intenset_Address_Field_Reset => 0, Set => 1); -- Enable interrupt on PAYLOAD event. - type PAYLOAD_Field is - ( - -- Interrupt disabled. + type INTENSET_PAYLOAD_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for PAYLOAD_Field use + for INTENSET_PAYLOAD_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on PAYLOAD event. - type PAYLOAD_Field_1 is - ( - -- Reset value for the field - Payload_Field_Reset, + type INTENSET_PAYLOAD_Field_1 is + (-- Reset value for the field + Intenset_Payload_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for PAYLOAD_Field_1 use - (Payload_Field_Reset => 0, + for INTENSET_PAYLOAD_Field_1 use + (Intenset_Payload_Field_Reset => 0, Set => 1); -- Enable interrupt on END event. - type END_Field is - ( - -- Interrupt disabled. + type INTENSET_END_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for END_Field use + for INTENSET_END_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on END event. - type END_Field_1 is - ( - -- Reset value for the field - End_Field_Reset, + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for END_Field_1 use - (End_Field_Reset => 0, + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, Set => 1); -- Enable interrupt on DISABLED event. - type DISABLED_Field is - ( - -- Interrupt disabled. + type INTENSET_DISABLED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for DISABLED_Field use + for INTENSET_DISABLED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on DISABLED event. - type DISABLED_Field_1 is - ( - -- Reset value for the field - Disabled_Field_Reset, + type INTENSET_DISABLED_Field_1 is + (-- Reset value for the field + Intenset_Disabled_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for DISABLED_Field_1 use - (Disabled_Field_Reset => 0, + for INTENSET_DISABLED_Field_1 use + (Intenset_Disabled_Field_Reset => 0, Set => 1); -- Enable interrupt on DEVMATCH event. - type DEVMATCH_Field is - ( - -- Interrupt disabled. + type INTENSET_DEVMATCH_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for DEVMATCH_Field use + for INTENSET_DEVMATCH_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on DEVMATCH event. - type DEVMATCH_Field_1 is - ( - -- Reset value for the field - Devmatch_Field_Reset, + type INTENSET_DEVMATCH_Field_1 is + (-- Reset value for the field + Intenset_Devmatch_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for DEVMATCH_Field_1 use - (Devmatch_Field_Reset => 0, + for INTENSET_DEVMATCH_Field_1 use + (Intenset_Devmatch_Field_Reset => 0, Set => 1); -- Enable interrupt on DEVMISS event. - type DEVMISS_Field is - ( - -- Interrupt disabled. + type INTENSET_DEVMISS_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for DEVMISS_Field use + for INTENSET_DEVMISS_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on DEVMISS event. - type DEVMISS_Field_1 is - ( - -- Reset value for the field - Devmiss_Field_Reset, + type INTENSET_DEVMISS_Field_1 is + (-- Reset value for the field + Intenset_Devmiss_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for DEVMISS_Field_1 use - (Devmiss_Field_Reset => 0, + for INTENSET_DEVMISS_Field_1 use + (Intenset_Devmiss_Field_Reset => 0, Set => 1); -- Enable interrupt on RSSIEND event. - type RSSIEND_Field is - ( - -- Interrupt disabled. + type INTENSET_RSSIEND_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for RSSIEND_Field use + for INTENSET_RSSIEND_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on RSSIEND event. - type RSSIEND_Field_1 is - ( - -- Reset value for the field - Rssiend_Field_Reset, + type INTENSET_RSSIEND_Field_1 is + (-- Reset value for the field + Intenset_Rssiend_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for RSSIEND_Field_1 use - (Rssiend_Field_Reset => 0, + for INTENSET_RSSIEND_Field_1 use + (Intenset_Rssiend_Field_Reset => 0, Set => 1); -- Enable interrupt on BCMATCH event. - type BCMATCH_Field is - ( - -- Interrupt disabled. + type INTENSET_BCMATCH_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for BCMATCH_Field use + for INTENSET_BCMATCH_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on BCMATCH event. - type BCMATCH_Field_1 is - ( - -- Reset value for the field - Bcmatch_Field_Reset, + type INTENSET_BCMATCH_Field_1 is + (-- Reset value for the field + Intenset_Bcmatch_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for BCMATCH_Field_1 use - (Bcmatch_Field_Reset => 0, + for INTENSET_BCMATCH_Field_1 use + (Intenset_Bcmatch_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on READY event. - READY : READY_Field_1 := Ready_Field_Reset; + READY : INTENSET_READY_Field_1 := Intenset_Ready_Field_Reset; -- Enable interrupt on ADDRESS event. - ADDRESS : ADDRESS_Field_1 := Address_Field_Reset; + ADDRESS : INTENSET_ADDRESS_Field_1 := + Intenset_Address_Field_Reset; -- Enable interrupt on PAYLOAD event. - PAYLOAD : PAYLOAD_Field_1 := Payload_Field_Reset; + PAYLOAD : INTENSET_PAYLOAD_Field_1 := + Intenset_Payload_Field_Reset; -- Enable interrupt on END event. - END_k : END_Field_1 := End_Field_Reset; + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; -- Enable interrupt on DISABLED event. - DISABLED : DISABLED_Field_1 := Disabled_Field_Reset; + DISABLED : INTENSET_DISABLED_Field_1 := + Intenset_Disabled_Field_Reset; -- Enable interrupt on DEVMATCH event. - DEVMATCH : DEVMATCH_Field_1 := Devmatch_Field_Reset; + DEVMATCH : INTENSET_DEVMATCH_Field_1 := + Intenset_Devmatch_Field_Reset; -- Enable interrupt on DEVMISS event. - DEVMISS : DEVMISS_Field_1 := Devmiss_Field_Reset; + DEVMISS : INTENSET_DEVMISS_Field_1 := + Intenset_Devmiss_Field_Reset; -- Enable interrupt on RSSIEND event. - RSSIEND : RSSIEND_Field_1 := Rssiend_Field_Reset; + RSSIEND : INTENSET_RSSIEND_Field_1 := + Intenset_Rssiend_Field_Reset; -- unspecified Reserved_8_9 : nrf51.UInt2 := 16#0#; -- Enable interrupt on BCMATCH event. - BCMATCH : BCMATCH_Field_1 := Bcmatch_Field_Reset; + BCMATCH : INTENSET_BCMATCH_Field_1 := + Intenset_Bcmatch_Field_Reset; -- unspecified Reserved_11_31 : nrf51.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -413,144 +420,237 @@ package nrf51.RADIO is Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on READY event. + type INTENCLR_READY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_READY_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on READY event. - type READY_Field_2 is - ( - -- Reset value for the field - Ready_Field_Reset, + type INTENCLR_READY_Field_1 is + (-- Reset value for the field + Intenclr_Ready_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for READY_Field_2 use - (Ready_Field_Reset => 0, + for INTENCLR_READY_Field_1 use + (Intenclr_Ready_Field_Reset => 0, Clear => 1); -- Disable interrupt on ADDRESS event. - type ADDRESS_Field_2 is - ( - -- Reset value for the field - Address_Field_Reset, + type INTENCLR_ADDRESS_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ADDRESS_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ADDRESS event. + type INTENCLR_ADDRESS_Field_1 is + (-- Reset value for the field + Intenclr_Address_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ADDRESS_Field_2 use - (Address_Field_Reset => 0, + for INTENCLR_ADDRESS_Field_1 use + (Intenclr_Address_Field_Reset => 0, Clear => 1); -- Disable interrupt on PAYLOAD event. - type PAYLOAD_Field_2 is - ( - -- Reset value for the field - Payload_Field_Reset, + type INTENCLR_PAYLOAD_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_PAYLOAD_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on PAYLOAD event. + type INTENCLR_PAYLOAD_Field_1 is + (-- Reset value for the field + Intenclr_Payload_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for PAYLOAD_Field_2 use - (Payload_Field_Reset => 0, + for INTENCLR_PAYLOAD_Field_1 use + (Intenclr_Payload_Field_Reset => 0, Clear => 1); -- Disable interrupt on END event. - type END_Field_2 is - ( - -- Reset value for the field - End_Field_Reset, + type INTENCLR_END_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on END event. + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for END_Field_2 use - (End_Field_Reset => 0, + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, Clear => 1); -- Disable interrupt on DISABLED event. - type DISABLED_Field_2 is - ( - -- Reset value for the field - Disabled_Field_Reset, + type INTENCLR_DISABLED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_DISABLED_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on DISABLED event. + type INTENCLR_DISABLED_Field_1 is + (-- Reset value for the field + Intenclr_Disabled_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for DISABLED_Field_2 use - (Disabled_Field_Reset => 0, + for INTENCLR_DISABLED_Field_1 use + (Intenclr_Disabled_Field_Reset => 0, Clear => 1); -- Disable interrupt on DEVMATCH event. - type DEVMATCH_Field_2 is - ( - -- Reset value for the field - Devmatch_Field_Reset, + type INTENCLR_DEVMATCH_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_DEVMATCH_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on DEVMATCH event. + type INTENCLR_DEVMATCH_Field_1 is + (-- Reset value for the field + Intenclr_Devmatch_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for DEVMATCH_Field_2 use - (Devmatch_Field_Reset => 0, + for INTENCLR_DEVMATCH_Field_1 use + (Intenclr_Devmatch_Field_Reset => 0, Clear => 1); -- Disable interrupt on DEVMISS event. - type DEVMISS_Field_2 is - ( - -- Reset value for the field - Devmiss_Field_Reset, + type INTENCLR_DEVMISS_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_DEVMISS_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on DEVMISS event. + type INTENCLR_DEVMISS_Field_1 is + (-- Reset value for the field + Intenclr_Devmiss_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for DEVMISS_Field_2 use - (Devmiss_Field_Reset => 0, + for INTENCLR_DEVMISS_Field_1 use + (Intenclr_Devmiss_Field_Reset => 0, Clear => 1); -- Disable interrupt on RSSIEND event. - type RSSIEND_Field_2 is - ( - -- Reset value for the field - Rssiend_Field_Reset, + type INTENCLR_RSSIEND_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_RSSIEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on RSSIEND event. + type INTENCLR_RSSIEND_Field_1 is + (-- Reset value for the field + Intenclr_Rssiend_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for RSSIEND_Field_2 use - (Rssiend_Field_Reset => 0, + for INTENCLR_RSSIEND_Field_1 use + (Intenclr_Rssiend_Field_Reset => 0, Clear => 1); -- Disable interrupt on BCMATCH event. - type BCMATCH_Field_2 is - ( - -- Reset value for the field - Bcmatch_Field_Reset, + type INTENCLR_BCMATCH_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_BCMATCH_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on BCMATCH event. + type INTENCLR_BCMATCH_Field_1 is + (-- Reset value for the field + Intenclr_Bcmatch_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for BCMATCH_Field_2 use - (Bcmatch_Field_Reset => 0, + for INTENCLR_BCMATCH_Field_1 use + (Intenclr_Bcmatch_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on READY event. - READY : READY_Field_2 := Ready_Field_Reset; + READY : INTENCLR_READY_Field_1 := Intenclr_Ready_Field_Reset; -- Disable interrupt on ADDRESS event. - ADDRESS : ADDRESS_Field_2 := Address_Field_Reset; + ADDRESS : INTENCLR_ADDRESS_Field_1 := + Intenclr_Address_Field_Reset; -- Disable interrupt on PAYLOAD event. - PAYLOAD : PAYLOAD_Field_2 := Payload_Field_Reset; + PAYLOAD : INTENCLR_PAYLOAD_Field_1 := + Intenclr_Payload_Field_Reset; -- Disable interrupt on END event. - END_k : END_Field_2 := End_Field_Reset; + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; -- Disable interrupt on DISABLED event. - DISABLED : DISABLED_Field_2 := Disabled_Field_Reset; + DISABLED : INTENCLR_DISABLED_Field_1 := + Intenclr_Disabled_Field_Reset; -- Disable interrupt on DEVMATCH event. - DEVMATCH : DEVMATCH_Field_2 := Devmatch_Field_Reset; + DEVMATCH : INTENCLR_DEVMATCH_Field_1 := + Intenclr_Devmatch_Field_Reset; -- Disable interrupt on DEVMISS event. - DEVMISS : DEVMISS_Field_2 := Devmiss_Field_Reset; + DEVMISS : INTENCLR_DEVMISS_Field_1 := + Intenclr_Devmiss_Field_Reset; -- Disable interrupt on RSSIEND event. - RSSIEND : RSSIEND_Field_2 := Rssiend_Field_Reset; + RSSIEND : INTENCLR_RSSIEND_Field_1 := + Intenclr_Rssiend_Field_Reset; -- unspecified Reserved_8_9 : nrf51.UInt2 := 16#0#; -- Disable interrupt on BCMATCH event. - BCMATCH : BCMATCH_Field_2 := Bcmatch_Field_Reset; + BCMATCH : INTENCLR_BCMATCH_Field_1 := + Intenclr_Bcmatch_Field_Reset; -- unspecified Reserved_11_31 : nrf51.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -567,30 +667,25 @@ package nrf51.RADIO is Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------------ - -- CRCSTATUS_Register -- - ------------------------ - -- CRC status of received packet. - type CRCSTATUS_Field is - ( - -- Packet received with CRC error. + type CRCSTATUS_CRCSTATUS_Field is + (-- Packet received with CRC error. Crcerror, -- Packet received with CRC ok. Crcok) with Size => 1; - for CRCSTATUS_Field use + for CRCSTATUS_CRCSTATUS_Field use (Crcerror => 0, Crcok => 1); -- CRC status of received packet. type CRCSTATUS_Register is record -- Read-only. CRC status of received packet. - CRCSTATUS : CRCSTATUS_Field; + CRCSTATUS : CRCSTATUS_CRCSTATUS_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCSTATUS_Register use record @@ -598,10 +693,6 @@ package nrf51.RADIO is Reserved_1_31 at 0 range 1 .. 31; end record; - ---------------------- - -- RXMATCH_Register -- - ---------------------- - subtype RXMATCH_RXMATCH_Field is nrf51.UInt3; -- Received address. @@ -611,7 +702,7 @@ package nrf51.RADIO is -- unspecified Reserved_3_31 : nrf51.UInt29; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXMATCH_Register use record @@ -619,10 +710,6 @@ package nrf51.RADIO is Reserved_3_31 at 0 range 3 .. 31; end record; - -------------------- - -- RXCRC_Register -- - -------------------- - subtype RXCRC_RXCRC_Field is nrf51.UInt24; -- Received CRC. @@ -632,7 +719,7 @@ package nrf51.RADIO is -- unspecified Reserved_24_31 : nrf51.Byte; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXCRC_Register use record @@ -640,10 +727,6 @@ package nrf51.RADIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- DAI_Register -- - ------------------ - subtype DAI_DAI_Field is nrf51.UInt3; -- Device address match index. @@ -654,7 +737,7 @@ package nrf51.RADIO is -- unspecified Reserved_3_31 : nrf51.UInt29; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DAI_Register use record @@ -662,10 +745,6 @@ package nrf51.RADIO is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------------ - -- FREQUENCY_Register -- - ------------------------ - subtype FREQUENCY_FREQUENCY_Field is nrf51.UInt7; -- Frequency. @@ -676,7 +755,7 @@ package nrf51.RADIO is -- unspecified Reserved_7_31 : nrf51.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for FREQUENCY_Register use record @@ -684,15 +763,10 @@ package nrf51.RADIO is Reserved_7_31 at 0 range 7 .. 31; end record; - ---------------------- - -- TXPOWER_Register -- - ---------------------- - -- Radio output power. Decision point: TXEN task. - type TXPOWER_Field is - ( - -- 0dBm. - TXPOWER_Field_0DBm, + type TXPOWER_TXPOWER_Field is + (-- 0dBm. + Val_0DBm, -- +4dBm. Pos4DBm, -- -30dBm. @@ -708,8 +782,8 @@ package nrf51.RADIO is -- -4dBm. Neg4DBm) with Size => 8; - for TXPOWER_Field use - (TXPOWER_Field_0DBm => 0, + for TXPOWER_TXPOWER_Field use + (Val_0DBm => 0, Pos4DBm => 4, Neg30DBm => 216, Neg20DBm => 236, @@ -721,11 +795,11 @@ package nrf51.RADIO is -- Output power. type TXPOWER_Register is record -- Radio output power. Decision point: TXEN task. - TXPOWER : TXPOWER_Field := TXPOWER_Field_0DBm; + TXPOWER : TXPOWER_TXPOWER_Field := nrf51.RADIO.Val_0DBm; -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXPOWER_Register use record @@ -733,15 +807,10 @@ package nrf51.RADIO is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- MODE_Register -- - ------------------- - -- Radio data rate and modulation setting. Decision point: TXEN or RXEN -- task. - type MODE_Field is - ( - -- 1Mbit/s Nordic propietary radio mode. + type MODE_MODE_Field is + (-- 1Mbit/s Nordic propietary radio mode. Nrf_1Mbit, -- 2Mbit/s Nordic propietary radio mode. Nrf_2Mbit, @@ -750,7 +819,7 @@ package nrf51.RADIO is -- 1Mbit/s Bluetooth Low Energy Ble_1Mbit) with Size => 2; - for MODE_Field use + for MODE_MODE_Field use (Nrf_1Mbit => 0, Nrf_2Mbit => 1, Nrf_250Kbit => 2, @@ -760,11 +829,11 @@ package nrf51.RADIO is type MODE_Register is record -- Radio data rate and modulation setting. Decision point: TXEN or RXEN -- task. - MODE : MODE_Field := Nrf_1Mbit; + MODE : MODE_MODE_Field := nrf51.RADIO.Nrf_1Mbit; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MODE_Register use record @@ -772,10 +841,6 @@ package nrf51.RADIO is Reserved_2_31 at 0 range 2 .. 31; end record; - -------------------- - -- PCNF0_Register -- - -------------------- - subtype PCNF0_LFLEN_Field is nrf51.UInt4; subtype PCNF0_S0LEN_Field is nrf51.Bit; subtype PCNF0_S1LEN_Field is nrf51.UInt4; @@ -795,7 +860,7 @@ package nrf51.RADIO is -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PCNF0_Register use record @@ -807,35 +872,29 @@ package nrf51.RADIO is Reserved_20_31 at 0 range 20 .. 31; end record; - -------------------- - -- PCNF1_Register -- - -------------------- - subtype PCNF1_MAXLEN_Field is nrf51.Byte; subtype PCNF1_STATLEN_Field is nrf51.Byte; subtype PCNF1_BALEN_Field is nrf51.UInt3; -- On air endianness of packet length field. Decision point: START task. - type ENDIAN_Field is - ( - -- Least significant bit on air first + type PCNF1_ENDIAN_Field is + (-- Least significant bit on air first Little, -- Most significant bit on air first Big) with Size => 1; - for ENDIAN_Field use + for PCNF1_ENDIAN_Field use (Little => 0, Big => 1); -- Packet whitening enable. - type WHITEEN_Field is - ( - -- Whitening disabled. + type PCNF1_WHITEEN_Field is + (-- Whitening disabled. Disabled, -- Whitening enabled. Enabled) with Size => 1; - for WHITEEN_Field use + for PCNF1_WHITEEN_Field use (Disabled => 0, Enabled => 1); @@ -850,13 +909,13 @@ package nrf51.RADIO is -- unspecified Reserved_19_23 : nrf51.UInt5 := 16#0#; -- On air endianness of packet length field. Decision point: START task. - ENDIAN : ENDIAN_Field := Little; + ENDIAN : PCNF1_ENDIAN_Field := nrf51.RADIO.Little; -- Packet whitening enable. - WHITEEN : WHITEEN_Field := Disabled; + WHITEEN : PCNF1_WHITEEN_Field := nrf51.RADIO.Disabled; -- unspecified Reserved_26_31 : nrf51.UInt6 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PCNF1_Register use record @@ -869,10 +928,6 @@ package nrf51.RADIO is Reserved_26_31 at 0 range 26 .. 31; end record; - ---------------------- - -- PREFIX0_Register -- - ---------------------- - -- PREFIX0_AP array element subtype PREFIX0_AP_Element is nrf51.Byte; @@ -887,13 +942,13 @@ package nrf51.RADIO is case As_Array is when False => -- AP as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- AP as an array Arr : PREFIX0_AP_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PREFIX0_Register use record @@ -901,10 +956,6 @@ package nrf51.RADIO is Arr at 0 range 0 .. 31; end record; - ---------------------- - -- PREFIX1_Register -- - ---------------------- - -- PREFIX1_AP array element subtype PREFIX1_AP_Element is nrf51.Byte; @@ -919,13 +970,13 @@ package nrf51.RADIO is case As_Array is when False => -- AP as a value - Val : nrf51.Word; + Val : nrf51.UInt32; when True => -- AP as an array Arr : PREFIX1_AP_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PREFIX1_Register use record @@ -933,10 +984,6 @@ package nrf51.RADIO is Arr at 0 range 0 .. 31; end record; - ------------------------ - -- TXADDRESS_Register -- - ------------------------ - subtype TXADDRESS_TXADDRESS_Field is nrf51.UInt3; -- Transmit address select. @@ -947,7 +994,7 @@ package nrf51.RADIO is -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXADDRESS_Register use record @@ -955,28 +1002,20 @@ package nrf51.RADIO is Reserved_3_31 at 0 range 3 .. 31; end record; - -------------------------- - -- RXADDRESSES_Register -- - -------------------------- - -- Enable reception on logical address 0. Decision point: START task. - type ADDR0_Field is - ( - -- Reception disabled. + type RXADDRESSES_ADDR0_Field is + (-- Reception disabled. Disabled, -- Reception enabled. Enabled) with Size => 1; - for ADDR0_Field use + for RXADDRESSES_ADDR0_Field use (Disabled => 0, Enabled => 1); - ---------------------- - -- RXADDRESSES.ADDR -- - ---------------------- - -- RXADDRESSES_ADDR array - type RXADDRESSES_ADDR_Field_Array is array (0 .. 7) of ADDR0_Field + type RXADDRESSES_ADDR_Field_Array is array (0 .. 7) + of RXADDRESSES_ADDR0_Field with Component_Size => 1, Size => 8; -- Type definition for RXADDRESSES_ADDR @@ -1007,7 +1046,7 @@ package nrf51.RADIO is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXADDRESSES_Register use record @@ -1015,14 +1054,9 @@ package nrf51.RADIO is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- CRCCNF_Register -- - --------------------- - -- CRC length. Decision point: START task. - type LEN_Field is - ( - -- CRC calculation disabled. + type CRCCNF_LEN_Field is + (-- CRC calculation disabled. Disabled, -- One byte long CRC. One, @@ -1031,7 +1065,7 @@ package nrf51.RADIO is -- Three bytes long CRC. Three) with Size => 2; - for LEN_Field use + for CRCCNF_LEN_Field use (Disabled => 0, One => 1, Two => 2, @@ -1039,31 +1073,30 @@ package nrf51.RADIO is -- Leave packet address field out of the CRC calculation. Decision point: -- START task. - type SKIPADDR_Field is - ( - -- Include packet address in CRC calculation. + type CRCCNF_SKIPADDR_Field is + (-- Include packet address in CRC calculation. Include, - -- Packet address is skipped in CRC calculation. The CRC calculation - -- will start at the first byte after the address. + -- Packet address is skipped in CRC calculation. The CRC calculation will +-- start at the first byte after the address. Skip) with Size => 1; - for SKIPADDR_Field use + for CRCCNF_SKIPADDR_Field use (Include => 0, Skip => 1); -- CRC configuration. type CRCCNF_Register is record -- CRC length. Decision point: START task. - LEN : LEN_Field := Disabled; + LEN : CRCCNF_LEN_Field := nrf51.RADIO.Disabled; -- unspecified Reserved_2_7 : nrf51.UInt6 := 16#0#; -- Leave packet address field out of the CRC calculation. Decision -- point: START task. - SKIPADDR : SKIPADDR_Field := Include; + SKIPADDR : CRCCNF_SKIPADDR_Field := nrf51.RADIO.Include; -- unspecified Reserved_9_31 : nrf51.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCCNF_Register use record @@ -1073,10 +1106,6 @@ package nrf51.RADIO is Reserved_9_31 at 0 range 9 .. 31; end record; - ---------------------- - -- CRCPOLY_Register -- - ---------------------- - subtype CRCPOLY_CRCPOLY_Field is nrf51.UInt24; -- CRC polynomial. @@ -1086,7 +1115,7 @@ package nrf51.RADIO is -- unspecified Reserved_24_31 : nrf51.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCPOLY_Register use record @@ -1094,10 +1123,6 @@ package nrf51.RADIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------- - -- CRCINIT_Register -- - ---------------------- - subtype CRCINIT_CRCINIT_Field is nrf51.UInt24; -- CRC initial value. @@ -1107,7 +1132,7 @@ package nrf51.RADIO is -- unspecified Reserved_24_31 : nrf51.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCINIT_Register use record @@ -1115,44 +1140,38 @@ package nrf51.RADIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- TEST_Register -- - ------------------- - -- Constant carrier. Decision point: TXEN task. - type CONSTCARRIER_Field is - ( - -- Constant carrier disabled. + type TEST_CONSTCARRIER_Field is + (-- Constant carrier disabled. Disabled, -- Constant carrier enabled. Enabled) with Size => 1; - for CONSTCARRIER_Field use + for TEST_CONSTCARRIER_Field use (Disabled => 0, Enabled => 1); -- PLL lock. Decision point: TXEN or RXEN task. - type PLLLOCK_Field is - ( - -- PLL lock disabled. + type TEST_PLLLOCK_Field is + (-- PLL lock disabled. Disabled, -- PLL lock enabled. Enabled) with Size => 1; - for PLLLOCK_Field use + for TEST_PLLLOCK_Field use (Disabled => 0, Enabled => 1); -- Test features enable register. type TEST_Register is record -- Constant carrier. Decision point: TXEN task. - CONSTCARRIER : CONSTCARRIER_Field := Disabled; + CONSTCARRIER : TEST_CONSTCARRIER_Field := nrf51.RADIO.Disabled; -- PLL lock. Decision point: TXEN or RXEN task. - PLLLOCK : PLLLOCK_Field := Disabled; + PLLLOCK : TEST_PLLLOCK_Field := nrf51.RADIO.Disabled; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TEST_Register use record @@ -1161,10 +1180,6 @@ package nrf51.RADIO is Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- TIFS_Register -- - ------------------- - subtype TIFS_TIFS_Field is nrf51.Byte; -- Inter Frame Spacing in microseconds. @@ -1174,7 +1189,7 @@ package nrf51.RADIO is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TIFS_Register use record @@ -1182,10 +1197,6 @@ package nrf51.RADIO is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------------- - -- RSSISAMPLE_Register -- - ------------------------- - subtype RSSISAMPLE_RSSISAMPLE_Field is nrf51.UInt7; -- RSSI sample. @@ -1196,7 +1207,7 @@ package nrf51.RADIO is -- unspecified Reserved_7_31 : nrf51.UInt25; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RSSISAMPLE_Register use record @@ -1204,14 +1215,9 @@ package nrf51.RADIO is Reserved_7_31 at 0 range 7 .. 31; end record; - -------------------- - -- STATE_Register -- - -------------------- - -- Current radio state. - type STATE_Field is - ( - -- Radio is in the Disabled state. + type STATE_STATE_Field is + (-- Radio is in the Disabled state. Disabled, -- Radio is in the Rx Ramp Up state. Rxru, @@ -1230,7 +1236,7 @@ package nrf51.RADIO is -- Radio is in the Tx Disable state. Txdisable) with Size => 4; - for STATE_Field use + for STATE_STATE_Field use (Disabled => 0, Rxru => 1, Rxidle => 2, @@ -1244,11 +1250,11 @@ package nrf51.RADIO is -- Current radio state. type STATE_Register is record -- Read-only. Current radio state. - STATE : STATE_Field; + STATE : STATE_STATE_Field; -- unspecified Reserved_4_31 : nrf51.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for STATE_Register use record @@ -1256,10 +1262,6 @@ package nrf51.RADIO is Reserved_4_31 at 0 range 4 .. 31; end record; - -------------------------- - -- DATAWHITEIV_Register -- - -------------------------- - subtype DATAWHITEIV_DATAWHITEIV_Field is nrf51.UInt7; -- Data whitening initial value. @@ -1270,7 +1272,7 @@ package nrf51.RADIO is -- unspecified Reserved_7_31 : nrf51.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DATAWHITEIV_Register use record @@ -1281,22 +1283,18 @@ package nrf51.RADIO is -- Device address base segment. -- Device address base segment. - type DAB_Registers is array (0 .. 7) of nrf51.Word; - - ------------------ - -- DAP_Register -- - ------------------ + type DAB_Registers is array (0 .. 7) of nrf51.UInt32; - subtype DAP_DAP_Field is nrf51.Short; + subtype DAP_DAP_Field is nrf51.UInt16; -- Device address prefix. type DAP_Register is record -- Device address prefix. DAP : DAP_DAP_Field := 16#0#; -- unspecified - Reserved_16_31 : nrf51.Short := 16#0#; + Reserved_16_31 : nrf51.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DAP_Register use record @@ -1307,28 +1305,19 @@ package nrf51.RADIO is -- Device address prefix. type DAP_Registers is array (0 .. 7) of DAP_Register; - -------------------- - -- DACNF_Register -- - -------------------- - -- Enable or disable device address matching using device address 0. - type ENA0_Field is - ( - -- Disabled. + type DACNF_ENA0_Field is + (-- Disabled. Disabled, -- Enabled. Enabled) with Size => 1; - for ENA0_Field use + for DACNF_ENA0_Field use (Disabled => 0, Enabled => 1); - --------------- - -- DACNF.ENA -- - --------------- - -- DACNF_ENA array - type DACNF_ENA_Field_Array is array (0 .. 7) of ENA0_Field + type DACNF_ENA_Field_Array is array (0 .. 7) of DACNF_ENA0_Field with Component_Size => 1, Size => 8; -- Type definition for DACNF_ENA @@ -1351,10 +1340,6 @@ package nrf51.RADIO is Arr at 0 range 0 .. 7; end record; - ----------------- - -- DACNF.TXADD -- - ----------------- - -- DACNF_TXADD array element subtype DACNF_TXADD_Element is nrf51.Bit; @@ -1389,9 +1374,9 @@ package nrf51.RADIO is -- TxAdd for device address 0. TXADD : DACNF_TXADD_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : nrf51.Short := 16#0#; + Reserved_16_31 : nrf51.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DACNF_Register use record @@ -1400,21 +1385,16 @@ package nrf51.RADIO is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------------ - -- OVERRIDE4_Register -- - ------------------------ - subtype OVERRIDE4_OVERRIDE4_Field is nrf51.UInt28; -- Enable or disable override of default trim values. - type ENABLE_Field is - ( - -- Override trim values disabled. + type OVERRIDE4_ENABLE_Field is + (-- Override trim values disabled. Disabled, -- Override trim values enabled. Enabled) with Size => 1; - for ENABLE_Field use + for OVERRIDE4_ENABLE_Field use (Disabled => 0, Enabled => 1); @@ -1425,9 +1405,9 @@ package nrf51.RADIO is -- unspecified Reserved_28_30 : nrf51.UInt3 := 16#0#; -- Enable or disable override of default trim values. - ENABLE : ENABLE_Field := Disabled; + ENABLE : OVERRIDE4_ENABLE_Field := nrf51.RADIO.Disabled; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OVERRIDE4_Register use record @@ -1436,30 +1416,25 @@ package nrf51.RADIO is ENABLE at 0 range 31 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.RADIO.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -1474,175 +1449,175 @@ package nrf51.RADIO is -- The radio. type RADIO_Peripheral is record -- Enable radio in TX mode. - TASKS_TXEN : nrf51.Word; + TASKS_TXEN : aliased nrf51.UInt32; -- Enable radio in RX mode. - TASKS_RXEN : nrf51.Word; + TASKS_RXEN : aliased nrf51.UInt32; -- Start radio. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop radio. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Disable radio. - TASKS_DISABLE : nrf51.Word; + TASKS_DISABLE : aliased nrf51.UInt32; -- Start the RSSI and take one sample of the receive signal strength. - TASKS_RSSISTART : nrf51.Word; + TASKS_RSSISTART : aliased nrf51.UInt32; -- Stop the RSSI measurement. - TASKS_RSSISTOP : nrf51.Word; + TASKS_RSSISTOP : aliased nrf51.UInt32; -- Start the bit counter. - TASKS_BCSTART : nrf51.Word; + TASKS_BCSTART : aliased nrf51.UInt32; -- Stop the bit counter. - TASKS_BCSTOP : nrf51.Word; + TASKS_BCSTOP : aliased nrf51.UInt32; -- Ready event. - EVENTS_READY : nrf51.Word; + EVENTS_READY : aliased nrf51.UInt32; -- Address event. - EVENTS_ADDRESS : nrf51.Word; + EVENTS_ADDRESS : aliased nrf51.UInt32; -- Payload event. - EVENTS_PAYLOAD : nrf51.Word; + EVENTS_PAYLOAD : aliased nrf51.UInt32; -- End event. - EVENTS_END : nrf51.Word; + EVENTS_END : aliased nrf51.UInt32; -- Disable event. - EVENTS_DISABLED : nrf51.Word; + EVENTS_DISABLED : aliased nrf51.UInt32; -- A device address match occurred on the last received packet. - EVENTS_DEVMATCH : nrf51.Word; + EVENTS_DEVMATCH : aliased nrf51.UInt32; -- No device address match occurred on the last received packet. - EVENTS_DEVMISS : nrf51.Word; + EVENTS_DEVMISS : aliased nrf51.UInt32; -- Sampling of the receive signal strength complete. A new RSSI sample -- is ready for readout at the RSSISAMPLE register. - EVENTS_RSSIEND : nrf51.Word; + EVENTS_RSSIEND : aliased nrf51.UInt32; -- Bit counter reached bit count value specified in BCC register. - EVENTS_BCMATCH : nrf51.Word; + EVENTS_BCMATCH : aliased nrf51.UInt32; -- Shortcuts for the radio. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- CRC status of received packet. - CRCSTATUS : CRCSTATUS_Register; + CRCSTATUS : aliased CRCSTATUS_Register; -- Received address. - RXMATCH : RXMATCH_Register; + RXMATCH : aliased RXMATCH_Register; -- Received CRC. - RXCRC : RXCRC_Register; + RXCRC : aliased RXCRC_Register; -- Device address match index. - DAI : DAI_Register; + DAI : aliased DAI_Register; -- Packet pointer. Decision point: START task. - PACKETPTR : nrf51.Word; + PACKETPTR : aliased nrf51.UInt32; -- Frequency. - FREQUENCY : FREQUENCY_Register; + FREQUENCY : aliased FREQUENCY_Register; -- Output power. - TXPOWER : TXPOWER_Register; + TXPOWER : aliased TXPOWER_Register; -- Data rate and modulation. - MODE : MODE_Register; + MODE : aliased MODE_Register; -- Packet configuration 0. - PCNF0 : PCNF0_Register; + PCNF0 : aliased PCNF0_Register; -- Packet configuration 1. - PCNF1 : PCNF1_Register; + PCNF1 : aliased PCNF1_Register; -- Radio base address 0. Decision point: START task. - BASE0 : nrf51.Word; + BASE0 : aliased nrf51.UInt32; -- Radio base address 1. Decision point: START task. - BASE1 : nrf51.Word; + BASE1 : aliased nrf51.UInt32; -- Prefixes bytes for logical addresses 0 to 3. - PREFIX0 : PREFIX0_Register; + PREFIX0 : aliased PREFIX0_Register; -- Prefixes bytes for logical addresses 4 to 7. - PREFIX1 : PREFIX1_Register; + PREFIX1 : aliased PREFIX1_Register; -- Transmit address select. - TXADDRESS : TXADDRESS_Register; + TXADDRESS : aliased TXADDRESS_Register; -- Receive address select. - RXADDRESSES : RXADDRESSES_Register; + RXADDRESSES : aliased RXADDRESSES_Register; -- CRC configuration. - CRCCNF : CRCCNF_Register; + CRCCNF : aliased CRCCNF_Register; -- CRC polynomial. - CRCPOLY : CRCPOLY_Register; + CRCPOLY : aliased CRCPOLY_Register; -- CRC initial value. - CRCINIT : CRCINIT_Register; + CRCINIT : aliased CRCINIT_Register; -- Test features enable register. - TEST : TEST_Register; + TEST : aliased TEST_Register; -- Inter Frame Spacing in microseconds. - TIFS : TIFS_Register; + TIFS : aliased TIFS_Register; -- RSSI sample. - RSSISAMPLE : RSSISAMPLE_Register; + RSSISAMPLE : aliased RSSISAMPLE_Register; -- Current radio state. - STATE : STATE_Register; + STATE : aliased STATE_Register; -- Data whitening initial value. - DATAWHITEIV : DATAWHITEIV_Register; + DATAWHITEIV : aliased DATAWHITEIV_Register; -- Bit counter compare. - BCC : nrf51.Word; + BCC : aliased nrf51.UInt32; -- Device address base segment. - DAB : DAB_Registers; + DAB : aliased DAB_Registers; -- Device address prefix. - DAP : DAP_Registers; + DAP : aliased DAP_Registers; -- Device address match configuration. - DACNF : DACNF_Register; + DACNF : aliased DACNF_Register; -- Trim value override register 0. - OVERRIDE0 : nrf51.Word; + OVERRIDE0 : aliased nrf51.UInt32; -- Trim value override register 1. - OVERRIDE1 : nrf51.Word; + OVERRIDE1 : aliased nrf51.UInt32; -- Trim value override register 2. - OVERRIDE2 : nrf51.Word; + OVERRIDE2 : aliased nrf51.UInt32; -- Trim value override register 3. - OVERRIDE3 : nrf51.Word; + OVERRIDE3 : aliased nrf51.UInt32; -- Trim value override register 4. - OVERRIDE4 : OVERRIDE4_Register; + OVERRIDE4 : aliased OVERRIDE4_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for RADIO_Peripheral use record - TASKS_TXEN at 0 range 0 .. 31; - TASKS_RXEN at 4 range 0 .. 31; - TASKS_START at 8 range 0 .. 31; - TASKS_STOP at 12 range 0 .. 31; - TASKS_DISABLE at 16 range 0 .. 31; - TASKS_RSSISTART at 20 range 0 .. 31; - TASKS_RSSISTOP at 24 range 0 .. 31; - TASKS_BCSTART at 28 range 0 .. 31; - TASKS_BCSTOP at 32 range 0 .. 31; - EVENTS_READY at 256 range 0 .. 31; - EVENTS_ADDRESS at 260 range 0 .. 31; - EVENTS_PAYLOAD at 264 range 0 .. 31; - EVENTS_END at 268 range 0 .. 31; - EVENTS_DISABLED at 272 range 0 .. 31; - EVENTS_DEVMATCH at 276 range 0 .. 31; - EVENTS_DEVMISS at 280 range 0 .. 31; - EVENTS_RSSIEND at 284 range 0 .. 31; - EVENTS_BCMATCH at 296 range 0 .. 31; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - CRCSTATUS at 1024 range 0 .. 31; - RXMATCH at 1032 range 0 .. 31; - RXCRC at 1036 range 0 .. 31; - DAI at 1040 range 0 .. 31; - PACKETPTR at 1284 range 0 .. 31; - FREQUENCY at 1288 range 0 .. 31; - TXPOWER at 1292 range 0 .. 31; - MODE at 1296 range 0 .. 31; - PCNF0 at 1300 range 0 .. 31; - PCNF1 at 1304 range 0 .. 31; - BASE0 at 1308 range 0 .. 31; - BASE1 at 1312 range 0 .. 31; - PREFIX0 at 1316 range 0 .. 31; - PREFIX1 at 1320 range 0 .. 31; - TXADDRESS at 1324 range 0 .. 31; - RXADDRESSES at 1328 range 0 .. 31; - CRCCNF at 1332 range 0 .. 31; - CRCPOLY at 1336 range 0 .. 31; - CRCINIT at 1340 range 0 .. 31; - TEST at 1344 range 0 .. 31; - TIFS at 1348 range 0 .. 31; - RSSISAMPLE at 1352 range 0 .. 31; - STATE at 1360 range 0 .. 31; - DATAWHITEIV at 1364 range 0 .. 31; - BCC at 1376 range 0 .. 31; - DAB at 1536 range 0 .. 255; - DAP at 1568 range 0 .. 255; - DACNF at 1600 range 0 .. 31; - OVERRIDE0 at 1828 range 0 .. 31; - OVERRIDE1 at 1832 range 0 .. 31; - OVERRIDE2 at 1836 range 0 .. 31; - OVERRIDE3 at 1840 range 0 .. 31; - OVERRIDE4 at 1844 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_TXEN at 16#0# range 0 .. 31; + TASKS_RXEN at 16#4# range 0 .. 31; + TASKS_START at 16#8# range 0 .. 31; + TASKS_STOP at 16#C# range 0 .. 31; + TASKS_DISABLE at 16#10# range 0 .. 31; + TASKS_RSSISTART at 16#14# range 0 .. 31; + TASKS_RSSISTOP at 16#18# range 0 .. 31; + TASKS_BCSTART at 16#1C# range 0 .. 31; + TASKS_BCSTOP at 16#20# range 0 .. 31; + EVENTS_READY at 16#100# range 0 .. 31; + EVENTS_ADDRESS at 16#104# range 0 .. 31; + EVENTS_PAYLOAD at 16#108# range 0 .. 31; + EVENTS_END at 16#10C# range 0 .. 31; + EVENTS_DISABLED at 16#110# range 0 .. 31; + EVENTS_DEVMATCH at 16#114# range 0 .. 31; + EVENTS_DEVMISS at 16#118# range 0 .. 31; + EVENTS_RSSIEND at 16#11C# range 0 .. 31; + EVENTS_BCMATCH at 16#128# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + CRCSTATUS at 16#400# range 0 .. 31; + RXMATCH at 16#408# range 0 .. 31; + RXCRC at 16#40C# range 0 .. 31; + DAI at 16#410# range 0 .. 31; + PACKETPTR at 16#504# range 0 .. 31; + FREQUENCY at 16#508# range 0 .. 31; + TXPOWER at 16#50C# range 0 .. 31; + MODE at 16#510# range 0 .. 31; + PCNF0 at 16#514# range 0 .. 31; + PCNF1 at 16#518# range 0 .. 31; + BASE0 at 16#51C# range 0 .. 31; + BASE1 at 16#520# range 0 .. 31; + PREFIX0 at 16#524# range 0 .. 31; + PREFIX1 at 16#528# range 0 .. 31; + TXADDRESS at 16#52C# range 0 .. 31; + RXADDRESSES at 16#530# range 0 .. 31; + CRCCNF at 16#534# range 0 .. 31; + CRCPOLY at 16#538# range 0 .. 31; + CRCINIT at 16#53C# range 0 .. 31; + TEST at 16#540# range 0 .. 31; + TIFS at 16#544# range 0 .. 31; + RSSISAMPLE at 16#548# range 0 .. 31; + STATE at 16#550# range 0 .. 31; + DATAWHITEIV at 16#554# range 0 .. 31; + BCC at 16#560# range 0 .. 31; + DAB at 16#600# range 0 .. 255; + DAP at 16#620# range 0 .. 255; + DACNF at 16#640# range 0 .. 31; + OVERRIDE0 at 16#724# range 0 .. 31; + OVERRIDE1 at 16#728# range 0 .. 31; + OVERRIDE2 at 16#72C# range 0 .. 31; + OVERRIDE3 at 16#730# range 0 .. 31; + OVERRIDE4 at 16#734# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- The radio. diff --git a/microbit/nrf51/nrf51-rng.ads b/microbit/nrf51/nrf51-rng.ads index 57b261e..6ebf858 100644 --- a/microbit/nrf51/nrf51-rng.ads +++ b/microbit/nrf51/nrf51-rng.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,30 +43,25 @@ package nrf51.RNG is -- Registers -- --------------- - --------------------- - -- SHORTS_Register -- - --------------------- - -- Shortcut between VALRDY event and STOP task. - type VALRDY_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_VALRDY_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for VALRDY_STOP_Field use + for SHORTS_VALRDY_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcuts for the RNG. type SHORTS_Register is record -- Shortcut between VALRDY event and STOP task. - VALRDY_STOP : VALRDY_STOP_Field := Disabled; + VALRDY_STOP : SHORTS_VALRDY_STOP_Field := nrf51.RNG.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -43,42 +69,36 @@ package nrf51.RNG is Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on VALRDY event. - type VALRDY_Field is - ( - -- Interrupt disabled. + type INTENSET_VALRDY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for VALRDY_Field use + for INTENSET_VALRDY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on VALRDY event. - type VALRDY_Field_1 is - ( - -- Reset value for the field - Valrdy_Field_Reset, + type INTENSET_VALRDY_Field_1 is + (-- Reset value for the field + Intenset_Valrdy_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for VALRDY_Field_1 use - (Valrdy_Field_Reset => 0, + for INTENSET_VALRDY_Field_1 use + (Intenset_Valrdy_Field_Reset => 0, Set => 1); -- Interrupt enable set register type INTENSET_Register is record -- Enable interrupt on VALRDY event. - VALRDY : VALRDY_Field_1 := Valrdy_Field_Reset; + VALRDY : INTENSET_VALRDY_Field_1 := Intenset_Valrdy_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -86,30 +106,36 @@ package nrf51.RNG is Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on VALRDY event. + type INTENCLR_VALRDY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_VALRDY_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on VALRDY event. - type VALRDY_Field_2 is - ( - -- Reset value for the field - Valrdy_Field_Reset, + type INTENCLR_VALRDY_Field_1 is + (-- Reset value for the field + Intenclr_Valrdy_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for VALRDY_Field_2 use - (Valrdy_Field_Reset => 0, + for INTENCLR_VALRDY_Field_1 use + (Intenclr_Valrdy_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register type INTENCLR_Register is record -- Disable interrupt on VALRDY event. - VALRDY : VALRDY_Field_2 := Valrdy_Field_Reset; + VALRDY : INTENCLR_VALRDY_Field_1 := Intenclr_Valrdy_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -117,30 +143,25 @@ package nrf51.RNG is Reserved_1_31 at 0 range 1 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- - -- Digital error correction enable. - type DERCEN_Field is - ( - -- Digital error correction disabled. + type CONFIG_DERCEN_Field is + (-- Digital error correction disabled. Disabled, -- Digital error correction enabled. Enabled) with Size => 1; - for DERCEN_Field use + for CONFIG_DERCEN_Field use (Disabled => 0, Enabled => 1); -- Configuration register. type CONFIG_Register is record -- Digital error correction enable. - DERCEN : DERCEN_Field := Disabled; + DERCEN : CONFIG_DERCEN_Field := nrf51.RNG.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -148,10 +169,6 @@ package nrf51.RNG is Reserved_1_31 at 0 range 1 .. 31; end record; - -------------------- - -- VALUE_Register -- - -------------------- - subtype VALUE_VALUE_Field is nrf51.Byte; -- RNG random number. @@ -161,7 +178,7 @@ package nrf51.RNG is -- unspecified Reserved_8_31 : nrf51.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for VALUE_Register use record @@ -169,30 +186,25 @@ package nrf51.RNG is Reserved_8_31 at 0 range 8 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.RNG.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -207,36 +219,36 @@ package nrf51.RNG is -- Random Number Generator. type RNG_Peripheral is record -- Start the random number generator. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop the random number generator. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- New random number generated and written to VALUE register. - EVENTS_VALRDY : nrf51.Word; + EVENTS_VALRDY : aliased nrf51.UInt32; -- Shortcuts for the RNG. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Configuration register. - CONFIG : CONFIG_Register; + CONFIG : aliased CONFIG_Register; -- RNG random number. - VALUE : VALUE_Register; + VALUE : aliased VALUE_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for RNG_Peripheral use record - TASKS_START at 0 range 0 .. 31; - TASKS_STOP at 4 range 0 .. 31; - EVENTS_VALRDY at 256 range 0 .. 31; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - CONFIG at 1284 range 0 .. 31; - VALUE at 1288 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + EVENTS_VALRDY at 16#100# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + CONFIG at 16#504# range 0 .. 31; + VALUE at 16#508# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- Random Number Generator. diff --git a/microbit/nrf51/nrf51-rtc.ads b/microbit/nrf51/nrf51-rtc.ads index 8d31e85..5e75125 100644 --- a/microbit/nrf51/nrf51-rtc.ads +++ b/microbit/nrf51/nrf51-rtc.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -15,90 +46,77 @@ package nrf51.RTC is -- Compare event on CC[n] match. -- Compare event on CC[n] match. - type EVENTS_COMPARE_Registers is array (0 .. 3) of nrf51.Word; - - ----------------------- - -- INTENSET_Register -- - ----------------------- + type EVENTS_COMPARE_Registers is array (0 .. 3) of nrf51.UInt32; -- Enable interrupt on TICK event. - type TICK_Field is - ( - -- Interrupt disabled. + type INTENSET_TICK_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for TICK_Field use + for INTENSET_TICK_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on TICK event. - type TICK_Field_1 is - ( - -- Reset value for the field - Tick_Field_Reset, + type INTENSET_TICK_Field_1 is + (-- Reset value for the field + Intenset_Tick_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for TICK_Field_1 use - (Tick_Field_Reset => 0, + for INTENSET_TICK_Field_1 use + (Intenset_Tick_Field_Reset => 0, Set => 1); -- Enable interrupt on OVRFLW event. - type OVRFLW_Field is - ( - -- Interrupt disabled. + type INTENSET_OVRFLW_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for OVRFLW_Field use + for INTENSET_OVRFLW_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on OVRFLW event. - type OVRFLW_Field_1 is - ( - -- Reset value for the field - Ovrflw_Field_Reset, + type INTENSET_OVRFLW_Field_1 is + (-- Reset value for the field + Intenset_Ovrflw_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for OVRFLW_Field_1 use - (Ovrflw_Field_Reset => 0, + for INTENSET_OVRFLW_Field_1 use + (Intenset_Ovrflw_Field_Reset => 0, Set => 1); -- Enable interrupt on COMPARE[0] event. - type COMPARE0_Field is - ( - -- Interrupt disabled. + type INTENSET_COMPARE0_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for COMPARE0_Field use + for INTENSET_COMPARE0_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on COMPARE[0] event. - type COMPARE0_Field_1 is - ( - -- Reset value for the field - Compare0_Field_Reset, + type INTENSET_COMPARE0_Field_1 is + (-- Reset value for the field + Intenset_Compare0_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for COMPARE0_Field_1 use - (Compare0_Field_Reset => 0, + for INTENSET_COMPARE0_Field_1 use + (Intenset_Compare0_Field_Reset => 0, Set => 1); - ---------------------- - -- INTENSET.COMPARE -- - ---------------------- - -- INTENSET_COMPARE array - type INTENSET_COMPARE_Field_Array is array (0 .. 3) of COMPARE0_Field_1 + type INTENSET_COMPARE_Field_Array is array (0 .. 3) + of INTENSET_COMPARE0_Field_1 with Component_Size => 1, Size => 4; -- Type definition for INTENSET_COMPARE @@ -124,9 +142,9 @@ package nrf51.RTC is -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on TICK event. - TICK : TICK_Field_1 := Tick_Field_Reset; + TICK : INTENSET_TICK_Field_1 := Intenset_Tick_Field_Reset; -- Enable interrupt on OVRFLW event. - OVRFLW : OVRFLW_Field_1 := Ovrflw_Field_Reset; + OVRFLW : INTENSET_OVRFLW_Field_1 := Intenset_Ovrflw_Field_Reset; -- unspecified Reserved_2_15 : nrf51.UInt14 := 16#0#; -- Enable interrupt on COMPARE[0] event. @@ -135,7 +153,7 @@ package nrf51.RTC is -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -146,52 +164,75 @@ package nrf51.RTC is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on TICK event. + type INTENCLR_TICK_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_TICK_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on TICK event. - type TICK_Field_2 is - ( - -- Reset value for the field - Tick_Field_Reset, + type INTENCLR_TICK_Field_1 is + (-- Reset value for the field + Intenclr_Tick_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for TICK_Field_2 use - (Tick_Field_Reset => 0, + for INTENCLR_TICK_Field_1 use + (Intenclr_Tick_Field_Reset => 0, Clear => 1); -- Disable interrupt on OVRFLW event. - type OVRFLW_Field_2 is - ( - -- Reset value for the field - Ovrflw_Field_Reset, + type INTENCLR_OVRFLW_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on OVRFLW event. + type INTENCLR_OVRFLW_Field_1 is + (-- Reset value for the field + Intenclr_Ovrflw_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for OVRFLW_Field_2 use - (Ovrflw_Field_Reset => 0, + for INTENCLR_OVRFLW_Field_1 use + (Intenclr_Ovrflw_Field_Reset => 0, Clear => 1); -- Disable interrupt on COMPARE[0] event. - type COMPARE0_Field_2 is - ( - -- Reset value for the field - Compare0_Field_Reset, + type INTENCLR_COMPARE0_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on COMPARE[0] event. + type INTENCLR_COMPARE0_Field_1 is + (-- Reset value for the field + Intenclr_Compare0_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for COMPARE0_Field_2 use - (Compare0_Field_Reset => 0, + for INTENCLR_COMPARE0_Field_1 use + (Intenclr_Compare0_Field_Reset => 0, Clear => 1); - ---------------------- - -- INTENCLR.COMPARE -- - ---------------------- - -- INTENCLR_COMPARE array - type INTENCLR_COMPARE_Field_Array is array (0 .. 3) of COMPARE0_Field_2 + type INTENCLR_COMPARE_Field_Array is array (0 .. 3) + of INTENCLR_COMPARE0_Field_1 with Component_Size => 1, Size => 4; -- Type definition for INTENCLR_COMPARE @@ -217,9 +258,9 @@ package nrf51.RTC is -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on TICK event. - TICK : TICK_Field_2 := Tick_Field_Reset; + TICK : INTENCLR_TICK_Field_1 := Intenclr_Tick_Field_Reset; -- Disable interrupt on OVRFLW event. - OVRFLW : OVRFLW_Field_2 := Ovrflw_Field_Reset; + OVRFLW : INTENCLR_OVRFLW_Field_1 := Intenclr_Ovrflw_Field_Reset; -- unspecified Reserved_2_15 : nrf51.UInt14 := 16#0#; -- Disable interrupt on COMPARE[0] event. @@ -228,7 +269,7 @@ package nrf51.RTC is -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -239,16 +280,41 @@ package nrf51.RTC is Reserved_20_31 at 0 range 20 .. 31; end record; - -------------------- - -- EVTEN_Register -- - -------------------- + -- TICK event enable. + type EVTEN_TICK_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTEN_TICK_Field use + (Disabled => 0, + Enabled => 1); - ------------------- - -- EVTEN.COMPARE -- - ------------------- + -- OVRFLW event enable. + type EVTEN_OVRFLW_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTEN_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- COMPARE[0] event enable. + type EVTEN_COMPARE0_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTEN_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); -- EVTEN_COMPARE array - type EVTEN_COMPARE_Field_Array is array (0 .. 3) of COMPARE0_Field + type EVTEN_COMPARE_Field_Array is array (0 .. 3) of EVTEN_COMPARE0_Field with Component_Size => 1, Size => 4; -- Type definition for EVTEN_COMPARE @@ -274,9 +340,9 @@ package nrf51.RTC is -- Configures event enable routing to PPI for each RTC event. type EVTEN_Register is record -- TICK event enable. - TICK : TICK_Field := Disabled; + TICK : EVTEN_TICK_Field := nrf51.RTC.Disabled; -- OVRFLW event enable. - OVRFLW : OVRFLW_Field := Disabled; + OVRFLW : EVTEN_OVRFLW_Field := nrf51.RTC.Disabled; -- unspecified Reserved_2_15 : nrf51.UInt14 := 16#0#; -- COMPARE[0] event enable. @@ -285,7 +351,7 @@ package nrf51.RTC is -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for EVTEN_Register use record @@ -296,16 +362,75 @@ package nrf51.RTC is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------------- - -- EVTENSET_Register -- - ----------------------- + -- Enable routing to PPI of TICK event. + type EVTENSET_TICK_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTENSET_TICK_Field use + (Disabled => 0, + Enabled => 1); - ---------------------- - -- EVTENSET.COMPARE -- - ---------------------- + -- Enable routing to PPI of TICK event. + type EVTENSET_TICK_Field_1 is + (-- Reset value for the field + Evtenset_Tick_Field_Reset, + -- Enable event on write. + Set) + with Size => 1; + for EVTENSET_TICK_Field_1 use + (Evtenset_Tick_Field_Reset => 0, + Set => 1); + + -- Enable routing to PPI of OVRFLW event. + type EVTENSET_OVRFLW_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTENSET_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable routing to PPI of OVRFLW event. + type EVTENSET_OVRFLW_Field_1 is + (-- Reset value for the field + Evtenset_Ovrflw_Field_Reset, + -- Enable event on write. + Set) + with Size => 1; + for EVTENSET_OVRFLW_Field_1 use + (Evtenset_Ovrflw_Field_Reset => 0, + Set => 1); + + -- Enable routing to PPI of COMPARE[0] event. + type EVTENSET_COMPARE0_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTENSET_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable routing to PPI of COMPARE[0] event. + type EVTENSET_COMPARE0_Field_1 is + (-- Reset value for the field + Evtenset_Compare0_Field_Reset, + -- Enable event on write. + Set) + with Size => 1; + for EVTENSET_COMPARE0_Field_1 use + (Evtenset_Compare0_Field_Reset => 0, + Set => 1); -- EVTENSET_COMPARE array - type EVTENSET_COMPARE_Field_Array is array (0 .. 3) of COMPARE0_Field_1 + type EVTENSET_COMPARE_Field_Array is array (0 .. 3) + of EVTENSET_COMPARE0_Field_1 with Component_Size => 1, Size => 4; -- Type definition for EVTENSET_COMPARE @@ -332,9 +457,9 @@ package nrf51.RTC is -- value of EVTEN. type EVTENSET_Register is record -- Enable routing to PPI of TICK event. - TICK : TICK_Field_1 := Tick_Field_Reset; + TICK : EVTENSET_TICK_Field_1 := Evtenset_Tick_Field_Reset; -- Enable routing to PPI of OVRFLW event. - OVRFLW : OVRFLW_Field_1 := Ovrflw_Field_Reset; + OVRFLW : EVTENSET_OVRFLW_Field_1 := Evtenset_Ovrflw_Field_Reset; -- unspecified Reserved_2_15 : nrf51.UInt14 := 16#0#; -- Enable routing to PPI of COMPARE[0] event. @@ -343,7 +468,7 @@ package nrf51.RTC is -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for EVTENSET_Register use record @@ -354,16 +479,75 @@ package nrf51.RTC is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------------- - -- EVTENCLR_Register -- - ----------------------- + -- Disable routing to PPI of TICK event. + type EVTENCLR_TICK_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTENCLR_TICK_Field use + (Disabled => 0, + Enabled => 1); - ---------------------- - -- EVTENCLR.COMPARE -- - ---------------------- + -- Disable routing to PPI of TICK event. + type EVTENCLR_TICK_Field_1 is + (-- Reset value for the field + Evtenclr_Tick_Field_Reset, + -- Disable event on write. + Clear) + with Size => 1; + for EVTENCLR_TICK_Field_1 use + (Evtenclr_Tick_Field_Reset => 0, + Clear => 1); + + -- Disable routing to PPI of OVRFLW event. + type EVTENCLR_OVRFLW_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTENCLR_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable routing to PPI of OVRFLW event. + type EVTENCLR_OVRFLW_Field_1 is + (-- Reset value for the field + Evtenclr_Ovrflw_Field_Reset, + -- Disable event on write. + Clear) + with Size => 1; + for EVTENCLR_OVRFLW_Field_1 use + (Evtenclr_Ovrflw_Field_Reset => 0, + Clear => 1); + + -- Disable routing to PPI of COMPARE[0] event. + type EVTENCLR_COMPARE0_Field is + (-- Event disabled. + Disabled, + -- Event enabled. + Enabled) + with Size => 1; + for EVTENCLR_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable routing to PPI of COMPARE[0] event. + type EVTENCLR_COMPARE0_Field_1 is + (-- Reset value for the field + Evtenclr_Compare0_Field_Reset, + -- Disable event on write. + Clear) + with Size => 1; + for EVTENCLR_COMPARE0_Field_1 use + (Evtenclr_Compare0_Field_Reset => 0, + Clear => 1); -- EVTENCLR_COMPARE array - type EVTENCLR_COMPARE_Field_Array is array (0 .. 3) of COMPARE0_Field_2 + type EVTENCLR_COMPARE_Field_Array is array (0 .. 3) + of EVTENCLR_COMPARE0_Field_1 with Component_Size => 1, Size => 4; -- Type definition for EVTENCLR_COMPARE @@ -390,9 +574,9 @@ package nrf51.RTC is -- value of EVTEN. type EVTENCLR_Register is record -- Disable routing to PPI of TICK event. - TICK : TICK_Field_2 := Tick_Field_Reset; + TICK : EVTENCLR_TICK_Field_1 := Evtenclr_Tick_Field_Reset; -- Disable routing to PPI of OVRFLW event. - OVRFLW : OVRFLW_Field_2 := Ovrflw_Field_Reset; + OVRFLW : EVTENCLR_OVRFLW_Field_1 := Evtenclr_Ovrflw_Field_Reset; -- unspecified Reserved_2_15 : nrf51.UInt14 := 16#0#; -- Disable routing to PPI of COMPARE[0] event. @@ -401,7 +585,7 @@ package nrf51.RTC is -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for EVTENCLR_Register use record @@ -412,10 +596,6 @@ package nrf51.RTC is Reserved_20_31 at 0 range 20 .. 31; end record; - ---------------------- - -- COUNTER_Register -- - ---------------------- - subtype COUNTER_COUNTER_Field is nrf51.UInt24; -- Current COUNTER value. @@ -425,7 +605,7 @@ package nrf51.RTC is -- unspecified Reserved_24_31 : nrf51.Byte; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for COUNTER_Register use record @@ -433,10 +613,6 @@ package nrf51.RTC is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------------ - -- PRESCALER_Register -- - ------------------------ - subtype PRESCALER_PRESCALER_Field is nrf51.UInt12; -- 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be @@ -447,7 +623,7 @@ package nrf51.RTC is -- unspecified Reserved_12_31 : nrf51.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PRESCALER_Register use record @@ -455,10 +631,6 @@ package nrf51.RTC is Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------- - -- CC_Register -- - ----------------- - subtype CC_COMPARE_Field is nrf51.UInt24; -- Capture/compare registers. @@ -468,7 +640,7 @@ package nrf51.RTC is -- unspecified Reserved_24_31 : nrf51.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CC_Register use record @@ -479,30 +651,25 @@ package nrf51.RTC is -- Capture/compare registers. type CC_Registers is array (0 .. 3) of CC_Register; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.RTC.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -517,60 +684,60 @@ package nrf51.RTC is -- Real time counter 0. type RTC_Peripheral is record -- Start RTC Counter. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop RTC Counter. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Clear RTC Counter. - TASKS_CLEAR : nrf51.Word; + TASKS_CLEAR : aliased nrf51.UInt32; -- Set COUNTER to 0xFFFFFFF0. - TASKS_TRIGOVRFLW : nrf51.Word; + TASKS_TRIGOVRFLW : aliased nrf51.UInt32; -- Event on COUNTER increment. - EVENTS_TICK : nrf51.Word; + EVENTS_TICK : aliased nrf51.UInt32; -- Event on COUNTER overflow. - EVENTS_OVRFLW : nrf51.Word; + EVENTS_OVRFLW : aliased nrf51.UInt32; -- Compare event on CC[n] match. - EVENTS_COMPARE : EVENTS_COMPARE_Registers; + EVENTS_COMPARE : aliased EVENTS_COMPARE_Registers; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Configures event enable routing to PPI for each RTC event. - EVTEN : EVTEN_Register; + EVTEN : aliased EVTEN_Register; -- Enable events routing to PPI. The reading of this register gives the -- value of EVTEN. - EVTENSET : EVTENSET_Register; + EVTENSET : aliased EVTENSET_Register; -- Disable events routing to PPI. The reading of this register gives the -- value of EVTEN. - EVTENCLR : EVTENCLR_Register; + EVTENCLR : aliased EVTENCLR_Register; -- Current COUNTER value. - COUNTER : COUNTER_Register; + COUNTER : aliased COUNTER_Register; -- 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be -- written when RTC is STOPed. - PRESCALER : PRESCALER_Register; + PRESCALER : aliased PRESCALER_Register; -- Capture/compare registers. - CC : CC_Registers; + CC : aliased CC_Registers; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for RTC_Peripheral use record - TASKS_START at 0 range 0 .. 31; - TASKS_STOP at 4 range 0 .. 31; - TASKS_CLEAR at 8 range 0 .. 31; - TASKS_TRIGOVRFLW at 12 range 0 .. 31; - EVENTS_TICK at 256 range 0 .. 31; - EVENTS_OVRFLW at 260 range 0 .. 31; - EVENTS_COMPARE at 320 range 0 .. 127; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - EVTEN at 832 range 0 .. 31; - EVTENSET at 836 range 0 .. 31; - EVTENCLR at 840 range 0 .. 31; - COUNTER at 1284 range 0 .. 31; - PRESCALER at 1288 range 0 .. 31; - CC at 1344 range 0 .. 127; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_CLEAR at 16#8# range 0 .. 31; + TASKS_TRIGOVRFLW at 16#C# range 0 .. 31; + EVENTS_TICK at 16#100# range 0 .. 31; + EVENTS_OVRFLW at 16#104# range 0 .. 31; + EVENTS_COMPARE at 16#140# range 0 .. 127; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + EVTEN at 16#340# range 0 .. 31; + EVTENSET at 16#344# range 0 .. 31; + EVTENCLR at 16#348# range 0 .. 31; + COUNTER at 16#504# range 0 .. 31; + PRESCALER at 16#508# range 0 .. 31; + CC at 16#540# range 0 .. 127; + POWER at 16#FFC# range 0 .. 31; end record; -- Real time counter 0. diff --git a/microbit/nrf51/nrf51-spi.ads b/microbit/nrf51/nrf51-spi.ads index d749656..88be4d1 100644 --- a/microbit/nrf51/nrf51-spi.ads +++ b/microbit/nrf51/nrf51-spi.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,32 +43,26 @@ package nrf51.SPI is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on READY event. - type READY_Field is - ( - -- Interrupt disabled. + type INTENSET_READY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for READY_Field use + for INTENSET_READY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on READY event. - type READY_Field_1 is - ( - -- Reset value for the field - Ready_Field_Reset, + type INTENSET_READY_Field_1 is + (-- Reset value for the field + Intenset_Ready_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for READY_Field_1 use - (Ready_Field_Reset => 0, + for INTENSET_READY_Field_1 use + (Intenset_Ready_Field_Reset => 0, Set => 1); -- Interrupt enable set register. @@ -45,11 +70,11 @@ package nrf51.SPI is -- unspecified Reserved_0_1 : nrf51.UInt2 := 16#0#; -- Enable interrupt on READY event. - READY : READY_Field_1 := Ready_Field_Reset; + READY : INTENSET_READY_Field_1 := Intenset_Ready_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -58,20 +83,26 @@ package nrf51.SPI is Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on READY event. + type INTENCLR_READY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_READY_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on READY event. - type READY_Field_2 is - ( - -- Reset value for the field - Ready_Field_Reset, + type INTENCLR_READY_Field_1 is + (-- Reset value for the field + Intenclr_Ready_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for READY_Field_2 use - (Ready_Field_Reset => 0, + for INTENCLR_READY_Field_1 use + (Intenclr_Ready_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. @@ -79,11 +110,11 @@ package nrf51.SPI is -- unspecified Reserved_0_1 : nrf51.UInt2 := 16#0#; -- Disable interrupt on READY event. - READY : READY_Field_2 := Ready_Field_Reset; + READY : INTENCLR_READY_Field_1 := Intenclr_Ready_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -92,30 +123,25 @@ package nrf51.SPI is Reserved_3_31 at 0 range 3 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- Enable or disable SPI. - type ENABLE_Field is - ( - -- Disabled SPI. + type ENABLE_ENABLE_Field is + (-- Disabled SPI. Disabled, -- Enable SPI. Enabled) with Size => 3; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 1); -- Enable SPI. type ENABLE_Register is record -- Enable or disable SPI. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.SPI.Disabled; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -123,10 +149,6 @@ package nrf51.SPI is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- RXD_Register -- - ------------------ - subtype RXD_RXD_Field is nrf51.Byte; -- RX data. @@ -137,7 +159,7 @@ package nrf51.SPI is -- unspecified Reserved_8_31 : nrf51.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXD_Register use record @@ -145,10 +167,6 @@ package nrf51.SPI is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- TXD_Register -- - ------------------ - subtype TXD_TXD_Field is nrf51.Byte; -- TX data. @@ -158,7 +176,7 @@ package nrf51.SPI is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXD_Register use record @@ -166,60 +184,51 @@ package nrf51.SPI is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- - -- Bit order. - type ORDER_Field is - ( - -- Most significant bit transmitted out first. + type CONFIG_ORDER_Field is + (-- Most significant bit transmitted out first. Msbfirst, -- Least significant bit transmitted out first. Lsbfirst) with Size => 1; - for ORDER_Field use + for CONFIG_ORDER_Field use (Msbfirst => 0, Lsbfirst => 1); -- Serial clock (SCK) phase. - type CPHA_Field is - ( - -- Sample on leading edge of the clock. Shift serial data on trailing - -- edge. + type CONFIG_CPHA_Field is + (-- Sample on leading edge of the clock. Shift serial data on trailing edge. Leading, - -- Sample on trailing edge of the clock. Shift serial data on leading - -- edge. + -- Sample on trailing edge of the clock. Shift serial data on leading edge. Trailing) with Size => 1; - for CPHA_Field use + for CONFIG_CPHA_Field use (Leading => 0, Trailing => 1); -- Serial clock (SCK) polarity. - type CPOL_Field is - ( - -- Active high. + type CONFIG_CPOL_Field is + (-- Active high. Activehigh, -- Active low. Activelow) with Size => 1; - for CPOL_Field use + for CONFIG_CPOL_Field use (Activehigh => 0, Activelow => 1); -- Configuration register. type CONFIG_Register is record -- Bit order. - ORDER : ORDER_Field := Msbfirst; + ORDER : CONFIG_ORDER_Field := nrf51.SPI.Msbfirst; -- Serial clock (SCK) phase. - CPHA : CPHA_Field := Leading; + CPHA : CONFIG_CPHA_Field := nrf51.SPI.Leading; -- Serial clock (SCK) polarity. - CPOL : CPOL_Field := Activehigh; + CPOL : CONFIG_CPOL_Field := nrf51.SPI.Activehigh; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -229,30 +238,25 @@ package nrf51.SPI is Reserved_3_31 at 0 range 3 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.SPI.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -267,45 +271,45 @@ package nrf51.SPI is -- SPI master 0. type SPI_Peripheral is record -- TXD byte sent and RXD byte received. - EVENTS_READY : nrf51.Word; + EVENTS_READY : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Enable SPI. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- Pin select for SCK. - PSELSCK : nrf51.Word; + PSELSCK : aliased nrf51.UInt32; -- Pin select for MOSI. - PSELMOSI : nrf51.Word; + PSELMOSI : aliased nrf51.UInt32; -- Pin select for MISO. - PSELMISO : nrf51.Word; + PSELMISO : aliased nrf51.UInt32; -- RX data. - RXD : RXD_Register; + RXD : aliased RXD_Register; -- TX data. - TXD : TXD_Register; + TXD : aliased TXD_Register; -- SPI frequency - FREQUENCY : nrf51.Word; + FREQUENCY : aliased nrf51.UInt32; -- Configuration register. - CONFIG : CONFIG_Register; + CONFIG : aliased CONFIG_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for SPI_Peripheral use record - EVENTS_READY at 264 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - PSELSCK at 1288 range 0 .. 31; - PSELMOSI at 1292 range 0 .. 31; - PSELMISO at 1296 range 0 .. 31; - RXD at 1304 range 0 .. 31; - TXD at 1308 range 0 .. 31; - FREQUENCY at 1316 range 0 .. 31; - CONFIG at 1364 range 0 .. 31; - POWER at 4092 range 0 .. 31; + EVENTS_READY at 16#108# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSELSCK at 16#508# range 0 .. 31; + PSELMOSI at 16#50C# range 0 .. 31; + PSELMISO at 16#510# range 0 .. 31; + RXD at 16#518# range 0 .. 31; + TXD at 16#51C# range 0 .. 31; + FREQUENCY at 16#524# range 0 .. 31; + CONFIG at 16#554# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- SPI master 0. diff --git a/microbit/nrf51/nrf51-spim.ads b/microbit/nrf51/nrf51-spim.ads index 9235074..e964e75 100644 --- a/microbit/nrf51/nrf51-spim.ads +++ b/microbit/nrf51/nrf51-spim.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,104 +43,92 @@ package nrf51.SPIM is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on STOPPED event. - type STOPPED_Field is - ( - -- Interrupt disabled. + type INTENSET_STOPPED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for STOPPED_Field use + for INTENSET_STOPPED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on STOPPED event. - type STOPPED_Field_1 is - ( - -- Reset value for the field - Stopped_Field_Reset, + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for STOPPED_Field_1 use - (Stopped_Field_Reset => 0, + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, Set => 1); -- Enable interrupt on ENDRX event. - type ENDRX_Field is - ( - -- Interrupt disabled. + type INTENSET_ENDRX_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ENDRX_Field use + for INTENSET_ENDRX_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ENDRX event. - type ENDRX_Field_1 is - ( - -- Reset value for the field - Endrx_Field_Reset, + type INTENSET_ENDRX_Field_1 is + (-- Reset value for the field + Intenset_Endrx_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ENDRX_Field_1 use - (Endrx_Field_Reset => 0, + for INTENSET_ENDRX_Field_1 use + (Intenset_Endrx_Field_Reset => 0, Set => 1); -- Enable interrupt on ENDTX event. - type ENDTX_Field is - ( - -- Interrupt disabled. + type INTENSET_ENDTX_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ENDTX_Field use + for INTENSET_ENDTX_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ENDTX event. - type ENDTX_Field_1 is - ( - -- Reset value for the field - Endtx_Field_Reset, + type INTENSET_ENDTX_Field_1 is + (-- Reset value for the field + Intenset_Endtx_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ENDTX_Field_1 use - (Endtx_Field_Reset => 0, + for INTENSET_ENDTX_Field_1 use + (Intenset_Endtx_Field_Reset => 0, Set => 1); -- Enable interrupt on STARTED event. - type STARTED_Field is - ( - -- Interrupt disabled. + type INTENSET_STARTED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for STARTED_Field use + for INTENSET_STARTED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on STARTED event. - type STARTED_Field_1 is - ( - -- Reset value for the field - Started_Field_Reset, + type INTENSET_STARTED_Field_1 is + (-- Reset value for the field + Intenset_Started_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for STARTED_Field_1 use - (Started_Field_Reset => 0, + for INTENSET_STARTED_Field_1 use + (Intenset_Started_Field_Reset => 0, Set => 1); -- Interrupt enable set register. @@ -117,23 +136,25 @@ package nrf51.SPIM is -- unspecified Reserved_0_0 : nrf51.Bit := 16#0#; -- Enable interrupt on STOPPED event. - STOPPED : STOPPED_Field_1 := Stopped_Field_Reset; + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; -- unspecified Reserved_2_3 : nrf51.UInt2 := 16#0#; -- Enable interrupt on ENDRX event. - ENDRX : ENDRX_Field_1 := Endrx_Field_Reset; + ENDRX : INTENSET_ENDRX_Field_1 := Intenset_Endrx_Field_Reset; -- unspecified Reserved_5_7 : nrf51.UInt3 := 16#0#; -- Enable interrupt on ENDTX event. - ENDTX : ENDTX_Field_1 := Endtx_Field_Reset; + ENDTX : INTENSET_ENDTX_Field_1 := Intenset_Endtx_Field_Reset; -- unspecified Reserved_9_18 : nrf51.UInt10 := 16#0#; -- Enable interrupt on STARTED event. - STARTED : STARTED_Field_1 := Started_Field_Reset; + STARTED : INTENSET_STARTED_Field_1 := + Intenset_Started_Field_Reset; -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -148,56 +169,92 @@ package nrf51.SPIM is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on STOPPED event. + type INTENCLR_STOPPED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on STOPPED event. - type STOPPED_Field_2 is - ( - -- Reset value for the field - Stopped_Field_Reset, + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for STOPPED_Field_2 use - (Stopped_Field_Reset => 0, + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, Clear => 1); -- Disable interrupt on ENDRX event. - type ENDRX_Field_2 is - ( - -- Reset value for the field - Endrx_Field_Reset, + type INTENCLR_ENDRX_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ENDRX event. + type INTENCLR_ENDRX_Field_1 is + (-- Reset value for the field + Intenclr_Endrx_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ENDRX_Field_2 use - (Endrx_Field_Reset => 0, + for INTENCLR_ENDRX_Field_1 use + (Intenclr_Endrx_Field_Reset => 0, Clear => 1); -- Disable interrupt on ENDTX event. - type ENDTX_Field_2 is - ( - -- Reset value for the field - Endtx_Field_Reset, + type INTENCLR_ENDTX_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ENDTX event. + type INTENCLR_ENDTX_Field_1 is + (-- Reset value for the field + Intenclr_Endtx_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ENDTX_Field_2 use - (Endtx_Field_Reset => 0, + for INTENCLR_ENDTX_Field_1 use + (Intenclr_Endtx_Field_Reset => 0, Clear => 1); -- Disable interrupt on STARTED event. - type STARTED_Field_2 is - ( - -- Reset value for the field - Started_Field_Reset, + type INTENCLR_STARTED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on STARTED event. + type INTENCLR_STARTED_Field_1 is + (-- Reset value for the field + Intenclr_Started_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for STARTED_Field_2 use - (Started_Field_Reset => 0, + for INTENCLR_STARTED_Field_1 use + (Intenclr_Started_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. @@ -205,23 +262,25 @@ package nrf51.SPIM is -- unspecified Reserved_0_0 : nrf51.Bit := 16#0#; -- Disable interrupt on STOPPED event. - STOPPED : STOPPED_Field_2 := Stopped_Field_Reset; + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; -- unspecified Reserved_2_3 : nrf51.UInt2 := 16#0#; -- Disable interrupt on ENDRX event. - ENDRX : ENDRX_Field_2 := Endrx_Field_Reset; + ENDRX : INTENCLR_ENDRX_Field_1 := Intenclr_Endrx_Field_Reset; -- unspecified Reserved_5_7 : nrf51.UInt3 := 16#0#; -- Disable interrupt on ENDTX event. - ENDTX : ENDTX_Field_2 := Endtx_Field_Reset; + ENDTX : INTENCLR_ENDTX_Field_1 := Intenclr_Endtx_Field_Reset; -- unspecified Reserved_9_18 : nrf51.UInt10 := 16#0#; -- Disable interrupt on STARTED event. - STARTED : STARTED_Field_2 := Started_Field_Reset; + STARTED : INTENCLR_STARTED_Field_1 := + Intenclr_Started_Field_Reset; -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -236,30 +295,25 @@ package nrf51.SPIM is Reserved_20_31 at 0 range 20 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- Enable or disable SPIM. - type ENABLE_Field is - ( - -- Disabled SPIM. + type ENABLE_ENABLE_Field is + (-- Disabled SPIM. Disabled, -- Enable SPIM. Enabled) with Size => 4; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 7); -- Enable SPIM. type ENABLE_Register is record -- Enable or disable SPIM. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.SPIM.Disabled; -- unspecified Reserved_4_31 : nrf51.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -267,60 +321,182 @@ package nrf51.SPIM is Reserved_4_31 at 0 range 4 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- + ----------------------------------- + -- SPIM_PSEL cluster's Registers -- + ----------------------------------- + + -- Pin select configuration. + type SPIM_PSEL_Cluster is record + -- Pin select for SCK. + SCK : aliased nrf51.UInt32; + -- Pin select for MOSI. + MOSI : aliased nrf51.UInt32; + -- Pin select for MISO. + MISO : aliased nrf51.UInt32; + end record + with Size => 96; + + for SPIM_PSEL_Cluster use record + SCK at 16#0# range 0 .. 31; + MOSI at 16#4# range 0 .. 31; + MISO at 16#8# range 0 .. 31; + end record; + + ---------------------------------- + -- SPIM_RXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_RXD_MAXCNT_Field is nrf51.Byte; + + -- Maximum number of buffer bytes to receive. + type MAXCNT_RXD_Register is record + -- Maximum number of buffer bytes to receive. + MAXCNT : MAXCNT_RXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : nrf51.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_RXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_RXD_AMOUNT_Field is nrf51.Byte; + + -- Number of bytes received in the last transaction. + type AMOUNT_RXD_Register is record + -- Read-only. Number of bytes received in the last transaction. + AMOUNT : AMOUNT_RXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : nrf51.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_RXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- RXD EasyDMA configuration and status. + type SPIM_RXD_Cluster is record + -- Data pointer. + PTR : aliased nrf51.UInt32; + -- Maximum number of buffer bytes to receive. + MAXCNT : aliased MAXCNT_RXD_Register; + -- Number of bytes received in the last transaction. + AMOUNT : aliased AMOUNT_RXD_Register; + end record + with Size => 96; + + for SPIM_RXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; + + ---------------------------------- + -- SPIM_TXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_TXD_MAXCNT_Field is nrf51.Byte; + + -- Maximum number of buffer bytes to send. + type MAXCNT_TXD_Register is record + -- Maximum number of buffer bytes to send. + MAXCNT : MAXCNT_TXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : nrf51.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_TXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_TXD_AMOUNT_Field is nrf51.Byte; + + -- Number of bytes sent in the last transaction. + type AMOUNT_TXD_Register is record + -- Read-only. Number of bytes sent in the last transaction. + AMOUNT : AMOUNT_TXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : nrf51.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_TXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- TXD EasyDMA configuration and status. + type SPIM_TXD_Cluster is record + -- Data pointer. + PTR : aliased nrf51.UInt32; + -- Maximum number of buffer bytes to send. + MAXCNT : aliased MAXCNT_TXD_Register; + -- Number of bytes sent in the last transaction. + AMOUNT : aliased AMOUNT_TXD_Register; + end record + with Size => 96; + + for SPIM_TXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; -- Bit order. - type ORDER_Field is - ( - -- Most significant bit transmitted out first. + type CONFIG_ORDER_Field is + (-- Most significant bit transmitted out first. Msbfirst, -- Least significant bit transmitted out first. Lsbfirst) with Size => 1; - for ORDER_Field use + for CONFIG_ORDER_Field use (Msbfirst => 0, Lsbfirst => 1); -- Serial clock (SCK) phase. - type CPHA_Field is - ( - -- Sample on leading edge of the clock. Shift serial data on trailing - -- edge. + type CONFIG_CPHA_Field is + (-- Sample on leading edge of the clock. Shift serial data on trailing edge. Leading, - -- Sample on trailing edge of the clock. Shift serial data on leading - -- edge. + -- Sample on trailing edge of the clock. Shift serial data on leading edge. Trailing) with Size => 1; - for CPHA_Field use + for CONFIG_CPHA_Field use (Leading => 0, Trailing => 1); -- Serial clock (SCK) polarity. - type CPOL_Field is - ( - -- Active high. + type CONFIG_CPOL_Field is + (-- Active high. Activehigh, -- Active low. Activelow) with Size => 1; - for CPOL_Field use + for CONFIG_CPOL_Field use (Activehigh => 0, Activelow => 1); -- Configuration register. type CONFIG_Register is record -- Bit order. - ORDER : ORDER_Field := Msbfirst; + ORDER : CONFIG_ORDER_Field := nrf51.SPIM.Msbfirst; -- Serial clock (SCK) phase. - CPHA : CPHA_Field := Leading; + CPHA : CONFIG_CPHA_Field := nrf51.SPIM.Leading; -- Serial clock (SCK) polarity. - CPOL : CPOL_Field := Activehigh; + CPOL : CONFIG_CPOL_Field := nrf51.SPIM.Activehigh; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -330,10 +506,6 @@ package nrf51.SPIM is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- ORC_Register -- - ------------------ - subtype ORC_ORC_Field is nrf51.Byte; -- Over-read character. @@ -343,7 +515,7 @@ package nrf51.SPIM is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ORC_Register use record @@ -351,30 +523,25 @@ package nrf51.SPIM is Reserved_8_31 at 0 range 8 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.SPIM.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -387,69 +554,69 @@ package nrf51.SPIM is ----------------- -- SPI master with easyDMA 1. - type SPIM1_Peripheral is record + type SPIM_Peripheral is record -- Start SPI transaction. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop SPI transaction. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Suspend SPI transaction. - TASKS_SUSPEND : nrf51.Word; + TASKS_SUSPEND : aliased nrf51.UInt32; -- Resume SPI transaction. - TASKS_RESUME : nrf51.Word; + TASKS_RESUME : aliased nrf51.UInt32; -- SPI transaction has stopped. - EVENTS_STOPPED : nrf51.Word; + EVENTS_STOPPED : aliased nrf51.UInt32; -- End of RXD buffer reached. - EVENTS_ENDRX : nrf51.Word; + EVENTS_ENDRX : aliased nrf51.UInt32; -- End of TXD buffer reached. - EVENTS_ENDTX : nrf51.Word; + EVENTS_ENDTX : aliased nrf51.UInt32; -- Transaction started. - EVENTS_STARTED : nrf51.Word; + EVENTS_STARTED : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Enable SPIM. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- Pin select configuration. - PSEL : nrf51.Word; + PSEL : aliased SPIM_PSEL_Cluster; -- SPI frequency. - FREQUENCY : nrf51.Word; + FREQUENCY : aliased nrf51.UInt32; -- RXD EasyDMA configuration and status. - RXD : nrf51.Word; + RXD : aliased SPIM_RXD_Cluster; -- TXD EasyDMA configuration and status. - TXD : nrf51.Word; + TXD : aliased SPIM_TXD_Cluster; -- Configuration register. - CONFIG : CONFIG_Register; + CONFIG : aliased CONFIG_Register; -- Over-read character. - ORC : ORC_Register; + ORC : aliased ORC_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; - for SPIM1_Peripheral use record - TASKS_START at 16 range 0 .. 31; - TASKS_STOP at 20 range 0 .. 31; - TASKS_SUSPEND at 28 range 0 .. 31; - TASKS_RESUME at 32 range 0 .. 31; - EVENTS_STOPPED at 260 range 0 .. 31; - EVENTS_ENDRX at 272 range 0 .. 31; - EVENTS_ENDTX at 288 range 0 .. 31; - EVENTS_STARTED at 332 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - PSEL at 1288 range 0 .. 31; - FREQUENCY at 1316 range 0 .. 31; - RXD at 1332 range 0 .. 31; - TXD at 1348 range 0 .. 31; - CONFIG at 1364 range 0 .. 31; - ORC at 1472 range 0 .. 31; - POWER at 4092 range 0 .. 31; + for SPIM_Peripheral use record + TASKS_START at 16#10# range 0 .. 31; + TASKS_STOP at 16#14# range 0 .. 31; + TASKS_SUSPEND at 16#1C# range 0 .. 31; + TASKS_RESUME at 16#20# range 0 .. 31; + EVENTS_STOPPED at 16#104# range 0 .. 31; + EVENTS_ENDRX at 16#110# range 0 .. 31; + EVENTS_ENDTX at 16#120# range 0 .. 31; + EVENTS_STARTED at 16#14C# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#508# range 0 .. 95; + FREQUENCY at 16#524# range 0 .. 31; + RXD at 16#534# range 0 .. 95; + TXD at 16#544# range 0 .. 95; + CONFIG at 16#554# range 0 .. 31; + ORC at 16#5C0# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- SPI master with easyDMA 1. - SPIM1_Periph : aliased SPIM1_Peripheral + SPIM1_Periph : aliased SPIM_Peripheral with Import, Address => SPIM1_Base; end nrf51.SPIM; diff --git a/microbit/nrf51/nrf51-spis.ads b/microbit/nrf51/nrf51-spis.ads index e056430..a5459fb 100644 --- a/microbit/nrf51/nrf51-spis.ads +++ b/microbit/nrf51/nrf51-spis.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,19 +43,14 @@ package nrf51.SPIS is -- Registers -- --------------- - --------------------- - -- SHORTS_Register -- - --------------------- - -- Shortcut between END event and the ACQUIRE task. - type END_ACQUIRE_Field is - ( - -- Shortcut disabled. + type SHORTS_END_ACQUIRE_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for END_ACQUIRE_Field use + for SHORTS_END_ACQUIRE_Field use (Disabled => 0, Enabled => 1); @@ -33,11 +59,11 @@ package nrf51.SPIS is -- unspecified Reserved_0_1 : nrf51.UInt2 := 16#0#; -- Shortcut between END event and the ACQUIRE task. - END_ACQUIRE : END_ACQUIRE_Field := Disabled; + END_ACQUIRE : SHORTS_END_ACQUIRE_Field := nrf51.SPIS.Disabled; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -46,80 +72,48 @@ package nrf51.SPIS is Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on END event. - type END_Field is - ( - -- Interrupt disabled. + type INTENSET_END_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for END_Field use + for INTENSET_END_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on END event. - type END_Field_1 is - ( - -- Reset value for the field - End_Field_Reset, + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for END_Field_1 use - (End_Field_Reset => 0, - Set => 1); - - -- enable interrupt on ENDRX event. - type ENDRX_Field is - ( - -- Interrupt disabled. - Disabled, - -- Interrupt enabled. - Enabled) - with Size => 1; - for ENDRX_Field use - (Disabled => 0, - Enabled => 1); - - -- enable interrupt on ENDRX event. - type ENDRX_Field_1 is - ( - -- Reset value for the field - Endrx_Field_Reset, - -- Enable interrupt on write. - Set) - with Size => 1; - for ENDRX_Field_1 use - (Endrx_Field_Reset => 0, + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, Set => 1); -- Enable interrupt on ACQUIRED event. - type ACQUIRED_Field is - ( - -- Interrupt disabled. + type INTENSET_ACQUIRED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ACQUIRED_Field use + for INTENSET_ACQUIRED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ACQUIRED event. - type ACQUIRED_Field_1 is - ( - -- Reset value for the field - Acquired_Field_Reset, + type INTENSET_ACQUIRED_Field_1 is + (-- Reset value for the field + Intenset_Acquired_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ACQUIRED_Field_1 use - (Acquired_Field_Reset => 0, + for INTENSET_ACQUIRED_Field_1 use + (Intenset_Acquired_Field_Reset => 0, Set => 1); -- Interrupt enable set register. @@ -127,69 +121,68 @@ package nrf51.SPIS is -- unspecified Reserved_0_0 : nrf51.Bit := 16#0#; -- Enable interrupt on END event. - END_k : END_Field_1 := End_Field_Reset; - -- unspecified - Reserved_2_3 : nrf51.UInt2 := 16#0#; - -- enable interrupt on ENDRX event. - ENDRX : ENDRX_Field_1 := Endrx_Field_Reset; + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; -- unspecified - Reserved_5_9 : nrf51.UInt5 := 16#0#; + Reserved_2_9 : nrf51.Byte := 16#0#; -- Enable interrupt on ACQUIRED event. - ACQUIRED : ACQUIRED_Field_1 := Acquired_Field_Reset; + ACQUIRED : INTENSET_ACQUIRED_Field_1 := + Intenset_Acquired_Field_Reset; -- unspecified Reserved_11_31 : nrf51.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record Reserved_0_0 at 0 range 0 .. 0; END_k at 0 range 1 .. 1; - Reserved_2_3 at 0 range 2 .. 3; - ENDRX at 0 range 4 .. 4; - Reserved_5_9 at 0 range 5 .. 9; + Reserved_2_9 at 0 range 2 .. 9; ACQUIRED at 0 range 10 .. 10; Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on END event. + type INTENCLR_END_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on END event. - type END_Field_2 is - ( - -- Reset value for the field - End_Field_Reset, + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for END_Field_2 use - (End_Field_Reset => 0, + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, Clear => 1); - -- Disable interrupt on ENDRX event. - type ENDRX_Field_2 is - ( - -- Reset value for the field - Endrx_Field_Reset, - -- Disable interrupt on write. - Clear) + -- Disable interrupt on ACQUIRED event. + type INTENCLR_ACQUIRED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) with Size => 1; - for ENDRX_Field_2 use - (Endrx_Field_Reset => 0, - Clear => 1); + for INTENCLR_ACQUIRED_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on ACQUIRED event. - type ACQUIRED_Field_2 is - ( - -- Reset value for the field - Acquired_Field_Reset, + type INTENCLR_ACQUIRED_Field_1 is + (-- Reset value for the field + Intenclr_Acquired_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ACQUIRED_Field_2 use - (Acquired_Field_Reset => 0, + for INTENCLR_ACQUIRED_Field_1 use + (Intenclr_Acquired_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. @@ -197,49 +190,38 @@ package nrf51.SPIS is -- unspecified Reserved_0_0 : nrf51.Bit := 16#0#; -- Disable interrupt on END event. - END_k : END_Field_2 := End_Field_Reset; - -- unspecified - Reserved_2_3 : nrf51.UInt2 := 16#0#; - -- Disable interrupt on ENDRX event. - ENDRX : ENDRX_Field_2 := Endrx_Field_Reset; + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; -- unspecified - Reserved_5_9 : nrf51.UInt5 := 16#0#; + Reserved_2_9 : nrf51.Byte := 16#0#; -- Disable interrupt on ACQUIRED event. - ACQUIRED : ACQUIRED_Field_2 := Acquired_Field_Reset; + ACQUIRED : INTENCLR_ACQUIRED_Field_1 := + Intenclr_Acquired_Field_Reset; -- unspecified Reserved_11_31 : nrf51.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record Reserved_0_0 at 0 range 0 .. 0; END_k at 0 range 1 .. 1; - Reserved_2_3 at 0 range 2 .. 3; - ENDRX at 0 range 4 .. 4; - Reserved_5_9 at 0 range 5 .. 9; + Reserved_2_9 at 0 range 2 .. 9; ACQUIRED at 0 range 10 .. 10; Reserved_11_31 at 0 range 11 .. 31; end record; - ---------------------- - -- SEMSTAT_Register -- - ---------------------- - -- Semaphore status. - type SEMSTAT_Field is - ( - -- Semaphore is free. + type SEMSTAT_SEMSTAT_Field is + (-- Semaphore is free. Free, -- Semaphore is assigned to the CPU. Cpu, -- Semaphore is assigned to the SPIS. Spis, - -- Semaphore is assigned to the SPIS, but a handover to the CPU is - -- pending. + -- Semaphore is assigned to the SPIS, but a handover to the CPU is pending. Cpupending) with Size => 2; - for SEMSTAT_Field use + for SEMSTAT_SEMSTAT_Field use (Free => 0, Cpu => 1, Spis => 2, @@ -248,11 +230,11 @@ package nrf51.SPIS is -- Semaphore status. type SEMSTAT_Register is record -- Read-only. Semaphore status. - SEMSTAT : SEMSTAT_Field; + SEMSTAT : SEMSTAT_SEMSTAT_Field; -- unspecified Reserved_2_31 : nrf51.UInt30; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SEMSTAT_Register use record @@ -260,68 +242,60 @@ package nrf51.SPIS is Reserved_2_31 at 0 range 2 .. 31; end record; - --------------------- - -- STATUS_Register -- - --------------------- - -- TX buffer overread detected, and prevented. - type OVERREAD_Field is - ( - -- Error not present. + type STATUS_OVERREAD_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for OVERREAD_Field use + for STATUS_OVERREAD_Field use (Notpresent => 0, Present => 1); -- TX buffer overread detected, and prevented. - type OVERREAD_Field_1 is - ( - -- Reset value for the field - Overread_Field_Reset, + type STATUS_OVERREAD_Field_1 is + (-- Reset value for the field + Status_Overread_Field_Reset, -- Clear on write. Clear) with Size => 1; - for OVERREAD_Field_1 use - (Overread_Field_Reset => 0, + for STATUS_OVERREAD_Field_1 use + (Status_Overread_Field_Reset => 0, Clear => 1); -- RX buffer overflow detected, and prevented. - type OVERFLOW_Field is - ( - -- Error not present. + type STATUS_OVERFLOW_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for OVERFLOW_Field use + for STATUS_OVERFLOW_Field use (Notpresent => 0, Present => 1); -- RX buffer overflow detected, and prevented. - type OVERFLOW_Field_1 is - ( - -- Reset value for the field - Overflow_Field_Reset, + type STATUS_OVERFLOW_Field_1 is + (-- Reset value for the field + Status_Overflow_Field_Reset, -- Clear on write. Clear) with Size => 1; - for OVERFLOW_Field_1 use - (Overflow_Field_Reset => 0, + for STATUS_OVERFLOW_Field_1 use + (Status_Overflow_Field_Reset => 0, Clear => 1); -- Status from last transaction. type STATUS_Register is record -- TX buffer overread detected, and prevented. - OVERREAD : OVERREAD_Field_1 := Overread_Field_Reset; + OVERREAD : STATUS_OVERREAD_Field_1 := Status_Overread_Field_Reset; -- RX buffer overflow detected, and prevented. - OVERFLOW : OVERFLOW_Field_1 := Overflow_Field_Reset; + OVERFLOW : STATUS_OVERFLOW_Field_1 := Status_Overflow_Field_Reset; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for STATUS_Register use record @@ -330,30 +304,25 @@ package nrf51.SPIS is Reserved_2_31 at 0 range 2 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- Enable or disable SPIS. - type ENABLE_Field is - ( - -- Disabled SPIS. + type ENABLE_ENABLE_Field is + (-- Disabled SPIS. Disabled, -- Enable SPIS. Enabled) with Size => 3; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 2); -- Enable SPIS. type ENABLE_Register is record -- Enable or disable SPIS. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.SPIS.Disabled; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -361,10 +330,6 @@ package nrf51.SPIS is Reserved_3_31 at 0 range 3 .. 31; end record; - -------------------- - -- MAXRX_Register -- - -------------------- - subtype MAXRX_MAXRX_Field is nrf51.Byte; -- Maximum number of bytes in the receive buffer. @@ -374,7 +339,7 @@ package nrf51.SPIS is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MAXRX_Register use record @@ -382,10 +347,6 @@ package nrf51.SPIS is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------------- - -- AMOUNTRX_Register -- - ----------------------- - subtype AMOUNTRX_AMOUNTRX_Field is nrf51.Byte; -- Number of bytes received in last granted transaction. @@ -395,7 +356,7 @@ package nrf51.SPIS is -- unspecified Reserved_8_31 : nrf51.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for AMOUNTRX_Register use record @@ -403,10 +364,6 @@ package nrf51.SPIS is Reserved_8_31 at 0 range 8 .. 31; end record; - -------------------- - -- MAXTX_Register -- - -------------------- - subtype MAXTX_MAXTX_Field is nrf51.Byte; -- Maximum number of bytes in the transmit buffer. @@ -416,7 +373,7 @@ package nrf51.SPIS is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MAXTX_Register use record @@ -424,10 +381,6 @@ package nrf51.SPIS is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------------- - -- AMOUNTTX_Register -- - ----------------------- - subtype AMOUNTTX_AMOUNTTX_Field is nrf51.Byte; -- Number of bytes transmitted in last granted transaction. @@ -437,7 +390,7 @@ package nrf51.SPIS is -- unspecified Reserved_8_31 : nrf51.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for AMOUNTTX_Register use record @@ -445,60 +398,51 @@ package nrf51.SPIS is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- - -- Bit order. - type ORDER_Field is - ( - -- Most significant bit transmitted out first. + type CONFIG_ORDER_Field is + (-- Most significant bit transmitted out first. Msbfirst, -- Least significant bit transmitted out first. Lsbfirst) with Size => 1; - for ORDER_Field use + for CONFIG_ORDER_Field use (Msbfirst => 0, Lsbfirst => 1); -- Serial clock (SCK) phase. - type CPHA_Field is - ( - -- Sample on leading edge of the clock. Shift serial data on trailing - -- edge. + type CONFIG_CPHA_Field is + (-- Sample on leading edge of the clock. Shift serial data on trailing edge. Leading, - -- Sample on trailing edge of the clock. Shift serial data on leading - -- edge. + -- Sample on trailing edge of the clock. Shift serial data on leading edge. Trailing) with Size => 1; - for CPHA_Field use + for CONFIG_CPHA_Field use (Leading => 0, Trailing => 1); -- Serial clock (SCK) polarity. - type CPOL_Field is - ( - -- Active high. + type CONFIG_CPOL_Field is + (-- Active high. Activehigh, -- Active low. Activelow) with Size => 1; - for CPOL_Field use + for CONFIG_CPOL_Field use (Activehigh => 0, Activelow => 1); -- Configuration register. type CONFIG_Register is record -- Bit order. - ORDER : ORDER_Field := Msbfirst; + ORDER : CONFIG_ORDER_Field := nrf51.SPIS.Msbfirst; -- Serial clock (SCK) phase. - CPHA : CPHA_Field := Leading; + CPHA : CONFIG_CPHA_Field := nrf51.SPIS.Leading; -- Serial clock (SCK) polarity. - CPOL : CPOL_Field := Activehigh; + CPOL : CONFIG_CPOL_Field := nrf51.SPIS.Activehigh; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -508,10 +452,6 @@ package nrf51.SPIS is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- DEF_Register -- - ------------------ - subtype DEF_DEF_Field is nrf51.Byte; -- Default character. @@ -521,7 +461,7 @@ package nrf51.SPIS is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DEF_Register use record @@ -529,10 +469,6 @@ package nrf51.SPIS is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- ORC_Register -- - ------------------ - subtype ORC_ORC_Field is nrf51.Byte; -- Over-read character. @@ -542,7 +478,7 @@ package nrf51.SPIS is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ORC_Register use record @@ -550,30 +486,25 @@ package nrf51.SPIS is Reserved_8_31 at 0 range 8 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.SPIS.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -586,90 +517,87 @@ package nrf51.SPIS is ----------------- -- SPI slave 1. - type SPIS1_Peripheral is record + type SPIS_Peripheral is record -- Acquire SPI semaphore. - TASKS_ACQUIRE : nrf51.Word; + TASKS_ACQUIRE : aliased nrf51.UInt32; -- Release SPI semaphore. - TASKS_RELEASE : nrf51.Word; + TASKS_RELEASE : aliased nrf51.UInt32; -- Granted transaction completed. - EVENTS_END : nrf51.Word; - -- End of RXD buffer reached - EVENTS_ENDRX : nrf51.Word; + EVENTS_END : aliased nrf51.UInt32; -- Semaphore acquired. - EVENTS_ACQUIRED : nrf51.Word; + EVENTS_ACQUIRED : aliased nrf51.UInt32; -- Shortcuts for SPIS. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Semaphore status. - SEMSTAT : SEMSTAT_Register; + SEMSTAT : aliased SEMSTAT_Register; -- Status from last transaction. - STATUS : STATUS_Register; + STATUS : aliased STATUS_Register; -- Enable SPIS. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- Pin select for SCK. - PSELSCK : nrf51.Word; + PSELSCK : aliased nrf51.UInt32; -- Pin select for MISO. - PSELMISO : nrf51.Word; + PSELMISO : aliased nrf51.UInt32; -- Pin select for MOSI. - PSELMOSI : nrf51.Word; + PSELMOSI : aliased nrf51.UInt32; -- Pin select for CSN. - PSELCSN : nrf51.Word; + PSELCSN : aliased nrf51.UInt32; -- RX data pointer. - RXDPTR : nrf51.Word; + RXDPTR : aliased nrf51.UInt32; -- Maximum number of bytes in the receive buffer. - MAXRX : MAXRX_Register; + MAXRX : aliased MAXRX_Register; -- Number of bytes received in last granted transaction. - AMOUNTRX : AMOUNTRX_Register; + AMOUNTRX : aliased AMOUNTRX_Register; -- TX data pointer. - TXDPTR : nrf51.Word; + TXDPTR : aliased nrf51.UInt32; -- Maximum number of bytes in the transmit buffer. - MAXTX : MAXTX_Register; + MAXTX : aliased MAXTX_Register; -- Number of bytes transmitted in last granted transaction. - AMOUNTTX : AMOUNTTX_Register; + AMOUNTTX : aliased AMOUNTTX_Register; -- Configuration register. - CONFIG : CONFIG_Register; + CONFIG : aliased CONFIG_Register; -- Default character. - DEF : DEF_Register; + DEF : aliased DEF_Register; -- Over-read character. - ORC : ORC_Register; + ORC : aliased ORC_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; - for SPIS1_Peripheral use record - TASKS_ACQUIRE at 36 range 0 .. 31; - TASKS_RELEASE at 40 range 0 .. 31; - EVENTS_END at 260 range 0 .. 31; - EVENTS_ENDRX at 272 range 0 .. 31; - EVENTS_ACQUIRED at 296 range 0 .. 31; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - SEMSTAT at 1024 range 0 .. 31; - STATUS at 1088 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - PSELSCK at 1288 range 0 .. 31; - PSELMISO at 1292 range 0 .. 31; - PSELMOSI at 1296 range 0 .. 31; - PSELCSN at 1300 range 0 .. 31; - RXDPTR at 1332 range 0 .. 31; - MAXRX at 1336 range 0 .. 31; - AMOUNTRX at 1340 range 0 .. 31; - TXDPTR at 1348 range 0 .. 31; - MAXTX at 1352 range 0 .. 31; - AMOUNTTX at 1356 range 0 .. 31; - CONFIG at 1364 range 0 .. 31; - DEF at 1372 range 0 .. 31; - ORC at 1472 range 0 .. 31; - POWER at 4092 range 0 .. 31; + for SPIS_Peripheral use record + TASKS_ACQUIRE at 16#24# range 0 .. 31; + TASKS_RELEASE at 16#28# range 0 .. 31; + EVENTS_END at 16#104# range 0 .. 31; + EVENTS_ACQUIRED at 16#128# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + SEMSTAT at 16#400# range 0 .. 31; + STATUS at 16#440# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSELSCK at 16#508# range 0 .. 31; + PSELMISO at 16#50C# range 0 .. 31; + PSELMOSI at 16#510# range 0 .. 31; + PSELCSN at 16#514# range 0 .. 31; + RXDPTR at 16#534# range 0 .. 31; + MAXRX at 16#538# range 0 .. 31; + AMOUNTRX at 16#53C# range 0 .. 31; + TXDPTR at 16#544# range 0 .. 31; + MAXTX at 16#548# range 0 .. 31; + AMOUNTTX at 16#54C# range 0 .. 31; + CONFIG at 16#554# range 0 .. 31; + DEF at 16#55C# range 0 .. 31; + ORC at 16#5C0# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- SPI slave 1. - SPIS1_Periph : aliased SPIS1_Peripheral + SPIS1_Periph : aliased SPIS_Peripheral with Import, Address => SPIS1_Base; end nrf51.SPIS; diff --git a/microbit/nrf51/nrf51-swi.ads b/microbit/nrf51/nrf51-swi.ads index b011eb0..4a0b733 100644 --- a/microbit/nrf51/nrf51-swi.ads +++ b/microbit/nrf51/nrf51-swi.ads @@ -1,9 +1,40 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; --- with System; +with System; package nrf51.SWI is pragma Preelaborate; @@ -19,7 +50,7 @@ package nrf51.SWI is -- SW Interrupts. type SWI_Peripheral is record -- Unused. - UNUSED : nrf51.Word; + UNUSED : aliased nrf51.UInt32; end record with Volatile; diff --git a/microbit/nrf51/nrf51-temp.ads b/microbit/nrf51/nrf51-temp.ads index 88d1b1d..59e178c 100644 --- a/microbit/nrf51/nrf51-temp.ads +++ b/microbit/nrf51/nrf51-temp.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,42 +43,37 @@ package nrf51.TEMP is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on DATARDY event. - type DATARDY_Field is - ( - -- Interrupt disabled. + type INTENSET_DATARDY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for DATARDY_Field use + for INTENSET_DATARDY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on DATARDY event. - type DATARDY_Field_1 is - ( - -- Reset value for the field - Datardy_Field_Reset, + type INTENSET_DATARDY_Field_1 is + (-- Reset value for the field + Intenset_Datardy_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for DATARDY_Field_1 use - (Datardy_Field_Reset => 0, + for INTENSET_DATARDY_Field_1 use + (Intenset_Datardy_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on DATARDY event. - DATARDY : DATARDY_Field_1 := Datardy_Field_Reset; + DATARDY : INTENSET_DATARDY_Field_1 := + Intenset_Datardy_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -55,30 +81,37 @@ package nrf51.TEMP is Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on DATARDY event. + type INTENCLR_DATARDY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_DATARDY_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on DATARDY event. - type DATARDY_Field_2 is - ( - -- Reset value for the field - Datardy_Field_Reset, + type INTENCLR_DATARDY_Field_1 is + (-- Reset value for the field + Intenclr_Datardy_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for DATARDY_Field_2 use - (Datardy_Field_Reset => 0, + for INTENCLR_DATARDY_Field_1 use + (Intenclr_Datardy_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on DATARDY event. - DATARDY : DATARDY_Field_2 := Datardy_Field_Reset; + DATARDY : INTENCLR_DATARDY_Field_1 := + Intenclr_Datardy_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -86,30 +119,25 @@ package nrf51.TEMP is Reserved_1_31 at 0 range 1 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.TEMP.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -124,30 +152,30 @@ package nrf51.TEMP is -- Temperature Sensor. type TEMP_Peripheral is record -- Start temperature measurement. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop temperature measurement. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Temperature measurement complete, data ready event. - EVENTS_DATARDY : nrf51.Word; + EVENTS_DATARDY : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Die temperature in degC, 2's complement format, 0.25 degC pecision. - TEMP : nrf51.Word; + TEMP : aliased nrf51.UInt32; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for TEMP_Peripheral use record - TASKS_START at 0 range 0 .. 31; - TASKS_STOP at 4 range 0 .. 31; - EVENTS_DATARDY at 256 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - TEMP at 1288 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + EVENTS_DATARDY at 16#100# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + TEMP at 16#508# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- Temperature Sensor. diff --git a/microbit/nrf51/nrf51-timer.ads b/microbit/nrf51/nrf51-timer.ads index a0aacfc..a95ae69 100644 --- a/microbit/nrf51/nrf51-timer.ads +++ b/microbit/nrf51/nrf51-timer.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -15,137 +46,125 @@ package nrf51.TIMER is -- Capture Timer value to CC[n] registers. -- Capture Timer value to CC[n] registers. - type TASKS_CAPTURE_Registers is array (0 .. 3) of nrf51.Word; + type TASKS_CAPTURE_Registers is array (0 .. 3) of nrf51.UInt32; -- Compare event on CC[n] match. -- Compare event on CC[n] match. - type EVENTS_COMPARE_Registers is array (0 .. 3) of nrf51.Word; - - --------------------- - -- SHORTS_Register -- - --------------------- + type EVENTS_COMPARE_Registers is array (0 .. 3) of nrf51.UInt32; -- Shortcut between CC[0] event and the CLEAR task. - type COMPARE0_CLEAR_Field is - ( - -- Shortcut disabled. + type SHORTS_COMPARE0_CLEAR_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for COMPARE0_CLEAR_Field use + for SHORTS_COMPARE0_CLEAR_Field use (Disabled => 0, Enabled => 1); -- Shortcut between CC[1] event and the CLEAR task. - type COMPARE1_CLEAR_Field is - ( - -- Shortcut disabled. + type SHORTS_COMPARE1_CLEAR_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for COMPARE1_CLEAR_Field use + for SHORTS_COMPARE1_CLEAR_Field use (Disabled => 0, Enabled => 1); -- Shortcut between CC[2] event and the CLEAR task. - type COMPARE2_CLEAR_Field is - ( - -- Shortcut disabled. + type SHORTS_COMPARE2_CLEAR_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for COMPARE2_CLEAR_Field use + for SHORTS_COMPARE2_CLEAR_Field use (Disabled => 0, Enabled => 1); -- Shortcut between CC[3] event and the CLEAR task. - type COMPARE3_CLEAR_Field is - ( - -- Shortcut disabled. + type SHORTS_COMPARE3_CLEAR_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for COMPARE3_CLEAR_Field use + for SHORTS_COMPARE3_CLEAR_Field use (Disabled => 0, Enabled => 1); -- Shortcut between CC[0] event and the STOP task. - type COMPARE0_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_COMPARE0_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for COMPARE0_STOP_Field use + for SHORTS_COMPARE0_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcut between CC[1] event and the STOP task. - type COMPARE1_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_COMPARE1_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for COMPARE1_STOP_Field use + for SHORTS_COMPARE1_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcut between CC[2] event and the STOP task. - type COMPARE2_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_COMPARE2_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for COMPARE2_STOP_Field use + for SHORTS_COMPARE2_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcut between CC[3] event and the STOP task. - type COMPARE3_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_COMPARE3_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for COMPARE3_STOP_Field use + for SHORTS_COMPARE3_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcuts for Timer. type SHORTS_Register is record -- Shortcut between CC[0] event and the CLEAR task. - COMPARE0_CLEAR : COMPARE0_CLEAR_Field := Disabled; + COMPARE0_CLEAR : SHORTS_COMPARE0_CLEAR_Field := nrf51.TIMER.Disabled; -- Shortcut between CC[1] event and the CLEAR task. - COMPARE1_CLEAR : COMPARE1_CLEAR_Field := Disabled; + COMPARE1_CLEAR : SHORTS_COMPARE1_CLEAR_Field := nrf51.TIMER.Disabled; -- Shortcut between CC[2] event and the CLEAR task. - COMPARE2_CLEAR : COMPARE2_CLEAR_Field := Disabled; + COMPARE2_CLEAR : SHORTS_COMPARE2_CLEAR_Field := nrf51.TIMER.Disabled; -- Shortcut between CC[3] event and the CLEAR task. - COMPARE3_CLEAR : COMPARE3_CLEAR_Field := Disabled; + COMPARE3_CLEAR : SHORTS_COMPARE3_CLEAR_Field := nrf51.TIMER.Disabled; -- unspecified Reserved_4_7 : nrf51.UInt4 := 16#0#; -- Shortcut between CC[0] event and the STOP task. - COMPARE0_STOP : COMPARE0_STOP_Field := Disabled; + COMPARE0_STOP : SHORTS_COMPARE0_STOP_Field := nrf51.TIMER.Disabled; -- Shortcut between CC[1] event and the STOP task. - COMPARE1_STOP : COMPARE1_STOP_Field := Disabled; + COMPARE1_STOP : SHORTS_COMPARE1_STOP_Field := nrf51.TIMER.Disabled; -- Shortcut between CC[2] event and the STOP task. - COMPARE2_STOP : COMPARE2_STOP_Field := Disabled; + COMPARE2_STOP : SHORTS_COMPARE2_STOP_Field := nrf51.TIMER.Disabled; -- Shortcut between CC[3] event and the STOP task. - COMPARE3_STOP : COMPARE3_STOP_Field := Disabled; + COMPARE3_STOP : SHORTS_COMPARE3_STOP_Field := nrf51.TIMER.Disabled; -- unspecified Reserved_12_31 : nrf51.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -161,40 +180,31 @@ package nrf51.TIMER is Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on COMPARE[0] - type COMPARE0_Field is - ( - -- Interrupt disabled. + type INTENSET_COMPARE0_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for COMPARE0_Field use + for INTENSET_COMPARE0_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on COMPARE[0] - type COMPARE0_Field_1 is - ( - -- Reset value for the field - Compare0_Field_Reset, + type INTENSET_COMPARE0_Field_1 is + (-- Reset value for the field + Intenset_Compare0_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for COMPARE0_Field_1 use - (Compare0_Field_Reset => 0, + for INTENSET_COMPARE0_Field_1 use + (Intenset_Compare0_Field_Reset => 0, Set => 1); - ---------------------- - -- INTENSET.COMPARE -- - ---------------------- - -- INTENSET_COMPARE array - type INTENSET_COMPARE_Field_Array is array (0 .. 3) of COMPARE0_Field_1 + type INTENSET_COMPARE_Field_Array is array (0 .. 3) + of INTENSET_COMPARE0_Field_1 with Component_Size => 1, Size => 4; -- Type definition for INTENSET_COMPARE @@ -220,14 +230,14 @@ package nrf51.TIMER is -- Interrupt enable set register. type INTENSET_Register is record -- unspecified - Reserved_0_15 : nrf51.Short := 16#0#; + Reserved_0_15 : nrf51.UInt16 := 16#0#; -- Enable interrupt on COMPARE[0] COMPARE : INTENSET_COMPARE_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -236,28 +246,31 @@ package nrf51.TIMER is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on COMPARE[0] + type INTENCLR_COMPARE0_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on COMPARE[0] - type COMPARE0_Field_2 is - ( - -- Reset value for the field - Compare0_Field_Reset, + type INTENCLR_COMPARE0_Field_1 is + (-- Reset value for the field + Intenclr_Compare0_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for COMPARE0_Field_2 use - (Compare0_Field_Reset => 0, + for INTENCLR_COMPARE0_Field_1 use + (Intenclr_Compare0_Field_Reset => 0, Clear => 1); - ---------------------- - -- INTENCLR.COMPARE -- - ---------------------- - -- INTENCLR_COMPARE array - type INTENCLR_COMPARE_Field_Array is array (0 .. 3) of COMPARE0_Field_2 + type INTENCLR_COMPARE_Field_Array is array (0 .. 3) + of INTENCLR_COMPARE0_Field_1 with Component_Size => 1, Size => 4; -- Type definition for INTENCLR_COMPARE @@ -283,14 +296,14 @@ package nrf51.TIMER is -- Interrupt enable clear register. type INTENCLR_Register is record -- unspecified - Reserved_0_15 : nrf51.Short := 16#0#; + Reserved_0_15 : nrf51.UInt16 := 16#0#; -- Disable interrupt on COMPARE[0] COMPARE : INTENCLR_COMPARE_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_20_31 : nrf51.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -299,30 +312,25 @@ package nrf51.TIMER is Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------- - -- MODE_Register -- - ------------------- - -- Select Normal or Counter mode. - type MODE_Field is - ( - -- Timer in Normal mode. + type MODE_MODE_Field is + (-- Timer in Normal mode. Timer, -- Timer in Counter mode. Counter) with Size => 1; - for MODE_Field use + for MODE_MODE_Field use (Timer => 0, Counter => 1); -- Timer Mode selection. type MODE_Register is record -- Select Normal or Counter mode. - MODE : MODE_Field := Timer; + MODE : MODE_MODE_Field := nrf51.TIMER.Timer; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MODE_Register use record @@ -330,38 +338,33 @@ package nrf51.TIMER is Reserved_1_31 at 0 range 1 .. 31; end record; - ---------------------- - -- BITMODE_Register -- - ---------------------- - -- Sets timer behaviour ro be like the implementation of a timer with width -- as indicated. - type BITMODE_Field is - ( - -- 16-bit timer behaviour. - BITMODE_Field_16Bit, + type BITMODE_BITMODE_Field is + (-- 16-bit timer behaviour. + Val_16Bit, -- 8-bit timer behaviour. - BITMODE_Field_08Bit, + Val_08Bit, -- 24-bit timer behaviour. - BITMODE_Field_24Bit, + Val_24Bit, -- 32-bit timer behaviour. - BITMODE_Field_32Bit) + Val_32Bit) with Size => 2; - for BITMODE_Field use - (BITMODE_Field_16Bit => 0, - BITMODE_Field_08Bit => 1, - BITMODE_Field_24Bit => 2, - BITMODE_Field_32Bit => 3); + for BITMODE_BITMODE_Field use + (Val_16Bit => 0, + Val_08Bit => 1, + Val_24Bit => 2, + Val_32Bit => 3); -- Sets timer behaviour. type BITMODE_Register is record -- Sets timer behaviour ro be like the implementation of a timer with -- width as indicated. - BITMODE : BITMODE_Field := BITMODE_Field_16Bit; + BITMODE : BITMODE_BITMODE_Field := nrf51.TIMER.Val_16Bit; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for BITMODE_Register use record @@ -369,10 +372,6 @@ package nrf51.TIMER is Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------------ - -- PRESCALER_Register -- - ------------------------ - subtype PRESCALER_PRESCALER_Field is nrf51.UInt4; -- 4-bit prescaler to source clock frequency (max value 9). Source clock @@ -383,7 +382,7 @@ package nrf51.TIMER is -- unspecified Reserved_4_31 : nrf51.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PRESCALER_Register use record @@ -394,32 +393,27 @@ package nrf51.TIMER is -- Capture/compare registers. -- Capture/compare registers. - type CC_Registers is array (0 .. 3) of nrf51.Word; - - -------------------- - -- POWER_Register -- - -------------------- + type CC_Registers is array (0 .. 3) of nrf51.UInt32; -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.TIMER.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -434,55 +428,55 @@ package nrf51.TIMER is -- Timer 0. type TIMER_Peripheral is record -- Start Timer. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Stop Timer. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Increment Timer (In counter mode). - TASKS_COUNT : nrf51.Word; + TASKS_COUNT : aliased nrf51.UInt32; -- Clear timer. - TASKS_CLEAR : nrf51.Word; + TASKS_CLEAR : aliased nrf51.UInt32; -- Shutdown timer. - TASKS_SHUTDOWN : nrf51.Word; + TASKS_SHUTDOWN : aliased nrf51.UInt32; -- Capture Timer value to CC[n] registers. - TASKS_CAPTURE : TASKS_CAPTURE_Registers; + TASKS_CAPTURE : aliased TASKS_CAPTURE_Registers; -- Compare event on CC[n] match. - EVENTS_COMPARE : EVENTS_COMPARE_Registers; + EVENTS_COMPARE : aliased EVENTS_COMPARE_Registers; -- Shortcuts for Timer. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Timer Mode selection. - MODE : MODE_Register; + MODE : aliased MODE_Register; -- Sets timer behaviour. - BITMODE : BITMODE_Register; + BITMODE : aliased BITMODE_Register; -- 4-bit prescaler to source clock frequency (max value 9). Source clock -- frequency is divided by 2^SCALE. - PRESCALER : PRESCALER_Register; + PRESCALER : aliased PRESCALER_Register; -- Capture/compare registers. - CC : CC_Registers; + CC : aliased CC_Registers; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for TIMER_Peripheral use record - TASKS_START at 0 range 0 .. 31; - TASKS_STOP at 4 range 0 .. 31; - TASKS_COUNT at 8 range 0 .. 31; - TASKS_CLEAR at 12 range 0 .. 31; - TASKS_SHUTDOWN at 16 range 0 .. 31; - TASKS_CAPTURE at 64 range 0 .. 127; - EVENTS_COMPARE at 320 range 0 .. 127; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - MODE at 1284 range 0 .. 31; - BITMODE at 1288 range 0 .. 31; - PRESCALER at 1296 range 0 .. 31; - CC at 1344 range 0 .. 127; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_COUNT at 16#8# range 0 .. 31; + TASKS_CLEAR at 16#C# range 0 .. 31; + TASKS_SHUTDOWN at 16#10# range 0 .. 31; + TASKS_CAPTURE at 16#40# range 0 .. 127; + EVENTS_COMPARE at 16#140# range 0 .. 127; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + MODE at 16#504# range 0 .. 31; + BITMODE at 16#508# range 0 .. 31; + PRESCALER at 16#510# range 0 .. 31; + CC at 16#540# range 0 .. 127; + POWER at 16#FFC# range 0 .. 31; end record; -- Timer 0. diff --git a/microbit/nrf51/nrf51-twi.ads b/microbit/nrf51/nrf51-twi.ads index d2e2699..3701afb 100644 --- a/microbit/nrf51/nrf51-twi.ads +++ b/microbit/nrf51/nrf51-twi.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,44 +43,38 @@ package nrf51.TWI is -- Registers -- --------------- - --------------------- - -- SHORTS_Register -- - --------------------- - -- Shortcut between BB event and the SUSPEND task. - type BB_SUSPEND_Field is - ( - -- Shortcut disabled. + type SHORTS_BB_SUSPEND_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for BB_SUSPEND_Field use + for SHORTS_BB_SUSPEND_Field use (Disabled => 0, Enabled => 1); -- Shortcut between BB event and the STOP task. - type BB_STOP_Field is - ( - -- Shortcut disabled. + type SHORTS_BB_STOP_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for BB_STOP_Field use + for SHORTS_BB_STOP_Field use (Disabled => 0, Enabled => 1); -- Shortcuts for TWI. type SHORTS_Register is record -- Shortcut between BB event and the SUSPEND task. - BB_SUSPEND : BB_SUSPEND_Field := Disabled; + BB_SUSPEND : SHORTS_BB_SUSPEND_Field := nrf51.TWI.Disabled; -- Shortcut between BB event and the STOP task. - BB_STOP : BB_STOP_Field := Disabled; + BB_STOP : SHORTS_BB_STOP_Field := nrf51.TWI.Disabled; -- unspecified Reserved_2_31 : nrf51.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -58,152 +83,136 @@ package nrf51.TWI is Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on STOPPED event. - type STOPPED_Field is - ( - -- Interrupt disabled. + type INTENSET_STOPPED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for STOPPED_Field use + for INTENSET_STOPPED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on STOPPED event. - type STOPPED_Field_1 is - ( - -- Reset value for the field - Stopped_Field_Reset, + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for STOPPED_Field_1 use - (Stopped_Field_Reset => 0, + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, Set => 1); -- Enable interrupt on READY event. - type RXDREADY_Field is - ( - -- Interrupt disabled. + type INTENSET_RXDREADY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for RXDREADY_Field use + for INTENSET_RXDREADY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on READY event. - type RXDREADY_Field_1 is - ( - -- Reset value for the field - Rxdready_Field_Reset, + type INTENSET_RXDREADY_Field_1 is + (-- Reset value for the field + Intenset_Rxdready_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for RXDREADY_Field_1 use - (Rxdready_Field_Reset => 0, + for INTENSET_RXDREADY_Field_1 use + (Intenset_Rxdready_Field_Reset => 0, Set => 1); -- Enable interrupt on TXDSENT event. - type TXDSENT_Field is - ( - -- Interrupt disabled. + type INTENSET_TXDSENT_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for TXDSENT_Field use + for INTENSET_TXDSENT_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on TXDSENT event. - type TXDSENT_Field_1 is - ( - -- Reset value for the field - Txdsent_Field_Reset, + type INTENSET_TXDSENT_Field_1 is + (-- Reset value for the field + Intenset_Txdsent_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for TXDSENT_Field_1 use - (Txdsent_Field_Reset => 0, + for INTENSET_TXDSENT_Field_1 use + (Intenset_Txdsent_Field_Reset => 0, Set => 1); -- Enable interrupt on ERROR event. - type ERROR_Field is - ( - -- Interrupt disabled. + type INTENSET_ERROR_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ERROR_Field use + for INTENSET_ERROR_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ERROR event. - type ERROR_Field_1 is - ( - -- Reset value for the field - Error_Field_Reset, + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ERROR_Field_1 use - (Error_Field_Reset => 0, + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, Set => 1); -- Enable interrupt on BB event. - type BB_Field is - ( - -- Interrupt disabled. + type INTENSET_BB_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for BB_Field use + for INTENSET_BB_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on BB event. - type BB_Field_1 is - ( - -- Reset value for the field - Bb_Field_Reset, + type INTENSET_BB_Field_1 is + (-- Reset value for the field + Intenset_Bb_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for BB_Field_1 use - (Bb_Field_Reset => 0, + for INTENSET_BB_Field_1 use + (Intenset_Bb_Field_Reset => 0, Set => 1); -- Enable interrupt on SUSPENDED event. - type SUSPENDED_Field is - ( - -- Interrupt disabled. + type INTENSET_SUSPENDED_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for SUSPENDED_Field use + for INTENSET_SUSPENDED_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on SUSPENDED event. - type SUSPENDED_Field_1 is - ( - -- Reset value for the field - Suspended_Field_Reset, + type INTENSET_SUSPENDED_Field_1 is + (-- Reset value for the field + Intenset_Suspended_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for SUSPENDED_Field_1 use - (Suspended_Field_Reset => 0, + for INTENSET_SUSPENDED_Field_1 use + (Intenset_Suspended_Field_Reset => 0, Set => 1); -- Interrupt enable set register. @@ -211,29 +220,33 @@ package nrf51.TWI is -- unspecified Reserved_0_0 : nrf51.Bit := 16#0#; -- Enable interrupt on STOPPED event. - STOPPED : STOPPED_Field_1 := Stopped_Field_Reset; + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; -- Enable interrupt on READY event. - RXDREADY : RXDREADY_Field_1 := Rxdready_Field_Reset; + RXDREADY : INTENSET_RXDREADY_Field_1 := + Intenset_Rxdready_Field_Reset; -- unspecified Reserved_3_6 : nrf51.UInt4 := 16#0#; -- Enable interrupt on TXDSENT event. - TXDSENT : TXDSENT_Field_1 := Txdsent_Field_Reset; + TXDSENT : INTENSET_TXDSENT_Field_1 := + Intenset_Txdsent_Field_Reset; -- unspecified Reserved_8_8 : nrf51.Bit := 16#0#; -- Enable interrupt on ERROR event. - ERROR : ERROR_Field_1 := Error_Field_Reset; + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; -- unspecified Reserved_10_13 : nrf51.UInt4 := 16#0#; -- Enable interrupt on BB event. - BB : BB_Field_1 := Bb_Field_Reset; + BB : INTENSET_BB_Field_1 := Intenset_Bb_Field_Reset; -- unspecified Reserved_15_17 : nrf51.UInt3 := 16#0#; -- Enable interrupt on SUSPENDED event. - SUSPENDED : SUSPENDED_Field_1 := Suspended_Field_Reset; + SUSPENDED : INTENSET_SUSPENDED_Field_1 := + Intenset_Suspended_Field_Reset; -- unspecified Reserved_19_31 : nrf51.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -251,80 +264,136 @@ package nrf51.TWI is Reserved_19_31 at 0 range 19 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on STOPPED event. + type INTENCLR_STOPPED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on STOPPED event. - type STOPPED_Field_2 is - ( - -- Reset value for the field - Stopped_Field_Reset, + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for STOPPED_Field_2 use - (Stopped_Field_Reset => 0, + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, Clear => 1); -- Disable interrupt on RXDREADY event. - type RXDREADY_Field_2 is - ( - -- Reset value for the field - Rxdready_Field_Reset, + type INTENCLR_RXDREADY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_RXDREADY_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on RXDREADY event. + type INTENCLR_RXDREADY_Field_1 is + (-- Reset value for the field + Intenclr_Rxdready_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for RXDREADY_Field_2 use - (Rxdready_Field_Reset => 0, + for INTENCLR_RXDREADY_Field_1 use + (Intenclr_Rxdready_Field_Reset => 0, Clear => 1); -- Disable interrupt on TXDSENT event. - type TXDSENT_Field_2 is - ( - -- Reset value for the field - Txdsent_Field_Reset, + type INTENCLR_TXDSENT_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_TXDSENT_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on TXDSENT event. + type INTENCLR_TXDSENT_Field_1 is + (-- Reset value for the field + Intenclr_Txdsent_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for TXDSENT_Field_2 use - (Txdsent_Field_Reset => 0, + for INTENCLR_TXDSENT_Field_1 use + (Intenclr_Txdsent_Field_Reset => 0, Clear => 1); -- Disable interrupt on ERROR event. - type ERROR_Field_2 is - ( - -- Reset value for the field - Error_Field_Reset, + type INTENCLR_ERROR_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ERROR event. + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ERROR_Field_2 use - (Error_Field_Reset => 0, + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, Clear => 1); -- Disable interrupt on BB event. - type BB_Field_2 is - ( - -- Reset value for the field - Bb_Field_Reset, + type INTENCLR_BB_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_BB_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on BB event. + type INTENCLR_BB_Field_1 is + (-- Reset value for the field + Intenclr_Bb_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for BB_Field_2 use - (Bb_Field_Reset => 0, + for INTENCLR_BB_Field_1 use + (Intenclr_Bb_Field_Reset => 0, Clear => 1); -- Disable interrupt on SUSPENDED event. - type SUSPENDED_Field_2 is - ( - -- Reset value for the field - Suspended_Field_Reset, + type INTENCLR_SUSPENDED_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_SUSPENDED_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on SUSPENDED event. + type INTENCLR_SUSPENDED_Field_1 is + (-- Reset value for the field + Intenclr_Suspended_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for SUSPENDED_Field_2 use - (Suspended_Field_Reset => 0, + for INTENCLR_SUSPENDED_Field_1 use + (Intenclr_Suspended_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. @@ -332,29 +401,33 @@ package nrf51.TWI is -- unspecified Reserved_0_0 : nrf51.Bit := 16#0#; -- Disable interrupt on STOPPED event. - STOPPED : STOPPED_Field_2 := Stopped_Field_Reset; + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; -- Disable interrupt on RXDREADY event. - RXDREADY : RXDREADY_Field_2 := Rxdready_Field_Reset; + RXDREADY : INTENCLR_RXDREADY_Field_1 := + Intenclr_Rxdready_Field_Reset; -- unspecified Reserved_3_6 : nrf51.UInt4 := 16#0#; -- Disable interrupt on TXDSENT event. - TXDSENT : TXDSENT_Field_2 := Txdsent_Field_Reset; + TXDSENT : INTENCLR_TXDSENT_Field_1 := + Intenclr_Txdsent_Field_Reset; -- unspecified Reserved_8_8 : nrf51.Bit := 16#0#; -- Disable interrupt on ERROR event. - ERROR : ERROR_Field_2 := Error_Field_Reset; + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; -- unspecified Reserved_10_13 : nrf51.UInt4 := 16#0#; -- Disable interrupt on BB event. - BB : BB_Field_2 := Bb_Field_Reset; + BB : INTENCLR_BB_Field_1 := Intenclr_Bb_Field_Reset; -- unspecified Reserved_15_17 : nrf51.UInt3 := 16#0#; -- Disable interrupt on SUSPENDED event. - SUSPENDED : SUSPENDED_Field_2 := Suspended_Field_Reset; + SUSPENDED : INTENCLR_SUSPENDED_Field_1 := + Intenclr_Suspended_Field_Reset; -- unspecified Reserved_19_31 : nrf51.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -372,97 +445,88 @@ package nrf51.TWI is Reserved_19_31 at 0 range 19 .. 31; end record; - ----------------------- - -- ERRORSRC_Register -- - ----------------------- - -- Byte received in RXD register before read of the last received byte -- (data loss). - type OVERRUN_Field is - ( - -- Error not present. + type ERRORSRC_OVERRUN_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for OVERRUN_Field use + for ERRORSRC_OVERRUN_Field use (Notpresent => 0, Present => 1); -- Byte received in RXD register before read of the last received byte -- (data loss). - type OVERRUN_Field_1 is - ( - -- Reset value for the field - Overrun_Field_Reset, + type ERRORSRC_OVERRUN_Field_1 is + (-- Reset value for the field + Errorsrc_Overrun_Field_Reset, -- Clear error on write. Clear) with Size => 1; - for OVERRUN_Field_1 use - (Overrun_Field_Reset => 0, + for ERRORSRC_OVERRUN_Field_1 use + (Errorsrc_Overrun_Field_Reset => 0, Clear => 1); -- NACK received after sending the address. - type ANACK_Field is - ( - -- Error not present. + type ERRORSRC_ANACK_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for ANACK_Field use + for ERRORSRC_ANACK_Field use (Notpresent => 0, Present => 1); -- NACK received after sending the address. - type ANACK_Field_1 is - ( - -- Reset value for the field - Anack_Field_Reset, + type ERRORSRC_ANACK_Field_1 is + (-- Reset value for the field + Errorsrc_Anack_Field_Reset, -- Clear error on write. Clear) with Size => 1; - for ANACK_Field_1 use - (Anack_Field_Reset => 0, + for ERRORSRC_ANACK_Field_1 use + (Errorsrc_Anack_Field_Reset => 0, Clear => 1); -- NACK received after sending a data byte. - type DNACK_Field is - ( - -- Error not present. + type ERRORSRC_DNACK_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for DNACK_Field use + for ERRORSRC_DNACK_Field use (Notpresent => 0, Present => 1); -- NACK received after sending a data byte. - type DNACK_Field_1 is - ( - -- Reset value for the field - Dnack_Field_Reset, + type ERRORSRC_DNACK_Field_1 is + (-- Reset value for the field + Errorsrc_Dnack_Field_Reset, -- Clear error on write. Clear) with Size => 1; - for DNACK_Field_1 use - (Dnack_Field_Reset => 0, + for ERRORSRC_DNACK_Field_1 use + (Errorsrc_Dnack_Field_Reset => 0, Clear => 1); -- Two-wire error source. Write error field to 1 to clear error. type ERRORSRC_Register is record -- Byte received in RXD register before read of the last received byte -- (data loss). - OVERRUN : OVERRUN_Field_1 := Overrun_Field_Reset; + OVERRUN : ERRORSRC_OVERRUN_Field_1 := + Errorsrc_Overrun_Field_Reset; -- NACK received after sending the address. - ANACK : ANACK_Field_1 := Anack_Field_Reset; + ANACK : ERRORSRC_ANACK_Field_1 := Errorsrc_Anack_Field_Reset; -- NACK received after sending a data byte. - DNACK : DNACK_Field_1 := Dnack_Field_Reset; + DNACK : ERRORSRC_DNACK_Field_1 := Errorsrc_Dnack_Field_Reset; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ERRORSRC_Register use record @@ -472,30 +536,25 @@ package nrf51.TWI is Reserved_3_31 at 0 range 3 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- Enable or disable W2M - type ENABLE_Field is - ( - -- Disabled. + type ENABLE_ENABLE_Field is + (-- Disabled. Disabled, -- Enabled. Enabled) with Size => 3; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 5); -- Enable two-wire master. type ENABLE_Register is record -- Enable or disable W2M - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.TWI.Disabled; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -503,10 +562,6 @@ package nrf51.TWI is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- RXD_Register -- - ------------------ - subtype RXD_RXD_Field is nrf51.Byte; -- RX data register. @@ -517,7 +572,7 @@ package nrf51.TWI is -- unspecified Reserved_8_31 : nrf51.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXD_Register use record @@ -525,10 +580,6 @@ package nrf51.TWI is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- TXD_Register -- - ------------------ - subtype TXD_TXD_Field is nrf51.Byte; -- TX data register. @@ -538,7 +589,7 @@ package nrf51.TWI is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXD_Register use record @@ -546,10 +597,6 @@ package nrf51.TWI is Reserved_8_31 at 0 range 8 .. 31; end record; - ---------------------- - -- ADDRESS_Register -- - ---------------------- - subtype ADDRESS_ADDRESS_Field is nrf51.UInt7; -- Address used in the two-wire transfer. @@ -559,7 +606,7 @@ package nrf51.TWI is -- unspecified Reserved_7_31 : nrf51.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ADDRESS_Register use record @@ -567,30 +614,25 @@ package nrf51.TWI is Reserved_7_31 at 0 range 7 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.TWI.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -605,78 +647,78 @@ package nrf51.TWI is -- Two-wire interface master 0. type TWI_Peripheral is record -- Start 2-Wire master receive sequence. - TASKS_STARTRX : nrf51.Word; + TASKS_STARTRX : aliased nrf51.UInt32; -- Start 2-Wire master transmit sequence. - TASKS_STARTTX : nrf51.Word; + TASKS_STARTTX : aliased nrf51.UInt32; -- Stop 2-Wire transaction. - TASKS_STOP : nrf51.Word; + TASKS_STOP : aliased nrf51.UInt32; -- Suspend 2-Wire transaction. - TASKS_SUSPEND : nrf51.Word; + TASKS_SUSPEND : aliased nrf51.UInt32; -- Resume 2-Wire transaction. - TASKS_RESUME : nrf51.Word; + TASKS_RESUME : aliased nrf51.UInt32; -- Two-wire stopped. - EVENTS_STOPPED : nrf51.Word; + EVENTS_STOPPED : aliased nrf51.UInt32; -- Two-wire ready to deliver new RXD byte received. - EVENTS_RXDREADY : nrf51.Word; + EVENTS_RXDREADY : aliased nrf51.UInt32; -- Two-wire finished sending last TXD byte. - EVENTS_TXDSENT : nrf51.Word; + EVENTS_TXDSENT : aliased nrf51.UInt32; -- Two-wire error detected. - EVENTS_ERROR : nrf51.Word; + EVENTS_ERROR : aliased nrf51.UInt32; -- Two-wire byte boundary. - EVENTS_BB : nrf51.Word; + EVENTS_BB : aliased nrf51.UInt32; -- Two-wire suspended. - EVENTS_SUSPENDED : nrf51.Word; + EVENTS_SUSPENDED : aliased nrf51.UInt32; -- Shortcuts for TWI. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Two-wire error source. Write error field to 1 to clear error. - ERRORSRC : ERRORSRC_Register; + ERRORSRC : aliased ERRORSRC_Register; -- Enable two-wire master. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- Pin select for SCL. - PSELSCL : nrf51.Word; + PSELSCL : aliased nrf51.UInt32; -- Pin select for SDA. - PSELSDA : nrf51.Word; + PSELSDA : aliased nrf51.UInt32; -- RX data register. - RXD : RXD_Register; + RXD : aliased RXD_Register; -- TX data register. - TXD : TXD_Register; + TXD : aliased TXD_Register; -- Two-wire frequency. - FREQUENCY : nrf51.Word; + FREQUENCY : aliased nrf51.UInt32; -- Address used in the two-wire transfer. - ADDRESS : ADDRESS_Register; + ADDRESS : aliased ADDRESS_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for TWI_Peripheral use record - TASKS_STARTRX at 0 range 0 .. 31; - TASKS_STARTTX at 8 range 0 .. 31; - TASKS_STOP at 20 range 0 .. 31; - TASKS_SUSPEND at 28 range 0 .. 31; - TASKS_RESUME at 32 range 0 .. 31; - EVENTS_STOPPED at 260 range 0 .. 31; - EVENTS_RXDREADY at 264 range 0 .. 31; - EVENTS_TXDSENT at 284 range 0 .. 31; - EVENTS_ERROR at 292 range 0 .. 31; - EVENTS_BB at 312 range 0 .. 31; - EVENTS_SUSPENDED at 328 range 0 .. 31; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - ERRORSRC at 1220 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - PSELSCL at 1288 range 0 .. 31; - PSELSDA at 1292 range 0 .. 31; - RXD at 1304 range 0 .. 31; - TXD at 1308 range 0 .. 31; - FREQUENCY at 1316 range 0 .. 31; - ADDRESS at 1416 range 0 .. 31; - POWER at 4092 range 0 .. 31; + TASKS_STARTRX at 16#0# range 0 .. 31; + TASKS_STARTTX at 16#8# range 0 .. 31; + TASKS_STOP at 16#14# range 0 .. 31; + TASKS_SUSPEND at 16#1C# range 0 .. 31; + TASKS_RESUME at 16#20# range 0 .. 31; + EVENTS_STOPPED at 16#104# range 0 .. 31; + EVENTS_RXDREADY at 16#108# range 0 .. 31; + EVENTS_TXDSENT at 16#11C# range 0 .. 31; + EVENTS_ERROR at 16#124# range 0 .. 31; + EVENTS_BB at 16#138# range 0 .. 31; + EVENTS_SUSPENDED at 16#148# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ERRORSRC at 16#4C4# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSELSCL at 16#508# range 0 .. 31; + PSELSDA at 16#50C# range 0 .. 31; + RXD at 16#518# range 0 .. 31; + TXD at 16#51C# range 0 .. 31; + FREQUENCY at 16#524# range 0 .. 31; + ADDRESS at 16#588# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- Two-wire interface master 0. diff --git a/microbit/nrf51/nrf51-uart.ads b/microbit/nrf51/nrf51-uart.ads index ef2d9ca..f91f3c1 100644 --- a/microbit/nrf51/nrf51-uart.ads +++ b/microbit/nrf51/nrf51-uart.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,31 +43,25 @@ package nrf51.UART is -- Registers -- --------------- - --------------------- - -- SHORTS_Register -- - --------------------- - -- Shortcut between CTS event and STARTRX task. - type CTS_STARTRX_Field is - ( - -- Shortcut disabled. + type SHORTS_CTS_STARTRX_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for CTS_STARTRX_Field use + for SHORTS_CTS_STARTRX_Field use (Disabled => 0, Enabled => 1); -- Shortcut between NCTS event and STOPRX task. - type NCTS_STOPRX_Field is - ( - -- Shortcut disabled. + type SHORTS_NCTS_STOPRX_Field is + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) with Size => 1; - for NCTS_STOPRX_Field use + for SHORTS_NCTS_STOPRX_Field use (Disabled => 0, Enabled => 1); @@ -45,13 +70,13 @@ package nrf51.UART is -- unspecified Reserved_0_2 : nrf51.UInt3 := 16#0#; -- Shortcut between CTS event and STARTRX task. - CTS_STARTRX : CTS_STARTRX_Field := Disabled; + CTS_STARTRX : SHORTS_CTS_STARTRX_Field := nrf51.UART.Disabled; -- Shortcut between NCTS event and STOPRX task. - NCTS_STOPRX : NCTS_STOPRX_Field := Disabled; + NCTS_STOPRX : SHORTS_NCTS_STOPRX_Field := nrf51.UART.Disabled; -- unspecified Reserved_5_31 : nrf51.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -61,178 +86,162 @@ package nrf51.UART is Reserved_5_31 at 0 range 5 .. 31; end record; - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on CTS event. - type CTS_Field is - ( - -- Interrupt disabled. + type INTENSET_CTS_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for CTS_Field use + for INTENSET_CTS_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on CTS event. - type CTS_Field_1 is - ( - -- Reset value for the field - Cts_Field_Reset, + type INTENSET_CTS_Field_1 is + (-- Reset value for the field + Intenset_Cts_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for CTS_Field_1 use - (Cts_Field_Reset => 0, + for INTENSET_CTS_Field_1 use + (Intenset_Cts_Field_Reset => 0, Set => 1); -- Enable interrupt on NCTS event. - type NCTS_Field is - ( - -- Interrupt disabled. + type INTENSET_NCTS_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for NCTS_Field use + for INTENSET_NCTS_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on NCTS event. - type NCTS_Field_1 is - ( - -- Reset value for the field - Ncts_Field_Reset, + type INTENSET_NCTS_Field_1 is + (-- Reset value for the field + Intenset_Ncts_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for NCTS_Field_1 use - (Ncts_Field_Reset => 0, + for INTENSET_NCTS_Field_1 use + (Intenset_Ncts_Field_Reset => 0, Set => 1); -- Enable interrupt on RXRDY event. - type RXDRDY_Field is - ( - -- Interrupt disabled. + type INTENSET_RXDRDY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for RXDRDY_Field use + for INTENSET_RXDRDY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on RXRDY event. - type RXDRDY_Field_1 is - ( - -- Reset value for the field - Rxdrdy_Field_Reset, + type INTENSET_RXDRDY_Field_1 is + (-- Reset value for the field + Intenset_Rxdrdy_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for RXDRDY_Field_1 use - (Rxdrdy_Field_Reset => 0, + for INTENSET_RXDRDY_Field_1 use + (Intenset_Rxdrdy_Field_Reset => 0, Set => 1); -- Enable interrupt on TXRDY event. - type TXDRDY_Field is - ( - -- Interrupt disabled. + type INTENSET_TXDRDY_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for TXDRDY_Field use + for INTENSET_TXDRDY_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on TXRDY event. - type TXDRDY_Field_1 is - ( - -- Reset value for the field - Txdrdy_Field_Reset, + type INTENSET_TXDRDY_Field_1 is + (-- Reset value for the field + Intenset_Txdrdy_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for TXDRDY_Field_1 use - (Txdrdy_Field_Reset => 0, + for INTENSET_TXDRDY_Field_1 use + (Intenset_Txdrdy_Field_Reset => 0, Set => 1); -- Enable interrupt on ERROR event. - type ERROR_Field is - ( - -- Interrupt disabled. + type INTENSET_ERROR_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for ERROR_Field use + for INTENSET_ERROR_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on ERROR event. - type ERROR_Field_1 is - ( - -- Reset value for the field - Error_Field_Reset, + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for ERROR_Field_1 use - (Error_Field_Reset => 0, + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, Set => 1); -- Enable interrupt on RXTO event. - type RXTO_Field is - ( - -- Interrupt disabled. + type INTENSET_RXTO_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for RXTO_Field use + for INTENSET_RXTO_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on RXTO event. - type RXTO_Field_1 is - ( - -- Reset value for the field - Rxto_Field_Reset, + type INTENSET_RXTO_Field_1 is + (-- Reset value for the field + Intenset_Rxto_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for RXTO_Field_1 use - (Rxto_Field_Reset => 0, + for INTENSET_RXTO_Field_1 use + (Intenset_Rxto_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on CTS event. - CTS : CTS_Field_1 := Cts_Field_Reset; + CTS : INTENSET_CTS_Field_1 := Intenset_Cts_Field_Reset; -- Enable interrupt on NCTS event. - NCTS : NCTS_Field_1 := Ncts_Field_Reset; + NCTS : INTENSET_NCTS_Field_1 := Intenset_Ncts_Field_Reset; -- Enable interrupt on RXRDY event. - RXDRDY : RXDRDY_Field_1 := Rxdrdy_Field_Reset; + RXDRDY : INTENSET_RXDRDY_Field_1 := Intenset_Rxdrdy_Field_Reset; -- unspecified Reserved_3_6 : nrf51.UInt4 := 16#0#; -- Enable interrupt on TXRDY event. - TXDRDY : TXDRDY_Field_1 := Txdrdy_Field_Reset; + TXDRDY : INTENSET_TXDRDY_Field_1 := Intenset_Txdrdy_Field_Reset; -- unspecified Reserved_8_8 : nrf51.Bit := 16#0#; -- Enable interrupt on ERROR event. - ERROR : ERROR_Field_1 := Error_Field_Reset; + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; -- unspecified Reserved_10_16 : nrf51.UInt7 := 16#0#; -- Enable interrupt on RXTO event. - RXTO : RXTO_Field_1 := Rxto_Field_Reset; + RXTO : INTENSET_RXTO_Field_1 := Intenset_Rxto_Field_Reset; -- unspecified Reserved_18_31 : nrf51.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -248,106 +257,162 @@ package nrf51.UART is Reserved_18_31 at 0 range 18 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on CTS event. + type INTENCLR_CTS_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_CTS_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on CTS event. - type CTS_Field_2 is - ( - -- Reset value for the field - Cts_Field_Reset, + type INTENCLR_CTS_Field_1 is + (-- Reset value for the field + Intenclr_Cts_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for CTS_Field_2 use - (Cts_Field_Reset => 0, + for INTENCLR_CTS_Field_1 use + (Intenclr_Cts_Field_Reset => 0, Clear => 1); -- Disable interrupt on NCTS event. - type NCTS_Field_2 is - ( - -- Reset value for the field - Ncts_Field_Reset, + type INTENCLR_NCTS_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_NCTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on NCTS event. + type INTENCLR_NCTS_Field_1 is + (-- Reset value for the field + Intenclr_Ncts_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for NCTS_Field_2 use - (Ncts_Field_Reset => 0, + for INTENCLR_NCTS_Field_1 use + (Intenclr_Ncts_Field_Reset => 0, Clear => 1); -- Disable interrupt on RXRDY event. - type RXDRDY_Field_2 is - ( - -- Reset value for the field - Rxdrdy_Field_Reset, + type INTENCLR_RXDRDY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_RXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on RXRDY event. + type INTENCLR_RXDRDY_Field_1 is + (-- Reset value for the field + Intenclr_Rxdrdy_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for RXDRDY_Field_2 use - (Rxdrdy_Field_Reset => 0, + for INTENCLR_RXDRDY_Field_1 use + (Intenclr_Rxdrdy_Field_Reset => 0, Clear => 1); -- Disable interrupt on TXRDY event. - type TXDRDY_Field_2 is - ( - -- Reset value for the field - Txdrdy_Field_Reset, + type INTENCLR_TXDRDY_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_TXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on TXRDY event. + type INTENCLR_TXDRDY_Field_1 is + (-- Reset value for the field + Intenclr_Txdrdy_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for TXDRDY_Field_2 use - (Txdrdy_Field_Reset => 0, + for INTENCLR_TXDRDY_Field_1 use + (Intenclr_Txdrdy_Field_Reset => 0, Clear => 1); -- Disable interrupt on ERROR event. - type ERROR_Field_2 is - ( - -- Reset value for the field - Error_Field_Reset, + type INTENCLR_ERROR_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on ERROR event. + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for ERROR_Field_2 use - (Error_Field_Reset => 0, + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, Clear => 1); -- Disable interrupt on RXTO event. - type RXTO_Field_2 is - ( - -- Reset value for the field - Rxto_Field_Reset, + type INTENCLR_RXTO_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_RXTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable interrupt on RXTO event. + type INTENCLR_RXTO_Field_1 is + (-- Reset value for the field + Intenclr_Rxto_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for RXTO_Field_2 use - (Rxto_Field_Reset => 0, + for INTENCLR_RXTO_Field_1 use + (Intenclr_Rxto_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on CTS event. - CTS : CTS_Field_2 := Cts_Field_Reset; + CTS : INTENCLR_CTS_Field_1 := Intenclr_Cts_Field_Reset; -- Disable interrupt on NCTS event. - NCTS : NCTS_Field_2 := Ncts_Field_Reset; + NCTS : INTENCLR_NCTS_Field_1 := Intenclr_Ncts_Field_Reset; -- Disable interrupt on RXRDY event. - RXDRDY : RXDRDY_Field_2 := Rxdrdy_Field_Reset; + RXDRDY : INTENCLR_RXDRDY_Field_1 := Intenclr_Rxdrdy_Field_Reset; -- unspecified Reserved_3_6 : nrf51.UInt4 := 16#0#; -- Disable interrupt on TXRDY event. - TXDRDY : TXDRDY_Field_2 := Txdrdy_Field_Reset; + TXDRDY : INTENCLR_TXDRDY_Field_1 := Intenclr_Txdrdy_Field_Reset; -- unspecified Reserved_8_8 : nrf51.Bit := 16#0#; -- Disable interrupt on ERROR event. - ERROR : ERROR_Field_2 := Error_Field_Reset; + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; -- unspecified Reserved_10_16 : nrf51.UInt7 := 16#0#; -- Disable interrupt on RXTO event. - RXTO : RXTO_Field_2 := Rxto_Field_Reset; + RXTO : INTENCLR_RXTO_Field_1 := Intenclr_Rxto_Field_Reset; -- unspecified Reserved_18_31 : nrf51.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -363,130 +428,120 @@ package nrf51.UART is Reserved_18_31 at 0 range 18 .. 31; end record; - ----------------------- - -- ERRORSRC_Register -- - ----------------------- - -- A start bit is received while the previous data still lies in RXD. (Data -- loss). - type OVERRUN_Field is - ( - -- Error not present. + type ERRORSRC_OVERRUN_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for OVERRUN_Field use + for ERRORSRC_OVERRUN_Field use (Notpresent => 0, Present => 1); -- A start bit is received while the previous data still lies in RXD. (Data -- loss). - type OVERRUN_Field_1 is - ( - -- Reset value for the field - Overrun_Field_Reset, + type ERRORSRC_OVERRUN_Field_1 is + (-- Reset value for the field + Errorsrc_Overrun_Field_Reset, -- Clear error on write. Clear) with Size => 1; - for OVERRUN_Field_1 use - (Overrun_Field_Reset => 0, + for ERRORSRC_OVERRUN_Field_1 use + (Errorsrc_Overrun_Field_Reset => 0, Clear => 1); -- A character with bad parity is received. Only checked if HW parity -- control is enabled. - type PARITY_Field is - ( - -- Error not present. + type ERRORSRC_PARITY_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for PARITY_Field use + for ERRORSRC_PARITY_Field use (Notpresent => 0, Present => 1); -- A character with bad parity is received. Only checked if HW parity -- control is enabled. - type PARITY_Field_1 is - ( - -- Reset value for the field - Parity_Field_Reset, + type ERRORSRC_PARITY_Field_1 is + (-- Reset value for the field + Errorsrc_Parity_Field_Reset, -- Clear error on write. Clear) with Size => 1; - for PARITY_Field_1 use - (Parity_Field_Reset => 0, + for ERRORSRC_PARITY_Field_1 use + (Errorsrc_Parity_Field_Reset => 0, Clear => 1); -- A valid stop bit is not detected on the serial data input after all bits -- in a character have been received. - type FRAMING_Field is - ( - -- Error not present. + type ERRORSRC_FRAMING_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for FRAMING_Field use + for ERRORSRC_FRAMING_Field use (Notpresent => 0, Present => 1); -- A valid stop bit is not detected on the serial data input after all bits -- in a character have been received. - type FRAMING_Field_1 is - ( - -- Reset value for the field - Framing_Field_Reset, + type ERRORSRC_FRAMING_Field_1 is + (-- Reset value for the field + Errorsrc_Framing_Field_Reset, -- Clear error on write. Clear) with Size => 1; - for FRAMING_Field_1 use - (Framing_Field_Reset => 0, + for ERRORSRC_FRAMING_Field_1 use + (Errorsrc_Framing_Field_Reset => 0, Clear => 1); -- The serial data input is '0' for longer than the length of a data frame. - type BREAK_Field is - ( - -- Error not present. + type ERRORSRC_BREAK_Field is + (-- Error not present. Notpresent, -- Error present. Present) with Size => 1; - for BREAK_Field use + for ERRORSRC_BREAK_Field use (Notpresent => 0, Present => 1); -- The serial data input is '0' for longer than the length of a data frame. - type BREAK_Field_1 is - ( - -- Reset value for the field - Break_Field_Reset, + type ERRORSRC_BREAK_Field_1 is + (-- Reset value for the field + Errorsrc_Break_Field_Reset, -- Clear error on write. Clear) with Size => 1; - for BREAK_Field_1 use - (Break_Field_Reset => 0, + for ERRORSRC_BREAK_Field_1 use + (Errorsrc_Break_Field_Reset => 0, Clear => 1); -- Error source. Write error field to 1 to clear error. type ERRORSRC_Register is record -- A start bit is received while the previous data still lies in RXD. -- (Data loss). - OVERRUN : OVERRUN_Field_1 := Overrun_Field_Reset; + OVERRUN : ERRORSRC_OVERRUN_Field_1 := + Errorsrc_Overrun_Field_Reset; -- A character with bad parity is received. Only checked if HW parity -- control is enabled. - PARITY : PARITY_Field_1 := Parity_Field_Reset; + PARITY : ERRORSRC_PARITY_Field_1 := Errorsrc_Parity_Field_Reset; -- A valid stop bit is not detected on the serial data input after all -- bits in a character have been received. - FRAMING : FRAMING_Field_1 := Framing_Field_Reset; + FRAMING : ERRORSRC_FRAMING_Field_1 := + Errorsrc_Framing_Field_Reset; -- The serial data input is '0' for longer than the length of a data -- frame. - BREAK : BREAK_Field_1 := Break_Field_Reset; + BREAK : ERRORSRC_BREAK_Field_1 := Errorsrc_Break_Field_Reset; -- unspecified Reserved_4_31 : nrf51.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ERRORSRC_Register use record @@ -497,30 +552,25 @@ package nrf51.UART is Reserved_4_31 at 0 range 4 .. 31; end record; - --------------------- - -- ENABLE_Register -- - --------------------- - -- Enable or disable UART and acquire IOs. - type ENABLE_Field is - ( - -- UART disabled. + type ENABLE_ENABLE_Field is + (-- UART disabled. Disabled, -- UART enabled. Enabled) with Size => 3; - for ENABLE_Field use + for ENABLE_ENABLE_Field use (Disabled => 0, Enabled => 4); -- Enable UART and acquire IOs. type ENABLE_Register is record -- Enable or disable UART and acquire IOs. - ENABLE : ENABLE_Field := Disabled; + ENABLE : ENABLE_ENABLE_Field := nrf51.UART.Disabled; -- unspecified Reserved_3_31 : nrf51.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -528,10 +578,6 @@ package nrf51.UART is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- RXD_Register -- - ------------------ - subtype RXD_RXD_Field is nrf51.Byte; -- RXD register. On read action the buffer pointer is displaced. Once read @@ -544,7 +590,7 @@ package nrf51.UART is -- unspecified Reserved_8_31 : nrf51.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXD_Register use record @@ -552,10 +598,6 @@ package nrf51.UART is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- TXD_Register -- - ------------------ - subtype TXD_TXD_Field is nrf51.Byte; -- TXD register. @@ -565,7 +607,7 @@ package nrf51.UART is -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXD_Register use record @@ -573,44 +615,38 @@ package nrf51.UART is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- - -- Hardware flow control. - type HWFC_Field is - ( - -- Hardware flow control disabled. + type CONFIG_HWFC_Field is + (-- Hardware flow control disabled. Disabled, -- Hardware flow control enabled. Enabled) with Size => 1; - for HWFC_Field use + for CONFIG_HWFC_Field use (Disabled => 0, Enabled => 1); -- Include parity bit. - type PARITY_Field_2 is - ( - -- Parity bit excluded. + type CONFIG_PARITY_Field is + (-- Parity bit excluded. Excluded, -- Parity bit included. Included) with Size => 3; - for PARITY_Field_2 use + for CONFIG_PARITY_Field use (Excluded => 0, Included => 7); -- Configuration of parity and hardware flow control register. type CONFIG_Register is record -- Hardware flow control. - HWFC : HWFC_Field := Disabled; + HWFC : CONFIG_HWFC_Field := nrf51.UART.Disabled; -- Include parity bit. - PARITY : PARITY_Field_2 := Excluded; + PARITY : CONFIG_PARITY_Field := nrf51.UART.Excluded; -- unspecified Reserved_4_31 : nrf51.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -619,30 +655,25 @@ package nrf51.UART is Reserved_4_31 at 0 range 4 .. 31; end record; - -------------------- - -- POWER_Register -- - -------------------- - -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.UART.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -655,92 +686,92 @@ package nrf51.UART is ----------------- -- Universal Asynchronous Receiver/Transmitter. - type UART0_Peripheral is record + type UART_Peripheral is record -- Start UART receiver. - TASKS_STARTRX : nrf51.Word; + TASKS_STARTRX : aliased nrf51.UInt32; -- Stop UART receiver. - TASKS_STOPRX : nrf51.Word; + TASKS_STOPRX : aliased nrf51.UInt32; -- Start UART transmitter. - TASKS_STARTTX : nrf51.Word; + TASKS_STARTTX : aliased nrf51.UInt32; -- Stop UART transmitter. - TASKS_STOPTX : nrf51.Word; + TASKS_STOPTX : aliased nrf51.UInt32; -- Suspend UART. - TASKS_SUSPEND : nrf51.Word; + TASKS_SUSPEND : aliased nrf51.UInt32; -- CTS activated. - EVENTS_CTS : nrf51.Word; + EVENTS_CTS : aliased nrf51.UInt32; -- CTS deactivated. - EVENTS_NCTS : nrf51.Word; + EVENTS_NCTS : aliased nrf51.UInt32; -- Data received in RXD. - EVENTS_RXDRDY : nrf51.Word; + EVENTS_RXDRDY : aliased nrf51.UInt32; -- Data sent from TXD. - EVENTS_TXDRDY : nrf51.Word; + EVENTS_TXDRDY : aliased nrf51.UInt32; -- Error detected. - EVENTS_ERROR : nrf51.Word; + EVENTS_ERROR : aliased nrf51.UInt32; -- Receiver timeout. - EVENTS_RXTO : nrf51.Word; + EVENTS_RXTO : aliased nrf51.UInt32; -- Shortcuts for UART. - SHORTS : SHORTS_Register; + SHORTS : aliased SHORTS_Register; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Error source. Write error field to 1 to clear error. - ERRORSRC : ERRORSRC_Register; + ERRORSRC : aliased ERRORSRC_Register; -- Enable UART and acquire IOs. - ENABLE : ENABLE_Register; + ENABLE : aliased ENABLE_Register; -- Pin select for RTS. - PSELRTS : nrf51.Word; + PSELRTS : aliased nrf51.UInt32; -- Pin select for TXD. - PSELTXD : nrf51.Word; + PSELTXD : aliased nrf51.UInt32; -- Pin select for CTS. - PSELCTS : nrf51.Word; + PSELCTS : aliased nrf51.UInt32; -- Pin select for RXD. - PSELRXD : nrf51.Word; + PSELRXD : aliased nrf51.UInt32; -- RXD register. On read action the buffer pointer is displaced. Once -- read the character is consumed. If read when no character available, -- the UART will stop working. - RXD : RXD_Register; + RXD : aliased RXD_Register; -- TXD register. - TXD : TXD_Register; + TXD : aliased TXD_Register; -- UART Baudrate. - BAUDRATE : nrf51.Word; + BAUDRATE : aliased nrf51.UInt32; -- Configuration of parity and hardware flow control register. - CONFIG : CONFIG_Register; + CONFIG : aliased CONFIG_Register; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; - for UART0_Peripheral use record - TASKS_STARTRX at 0 range 0 .. 31; - TASKS_STOPRX at 4 range 0 .. 31; - TASKS_STARTTX at 8 range 0 .. 31; - TASKS_STOPTX at 12 range 0 .. 31; - TASKS_SUSPEND at 28 range 0 .. 31; - EVENTS_CTS at 256 range 0 .. 31; - EVENTS_NCTS at 260 range 0 .. 31; - EVENTS_RXDRDY at 264 range 0 .. 31; - EVENTS_TXDRDY at 284 range 0 .. 31; - EVENTS_ERROR at 292 range 0 .. 31; - EVENTS_RXTO at 324 range 0 .. 31; - SHORTS at 512 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - ERRORSRC at 1152 range 0 .. 31; - ENABLE at 1280 range 0 .. 31; - PSELRTS at 1288 range 0 .. 31; - PSELTXD at 1292 range 0 .. 31; - PSELCTS at 1296 range 0 .. 31; - PSELRXD at 1300 range 0 .. 31; - RXD at 1304 range 0 .. 31; - TXD at 1308 range 0 .. 31; - BAUDRATE at 1316 range 0 .. 31; - CONFIG at 1388 range 0 .. 31; - POWER at 4092 range 0 .. 31; + for UART_Peripheral use record + TASKS_STARTRX at 16#0# range 0 .. 31; + TASKS_STOPRX at 16#4# range 0 .. 31; + TASKS_STARTTX at 16#8# range 0 .. 31; + TASKS_STOPTX at 16#C# range 0 .. 31; + TASKS_SUSPEND at 16#1C# range 0 .. 31; + EVENTS_CTS at 16#100# range 0 .. 31; + EVENTS_NCTS at 16#104# range 0 .. 31; + EVENTS_RXDRDY at 16#108# range 0 .. 31; + EVENTS_TXDRDY at 16#11C# range 0 .. 31; + EVENTS_ERROR at 16#124# range 0 .. 31; + EVENTS_RXTO at 16#144# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ERRORSRC at 16#480# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSELRTS at 16#508# range 0 .. 31; + PSELTXD at 16#50C# range 0 .. 31; + PSELCTS at 16#510# range 0 .. 31; + PSELRXD at 16#514# range 0 .. 31; + RXD at 16#518# range 0 .. 31; + TXD at 16#51C# range 0 .. 31; + BAUDRATE at 16#524# range 0 .. 31; + CONFIG at 16#56C# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; end record; -- Universal Asynchronous Receiver/Transmitter. - UART0_Periph : aliased UART0_Peripheral + UART0_Periph : aliased UART_Peripheral with Import, Address => UART0_Base; end nrf51.UART; diff --git a/microbit/nrf51/nrf51-uicr.ads b/microbit/nrf51/nrf51-uicr.ads index 05ed57e..590203a 100644 --- a/microbit/nrf51/nrf51-uicr.ads +++ b/microbit/nrf51/nrf51-uicr.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,32 +43,26 @@ package nrf51.UICR is -- Registers -- --------------- - ---------------------- - -- RBPCONF_Register -- - ---------------------- - -- Readback protect region 0. Will be ignored if pre-programmed factory -- code is present on the chip. - type PR0_Field is - ( - -- Enabled. + type RBPCONF_PR0_Field is + (-- Enabled. Enabled, -- Disabled. Disabled) with Size => 8; - for PR0_Field use + for RBPCONF_PR0_Field use (Enabled => 0, Disabled => 255); -- Readback protect all code in the device. - type PALL_Field is - ( - -- Enabled. + type RBPCONF_PALL_Field is + (-- Enabled. Enabled, -- Disabled. Disabled) with Size => 8; - for PALL_Field use + for RBPCONF_PALL_Field use (Enabled => 0, Disabled => 255); @@ -45,13 +70,13 @@ package nrf51.UICR is type RBPCONF_Register is record -- Readback protect region 0. Will be ignored if pre-programmed factory -- code is present on the chip. - PR0 : PR0_Field := Disabled; + PR0 : RBPCONF_PR0_Field := nrf51.UICR.Disabled; -- Readback protect all code in the device. - PALL : PALL_Field := Disabled; + PALL : RBPCONF_PALL_Field := nrf51.UICR.Disabled; -- unspecified - Reserved_16_31 : nrf51.Short := 16#FFFF#; + Reserved_16_31 : nrf51.UInt16 := 16#FFFF#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RBPCONF_Register use record @@ -60,30 +85,25 @@ package nrf51.UICR is Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------- - -- XTALFREQ_Register -- - ----------------------- - -- Reset value for CLOCK XTALFREQ register. - type XTALFREQ_Field is - ( - -- 32MHz Xtal is used. - XTALFREQ_Field_32Mhz, + type XTALFREQ_XTALFREQ_Field is + (-- 32MHz Xtal is used. + Val_32Mhz, -- 16MHz Xtal is used. - XTALFREQ_Field_16Mhz) + Val_16Mhz) with Size => 8; - for XTALFREQ_Field use - (XTALFREQ_Field_32Mhz => 0, - XTALFREQ_Field_16Mhz => 255); + for XTALFREQ_XTALFREQ_Field use + (Val_32Mhz => 0, + Val_16Mhz => 255); -- Reset value for CLOCK XTALFREQ register. type XTALFREQ_Register is record -- Reset value for CLOCK XTALFREQ register. - XTALFREQ : XTALFREQ_Field := XTALFREQ_Field_16Mhz; + XTALFREQ : XTALFREQ_XTALFREQ_Field := nrf51.UICR.Val_16Mhz; -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#FFFFFF#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for XTALFREQ_Register use record @@ -91,11 +111,7 @@ package nrf51.UICR is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- FWID_Register -- - ------------------- - - subtype FWID_FWID_Field is nrf51.Short; + subtype FWID_FWID_Field is nrf51.UInt16; -- Firmware ID. type FWID_Register is record @@ -103,9 +119,9 @@ package nrf51.UICR is -- chip. FWID : FWID_FWID_Field; -- unspecified - Reserved_16_31 : nrf51.Short; + Reserved_16_31 : nrf51.UInt16; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for FWID_Register use record @@ -116,25 +132,24 @@ package nrf51.UICR is -- Reserved for Nordic firmware design. -- Reserved for Nordic firmware design. - type NRFFW_Registers is array (0 .. 14) of nrf51.Word; + type NRFFW_Registers is array (0 .. 14) of nrf51.UInt32; -- Reserved for Nordic hardware design. -- Reserved for Nordic hardware design. - type NRFHW_Registers is array (0 .. 11) of nrf51.Word; + type NRFHW_Registers is array (0 .. 11) of nrf51.UInt32; -- Reserved for customer. -- Reserved for customer. - type CUSTOMER_Registers is array (0 .. 31) of nrf51.Word; + type CUSTOMER_Registers is array (0 .. 31) of nrf51.UInt32; ----------------- -- Peripherals -- ----------------- type UICR_Disc is - ( - Mode_1, + (Mode_1, Mode_2); -- User Information Configuration. @@ -142,37 +157,37 @@ package nrf51.UICR is (Discriminent : UICR_Disc := Mode_1) is record -- Length of code region 0. - CLENR0 : nrf51.Word; + CLENR0 : aliased nrf51.UInt32; -- Readback protection configuration. - RBPCONF : RBPCONF_Register; + RBPCONF : aliased RBPCONF_Register; -- Reset value for CLOCK XTALFREQ register. - XTALFREQ : XTALFREQ_Register; + XTALFREQ : aliased XTALFREQ_Register; -- Firmware ID. - FWID : FWID_Register; + FWID : aliased FWID_Register; -- Reserved for Nordic hardware design. - NRFHW : NRFHW_Registers; + NRFHW : aliased NRFHW_Registers; -- Reserved for customer. - CUSTOMER : CUSTOMER_Registers; + CUSTOMER : aliased CUSTOMER_Registers; case Discriminent is when Mode_1 => -- Bootloader start address. - BOOTLOADERADDR : nrf51.Word; + BOOTLOADERADDR : aliased nrf51.UInt32; when Mode_2 => -- Reserved for Nordic firmware design. - NRFFW : NRFFW_Registers; + NRFFW : aliased NRFFW_Registers; end case; end record with Unchecked_Union, Volatile; for UICR_Peripheral use record - CLENR0 at 0 range 0 .. 31; - RBPCONF at 4 range 0 .. 31; - XTALFREQ at 8 range 0 .. 31; - FWID at 16 range 0 .. 31; - NRFHW at 80 range 0 .. 383; - CUSTOMER at 128 range 0 .. 1023; - BOOTLOADERADDR at 20 range 0 .. 31; - NRFFW at 20 range 0 .. 479; + CLENR0 at 16#0# range 0 .. 31; + RBPCONF at 16#4# range 0 .. 31; + XTALFREQ at 16#8# range 0 .. 31; + FWID at 16#10# range 0 .. 31; + NRFHW at 16#50# range 0 .. 383; + CUSTOMER at 16#80# range 0 .. 1023; + BOOTLOADERADDR at 16#14# range 0 .. 31; + NRFFW at 16#14# range 0 .. 479; end record; -- User Information Configuration. diff --git a/microbit/nrf51/nrf51-wdt.ads b/microbit/nrf51/nrf51-wdt.ads index 6c4bd67..73f461d 100644 --- a/microbit/nrf51/nrf51-wdt.ads +++ b/microbit/nrf51/nrf51-wdt.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -12,42 +43,37 @@ package nrf51.WDT is -- Registers -- --------------- - ----------------------- - -- INTENSET_Register -- - ----------------------- - -- Enable interrupt on TIMEOUT event. - type TIMEOUT_Field is - ( - -- Interrupt disabled. + type INTENSET_TIMEOUT_Field is + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) with Size => 1; - for TIMEOUT_Field use + for INTENSET_TIMEOUT_Field use (Disabled => 0, Enabled => 1); -- Enable interrupt on TIMEOUT event. - type TIMEOUT_Field_1 is - ( - -- Reset value for the field - Timeout_Field_Reset, + type INTENSET_TIMEOUT_Field_1 is + (-- Reset value for the field + Intenset_Timeout_Field_Reset, -- Enable interrupt on write. Set) with Size => 1; - for TIMEOUT_Field_1 use - (Timeout_Field_Reset => 0, + for INTENSET_TIMEOUT_Field_1 use + (Intenset_Timeout_Field_Reset => 0, Set => 1); -- Interrupt enable set register. type INTENSET_Register is record -- Enable interrupt on TIMEOUT event. - TIMEOUT : TIMEOUT_Field_1 := Timeout_Field_Reset; + TIMEOUT : INTENSET_TIMEOUT_Field_1 := + Intenset_Timeout_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -55,30 +81,37 @@ package nrf51.WDT is Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- INTENCLR_Register -- - ----------------------- + -- Disable interrupt on TIMEOUT event. + type INTENCLR_TIMEOUT_Field is + (-- Interrupt disabled. + Disabled, + -- Interrupt enabled. + Enabled) + with Size => 1; + for INTENCLR_TIMEOUT_Field use + (Disabled => 0, + Enabled => 1); -- Disable interrupt on TIMEOUT event. - type TIMEOUT_Field_2 is - ( - -- Reset value for the field - Timeout_Field_Reset, + type INTENCLR_TIMEOUT_Field_1 is + (-- Reset value for the field + Intenclr_Timeout_Field_Reset, -- Disable interrupt on write. Clear) with Size => 1; - for TIMEOUT_Field_2 use - (Timeout_Field_Reset => 0, + for INTENCLR_TIMEOUT_Field_1 use + (Intenclr_Timeout_Field_Reset => 0, Clear => 1); -- Interrupt enable clear register. type INTENCLR_Register is record -- Disable interrupt on TIMEOUT event. - TIMEOUT : TIMEOUT_Field_2 := Timeout_Field_Reset; + TIMEOUT : INTENCLR_TIMEOUT_Field_1 := + Intenclr_Timeout_Field_Reset; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -86,30 +119,25 @@ package nrf51.WDT is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- RUNSTATUS_Register -- - ------------------------ - -- Watchdog running status. - type RUNSTATUS_Field is - ( - -- Watchdog timer is not running. + type RUNSTATUS_RUNSTATUS_Field is + (-- Watchdog timer is not running. Notrunning, -- Watchdog timer is running. Running) with Size => 1; - for RUNSTATUS_Field use + for RUNSTATUS_RUNSTATUS_Field use (Notrunning => 0, Running => 1); -- Watchdog running status. type RUNSTATUS_Register is record -- Read-only. Watchdog running status. - RUNSTATUS : RUNSTATUS_Field; + RUNSTATUS : RUNSTATUS_RUNSTATUS_Field; -- unspecified Reserved_1_31 : nrf51.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RUNSTATUS_Register use record @@ -117,128 +145,116 @@ package nrf51.WDT is Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- REQSTATUS_Register -- - ------------------------ - -- Request status for RR[0]. - type RR0_Field is - ( - -- RR[0] register is not enabled or has already requested reload. + type REQSTATUS_RR0_Field is + (-- RR[0] register is not enabled or has already requested reload. Disabledorrequested, -- RR[0] register is enabled and has not jet requested. Enabledandunrequested) with Size => 1; - for RR0_Field use + for REQSTATUS_RR0_Field use (Disabledorrequested => 0, Enabledandunrequested => 1); -- Request status for RR[1]. - type RR1_Field is - ( - -- RR[1] register is not enabled or has already requested reload. + type REQSTATUS_RR1_Field is + (-- RR[1] register is not enabled or has already requested reload. Disabledorrequested, -- RR[1] register is enabled and has not jet requested. Enabledandunrequested) with Size => 1; - for RR1_Field use + for REQSTATUS_RR1_Field use (Disabledorrequested => 0, Enabledandunrequested => 1); -- Request status for RR[2]. - type RR2_Field is - ( - -- RR[2] register is not enabled or has already requested reload. + type REQSTATUS_RR2_Field is + (-- RR[2] register is not enabled or has already requested reload. Disabledorrequested, -- RR[2] register is enabled and has not jet requested. Enabledandunrequested) with Size => 1; - for RR2_Field use + for REQSTATUS_RR2_Field use (Disabledorrequested => 0, Enabledandunrequested => 1); -- Request status for RR[3]. - type RR3_Field is - ( - -- RR[3] register is not enabled or has already requested reload. + type REQSTATUS_RR3_Field is + (-- RR[3] register is not enabled or has already requested reload. Disabledorrequested, -- RR[3] register is enabled and has not jet requested. Enabledandunrequested) with Size => 1; - for RR3_Field use + for REQSTATUS_RR3_Field use (Disabledorrequested => 0, Enabledandunrequested => 1); -- Request status for RR[4]. - type RR4_Field is - ( - -- RR[4] register is not enabled or has already requested reload. + type REQSTATUS_RR4_Field is + (-- RR[4] register is not enabled or has already requested reload. Disabledorrequested, -- RR[4] register is enabled and has not jet requested. Enabledandunrequested) with Size => 1; - for RR4_Field use + for REQSTATUS_RR4_Field use (Disabledorrequested => 0, Enabledandunrequested => 1); -- Request status for RR[5]. - type RR5_Field is - ( - -- RR[5] register is not enabled or has already requested reload. + type REQSTATUS_RR5_Field is + (-- RR[5] register is not enabled or has already requested reload. Disabledorrequested, -- RR[5] register is enabled and has not jet requested. Enabledandunrequested) with Size => 1; - for RR5_Field use + for REQSTATUS_RR5_Field use (Disabledorrequested => 0, Enabledandunrequested => 1); -- Request status for RR[6]. - type RR6_Field is - ( - -- RR[6] register is not enabled or has already requested reload. + type REQSTATUS_RR6_Field is + (-- RR[6] register is not enabled or has already requested reload. Disabledorrequested, -- RR[6] register is enabled and has not jet requested. Enabledandunrequested) with Size => 1; - for RR6_Field use + for REQSTATUS_RR6_Field use (Disabledorrequested => 0, Enabledandunrequested => 1); -- Request status for RR[7]. - type RR7_Field is - ( - -- RR[7] register is not enabled or has already requested reload. + type REQSTATUS_RR7_Field is + (-- RR[7] register is not enabled or has already requested reload. Disabledorrequested, -- RR[7] register is enabled and has not jet requested. Enabledandunrequested) with Size => 1; - for RR7_Field use + for REQSTATUS_RR7_Field use (Disabledorrequested => 0, Enabledandunrequested => 1); -- Request status. type REQSTATUS_Register is record -- Read-only. Request status for RR[0]. - RR0 : RR0_Field; + RR0 : REQSTATUS_RR0_Field; -- Read-only. Request status for RR[1]. - RR1 : RR1_Field; + RR1 : REQSTATUS_RR1_Field; -- Read-only. Request status for RR[2]. - RR2 : RR2_Field; + RR2 : REQSTATUS_RR2_Field; -- Read-only. Request status for RR[3]. - RR3 : RR3_Field; + RR3 : REQSTATUS_RR3_Field; -- Read-only. Request status for RR[4]. - RR4 : RR4_Field; + RR4 : REQSTATUS_RR4_Field; -- Read-only. Request status for RR[5]. - RR5 : RR5_Field; + RR5 : REQSTATUS_RR5_Field; -- Read-only. Request status for RR[6]. - RR6 : RR6_Field; + RR6 : REQSTATUS_RR6_Field; -- Read-only. Request status for RR[7]. - RR7 : RR7_Field; + RR7 : REQSTATUS_RR7_Field; -- unspecified Reserved_8_31 : nrf51.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for REQSTATUS_Register use record @@ -253,128 +269,116 @@ package nrf51.WDT is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- RREN_Register -- - ------------------- - -- Enable or disable RR[0] register. - type RR0_Field_1 is - ( - -- RR[0] register is disabled. + type RREN_RR0_Field is + (-- RR[0] register is disabled. Disabled, -- RR[0] register is enabled. Enabled) with Size => 1; - for RR0_Field_1 use + for RREN_RR0_Field use (Disabled => 0, Enabled => 1); -- Enable or disable RR[1] register. - type RR1_Field_1 is - ( - -- RR[1] register is disabled. + type RREN_RR1_Field is + (-- RR[1] register is disabled. Disabled, -- RR[1] register is enabled. Enabled) with Size => 1; - for RR1_Field_1 use + for RREN_RR1_Field use (Disabled => 0, Enabled => 1); -- Enable or disable RR[2] register. - type RR2_Field_1 is - ( - -- RR[2] register is disabled. + type RREN_RR2_Field is + (-- RR[2] register is disabled. Disabled, -- RR[2] register is enabled. Enabled) with Size => 1; - for RR2_Field_1 use + for RREN_RR2_Field use (Disabled => 0, Enabled => 1); -- Enable or disable RR[3] register. - type RR3_Field_1 is - ( - -- RR[3] register is disabled. + type RREN_RR3_Field is + (-- RR[3] register is disabled. Disabled, -- RR[3] register is enabled. Enabled) with Size => 1; - for RR3_Field_1 use + for RREN_RR3_Field use (Disabled => 0, Enabled => 1); -- Enable or disable RR[4] register. - type RR4_Field_1 is - ( - -- RR[4] register is disabled. + type RREN_RR4_Field is + (-- RR[4] register is disabled. Disabled, -- RR[4] register is enabled. Enabled) with Size => 1; - for RR4_Field_1 use + for RREN_RR4_Field use (Disabled => 0, Enabled => 1); -- Enable or disable RR[5] register. - type RR5_Field_1 is - ( - -- RR[5] register is disabled. + type RREN_RR5_Field is + (-- RR[5] register is disabled. Disabled, -- RR[5] register is enabled. Enabled) with Size => 1; - for RR5_Field_1 use + for RREN_RR5_Field use (Disabled => 0, Enabled => 1); -- Enable or disable RR[6] register. - type RR6_Field_1 is - ( - -- RR[6] register is disabled. + type RREN_RR6_Field is + (-- RR[6] register is disabled. Disabled, -- RR[6] register is enabled. Enabled) with Size => 1; - for RR6_Field_1 use + for RREN_RR6_Field use (Disabled => 0, Enabled => 1); -- Enable or disable RR[7] register. - type RR7_Field_1 is - ( - -- RR[7] register is disabled. + type RREN_RR7_Field is + (-- RR[7] register is disabled. Disabled, -- RR[7] register is enabled. Enabled) with Size => 1; - for RR7_Field_1 use + for RREN_RR7_Field use (Disabled => 0, Enabled => 1); -- Reload request enable. type RREN_Register is record -- Enable or disable RR[0] register. - RR0 : RR0_Field_1 := Enabled; + RR0 : RREN_RR0_Field := nrf51.WDT.Enabled; -- Enable or disable RR[1] register. - RR1 : RR1_Field_1 := Disabled; + RR1 : RREN_RR1_Field := nrf51.WDT.Disabled; -- Enable or disable RR[2] register. - RR2 : RR2_Field_1 := Disabled; + RR2 : RREN_RR2_Field := nrf51.WDT.Disabled; -- Enable or disable RR[3] register. - RR3 : RR3_Field_1 := Disabled; + RR3 : RREN_RR3_Field := nrf51.WDT.Disabled; -- Enable or disable RR[4] register. - RR4 : RR4_Field_1 := Disabled; + RR4 : RREN_RR4_Field := nrf51.WDT.Disabled; -- Enable or disable RR[5] register. - RR5 : RR5_Field_1 := Disabled; + RR5 : RREN_RR5_Field := nrf51.WDT.Disabled; -- Enable or disable RR[6] register. - RR6 : RR6_Field_1 := Disabled; + RR6 : RREN_RR6_Field := nrf51.WDT.Disabled; -- Enable or disable RR[7] register. - RR7 : RR7_Field_1 := Disabled; + RR7 : RREN_RR7_Field := nrf51.WDT.Disabled; -- unspecified Reserved_8_31 : nrf51.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RREN_Register use record @@ -389,48 +393,42 @@ package nrf51.WDT is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- CONFIG_Register -- - --------------------- - -- Configure the watchdog to pause or not while the CPU is sleeping. - type SLEEP_Field is - ( - -- Pause watchdog while the CPU is asleep. + type CONFIG_SLEEP_Field is + (-- Pause watchdog while the CPU is asleep. Pause, -- Do not pause watchdog while the CPU is asleep. Run) with Size => 1; - for SLEEP_Field use + for CONFIG_SLEEP_Field use (Pause => 0, Run => 1); -- Configure the watchdog to pause or not while the CPU is halted by the -- debugger. - type HALT_Field is - ( - -- Pause watchdog while the CPU is halted by the debugger. + type CONFIG_HALT_Field is + (-- Pause watchdog while the CPU is halted by the debugger. Pause, -- Do not pause watchdog while the CPU is halted by the debugger. Run) with Size => 1; - for HALT_Field use + for CONFIG_HALT_Field use (Pause => 0, Run => 1); -- Configuration register. type CONFIG_Register is record -- Configure the watchdog to pause or not while the CPU is sleeping. - SLEEP : SLEEP_Field := Run; + SLEEP : CONFIG_SLEEP_Field := nrf51.WDT.Run; -- unspecified Reserved_1_2 : nrf51.UInt2 := 16#0#; -- Configure the watchdog to pause or not while the CPU is halted by the -- debugger. - HALT : HALT_Field := Pause; + HALT : CONFIG_HALT_Field := nrf51.WDT.Pause; -- unspecified Reserved_4_31 : nrf51.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -443,32 +441,27 @@ package nrf51.WDT is -- Reload requests registers. -- Reload requests registers. - type RR_Registers is array (0 .. 7) of nrf51.Word; - - -------------------- - -- POWER_Register -- - -------------------- + type RR_Registers is array (0 .. 7) of nrf51.UInt32; -- Peripheral power control. - type POWER_Field is - ( - -- Module power disabled. + type POWER_POWER_Field is + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) with Size => 1; - for POWER_Field use + for POWER_POWER_Field use (Disabled => 0, Enabled => 1); -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_Field := Disabled; + POWER : POWER_POWER_Field := nrf51.WDT.Disabled; -- unspecified Reserved_1_31 : nrf51.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -483,42 +476,42 @@ package nrf51.WDT is -- Watchdog Timer. type WDT_Peripheral is record -- Start the watchdog. - TASKS_START : nrf51.Word; + TASKS_START : aliased nrf51.UInt32; -- Watchdog timeout. - EVENTS_TIMEOUT : nrf51.Word; + EVENTS_TIMEOUT : aliased nrf51.UInt32; -- Interrupt enable set register. - INTENSET : INTENSET_Register; + INTENSET : aliased INTENSET_Register; -- Interrupt enable clear register. - INTENCLR : INTENCLR_Register; + INTENCLR : aliased INTENCLR_Register; -- Watchdog running status. - RUNSTATUS : RUNSTATUS_Register; + RUNSTATUS : aliased RUNSTATUS_Register; -- Request status. - REQSTATUS : REQSTATUS_Register; + REQSTATUS : aliased REQSTATUS_Register; -- Counter reload value in number of 32kiHz clock cycles. - CRV : nrf51.Word; + CRV : aliased nrf51.UInt32; -- Reload request enable. - RREN : RREN_Register; + RREN : aliased RREN_Register; -- Configuration register. - CONFIG : CONFIG_Register; + CONFIG : aliased CONFIG_Register; -- Reload requests registers. - RR : RR_Registers; + RR : aliased RR_Registers; -- Peripheral power control. - POWER : POWER_Register; + POWER : aliased POWER_Register; end record with Volatile; for WDT_Peripheral use record - TASKS_START at 0 range 0 .. 31; - EVENTS_TIMEOUT at 256 range 0 .. 31; - INTENSET at 772 range 0 .. 31; - INTENCLR at 776 range 0 .. 31; - RUNSTATUS at 1024 range 0 .. 31; - REQSTATUS at 1028 range 0 .. 31; - CRV at 1284 range 0 .. 31; - RREN at 1288 range 0 .. 31; - CONFIG at 1292 range 0 .. 31; - RR at 1536 range 0 .. 255; - POWER at 4092 range 0 .. 31; + TASKS_START at 16#0# range 0 .. 31; + EVENTS_TIMEOUT at 16#100# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + RUNSTATUS at 16#400# range 0 .. 31; + REQSTATUS at 16#404# range 0 .. 31; + CRV at 16#504# range 0 .. 31; + RREN at 16#508# range 0 .. 31; + CONFIG at 16#50C# range 0 .. 31; + RR at 16#600# range 0 .. 255; + POWER at 16#FFC# range 0 .. 31; end record; -- Watchdog Timer. diff --git a/microbit/nrf51/nrf51.ads b/microbit/nrf51/nrf51.ads index cfbc1b8..eedfb58 100644 --- a/microbit/nrf51/nrf51.ads +++ b/microbit/nrf51/nrf51.ads @@ -1,7 +1,38 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + -- This spec has been automatically generated from nrf51.svd pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with Interfaces; with System; @@ -15,9 +46,9 @@ package nrf51 is -- Base type -- --------------- - subtype Word is Interfaces.Unsigned_32; - subtype Short is Interfaces.Unsigned_16; - subtype Byte is Interfaces.Unsigned_8; + type UInt32 is new Interfaces.Unsigned_32; + type UInt16 is new Interfaces.Unsigned_16; + type Byte is new Interfaces.Unsigned_8; type Bit is mod 2**1 with Size => 1; type UInt2 is mod 2**2 @@ -81,71 +112,38 @@ package nrf51 is -- Base addresses -- -------------------- - POWER_Base : constant System.Address := - System'To_Address (16#40000000#); - CLOCK_Base : constant System.Address := - System'To_Address (16#40000000#); - MPU_Base : constant System.Address := - System'To_Address (16#40000000#); - AMLI_Base : constant System.Address := - System'To_Address (16#40000000#); - RADIO_Base : constant System.Address := - System'To_Address (16#40001000#); - UART0_Base : constant System.Address := - System'To_Address (16#40002000#); - SPI0_Base : constant System.Address := - System'To_Address (16#40003000#); - TWI0_Base : constant System.Address := - System'To_Address (16#40003000#); - SPI1_Base : constant System.Address := - System'To_Address (16#40004000#); - TWI1_Base : constant System.Address := - System'To_Address (16#40004000#); - SPIS1_Base : constant System.Address := - System'To_Address (16#40004000#); - SPIM1_Base : constant System.Address := - System'To_Address (16#40004000#); - GPIOTE_Base : constant System.Address := - System'To_Address (16#40006000#); - ADC_Base : constant System.Address := - System'To_Address (16#40007000#); - TIMER0_Base : constant System.Address := - System'To_Address (16#40008000#); - TIMER1_Base : constant System.Address := - System'To_Address (16#40009000#); - TIMER2_Base : constant System.Address := - System'To_Address (16#4000A000#); - RTC0_Base : constant System.Address := - System'To_Address (16#4000B000#); - TEMP_Base : constant System.Address := - System'To_Address (16#4000C000#); - RNG_Base : constant System.Address := - System'To_Address (16#4000D000#); - ECB_Base : constant System.Address := - System'To_Address (16#4000E000#); - AAR_Base : constant System.Address := - System'To_Address (16#4000F000#); - CCM_Base : constant System.Address := - System'To_Address (16#4000F000#); - WDT_Base : constant System.Address := - System'To_Address (16#40010000#); - RTC1_Base : constant System.Address := - System'To_Address (16#40011000#); - QDEC_Base : constant System.Address := - System'To_Address (16#40012000#); - LPCOMP_Base : constant System.Address := - System'To_Address (16#40013000#); - SWI_Base : constant System.Address := - System'To_Address (16#40014000#); - NVMC_Base : constant System.Address := - System'To_Address (16#4001E000#); - PPI_Base : constant System.Address := - System'To_Address (16#4001F000#); - FICR_Base : constant System.Address := - System'To_Address (16#10000000#); - UICR_Base : constant System.Address := - System'To_Address (16#10001000#); - GPIO_Base : constant System.Address := - System'To_Address (16#50000000#); + POWER_Base : constant System.Address := System'To_Address (16#40000000#); + CLOCK_Base : constant System.Address := System'To_Address (16#40000000#); + MPU_Base : constant System.Address := System'To_Address (16#40000000#); + AMLI_Base : constant System.Address := System'To_Address (16#40000000#); + RADIO_Base : constant System.Address := System'To_Address (16#40001000#); + UART0_Base : constant System.Address := System'To_Address (16#40002000#); + SPI0_Base : constant System.Address := System'To_Address (16#40003000#); + TWI0_Base : constant System.Address := System'To_Address (16#40003000#); + SPI1_Base : constant System.Address := System'To_Address (16#40004000#); + TWI1_Base : constant System.Address := System'To_Address (16#40004000#); + SPIS1_Base : constant System.Address := System'To_Address (16#40004000#); + SPIM1_Base : constant System.Address := System'To_Address (16#40004000#); + GPIOTE_Base : constant System.Address := System'To_Address (16#40006000#); + ADC_Base : constant System.Address := System'To_Address (16#40007000#); + TIMER0_Base : constant System.Address := System'To_Address (16#40008000#); + TIMER1_Base : constant System.Address := System'To_Address (16#40009000#); + TIMER2_Base : constant System.Address := System'To_Address (16#4000A000#); + RTC0_Base : constant System.Address := System'To_Address (16#4000B000#); + TEMP_Base : constant System.Address := System'To_Address (16#4000C000#); + RNG_Base : constant System.Address := System'To_Address (16#4000D000#); + ECB_Base : constant System.Address := System'To_Address (16#4000E000#); + AAR_Base : constant System.Address := System'To_Address (16#4000F000#); + CCM_Base : constant System.Address := System'To_Address (16#4000F000#); + WDT_Base : constant System.Address := System'To_Address (16#40010000#); + RTC1_Base : constant System.Address := System'To_Address (16#40011000#); + QDEC_Base : constant System.Address := System'To_Address (16#40012000#); + LPCOMP_Base : constant System.Address := System'To_Address (16#40013000#); + SWI_Base : constant System.Address := System'To_Address (16#40014000#); + NVMC_Base : constant System.Address := System'To_Address (16#4001E000#); + PPI_Base : constant System.Address := System'To_Address (16#4001F000#); + FICR_Base : constant System.Address := System'To_Address (16#10000000#); + UICR_Base : constant System.Address := System'To_Address (16#10001000#); + GPIO_Base : constant System.Address := System'To_Address (16#50000000#); end nrf51; diff --git a/stm32f4/Makefile b/stm32f4/Makefile index e9d0e16..50078ac 100644 --- a/stm32f4/Makefile +++ b/stm32f4/Makefile @@ -1,4 +1,4 @@ -# Copyright (C) 2016, 2018 Free Software Foundation, Inc. +# Copyright (C) 2016, 2018, 2020 Free Software Foundation, Inc. # # This file is part of the Cortex GNAT RTS package. # @@ -16,13 +16,22 @@ # along with this program; see the file COPYING3. If not, see # . -all: +SVD2ADA ?= ~/adacore/svd2ada + +all: stm32f40x gprbuild -p -P build_runtime.gpr +stm32f40x: + $(SVD2ADA)/svd2ada \ + --output=stm32f40x \ + --no-vfa-on-types \ + $(SVD2ADA)/CMSIS-SVD/ST/STM32F40x.svd + install: all gprinstall -p -P build_runtime.gpr -f clean: - gprclean -P build_runtime.gpr + -gprclean -P build_runtime.gpr + rm -rf stm32f40x .PHONY: all install clean diff --git a/stm32f4/stm32f40x/stm32f40x-adc.ads b/stm32f4/stm32f40x/stm32f40x-adc.ads index 4724e9f..5d1c72d 100644 --- a/stm32f4/stm32f40x/stm32f40x-adc.ads +++ b/stm32f4/stm32f40x/stm32f40x-adc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.ADC is -- Registers -- --------------- - ----------------- - -- SR_Register -- - ----------------- - subtype SR_AWD_Field is STM32F40x.Bit; subtype SR_EOC_Field is STM32F40x.Bit; subtype SR_JEOC_Field is STM32F40x.Bit; @@ -41,8 +38,7 @@ package STM32F40x.ADC is -- unspecified Reserved_6_31 : STM32F40x.UInt26 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record AWD at 0 range 0 .. 0; @@ -54,10 +50,6 @@ package STM32F40x.ADC is Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_AWDCH_Field is STM32F40x.UInt5; subtype CR1_EOCIE_Field is STM32F40x.Bit; subtype CR1_AWDIE_Field is STM32F40x.Bit; @@ -108,8 +100,7 @@ package STM32F40x.ADC is -- unspecified Reserved_27_31 : STM32F40x.UInt5 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record AWDCH at 0 range 0 .. 4; @@ -130,10 +121,6 @@ package STM32F40x.ADC is Reserved_27_31 at 0 range 27 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_ADON_Field is STM32F40x.Bit; subtype CR2_CONT_Field is STM32F40x.Bit; subtype CR2_DMA_Field is STM32F40x.Bit; @@ -182,8 +169,7 @@ package STM32F40x.ADC is -- unspecified Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record ADON at 0 range 0 .. 0; @@ -204,14 +190,6 @@ package STM32F40x.ADC is Reserved_31_31 at 0 range 31 .. 31; end record; - -------------------- - -- SMPR1_Register -- - -------------------- - - --------------- - -- SMPR1.SMP -- - --------------- - -- SMPR1_SMP array element subtype SMPR1_SMP_Element is STM32F40x.UInt3; @@ -246,22 +224,13 @@ package STM32F40x.ADC is -- unspecified Reserved_27_31 : STM32F40x.UInt5 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SMPR1_Register use record SMP at 0 range 0 .. 26; Reserved_27_31 at 0 range 27 .. 31; end record; - -------------------- - -- SMPR2_Register -- - -------------------- - - --------------- - -- SMPR2.SMP -- - --------------- - -- SMPR2_SMP array element subtype SMPR2_SMP_Element is STM32F40x.UInt3; @@ -296,38 +265,76 @@ package STM32F40x.ADC is -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SMPR2_Register use record SMP at 0 range 0 .. 29; Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- JOFR_Register -- - ------------------- - subtype JOFR1_JOFFSET1_Field is STM32F40x.UInt12; -- injected channel data offset register x - type JOFR_Register is record + type JOFR1_Register is record -- Data offset for injected channel x JOFFSET1 : JOFR1_JOFFSET1_Field := 16#0#; -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for JOFR_Register use record + for JOFR1_Register use record JOFFSET1 at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- HTR_Register -- - ------------------ + subtype JOFR2_JOFFSET2_Field is STM32F40x.UInt12; + + -- injected channel data offset register x + type JOFR2_Register is record + -- Data offset for injected channel x + JOFFSET2 : JOFR2_JOFFSET2_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for JOFR2_Register use record + JOFFSET2 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype JOFR3_JOFFSET3_Field is STM32F40x.UInt12; + + -- injected channel data offset register x + type JOFR3_Register is record + -- Data offset for injected channel x + JOFFSET3 : JOFR3_JOFFSET3_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for JOFR3_Register use record + JOFFSET3 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype JOFR4_JOFFSET4_Field is STM32F40x.UInt12; + + -- injected channel data offset register x + type JOFR4_Register is record + -- Data offset for injected channel x + JOFFSET4 : JOFR4_JOFFSET4_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for JOFR4_Register use record + JOFFSET4 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; subtype HTR_HT_Field is STM32F40x.UInt12; @@ -338,18 +345,13 @@ package STM32F40x.ADC is -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for HTR_Register use record HT at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- LTR_Register -- - ------------------ - subtype LTR_LT_Field is STM32F40x.UInt12; -- watchdog lower threshold register @@ -359,22 +361,13 @@ package STM32F40x.ADC is -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LTR_Register use record LT at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------- - -- SQR1_Register -- - ------------------- - - ------------- - -- SQR1.SQ -- - ------------- - -- SQR1_SQ array element subtype SQR1_SQ_Element is STM32F40x.UInt5; @@ -413,8 +406,7 @@ package STM32F40x.ADC is -- unspecified Reserved_24_31 : STM32F40x.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SQR1_Register use record SQ at 0 range 0 .. 19; @@ -422,14 +414,6 @@ package STM32F40x.ADC is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- SQR_Register -- - ------------------ - - ------------- - -- SQR2.SQ -- - ------------- - -- SQR2_SQ array element subtype SQR2_SQ_Element is STM32F40x.UInt5; @@ -458,27 +442,59 @@ package STM32F40x.ADC is end record; -- regular sequence register 2 - type SQR_Register is record + type SQR2_Register is record -- 7th conversion in regular sequence SQ : SQR2_SQ_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SQR_Register use record + for SQR2_Register use record SQ at 0 range 0 .. 29; Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- JSQR_Register -- - ------------------- + -- SQR3_SQ array element + subtype SQR3_SQ_Element is STM32F40x.UInt5; - -------------- - -- JSQR.JSQ -- - -------------- + -- SQR3_SQ array + type SQR3_SQ_Field_Array is array (1 .. 6) of SQR3_SQ_Element + with Component_Size => 5, Size => 30; + + -- Type definition for SQR3_SQ + type SQR3_SQ_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SQ as a value + Val : STM32F40x.UInt30; + when True => + -- SQ as an array + Arr : SQR3_SQ_Field_Array; + end case; + end record + with Unchecked_Union, Size => 30; + + for SQR3_SQ_Field use record + Val at 0 range 0 .. 29; + Arr at 0 range 0 .. 29; + end record; + + -- regular sequence register 3 + type SQR3_Register is record + -- 1st conversion in regular sequence + SQ : SQR3_SQ_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_30_31 : STM32F40x.UInt2 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SQR3_Register use record + SQ at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; -- JSQR_JSQ array element subtype JSQR_JSQ_Element is STM32F40x.UInt5; @@ -518,8 +534,7 @@ package STM32F40x.ADC is -- unspecified Reserved_22_31 : STM32F40x.UInt10 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for JSQR_Register use record JSQ at 0 range 0 .. 19; @@ -527,52 +542,38 @@ package STM32F40x.ADC is Reserved_22_31 at 0 range 22 .. 31; end record; - ------------------ - -- JDR_Register -- - ------------------ - - subtype JDR1_JDATA_Field is STM32F40x.Short; + subtype JDR_JDATA_Field is STM32F40x.UInt16; -- injected data register x type JDR_Register is record -- Read-only. Injected data - JDATA : JDR1_JDATA_Field := 16#0#; + JDATA : JDR_JDATA_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for JDR_Register use record JDATA at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - - subtype DR_DATA_Field is STM32F40x.Short; + subtype DR_DATA_Field is STM32F40x.UInt16; -- regular data register type DR_Register is record -- Read-only. Regular data - DATA : DR_DATA_Field := 16#0#; + DATA : DR_DATA_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DATA at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CSR_Register -- - ------------------ - subtype CSR_AWD1_Field is STM32F40x.Bit; subtype CSR_EOC1_Field is STM32F40x.Bit; subtype CSR_JEOC1_Field is STM32F40x.Bit; @@ -595,50 +596,49 @@ package STM32F40x.ADC is -- ADC Common status register type CSR_Register is record -- Read-only. Analog watchdog flag of ADC 1 - AWD1 : CSR_AWD1_Field := 16#0#; + AWD1 : CSR_AWD1_Field; -- Read-only. End of conversion of ADC 1 - EOC1 : CSR_EOC1_Field := 16#0#; + EOC1 : CSR_EOC1_Field; -- Read-only. Injected channel end of conversion of ADC 1 - JEOC1 : CSR_JEOC1_Field := 16#0#; + JEOC1 : CSR_JEOC1_Field; -- Read-only. Injected channel Start flag of ADC 1 - JSTRT1 : CSR_JSTRT1_Field := 16#0#; + JSTRT1 : CSR_JSTRT1_Field; -- Read-only. Regular channel Start flag of ADC 1 - STRT1 : CSR_STRT1_Field := 16#0#; + STRT1 : CSR_STRT1_Field; -- Read-only. Overrun flag of ADC 1 - OVR1 : CSR_OVR1_Field := 16#0#; + OVR1 : CSR_OVR1_Field; -- unspecified Reserved_6_7 : STM32F40x.UInt2; -- Read-only. Analog watchdog flag of ADC 2 - AWD2 : CSR_AWD2_Field := 16#0#; + AWD2 : CSR_AWD2_Field; -- Read-only. End of conversion of ADC 2 - EOC2 : CSR_EOC2_Field := 16#0#; + EOC2 : CSR_EOC2_Field; -- Read-only. Injected channel end of conversion of ADC 2 - JEOC2 : CSR_JEOC2_Field := 16#0#; + JEOC2 : CSR_JEOC2_Field; -- Read-only. Injected channel Start flag of ADC 2 - JSTRT2 : CSR_JSTRT2_Field := 16#0#; + JSTRT2 : CSR_JSTRT2_Field; -- Read-only. Regular channel Start flag of ADC 2 - STRT2 : CSR_STRT2_Field := 16#0#; + STRT2 : CSR_STRT2_Field; -- Read-only. Overrun flag of ADC 2 - OVR2 : CSR_OVR2_Field := 16#0#; + OVR2 : CSR_OVR2_Field; -- unspecified Reserved_14_15 : STM32F40x.UInt2; -- Read-only. Analog watchdog flag of ADC 3 - AWD3 : CSR_AWD3_Field := 16#0#; + AWD3 : CSR_AWD3_Field; -- Read-only. End of conversion of ADC 3 - EOC3 : CSR_EOC3_Field := 16#0#; + EOC3 : CSR_EOC3_Field; -- Read-only. Injected channel end of conversion of ADC 3 - JEOC3 : CSR_JEOC3_Field := 16#0#; + JEOC3 : CSR_JEOC3_Field; -- Read-only. Injected channel Start flag of ADC 3 - JSTRT3 : CSR_JSTRT3_Field := 16#0#; + JSTRT3 : CSR_JSTRT3_Field; -- Read-only. Regular channel Start flag of ADC 3 - STRT3 : CSR_STRT3_Field := 16#0#; + STRT3 : CSR_STRT3_Field; -- Read-only. Overrun flag of ADC3 - OVR3 : CSR_OVR3_Field := 16#0#; + OVR3 : CSR_OVR3_Field; -- unspecified Reserved_22_31 : STM32F40x.UInt10; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CSR_Register use record AWD1 at 0 range 0 .. 0; @@ -664,10 +664,6 @@ package STM32F40x.ADC is Reserved_22_31 at 0 range 22 .. 31; end record; - ------------------ - -- CCR_Register -- - ------------------ - subtype CCR_MULT_Field is STM32F40x.UInt5; subtype CCR_DELAY_Field is STM32F40x.UInt4; subtype CCR_DDS_Field is STM32F40x.Bit; @@ -701,8 +697,7 @@ package STM32F40x.ADC is -- unspecified Reserved_24_31 : STM32F40x.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCR_Register use record MULT at 0 range 0 .. 4; @@ -718,12 +713,8 @@ package STM32F40x.ADC is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- CDR_Register -- - ------------------ - -- CDR_DATA array element - subtype CDR_DATA_Element is STM32F40x.Short; + subtype CDR_DATA_Element is STM32F40x.UInt16; -- CDR_DATA array type CDR_DATA_Field_Array is array (1 .. 2) of CDR_DATA_Element @@ -736,13 +727,13 @@ package STM32F40x.ADC is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : CDR_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for CDR_Register use record @@ -757,69 +748,89 @@ package STM32F40x.ADC is -- Analog-to-digital converter type ADC1_Peripheral is record -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- sample time register 1 - SMPR1 : SMPR1_Register; + SMPR1 : aliased SMPR1_Register; + pragma Volatile_Full_Access (SMPR1); -- sample time register 2 - SMPR2 : SMPR2_Register; + SMPR2 : aliased SMPR2_Register; + pragma Volatile_Full_Access (SMPR2); -- injected channel data offset register x - JOFR1 : JOFR_Register; + JOFR1 : aliased JOFR1_Register; + pragma Volatile_Full_Access (JOFR1); -- injected channel data offset register x - JOFR2 : JOFR_Register; + JOFR2 : aliased JOFR2_Register; + pragma Volatile_Full_Access (JOFR2); -- injected channel data offset register x - JOFR3 : JOFR_Register; + JOFR3 : aliased JOFR3_Register; + pragma Volatile_Full_Access (JOFR3); -- injected channel data offset register x - JOFR4 : JOFR_Register; + JOFR4 : aliased JOFR4_Register; + pragma Volatile_Full_Access (JOFR4); -- watchdog higher threshold register - HTR : HTR_Register; + HTR : aliased HTR_Register; + pragma Volatile_Full_Access (HTR); -- watchdog lower threshold register - LTR : LTR_Register; + LTR : aliased LTR_Register; + pragma Volatile_Full_Access (LTR); -- regular sequence register 1 - SQR1 : SQR1_Register; + SQR1 : aliased SQR1_Register; + pragma Volatile_Full_Access (SQR1); -- regular sequence register 2 - SQR2 : SQR_Register; + SQR2 : aliased SQR2_Register; + pragma Volatile_Full_Access (SQR2); -- regular sequence register 3 - SQR3 : SQR_Register; + SQR3 : aliased SQR3_Register; + pragma Volatile_Full_Access (SQR3); -- injected sequence register - JSQR : JSQR_Register; + JSQR : aliased JSQR_Register; + pragma Volatile_Full_Access (JSQR); -- injected data register x - JDR1 : JDR_Register; + JDR1 : aliased JDR_Register; + pragma Volatile_Full_Access (JDR1); -- injected data register x - JDR2 : JDR_Register; + JDR2 : aliased JDR_Register; + pragma Volatile_Full_Access (JDR2); -- injected data register x - JDR3 : JDR_Register; + JDR3 : aliased JDR_Register; + pragma Volatile_Full_Access (JDR3); -- injected data register x - JDR4 : JDR_Register; + JDR4 : aliased JDR_Register; + pragma Volatile_Full_Access (JDR4); -- regular data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); end record with Volatile; for ADC1_Peripheral use record - SR at 0 range 0 .. 31; - CR1 at 4 range 0 .. 31; - CR2 at 8 range 0 .. 31; - SMPR1 at 12 range 0 .. 31; - SMPR2 at 16 range 0 .. 31; - JOFR1 at 20 range 0 .. 31; - JOFR2 at 24 range 0 .. 31; - JOFR3 at 28 range 0 .. 31; - JOFR4 at 32 range 0 .. 31; - HTR at 36 range 0 .. 31; - LTR at 40 range 0 .. 31; - SQR1 at 44 range 0 .. 31; - SQR2 at 48 range 0 .. 31; - SQR3 at 52 range 0 .. 31; - JSQR at 56 range 0 .. 31; - JDR1 at 60 range 0 .. 31; - JDR2 at 64 range 0 .. 31; - JDR3 at 68 range 0 .. 31; - JDR4 at 72 range 0 .. 31; - DR at 76 range 0 .. 31; + SR at 16#0# range 0 .. 31; + CR1 at 16#4# range 0 .. 31; + CR2 at 16#8# range 0 .. 31; + SMPR1 at 16#C# range 0 .. 31; + SMPR2 at 16#10# range 0 .. 31; + JOFR1 at 16#14# range 0 .. 31; + JOFR2 at 16#18# range 0 .. 31; + JOFR3 at 16#1C# range 0 .. 31; + JOFR4 at 16#20# range 0 .. 31; + HTR at 16#24# range 0 .. 31; + LTR at 16#28# range 0 .. 31; + SQR1 at 16#2C# range 0 .. 31; + SQR2 at 16#30# range 0 .. 31; + SQR3 at 16#34# range 0 .. 31; + JSQR at 16#38# range 0 .. 31; + JDR1 at 16#3C# range 0 .. 31; + JDR2 at 16#40# range 0 .. 31; + JDR3 at 16#44# range 0 .. 31; + JDR4 at 16#48# range 0 .. 31; + DR at 16#4C# range 0 .. 31; end record; -- Analog-to-digital converter @@ -837,18 +848,21 @@ package STM32F40x.ADC is -- Common ADC registers type C_ADC_Peripheral is record -- ADC Common status register - CSR : CSR_Register; + CSR : aliased CSR_Register; + pragma Volatile_Full_Access (CSR); -- ADC common control register - CCR : CCR_Register; + CCR : aliased CCR_Register; + pragma Volatile_Full_Access (CCR); -- ADC common regular data register for dual and triple modes - CDR : CDR_Register; + CDR : aliased CDR_Register; + pragma Volatile_Full_Access (CDR); end record with Volatile; for C_ADC_Peripheral use record - CSR at 0 range 0 .. 31; - CCR at 4 range 0 .. 31; - CDR at 8 range 0 .. 31; + CSR at 16#0# range 0 .. 31; + CCR at 16#4# range 0 .. 31; + CDR at 16#8# range 0 .. 31; end record; -- Common ADC registers diff --git a/stm32f4/stm32f40x/stm32f40x-can.ads b/stm32f4/stm32f40x/stm32f40x-can.ads index 5c0146f..fa5bb50 100644 --- a/stm32f4/stm32f40x/stm32f40x-can.ads +++ b/stm32f4/stm32f40x/stm32f40x-can.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.CAN is -- Registers -- --------------- - ------------------ - -- MCR_Register -- - ------------------ - subtype MCR_INRQ_Field is STM32F40x.Bit; subtype MCR_SLEEP_Field is STM32F40x.Bit; subtype MCR_TXFP_Field is STM32F40x.Bit; @@ -55,8 +52,7 @@ package STM32F40x.CAN is -- unspecified Reserved_17_31 : STM32F40x.UInt15 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MCR_Register use record INRQ at 0 range 0 .. 0; @@ -73,10 +69,6 @@ package STM32F40x.CAN is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------ - -- MSR_Register -- - ------------------ - subtype MSR_INAK_Field is STM32F40x.Bit; subtype MSR_SLAK_Field is STM32F40x.Bit; subtype MSR_ERRI_Field is STM32F40x.Bit; @@ -112,8 +104,7 @@ package STM32F40x.CAN is -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MSR_Register use record INAK at 0 range 0 .. 0; @@ -129,10 +120,6 @@ package STM32F40x.CAN is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- TSR_Register -- - ------------------ - subtype TSR_RQCP0_Field is STM32F40x.Bit; subtype TSR_TXOK0_Field is STM32F40x.Bit; subtype TSR_ALST0_Field is STM32F40x.Bit; @@ -149,11 +136,6 @@ package STM32F40x.CAN is subtype TSR_TERR2_Field is STM32F40x.Bit; subtype TSR_ABRQ2_Field is STM32F40x.Bit; subtype TSR_CODE_Field is STM32F40x.UInt2; - - ------------- - -- TSR.TME -- - ------------- - -- TSR_TME array element subtype TSR_TME_Element is STM32F40x.Bit; @@ -181,10 +163,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 2; end record; - ------------- - -- TSR.LOW -- - ------------- - -- TSR_LOW array element subtype TSR_LOW_Element is STM32F40x.Bit; @@ -257,8 +235,7 @@ package STM32F40x.CAN is -- Read-only. Lowest priority flag for mailbox 0 LOW : TSR_LOW_Field := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TSR_Register use record RQCP0 at 0 range 0 .. 0; @@ -284,10 +261,6 @@ package STM32F40x.CAN is LOW at 0 range 29 .. 31; end record; - ------------------- - -- RF0R_Register -- - ------------------- - subtype RF0R_FMP0_Field is STM32F40x.UInt2; subtype RF0R_FULL0_Field is STM32F40x.Bit; subtype RF0R_FOVR0_Field is STM32F40x.Bit; @@ -308,8 +281,7 @@ package STM32F40x.CAN is -- unspecified Reserved_6_31 : STM32F40x.UInt26 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RF0R_Register use record FMP0 at 0 range 0 .. 1; @@ -320,10 +292,6 @@ package STM32F40x.CAN is Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------- - -- RF1R_Register -- - ------------------- - subtype RF1R_FMP1_Field is STM32F40x.UInt2; subtype RF1R_FULL1_Field is STM32F40x.Bit; subtype RF1R_FOVR1_Field is STM32F40x.Bit; @@ -344,8 +312,7 @@ package STM32F40x.CAN is -- unspecified Reserved_6_31 : STM32F40x.UInt26 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RF1R_Register use record FMP1 at 0 range 0 .. 1; @@ -356,10 +323,6 @@ package STM32F40x.CAN is Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - subtype IER_TMEIE_Field is STM32F40x.Bit; subtype IER_FMPIE0_Field is STM32F40x.Bit; subtype IER_FFIE0_Field is STM32F40x.Bit; @@ -412,8 +375,7 @@ package STM32F40x.CAN is -- unspecified Reserved_18_31 : STM32F40x.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IER_Register use record TMEIE at 0 range 0 .. 0; @@ -435,10 +397,6 @@ package STM32F40x.CAN is Reserved_18_31 at 0 range 18 .. 31; end record; - ------------------ - -- ESR_Register -- - ------------------ - subtype ESR_EWGF_Field is STM32F40x.Bit; subtype ESR_EPVF_Field is STM32F40x.Bit; subtype ESR_BOFF_Field is STM32F40x.Bit; @@ -465,8 +423,7 @@ package STM32F40x.CAN is -- Read-only. REC REC : ESR_REC_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ESR_Register use record EWGF at 0 range 0 .. 0; @@ -479,10 +436,6 @@ package STM32F40x.CAN is REC at 0 range 24 .. 31; end record; - ------------------ - -- BTR_Register -- - ------------------ - subtype BTR_BRP_Field is STM32F40x.UInt10; subtype BTR_TS1_Field is STM32F40x.UInt4; subtype BTR_TS2_Field is STM32F40x.UInt3; @@ -511,8 +464,7 @@ package STM32F40x.CAN is -- SILM SILM : BTR_SILM_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BTR_Register use record BRP at 0 range 0 .. 9; @@ -526,10 +478,6 @@ package STM32F40x.CAN is SILM at 0 range 31 .. 31; end record; - ------------------- - -- TI0R_Register -- - ------------------- - subtype TI0R_TXRQ_Field is STM32F40x.Bit; subtype TI0R_RTR_Field is STM32F40x.Bit; subtype TI0R_IDE_Field is STM32F40x.Bit; @@ -549,8 +497,7 @@ package STM32F40x.CAN is -- STID STID : TI0R_STID_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TI0R_Register use record TXRQ at 0 range 0 .. 0; @@ -560,13 +507,9 @@ package STM32F40x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- TDT0R_Register -- - -------------------- - subtype TDT0R_DLC_Field is STM32F40x.UInt4; subtype TDT0R_TGT_Field is STM32F40x.Bit; - subtype TDT0R_TIME_Field is STM32F40x.Short; + subtype TDT0R_TIME_Field is STM32F40x.UInt16; -- mailbox data length control and time stamp register type TDT0R_Register is record @@ -581,8 +524,7 @@ package STM32F40x.CAN is -- TIME TIME : TDT0R_TIME_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TDT0R_Register use record DLC at 0 range 0 .. 3; @@ -592,10 +534,6 @@ package STM32F40x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- TDL0R_Register -- - -------------------- - -- TDL0R_DATA array element subtype TDL0R_DATA_Element is STM32F40x.Byte; @@ -610,13 +548,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : TDL0R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDL0R_Register use record @@ -624,10 +562,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- TDH0R_Register -- - -------------------- - -- TDH0R_DATA array element subtype TDH0R_DATA_Element is STM32F40x.Byte; @@ -642,13 +576,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : TDH0R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDH0R_Register use record @@ -656,10 +590,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- TI1R_Register -- - ------------------- - subtype TI1R_TXRQ_Field is STM32F40x.Bit; subtype TI1R_RTR_Field is STM32F40x.Bit; subtype TI1R_IDE_Field is STM32F40x.Bit; @@ -679,8 +609,7 @@ package STM32F40x.CAN is -- STID STID : TI1R_STID_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TI1R_Register use record TXRQ at 0 range 0 .. 0; @@ -690,13 +619,9 @@ package STM32F40x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- TDT1R_Register -- - -------------------- - subtype TDT1R_DLC_Field is STM32F40x.UInt4; subtype TDT1R_TGT_Field is STM32F40x.Bit; - subtype TDT1R_TIME_Field is STM32F40x.Short; + subtype TDT1R_TIME_Field is STM32F40x.UInt16; -- mailbox data length control and time stamp register type TDT1R_Register is record @@ -711,8 +636,7 @@ package STM32F40x.CAN is -- TIME TIME : TDT1R_TIME_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TDT1R_Register use record DLC at 0 range 0 .. 3; @@ -722,10 +646,6 @@ package STM32F40x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- TDL1R_Register -- - -------------------- - -- TDL1R_DATA array element subtype TDL1R_DATA_Element is STM32F40x.Byte; @@ -740,13 +660,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : TDL1R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDL1R_Register use record @@ -754,10 +674,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- TDH1R_Register -- - -------------------- - -- TDH1R_DATA array element subtype TDH1R_DATA_Element is STM32F40x.Byte; @@ -772,13 +688,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : TDH1R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDH1R_Register use record @@ -786,10 +702,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- TI2R_Register -- - ------------------- - subtype TI2R_TXRQ_Field is STM32F40x.Bit; subtype TI2R_RTR_Field is STM32F40x.Bit; subtype TI2R_IDE_Field is STM32F40x.Bit; @@ -809,8 +721,7 @@ package STM32F40x.CAN is -- STID STID : TI2R_STID_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TI2R_Register use record TXRQ at 0 range 0 .. 0; @@ -820,13 +731,9 @@ package STM32F40x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- TDT2R_Register -- - -------------------- - subtype TDT2R_DLC_Field is STM32F40x.UInt4; subtype TDT2R_TGT_Field is STM32F40x.Bit; - subtype TDT2R_TIME_Field is STM32F40x.Short; + subtype TDT2R_TIME_Field is STM32F40x.UInt16; -- mailbox data length control and time stamp register type TDT2R_Register is record @@ -841,8 +748,7 @@ package STM32F40x.CAN is -- TIME TIME : TDT2R_TIME_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TDT2R_Register use record DLC at 0 range 0 .. 3; @@ -852,10 +758,6 @@ package STM32F40x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- TDL2R_Register -- - -------------------- - -- TDL2R_DATA array element subtype TDL2R_DATA_Element is STM32F40x.Byte; @@ -870,13 +772,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : TDL2R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDL2R_Register use record @@ -884,10 +786,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- TDH2R_Register -- - -------------------- - -- TDH2R_DATA array element subtype TDH2R_DATA_Element is STM32F40x.Byte; @@ -902,13 +800,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : TDH2R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDH2R_Register use record @@ -916,10 +814,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- RI0R_Register -- - ------------------- - subtype RI0R_RTR_Field is STM32F40x.Bit; subtype RI0R_IDE_Field is STM32F40x.Bit; subtype RI0R_EXID_Field is STM32F40x.UInt18; @@ -930,16 +824,15 @@ package STM32F40x.CAN is -- unspecified Reserved_0_0 : STM32F40x.Bit; -- Read-only. RTR - RTR : RI0R_RTR_Field := 16#0#; + RTR : RI0R_RTR_Field; -- Read-only. IDE - IDE : RI0R_IDE_Field := 16#0#; + IDE : RI0R_IDE_Field; -- Read-only. EXID - EXID : RI0R_EXID_Field := 16#0#; + EXID : RI0R_EXID_Field; -- Read-only. STID - STID : RI0R_STID_Field := 16#0#; + STID : RI0R_STID_Field; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RI0R_Register use record Reserved_0_0 at 0 range 0 .. 0; @@ -949,27 +842,22 @@ package STM32F40x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- RDT0R_Register -- - -------------------- - subtype RDT0R_DLC_Field is STM32F40x.UInt4; subtype RDT0R_FMI_Field is STM32F40x.Byte; - subtype RDT0R_TIME_Field is STM32F40x.Short; + subtype RDT0R_TIME_Field is STM32F40x.UInt16; -- mailbox data high register type RDT0R_Register is record -- Read-only. DLC - DLC : RDT0R_DLC_Field := 16#0#; + DLC : RDT0R_DLC_Field; -- unspecified Reserved_4_7 : STM32F40x.UInt4; -- Read-only. FMI - FMI : RDT0R_FMI_Field := 16#0#; + FMI : RDT0R_FMI_Field; -- Read-only. TIME - TIME : RDT0R_TIME_Field := 16#0#; + TIME : RDT0R_TIME_Field; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RDT0R_Register use record DLC at 0 range 0 .. 3; @@ -978,10 +866,6 @@ package STM32F40x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- RDL0R_Register -- - -------------------- - -- RDL0R_DATA array element subtype RDL0R_DATA_Element is STM32F40x.Byte; @@ -996,13 +880,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : RDL0R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for RDL0R_Register use record @@ -1010,10 +894,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- RDH0R_Register -- - -------------------- - -- RDH0R_DATA array element subtype RDH0R_DATA_Element is STM32F40x.Byte; @@ -1028,13 +908,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : RDH0R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for RDH0R_Register use record @@ -1042,10 +922,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- RI1R_Register -- - ------------------- - subtype RI1R_RTR_Field is STM32F40x.Bit; subtype RI1R_IDE_Field is STM32F40x.Bit; subtype RI1R_EXID_Field is STM32F40x.UInt18; @@ -1056,16 +932,15 @@ package STM32F40x.CAN is -- unspecified Reserved_0_0 : STM32F40x.Bit; -- Read-only. RTR - RTR : RI1R_RTR_Field := 16#0#; + RTR : RI1R_RTR_Field; -- Read-only. IDE - IDE : RI1R_IDE_Field := 16#0#; + IDE : RI1R_IDE_Field; -- Read-only. EXID - EXID : RI1R_EXID_Field := 16#0#; + EXID : RI1R_EXID_Field; -- Read-only. STID - STID : RI1R_STID_Field := 16#0#; + STID : RI1R_STID_Field; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RI1R_Register use record Reserved_0_0 at 0 range 0 .. 0; @@ -1075,27 +950,22 @@ package STM32F40x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- RDT1R_Register -- - -------------------- - subtype RDT1R_DLC_Field is STM32F40x.UInt4; subtype RDT1R_FMI_Field is STM32F40x.Byte; - subtype RDT1R_TIME_Field is STM32F40x.Short; + subtype RDT1R_TIME_Field is STM32F40x.UInt16; -- mailbox data high register type RDT1R_Register is record -- Read-only. DLC - DLC : RDT1R_DLC_Field := 16#0#; + DLC : RDT1R_DLC_Field; -- unspecified Reserved_4_7 : STM32F40x.UInt4; -- Read-only. FMI - FMI : RDT1R_FMI_Field := 16#0#; + FMI : RDT1R_FMI_Field; -- Read-only. TIME - TIME : RDT1R_TIME_Field := 16#0#; + TIME : RDT1R_TIME_Field; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RDT1R_Register use record DLC at 0 range 0 .. 3; @@ -1104,10 +974,6 @@ package STM32F40x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- RDL1R_Register -- - -------------------- - -- RDL1R_DATA array element subtype RDL1R_DATA_Element is STM32F40x.Byte; @@ -1122,13 +988,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : RDL1R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for RDL1R_Register use record @@ -1136,10 +1002,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- RDH1R_Register -- - -------------------- - -- RDH1R_DATA array element subtype RDH1R_DATA_Element is STM32F40x.Byte; @@ -1154,13 +1016,13 @@ package STM32F40x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- DATA as an array Arr : RDH1R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for RDH1R_Register use record @@ -1168,10 +1030,6 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- FMR_Register -- - ------------------ - subtype FMR_FINIT_Field is STM32F40x.Bit; subtype FMR_CAN2SB_Field is STM32F40x.UInt6; @@ -1186,8 +1044,7 @@ package STM32F40x.CAN is -- unspecified Reserved_14_31 : STM32F40x.UInt18 := 16#A870#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FMR_Register use record FINIT at 0 range 0 .. 0; @@ -1196,14 +1053,6 @@ package STM32F40x.CAN is Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------- - -- FM1R_Register -- - ------------------- - - -------------- - -- FM1R.FBM -- - -------------- - -- FM1R_FBM array element subtype FM1R_FBM_Element is STM32F40x.Bit; @@ -1238,22 +1087,13 @@ package STM32F40x.CAN is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FM1R_Register use record FBM at 0 range 0 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- FS1R_Register -- - ------------------- - - -------------- - -- FS1R.FSC -- - -------------- - -- FS1R_FSC array element subtype FS1R_FSC_Element is STM32F40x.Bit; @@ -1288,22 +1128,13 @@ package STM32F40x.CAN is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FS1R_Register use record FSC at 0 range 0 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - -------------------- - -- FFA1R_Register -- - -------------------- - - --------------- - -- FFA1R.FFA -- - --------------- - -- FFA1R_FFA array element subtype FFA1R_FFA_Element is STM32F40x.Bit; @@ -1338,22 +1169,13 @@ package STM32F40x.CAN is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FFA1R_Register use record FFA at 0 range 0 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- FA1R_Register -- - ------------------- - - --------------- - -- FA1R.FACT -- - --------------- - -- FA1R_FACT array element subtype FA1R_FACT_Element is STM32F40x.Bit; @@ -1388,23 +1210,18 @@ package STM32F40x.CAN is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FA1R_Register use record FACT at 0 range 0 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------ - -- F0R_Register -- - ------------------ - - -- F0R1_FB array element - subtype F0R1_FB_Element is STM32F40x.Bit; + -- F0R_FB array element + subtype F0R_FB_Element is STM32F40x.Bit; - -- F0R1_FB array - type F0R1_FB_Field_Array is array (0 .. 31) of F0R1_FB_Element + -- F0R_FB array + type F0R_FB_Field_Array is array (0 .. 31) of F0R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 0 register 1 @@ -1414,13 +1231,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F0R1_FB_Field_Array; + Arr : F0R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F0R_Register use record @@ -1428,15 +1245,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F1R_Register -- - ------------------ + -- F1R_FB array element + subtype F1R_FB_Element is STM32F40x.Bit; - -- F1R1_FB array element - subtype F1R1_FB_Element is STM32F40x.Bit; - - -- F1R1_FB array - type F1R1_FB_Field_Array is array (0 .. 31) of F1R1_FB_Element + -- F1R_FB array + type F1R_FB_Field_Array is array (0 .. 31) of F1R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 1 register 1 @@ -1446,13 +1259,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F1R1_FB_Field_Array; + Arr : F1R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F1R_Register use record @@ -1460,15 +1273,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F2R_Register -- - ------------------ - - -- F2R1_FB array element - subtype F2R1_FB_Element is STM32F40x.Bit; + -- F2R_FB array element + subtype F2R_FB_Element is STM32F40x.Bit; - -- F2R1_FB array - type F2R1_FB_Field_Array is array (0 .. 31) of F2R1_FB_Element + -- F2R_FB array + type F2R_FB_Field_Array is array (0 .. 31) of F2R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 2 register 1 @@ -1478,13 +1287,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F2R1_FB_Field_Array; + Arr : F2R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F2R_Register use record @@ -1492,15 +1301,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F3R_Register -- - ------------------ - - -- F3R1_FB array element - subtype F3R1_FB_Element is STM32F40x.Bit; + -- F3R_FB array element + subtype F3R_FB_Element is STM32F40x.Bit; - -- F3R1_FB array - type F3R1_FB_Field_Array is array (0 .. 31) of F3R1_FB_Element + -- F3R_FB array + type F3R_FB_Field_Array is array (0 .. 31) of F3R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 3 register 1 @@ -1510,13 +1315,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F3R1_FB_Field_Array; + Arr : F3R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F3R_Register use record @@ -1524,15 +1329,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F4R_Register -- - ------------------ + -- F4R_FB array element + subtype F4R_FB_Element is STM32F40x.Bit; - -- F4R1_FB array element - subtype F4R1_FB_Element is STM32F40x.Bit; - - -- F4R1_FB array - type F4R1_FB_Field_Array is array (0 .. 31) of F4R1_FB_Element + -- F4R_FB array + type F4R_FB_Field_Array is array (0 .. 31) of F4R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 4 register 1 @@ -1542,13 +1343,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F4R1_FB_Field_Array; + Arr : F4R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F4R_Register use record @@ -1556,15 +1357,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F5R_Register -- - ------------------ - - -- F5R1_FB array element - subtype F5R1_FB_Element is STM32F40x.Bit; + -- F5R_FB array element + subtype F5R_FB_Element is STM32F40x.Bit; - -- F5R1_FB array - type F5R1_FB_Field_Array is array (0 .. 31) of F5R1_FB_Element + -- F5R_FB array + type F5R_FB_Field_Array is array (0 .. 31) of F5R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 5 register 1 @@ -1574,13 +1371,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F5R1_FB_Field_Array; + Arr : F5R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F5R_Register use record @@ -1588,15 +1385,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F6R_Register -- - ------------------ - - -- F6R1_FB array element - subtype F6R1_FB_Element is STM32F40x.Bit; + -- F6R_FB array element + subtype F6R_FB_Element is STM32F40x.Bit; - -- F6R1_FB array - type F6R1_FB_Field_Array is array (0 .. 31) of F6R1_FB_Element + -- F6R_FB array + type F6R_FB_Field_Array is array (0 .. 31) of F6R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 6 register 1 @@ -1606,13 +1399,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F6R1_FB_Field_Array; + Arr : F6R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F6R_Register use record @@ -1620,15 +1413,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F7R_Register -- - ------------------ + -- F7R_FB array element + subtype F7R_FB_Element is STM32F40x.Bit; - -- F7R1_FB array element - subtype F7R1_FB_Element is STM32F40x.Bit; - - -- F7R1_FB array - type F7R1_FB_Field_Array is array (0 .. 31) of F7R1_FB_Element + -- F7R_FB array + type F7R_FB_Field_Array is array (0 .. 31) of F7R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 7 register 1 @@ -1638,13 +1427,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F7R1_FB_Field_Array; + Arr : F7R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F7R_Register use record @@ -1652,15 +1441,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F8R_Register -- - ------------------ - - -- F8R1_FB array element - subtype F8R1_FB_Element is STM32F40x.Bit; + -- F8R_FB array element + subtype F8R_FB_Element is STM32F40x.Bit; - -- F8R1_FB array - type F8R1_FB_Field_Array is array (0 .. 31) of F8R1_FB_Element + -- F8R_FB array + type F8R_FB_Field_Array is array (0 .. 31) of F8R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 8 register 1 @@ -1670,13 +1455,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F8R1_FB_Field_Array; + Arr : F8R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F8R_Register use record @@ -1684,15 +1469,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F9R_Register -- - ------------------ - - -- F9R1_FB array element - subtype F9R1_FB_Element is STM32F40x.Bit; + -- F9R_FB array element + subtype F9R_FB_Element is STM32F40x.Bit; - -- F9R1_FB array - type F9R1_FB_Field_Array is array (0 .. 31) of F9R1_FB_Element + -- F9R_FB array + type F9R_FB_Field_Array is array (0 .. 31) of F9R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 9 register 1 @@ -1702,13 +1483,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F9R1_FB_Field_Array; + Arr : F9R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F9R_Register use record @@ -1716,15 +1497,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F10R_Register -- - ------------------- + -- F10R_FB array element + subtype F10R_FB_Element is STM32F40x.Bit; - -- F10R1_FB array element - subtype F10R1_FB_Element is STM32F40x.Bit; - - -- F10R1_FB array - type F10R1_FB_Field_Array is array (0 .. 31) of F10R1_FB_Element + -- F10R_FB array + type F10R_FB_Field_Array is array (0 .. 31) of F10R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 10 register 1 @@ -1734,13 +1511,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F10R1_FB_Field_Array; + Arr : F10R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F10R_Register use record @@ -1748,15 +1525,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F11R_Register -- - ------------------- - - -- F11R1_FB array element - subtype F11R1_FB_Element is STM32F40x.Bit; + -- F11R_FB array element + subtype F11R_FB_Element is STM32F40x.Bit; - -- F11R1_FB array - type F11R1_FB_Field_Array is array (0 .. 31) of F11R1_FB_Element + -- F11R_FB array + type F11R_FB_Field_Array is array (0 .. 31) of F11R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 11 register 1 @@ -1766,13 +1539,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F11R1_FB_Field_Array; + Arr : F11R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F11R_Register use record @@ -1780,15 +1553,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F12R_Register -- - ------------------- - - -- F12R1_FB array element - subtype F12R1_FB_Element is STM32F40x.Bit; + -- F12R_FB array element + subtype F12R_FB_Element is STM32F40x.Bit; - -- F12R1_FB array - type F12R1_FB_Field_Array is array (0 .. 31) of F12R1_FB_Element + -- F12R_FB array + type F12R_FB_Field_Array is array (0 .. 31) of F12R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 4 register 1 @@ -1798,13 +1567,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F12R1_FB_Field_Array; + Arr : F12R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F12R_Register use record @@ -1812,15 +1581,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F13R_Register -- - ------------------- + -- F13R_FB array element + subtype F13R_FB_Element is STM32F40x.Bit; - -- F13R1_FB array element - subtype F13R1_FB_Element is STM32F40x.Bit; - - -- F13R1_FB array - type F13R1_FB_Field_Array is array (0 .. 31) of F13R1_FB_Element + -- F13R_FB array + type F13R_FB_Field_Array is array (0 .. 31) of F13R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 13 register 1 @@ -1830,13 +1595,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F13R1_FB_Field_Array; + Arr : F13R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F13R_Register use record @@ -1844,15 +1609,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F14R_Register -- - ------------------- - - -- F14R1_FB array element - subtype F14R1_FB_Element is STM32F40x.Bit; + -- F14R_FB array element + subtype F14R_FB_Element is STM32F40x.Bit; - -- F14R1_FB array - type F14R1_FB_Field_Array is array (0 .. 31) of F14R1_FB_Element + -- F14R_FB array + type F14R_FB_Field_Array is array (0 .. 31) of F14R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 14 register 1 @@ -1862,13 +1623,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F14R1_FB_Field_Array; + Arr : F14R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F14R_Register use record @@ -1876,15 +1637,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F15R_Register -- - ------------------- - - -- F15R1_FB array element - subtype F15R1_FB_Element is STM32F40x.Bit; + -- F15R_FB array element + subtype F15R_FB_Element is STM32F40x.Bit; - -- F15R1_FB array - type F15R1_FB_Field_Array is array (0 .. 31) of F15R1_FB_Element + -- F15R_FB array + type F15R_FB_Field_Array is array (0 .. 31) of F15R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 15 register 1 @@ -1894,13 +1651,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F15R1_FB_Field_Array; + Arr : F15R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F15R_Register use record @@ -1908,15 +1665,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F16R_Register -- - ------------------- + -- F16R_FB array element + subtype F16R_FB_Element is STM32F40x.Bit; - -- F16R1_FB array element - subtype F16R1_FB_Element is STM32F40x.Bit; - - -- F16R1_FB array - type F16R1_FB_Field_Array is array (0 .. 31) of F16R1_FB_Element + -- F16R_FB array + type F16R_FB_Field_Array is array (0 .. 31) of F16R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 16 register 1 @@ -1926,13 +1679,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F16R1_FB_Field_Array; + Arr : F16R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F16R_Register use record @@ -1940,15 +1693,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F17R_Register -- - ------------------- - - -- F17R1_FB array element - subtype F17R1_FB_Element is STM32F40x.Bit; + -- F17R_FB array element + subtype F17R_FB_Element is STM32F40x.Bit; - -- F17R1_FB array - type F17R1_FB_Field_Array is array (0 .. 31) of F17R1_FB_Element + -- F17R_FB array + type F17R_FB_Field_Array is array (0 .. 31) of F17R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 17 register 1 @@ -1958,13 +1707,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F17R1_FB_Field_Array; + Arr : F17R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F17R_Register use record @@ -1972,15 +1721,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F18R_Register -- - ------------------- - - -- F18R1_FB array element - subtype F18R1_FB_Element is STM32F40x.Bit; + -- F18R_FB array element + subtype F18R_FB_Element is STM32F40x.Bit; - -- F18R1_FB array - type F18R1_FB_Field_Array is array (0 .. 31) of F18R1_FB_Element + -- F18R_FB array + type F18R_FB_Field_Array is array (0 .. 31) of F18R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 18 register 1 @@ -1990,13 +1735,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F18R1_FB_Field_Array; + Arr : F18R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F18R_Register use record @@ -2004,15 +1749,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F19R_Register -- - ------------------- + -- F19R_FB array element + subtype F19R_FB_Element is STM32F40x.Bit; - -- F19R1_FB array element - subtype F19R1_FB_Element is STM32F40x.Bit; - - -- F19R1_FB array - type F19R1_FB_Field_Array is array (0 .. 31) of F19R1_FB_Element + -- F19R_FB array + type F19R_FB_Field_Array is array (0 .. 31) of F19R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 19 register 1 @@ -2022,13 +1763,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F19R1_FB_Field_Array; + Arr : F19R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F19R_Register use record @@ -2036,15 +1777,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F20R_Register -- - ------------------- - - -- F20R1_FB array element - subtype F20R1_FB_Element is STM32F40x.Bit; + -- F20R_FB array element + subtype F20R_FB_Element is STM32F40x.Bit; - -- F20R1_FB array - type F20R1_FB_Field_Array is array (0 .. 31) of F20R1_FB_Element + -- F20R_FB array + type F20R_FB_Field_Array is array (0 .. 31) of F20R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 20 register 1 @@ -2054,13 +1791,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F20R1_FB_Field_Array; + Arr : F20R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F20R_Register use record @@ -2068,15 +1805,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F21R_Register -- - ------------------- - - -- F21R1_FB array element - subtype F21R1_FB_Element is STM32F40x.Bit; + -- F21R_FB array element + subtype F21R_FB_Element is STM32F40x.Bit; - -- F21R1_FB array - type F21R1_FB_Field_Array is array (0 .. 31) of F21R1_FB_Element + -- F21R_FB array + type F21R_FB_Field_Array is array (0 .. 31) of F21R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 21 register 1 @@ -2086,13 +1819,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F21R1_FB_Field_Array; + Arr : F21R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F21R_Register use record @@ -2100,15 +1833,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F22R_Register -- - ------------------- + -- F22R_FB array element + subtype F22R_FB_Element is STM32F40x.Bit; - -- F22R1_FB array element - subtype F22R1_FB_Element is STM32F40x.Bit; - - -- F22R1_FB array - type F22R1_FB_Field_Array is array (0 .. 31) of F22R1_FB_Element + -- F22R_FB array + type F22R_FB_Field_Array is array (0 .. 31) of F22R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 22 register 1 @@ -2118,13 +1847,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F22R1_FB_Field_Array; + Arr : F22R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F22R_Register use record @@ -2132,15 +1861,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F23R_Register -- - ------------------- - - -- F23R1_FB array element - subtype F23R1_FB_Element is STM32F40x.Bit; + -- F23R_FB array element + subtype F23R_FB_Element is STM32F40x.Bit; - -- F23R1_FB array - type F23R1_FB_Field_Array is array (0 .. 31) of F23R1_FB_Element + -- F23R_FB array + type F23R_FB_Field_Array is array (0 .. 31) of F23R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 23 register 1 @@ -2150,13 +1875,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F23R1_FB_Field_Array; + Arr : F23R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F23R_Register use record @@ -2164,15 +1889,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F24R_Register -- - ------------------- - - -- F24R1_FB array element - subtype F24R1_FB_Element is STM32F40x.Bit; + -- F24R_FB array element + subtype F24R_FB_Element is STM32F40x.Bit; - -- F24R1_FB array - type F24R1_FB_Field_Array is array (0 .. 31) of F24R1_FB_Element + -- F24R_FB array + type F24R_FB_Field_Array is array (0 .. 31) of F24R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 24 register 1 @@ -2182,13 +1903,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F24R1_FB_Field_Array; + Arr : F24R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F24R_Register use record @@ -2196,15 +1917,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F25R_Register -- - ------------------- + -- F25R_FB array element + subtype F25R_FB_Element is STM32F40x.Bit; - -- F25R1_FB array element - subtype F25R1_FB_Element is STM32F40x.Bit; - - -- F25R1_FB array - type F25R1_FB_Field_Array is array (0 .. 31) of F25R1_FB_Element + -- F25R_FB array + type F25R_FB_Field_Array is array (0 .. 31) of F25R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 25 register 1 @@ -2214,13 +1931,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F25R1_FB_Field_Array; + Arr : F25R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F25R_Register use record @@ -2228,15 +1945,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F26R_Register -- - ------------------- - - -- F26R1_FB array element - subtype F26R1_FB_Element is STM32F40x.Bit; + -- F26R_FB array element + subtype F26R_FB_Element is STM32F40x.Bit; - -- F26R1_FB array - type F26R1_FB_Field_Array is array (0 .. 31) of F26R1_FB_Element + -- F26R_FB array + type F26R_FB_Field_Array is array (0 .. 31) of F26R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 26 register 1 @@ -2246,13 +1959,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F26R1_FB_Field_Array; + Arr : F26R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F26R_Register use record @@ -2260,15 +1973,11 @@ package STM32F40x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F27R_Register -- - ------------------- - - -- F27R1_FB array element - subtype F27R1_FB_Element is STM32F40x.Bit; + -- F27R_FB array element + subtype F27R_FB_Element is STM32F40x.Bit; - -- F27R1_FB array - type F27R1_FB_Field_Array is array (0 .. 31) of F27R1_FB_Element + -- F27R_FB array + type F27R_FB_Field_Array is array (0 .. 31) of F27R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 27 register 1 @@ -2278,13 +1987,13 @@ package STM32F40x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- FB as an array - Arr : F27R1_FB_Field_Array; + Arr : F27R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F27R_Register use record @@ -2299,276 +2008,365 @@ package STM32F40x.CAN is -- Controller area network type CAN_Peripheral is record -- master control register - MCR : MCR_Register; + MCR : aliased MCR_Register; + pragma Volatile_Full_Access (MCR); -- master status register - MSR : MSR_Register; + MSR : aliased MSR_Register; + pragma Volatile_Full_Access (MSR); -- transmit status register - TSR : TSR_Register; + TSR : aliased TSR_Register; + pragma Volatile_Full_Access (TSR); -- receive FIFO 0 register - RF0R : RF0R_Register; + RF0R : aliased RF0R_Register; + pragma Volatile_Full_Access (RF0R); -- receive FIFO 1 register - RF1R : RF1R_Register; + RF1R : aliased RF1R_Register; + pragma Volatile_Full_Access (RF1R); -- interrupt enable register - IER : IER_Register; + IER : aliased IER_Register; + pragma Volatile_Full_Access (IER); -- interrupt enable register - ESR : ESR_Register; + ESR : aliased ESR_Register; + pragma Volatile_Full_Access (ESR); -- bit timing register - BTR : BTR_Register; + BTR : aliased BTR_Register; + pragma Volatile_Full_Access (BTR); -- TX mailbox identifier register - TI0R : TI0R_Register; + TI0R : aliased TI0R_Register; + pragma Volatile_Full_Access (TI0R); -- mailbox data length control and time stamp register - TDT0R : TDT0R_Register; + TDT0R : aliased TDT0R_Register; + pragma Volatile_Full_Access (TDT0R); -- mailbox data low register - TDL0R : TDL0R_Register; + TDL0R : aliased TDL0R_Register; + pragma Volatile_Full_Access (TDL0R); -- mailbox data high register - TDH0R : TDH0R_Register; + TDH0R : aliased TDH0R_Register; + pragma Volatile_Full_Access (TDH0R); -- mailbox identifier register - TI1R : TI1R_Register; + TI1R : aliased TI1R_Register; + pragma Volatile_Full_Access (TI1R); -- mailbox data length control and time stamp register - TDT1R : TDT1R_Register; + TDT1R : aliased TDT1R_Register; + pragma Volatile_Full_Access (TDT1R); -- mailbox data low register - TDL1R : TDL1R_Register; + TDL1R : aliased TDL1R_Register; + pragma Volatile_Full_Access (TDL1R); -- mailbox data high register - TDH1R : TDH1R_Register; + TDH1R : aliased TDH1R_Register; + pragma Volatile_Full_Access (TDH1R); -- mailbox identifier register - TI2R : TI2R_Register; + TI2R : aliased TI2R_Register; + pragma Volatile_Full_Access (TI2R); -- mailbox data length control and time stamp register - TDT2R : TDT2R_Register; + TDT2R : aliased TDT2R_Register; + pragma Volatile_Full_Access (TDT2R); -- mailbox data low register - TDL2R : TDL2R_Register; + TDL2R : aliased TDL2R_Register; + pragma Volatile_Full_Access (TDL2R); -- mailbox data high register - TDH2R : TDH2R_Register; + TDH2R : aliased TDH2R_Register; + pragma Volatile_Full_Access (TDH2R); -- receive FIFO mailbox identifier register - RI0R : RI0R_Register; + RI0R : aliased RI0R_Register; + pragma Volatile_Full_Access (RI0R); -- mailbox data high register - RDT0R : RDT0R_Register; + RDT0R : aliased RDT0R_Register; + pragma Volatile_Full_Access (RDT0R); -- mailbox data high register - RDL0R : RDL0R_Register; + RDL0R : aliased RDL0R_Register; + pragma Volatile_Full_Access (RDL0R); -- receive FIFO mailbox data high register - RDH0R : RDH0R_Register; + RDH0R : aliased RDH0R_Register; + pragma Volatile_Full_Access (RDH0R); -- mailbox data high register - RI1R : RI1R_Register; + RI1R : aliased RI1R_Register; + pragma Volatile_Full_Access (RI1R); -- mailbox data high register - RDT1R : RDT1R_Register; + RDT1R : aliased RDT1R_Register; + pragma Volatile_Full_Access (RDT1R); -- mailbox data high register - RDL1R : RDL1R_Register; + RDL1R : aliased RDL1R_Register; + pragma Volatile_Full_Access (RDL1R); -- mailbox data high register - RDH1R : RDH1R_Register; + RDH1R : aliased RDH1R_Register; + pragma Volatile_Full_Access (RDH1R); -- filter master register - FMR : FMR_Register; + FMR : aliased FMR_Register; + pragma Volatile_Full_Access (FMR); -- filter mode register - FM1R : FM1R_Register; + FM1R : aliased FM1R_Register; + pragma Volatile_Full_Access (FM1R); -- filter scale register - FS1R : FS1R_Register; + FS1R : aliased FS1R_Register; + pragma Volatile_Full_Access (FS1R); -- filter FIFO assignment register - FFA1R : FFA1R_Register; + FFA1R : aliased FFA1R_Register; + pragma Volatile_Full_Access (FFA1R); -- filter activation register - FA1R : FA1R_Register; + FA1R : aliased FA1R_Register; + pragma Volatile_Full_Access (FA1R); -- Filter bank 0 register 1 - F0R1 : F0R_Register; + F0R1 : aliased F0R_Register; + pragma Volatile_Full_Access (F0R1); -- Filter bank 0 register 2 - F0R2 : F0R_Register; + F0R2 : aliased F0R_Register; + pragma Volatile_Full_Access (F0R2); -- Filter bank 1 register 1 - F1R1 : F1R_Register; + F1R1 : aliased F1R_Register; + pragma Volatile_Full_Access (F1R1); -- Filter bank 1 register 2 - F1R2 : F1R_Register; + F1R2 : aliased F1R_Register; + pragma Volatile_Full_Access (F1R2); -- Filter bank 2 register 1 - F2R1 : F2R_Register; + F2R1 : aliased F2R_Register; + pragma Volatile_Full_Access (F2R1); -- Filter bank 2 register 2 - F2R2 : F2R_Register; + F2R2 : aliased F2R_Register; + pragma Volatile_Full_Access (F2R2); -- Filter bank 3 register 1 - F3R1 : F3R_Register; + F3R1 : aliased F3R_Register; + pragma Volatile_Full_Access (F3R1); -- Filter bank 3 register 2 - F3R2 : F3R_Register; + F3R2 : aliased F3R_Register; + pragma Volatile_Full_Access (F3R2); -- Filter bank 4 register 1 - F4R1 : F4R_Register; + F4R1 : aliased F4R_Register; + pragma Volatile_Full_Access (F4R1); -- Filter bank 4 register 2 - F4R2 : F4R_Register; + F4R2 : aliased F4R_Register; + pragma Volatile_Full_Access (F4R2); -- Filter bank 5 register 1 - F5R1 : F5R_Register; + F5R1 : aliased F5R_Register; + pragma Volatile_Full_Access (F5R1); -- Filter bank 5 register 2 - F5R2 : F5R_Register; + F5R2 : aliased F5R_Register; + pragma Volatile_Full_Access (F5R2); -- Filter bank 6 register 1 - F6R1 : F6R_Register; + F6R1 : aliased F6R_Register; + pragma Volatile_Full_Access (F6R1); -- Filter bank 6 register 2 - F6R2 : F6R_Register; + F6R2 : aliased F6R_Register; + pragma Volatile_Full_Access (F6R2); -- Filter bank 7 register 1 - F7R1 : F7R_Register; + F7R1 : aliased F7R_Register; + pragma Volatile_Full_Access (F7R1); -- Filter bank 7 register 2 - F7R2 : F7R_Register; + F7R2 : aliased F7R_Register; + pragma Volatile_Full_Access (F7R2); -- Filter bank 8 register 1 - F8R1 : F8R_Register; + F8R1 : aliased F8R_Register; + pragma Volatile_Full_Access (F8R1); -- Filter bank 8 register 2 - F8R2 : F8R_Register; + F8R2 : aliased F8R_Register; + pragma Volatile_Full_Access (F8R2); -- Filter bank 9 register 1 - F9R1 : F9R_Register; + F9R1 : aliased F9R_Register; + pragma Volatile_Full_Access (F9R1); -- Filter bank 9 register 2 - F9R2 : F9R_Register; + F9R2 : aliased F9R_Register; + pragma Volatile_Full_Access (F9R2); -- Filter bank 10 register 1 - F10R1 : F10R_Register; + F10R1 : aliased F10R_Register; + pragma Volatile_Full_Access (F10R1); -- Filter bank 10 register 2 - F10R2 : F10R_Register; + F10R2 : aliased F10R_Register; + pragma Volatile_Full_Access (F10R2); -- Filter bank 11 register 1 - F11R1 : F11R_Register; + F11R1 : aliased F11R_Register; + pragma Volatile_Full_Access (F11R1); -- Filter bank 11 register 2 - F11R2 : F11R_Register; + F11R2 : aliased F11R_Register; + pragma Volatile_Full_Access (F11R2); -- Filter bank 4 register 1 - F12R1 : F12R_Register; + F12R1 : aliased F12R_Register; + pragma Volatile_Full_Access (F12R1); -- Filter bank 12 register 2 - F12R2 : F12R_Register; + F12R2 : aliased F12R_Register; + pragma Volatile_Full_Access (F12R2); -- Filter bank 13 register 1 - F13R1 : F13R_Register; + F13R1 : aliased F13R_Register; + pragma Volatile_Full_Access (F13R1); -- Filter bank 13 register 2 - F13R2 : F13R_Register; + F13R2 : aliased F13R_Register; + pragma Volatile_Full_Access (F13R2); -- Filter bank 14 register 1 - F14R1 : F14R_Register; + F14R1 : aliased F14R_Register; + pragma Volatile_Full_Access (F14R1); -- Filter bank 14 register 2 - F14R2 : F14R_Register; + F14R2 : aliased F14R_Register; + pragma Volatile_Full_Access (F14R2); -- Filter bank 15 register 1 - F15R1 : F15R_Register; + F15R1 : aliased F15R_Register; + pragma Volatile_Full_Access (F15R1); -- Filter bank 15 register 2 - F15R2 : F15R_Register; + F15R2 : aliased F15R_Register; + pragma Volatile_Full_Access (F15R2); -- Filter bank 16 register 1 - F16R1 : F16R_Register; + F16R1 : aliased F16R_Register; + pragma Volatile_Full_Access (F16R1); -- Filter bank 16 register 2 - F16R2 : F16R_Register; + F16R2 : aliased F16R_Register; + pragma Volatile_Full_Access (F16R2); -- Filter bank 17 register 1 - F17R1 : F17R_Register; + F17R1 : aliased F17R_Register; + pragma Volatile_Full_Access (F17R1); -- Filter bank 17 register 2 - F17R2 : F17R_Register; + F17R2 : aliased F17R_Register; + pragma Volatile_Full_Access (F17R2); -- Filter bank 18 register 1 - F18R1 : F18R_Register; + F18R1 : aliased F18R_Register; + pragma Volatile_Full_Access (F18R1); -- Filter bank 18 register 2 - F18R2 : F18R_Register; + F18R2 : aliased F18R_Register; + pragma Volatile_Full_Access (F18R2); -- Filter bank 19 register 1 - F19R1 : F19R_Register; + F19R1 : aliased F19R_Register; + pragma Volatile_Full_Access (F19R1); -- Filter bank 19 register 2 - F19R2 : F19R_Register; + F19R2 : aliased F19R_Register; + pragma Volatile_Full_Access (F19R2); -- Filter bank 20 register 1 - F20R1 : F20R_Register; + F20R1 : aliased F20R_Register; + pragma Volatile_Full_Access (F20R1); -- Filter bank 20 register 2 - F20R2 : F20R_Register; + F20R2 : aliased F20R_Register; + pragma Volatile_Full_Access (F20R2); -- Filter bank 21 register 1 - F21R1 : F21R_Register; + F21R1 : aliased F21R_Register; + pragma Volatile_Full_Access (F21R1); -- Filter bank 21 register 2 - F21R2 : F21R_Register; + F21R2 : aliased F21R_Register; + pragma Volatile_Full_Access (F21R2); -- Filter bank 22 register 1 - F22R1 : F22R_Register; + F22R1 : aliased F22R_Register; + pragma Volatile_Full_Access (F22R1); -- Filter bank 22 register 2 - F22R2 : F22R_Register; + F22R2 : aliased F22R_Register; + pragma Volatile_Full_Access (F22R2); -- Filter bank 23 register 1 - F23R1 : F23R_Register; + F23R1 : aliased F23R_Register; + pragma Volatile_Full_Access (F23R1); -- Filter bank 23 register 2 - F23R2 : F23R_Register; + F23R2 : aliased F23R_Register; + pragma Volatile_Full_Access (F23R2); -- Filter bank 24 register 1 - F24R1 : F24R_Register; + F24R1 : aliased F24R_Register; + pragma Volatile_Full_Access (F24R1); -- Filter bank 24 register 2 - F24R2 : F24R_Register; + F24R2 : aliased F24R_Register; + pragma Volatile_Full_Access (F24R2); -- Filter bank 25 register 1 - F25R1 : F25R_Register; + F25R1 : aliased F25R_Register; + pragma Volatile_Full_Access (F25R1); -- Filter bank 25 register 2 - F25R2 : F25R_Register; + F25R2 : aliased F25R_Register; + pragma Volatile_Full_Access (F25R2); -- Filter bank 26 register 1 - F26R1 : F26R_Register; + F26R1 : aliased F26R_Register; + pragma Volatile_Full_Access (F26R1); -- Filter bank 26 register 2 - F26R2 : F26R_Register; + F26R2 : aliased F26R_Register; + pragma Volatile_Full_Access (F26R2); -- Filter bank 27 register 1 - F27R1 : F27R_Register; + F27R1 : aliased F27R_Register; + pragma Volatile_Full_Access (F27R1); -- Filter bank 27 register 2 - F27R2 : F27R_Register; + F27R2 : aliased F27R_Register; + pragma Volatile_Full_Access (F27R2); end record with Volatile; for CAN_Peripheral use record - MCR at 0 range 0 .. 31; - MSR at 4 range 0 .. 31; - TSR at 8 range 0 .. 31; - RF0R at 12 range 0 .. 31; - RF1R at 16 range 0 .. 31; - IER at 20 range 0 .. 31; - ESR at 24 range 0 .. 31; - BTR at 28 range 0 .. 31; - TI0R at 384 range 0 .. 31; - TDT0R at 388 range 0 .. 31; - TDL0R at 392 range 0 .. 31; - TDH0R at 396 range 0 .. 31; - TI1R at 400 range 0 .. 31; - TDT1R at 404 range 0 .. 31; - TDL1R at 408 range 0 .. 31; - TDH1R at 412 range 0 .. 31; - TI2R at 416 range 0 .. 31; - TDT2R at 420 range 0 .. 31; - TDL2R at 424 range 0 .. 31; - TDH2R at 428 range 0 .. 31; - RI0R at 432 range 0 .. 31; - RDT0R at 436 range 0 .. 31; - RDL0R at 440 range 0 .. 31; - RDH0R at 444 range 0 .. 31; - RI1R at 448 range 0 .. 31; - RDT1R at 452 range 0 .. 31; - RDL1R at 456 range 0 .. 31; - RDH1R at 460 range 0 .. 31; - FMR at 512 range 0 .. 31; - FM1R at 516 range 0 .. 31; - FS1R at 524 range 0 .. 31; - FFA1R at 532 range 0 .. 31; - FA1R at 540 range 0 .. 31; - F0R1 at 576 range 0 .. 31; - F0R2 at 580 range 0 .. 31; - F1R1 at 584 range 0 .. 31; - F1R2 at 588 range 0 .. 31; - F2R1 at 592 range 0 .. 31; - F2R2 at 596 range 0 .. 31; - F3R1 at 600 range 0 .. 31; - F3R2 at 604 range 0 .. 31; - F4R1 at 608 range 0 .. 31; - F4R2 at 612 range 0 .. 31; - F5R1 at 616 range 0 .. 31; - F5R2 at 620 range 0 .. 31; - F6R1 at 624 range 0 .. 31; - F6R2 at 628 range 0 .. 31; - F7R1 at 632 range 0 .. 31; - F7R2 at 636 range 0 .. 31; - F8R1 at 640 range 0 .. 31; - F8R2 at 644 range 0 .. 31; - F9R1 at 648 range 0 .. 31; - F9R2 at 652 range 0 .. 31; - F10R1 at 656 range 0 .. 31; - F10R2 at 660 range 0 .. 31; - F11R1 at 664 range 0 .. 31; - F11R2 at 668 range 0 .. 31; - F12R1 at 672 range 0 .. 31; - F12R2 at 676 range 0 .. 31; - F13R1 at 680 range 0 .. 31; - F13R2 at 684 range 0 .. 31; - F14R1 at 688 range 0 .. 31; - F14R2 at 692 range 0 .. 31; - F15R1 at 696 range 0 .. 31; - F15R2 at 700 range 0 .. 31; - F16R1 at 704 range 0 .. 31; - F16R2 at 708 range 0 .. 31; - F17R1 at 712 range 0 .. 31; - F17R2 at 716 range 0 .. 31; - F18R1 at 720 range 0 .. 31; - F18R2 at 724 range 0 .. 31; - F19R1 at 728 range 0 .. 31; - F19R2 at 732 range 0 .. 31; - F20R1 at 736 range 0 .. 31; - F20R2 at 740 range 0 .. 31; - F21R1 at 744 range 0 .. 31; - F21R2 at 748 range 0 .. 31; - F22R1 at 752 range 0 .. 31; - F22R2 at 756 range 0 .. 31; - F23R1 at 760 range 0 .. 31; - F23R2 at 764 range 0 .. 31; - F24R1 at 768 range 0 .. 31; - F24R2 at 772 range 0 .. 31; - F25R1 at 776 range 0 .. 31; - F25R2 at 780 range 0 .. 31; - F26R1 at 784 range 0 .. 31; - F26R2 at 788 range 0 .. 31; - F27R1 at 792 range 0 .. 31; - F27R2 at 796 range 0 .. 31; + MCR at 16#0# range 0 .. 31; + MSR at 16#4# range 0 .. 31; + TSR at 16#8# range 0 .. 31; + RF0R at 16#C# range 0 .. 31; + RF1R at 16#10# range 0 .. 31; + IER at 16#14# range 0 .. 31; + ESR at 16#18# range 0 .. 31; + BTR at 16#1C# range 0 .. 31; + TI0R at 16#180# range 0 .. 31; + TDT0R at 16#184# range 0 .. 31; + TDL0R at 16#188# range 0 .. 31; + TDH0R at 16#18C# range 0 .. 31; + TI1R at 16#190# range 0 .. 31; + TDT1R at 16#194# range 0 .. 31; + TDL1R at 16#198# range 0 .. 31; + TDH1R at 16#19C# range 0 .. 31; + TI2R at 16#1A0# range 0 .. 31; + TDT2R at 16#1A4# range 0 .. 31; + TDL2R at 16#1A8# range 0 .. 31; + TDH2R at 16#1AC# range 0 .. 31; + RI0R at 16#1B0# range 0 .. 31; + RDT0R at 16#1B4# range 0 .. 31; + RDL0R at 16#1B8# range 0 .. 31; + RDH0R at 16#1BC# range 0 .. 31; + RI1R at 16#1C0# range 0 .. 31; + RDT1R at 16#1C4# range 0 .. 31; + RDL1R at 16#1C8# range 0 .. 31; + RDH1R at 16#1CC# range 0 .. 31; + FMR at 16#200# range 0 .. 31; + FM1R at 16#204# range 0 .. 31; + FS1R at 16#20C# range 0 .. 31; + FFA1R at 16#214# range 0 .. 31; + FA1R at 16#21C# range 0 .. 31; + F0R1 at 16#240# range 0 .. 31; + F0R2 at 16#244# range 0 .. 31; + F1R1 at 16#248# range 0 .. 31; + F1R2 at 16#24C# range 0 .. 31; + F2R1 at 16#250# range 0 .. 31; + F2R2 at 16#254# range 0 .. 31; + F3R1 at 16#258# range 0 .. 31; + F3R2 at 16#25C# range 0 .. 31; + F4R1 at 16#260# range 0 .. 31; + F4R2 at 16#264# range 0 .. 31; + F5R1 at 16#268# range 0 .. 31; + F5R2 at 16#26C# range 0 .. 31; + F6R1 at 16#270# range 0 .. 31; + F6R2 at 16#274# range 0 .. 31; + F7R1 at 16#278# range 0 .. 31; + F7R2 at 16#27C# range 0 .. 31; + F8R1 at 16#280# range 0 .. 31; + F8R2 at 16#284# range 0 .. 31; + F9R1 at 16#288# range 0 .. 31; + F9R2 at 16#28C# range 0 .. 31; + F10R1 at 16#290# range 0 .. 31; + F10R2 at 16#294# range 0 .. 31; + F11R1 at 16#298# range 0 .. 31; + F11R2 at 16#29C# range 0 .. 31; + F12R1 at 16#2A0# range 0 .. 31; + F12R2 at 16#2A4# range 0 .. 31; + F13R1 at 16#2A8# range 0 .. 31; + F13R2 at 16#2AC# range 0 .. 31; + F14R1 at 16#2B0# range 0 .. 31; + F14R2 at 16#2B4# range 0 .. 31; + F15R1 at 16#2B8# range 0 .. 31; + F15R2 at 16#2BC# range 0 .. 31; + F16R1 at 16#2C0# range 0 .. 31; + F16R2 at 16#2C4# range 0 .. 31; + F17R1 at 16#2C8# range 0 .. 31; + F17R2 at 16#2CC# range 0 .. 31; + F18R1 at 16#2D0# range 0 .. 31; + F18R2 at 16#2D4# range 0 .. 31; + F19R1 at 16#2D8# range 0 .. 31; + F19R2 at 16#2DC# range 0 .. 31; + F20R1 at 16#2E0# range 0 .. 31; + F20R2 at 16#2E4# range 0 .. 31; + F21R1 at 16#2E8# range 0 .. 31; + F21R2 at 16#2EC# range 0 .. 31; + F22R1 at 16#2F0# range 0 .. 31; + F22R2 at 16#2F4# range 0 .. 31; + F23R1 at 16#2F8# range 0 .. 31; + F23R2 at 16#2FC# range 0 .. 31; + F24R1 at 16#300# range 0 .. 31; + F24R2 at 16#304# range 0 .. 31; + F25R1 at 16#308# range 0 .. 31; + F25R2 at 16#30C# range 0 .. 31; + F26R1 at 16#310# range 0 .. 31; + F26R2 at 16#314# range 0 .. 31; + F27R1 at 16#318# range 0 .. 31; + F27R2 at 16#31C# range 0 .. 31; end record; -- Controller area network diff --git a/stm32f4/stm32f40x/stm32f40x-crc.ads b/stm32f4/stm32f40x/stm32f40x-crc.ads index 5479d83..ef0c865 100644 --- a/stm32f4/stm32f40x/stm32f40x-crc.ads +++ b/stm32f4/stm32f40x/stm32f40x-crc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.CRC is -- Registers -- --------------- - ------------------ - -- IDR_Register -- - ------------------ - subtype IDR_IDR_Field is STM32F40x.Byte; -- Independent Data register @@ -26,18 +23,13 @@ package STM32F40x.CRC is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IDR_Register use record IDR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- CR_Register -- - ----------------- - subtype CR_CR_Field is STM32F40x.Bit; -- Control register @@ -47,8 +39,7 @@ package STM32F40x.CRC is -- unspecified Reserved_1_31 : STM32F40x.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record CR at 0 range 0 .. 0; @@ -59,24 +50,26 @@ package STM32F40x.CRC is -- Peripherals -- ----------------- - -- Cryptographic processor + -- Cyclic Redundancy Check (CRC) unit type CRC_Peripheral is record -- Data register - DR : STM32F40x.Word; + DR : aliased STM32F40x.UInt32; -- Independent Data register - IDR : IDR_Register; + IDR : aliased IDR_Register; + pragma Volatile_Full_Access (IDR); -- Control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); end record with Volatile; for CRC_Peripheral use record - DR at 0 range 0 .. 31; - IDR at 4 range 0 .. 31; - CR at 8 range 0 .. 31; + DR at 16#0# range 0 .. 31; + IDR at 16#4# range 0 .. 31; + CR at 16#8# range 0 .. 31; end record; - -- Cryptographic processor + -- Cyclic Redundancy Check (CRC) unit CRC_Periph : aliased CRC_Peripheral with Import, Address => CRC_Base; diff --git a/stm32f4/stm32f40x/stm32f40x-dac.ads b/stm32f4/stm32f40x/stm32f40x-dac.ads index d64b6b6..2ab2340 100644 --- a/stm32f4/stm32f40x/stm32f40x-dac.ads +++ b/stm32f4/stm32f40x/stm32f40x-dac.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.DAC is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_EN1_Field is STM32F40x.Bit; subtype CR_BOFF1_Field is STM32F40x.Bit; subtype CR_TEN1_Field is STM32F40x.Bit; @@ -73,8 +70,7 @@ package STM32F40x.DAC is -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record EN1 at 0 range 0 .. 0; @@ -97,14 +93,6 @@ package STM32F40x.DAC is Reserved_30_31 at 0 range 30 .. 31; end record; - ---------------------- - -- SWTRIGR_Register -- - ---------------------- - - -------------------- - -- SWTRIGR.SWTRIG -- - -------------------- - -- SWTRIGR_SWTRIG array element subtype SWTRIGR_SWTRIG_Element is STM32F40x.Bit; @@ -141,83 +129,114 @@ package STM32F40x.DAC is -- unspecified Reserved_2_31 : STM32F40x.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SWTRIGR_Register use record SWTRIG at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - --------------------- - -- DHR12R_Register -- - --------------------- - subtype DHR12R1_DACC1DHR_Field is STM32F40x.UInt12; -- channel1 12-bit right-aligned data holding register - type DHR12R_Register is record + type DHR12R1_Register is record -- DAC channel1 12-bit right-aligned data DACC1DHR : DHR12R1_DACC1DHR_Field := 16#0#; -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DHR12R_Register use record + for DHR12R1_Register use record DACC1DHR at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - --------------------- - -- DHR12L_Register -- - --------------------- - subtype DHR12L1_DACC1DHR_Field is STM32F40x.UInt12; -- channel1 12-bit left aligned data holding register - type DHR12L_Register is record + type DHR12L1_Register is record -- unspecified Reserved_0_3 : STM32F40x.UInt4 := 16#0#; -- DAC channel1 12-bit left-aligned data DACC1DHR : DHR12L1_DACC1DHR_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DHR12L_Register use record + for DHR12L1_Register use record Reserved_0_3 at 0 range 0 .. 3; DACC1DHR at 0 range 4 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- DHR8R_Register -- - -------------------- - subtype DHR8R1_DACC1DHR_Field is STM32F40x.Byte; -- channel1 8-bit right aligned data holding register - type DHR8R_Register is record + type DHR8R1_Register is record -- DAC channel1 8-bit right-aligned data DACC1DHR : DHR8R1_DACC1DHR_Field := 16#0#; -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DHR8R_Register use record + for DHR8R1_Register use record DACC1DHR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ---------------------- - -- DHR12RD_Register -- - ---------------------- + subtype DHR12R2_DACC2DHR_Field is STM32F40x.UInt12; + + -- channel2 12-bit right aligned data holding register + type DHR12R2_Register is record + -- DAC channel2 12-bit right-aligned data + DACC2DHR : DHR12R2_DACC2DHR_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DHR12R2_Register use record + DACC2DHR at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype DHR12L2_DACC2DHR_Field is STM32F40x.UInt12; + + -- channel2 12-bit left aligned data holding register + type DHR12L2_Register is record + -- unspecified + Reserved_0_3 : STM32F40x.UInt4 := 16#0#; + -- DAC channel2 12-bit left-aligned data + DACC2DHR : DHR12L2_DACC2DHR_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DHR12L2_Register use record + Reserved_0_3 at 0 range 0 .. 3; + DACC2DHR at 0 range 4 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DHR8R2_DACC2DHR_Field is STM32F40x.Byte; + + -- channel2 8-bit right-aligned data holding register + type DHR8R2_Register is record + -- DAC channel2 8-bit right-aligned data + DACC2DHR : DHR8R2_DACC2DHR_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F40x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DHR8R2_Register use record + DACC2DHR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; subtype DHR12RD_DACC1DHR_Field is STM32F40x.UInt12; subtype DHR12RD_DACC2DHR_Field is STM32F40x.UInt12; @@ -233,8 +252,7 @@ package STM32F40x.DAC is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DHR12RD_Register use record DACC1DHR at 0 range 0 .. 11; @@ -243,10 +261,6 @@ package STM32F40x.DAC is Reserved_28_31 at 0 range 28 .. 31; end record; - ---------------------- - -- DHR12LD_Register -- - ---------------------- - subtype DHR12LD_DACC1DHR_Field is STM32F40x.UInt12; subtype DHR12LD_DACC2DHR_Field is STM32F40x.UInt12; @@ -261,8 +275,7 @@ package STM32F40x.DAC is -- DAC channel2 12-bit left-aligned data DACC2DHR : DHR12LD_DACC2DHR_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DHR12LD_Register use record Reserved_0_3 at 0 range 0 .. 3; @@ -271,10 +284,6 @@ package STM32F40x.DAC is DACC2DHR at 0 range 20 .. 31; end record; - --------------------- - -- DHR8RD_Register -- - --------------------- - subtype DHR8RD_DACC1DHR_Field is STM32F40x.Byte; subtype DHR8RD_DACC2DHR_Field is STM32F40x.Byte; @@ -285,10 +294,9 @@ package STM32F40x.DAC is -- DAC channel2 8-bit right-aligned data DACC2DHR : DHR8RD_DACC2DHR_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DHR8RD_Register use record DACC1DHR at 0 range 0 .. 7; @@ -296,30 +304,37 @@ package STM32F40x.DAC is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- DOR_Register -- - ------------------ - subtype DOR1_DACC1DOR_Field is STM32F40x.UInt12; -- channel1 data output register - type DOR_Register is record + type DOR1_Register is record -- Read-only. DAC channel1 data output - DACC1DOR : DOR1_DACC1DOR_Field := 16#0#; + DACC1DOR : DOR1_DACC1DOR_Field; -- unspecified Reserved_12_31 : STM32F40x.UInt20; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOR_Register use record + for DOR1_Register use record DACC1DOR at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- + subtype DOR2_DACC2DOR_Field is STM32F40x.UInt12; + + -- channel2 data output register + type DOR2_Register is record + -- Read-only. DAC channel2 data output + DACC2DOR : DOR2_DACC2DOR_Field; + -- unspecified + Reserved_12_31 : STM32F40x.UInt20; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DOR2_Register use record + DACC2DOR at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; subtype SR_DMAUDR1_Field is STM32F40x.Bit; subtype SR_DMAUDR2_Field is STM32F40x.Bit; @@ -337,8 +352,7 @@ package STM32F40x.DAC is -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record Reserved_0_12 at 0 range 0 .. 12; @@ -355,51 +369,65 @@ package STM32F40x.DAC is -- Digital-to-analog converter type DAC_Peripheral is record -- control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- software trigger register - SWTRIGR : SWTRIGR_Register; + SWTRIGR : aliased SWTRIGR_Register; + pragma Volatile_Full_Access (SWTRIGR); -- channel1 12-bit right-aligned data holding register - DHR12R1 : DHR12R_Register; + DHR12R1 : aliased DHR12R1_Register; + pragma Volatile_Full_Access (DHR12R1); -- channel1 12-bit left aligned data holding register - DHR12L1 : DHR12L_Register; + DHR12L1 : aliased DHR12L1_Register; + pragma Volatile_Full_Access (DHR12L1); -- channel1 8-bit right aligned data holding register - DHR8R1 : DHR8R_Register; + DHR8R1 : aliased DHR8R1_Register; + pragma Volatile_Full_Access (DHR8R1); -- channel2 12-bit right aligned data holding register - DHR12R2 : DHR12R_Register; + DHR12R2 : aliased DHR12R2_Register; + pragma Volatile_Full_Access (DHR12R2); -- channel2 12-bit left aligned data holding register - DHR12L2 : DHR12L_Register; + DHR12L2 : aliased DHR12L2_Register; + pragma Volatile_Full_Access (DHR12L2); -- channel2 8-bit right-aligned data holding register - DHR8R2 : DHR8R_Register; + DHR8R2 : aliased DHR8R2_Register; + pragma Volatile_Full_Access (DHR8R2); -- Dual DAC 12-bit right-aligned data holding register - DHR12RD : DHR12RD_Register; + DHR12RD : aliased DHR12RD_Register; + pragma Volatile_Full_Access (DHR12RD); -- DUAL DAC 12-bit left aligned data holding register - DHR12LD : DHR12LD_Register; + DHR12LD : aliased DHR12LD_Register; + pragma Volatile_Full_Access (DHR12LD); -- DUAL DAC 8-bit right aligned data holding register - DHR8RD : DHR8RD_Register; + DHR8RD : aliased DHR8RD_Register; + pragma Volatile_Full_Access (DHR8RD); -- channel1 data output register - DOR1 : DOR_Register; + DOR1 : aliased DOR1_Register; + pragma Volatile_Full_Access (DOR1); -- channel2 data output register - DOR2 : DOR_Register; + DOR2 : aliased DOR2_Register; + pragma Volatile_Full_Access (DOR2); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; for DAC_Peripheral use record - CR at 0 range 0 .. 31; - SWTRIGR at 4 range 0 .. 31; - DHR12R1 at 8 range 0 .. 31; - DHR12L1 at 12 range 0 .. 31; - DHR8R1 at 16 range 0 .. 31; - DHR12R2 at 20 range 0 .. 31; - DHR12L2 at 24 range 0 .. 31; - DHR8R2 at 28 range 0 .. 31; - DHR12RD at 32 range 0 .. 31; - DHR12LD at 36 range 0 .. 31; - DHR8RD at 40 range 0 .. 31; - DOR1 at 44 range 0 .. 31; - DOR2 at 48 range 0 .. 31; - SR at 52 range 0 .. 31; + CR at 16#0# range 0 .. 31; + SWTRIGR at 16#4# range 0 .. 31; + DHR12R1 at 16#8# range 0 .. 31; + DHR12L1 at 16#C# range 0 .. 31; + DHR8R1 at 16#10# range 0 .. 31; + DHR12R2 at 16#14# range 0 .. 31; + DHR12L2 at 16#18# range 0 .. 31; + DHR8R2 at 16#1C# range 0 .. 31; + DHR12RD at 16#20# range 0 .. 31; + DHR12LD at 16#24# range 0 .. 31; + DHR8RD at 16#28# range 0 .. 31; + DOR1 at 16#2C# range 0 .. 31; + DOR2 at 16#30# range 0 .. 31; + SR at 16#34# range 0 .. 31; end record; -- Digital-to-analog converter diff --git a/stm32f4/stm32f40x/stm32f40x-dbg.ads b/stm32f4/stm32f40x/stm32f40x-dbg.ads index 8add685..a3ef4f2 100644 --- a/stm32f4/stm32f40x/stm32f40x-dbg.ads +++ b/stm32f4/stm32f40x/stm32f40x-dbg.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,24 +14,19 @@ package STM32F40x.DBG is -- Registers -- --------------- - ---------------------------- - -- DBGMCU_IDCODE_Register -- - ---------------------------- - subtype DBGMCU_IDCODE_DEV_ID_Field is STM32F40x.UInt12; - subtype DBGMCU_IDCODE_REV_ID_Field is STM32F40x.Short; + subtype DBGMCU_IDCODE_REV_ID_Field is STM32F40x.UInt16; -- IDCODE type DBGMCU_IDCODE_Register is record -- Read-only. DEV_ID - DEV_ID : DBGMCU_IDCODE_DEV_ID_Field := 16#411#; + DEV_ID : DBGMCU_IDCODE_DEV_ID_Field; -- unspecified Reserved_12_15 : STM32F40x.UInt4; -- Read-only. REV_ID - REV_ID : DBGMCU_IDCODE_REV_ID_Field := 16#1000#; + REV_ID : DBGMCU_IDCODE_REV_ID_Field; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DBGMCU_IDCODE_Register use record DEV_ID at 0 range 0 .. 11; @@ -38,10 +34,6 @@ package STM32F40x.DBG is REV_ID at 0 range 16 .. 31; end record; - ------------------------ - -- DBGMCU_CR_Register -- - ------------------------ - subtype DBGMCU_CR_DBG_SLEEP_Field is STM32F40x.Bit; subtype DBGMCU_CR_DBG_STOP_Field is STM32F40x.Bit; subtype DBGMCU_CR_DBG_STANDBY_Field is STM32F40x.Bit; @@ -83,8 +75,7 @@ package STM32F40x.DBG is -- unspecified Reserved_21_31 : STM32F40x.UInt11 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DBGMCU_CR_Register use record DBG_SLEEP at 0 range 0 .. 0; @@ -102,10 +93,6 @@ package STM32F40x.DBG is Reserved_21_31 at 0 range 21 .. 31; end record; - ----------------------------- - -- DBGMCU_APB1_FZ_Register -- - ----------------------------- - subtype DBGMCU_APB1_FZ_DBG_TIM2_STOP_Field is STM32F40x.Bit; subtype DBGMCU_APB1_FZ_DBG_TIM3_STOP_Field is STM32F40x.Bit; subtype DBGMCU_APB1_FZ_DBG_TIM4_STOP_Field is STM32F40x.Bit; @@ -169,8 +156,7 @@ package STM32F40x.DBG is -- unspecified Reserved_27_31 : STM32F40x.UInt5 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DBGMCU_APB1_FZ_Register use record DBG_TIM2_STOP at 0 range 0 .. 0; @@ -195,10 +181,6 @@ package STM32F40x.DBG is Reserved_27_31 at 0 range 27 .. 31; end record; - ----------------------------- - -- DBGMCU_APB2_FZ_Register -- - ----------------------------- - subtype DBGMCU_APB2_FZ_DBG_TIM1_STOP_Field is STM32F40x.Bit; subtype DBGMCU_APB2_FZ_DBG_TIM8_STOP_Field is STM32F40x.Bit; subtype DBGMCU_APB2_FZ_DBG_TIM9_STOP_Field is STM32F40x.Bit; @@ -222,8 +204,7 @@ package STM32F40x.DBG is -- unspecified Reserved_19_31 : STM32F40x.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DBGMCU_APB2_FZ_Register use record DBG_TIM1_STOP at 0 range 0 .. 0; @@ -242,21 +223,25 @@ package STM32F40x.DBG is -- Debug support type DBG_Peripheral is record -- IDCODE - DBGMCU_IDCODE : DBGMCU_IDCODE_Register; + DBGMCU_IDCODE : aliased DBGMCU_IDCODE_Register; + pragma Volatile_Full_Access (DBGMCU_IDCODE); -- Control Register - DBGMCU_CR : DBGMCU_CR_Register; + DBGMCU_CR : aliased DBGMCU_CR_Register; + pragma Volatile_Full_Access (DBGMCU_CR); -- Debug MCU APB1 Freeze registe - DBGMCU_APB1_FZ : DBGMCU_APB1_FZ_Register; + DBGMCU_APB1_FZ : aliased DBGMCU_APB1_FZ_Register; + pragma Volatile_Full_Access (DBGMCU_APB1_FZ); -- Debug MCU APB2 Freeze registe - DBGMCU_APB2_FZ : DBGMCU_APB2_FZ_Register; + DBGMCU_APB2_FZ : aliased DBGMCU_APB2_FZ_Register; + pragma Volatile_Full_Access (DBGMCU_APB2_FZ); end record with Volatile; for DBG_Peripheral use record - DBGMCU_IDCODE at 0 range 0 .. 31; - DBGMCU_CR at 4 range 0 .. 31; - DBGMCU_APB1_FZ at 8 range 0 .. 31; - DBGMCU_APB2_FZ at 12 range 0 .. 31; + DBGMCU_IDCODE at 16#0# range 0 .. 31; + DBGMCU_CR at 16#4# range 0 .. 31; + DBGMCU_APB1_FZ at 16#8# range 0 .. 31; + DBGMCU_APB2_FZ at 16#C# range 0 .. 31; end record; -- Debug support diff --git a/stm32f4/stm32f40x/stm32f40x-dcmi.ads b/stm32f4/stm32f40x/stm32f40x-dcmi.ads index 6757a70..bbefd96 100644 --- a/stm32f4/stm32f40x/stm32f40x-dcmi.ads +++ b/stm32f4/stm32f40x/stm32f40x-dcmi.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.DCMI is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_CAPTURE_Field is STM32F40x.Bit; subtype CR_CM_Field is STM32F40x.Bit; subtype CR_CROP_Field is STM32F40x.Bit; @@ -58,8 +55,7 @@ package STM32F40x.DCMI is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record CAPTURE at 0 range 0 .. 0; @@ -77,10 +73,6 @@ package STM32F40x.DCMI is Reserved_15_31 at 0 range 15 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_HSYNC_Field is STM32F40x.Bit; subtype SR_VSYNC_Field is STM32F40x.Bit; subtype SR_FNE_Field is STM32F40x.Bit; @@ -88,16 +80,15 @@ package STM32F40x.DCMI is -- status register type SR_Register is record -- Read-only. HSYNC - HSYNC : SR_HSYNC_Field := 16#0#; + HSYNC : SR_HSYNC_Field; -- Read-only. VSYNC - VSYNC : SR_VSYNC_Field := 16#0#; + VSYNC : SR_VSYNC_Field; -- Read-only. FIFO not empty - FNE : SR_FNE_Field := 16#0#; + FNE : SR_FNE_Field; -- unspecified Reserved_3_31 : STM32F40x.UInt29; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record HSYNC at 0 range 0 .. 0; @@ -106,10 +97,6 @@ package STM32F40x.DCMI is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- RIS_Register -- - ------------------ - subtype RIS_FRAME_RIS_Field is STM32F40x.Bit; subtype RIS_OVR_RIS_Field is STM32F40x.Bit; subtype RIS_ERR_RIS_Field is STM32F40x.Bit; @@ -119,20 +106,19 @@ package STM32F40x.DCMI is -- raw interrupt status register type RIS_Register is record -- Read-only. Capture complete raw interrupt status - FRAME_RIS : RIS_FRAME_RIS_Field := 16#0#; + FRAME_RIS : RIS_FRAME_RIS_Field; -- Read-only. Overrun raw interrupt status - OVR_RIS : RIS_OVR_RIS_Field := 16#0#; + OVR_RIS : RIS_OVR_RIS_Field; -- Read-only. Synchronization error raw interrupt status - ERR_RIS : RIS_ERR_RIS_Field := 16#0#; + ERR_RIS : RIS_ERR_RIS_Field; -- Read-only. VSYNC raw interrupt status - VSYNC_RIS : RIS_VSYNC_RIS_Field := 16#0#; + VSYNC_RIS : RIS_VSYNC_RIS_Field; -- Read-only. Line raw interrupt status - LINE_RIS : RIS_LINE_RIS_Field := 16#0#; + LINE_RIS : RIS_LINE_RIS_Field; -- unspecified Reserved_5_31 : STM32F40x.UInt27; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RIS_Register use record FRAME_RIS at 0 range 0 .. 0; @@ -143,10 +129,6 @@ package STM32F40x.DCMI is Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - subtype IER_FRAME_IE_Field is STM32F40x.Bit; subtype IER_OVR_IE_Field is STM32F40x.Bit; subtype IER_ERR_IE_Field is STM32F40x.Bit; @@ -168,8 +150,7 @@ package STM32F40x.DCMI is -- unspecified Reserved_5_31 : STM32F40x.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IER_Register use record FRAME_IE at 0 range 0 .. 0; @@ -180,10 +161,6 @@ package STM32F40x.DCMI is Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------ - -- MIS_Register -- - ------------------ - subtype MIS_FRAME_MIS_Field is STM32F40x.Bit; subtype MIS_OVR_MIS_Field is STM32F40x.Bit; subtype MIS_ERR_MIS_Field is STM32F40x.Bit; @@ -193,20 +170,19 @@ package STM32F40x.DCMI is -- masked interrupt status register type MIS_Register is record -- Read-only. Capture complete masked interrupt status - FRAME_MIS : MIS_FRAME_MIS_Field := 16#0#; + FRAME_MIS : MIS_FRAME_MIS_Field; -- Read-only. Overrun masked interrupt status - OVR_MIS : MIS_OVR_MIS_Field := 16#0#; + OVR_MIS : MIS_OVR_MIS_Field; -- Read-only. Synchronization error masked interrupt status - ERR_MIS : MIS_ERR_MIS_Field := 16#0#; + ERR_MIS : MIS_ERR_MIS_Field; -- Read-only. VSYNC masked interrupt status - VSYNC_MIS : MIS_VSYNC_MIS_Field := 16#0#; + VSYNC_MIS : MIS_VSYNC_MIS_Field; -- Read-only. Line masked interrupt status - LINE_MIS : MIS_LINE_MIS_Field := 16#0#; + LINE_MIS : MIS_LINE_MIS_Field; -- unspecified Reserved_5_31 : STM32F40x.UInt27; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MIS_Register use record FRAME_MIS at 0 range 0 .. 0; @@ -217,10 +193,6 @@ package STM32F40x.DCMI is Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------ - -- ICR_Register -- - ------------------ - subtype ICR_FRAME_ISC_Field is STM32F40x.Bit; subtype ICR_OVR_ISC_Field is STM32F40x.Bit; subtype ICR_ERR_ISC_Field is STM32F40x.Bit; @@ -242,8 +214,7 @@ package STM32F40x.DCMI is -- unspecified Reserved_5_31 : STM32F40x.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ICR_Register use record FRAME_ISC at 0 range 0 .. 0; @@ -254,10 +225,6 @@ package STM32F40x.DCMI is Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------- - -- ESCR_Register -- - ------------------- - subtype ESCR_FSC_Field is STM32F40x.Byte; subtype ESCR_LSC_Field is STM32F40x.Byte; subtype ESCR_LEC_Field is STM32F40x.Byte; @@ -274,8 +241,7 @@ package STM32F40x.DCMI is -- Frame end delimiter code FEC : ESCR_FEC_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ESCR_Register use record FSC at 0 range 0 .. 7; @@ -284,10 +250,6 @@ package STM32F40x.DCMI is FEC at 0 range 24 .. 31; end record; - ------------------- - -- ESUR_Register -- - ------------------- - subtype ESUR_FSU_Field is STM32F40x.Byte; subtype ESUR_LSU_Field is STM32F40x.Byte; subtype ESUR_LEU_Field is STM32F40x.Byte; @@ -304,8 +266,7 @@ package STM32F40x.DCMI is -- Frame end delimiter unmask FEU : ESUR_FEU_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ESUR_Register use record FSU at 0 range 0 .. 7; @@ -314,10 +275,6 @@ package STM32F40x.DCMI is FEU at 0 range 24 .. 31; end record; - --------------------- - -- CWSTRT_Register -- - --------------------- - subtype CWSTRT_HOFFCNT_Field is STM32F40x.UInt14; subtype CWSTRT_VST_Field is STM32F40x.UInt13; @@ -332,8 +289,7 @@ package STM32F40x.DCMI is -- unspecified Reserved_29_31 : STM32F40x.UInt3 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CWSTRT_Register use record HOFFCNT at 0 range 0 .. 13; @@ -342,10 +298,6 @@ package STM32F40x.DCMI is Reserved_29_31 at 0 range 29 .. 31; end record; - --------------------- - -- CWSIZE_Register -- - --------------------- - subtype CWSIZE_CAPCNT_Field is STM32F40x.UInt14; subtype CWSIZE_VLINE_Field is STM32F40x.UInt14; @@ -360,8 +312,7 @@ package STM32F40x.DCMI is -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CWSIZE_Register use record CAPCNT at 0 range 0 .. 13; @@ -370,10 +321,6 @@ package STM32F40x.DCMI is Reserved_30_31 at 0 range 30 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - -- DR_Byte array element subtype DR_Byte_Element is STM32F40x.Byte; @@ -388,13 +335,13 @@ package STM32F40x.DCMI is case As_Array is when False => -- Byte as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- Byte as an array Arr : DR_Byte_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record @@ -409,42 +356,53 @@ package STM32F40x.DCMI is -- Digital camera interface type DCMI_Peripheral is record -- control register 1 - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- raw interrupt status register - RIS : RIS_Register; + RIS : aliased RIS_Register; + pragma Volatile_Full_Access (RIS); -- interrupt enable register - IER : IER_Register; + IER : aliased IER_Register; + pragma Volatile_Full_Access (IER); -- masked interrupt status register - MIS : MIS_Register; + MIS : aliased MIS_Register; + pragma Volatile_Full_Access (MIS); -- interrupt clear register - ICR : ICR_Register; + ICR : aliased ICR_Register; + pragma Volatile_Full_Access (ICR); -- embedded synchronization code register - ESCR : ESCR_Register; + ESCR : aliased ESCR_Register; + pragma Volatile_Full_Access (ESCR); -- embedded synchronization unmask register - ESUR : ESUR_Register; + ESUR : aliased ESUR_Register; + pragma Volatile_Full_Access (ESUR); -- crop window start - CWSTRT : CWSTRT_Register; + CWSTRT : aliased CWSTRT_Register; + pragma Volatile_Full_Access (CWSTRT); -- crop window size - CWSIZE : CWSIZE_Register; + CWSIZE : aliased CWSIZE_Register; + pragma Volatile_Full_Access (CWSIZE); -- data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); end record with Volatile; for DCMI_Peripheral use record - CR at 0 range 0 .. 31; - SR at 4 range 0 .. 31; - RIS at 8 range 0 .. 31; - IER at 12 range 0 .. 31; - MIS at 16 range 0 .. 31; - ICR at 20 range 0 .. 31; - ESCR at 24 range 0 .. 31; - ESUR at 28 range 0 .. 31; - CWSTRT at 32 range 0 .. 31; - CWSIZE at 36 range 0 .. 31; - DR at 40 range 0 .. 31; + CR at 16#0# range 0 .. 31; + SR at 16#4# range 0 .. 31; + RIS at 16#8# range 0 .. 31; + IER at 16#C# range 0 .. 31; + MIS at 16#10# range 0 .. 31; + ICR at 16#14# range 0 .. 31; + ESCR at 16#18# range 0 .. 31; + ESUR at 16#1C# range 0 .. 31; + CWSTRT at 16#20# range 0 .. 31; + CWSIZE at 16#24# range 0 .. 31; + DR at 16#28# range 0 .. 31; end record; -- Digital camera interface diff --git a/stm32f4/stm32f40x/stm32f40x-dma.ads b/stm32f4/stm32f40x/stm32f40x-dma.ads index c3c60e7..9061c5e 100644 --- a/stm32f4/stm32f40x/stm32f40x-dma.ads +++ b/stm32f4/stm32f40x/stm32f40x-dma.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.DMA is -- Registers -- --------------- - ------------------- - -- LISR_Register -- - ------------------- - subtype LISR_FEIF0_Field is STM32F40x.Bit; subtype LISR_DMEIF0_Field is STM32F40x.Bit; subtype LISR_TEIF0_Field is STM32F40x.Bit; @@ -41,60 +38,59 @@ package STM32F40x.DMA is -- low interrupt status register type LISR_Register is record -- Read-only. Stream x FIFO error interrupt flag (x=3..0) - FEIF0 : LISR_FEIF0_Field := 16#0#; + FEIF0 : LISR_FEIF0_Field; -- unspecified Reserved_1_1 : STM32F40x.Bit; -- Read-only. Stream x direct mode error interrupt flag (x=3..0) - DMEIF0 : LISR_DMEIF0_Field := 16#0#; + DMEIF0 : LISR_DMEIF0_Field; -- Read-only. Stream x transfer error interrupt flag (x=3..0) - TEIF0 : LISR_TEIF0_Field := 16#0#; + TEIF0 : LISR_TEIF0_Field; -- Read-only. Stream x half transfer interrupt flag (x=3..0) - HTIF0 : LISR_HTIF0_Field := 16#0#; + HTIF0 : LISR_HTIF0_Field; -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) - TCIF0 : LISR_TCIF0_Field := 16#0#; + TCIF0 : LISR_TCIF0_Field; -- Read-only. Stream x FIFO error interrupt flag (x=3..0) - FEIF1 : LISR_FEIF1_Field := 16#0#; + FEIF1 : LISR_FEIF1_Field; -- unspecified Reserved_7_7 : STM32F40x.Bit; -- Read-only. Stream x direct mode error interrupt flag (x=3..0) - DMEIF1 : LISR_DMEIF1_Field := 16#0#; + DMEIF1 : LISR_DMEIF1_Field; -- Read-only. Stream x transfer error interrupt flag (x=3..0) - TEIF1 : LISR_TEIF1_Field := 16#0#; + TEIF1 : LISR_TEIF1_Field; -- Read-only. Stream x half transfer interrupt flag (x=3..0) - HTIF1 : LISR_HTIF1_Field := 16#0#; + HTIF1 : LISR_HTIF1_Field; -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) - TCIF1 : LISR_TCIF1_Field := 16#0#; + TCIF1 : LISR_TCIF1_Field; -- unspecified Reserved_12_15 : STM32F40x.UInt4; -- Read-only. Stream x FIFO error interrupt flag (x=3..0) - FEIF2 : LISR_FEIF2_Field := 16#0#; + FEIF2 : LISR_FEIF2_Field; -- unspecified Reserved_17_17 : STM32F40x.Bit; -- Read-only. Stream x direct mode error interrupt flag (x=3..0) - DMEIF2 : LISR_DMEIF2_Field := 16#0#; + DMEIF2 : LISR_DMEIF2_Field; -- Read-only. Stream x transfer error interrupt flag (x=3..0) - TEIF2 : LISR_TEIF2_Field := 16#0#; + TEIF2 : LISR_TEIF2_Field; -- Read-only. Stream x half transfer interrupt flag (x=3..0) - HTIF2 : LISR_HTIF2_Field := 16#0#; + HTIF2 : LISR_HTIF2_Field; -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) - TCIF2 : LISR_TCIF2_Field := 16#0#; + TCIF2 : LISR_TCIF2_Field; -- Read-only. Stream x FIFO error interrupt flag (x=3..0) - FEIF3 : LISR_FEIF3_Field := 16#0#; + FEIF3 : LISR_FEIF3_Field; -- unspecified Reserved_23_23 : STM32F40x.Bit; -- Read-only. Stream x direct mode error interrupt flag (x=3..0) - DMEIF3 : LISR_DMEIF3_Field := 16#0#; + DMEIF3 : LISR_DMEIF3_Field; -- Read-only. Stream x transfer error interrupt flag (x=3..0) - TEIF3 : LISR_TEIF3_Field := 16#0#; + TEIF3 : LISR_TEIF3_Field; -- Read-only. Stream x half transfer interrupt flag (x=3..0) - HTIF3 : LISR_HTIF3_Field := 16#0#; + HTIF3 : LISR_HTIF3_Field; -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) - TCIF3 : LISR_TCIF3_Field := 16#0#; + TCIF3 : LISR_TCIF3_Field; -- unspecified Reserved_28_31 : STM32F40x.UInt4; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LISR_Register use record FEIF0 at 0 range 0 .. 0; @@ -125,10 +121,6 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- HISR_Register -- - ------------------- - subtype HISR_FEIF4_Field is STM32F40x.Bit; subtype HISR_DMEIF4_Field is STM32F40x.Bit; subtype HISR_TEIF4_Field is STM32F40x.Bit; @@ -153,60 +145,59 @@ package STM32F40x.DMA is -- high interrupt status register type HISR_Register is record -- Read-only. Stream x FIFO error interrupt flag (x=7..4) - FEIF4 : HISR_FEIF4_Field := 16#0#; + FEIF4 : HISR_FEIF4_Field; -- unspecified Reserved_1_1 : STM32F40x.Bit; -- Read-only. Stream x direct mode error interrupt flag (x=7..4) - DMEIF4 : HISR_DMEIF4_Field := 16#0#; + DMEIF4 : HISR_DMEIF4_Field; -- Read-only. Stream x transfer error interrupt flag (x=7..4) - TEIF4 : HISR_TEIF4_Field := 16#0#; + TEIF4 : HISR_TEIF4_Field; -- Read-only. Stream x half transfer interrupt flag (x=7..4) - HTIF4 : HISR_HTIF4_Field := 16#0#; + HTIF4 : HISR_HTIF4_Field; -- Read-only. Stream x transfer complete interrupt flag (x=7..4) - TCIF4 : HISR_TCIF4_Field := 16#0#; + TCIF4 : HISR_TCIF4_Field; -- Read-only. Stream x FIFO error interrupt flag (x=7..4) - FEIF5 : HISR_FEIF5_Field := 16#0#; + FEIF5 : HISR_FEIF5_Field; -- unspecified Reserved_7_7 : STM32F40x.Bit; -- Read-only. Stream x direct mode error interrupt flag (x=7..4) - DMEIF5 : HISR_DMEIF5_Field := 16#0#; + DMEIF5 : HISR_DMEIF5_Field; -- Read-only. Stream x transfer error interrupt flag (x=7..4) - TEIF5 : HISR_TEIF5_Field := 16#0#; + TEIF5 : HISR_TEIF5_Field; -- Read-only. Stream x half transfer interrupt flag (x=7..4) - HTIF5 : HISR_HTIF5_Field := 16#0#; + HTIF5 : HISR_HTIF5_Field; -- Read-only. Stream x transfer complete interrupt flag (x=7..4) - TCIF5 : HISR_TCIF5_Field := 16#0#; + TCIF5 : HISR_TCIF5_Field; -- unspecified Reserved_12_15 : STM32F40x.UInt4; -- Read-only. Stream x FIFO error interrupt flag (x=7..4) - FEIF6 : HISR_FEIF6_Field := 16#0#; + FEIF6 : HISR_FEIF6_Field; -- unspecified Reserved_17_17 : STM32F40x.Bit; -- Read-only. Stream x direct mode error interrupt flag (x=7..4) - DMEIF6 : HISR_DMEIF6_Field := 16#0#; + DMEIF6 : HISR_DMEIF6_Field; -- Read-only. Stream x transfer error interrupt flag (x=7..4) - TEIF6 : HISR_TEIF6_Field := 16#0#; + TEIF6 : HISR_TEIF6_Field; -- Read-only. Stream x half transfer interrupt flag (x=7..4) - HTIF6 : HISR_HTIF6_Field := 16#0#; + HTIF6 : HISR_HTIF6_Field; -- Read-only. Stream x transfer complete interrupt flag (x=7..4) - TCIF6 : HISR_TCIF6_Field := 16#0#; + TCIF6 : HISR_TCIF6_Field; -- Read-only. Stream x FIFO error interrupt flag (x=7..4) - FEIF7 : HISR_FEIF7_Field := 16#0#; + FEIF7 : HISR_FEIF7_Field; -- unspecified Reserved_23_23 : STM32F40x.Bit; -- Read-only. Stream x direct mode error interrupt flag (x=7..4) - DMEIF7 : HISR_DMEIF7_Field := 16#0#; + DMEIF7 : HISR_DMEIF7_Field; -- Read-only. Stream x transfer error interrupt flag (x=7..4) - TEIF7 : HISR_TEIF7_Field := 16#0#; + TEIF7 : HISR_TEIF7_Field; -- Read-only. Stream x half transfer interrupt flag (x=7..4) - HTIF7 : HISR_HTIF7_Field := 16#0#; + HTIF7 : HISR_HTIF7_Field; -- Read-only. Stream x transfer complete interrupt flag (x=7..4) - TCIF7 : HISR_TCIF7_Field := 16#0#; + TCIF7 : HISR_TCIF7_Field; -- unspecified Reserved_28_31 : STM32F40x.UInt4; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for HISR_Register use record FEIF4 at 0 range 0 .. 0; @@ -237,10 +228,6 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - -------------------- - -- LIFCR_Register -- - -------------------- - subtype LIFCR_CFEIF0_Field is STM32F40x.Bit; subtype LIFCR_CDMEIF0_Field is STM32F40x.Bit; subtype LIFCR_CTEIF0_Field is STM32F40x.Bit; @@ -317,8 +304,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LIFCR_Register use record CFEIF0 at 0 range 0 .. 0; @@ -349,10 +335,6 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - -------------------- - -- HIFCR_Register -- - -------------------- - subtype HIFCR_CFEIF4_Field is STM32F40x.Bit; subtype HIFCR_CDMEIF4_Field is STM32F40x.Bit; subtype HIFCR_CTEIF4_Field is STM32F40x.Bit; @@ -429,8 +411,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for HIFCR_Register use record CFEIF4 at 0 range 0 .. 0; @@ -461,10 +442,6 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- S0CR_Register -- - ------------------- - subtype S0CR_EN_Field is STM32F40x.Bit; subtype S0CR_DMEIE_Field is STM32F40x.Bit; subtype S0CR_TEIE_Field is STM32F40x.Bit; @@ -530,8 +507,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S0CR_Register use record EN at 0 range 0 .. 0; @@ -557,31 +533,22 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S0NDTR_Register -- - --------------------- - - subtype S0NDTR_NDT_Field is STM32F40x.Short; + subtype S0NDTR_NDT_Field is STM32F40x.UInt16; -- stream x number of data register type S0NDTR_Register is record -- Number of data items to transfer NDT : S0NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S0NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S0FCR_Register -- - -------------------- - subtype S0FCR_FTH_Field is STM32F40x.UInt2; subtype S0FCR_DMDIS_Field is STM32F40x.Bit; subtype S0FCR_FS_Field is STM32F40x.UInt3; @@ -602,8 +569,7 @@ package STM32F40x.DMA is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S0FCR_Register use record FTH at 0 range 0 .. 1; @@ -614,10 +580,6 @@ package STM32F40x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S1CR_Register -- - ------------------- - subtype S1CR_EN_Field is STM32F40x.Bit; subtype S1CR_DMEIE_Field is STM32F40x.Bit; subtype S1CR_TEIE_Field is STM32F40x.Bit; @@ -684,8 +646,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S1CR_Register use record EN at 0 range 0 .. 0; @@ -711,31 +672,22 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S1NDTR_Register -- - --------------------- - - subtype S1NDTR_NDT_Field is STM32F40x.Short; + subtype S1NDTR_NDT_Field is STM32F40x.UInt16; -- stream x number of data register type S1NDTR_Register is record -- Number of data items to transfer NDT : S1NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S1NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S1FCR_Register -- - -------------------- - subtype S1FCR_FTH_Field is STM32F40x.UInt2; subtype S1FCR_DMDIS_Field is STM32F40x.Bit; subtype S1FCR_FS_Field is STM32F40x.UInt3; @@ -756,8 +708,7 @@ package STM32F40x.DMA is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S1FCR_Register use record FTH at 0 range 0 .. 1; @@ -768,10 +719,6 @@ package STM32F40x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S2CR_Register -- - ------------------- - subtype S2CR_EN_Field is STM32F40x.Bit; subtype S2CR_DMEIE_Field is STM32F40x.Bit; subtype S2CR_TEIE_Field is STM32F40x.Bit; @@ -838,8 +785,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S2CR_Register use record EN at 0 range 0 .. 0; @@ -865,31 +811,22 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S2NDTR_Register -- - --------------------- - - subtype S2NDTR_NDT_Field is STM32F40x.Short; + subtype S2NDTR_NDT_Field is STM32F40x.UInt16; -- stream x number of data register type S2NDTR_Register is record -- Number of data items to transfer NDT : S2NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S2NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S2FCR_Register -- - -------------------- - subtype S2FCR_FTH_Field is STM32F40x.UInt2; subtype S2FCR_DMDIS_Field is STM32F40x.Bit; subtype S2FCR_FS_Field is STM32F40x.UInt3; @@ -910,8 +847,7 @@ package STM32F40x.DMA is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S2FCR_Register use record FTH at 0 range 0 .. 1; @@ -922,10 +858,6 @@ package STM32F40x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S3CR_Register -- - ------------------- - subtype S3CR_EN_Field is STM32F40x.Bit; subtype S3CR_DMEIE_Field is STM32F40x.Bit; subtype S3CR_TEIE_Field is STM32F40x.Bit; @@ -992,8 +924,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S3CR_Register use record EN at 0 range 0 .. 0; @@ -1019,31 +950,22 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S3NDTR_Register -- - --------------------- - - subtype S3NDTR_NDT_Field is STM32F40x.Short; + subtype S3NDTR_NDT_Field is STM32F40x.UInt16; -- stream x number of data register type S3NDTR_Register is record -- Number of data items to transfer NDT : S3NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S3NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S3FCR_Register -- - -------------------- - subtype S3FCR_FTH_Field is STM32F40x.UInt2; subtype S3FCR_DMDIS_Field is STM32F40x.Bit; subtype S3FCR_FS_Field is STM32F40x.UInt3; @@ -1064,8 +986,7 @@ package STM32F40x.DMA is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S3FCR_Register use record FTH at 0 range 0 .. 1; @@ -1076,10 +997,6 @@ package STM32F40x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S4CR_Register -- - ------------------- - subtype S4CR_EN_Field is STM32F40x.Bit; subtype S4CR_DMEIE_Field is STM32F40x.Bit; subtype S4CR_TEIE_Field is STM32F40x.Bit; @@ -1146,8 +1063,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S4CR_Register use record EN at 0 range 0 .. 0; @@ -1173,31 +1089,22 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S4NDTR_Register -- - --------------------- - - subtype S4NDTR_NDT_Field is STM32F40x.Short; + subtype S4NDTR_NDT_Field is STM32F40x.UInt16; -- stream x number of data register type S4NDTR_Register is record -- Number of data items to transfer NDT : S4NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S4NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S4FCR_Register -- - -------------------- - subtype S4FCR_FTH_Field is STM32F40x.UInt2; subtype S4FCR_DMDIS_Field is STM32F40x.Bit; subtype S4FCR_FS_Field is STM32F40x.UInt3; @@ -1218,8 +1125,7 @@ package STM32F40x.DMA is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S4FCR_Register use record FTH at 0 range 0 .. 1; @@ -1230,10 +1136,6 @@ package STM32F40x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S5CR_Register -- - ------------------- - subtype S5CR_EN_Field is STM32F40x.Bit; subtype S5CR_DMEIE_Field is STM32F40x.Bit; subtype S5CR_TEIE_Field is STM32F40x.Bit; @@ -1300,8 +1202,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S5CR_Register use record EN at 0 range 0 .. 0; @@ -1327,31 +1228,22 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S5NDTR_Register -- - --------------------- - - subtype S5NDTR_NDT_Field is STM32F40x.Short; + subtype S5NDTR_NDT_Field is STM32F40x.UInt16; -- stream x number of data register type S5NDTR_Register is record -- Number of data items to transfer NDT : S5NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S5NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S5FCR_Register -- - -------------------- - subtype S5FCR_FTH_Field is STM32F40x.UInt2; subtype S5FCR_DMDIS_Field is STM32F40x.Bit; subtype S5FCR_FS_Field is STM32F40x.UInt3; @@ -1372,8 +1264,7 @@ package STM32F40x.DMA is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S5FCR_Register use record FTH at 0 range 0 .. 1; @@ -1384,10 +1275,6 @@ package STM32F40x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S6CR_Register -- - ------------------- - subtype S6CR_EN_Field is STM32F40x.Bit; subtype S6CR_DMEIE_Field is STM32F40x.Bit; subtype S6CR_TEIE_Field is STM32F40x.Bit; @@ -1454,8 +1341,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S6CR_Register use record EN at 0 range 0 .. 0; @@ -1481,31 +1367,22 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S6NDTR_Register -- - --------------------- - - subtype S6NDTR_NDT_Field is STM32F40x.Short; + subtype S6NDTR_NDT_Field is STM32F40x.UInt16; -- stream x number of data register type S6NDTR_Register is record -- Number of data items to transfer NDT : S6NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S6NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S6FCR_Register -- - -------------------- - subtype S6FCR_FTH_Field is STM32F40x.UInt2; subtype S6FCR_DMDIS_Field is STM32F40x.Bit; subtype S6FCR_FS_Field is STM32F40x.UInt3; @@ -1526,8 +1403,7 @@ package STM32F40x.DMA is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S6FCR_Register use record FTH at 0 range 0 .. 1; @@ -1538,10 +1414,6 @@ package STM32F40x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S7CR_Register -- - ------------------- - subtype S7CR_EN_Field is STM32F40x.Bit; subtype S7CR_DMEIE_Field is STM32F40x.Bit; subtype S7CR_TEIE_Field is STM32F40x.Bit; @@ -1608,8 +1480,7 @@ package STM32F40x.DMA is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S7CR_Register use record EN at 0 range 0 .. 0; @@ -1635,31 +1506,22 @@ package STM32F40x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S7NDTR_Register -- - --------------------- - - subtype S7NDTR_NDT_Field is STM32F40x.Short; + subtype S7NDTR_NDT_Field is STM32F40x.UInt16; -- stream x number of data register type S7NDTR_Register is record -- Number of data items to transfer NDT : S7NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S7NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S7FCR_Register -- - -------------------- - subtype S7FCR_FTH_Field is STM32F40x.UInt2; subtype S7FCR_DMDIS_Field is STM32F40x.Bit; subtype S7FCR_FS_Field is STM32F40x.UInt3; @@ -1680,8 +1542,7 @@ package STM32F40x.DMA is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S7FCR_Register use record FTH at 0 range 0 .. 1; @@ -1699,165 +1560,193 @@ package STM32F40x.DMA is -- DMA controller type DMA_Peripheral is record -- low interrupt status register - LISR : LISR_Register; + LISR : aliased LISR_Register; + pragma Volatile_Full_Access (LISR); -- high interrupt status register - HISR : HISR_Register; + HISR : aliased HISR_Register; + pragma Volatile_Full_Access (HISR); -- low interrupt flag clear register - LIFCR : LIFCR_Register; + LIFCR : aliased LIFCR_Register; + pragma Volatile_Full_Access (LIFCR); -- high interrupt flag clear register - HIFCR : HIFCR_Register; + HIFCR : aliased HIFCR_Register; + pragma Volatile_Full_Access (HIFCR); -- stream x configuration register - S0CR : S0CR_Register; + S0CR : aliased S0CR_Register; + pragma Volatile_Full_Access (S0CR); -- stream x number of data register - S0NDTR : S0NDTR_Register; + S0NDTR : aliased S0NDTR_Register; + pragma Volatile_Full_Access (S0NDTR); -- stream x peripheral address register - S0PAR : STM32F40x.Word; + S0PAR : aliased STM32F40x.UInt32; -- stream x memory 0 address register - S0M0AR : STM32F40x.Word; + S0M0AR : aliased STM32F40x.UInt32; -- stream x memory 1 address register - S0M1AR : STM32F40x.Word; + S0M1AR : aliased STM32F40x.UInt32; -- stream x FIFO control register - S0FCR : S0FCR_Register; + S0FCR : aliased S0FCR_Register; + pragma Volatile_Full_Access (S0FCR); -- stream x configuration register - S1CR : S1CR_Register; + S1CR : aliased S1CR_Register; + pragma Volatile_Full_Access (S1CR); -- stream x number of data register - S1NDTR : S1NDTR_Register; + S1NDTR : aliased S1NDTR_Register; + pragma Volatile_Full_Access (S1NDTR); -- stream x peripheral address register - S1PAR : STM32F40x.Word; + S1PAR : aliased STM32F40x.UInt32; -- stream x memory 0 address register - S1M0AR : STM32F40x.Word; + S1M0AR : aliased STM32F40x.UInt32; -- stream x memory 1 address register - S1M1AR : STM32F40x.Word; + S1M1AR : aliased STM32F40x.UInt32; -- stream x FIFO control register - S1FCR : S1FCR_Register; + S1FCR : aliased S1FCR_Register; + pragma Volatile_Full_Access (S1FCR); -- stream x configuration register - S2CR : S2CR_Register; + S2CR : aliased S2CR_Register; + pragma Volatile_Full_Access (S2CR); -- stream x number of data register - S2NDTR : S2NDTR_Register; + S2NDTR : aliased S2NDTR_Register; + pragma Volatile_Full_Access (S2NDTR); -- stream x peripheral address register - S2PAR : STM32F40x.Word; + S2PAR : aliased STM32F40x.UInt32; -- stream x memory 0 address register - S2M0AR : STM32F40x.Word; + S2M0AR : aliased STM32F40x.UInt32; -- stream x memory 1 address register - S2M1AR : STM32F40x.Word; + S2M1AR : aliased STM32F40x.UInt32; -- stream x FIFO control register - S2FCR : S2FCR_Register; + S2FCR : aliased S2FCR_Register; + pragma Volatile_Full_Access (S2FCR); -- stream x configuration register - S3CR : S3CR_Register; + S3CR : aliased S3CR_Register; + pragma Volatile_Full_Access (S3CR); -- stream x number of data register - S3NDTR : S3NDTR_Register; + S3NDTR : aliased S3NDTR_Register; + pragma Volatile_Full_Access (S3NDTR); -- stream x peripheral address register - S3PAR : STM32F40x.Word; + S3PAR : aliased STM32F40x.UInt32; -- stream x memory 0 address register - S3M0AR : STM32F40x.Word; + S3M0AR : aliased STM32F40x.UInt32; -- stream x memory 1 address register - S3M1AR : STM32F40x.Word; + S3M1AR : aliased STM32F40x.UInt32; -- stream x FIFO control register - S3FCR : S3FCR_Register; + S3FCR : aliased S3FCR_Register; + pragma Volatile_Full_Access (S3FCR); -- stream x configuration register - S4CR : S4CR_Register; + S4CR : aliased S4CR_Register; + pragma Volatile_Full_Access (S4CR); -- stream x number of data register - S4NDTR : S4NDTR_Register; + S4NDTR : aliased S4NDTR_Register; + pragma Volatile_Full_Access (S4NDTR); -- stream x peripheral address register - S4PAR : STM32F40x.Word; + S4PAR : aliased STM32F40x.UInt32; -- stream x memory 0 address register - S4M0AR : STM32F40x.Word; + S4M0AR : aliased STM32F40x.UInt32; -- stream x memory 1 address register - S4M1AR : STM32F40x.Word; + S4M1AR : aliased STM32F40x.UInt32; -- stream x FIFO control register - S4FCR : S4FCR_Register; + S4FCR : aliased S4FCR_Register; + pragma Volatile_Full_Access (S4FCR); -- stream x configuration register - S5CR : S5CR_Register; + S5CR : aliased S5CR_Register; + pragma Volatile_Full_Access (S5CR); -- stream x number of data register - S5NDTR : S5NDTR_Register; + S5NDTR : aliased S5NDTR_Register; + pragma Volatile_Full_Access (S5NDTR); -- stream x peripheral address register - S5PAR : STM32F40x.Word; + S5PAR : aliased STM32F40x.UInt32; -- stream x memory 0 address register - S5M0AR : STM32F40x.Word; + S5M0AR : aliased STM32F40x.UInt32; -- stream x memory 1 address register - S5M1AR : STM32F40x.Word; + S5M1AR : aliased STM32F40x.UInt32; -- stream x FIFO control register - S5FCR : S5FCR_Register; + S5FCR : aliased S5FCR_Register; + pragma Volatile_Full_Access (S5FCR); -- stream x configuration register - S6CR : S6CR_Register; + S6CR : aliased S6CR_Register; + pragma Volatile_Full_Access (S6CR); -- stream x number of data register - S6NDTR : S6NDTR_Register; + S6NDTR : aliased S6NDTR_Register; + pragma Volatile_Full_Access (S6NDTR); -- stream x peripheral address register - S6PAR : STM32F40x.Word; + S6PAR : aliased STM32F40x.UInt32; -- stream x memory 0 address register - S6M0AR : STM32F40x.Word; + S6M0AR : aliased STM32F40x.UInt32; -- stream x memory 1 address register - S6M1AR : STM32F40x.Word; + S6M1AR : aliased STM32F40x.UInt32; -- stream x FIFO control register - S6FCR : S6FCR_Register; + S6FCR : aliased S6FCR_Register; + pragma Volatile_Full_Access (S6FCR); -- stream x configuration register - S7CR : S7CR_Register; + S7CR : aliased S7CR_Register; + pragma Volatile_Full_Access (S7CR); -- stream x number of data register - S7NDTR : S7NDTR_Register; + S7NDTR : aliased S7NDTR_Register; + pragma Volatile_Full_Access (S7NDTR); -- stream x peripheral address register - S7PAR : STM32F40x.Word; + S7PAR : aliased STM32F40x.UInt32; -- stream x memory 0 address register - S7M0AR : STM32F40x.Word; + S7M0AR : aliased STM32F40x.UInt32; -- stream x memory 1 address register - S7M1AR : STM32F40x.Word; + S7M1AR : aliased STM32F40x.UInt32; -- stream x FIFO control register - S7FCR : S7FCR_Register; + S7FCR : aliased S7FCR_Register; + pragma Volatile_Full_Access (S7FCR); end record with Volatile; for DMA_Peripheral use record - LISR at 0 range 0 .. 31; - HISR at 4 range 0 .. 31; - LIFCR at 8 range 0 .. 31; - HIFCR at 12 range 0 .. 31; - S0CR at 16 range 0 .. 31; - S0NDTR at 20 range 0 .. 31; - S0PAR at 24 range 0 .. 31; - S0M0AR at 28 range 0 .. 31; - S0M1AR at 32 range 0 .. 31; - S0FCR at 36 range 0 .. 31; - S1CR at 40 range 0 .. 31; - S1NDTR at 44 range 0 .. 31; - S1PAR at 48 range 0 .. 31; - S1M0AR at 52 range 0 .. 31; - S1M1AR at 56 range 0 .. 31; - S1FCR at 60 range 0 .. 31; - S2CR at 64 range 0 .. 31; - S2NDTR at 68 range 0 .. 31; - S2PAR at 72 range 0 .. 31; - S2M0AR at 76 range 0 .. 31; - S2M1AR at 80 range 0 .. 31; - S2FCR at 84 range 0 .. 31; - S3CR at 88 range 0 .. 31; - S3NDTR at 92 range 0 .. 31; - S3PAR at 96 range 0 .. 31; - S3M0AR at 100 range 0 .. 31; - S3M1AR at 104 range 0 .. 31; - S3FCR at 108 range 0 .. 31; - S4CR at 112 range 0 .. 31; - S4NDTR at 116 range 0 .. 31; - S4PAR at 120 range 0 .. 31; - S4M0AR at 124 range 0 .. 31; - S4M1AR at 128 range 0 .. 31; - S4FCR at 132 range 0 .. 31; - S5CR at 136 range 0 .. 31; - S5NDTR at 140 range 0 .. 31; - S5PAR at 144 range 0 .. 31; - S5M0AR at 148 range 0 .. 31; - S5M1AR at 152 range 0 .. 31; - S5FCR at 156 range 0 .. 31; - S6CR at 160 range 0 .. 31; - S6NDTR at 164 range 0 .. 31; - S6PAR at 168 range 0 .. 31; - S6M0AR at 172 range 0 .. 31; - S6M1AR at 176 range 0 .. 31; - S6FCR at 180 range 0 .. 31; - S7CR at 184 range 0 .. 31; - S7NDTR at 188 range 0 .. 31; - S7PAR at 192 range 0 .. 31; - S7M0AR at 196 range 0 .. 31; - S7M1AR at 200 range 0 .. 31; - S7FCR at 204 range 0 .. 31; + LISR at 16#0# range 0 .. 31; + HISR at 16#4# range 0 .. 31; + LIFCR at 16#8# range 0 .. 31; + HIFCR at 16#C# range 0 .. 31; + S0CR at 16#10# range 0 .. 31; + S0NDTR at 16#14# range 0 .. 31; + S0PAR at 16#18# range 0 .. 31; + S0M0AR at 16#1C# range 0 .. 31; + S0M1AR at 16#20# range 0 .. 31; + S0FCR at 16#24# range 0 .. 31; + S1CR at 16#28# range 0 .. 31; + S1NDTR at 16#2C# range 0 .. 31; + S1PAR at 16#30# range 0 .. 31; + S1M0AR at 16#34# range 0 .. 31; + S1M1AR at 16#38# range 0 .. 31; + S1FCR at 16#3C# range 0 .. 31; + S2CR at 16#40# range 0 .. 31; + S2NDTR at 16#44# range 0 .. 31; + S2PAR at 16#48# range 0 .. 31; + S2M0AR at 16#4C# range 0 .. 31; + S2M1AR at 16#50# range 0 .. 31; + S2FCR at 16#54# range 0 .. 31; + S3CR at 16#58# range 0 .. 31; + S3NDTR at 16#5C# range 0 .. 31; + S3PAR at 16#60# range 0 .. 31; + S3M0AR at 16#64# range 0 .. 31; + S3M1AR at 16#68# range 0 .. 31; + S3FCR at 16#6C# range 0 .. 31; + S4CR at 16#70# range 0 .. 31; + S4NDTR at 16#74# range 0 .. 31; + S4PAR at 16#78# range 0 .. 31; + S4M0AR at 16#7C# range 0 .. 31; + S4M1AR at 16#80# range 0 .. 31; + S4FCR at 16#84# range 0 .. 31; + S5CR at 16#88# range 0 .. 31; + S5NDTR at 16#8C# range 0 .. 31; + S5PAR at 16#90# range 0 .. 31; + S5M0AR at 16#94# range 0 .. 31; + S5M1AR at 16#98# range 0 .. 31; + S5FCR at 16#9C# range 0 .. 31; + S6CR at 16#A0# range 0 .. 31; + S6NDTR at 16#A4# range 0 .. 31; + S6PAR at 16#A8# range 0 .. 31; + S6M0AR at 16#AC# range 0 .. 31; + S6M1AR at 16#B0# range 0 .. 31; + S6FCR at 16#B4# range 0 .. 31; + S7CR at 16#B8# range 0 .. 31; + S7NDTR at 16#BC# range 0 .. 31; + S7PAR at 16#C0# range 0 .. 31; + S7M0AR at 16#C4# range 0 .. 31; + S7M1AR at 16#C8# range 0 .. 31; + S7FCR at 16#CC# range 0 .. 31; end record; -- DMA controller diff --git a/stm32f4/stm32f40x/stm32f40x-ethernet.ads b/stm32f4/stm32f40x/stm32f40x-ethernet.ads index 1fab14e..9994782 100644 --- a/stm32f4/stm32f40x/stm32f40x-ethernet.ads +++ b/stm32f4/stm32f40x/stm32f40x-ethernet.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,1441 +14,1356 @@ package STM32F40x.Ethernet is -- Registers -- --------------- - -------------------- - -- MACCR_Register -- - -------------------- - - subtype MACCR_RE_Field is STM32F40x.Bit; - subtype MACCR_TE_Field is STM32F40x.Bit; - subtype MACCR_DC_Field is STM32F40x.Bit; - subtype MACCR_BL_Field is STM32F40x.UInt2; - subtype MACCR_APCS_Field is STM32F40x.Bit; - subtype MACCR_RD_Field is STM32F40x.Bit; - subtype MACCR_IPCO_Field is STM32F40x.Bit; - subtype MACCR_DM_Field is STM32F40x.Bit; - subtype MACCR_LM_Field is STM32F40x.Bit; - subtype MACCR_ROD_Field is STM32F40x.Bit; - subtype MACCR_FES_Field is STM32F40x.Bit; - subtype MACCR_CSD_Field is STM32F40x.Bit; - subtype MACCR_IFG_Field is STM32F40x.UInt3; - subtype MACCR_JD_Field is STM32F40x.Bit; - subtype MACCR_WD_Field is STM32F40x.Bit; - subtype MACCR_CSTF_Field is STM32F40x.Bit; - - -- Ethernet MAC configuration register - type MACCR_Register is record - -- unspecified - Reserved_0_1 : STM32F40x.UInt2 := 16#0#; - -- RE - RE : MACCR_RE_Field := 16#0#; - -- TE - TE : MACCR_TE_Field := 16#0#; - -- DC - DC : MACCR_DC_Field := 16#0#; - -- BL - BL : MACCR_BL_Field := 16#0#; - -- APCS - APCS : MACCR_APCS_Field := 16#0#; - -- unspecified - Reserved_8_8 : STM32F40x.Bit := 16#0#; - -- RD - RD : MACCR_RD_Field := 16#0#; - -- IPCO - IPCO : MACCR_IPCO_Field := 16#0#; - -- DM - DM : MACCR_DM_Field := 16#0#; - -- LM - LM : MACCR_LM_Field := 16#0#; - -- ROD - ROD : MACCR_ROD_Field := 16#0#; - -- FES - FES : MACCR_FES_Field := 16#0#; - -- unspecified - Reserved_15_15 : STM32F40x.Bit := 16#1#; - -- CSD - CSD : MACCR_CSD_Field := 16#0#; - -- IFG - IFG : MACCR_IFG_Field := 16#0#; - -- unspecified - Reserved_20_21 : STM32F40x.UInt2 := 16#0#; - -- JD - JD : MACCR_JD_Field := 16#0#; - -- WD - WD : MACCR_WD_Field := 16#0#; - -- unspecified - Reserved_24_24 : STM32F40x.Bit := 16#0#; - -- CSTF - CSTF : MACCR_CSTF_Field := 16#0#; - -- unspecified - Reserved_26_31 : STM32F40x.UInt6 := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACCR_Register use record - Reserved_0_1 at 0 range 0 .. 1; - RE at 0 range 2 .. 2; - TE at 0 range 3 .. 3; - DC at 0 range 4 .. 4; - BL at 0 range 5 .. 6; - APCS at 0 range 7 .. 7; - Reserved_8_8 at 0 range 8 .. 8; - RD at 0 range 9 .. 9; - IPCO at 0 range 10 .. 10; - DM at 0 range 11 .. 11; - LM at 0 range 12 .. 12; - ROD at 0 range 13 .. 13; - FES at 0 range 14 .. 14; - Reserved_15_15 at 0 range 15 .. 15; - CSD at 0 range 16 .. 16; - IFG at 0 range 17 .. 19; - Reserved_20_21 at 0 range 20 .. 21; - JD at 0 range 22 .. 22; - WD at 0 range 23 .. 23; - Reserved_24_24 at 0 range 24 .. 24; - CSTF at 0 range 25 .. 25; - Reserved_26_31 at 0 range 26 .. 31; - end record; - - --------------------- - -- MACFFR_Register -- - --------------------- - - subtype MACFFR_PM_Field is STM32F40x.Bit; - subtype MACFFR_HU_Field is STM32F40x.Bit; - subtype MACFFR_HM_Field is STM32F40x.Bit; - subtype MACFFR_DAIF_Field is STM32F40x.Bit; - subtype MACFFR_RAM_Field is STM32F40x.Bit; - subtype MACFFR_BFD_Field is STM32F40x.Bit; - subtype MACFFR_PCF_Field is STM32F40x.Bit; - subtype MACFFR_SAIF_Field is STM32F40x.Bit; - subtype MACFFR_SAF_Field is STM32F40x.Bit; - subtype MACFFR_HPF_Field is STM32F40x.Bit; - subtype MACFFR_RA_Field is STM32F40x.Bit; + subtype DMABMR_SR_Field is STM32F40x.Bit; + subtype DMABMR_DA_Field is STM32F40x.Bit; + subtype DMABMR_DSL_Field is STM32F40x.UInt5; + subtype DMABMR_EDFE_Field is STM32F40x.Bit; + subtype DMABMR_PBL_Field is STM32F40x.UInt6; + subtype DMABMR_RTPR_Field is STM32F40x.UInt2; + subtype DMABMR_FB_Field is STM32F40x.Bit; + subtype DMABMR_RDP_Field is STM32F40x.UInt6; + subtype DMABMR_USP_Field is STM32F40x.Bit; + subtype DMABMR_FPM_Field is STM32F40x.Bit; + subtype DMABMR_AAB_Field is STM32F40x.Bit; + subtype DMABMR_MB_Field is STM32F40x.Bit; - -- Ethernet MAC frame filter register - type MACFFR_Register is record + -- Ethernet DMA bus mode register + type DMABMR_Register is record -- no description available - PM : MACFFR_PM_Field := 16#0#; + SR : DMABMR_SR_Field := 16#1#; -- no description available - HU : MACFFR_HU_Field := 16#0#; + DA : DMABMR_DA_Field := 16#0#; -- no description available - HM : MACFFR_HM_Field := 16#0#; + DSL : DMABMR_DSL_Field := 16#0#; -- no description available - DAIF : MACFFR_DAIF_Field := 16#0#; + EDFE : DMABMR_EDFE_Field := 16#0#; -- no description available - RAM : MACFFR_RAM_Field := 16#0#; + PBL : DMABMR_PBL_Field := 16#21#; -- no description available - BFD : MACFFR_BFD_Field := 16#0#; + RTPR : DMABMR_RTPR_Field := 16#0#; -- no description available - PCF : MACFFR_PCF_Field := 16#0#; + FB : DMABMR_FB_Field := 16#0#; -- no description available - SAIF : MACFFR_SAIF_Field := 16#0#; + RDP : DMABMR_RDP_Field := 16#0#; -- no description available - SAF : MACFFR_SAF_Field := 16#0#; + USP : DMABMR_USP_Field := 16#0#; -- no description available - HPF : MACFFR_HPF_Field := 16#0#; - -- unspecified - Reserved_10_30 : STM32F40x.UInt21 := 16#0#; + FPM : DMABMR_FPM_Field := 16#0#; -- no description available - RA : MACFFR_RA_Field := 16#0#; + AAB : DMABMR_AAB_Field := 16#0#; + -- no description available + MB : DMABMR_MB_Field := 16#0#; + -- unspecified + Reserved_27_31 : STM32F40x.UInt5 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACFFR_Register use record - PM at 0 range 0 .. 0; - HU at 0 range 1 .. 1; - HM at 0 range 2 .. 2; - DAIF at 0 range 3 .. 3; - RAM at 0 range 4 .. 4; - BFD at 0 range 5 .. 5; - PCF at 0 range 6 .. 6; - SAIF at 0 range 7 .. 7; - SAF at 0 range 8 .. 8; - HPF at 0 range 9 .. 9; - Reserved_10_30 at 0 range 10 .. 30; - RA at 0 range 31 .. 31; + for DMABMR_Register use record + SR at 0 range 0 .. 0; + DA at 0 range 1 .. 1; + DSL at 0 range 2 .. 6; + EDFE at 0 range 7 .. 7; + PBL at 0 range 8 .. 13; + RTPR at 0 range 14 .. 15; + FB at 0 range 16 .. 16; + RDP at 0 range 17 .. 22; + USP at 0 range 23 .. 23; + FPM at 0 range 24 .. 24; + AAB at 0 range 25 .. 25; + MB at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; end record; - ----------------------- - -- MACMIIAR_Register -- - ----------------------- - - subtype MACMIIAR_MB_Field is STM32F40x.Bit; - subtype MACMIIAR_MW_Field is STM32F40x.Bit; - subtype MACMIIAR_CR_Field is STM32F40x.UInt3; - subtype MACMIIAR_MR_Field is STM32F40x.UInt5; - subtype MACMIIAR_PA_Field is STM32F40x.UInt5; + subtype DMASR_TS_Field is STM32F40x.Bit; + subtype DMASR_TPSS_Field is STM32F40x.Bit; + subtype DMASR_TBUS_Field is STM32F40x.Bit; + subtype DMASR_TJTS_Field is STM32F40x.Bit; + subtype DMASR_ROS_Field is STM32F40x.Bit; + subtype DMASR_TUS_Field is STM32F40x.Bit; + subtype DMASR_RS_Field is STM32F40x.Bit; + subtype DMASR_RBUS_Field is STM32F40x.Bit; + subtype DMASR_RPSS_Field is STM32F40x.Bit; + subtype DMASR_PWTS_Field is STM32F40x.Bit; + subtype DMASR_ETS_Field is STM32F40x.Bit; + subtype DMASR_FBES_Field is STM32F40x.Bit; + subtype DMASR_ERS_Field is STM32F40x.Bit; + subtype DMASR_AIS_Field is STM32F40x.Bit; + subtype DMASR_NIS_Field is STM32F40x.Bit; + subtype DMASR_RPS_Field is STM32F40x.UInt3; + subtype DMASR_TPS_Field is STM32F40x.UInt3; + subtype DMASR_EBS_Field is STM32F40x.UInt3; + subtype DMASR_MMCS_Field is STM32F40x.Bit; + subtype DMASR_PMTS_Field is STM32F40x.Bit; + subtype DMASR_TSTS_Field is STM32F40x.Bit; - -- Ethernet MAC MII address register - type MACMIIAR_Register is record + -- Ethernet DMA status register + type DMASR_Register is record -- no description available - MB : MACMIIAR_MB_Field := 16#0#; + TS : DMASR_TS_Field := 16#0#; -- no description available - MW : MACMIIAR_MW_Field := 16#0#; + TPSS : DMASR_TPSS_Field := 16#0#; -- no description available - CR : MACMIIAR_CR_Field := 16#0#; + TBUS : DMASR_TBUS_Field := 16#0#; + -- no description available + TJTS : DMASR_TJTS_Field := 16#0#; + -- no description available + ROS : DMASR_ROS_Field := 16#0#; + -- no description available + TUS : DMASR_TUS_Field := 16#0#; + -- no description available + RS : DMASR_RS_Field := 16#0#; + -- no description available + RBUS : DMASR_RBUS_Field := 16#0#; + -- no description available + RPSS : DMASR_RPSS_Field := 16#0#; + -- no description available + PWTS : DMASR_PWTS_Field := 16#0#; + -- no description available + ETS : DMASR_ETS_Field := 16#0#; -- unspecified - Reserved_5_5 : STM32F40x.Bit := 16#0#; + Reserved_11_12 : STM32F40x.UInt2 := 16#0#; -- no description available - MR : MACMIIAR_MR_Field := 16#0#; + FBES : DMASR_FBES_Field := 16#0#; -- no description available - PA : MACMIIAR_PA_Field := 16#0#; + ERS : DMASR_ERS_Field := 16#0#; + -- no description available + AIS : DMASR_AIS_Field := 16#0#; + -- no description available + NIS : DMASR_NIS_Field := 16#0#; + -- Read-only. no description available + RPS : DMASR_RPS_Field := 16#0#; + -- Read-only. no description available + TPS : DMASR_TPS_Field := 16#0#; + -- Read-only. no description available + EBS : DMASR_EBS_Field := 16#0#; + -- unspecified + Reserved_26_26 : STM32F40x.Bit := 16#0#; + -- Read-only. no description available + MMCS : DMASR_MMCS_Field := 16#0#; + -- Read-only. no description available + PMTS : DMASR_PMTS_Field := 16#0#; + -- Read-only. no description available + TSTS : DMASR_TSTS_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACMIIAR_Register use record - MB at 0 range 0 .. 0; - MW at 0 range 1 .. 1; - CR at 0 range 2 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - MR at 0 range 6 .. 10; - PA at 0 range 11 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for DMASR_Register use record + TS at 0 range 0 .. 0; + TPSS at 0 range 1 .. 1; + TBUS at 0 range 2 .. 2; + TJTS at 0 range 3 .. 3; + ROS at 0 range 4 .. 4; + TUS at 0 range 5 .. 5; + RS at 0 range 6 .. 6; + RBUS at 0 range 7 .. 7; + RPSS at 0 range 8 .. 8; + PWTS at 0 range 9 .. 9; + ETS at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + FBES at 0 range 13 .. 13; + ERS at 0 range 14 .. 14; + AIS at 0 range 15 .. 15; + NIS at 0 range 16 .. 16; + RPS at 0 range 17 .. 19; + TPS at 0 range 20 .. 22; + EBS at 0 range 23 .. 25; + Reserved_26_26 at 0 range 26 .. 26; + MMCS at 0 range 27 .. 27; + PMTS at 0 range 28 .. 28; + TSTS at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; end record; - ----------------------- - -- MACMIIDR_Register -- - ----------------------- - - subtype MACMIIDR_TD_Field is STM32F40x.Short; + subtype DMAOMR_SR_Field is STM32F40x.Bit; + subtype DMAOMR_OSF_Field is STM32F40x.Bit; + subtype DMAOMR_RTC_Field is STM32F40x.UInt2; + subtype DMAOMR_FUGF_Field is STM32F40x.Bit; + subtype DMAOMR_FEF_Field is STM32F40x.Bit; + subtype DMAOMR_ST_Field is STM32F40x.Bit; + subtype DMAOMR_TTC_Field is STM32F40x.UInt3; + subtype DMAOMR_FTF_Field is STM32F40x.Bit; + subtype DMAOMR_TSF_Field is STM32F40x.Bit; + subtype DMAOMR_DFRF_Field is STM32F40x.Bit; + subtype DMAOMR_RSF_Field is STM32F40x.Bit; + subtype DMAOMR_DTCEFD_Field is STM32F40x.Bit; - -- Ethernet MAC MII data register - type MACMIIDR_Register is record - -- no description available - TD : MACMIIDR_TD_Field := 16#0#; + -- Ethernet DMA operation mode register + type DMAOMR_Register is record + -- unspecified + Reserved_0_0 : STM32F40x.Bit := 16#0#; + -- SR + SR : DMAOMR_SR_Field := 16#0#; + -- OSF + OSF : DMAOMR_OSF_Field := 16#0#; + -- RTC + RTC : DMAOMR_RTC_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F40x.Bit := 16#0#; + -- FUGF + FUGF : DMAOMR_FUGF_Field := 16#0#; + -- FEF + FEF : DMAOMR_FEF_Field := 16#0#; + -- unspecified + Reserved_8_12 : STM32F40x.UInt5 := 16#0#; + -- ST + ST : DMAOMR_ST_Field := 16#0#; + -- TTC + TTC : DMAOMR_TTC_Field := 16#0#; + -- unspecified + Reserved_17_19 : STM32F40x.UInt3 := 16#0#; + -- FTF + FTF : DMAOMR_FTF_Field := 16#0#; + -- TSF + TSF : DMAOMR_TSF_Field := 16#0#; + -- unspecified + Reserved_22_23 : STM32F40x.UInt2 := 16#0#; + -- DFRF + DFRF : DMAOMR_DFRF_Field := 16#0#; + -- RSF + RSF : DMAOMR_RSF_Field := 16#0#; + -- DTCEFD + DTCEFD : DMAOMR_DTCEFD_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_27_31 : STM32F40x.UInt5 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACMIIDR_Register use record - TD at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for DMAOMR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + SR at 0 range 1 .. 1; + OSF at 0 range 2 .. 2; + RTC at 0 range 3 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + FUGF at 0 range 6 .. 6; + FEF at 0 range 7 .. 7; + Reserved_8_12 at 0 range 8 .. 12; + ST at 0 range 13 .. 13; + TTC at 0 range 14 .. 16; + Reserved_17_19 at 0 range 17 .. 19; + FTF at 0 range 20 .. 20; + TSF at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + DFRF at 0 range 24 .. 24; + RSF at 0 range 25 .. 25; + DTCEFD at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; end record; - --------------------- - -- MACFCR_Register -- - --------------------- - - subtype MACFCR_FCB_Field is STM32F40x.Bit; - subtype MACFCR_TFCE_Field is STM32F40x.Bit; - subtype MACFCR_RFCE_Field is STM32F40x.Bit; - subtype MACFCR_UPFD_Field is STM32F40x.Bit; - subtype MACFCR_PLT_Field is STM32F40x.UInt2; - subtype MACFCR_ZQPD_Field is STM32F40x.Bit; - subtype MACFCR_PT_Field is STM32F40x.Short; + subtype DMAIER_TIE_Field is STM32F40x.Bit; + subtype DMAIER_TPSIE_Field is STM32F40x.Bit; + subtype DMAIER_TBUIE_Field is STM32F40x.Bit; + subtype DMAIER_TJTIE_Field is STM32F40x.Bit; + subtype DMAIER_ROIE_Field is STM32F40x.Bit; + subtype DMAIER_TUIE_Field is STM32F40x.Bit; + subtype DMAIER_RIE_Field is STM32F40x.Bit; + subtype DMAIER_RBUIE_Field is STM32F40x.Bit; + subtype DMAIER_RPSIE_Field is STM32F40x.Bit; + subtype DMAIER_RWTIE_Field is STM32F40x.Bit; + subtype DMAIER_ETIE_Field is STM32F40x.Bit; + subtype DMAIER_FBEIE_Field is STM32F40x.Bit; + subtype DMAIER_ERIE_Field is STM32F40x.Bit; + subtype DMAIER_AISE_Field is STM32F40x.Bit; + subtype DMAIER_NISE_Field is STM32F40x.Bit; - -- Ethernet MAC flow control register - type MACFCR_Register is record + -- Ethernet DMA interrupt enable register + type DMAIER_Register is record -- no description available - FCB : MACFCR_FCB_Field := 16#0#; + TIE : DMAIER_TIE_Field := 16#0#; -- no description available - TFCE : MACFCR_TFCE_Field := 16#0#; + TPSIE : DMAIER_TPSIE_Field := 16#0#; -- no description available - RFCE : MACFCR_RFCE_Field := 16#0#; + TBUIE : DMAIER_TBUIE_Field := 16#0#; -- no description available - UPFD : MACFCR_UPFD_Field := 16#0#; + TJTIE : DMAIER_TJTIE_Field := 16#0#; -- no description available - PLT : MACFCR_PLT_Field := 16#0#; - -- unspecified - Reserved_6_6 : STM32F40x.Bit := 16#0#; + ROIE : DMAIER_ROIE_Field := 16#0#; -- no description available - ZQPD : MACFCR_ZQPD_Field := 16#0#; + TUIE : DMAIER_TUIE_Field := 16#0#; + -- no description available + RIE : DMAIER_RIE_Field := 16#0#; + -- no description available + RBUIE : DMAIER_RBUIE_Field := 16#0#; + -- no description available + RPSIE : DMAIER_RPSIE_Field := 16#0#; + -- no description available + RWTIE : DMAIER_RWTIE_Field := 16#0#; + -- no description available + ETIE : DMAIER_ETIE_Field := 16#0#; -- unspecified - Reserved_8_15 : STM32F40x.Byte := 16#0#; + Reserved_11_12 : STM32F40x.UInt2 := 16#0#; -- no description available - PT : MACFCR_PT_Field := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACFCR_Register use record - FCB at 0 range 0 .. 0; - TFCE at 0 range 1 .. 1; - RFCE at 0 range 2 .. 2; - UPFD at 0 range 3 .. 3; - PLT at 0 range 4 .. 5; - Reserved_6_6 at 0 range 6 .. 6; - ZQPD at 0 range 7 .. 7; - Reserved_8_15 at 0 range 8 .. 15; - PT at 0 range 16 .. 31; - end record; - - ------------------------ - -- MACVLANTR_Register -- - ------------------------ - - subtype MACVLANTR_VLANTI_Field is STM32F40x.Short; - subtype MACVLANTR_VLANTC_Field is STM32F40x.Bit; - - -- Ethernet MAC VLAN tag register - type MACVLANTR_Register is record + FBEIE : DMAIER_FBEIE_Field := 16#0#; -- no description available - VLANTI : MACVLANTR_VLANTI_Field := 16#0#; + ERIE : DMAIER_ERIE_Field := 16#0#; -- no description available - VLANTC : MACVLANTR_VLANTC_Field := 16#0#; + AISE : DMAIER_AISE_Field := 16#0#; + -- no description available + NISE : DMAIER_NISE_Field := 16#0#; -- unspecified Reserved_17_31 : STM32F40x.UInt15 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACVLANTR_Register use record - VLANTI at 0 range 0 .. 15; - VLANTC at 0 range 16 .. 16; + for DMAIER_Register use record + TIE at 0 range 0 .. 0; + TPSIE at 0 range 1 .. 1; + TBUIE at 0 range 2 .. 2; + TJTIE at 0 range 3 .. 3; + ROIE at 0 range 4 .. 4; + TUIE at 0 range 5 .. 5; + RIE at 0 range 6 .. 6; + RBUIE at 0 range 7 .. 7; + RPSIE at 0 range 8 .. 8; + RWTIE at 0 range 9 .. 9; + ETIE at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + FBEIE at 0 range 13 .. 13; + ERIE at 0 range 14 .. 14; + AISE at 0 range 15 .. 15; + NISE at 0 range 16 .. 16; Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------------ - -- MACPMTCSR_Register -- - ------------------------ - - subtype MACPMTCSR_PD_Field is STM32F40x.Bit; - subtype MACPMTCSR_MPE_Field is STM32F40x.Bit; - subtype MACPMTCSR_WFE_Field is STM32F40x.Bit; - subtype MACPMTCSR_MPR_Field is STM32F40x.Bit; - subtype MACPMTCSR_WFR_Field is STM32F40x.Bit; - subtype MACPMTCSR_GU_Field is STM32F40x.Bit; - subtype MACPMTCSR_WFFRPR_Field is STM32F40x.Bit; + subtype DMAMFBOCR_MFC_Field is STM32F40x.UInt16; + subtype DMAMFBOCR_OMFC_Field is STM32F40x.Bit; + subtype DMAMFBOCR_MFA_Field is STM32F40x.UInt11; + subtype DMAMFBOCR_OFOC_Field is STM32F40x.Bit; - -- Ethernet MAC PMT control and status register - type MACPMTCSR_Register is record - -- no description available - PD : MACPMTCSR_PD_Field := 16#0#; - -- no description available - MPE : MACPMTCSR_MPE_Field := 16#0#; + -- Ethernet DMA missed frame and buffer overflow counter register + type DMAMFBOCR_Register is record -- no description available - WFE : MACPMTCSR_WFE_Field := 16#0#; - -- unspecified - Reserved_3_4 : STM32F40x.UInt2 := 16#0#; + MFC : DMAMFBOCR_MFC_Field := 16#0#; -- no description available - MPR : MACPMTCSR_MPR_Field := 16#0#; + OMFC : DMAMFBOCR_OMFC_Field := 16#0#; -- no description available - WFR : MACPMTCSR_WFR_Field := 16#0#; - -- unspecified - Reserved_7_8 : STM32F40x.UInt2 := 16#0#; + MFA : DMAMFBOCR_MFA_Field := 16#0#; -- no description available - GU : MACPMTCSR_GU_Field := 16#0#; + OFOC : DMAMFBOCR_OFOC_Field := 16#0#; -- unspecified - Reserved_10_30 : STM32F40x.UInt21 := 16#0#; - -- no description available - WFFRPR : MACPMTCSR_WFFRPR_Field := 16#0#; + Reserved_29_31 : STM32F40x.UInt3 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACPMTCSR_Register use record - PD at 0 range 0 .. 0; - MPE at 0 range 1 .. 1; - WFE at 0 range 2 .. 2; - Reserved_3_4 at 0 range 3 .. 4; - MPR at 0 range 5 .. 5; - WFR at 0 range 6 .. 6; - Reserved_7_8 at 0 range 7 .. 8; - GU at 0 range 9 .. 9; - Reserved_10_30 at 0 range 10 .. 30; - WFFRPR at 0 range 31 .. 31; - end record; - - ---------------------- - -- MACDBGR_Register -- - ---------------------- + with Object_Size => 32, Bit_Order => System.Low_Order_First; - subtype MACDBGR_CR_Field is STM32F40x.Bit; - subtype MACDBGR_CSR_Field is STM32F40x.Bit; - subtype MACDBGR_ROR_Field is STM32F40x.Bit; - subtype MACDBGR_MCF_Field is STM32F40x.Bit; - subtype MACDBGR_MCP_Field is STM32F40x.Bit; - subtype MACDBGR_MCFHP_Field is STM32F40x.Bit; - - -- Ethernet MAC debug register - type MACDBGR_Register is record - -- Read-only. CR - CR : MACDBGR_CR_Field := 16#0#; - -- Read-only. CSR - CSR : MACDBGR_CSR_Field := 16#0#; - -- Read-only. ROR - ROR : MACDBGR_ROR_Field := 16#0#; - -- Read-only. MCF - MCF : MACDBGR_MCF_Field := 16#0#; - -- Read-only. MCP - MCP : MACDBGR_MCP_Field := 16#0#; - -- Read-only. MCFHP - MCFHP : MACDBGR_MCFHP_Field := 16#0#; - -- unspecified - Reserved_6_31 : STM32F40x.UInt26; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACDBGR_Register use record - CR at 0 range 0 .. 0; - CSR at 0 range 1 .. 1; - ROR at 0 range 2 .. 2; - MCF at 0 range 3 .. 3; - MCP at 0 range 4 .. 4; - MCFHP at 0 range 5 .. 5; - Reserved_6_31 at 0 range 6 .. 31; + for DMAMFBOCR_Register use record + MFC at 0 range 0 .. 15; + OMFC at 0 range 16 .. 16; + MFA at 0 range 17 .. 27; + OFOC at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; end record; - -------------------- - -- MACSR_Register -- - -------------------- - - subtype MACSR_PMTS_Field is STM32F40x.Bit; - subtype MACSR_MMCS_Field is STM32F40x.Bit; - subtype MACSR_MMCRS_Field is STM32F40x.Bit; - subtype MACSR_MMCTS_Field is STM32F40x.Bit; - subtype MACSR_TSTS_Field is STM32F40x.Bit; + subtype DMARSWTR_RSWTC_Field is STM32F40x.Byte; - -- Ethernet MAC interrupt status register - type MACSR_Register is record - -- unspecified - Reserved_0_2 : STM32F40x.UInt3 := 16#0#; - -- Read-only. no description available - PMTS : MACSR_PMTS_Field := 16#0#; - -- Read-only. no description available - MMCS : MACSR_MMCS_Field := 16#0#; - -- Read-only. no description available - MMCRS : MACSR_MMCRS_Field := 16#0#; - -- Read-only. no description available - MMCTS : MACSR_MMCTS_Field := 16#0#; - -- unspecified - Reserved_7_8 : STM32F40x.UInt2 := 16#0#; - -- no description available - TSTS : MACSR_TSTS_Field := 16#0#; + -- Ethernet DMA receive status watchdog timer register + type DMARSWTR_Register is record + -- RSWTC + RSWTC : DMARSWTR_RSWTC_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F40x.UInt22 := 16#0#; + Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACSR_Register use record - Reserved_0_2 at 0 range 0 .. 2; - PMTS at 0 range 3 .. 3; - MMCS at 0 range 4 .. 4; - MMCRS at 0 range 5 .. 5; - MMCTS at 0 range 6 .. 6; - Reserved_7_8 at 0 range 7 .. 8; - TSTS at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + for DMARSWTR_Register use record + RSWTC at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- MACIMR_Register -- - --------------------- - - subtype MACIMR_PMTIM_Field is STM32F40x.Bit; - subtype MACIMR_TSTIM_Field is STM32F40x.Bit; + subtype MACCR_RE_Field is STM32F40x.Bit; + subtype MACCR_TE_Field is STM32F40x.Bit; + subtype MACCR_DC_Field is STM32F40x.Bit; + subtype MACCR_BL_Field is STM32F40x.UInt2; + subtype MACCR_APCS_Field is STM32F40x.Bit; + subtype MACCR_RD_Field is STM32F40x.Bit; + subtype MACCR_IPCO_Field is STM32F40x.Bit; + subtype MACCR_DM_Field is STM32F40x.Bit; + subtype MACCR_LM_Field is STM32F40x.Bit; + subtype MACCR_ROD_Field is STM32F40x.Bit; + subtype MACCR_FES_Field is STM32F40x.Bit; + subtype MACCR_CSD_Field is STM32F40x.Bit; + subtype MACCR_IFG_Field is STM32F40x.UInt3; + subtype MACCR_JD_Field is STM32F40x.Bit; + subtype MACCR_WD_Field is STM32F40x.Bit; + subtype MACCR_CSTF_Field is STM32F40x.Bit; - -- Ethernet MAC interrupt mask register - type MACIMR_Register is record - -- unspecified - Reserved_0_2 : STM32F40x.UInt3 := 16#0#; - -- no description available - PMTIM : MACIMR_PMTIM_Field := 16#0#; + -- Ethernet MAC configuration register + type MACCR_Register is record -- unspecified - Reserved_4_8 : STM32F40x.UInt5 := 16#0#; - -- no description available - TSTIM : MACIMR_TSTIM_Field := 16#0#; + Reserved_0_1 : STM32F40x.UInt2 := 16#0#; + -- RE + RE : MACCR_RE_Field := 16#0#; + -- TE + TE : MACCR_TE_Field := 16#0#; + -- DC + DC : MACCR_DC_Field := 16#0#; + -- BL + BL : MACCR_BL_Field := 16#0#; + -- APCS + APCS : MACCR_APCS_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F40x.UInt22 := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACIMR_Register use record - Reserved_0_2 at 0 range 0 .. 2; - PMTIM at 0 range 3 .. 3; - Reserved_4_8 at 0 range 4 .. 8; - TSTIM at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; - end record; - - ---------------------- - -- MACA0HR_Register -- - ---------------------- - - subtype MACA0HR_MACA0H_Field is STM32F40x.Short; - subtype MACA0HR_MO_Field is STM32F40x.Bit; - - -- Ethernet MAC address 0 high register - type MACA0HR_Register is record - -- MAC address0 high - MACA0H : MACA0HR_MACA0H_Field := 16#FFFF#; + Reserved_8_8 : STM32F40x.Bit := 16#0#; + -- RD + RD : MACCR_RD_Field := 16#0#; + -- IPCO + IPCO : MACCR_IPCO_Field := 16#0#; + -- DM + DM : MACCR_DM_Field := 16#0#; + -- LM + LM : MACCR_LM_Field := 16#0#; + -- ROD + ROD : MACCR_ROD_Field := 16#0#; + -- FES + FES : MACCR_FES_Field := 16#0#; -- unspecified - Reserved_16_30 : STM32F40x.UInt15 := 16#10#; - -- Read-only. Always 1 - MO : MACA0HR_MO_Field := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACA0HR_Register use record - MACA0H at 0 range 0 .. 15; - Reserved_16_30 at 0 range 16 .. 30; - MO at 0 range 31 .. 31; - end record; - - ---------------------- - -- MACA1HR_Register -- - ---------------------- - - subtype MACA1HR_MACA1H_Field is STM32F40x.Short; - subtype MACA1HR_MBC_Field is STM32F40x.UInt6; - subtype MACA1HR_SA_Field is STM32F40x.Bit; - subtype MACA1HR_AE_Field is STM32F40x.Bit; - - -- Ethernet MAC address 1 high register - type MACA1HR_Register is record - -- no description available - MACA1H : MACA1HR_MACA1H_Field := 16#FFFF#; + Reserved_15_15 : STM32F40x.Bit := 16#1#; + -- CSD + CSD : MACCR_CSD_Field := 16#0#; + -- IFG + IFG : MACCR_IFG_Field := 16#0#; -- unspecified - Reserved_16_23 : STM32F40x.Byte := 16#0#; - -- no description available - MBC : MACA1HR_MBC_Field := 16#0#; - -- no description available - SA : MACA1HR_SA_Field := 16#0#; - -- no description available - AE : MACA1HR_AE_Field := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACA1HR_Register use record - MACA1H at 0 range 0 .. 15; - Reserved_16_23 at 0 range 16 .. 23; - MBC at 0 range 24 .. 29; - SA at 0 range 30 .. 30; - AE at 0 range 31 .. 31; - end record; - - ---------------------- - -- MACA2HR_Register -- - ---------------------- - - subtype MACA2HR_MAC2AH_Field is STM32F40x.Short; - subtype MACA2HR_MBC_Field is STM32F40x.UInt6; - subtype MACA2HR_SA_Field is STM32F40x.Bit; - subtype MACA2HR_AE_Field is STM32F40x.Bit; - - -- Ethernet MAC address 2 high register - type MACA2HR_Register is record - -- no description available - MAC2AH : MACA2HR_MAC2AH_Field := 16#FFFF#; + Reserved_20_21 : STM32F40x.UInt2 := 16#0#; + -- JD + JD : MACCR_JD_Field := 16#0#; + -- WD + WD : MACCR_WD_Field := 16#0#; -- unspecified - Reserved_16_23 : STM32F40x.Byte := 16#0#; - -- no description available - MBC : MACA2HR_MBC_Field := 16#0#; - -- no description available - SA : MACA2HR_SA_Field := 16#0#; - -- no description available - AE : MACA2HR_AE_Field := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACA2HR_Register use record - MAC2AH at 0 range 0 .. 15; - Reserved_16_23 at 0 range 16 .. 23; - MBC at 0 range 24 .. 29; - SA at 0 range 30 .. 30; - AE at 0 range 31 .. 31; - end record; - - ---------------------- - -- MACA2LR_Register -- - ---------------------- - - subtype MACA2LR_MACA2L_Field is STM32F40x.UInt31; - - -- Ethernet MAC address 2 low register - type MACA2LR_Register is record - -- no description available - MACA2L : MACA2LR_MACA2L_Field := 16#7FFFFFFF#; + Reserved_24_24 : STM32F40x.Bit := 16#0#; + -- CSTF + CSTF : MACCR_CSTF_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F40x.Bit := 16#1#; + Reserved_26_31 : STM32F40x.UInt6 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACA2LR_Register use record - MACA2L at 0 range 0 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for MACCR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + RE at 0 range 2 .. 2; + TE at 0 range 3 .. 3; + DC at 0 range 4 .. 4; + BL at 0 range 5 .. 6; + APCS at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + RD at 0 range 9 .. 9; + IPCO at 0 range 10 .. 10; + DM at 0 range 11 .. 11; + LM at 0 range 12 .. 12; + ROD at 0 range 13 .. 13; + FES at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + CSD at 0 range 16 .. 16; + IFG at 0 range 17 .. 19; + Reserved_20_21 at 0 range 20 .. 21; + JD at 0 range 22 .. 22; + WD at 0 range 23 .. 23; + Reserved_24_24 at 0 range 24 .. 24; + CSTF at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; end record; - ---------------------- - -- MACA3HR_Register -- - ---------------------- - - subtype MACA3HR_MACA3H_Field is STM32F40x.Short; - subtype MACA3HR_MBC_Field is STM32F40x.UInt6; - subtype MACA3HR_SA_Field is STM32F40x.Bit; - subtype MACA3HR_AE_Field is STM32F40x.Bit; + subtype MACFFR_PM_Field is STM32F40x.Bit; + subtype MACFFR_HU_Field is STM32F40x.Bit; + subtype MACFFR_HM_Field is STM32F40x.Bit; + subtype MACFFR_DAIF_Field is STM32F40x.Bit; + subtype MACFFR_RAM_Field is STM32F40x.Bit; + subtype MACFFR_BFD_Field is STM32F40x.Bit; + subtype MACFFR_PCF_Field is STM32F40x.Bit; + subtype MACFFR_SAIF_Field is STM32F40x.Bit; + subtype MACFFR_SAF_Field is STM32F40x.Bit; + subtype MACFFR_HPF_Field is STM32F40x.Bit; + subtype MACFFR_RA_Field is STM32F40x.Bit; - -- Ethernet MAC address 3 high register - type MACA3HR_Register is record + -- Ethernet MAC frame filter register + type MACFFR_Register is record -- no description available - MACA3H : MACA3HR_MACA3H_Field := 16#FFFF#; - -- unspecified - Reserved_16_23 : STM32F40x.Byte := 16#0#; + PM : MACFFR_PM_Field := 16#0#; -- no description available - MBC : MACA3HR_MBC_Field := 16#0#; + HU : MACFFR_HU_Field := 16#0#; -- no description available - SA : MACA3HR_SA_Field := 16#0#; + HM : MACFFR_HM_Field := 16#0#; -- no description available - AE : MACA3HR_AE_Field := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for MACA3HR_Register use record - MACA3H at 0 range 0 .. 15; - Reserved_16_23 at 0 range 16 .. 23; - MBC at 0 range 24 .. 29; - SA at 0 range 30 .. 30; - AE at 0 range 31 .. 31; - end record; - - -------------------- - -- MMCCR_Register -- - -------------------- - - subtype MMCCR_CR_Field is STM32F40x.Bit; - subtype MMCCR_CSR_Field is STM32F40x.Bit; - subtype MMCCR_ROR_Field is STM32F40x.Bit; - subtype MMCCR_MCF_Field is STM32F40x.Bit; - subtype MMCCR_MCP_Field is STM32F40x.Bit; - subtype MMCCR_MCFHP_Field is STM32F40x.Bit; - - -- Ethernet MMC control register - type MMCCR_Register is record + DAIF : MACFFR_DAIF_Field := 16#0#; -- no description available - CR : MMCCR_CR_Field := 16#0#; + RAM : MACFFR_RAM_Field := 16#0#; -- no description available - CSR : MMCCR_CSR_Field := 16#0#; + BFD : MACFFR_BFD_Field := 16#0#; -- no description available - ROR : MMCCR_ROR_Field := 16#0#; + PCF : MACFFR_PCF_Field := 16#0#; -- no description available - MCF : MMCCR_MCF_Field := 16#0#; + SAIF : MACFFR_SAIF_Field := 16#0#; -- no description available - MCP : MMCCR_MCP_Field := 16#0#; + SAF : MACFFR_SAF_Field := 16#0#; -- no description available - MCFHP : MMCCR_MCFHP_Field := 16#0#; + HPF : MACFFR_HPF_Field := 16#0#; -- unspecified - Reserved_6_31 : STM32F40x.UInt26 := 16#0#; + Reserved_10_30 : STM32F40x.UInt21 := 16#0#; + -- no description available + RA : MACFFR_RA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MMCCR_Register use record - CR at 0 range 0 .. 0; - CSR at 0 range 1 .. 1; - ROR at 0 range 2 .. 2; - MCF at 0 range 3 .. 3; - MCP at 0 range 4 .. 4; - MCFHP at 0 range 5 .. 5; - Reserved_6_31 at 0 range 6 .. 31; + for MACFFR_Register use record + PM at 0 range 0 .. 0; + HU at 0 range 1 .. 1; + HM at 0 range 2 .. 2; + DAIF at 0 range 3 .. 3; + RAM at 0 range 4 .. 4; + BFD at 0 range 5 .. 5; + PCF at 0 range 6 .. 6; + SAIF at 0 range 7 .. 7; + SAF at 0 range 8 .. 8; + HPF at 0 range 9 .. 9; + Reserved_10_30 at 0 range 10 .. 30; + RA at 0 range 31 .. 31; end record; - --------------------- - -- MMCRIR_Register -- - --------------------- - - subtype MMCRIR_RFCES_Field is STM32F40x.Bit; - subtype MMCRIR_RFAES_Field is STM32F40x.Bit; - subtype MMCRIR_RGUFS_Field is STM32F40x.Bit; + subtype MACMIIAR_MB_Field is STM32F40x.Bit; + subtype MACMIIAR_MW_Field is STM32F40x.Bit; + subtype MACMIIAR_CR_Field is STM32F40x.UInt3; + subtype MACMIIAR_MR_Field is STM32F40x.UInt5; + subtype MACMIIAR_PA_Field is STM32F40x.UInt5; - -- Ethernet MMC receive interrupt register - type MMCRIR_Register is record - -- unspecified - Reserved_0_4 : STM32F40x.UInt5 := 16#0#; + -- Ethernet MAC MII address register + type MACMIIAR_Register is record -- no description available - RFCES : MMCRIR_RFCES_Field := 16#0#; + MB : MACMIIAR_MB_Field := 16#0#; -- no description available - RFAES : MMCRIR_RFAES_Field := 16#0#; + MW : MACMIIAR_MW_Field := 16#0#; + -- no description available + CR : MACMIIAR_CR_Field := 16#0#; -- unspecified - Reserved_7_16 : STM32F40x.UInt10 := 16#0#; + Reserved_5_5 : STM32F40x.Bit := 16#0#; -- no description available - RGUFS : MMCRIR_RGUFS_Field := 16#0#; + MR : MACMIIAR_MR_Field := 16#0#; + -- no description available + PA : MACMIIAR_PA_Field := 16#0#; -- unspecified - Reserved_18_31 : STM32F40x.UInt14 := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MMCRIR_Register use record - Reserved_0_4 at 0 range 0 .. 4; - RFCES at 0 range 5 .. 5; - RFAES at 0 range 6 .. 6; - Reserved_7_16 at 0 range 7 .. 16; - RGUFS at 0 range 17 .. 17; - Reserved_18_31 at 0 range 18 .. 31; + for MACMIIAR_Register use record + MB at 0 range 0 .. 0; + MW at 0 range 1 .. 1; + CR at 0 range 2 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + MR at 0 range 6 .. 10; + PA at 0 range 11 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- MMCTIR_Register -- - --------------------- - - subtype MMCTIR_TGFSCS_Field is STM32F40x.Bit; - subtype MMCTIR_TGFMSCS_Field is STM32F40x.Bit; - subtype MMCTIR_TGFS_Field is STM32F40x.Bit; + subtype MACMIIDR_TD_Field is STM32F40x.UInt16; - -- Ethernet MMC transmit interrupt register - type MMCTIR_Register is record - -- unspecified - Reserved_0_13 : STM32F40x.UInt14; - -- Read-only. no description available - TGFSCS : MMCTIR_TGFSCS_Field := 16#0#; - -- Read-only. no description available - TGFMSCS : MMCTIR_TGFMSCS_Field := 16#0#; - -- unspecified - Reserved_16_20 : STM32F40x.UInt5; - -- Read-only. no description available - TGFS : MMCTIR_TGFS_Field := 16#0#; + -- Ethernet MAC MII data register + type MACMIIDR_Register is record + -- no description available + TD : MACMIIDR_TD_Field := 16#0#; -- unspecified - Reserved_22_31 : STM32F40x.UInt10; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MMCTIR_Register use record - Reserved_0_13 at 0 range 0 .. 13; - TGFSCS at 0 range 14 .. 14; - TGFMSCS at 0 range 15 .. 15; - Reserved_16_20 at 0 range 16 .. 20; - TGFS at 0 range 21 .. 21; - Reserved_22_31 at 0 range 22 .. 31; + for MACMIIDR_Register use record + TD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- MMCRIMR_Register -- - ---------------------- - - subtype MMCRIMR_RFCEM_Field is STM32F40x.Bit; - subtype MMCRIMR_RFAEM_Field is STM32F40x.Bit; - subtype MMCRIMR_RGUFM_Field is STM32F40x.Bit; + subtype MACFCR_FCB_Field is STM32F40x.Bit; + subtype MACFCR_TFCE_Field is STM32F40x.Bit; + subtype MACFCR_RFCE_Field is STM32F40x.Bit; + subtype MACFCR_UPFD_Field is STM32F40x.Bit; + subtype MACFCR_PLT_Field is STM32F40x.UInt2; + subtype MACFCR_ZQPD_Field is STM32F40x.Bit; + subtype MACFCR_PT_Field is STM32F40x.UInt16; - -- Ethernet MMC receive interrupt mask register - type MMCRIMR_Register is record - -- unspecified - Reserved_0_4 : STM32F40x.UInt5 := 16#0#; + -- Ethernet MAC flow control register + type MACFCR_Register is record -- no description available - RFCEM : MMCRIMR_RFCEM_Field := 16#0#; + FCB : MACFCR_FCB_Field := 16#0#; -- no description available - RFAEM : MMCRIMR_RFAEM_Field := 16#0#; + TFCE : MACFCR_TFCE_Field := 16#0#; + -- no description available + RFCE : MACFCR_RFCE_Field := 16#0#; + -- no description available + UPFD : MACFCR_UPFD_Field := 16#0#; + -- no description available + PLT : MACFCR_PLT_Field := 16#0#; -- unspecified - Reserved_7_16 : STM32F40x.UInt10 := 16#0#; + Reserved_6_6 : STM32F40x.Bit := 16#0#; -- no description available - RGUFM : MMCRIMR_RGUFM_Field := 16#0#; + ZQPD : MACFCR_ZQPD_Field := 16#0#; -- unspecified - Reserved_18_31 : STM32F40x.UInt14 := 16#0#; + Reserved_8_15 : STM32F40x.Byte := 16#0#; + -- no description available + PT : MACFCR_PT_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MMCRIMR_Register use record - Reserved_0_4 at 0 range 0 .. 4; - RFCEM at 0 range 5 .. 5; - RFAEM at 0 range 6 .. 6; - Reserved_7_16 at 0 range 7 .. 16; - RGUFM at 0 range 17 .. 17; - Reserved_18_31 at 0 range 18 .. 31; + for MACFCR_Register use record + FCB at 0 range 0 .. 0; + TFCE at 0 range 1 .. 1; + RFCE at 0 range 2 .. 2; + UPFD at 0 range 3 .. 3; + PLT at 0 range 4 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + ZQPD at 0 range 7 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + PT at 0 range 16 .. 31; end record; - ---------------------- - -- MMCTIMR_Register -- - ---------------------- - - subtype MMCTIMR_TGFSCM_Field is STM32F40x.Bit; - subtype MMCTIMR_TGFMSCM_Field is STM32F40x.Bit; - subtype MMCTIMR_TGFM_Field is STM32F40x.Bit; + subtype MACVLANTR_VLANTI_Field is STM32F40x.UInt16; + subtype MACVLANTR_VLANTC_Field is STM32F40x.Bit; - -- Ethernet MMC transmit interrupt mask register - type MMCTIMR_Register is record - -- unspecified - Reserved_0_13 : STM32F40x.UInt14 := 16#0#; - -- no description available - TGFSCM : MMCTIMR_TGFSCM_Field := 16#0#; + -- Ethernet MAC VLAN tag register + type MACVLANTR_Register is record -- no description available - TGFMSCM : MMCTIMR_TGFMSCM_Field := 16#0#; + VLANTI : MACVLANTR_VLANTI_Field := 16#0#; -- no description available - TGFM : MMCTIMR_TGFM_Field := 16#0#; + VLANTC : MACVLANTR_VLANTC_Field := 16#0#; -- unspecified Reserved_17_31 : STM32F40x.UInt15 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MMCTIMR_Register use record - Reserved_0_13 at 0 range 0 .. 13; - TGFSCM at 0 range 14 .. 14; - TGFMSCM at 0 range 15 .. 15; - TGFM at 0 range 16 .. 16; + for MACVLANTR_Register use record + VLANTI at 0 range 0 .. 15; + VLANTC at 0 range 16 .. 16; Reserved_17_31 at 0 range 17 .. 31; end record; - ---------------------- - -- PTPTSCR_Register -- - ---------------------- - - subtype PTPTSCR_TSE_Field is STM32F40x.Bit; - subtype PTPTSCR_TSFCU_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSTI_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSTU_Field is STM32F40x.Bit; - subtype PTPTSCR_TSITE_Field is STM32F40x.Bit; - subtype PTPTSCR_TTSARU_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSARFE_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSSR_Field is STM32F40x.Bit; - subtype PTPTSCR_TSPTPPSV2E_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSPTPOEFE_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSIPV6FE_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSIPV4FE_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSEME_Field is STM32F40x.Bit; - subtype PTPTSCR_TSSMRME_Field is STM32F40x.Bit; - subtype PTPTSCR_TSCNT_Field is STM32F40x.UInt2; - subtype PTPTSCR_TSPFFMAE_Field is STM32F40x.Bit; + subtype MACPMTCSR_PD_Field is STM32F40x.Bit; + subtype MACPMTCSR_MPE_Field is STM32F40x.Bit; + subtype MACPMTCSR_WFE_Field is STM32F40x.Bit; + subtype MACPMTCSR_MPR_Field is STM32F40x.Bit; + subtype MACPMTCSR_WFR_Field is STM32F40x.Bit; + subtype MACPMTCSR_GU_Field is STM32F40x.Bit; + subtype MACPMTCSR_WFFRPR_Field is STM32F40x.Bit; - -- Ethernet PTP time stamp control register - type PTPTSCR_Register is record - -- no description available - TSE : PTPTSCR_TSE_Field := 16#0#; - -- no description available - TSFCU : PTPTSCR_TSFCU_Field := 16#0#; - -- no description available - TSSTI : PTPTSCR_TSSTI_Field := 16#0#; + -- Ethernet MAC PMT control and status register + type MACPMTCSR_Register is record -- no description available - TSSTU : PTPTSCR_TSSTU_Field := 16#0#; + PD : MACPMTCSR_PD_Field := 16#0#; -- no description available - TSITE : PTPTSCR_TSITE_Field := 16#0#; + MPE : MACPMTCSR_MPE_Field := 16#0#; -- no description available - TTSARU : PTPTSCR_TTSARU_Field := 16#0#; + WFE : MACPMTCSR_WFE_Field := 16#0#; -- unspecified - Reserved_6_7 : STM32F40x.UInt2 := 16#0#; - -- no description available - TSSARFE : PTPTSCR_TSSARFE_Field := 16#0#; - -- no description available - TSSSR : PTPTSCR_TSSSR_Field := 16#0#; - -- no description available - TSPTPPSV2E : PTPTSCR_TSPTPPSV2E_Field := 16#0#; - -- no description available - TSSPTPOEFE : PTPTSCR_TSSPTPOEFE_Field := 16#0#; - -- no description available - TSSIPV6FE : PTPTSCR_TSSIPV6FE_Field := 16#0#; - -- no description available - TSSIPV4FE : PTPTSCR_TSSIPV4FE_Field := 16#1#; - -- no description available - TSSEME : PTPTSCR_TSSEME_Field := 16#0#; + Reserved_3_4 : STM32F40x.UInt2 := 16#0#; -- no description available - TSSMRME : PTPTSCR_TSSMRME_Field := 16#0#; + MPR : MACPMTCSR_MPR_Field := 16#0#; -- no description available - TSCNT : PTPTSCR_TSCNT_Field := 16#0#; + WFR : MACPMTCSR_WFR_Field := 16#0#; + -- unspecified + Reserved_7_8 : STM32F40x.UInt2 := 16#0#; -- no description available - TSPFFMAE : PTPTSCR_TSPFFMAE_Field := 16#0#; + GU : MACPMTCSR_GU_Field := 16#0#; -- unspecified - Reserved_19_31 : STM32F40x.UInt13 := 16#0#; + Reserved_10_30 : STM32F40x.UInt21 := 16#0#; + -- no description available + WFFRPR : MACPMTCSR_WFFRPR_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTPTSCR_Register use record - TSE at 0 range 0 .. 0; - TSFCU at 0 range 1 .. 1; - TSSTI at 0 range 2 .. 2; - TSSTU at 0 range 3 .. 3; - TSITE at 0 range 4 .. 4; - TTSARU at 0 range 5 .. 5; - Reserved_6_7 at 0 range 6 .. 7; - TSSARFE at 0 range 8 .. 8; - TSSSR at 0 range 9 .. 9; - TSPTPPSV2E at 0 range 10 .. 10; - TSSPTPOEFE at 0 range 11 .. 11; - TSSIPV6FE at 0 range 12 .. 12; - TSSIPV4FE at 0 range 13 .. 13; - TSSEME at 0 range 14 .. 14; - TSSMRME at 0 range 15 .. 15; - TSCNT at 0 range 16 .. 17; - TSPFFMAE at 0 range 18 .. 18; - Reserved_19_31 at 0 range 19 .. 31; + for MACPMTCSR_Register use record + PD at 0 range 0 .. 0; + MPE at 0 range 1 .. 1; + WFE at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + MPR at 0 range 5 .. 5; + WFR at 0 range 6 .. 6; + Reserved_7_8 at 0 range 7 .. 8; + GU at 0 range 9 .. 9; + Reserved_10_30 at 0 range 10 .. 30; + WFFRPR at 0 range 31 .. 31; end record; - ---------------------- - -- PTPSSIR_Register -- - ---------------------- - - subtype PTPSSIR_STSSI_Field is STM32F40x.Byte; + subtype MACDBGR_CR_Field is STM32F40x.Bit; + subtype MACDBGR_CSR_Field is STM32F40x.Bit; + subtype MACDBGR_ROR_Field is STM32F40x.Bit; + subtype MACDBGR_MCF_Field is STM32F40x.Bit; + subtype MACDBGR_MCP_Field is STM32F40x.Bit; + subtype MACDBGR_MCFHP_Field is STM32F40x.Bit; - -- Ethernet PTP subsecond increment register - type PTPSSIR_Register is record - -- no description available - STSSI : PTPSSIR_STSSI_Field := 16#0#; + -- Ethernet MAC debug register + type MACDBGR_Register is record + -- Read-only. CR + CR : MACDBGR_CR_Field; + -- Read-only. CSR + CSR : MACDBGR_CSR_Field; + -- Read-only. ROR + ROR : MACDBGR_ROR_Field; + -- Read-only. MCF + MCF : MACDBGR_MCF_Field; + -- Read-only. MCP + MCP : MACDBGR_MCP_Field; + -- Read-only. MCFHP + MCFHP : MACDBGR_MCFHP_Field; -- unspecified - Reserved_8_31 : STM32F40x.UInt24 := 16#0#; + Reserved_6_31 : STM32F40x.UInt26; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTPSSIR_Register use record - STSSI at 0 range 0 .. 7; - Reserved_8_31 at 0 range 8 .. 31; + for MACDBGR_Register use record + CR at 0 range 0 .. 0; + CSR at 0 range 1 .. 1; + ROR at 0 range 2 .. 2; + MCF at 0 range 3 .. 3; + MCP at 0 range 4 .. 4; + MCFHP at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; end record; - ---------------------- - -- PTPTSLR_Register -- - ---------------------- - - subtype PTPTSLR_STSS_Field is STM32F40x.UInt31; - subtype PTPTSLR_STPNS_Field is STM32F40x.Bit; + subtype MACSR_PMTS_Field is STM32F40x.Bit; + subtype MACSR_MMCS_Field is STM32F40x.Bit; + subtype MACSR_MMCRS_Field is STM32F40x.Bit; + subtype MACSR_MMCTS_Field is STM32F40x.Bit; + subtype MACSR_TSTS_Field is STM32F40x.Bit; - -- Ethernet PTP time stamp low register - type PTPTSLR_Register is record + -- Ethernet MAC interrupt status register + type MACSR_Register is record + -- unspecified + Reserved_0_2 : STM32F40x.UInt3 := 16#0#; + -- Read-only. no description available + PMTS : MACSR_PMTS_Field := 16#0#; -- Read-only. no description available - STSS : PTPTSLR_STSS_Field := 16#0#; + MMCS : MACSR_MMCS_Field := 16#0#; + -- Read-only. no description available + MMCRS : MACSR_MMCRS_Field := 16#0#; -- Read-only. no description available - STPNS : PTPTSLR_STPNS_Field := 16#0#; + MMCTS : MACSR_MMCTS_Field := 16#0#; + -- unspecified + Reserved_7_8 : STM32F40x.UInt2 := 16#0#; + -- no description available + TSTS : MACSR_TSTS_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTPTSLR_Register use record - STSS at 0 range 0 .. 30; - STPNS at 0 range 31 .. 31; + for MACSR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + PMTS at 0 range 3 .. 3; + MMCS at 0 range 4 .. 4; + MMCRS at 0 range 5 .. 5; + MMCTS at 0 range 6 .. 6; + Reserved_7_8 at 0 range 7 .. 8; + TSTS at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; end record; - ----------------------- - -- PTPTSLUR_Register -- - ----------------------- - - subtype PTPTSLUR_TSUSS_Field is STM32F40x.UInt31; - subtype PTPTSLUR_TSUPNS_Field is STM32F40x.Bit; + subtype MACIMR_PMTIM_Field is STM32F40x.Bit; + subtype MACIMR_TSTIM_Field is STM32F40x.Bit; - -- Ethernet PTP time stamp low update register - type PTPTSLUR_Register is record + -- Ethernet MAC interrupt mask register + type MACIMR_Register is record + -- unspecified + Reserved_0_2 : STM32F40x.UInt3 := 16#0#; -- no description available - TSUSS : PTPTSLUR_TSUSS_Field := 16#0#; + PMTIM : MACIMR_PMTIM_Field := 16#0#; + -- unspecified + Reserved_4_8 : STM32F40x.UInt5 := 16#0#; -- no description available - TSUPNS : PTPTSLUR_TSUPNS_Field := 16#0#; + TSTIM : MACIMR_TSTIM_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTPTSLUR_Register use record - TSUSS at 0 range 0 .. 30; - TSUPNS at 0 range 31 .. 31; + for MACIMR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + PMTIM at 0 range 3 .. 3; + Reserved_4_8 at 0 range 4 .. 8; + TSTIM at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; end record; - ---------------------- - -- PTPTSSR_Register -- - ---------------------- - - subtype PTPTSSR_TSSO_Field is STM32F40x.Bit; - subtype PTPTSSR_TSTTR_Field is STM32F40x.Bit; + subtype MACA0HR_MACA0H_Field is STM32F40x.UInt16; + subtype MACA0HR_MO_Field is STM32F40x.Bit; - -- Ethernet PTP time stamp status register - type PTPTSSR_Register is record - -- Read-only. no description available - TSSO : PTPTSSR_TSSO_Field := 16#0#; - -- Read-only. no description available - TSTTR : PTPTSSR_TSTTR_Field := 16#0#; + -- Ethernet MAC address 0 high register + type MACA0HR_Register is record + -- MAC address0 high + MACA0H : MACA0HR_MACA0H_Field := 16#FFFF#; -- unspecified - Reserved_2_31 : STM32F40x.UInt30; + Reserved_16_30 : STM32F40x.UInt15 := 16#10#; + -- Read-only. Always 1 + MO : MACA0HR_MO_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTPTSSR_Register use record - TSSO at 0 range 0 .. 0; - TSTTR at 0 range 1 .. 1; - Reserved_2_31 at 0 range 2 .. 31; + for MACA0HR_Register use record + MACA0H at 0 range 0 .. 15; + Reserved_16_30 at 0 range 16 .. 30; + MO at 0 range 31 .. 31; end record; - ----------------------- - -- PTPPPSCR_Register -- - ----------------------- - - subtype PTPPPSCR_TSSO_Field is STM32F40x.Bit; - subtype PTPPPSCR_TSTTR_Field is STM32F40x.Bit; + subtype MACA1HR_MACA1H_Field is STM32F40x.UInt16; + subtype MACA1HR_MBC_Field is STM32F40x.UInt6; + subtype MACA1HR_SA_Field is STM32F40x.Bit; + subtype MACA1HR_AE_Field is STM32F40x.Bit; - -- Ethernet PTP PPS control register - type PTPPPSCR_Register is record - -- Read-only. TSSO - TSSO : PTPPPSCR_TSSO_Field := 16#0#; - -- Read-only. TSTTR - TSTTR : PTPPPSCR_TSTTR_Field := 16#0#; + -- Ethernet MAC address 1 high register + type MACA1HR_Register is record + -- no description available + MACA1H : MACA1HR_MACA1H_Field := 16#FFFF#; -- unspecified - Reserved_2_31 : STM32F40x.UInt30; + Reserved_16_23 : STM32F40x.Byte := 16#0#; + -- no description available + MBC : MACA1HR_MBC_Field := 16#0#; + -- no description available + SA : MACA1HR_SA_Field := 16#0#; + -- no description available + AE : MACA1HR_AE_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for PTPPPSCR_Register use record - TSSO at 0 range 0 .. 0; - TSTTR at 0 range 1 .. 1; - Reserved_2_31 at 0 range 2 .. 31; + for MACA1HR_Register use record + MACA1H at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + MBC at 0 range 24 .. 29; + SA at 0 range 30 .. 30; + AE at 0 range 31 .. 31; end record; - --------------------- - -- DMABMR_Register -- - --------------------- - - subtype DMABMR_SR_Field is STM32F40x.Bit; - subtype DMABMR_DA_Field is STM32F40x.Bit; - subtype DMABMR_DSL_Field is STM32F40x.UInt5; - subtype DMABMR_EDFE_Field is STM32F40x.Bit; - subtype DMABMR_PBL_Field is STM32F40x.UInt6; - subtype DMABMR_RTPR_Field is STM32F40x.UInt2; - subtype DMABMR_FB_Field is STM32F40x.Bit; - subtype DMABMR_RDP_Field is STM32F40x.UInt6; - subtype DMABMR_USP_Field is STM32F40x.Bit; - subtype DMABMR_FPM_Field is STM32F40x.Bit; - subtype DMABMR_AAB_Field is STM32F40x.Bit; - subtype DMABMR_MB_Field is STM32F40x.Bit; + subtype MACA2HR_MAC2AH_Field is STM32F40x.UInt16; + subtype MACA2HR_MBC_Field is STM32F40x.UInt6; + subtype MACA2HR_SA_Field is STM32F40x.Bit; + subtype MACA2HR_AE_Field is STM32F40x.Bit; - -- Ethernet DMA bus mode register - type DMABMR_Register is record - -- no description available - SR : DMABMR_SR_Field := 16#1#; - -- no description available - DA : DMABMR_DA_Field := 16#0#; - -- no description available - DSL : DMABMR_DSL_Field := 16#0#; - -- no description available - EDFE : DMABMR_EDFE_Field := 16#0#; - -- no description available - PBL : DMABMR_PBL_Field := 16#21#; - -- no description available - RTPR : DMABMR_RTPR_Field := 16#0#; - -- no description available - FB : DMABMR_FB_Field := 16#0#; + -- Ethernet MAC address 2 high register + type MACA2HR_Register is record -- no description available - RDP : DMABMR_RDP_Field := 16#0#; + MAC2AH : MACA2HR_MAC2AH_Field := 16#FFFF#; + -- unspecified + Reserved_16_23 : STM32F40x.Byte := 16#0#; -- no description available - USP : DMABMR_USP_Field := 16#0#; + MBC : MACA2HR_MBC_Field := 16#0#; -- no description available - FPM : DMABMR_FPM_Field := 16#0#; + SA : MACA2HR_SA_Field := 16#0#; -- no description available - AAB : DMABMR_AAB_Field := 16#0#; + AE : MACA2HR_AE_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACA2HR_Register use record + MAC2AH at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + MBC at 0 range 24 .. 29; + SA at 0 range 30 .. 30; + AE at 0 range 31 .. 31; + end record; + + subtype MACA2LR_MACA2L_Field is STM32F40x.UInt31; + + -- Ethernet MAC address 2 low register + type MACA2LR_Register is record -- no description available - MB : DMABMR_MB_Field := 16#0#; + MACA2L : MACA2LR_MACA2L_Field := 16#7FFFFFFF#; -- unspecified - Reserved_27_31 : STM32F40x.UInt5 := 16#0#; + Reserved_31_31 : STM32F40x.Bit := 16#1#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMABMR_Register use record - SR at 0 range 0 .. 0; - DA at 0 range 1 .. 1; - DSL at 0 range 2 .. 6; - EDFE at 0 range 7 .. 7; - PBL at 0 range 8 .. 13; - RTPR at 0 range 14 .. 15; - FB at 0 range 16 .. 16; - RDP at 0 range 17 .. 22; - USP at 0 range 23 .. 23; - FPM at 0 range 24 .. 24; - AAB at 0 range 25 .. 25; - MB at 0 range 26 .. 26; - Reserved_27_31 at 0 range 27 .. 31; + for MACA2LR_Register use record + MACA2L at 0 range 0 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - -------------------- - -- DMASR_Register -- - -------------------- - - subtype DMASR_TS_Field is STM32F40x.Bit; - subtype DMASR_TPSS_Field is STM32F40x.Bit; - subtype DMASR_TBUS_Field is STM32F40x.Bit; - subtype DMASR_TJTS_Field is STM32F40x.Bit; - subtype DMASR_ROS_Field is STM32F40x.Bit; - subtype DMASR_TUS_Field is STM32F40x.Bit; - subtype DMASR_RS_Field is STM32F40x.Bit; - subtype DMASR_RBUS_Field is STM32F40x.Bit; - subtype DMASR_RPSS_Field is STM32F40x.Bit; - subtype DMASR_PWTS_Field is STM32F40x.Bit; - subtype DMASR_ETS_Field is STM32F40x.Bit; - subtype DMASR_FBES_Field is STM32F40x.Bit; - subtype DMASR_ERS_Field is STM32F40x.Bit; - subtype DMASR_AIS_Field is STM32F40x.Bit; - subtype DMASR_NIS_Field is STM32F40x.Bit; - subtype DMASR_RPS_Field is STM32F40x.UInt3; - subtype DMASR_TPS_Field is STM32F40x.UInt3; - subtype DMASR_EBS_Field is STM32F40x.UInt3; - subtype DMASR_MMCS_Field is STM32F40x.Bit; - subtype DMASR_PMTS_Field is STM32F40x.Bit; - subtype DMASR_TSTS_Field is STM32F40x.Bit; + subtype MACA3HR_MACA3H_Field is STM32F40x.UInt16; + subtype MACA3HR_MBC_Field is STM32F40x.UInt6; + subtype MACA3HR_SA_Field is STM32F40x.Bit; + subtype MACA3HR_AE_Field is STM32F40x.Bit; - -- Ethernet DMA status register - type DMASR_Register is record - -- no description available - TS : DMASR_TS_Field := 16#0#; + -- Ethernet MAC address 3 high register + type MACA3HR_Register is record -- no description available - TPSS : DMASR_TPSS_Field := 16#0#; + MACA3H : MACA3HR_MACA3H_Field := 16#FFFF#; + -- unspecified + Reserved_16_23 : STM32F40x.Byte := 16#0#; -- no description available - TBUS : DMASR_TBUS_Field := 16#0#; + MBC : MACA3HR_MBC_Field := 16#0#; -- no description available - TJTS : DMASR_TJTS_Field := 16#0#; + SA : MACA3HR_SA_Field := 16#0#; -- no description available - ROS : DMASR_ROS_Field := 16#0#; + AE : MACA3HR_AE_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACA3HR_Register use record + MACA3H at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + MBC at 0 range 24 .. 29; + SA at 0 range 30 .. 30; + AE at 0 range 31 .. 31; + end record; + + subtype MMCCR_CR_Field is STM32F40x.Bit; + subtype MMCCR_CSR_Field is STM32F40x.Bit; + subtype MMCCR_ROR_Field is STM32F40x.Bit; + subtype MMCCR_MCF_Field is STM32F40x.Bit; + subtype MMCCR_MCP_Field is STM32F40x.Bit; + subtype MMCCR_MCFHP_Field is STM32F40x.Bit; + + -- Ethernet MMC control register + type MMCCR_Register is record -- no description available - TUS : DMASR_TUS_Field := 16#0#; + CR : MMCCR_CR_Field := 16#0#; -- no description available - RS : DMASR_RS_Field := 16#0#; + CSR : MMCCR_CSR_Field := 16#0#; -- no description available - RBUS : DMASR_RBUS_Field := 16#0#; + ROR : MMCCR_ROR_Field := 16#0#; -- no description available - RPSS : DMASR_RPSS_Field := 16#0#; + MCF : MMCCR_MCF_Field := 16#0#; -- no description available - PWTS : DMASR_PWTS_Field := 16#0#; + MCP : MMCCR_MCP_Field := 16#0#; -- no description available - ETS : DMASR_ETS_Field := 16#0#; + MCFHP : MMCCR_MCFHP_Field := 16#0#; -- unspecified - Reserved_11_12 : STM32F40x.UInt2 := 16#0#; - -- no description available - FBES : DMASR_FBES_Field := 16#0#; + Reserved_6_31 : STM32F40x.UInt26 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MMCCR_Register use record + CR at 0 range 0 .. 0; + CSR at 0 range 1 .. 1; + ROR at 0 range 2 .. 2; + MCF at 0 range 3 .. 3; + MCP at 0 range 4 .. 4; + MCFHP at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype MMCRIR_RFCES_Field is STM32F40x.Bit; + subtype MMCRIR_RFAES_Field is STM32F40x.Bit; + subtype MMCRIR_RGUFS_Field is STM32F40x.Bit; + + -- Ethernet MMC receive interrupt register + type MMCRIR_Register is record + -- unspecified + Reserved_0_4 : STM32F40x.UInt5 := 16#0#; -- no description available - ERS : DMASR_ERS_Field := 16#0#; + RFCES : MMCRIR_RFCES_Field := 16#0#; -- no description available - AIS : DMASR_AIS_Field := 16#0#; + RFAES : MMCRIR_RFAES_Field := 16#0#; + -- unspecified + Reserved_7_16 : STM32F40x.UInt10 := 16#0#; -- no description available - NIS : DMASR_NIS_Field := 16#0#; - -- Read-only. no description available - RPS : DMASR_RPS_Field := 16#0#; - -- Read-only. no description available - TPS : DMASR_TPS_Field := 16#0#; - -- Read-only. no description available - EBS : DMASR_EBS_Field := 16#0#; + RGUFS : MMCRIR_RGUFS_Field := 16#0#; -- unspecified - Reserved_26_26 : STM32F40x.Bit := 16#0#; + Reserved_18_31 : STM32F40x.UInt14 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MMCRIR_Register use record + Reserved_0_4 at 0 range 0 .. 4; + RFCES at 0 range 5 .. 5; + RFAES at 0 range 6 .. 6; + Reserved_7_16 at 0 range 7 .. 16; + RGUFS at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype MMCTIR_TGFSCS_Field is STM32F40x.Bit; + subtype MMCTIR_TGFMSCS_Field is STM32F40x.Bit; + subtype MMCTIR_TGFS_Field is STM32F40x.Bit; + + -- Ethernet MMC transmit interrupt register + type MMCTIR_Register is record + -- unspecified + Reserved_0_13 : STM32F40x.UInt14; -- Read-only. no description available - MMCS : DMASR_MMCS_Field := 16#0#; + TGFSCS : MMCTIR_TGFSCS_Field; -- Read-only. no description available - PMTS : DMASR_PMTS_Field := 16#0#; + TGFMSCS : MMCTIR_TGFMSCS_Field; + -- unspecified + Reserved_16_20 : STM32F40x.UInt5; -- Read-only. no description available - TSTS : DMASR_TSTS_Field := 16#0#; + TGFS : MMCTIR_TGFS_Field; -- unspecified - Reserved_30_31 : STM32F40x.UInt2 := 16#0#; + Reserved_22_31 : STM32F40x.UInt10; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMASR_Register use record - TS at 0 range 0 .. 0; - TPSS at 0 range 1 .. 1; - TBUS at 0 range 2 .. 2; - TJTS at 0 range 3 .. 3; - ROS at 0 range 4 .. 4; - TUS at 0 range 5 .. 5; - RS at 0 range 6 .. 6; - RBUS at 0 range 7 .. 7; - RPSS at 0 range 8 .. 8; - PWTS at 0 range 9 .. 9; - ETS at 0 range 10 .. 10; - Reserved_11_12 at 0 range 11 .. 12; - FBES at 0 range 13 .. 13; - ERS at 0 range 14 .. 14; - AIS at 0 range 15 .. 15; - NIS at 0 range 16 .. 16; - RPS at 0 range 17 .. 19; - TPS at 0 range 20 .. 22; - EBS at 0 range 23 .. 25; - Reserved_26_26 at 0 range 26 .. 26; - MMCS at 0 range 27 .. 27; - PMTS at 0 range 28 .. 28; - TSTS at 0 range 29 .. 29; - Reserved_30_31 at 0 range 30 .. 31; + for MMCTIR_Register use record + Reserved_0_13 at 0 range 0 .. 13; + TGFSCS at 0 range 14 .. 14; + TGFMSCS at 0 range 15 .. 15; + Reserved_16_20 at 0 range 16 .. 20; + TGFS at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; end record; - --------------------- - -- DMAOMR_Register -- - --------------------- - - subtype DMAOMR_SR_Field is STM32F40x.Bit; - subtype DMAOMR_OSF_Field is STM32F40x.Bit; - subtype DMAOMR_RTC_Field is STM32F40x.UInt2; - subtype DMAOMR_FUGF_Field is STM32F40x.Bit; - subtype DMAOMR_FEF_Field is STM32F40x.Bit; - subtype DMAOMR_ST_Field is STM32F40x.Bit; - subtype DMAOMR_TTC_Field is STM32F40x.UInt3; - subtype DMAOMR_FTF_Field is STM32F40x.Bit; - subtype DMAOMR_TSF_Field is STM32F40x.Bit; - subtype DMAOMR_DFRF_Field is STM32F40x.Bit; - subtype DMAOMR_RSF_Field is STM32F40x.Bit; - subtype DMAOMR_DTCEFD_Field is STM32F40x.Bit; + subtype MMCRIMR_RFCEM_Field is STM32F40x.Bit; + subtype MMCRIMR_RFAEM_Field is STM32F40x.Bit; + subtype MMCRIMR_RGUFM_Field is STM32F40x.Bit; - -- Ethernet DMA operation mode register - type DMAOMR_Register is record - -- unspecified - Reserved_0_0 : STM32F40x.Bit := 16#0#; - -- SR - SR : DMAOMR_SR_Field := 16#0#; - -- OSF - OSF : DMAOMR_OSF_Field := 16#0#; - -- RTC - RTC : DMAOMR_RTC_Field := 16#0#; + -- Ethernet MMC receive interrupt mask register + type MMCRIMR_Register is record -- unspecified - Reserved_5_5 : STM32F40x.Bit := 16#0#; - -- FUGF - FUGF : DMAOMR_FUGF_Field := 16#0#; - -- FEF - FEF : DMAOMR_FEF_Field := 16#0#; + Reserved_0_4 : STM32F40x.UInt5 := 16#0#; + -- no description available + RFCEM : MMCRIMR_RFCEM_Field := 16#0#; + -- no description available + RFAEM : MMCRIMR_RFAEM_Field := 16#0#; -- unspecified - Reserved_8_12 : STM32F40x.UInt5 := 16#0#; - -- ST - ST : DMAOMR_ST_Field := 16#0#; - -- TTC - TTC : DMAOMR_TTC_Field := 16#0#; + Reserved_7_16 : STM32F40x.UInt10 := 16#0#; + -- no description available + RGUFM : MMCRIMR_RGUFM_Field := 16#0#; -- unspecified - Reserved_17_19 : STM32F40x.UInt3 := 16#0#; - -- FTF - FTF : DMAOMR_FTF_Field := 16#0#; - -- TSF - TSF : DMAOMR_TSF_Field := 16#0#; + Reserved_18_31 : STM32F40x.UInt14 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MMCRIMR_Register use record + Reserved_0_4 at 0 range 0 .. 4; + RFCEM at 0 range 5 .. 5; + RFAEM at 0 range 6 .. 6; + Reserved_7_16 at 0 range 7 .. 16; + RGUFM at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype MMCTIMR_TGFSCM_Field is STM32F40x.Bit; + subtype MMCTIMR_TGFMSCM_Field is STM32F40x.Bit; + subtype MMCTIMR_TGFM_Field is STM32F40x.Bit; + + -- Ethernet MMC transmit interrupt mask register + type MMCTIMR_Register is record -- unspecified - Reserved_22_23 : STM32F40x.UInt2 := 16#0#; - -- DFRF - DFRF : DMAOMR_DFRF_Field := 16#0#; - -- RSF - RSF : DMAOMR_RSF_Field := 16#0#; - -- DTCEFD - DTCEFD : DMAOMR_DTCEFD_Field := 16#0#; + Reserved_0_13 : STM32F40x.UInt14 := 16#0#; + -- no description available + TGFSCM : MMCTIMR_TGFSCM_Field := 16#0#; + -- no description available + TGFMSCM : MMCTIMR_TGFMSCM_Field := 16#0#; + -- no description available + TGFM : MMCTIMR_TGFM_Field := 16#0#; -- unspecified - Reserved_27_31 : STM32F40x.UInt5 := 16#0#; + Reserved_17_31 : STM32F40x.UInt15 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMAOMR_Register use record - Reserved_0_0 at 0 range 0 .. 0; - SR at 0 range 1 .. 1; - OSF at 0 range 2 .. 2; - RTC at 0 range 3 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - FUGF at 0 range 6 .. 6; - FEF at 0 range 7 .. 7; - Reserved_8_12 at 0 range 8 .. 12; - ST at 0 range 13 .. 13; - TTC at 0 range 14 .. 16; - Reserved_17_19 at 0 range 17 .. 19; - FTF at 0 range 20 .. 20; - TSF at 0 range 21 .. 21; - Reserved_22_23 at 0 range 22 .. 23; - DFRF at 0 range 24 .. 24; - RSF at 0 range 25 .. 25; - DTCEFD at 0 range 26 .. 26; - Reserved_27_31 at 0 range 27 .. 31; + for MMCTIMR_Register use record + Reserved_0_13 at 0 range 0 .. 13; + TGFSCM at 0 range 14 .. 14; + TGFMSCM at 0 range 15 .. 15; + TGFM at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; end record; - --------------------- - -- DMAIER_Register -- - --------------------- - - subtype DMAIER_TIE_Field is STM32F40x.Bit; - subtype DMAIER_TPSIE_Field is STM32F40x.Bit; - subtype DMAIER_TBUIE_Field is STM32F40x.Bit; - subtype DMAIER_TJTIE_Field is STM32F40x.Bit; - subtype DMAIER_ROIE_Field is STM32F40x.Bit; - subtype DMAIER_TUIE_Field is STM32F40x.Bit; - subtype DMAIER_RIE_Field is STM32F40x.Bit; - subtype DMAIER_RBUIE_Field is STM32F40x.Bit; - subtype DMAIER_RPSIE_Field is STM32F40x.Bit; - subtype DMAIER_RWTIE_Field is STM32F40x.Bit; - subtype DMAIER_ETIE_Field is STM32F40x.Bit; - subtype DMAIER_FBEIE_Field is STM32F40x.Bit; - subtype DMAIER_ERIE_Field is STM32F40x.Bit; - subtype DMAIER_AISE_Field is STM32F40x.Bit; - subtype DMAIER_NISE_Field is STM32F40x.Bit; + subtype PTPTSCR_TSE_Field is STM32F40x.Bit; + subtype PTPTSCR_TSFCU_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSTI_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSTU_Field is STM32F40x.Bit; + subtype PTPTSCR_TSITE_Field is STM32F40x.Bit; + subtype PTPTSCR_TTSARU_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSARFE_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSSR_Field is STM32F40x.Bit; + subtype PTPTSCR_TSPTPPSV2E_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSPTPOEFE_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSIPV6FE_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSIPV4FE_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSEME_Field is STM32F40x.Bit; + subtype PTPTSCR_TSSMRME_Field is STM32F40x.Bit; + subtype PTPTSCR_TSCNT_Field is STM32F40x.UInt2; + subtype PTPTSCR_TSPFFMAE_Field is STM32F40x.Bit; - -- Ethernet DMA interrupt enable register - type DMAIER_Register is record + -- Ethernet PTP time stamp control register + type PTPTSCR_Register is record -- no description available - TIE : DMAIER_TIE_Field := 16#0#; + TSE : PTPTSCR_TSE_Field := 16#0#; -- no description available - TPSIE : DMAIER_TPSIE_Field := 16#0#; + TSFCU : PTPTSCR_TSFCU_Field := 16#0#; -- no description available - TBUIE : DMAIER_TBUIE_Field := 16#0#; + TSSTI : PTPTSCR_TSSTI_Field := 16#0#; -- no description available - TJTIE : DMAIER_TJTIE_Field := 16#0#; + TSSTU : PTPTSCR_TSSTU_Field := 16#0#; -- no description available - ROIE : DMAIER_ROIE_Field := 16#0#; + TSITE : PTPTSCR_TSITE_Field := 16#0#; -- no description available - TUIE : DMAIER_TUIE_Field := 16#0#; + TTSARU : PTPTSCR_TTSARU_Field := 16#0#; + -- unspecified + Reserved_6_7 : STM32F40x.UInt2 := 16#0#; -- no description available - RIE : DMAIER_RIE_Field := 16#0#; + TSSARFE : PTPTSCR_TSSARFE_Field := 16#0#; -- no description available - RBUIE : DMAIER_RBUIE_Field := 16#0#; + TSSSR : PTPTSCR_TSSSR_Field := 16#0#; -- no description available - RPSIE : DMAIER_RPSIE_Field := 16#0#; + TSPTPPSV2E : PTPTSCR_TSPTPPSV2E_Field := 16#0#; -- no description available - RWTIE : DMAIER_RWTIE_Field := 16#0#; + TSSPTPOEFE : PTPTSCR_TSSPTPOEFE_Field := 16#0#; -- no description available - ETIE : DMAIER_ETIE_Field := 16#0#; - -- unspecified - Reserved_11_12 : STM32F40x.UInt2 := 16#0#; + TSSIPV6FE : PTPTSCR_TSSIPV6FE_Field := 16#0#; -- no description available - FBEIE : DMAIER_FBEIE_Field := 16#0#; + TSSIPV4FE : PTPTSCR_TSSIPV4FE_Field := 16#1#; -- no description available - ERIE : DMAIER_ERIE_Field := 16#0#; + TSSEME : PTPTSCR_TSSEME_Field := 16#0#; -- no description available - AISE : DMAIER_AISE_Field := 16#0#; + TSSMRME : PTPTSCR_TSSMRME_Field := 16#0#; -- no description available - NISE : DMAIER_NISE_Field := 16#0#; + TSCNT : PTPTSCR_TSCNT_Field := 16#0#; + -- no description available + TSPFFMAE : PTPTSCR_TSPFFMAE_Field := 16#0#; -- unspecified - Reserved_17_31 : STM32F40x.UInt15 := 16#0#; + Reserved_19_31 : STM32F40x.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMAIER_Register use record - TIE at 0 range 0 .. 0; - TPSIE at 0 range 1 .. 1; - TBUIE at 0 range 2 .. 2; - TJTIE at 0 range 3 .. 3; - ROIE at 0 range 4 .. 4; - TUIE at 0 range 5 .. 5; - RIE at 0 range 6 .. 6; - RBUIE at 0 range 7 .. 7; - RPSIE at 0 range 8 .. 8; - RWTIE at 0 range 9 .. 9; - ETIE at 0 range 10 .. 10; - Reserved_11_12 at 0 range 11 .. 12; - FBEIE at 0 range 13 .. 13; - ERIE at 0 range 14 .. 14; - AISE at 0 range 15 .. 15; - NISE at 0 range 16 .. 16; - Reserved_17_31 at 0 range 17 .. 31; + for PTPTSCR_Register use record + TSE at 0 range 0 .. 0; + TSFCU at 0 range 1 .. 1; + TSSTI at 0 range 2 .. 2; + TSSTU at 0 range 3 .. 3; + TSITE at 0 range 4 .. 4; + TTSARU at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + TSSARFE at 0 range 8 .. 8; + TSSSR at 0 range 9 .. 9; + TSPTPPSV2E at 0 range 10 .. 10; + TSSPTPOEFE at 0 range 11 .. 11; + TSSIPV6FE at 0 range 12 .. 12; + TSSIPV4FE at 0 range 13 .. 13; + TSSEME at 0 range 14 .. 14; + TSSMRME at 0 range 15 .. 15; + TSCNT at 0 range 16 .. 17; + TSPFFMAE at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------------ - -- DMAMFBOCR_Register -- - ------------------------ - - subtype DMAMFBOCR_MFC_Field is STM32F40x.Short; - subtype DMAMFBOCR_OMFC_Field is STM32F40x.Bit; - subtype DMAMFBOCR_MFA_Field is STM32F40x.UInt11; - subtype DMAMFBOCR_OFOC_Field is STM32F40x.Bit; + subtype PTPSSIR_STSSI_Field is STM32F40x.Byte; - -- Ethernet DMA missed frame and buffer overflow counter register - type DMAMFBOCR_Register is record - -- no description available - MFC : DMAMFBOCR_MFC_Field := 16#0#; + -- Ethernet PTP subsecond increment register + type PTPSSIR_Register is record -- no description available - OMFC : DMAMFBOCR_OMFC_Field := 16#0#; + STSSI : PTPSSIR_STSSI_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F40x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for PTPSSIR_Register use record + STSSI at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PTPTSLR_STSS_Field is STM32F40x.UInt31; + subtype PTPTSLR_STPNS_Field is STM32F40x.Bit; + + -- Ethernet PTP time stamp low register + type PTPTSLR_Register is record + -- Read-only. no description available + STSS : PTPTSLR_STSS_Field; + -- Read-only. no description available + STPNS : PTPTSLR_STPNS_Field; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for PTPTSLR_Register use record + STSS at 0 range 0 .. 30; + STPNS at 0 range 31 .. 31; + end record; + + subtype PTPTSLUR_TSUSS_Field is STM32F40x.UInt31; + subtype PTPTSLUR_TSUPNS_Field is STM32F40x.Bit; + + -- Ethernet PTP time stamp low update register + type PTPTSLUR_Register is record -- no description available - MFA : DMAMFBOCR_MFA_Field := 16#0#; + TSUSS : PTPTSLUR_TSUSS_Field := 16#0#; -- no description available - OFOC : DMAMFBOCR_OFOC_Field := 16#0#; - -- unspecified - Reserved_29_31 : STM32F40x.UInt3 := 16#0#; + TSUPNS : PTPTSLUR_TSUPNS_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMAMFBOCR_Register use record - MFC at 0 range 0 .. 15; - OMFC at 0 range 16 .. 16; - MFA at 0 range 17 .. 27; - OFOC at 0 range 28 .. 28; - Reserved_29_31 at 0 range 29 .. 31; + for PTPTSLUR_Register use record + TSUSS at 0 range 0 .. 30; + TSUPNS at 0 range 31 .. 31; end record; - ----------------------- - -- DMARSWTR_Register -- - ----------------------- + subtype PTPTSSR_TSSO_Field is STM32F40x.Bit; + subtype PTPTSSR_TSTTR_Field is STM32F40x.Bit; - subtype DMARSWTR_RSWTC_Field is STM32F40x.Byte; + -- Ethernet PTP time stamp status register + type PTPTSSR_Register is record + -- Read-only. no description available + TSSO : PTPTSSR_TSSO_Field; + -- Read-only. no description available + TSTTR : PTPTSSR_TSTTR_Field; + -- unspecified + Reserved_2_31 : STM32F40x.UInt30; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- Ethernet DMA receive status watchdog timer register - type DMARSWTR_Register is record - -- RSWTC - RSWTC : DMARSWTR_RSWTC_Field := 16#0#; + for PTPTSSR_Register use record + TSSO at 0 range 0 .. 0; + TSTTR at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype PTPPPSCR_TSSO_Field is STM32F40x.Bit; + subtype PTPPPSCR_TSTTR_Field is STM32F40x.Bit; + + -- Ethernet PTP PPS control register + type PTPPPSCR_Register is record + -- Read-only. TSSO + TSSO : PTPPPSCR_TSSO_Field; + -- Read-only. TSTTR + TSTTR : PTPPPSCR_TSTTR_Field; -- unspecified - Reserved_8_31 : STM32F40x.UInt24 := 16#0#; + Reserved_2_31 : STM32F40x.UInt30; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMARSWTR_Register use record - RSWTC at 0 range 0 .. 7; - Reserved_8_31 at 0 range 8 .. 31; + for PTPPPSCR_Register use record + TSSO at 0 range 0 .. 0; + TSTTR at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; end record; ----------------- -- Peripherals -- ----------------- + -- Ethernet: DMA controller operation + type Ethernet_DMA_Peripheral is record + -- Ethernet DMA bus mode register + DMABMR : aliased DMABMR_Register; + pragma Volatile_Full_Access (DMABMR); + -- Ethernet DMA transmit poll demand register + DMATPDR : aliased STM32F40x.UInt32; + -- EHERNET DMA receive poll demand register + DMARPDR : aliased STM32F40x.UInt32; + -- Ethernet DMA receive descriptor list address register + DMARDLAR : aliased STM32F40x.UInt32; + -- Ethernet DMA transmit descriptor list address register + DMATDLAR : aliased STM32F40x.UInt32; + -- Ethernet DMA status register + DMASR : aliased DMASR_Register; + pragma Volatile_Full_Access (DMASR); + -- Ethernet DMA operation mode register + DMAOMR : aliased DMAOMR_Register; + pragma Volatile_Full_Access (DMAOMR); + -- Ethernet DMA interrupt enable register + DMAIER : aliased DMAIER_Register; + pragma Volatile_Full_Access (DMAIER); + -- Ethernet DMA missed frame and buffer overflow counter register + DMAMFBOCR : aliased DMAMFBOCR_Register; + pragma Volatile_Full_Access (DMAMFBOCR); + -- Ethernet DMA receive status watchdog timer register + DMARSWTR : aliased DMARSWTR_Register; + pragma Volatile_Full_Access (DMARSWTR); + -- Ethernet DMA current host transmit descriptor register + DMACHTDR : aliased STM32F40x.UInt32; + -- Ethernet DMA current host receive descriptor register + DMACHRDR : aliased STM32F40x.UInt32; + -- Ethernet DMA current host transmit buffer address register + DMACHTBAR : aliased STM32F40x.UInt32; + -- Ethernet DMA current host receive buffer address register + DMACHRBAR : aliased STM32F40x.UInt32; + end record + with Volatile; + + for Ethernet_DMA_Peripheral use record + DMABMR at 16#0# range 0 .. 31; + DMATPDR at 16#4# range 0 .. 31; + DMARPDR at 16#8# range 0 .. 31; + DMARDLAR at 16#C# range 0 .. 31; + DMATDLAR at 16#10# range 0 .. 31; + DMASR at 16#14# range 0 .. 31; + DMAOMR at 16#18# range 0 .. 31; + DMAIER at 16#1C# range 0 .. 31; + DMAMFBOCR at 16#20# range 0 .. 31; + DMARSWTR at 16#24# range 0 .. 31; + DMACHTDR at 16#48# range 0 .. 31; + DMACHRDR at 16#4C# range 0 .. 31; + DMACHTBAR at 16#50# range 0 .. 31; + DMACHRBAR at 16#54# range 0 .. 31; + end record; + + -- Ethernet: DMA controller operation + Ethernet_DMA_Periph : aliased Ethernet_DMA_Peripheral + with Import, Address => Ethernet_DMA_Base; + -- Ethernet: media access control (MAC) type Ethernet_MAC_Peripheral is record -- Ethernet MAC configuration register - MACCR : MACCR_Register; + MACCR : aliased MACCR_Register; + pragma Volatile_Full_Access (MACCR); -- Ethernet MAC frame filter register - MACFFR : MACFFR_Register; + MACFFR : aliased MACFFR_Register; + pragma Volatile_Full_Access (MACFFR); -- Ethernet MAC hash table high register - MACHTHR : STM32F40x.Word; + MACHTHR : aliased STM32F40x.UInt32; -- Ethernet MAC hash table low register - MACHTLR : STM32F40x.Word; + MACHTLR : aliased STM32F40x.UInt32; -- Ethernet MAC MII address register - MACMIIAR : MACMIIAR_Register; + MACMIIAR : aliased MACMIIAR_Register; + pragma Volatile_Full_Access (MACMIIAR); -- Ethernet MAC MII data register - MACMIIDR : MACMIIDR_Register; + MACMIIDR : aliased MACMIIDR_Register; + pragma Volatile_Full_Access (MACMIIDR); -- Ethernet MAC flow control register - MACFCR : MACFCR_Register; + MACFCR : aliased MACFCR_Register; + pragma Volatile_Full_Access (MACFCR); -- Ethernet MAC VLAN tag register - MACVLANTR : MACVLANTR_Register; + MACVLANTR : aliased MACVLANTR_Register; + pragma Volatile_Full_Access (MACVLANTR); -- Ethernet MAC PMT control and status register - MACPMTCSR : MACPMTCSR_Register; + MACPMTCSR : aliased MACPMTCSR_Register; + pragma Volatile_Full_Access (MACPMTCSR); -- Ethernet MAC debug register - MACDBGR : MACDBGR_Register; + MACDBGR : aliased MACDBGR_Register; + pragma Volatile_Full_Access (MACDBGR); -- Ethernet MAC interrupt status register - MACSR : MACSR_Register; + MACSR : aliased MACSR_Register; + pragma Volatile_Full_Access (MACSR); -- Ethernet MAC interrupt mask register - MACIMR : MACIMR_Register; + MACIMR : aliased MACIMR_Register; + pragma Volatile_Full_Access (MACIMR); -- Ethernet MAC address 0 high register - MACA0HR : MACA0HR_Register; + MACA0HR : aliased MACA0HR_Register; + pragma Volatile_Full_Access (MACA0HR); -- Ethernet MAC address 0 low register - MACA0LR : STM32F40x.Word; + MACA0LR : aliased STM32F40x.UInt32; -- Ethernet MAC address 1 high register - MACA1HR : MACA1HR_Register; + MACA1HR : aliased MACA1HR_Register; + pragma Volatile_Full_Access (MACA1HR); -- Ethernet MAC address1 low register - MACA1LR : STM32F40x.Word; + MACA1LR : aliased STM32F40x.UInt32; -- Ethernet MAC address 2 high register - MACA2HR : MACA2HR_Register; + MACA2HR : aliased MACA2HR_Register; + pragma Volatile_Full_Access (MACA2HR); -- Ethernet MAC address 2 low register - MACA2LR : MACA2LR_Register; + MACA2LR : aliased MACA2LR_Register; + pragma Volatile_Full_Access (MACA2LR); -- Ethernet MAC address 3 high register - MACA3HR : MACA3HR_Register; + MACA3HR : aliased MACA3HR_Register; + pragma Volatile_Full_Access (MACA3HR); -- Ethernet MAC address 3 low register - MACA3LR : STM32F40x.Word; + MACA3LR : aliased STM32F40x.UInt32; end record with Volatile; for Ethernet_MAC_Peripheral use record - MACCR at 0 range 0 .. 31; - MACFFR at 4 range 0 .. 31; - MACHTHR at 8 range 0 .. 31; - MACHTLR at 12 range 0 .. 31; - MACMIIAR at 16 range 0 .. 31; - MACMIIDR at 20 range 0 .. 31; - MACFCR at 24 range 0 .. 31; - MACVLANTR at 28 range 0 .. 31; - MACPMTCSR at 44 range 0 .. 31; - MACDBGR at 52 range 0 .. 31; - MACSR at 56 range 0 .. 31; - MACIMR at 60 range 0 .. 31; - MACA0HR at 64 range 0 .. 31; - MACA0LR at 68 range 0 .. 31; - MACA1HR at 72 range 0 .. 31; - MACA1LR at 76 range 0 .. 31; - MACA2HR at 80 range 0 .. 31; - MACA2LR at 84 range 0 .. 31; - MACA3HR at 88 range 0 .. 31; - MACA3LR at 92 range 0 .. 31; + MACCR at 16#0# range 0 .. 31; + MACFFR at 16#4# range 0 .. 31; + MACHTHR at 16#8# range 0 .. 31; + MACHTLR at 16#C# range 0 .. 31; + MACMIIAR at 16#10# range 0 .. 31; + MACMIIDR at 16#14# range 0 .. 31; + MACFCR at 16#18# range 0 .. 31; + MACVLANTR at 16#1C# range 0 .. 31; + MACPMTCSR at 16#2C# range 0 .. 31; + MACDBGR at 16#34# range 0 .. 31; + MACSR at 16#38# range 0 .. 31; + MACIMR at 16#3C# range 0 .. 31; + MACA0HR at 16#40# range 0 .. 31; + MACA0LR at 16#44# range 0 .. 31; + MACA1HR at 16#48# range 0 .. 31; + MACA1LR at 16#4C# range 0 .. 31; + MACA2HR at 16#50# range 0 .. 31; + MACA2LR at 16#54# range 0 .. 31; + MACA3HR at 16#58# range 0 .. 31; + MACA3LR at 16#5C# range 0 .. 31; end record; -- Ethernet: media access control (MAC) @@ -1457,43 +1373,48 @@ package STM32F40x.Ethernet is -- Ethernet: MAC management counters type Ethernet_MMC_Peripheral is record -- Ethernet MMC control register - MMCCR : MMCCR_Register; + MMCCR : aliased MMCCR_Register; + pragma Volatile_Full_Access (MMCCR); -- Ethernet MMC receive interrupt register - MMCRIR : MMCRIR_Register; + MMCRIR : aliased MMCRIR_Register; + pragma Volatile_Full_Access (MMCRIR); -- Ethernet MMC transmit interrupt register - MMCTIR : MMCTIR_Register; + MMCTIR : aliased MMCTIR_Register; + pragma Volatile_Full_Access (MMCTIR); -- Ethernet MMC receive interrupt mask register - MMCRIMR : MMCRIMR_Register; + MMCRIMR : aliased MMCRIMR_Register; + pragma Volatile_Full_Access (MMCRIMR); -- Ethernet MMC transmit interrupt mask register - MMCTIMR : MMCTIMR_Register; + MMCTIMR : aliased MMCTIMR_Register; + pragma Volatile_Full_Access (MMCTIMR); -- Ethernet MMC transmitted good frames after a single collision counter - MMCTGFSCCR : STM32F40x.Word; + MMCTGFSCCR : aliased STM32F40x.UInt32; -- Ethernet MMC transmitted good frames after more than a single -- collision - MMCTGFMSCCR : STM32F40x.Word; + MMCTGFMSCCR : aliased STM32F40x.UInt32; -- Ethernet MMC transmitted good frames counter register - MMCTGFCR : STM32F40x.Word; + MMCTGFCR : aliased STM32F40x.UInt32; -- Ethernet MMC received frames with CRC error counter register - MMCRFCECR : STM32F40x.Word; + MMCRFCECR : aliased STM32F40x.UInt32; -- Ethernet MMC received frames with alignment error counter register - MMCRFAECR : STM32F40x.Word; + MMCRFAECR : aliased STM32F40x.UInt32; -- MMC received good unicast frames counter register - MMCRGUFCR : STM32F40x.Word; + MMCRGUFCR : aliased STM32F40x.UInt32; end record with Volatile; for Ethernet_MMC_Peripheral use record - MMCCR at 0 range 0 .. 31; - MMCRIR at 4 range 0 .. 31; - MMCTIR at 8 range 0 .. 31; - MMCRIMR at 12 range 0 .. 31; - MMCTIMR at 16 range 0 .. 31; - MMCTGFSCCR at 76 range 0 .. 31; - MMCTGFMSCCR at 80 range 0 .. 31; - MMCTGFCR at 104 range 0 .. 31; - MMCRFCECR at 148 range 0 .. 31; - MMCRFAECR at 152 range 0 .. 31; - MMCRGUFCR at 196 range 0 .. 31; + MMCCR at 16#0# range 0 .. 31; + MMCRIR at 16#4# range 0 .. 31; + MMCTIR at 16#8# range 0 .. 31; + MMCRIMR at 16#C# range 0 .. 31; + MMCTIMR at 16#10# range 0 .. 31; + MMCTGFSCCR at 16#4C# range 0 .. 31; + MMCTGFMSCCR at 16#50# range 0 .. 31; + MMCTGFCR at 16#68# range 0 .. 31; + MMCRFCECR at 16#94# range 0 .. 31; + MMCRFAECR at 16#98# range 0 .. 31; + MMCRGUFCR at 16#C4# range 0 .. 31; end record; -- Ethernet: MAC management counters @@ -1503,100 +1424,52 @@ package STM32F40x.Ethernet is -- Ethernet: Precision time protocol type Ethernet_PTP_Peripheral is record -- Ethernet PTP time stamp control register - PTPTSCR : PTPTSCR_Register; + PTPTSCR : aliased PTPTSCR_Register; + pragma Volatile_Full_Access (PTPTSCR); -- Ethernet PTP subsecond increment register - PTPSSIR : PTPSSIR_Register; + PTPSSIR : aliased PTPSSIR_Register; + pragma Volatile_Full_Access (PTPSSIR); -- Ethernet PTP time stamp high register - PTPTSHR : STM32F40x.Word; + PTPTSHR : aliased STM32F40x.UInt32; -- Ethernet PTP time stamp low register - PTPTSLR : PTPTSLR_Register; + PTPTSLR : aliased PTPTSLR_Register; + pragma Volatile_Full_Access (PTPTSLR); -- Ethernet PTP time stamp high update register - PTPTSHUR : STM32F40x.Word; + PTPTSHUR : aliased STM32F40x.UInt32; -- Ethernet PTP time stamp low update register - PTPTSLUR : PTPTSLUR_Register; + PTPTSLUR : aliased PTPTSLUR_Register; + pragma Volatile_Full_Access (PTPTSLUR); -- Ethernet PTP time stamp addend register - PTPTSAR : STM32F40x.Word; + PTPTSAR : aliased STM32F40x.UInt32; -- Ethernet PTP target time high register - PTPTTHR : STM32F40x.Word; + PTPTTHR : aliased STM32F40x.UInt32; -- Ethernet PTP target time low register - PTPTTLR : STM32F40x.Word; + PTPTTLR : aliased STM32F40x.UInt32; -- Ethernet PTP time stamp status register - PTPTSSR : PTPTSSR_Register; + PTPTSSR : aliased PTPTSSR_Register; + pragma Volatile_Full_Access (PTPTSSR); -- Ethernet PTP PPS control register - PTPPPSCR : PTPPPSCR_Register; + PTPPPSCR : aliased PTPPPSCR_Register; + pragma Volatile_Full_Access (PTPPPSCR); end record with Volatile; for Ethernet_PTP_Peripheral use record - PTPTSCR at 0 range 0 .. 31; - PTPSSIR at 4 range 0 .. 31; - PTPTSHR at 8 range 0 .. 31; - PTPTSLR at 12 range 0 .. 31; - PTPTSHUR at 16 range 0 .. 31; - PTPTSLUR at 20 range 0 .. 31; - PTPTSAR at 24 range 0 .. 31; - PTPTTHR at 28 range 0 .. 31; - PTPTTLR at 32 range 0 .. 31; - PTPTSSR at 40 range 0 .. 31; - PTPPPSCR at 44 range 0 .. 31; + PTPTSCR at 16#0# range 0 .. 31; + PTPSSIR at 16#4# range 0 .. 31; + PTPTSHR at 16#8# range 0 .. 31; + PTPTSLR at 16#C# range 0 .. 31; + PTPTSHUR at 16#10# range 0 .. 31; + PTPTSLUR at 16#14# range 0 .. 31; + PTPTSAR at 16#18# range 0 .. 31; + PTPTTHR at 16#1C# range 0 .. 31; + PTPTTLR at 16#20# range 0 .. 31; + PTPTSSR at 16#28# range 0 .. 31; + PTPPPSCR at 16#2C# range 0 .. 31; end record; -- Ethernet: Precision time protocol Ethernet_PTP_Periph : aliased Ethernet_PTP_Peripheral with Import, Address => Ethernet_PTP_Base; - -- Ethernet: DMA controller operation - type Ethernet_DMA_Peripheral is record - -- Ethernet DMA bus mode register - DMABMR : DMABMR_Register; - -- Ethernet DMA transmit poll demand register - DMATPDR : STM32F40x.Word; - -- EHERNET DMA receive poll demand register - DMARPDR : STM32F40x.Word; - -- Ethernet DMA receive descriptor list address register - DMARDLAR : STM32F40x.Word; - -- Ethernet DMA transmit descriptor list address register - DMATDLAR : STM32F40x.Word; - -- Ethernet DMA status register - DMASR : DMASR_Register; - -- Ethernet DMA operation mode register - DMAOMR : DMAOMR_Register; - -- Ethernet DMA interrupt enable register - DMAIER : DMAIER_Register; - -- Ethernet DMA missed frame and buffer overflow counter register - DMAMFBOCR : DMAMFBOCR_Register; - -- Ethernet DMA receive status watchdog timer register - DMARSWTR : DMARSWTR_Register; - -- Ethernet DMA current host transmit descriptor register - DMACHTDR : STM32F40x.Word; - -- Ethernet DMA current host receive descriptor register - DMACHRDR : STM32F40x.Word; - -- Ethernet DMA current host transmit buffer address register - DMACHTBAR : STM32F40x.Word; - -- Ethernet DMA current host receive buffer address register - DMACHRBAR : STM32F40x.Word; - end record - with Volatile; - - for Ethernet_DMA_Peripheral use record - DMABMR at 0 range 0 .. 31; - DMATPDR at 4 range 0 .. 31; - DMARPDR at 8 range 0 .. 31; - DMARDLAR at 12 range 0 .. 31; - DMATDLAR at 16 range 0 .. 31; - DMASR at 20 range 0 .. 31; - DMAOMR at 24 range 0 .. 31; - DMAIER at 28 range 0 .. 31; - DMAMFBOCR at 32 range 0 .. 31; - DMARSWTR at 36 range 0 .. 31; - DMACHTDR at 72 range 0 .. 31; - DMACHRDR at 76 range 0 .. 31; - DMACHTBAR at 80 range 0 .. 31; - DMACHRBAR at 84 range 0 .. 31; - end record; - - -- Ethernet: DMA controller operation - Ethernet_DMA_Periph : aliased Ethernet_DMA_Peripheral - with Import, Address => Ethernet_DMA_Base; - end STM32F40x.Ethernet; diff --git a/stm32f4/stm32f40x/stm32f40x-exti.ads b/stm32f4/stm32f40x/stm32f40x-exti.ads index 15ed77d..0b76230 100644 --- a/stm32f4/stm32f40x/stm32f40x-exti.ads +++ b/stm32f4/stm32f40x/stm32f40x-exti.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,14 +14,6 @@ package STM32F40x.EXTI is -- Registers -- --------------- - ------------------ - -- IMR_Register -- - ------------------ - - ------------ - -- IMR.MR -- - ------------ - -- IMR_MR array element subtype IMR_MR_Element is STM32F40x.Bit; @@ -55,22 +48,13 @@ package STM32F40x.EXTI is -- unspecified Reserved_23_31 : STM32F40x.UInt9 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IMR_Register use record MR at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------ - -- EMR_Register -- - ------------------ - - ------------ - -- EMR.MR -- - ------------ - -- EMR_MR array element subtype EMR_MR_Element is STM32F40x.Bit; @@ -105,22 +89,13 @@ package STM32F40x.EXTI is -- unspecified Reserved_23_31 : STM32F40x.UInt9 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for EMR_Register use record MR at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- RTSR_Register -- - ------------------- - - ------------- - -- RTSR.TR -- - ------------- - -- RTSR_TR array element subtype RTSR_TR_Element is STM32F40x.Bit; @@ -155,22 +130,13 @@ package STM32F40x.EXTI is -- unspecified Reserved_23_31 : STM32F40x.UInt9 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RTSR_Register use record TR at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- FTSR_Register -- - ------------------- - - ------------- - -- FTSR.TR -- - ------------- - -- FTSR_TR array element subtype FTSR_TR_Element is STM32F40x.Bit; @@ -205,22 +171,13 @@ package STM32F40x.EXTI is -- unspecified Reserved_23_31 : STM32F40x.UInt9 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FTSR_Register use record TR at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - -------------------- - -- SWIER_Register -- - -------------------- - - ----------------- - -- SWIER.SWIER -- - ----------------- - -- SWIER array element subtype SWIER_Element is STM32F40x.Bit; @@ -255,22 +212,13 @@ package STM32F40x.EXTI is -- unspecified Reserved_23_31 : STM32F40x.UInt9 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SWIER_Register use record SWIER at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ----------------- - -- PR_Register -- - ----------------- - - ----------- - -- PR.PR -- - ----------- - -- PR array element subtype PR_Element is STM32F40x.Bit; @@ -305,8 +253,7 @@ package STM32F40x.EXTI is -- unspecified Reserved_23_31 : STM32F40x.UInt9 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PR_Register use record PR at 0 range 0 .. 22; @@ -320,27 +267,33 @@ package STM32F40x.EXTI is -- External interrupt/event controller type EXTI_Peripheral is record -- Interrupt mask register (EXTI_IMR) - IMR : IMR_Register; + IMR : aliased IMR_Register; + pragma Volatile_Full_Access (IMR); -- Event mask register (EXTI_EMR) - EMR : EMR_Register; + EMR : aliased EMR_Register; + pragma Volatile_Full_Access (EMR); -- Rising Trigger selection register (EXTI_RTSR) - RTSR : RTSR_Register; + RTSR : aliased RTSR_Register; + pragma Volatile_Full_Access (RTSR); -- Falling Trigger selection register (EXTI_FTSR) - FTSR : FTSR_Register; + FTSR : aliased FTSR_Register; + pragma Volatile_Full_Access (FTSR); -- Software interrupt event register (EXTI_SWIER) - SWIER : SWIER_Register; + SWIER : aliased SWIER_Register; + pragma Volatile_Full_Access (SWIER); -- Pending register (EXTI_PR) - PR : PR_Register; + PR : aliased PR_Register; + pragma Volatile_Full_Access (PR); end record with Volatile; for EXTI_Peripheral use record - IMR at 0 range 0 .. 31; - EMR at 4 range 0 .. 31; - RTSR at 8 range 0 .. 31; - FTSR at 12 range 0 .. 31; - SWIER at 16 range 0 .. 31; - PR at 20 range 0 .. 31; + IMR at 16#0# range 0 .. 31; + EMR at 16#4# range 0 .. 31; + RTSR at 16#8# range 0 .. 31; + FTSR at 16#C# range 0 .. 31; + SWIER at 16#10# range 0 .. 31; + PR at 16#14# range 0 .. 31; end record; -- External interrupt/event controller diff --git a/stm32f4/stm32f40x/stm32f40x-flash.ads b/stm32f4/stm32f40x/stm32f40x-flash.ads index 5c622ec..369fe5b 100644 --- a/stm32f4/stm32f40x/stm32f40x-flash.ads +++ b/stm32f4/stm32f40x/stm32f40x-flash.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.FLASH is -- Registers -- --------------- - ------------------ - -- ACR_Register -- - ------------------ - subtype ACR_LATENCY_Field is STM32F40x.UInt3; subtype ACR_PRFTEN_Field is STM32F40x.Bit; subtype ACR_ICEN_Field is STM32F40x.Bit; @@ -43,8 +40,7 @@ package STM32F40x.FLASH is -- unspecified Reserved_13_31 : STM32F40x.UInt19 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ACR_Register use record LATENCY at 0 range 0 .. 2; @@ -57,10 +53,6 @@ package STM32F40x.FLASH is Reserved_13_31 at 0 range 13 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_EOP_Field is STM32F40x.Bit; subtype SR_OPERR_Field is STM32F40x.Bit; subtype SR_WRPERR_Field is STM32F40x.Bit; @@ -92,8 +84,7 @@ package STM32F40x.FLASH is -- unspecified Reserved_17_31 : STM32F40x.UInt15 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record EOP at 0 range 0 .. 0; @@ -108,10 +99,6 @@ package STM32F40x.FLASH is Reserved_17_31 at 0 range 17 .. 31; end record; - ----------------- - -- CR_Register -- - ----------------- - subtype CR_PG_Field is STM32F40x.Bit; subtype CR_SER_Field is STM32F40x.Bit; subtype CR_MER_Field is STM32F40x.Bit; @@ -151,8 +138,7 @@ package STM32F40x.FLASH is -- Lock LOCK : CR_LOCK_Field := 16#1#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record PG at 0 range 0 .. 0; @@ -170,10 +156,6 @@ package STM32F40x.FLASH is LOCK at 0 range 31 .. 31; end record; - -------------------- - -- OPTCR_Register -- - -------------------- - subtype OPTCR_OPTLOCK_Field is STM32F40x.Bit; subtype OPTCR_OPTSTRT_Field is STM32F40x.Bit; subtype OPTCR_BOR_LEV_Field is STM32F40x.UInt2; @@ -206,8 +188,7 @@ package STM32F40x.FLASH is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OPTCR_Register use record OPTLOCK at 0 range 0 .. 0; @@ -229,27 +210,31 @@ package STM32F40x.FLASH is -- FLASH type FLASH_Peripheral is record -- Flash access control register - ACR : ACR_Register; + ACR : aliased ACR_Register; + pragma Volatile_Full_Access (ACR); -- Flash key register - KEYR : STM32F40x.Word; + KEYR : aliased STM32F40x.UInt32; -- Flash option key register - OPTKEYR : STM32F40x.Word; + OPTKEYR : aliased STM32F40x.UInt32; -- Status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- Control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- Flash option control register - OPTCR : OPTCR_Register; + OPTCR : aliased OPTCR_Register; + pragma Volatile_Full_Access (OPTCR); end record with Volatile; for FLASH_Peripheral use record - ACR at 0 range 0 .. 31; - KEYR at 4 range 0 .. 31; - OPTKEYR at 8 range 0 .. 31; - SR at 12 range 0 .. 31; - CR at 16 range 0 .. 31; - OPTCR at 20 range 0 .. 31; + ACR at 16#0# range 0 .. 31; + KEYR at 16#4# range 0 .. 31; + OPTKEYR at 16#8# range 0 .. 31; + SR at 16#C# range 0 .. 31; + CR at 16#10# range 0 .. 31; + OPTCR at 16#14# range 0 .. 31; end record; -- FLASH diff --git a/stm32f4/stm32f40x/stm32f40x-fsmc.ads b/stm32f4/stm32f40x/stm32f40x-fsmc.ads index 1c70269..35ad0ef 100644 --- a/stm32f4/stm32f40x/stm32f40x-fsmc.ads +++ b/stm32f4/stm32f40x/stm32f40x-fsmc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.FSMC is -- Registers -- --------------- - ------------------- - -- BCR1_Register -- - ------------------- - subtype BCR1_MBKEN_Field is STM32F40x.Bit; subtype BCR1_MUXEN_Field is STM32F40x.Bit; subtype BCR1_MTYP_Field is STM32F40x.UInt2; @@ -68,8 +65,7 @@ package STM32F40x.FSMC is -- unspecified Reserved_20_31 : STM32F40x.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BCR1_Register use record MBKEN at 0 range 0 .. 0; @@ -91,39 +87,34 @@ package STM32F40x.FSMC is Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------ - -- BTR_Register -- - ------------------ - - subtype BTR1_ADDSET_Field is STM32F40x.UInt4; - subtype BTR1_ADDHLD_Field is STM32F40x.UInt4; - subtype BTR1_DATAST_Field is STM32F40x.Byte; - subtype BTR1_BUSTURN_Field is STM32F40x.UInt4; - subtype BTR1_CLKDIV_Field is STM32F40x.UInt4; - subtype BTR1_DATLAT_Field is STM32F40x.UInt4; - subtype BTR1_ACCMOD_Field is STM32F40x.UInt2; + subtype BTR_ADDSET_Field is STM32F40x.UInt4; + subtype BTR_ADDHLD_Field is STM32F40x.UInt4; + subtype BTR_DATAST_Field is STM32F40x.Byte; + subtype BTR_BUSTURN_Field is STM32F40x.UInt4; + subtype BTR_CLKDIV_Field is STM32F40x.UInt4; + subtype BTR_DATLAT_Field is STM32F40x.UInt4; + subtype BTR_ACCMOD_Field is STM32F40x.UInt2; -- SRAM/NOR-Flash chip-select timing register 1 type BTR_Register is record -- ADDSET - ADDSET : BTR1_ADDSET_Field := 16#F#; + ADDSET : BTR_ADDSET_Field := 16#F#; -- ADDHLD - ADDHLD : BTR1_ADDHLD_Field := 16#F#; + ADDHLD : BTR_ADDHLD_Field := 16#F#; -- DATAST - DATAST : BTR1_DATAST_Field := 16#FF#; + DATAST : BTR_DATAST_Field := 16#FF#; -- BUSTURN - BUSTURN : BTR1_BUSTURN_Field := 16#F#; + BUSTURN : BTR_BUSTURN_Field := 16#F#; -- CLKDIV - CLKDIV : BTR1_CLKDIV_Field := 16#F#; + CLKDIV : BTR_CLKDIV_Field := 16#F#; -- DATLAT - DATLAT : BTR1_DATLAT_Field := 16#F#; + DATLAT : BTR_DATLAT_Field := 16#F#; -- ACCMOD - ACCMOD : BTR1_ACCMOD_Field := 16#3#; + ACCMOD : BTR_ACCMOD_Field := 16#3#; -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#3#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BTR_Register use record ADDSET at 0 range 0 .. 3; @@ -136,64 +127,59 @@ package STM32F40x.FSMC is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- BCR_Register -- - ------------------ - - subtype BCR2_MBKEN_Field is STM32F40x.Bit; - subtype BCR2_MUXEN_Field is STM32F40x.Bit; - subtype BCR2_MTYP_Field is STM32F40x.UInt2; - subtype BCR2_MWID_Field is STM32F40x.UInt2; - subtype BCR2_FACCEN_Field is STM32F40x.Bit; - subtype BCR2_BURSTEN_Field is STM32F40x.Bit; - subtype BCR2_WAITPOL_Field is STM32F40x.Bit; - subtype BCR2_WRAPMOD_Field is STM32F40x.Bit; - subtype BCR2_WAITCFG_Field is STM32F40x.Bit; - subtype BCR2_WREN_Field is STM32F40x.Bit; - subtype BCR2_WAITEN_Field is STM32F40x.Bit; - subtype BCR2_EXTMOD_Field is STM32F40x.Bit; - subtype BCR2_ASYNCWAIT_Field is STM32F40x.Bit; - subtype BCR2_CBURSTRW_Field is STM32F40x.Bit; + subtype BCR_MBKEN_Field is STM32F40x.Bit; + subtype BCR_MUXEN_Field is STM32F40x.Bit; + subtype BCR_MTYP_Field is STM32F40x.UInt2; + subtype BCR_MWID_Field is STM32F40x.UInt2; + subtype BCR_FACCEN_Field is STM32F40x.Bit; + subtype BCR_BURSTEN_Field is STM32F40x.Bit; + subtype BCR_WAITPOL_Field is STM32F40x.Bit; + subtype BCR_WRAPMOD_Field is STM32F40x.Bit; + subtype BCR_WAITCFG_Field is STM32F40x.Bit; + subtype BCR_WREN_Field is STM32F40x.Bit; + subtype BCR_WAITEN_Field is STM32F40x.Bit; + subtype BCR_EXTMOD_Field is STM32F40x.Bit; + subtype BCR_ASYNCWAIT_Field is STM32F40x.Bit; + subtype BCR_CBURSTRW_Field is STM32F40x.Bit; -- SRAM/NOR-Flash chip-select control register 2 type BCR_Register is record -- MBKEN - MBKEN : BCR2_MBKEN_Field := 16#0#; + MBKEN : BCR_MBKEN_Field := 16#0#; -- MUXEN - MUXEN : BCR2_MUXEN_Field := 16#0#; + MUXEN : BCR_MUXEN_Field := 16#0#; -- MTYP - MTYP : BCR2_MTYP_Field := 16#0#; + MTYP : BCR_MTYP_Field := 16#0#; -- MWID - MWID : BCR2_MWID_Field := 16#1#; + MWID : BCR_MWID_Field := 16#1#; -- FACCEN - FACCEN : BCR2_FACCEN_Field := 16#1#; + FACCEN : BCR_FACCEN_Field := 16#1#; -- unspecified Reserved_7_7 : STM32F40x.Bit := 16#1#; -- BURSTEN - BURSTEN : BCR2_BURSTEN_Field := 16#0#; + BURSTEN : BCR_BURSTEN_Field := 16#0#; -- WAITPOL - WAITPOL : BCR2_WAITPOL_Field := 16#0#; + WAITPOL : BCR_WAITPOL_Field := 16#0#; -- WRAPMOD - WRAPMOD : BCR2_WRAPMOD_Field := 16#0#; + WRAPMOD : BCR_WRAPMOD_Field := 16#0#; -- WAITCFG - WAITCFG : BCR2_WAITCFG_Field := 16#0#; + WAITCFG : BCR_WAITCFG_Field := 16#0#; -- WREN - WREN : BCR2_WREN_Field := 16#1#; + WREN : BCR_WREN_Field := 16#1#; -- WAITEN - WAITEN : BCR2_WAITEN_Field := 16#1#; + WAITEN : BCR_WAITEN_Field := 16#1#; -- EXTMOD - EXTMOD : BCR2_EXTMOD_Field := 16#0#; + EXTMOD : BCR_EXTMOD_Field := 16#0#; -- ASYNCWAIT - ASYNCWAIT : BCR2_ASYNCWAIT_Field := 16#0#; + ASYNCWAIT : BCR_ASYNCWAIT_Field := 16#0#; -- unspecified Reserved_16_18 : STM32F40x.UInt3 := 16#0#; -- CBURSTRW - CBURSTRW : BCR2_CBURSTRW_Field := 16#0#; + CBURSTRW : BCR_CBURSTRW_Field := 16#0#; -- unspecified Reserved_20_31 : STM32F40x.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BCR_Register use record MBKEN at 0 range 0 .. 0; @@ -215,46 +201,41 @@ package STM32F40x.FSMC is Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------ - -- PCR_Register -- - ------------------ - - subtype PCR2_PWAITEN_Field is STM32F40x.Bit; - subtype PCR2_PBKEN_Field is STM32F40x.Bit; - subtype PCR2_PTYP_Field is STM32F40x.Bit; - subtype PCR2_PWID_Field is STM32F40x.UInt2; - subtype PCR2_ECCEN_Field is STM32F40x.Bit; - subtype PCR2_TCLR_Field is STM32F40x.UInt4; - subtype PCR2_TAR_Field is STM32F40x.UInt4; - subtype PCR2_ECCPS_Field is STM32F40x.UInt3; + subtype PCR_PWAITEN_Field is STM32F40x.Bit; + subtype PCR_PBKEN_Field is STM32F40x.Bit; + subtype PCR_PTYP_Field is STM32F40x.Bit; + subtype PCR_PWID_Field is STM32F40x.UInt2; + subtype PCR_ECCEN_Field is STM32F40x.Bit; + subtype PCR_TCLR_Field is STM32F40x.UInt4; + subtype PCR_TAR_Field is STM32F40x.UInt4; + subtype PCR_ECCPS_Field is STM32F40x.UInt3; -- PC Card/NAND Flash control register 2 type PCR_Register is record -- unspecified Reserved_0_0 : STM32F40x.Bit := 16#0#; -- PWAITEN - PWAITEN : PCR2_PWAITEN_Field := 16#0#; + PWAITEN : PCR_PWAITEN_Field := 16#0#; -- PBKEN - PBKEN : PCR2_PBKEN_Field := 16#0#; + PBKEN : PCR_PBKEN_Field := 16#0#; -- PTYP - PTYP : PCR2_PTYP_Field := 16#1#; + PTYP : PCR_PTYP_Field := 16#1#; -- PWID - PWID : PCR2_PWID_Field := 16#1#; + PWID : PCR_PWID_Field := 16#1#; -- ECCEN - ECCEN : PCR2_ECCEN_Field := 16#0#; + ECCEN : PCR_ECCEN_Field := 16#0#; -- unspecified Reserved_7_8 : STM32F40x.UInt2 := 16#0#; -- TCLR - TCLR : PCR2_TCLR_Field := 16#0#; + TCLR : PCR_TCLR_Field := 16#0#; -- TAR - TAR : PCR2_TAR_Field := 16#0#; + TAR : PCR_TAR_Field := 16#0#; -- ECCPS - ECCPS : PCR2_ECCPS_Field := 16#0#; + ECCPS : PCR_ECCPS_Field := 16#0#; -- unspecified Reserved_20_31 : STM32F40x.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PCR_Register use record Reserved_0_0 at 0 range 0 .. 0; @@ -270,39 +251,34 @@ package STM32F40x.FSMC is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR2_IRS_Field is STM32F40x.Bit; - subtype SR2_ILS_Field is STM32F40x.Bit; - subtype SR2_IFS_Field is STM32F40x.Bit; - subtype SR2_IREN_Field is STM32F40x.Bit; - subtype SR2_ILEN_Field is STM32F40x.Bit; - subtype SR2_IFEN_Field is STM32F40x.Bit; - subtype SR2_FEMPT_Field is STM32F40x.Bit; + subtype SR_IRS_Field is STM32F40x.Bit; + subtype SR_ILS_Field is STM32F40x.Bit; + subtype SR_IFS_Field is STM32F40x.Bit; + subtype SR_IREN_Field is STM32F40x.Bit; + subtype SR_ILEN_Field is STM32F40x.Bit; + subtype SR_IFEN_Field is STM32F40x.Bit; + subtype SR_FEMPT_Field is STM32F40x.Bit; -- FIFO status and interrupt register 2 type SR_Register is record -- IRS - IRS : SR2_IRS_Field := 16#0#; + IRS : SR_IRS_Field := 16#0#; -- ILS - ILS : SR2_ILS_Field := 16#0#; + ILS : SR_ILS_Field := 16#0#; -- IFS - IFS : SR2_IFS_Field := 16#0#; + IFS : SR_IFS_Field := 16#0#; -- IREN - IREN : SR2_IREN_Field := 16#0#; + IREN : SR_IREN_Field := 16#0#; -- ILEN - ILEN : SR2_ILEN_Field := 16#0#; + ILEN : SR_ILEN_Field := 16#0#; -- IFEN - IFEN : SR2_IFEN_Field := 16#0#; + IFEN : SR_IFEN_Field := 16#0#; -- Read-only. FEMPT - FEMPT : SR2_FEMPT_Field := 16#1#; + FEMPT : SR_FEMPT_Field := 16#1#; -- unspecified Reserved_7_31 : STM32F40x.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record IRS at 0 range 0 .. 0; @@ -315,28 +291,23 @@ package STM32F40x.FSMC is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------- - -- PMEM_Register -- - ------------------- - - subtype PMEM2_MEMSETx_Field is STM32F40x.Byte; - subtype PMEM2_MEMWAITx_Field is STM32F40x.Byte; - subtype PMEM2_MEMHOLDx_Field is STM32F40x.Byte; - subtype PMEM2_MEMHIZx_Field is STM32F40x.Byte; + subtype PMEM_MEMSETx_Field is STM32F40x.Byte; + subtype PMEM_MEMWAITx_Field is STM32F40x.Byte; + subtype PMEM_MEMHOLDx_Field is STM32F40x.Byte; + subtype PMEM_MEMHIZx_Field is STM32F40x.Byte; -- Common memory space timing register 2 type PMEM_Register is record -- MEMSETx - MEMSETx : PMEM2_MEMSETx_Field := 16#FC#; + MEMSETx : PMEM_MEMSETx_Field := 16#FC#; -- MEMWAITx - MEMWAITx : PMEM2_MEMWAITx_Field := 16#FC#; + MEMWAITx : PMEM_MEMWAITx_Field := 16#FC#; -- MEMHOLDx - MEMHOLDx : PMEM2_MEMHOLDx_Field := 16#FC#; + MEMHOLDx : PMEM_MEMHOLDx_Field := 16#FC#; -- MEMHIZx - MEMHIZx : PMEM2_MEMHIZx_Field := 16#FC#; + MEMHIZx : PMEM_MEMHIZx_Field := 16#FC#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMEM_Register use record MEMSETx at 0 range 0 .. 7; @@ -345,28 +316,23 @@ package STM32F40x.FSMC is MEMHIZx at 0 range 24 .. 31; end record; - ------------------- - -- PATT_Register -- - ------------------- - - subtype PATT2_ATTSETx_Field is STM32F40x.Byte; - subtype PATT2_ATTWAITx_Field is STM32F40x.Byte; - subtype PATT2_ATTHOLDx_Field is STM32F40x.Byte; - subtype PATT2_ATTHIZx_Field is STM32F40x.Byte; + subtype PATT_ATTSETx_Field is STM32F40x.Byte; + subtype PATT_ATTWAITx_Field is STM32F40x.Byte; + subtype PATT_ATTHOLDx_Field is STM32F40x.Byte; + subtype PATT_ATTHIZx_Field is STM32F40x.Byte; -- Attribute memory space timing register 2 type PATT_Register is record -- ATTSETx - ATTSETx : PATT2_ATTSETx_Field := 16#FC#; + ATTSETx : PATT_ATTSETx_Field := 16#FC#; -- ATTWAITx - ATTWAITx : PATT2_ATTWAITx_Field := 16#FC#; + ATTWAITx : PATT_ATTWAITx_Field := 16#FC#; -- ATTHOLDx - ATTHOLDx : PATT2_ATTHOLDx_Field := 16#FC#; + ATTHOLDx : PATT_ATTHOLDx_Field := 16#FC#; -- ATTHIZx - ATTHIZx : PATT2_ATTHIZx_Field := 16#FC#; + ATTHIZx : PATT_ATTHIZx_Field := 16#FC#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PATT_Register use record ATTSETx at 0 range 0 .. 7; @@ -375,10 +341,6 @@ package STM32F40x.FSMC is ATTHIZx at 0 range 24 .. 31; end record; - ------------------- - -- PIO4_Register -- - ------------------- - subtype PIO4_IOSETx_Field is STM32F40x.Byte; subtype PIO4_IOWAITx_Field is STM32F40x.Byte; subtype PIO4_IOHOLDx_Field is STM32F40x.Byte; @@ -395,8 +357,7 @@ package STM32F40x.FSMC is -- IOHIZx IOHIZx : PIO4_IOHIZx_Field := 16#FC#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PIO4_Register use record IOSETx at 0 range 0 .. 7; @@ -405,38 +366,33 @@ package STM32F40x.FSMC is IOHIZx at 0 range 24 .. 31; end record; - ------------------- - -- BWTR_Register -- - ------------------- - - subtype BWTR1_ADDSET_Field is STM32F40x.UInt4; - subtype BWTR1_ADDHLD_Field is STM32F40x.UInt4; - subtype BWTR1_DATAST_Field is STM32F40x.Byte; - subtype BWTR1_CLKDIV_Field is STM32F40x.UInt4; - subtype BWTR1_DATLAT_Field is STM32F40x.UInt4; - subtype BWTR1_ACCMOD_Field is STM32F40x.UInt2; + subtype BWTR_ADDSET_Field is STM32F40x.UInt4; + subtype BWTR_ADDHLD_Field is STM32F40x.UInt4; + subtype BWTR_DATAST_Field is STM32F40x.Byte; + subtype BWTR_CLKDIV_Field is STM32F40x.UInt4; + subtype BWTR_DATLAT_Field is STM32F40x.UInt4; + subtype BWTR_ACCMOD_Field is STM32F40x.UInt2; -- SRAM/NOR-Flash write timing registers 1 type BWTR_Register is record -- ADDSET - ADDSET : BWTR1_ADDSET_Field := 16#F#; + ADDSET : BWTR_ADDSET_Field := 16#F#; -- ADDHLD - ADDHLD : BWTR1_ADDHLD_Field := 16#F#; + ADDHLD : BWTR_ADDHLD_Field := 16#F#; -- DATAST - DATAST : BWTR1_DATAST_Field := 16#FF#; + DATAST : BWTR_DATAST_Field := 16#FF#; -- unspecified Reserved_16_19 : STM32F40x.UInt4 := 16#F#; -- CLKDIV - CLKDIV : BWTR1_CLKDIV_Field := 16#F#; + CLKDIV : BWTR_CLKDIV_Field := 16#F#; -- DATLAT - DATLAT : BWTR1_DATLAT_Field := 16#F#; + DATLAT : BWTR_DATLAT_Field := 16#F#; -- ACCMOD - ACCMOD : BWTR1_ACCMOD_Field := 16#0#; + ACCMOD : BWTR_ACCMOD_Field := 16#0#; -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BWTR_Register use record ADDSET at 0 range 0 .. 3; @@ -456,90 +412,115 @@ package STM32F40x.FSMC is -- Flexible static memory controller type FSMC_Peripheral is record -- SRAM/NOR-Flash chip-select control register 1 - BCR1 : BCR1_Register; + BCR1 : aliased BCR1_Register; + pragma Volatile_Full_Access (BCR1); -- SRAM/NOR-Flash chip-select timing register 1 - BTR1 : BTR_Register; + BTR1 : aliased BTR_Register; + pragma Volatile_Full_Access (BTR1); -- SRAM/NOR-Flash chip-select control register 2 - BCR2 : BCR_Register; + BCR2 : aliased BCR_Register; + pragma Volatile_Full_Access (BCR2); -- SRAM/NOR-Flash chip-select timing register 2 - BTR2 : BTR_Register; + BTR2 : aliased BTR_Register; + pragma Volatile_Full_Access (BTR2); -- SRAM/NOR-Flash chip-select control register 3 - BCR3 : BCR_Register; + BCR3 : aliased BCR_Register; + pragma Volatile_Full_Access (BCR3); -- SRAM/NOR-Flash chip-select timing register 3 - BTR3 : BTR_Register; + BTR3 : aliased BTR_Register; + pragma Volatile_Full_Access (BTR3); -- SRAM/NOR-Flash chip-select control register 4 - BCR4 : BCR_Register; + BCR4 : aliased BCR_Register; + pragma Volatile_Full_Access (BCR4); -- SRAM/NOR-Flash chip-select timing register 4 - BTR4 : BTR_Register; + BTR4 : aliased BTR_Register; + pragma Volatile_Full_Access (BTR4); -- PC Card/NAND Flash control register 2 - PCR2 : PCR_Register; + PCR2 : aliased PCR_Register; + pragma Volatile_Full_Access (PCR2); -- FIFO status and interrupt register 2 - SR2 : SR_Register; + SR2 : aliased SR_Register; + pragma Volatile_Full_Access (SR2); -- Common memory space timing register 2 - PMEM2 : PMEM_Register; + PMEM2 : aliased PMEM_Register; + pragma Volatile_Full_Access (PMEM2); -- Attribute memory space timing register 2 - PATT2 : PATT_Register; + PATT2 : aliased PATT_Register; + pragma Volatile_Full_Access (PATT2); -- ECC result register 2 - ECCR2 : STM32F40x.Word; + ECCR2 : aliased STM32F40x.UInt32; -- PC Card/NAND Flash control register 3 - PCR3 : PCR_Register; + PCR3 : aliased PCR_Register; + pragma Volatile_Full_Access (PCR3); -- FIFO status and interrupt register 3 - SR3 : SR_Register; + SR3 : aliased SR_Register; + pragma Volatile_Full_Access (SR3); -- Common memory space timing register 3 - PMEM3 : PMEM_Register; + PMEM3 : aliased PMEM_Register; + pragma Volatile_Full_Access (PMEM3); -- Attribute memory space timing register 3 - PATT3 : PATT_Register; + PATT3 : aliased PATT_Register; + pragma Volatile_Full_Access (PATT3); -- ECC result register 3 - ECCR3 : STM32F40x.Word; + ECCR3 : aliased STM32F40x.UInt32; -- PC Card/NAND Flash control register 4 - PCR4 : PCR_Register; + PCR4 : aliased PCR_Register; + pragma Volatile_Full_Access (PCR4); -- FIFO status and interrupt register 4 - SR4 : SR_Register; + SR4 : aliased SR_Register; + pragma Volatile_Full_Access (SR4); -- Common memory space timing register 4 - PMEM4 : PMEM_Register; + PMEM4 : aliased PMEM_Register; + pragma Volatile_Full_Access (PMEM4); -- Attribute memory space timing register 4 - PATT4 : PATT_Register; + PATT4 : aliased PATT_Register; + pragma Volatile_Full_Access (PATT4); -- I/O space timing register 4 - PIO4 : PIO4_Register; + PIO4 : aliased PIO4_Register; + pragma Volatile_Full_Access (PIO4); -- SRAM/NOR-Flash write timing registers 1 - BWTR1 : BWTR_Register; + BWTR1 : aliased BWTR_Register; + pragma Volatile_Full_Access (BWTR1); -- SRAM/NOR-Flash write timing registers 2 - BWTR2 : BWTR_Register; + BWTR2 : aliased BWTR_Register; + pragma Volatile_Full_Access (BWTR2); -- SRAM/NOR-Flash write timing registers 3 - BWTR3 : BWTR_Register; + BWTR3 : aliased BWTR_Register; + pragma Volatile_Full_Access (BWTR3); -- SRAM/NOR-Flash write timing registers 4 - BWTR4 : BWTR_Register; + BWTR4 : aliased BWTR_Register; + pragma Volatile_Full_Access (BWTR4); end record with Volatile; for FSMC_Peripheral use record - BCR1 at 0 range 0 .. 31; - BTR1 at 4 range 0 .. 31; - BCR2 at 8 range 0 .. 31; - BTR2 at 12 range 0 .. 31; - BCR3 at 16 range 0 .. 31; - BTR3 at 20 range 0 .. 31; - BCR4 at 24 range 0 .. 31; - BTR4 at 28 range 0 .. 31; - PCR2 at 96 range 0 .. 31; - SR2 at 100 range 0 .. 31; - PMEM2 at 104 range 0 .. 31; - PATT2 at 108 range 0 .. 31; - ECCR2 at 116 range 0 .. 31; - PCR3 at 128 range 0 .. 31; - SR3 at 132 range 0 .. 31; - PMEM3 at 136 range 0 .. 31; - PATT3 at 140 range 0 .. 31; - ECCR3 at 148 range 0 .. 31; - PCR4 at 160 range 0 .. 31; - SR4 at 164 range 0 .. 31; - PMEM4 at 168 range 0 .. 31; - PATT4 at 172 range 0 .. 31; - PIO4 at 176 range 0 .. 31; - BWTR1 at 260 range 0 .. 31; - BWTR2 at 268 range 0 .. 31; - BWTR3 at 276 range 0 .. 31; - BWTR4 at 284 range 0 .. 31; + BCR1 at 16#0# range 0 .. 31; + BTR1 at 16#4# range 0 .. 31; + BCR2 at 16#8# range 0 .. 31; + BTR2 at 16#C# range 0 .. 31; + BCR3 at 16#10# range 0 .. 31; + BTR3 at 16#14# range 0 .. 31; + BCR4 at 16#18# range 0 .. 31; + BTR4 at 16#1C# range 0 .. 31; + PCR2 at 16#60# range 0 .. 31; + SR2 at 16#64# range 0 .. 31; + PMEM2 at 16#68# range 0 .. 31; + PATT2 at 16#6C# range 0 .. 31; + ECCR2 at 16#74# range 0 .. 31; + PCR3 at 16#80# range 0 .. 31; + SR3 at 16#84# range 0 .. 31; + PMEM3 at 16#88# range 0 .. 31; + PATT3 at 16#8C# range 0 .. 31; + ECCR3 at 16#94# range 0 .. 31; + PCR4 at 16#A0# range 0 .. 31; + SR4 at 16#A4# range 0 .. 31; + PMEM4 at 16#A8# range 0 .. 31; + PATT4 at 16#AC# range 0 .. 31; + PIO4 at 16#B0# range 0 .. 31; + BWTR1 at 16#104# range 0 .. 31; + BWTR2 at 16#10C# range 0 .. 31; + BWTR3 at 16#114# range 0 .. 31; + BWTR4 at 16#11C# range 0 .. 31; end record; -- Flexible static memory controller diff --git a/stm32f4/stm32f40x/stm32f40x-gpio.ads b/stm32f4/stm32f40x/stm32f40x-gpio.ads index 0b30456..75e1ebe 100644 --- a/stm32f4/stm32f40x/stm32f40x-gpio.ads +++ b/stm32f4/stm32f40x/stm32f40x-gpio.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.GPIO is -- Registers -- --------------- - -------------------- - -- MODER_Register -- - -------------------- - -- MODER array element subtype MODER_Element is STM32F40x.UInt2; @@ -31,13 +28,13 @@ package STM32F40x.GPIO is case As_Array is when False => -- MODER as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- MODER as an array Arr : MODER_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for MODER_Register use record @@ -45,14 +42,6 @@ package STM32F40x.GPIO is Arr at 0 range 0 .. 31; end record; - --------------------- - -- OTYPER_Register -- - --------------------- - - --------------- - -- OTYPER.OT -- - --------------- - -- OTYPER_OT array element subtype OTYPER_OT_Element is STM32F40x.Bit; @@ -67,7 +56,7 @@ package STM32F40x.GPIO is case As_Array is when False => -- OT as a value - Val : STM32F40x.Short; + Val : STM32F40x.UInt16; when True => -- OT as an array Arr : OTYPER_OT_Field_Array; @@ -85,20 +74,15 @@ package STM32F40x.GPIO is -- Port x configuration bits (y = 0..15) OT : OTYPER_OT_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OTYPER_Register use record OT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- OSPEEDR_Register -- - ---------------------- - -- OSPEEDR array element subtype OSPEEDR_Element is STM32F40x.UInt2; @@ -113,13 +97,13 @@ package STM32F40x.GPIO is case As_Array is when False => -- OSPEEDR as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- OSPEEDR as an array Arr : OSPEEDR_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for OSPEEDR_Register use record @@ -127,10 +111,6 @@ package STM32F40x.GPIO is Arr at 0 range 0 .. 31; end record; - -------------------- - -- PUPDR_Register -- - -------------------- - -- PUPDR array element subtype PUPDR_Element is STM32F40x.UInt2; @@ -145,13 +125,13 @@ package STM32F40x.GPIO is case As_Array is when False => -- PUPDR as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- PUPDR as an array Arr : PUPDR_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for PUPDR_Register use record @@ -159,14 +139,6 @@ package STM32F40x.GPIO is Arr at 0 range 0 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - ------------- - -- IDR.IDR -- - ------------- - -- IDR array element subtype IDR_Element is STM32F40x.Bit; @@ -181,7 +153,7 @@ package STM32F40x.GPIO is case As_Array is when False => -- IDR as a value - Val : STM32F40x.Short; + Val : STM32F40x.UInt16; when True => -- IDR as an array Arr : IDR_Field_Array; @@ -197,26 +169,17 @@ package STM32F40x.GPIO is -- GPIO port input data register type IDR_Register is record -- Read-only. Port input data (y = 0..15) - IDR : IDR_Field := (As_Array => False, Val => 16#0#); + IDR : IDR_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IDR_Register use record IDR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- ODR_Register -- - ------------------ - - ------------- - -- ODR.ODR -- - ------------- - -- ODR array element subtype ODR_Element is STM32F40x.Bit; @@ -231,7 +194,7 @@ package STM32F40x.GPIO is case As_Array is when False => -- ODR as a value - Val : STM32F40x.Short; + Val : STM32F40x.UInt16; when True => -- ODR as an array Arr : ODR_Field_Array; @@ -249,24 +212,15 @@ package STM32F40x.GPIO is -- Port output data (y = 0..15) ODR : ODR_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ODR_Register use record ODR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- BSRR_Register -- - ------------------- - - ------------- - -- BSRR.BS -- - ------------- - -- BSRR_BS array element subtype BSRR_BS_Element is STM32F40x.Bit; @@ -281,7 +235,7 @@ package STM32F40x.GPIO is case As_Array is when False => -- BS as a value - Val : STM32F40x.Short; + Val : STM32F40x.UInt16; when True => -- BS as an array Arr : BSRR_BS_Field_Array; @@ -294,10 +248,6 @@ package STM32F40x.GPIO is Arr at 0 range 0 .. 15; end record; - ------------- - -- BSRR.BR -- - ------------- - -- BSRR_BR array element subtype BSRR_BR_Element is STM32F40x.Bit; @@ -312,7 +262,7 @@ package STM32F40x.GPIO is case As_Array is when False => -- BR as a value - Val : STM32F40x.Short; + Val : STM32F40x.UInt16; when True => -- BR as an array Arr : BSRR_BR_Field_Array; @@ -332,22 +282,13 @@ package STM32F40x.GPIO is -- Write-only. Port x set bit y (y= 0..15) BR : BSRR_BR_Field := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BSRR_Register use record BS at 0 range 0 .. 15; BR at 0 range 16 .. 31; end record; - ------------------- - -- LCKR_Register -- - ------------------- - - -------------- - -- LCKR.LCK -- - -------------- - -- LCKR_LCK array element subtype LCKR_LCK_Element is STM32F40x.Bit; @@ -362,7 +303,7 @@ package STM32F40x.GPIO is case As_Array is when False => -- LCK as a value - Val : STM32F40x.Short; + Val : STM32F40x.UInt16; when True => -- LCK as an array Arr : LCKR_LCK_Field_Array; @@ -386,8 +327,7 @@ package STM32F40x.GPIO is -- unspecified Reserved_17_31 : STM32F40x.UInt15 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LCKR_Register use record LCK at 0 range 0 .. 15; @@ -395,10 +335,6 @@ package STM32F40x.GPIO is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------- - -- AFRL_Register -- - ------------------- - -- AFRL array element subtype AFRL_Element is STM32F40x.UInt4; @@ -413,13 +349,13 @@ package STM32F40x.GPIO is case As_Array is when False => -- AFRL as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- AFRL as an array Arr : AFRL_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for AFRL_Register use record @@ -427,10 +363,6 @@ package STM32F40x.GPIO is Arr at 0 range 0 .. 31; end record; - ------------------- - -- AFRH_Register -- - ------------------- - -- AFRH array element subtype AFRH_Element is STM32F40x.UInt4; @@ -445,13 +377,13 @@ package STM32F40x.GPIO is case As_Array is when False => -- AFRH as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- AFRH as an array Arr : AFRH_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for AFRH_Register use record @@ -466,39 +398,49 @@ package STM32F40x.GPIO is -- General-purpose I/Os type GPIO_Peripheral is record -- GPIO port mode register - MODER : MODER_Register; + MODER : aliased MODER_Register; + pragma Volatile_Full_Access (MODER); -- GPIO port output type register - OTYPER : OTYPER_Register; + OTYPER : aliased OTYPER_Register; + pragma Volatile_Full_Access (OTYPER); -- GPIO port output speed register - OSPEEDR : OSPEEDR_Register; + OSPEEDR : aliased OSPEEDR_Register; + pragma Volatile_Full_Access (OSPEEDR); -- GPIO port pull-up/pull-down register - PUPDR : PUPDR_Register; + PUPDR : aliased PUPDR_Register; + pragma Volatile_Full_Access (PUPDR); -- GPIO port input data register - IDR : IDR_Register; + IDR : aliased IDR_Register; + pragma Volatile_Full_Access (IDR); -- GPIO port output data register - ODR : ODR_Register; + ODR : aliased ODR_Register; + pragma Volatile_Full_Access (ODR); -- GPIO port bit set/reset register - BSRR : BSRR_Register; + BSRR : aliased BSRR_Register; + pragma Volatile_Full_Access (BSRR); -- GPIO port configuration lock register - LCKR : LCKR_Register; + LCKR : aliased LCKR_Register; + pragma Volatile_Full_Access (LCKR); -- GPIO alternate function low register - AFRL : AFRL_Register; + AFRL : aliased AFRL_Register; + pragma Volatile_Full_Access (AFRL); -- GPIO alternate function high register - AFRH : AFRH_Register; + AFRH : aliased AFRH_Register; + pragma Volatile_Full_Access (AFRH); end record with Volatile; for GPIO_Peripheral use record - MODER at 0 range 0 .. 31; - OTYPER at 4 range 0 .. 31; - OSPEEDR at 8 range 0 .. 31; - PUPDR at 12 range 0 .. 31; - IDR at 16 range 0 .. 31; - ODR at 20 range 0 .. 31; - BSRR at 24 range 0 .. 31; - LCKR at 28 range 0 .. 31; - AFRL at 32 range 0 .. 31; - AFRH at 36 range 0 .. 31; + MODER at 16#0# range 0 .. 31; + OTYPER at 16#4# range 0 .. 31; + OSPEEDR at 16#8# range 0 .. 31; + PUPDR at 16#C# range 0 .. 31; + IDR at 16#10# range 0 .. 31; + ODR at 16#14# range 0 .. 31; + BSRR at 16#18# range 0 .. 31; + LCKR at 16#1C# range 0 .. 31; + AFRL at 16#20# range 0 .. 31; + AFRH at 16#24# range 0 .. 31; end record; -- General-purpose I/Os diff --git a/stm32f4/stm32f40x/stm32f40x-i2c.ads b/stm32f4/stm32f40x/stm32f40x-i2c.ads index 2a3d673..3840a8d 100644 --- a/stm32f4/stm32f40x/stm32f40x-i2c.ads +++ b/stm32f4/stm32f40x/stm32f40x-i2c.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.I2C is -- Registers -- --------------- - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_PE_Field is STM32F40x.Bit; subtype CR1_SMBUS_Field is STM32F40x.Bit; subtype CR1_SMBTYPE_Field is STM32F40x.Bit; @@ -67,10 +64,9 @@ package STM32F40x.I2C is -- Software reset SWRST : CR1_SWRST_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record PE at 0 range 0 .. 0; @@ -92,10 +88,6 @@ package STM32F40x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_FREQ_Field is STM32F40x.UInt6; subtype CR2_ITERREN_Field is STM32F40x.Bit; subtype CR2_ITEVTEN_Field is STM32F40x.Bit; @@ -122,8 +114,7 @@ package STM32F40x.I2C is -- unspecified Reserved_13_31 : STM32F40x.UInt19 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record FREQ at 0 range 0 .. 5; @@ -136,10 +127,6 @@ package STM32F40x.I2C is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------- - -- OAR1_Register -- - ------------------- - subtype OAR1_ADD0_Field is STM32F40x.Bit; subtype OAR1_ADD7_Field is STM32F40x.UInt7; subtype OAR1_ADD10_Field is STM32F40x.UInt2; @@ -158,10 +145,9 @@ package STM32F40x.I2C is -- Addressing mode (slave mode) ADDMODE : OAR1_ADDMODE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OAR1_Register use record ADD0 at 0 range 0 .. 0; @@ -172,10 +158,6 @@ package STM32F40x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- OAR2_Register -- - ------------------- - subtype OAR2_ENDUAL_Field is STM32F40x.Bit; subtype OAR2_ADD2_Field is STM32F40x.UInt7; @@ -188,8 +170,7 @@ package STM32F40x.I2C is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OAR2_Register use record ENDUAL at 0 range 0 .. 0; @@ -197,10 +178,6 @@ package STM32F40x.I2C is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - subtype DR_DR_Field is STM32F40x.Byte; -- Data register @@ -210,18 +187,13 @@ package STM32F40x.I2C is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- SR1_Register -- - ------------------ - subtype SR1_SB_Field is STM32F40x.Bit; subtype SR1_ADDR_Field is STM32F40x.Bit; subtype SR1_BTF_Field is STM32F40x.Bit; @@ -272,10 +244,9 @@ package STM32F40x.I2C is -- SMBus alert SMBALERT : SR1_SMBALERT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR1_Register use record SB at 0 range 0 .. 0; @@ -297,10 +268,6 @@ package STM32F40x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- SR2_Register -- - ------------------ - subtype SR2_MSL_Field is STM32F40x.Bit; subtype SR2_BUSY_Field is STM32F40x.Bit; subtype SR2_TRA_Field is STM32F40x.Bit; @@ -313,28 +280,27 @@ package STM32F40x.I2C is -- Status register 2 type SR2_Register is record -- Read-only. Master/slave - MSL : SR2_MSL_Field := 16#0#; + MSL : SR2_MSL_Field; -- Read-only. Bus busy - BUSY : SR2_BUSY_Field := 16#0#; + BUSY : SR2_BUSY_Field; -- Read-only. Transmitter/receiver - TRA : SR2_TRA_Field := 16#0#; + TRA : SR2_TRA_Field; -- unspecified Reserved_3_3 : STM32F40x.Bit; -- Read-only. General call address (Slave mode) - GENCALL : SR2_GENCALL_Field := 16#0#; + GENCALL : SR2_GENCALL_Field; -- Read-only. SMBus device default address (Slave mode) - SMBDEFAULT : SR2_SMBDEFAULT_Field := 16#0#; + SMBDEFAULT : SR2_SMBDEFAULT_Field; -- Read-only. SMBus host header (Slave mode) - SMBHOST : SR2_SMBHOST_Field := 16#0#; + SMBHOST : SR2_SMBHOST_Field; -- Read-only. Dual flag (Slave mode) - DUALF : SR2_DUALF_Field := 16#0#; + DUALF : SR2_DUALF_Field; -- Read-only. acket error checking register - PEC : SR2_PEC_Field := 16#0#; + PEC : SR2_PEC_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR2_Register use record MSL at 0 range 0 .. 0; @@ -349,10 +315,6 @@ package STM32F40x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CCR_Register -- - ------------------ - subtype CCR_CCR_Field is STM32F40x.UInt12; subtype CCR_DUTY_Field is STM32F40x.Bit; subtype CCR_F_S_Field is STM32F40x.Bit; @@ -368,10 +330,9 @@ package STM32F40x.I2C is -- I2C master mode selection F_S : CCR_F_S_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCR_Register use record CCR at 0 range 0 .. 11; @@ -381,10 +342,6 @@ package STM32F40x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- TRISE_Register -- - -------------------- - subtype TRISE_TRISE_Field is STM32F40x.UInt6; -- TRISE register @@ -394,8 +351,7 @@ package STM32F40x.I2C is -- unspecified Reserved_6_31 : STM32F40x.UInt26 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TRISE_Register use record TRISE at 0 range 0 .. 5; @@ -409,36 +365,45 @@ package STM32F40x.I2C is -- Inter-integrated circuit type I2C_Peripheral is record -- Control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- Control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- Own address register 1 - OAR1 : OAR1_Register; + OAR1 : aliased OAR1_Register; + pragma Volatile_Full_Access (OAR1); -- Own address register 2 - OAR2 : OAR2_Register; + OAR2 : aliased OAR2_Register; + pragma Volatile_Full_Access (OAR2); -- Data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- Status register 1 - SR1 : SR1_Register; + SR1 : aliased SR1_Register; + pragma Volatile_Full_Access (SR1); -- Status register 2 - SR2 : SR2_Register; + SR2 : aliased SR2_Register; + pragma Volatile_Full_Access (SR2); -- Clock control register - CCR : CCR_Register; + CCR : aliased CCR_Register; + pragma Volatile_Full_Access (CCR); -- TRISE register - TRISE : TRISE_Register; + TRISE : aliased TRISE_Register; + pragma Volatile_Full_Access (TRISE); end record with Volatile; for I2C_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - OAR1 at 8 range 0 .. 31; - OAR2 at 12 range 0 .. 31; - DR at 16 range 0 .. 31; - SR1 at 20 range 0 .. 31; - SR2 at 24 range 0 .. 31; - CCR at 28 range 0 .. 31; - TRISE at 32 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + OAR1 at 16#8# range 0 .. 31; + OAR2 at 16#C# range 0 .. 31; + DR at 16#10# range 0 .. 31; + SR1 at 16#14# range 0 .. 31; + SR2 at 16#18# range 0 .. 31; + CCR at 16#1C# range 0 .. 31; + TRISE at 16#20# range 0 .. 31; end record; -- Inter-integrated circuit diff --git a/stm32f4/stm32f40x/stm32f40x-iwdg.ads b/stm32f4/stm32f40x/stm32f40x-iwdg.ads index bd94c42..3a9e0a3 100644 --- a/stm32f4/stm32f40x/stm32f40x-iwdg.ads +++ b/stm32f4/stm32f40x/stm32f40x-iwdg.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,31 +14,22 @@ package STM32F40x.IWDG is -- Registers -- --------------- - ----------------- - -- KR_Register -- - ----------------- - - subtype KR_KEY_Field is STM32F40x.Short; + subtype KR_KEY_Field is STM32F40x.UInt16; -- Key register type KR_Register is record -- Write-only. Key value (write only, read 0000h) KEY : KR_KEY_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for KR_Register use record KEY at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------- - -- PR_Register -- - ----------------- - subtype PR_PR_Field is STM32F40x.UInt3; -- Prescaler register @@ -47,18 +39,13 @@ package STM32F40x.IWDG is -- unspecified Reserved_3_31 : STM32F40x.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PR_Register use record PR at 0 range 0 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- RLR_Register -- - ------------------ - subtype RLR_RL_Field is STM32F40x.UInt12; -- Reload register @@ -68,32 +55,26 @@ package STM32F40x.IWDG is -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RLR_Register use record RL at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_PVU_Field is STM32F40x.Bit; subtype SR_RVU_Field is STM32F40x.Bit; -- Status register type SR_Register is record -- Read-only. Watchdog prescaler value update - PVU : SR_PVU_Field := 16#0#; + PVU : SR_PVU_Field; -- Read-only. Watchdog counter reload value update - RVU : SR_RVU_Field := 16#0#; + RVU : SR_RVU_Field; -- unspecified Reserved_2_31 : STM32F40x.UInt30; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record PVU at 0 range 0 .. 0; @@ -108,21 +89,25 @@ package STM32F40x.IWDG is -- Independent watchdog type IWDG_Peripheral is record -- Key register - KR : KR_Register; + KR : aliased KR_Register; + pragma Volatile_Full_Access (KR); -- Prescaler register - PR : PR_Register; + PR : aliased PR_Register; + pragma Volatile_Full_Access (PR); -- Reload register - RLR : RLR_Register; + RLR : aliased RLR_Register; + pragma Volatile_Full_Access (RLR); -- Status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; for IWDG_Peripheral use record - KR at 0 range 0 .. 31; - PR at 4 range 0 .. 31; - RLR at 8 range 0 .. 31; - SR at 12 range 0 .. 31; + KR at 16#0# range 0 .. 31; + PR at 16#4# range 0 .. 31; + RLR at 16#8# range 0 .. 31; + SR at 16#C# range 0 .. 31; end record; -- Independent watchdog diff --git a/stm32f4/stm32f40x/stm32f40x-nvic.ads b/stm32f4/stm32f40x/stm32f40x-nvic.ads index 94232c5..65e7d1a 100644 --- a/stm32f4/stm32f40x/stm32f40x-nvic.ads +++ b/stm32f4/stm32f40x/stm32f40x-nvic.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,36 +14,27 @@ package STM32F40x.NVIC is -- Registers -- --------------- - ------------------- - -- ICTR_Register -- - ------------------- - subtype ICTR_INTLINESNUM_Field is STM32F40x.UInt4; -- Interrupt Controller Type Register type ICTR_Register is record -- Read-only. Total number of interrupt lines in groups - INTLINESNUM : ICTR_INTLINESNUM_Field := 16#0#; + INTLINESNUM : ICTR_INTLINESNUM_Field; -- unspecified Reserved_4_31 : STM32F40x.UInt28; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ICTR_Register use record INTLINESNUM at 0 range 0 .. 3; Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------ - -- IPR_Register -- - ------------------ - - -- IPR0_IPR_N array element - subtype IPR0_IPR_N_Element is STM32F40x.Byte; + -- IPR_IPR_N array element + subtype IPR_IPR_N_Element is STM32F40x.Byte; - -- IPR0_IPR_N array - type IPR0_IPR_N_Field_Array is array (0 .. 3) of IPR0_IPR_N_Element + -- IPR_IPR_N array + type IPR_IPR_N_Field_Array is array (0 .. 3) of IPR_IPR_N_Element with Component_Size => 8, Size => 32; -- Interrupt Priority Register @@ -52,13 +44,13 @@ package STM32F40x.NVIC is case As_Array is when False => -- IPR_N as a value - Val : STM32F40x.Word; + Val : STM32F40x.UInt32; when True => -- IPR_N as an array - Arr : IPR0_IPR_N_Field_Array; + Arr : IPR_IPR_N_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for IPR_Register use record @@ -66,10 +58,6 @@ package STM32F40x.NVIC is Arr at 0 range 0 .. 31; end record; - ------------------- - -- STIR_Register -- - ------------------- - subtype STIR_INTID_Field is STM32F40x.UInt9; -- Software Triggered Interrupt Register @@ -79,8 +67,7 @@ package STM32F40x.NVIC is -- unspecified Reserved_9_31 : STM32F40x.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for STIR_Register use record INTID at 0 range 0 .. 8; @@ -94,120 +81,142 @@ package STM32F40x.NVIC is -- Nested Vectored Interrupt Controller type NVIC_Peripheral is record -- Interrupt Controller Type Register - ICTR : ICTR_Register; + ICTR : aliased ICTR_Register; + pragma Volatile_Full_Access (ICTR); -- Interrupt Set-Enable Register - ISER0 : STM32F40x.Word; + ISER0 : aliased STM32F40x.UInt32; -- Interrupt Set-Enable Register - ISER1 : STM32F40x.Word; + ISER1 : aliased STM32F40x.UInt32; -- Interrupt Set-Enable Register - ISER2 : STM32F40x.Word; + ISER2 : aliased STM32F40x.UInt32; -- Interrupt Clear-Enable Register - ICER0 : STM32F40x.Word; + ICER0 : aliased STM32F40x.UInt32; -- Interrupt Clear-Enable Register - ICER1 : STM32F40x.Word; + ICER1 : aliased STM32F40x.UInt32; -- Interrupt Clear-Enable Register - ICER2 : STM32F40x.Word; + ICER2 : aliased STM32F40x.UInt32; -- Interrupt Set-Pending Register - ISPR0 : STM32F40x.Word; + ISPR0 : aliased STM32F40x.UInt32; -- Interrupt Set-Pending Register - ISPR1 : STM32F40x.Word; + ISPR1 : aliased STM32F40x.UInt32; -- Interrupt Set-Pending Register - ISPR2 : STM32F40x.Word; + ISPR2 : aliased STM32F40x.UInt32; -- Interrupt Clear-Pending Register - ICPR0 : STM32F40x.Word; + ICPR0 : aliased STM32F40x.UInt32; -- Interrupt Clear-Pending Register - ICPR1 : STM32F40x.Word; + ICPR1 : aliased STM32F40x.UInt32; -- Interrupt Clear-Pending Register - ICPR2 : STM32F40x.Word; + ICPR2 : aliased STM32F40x.UInt32; -- Interrupt Active Bit Register - IABR0 : STM32F40x.Word; + IABR0 : aliased STM32F40x.UInt32; -- Interrupt Active Bit Register - IABR1 : STM32F40x.Word; + IABR1 : aliased STM32F40x.UInt32; -- Interrupt Active Bit Register - IABR2 : STM32F40x.Word; + IABR2 : aliased STM32F40x.UInt32; -- Interrupt Priority Register - IPR0 : IPR_Register; + IPR0 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR0); -- Interrupt Priority Register - IPR1 : IPR_Register; + IPR1 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR1); -- Interrupt Priority Register - IPR2 : IPR_Register; + IPR2 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR2); -- Interrupt Priority Register - IPR3 : IPR_Register; + IPR3 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR3); -- Interrupt Priority Register - IPR4 : IPR_Register; + IPR4 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR4); -- Interrupt Priority Register - IPR5 : IPR_Register; + IPR5 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR5); -- Interrupt Priority Register - IPR6 : IPR_Register; + IPR6 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR6); -- Interrupt Priority Register - IPR7 : IPR_Register; + IPR7 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR7); -- Interrupt Priority Register - IPR8 : IPR_Register; + IPR8 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR8); -- Interrupt Priority Register - IPR9 : IPR_Register; + IPR9 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR9); -- Interrupt Priority Register - IPR10 : IPR_Register; + IPR10 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR10); -- Interrupt Priority Register - IPR11 : IPR_Register; + IPR11 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR11); -- Interrupt Priority Register - IPR12 : IPR_Register; + IPR12 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR12); -- Interrupt Priority Register - IPR13 : IPR_Register; + IPR13 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR13); -- Interrupt Priority Register - IPR14 : IPR_Register; + IPR14 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR14); -- Interrupt Priority Register - IPR15 : IPR_Register; + IPR15 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR15); -- Interrupt Priority Register - IPR16 : IPR_Register; + IPR16 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR16); -- Interrupt Priority Register - IPR17 : IPR_Register; + IPR17 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR17); -- Interrupt Priority Register - IPR18 : IPR_Register; + IPR18 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR18); -- Interrupt Priority Register - IPR19 : IPR_Register; + IPR19 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR19); -- Software Triggered Interrupt Register - STIR : STIR_Register; + STIR : aliased STIR_Register; + pragma Volatile_Full_Access (STIR); end record with Volatile; for NVIC_Peripheral use record - ICTR at 4 range 0 .. 31; - ISER0 at 256 range 0 .. 31; - ISER1 at 260 range 0 .. 31; - ISER2 at 264 range 0 .. 31; - ICER0 at 384 range 0 .. 31; - ICER1 at 388 range 0 .. 31; - ICER2 at 392 range 0 .. 31; - ISPR0 at 512 range 0 .. 31; - ISPR1 at 516 range 0 .. 31; - ISPR2 at 520 range 0 .. 31; - ICPR0 at 640 range 0 .. 31; - ICPR1 at 644 range 0 .. 31; - ICPR2 at 648 range 0 .. 31; - IABR0 at 768 range 0 .. 31; - IABR1 at 772 range 0 .. 31; - IABR2 at 776 range 0 .. 31; - IPR0 at 1024 range 0 .. 31; - IPR1 at 1028 range 0 .. 31; - IPR2 at 1032 range 0 .. 31; - IPR3 at 1036 range 0 .. 31; - IPR4 at 1040 range 0 .. 31; - IPR5 at 1044 range 0 .. 31; - IPR6 at 1048 range 0 .. 31; - IPR7 at 1052 range 0 .. 31; - IPR8 at 1056 range 0 .. 31; - IPR9 at 1060 range 0 .. 31; - IPR10 at 1064 range 0 .. 31; - IPR11 at 1068 range 0 .. 31; - IPR12 at 1072 range 0 .. 31; - IPR13 at 1076 range 0 .. 31; - IPR14 at 1080 range 0 .. 31; - IPR15 at 1084 range 0 .. 31; - IPR16 at 1088 range 0 .. 31; - IPR17 at 1092 range 0 .. 31; - IPR18 at 1096 range 0 .. 31; - IPR19 at 1100 range 0 .. 31; - STIR at 3840 range 0 .. 31; + ICTR at 16#4# range 0 .. 31; + ISER0 at 16#100# range 0 .. 31; + ISER1 at 16#104# range 0 .. 31; + ISER2 at 16#108# range 0 .. 31; + ICER0 at 16#180# range 0 .. 31; + ICER1 at 16#184# range 0 .. 31; + ICER2 at 16#188# range 0 .. 31; + ISPR0 at 16#200# range 0 .. 31; + ISPR1 at 16#204# range 0 .. 31; + ISPR2 at 16#208# range 0 .. 31; + ICPR0 at 16#280# range 0 .. 31; + ICPR1 at 16#284# range 0 .. 31; + ICPR2 at 16#288# range 0 .. 31; + IABR0 at 16#300# range 0 .. 31; + IABR1 at 16#304# range 0 .. 31; + IABR2 at 16#308# range 0 .. 31; + IPR0 at 16#400# range 0 .. 31; + IPR1 at 16#404# range 0 .. 31; + IPR2 at 16#408# range 0 .. 31; + IPR3 at 16#40C# range 0 .. 31; + IPR4 at 16#410# range 0 .. 31; + IPR5 at 16#414# range 0 .. 31; + IPR6 at 16#418# range 0 .. 31; + IPR7 at 16#41C# range 0 .. 31; + IPR8 at 16#420# range 0 .. 31; + IPR9 at 16#424# range 0 .. 31; + IPR10 at 16#428# range 0 .. 31; + IPR11 at 16#42C# range 0 .. 31; + IPR12 at 16#430# range 0 .. 31; + IPR13 at 16#434# range 0 .. 31; + IPR14 at 16#438# range 0 .. 31; + IPR15 at 16#43C# range 0 .. 31; + IPR16 at 16#440# range 0 .. 31; + IPR17 at 16#444# range 0 .. 31; + IPR18 at 16#448# range 0 .. 31; + IPR19 at 16#44C# range 0 .. 31; + STIR at 16#F00# range 0 .. 31; end record; -- Nested Vectored Interrupt Controller diff --git a/stm32f4/stm32f40x/stm32f40x-pwr.ads b/stm32f4/stm32f40x/stm32f40x-pwr.ads index 930742f..d6e4997 100644 --- a/stm32f4/stm32f40x/stm32f40x-pwr.ads +++ b/stm32f4/stm32f40x/stm32f40x-pwr.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.PWR is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_LPDS_Field is STM32F40x.Bit; subtype CR_PDDS_Field is STM32F40x.Bit; subtype CR_CWUF_Field is STM32F40x.Bit; @@ -52,8 +49,7 @@ package STM32F40x.PWR is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record LPDS at 0 range 0 .. 0; @@ -69,10 +65,6 @@ package STM32F40x.PWR is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------ - -- CSR_Register -- - ------------------ - subtype CSR_WUF_Field is STM32F40x.Bit; subtype CSR_SBF_Field is STM32F40x.Bit; subtype CSR_PVDO_Field is STM32F40x.Bit; @@ -104,8 +96,7 @@ package STM32F40x.PWR is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CSR_Register use record WUF at 0 range 0 .. 0; @@ -127,15 +118,17 @@ package STM32F40x.PWR is -- Power control type PWR_Peripheral is record -- power control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- power control/status register - CSR : CSR_Register; + CSR : aliased CSR_Register; + pragma Volatile_Full_Access (CSR); end record with Volatile; for PWR_Peripheral use record - CR at 0 range 0 .. 31; - CSR at 4 range 0 .. 31; + CR at 16#0# range 0 .. 31; + CSR at 16#4# range 0 .. 31; end record; -- Power control diff --git a/stm32f4/stm32f40x/stm32f40x-rcc.ads b/stm32f4/stm32f40x/stm32f40x-rcc.ads index 4f086f5..b5719c9 100644 --- a/stm32f4/stm32f40x/stm32f40x-rcc.ads +++ b/stm32f4/stm32f40x/stm32f40x-rcc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.RCC is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_HSION_Field is STM32F40x.Bit; subtype CR_HSIRDY_Field is STM32F40x.Bit; subtype CR_HSITRIM_Field is STM32F40x.UInt5; @@ -63,8 +60,7 @@ package STM32F40x.RCC is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record HSION at 0 range 0 .. 0; @@ -84,10 +80,6 @@ package STM32F40x.RCC is Reserved_28_31 at 0 range 28 .. 31; end record; - ---------------------- - -- PLLCFGR_Register -- - ---------------------- - subtype PLLCFGR_PLLM_Field is STM32F40x.UInt6; subtype PLLCFGR_PLLN_Field is STM32F40x.UInt9; subtype PLLCFGR_PLLP_Field is STM32F40x.UInt2; @@ -117,8 +109,7 @@ package STM32F40x.RCC is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#2#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PLLCFGR_Register use record PLLM at 0 range 0 .. 5; @@ -132,18 +123,9 @@ package STM32F40x.RCC is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- CFGR_Register -- - ------------------- - subtype CFGR_SW_Field is STM32F40x.UInt2; subtype CFGR_SWS_Field is STM32F40x.UInt2; subtype CFGR_HPRE_Field is STM32F40x.UInt4; - - --------------- - -- CFGR.PPRE -- - --------------- - -- CFGR_PPRE array element subtype CFGR_PPRE_Element is STM32F40x.UInt3; @@ -203,8 +185,7 @@ package STM32F40x.RCC is -- Microcontroller clock output 2 MCO2 : CFGR_MCO2_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CFGR_Register use record SW at 0 range 0 .. 1; @@ -220,10 +201,6 @@ package STM32F40x.RCC is MCO2 at 0 range 30 .. 31; end record; - ------------------ - -- CIR_Register -- - ------------------ - subtype CIR_LSIRDYF_Field is STM32F40x.Bit; subtype CIR_LSERDYF_Field is STM32F40x.Bit; subtype CIR_HSIRDYF_Field is STM32F40x.Bit; @@ -296,8 +273,7 @@ package STM32F40x.RCC is -- unspecified Reserved_24_31 : STM32F40x.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CIR_Register use record LSIRDYF at 0 range 0 .. 0; @@ -326,10 +302,6 @@ package STM32F40x.RCC is Reserved_24_31 at 0 range 24 .. 31; end record; - ----------------------- - -- AHB1RSTR_Register -- - ----------------------- - subtype AHB1RSTR_GPIOARST_Field is STM32F40x.Bit; subtype AHB1RSTR_GPIOBRST_Field is STM32F40x.Bit; subtype AHB1RSTR_GPIOCRST_Field is STM32F40x.Bit; @@ -386,8 +358,7 @@ package STM32F40x.RCC is -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB1RSTR_Register use record GPIOARST at 0 range 0 .. 0; @@ -411,10 +382,6 @@ package STM32F40x.RCC is Reserved_30_31 at 0 range 30 .. 31; end record; - ----------------------- - -- AHB2RSTR_Register -- - ----------------------- - subtype AHB2RSTR_DCMIRST_Field is STM32F40x.Bit; subtype AHB2RSTR_RNGRST_Field is STM32F40x.Bit; subtype AHB2RSTR_OTGFSRST_Field is STM32F40x.Bit; @@ -432,8 +399,7 @@ package STM32F40x.RCC is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB2RSTR_Register use record DCMIRST at 0 range 0 .. 0; @@ -443,10 +409,6 @@ package STM32F40x.RCC is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------------- - -- AHB3RSTR_Register -- - ----------------------- - subtype AHB3RSTR_FSMCRST_Field is STM32F40x.Bit; -- AHB3 peripheral reset register @@ -456,18 +418,13 @@ package STM32F40x.RCC is -- unspecified Reserved_1_31 : STM32F40x.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB3RSTR_Register use record FSMCRST at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- APB1RSTR_Register -- - ----------------------- - subtype APB1RSTR_TIM2RST_Field is STM32F40x.Bit; subtype APB1RSTR_TIM3RST_Field is STM32F40x.Bit; subtype APB1RSTR_TIM4RST_Field is STM32F40x.Bit; @@ -553,8 +510,7 @@ package STM32F40x.RCC is -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB1RSTR_Register use record TIM2RST at 0 range 0 .. 0; @@ -588,10 +544,6 @@ package STM32F40x.RCC is Reserved_30_31 at 0 range 30 .. 31; end record; - ----------------------- - -- APB2RSTR_Register -- - ----------------------- - subtype APB2RSTR_TIM1RST_Field is STM32F40x.Bit; subtype APB2RSTR_TIM8RST_Field is STM32F40x.Bit; subtype APB2RSTR_USART1RST_Field is STM32F40x.Bit; @@ -641,8 +593,7 @@ package STM32F40x.RCC is -- unspecified Reserved_19_31 : STM32F40x.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB2RSTR_Register use record TIM1RST at 0 range 0 .. 0; @@ -664,10 +615,6 @@ package STM32F40x.RCC is Reserved_19_31 at 0 range 19 .. 31; end record; - ---------------------- - -- AHB1ENR_Register -- - ---------------------- - subtype AHB1ENR_GPIOAEN_Field is STM32F40x.Bit; subtype AHB1ENR_GPIOBEN_Field is STM32F40x.Bit; subtype AHB1ENR_GPIOCEN_Field is STM32F40x.Bit; @@ -739,8 +686,7 @@ package STM32F40x.RCC is -- unspecified Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB1ENR_Register use record GPIOAEN at 0 range 0 .. 0; @@ -769,10 +715,6 @@ package STM32F40x.RCC is Reserved_31_31 at 0 range 31 .. 31; end record; - ---------------------- - -- AHB2ENR_Register -- - ---------------------- - subtype AHB2ENR_DCMIEN_Field is STM32F40x.Bit; subtype AHB2ENR_RNGEN_Field is STM32F40x.Bit; subtype AHB2ENR_OTGFSEN_Field is STM32F40x.Bit; @@ -790,8 +732,7 @@ package STM32F40x.RCC is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB2ENR_Register use record DCMIEN at 0 range 0 .. 0; @@ -801,10 +742,6 @@ package STM32F40x.RCC is Reserved_8_31 at 0 range 8 .. 31; end record; - ---------------------- - -- AHB3ENR_Register -- - ---------------------- - subtype AHB3ENR_FSMCEN_Field is STM32F40x.Bit; -- AHB3 peripheral clock enable register @@ -814,18 +751,13 @@ package STM32F40x.RCC is -- unspecified Reserved_1_31 : STM32F40x.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB3ENR_Register use record FSMCEN at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ---------------------- - -- APB1ENR_Register -- - ---------------------- - subtype APB1ENR_TIM2EN_Field is STM32F40x.Bit; subtype APB1ENR_TIM3EN_Field is STM32F40x.Bit; subtype APB1ENR_TIM4EN_Field is STM32F40x.Bit; @@ -911,8 +843,7 @@ package STM32F40x.RCC is -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB1ENR_Register use record TIM2EN at 0 range 0 .. 0; @@ -946,10 +877,6 @@ package STM32F40x.RCC is Reserved_30_31 at 0 range 30 .. 31; end record; - ---------------------- - -- APB2ENR_Register -- - ---------------------- - subtype APB2ENR_TIM1EN_Field is STM32F40x.Bit; subtype APB2ENR_TIM8EN_Field is STM32F40x.Bit; subtype APB2ENR_USART1EN_Field is STM32F40x.Bit; @@ -1003,8 +930,7 @@ package STM32F40x.RCC is -- unspecified Reserved_19_31 : STM32F40x.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB2ENR_Register use record TIM1EN at 0 range 0 .. 0; @@ -1027,10 +953,6 @@ package STM32F40x.RCC is Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------------ - -- AHB1LPENR_Register -- - ------------------------ - subtype AHB1LPENR_GPIOALPEN_Field is STM32F40x.Bit; subtype AHB1LPENR_GPIOBLPEN_Field is STM32F40x.Bit; subtype AHB1LPENR_GPIOCLPEN_Field is STM32F40x.Bit; @@ -1111,8 +1033,7 @@ package STM32F40x.RCC is -- unspecified Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB1LPENR_Register use record GPIOALPEN at 0 range 0 .. 0; @@ -1144,10 +1065,6 @@ package STM32F40x.RCC is Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------ - -- AHB2LPENR_Register -- - ------------------------ - subtype AHB2LPENR_DCMILPEN_Field is STM32F40x.Bit; subtype AHB2LPENR_RNGLPEN_Field is STM32F40x.Bit; subtype AHB2LPENR_OTGFSLPEN_Field is STM32F40x.Bit; @@ -1165,8 +1082,7 @@ package STM32F40x.RCC is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB2LPENR_Register use record DCMILPEN at 0 range 0 .. 0; @@ -1176,10 +1092,6 @@ package STM32F40x.RCC is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------------ - -- AHB3LPENR_Register -- - ------------------------ - subtype AHB3LPENR_FSMCLPEN_Field is STM32F40x.Bit; -- AHB3 peripheral clock enable in low power mode register @@ -1190,18 +1102,13 @@ package STM32F40x.RCC is -- unspecified Reserved_1_31 : STM32F40x.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB3LPENR_Register use record FSMCLPEN at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- APB1LPENR_Register -- - ------------------------ - subtype APB1LPENR_TIM2LPEN_Field is STM32F40x.Bit; subtype APB1LPENR_TIM3LPEN_Field is STM32F40x.Bit; subtype APB1LPENR_TIM4LPEN_Field is STM32F40x.Bit; @@ -1287,8 +1194,7 @@ package STM32F40x.RCC is -- unspecified Reserved_30_31 : STM32F40x.UInt2 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB1LPENR_Register use record TIM2LPEN at 0 range 0 .. 0; @@ -1322,10 +1228,6 @@ package STM32F40x.RCC is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------------ - -- APB2LPENR_Register -- - ------------------------ - subtype APB2LPENR_TIM1LPEN_Field is STM32F40x.Bit; subtype APB2LPENR_TIM8LPEN_Field is STM32F40x.Bit; subtype APB2LPENR_USART1LPEN_Field is STM32F40x.Bit; @@ -1379,8 +1281,7 @@ package STM32F40x.RCC is -- unspecified Reserved_19_31 : STM32F40x.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB2LPENR_Register use record TIM1LPEN at 0 range 0 .. 0; @@ -1403,18 +1304,9 @@ package STM32F40x.RCC is Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------- - -- BDCR_Register -- - ------------------- - subtype BDCR_LSEON_Field is STM32F40x.Bit; subtype BDCR_LSERDY_Field is STM32F40x.Bit; subtype BDCR_LSEBYP_Field is STM32F40x.Bit; - - ----------------- - -- BDCR.RTCSEL -- - ----------------- - -- BDCR_RTCSEL array element subtype BDCR_RTCSEL_Element is STM32F40x.Bit; @@ -1466,8 +1358,7 @@ package STM32F40x.RCC is -- unspecified Reserved_17_31 : STM32F40x.UInt15 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BDCR_Register use record LSEON at 0 range 0 .. 0; @@ -1481,10 +1372,6 @@ package STM32F40x.RCC is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------ - -- CSR_Register -- - ------------------ - subtype CSR_LSION_Field is STM32F40x.Bit; subtype CSR_LSIRDY_Field is STM32F40x.Bit; subtype CSR_RMVF_Field is STM32F40x.Bit; @@ -1521,8 +1408,7 @@ package STM32F40x.RCC is -- Low-power reset flag LPWRRSTF : CSR_LPWRRSTF_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CSR_Register use record LSION at 0 range 0 .. 0; @@ -1538,10 +1424,6 @@ package STM32F40x.RCC is LPWRRSTF at 0 range 31 .. 31; end record; - -------------------- - -- SSCGR_Register -- - -------------------- - subtype SSCGR_MODPER_Field is STM32F40x.UInt13; subtype SSCGR_INCSTEP_Field is STM32F40x.UInt15; subtype SSCGR_SPREADSEL_Field is STM32F40x.Bit; @@ -1560,8 +1442,7 @@ package STM32F40x.RCC is -- Spread spectrum modulation enable SSCGEN : SSCGR_SSCGEN_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SSCGR_Register use record MODPER at 0 range 0 .. 12; @@ -1571,10 +1452,6 @@ package STM32F40x.RCC is SSCGEN at 0 range 31 .. 31; end record; - ------------------------- - -- PLLI2SCFGR_Register -- - ------------------------- - subtype PLLI2SCFGR_PLLI2SNx_Field is STM32F40x.UInt9; subtype PLLI2SCFGR_PLLI2SRx_Field is STM32F40x.UInt3; @@ -1591,8 +1468,7 @@ package STM32F40x.RCC is -- unspecified Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PLLI2SCFGR_Register use record Reserved_0_5 at 0 range 0 .. 5; @@ -1609,78 +1485,101 @@ package STM32F40x.RCC is -- Reset and clock control type RCC_Peripheral is record -- clock control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- PLL configuration register - PLLCFGR : PLLCFGR_Register; + PLLCFGR : aliased PLLCFGR_Register; + pragma Volatile_Full_Access (PLLCFGR); -- clock configuration register - CFGR : CFGR_Register; + CFGR : aliased CFGR_Register; + pragma Volatile_Full_Access (CFGR); -- clock interrupt register - CIR : CIR_Register; + CIR : aliased CIR_Register; + pragma Volatile_Full_Access (CIR); -- AHB1 peripheral reset register - AHB1RSTR : AHB1RSTR_Register; + AHB1RSTR : aliased AHB1RSTR_Register; + pragma Volatile_Full_Access (AHB1RSTR); -- AHB2 peripheral reset register - AHB2RSTR : AHB2RSTR_Register; + AHB2RSTR : aliased AHB2RSTR_Register; + pragma Volatile_Full_Access (AHB2RSTR); -- AHB3 peripheral reset register - AHB3RSTR : AHB3RSTR_Register; + AHB3RSTR : aliased AHB3RSTR_Register; + pragma Volatile_Full_Access (AHB3RSTR); -- APB1 peripheral reset register - APB1RSTR : APB1RSTR_Register; + APB1RSTR : aliased APB1RSTR_Register; + pragma Volatile_Full_Access (APB1RSTR); -- APB2 peripheral reset register - APB2RSTR : APB2RSTR_Register; + APB2RSTR : aliased APB2RSTR_Register; + pragma Volatile_Full_Access (APB2RSTR); -- AHB1 peripheral clock register - AHB1ENR : AHB1ENR_Register; + AHB1ENR : aliased AHB1ENR_Register; + pragma Volatile_Full_Access (AHB1ENR); -- AHB2 peripheral clock enable register - AHB2ENR : AHB2ENR_Register; + AHB2ENR : aliased AHB2ENR_Register; + pragma Volatile_Full_Access (AHB2ENR); -- AHB3 peripheral clock enable register - AHB3ENR : AHB3ENR_Register; + AHB3ENR : aliased AHB3ENR_Register; + pragma Volatile_Full_Access (AHB3ENR); -- APB1 peripheral clock enable register - APB1ENR : APB1ENR_Register; + APB1ENR : aliased APB1ENR_Register; + pragma Volatile_Full_Access (APB1ENR); -- APB2 peripheral clock enable register - APB2ENR : APB2ENR_Register; + APB2ENR : aliased APB2ENR_Register; + pragma Volatile_Full_Access (APB2ENR); -- AHB1 peripheral clock enable in low power mode register - AHB1LPENR : AHB1LPENR_Register; + AHB1LPENR : aliased AHB1LPENR_Register; + pragma Volatile_Full_Access (AHB1LPENR); -- AHB2 peripheral clock enable in low power mode register - AHB2LPENR : AHB2LPENR_Register; + AHB2LPENR : aliased AHB2LPENR_Register; + pragma Volatile_Full_Access (AHB2LPENR); -- AHB3 peripheral clock enable in low power mode register - AHB3LPENR : AHB3LPENR_Register; + AHB3LPENR : aliased AHB3LPENR_Register; + pragma Volatile_Full_Access (AHB3LPENR); -- APB1 peripheral clock enable in low power mode register - APB1LPENR : APB1LPENR_Register; + APB1LPENR : aliased APB1LPENR_Register; + pragma Volatile_Full_Access (APB1LPENR); -- APB2 peripheral clock enabled in low power mode register - APB2LPENR : APB2LPENR_Register; + APB2LPENR : aliased APB2LPENR_Register; + pragma Volatile_Full_Access (APB2LPENR); -- Backup domain control register - BDCR : BDCR_Register; + BDCR : aliased BDCR_Register; + pragma Volatile_Full_Access (BDCR); -- clock control & status register - CSR : CSR_Register; + CSR : aliased CSR_Register; + pragma Volatile_Full_Access (CSR); -- spread spectrum clock generation register - SSCGR : SSCGR_Register; + SSCGR : aliased SSCGR_Register; + pragma Volatile_Full_Access (SSCGR); -- PLLI2S configuration register - PLLI2SCFGR : PLLI2SCFGR_Register; + PLLI2SCFGR : aliased PLLI2SCFGR_Register; + pragma Volatile_Full_Access (PLLI2SCFGR); end record with Volatile; for RCC_Peripheral use record - CR at 0 range 0 .. 31; - PLLCFGR at 4 range 0 .. 31; - CFGR at 8 range 0 .. 31; - CIR at 12 range 0 .. 31; - AHB1RSTR at 16 range 0 .. 31; - AHB2RSTR at 20 range 0 .. 31; - AHB3RSTR at 24 range 0 .. 31; - APB1RSTR at 32 range 0 .. 31; - APB2RSTR at 36 range 0 .. 31; - AHB1ENR at 48 range 0 .. 31; - AHB2ENR at 52 range 0 .. 31; - AHB3ENR at 56 range 0 .. 31; - APB1ENR at 64 range 0 .. 31; - APB2ENR at 68 range 0 .. 31; - AHB1LPENR at 80 range 0 .. 31; - AHB2LPENR at 84 range 0 .. 31; - AHB3LPENR at 88 range 0 .. 31; - APB1LPENR at 96 range 0 .. 31; - APB2LPENR at 100 range 0 .. 31; - BDCR at 112 range 0 .. 31; - CSR at 116 range 0 .. 31; - SSCGR at 128 range 0 .. 31; - PLLI2SCFGR at 132 range 0 .. 31; + CR at 16#0# range 0 .. 31; + PLLCFGR at 16#4# range 0 .. 31; + CFGR at 16#8# range 0 .. 31; + CIR at 16#C# range 0 .. 31; + AHB1RSTR at 16#10# range 0 .. 31; + AHB2RSTR at 16#14# range 0 .. 31; + AHB3RSTR at 16#18# range 0 .. 31; + APB1RSTR at 16#20# range 0 .. 31; + APB2RSTR at 16#24# range 0 .. 31; + AHB1ENR at 16#30# range 0 .. 31; + AHB2ENR at 16#34# range 0 .. 31; + AHB3ENR at 16#38# range 0 .. 31; + APB1ENR at 16#40# range 0 .. 31; + APB2ENR at 16#44# range 0 .. 31; + AHB1LPENR at 16#50# range 0 .. 31; + AHB2LPENR at 16#54# range 0 .. 31; + AHB3LPENR at 16#58# range 0 .. 31; + APB1LPENR at 16#60# range 0 .. 31; + APB2LPENR at 16#64# range 0 .. 31; + BDCR at 16#70# range 0 .. 31; + CSR at 16#74# range 0 .. 31; + SSCGR at 16#80# range 0 .. 31; + PLLI2SCFGR at 16#84# range 0 .. 31; end record; -- Reset and clock control diff --git a/stm32f4/stm32f40x/stm32f40x-rng.ads b/stm32f4/stm32f40x/stm32f40x-rng.ads index c377663..863428e 100644 --- a/stm32f4/stm32f40x/stm32f40x-rng.ads +++ b/stm32f4/stm32f40x/stm32f40x-rng.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.RNG is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_RNGEN_Field is STM32F40x.Bit; subtype CR_IE_Field is STM32F40x.Bit; @@ -31,8 +28,7 @@ package STM32F40x.RNG is -- unspecified Reserved_4_31 : STM32F40x.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record Reserved_0_1 at 0 range 0 .. 1; @@ -41,10 +37,6 @@ package STM32F40x.RNG is Reserved_4_31 at 0 range 4 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_DRDY_Field is STM32F40x.Bit; subtype SR_CECS_Field is STM32F40x.Bit; subtype SR_SECS_Field is STM32F40x.Bit; @@ -68,8 +60,7 @@ package STM32F40x.RNG is -- unspecified Reserved_7_31 : STM32F40x.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record DRDY at 0 range 0 .. 0; @@ -88,18 +79,20 @@ package STM32F40x.RNG is -- Random number generator type RNG_Peripheral is record -- control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- data register - DR : STM32F40x.Word; + DR : aliased STM32F40x.UInt32; end record with Volatile; for RNG_Peripheral use record - CR at 0 range 0 .. 31; - SR at 4 range 0 .. 31; - DR at 8 range 0 .. 31; + CR at 16#0# range 0 .. 31; + SR at 16#4# range 0 .. 31; + DR at 16#8# range 0 .. 31; end record; -- Random number generator diff --git a/stm32f4/stm32f40x/stm32f40x-rtc.ads b/stm32f4/stm32f40x/stm32f40x-rtc.ads index 079bf88..83c98d8 100644 --- a/stm32f4/stm32f40x/stm32f40x-rtc.ads +++ b/stm32f4/stm32f40x/stm32f40x-rtc.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.RTC is -- Registers -- --------------- - ----------------- - -- TR_Register -- - ----------------- - subtype TR_SU_Field is STM32F40x.UInt4; subtype TR_ST_Field is STM32F40x.UInt3; subtype TR_MNU_Field is STM32F40x.UInt4; @@ -48,8 +45,7 @@ package STM32F40x.RTC is -- unspecified Reserved_23_31 : STM32F40x.UInt9 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TR_Register use record SU at 0 range 0 .. 3; @@ -64,10 +60,6 @@ package STM32F40x.RTC is Reserved_23_31 at 0 range 23 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - subtype DR_DU_Field is STM32F40x.UInt4; subtype DR_DT_Field is STM32F40x.UInt2; subtype DR_MU_Field is STM32F40x.UInt4; @@ -97,8 +89,7 @@ package STM32F40x.RTC is -- unspecified Reserved_24_31 : STM32F40x.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DU at 0 range 0 .. 3; @@ -112,10 +103,6 @@ package STM32F40x.RTC is Reserved_24_31 at 0 range 24 .. 31; end record; - ----------------- - -- CR_Register -- - ----------------- - subtype CR_WCKSEL_Field is STM32F40x.UInt3; subtype CR_TSEDGE_Field is STM32F40x.Bit; subtype CR_REFCKON_Field is STM32F40x.Bit; @@ -183,8 +170,7 @@ package STM32F40x.RTC is -- unspecified Reserved_24_31 : STM32F40x.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record WCKSEL at 0 range 0 .. 2; @@ -211,10 +197,6 @@ package STM32F40x.RTC is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ - subtype ISR_ALRAWF_Field is STM32F40x.Bit; subtype ISR_ALRBWF_Field is STM32F40x.Bit; subtype ISR_WUTWF_Field is STM32F40x.Bit; @@ -271,8 +253,7 @@ package STM32F40x.RTC is -- unspecified Reserved_17_31 : STM32F40x.UInt15 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ISR_Register use record ALRAWF at 0 range 0 .. 0; @@ -295,10 +276,6 @@ package STM32F40x.RTC is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------- - -- PRER_Register -- - ------------------- - subtype PRER_PREDIV_S_Field is STM32F40x.UInt15; subtype PRER_PREDIV_A_Field is STM32F40x.UInt7; @@ -313,8 +290,7 @@ package STM32F40x.RTC is -- unspecified Reserved_23_31 : STM32F40x.UInt9 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PRER_Register use record PREDIV_S at 0 range 0 .. 14; @@ -323,31 +299,22 @@ package STM32F40x.RTC is Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- WUTR_Register -- - ------------------- - - subtype WUTR_WUT_Field is STM32F40x.Short; + subtype WUTR_WUT_Field is STM32F40x.UInt16; -- wakeup timer register type WUTR_Register is record -- Wakeup auto-reload value bits WUT : WUTR_WUT_Field := 16#FFFF#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for WUTR_Register use record WUT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- CALIBR_Register -- - --------------------- - subtype CALIBR_DC_Field is STM32F40x.UInt5; subtype CALIBR_DCS_Field is STM32F40x.Bit; @@ -362,8 +329,7 @@ package STM32F40x.RTC is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CALIBR_Register use record DC at 0 range 0 .. 4; @@ -372,10 +338,6 @@ package STM32F40x.RTC is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- ALRMAR_Register -- - --------------------- - subtype ALRMAR_SU_Field is STM32F40x.UInt4; subtype ALRMAR_ST_Field is STM32F40x.UInt3; subtype ALRMAR_MSK1_Field is STM32F40x.Bit; @@ -422,8 +384,7 @@ package STM32F40x.RTC is -- Alarm A date mask MSK4 : ALRMAR_MSK4_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ALRMAR_Register use record SU at 0 range 0 .. 3; @@ -442,10 +403,6 @@ package STM32F40x.RTC is MSK4 at 0 range 31 .. 31; end record; - --------------------- - -- ALRMBR_Register -- - --------------------- - subtype ALRMBR_SU_Field is STM32F40x.UInt4; subtype ALRMBR_ST_Field is STM32F40x.UInt3; subtype ALRMBR_MSK1_Field is STM32F40x.Bit; @@ -492,8 +449,7 @@ package STM32F40x.RTC is -- Alarm B date mask MSK4 : ALRMBR_MSK4_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ALRMBR_Register use record SU at 0 range 0 .. 3; @@ -512,10 +468,6 @@ package STM32F40x.RTC is MSK4 at 0 range 31 .. 31; end record; - ------------------ - -- WPR_Register -- - ------------------ - subtype WPR_KEY_Field is STM32F40x.Byte; -- write protection register @@ -525,39 +477,29 @@ package STM32F40x.RTC is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for WPR_Register use record KEY at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- SSR_Register -- - ------------------ - - subtype SSR_SS_Field is STM32F40x.Short; + subtype SSR_SS_Field is STM32F40x.UInt16; -- sub second register type SSR_Register is record -- Read-only. Sub second value - SS : SSR_SS_Field := 16#0#; + SS : SSR_SS_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SSR_Register use record SS at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- SHIFTR_Register -- - --------------------- - subtype SHIFTR_SUBFS_Field is STM32F40x.UInt15; subtype SHIFTR_ADD1S_Field is STM32F40x.Bit; @@ -566,12 +508,11 @@ package STM32F40x.RTC is -- Write-only. Subtract a fraction of a second SUBFS : SHIFTR_SUBFS_Field := 16#0#; -- unspecified - Reserved_15_30 : STM32F40x.Short := 16#0#; + Reserved_15_30 : STM32F40x.UInt16 := 16#0#; -- Write-only. Add one second ADD1S : SHIFTR_ADD1S_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SHIFTR_Register use record SUBFS at 0 range 0 .. 14; @@ -579,10 +520,6 @@ package STM32F40x.RTC is ADD1S at 0 range 31 .. 31; end record; - ------------------- - -- TSTR_Register -- - ------------------- - subtype TSTR_TAMP1E_Field is STM32F40x.Bit; subtype TSTR_TAMP1TRG_Field is STM32F40x.Bit; subtype TSTR_TAMPIE_Field is STM32F40x.Bit; @@ -593,24 +530,23 @@ package STM32F40x.RTC is -- time stamp time register type TSTR_Register is record -- Read-only. Tamper 1 detection enable - TAMP1E : TSTR_TAMP1E_Field := 16#0#; + TAMP1E : TSTR_TAMP1E_Field; -- Read-only. Active level for tamper 1 - TAMP1TRG : TSTR_TAMP1TRG_Field := 16#0#; + TAMP1TRG : TSTR_TAMP1TRG_Field; -- Read-only. Tamper interrupt enable - TAMPIE : TSTR_TAMPIE_Field := 16#0#; + TAMPIE : TSTR_TAMPIE_Field; -- unspecified Reserved_3_15 : STM32F40x.UInt13; -- Read-only. TAMPER1 mapping - TAMP1INSEL : TSTR_TAMP1INSEL_Field := 16#0#; + TAMP1INSEL : TSTR_TAMP1INSEL_Field; -- Read-only. TIMESTAMP mapping - TSINSEL : TSTR_TSINSEL_Field := 16#0#; + TSINSEL : TSTR_TSINSEL_Field; -- Read-only. AFO_ALARM output type - ALARMOUTTYPE : TSTR_ALARMOUTTYPE_Field := 16#0#; + ALARMOUTTYPE : TSTR_ALARMOUTTYPE_Field; -- unspecified Reserved_19_31 : STM32F40x.UInt13; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TSTR_Register use record TAMP1E at 0 range 0 .. 0; @@ -623,10 +559,6 @@ package STM32F40x.RTC is Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------- - -- TSDR_Register -- - ------------------- - subtype TSDR_DU_Field is STM32F40x.UInt4; subtype TSDR_DT_Field is STM32F40x.UInt2; subtype TSDR_MU_Field is STM32F40x.UInt4; @@ -636,22 +568,21 @@ package STM32F40x.RTC is -- time stamp date register type TSDR_Register is record -- Read-only. Date units in BCD format - DU : TSDR_DU_Field := 16#0#; + DU : TSDR_DU_Field; -- Read-only. Date tens in BCD format - DT : TSDR_DT_Field := 16#0#; + DT : TSDR_DT_Field; -- unspecified Reserved_6_7 : STM32F40x.UInt2; -- Read-only. Month units in BCD format - MU : TSDR_MU_Field := 16#0#; + MU : TSDR_MU_Field; -- Read-only. Month tens in BCD format - MT : TSDR_MT_Field := 16#0#; + MT : TSDR_MT_Field; -- Read-only. Week day units - WDU : TSDR_WDU_Field := 16#0#; + WDU : TSDR_WDU_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TSDR_Register use record DU at 0 range 0 .. 3; @@ -663,64 +594,25 @@ package STM32F40x.RTC is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- TSSSR_Register -- - -------------------- - - subtype TSSSR_SS_Field is STM32F40x.Short; + subtype TSSSR_SS_Field is STM32F40x.UInt16; -- timestamp sub second register type TSSSR_Register is record -- Read-only. Sub second value - SS : TSSSR_SS_Field := 16#0#; + SS : TSSSR_SS_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TSSSR_Register use record SS at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- CALR_Register -- - ------------------- - subtype CALR_CALM_Field is STM32F40x.UInt9; - - --------------- - -- CALR.CALW -- - --------------- - - -- CALR_CALW array element - subtype CALR_CALW_Element is STM32F40x.Bit; - - -- CALR_CALW array - type CALR_CALW_Field_Array is array (8 .. 9) of CALR_CALW_Element - with Component_Size => 1, Size => 2; - - -- Type definition for CALR_CALW - type CALR_CALW_Field - (As_Array : Boolean := False) - is record - case As_Array is - when False => - -- CALW as a value - Val : STM32F40x.UInt2; - when True => - -- CALW as an array - Arr : CALR_CALW_Field_Array; - end case; - end record - with Unchecked_Union, Size => 2; - - for CALR_CALW_Field use record - Val at 0 range 0 .. 1; - Arr at 0 range 0 .. 1; - end record; - + subtype CALR_CALW16_Field is STM32F40x.Bit; + subtype CALR_CALW8_Field is STM32F40x.Bit; subtype CALR_CALP_Field is STM32F40x.Bit; -- calibration register @@ -730,27 +622,25 @@ package STM32F40x.RTC is -- unspecified Reserved_9_12 : STM32F40x.UInt4 := 16#0#; -- Use a 16-second calibration cycle period - CALW : CALR_CALW_Field := (As_Array => False, Val => 16#0#); + CALW16 : CALR_CALW16_Field := 16#0#; + -- Use an 8-second calibration cycle period + CALW8 : CALR_CALW8_Field := 16#0#; -- Increase frequency of RTC by 488.5 ppm CALP : CALR_CALP_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CALR_Register use record CALM at 0 range 0 .. 8; Reserved_9_12 at 0 range 9 .. 12; - CALW at 0 range 13 .. 14; + CALW16 at 0 range 13 .. 13; + CALW8 at 0 range 14 .. 14; CALP at 0 range 15 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- TAFCR_Register -- - -------------------- - subtype TAFCR_TAMP1E_Field is STM32F40x.Bit; subtype TAFCR_TAMP1TRG_Field is STM32F40x.Bit; subtype TAFCR_TAMPIE_Field is STM32F40x.Bit; @@ -798,8 +688,7 @@ package STM32F40x.RTC is -- unspecified Reserved_19_31 : STM32F40x.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TAFCR_Register use record TAMP1E at 0 range 0 .. 0; @@ -819,10 +708,6 @@ package STM32F40x.RTC is Reserved_19_31 at 0 range 19 .. 31; end record; - ----------------------- - -- ALRMASSR_Register -- - ----------------------- - subtype ALRMASSR_SS_Field is STM32F40x.UInt15; subtype ALRMASSR_MASKSS_Field is STM32F40x.UInt4; @@ -837,8 +722,7 @@ package STM32F40x.RTC is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ALRMASSR_Register use record SS at 0 range 0 .. 14; @@ -847,10 +731,6 @@ package STM32F40x.RTC is Reserved_28_31 at 0 range 28 .. 31; end record; - ----------------------- - -- ALRMBSSR_Register -- - ----------------------- - subtype ALRMBSSR_SS_Field is STM32F40x.UInt15; subtype ALRMBSSR_MASKSS_Field is STM32F40x.UInt4; @@ -865,8 +745,7 @@ package STM32F40x.RTC is -- unspecified Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ALRMBSSR_Register use record SS at 0 range 0 .. 14; @@ -882,126 +761,145 @@ package STM32F40x.RTC is -- Real-time clock type RTC_Peripheral is record -- time register - TR : TR_Register; + TR : aliased TR_Register; + pragma Volatile_Full_Access (TR); -- date register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- initialization and status register - ISR : ISR_Register; + ISR : aliased ISR_Register; + pragma Volatile_Full_Access (ISR); -- prescaler register - PRER : PRER_Register; + PRER : aliased PRER_Register; + pragma Volatile_Full_Access (PRER); -- wakeup timer register - WUTR : WUTR_Register; + WUTR : aliased WUTR_Register; + pragma Volatile_Full_Access (WUTR); -- calibration register - CALIBR : CALIBR_Register; + CALIBR : aliased CALIBR_Register; + pragma Volatile_Full_Access (CALIBR); -- alarm A register - ALRMAR : ALRMAR_Register; + ALRMAR : aliased ALRMAR_Register; + pragma Volatile_Full_Access (ALRMAR); -- alarm B register - ALRMBR : ALRMBR_Register; + ALRMBR : aliased ALRMBR_Register; + pragma Volatile_Full_Access (ALRMBR); -- write protection register - WPR : WPR_Register; + WPR : aliased WPR_Register; + pragma Volatile_Full_Access (WPR); -- sub second register - SSR : SSR_Register; + SSR : aliased SSR_Register; + pragma Volatile_Full_Access (SSR); -- shift control register - SHIFTR : SHIFTR_Register; + SHIFTR : aliased SHIFTR_Register; + pragma Volatile_Full_Access (SHIFTR); -- time stamp time register - TSTR : TSTR_Register; + TSTR : aliased TSTR_Register; + pragma Volatile_Full_Access (TSTR); -- time stamp date register - TSDR : TSDR_Register; + TSDR : aliased TSDR_Register; + pragma Volatile_Full_Access (TSDR); -- timestamp sub second register - TSSSR : TSSSR_Register; + TSSSR : aliased TSSSR_Register; + pragma Volatile_Full_Access (TSSSR); -- calibration register - CALR : CALR_Register; + CALR : aliased CALR_Register; + pragma Volatile_Full_Access (CALR); -- tamper and alternate function configuration register - TAFCR : TAFCR_Register; + TAFCR : aliased TAFCR_Register; + pragma Volatile_Full_Access (TAFCR); -- alarm A sub second register - ALRMASSR : ALRMASSR_Register; + ALRMASSR : aliased ALRMASSR_Register; + pragma Volatile_Full_Access (ALRMASSR); -- alarm B sub second register - ALRMBSSR : ALRMBSSR_Register; + ALRMBSSR : aliased ALRMBSSR_Register; + pragma Volatile_Full_Access (ALRMBSSR); -- backup register - BKP0R : STM32F40x.Word; + BKP0R : aliased STM32F40x.UInt32; -- backup register - BKP1R : STM32F40x.Word; + BKP1R : aliased STM32F40x.UInt32; -- backup register - BKP2R : STM32F40x.Word; + BKP2R : aliased STM32F40x.UInt32; -- backup register - BKP3R : STM32F40x.Word; + BKP3R : aliased STM32F40x.UInt32; -- backup register - BKP4R : STM32F40x.Word; + BKP4R : aliased STM32F40x.UInt32; -- backup register - BKP5R : STM32F40x.Word; + BKP5R : aliased STM32F40x.UInt32; -- backup register - BKP6R : STM32F40x.Word; + BKP6R : aliased STM32F40x.UInt32; -- backup register - BKP7R : STM32F40x.Word; + BKP7R : aliased STM32F40x.UInt32; -- backup register - BKP8R : STM32F40x.Word; + BKP8R : aliased STM32F40x.UInt32; -- backup register - BKP9R : STM32F40x.Word; + BKP9R : aliased STM32F40x.UInt32; -- backup register - BKP10R : STM32F40x.Word; + BKP10R : aliased STM32F40x.UInt32; -- backup register - BKP11R : STM32F40x.Word; + BKP11R : aliased STM32F40x.UInt32; -- backup register - BKP12R : STM32F40x.Word; + BKP12R : aliased STM32F40x.UInt32; -- backup register - BKP13R : STM32F40x.Word; + BKP13R : aliased STM32F40x.UInt32; -- backup register - BKP14R : STM32F40x.Word; + BKP14R : aliased STM32F40x.UInt32; -- backup register - BKP15R : STM32F40x.Word; + BKP15R : aliased STM32F40x.UInt32; -- backup register - BKP16R : STM32F40x.Word; + BKP16R : aliased STM32F40x.UInt32; -- backup register - BKP17R : STM32F40x.Word; + BKP17R : aliased STM32F40x.UInt32; -- backup register - BKP18R : STM32F40x.Word; + BKP18R : aliased STM32F40x.UInt32; -- backup register - BKP19R : STM32F40x.Word; + BKP19R : aliased STM32F40x.UInt32; end record with Volatile; for RTC_Peripheral use record - TR at 0 range 0 .. 31; - DR at 4 range 0 .. 31; - CR at 8 range 0 .. 31; - ISR at 12 range 0 .. 31; - PRER at 16 range 0 .. 31; - WUTR at 20 range 0 .. 31; - CALIBR at 24 range 0 .. 31; - ALRMAR at 28 range 0 .. 31; - ALRMBR at 32 range 0 .. 31; - WPR at 36 range 0 .. 31; - SSR at 40 range 0 .. 31; - SHIFTR at 44 range 0 .. 31; - TSTR at 48 range 0 .. 31; - TSDR at 52 range 0 .. 31; - TSSSR at 56 range 0 .. 31; - CALR at 60 range 0 .. 31; - TAFCR at 64 range 0 .. 31; - ALRMASSR at 68 range 0 .. 31; - ALRMBSSR at 72 range 0 .. 31; - BKP0R at 80 range 0 .. 31; - BKP1R at 84 range 0 .. 31; - BKP2R at 88 range 0 .. 31; - BKP3R at 92 range 0 .. 31; - BKP4R at 96 range 0 .. 31; - BKP5R at 100 range 0 .. 31; - BKP6R at 104 range 0 .. 31; - BKP7R at 108 range 0 .. 31; - BKP8R at 112 range 0 .. 31; - BKP9R at 116 range 0 .. 31; - BKP10R at 120 range 0 .. 31; - BKP11R at 124 range 0 .. 31; - BKP12R at 128 range 0 .. 31; - BKP13R at 132 range 0 .. 31; - BKP14R at 136 range 0 .. 31; - BKP15R at 140 range 0 .. 31; - BKP16R at 144 range 0 .. 31; - BKP17R at 148 range 0 .. 31; - BKP18R at 152 range 0 .. 31; - BKP19R at 156 range 0 .. 31; + TR at 16#0# range 0 .. 31; + DR at 16#4# range 0 .. 31; + CR at 16#8# range 0 .. 31; + ISR at 16#C# range 0 .. 31; + PRER at 16#10# range 0 .. 31; + WUTR at 16#14# range 0 .. 31; + CALIBR at 16#18# range 0 .. 31; + ALRMAR at 16#1C# range 0 .. 31; + ALRMBR at 16#20# range 0 .. 31; + WPR at 16#24# range 0 .. 31; + SSR at 16#28# range 0 .. 31; + SHIFTR at 16#2C# range 0 .. 31; + TSTR at 16#30# range 0 .. 31; + TSDR at 16#34# range 0 .. 31; + TSSSR at 16#38# range 0 .. 31; + CALR at 16#3C# range 0 .. 31; + TAFCR at 16#40# range 0 .. 31; + ALRMASSR at 16#44# range 0 .. 31; + ALRMBSSR at 16#48# range 0 .. 31; + BKP0R at 16#50# range 0 .. 31; + BKP1R at 16#54# range 0 .. 31; + BKP2R at 16#58# range 0 .. 31; + BKP3R at 16#5C# range 0 .. 31; + BKP4R at 16#60# range 0 .. 31; + BKP5R at 16#64# range 0 .. 31; + BKP6R at 16#68# range 0 .. 31; + BKP7R at 16#6C# range 0 .. 31; + BKP8R at 16#70# range 0 .. 31; + BKP9R at 16#74# range 0 .. 31; + BKP10R at 16#78# range 0 .. 31; + BKP11R at 16#7C# range 0 .. 31; + BKP12R at 16#80# range 0 .. 31; + BKP13R at 16#84# range 0 .. 31; + BKP14R at 16#88# range 0 .. 31; + BKP15R at 16#8C# range 0 .. 31; + BKP16R at 16#90# range 0 .. 31; + BKP17R at 16#94# range 0 .. 31; + BKP18R at 16#98# range 0 .. 31; + BKP19R at 16#9C# range 0 .. 31; end record; -- Real-time clock diff --git a/stm32f4/stm32f40x/stm32f40x-sdio.ads b/stm32f4/stm32f40x/stm32f40x-sdio.ads index b32fff1..4b6dfbd 100644 --- a/stm32f4/stm32f40x/stm32f40x-sdio.ads +++ b/stm32f4/stm32f40x/stm32f40x-sdio.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,37 +14,62 @@ package STM32F40x.SDIO is -- Registers -- --------------- - -------------------- - -- POWER_Register -- - -------------------- - - subtype POWER_PWRCTRL_Field is STM32F40x.UInt2; + -- PWRCTRL + type POWER_PWRCTRL_Field is + (-- The clock to card is stopped. + Power_Off, + -- The card is clocked. + Power_On) + with Size => 2; + for POWER_PWRCTRL_Field use + (Power_Off => 0, + Power_On => 3); -- power control register type POWER_Register is record -- PWRCTRL - PWRCTRL : POWER_PWRCTRL_Field := 16#0#; + PWRCTRL : POWER_PWRCTRL_Field := STM32F40x.SDIO.Power_Off; -- unspecified Reserved_2_31 : STM32F40x.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record PWRCTRL at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - -------------------- - -- CLKCR_Register -- - -------------------- - subtype CLKCR_CLKDIV_Field is STM32F40x.Byte; subtype CLKCR_CLKEN_Field is STM32F40x.Bit; subtype CLKCR_PWRSAV_Field is STM32F40x.Bit; subtype CLKCR_BYPASS_Field is STM32F40x.Bit; - subtype CLKCR_WIDBUS_Field is STM32F40x.UInt2; - subtype CLKCR_NEGEDGE_Field is STM32F40x.Bit; + + -- Wide bus mode enable bit + type CLKCR_WIDBUS_Field is + (-- Default bus mode: SDMMC_D0 is used. + Bus_Wide_1B, + -- 4-wide bus mode: SDMMC_D[3:0] used. + Bus_Wide_4B, + -- 8-wide bus mode: SDMMC_D[7:0] used. + Bus_Wide_8B) + with Size => 2; + for CLKCR_WIDBUS_Field use + (Bus_Wide_1B => 0, + Bus_Wide_4B => 1, + Bus_Wide_8B => 2); + + -- SDIO_CK dephasing selection bit + type CLKCR_NEGEDGE_Field is + (-- Cmd and Data changed on the SDMMCCLK falling edge succeeding the rising +-- edge of SDMMC_CK. + Edge_Rising, + -- Cmd and Data changed on the SDMMC_CK falling edge. + Edge_Falling) + with Size => 1; + for CLKCR_NEGEDGE_Field use + (Edge_Rising => 0, + Edge_Falling => 1); + subtype CLKCR_HWFC_EN_Field is STM32F40x.Bit; -- SDI clock control register @@ -57,16 +83,15 @@ package STM32F40x.SDIO is -- Clock divider bypass enable bit BYPASS : CLKCR_BYPASS_Field := 16#0#; -- Wide bus mode enable bit - WIDBUS : CLKCR_WIDBUS_Field := 16#0#; + WIDBUS : CLKCR_WIDBUS_Field := STM32F40x.SDIO.Bus_Wide_1B; -- SDIO_CK dephasing selection bit - NEGEDGE : CLKCR_NEGEDGE_Field := 16#0#; + NEGEDGE : CLKCR_NEGEDGE_Field := STM32F40x.SDIO.Edge_Rising; -- HW Flow Control enable HWFC_EN : CLKCR_HWFC_EN_Field := 16#0#; -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CLKCR_Register use record CLKDIV at 0 range 0 .. 7; @@ -79,12 +104,22 @@ package STM32F40x.SDIO is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------ - -- CMD_Register -- - ------------------ - subtype CMD_CMDINDEX_Field is STM32F40x.UInt6; - subtype CMD_WAITRESP_Field is STM32F40x.UInt2; + + -- Wait for response bits + type CMD_WAITRESP_Field is + (-- No response, expect CMDSENT flag. + No_Response, + -- Short response, expect CMDREND or CCRCFAIL flag. + Short_Response, + -- Long response, expect CMDREND or CCRCFAIL flag. + Long_Response) + with Size => 2; + for CMD_WAITRESP_Field use + (No_Response => 0, + Short_Response => 1, + Long_Response => 3); + subtype CMD_WAITINT_Field is STM32F40x.Bit; subtype CMD_WAITPEND_Field is STM32F40x.Bit; subtype CMD_CPSMEN_Field is STM32F40x.Bit; @@ -98,7 +133,7 @@ package STM32F40x.SDIO is -- Command index CMDINDEX : CMD_CMDINDEX_Field := 16#0#; -- Wait for response bits - WAITRESP : CMD_WAITRESP_Field := 16#0#; + WAITRESP : CMD_WAITRESP_Field := STM32F40x.SDIO.No_Response; -- CPSM waits for interrupt request WAITINT : CMD_WAITINT_Field := 16#0#; -- CPSM Waits for ends of data transfer (CmdPend internal signal). @@ -116,8 +151,7 @@ package STM32F40x.SDIO is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMD_Register use record CMDINDEX at 0 range 0 .. 5; @@ -132,31 +166,22 @@ package STM32F40x.SDIO is Reserved_15_31 at 0 range 15 .. 31; end record; - ---------------------- - -- RESPCMD_Register -- - ---------------------- - subtype RESPCMD_RESPCMD_Field is STM32F40x.UInt6; -- command response register type RESPCMD_Register is record -- Read-only. Response command index - RESPCMD : RESPCMD_RESPCMD_Field := 16#0#; + RESPCMD : RESPCMD_RESPCMD_Field; -- unspecified Reserved_6_31 : STM32F40x.UInt26; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RESPCMD_Register use record RESPCMD at 0 range 0 .. 5; Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------- - -- DLEN_Register -- - ------------------- - subtype DLEN_DATALENGTH_Field is STM32F40x.UInt25; -- data length register @@ -166,23 +191,89 @@ package STM32F40x.SDIO is -- unspecified Reserved_25_31 : STM32F40x.UInt7 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DLEN_Register use record DATALENGTH at 0 range 0 .. 24; Reserved_25_31 at 0 range 25 .. 31; end record; - -------------------- - -- DCTRL_Register -- - -------------------- - subtype DCTRL_DTEN_Field is STM32F40x.Bit; - subtype DCTRL_DTDIR_Field is STM32F40x.Bit; - subtype DCTRL_DTMODE_Field is STM32F40x.Bit; + + -- Data transfer direction selection + type DCTRL_DTDIR_Field is + (-- Data is sent to the card + Controller_To_Card, + -- Data is read from the card + Card_To_Controller) + with Size => 1; + for DCTRL_DTDIR_Field use + (Controller_To_Card => 0, + Card_To_Controller => 1); + + -- Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + type DCTRL_DTMODE_Field is + (-- Block data transfer + Block, + -- Stream or SDIO multibyte data transfer + Stream) + with Size => 1; + for DCTRL_DTMODE_Field use + (Block => 0, + Stream => 1); + subtype DCTRL_DMAEN_Field is STM32F40x.Bit; - subtype DCTRL_DBLOCKSIZE_Field is STM32F40x.UInt4; + + -- Data block size + type DCTRL_DBLOCKSIZE_Field is + (-- Block length = 2**0 = 1 byte + Block_1B, + -- Block length = 2**1 = 2 byte + Block_2B, + -- Block length = 2**2 = 4 byte + Block_4B, + -- Block length = 2**3 = 8 byte + Block_8B, + -- Block length = 2**4 = 16 byte + Block_16B, + -- Block length = 2**5 = 32 byte + Block_32B, + -- Block length = 2**6 = 64 byte + Block_64B, + -- Block length = 2**7 = 128 byte + Block_128B, + -- Block length = 2**8 = 256 byte + Block_256B, + -- Block length = 2**9 = 512 byte + Block_512B, + -- Block length = 2**10 = 1024 byte + Block_1024B, + -- Block length = 2**11 = 2048 byte + Block_2048B, + -- Block length = 2**12 = 4096 byte + Block_4096B, + -- Block length = 2**13 = 8192 byte + Block_8192B, + -- Block length = 2**14 = 16384 byte + Block_16384B) + with Size => 4; + for DCTRL_DBLOCKSIZE_Field use + (Block_1B => 0, + Block_2B => 1, + Block_4B => 2, + Block_8B => 3, + Block_16B => 4, + Block_32B => 5, + Block_64B => 6, + Block_128B => 7, + Block_256B => 8, + Block_512B => 9, + Block_1024B => 10, + Block_2048B => 11, + Block_4096B => 12, + Block_8192B => 13, + Block_16384B => 14); + subtype DCTRL_RWSTART_Field is STM32F40x.Bit; subtype DCTRL_RWSTOP_Field is STM32F40x.Bit; subtype DCTRL_RWMOD_Field is STM32F40x.Bit; @@ -193,14 +284,14 @@ package STM32F40x.SDIO is -- DTEN DTEN : DCTRL_DTEN_Field := 16#0#; -- Data transfer direction selection - DTDIR : DCTRL_DTDIR_Field := 16#0#; + DTDIR : DCTRL_DTDIR_Field := STM32F40x.SDIO.Controller_To_Card; -- Data transfer mode selection 1: Stream or SDIO multibyte data -- transfer. - DTMODE : DCTRL_DTMODE_Field := 16#0#; + DTMODE : DCTRL_DTMODE_Field := STM32F40x.SDIO.Block; -- DMA enable bit DMAEN : DCTRL_DMAEN_Field := 16#0#; -- Data block size - DBLOCKSIZE : DCTRL_DBLOCKSIZE_Field := 16#0#; + DBLOCKSIZE : DCTRL_DBLOCKSIZE_Field := STM32F40x.SDIO.Block_1B; -- Read wait start RWSTART : DCTRL_RWSTART_Field := 16#0#; -- Read wait stop @@ -212,8 +303,7 @@ package STM32F40x.SDIO is -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DCTRL_Register use record DTEN at 0 range 0 .. 0; @@ -228,31 +318,22 @@ package STM32F40x.SDIO is Reserved_12_31 at 0 range 12 .. 31; end record; - --------------------- - -- DCOUNT_Register -- - --------------------- - subtype DCOUNT_DATACOUNT_Field is STM32F40x.UInt25; -- data counter register type DCOUNT_Register is record -- Read-only. Data count value - DATACOUNT : DCOUNT_DATACOUNT_Field := 16#0#; + DATACOUNT : DCOUNT_DATACOUNT_Field; -- unspecified Reserved_25_31 : STM32F40x.UInt7; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DCOUNT_Register use record DATACOUNT at 0 range 0 .. 24; Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- STA_Register -- - ------------------ - subtype STA_CCRCFAIL_Field is STM32F40x.Bit; subtype STA_DCRCFAIL_Field is STM32F40x.Bit; subtype STA_CTIMEOUT_Field is STM32F40x.Bit; @@ -281,61 +362,60 @@ package STM32F40x.SDIO is -- status register type STA_Register is record -- Read-only. Command response received (CRC check failed) - CCRCFAIL : STA_CCRCFAIL_Field := 16#0#; + CCRCFAIL : STA_CCRCFAIL_Field; -- Read-only. Data block sent/received (CRC check failed) - DCRCFAIL : STA_DCRCFAIL_Field := 16#0#; + DCRCFAIL : STA_DCRCFAIL_Field; -- Read-only. Command response timeout - CTIMEOUT : STA_CTIMEOUT_Field := 16#0#; + CTIMEOUT : STA_CTIMEOUT_Field; -- Read-only. Data timeout - DTIMEOUT : STA_DTIMEOUT_Field := 16#0#; + DTIMEOUT : STA_DTIMEOUT_Field; -- Read-only. Transmit FIFO underrun error - TXUNDERR : STA_TXUNDERR_Field := 16#0#; + TXUNDERR : STA_TXUNDERR_Field; -- Read-only. Received FIFO overrun error - RXOVERR : STA_RXOVERR_Field := 16#0#; + RXOVERR : STA_RXOVERR_Field; -- Read-only. Command response received (CRC check passed) - CMDREND : STA_CMDREND_Field := 16#0#; + CMDREND : STA_CMDREND_Field; -- Read-only. Command sent (no response required) - CMDSENT : STA_CMDSENT_Field := 16#0#; + CMDSENT : STA_CMDSENT_Field; -- Read-only. Data end (data counter, SDIDCOUNT, is zero) - DATAEND : STA_DATAEND_Field := 16#0#; + DATAEND : STA_DATAEND_Field; -- Read-only. Start bit not detected on all data signals in wide bus -- mode - STBITERR : STA_STBITERR_Field := 16#0#; + STBITERR : STA_STBITERR_Field; -- Read-only. Data block sent/received (CRC check passed) - DBCKEND : STA_DBCKEND_Field := 16#0#; + DBCKEND : STA_DBCKEND_Field; -- Read-only. Command transfer in progress - CMDACT : STA_CMDACT_Field := 16#0#; + CMDACT : STA_CMDACT_Field; -- Read-only. Data transmit in progress - TXACT : STA_TXACT_Field := 16#0#; + TXACT : STA_TXACT_Field; -- Read-only. Data receive in progress - RXACT : STA_RXACT_Field := 16#0#; + RXACT : STA_RXACT_Field; -- Read-only. Transmit FIFO half empty: at least 8 words can be written -- into the FIFO - TXFIFOHE : STA_TXFIFOHE_Field := 16#0#; + TXFIFOHE : STA_TXFIFOHE_Field; -- Read-only. Receive FIFO half full: there are at least 8 words in the -- FIFO - RXFIFOHF : STA_RXFIFOHF_Field := 16#0#; + RXFIFOHF : STA_RXFIFOHF_Field; -- Read-only. Transmit FIFO full - TXFIFOF : STA_TXFIFOF_Field := 16#0#; + TXFIFOF : STA_TXFIFOF_Field; -- Read-only. Receive FIFO full - RXFIFOF : STA_RXFIFOF_Field := 16#0#; + RXFIFOF : STA_RXFIFOF_Field; -- Read-only. Transmit FIFO empty - TXFIFOE : STA_TXFIFOE_Field := 16#0#; + TXFIFOE : STA_TXFIFOE_Field; -- Read-only. Receive FIFO empty - RXFIFOE : STA_RXFIFOE_Field := 16#0#; + RXFIFOE : STA_RXFIFOE_Field; -- Read-only. Data available in transmit FIFO - TXDAVL : STA_TXDAVL_Field := 16#0#; + TXDAVL : STA_TXDAVL_Field; -- Read-only. Data available in receive FIFO - RXDAVL : STA_RXDAVL_Field := 16#0#; + RXDAVL : STA_RXDAVL_Field; -- Read-only. SDIO interrupt received - SDIOIT : STA_SDIOIT_Field := 16#0#; + SDIOIT : STA_SDIOIT_Field; -- Read-only. CE-ATA command completion signal received for CMD61 - CEATAEND : STA_CEATAEND_Field := 16#0#; + CEATAEND : STA_CEATAEND_Field; -- unspecified Reserved_24_31 : STM32F40x.Byte; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for STA_Register use record CCRCFAIL at 0 range 0 .. 0; @@ -365,10 +445,6 @@ package STM32F40x.SDIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- ICR_Register -- - ------------------ - subtype ICR_CCRCFAILC_Field is STM32F40x.Bit; subtype ICR_DCRCFAILC_Field is STM32F40x.Bit; subtype ICR_CTIMEOUTC_Field is STM32F40x.Bit; @@ -416,8 +492,7 @@ package STM32F40x.SDIO is -- unspecified Reserved_24_31 : STM32F40x.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ICR_Register use record CCRCFAILC at 0 range 0 .. 0; @@ -437,10 +512,6 @@ package STM32F40x.SDIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- MASK_Register -- - ------------------- - subtype MASK_CCRCFAILIE_Field is STM32F40x.Bit; subtype MASK_DCRCFAILIE_Field is STM32F40x.Bit; subtype MASK_CTIMEOUTIE_Field is STM32F40x.Bit; @@ -519,8 +590,7 @@ package STM32F40x.SDIO is -- unspecified Reserved_24_31 : STM32F40x.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MASK_Register use record CCRCFAILIE at 0 range 0 .. 0; @@ -550,22 +620,17 @@ package STM32F40x.SDIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------- - -- FIFOCNT_Register -- - ---------------------- - subtype FIFOCNT_FIFOCOUNT_Field is STM32F40x.UInt24; -- FIFO counter register type FIFOCNT_Register is record -- Read-only. Remaining number of words to be written to or read from -- the FIFO. - FIFOCOUNT : FIFOCNT_FIFOCOUNT_Field := 16#0#; + FIFOCOUNT : FIFOCNT_FIFOCOUNT_Field; -- unspecified Reserved_24_31 : STM32F40x.Byte; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FIFOCNT_Register use record FIFOCOUNT at 0 range 0 .. 23; @@ -579,63 +644,74 @@ package STM32F40x.SDIO is -- Secure digital input/output interface type SDIO_Peripheral is record -- power control register - POWER : POWER_Register; + POWER : aliased POWER_Register; + pragma Volatile_Full_Access (POWER); -- SDI clock control register - CLKCR : CLKCR_Register; + CLKCR : aliased CLKCR_Register; + pragma Volatile_Full_Access (CLKCR); -- argument register - ARG : STM32F40x.Word; + ARG : aliased STM32F40x.UInt32; -- command register - CMD : CMD_Register; + CMD : aliased CMD_Register; + pragma Volatile_Full_Access (CMD); -- command response register - RESPCMD : RESPCMD_Register; + RESPCMD : aliased RESPCMD_Register; + pragma Volatile_Full_Access (RESPCMD); -- response 1..4 register - RESP1 : STM32F40x.Word; + RESP1 : aliased STM32F40x.UInt32; -- response 1..4 register - RESP2 : STM32F40x.Word; + RESP2 : aliased STM32F40x.UInt32; -- response 1..4 register - RESP3 : STM32F40x.Word; + RESP3 : aliased STM32F40x.UInt32; -- response 1..4 register - RESP4 : STM32F40x.Word; + RESP4 : aliased STM32F40x.UInt32; -- data timer register - DTIMER : STM32F40x.Word; + DTIMER : aliased STM32F40x.UInt32; -- data length register - DLEN : DLEN_Register; + DLEN : aliased DLEN_Register; + pragma Volatile_Full_Access (DLEN); -- data control register - DCTRL : DCTRL_Register; + DCTRL : aliased DCTRL_Register; + pragma Volatile_Full_Access (DCTRL); -- data counter register - DCOUNT : DCOUNT_Register; + DCOUNT : aliased DCOUNT_Register; + pragma Volatile_Full_Access (DCOUNT); -- status register - STA : STA_Register; + STA : aliased STA_Register; + pragma Volatile_Full_Access (STA); -- interrupt clear register - ICR : ICR_Register; + ICR : aliased ICR_Register; + pragma Volatile_Full_Access (ICR); -- mask register - MASK : MASK_Register; + MASK : aliased MASK_Register; + pragma Volatile_Full_Access (MASK); -- FIFO counter register - FIFOCNT : FIFOCNT_Register; + FIFOCNT : aliased FIFOCNT_Register; + pragma Volatile_Full_Access (FIFOCNT); -- data FIFO register - FIFO : STM32F40x.Word; + FIFO : aliased STM32F40x.UInt32; end record with Volatile; for SDIO_Peripheral use record - POWER at 0 range 0 .. 31; - CLKCR at 4 range 0 .. 31; - ARG at 8 range 0 .. 31; - CMD at 12 range 0 .. 31; - RESPCMD at 16 range 0 .. 31; - RESP1 at 20 range 0 .. 31; - RESP2 at 24 range 0 .. 31; - RESP3 at 28 range 0 .. 31; - RESP4 at 32 range 0 .. 31; - DTIMER at 36 range 0 .. 31; - DLEN at 40 range 0 .. 31; - DCTRL at 44 range 0 .. 31; - DCOUNT at 48 range 0 .. 31; - STA at 52 range 0 .. 31; - ICR at 56 range 0 .. 31; - MASK at 60 range 0 .. 31; - FIFOCNT at 72 range 0 .. 31; - FIFO at 128 range 0 .. 31; + POWER at 16#0# range 0 .. 31; + CLKCR at 16#4# range 0 .. 31; + ARG at 16#8# range 0 .. 31; + CMD at 16#C# range 0 .. 31; + RESPCMD at 16#10# range 0 .. 31; + RESP1 at 16#14# range 0 .. 31; + RESP2 at 16#18# range 0 .. 31; + RESP3 at 16#1C# range 0 .. 31; + RESP4 at 16#20# range 0 .. 31; + DTIMER at 16#24# range 0 .. 31; + DLEN at 16#28# range 0 .. 31; + DCTRL at 16#2C# range 0 .. 31; + DCOUNT at 16#30# range 0 .. 31; + STA at 16#34# range 0 .. 31; + ICR at 16#38# range 0 .. 31; + MASK at 16#3C# range 0 .. 31; + FIFOCNT at 16#48# range 0 .. 31; + FIFO at 16#80# range 0 .. 31; end record; -- Secure digital input/output interface diff --git a/stm32f4/stm32f40x/stm32f40x-spi.ads b/stm32f4/stm32f40x/stm32f40x-spi.ads index 9f59ff6..d28d211 100644 --- a/stm32f4/stm32f40x/stm32f40x-spi.ads +++ b/stm32f4/stm32f40x/stm32f40x-spi.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.SPI is -- Registers -- --------------- - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_CPHA_Field is STM32F40x.Bit; subtype CR1_CPOL_Field is STM32F40x.Bit; subtype CR1_MSTR_Field is STM32F40x.Bit; @@ -63,10 +60,9 @@ package STM32F40x.SPI is -- Bidirectional data mode enable BIDIMODE : CR1_BIDIMODE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record CPHA at 0 range 0 .. 0; @@ -86,10 +82,6 @@ package STM32F40x.SPI is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_RXDMAEN_Field is STM32F40x.Bit; subtype CR2_TXDMAEN_Field is STM32F40x.Bit; subtype CR2_SSOE_Field is STM32F40x.Bit; @@ -119,8 +111,7 @@ package STM32F40x.SPI is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record RXDMAEN at 0 range 0 .. 0; @@ -134,10 +125,6 @@ package STM32F40x.SPI is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_RXNE_Field is STM32F40x.Bit; subtype SR_TXE_Field is STM32F40x.Bit; subtype SR_CHSIDE_Field is STM32F40x.Bit; @@ -171,8 +158,7 @@ package STM32F40x.SPI is -- unspecified Reserved_9_31 : STM32F40x.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record RXNE at 0 range 0 .. 0; @@ -187,94 +173,70 @@ package STM32F40x.SPI is Reserved_9_31 at 0 range 9 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - - subtype DR_DR_Field is STM32F40x.Short; + subtype DR_DR_Field is STM32F40x.UInt16; -- data register type DR_Register is record -- Data register DR : DR_DR_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- CRCPR_Register -- - -------------------- - - subtype CRCPR_CRCPOLY_Field is STM32F40x.Short; + subtype CRCPR_CRCPOLY_Field is STM32F40x.UInt16; -- CRC polynomial register type CRCPR_Register is record -- CRC polynomial register CRCPOLY : CRCPR_CRCPOLY_Field := 16#7#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCPR_Register use record CRCPOLY at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- RXCRCR_Register -- - --------------------- - - subtype RXCRCR_RxCRC_Field is STM32F40x.Short; + subtype RXCRCR_RxCRC_Field is STM32F40x.UInt16; -- RX CRC register type RXCRCR_Register is record -- Read-only. Rx CRC register - RxCRC : RXCRCR_RxCRC_Field := 16#0#; + RxCRC : RXCRCR_RxCRC_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RXCRCR_Register use record RxCRC at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- TXCRCR_Register -- - --------------------- - - subtype TXCRCR_TxCRC_Field is STM32F40x.Short; + subtype TXCRCR_TxCRC_Field is STM32F40x.UInt16; -- TX CRC register type TXCRCR_Register is record -- Read-only. Tx CRC register - TxCRC : TXCRCR_TxCRC_Field := 16#0#; + TxCRC : TXCRCR_TxCRC_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TXCRCR_Register use record TxCRC at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- I2SCFGR_Register -- - ---------------------- - subtype I2SCFGR_CHLEN_Field is STM32F40x.Bit; subtype I2SCFGR_DATLEN_Field is STM32F40x.UInt2; subtype I2SCFGR_CKPOL_Field is STM32F40x.Bit; @@ -307,8 +269,7 @@ package STM32F40x.SPI is -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for I2SCFGR_Register use record CHLEN at 0 range 0 .. 0; @@ -323,10 +284,6 @@ package STM32F40x.SPI is Reserved_12_31 at 0 range 12 .. 31; end record; - -------------------- - -- I2SPR_Register -- - -------------------- - subtype I2SPR_I2SDIV_Field is STM32F40x.Byte; subtype I2SPR_ODD_Field is STM32F40x.Bit; subtype I2SPR_MCKOE_Field is STM32F40x.Bit; @@ -342,8 +299,7 @@ package STM32F40x.SPI is -- unspecified Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for I2SPR_Register use record I2SDIV at 0 range 0 .. 7; @@ -359,50 +315,51 @@ package STM32F40x.SPI is -- Serial peripheral interface type SPI_Peripheral is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- CRC polynomial register - CRCPR : CRCPR_Register; + CRCPR : aliased CRCPR_Register; + pragma Volatile_Full_Access (CRCPR); -- RX CRC register - RXCRCR : RXCRCR_Register; + RXCRCR : aliased RXCRCR_Register; + pragma Volatile_Full_Access (RXCRCR); -- TX CRC register - TXCRCR : TXCRCR_Register; + TXCRCR : aliased TXCRCR_Register; + pragma Volatile_Full_Access (TXCRCR); -- I2S configuration register - I2SCFGR : I2SCFGR_Register; + I2SCFGR : aliased I2SCFGR_Register; + pragma Volatile_Full_Access (I2SCFGR); -- I2S prescaler register - I2SPR : I2SPR_Register; + I2SPR : aliased I2SPR_Register; + pragma Volatile_Full_Access (I2SPR); end record with Volatile; for SPI_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SR at 8 range 0 .. 31; - DR at 12 range 0 .. 31; - CRCPR at 16 range 0 .. 31; - RXCRCR at 20 range 0 .. 31; - TXCRCR at 24 range 0 .. 31; - I2SCFGR at 28 range 0 .. 31; - I2SPR at 32 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SR at 16#8# range 0 .. 31; + DR at 16#C# range 0 .. 31; + CRCPR at 16#10# range 0 .. 31; + RXCRCR at 16#14# range 0 .. 31; + TXCRCR at 16#18# range 0 .. 31; + I2SCFGR at 16#1C# range 0 .. 31; + I2SPR at 16#20# range 0 .. 31; end record; -- Serial peripheral interface I2S2ext_Periph : aliased SPI_Peripheral with Import, Address => I2S2ext_Base; - -- Serial peripheral interface - SPI2_Periph : aliased SPI_Peripheral - with Import, Address => SPI2_Base; - - -- Serial peripheral interface - SPI3_Periph : aliased SPI_Peripheral - with Import, Address => SPI3_Base; - -- Serial peripheral interface I2S3ext_Periph : aliased SPI_Peripheral with Import, Address => I2S3ext_Base; @@ -411,4 +368,12 @@ package STM32F40x.SPI is SPI1_Periph : aliased SPI_Peripheral with Import, Address => SPI1_Base; + -- Serial peripheral interface + SPI2_Periph : aliased SPI_Peripheral + with Import, Address => SPI2_Base; + + -- Serial peripheral interface + SPI3_Periph : aliased SPI_Peripheral + with Import, Address => SPI3_Base; + end STM32F40x.SPI; diff --git a/stm32f4/stm32f40x/stm32f40x-syscfg.ads b/stm32f4/stm32f40x/stm32f40x-syscfg.ads index 6cc9597..8b877fd 100644 --- a/stm32f4/stm32f40x/stm32f40x-syscfg.ads +++ b/stm32f4/stm32f40x/stm32f40x-syscfg.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.SYSCFG is -- Registers -- --------------- - -------------------- - -- MEMRM_Register -- - -------------------- - subtype MEMRM_MEM_MODE_Field is STM32F40x.UInt2; -- memory remap register @@ -26,18 +23,13 @@ package STM32F40x.SYSCFG is -- unspecified Reserved_2_31 : STM32F40x.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MEMRM_Register use record MEM_MODE at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------ - -- PMC_Register -- - ------------------ - subtype PMC_MII_RMII_SEL_Field is STM32F40x.Bit; -- peripheral mode configuration register @@ -49,8 +41,7 @@ package STM32F40x.SYSCFG is -- unspecified Reserved_24_31 : STM32F40x.Byte := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_Register use record Reserved_0_22 at 0 range 0 .. 22; @@ -58,14 +49,6 @@ package STM32F40x.SYSCFG is Reserved_24_31 at 0 range 24 .. 31; end record; - --------------------- - -- EXTICR_Register -- - --------------------- - - ------------------ - -- EXTICR1.EXTI -- - ------------------ - -- EXTICR1_EXTI array element subtype EXTICR1_EXTI_Element is STM32F40x.UInt4; @@ -80,7 +63,7 @@ package STM32F40x.SYSCFG is case As_Array is when False => -- EXTI as a value - Val : STM32F40x.Short; + Val : STM32F40x.UInt16; when True => -- EXTI as an array Arr : EXTICR1_EXTI_Field_Array; @@ -94,24 +77,145 @@ package STM32F40x.SYSCFG is end record; -- external interrupt configuration register 1 - type EXTICR_Register is record + type EXTICR1_Register is record -- EXTI x configuration (x = 0 to 3) EXTI : EXTICR1_EXTI_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EXTICR1_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- EXTICR2_EXTI array element + subtype EXTICR2_EXTI_Element is STM32F40x.UInt4; + + -- EXTICR2_EXTI array + type EXTICR2_EXTI_Field_Array is array (4 .. 7) of EXTICR2_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR2_EXTI + type EXTICR2_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : STM32F40x.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR2_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR2_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 2 + type EXTICR2_Register is record + -- EXTI x configuration (x = 4 to 7) + EXTI : EXTICR2_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EXTICR2_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- EXTICR3_EXTI array element + subtype EXTICR3_EXTI_Element is STM32F40x.UInt4; + + -- EXTICR3_EXTI array + type EXTICR3_EXTI_Field_Array is array (8 .. 11) of EXTICR3_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR3_EXTI + type EXTICR3_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : STM32F40x.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR3_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR3_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 3 + type EXTICR3_Register is record + -- EXTI x configuration (x = 8 to 11) + EXTI : EXTICR3_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EXTICR_Register use record + for EXTICR3_Register use record EXTI at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- CMPCR_Register -- - -------------------- + -- EXTICR4_EXTI array element + subtype EXTICR4_EXTI_Element is STM32F40x.UInt4; + + -- EXTICR4_EXTI array + type EXTICR4_EXTI_Field_Array is array (12 .. 15) of EXTICR4_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR4_EXTI + type EXTICR4_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : STM32F40x.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR4_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR4_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 4 + type EXTICR4_Register is record + -- EXTI x configuration (x = 12 to 15) + EXTI : EXTICR4_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EXTICR4_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; subtype CMPCR_CMP_PD_Field is STM32F40x.Bit; subtype CMPCR_READY_Field is STM32F40x.Bit; @@ -119,16 +223,15 @@ package STM32F40x.SYSCFG is -- Compensation cell control register type CMPCR_Register is record -- Read-only. Compensation cell power-down - CMP_PD : CMPCR_CMP_PD_Field := 16#0#; + CMP_PD : CMPCR_CMP_PD_Field; -- unspecified Reserved_1_7 : STM32F40x.UInt7; -- Read-only. READY - READY : CMPCR_READY_Field := 16#0#; + READY : CMPCR_READY_Field; -- unspecified Reserved_9_31 : STM32F40x.UInt23; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMPCR_Register use record CMP_PD at 0 range 0 .. 0; @@ -144,30 +247,37 @@ package STM32F40x.SYSCFG is -- System configuration controller type SYSCFG_Peripheral is record -- memory remap register - MEMRM : MEMRM_Register; + MEMRM : aliased MEMRM_Register; + pragma Volatile_Full_Access (MEMRM); -- peripheral mode configuration register - PMC : PMC_Register; + PMC : aliased PMC_Register; + pragma Volatile_Full_Access (PMC); -- external interrupt configuration register 1 - EXTICR1 : EXTICR_Register; + EXTICR1 : aliased EXTICR1_Register; + pragma Volatile_Full_Access (EXTICR1); -- external interrupt configuration register 2 - EXTICR2 : EXTICR_Register; + EXTICR2 : aliased EXTICR2_Register; + pragma Volatile_Full_Access (EXTICR2); -- external interrupt configuration register 3 - EXTICR3 : EXTICR_Register; + EXTICR3 : aliased EXTICR3_Register; + pragma Volatile_Full_Access (EXTICR3); -- external interrupt configuration register 4 - EXTICR4 : EXTICR_Register; + EXTICR4 : aliased EXTICR4_Register; + pragma Volatile_Full_Access (EXTICR4); -- Compensation cell control register - CMPCR : CMPCR_Register; + CMPCR : aliased CMPCR_Register; + pragma Volatile_Full_Access (CMPCR); end record with Volatile; for SYSCFG_Peripheral use record - MEMRM at 0 range 0 .. 31; - PMC at 4 range 0 .. 31; - EXTICR1 at 8 range 0 .. 31; - EXTICR2 at 12 range 0 .. 31; - EXTICR3 at 16 range 0 .. 31; - EXTICR4 at 20 range 0 .. 31; - CMPCR at 32 range 0 .. 31; + MEMRM at 16#0# range 0 .. 31; + PMC at 16#4# range 0 .. 31; + EXTICR1 at 16#8# range 0 .. 31; + EXTICR2 at 16#C# range 0 .. 31; + EXTICR3 at 16#10# range 0 .. 31; + EXTICR4 at 16#14# range 0 .. 31; + CMPCR at 16#20# range 0 .. 31; end record; -- System configuration controller diff --git a/stm32f4/stm32f40x/stm32f40x-tim.ads b/stm32f4/stm32f40x/stm32f40x-tim.ads index a6778d9..230e984 100644 --- a/stm32f4/stm32f40x/stm32f40x-tim.ads +++ b/stm32f4/stm32f40x/stm32f40x-tim.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.TIM is -- Registers -- --------------- - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_CEN_Field is STM32F40x.Bit; subtype CR1_UDIS_Field is STM32F40x.Bit; subtype CR1_URS_Field is STM32F40x.Bit; @@ -47,8 +44,7 @@ package STM32F40x.TIM is -- unspecified Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record CEN at 0 range 0 .. 0; @@ -62,10 +58,6 @@ package STM32F40x.TIM is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_CCPC_Field is STM32F40x.Bit; subtype CR2_CCUS_Field is STM32F40x.Bit; subtype CR2_CCDS_Field is STM32F40x.Bit; @@ -110,8 +102,7 @@ package STM32F40x.TIM is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record CCPC at 0 range 0 .. 0; @@ -130,10 +121,6 @@ package STM32F40x.TIM is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------- - -- SMCR_Register -- - ------------------- - subtype SMCR_SMS_Field is STM32F40x.UInt3; subtype SMCR_TS_Field is STM32F40x.UInt3; subtype SMCR_MSM_Field is STM32F40x.Bit; @@ -161,10 +148,9 @@ package STM32F40x.TIM is -- External trigger polarity ETP : SMCR_ETP_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SMCR_Register use record SMS at 0 range 0 .. 2; @@ -178,10 +164,6 @@ package STM32F40x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- DIER_Register -- - ------------------- - subtype DIER_UIE_Field is STM32F40x.Bit; subtype DIER_CC1IE_Field is STM32F40x.Bit; subtype DIER_CC2IE_Field is STM32F40x.Bit; @@ -233,8 +215,7 @@ package STM32F40x.TIM is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DIER_Register use record UIE at 0 range 0 .. 0; @@ -255,10 +236,6 @@ package STM32F40x.TIM is Reserved_15_31 at 0 range 15 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_UIF_Field is STM32F40x.Bit; subtype SR_CC1IF_Field is STM32F40x.Bit; subtype SR_CC2IF_Field is STM32F40x.Bit; @@ -303,8 +280,7 @@ package STM32F40x.TIM is -- unspecified Reserved_13_31 : STM32F40x.UInt19 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record UIF at 0 range 0 .. 0; @@ -323,10 +299,6 @@ package STM32F40x.TIM is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------ - -- EGR_Register -- - ------------------ - subtype EGR_UG_Field is STM32F40x.Bit; subtype EGR_CC1G_Field is STM32F40x.Bit; subtype EGR_CC2G_Field is STM32F40x.Bit; @@ -357,8 +329,7 @@ package STM32F40x.TIM is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for EGR_Register use record UG at 0 range 0 .. 0; @@ -372,10 +343,6 @@ package STM32F40x.TIM is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------------- - -- CCMR1_Output_Register -- - --------------------------- - subtype CCMR1_Output_CC1S_Field is STM32F40x.UInt2; subtype CCMR1_Output_OC1FE_Field is STM32F40x.Bit; subtype CCMR1_Output_OC1PE_Field is STM32F40x.Bit; @@ -410,10 +377,9 @@ package STM32F40x.TIM is -- Output Compare 2 clear enable OC2CE : CCMR1_Output_OC2CE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR1_Output_Register use record CC1S at 0 range 0 .. 1; @@ -429,10 +395,6 @@ package STM32F40x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------------- - -- CCMR1_Input_Register -- - -------------------------- - subtype CCMR1_Input_CC1S_Field is STM32F40x.UInt2; subtype CCMR1_Input_ICPCS_Field is STM32F40x.UInt2; subtype CCMR1_Input_IC1F_Field is STM32F40x.UInt4; @@ -455,10 +417,9 @@ package STM32F40x.TIM is -- Input capture 2 filter IC2F : CCMR1_Input_IC2F_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR1_Input_Register use record CC1S at 0 range 0 .. 1; @@ -470,10 +431,6 @@ package STM32F40x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------------- - -- CCMR2_Output_Register -- - --------------------------- - subtype CCMR2_Output_CC3S_Field is STM32F40x.UInt2; subtype CCMR2_Output_OC3FE_Field is STM32F40x.Bit; subtype CCMR2_Output_OC3PE_Field is STM32F40x.Bit; @@ -508,10 +465,9 @@ package STM32F40x.TIM is -- Output compare 4 clear enable OC4CE : CCMR2_Output_OC4CE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR2_Output_Register use record CC3S at 0 range 0 .. 1; @@ -527,10 +483,6 @@ package STM32F40x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------------- - -- CCMR2_Input_Register -- - -------------------------- - subtype CCMR2_Input_CC3S_Field is STM32F40x.UInt2; subtype CCMR2_Input_IC3PSC_Field is STM32F40x.UInt2; subtype CCMR2_Input_IC3F_Field is STM32F40x.UInt4; @@ -553,10 +505,9 @@ package STM32F40x.TIM is -- Input capture 4 filter IC4F : CCMR2_Input_IC4F_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR2_Input_Register use record CC3S at 0 range 0 .. 1; @@ -568,10 +519,6 @@ package STM32F40x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- CCER_Register -- - ------------------- - subtype CCER_CC1E_Field is STM32F40x.Bit; subtype CCER_CC1P_Field is STM32F40x.Bit; subtype CCER_CC1NE_Field is STM32F40x.Bit; @@ -620,8 +567,7 @@ package STM32F40x.TIM is -- unspecified Reserved_14_31 : STM32F40x.UInt18 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCER_Register use record CC1E at 0 range 0 .. 0; @@ -641,73 +587,54 @@ package STM32F40x.TIM is Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------ - -- CNT_Register -- - ------------------ - - subtype CNT_CNT_Field is STM32F40x.Short; + subtype CNT_CNT_Field is STM32F40x.UInt16; -- counter type CNT_Register is record -- counter value CNT : CNT_CNT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CNT_Register use record CNT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- PSC_Register -- - ------------------ - - subtype PSC_PSC_Field is STM32F40x.Short; + subtype PSC_PSC_Field is STM32F40x.UInt16; -- prescaler type PSC_Register is record -- Prescaler value PSC : PSC_PSC_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PSC_Register use record PSC at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- ARR_Register -- - ------------------ - - subtype ARR_ARR_Field is STM32F40x.Short; + subtype ARR_ARR_Field is STM32F40x.UInt16; -- auto-reload register type ARR_Register is record -- Auto-reload value ARR : ARR_ARR_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ARR_Register use record ARR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- RCR_Register -- - ------------------ - subtype RCR_REP_Field is STM32F40x.Byte; -- repetition counter register @@ -717,38 +644,76 @@ package STM32F40x.TIM is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RCR_Register use record REP at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- CCR_Register -- - ------------------ - - subtype CCR1_CCR1_Field is STM32F40x.Short; + subtype CCR1_CCR1_Field is STM32F40x.UInt16; -- capture/compare register 1 - type CCR_Register is record + type CCR1_Register is record -- Capture/Compare 1 value CCR1 : CCR1_CCR1_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CCR_Register use record + for CCR1_Register use record CCR1 at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- BDTR_Register -- - ------------------- + subtype CCR2_CCR2_Field is STM32F40x.UInt16; + + -- capture/compare register 2 + type CCR2_Register is record + -- Capture/Compare 2 value + CCR2 : CCR2_CCR2_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR2_Register use record + CCR2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCR3_CCR3_Field is STM32F40x.UInt16; + + -- capture/compare register 3 + type CCR3_Register is record + -- Capture/Compare value + CCR3 : CCR3_CCR3_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR3_Register use record + CCR3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCR4_CCR4_Field is STM32F40x.UInt16; + + -- capture/compare register 4 + type CCR4_Register is record + -- Capture/Compare value + CCR4 : CCR4_CCR4_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR4_Register use record + CCR4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; subtype BDTR_DTG_Field is STM32F40x.Byte; subtype BDTR_LOCK_Field is STM32F40x.UInt2; @@ -778,10 +743,9 @@ package STM32F40x.TIM is -- Main output enable MOE : BDTR_MOE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BDTR_Register use record DTG at 0 range 0 .. 7; @@ -795,10 +759,6 @@ package STM32F40x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- DCR_Register -- - ------------------ - subtype DCR_DBA_Field is STM32F40x.UInt5; subtype DCR_DBL_Field is STM32F40x.UInt5; @@ -813,8 +773,7 @@ package STM32F40x.TIM is -- unspecified Reserved_13_31 : STM32F40x.UInt19 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DCR_Register use record DBA at 0 range 0 .. 4; @@ -823,31 +782,22 @@ package STM32F40x.TIM is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------- - -- DMAR_Register -- - ------------------- - - subtype DMAR_DMAB_Field is STM32F40x.Short; + subtype DMAR_DMAB_Field is STM32F40x.UInt16; -- DMA address for full transfer type DMAR_Register is record -- DMA register for burst accesses DMAB : DMAR_DMAB_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DMAR_Register use record DMAB at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - -- control register 2 type CR2_Register_1 is record -- unspecified @@ -861,8 +811,7 @@ package STM32F40x.TIM is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register_1 use record Reserved_0_2 at 0 range 0 .. 2; @@ -872,10 +821,6 @@ package STM32F40x.TIM is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- DIER_Register -- - ------------------- - -- DMA/Interrupt enable register type DIER_Register_1 is record -- Update interrupt enable @@ -911,8 +856,7 @@ package STM32F40x.TIM is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DIER_Register_1 use record UIE at 0 range 0 .. 0; @@ -933,10 +877,6 @@ package STM32F40x.TIM is Reserved_15_31 at 0 range 15 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - -- status register type SR_Register_1 is record -- Update interrupt flag @@ -966,8 +906,7 @@ package STM32F40x.TIM is -- unspecified Reserved_13_31 : STM32F40x.UInt19 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register_1 use record UIF at 0 range 0 .. 0; @@ -985,10 +924,6 @@ package STM32F40x.TIM is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------ - -- EGR_Register -- - ------------------ - -- event generation register type EGR_Register_1 is record -- Write-only. Update generation @@ -1008,8 +943,7 @@ package STM32F40x.TIM is -- unspecified Reserved_7_31 : STM32F40x.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for EGR_Register_1 use record UG at 0 range 0 .. 0; @@ -1022,9 +956,48 @@ package STM32F40x.TIM is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------- - -- CCER_Register -- - ------------------- + subtype CCMR2_Output_O24CE_Field is STM32F40x.Bit; + + -- capture/compare mode register 2 (output mode) + type CCMR2_Output_Register_1 is record + -- CC3S + CC3S : CCMR2_Output_CC3S_Field := 16#0#; + -- OC3FE + OC3FE : CCMR2_Output_OC3FE_Field := 16#0#; + -- OC3PE + OC3PE : CCMR2_Output_OC3PE_Field := 16#0#; + -- OC3M + OC3M : CCMR2_Output_OC3M_Field := 16#0#; + -- OC3CE + OC3CE : CCMR2_Output_OC3CE_Field := 16#0#; + -- CC4S + CC4S : CCMR2_Output_CC4S_Field := 16#0#; + -- OC4FE + OC4FE : CCMR2_Output_OC4FE_Field := 16#0#; + -- OC4PE + OC4PE : CCMR2_Output_OC4PE_Field := 16#0#; + -- OC4M + OC4M : CCMR2_Output_OC4M_Field := 16#0#; + -- O24CE + O24CE : CCMR2_Output_O24CE_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCMR2_Output_Register_1 use record + CC3S at 0 range 0 .. 1; + OC3FE at 0 range 2 .. 2; + OC3PE at 0 range 3 .. 3; + OC3M at 0 range 4 .. 6; + OC3CE at 0 range 7 .. 7; + CC4S at 0 range 8 .. 9; + OC4FE at 0 range 10 .. 10; + OC4PE at 0 range 11 .. 11; + OC4M at 0 range 12 .. 14; + O24CE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; subtype CCER_CC4NP_Field is STM32F40x.Bit; @@ -1063,10 +1036,9 @@ package STM32F40x.TIM is -- Capture/Compare 4 output Polarity CC4NP : CCER_CC4NP_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCER_Register_1 use record CC1E at 0 range 0 .. 0; @@ -1088,12 +1060,8 @@ package STM32F40x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CNT_Register -- - ------------------ - - subtype CNT_CNT_L_Field is STM32F40x.Short; - subtype CNT_CNT_H_Field is STM32F40x.Short; + subtype CNT_CNT_L_Field is STM32F40x.UInt16; + subtype CNT_CNT_H_Field is STM32F40x.UInt16; -- counter type CNT_Register_1 is record @@ -1102,20 +1070,15 @@ package STM32F40x.TIM is -- High counter value CNT_H : CNT_CNT_H_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CNT_Register_1 use record CNT_L at 0 range 0 .. 15; CNT_H at 0 range 16 .. 31; end record; - ------------------ - -- ARR_Register -- - ------------------ - - subtype ARR_ARR_L_Field is STM32F40x.Short; - subtype ARR_ARR_H_Field is STM32F40x.Short; + subtype ARR_ARR_L_Field is STM32F40x.UInt16; + subtype ARR_ARR_H_Field is STM32F40x.UInt16; -- auto-reload register type ARR_Register_1 is record @@ -1124,39 +1087,80 @@ package STM32F40x.TIM is -- High Auto-reload value ARR_H : ARR_ARR_H_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ARR_Register_1 use record ARR_L at 0 range 0 .. 15; ARR_H at 0 range 16 .. 31; end record; - ------------------ - -- CCR_Register -- - ------------------ - - subtype CCR1_CCR1_L_Field is STM32F40x.Short; - subtype CCR1_CCR1_H_Field is STM32F40x.Short; + subtype CCR1_CCR1_L_Field is STM32F40x.UInt16; + subtype CCR1_CCR1_H_Field is STM32F40x.UInt16; -- capture/compare register 1 - type CCR_Register_1 is record + type CCR1_Register_1 is record -- Low Capture/Compare 1 value CCR1_L : CCR1_CCR1_L_Field := 16#0#; -- High Capture/Compare 1 value CCR1_H : CCR1_CCR1_H_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CCR_Register_1 use record + for CCR1_Register_1 use record CCR1_L at 0 range 0 .. 15; CCR1_H at 0 range 16 .. 31; end record; - ----------------- - -- OR_Register -- - ----------------- + subtype CCR2_CCR2_L_Field is STM32F40x.UInt16; + subtype CCR2_CCR2_H_Field is STM32F40x.UInt16; + + -- capture/compare register 2 + type CCR2_Register_1 is record + -- Low Capture/Compare 2 value + CCR2_L : CCR2_CCR2_L_Field := 16#0#; + -- High Capture/Compare 2 value + CCR2_H : CCR2_CCR2_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR2_Register_1 use record + CCR2_L at 0 range 0 .. 15; + CCR2_H at 0 range 16 .. 31; + end record; + + subtype CCR3_CCR3_L_Field is STM32F40x.UInt16; + subtype CCR3_CCR3_H_Field is STM32F40x.UInt16; + + -- capture/compare register 3 + type CCR3_Register_1 is record + -- Low Capture/Compare value + CCR3_L : CCR3_CCR3_L_Field := 16#0#; + -- High Capture/Compare value + CCR3_H : CCR3_CCR3_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR3_Register_1 use record + CCR3_L at 0 range 0 .. 15; + CCR3_H at 0 range 16 .. 31; + end record; + + subtype CCR4_CCR4_L_Field is STM32F40x.UInt16; + subtype CCR4_CCR4_H_Field is STM32F40x.UInt16; + + -- capture/compare register 4 + type CCR4_Register_1 is record + -- Low Capture/Compare value + CCR4_L : CCR4_CCR4_L_Field := 16#0#; + -- High Capture/Compare value + CCR4_H : CCR4_CCR4_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR4_Register_1 use record + CCR4_L at 0 range 0 .. 15; + CCR4_H at 0 range 16 .. 31; + end record; subtype OR_ITR1_RMP_Field is STM32F40x.UInt2; @@ -1169,8 +1173,7 @@ package STM32F40x.TIM is -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OR_Register use record Reserved_0_9 at 0 range 0 .. 9; @@ -1178,10 +1181,6 @@ package STM32F40x.TIM is Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------- - -- OR_Register -- - ----------------- - subtype OR_IT4_RMP_Field is STM32F40x.UInt2; -- TIM5 option register @@ -1193,8 +1192,7 @@ package STM32F40x.TIM is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OR_Register_1 use record Reserved_0_5 at 0 range 0 .. 5; @@ -1202,47 +1200,35 @@ package STM32F40x.TIM is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- CR1_Register -- - ------------------ - -- control register 1 type CR1_Register_1 is record -- Counter enable - CEN : CR1_CEN_Field := 16#0#; + CEN : CR1_CEN_Field := 16#0#; -- Update disable - UDIS : CR1_UDIS_Field := 16#0#; + UDIS : CR1_UDIS_Field := 16#0#; -- Update request source - URS : CR1_URS_Field := 16#0#; + URS : CR1_URS_Field := 16#0#; -- One-pulse mode - OPM : CR1_OPM_Field := 16#0#; + OPM : CR1_OPM_Field := 16#0#; -- unspecified - Reserved_4_6 : STM32F40x.UInt3 := 16#0#; + Reserved_4_6 : STM32F40x.UInt3 := 16#0#; -- Auto-reload preload enable - ARPE : CR1_ARPE_Field := 16#0#; - -- Clock division - CKD : CR1_CKD_Field := 16#0#; + ARPE : CR1_ARPE_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F40x.UInt22 := 16#0#; + Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register_1 use record - CEN at 0 range 0 .. 0; - UDIS at 0 range 1 .. 1; - URS at 0 range 2 .. 2; - OPM at 0 range 3 .. 3; - Reserved_4_6 at 0 range 4 .. 6; - ARPE at 0 range 7 .. 7; - CKD at 0 range 8 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + CEN at 0 range 0 .. 0; + UDIS at 0 range 1 .. 1; + URS at 0 range 2 .. 2; + OPM at 0 range 3 .. 3; + Reserved_4_6 at 0 range 4 .. 6; + ARPE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - -- control register 2 type CR2_Register_2 is record -- unspecified @@ -1252,8 +1238,7 @@ package STM32F40x.TIM is -- unspecified Reserved_7_31 : STM32F40x.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register_2 use record Reserved_0_3 at 0 range 0 .. 3; @@ -1261,9 +1246,85 @@ package STM32F40x.TIM is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------- - -- SMCR_Register -- - ------------------- + -- DMA/Interrupt enable register + type DIER_Register_2 is record + -- Update interrupt enable + UIE : DIER_UIE_Field := 16#0#; + -- unspecified + Reserved_1_7 : STM32F40x.UInt7 := 16#0#; + -- Update DMA request enable + UDE : DIER_UDE_Field := 16#0#; + -- unspecified + Reserved_9_31 : STM32F40x.UInt23 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DIER_Register_2 use record + UIE at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + UDE at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- status register + type SR_Register_2 is record + -- Update interrupt flag + UIF : SR_UIF_Field := 16#0#; + -- unspecified + Reserved_1_31 : STM32F40x.UInt31 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SR_Register_2 use record + UIF at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- event generation register + type EGR_Register_2 is record + -- Write-only. Update generation + UG : EGR_UG_Field := 16#0#; + -- unspecified + Reserved_1_31 : STM32F40x.UInt31 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EGR_Register_2 use record + UG at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- control register 1 + type CR1_Register_2 is record + -- Counter enable + CEN : CR1_CEN_Field := 16#0#; + -- Update disable + UDIS : CR1_UDIS_Field := 16#0#; + -- Update request source + URS : CR1_URS_Field := 16#0#; + -- One-pulse mode + OPM : CR1_OPM_Field := 16#0#; + -- unspecified + Reserved_4_6 : STM32F40x.UInt3 := 16#0#; + -- Auto-reload preload enable + ARPE : CR1_ARPE_Field := 16#0#; + -- Clock division + CKD : CR1_CKD_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F40x.UInt22 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CR1_Register_2 use record + CEN at 0 range 0 .. 0; + UDIS at 0 range 1 .. 1; + URS at 0 range 2 .. 2; + OPM at 0 range 3 .. 3; + Reserved_4_6 at 0 range 4 .. 6; + ARPE at 0 range 7 .. 7; + CKD at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; -- slave mode control register type SMCR_Register_1 is record @@ -1278,8 +1339,7 @@ package STM32F40x.TIM is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SMCR_Register_1 use record SMS at 0 range 0 .. 2; @@ -1289,12 +1349,8 @@ package STM32F40x.TIM is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- DIER_Register -- - ------------------- - -- DMA/Interrupt enable register - type DIER_Register_2 is record + type DIER_Register_3 is record -- Update interrupt enable UIE : DIER_UIE_Field := 16#0#; -- Capture/Compare 1 interrupt enable @@ -1308,10 +1364,9 @@ package STM32F40x.TIM is -- unspecified Reserved_7_31 : STM32F40x.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIER_Register_2 use record + for DIER_Register_3 use record UIE at 0 range 0 .. 0; CC1IE at 0 range 1 .. 1; CC2IE at 0 range 2 .. 2; @@ -1320,12 +1375,8 @@ package STM32F40x.TIM is Reserved_7_31 at 0 range 7 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - -- status register - type SR_Register_2 is record + type SR_Register_3 is record -- Update interrupt flag UIF : SR_UIF_Field := 16#0#; -- Capture/compare 1 interrupt flag @@ -1345,10 +1396,9 @@ package STM32F40x.TIM is -- unspecified Reserved_11_31 : STM32F40x.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register_2 use record + for SR_Register_3 use record UIF at 0 range 0 .. 0; CC1IF at 0 range 1 .. 1; CC2IF at 0 range 2 .. 2; @@ -1360,12 +1410,8 @@ package STM32F40x.TIM is Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------ - -- EGR_Register -- - ------------------ - -- event generation register - type EGR_Register_2 is record + type EGR_Register_3 is record -- Write-only. Update generation UG : EGR_UG_Field := 16#0#; -- Write-only. Capture/compare 1 generation @@ -1379,10 +1425,9 @@ package STM32F40x.TIM is -- unspecified Reserved_7_31 : STM32F40x.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EGR_Register_2 use record + for EGR_Register_3 use record UG at 0 range 0 .. 0; CC1G at 0 range 1 .. 1; CC2G at 0 range 2 .. 2; @@ -1391,10 +1436,6 @@ package STM32F40x.TIM is Reserved_7_31 at 0 range 7 .. 31; end record; - --------------------------- - -- CCMR1_Output_Register -- - --------------------------- - -- capture/compare mode register 1 (output mode) type CCMR1_Output_Register_1 is record -- Capture/Compare 1 selection @@ -1418,8 +1459,7 @@ package STM32F40x.TIM is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR1_Output_Register_1 use record CC1S at 0 range 0 .. 1; @@ -1434,10 +1474,6 @@ package STM32F40x.TIM is Reserved_15_31 at 0 range 15 .. 31; end record; - -------------------------- - -- CCMR1_Input_Register -- - -------------------------- - subtype CCMR1_Input_IC1F_Field_1 is STM32F40x.UInt3; subtype CCMR1_Input_IC2F_Field_1 is STM32F40x.UInt3; @@ -1460,8 +1496,7 @@ package STM32F40x.TIM is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR1_Input_Register_1 use record CC1S at 0 range 0 .. 1; @@ -1474,10 +1509,6 @@ package STM32F40x.TIM is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------- - -- CCER_Register -- - ------------------- - -- capture/compare enable register type CCER_Register_2 is record -- Capture/Compare 1 output enable @@ -1499,8 +1530,7 @@ package STM32F40x.TIM is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCER_Register_2 use record CC1E at 0 range 0 .. 0; @@ -1514,12 +1544,8 @@ package STM32F40x.TIM is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- CR1_Register -- - ------------------ - -- control register 1 - type CR1_Register_2 is record + type CR1_Register_3 is record -- Counter enable CEN : CR1_CEN_Field := 16#0#; -- Update disable @@ -1535,10 +1561,9 @@ package STM32F40x.TIM is -- unspecified Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR1_Register_2 use record + for CR1_Register_3 use record CEN at 0 range 0 .. 0; UDIS at 0 range 1 .. 1; URS at 0 range 2 .. 2; @@ -1548,12 +1573,8 @@ package STM32F40x.TIM is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------- - -- DIER_Register -- - ------------------- - -- DMA/Interrupt enable register - type DIER_Register_3 is record + type DIER_Register_4 is record -- Update interrupt enable UIE : DIER_UIE_Field := 16#0#; -- Capture/Compare 1 interrupt enable @@ -1561,21 +1582,16 @@ package STM32F40x.TIM is -- unspecified Reserved_2_31 : STM32F40x.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIER_Register_3 use record + for DIER_Register_4 use record UIE at 0 range 0 .. 0; CC1IE at 0 range 1 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - -- status register - type SR_Register_3 is record + type SR_Register_4 is record -- Update interrupt flag UIF : SR_UIF_Field := 16#0#; -- Capture/compare 1 interrupt flag @@ -1587,10 +1603,9 @@ package STM32F40x.TIM is -- unspecified Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SR_Register_3 use record + for SR_Register_4 use record UIF at 0 range 0 .. 0; CC1IF at 0 range 1 .. 1; Reserved_2_8 at 0 range 2 .. 8; @@ -1598,12 +1613,8 @@ package STM32F40x.TIM is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------ - -- EGR_Register -- - ------------------ - -- event generation register - type EGR_Register_3 is record + type EGR_Register_4 is record -- Write-only. Update generation UG : EGR_UG_Field := 16#0#; -- Write-only. Capture/compare 1 generation @@ -1611,19 +1622,14 @@ package STM32F40x.TIM is -- unspecified Reserved_2_31 : STM32F40x.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EGR_Register_3 use record + for EGR_Register_4 use record UG at 0 range 0 .. 0; CC1G at 0 range 1 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - --------------------------- - -- CCMR1_Output_Register -- - --------------------------- - -- capture/compare mode register 1 (output mode) type CCMR1_Output_Register_2 is record -- Capture/Compare 1 selection @@ -1637,8 +1643,7 @@ package STM32F40x.TIM is -- unspecified Reserved_7_31 : STM32F40x.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR1_Output_Register_2 use record CC1S at 0 range 0 .. 1; @@ -1648,10 +1653,6 @@ package STM32F40x.TIM is Reserved_7_31 at 0 range 7 .. 31; end record; - -------------------------- - -- CCMR1_Input_Register -- - -------------------------- - -- capture/compare mode register 1 (input mode) type CCMR1_Input_Register_2 is record -- Capture/Compare 1 selection @@ -1663,8 +1664,7 @@ package STM32F40x.TIM is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR1_Input_Register_2 use record CC1S at 0 range 0 .. 1; @@ -1673,10 +1673,6 @@ package STM32F40x.TIM is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- CCER_Register -- - ------------------- - -- capture/compare enable register type CCER_Register_3 is record -- Capture/Compare 1 output enable @@ -1690,8 +1686,7 @@ package STM32F40x.TIM is -- unspecified Reserved_4_31 : STM32F40x.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCER_Register_3 use record CC1E at 0 range 0 .. 0; @@ -1701,10 +1696,6 @@ package STM32F40x.TIM is Reserved_4_31 at 0 range 4 .. 31; end record; - ----------------- - -- OR_Register -- - ----------------- - subtype OR_RMP_Field is STM32F40x.UInt2; -- option register @@ -1714,322 +1705,333 @@ package STM32F40x.TIM is -- unspecified Reserved_2_31 : STM32F40x.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OR_Register_2 use record RMP at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------ - -- CR1_Register -- - ------------------ - - -- control register 1 - type CR1_Register_3 is record - -- Counter enable - CEN : CR1_CEN_Field := 16#0#; - -- Update disable - UDIS : CR1_UDIS_Field := 16#0#; - -- Update request source - URS : CR1_URS_Field := 16#0#; - -- One-pulse mode - OPM : CR1_OPM_Field := 16#0#; - -- unspecified - Reserved_4_6 : STM32F40x.UInt3 := 16#0#; - -- Auto-reload preload enable - ARPE : CR1_ARPE_Field := 16#0#; - -- unspecified - Reserved_8_31 : STM32F40x.UInt24 := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for CR1_Register_3 use record - CEN at 0 range 0 .. 0; - UDIS at 0 range 1 .. 1; - URS at 0 range 2 .. 2; - OPM at 0 range 3 .. 3; - Reserved_4_6 at 0 range 4 .. 6; - ARPE at 0 range 7 .. 7; - Reserved_8_31 at 0 range 8 .. 31; - end record; - - ------------------- - -- DIER_Register -- - ------------------- - - -- DMA/Interrupt enable register - type DIER_Register_4 is record - -- Update interrupt enable - UIE : DIER_UIE_Field := 16#0#; - -- unspecified - Reserved_1_7 : STM32F40x.UInt7 := 16#0#; - -- Update DMA request enable - UDE : DIER_UDE_Field := 16#0#; - -- unspecified - Reserved_9_31 : STM32F40x.UInt23 := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for DIER_Register_4 use record - UIE at 0 range 0 .. 0; - Reserved_1_7 at 0 range 1 .. 7; - UDE at 0 range 8 .. 8; - Reserved_9_31 at 0 range 9 .. 31; - end record; - ----------------- - -- SR_Register -- + -- Peripherals -- ----------------- - -- status register - type SR_Register_4 is record - -- Update interrupt flag - UIF : SR_UIF_Field := 16#0#; - -- unspecified - Reserved_1_31 : STM32F40x.UInt31 := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for SR_Register_4 use record - UIF at 0 range 0 .. 0; - Reserved_1_31 at 0 range 1 .. 31; - end record; - - ------------------ - -- EGR_Register -- - ------------------ - - -- event generation register - type EGR_Register_4 is record - -- Write-only. Update generation - UG : EGR_UG_Field := 16#0#; - -- unspecified - Reserved_1_31 : STM32F40x.UInt31 := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for EGR_Register_4 use record - UG at 0 range 0 .. 0; - Reserved_1_31 at 0 range 1 .. 31; - end record; - - type CCMR1_Discriminent is - ( - Output, + type TIM1_Disc is + (Output, Input); - type CCMR1_Aliased_Register - (Disc : CCMR1_Discriminent := Output) - is record - case Disc is - when Output => - Output : CCMR1_Output_Register; - when Input => - Input : CCMR1_Input_Register; - end case; - end record - with Unchecked_Union; - - for CCMR1_Aliased_Register use record - Output at 0 range 0 .. 31; - Input at 0 range 0 .. 31; - end record; - - type CCMR2_Discriminent is - ( - Output, - Input); - - type CCMR2_Aliased_Register - (Disc : CCMR2_Discriminent := Output) - is record - case Disc is - when Output => - Output : CCMR2_Output_Register; - when Input => - Input : CCMR2_Input_Register; - end case; - end record - with Unchecked_Union; - - for CCMR2_Aliased_Register use record - Output at 0 range 0 .. 31; - Input at 0 range 0 .. 31; - end record; - - type CCMR1_Aliased_Register_1 - (Disc : CCMR1_Discriminent := Output) + -- Advanced-timers + type TIM1_Peripheral + (Discriminent : TIM1_Disc := Output) is record - case Disc is + -- control register 1 + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); + -- control register 2 + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); + -- slave mode control register + SMCR : aliased SMCR_Register; + pragma Volatile_Full_Access (SMCR); + -- DMA/Interrupt enable register + DIER : aliased DIER_Register; + pragma Volatile_Full_Access (DIER); + -- status register + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); + -- event generation register + EGR : aliased EGR_Register; + pragma Volatile_Full_Access (EGR); + -- capture/compare enable register + CCER : aliased CCER_Register; + pragma Volatile_Full_Access (CCER); + -- counter + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); + -- prescaler + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); + -- auto-reload register + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); + -- repetition counter register + RCR : aliased RCR_Register; + pragma Volatile_Full_Access (RCR); + -- capture/compare register 1 + CCR1 : aliased CCR1_Register; + pragma Volatile_Full_Access (CCR1); + -- capture/compare register 2 + CCR2 : aliased CCR2_Register; + pragma Volatile_Full_Access (CCR2); + -- capture/compare register 3 + CCR3 : aliased CCR3_Register; + pragma Volatile_Full_Access (CCR3); + -- capture/compare register 4 + CCR4 : aliased CCR4_Register; + pragma Volatile_Full_Access (CCR4); + -- break and dead-time register + BDTR : aliased BDTR_Register; + pragma Volatile_Full_Access (BDTR); + -- DMA control register + DCR : aliased DCR_Register; + pragma Volatile_Full_Access (DCR); + -- DMA address for full transfer + DMAR : aliased DMAR_Register; + pragma Volatile_Full_Access (DMAR); + case Discriminent is when Output => - Output : CCMR1_Output_Register_1; + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + pragma Volatile_Full_Access (CCMR1_Output); + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register; + pragma Volatile_Full_Access (CCMR2_Output); when Input => - Input : CCMR1_Input_Register_1; + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + pragma Volatile_Full_Access (CCMR1_Input); + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + pragma Volatile_Full_Access (CCMR2_Input); end case; end record - with Unchecked_Union; + with Unchecked_Union, Volatile; - for CCMR1_Aliased_Register_1 use record - Output at 0 range 0 .. 31; - Input at 0 range 0 .. 31; + for TIM1_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + RCR at 16#30# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + BDTR at 16#44# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; end record; - type CCMR1_Aliased_Register_2 - (Disc : CCMR1_Discriminent := Output) - is record - case Disc is - when Output => - Output : CCMR1_Output_Register_2; - when Input => - Input : CCMR1_Input_Register_2; - end case; - end record - with Unchecked_Union; + -- Advanced-timers + TIM1_Periph : aliased TIM1_Peripheral + with Import, Address => TIM1_Base; - for CCMR1_Aliased_Register_2 use record - Output at 0 range 0 .. 31; - Input at 0 range 0 .. 31; - end record; + -- Advanced-timers + TIM8_Periph : aliased TIM1_Peripheral + with Import, Address => TIM8_Base; - ----------------- - -- Peripherals -- - ----------------- + type TIM2_Disc is + (Output, + Input); -- General purpose timers - type TIM2_Peripheral is record + type TIM2_Peripheral + (Discriminent : TIM2_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register_1; + CR2 : aliased CR2_Register_1; + pragma Volatile_Full_Access (CR2); -- slave mode control register - SMCR : SMCR_Register; + SMCR : aliased SMCR_Register; + pragma Volatile_Full_Access (SMCR); -- DMA/Interrupt enable register - DIER : DIER_Register_1; + DIER : aliased DIER_Register_1; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register_1; + SR : aliased SR_Register_1; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register_1; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Aliased_Register; - -- capture/compare mode register 2 (output mode) - CCMR2 : CCMR2_Aliased_Register; + EGR : aliased EGR_Register_1; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register_1; + CCER : aliased CCER_Register_1; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register_1; + CNT : aliased CNT_Register_1; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register_1; + ARR : aliased ARR_Register_1; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register_1; + CCR1 : aliased CCR1_Register_1; + pragma Volatile_Full_Access (CCR1); -- capture/compare register 2 - CCR2 : CCR_Register_1; + CCR2 : aliased CCR2_Register_1; + pragma Volatile_Full_Access (CCR2); -- capture/compare register 3 - CCR3 : CCR_Register_1; + CCR3 : aliased CCR3_Register_1; + pragma Volatile_Full_Access (CCR3); -- capture/compare register 4 - CCR4 : CCR_Register_1; + CCR4 : aliased CCR4_Register_1; + pragma Volatile_Full_Access (CCR4); -- DMA control register - DCR : DCR_Register; + DCR : aliased DCR_Register; + pragma Volatile_Full_Access (DCR); -- DMA address for full transfer - DMAR : DMAR_Register; + DMAR : aliased DMAR_Register; + pragma Volatile_Full_Access (DMAR); -- TIM5 option register - OR_k : OR_Register; + OR_k : aliased OR_Register; + pragma Volatile_Full_Access (OR_k); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + pragma Volatile_Full_Access (CCMR1_Output); + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + pragma Volatile_Full_Access (CCMR2_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + pragma Volatile_Full_Access (CCMR1_Input); + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + pragma Volatile_Full_Access (CCMR2_Input); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for TIM2_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCMR2 at 28 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; - CCR3 at 60 range 0 .. 31; - CCR4 at 64 range 0 .. 31; - DCR at 72 range 0 .. 31; - DMAR at 76 range 0 .. 31; - OR_k at 80 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; end record; -- General purpose timers TIM2_Periph : aliased TIM2_Peripheral with Import, Address => TIM2_Base; + type TIM3_Disc is + (Output, + Input); + -- General purpose timers - type TIM3_Peripheral is record + type TIM3_Peripheral + (Discriminent : TIM3_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register_1; + CR2 : aliased CR2_Register_1; + pragma Volatile_Full_Access (CR2); -- slave mode control register - SMCR : SMCR_Register; + SMCR : aliased SMCR_Register; + pragma Volatile_Full_Access (SMCR); -- DMA/Interrupt enable register - DIER : DIER_Register_1; + DIER : aliased DIER_Register_1; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register_1; + SR : aliased SR_Register_1; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register_1; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Aliased_Register; - -- capture/compare mode register 2 (output mode) - CCMR2 : CCMR2_Aliased_Register; + EGR : aliased EGR_Register_1; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register_1; + CCER : aliased CCER_Register_1; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register_1; + CNT : aliased CNT_Register_1; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register_1; + ARR : aliased ARR_Register_1; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register_1; + CCR1 : aliased CCR1_Register_1; + pragma Volatile_Full_Access (CCR1); -- capture/compare register 2 - CCR2 : CCR_Register_1; + CCR2 : aliased CCR2_Register_1; + pragma Volatile_Full_Access (CCR2); -- capture/compare register 3 - CCR3 : CCR_Register_1; + CCR3 : aliased CCR3_Register_1; + pragma Volatile_Full_Access (CCR3); -- capture/compare register 4 - CCR4 : CCR_Register_1; + CCR4 : aliased CCR4_Register_1; + pragma Volatile_Full_Access (CCR4); -- DMA control register - DCR : DCR_Register; + DCR : aliased DCR_Register; + pragma Volatile_Full_Access (DCR); -- DMA address for full transfer - DMAR : DMAR_Register; + DMAR : aliased DMAR_Register; + pragma Volatile_Full_Access (DMAR); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + pragma Volatile_Full_Access (CCMR1_Output); + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + pragma Volatile_Full_Access (CCMR2_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + pragma Volatile_Full_Access (CCMR1_Input); + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + pragma Volatile_Full_Access (CCMR2_Input); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for TIM3_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCMR2 at 28 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; - CCR3 at 60 range 0 .. 31; - CCR4 at 64 range 0 .. 31; - DCR at 72 range 0 .. 31; - DMAR at 76 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; end record; -- General purpose timers @@ -2040,69 +2042,106 @@ package STM32F40x.TIM is TIM4_Periph : aliased TIM3_Peripheral with Import, Address => TIM4_Base; + type TIM5_Disc is + (Output, + Input); + -- General-purpose-timers - type TIM5_Peripheral is record + type TIM5_Peripheral + (Discriminent : TIM5_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register_1; + CR2 : aliased CR2_Register_1; + pragma Volatile_Full_Access (CR2); -- slave mode control register - SMCR : SMCR_Register; + SMCR : aliased SMCR_Register; + pragma Volatile_Full_Access (SMCR); -- DMA/Interrupt enable register - DIER : DIER_Register_1; + DIER : aliased DIER_Register_1; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register_1; + SR : aliased SR_Register_1; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register_1; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Aliased_Register; - -- capture/compare mode register 2 (output mode) - CCMR2 : CCMR2_Aliased_Register; + EGR : aliased EGR_Register_1; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register_1; + CCER : aliased CCER_Register_1; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register_1; + CNT : aliased CNT_Register_1; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register_1; + ARR : aliased ARR_Register_1; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register_1; + CCR1 : aliased CCR1_Register_1; + pragma Volatile_Full_Access (CCR1); -- capture/compare register 2 - CCR2 : CCR_Register_1; + CCR2 : aliased CCR2_Register_1; + pragma Volatile_Full_Access (CCR2); -- capture/compare register 3 - CCR3 : CCR_Register_1; + CCR3 : aliased CCR3_Register_1; + pragma Volatile_Full_Access (CCR3); -- capture/compare register 4 - CCR4 : CCR_Register_1; + CCR4 : aliased CCR4_Register_1; + pragma Volatile_Full_Access (CCR4); -- DMA control register - DCR : DCR_Register; + DCR : aliased DCR_Register; + pragma Volatile_Full_Access (DCR); -- DMA address for full transfer - DMAR : DMAR_Register; + DMAR : aliased DMAR_Register; + pragma Volatile_Full_Access (DMAR); -- TIM5 option register - OR_k : OR_Register_1; + OR_k : aliased OR_Register_1; + pragma Volatile_Full_Access (OR_k); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + pragma Volatile_Full_Access (CCMR1_Output); + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + pragma Volatile_Full_Access (CCMR2_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + pragma Volatile_Full_Access (CCMR1_Input); + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + pragma Volatile_Full_Access (CCMR2_Input); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for TIM5_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCMR2 at 28 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; - CCR3 at 60 range 0 .. 31; - CCR4 at 64 range 0 .. 31; - DCR at 72 range 0 .. 31; - DMAR at 76 range 0 .. 31; - OR_k at 80 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; end record; -- General-purpose-timers @@ -2112,33 +2151,41 @@ package STM32F40x.TIM is -- Basic timers type TIM6_Peripheral is record -- control register 1 - CR1 : CR1_Register_3; + CR1 : aliased CR1_Register_1; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register_2; + CR2 : aliased CR2_Register_2; + pragma Volatile_Full_Access (CR2); -- DMA/Interrupt enable register - DIER : DIER_Register_4; + DIER : aliased DIER_Register_2; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register_4; + SR : aliased SR_Register_2; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register_4; + EGR : aliased EGR_Register_2; + pragma Volatile_Full_Access (EGR); -- counter - CNT : CNT_Register; + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register; + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); end record with Volatile; for TIM6_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; end record; -- Basic timers @@ -2149,226 +2196,226 @@ package STM32F40x.TIM is TIM7_Periph : aliased TIM6_Peripheral with Import, Address => TIM7_Base; + type TIM9_Disc is + (Output, + Input); + -- General purpose timers - type TIM12_Peripheral is record + type TIM9_Peripheral + (Discriminent : TIM9_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register_1; + CR1 : aliased CR1_Register_2; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register_2; + CR2 : aliased CR2_Register_2; + pragma Volatile_Full_Access (CR2); -- slave mode control register - SMCR : SMCR_Register_1; + SMCR : aliased SMCR_Register_1; + pragma Volatile_Full_Access (SMCR); -- DMA/Interrupt enable register - DIER : DIER_Register_2; + DIER : aliased DIER_Register_3; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register_2; + SR : aliased SR_Register_3; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register_2; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Aliased_Register_1; + EGR : aliased EGR_Register_3; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register_2; + CCER : aliased CCER_Register_2; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register; + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register; + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register; + CCR1 : aliased CCR1_Register; + pragma Volatile_Full_Access (CCR1); -- capture/compare register 2 - CCR2 : CCR_Register; + CCR2 : aliased CCR2_Register; + pragma Volatile_Full_Access (CCR2); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_1; + pragma Volatile_Full_Access (CCMR1_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_1; + pragma Volatile_Full_Access (CCMR1_Input); + end case; end record - with Volatile; - - for TIM12_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; + with Unchecked_Union, Volatile; + + for TIM9_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; end record; -- General purpose timers - TIM12_Periph : aliased TIM12_Peripheral - with Import, Address => TIM12_Base; + TIM9_Periph : aliased TIM9_Peripheral + with Import, Address => TIM9_Base; -- General purpose timers - TIM9_Periph : aliased TIM12_Peripheral - with Import, Address => TIM9_Base; + TIM12_Periph : aliased TIM9_Peripheral + with Import, Address => TIM12_Base; + + type TIM10_Disc is + (Output, + Input); -- General-purpose-timers - type TIM13_Peripheral is record + type TIM10_Peripheral + (Discriminent : TIM10_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register_2; + CR1 : aliased CR1_Register_3; + pragma Volatile_Full_Access (CR1); -- DMA/Interrupt enable register - DIER : DIER_Register_3; + DIER : aliased DIER_Register_4; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register_3; + SR : aliased SR_Register_4; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register_3; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Aliased_Register_2; + EGR : aliased EGR_Register_4; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register_3; + CCER : aliased CCER_Register_3; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register; + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register; + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register; + CCR1 : aliased CCR1_Register; + pragma Volatile_Full_Access (CCR1); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_2; + pragma Volatile_Full_Access (CCMR1_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_2; + pragma Volatile_Full_Access (CCMR1_Input); + end case; end record - with Volatile; - - for TIM13_Peripheral use record - CR1 at 0 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; + with Unchecked_Union, Volatile; + + for TIM10_Peripheral use record + CR1 at 16#0# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; end record; -- General-purpose-timers - TIM13_Periph : aliased TIM13_Peripheral - with Import, Address => TIM13_Base; + TIM10_Periph : aliased TIM10_Peripheral + with Import, Address => TIM10_Base; -- General-purpose-timers - TIM14_Periph : aliased TIM13_Peripheral - with Import, Address => TIM14_Base; + TIM13_Periph : aliased TIM10_Peripheral + with Import, Address => TIM13_Base; -- General-purpose-timers - TIM10_Periph : aliased TIM13_Peripheral - with Import, Address => TIM10_Base; - - -- Advanced-timers - type TIM1_Peripheral is record - -- control register 1 - CR1 : CR1_Register; - -- control register 2 - CR2 : CR2_Register; - -- slave mode control register - SMCR : SMCR_Register; - -- DMA/Interrupt enable register - DIER : DIER_Register; - -- status register - SR : SR_Register; - -- event generation register - EGR : EGR_Register; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Aliased_Register; - -- capture/compare mode register 2 (output mode) - CCMR2 : CCMR2_Aliased_Register; - -- capture/compare enable register - CCER : CCER_Register; - -- counter - CNT : CNT_Register; - -- prescaler - PSC : PSC_Register; - -- auto-reload register - ARR : ARR_Register; - -- repetition counter register - RCR : RCR_Register; - -- capture/compare register 1 - CCR1 : CCR_Register; - -- capture/compare register 2 - CCR2 : CCR_Register; - -- capture/compare register 3 - CCR3 : CCR_Register; - -- capture/compare register 4 - CCR4 : CCR_Register; - -- break and dead-time register - BDTR : BDTR_Register; - -- DMA control register - DCR : DCR_Register; - -- DMA address for full transfer - DMAR : DMAR_Register; - end record - with Volatile; - - for TIM1_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCMR2 at 28 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - RCR at 48 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; - CCR3 at 60 range 0 .. 31; - CCR4 at 64 range 0 .. 31; - BDTR at 68 range 0 .. 31; - DCR at 72 range 0 .. 31; - DMAR at 76 range 0 .. 31; - end record; - - -- Advanced-timers - TIM1_Periph : aliased TIM1_Peripheral - with Import, Address => TIM1_Base; + TIM14_Periph : aliased TIM10_Peripheral + with Import, Address => TIM14_Base; - -- Advanced-timers - TIM8_Periph : aliased TIM1_Peripheral - with Import, Address => TIM8_Base; + type TIM11_Disc is + (Output, + Input); -- General-purpose-timers - type TIM11_Peripheral is record + type TIM11_Peripheral + (Discriminent : TIM11_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register_2; + CR1 : aliased CR1_Register_3; + pragma Volatile_Full_Access (CR1); -- DMA/Interrupt enable register - DIER : DIER_Register_3; + DIER : aliased DIER_Register_4; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register_3; + SR : aliased SR_Register_4; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register_3; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Aliased_Register_2; + EGR : aliased EGR_Register_4; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register_3; + CCER : aliased CCER_Register_3; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register; + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register; + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register; + CCR1 : aliased CCR1_Register; + pragma Volatile_Full_Access (CCR1); -- option register - OR_k : OR_Register_2; + OR_k : aliased OR_Register_2; + pragma Volatile_Full_Access (OR_k); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_2; + pragma Volatile_Full_Access (CCMR1_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_2; + pragma Volatile_Full_Access (CCMR1_Input); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for TIM11_Peripheral use record - CR1 at 0 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - OR_k at 80 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; end record; -- General-purpose-timers diff --git a/stm32f4/stm32f40x/stm32f40x-usart.ads b/stm32f4/stm32f40x/stm32f40x-usart.ads index 8c6b87e..613ee74 100644 --- a/stm32f4/stm32f40x/stm32f40x-usart.ads +++ b/stm32f4/stm32f40x/stm32f40x-usart.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.USART is -- Registers -- --------------- - ----------------- - -- SR_Register -- - ----------------- - subtype SR_PE_Field is STM32F40x.Bit; subtype SR_FE_Field is STM32F40x.Bit; subtype SR_NF_Field is STM32F40x.Bit; @@ -26,54 +23,45 @@ package STM32F40x.USART is subtype SR_TC_Field is STM32F40x.Bit; subtype SR_TXE_Field is STM32F40x.Bit; subtype SR_LBD_Field is STM32F40x.Bit; - subtype SR_CTS_Field is STM32F40x.Bit; -- Status register type SR_Register is record -- Read-only. Parity error - PE : SR_PE_Field := 16#0#; + PE : SR_PE_Field := 16#0#; -- Read-only. Framing error - FE : SR_FE_Field := 16#0#; + FE : SR_FE_Field := 16#0#; -- Read-only. Noise detected flag - NF : SR_NF_Field := 16#0#; + NF : SR_NF_Field := 16#0#; -- Read-only. Overrun error - ORE : SR_ORE_Field := 16#0#; + ORE : SR_ORE_Field := 16#0#; -- Read-only. IDLE line detected - IDLE : SR_IDLE_Field := 16#0#; + IDLE : SR_IDLE_Field := 16#0#; -- Read data register not empty - RXNE : SR_RXNE_Field := 16#0#; + RXNE : SR_RXNE_Field := 16#0#; -- Transmission complete - TC : SR_TC_Field := 16#0#; + TC : SR_TC_Field := 16#0#; -- Read-only. Transmit data register empty - TXE : SR_TXE_Field := 16#0#; + TXE : SR_TXE_Field := 16#0#; -- LIN break detection flag - LBD : SR_LBD_Field := 16#0#; - -- CTS flag - CTS : SR_CTS_Field := 16#0#; + LBD : SR_LBD_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F40x.UInt22 := 16#3000#; + Reserved_9_31 : STM32F40x.UInt23 := 16#6000#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record - PE at 0 range 0 .. 0; - FE at 0 range 1 .. 1; - NF at 0 range 2 .. 2; - ORE at 0 range 3 .. 3; - IDLE at 0 range 4 .. 4; - RXNE at 0 range 5 .. 5; - TC at 0 range 6 .. 6; - TXE at 0 range 7 .. 7; - LBD at 0 range 8 .. 8; - CTS at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + PE at 0 range 0 .. 0; + FE at 0 range 1 .. 1; + NF at 0 range 2 .. 2; + ORE at 0 range 3 .. 3; + IDLE at 0 range 4 .. 4; + RXNE at 0 range 5 .. 5; + TC at 0 range 6 .. 6; + TXE at 0 range 7 .. 7; + LBD at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - subtype DR_DR_Field is STM32F40x.UInt9; -- Data register @@ -83,18 +71,13 @@ package STM32F40x.USART is -- unspecified Reserved_9_31 : STM32F40x.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DR at 0 range 0 .. 8; Reserved_9_31 at 0 range 9 .. 31; end record; - ------------------ - -- BRR_Register -- - ------------------ - subtype BRR_DIV_Fraction_Field is STM32F40x.UInt4; subtype BRR_DIV_Mantissa_Field is STM32F40x.UInt12; @@ -105,10 +88,9 @@ package STM32F40x.USART is -- mantissa of USARTDIV DIV_Mantissa : BRR_DIV_Mantissa_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BRR_Register use record DIV_Fraction at 0 range 0 .. 3; @@ -116,10 +98,6 @@ package STM32F40x.USART is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_SBK_Field is STM32F40x.Bit; subtype CR1_RWU_Field is STM32F40x.Bit; subtype CR1_RE_Field is STM32F40x.Bit; @@ -171,10 +149,9 @@ package STM32F40x.USART is -- Oversampling mode OVER8 : CR1_OVER8_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record SBK at 0 range 0 .. 0; @@ -196,17 +173,9 @@ package STM32F40x.USART is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_ADD_Field is STM32F40x.UInt4; subtype CR2_LBDL_Field is STM32F40x.Bit; subtype CR2_LBDIE_Field is STM32F40x.Bit; - subtype CR2_LBCL_Field is STM32F40x.Bit; - subtype CR2_CPHA_Field is STM32F40x.Bit; - subtype CR2_CPOL_Field is STM32F40x.Bit; - subtype CR2_CLKEN_Field is STM32F40x.Bit; subtype CR2_STOP_Field is STM32F40x.UInt2; subtype CR2_LINEN_Field is STM32F40x.Bit; @@ -221,15 +190,7 @@ package STM32F40x.USART is -- LIN break detection interrupt enable LBDIE : CR2_LBDIE_Field := 16#0#; -- unspecified - Reserved_7_7 : STM32F40x.Bit := 16#0#; - -- Last bit clock pulse - LBCL : CR2_LBCL_Field := 16#0#; - -- Clock phase - CPHA : CR2_CPHA_Field := 16#0#; - -- Clock polarity - CPOL : CR2_CPOL_Field := 16#0#; - -- Clock enable - CLKEN : CR2_CLKEN_Field := 16#0#; + Reserved_7_11 : STM32F40x.UInt5 := 16#0#; -- STOP bits STOP : CR2_STOP_Field := 16#0#; -- LIN mode enable @@ -237,39 +198,25 @@ package STM32F40x.USART is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record ADD at 0 range 0 .. 3; Reserved_4_4 at 0 range 4 .. 4; LBDL at 0 range 5 .. 5; LBDIE at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - LBCL at 0 range 8 .. 8; - CPHA at 0 range 9 .. 9; - CPOL at 0 range 10 .. 10; - CLKEN at 0 range 11 .. 11; + Reserved_7_11 at 0 range 7 .. 11; STOP at 0 range 12 .. 13; LINEN at 0 range 14 .. 14; Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------ - -- CR3_Register -- - ------------------ - subtype CR3_EIE_Field is STM32F40x.Bit; subtype CR3_IREN_Field is STM32F40x.Bit; subtype CR3_IRLP_Field is STM32F40x.Bit; subtype CR3_HDSEL_Field is STM32F40x.Bit; - subtype CR3_NACK_Field is STM32F40x.Bit; - subtype CR3_SCEN_Field is STM32F40x.Bit; subtype CR3_DMAR_Field is STM32F40x.Bit; subtype CR3_DMAT_Field is STM32F40x.Bit; - subtype CR3_RTSE_Field is STM32F40x.Bit; - subtype CR3_CTSE_Field is STM32F40x.Bit; - subtype CR3_CTSIE_Field is STM32F40x.Bit; subtype CR3_ONEBIT_Field is STM32F40x.Bit; -- Control register 3 @@ -282,115 +229,81 @@ package STM32F40x.USART is IRLP : CR3_IRLP_Field := 16#0#; -- Half-duplex selection HDSEL : CR3_HDSEL_Field := 16#0#; - -- Smartcard NACK enable - NACK : CR3_NACK_Field := 16#0#; - -- Smartcard mode enable - SCEN : CR3_SCEN_Field := 16#0#; + -- unspecified + Reserved_4_5 : STM32F40x.UInt2 := 16#0#; -- DMA enable receiver DMAR : CR3_DMAR_Field := 16#0#; -- DMA enable transmitter DMAT : CR3_DMAT_Field := 16#0#; - -- RTS enable - RTSE : CR3_RTSE_Field := 16#0#; - -- CTS enable - CTSE : CR3_CTSE_Field := 16#0#; - -- CTS interrupt enable - CTSIE : CR3_CTSIE_Field := 16#0#; + -- unspecified + Reserved_8_10 : STM32F40x.UInt3 := 16#0#; -- One sample bit method enable ONEBIT : CR3_ONEBIT_Field := 16#0#; -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR3_Register use record EIE at 0 range 0 .. 0; IREN at 0 range 1 .. 1; IRLP at 0 range 2 .. 2; HDSEL at 0 range 3 .. 3; - NACK at 0 range 4 .. 4; - SCEN at 0 range 5 .. 5; + Reserved_4_5 at 0 range 4 .. 5; DMAR at 0 range 6 .. 6; DMAT at 0 range 7 .. 7; - RTSE at 0 range 8 .. 8; - CTSE at 0 range 9 .. 9; - CTSIE at 0 range 10 .. 10; + Reserved_8_10 at 0 range 8 .. 10; ONEBIT at 0 range 11 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------- - -- GTPR_Register -- - ------------------- - - subtype GTPR_PSC_Field is STM32F40x.Byte; - subtype GTPR_GT_Field is STM32F40x.Byte; - - -- Guard time and prescaler register - type GTPR_Register is record - -- Prescaler value - PSC : GTPR_PSC_Field := 16#0#; - -- Guard time value - GT : GTPR_GT_Field := 16#0#; - -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for GTPR_Register use record - PSC at 0 range 0 .. 7; - GT at 0 range 8 .. 15; - Reserved_16_31 at 0 range 16 .. 31; - end record; - - ----------------- - -- SR_Register -- - ----------------- + subtype SR_CTS_Field is STM32F40x.Bit; -- Status register type SR_Register_1 is record -- Read-only. Parity error - PE : SR_PE_Field := 16#0#; + PE : SR_PE_Field := 16#0#; -- Read-only. Framing error - FE : SR_FE_Field := 16#0#; + FE : SR_FE_Field := 16#0#; -- Read-only. Noise detected flag - NF : SR_NF_Field := 16#0#; + NF : SR_NF_Field := 16#0#; -- Read-only. Overrun error - ORE : SR_ORE_Field := 16#0#; + ORE : SR_ORE_Field := 16#0#; -- Read-only. IDLE line detected - IDLE : SR_IDLE_Field := 16#0#; + IDLE : SR_IDLE_Field := 16#0#; -- Read data register not empty - RXNE : SR_RXNE_Field := 16#0#; + RXNE : SR_RXNE_Field := 16#0#; -- Transmission complete - TC : SR_TC_Field := 16#0#; + TC : SR_TC_Field := 16#0#; -- Read-only. Transmit data register empty - TXE : SR_TXE_Field := 16#0#; + TXE : SR_TXE_Field := 16#0#; -- LIN break detection flag - LBD : SR_LBD_Field := 16#0#; + LBD : SR_LBD_Field := 16#0#; + -- CTS flag + CTS : SR_CTS_Field := 16#0#; -- unspecified - Reserved_9_31 : STM32F40x.UInt23 := 16#6000#; + Reserved_10_31 : STM32F40x.UInt22 := 16#3000#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register_1 use record - PE at 0 range 0 .. 0; - FE at 0 range 1 .. 1; - NF at 0 range 2 .. 2; - ORE at 0 range 3 .. 3; - IDLE at 0 range 4 .. 4; - RXNE at 0 range 5 .. 5; - TC at 0 range 6 .. 6; - TXE at 0 range 7 .. 7; - LBD at 0 range 8 .. 8; - Reserved_9_31 at 0 range 9 .. 31; + PE at 0 range 0 .. 0; + FE at 0 range 1 .. 1; + NF at 0 range 2 .. 2; + ORE at 0 range 3 .. 3; + IDLE at 0 range 4 .. 4; + RXNE at 0 range 5 .. 5; + TC at 0 range 6 .. 6; + TXE at 0 range 7 .. 7; + LBD at 0 range 8 .. 8; + CTS at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ + subtype CR2_LBCL_Field is STM32F40x.Bit; + subtype CR2_CPHA_Field is STM32F40x.Bit; + subtype CR2_CPOL_Field is STM32F40x.Bit; + subtype CR2_CLKEN_Field is STM32F40x.Bit; -- Control register 2 type CR2_Register_1 is record @@ -403,7 +316,15 @@ package STM32F40x.USART is -- LIN break detection interrupt enable LBDIE : CR2_LBDIE_Field := 16#0#; -- unspecified - Reserved_7_11 : STM32F40x.UInt5 := 16#0#; + Reserved_7_7 : STM32F40x.Bit := 16#0#; + -- Last bit clock pulse + LBCL : CR2_LBCL_Field := 16#0#; + -- Clock phase + CPHA : CR2_CPHA_Field := 16#0#; + -- Clock polarity + CPOL : CR2_CPOL_Field := 16#0#; + -- Clock enable + CLKEN : CR2_CLKEN_Field := 16#0#; -- STOP bits STOP : CR2_STOP_Field := 16#0#; -- LIN mode enable @@ -411,23 +332,28 @@ package STM32F40x.USART is -- unspecified Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register_1 use record ADD at 0 range 0 .. 3; Reserved_4_4 at 0 range 4 .. 4; LBDL at 0 range 5 .. 5; LBDIE at 0 range 6 .. 6; - Reserved_7_11 at 0 range 7 .. 11; + Reserved_7_7 at 0 range 7 .. 7; + LBCL at 0 range 8 .. 8; + CPHA at 0 range 9 .. 9; + CPOL at 0 range 10 .. 10; + CLKEN at 0 range 11 .. 11; STOP at 0 range 12 .. 13; LINEN at 0 range 14 .. 14; Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------ - -- CR3_Register -- - ------------------ + subtype CR3_NACK_Field is STM32F40x.Bit; + subtype CR3_SCEN_Field is STM32F40x.Bit; + subtype CR3_RTSE_Field is STM32F40x.Bit; + subtype CR3_CTSE_Field is STM32F40x.Bit; + subtype CR3_CTSIE_Field is STM32F40x.Bit; -- Control register 3 type CR3_Register_1 is record @@ -439,116 +365,157 @@ package STM32F40x.USART is IRLP : CR3_IRLP_Field := 16#0#; -- Half-duplex selection HDSEL : CR3_HDSEL_Field := 16#0#; - -- unspecified - Reserved_4_5 : STM32F40x.UInt2 := 16#0#; + -- Smartcard NACK enable + NACK : CR3_NACK_Field := 16#0#; + -- Smartcard mode enable + SCEN : CR3_SCEN_Field := 16#0#; -- DMA enable receiver DMAR : CR3_DMAR_Field := 16#0#; -- DMA enable transmitter DMAT : CR3_DMAT_Field := 16#0#; - -- unspecified - Reserved_8_10 : STM32F40x.UInt3 := 16#0#; + -- RTS enable + RTSE : CR3_RTSE_Field := 16#0#; + -- CTS enable + CTSE : CR3_CTSE_Field := 16#0#; + -- CTS interrupt enable + CTSIE : CR3_CTSIE_Field := 16#0#; -- One sample bit method enable ONEBIT : CR3_ONEBIT_Field := 16#0#; -- unspecified Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR3_Register_1 use record EIE at 0 range 0 .. 0; IREN at 0 range 1 .. 1; IRLP at 0 range 2 .. 2; HDSEL at 0 range 3 .. 3; - Reserved_4_5 at 0 range 4 .. 5; + NACK at 0 range 4 .. 4; + SCEN at 0 range 5 .. 5; DMAR at 0 range 6 .. 6; DMAT at 0 range 7 .. 7; - Reserved_8_10 at 0 range 8 .. 10; + RTSE at 0 range 8 .. 8; + CTSE at 0 range 9 .. 9; + CTSIE at 0 range 10 .. 10; ONEBIT at 0 range 11 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; + subtype GTPR_PSC_Field is STM32F40x.Byte; + subtype GTPR_GT_Field is STM32F40x.Byte; + + -- Guard time and prescaler register + type GTPR_Register is record + -- Prescaler value + PSC : GTPR_PSC_Field := 16#0#; + -- Guard time value + GT : GTPR_GT_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for GTPR_Register use record + PSC at 0 range 0 .. 7; + GT at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + ----------------- -- Peripherals -- ----------------- -- Universal synchronous asynchronous receiver transmitter - type USART2_Peripheral is record + type UART4_Peripheral is record -- Status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- Data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- Baud rate register - BRR : BRR_Register; + BRR : aliased BRR_Register; + pragma Volatile_Full_Access (BRR); -- Control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- Control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- Control register 3 - CR3 : CR3_Register; - -- Guard time and prescaler register - GTPR : GTPR_Register; + CR3 : aliased CR3_Register; + pragma Volatile_Full_Access (CR3); end record with Volatile; - for USART2_Peripheral use record - SR at 0 range 0 .. 31; - DR at 4 range 0 .. 31; - BRR at 8 range 0 .. 31; - CR1 at 12 range 0 .. 31; - CR2 at 16 range 0 .. 31; - CR3 at 20 range 0 .. 31; - GTPR at 24 range 0 .. 31; + for UART4_Peripheral use record + SR at 16#0# range 0 .. 31; + DR at 16#4# range 0 .. 31; + BRR at 16#8# range 0 .. 31; + CR1 at 16#C# range 0 .. 31; + CR2 at 16#10# range 0 .. 31; + CR3 at 16#14# range 0 .. 31; end record; -- Universal synchronous asynchronous receiver transmitter - USART2_Periph : aliased USART2_Peripheral - with Import, Address => USART2_Base; - - -- Universal synchronous asynchronous receiver transmitter - USART3_Periph : aliased USART2_Peripheral - with Import, Address => USART3_Base; - - -- Universal synchronous asynchronous receiver transmitter - USART1_Periph : aliased USART2_Peripheral - with Import, Address => USART1_Base; + UART4_Periph : aliased UART4_Peripheral + with Import, Address => UART4_Base; -- Universal synchronous asynchronous receiver transmitter - USART6_Periph : aliased USART2_Peripheral - with Import, Address => USART6_Base; + UART5_Periph : aliased UART4_Peripheral + with Import, Address => UART5_Base; -- Universal synchronous asynchronous receiver transmitter - type UART4_Peripheral is record + type USART1_Peripheral is record -- Status register - SR : SR_Register_1; + SR : aliased SR_Register_1; + pragma Volatile_Full_Access (SR); -- Data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- Baud rate register - BRR : BRR_Register; + BRR : aliased BRR_Register; + pragma Volatile_Full_Access (BRR); -- Control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- Control register 2 - CR2 : CR2_Register_1; + CR2 : aliased CR2_Register_1; + pragma Volatile_Full_Access (CR2); -- Control register 3 - CR3 : CR3_Register_1; + CR3 : aliased CR3_Register_1; + pragma Volatile_Full_Access (CR3); + -- Guard time and prescaler register + GTPR : aliased GTPR_Register; + pragma Volatile_Full_Access (GTPR); end record with Volatile; - for UART4_Peripheral use record - SR at 0 range 0 .. 31; - DR at 4 range 0 .. 31; - BRR at 8 range 0 .. 31; - CR1 at 12 range 0 .. 31; - CR2 at 16 range 0 .. 31; - CR3 at 20 range 0 .. 31; + for USART1_Peripheral use record + SR at 16#0# range 0 .. 31; + DR at 16#4# range 0 .. 31; + BRR at 16#8# range 0 .. 31; + CR1 at 16#C# range 0 .. 31; + CR2 at 16#10# range 0 .. 31; + CR3 at 16#14# range 0 .. 31; + GTPR at 16#18# range 0 .. 31; end record; -- Universal synchronous asynchronous receiver transmitter - UART4_Periph : aliased UART4_Peripheral - with Import, Address => UART4_Base; + USART1_Periph : aliased USART1_Peripheral + with Import, Address => USART1_Base; -- Universal synchronous asynchronous receiver transmitter - UART5_Periph : aliased UART4_Peripheral - with Import, Address => UART5_Base; + USART2_Periph : aliased USART1_Peripheral + with Import, Address => USART2_Base; + + -- Universal synchronous asynchronous receiver transmitter + USART3_Periph : aliased USART1_Peripheral + with Import, Address => USART3_Base; + + -- Universal synchronous asynchronous receiver transmitter + USART6_Periph : aliased USART1_Peripheral + with Import, Address => USART6_Base; end STM32F40x.USART; diff --git a/stm32f4/stm32f40x/stm32f40x-usb_otg_fs.ads b/stm32f4/stm32f40x/stm32f40x-usb_otg_fs.ads index f63309e..4ad1f22 100644 --- a/stm32f4/stm32f40x/stm32f40x-usb_otg_fs.ads +++ b/stm32f4/stm32f40x/stm32f40x-usb_otg_fs.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,2007 +14,1830 @@ package STM32F40x.USB_OTG_FS is -- Registers -- --------------- - ------------------------- - -- FS_GOTGCTL_Register -- - ------------------------- - - subtype FS_GOTGCTL_SRQSCS_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_SRQ_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_HNGSCS_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_HNPRQ_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_HSHNPEN_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_DHNPEN_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_CIDSTS_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_DBCT_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_ASVLD_Field is STM32F40x.Bit; - subtype FS_GOTGCTL_BSVLD_Field is STM32F40x.Bit; + subtype FS_DCFG_DSPD_Field is STM32F40x.UInt2; + subtype FS_DCFG_NZLSOHSK_Field is STM32F40x.Bit; + subtype FS_DCFG_DAD_Field is STM32F40x.UInt7; + subtype FS_DCFG_PFIVL_Field is STM32F40x.UInt2; - -- OTG_FS control and status register (OTG_FS_GOTGCTL) - type FS_GOTGCTL_Register is record - -- Read-only. Session request success - SRQSCS : FS_GOTGCTL_SRQSCS_Field := 16#0#; - -- Session request - SRQ : FS_GOTGCTL_SRQ_Field := 16#0#; - -- unspecified - Reserved_2_7 : STM32F40x.UInt6 := 16#0#; - -- Read-only. Host negotiation success - HNGSCS : FS_GOTGCTL_HNGSCS_Field := 16#0#; - -- HNP request - HNPRQ : FS_GOTGCTL_HNPRQ_Field := 16#0#; - -- Host set HNP enable - HSHNPEN : FS_GOTGCTL_HSHNPEN_Field := 16#0#; - -- Device HNP enabled - DHNPEN : FS_GOTGCTL_DHNPEN_Field := 16#1#; + -- OTG_FS device configuration register (OTG_FS_DCFG) + type FS_DCFG_Register is record + -- Device speed + DSPD : FS_DCFG_DSPD_Field := 16#0#; + -- Non-zero-length status OUT handshake + NZLSOHSK : FS_DCFG_NZLSOHSK_Field := 16#0#; -- unspecified - Reserved_12_15 : STM32F40x.UInt4 := 16#0#; - -- Read-only. Connector ID status - CIDSTS : FS_GOTGCTL_CIDSTS_Field := 16#0#; - -- Read-only. Long/short debounce time - DBCT : FS_GOTGCTL_DBCT_Field := 16#0#; - -- Read-only. A-session valid - ASVLD : FS_GOTGCTL_ASVLD_Field := 16#0#; - -- Read-only. B-session valid - BSVLD : FS_GOTGCTL_BSVLD_Field := 16#0#; + Reserved_3_3 : STM32F40x.Bit := 16#0#; + -- Device address + DAD : FS_DCFG_DAD_Field := 16#0#; + -- Periodic frame interval + PFIVL : FS_DCFG_PFIVL_Field := 16#0#; -- unspecified - Reserved_20_31 : STM32F40x.UInt12 := 16#0#; + Reserved_13_31 : STM32F40x.UInt19 := 16#1100#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GOTGCTL_Register use record - SRQSCS at 0 range 0 .. 0; - SRQ at 0 range 1 .. 1; - Reserved_2_7 at 0 range 2 .. 7; - HNGSCS at 0 range 8 .. 8; - HNPRQ at 0 range 9 .. 9; - HSHNPEN at 0 range 10 .. 10; - DHNPEN at 0 range 11 .. 11; - Reserved_12_15 at 0 range 12 .. 15; - CIDSTS at 0 range 16 .. 16; - DBCT at 0 range 17 .. 17; - ASVLD at 0 range 18 .. 18; - BSVLD at 0 range 19 .. 19; - Reserved_20_31 at 0 range 20 .. 31; + for FS_DCFG_Register use record + DSPD at 0 range 0 .. 1; + NZLSOHSK at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DAD at 0 range 4 .. 10; + PFIVL at 0 range 11 .. 12; + Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------------- - -- FS_GOTGINT_Register -- - ------------------------- - - subtype FS_GOTGINT_SEDET_Field is STM32F40x.Bit; - subtype FS_GOTGINT_SRSSCHG_Field is STM32F40x.Bit; - subtype FS_GOTGINT_HNSSCHG_Field is STM32F40x.Bit; - subtype FS_GOTGINT_HNGDET_Field is STM32F40x.Bit; - subtype FS_GOTGINT_ADTOCHG_Field is STM32F40x.Bit; - subtype FS_GOTGINT_DBCDNE_Field is STM32F40x.Bit; + subtype FS_DCTL_RWUSIG_Field is STM32F40x.Bit; + subtype FS_DCTL_SDIS_Field is STM32F40x.Bit; + subtype FS_DCTL_GINSTS_Field is STM32F40x.Bit; + subtype FS_DCTL_GONSTS_Field is STM32F40x.Bit; + subtype FS_DCTL_TCTL_Field is STM32F40x.UInt3; + subtype FS_DCTL_SGINAK_Field is STM32F40x.Bit; + subtype FS_DCTL_CGINAK_Field is STM32F40x.Bit; + subtype FS_DCTL_SGONAK_Field is STM32F40x.Bit; + subtype FS_DCTL_CGONAK_Field is STM32F40x.Bit; + subtype FS_DCTL_POPRGDNE_Field is STM32F40x.Bit; - -- OTG_FS interrupt register (OTG_FS_GOTGINT) - type FS_GOTGINT_Register is record - -- unspecified - Reserved_0_1 : STM32F40x.UInt2 := 16#0#; - -- Session end detected - SEDET : FS_GOTGINT_SEDET_Field := 16#0#; - -- unspecified - Reserved_3_7 : STM32F40x.UInt5 := 16#0#; - -- Session request success status change - SRSSCHG : FS_GOTGINT_SRSSCHG_Field := 16#0#; - -- Host negotiation success status change - HNSSCHG : FS_GOTGINT_HNSSCHG_Field := 16#0#; - -- unspecified - Reserved_10_16 : STM32F40x.UInt7 := 16#0#; - -- Host negotiation detected - HNGDET : FS_GOTGINT_HNGDET_Field := 16#0#; - -- A-device timeout change - ADTOCHG : FS_GOTGINT_ADTOCHG_Field := 16#0#; - -- Debounce done - DBCDNE : FS_GOTGINT_DBCDNE_Field := 16#0#; + -- OTG_FS device control register (OTG_FS_DCTL) + type FS_DCTL_Register is record + -- Remote wakeup signaling + RWUSIG : FS_DCTL_RWUSIG_Field := 16#0#; + -- Soft disconnect + SDIS : FS_DCTL_SDIS_Field := 16#0#; + -- Read-only. Global IN NAK status + GINSTS : FS_DCTL_GINSTS_Field := 16#0#; + -- Read-only. Global OUT NAK status + GONSTS : FS_DCTL_GONSTS_Field := 16#0#; + -- Test control + TCTL : FS_DCTL_TCTL_Field := 16#0#; + -- Set global IN NAK + SGINAK : FS_DCTL_SGINAK_Field := 16#0#; + -- Clear global IN NAK + CGINAK : FS_DCTL_CGINAK_Field := 16#0#; + -- Set global OUT NAK + SGONAK : FS_DCTL_SGONAK_Field := 16#0#; + -- Clear global OUT NAK + CGONAK : FS_DCTL_CGONAK_Field := 16#0#; + -- Power-on programming done + POPRGDNE : FS_DCTL_POPRGDNE_Field := 16#0#; -- unspecified - Reserved_20_31 : STM32F40x.UInt12 := 16#0#; + Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GOTGINT_Register use record - Reserved_0_1 at 0 range 0 .. 1; - SEDET at 0 range 2 .. 2; - Reserved_3_7 at 0 range 3 .. 7; - SRSSCHG at 0 range 8 .. 8; - HNSSCHG at 0 range 9 .. 9; - Reserved_10_16 at 0 range 10 .. 16; - HNGDET at 0 range 17 .. 17; - ADTOCHG at 0 range 18 .. 18; - DBCDNE at 0 range 19 .. 19; - Reserved_20_31 at 0 range 20 .. 31; + for FS_DCTL_Register use record + RWUSIG at 0 range 0 .. 0; + SDIS at 0 range 1 .. 1; + GINSTS at 0 range 2 .. 2; + GONSTS at 0 range 3 .. 3; + TCTL at 0 range 4 .. 6; + SGINAK at 0 range 7 .. 7; + CGINAK at 0 range 8 .. 8; + SGONAK at 0 range 9 .. 9; + CGONAK at 0 range 10 .. 10; + POPRGDNE at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------------- - -- FS_GAHBCFG_Register -- - ------------------------- - - subtype FS_GAHBCFG_GINT_Field is STM32F40x.Bit; - subtype FS_GAHBCFG_TXFELVL_Field is STM32F40x.Bit; - subtype FS_GAHBCFG_PTXFELVL_Field is STM32F40x.Bit; + subtype FS_DSTS_SUSPSTS_Field is STM32F40x.Bit; + subtype FS_DSTS_ENUMSPD_Field is STM32F40x.UInt2; + subtype FS_DSTS_EERR_Field is STM32F40x.Bit; + subtype FS_DSTS_FNSOF_Field is STM32F40x.UInt14; - -- OTG_FS AHB configuration register (OTG_FS_GAHBCFG) - type FS_GAHBCFG_Register is record - -- Global interrupt mask - GINT : FS_GAHBCFG_GINT_Field := 16#0#; + -- OTG_FS device status register (OTG_FS_DSTS) + type FS_DSTS_Register is record + -- Read-only. Suspend status + SUSPSTS : FS_DSTS_SUSPSTS_Field; + -- Read-only. Enumerated speed + ENUMSPD : FS_DSTS_ENUMSPD_Field; + -- Read-only. Erratic error + EERR : FS_DSTS_EERR_Field; -- unspecified - Reserved_1_6 : STM32F40x.UInt6 := 16#0#; - -- TxFIFO empty level - TXFELVL : FS_GAHBCFG_TXFELVL_Field := 16#0#; - -- Periodic TxFIFO empty level - PTXFELVL : FS_GAHBCFG_PTXFELVL_Field := 16#0#; + Reserved_4_7 : STM32F40x.UInt4; + -- Read-only. Frame number of the received SOF + FNSOF : FS_DSTS_FNSOF_Field; -- unspecified - Reserved_9_31 : STM32F40x.UInt23 := 16#0#; + Reserved_22_31 : STM32F40x.UInt10; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GAHBCFG_Register use record - GINT at 0 range 0 .. 0; - Reserved_1_6 at 0 range 1 .. 6; - TXFELVL at 0 range 7 .. 7; - PTXFELVL at 0 range 8 .. 8; - Reserved_9_31 at 0 range 9 .. 31; + for FS_DSTS_Register use record + SUSPSTS at 0 range 0 .. 0; + ENUMSPD at 0 range 1 .. 2; + EERR at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + FNSOF at 0 range 8 .. 21; + Reserved_22_31 at 0 range 22 .. 31; end record; - ------------------------- - -- FS_GUSBCFG_Register -- - ------------------------- - - subtype FS_GUSBCFG_TOCAL_Field is STM32F40x.UInt3; - subtype FS_GUSBCFG_PHYSEL_Field is STM32F40x.Bit; - subtype FS_GUSBCFG_SRPCAP_Field is STM32F40x.Bit; - subtype FS_GUSBCFG_HNPCAP_Field is STM32F40x.Bit; - subtype FS_GUSBCFG_TRDT_Field is STM32F40x.UInt4; - subtype FS_GUSBCFG_FHMOD_Field is STM32F40x.Bit; - subtype FS_GUSBCFG_FDMOD_Field is STM32F40x.Bit; - subtype FS_GUSBCFG_CTXPKT_Field is STM32F40x.Bit; + subtype FS_DIEPMSK_XFRCM_Field is STM32F40x.Bit; + subtype FS_DIEPMSK_EPDM_Field is STM32F40x.Bit; + subtype FS_DIEPMSK_TOM_Field is STM32F40x.Bit; + subtype FS_DIEPMSK_ITTXFEMSK_Field is STM32F40x.Bit; + subtype FS_DIEPMSK_INEPNMM_Field is STM32F40x.Bit; + subtype FS_DIEPMSK_INEPNEM_Field is STM32F40x.Bit; - -- OTG_FS USB configuration register (OTG_FS_GUSBCFG) - type FS_GUSBCFG_Register is record - -- FS timeout calibration - TOCAL : FS_GUSBCFG_TOCAL_Field := 16#0#; - -- unspecified - Reserved_3_5 : STM32F40x.UInt3 := 16#0#; - -- Write-only. Full Speed serial transceiver select - PHYSEL : FS_GUSBCFG_PHYSEL_Field := 16#0#; + -- OTG_FS device IN endpoint common interrupt mask register + -- (OTG_FS_DIEPMSK) + type FS_DIEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : FS_DIEPMSK_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : FS_DIEPMSK_EPDM_Field := 16#0#; -- unspecified - Reserved_7_7 : STM32F40x.Bit := 16#0#; - -- SRP-capable - SRPCAP : FS_GUSBCFG_SRPCAP_Field := 16#0#; - -- HNP-capable - HNPCAP : FS_GUSBCFG_HNPCAP_Field := 16#1#; - -- USB turnaround time - TRDT : FS_GUSBCFG_TRDT_Field := 16#2#; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- Timeout condition mask (Non-isochronous endpoints) + TOM : FS_DIEPMSK_TOM_Field := 16#0#; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : FS_DIEPMSK_ITTXFEMSK_Field := 16#0#; + -- IN token received with EP mismatch mask + INEPNMM : FS_DIEPMSK_INEPNMM_Field := 16#0#; + -- IN endpoint NAK effective mask + INEPNEM : FS_DIEPMSK_INEPNEM_Field := 16#0#; -- unspecified - Reserved_14_28 : STM32F40x.UInt15 := 16#0#; - -- Force host mode - FHMOD : FS_GUSBCFG_FHMOD_Field := 16#0#; - -- Force device mode - FDMOD : FS_GUSBCFG_FDMOD_Field := 16#0#; - -- Corrupt Tx packet - CTXPKT : FS_GUSBCFG_CTXPKT_Field := 16#0#; + Reserved_7_31 : STM32F40x.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GUSBCFG_Register use record - TOCAL at 0 range 0 .. 2; - Reserved_3_5 at 0 range 3 .. 5; - PHYSEL at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - SRPCAP at 0 range 8 .. 8; - HNPCAP at 0 range 9 .. 9; - TRDT at 0 range 10 .. 13; - Reserved_14_28 at 0 range 14 .. 28; - FHMOD at 0 range 29 .. 29; - FDMOD at 0 range 30 .. 30; - CTXPKT at 0 range 31 .. 31; + for FS_DIEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------------- - -- FS_GRSTCTL_Register -- - ------------------------- - - subtype FS_GRSTCTL_CSRST_Field is STM32F40x.Bit; - subtype FS_GRSTCTL_HSRST_Field is STM32F40x.Bit; - subtype FS_GRSTCTL_FCRST_Field is STM32F40x.Bit; - subtype FS_GRSTCTL_RXFFLSH_Field is STM32F40x.Bit; - subtype FS_GRSTCTL_TXFFLSH_Field is STM32F40x.Bit; - subtype FS_GRSTCTL_TXFNUM_Field is STM32F40x.UInt5; - subtype FS_GRSTCTL_AHBIDL_Field is STM32F40x.Bit; + subtype FS_DOEPMSK_XFRCM_Field is STM32F40x.Bit; + subtype FS_DOEPMSK_EPDM_Field is STM32F40x.Bit; + subtype FS_DOEPMSK_STUPM_Field is STM32F40x.Bit; + subtype FS_DOEPMSK_OTEPDM_Field is STM32F40x.Bit; - -- OTG_FS reset register (OTG_FS_GRSTCTL) - type FS_GRSTCTL_Register is record - -- Core soft reset - CSRST : FS_GRSTCTL_CSRST_Field := 16#0#; - -- HCLK soft reset - HSRST : FS_GRSTCTL_HSRST_Field := 16#0#; - -- Host frame counter reset - FCRST : FS_GRSTCTL_FCRST_Field := 16#0#; + -- OTG_FS device OUT endpoint common interrupt mask register + -- (OTG_FS_DOEPMSK) + type FS_DOEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : FS_DOEPMSK_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : FS_DOEPMSK_EPDM_Field := 16#0#; -- unspecified - Reserved_3_3 : STM32F40x.Bit := 16#0#; - -- RxFIFO flush - RXFFLSH : FS_GRSTCTL_RXFFLSH_Field := 16#0#; - -- TxFIFO flush - TXFFLSH : FS_GRSTCTL_TXFFLSH_Field := 16#0#; - -- TxFIFO number - TXFNUM : FS_GRSTCTL_TXFNUM_Field := 16#0#; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- SETUP phase done mask + STUPM : FS_DOEPMSK_STUPM_Field := 16#0#; + -- OUT token received when endpoint disabled mask + OTEPDM : FS_DOEPMSK_OTEPDM_Field := 16#0#; -- unspecified - Reserved_11_30 : STM32F40x.UInt20 := 16#40000#; - -- Read-only. AHB master idle - AHBIDL : FS_GRSTCTL_AHBIDL_Field := 16#0#; + Reserved_5_31 : STM32F40x.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GRSTCTL_Register use record - CSRST at 0 range 0 .. 0; - HSRST at 0 range 1 .. 1; - FCRST at 0 range 2 .. 2; - Reserved_3_3 at 0 range 3 .. 3; - RXFFLSH at 0 range 4 .. 4; - TXFFLSH at 0 range 5 .. 5; - TXFNUM at 0 range 6 .. 10; - Reserved_11_30 at 0 range 11 .. 30; - AHBIDL at 0 range 31 .. 31; + for FS_DOEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUPM at 0 range 3 .. 3; + OTEPDM at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------------- - -- FS_GINTSTS_Register -- - ------------------------- + subtype FS_DAINT_IEPINT_Field is STM32F40x.UInt16; + subtype FS_DAINT_OEPINT_Field is STM32F40x.UInt16; - subtype FS_GINTSTS_CMOD_Field is STM32F40x.Bit; - subtype FS_GINTSTS_MMIS_Field is STM32F40x.Bit; - subtype FS_GINTSTS_OTGINT_Field is STM32F40x.Bit; - subtype FS_GINTSTS_SOF_Field is STM32F40x.Bit; - subtype FS_GINTSTS_RXFLVL_Field is STM32F40x.Bit; - subtype FS_GINTSTS_NPTXFE_Field is STM32F40x.Bit; - subtype FS_GINTSTS_GINAKEFF_Field is STM32F40x.Bit; - subtype FS_GINTSTS_GOUTNAKEFF_Field is STM32F40x.Bit; - subtype FS_GINTSTS_ESUSP_Field is STM32F40x.Bit; - subtype FS_GINTSTS_USBSUSP_Field is STM32F40x.Bit; - subtype FS_GINTSTS_USBRST_Field is STM32F40x.Bit; - subtype FS_GINTSTS_ENUMDNE_Field is STM32F40x.Bit; - subtype FS_GINTSTS_ISOODRP_Field is STM32F40x.Bit; - subtype FS_GINTSTS_EOPF_Field is STM32F40x.Bit; - subtype FS_GINTSTS_IEPINT_Field is STM32F40x.Bit; - subtype FS_GINTSTS_OEPINT_Field is STM32F40x.Bit; - subtype FS_GINTSTS_IISOIXFR_Field is STM32F40x.Bit; - subtype FS_GINTSTS_IPXFR_INCOMPISOOUT_Field is STM32F40x.Bit; - subtype FS_GINTSTS_HPRTINT_Field is STM32F40x.Bit; - subtype FS_GINTSTS_HCINT_Field is STM32F40x.Bit; - subtype FS_GINTSTS_PTXFE_Field is STM32F40x.Bit; - subtype FS_GINTSTS_CIDSCHG_Field is STM32F40x.Bit; - subtype FS_GINTSTS_DISCINT_Field is STM32F40x.Bit; - subtype FS_GINTSTS_SRQINT_Field is STM32F40x.Bit; - subtype FS_GINTSTS_WKUPINT_Field is STM32F40x.Bit; + -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + type FS_DAINT_Register is record + -- Read-only. IN endpoint interrupt bits + IEPINT : FS_DAINT_IEPINT_Field; + -- Read-only. OUT endpoint interrupt bits + OEPINT : FS_DAINT_OEPINT_Field; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG_FS core interrupt register (OTG_FS_GINTSTS) - type FS_GINTSTS_Register is record - -- Read-only. Current mode of operation - CMOD : FS_GINTSTS_CMOD_Field := 16#0#; - -- Mode mismatch interrupt - MMIS : FS_GINTSTS_MMIS_Field := 16#0#; - -- Read-only. OTG interrupt - OTGINT : FS_GINTSTS_OTGINT_Field := 16#0#; - -- Start of frame - SOF : FS_GINTSTS_SOF_Field := 16#0#; - -- Read-only. RxFIFO non-empty - RXFLVL : FS_GINTSTS_RXFLVL_Field := 16#0#; - -- Read-only. Non-periodic TxFIFO empty - NPTXFE : FS_GINTSTS_NPTXFE_Field := 16#1#; - -- Read-only. Global IN non-periodic NAK effective - GINAKEFF : FS_GINTSTS_GINAKEFF_Field := 16#0#; - -- Read-only. Global OUT NAK effective - GOUTNAKEFF : FS_GINTSTS_GOUTNAKEFF_Field := 16#0#; - -- unspecified - Reserved_8_9 : STM32F40x.UInt2 := 16#0#; - -- Early suspend - ESUSP : FS_GINTSTS_ESUSP_Field := 16#0#; - -- USB suspend - USBSUSP : FS_GINTSTS_USBSUSP_Field := 16#0#; - -- USB reset - USBRST : FS_GINTSTS_USBRST_Field := 16#0#; - -- Enumeration done - ENUMDNE : FS_GINTSTS_ENUMDNE_Field := 16#0#; - -- Isochronous OUT packet dropped interrupt - ISOODRP : FS_GINTSTS_ISOODRP_Field := 16#0#; - -- End of periodic frame interrupt - EOPF : FS_GINTSTS_EOPF_Field := 16#0#; + for FS_DAINT_Register use record + IEPINT at 0 range 0 .. 15; + OEPINT at 0 range 16 .. 31; + end record; + + subtype FS_DAINTMSK_IEPM_Field is STM32F40x.UInt16; + subtype FS_DAINTMSK_OEPM_Field is STM32F40x.UInt16; + + -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + type FS_DAINTMSK_Register is record + -- IN EP interrupt mask bits + IEPM : FS_DAINTMSK_IEPM_Field := 16#0#; + -- OUT EP interrupt mask bits + OEPM : FS_DAINTMSK_OEPM_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for FS_DAINTMSK_Register use record + IEPM at 0 range 0 .. 15; + OEPM at 0 range 16 .. 31; + end record; + + subtype DVBUSDIS_VBUSDT_Field is STM32F40x.UInt16; + + -- OTG_FS device VBUS discharge time register + type DVBUSDIS_Register is record + -- Device VBUS discharge time + VBUSDT : DVBUSDIS_VBUSDT_Field := 16#17D7#; -- unspecified - Reserved_16_17 : STM32F40x.UInt2 := 16#0#; - -- Read-only. IN endpoint interrupt - IEPINT : FS_GINTSTS_IEPINT_Field := 16#0#; - -- Read-only. OUT endpoint interrupt - OEPINT : FS_GINTSTS_OEPINT_Field := 16#0#; - -- Incomplete isochronous IN transfer - IISOIXFR : FS_GINTSTS_IISOIXFR_Field := 16#0#; - -- Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT - -- transfer(Device mode) - IPXFR_INCOMPISOOUT : FS_GINTSTS_IPXFR_INCOMPISOOUT_Field := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DVBUSDIS_Register use record + VBUSDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DVBUSPULSE_DVBUSP_Field is STM32F40x.UInt12; + + -- OTG_FS device VBUS pulsing time register + type DVBUSPULSE_Register is record + -- Device VBUS pulsing time + DVBUSP : DVBUSPULSE_DVBUSP_Field := 16#5B8#; -- unspecified - Reserved_22_23 : STM32F40x.UInt2 := 16#0#; - -- Read-only. Host port interrupt - HPRTINT : FS_GINTSTS_HPRTINT_Field := 16#0#; - -- Read-only. Host channels interrupt - HCINT : FS_GINTSTS_HCINT_Field := 16#0#; - -- Read-only. Periodic TxFIFO empty - PTXFE : FS_GINTSTS_PTXFE_Field := 16#1#; + Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DVBUSPULSE_Register use record + DVBUSP at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype DIEPEMPMSK_INEPTXFEM_Field is STM32F40x.UInt16; + + -- OTG_FS device IN endpoint FIFO empty interrupt mask register + type DIEPEMPMSK_Register is record + -- IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM : DIEPEMPMSK_INEPTXFEM_Field := 16#0#; -- unspecified - Reserved_27_27 : STM32F40x.Bit := 16#0#; - -- Connector ID status change - CIDSCHG : FS_GINTSTS_CIDSCHG_Field := 16#0#; - -- Disconnect detected interrupt - DISCINT : FS_GINTSTS_DISCINT_Field := 16#0#; - -- Session request/new session detected interrupt - SRQINT : FS_GINTSTS_SRQINT_Field := 16#0#; - -- Resume/remote wakeup detected interrupt - WKUPINT : FS_GINTSTS_WKUPINT_Field := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GINTSTS_Register use record - CMOD at 0 range 0 .. 0; - MMIS at 0 range 1 .. 1; - OTGINT at 0 range 2 .. 2; - SOF at 0 range 3 .. 3; - RXFLVL at 0 range 4 .. 4; - NPTXFE at 0 range 5 .. 5; - GINAKEFF at 0 range 6 .. 6; - GOUTNAKEFF at 0 range 7 .. 7; - Reserved_8_9 at 0 range 8 .. 9; - ESUSP at 0 range 10 .. 10; - USBSUSP at 0 range 11 .. 11; - USBRST at 0 range 12 .. 12; - ENUMDNE at 0 range 13 .. 13; - ISOODRP at 0 range 14 .. 14; - EOPF at 0 range 15 .. 15; - Reserved_16_17 at 0 range 16 .. 17; - IEPINT at 0 range 18 .. 18; - OEPINT at 0 range 19 .. 19; - IISOIXFR at 0 range 20 .. 20; - IPXFR_INCOMPISOOUT at 0 range 21 .. 21; - Reserved_22_23 at 0 range 22 .. 23; - HPRTINT at 0 range 24 .. 24; - HCINT at 0 range 25 .. 25; - PTXFE at 0 range 26 .. 26; - Reserved_27_27 at 0 range 27 .. 27; - CIDSCHG at 0 range 28 .. 28; - DISCINT at 0 range 29 .. 29; - SRQINT at 0 range 30 .. 30; - WKUPINT at 0 range 31 .. 31; + for DIEPEMPMSK_Register use record + INEPTXFEM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------------- - -- FS_GINTMSK_Register -- - ------------------------- + subtype FS_DIEPCTL0_MPSIZ_Field is STM32F40x.UInt2; + subtype FS_DIEPCTL0_USBAEP_Field is STM32F40x.Bit; + subtype FS_DIEPCTL0_NAKSTS_Field is STM32F40x.Bit; + subtype FS_DIEPCTL0_EPTYP_Field is STM32F40x.UInt2; + subtype FS_DIEPCTL0_STALL_Field is STM32F40x.Bit; + subtype FS_DIEPCTL0_TXFNUM_Field is STM32F40x.UInt4; + subtype FS_DIEPCTL0_CNAK_Field is STM32F40x.Bit; + subtype FS_DIEPCTL0_SNAK_Field is STM32F40x.Bit; + subtype FS_DIEPCTL0_EPDIS_Field is STM32F40x.Bit; + subtype FS_DIEPCTL0_EPENA_Field is STM32F40x.Bit; - subtype FS_GINTMSK_MMISM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_OTGINT_Field is STM32F40x.Bit; - subtype FS_GINTMSK_SOFM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_RXFLVLM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_NPTXFEM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_GINAKEFFM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_GONAKEFFM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_ESUSPM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_USBSUSPM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_USBRST_Field is STM32F40x.Bit; - subtype FS_GINTMSK_ENUMDNEM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_ISOODRPM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_EOPFM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_EPMISM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_IEPINT_Field is STM32F40x.Bit; - subtype FS_GINTMSK_OEPINT_Field is STM32F40x.Bit; - subtype FS_GINTMSK_IISOIXFRM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_IPXFRM_IISOOXFRM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_PRTIM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_HCIM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_PTXFEM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_CIDSCHGM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_DISCINT_Field is STM32F40x.Bit; - subtype FS_GINTMSK_SRQIM_Field is STM32F40x.Bit; - subtype FS_GINTMSK_WUIM_Field is STM32F40x.Bit; - - -- OTG_FS interrupt mask register (OTG_FS_GINTMSK) - type FS_GINTMSK_Register is record - -- unspecified - Reserved_0_0 : STM32F40x.Bit := 16#0#; - -- Mode mismatch interrupt mask - MMISM : FS_GINTMSK_MMISM_Field := 16#0#; - -- OTG interrupt mask - OTGINT : FS_GINTMSK_OTGINT_Field := 16#0#; - -- Start of frame mask - SOFM : FS_GINTMSK_SOFM_Field := 16#0#; - -- Receive FIFO non-empty mask - RXFLVLM : FS_GINTMSK_RXFLVLM_Field := 16#0#; - -- Non-periodic TxFIFO empty mask - NPTXFEM : FS_GINTMSK_NPTXFEM_Field := 16#0#; - -- Global non-periodic IN NAK effective mask - GINAKEFFM : FS_GINTMSK_GINAKEFFM_Field := 16#0#; - -- Global OUT NAK effective mask - GONAKEFFM : FS_GINTMSK_GONAKEFFM_Field := 16#0#; + -- OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + type FS_DIEPCTL0_Register is record + -- Maximum packet size + MPSIZ : FS_DIEPCTL0_MPSIZ_Field := 16#0#; -- unspecified - Reserved_8_9 : STM32F40x.UInt2 := 16#0#; - -- Early suspend mask - ESUSPM : FS_GINTMSK_ESUSPM_Field := 16#0#; - -- USB suspend mask - USBSUSPM : FS_GINTMSK_USBSUSPM_Field := 16#0#; - -- USB reset mask - USBRST : FS_GINTMSK_USBRST_Field := 16#0#; - -- Enumeration done mask - ENUMDNEM : FS_GINTMSK_ENUMDNEM_Field := 16#0#; - -- Isochronous OUT packet dropped interrupt mask - ISOODRPM : FS_GINTMSK_ISOODRPM_Field := 16#0#; - -- End of periodic frame interrupt mask - EOPFM : FS_GINTMSK_EOPFM_Field := 16#0#; + Reserved_2_14 : STM32F40x.UInt13 := 16#0#; + -- Read-only. USB active endpoint + USBAEP : FS_DIEPCTL0_USBAEP_Field := 16#0#; -- unspecified - Reserved_16_16 : STM32F40x.Bit := 16#0#; - -- Endpoint mismatch interrupt mask - EPMISM : FS_GINTMSK_EPMISM_Field := 16#0#; - -- IN endpoints interrupt mask - IEPINT : FS_GINTMSK_IEPINT_Field := 16#0#; - -- OUT endpoints interrupt mask - OEPINT : FS_GINTMSK_OEPINT_Field := 16#0#; - -- Incomplete isochronous IN transfer mask - IISOIXFRM : FS_GINTMSK_IISOIXFRM_Field := 16#0#; - -- Incomplete periodic transfer mask(Host mode)/Incomplete isochronous - -- OUT transfer mask(Device mode) - IPXFRM_IISOOXFRM : FS_GINTMSK_IPXFRM_IISOOXFRM_Field := 16#0#; + Reserved_16_16 : STM32F40x.Bit := 16#0#; + -- Read-only. NAK status + NAKSTS : FS_DIEPCTL0_NAKSTS_Field := 16#0#; + -- Read-only. Endpoint type + EPTYP : FS_DIEPCTL0_EPTYP_Field := 16#0#; -- unspecified - Reserved_22_23 : STM32F40x.UInt2 := 16#0#; - -- Read-only. Host port interrupt mask - PRTIM : FS_GINTMSK_PRTIM_Field := 16#0#; - -- Host channels interrupt mask - HCIM : FS_GINTMSK_HCIM_Field := 16#0#; - -- Periodic TxFIFO empty mask - PTXFEM : FS_GINTMSK_PTXFEM_Field := 16#0#; + Reserved_20_20 : STM32F40x.Bit := 16#0#; + -- STALL handshake + STALL : FS_DIEPCTL0_STALL_Field := 16#0#; + -- TxFIFO number + TXFNUM : FS_DIEPCTL0_TXFNUM_Field := 16#0#; + -- Write-only. Clear NAK + CNAK : FS_DIEPCTL0_CNAK_Field := 16#0#; + -- Write-only. Set NAK + SNAK : FS_DIEPCTL0_SNAK_Field := 16#0#; -- unspecified - Reserved_27_27 : STM32F40x.Bit := 16#0#; - -- Connector ID status change mask - CIDSCHGM : FS_GINTMSK_CIDSCHGM_Field := 16#0#; - -- Disconnect detected interrupt mask - DISCINT : FS_GINTMSK_DISCINT_Field := 16#0#; - -- Session request/new session detected interrupt mask - SRQIM : FS_GINTMSK_SRQIM_Field := 16#0#; - -- Resume/remote wakeup detected interrupt mask - WUIM : FS_GINTMSK_WUIM_Field := 16#0#; + Reserved_28_29 : STM32F40x.UInt2 := 16#0#; + -- Read-only. Endpoint disable + EPDIS : FS_DIEPCTL0_EPDIS_Field := 16#0#; + -- Read-only. Endpoint enable + EPENA : FS_DIEPCTL0_EPENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GINTMSK_Register use record - Reserved_0_0 at 0 range 0 .. 0; - MMISM at 0 range 1 .. 1; - OTGINT at 0 range 2 .. 2; - SOFM at 0 range 3 .. 3; - RXFLVLM at 0 range 4 .. 4; - NPTXFEM at 0 range 5 .. 5; - GINAKEFFM at 0 range 6 .. 6; - GONAKEFFM at 0 range 7 .. 7; - Reserved_8_9 at 0 range 8 .. 9; - ESUSPM at 0 range 10 .. 10; - USBSUSPM at 0 range 11 .. 11; - USBRST at 0 range 12 .. 12; - ENUMDNEM at 0 range 13 .. 13; - ISOODRPM at 0 range 14 .. 14; - EOPFM at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - EPMISM at 0 range 17 .. 17; - IEPINT at 0 range 18 .. 18; - OEPINT at 0 range 19 .. 19; - IISOIXFRM at 0 range 20 .. 20; - IPXFRM_IISOOXFRM at 0 range 21 .. 21; - Reserved_22_23 at 0 range 22 .. 23; - PRTIM at 0 range 24 .. 24; - HCIM at 0 range 25 .. 25; - PTXFEM at 0 range 26 .. 26; - Reserved_27_27 at 0 range 27 .. 27; - CIDSCHGM at 0 range 28 .. 28; - DISCINT at 0 range 29 .. 29; - SRQIM at 0 range 30 .. 30; - WUIM at 0 range 31 .. 31; + for FS_DIEPCTL0_Register use record + MPSIZ at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + USBAEP at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + STALL at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - -------------------------------- - -- FS_GRXSTSR_Device_Register -- - -------------------------------- - - subtype FS_GRXSTSR_Device_EPNUM_Field is STM32F40x.UInt4; - subtype FS_GRXSTSR_Device_BCNT_Field is STM32F40x.UInt11; - subtype FS_GRXSTSR_Device_DPID_Field is STM32F40x.UInt2; - subtype FS_GRXSTSR_Device_PKTSTS_Field is STM32F40x.UInt4; - subtype FS_GRXSTSR_Device_FRMNUM_Field is STM32F40x.UInt4; + subtype DIEPINT_XFRC_Field is STM32F40x.Bit; + subtype DIEPINT_EPDISD_Field is STM32F40x.Bit; + subtype DIEPINT_TOC_Field is STM32F40x.Bit; + subtype DIEPINT_ITTXFE_Field is STM32F40x.Bit; + subtype DIEPINT_INEPNE_Field is STM32F40x.Bit; + subtype DIEPINT_TXFE_Field is STM32F40x.Bit; - -- OTG_FS Receive status debug read(Device mode) - type FS_GRXSTSR_Device_Register is record - -- Read-only. Endpoint number - EPNUM : FS_GRXSTSR_Device_EPNUM_Field := 16#0#; - -- Read-only. Byte count - BCNT : FS_GRXSTSR_Device_BCNT_Field := 16#0#; - -- Read-only. Data PID - DPID : FS_GRXSTSR_Device_DPID_Field := 16#0#; - -- Read-only. Packet status - PKTSTS : FS_GRXSTSR_Device_PKTSTS_Field := 16#0#; - -- Read-only. Frame number - FRMNUM : FS_GRXSTSR_Device_FRMNUM_Field := 16#0#; + -- device endpoint-x interrupt register + type DIEPINT_Register is record + -- XFRC + XFRC : DIEPINT_XFRC_Field := 16#0#; + -- EPDISD + EPDISD : DIEPINT_EPDISD_Field := 16#0#; -- unspecified - Reserved_25_31 : STM32F40x.UInt7; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- TOC + TOC : DIEPINT_TOC_Field := 16#0#; + -- ITTXFE + ITTXFE : DIEPINT_ITTXFE_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F40x.Bit := 16#0#; + -- INEPNE + INEPNE : DIEPINT_INEPNE_Field := 16#0#; + -- Read-only. TXFE + TXFE : DIEPINT_TXFE_Field := 16#1#; + -- unspecified + Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GRXSTSR_Device_Register use record - EPNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - FRMNUM at 0 range 21 .. 24; - Reserved_25_31 at 0 range 25 .. 31; + for DIEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOC at 0 range 3 .. 3; + ITTXFE at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + INEPNE at 0 range 6 .. 6; + TXFE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------------------ - -- FS_GRXSTSR_Host_Register -- - ------------------------------ - - subtype FS_GRXSTSR_Host_EPNUM_Field is STM32F40x.UInt4; - subtype FS_GRXSTSR_Host_BCNT_Field is STM32F40x.UInt11; - subtype FS_GRXSTSR_Host_DPID_Field is STM32F40x.UInt2; - subtype FS_GRXSTSR_Host_PKTSTS_Field is STM32F40x.UInt4; - subtype FS_GRXSTSR_Host_FRMNUM_Field is STM32F40x.UInt4; + subtype DIEPTSIZ0_XFRSIZ_Field is STM32F40x.UInt7; + subtype DIEPTSIZ0_PKTCNT_Field is STM32F40x.UInt2; - -- OTG_FS Receive status debug read(Host mode) - type FS_GRXSTSR_Host_Register is record - -- Read-only. Endpoint number - EPNUM : FS_GRXSTSR_Host_EPNUM_Field := 16#0#; - -- Read-only. Byte count - BCNT : FS_GRXSTSR_Host_BCNT_Field := 16#0#; - -- Read-only. Data PID - DPID : FS_GRXSTSR_Host_DPID_Field := 16#0#; - -- Read-only. Packet status - PKTSTS : FS_GRXSTSR_Host_PKTSTS_Field := 16#0#; - -- Read-only. Frame number - FRMNUM : FS_GRXSTSR_Host_FRMNUM_Field := 16#0#; + -- device endpoint-0 transfer size register + type DIEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : DIEPTSIZ0_XFRSIZ_Field := 16#0#; -- unspecified - Reserved_25_31 : STM32F40x.UInt7; + Reserved_7_18 : STM32F40x.UInt12 := 16#0#; + -- Packet count + PKTCNT : DIEPTSIZ0_PKTCNT_Field := 16#0#; + -- unspecified + Reserved_21_31 : STM32F40x.UInt11 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GRXSTSR_Host_Register use record - EPNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - FRMNUM at 0 range 21 .. 24; - Reserved_25_31 at 0 range 25 .. 31; + for DIEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------------- - -- FS_GRXFSIZ_Register -- - ------------------------- - - subtype FS_GRXFSIZ_RXFD_Field is STM32F40x.Short; + subtype DTXFSTS_INEPTFSAV_Field is STM32F40x.UInt16; - -- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) - type FS_GRXFSIZ_Register is record - -- RxFIFO depth - RXFD : FS_GRXFSIZ_RXFD_Field := 16#200#; + -- OTG_FS device IN endpoint transmit FIFO status register + type DTXFSTS_Register is record + -- Read-only. IN endpoint TxFIFO space available + INEPTFSAV : DTXFSTS_INEPTFSAV_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GRXFSIZ_Register use record - RXFD at 0 range 0 .. 15; + for DTXFSTS_Register use record + INEPTFSAV at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------------------- - -- FS_GNPTXFSIZ_Device_Register -- - ---------------------------------- - - subtype FS_GNPTXFSIZ_Device_TX0FSA_Field is STM32F40x.Short; - subtype FS_GNPTXFSIZ_Device_TX0FD_Field is STM32F40x.Short; - - -- OTG_FS non-periodic transmit FIFO size register (Device mode) - type FS_GNPTXFSIZ_Device_Register is record - -- Endpoint 0 transmit RAM start address - TX0FSA : FS_GNPTXFSIZ_Device_TX0FSA_Field := 16#200#; - -- Endpoint 0 TxFIFO depth - TX0FD : FS_GNPTXFSIZ_Device_TX0FD_Field := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for FS_GNPTXFSIZ_Device_Register use record - TX0FSA at 0 range 0 .. 15; - TX0FD at 0 range 16 .. 31; - end record; - - -------------------------------- - -- FS_GNPTXFSIZ_Host_Register -- - -------------------------------- - - subtype FS_GNPTXFSIZ_Host_NPTXFSA_Field is STM32F40x.Short; - subtype FS_GNPTXFSIZ_Host_NPTXFD_Field is STM32F40x.Short; + subtype DIEPCTL1_MPSIZ_Field is STM32F40x.UInt11; + subtype DIEPCTL1_USBAEP_Field is STM32F40x.Bit; + subtype DIEPCTL1_EONUM_DPID_Field is STM32F40x.Bit; + subtype DIEPCTL1_NAKSTS_Field is STM32F40x.Bit; + subtype DIEPCTL1_EPTYP_Field is STM32F40x.UInt2; + subtype DIEPCTL1_Stall_Field is STM32F40x.Bit; + subtype DIEPCTL1_TXFNUM_Field is STM32F40x.UInt4; + subtype DIEPCTL1_CNAK_Field is STM32F40x.Bit; + subtype DIEPCTL1_SNAK_Field is STM32F40x.Bit; + subtype DIEPCTL1_SD0PID_SEVNFRM_Field is STM32F40x.Bit; + subtype DIEPCTL1_SODDFRM_SD1PID_Field is STM32F40x.Bit; + subtype DIEPCTL1_EPDIS_Field is STM32F40x.Bit; + subtype DIEPCTL1_EPENA_Field is STM32F40x.Bit; - -- OTG_FS non-periodic transmit FIFO size register (Host mode) - type FS_GNPTXFSIZ_Host_Register is record - -- Non-periodic transmit RAM start address - NPTXFSA : FS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; - -- Non-periodic TxFIFO depth - NPTXFD : FS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; + -- OTG device endpoint-1 control register + type DIEPCTL1_Register is record + -- MPSIZ + MPSIZ : DIEPCTL1_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : STM32F40x.UInt4 := 16#0#; + -- USBAEP + USBAEP : DIEPCTL1_USBAEP_Field := 16#0#; + -- Read-only. EONUM/DPID + EONUM_DPID : DIEPCTL1_EONUM_DPID_Field := 16#0#; + -- Read-only. NAKSTS + NAKSTS : DIEPCTL1_NAKSTS_Field := 16#0#; + -- EPTYP + EPTYP : DIEPCTL1_EPTYP_Field := 16#0#; + -- unspecified + Reserved_20_20 : STM32F40x.Bit := 16#0#; + -- Stall + Stall : DIEPCTL1_Stall_Field := 16#0#; + -- TXFNUM + TXFNUM : DIEPCTL1_TXFNUM_Field := 16#0#; + -- Write-only. CNAK + CNAK : DIEPCTL1_CNAK_Field := 16#0#; + -- Write-only. SNAK + SNAK : DIEPCTL1_SNAK_Field := 16#0#; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : DIEPCTL1_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. SODDFRM/SD1PID + SODDFRM_SD1PID : DIEPCTL1_SODDFRM_SD1PID_Field := 16#0#; + -- EPDIS + EPDIS : DIEPCTL1_EPDIS_Field := 16#0#; + -- EPENA + EPENA : DIEPCTL1_EPENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GNPTXFSIZ_Host_Register use record - NPTXFSA at 0 range 0 .. 15; - NPTXFD at 0 range 16 .. 31; + for DIEPCTL1_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM_SD1PID at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - -------------------------- - -- FS_GNPTXSTS_Register -- - -------------------------- - - subtype FS_GNPTXSTS_NPTXFSAV_Field is STM32F40x.Short; - subtype FS_GNPTXSTS_NPTQXSAV_Field is STM32F40x.Byte; - subtype FS_GNPTXSTS_NPTXQTOP_Field is STM32F40x.UInt7; + subtype DIEPTSIZ_XFRSIZ_Field is STM32F40x.UInt19; + subtype DIEPTSIZ_PKTCNT_Field is STM32F40x.UInt10; + subtype DIEPTSIZ_MCNT_Field is STM32F40x.UInt2; - -- OTG_FS non-periodic transmit FIFO/queue status register - -- (OTG_FS_GNPTXSTS) - type FS_GNPTXSTS_Register is record - -- Read-only. Non-periodic TxFIFO space available - NPTXFSAV : FS_GNPTXSTS_NPTXFSAV_Field := 16#200#; - -- Read-only. Non-periodic transmit request queue space available - NPTQXSAV : FS_GNPTXSTS_NPTQXSAV_Field := 16#8#; - -- Read-only. Top of the non-periodic transmit request queue - NPTXQTOP : FS_GNPTXSTS_NPTXQTOP_Field := 16#0#; + -- device endpoint-1 transfer size register + type DIEPTSIZ_Register is record + -- Transfer size + XFRSIZ : DIEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : DIEPTSIZ_PKTCNT_Field := 16#0#; + -- Multi count + MCNT : DIEPTSIZ_MCNT_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F40x.Bit; + Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GNPTXSTS_Register use record - NPTXFSAV at 0 range 0 .. 15; - NPTQXSAV at 0 range 16 .. 23; - NPTXQTOP at 0 range 24 .. 30; + for DIEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + MCNT at 0 range 29 .. 30; Reserved_31_31 at 0 range 31 .. 31; end record; - ----------------------- - -- FS_GCCFG_Register -- - ----------------------- - - subtype FS_GCCFG_PWRDWN_Field is STM32F40x.Bit; - subtype FS_GCCFG_VBUSASEN_Field is STM32F40x.Bit; - subtype FS_GCCFG_VBUSBSEN_Field is STM32F40x.Bit; - subtype FS_GCCFG_SOFOUTEN_Field is STM32F40x.Bit; - - -- OTG_FS general core configuration register (OTG_FS_GCCFG) - type FS_GCCFG_Register is record - -- unspecified - Reserved_0_15 : STM32F40x.Short := 16#0#; - -- Power down - PWRDWN : FS_GCCFG_PWRDWN_Field := 16#0#; + subtype DIEPCTL_MPSIZ_Field is STM32F40x.UInt11; + subtype DIEPCTL_USBAEP_Field is STM32F40x.Bit; + subtype DIEPCTL_EONUM_DPID_Field is STM32F40x.Bit; + subtype DIEPCTL_NAKSTS_Field is STM32F40x.Bit; + subtype DIEPCTL_EPTYP_Field is STM32F40x.UInt2; + subtype DIEPCTL_Stall_Field is STM32F40x.Bit; + subtype DIEPCTL_TXFNUM_Field is STM32F40x.UInt4; + subtype DIEPCTL_CNAK_Field is STM32F40x.Bit; + subtype DIEPCTL_SNAK_Field is STM32F40x.Bit; + subtype DIEPCTL_SD0PID_SEVNFRM_Field is STM32F40x.Bit; + subtype DIEPCTL_SODDFRM_Field is STM32F40x.Bit; + subtype DIEPCTL_EPDIS_Field is STM32F40x.Bit; + subtype DIEPCTL_EPENA_Field is STM32F40x.Bit; + + -- OTG device endpoint-2 control register + type DIEPCTL_Register is record + -- MPSIZ + MPSIZ : DIEPCTL_MPSIZ_Field := 16#0#; -- unspecified - Reserved_17_17 : STM32F40x.Bit := 16#0#; - -- Enable the VBUS sensing device - VBUSASEN : FS_GCCFG_VBUSASEN_Field := 16#0#; - -- Enable the VBUS sensing device - VBUSBSEN : FS_GCCFG_VBUSBSEN_Field := 16#0#; - -- SOF output enable - SOFOUTEN : FS_GCCFG_SOFOUTEN_Field := 16#0#; + Reserved_11_14 : STM32F40x.UInt4 := 16#0#; + -- USBAEP + USBAEP : DIEPCTL_USBAEP_Field := 16#0#; + -- Read-only. EONUM/DPID + EONUM_DPID : DIEPCTL_EONUM_DPID_Field := 16#0#; + -- Read-only. NAKSTS + NAKSTS : DIEPCTL_NAKSTS_Field := 16#0#; + -- EPTYP + EPTYP : DIEPCTL_EPTYP_Field := 16#0#; -- unspecified - Reserved_21_31 : STM32F40x.UInt11 := 16#0#; + Reserved_20_20 : STM32F40x.Bit := 16#0#; + -- Stall + Stall : DIEPCTL_Stall_Field := 16#0#; + -- TXFNUM + TXFNUM : DIEPCTL_TXFNUM_Field := 16#0#; + -- Write-only. CNAK + CNAK : DIEPCTL_CNAK_Field := 16#0#; + -- Write-only. SNAK + SNAK : DIEPCTL_SNAK_Field := 16#0#; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : DIEPCTL_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. SODDFRM + SODDFRM : DIEPCTL_SODDFRM_Field := 16#0#; + -- EPDIS + EPDIS : DIEPCTL_EPDIS_Field := 16#0#; + -- EPENA + EPENA : DIEPCTL_EPENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GCCFG_Register use record - Reserved_0_15 at 0 range 0 .. 15; - PWRDWN at 0 range 16 .. 16; - Reserved_17_17 at 0 range 17 .. 17; - VBUSASEN at 0 range 18 .. 18; - VBUSBSEN at 0 range 19 .. 19; - SOFOUTEN at 0 range 20 .. 20; - Reserved_21_31 at 0 range 21 .. 31; + for DIEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - -------------------------- - -- FS_HPTXFSIZ_Register -- - -------------------------- - - subtype FS_HPTXFSIZ_PTXSA_Field is STM32F40x.Short; - subtype FS_HPTXFSIZ_PTXFSIZ_Field is STM32F40x.Short; + subtype DOEPCTL0_MPSIZ_Field is STM32F40x.UInt2; + subtype DOEPCTL0_USBAEP_Field is STM32F40x.Bit; + subtype DOEPCTL0_NAKSTS_Field is STM32F40x.Bit; + subtype DOEPCTL0_EPTYP_Field is STM32F40x.UInt2; + subtype DOEPCTL0_SNPM_Field is STM32F40x.Bit; + subtype DOEPCTL0_Stall_Field is STM32F40x.Bit; + subtype DOEPCTL0_CNAK_Field is STM32F40x.Bit; + subtype DOEPCTL0_SNAK_Field is STM32F40x.Bit; + subtype DOEPCTL0_EPDIS_Field is STM32F40x.Bit; + subtype DOEPCTL0_EPENA_Field is STM32F40x.Bit; - -- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) - type FS_HPTXFSIZ_Register is record - -- Host periodic TxFIFO start address - PTXSA : FS_HPTXFSIZ_PTXSA_Field := 16#600#; - -- Host periodic TxFIFO depth - PTXFSIZ : FS_HPTXFSIZ_PTXFSIZ_Field := 16#200#; + -- device endpoint-0 control register + type DOEPCTL0_Register is record + -- Read-only. MPSIZ + MPSIZ : DOEPCTL0_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_2_14 : STM32F40x.UInt13 := 16#0#; + -- Read-only. USBAEP + USBAEP : DOEPCTL0_USBAEP_Field := 16#1#; + -- unspecified + Reserved_16_16 : STM32F40x.Bit := 16#0#; + -- Read-only. NAKSTS + NAKSTS : DOEPCTL0_NAKSTS_Field := 16#0#; + -- Read-only. EPTYP + EPTYP : DOEPCTL0_EPTYP_Field := 16#0#; + -- SNPM + SNPM : DOEPCTL0_SNPM_Field := 16#0#; + -- Stall + Stall : DOEPCTL0_Stall_Field := 16#0#; + -- unspecified + Reserved_22_25 : STM32F40x.UInt4 := 16#0#; + -- Write-only. CNAK + CNAK : DOEPCTL0_CNAK_Field := 16#0#; + -- Write-only. SNAK + SNAK : DOEPCTL0_SNAK_Field := 16#0#; + -- unspecified + Reserved_28_29 : STM32F40x.UInt2 := 16#0#; + -- Read-only. EPDIS + EPDIS : DOEPCTL0_EPDIS_Field := 16#0#; + -- Write-only. EPENA + EPENA : DOEPCTL0_EPENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HPTXFSIZ_Register use record - PTXSA at 0 range 0 .. 15; - PTXFSIZ at 0 range 16 .. 31; + for DOEPCTL0_Register use record + MPSIZ at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + USBAEP at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - ------------------------- - -- FS_DIEPTXF_Register -- - ------------------------- - - subtype FS_DIEPTXF1_INEPTXSA_Field is STM32F40x.Short; - subtype FS_DIEPTXF1_INEPTXFD_Field is STM32F40x.Short; + subtype DOEPINT_XFRC_Field is STM32F40x.Bit; + subtype DOEPINT_EPDISD_Field is STM32F40x.Bit; + subtype DOEPINT_STUP_Field is STM32F40x.Bit; + subtype DOEPINT_OTEPDIS_Field is STM32F40x.Bit; + subtype DOEPINT_B2BSTUP_Field is STM32F40x.Bit; - -- OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) - type FS_DIEPTXF_Register is record - -- IN endpoint FIFO2 transmit RAM start address - INEPTXSA : FS_DIEPTXF1_INEPTXSA_Field := 16#400#; - -- IN endpoint TxFIFO depth - INEPTXFD : FS_DIEPTXF1_INEPTXFD_Field := 16#200#; + -- device endpoint-0 interrupt register + type DOEPINT_Register is record + -- XFRC + XFRC : DOEPINT_XFRC_Field := 16#0#; + -- EPDISD + EPDISD : DOEPINT_EPDISD_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- STUP + STUP : DOEPINT_STUP_Field := 16#0#; + -- OTEPDIS + OTEPDIS : DOEPINT_OTEPDIS_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F40x.Bit := 16#0#; + -- B2BSTUP + B2BSTUP : DOEPINT_B2BSTUP_Field := 16#0#; + -- unspecified + Reserved_7_31 : STM32F40x.UInt25 := 16#1#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DIEPTXF_Register use record - INEPTXSA at 0 range 0 .. 15; - INEPTXFD at 0 range 16 .. 31; + for DOEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUP at 0 range 3 .. 3; + OTEPDIS at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + B2BSTUP at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; end record; - ---------------------- - -- FS_HCFG_Register -- - ---------------------- - - subtype FS_HCFG_FSLSPCS_Field is STM32F40x.UInt2; - subtype FS_HCFG_FSLSS_Field is STM32F40x.Bit; + subtype DOEPTSIZ0_XFRSIZ_Field is STM32F40x.UInt7; + subtype DOEPTSIZ0_PKTCNT_Field is STM32F40x.Bit; + subtype DOEPTSIZ0_STUPCNT_Field is STM32F40x.UInt2; - -- OTG_FS host configuration register (OTG_FS_HCFG) - type FS_HCFG_Register is record - -- FS/LS PHY clock select - FSLSPCS : FS_HCFG_FSLSPCS_Field := 16#0#; - -- Read-only. FS- and LS-only support - FSLSS : FS_HCFG_FSLSS_Field := 16#0#; + -- device OUT endpoint-0 transfer size register + type DOEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : DOEPTSIZ0_XFRSIZ_Field := 16#0#; -- unspecified - Reserved_3_31 : STM32F40x.UInt29 := 16#0#; + Reserved_7_18 : STM32F40x.UInt12 := 16#0#; + -- Packet count + PKTCNT : DOEPTSIZ0_PKTCNT_Field := 16#0#; + -- unspecified + Reserved_20_28 : STM32F40x.UInt9 := 16#0#; + -- SETUP packet count + STUPCNT : DOEPTSIZ0_STUPCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HCFG_Register use record - FSLSPCS at 0 range 0 .. 1; - FSLSS at 0 range 2 .. 2; - Reserved_3_31 at 0 range 3 .. 31; + for DOEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 19; + Reserved_20_28 at 0 range 20 .. 28; + STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------- - -- HFIR_Register -- - ------------------- + subtype DOEPCTL_MPSIZ_Field is STM32F40x.UInt11; + subtype DOEPCTL_USBAEP_Field is STM32F40x.Bit; + subtype DOEPCTL_EONUM_DPID_Field is STM32F40x.Bit; + subtype DOEPCTL_NAKSTS_Field is STM32F40x.Bit; + subtype DOEPCTL_EPTYP_Field is STM32F40x.UInt2; + subtype DOEPCTL_SNPM_Field is STM32F40x.Bit; + subtype DOEPCTL_Stall_Field is STM32F40x.Bit; + subtype DOEPCTL_CNAK_Field is STM32F40x.Bit; + subtype DOEPCTL_SNAK_Field is STM32F40x.Bit; + subtype DOEPCTL_SD0PID_SEVNFRM_Field is STM32F40x.Bit; + subtype DOEPCTL_SODDFRM_Field is STM32F40x.Bit; + subtype DOEPCTL_EPDIS_Field is STM32F40x.Bit; + subtype DOEPCTL_EPENA_Field is STM32F40x.Bit; - subtype HFIR_FRIVL_Field is STM32F40x.Short; - - -- OTG_FS Host frame interval register - type HFIR_Register is record - -- Frame interval - FRIVL : HFIR_FRIVL_Field := 16#EA60#; + -- device endpoint-1 control register + type DOEPCTL_Register is record + -- MPSIZ + MPSIZ : DOEPCTL_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : STM32F40x.UInt4 := 16#0#; + -- USBAEP + USBAEP : DOEPCTL_USBAEP_Field := 16#0#; + -- Read-only. EONUM/DPID + EONUM_DPID : DOEPCTL_EONUM_DPID_Field := 16#0#; + -- Read-only. NAKSTS + NAKSTS : DOEPCTL_NAKSTS_Field := 16#0#; + -- EPTYP + EPTYP : DOEPCTL_EPTYP_Field := 16#0#; + -- SNPM + SNPM : DOEPCTL_SNPM_Field := 16#0#; + -- Stall + Stall : DOEPCTL_Stall_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_22_25 : STM32F40x.UInt4 := 16#0#; + -- Write-only. CNAK + CNAK : DOEPCTL_CNAK_Field := 16#0#; + -- Write-only. SNAK + SNAK : DOEPCTL_SNAK_Field := 16#0#; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : DOEPCTL_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. SODDFRM + SODDFRM : DOEPCTL_SODDFRM_Field := 16#0#; + -- EPDIS + EPDIS : DOEPCTL_EPDIS_Field := 16#0#; + -- EPENA + EPENA : DOEPCTL_EPENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HFIR_Register use record - FRIVL at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for DOEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - ----------------------- - -- FS_HFNUM_Register -- - ----------------------- + subtype DOEPTSIZ_XFRSIZ_Field is STM32F40x.UInt19; + subtype DOEPTSIZ_PKTCNT_Field is STM32F40x.UInt10; + subtype DOEPTSIZ_RXDPID_STUPCNT_Field is STM32F40x.UInt2; - subtype FS_HFNUM_FRNUM_Field is STM32F40x.Short; - subtype FS_HFNUM_FTREM_Field is STM32F40x.Short; - - -- OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) - type FS_HFNUM_Register is record - -- Read-only. Frame number - FRNUM : FS_HFNUM_FRNUM_Field := 16#3FFF#; - -- Read-only. Frame time remaining - FTREM : FS_HFNUM_FTREM_Field := 16#0#; + -- device OUT endpoint-1 transfer size register + type DOEPTSIZ_Register is record + -- Transfer size + XFRSIZ : DOEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : DOEPTSIZ_PKTCNT_Field := 16#0#; + -- Received data PID/SETUP packet count + RXDPID_STUPCNT : DOEPTSIZ_RXDPID_STUPCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HFNUM_Register use record - FRNUM at 0 range 0 .. 15; - FTREM at 0 range 16 .. 31; + for DOEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + RXDPID_STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------- - -- FS_HPTXSTS_Register -- - ------------------------- - - subtype FS_HPTXSTS_PTXFSAVL_Field is STM32F40x.Short; - subtype FS_HPTXSTS_PTXQSAV_Field is STM32F40x.Byte; - subtype FS_HPTXSTS_PTXQTOP_Field is STM32F40x.Byte; + subtype FS_GOTGCTL_SRQSCS_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_SRQ_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_HNGSCS_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_HNPRQ_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_HSHNPEN_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_DHNPEN_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_CIDSTS_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_DBCT_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_ASVLD_Field is STM32F40x.Bit; + subtype FS_GOTGCTL_BSVLD_Field is STM32F40x.Bit; - -- OTG_FS_Host periodic transmit FIFO/queue status register - -- (OTG_FS_HPTXSTS) - type FS_HPTXSTS_Register is record - -- Periodic transmit data FIFO space available - PTXFSAVL : FS_HPTXSTS_PTXFSAVL_Field := 16#100#; - -- Read-only. Periodic transmit request queue space available - PTXQSAV : FS_HPTXSTS_PTXQSAV_Field := 16#8#; - -- Read-only. Top of the periodic transmit request queue - PTXQTOP : FS_HPTXSTS_PTXQTOP_Field := 16#0#; + -- OTG_FS control and status register (OTG_FS_GOTGCTL) + type FS_GOTGCTL_Register is record + -- Read-only. Session request success + SRQSCS : FS_GOTGCTL_SRQSCS_Field := 16#0#; + -- Session request + SRQ : FS_GOTGCTL_SRQ_Field := 16#0#; + -- unspecified + Reserved_2_7 : STM32F40x.UInt6 := 16#0#; + -- Read-only. Host negotiation success + HNGSCS : FS_GOTGCTL_HNGSCS_Field := 16#0#; + -- HNP request + HNPRQ : FS_GOTGCTL_HNPRQ_Field := 16#0#; + -- Host set HNP enable + HSHNPEN : FS_GOTGCTL_HSHNPEN_Field := 16#0#; + -- Device HNP enabled + DHNPEN : FS_GOTGCTL_DHNPEN_Field := 16#1#; + -- unspecified + Reserved_12_15 : STM32F40x.UInt4 := 16#0#; + -- Read-only. Connector ID status + CIDSTS : FS_GOTGCTL_CIDSTS_Field := 16#0#; + -- Read-only. Long/short debounce time + DBCT : FS_GOTGCTL_DBCT_Field := 16#0#; + -- Read-only. A-session valid + ASVLD : FS_GOTGCTL_ASVLD_Field := 16#0#; + -- Read-only. B-session valid + BSVLD : FS_GOTGCTL_BSVLD_Field := 16#0#; + -- unspecified + Reserved_20_31 : STM32F40x.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HPTXSTS_Register use record - PTXFSAVL at 0 range 0 .. 15; - PTXQSAV at 0 range 16 .. 23; - PTXQTOP at 0 range 24 .. 31; + for FS_GOTGCTL_Register use record + SRQSCS at 0 range 0 .. 0; + SRQ at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + HNGSCS at 0 range 8 .. 8; + HNPRQ at 0 range 9 .. 9; + HSHNPEN at 0 range 10 .. 10; + DHNPEN at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + CIDSTS at 0 range 16 .. 16; + DBCT at 0 range 17 .. 17; + ASVLD at 0 range 18 .. 18; + BSVLD at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - -------------------- - -- HAINT_Register -- - -------------------- - - subtype HAINT_HAINT_Field is STM32F40x.Short; + subtype FS_GOTGINT_SEDET_Field is STM32F40x.Bit; + subtype FS_GOTGINT_SRSSCHG_Field is STM32F40x.Bit; + subtype FS_GOTGINT_HNSSCHG_Field is STM32F40x.Bit; + subtype FS_GOTGINT_HNGDET_Field is STM32F40x.Bit; + subtype FS_GOTGINT_ADTOCHG_Field is STM32F40x.Bit; + subtype FS_GOTGINT_DBCDNE_Field is STM32F40x.Bit; - -- OTG_FS Host all channels interrupt register - type HAINT_Register is record - -- Read-only. Channel interrupts - HAINT : HAINT_HAINT_Field := 16#0#; + -- OTG_FS interrupt register (OTG_FS_GOTGINT) + type FS_GOTGINT_Register is record + -- unspecified + Reserved_0_1 : STM32F40x.UInt2 := 16#0#; + -- Session end detected + SEDET : FS_GOTGINT_SEDET_Field := 16#0#; + -- unspecified + Reserved_3_7 : STM32F40x.UInt5 := 16#0#; + -- Session request success status change + SRSSCHG : FS_GOTGINT_SRSSCHG_Field := 16#0#; + -- Host negotiation success status change + HNSSCHG : FS_GOTGINT_HNSSCHG_Field := 16#0#; + -- unspecified + Reserved_10_16 : STM32F40x.UInt7 := 16#0#; + -- Host negotiation detected + HNGDET : FS_GOTGINT_HNGDET_Field := 16#0#; + -- A-device timeout change + ADTOCHG : FS_GOTGINT_ADTOCHG_Field := 16#0#; + -- Debounce done + DBCDNE : FS_GOTGINT_DBCDNE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_20_31 : STM32F40x.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HAINT_Register use record - HAINT at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_GOTGINT_Register use record + Reserved_0_1 at 0 range 0 .. 1; + SEDET at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + SRSSCHG at 0 range 8 .. 8; + HNSSCHG at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + HNGDET at 0 range 17 .. 17; + ADTOCHG at 0 range 18 .. 18; + DBCDNE at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------------- - -- HAINTMSK_Register -- - ----------------------- - - subtype HAINTMSK_HAINTM_Field is STM32F40x.Short; + subtype FS_GAHBCFG_GINT_Field is STM32F40x.Bit; + subtype FS_GAHBCFG_TXFELVL_Field is STM32F40x.Bit; + subtype FS_GAHBCFG_PTXFELVL_Field is STM32F40x.Bit; - -- OTG_FS host all channels interrupt mask register - type HAINTMSK_Register is record - -- Channel interrupt mask - HAINTM : HAINTMSK_HAINTM_Field := 16#0#; + -- OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + type FS_GAHBCFG_Register is record + -- Global interrupt mask + GINT : FS_GAHBCFG_GINT_Field := 16#0#; + -- unspecified + Reserved_1_6 : STM32F40x.UInt6 := 16#0#; + -- TxFIFO empty level + TXFELVL : FS_GAHBCFG_TXFELVL_Field := 16#0#; + -- Periodic TxFIFO empty level + PTXFELVL : FS_GAHBCFG_PTXFELVL_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_9_31 : STM32F40x.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HAINTMSK_Register use record - HAINTM at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_GAHBCFG_Register use record + GINT at 0 range 0 .. 0; + Reserved_1_6 at 0 range 1 .. 6; + TXFELVL at 0 range 7 .. 7; + PTXFELVL at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; end record; - ---------------------- - -- FS_HPRT_Register -- - ---------------------- + subtype FS_GUSBCFG_TOCAL_Field is STM32F40x.UInt3; + subtype FS_GUSBCFG_PHYSEL_Field is STM32F40x.Bit; + subtype FS_GUSBCFG_SRPCAP_Field is STM32F40x.Bit; + subtype FS_GUSBCFG_HNPCAP_Field is STM32F40x.Bit; + subtype FS_GUSBCFG_TRDT_Field is STM32F40x.UInt4; + subtype FS_GUSBCFG_FHMOD_Field is STM32F40x.Bit; + subtype FS_GUSBCFG_FDMOD_Field is STM32F40x.Bit; + subtype FS_GUSBCFG_CTXPKT_Field is STM32F40x.Bit; - subtype FS_HPRT_PCSTS_Field is STM32F40x.Bit; - subtype FS_HPRT_PCDET_Field is STM32F40x.Bit; - subtype FS_HPRT_PENA_Field is STM32F40x.Bit; - subtype FS_HPRT_PENCHNG_Field is STM32F40x.Bit; - subtype FS_HPRT_POCA_Field is STM32F40x.Bit; - subtype FS_HPRT_POCCHNG_Field is STM32F40x.Bit; - subtype FS_HPRT_PRES_Field is STM32F40x.Bit; - subtype FS_HPRT_PSUSP_Field is STM32F40x.Bit; - subtype FS_HPRT_PRST_Field is STM32F40x.Bit; - subtype FS_HPRT_PLSTS_Field is STM32F40x.UInt2; - subtype FS_HPRT_PPWR_Field is STM32F40x.Bit; - subtype FS_HPRT_PTCTL_Field is STM32F40x.UInt4; - subtype FS_HPRT_PSPD_Field is STM32F40x.UInt2; - - -- OTG_FS host port control and status register (OTG_FS_HPRT) - type FS_HPRT_Register is record - -- Read-only. Port connect status - PCSTS : FS_HPRT_PCSTS_Field := 16#0#; - -- Port connect detected - PCDET : FS_HPRT_PCDET_Field := 16#0#; - -- Port enable - PENA : FS_HPRT_PENA_Field := 16#0#; - -- Port enable/disable change - PENCHNG : FS_HPRT_PENCHNG_Field := 16#0#; - -- Read-only. Port overcurrent active - POCA : FS_HPRT_POCA_Field := 16#0#; - -- Port overcurrent change - POCCHNG : FS_HPRT_POCCHNG_Field := 16#0#; - -- Port resume - PRES : FS_HPRT_PRES_Field := 16#0#; - -- Port suspend - PSUSP : FS_HPRT_PSUSP_Field := 16#0#; - -- Port reset - PRST : FS_HPRT_PRST_Field := 16#0#; + -- OTG_FS USB configuration register (OTG_FS_GUSBCFG) + type FS_GUSBCFG_Register is record + -- FS timeout calibration + TOCAL : FS_GUSBCFG_TOCAL_Field := 16#0#; -- unspecified - Reserved_9_9 : STM32F40x.Bit := 16#0#; - -- Read-only. Port line status - PLSTS : FS_HPRT_PLSTS_Field := 16#0#; - -- Port power - PPWR : FS_HPRT_PPWR_Field := 16#0#; - -- Port test control - PTCTL : FS_HPRT_PTCTL_Field := 16#0#; - -- Read-only. Port speed - PSPD : FS_HPRT_PSPD_Field := 16#0#; + Reserved_3_5 : STM32F40x.UInt3 := 16#0#; + -- Write-only. Full Speed serial transceiver select + PHYSEL : FS_GUSBCFG_PHYSEL_Field := 16#0#; -- unspecified - Reserved_19_31 : STM32F40x.UInt13 := 16#0#; + Reserved_7_7 : STM32F40x.Bit := 16#0#; + -- SRP-capable + SRPCAP : FS_GUSBCFG_SRPCAP_Field := 16#0#; + -- HNP-capable + HNPCAP : FS_GUSBCFG_HNPCAP_Field := 16#1#; + -- USB turnaround time + TRDT : FS_GUSBCFG_TRDT_Field := 16#2#; + -- unspecified + Reserved_14_28 : STM32F40x.UInt15 := 16#0#; + -- Force host mode + FHMOD : FS_GUSBCFG_FHMOD_Field := 16#0#; + -- Force device mode + FDMOD : FS_GUSBCFG_FDMOD_Field := 16#0#; + -- Corrupt Tx packet + CTXPKT : FS_GUSBCFG_CTXPKT_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HPRT_Register use record - PCSTS at 0 range 0 .. 0; - PCDET at 0 range 1 .. 1; - PENA at 0 range 2 .. 2; - PENCHNG at 0 range 3 .. 3; - POCA at 0 range 4 .. 4; - POCCHNG at 0 range 5 .. 5; - PRES at 0 range 6 .. 6; - PSUSP at 0 range 7 .. 7; - PRST at 0 range 8 .. 8; - Reserved_9_9 at 0 range 9 .. 9; - PLSTS at 0 range 10 .. 11; - PPWR at 0 range 12 .. 12; - PTCTL at 0 range 13 .. 16; - PSPD at 0 range 17 .. 18; - Reserved_19_31 at 0 range 19 .. 31; + for FS_GUSBCFG_Register use record + TOCAL at 0 range 0 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + PHYSEL at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + SRPCAP at 0 range 8 .. 8; + HNPCAP at 0 range 9 .. 9; + TRDT at 0 range 10 .. 13; + Reserved_14_28 at 0 range 14 .. 28; + FHMOD at 0 range 29 .. 29; + FDMOD at 0 range 30 .. 30; + CTXPKT at 0 range 31 .. 31; end record; - ------------------------ - -- FS_HCCHAR_Register -- - ------------------------ - - subtype FS_HCCHAR0_MPSIZ_Field is STM32F40x.UInt11; - subtype FS_HCCHAR0_EPNUM_Field is STM32F40x.UInt4; - subtype FS_HCCHAR0_EPDIR_Field is STM32F40x.Bit; - subtype FS_HCCHAR0_LSDEV_Field is STM32F40x.Bit; - subtype FS_HCCHAR0_EPTYP_Field is STM32F40x.UInt2; - subtype FS_HCCHAR0_MCNT_Field is STM32F40x.UInt2; - subtype FS_HCCHAR0_DAD_Field is STM32F40x.UInt7; - subtype FS_HCCHAR0_ODDFRM_Field is STM32F40x.Bit; - subtype FS_HCCHAR0_CHDIS_Field is STM32F40x.Bit; - subtype FS_HCCHAR0_CHENA_Field is STM32F40x.Bit; + subtype FS_GRSTCTL_CSRST_Field is STM32F40x.Bit; + subtype FS_GRSTCTL_HSRST_Field is STM32F40x.Bit; + subtype FS_GRSTCTL_FCRST_Field is STM32F40x.Bit; + subtype FS_GRSTCTL_RXFFLSH_Field is STM32F40x.Bit; + subtype FS_GRSTCTL_TXFFLSH_Field is STM32F40x.Bit; + subtype FS_GRSTCTL_TXFNUM_Field is STM32F40x.UInt5; + subtype FS_GRSTCTL_AHBIDL_Field is STM32F40x.Bit; - -- OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) - type FS_HCCHAR_Register is record - -- Maximum packet size - MPSIZ : FS_HCCHAR0_MPSIZ_Field := 16#0#; - -- Endpoint number - EPNUM : FS_HCCHAR0_EPNUM_Field := 16#0#; - -- Endpoint direction - EPDIR : FS_HCCHAR0_EPDIR_Field := 16#0#; + -- OTG_FS reset register (OTG_FS_GRSTCTL) + type FS_GRSTCTL_Register is record + -- Core soft reset + CSRST : FS_GRSTCTL_CSRST_Field := 16#0#; + -- HCLK soft reset + HSRST : FS_GRSTCTL_HSRST_Field := 16#0#; + -- Host frame counter reset + FCRST : FS_GRSTCTL_FCRST_Field := 16#0#; -- unspecified - Reserved_16_16 : STM32F40x.Bit := 16#0#; - -- Low-speed device - LSDEV : FS_HCCHAR0_LSDEV_Field := 16#0#; - -- Endpoint type - EPTYP : FS_HCCHAR0_EPTYP_Field := 16#0#; - -- Multicount - MCNT : FS_HCCHAR0_MCNT_Field := 16#0#; - -- Device address - DAD : FS_HCCHAR0_DAD_Field := 16#0#; - -- Odd frame - ODDFRM : FS_HCCHAR0_ODDFRM_Field := 16#0#; - -- Channel disable - CHDIS : FS_HCCHAR0_CHDIS_Field := 16#0#; - -- Channel enable - CHENA : FS_HCCHAR0_CHENA_Field := 16#0#; + Reserved_3_3 : STM32F40x.Bit := 16#0#; + -- RxFIFO flush + RXFFLSH : FS_GRSTCTL_RXFFLSH_Field := 16#0#; + -- TxFIFO flush + TXFFLSH : FS_GRSTCTL_TXFFLSH_Field := 16#0#; + -- TxFIFO number + TXFNUM : FS_GRSTCTL_TXFNUM_Field := 16#0#; + -- unspecified + Reserved_11_30 : STM32F40x.UInt20 := 16#40000#; + -- Read-only. AHB master idle + AHBIDL : FS_GRSTCTL_AHBIDL_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HCCHAR_Register use record - MPSIZ at 0 range 0 .. 10; - EPNUM at 0 range 11 .. 14; - EPDIR at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - LSDEV at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - MCNT at 0 range 20 .. 21; - DAD at 0 range 22 .. 28; - ODDFRM at 0 range 29 .. 29; - CHDIS at 0 range 30 .. 30; - CHENA at 0 range 31 .. 31; + for FS_GRSTCTL_Register use record + CSRST at 0 range 0 .. 0; + HSRST at 0 range 1 .. 1; + FCRST at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + RXFFLSH at 0 range 4 .. 4; + TXFFLSH at 0 range 5 .. 5; + TXFNUM at 0 range 6 .. 10; + Reserved_11_30 at 0 range 11 .. 30; + AHBIDL at 0 range 31 .. 31; end record; - ----------------------- - -- FS_HCINT_Register -- - ----------------------- - - subtype FS_HCINT0_XFRC_Field is STM32F40x.Bit; - subtype FS_HCINT0_CHH_Field is STM32F40x.Bit; - subtype FS_HCINT0_STALL_Field is STM32F40x.Bit; - subtype FS_HCINT0_NAK_Field is STM32F40x.Bit; - subtype FS_HCINT0_ACK_Field is STM32F40x.Bit; - subtype FS_HCINT0_TXERR_Field is STM32F40x.Bit; - subtype FS_HCINT0_BBERR_Field is STM32F40x.Bit; - subtype FS_HCINT0_FRMOR_Field is STM32F40x.Bit; - subtype FS_HCINT0_DTERR_Field is STM32F40x.Bit; + subtype FS_GINTSTS_CMOD_Field is STM32F40x.Bit; + subtype FS_GINTSTS_MMIS_Field is STM32F40x.Bit; + subtype FS_GINTSTS_OTGINT_Field is STM32F40x.Bit; + subtype FS_GINTSTS_SOF_Field is STM32F40x.Bit; + subtype FS_GINTSTS_RXFLVL_Field is STM32F40x.Bit; + subtype FS_GINTSTS_NPTXFE_Field is STM32F40x.Bit; + subtype FS_GINTSTS_GINAKEFF_Field is STM32F40x.Bit; + subtype FS_GINTSTS_GOUTNAKEFF_Field is STM32F40x.Bit; + subtype FS_GINTSTS_ESUSP_Field is STM32F40x.Bit; + subtype FS_GINTSTS_USBSUSP_Field is STM32F40x.Bit; + subtype FS_GINTSTS_USBRST_Field is STM32F40x.Bit; + subtype FS_GINTSTS_ENUMDNE_Field is STM32F40x.Bit; + subtype FS_GINTSTS_ISOODRP_Field is STM32F40x.Bit; + subtype FS_GINTSTS_EOPF_Field is STM32F40x.Bit; + subtype FS_GINTSTS_IEPINT_Field is STM32F40x.Bit; + subtype FS_GINTSTS_OEPINT_Field is STM32F40x.Bit; + subtype FS_GINTSTS_IISOIXFR_Field is STM32F40x.Bit; + subtype FS_GINTSTS_IPXFR_INCOMPISOOUT_Field is STM32F40x.Bit; + subtype FS_GINTSTS_HPRTINT_Field is STM32F40x.Bit; + subtype FS_GINTSTS_HCINT_Field is STM32F40x.Bit; + subtype FS_GINTSTS_PTXFE_Field is STM32F40x.Bit; + subtype FS_GINTSTS_CIDSCHG_Field is STM32F40x.Bit; + subtype FS_GINTSTS_DISCINT_Field is STM32F40x.Bit; + subtype FS_GINTSTS_SRQINT_Field is STM32F40x.Bit; + subtype FS_GINTSTS_WKUPINT_Field is STM32F40x.Bit; - -- OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) - type FS_HCINT_Register is record - -- Transfer completed - XFRC : FS_HCINT0_XFRC_Field := 16#0#; - -- Channel halted - CHH : FS_HCINT0_CHH_Field := 16#0#; + -- OTG_FS core interrupt register (OTG_FS_GINTSTS) + type FS_GINTSTS_Register is record + -- Read-only. Current mode of operation + CMOD : FS_GINTSTS_CMOD_Field := 16#0#; + -- Mode mismatch interrupt + MMIS : FS_GINTSTS_MMIS_Field := 16#0#; + -- Read-only. OTG interrupt + OTGINT : FS_GINTSTS_OTGINT_Field := 16#0#; + -- Start of frame + SOF : FS_GINTSTS_SOF_Field := 16#0#; + -- Read-only. RxFIFO non-empty + RXFLVL : FS_GINTSTS_RXFLVL_Field := 16#0#; + -- Read-only. Non-periodic TxFIFO empty + NPTXFE : FS_GINTSTS_NPTXFE_Field := 16#1#; + -- Read-only. Global IN non-periodic NAK effective + GINAKEFF : FS_GINTSTS_GINAKEFF_Field := 16#0#; + -- Read-only. Global OUT NAK effective + GOUTNAKEFF : FS_GINTSTS_GOUTNAKEFF_Field := 16#0#; -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- STALL response received interrupt - STALL : FS_HCINT0_STALL_Field := 16#0#; - -- NAK response received interrupt - NAK : FS_HCINT0_NAK_Field := 16#0#; - -- ACK response received/transmitted interrupt - ACK : FS_HCINT0_ACK_Field := 16#0#; + Reserved_8_9 : STM32F40x.UInt2 := 16#0#; + -- Early suspend + ESUSP : FS_GINTSTS_ESUSP_Field := 16#0#; + -- USB suspend + USBSUSP : FS_GINTSTS_USBSUSP_Field := 16#0#; + -- USB reset + USBRST : FS_GINTSTS_USBRST_Field := 16#0#; + -- Enumeration done + ENUMDNE : FS_GINTSTS_ENUMDNE_Field := 16#0#; + -- Isochronous OUT packet dropped interrupt + ISOODRP : FS_GINTSTS_ISOODRP_Field := 16#0#; + -- End of periodic frame interrupt + EOPF : FS_GINTSTS_EOPF_Field := 16#0#; -- unspecified - Reserved_6_6 : STM32F40x.Bit := 16#0#; - -- Transaction error - TXERR : FS_HCINT0_TXERR_Field := 16#0#; - -- Babble error - BBERR : FS_HCINT0_BBERR_Field := 16#0#; - -- Frame overrun - FRMOR : FS_HCINT0_FRMOR_Field := 16#0#; - -- Data toggle error - DTERR : FS_HCINT0_DTERR_Field := 16#0#; + Reserved_16_17 : STM32F40x.UInt2 := 16#0#; + -- Read-only. IN endpoint interrupt + IEPINT : FS_GINTSTS_IEPINT_Field := 16#0#; + -- Read-only. OUT endpoint interrupt + OEPINT : FS_GINTSTS_OEPINT_Field := 16#0#; + -- Incomplete isochronous IN transfer + IISOIXFR : FS_GINTSTS_IISOIXFR_Field := 16#0#; + -- Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT + -- transfer(Device mode) + IPXFR_INCOMPISOOUT : FS_GINTSTS_IPXFR_INCOMPISOOUT_Field := 16#0#; -- unspecified - Reserved_11_31 : STM32F40x.UInt21 := 16#0#; + Reserved_22_23 : STM32F40x.UInt2 := 16#0#; + -- Read-only. Host port interrupt + HPRTINT : FS_GINTSTS_HPRTINT_Field := 16#0#; + -- Read-only. Host channels interrupt + HCINT : FS_GINTSTS_HCINT_Field := 16#0#; + -- Read-only. Periodic TxFIFO empty + PTXFE : FS_GINTSTS_PTXFE_Field := 16#1#; + -- unspecified + Reserved_27_27 : STM32F40x.Bit := 16#0#; + -- Connector ID status change + CIDSCHG : FS_GINTSTS_CIDSCHG_Field := 16#0#; + -- Disconnect detected interrupt + DISCINT : FS_GINTSTS_DISCINT_Field := 16#0#; + -- Session request/new session detected interrupt + SRQINT : FS_GINTSTS_SRQINT_Field := 16#0#; + -- Resume/remote wakeup detected interrupt + WKUPINT : FS_GINTSTS_WKUPINT_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HCINT_Register use record - XFRC at 0 range 0 .. 0; - CHH at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STALL at 0 range 3 .. 3; - NAK at 0 range 4 .. 4; - ACK at 0 range 5 .. 5; - Reserved_6_6 at 0 range 6 .. 6; - TXERR at 0 range 7 .. 7; - BBERR at 0 range 8 .. 8; - FRMOR at 0 range 9 .. 9; - DTERR at 0 range 10 .. 10; - Reserved_11_31 at 0 range 11 .. 31; + for FS_GINTSTS_Register use record + CMOD at 0 range 0 .. 0; + MMIS at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOF at 0 range 3 .. 3; + RXFLVL at 0 range 4 .. 4; + NPTXFE at 0 range 5 .. 5; + GINAKEFF at 0 range 6 .. 6; + GOUTNAKEFF at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSP at 0 range 10 .. 10; + USBSUSP at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNE at 0 range 13 .. 13; + ISOODRP at 0 range 14 .. 14; + EOPF at 0 range 15 .. 15; + Reserved_16_17 at 0 range 16 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFR at 0 range 20 .. 20; + IPXFR_INCOMPISOOUT at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + HPRTINT at 0 range 24 .. 24; + HCINT at 0 range 25 .. 25; + PTXFE at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHG at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQINT at 0 range 30 .. 30; + WKUPINT at 0 range 31 .. 31; end record; - -------------------------- - -- FS_HCINTMSK_Register -- - -------------------------- - - subtype FS_HCINTMSK0_XFRCM_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_CHHM_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_STALLM_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_NAKM_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_ACKM_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_NYET_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_TXERRM_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_BBERRM_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_FRMORM_Field is STM32F40x.Bit; - subtype FS_HCINTMSK0_DTERRM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_MMISM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_OTGINT_Field is STM32F40x.Bit; + subtype FS_GINTMSK_SOFM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_RXFLVLM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_NPTXFEM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_GINAKEFFM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_GONAKEFFM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_ESUSPM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_USBSUSPM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_USBRST_Field is STM32F40x.Bit; + subtype FS_GINTMSK_ENUMDNEM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_ISOODRPM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_EOPFM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_EPMISM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_IEPINT_Field is STM32F40x.Bit; + subtype FS_GINTMSK_OEPINT_Field is STM32F40x.Bit; + subtype FS_GINTMSK_IISOIXFRM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_IPXFRM_IISOOXFRM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_PRTIM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_HCIM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_PTXFEM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_CIDSCHGM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_DISCINT_Field is STM32F40x.Bit; + subtype FS_GINTMSK_SRQIM_Field is STM32F40x.Bit; + subtype FS_GINTMSK_WUIM_Field is STM32F40x.Bit; - -- OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) - type FS_HCINTMSK_Register is record - -- Transfer completed mask - XFRCM : FS_HCINTMSK0_XFRCM_Field := 16#0#; - -- Channel halted mask - CHHM : FS_HCINTMSK0_CHHM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- STALL response received interrupt mask - STALLM : FS_HCINTMSK0_STALLM_Field := 16#0#; - -- NAK response received interrupt mask - NAKM : FS_HCINTMSK0_NAKM_Field := 16#0#; - -- ACK response received/transmitted interrupt mask - ACKM : FS_HCINTMSK0_ACKM_Field := 16#0#; - -- response received interrupt mask - NYET : FS_HCINTMSK0_NYET_Field := 16#0#; - -- Transaction error mask - TXERRM : FS_HCINTMSK0_TXERRM_Field := 16#0#; - -- Babble error mask - BBERRM : FS_HCINTMSK0_BBERRM_Field := 16#0#; - -- Frame overrun mask - FRMORM : FS_HCINTMSK0_FRMORM_Field := 16#0#; - -- Data toggle error mask - DTERRM : FS_HCINTMSK0_DTERRM_Field := 16#0#; + -- OTG_FS interrupt mask register (OTG_FS_GINTMSK) + type FS_GINTMSK_Register is record -- unspecified - Reserved_11_31 : STM32F40x.UInt21 := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for FS_HCINTMSK_Register use record - XFRCM at 0 range 0 .. 0; - CHHM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STALLM at 0 range 3 .. 3; - NAKM at 0 range 4 .. 4; - ACKM at 0 range 5 .. 5; - NYET at 0 range 6 .. 6; - TXERRM at 0 range 7 .. 7; - BBERRM at 0 range 8 .. 8; - FRMORM at 0 range 9 .. 9; - DTERRM at 0 range 10 .. 10; - Reserved_11_31 at 0 range 11 .. 31; - end record; - - ------------------------ - -- FS_HCTSIZ_Register -- - ------------------------ - - subtype FS_HCTSIZ0_XFRSIZ_Field is STM32F40x.UInt19; - subtype FS_HCTSIZ0_PKTCNT_Field is STM32F40x.UInt10; - subtype FS_HCTSIZ0_DPID_Field is STM32F40x.UInt2; - - -- OTG_FS host channel-0 transfer size register - type FS_HCTSIZ_Register is record - -- Transfer size - XFRSIZ : FS_HCTSIZ0_XFRSIZ_Field := 16#0#; - -- Packet count - PKTCNT : FS_HCTSIZ0_PKTCNT_Field := 16#0#; - -- Data PID - DPID : FS_HCTSIZ0_DPID_Field := 16#0#; + Reserved_0_0 : STM32F40x.Bit := 16#0#; + -- Mode mismatch interrupt mask + MMISM : FS_GINTMSK_MMISM_Field := 16#0#; + -- OTG interrupt mask + OTGINT : FS_GINTMSK_OTGINT_Field := 16#0#; + -- Start of frame mask + SOFM : FS_GINTMSK_SOFM_Field := 16#0#; + -- Receive FIFO non-empty mask + RXFLVLM : FS_GINTMSK_RXFLVLM_Field := 16#0#; + -- Non-periodic TxFIFO empty mask + NPTXFEM : FS_GINTMSK_NPTXFEM_Field := 16#0#; + -- Global non-periodic IN NAK effective mask + GINAKEFFM : FS_GINTMSK_GINAKEFFM_Field := 16#0#; + -- Global OUT NAK effective mask + GONAKEFFM : FS_GINTMSK_GONAKEFFM_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F40x.Bit := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for FS_HCTSIZ_Register use record - XFRSIZ at 0 range 0 .. 18; - PKTCNT at 0 range 19 .. 28; - DPID at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; - end record; - - ---------------------- - -- FS_DCFG_Register -- - ---------------------- - - subtype FS_DCFG_DSPD_Field is STM32F40x.UInt2; - subtype FS_DCFG_NZLSOHSK_Field is STM32F40x.Bit; - subtype FS_DCFG_DAD_Field is STM32F40x.UInt7; - subtype FS_DCFG_PFIVL_Field is STM32F40x.UInt2; - - -- OTG_FS device configuration register (OTG_FS_DCFG) - type FS_DCFG_Register is record - -- Device speed - DSPD : FS_DCFG_DSPD_Field := 16#0#; - -- Non-zero-length status OUT handshake - NZLSOHSK : FS_DCFG_NZLSOHSK_Field := 16#0#; + Reserved_8_9 : STM32F40x.UInt2 := 16#0#; + -- Early suspend mask + ESUSPM : FS_GINTMSK_ESUSPM_Field := 16#0#; + -- USB suspend mask + USBSUSPM : FS_GINTMSK_USBSUSPM_Field := 16#0#; + -- USB reset mask + USBRST : FS_GINTMSK_USBRST_Field := 16#0#; + -- Enumeration done mask + ENUMDNEM : FS_GINTMSK_ENUMDNEM_Field := 16#0#; + -- Isochronous OUT packet dropped interrupt mask + ISOODRPM : FS_GINTMSK_ISOODRPM_Field := 16#0#; + -- End of periodic frame interrupt mask + EOPFM : FS_GINTMSK_EOPFM_Field := 16#0#; -- unspecified - Reserved_3_3 : STM32F40x.Bit := 16#0#; - -- Device address - DAD : FS_DCFG_DAD_Field := 16#0#; - -- Periodic frame interval - PFIVL : FS_DCFG_PFIVL_Field := 16#0#; + Reserved_16_16 : STM32F40x.Bit := 16#0#; + -- Endpoint mismatch interrupt mask + EPMISM : FS_GINTMSK_EPMISM_Field := 16#0#; + -- IN endpoints interrupt mask + IEPINT : FS_GINTMSK_IEPINT_Field := 16#0#; + -- OUT endpoints interrupt mask + OEPINT : FS_GINTMSK_OEPINT_Field := 16#0#; + -- Incomplete isochronous IN transfer mask + IISOIXFRM : FS_GINTMSK_IISOIXFRM_Field := 16#0#; + -- Incomplete periodic transfer mask(Host mode)/Incomplete isochronous + -- OUT transfer mask(Device mode) + IPXFRM_IISOOXFRM : FS_GINTMSK_IPXFRM_IISOOXFRM_Field := 16#0#; -- unspecified - Reserved_13_31 : STM32F40x.UInt19 := 16#1100#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for FS_DCFG_Register use record - DSPD at 0 range 0 .. 1; - NZLSOHSK at 0 range 2 .. 2; - Reserved_3_3 at 0 range 3 .. 3; - DAD at 0 range 4 .. 10; - PFIVL at 0 range 11 .. 12; - Reserved_13_31 at 0 range 13 .. 31; - end record; - - ---------------------- - -- FS_DCTL_Register -- - ---------------------- - - subtype FS_DCTL_RWUSIG_Field is STM32F40x.Bit; - subtype FS_DCTL_SDIS_Field is STM32F40x.Bit; - subtype FS_DCTL_GINSTS_Field is STM32F40x.Bit; - subtype FS_DCTL_GONSTS_Field is STM32F40x.Bit; - subtype FS_DCTL_TCTL_Field is STM32F40x.UInt3; - subtype FS_DCTL_SGINAK_Field is STM32F40x.Bit; - subtype FS_DCTL_CGINAK_Field is STM32F40x.Bit; - subtype FS_DCTL_SGONAK_Field is STM32F40x.Bit; - subtype FS_DCTL_CGONAK_Field is STM32F40x.Bit; - subtype FS_DCTL_POPRGDNE_Field is STM32F40x.Bit; - - -- OTG_FS device control register (OTG_FS_DCTL) - type FS_DCTL_Register is record - -- Remote wakeup signaling - RWUSIG : FS_DCTL_RWUSIG_Field := 16#0#; - -- Soft disconnect - SDIS : FS_DCTL_SDIS_Field := 16#0#; - -- Read-only. Global IN NAK status - GINSTS : FS_DCTL_GINSTS_Field := 16#0#; - -- Read-only. Global OUT NAK status - GONSTS : FS_DCTL_GONSTS_Field := 16#0#; - -- Test control - TCTL : FS_DCTL_TCTL_Field := 16#0#; - -- Set global IN NAK - SGINAK : FS_DCTL_SGINAK_Field := 16#0#; - -- Clear global IN NAK - CGINAK : FS_DCTL_CGINAK_Field := 16#0#; - -- Set global OUT NAK - SGONAK : FS_DCTL_SGONAK_Field := 16#0#; - -- Clear global OUT NAK - CGONAK : FS_DCTL_CGONAK_Field := 16#0#; - -- Power-on programming done - POPRGDNE : FS_DCTL_POPRGDNE_Field := 16#0#; + Reserved_22_23 : STM32F40x.UInt2 := 16#0#; + -- Read-only. Host port interrupt mask + PRTIM : FS_GINTMSK_PRTIM_Field := 16#0#; + -- Host channels interrupt mask + HCIM : FS_GINTMSK_HCIM_Field := 16#0#; + -- Periodic TxFIFO empty mask + PTXFEM : FS_GINTMSK_PTXFEM_Field := 16#0#; -- unspecified - Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + Reserved_27_27 : STM32F40x.Bit := 16#0#; + -- Connector ID status change mask + CIDSCHGM : FS_GINTMSK_CIDSCHGM_Field := 16#0#; + -- Disconnect detected interrupt mask + DISCINT : FS_GINTMSK_DISCINT_Field := 16#0#; + -- Session request/new session detected interrupt mask + SRQIM : FS_GINTMSK_SRQIM_Field := 16#0#; + -- Resume/remote wakeup detected interrupt mask + WUIM : FS_GINTMSK_WUIM_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DCTL_Register use record - RWUSIG at 0 range 0 .. 0; - SDIS at 0 range 1 .. 1; - GINSTS at 0 range 2 .. 2; - GONSTS at 0 range 3 .. 3; - TCTL at 0 range 4 .. 6; - SGINAK at 0 range 7 .. 7; - CGINAK at 0 range 8 .. 8; - SGONAK at 0 range 9 .. 9; - CGONAK at 0 range 10 .. 10; - POPRGDNE at 0 range 11 .. 11; - Reserved_12_31 at 0 range 12 .. 31; + for FS_GINTMSK_Register use record + Reserved_0_0 at 0 range 0 .. 0; + MMISM at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOFM at 0 range 3 .. 3; + RXFLVLM at 0 range 4 .. 4; + NPTXFEM at 0 range 5 .. 5; + GINAKEFFM at 0 range 6 .. 6; + GONAKEFFM at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSPM at 0 range 10 .. 10; + USBSUSPM at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNEM at 0 range 13 .. 13; + ISOODRPM at 0 range 14 .. 14; + EOPFM at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + EPMISM at 0 range 17 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFRM at 0 range 20 .. 20; + IPXFRM_IISOOXFRM at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PRTIM at 0 range 24 .. 24; + HCIM at 0 range 25 .. 25; + PTXFEM at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHGM at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQIM at 0 range 30 .. 30; + WUIM at 0 range 31 .. 31; end record; - ---------------------- - -- FS_DSTS_Register -- - ---------------------- - - subtype FS_DSTS_SUSPSTS_Field is STM32F40x.Bit; - subtype FS_DSTS_ENUMSPD_Field is STM32F40x.UInt2; - subtype FS_DSTS_EERR_Field is STM32F40x.Bit; - subtype FS_DSTS_FNSOF_Field is STM32F40x.UInt14; + subtype FS_GRXSTSR_Device_EPNUM_Field is STM32F40x.UInt4; + subtype FS_GRXSTSR_Device_BCNT_Field is STM32F40x.UInt11; + subtype FS_GRXSTSR_Device_DPID_Field is STM32F40x.UInt2; + subtype FS_GRXSTSR_Device_PKTSTS_Field is STM32F40x.UInt4; + subtype FS_GRXSTSR_Device_FRMNUM_Field is STM32F40x.UInt4; - -- OTG_FS device status register (OTG_FS_DSTS) - type FS_DSTS_Register is record - -- Read-only. Suspend status - SUSPSTS : FS_DSTS_SUSPSTS_Field := 16#0#; - -- Read-only. Enumerated speed - ENUMSPD : FS_DSTS_ENUMSPD_Field := 16#0#; - -- Read-only. Erratic error - EERR : FS_DSTS_EERR_Field := 16#0#; - -- unspecified - Reserved_4_7 : STM32F40x.UInt4; - -- Read-only. Frame number of the received SOF - FNSOF : FS_DSTS_FNSOF_Field := 16#0#; + -- OTG_FS Receive status debug read(Device mode) + type FS_GRXSTSR_Device_Register is record + -- Read-only. Endpoint number + EPNUM : FS_GRXSTSR_Device_EPNUM_Field; + -- Read-only. Byte count + BCNT : FS_GRXSTSR_Device_BCNT_Field; + -- Read-only. Data PID + DPID : FS_GRXSTSR_Device_DPID_Field; + -- Read-only. Packet status + PKTSTS : FS_GRXSTSR_Device_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : FS_GRXSTSR_Device_FRMNUM_Field; -- unspecified - Reserved_22_31 : STM32F40x.UInt10; + Reserved_25_31 : STM32F40x.UInt7; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DSTS_Register use record - SUSPSTS at 0 range 0 .. 0; - ENUMSPD at 0 range 1 .. 2; - EERR at 0 range 3 .. 3; - Reserved_4_7 at 0 range 4 .. 7; - FNSOF at 0 range 8 .. 21; - Reserved_22_31 at 0 range 22 .. 31; + for FS_GRXSTSR_Device_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------------- - -- FS_DIEPMSK_Register -- - ------------------------- - - subtype FS_DIEPMSK_XFRCM_Field is STM32F40x.Bit; - subtype FS_DIEPMSK_EPDM_Field is STM32F40x.Bit; - subtype FS_DIEPMSK_TOM_Field is STM32F40x.Bit; - subtype FS_DIEPMSK_ITTXFEMSK_Field is STM32F40x.Bit; - subtype FS_DIEPMSK_INEPNMM_Field is STM32F40x.Bit; - subtype FS_DIEPMSK_INEPNEM_Field is STM32F40x.Bit; + subtype FS_GRXSTSR_Host_EPNUM_Field is STM32F40x.UInt4; + subtype FS_GRXSTSR_Host_BCNT_Field is STM32F40x.UInt11; + subtype FS_GRXSTSR_Host_DPID_Field is STM32F40x.UInt2; + subtype FS_GRXSTSR_Host_PKTSTS_Field is STM32F40x.UInt4; + subtype FS_GRXSTSR_Host_FRMNUM_Field is STM32F40x.UInt4; - -- OTG_FS device IN endpoint common interrupt mask register - -- (OTG_FS_DIEPMSK) - type FS_DIEPMSK_Register is record - -- Transfer completed interrupt mask - XFRCM : FS_DIEPMSK_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : FS_DIEPMSK_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- Timeout condition mask (Non-isochronous endpoints) - TOM : FS_DIEPMSK_TOM_Field := 16#0#; - -- IN token received when TxFIFO empty mask - ITTXFEMSK : FS_DIEPMSK_ITTXFEMSK_Field := 16#0#; - -- IN token received with EP mismatch mask - INEPNMM : FS_DIEPMSK_INEPNMM_Field := 16#0#; - -- IN endpoint NAK effective mask - INEPNEM : FS_DIEPMSK_INEPNEM_Field := 16#0#; + -- OTG_FS Receive status debug read(Host mode) + type FS_GRXSTSR_Host_Register is record + -- Read-only. Endpoint number + EPNUM : FS_GRXSTSR_Host_EPNUM_Field; + -- Read-only. Byte count + BCNT : FS_GRXSTSR_Host_BCNT_Field; + -- Read-only. Data PID + DPID : FS_GRXSTSR_Host_DPID_Field; + -- Read-only. Packet status + PKTSTS : FS_GRXSTSR_Host_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : FS_GRXSTSR_Host_FRMNUM_Field; -- unspecified - Reserved_7_31 : STM32F40x.UInt25 := 16#0#; + Reserved_25_31 : STM32F40x.UInt7; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DIEPMSK_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOM at 0 range 3 .. 3; - ITTXFEMSK at 0 range 4 .. 4; - INEPNMM at 0 range 5 .. 5; - INEPNEM at 0 range 6 .. 6; - Reserved_7_31 at 0 range 7 .. 31; - end record; - - ------------------------- - -- FS_DOEPMSK_Register -- - ------------------------- - - subtype FS_DOEPMSK_XFRCM_Field is STM32F40x.Bit; - subtype FS_DOEPMSK_EPDM_Field is STM32F40x.Bit; - subtype FS_DOEPMSK_STUPM_Field is STM32F40x.Bit; - subtype FS_DOEPMSK_OTEPDM_Field is STM32F40x.Bit; - - -- OTG_FS device OUT endpoint common interrupt mask register - -- (OTG_FS_DOEPMSK) - type FS_DOEPMSK_Register is record - -- Transfer completed interrupt mask - XFRCM : FS_DOEPMSK_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : FS_DOEPMSK_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- SETUP phase done mask - STUPM : FS_DOEPMSK_STUPM_Field := 16#0#; - -- OUT token received when endpoint disabled mask - OTEPDM : FS_DOEPMSK_OTEPDM_Field := 16#0#; + for FS_GRXSTSR_Host_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype FS_GRXFSIZ_RXFD_Field is STM32F40x.UInt16; + + -- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + type FS_GRXFSIZ_Register is record + -- RxFIFO depth + RXFD : FS_GRXFSIZ_RXFD_Field := 16#200#; -- unspecified - Reserved_5_31 : STM32F40x.UInt27 := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DOEPMSK_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STUPM at 0 range 3 .. 3; - OTEPDM at 0 range 4 .. 4; - Reserved_5_31 at 0 range 5 .. 31; + for FS_GRXFSIZ_Register use record + RXFD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------- - -- FS_DAINT_Register -- - ----------------------- + subtype FS_GNPTXFSIZ_Device_TX0FSA_Field is STM32F40x.UInt16; + subtype FS_GNPTXFSIZ_Device_TX0FD_Field is STM32F40x.UInt16; - subtype FS_DAINT_IEPINT_Field is STM32F40x.Short; - subtype FS_DAINT_OEPINT_Field is STM32F40x.Short; - - -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) - type FS_DAINT_Register is record - -- Read-only. IN endpoint interrupt bits - IEPINT : FS_DAINT_IEPINT_Field := 16#0#; - -- Read-only. OUT endpoint interrupt bits - OEPINT : FS_DAINT_OEPINT_Field := 16#0#; + -- OTG_FS non-periodic transmit FIFO size register (Device mode) + type FS_GNPTXFSIZ_Device_Register is record + -- Endpoint 0 transmit RAM start address + TX0FSA : FS_GNPTXFSIZ_Device_TX0FSA_Field := 16#200#; + -- Endpoint 0 TxFIFO depth + TX0FD : FS_GNPTXFSIZ_Device_TX0FD_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DAINT_Register use record - IEPINT at 0 range 0 .. 15; - OEPINT at 0 range 16 .. 31; + for FS_GNPTXFSIZ_Device_Register use record + TX0FSA at 0 range 0 .. 15; + TX0FD at 0 range 16 .. 31; end record; - -------------------------- - -- FS_DAINTMSK_Register -- - -------------------------- - - subtype FS_DAINTMSK_IEPM_Field is STM32F40x.Short; - subtype FS_DAINTMSK_OEPINT_Field is STM32F40x.Short; + subtype FS_GNPTXFSIZ_Host_NPTXFSA_Field is STM32F40x.UInt16; + subtype FS_GNPTXFSIZ_Host_NPTXFD_Field is STM32F40x.UInt16; - -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) - type FS_DAINTMSK_Register is record - -- IN EP interrupt mask bits - IEPM : FS_DAINTMSK_IEPM_Field := 16#0#; - -- OUT endpoint interrupt bits - OEPINT : FS_DAINTMSK_OEPINT_Field := 16#0#; + -- OTG_FS non-periodic transmit FIFO size register (Host mode) + type FS_GNPTXFSIZ_Host_Register is record + -- Non-periodic transmit RAM start address + NPTXFSA : FS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; + -- Non-periodic TxFIFO depth + NPTXFD : FS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DAINTMSK_Register use record - IEPM at 0 range 0 .. 15; - OEPINT at 0 range 16 .. 31; + for FS_GNPTXFSIZ_Host_Register use record + NPTXFSA at 0 range 0 .. 15; + NPTXFD at 0 range 16 .. 31; end record; - ----------------------- - -- DVBUSDIS_Register -- - ----------------------- - - subtype DVBUSDIS_VBUSDT_Field is STM32F40x.Short; + subtype FS_GNPTXSTS_NPTXFSAV_Field is STM32F40x.UInt16; + subtype FS_GNPTXSTS_NPTQXSAV_Field is STM32F40x.Byte; + subtype FS_GNPTXSTS_NPTXQTOP_Field is STM32F40x.UInt7; - -- OTG_FS device VBUS discharge time register - type DVBUSDIS_Register is record - -- Device VBUS discharge time - VBUSDT : DVBUSDIS_VBUSDT_Field := 16#17D7#; + -- OTG_FS non-periodic transmit FIFO/queue status register + -- (OTG_FS_GNPTXSTS) + type FS_GNPTXSTS_Register is record + -- Read-only. Non-periodic TxFIFO space available + NPTXFSAV : FS_GNPTXSTS_NPTXFSAV_Field; + -- Read-only. Non-periodic transmit request queue space available + NPTQXSAV : FS_GNPTXSTS_NPTQXSAV_Field; + -- Read-only. Top of the non-periodic transmit request queue + NPTXQTOP : FS_GNPTXSTS_NPTXQTOP_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_31_31 : STM32F40x.Bit; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DVBUSDIS_Register use record - VBUSDT at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_GNPTXSTS_Register use record + NPTXFSAV at 0 range 0 .. 15; + NPTQXSAV at 0 range 16 .. 23; + NPTXQTOP at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------- - -- DVBUSPULSE_Register -- - ------------------------- - - subtype DVBUSPULSE_DVBUSP_Field is STM32F40x.UInt12; + subtype FS_GCCFG_PWRDWN_Field is STM32F40x.Bit; + subtype FS_GCCFG_VBUSASEN_Field is STM32F40x.Bit; + subtype FS_GCCFG_VBUSBSEN_Field is STM32F40x.Bit; + subtype FS_GCCFG_SOFOUTEN_Field is STM32F40x.Bit; - -- OTG_FS device VBUS pulsing time register - type DVBUSPULSE_Register is record - -- Device VBUS pulsing time - DVBUSP : DVBUSPULSE_DVBUSP_Field := 16#5B8#; + -- OTG_FS general core configuration register (OTG_FS_GCCFG) + type FS_GCCFG_Register is record -- unspecified - Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + Reserved_0_15 : STM32F40x.UInt16 := 16#0#; + -- Power down + PWRDWN : FS_GCCFG_PWRDWN_Field := 16#0#; + -- unspecified + Reserved_17_17 : STM32F40x.Bit := 16#0#; + -- Enable the VBUS sensing device + VBUSASEN : FS_GCCFG_VBUSASEN_Field := 16#0#; + -- Enable the VBUS sensing device + VBUSBSEN : FS_GCCFG_VBUSBSEN_Field := 16#0#; + -- SOF output enable + SOFOUTEN : FS_GCCFG_SOFOUTEN_Field := 16#0#; + -- unspecified + Reserved_21_31 : STM32F40x.UInt11 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DVBUSPULSE_Register use record - DVBUSP at 0 range 0 .. 11; - Reserved_12_31 at 0 range 12 .. 31; + for FS_GCCFG_Register use record + Reserved_0_15 at 0 range 0 .. 15; + PWRDWN at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + VBUSASEN at 0 range 18 .. 18; + VBUSBSEN at 0 range 19 .. 19; + SOFOUTEN at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------------- - -- DIEPEMPMSK_Register -- - ------------------------- + subtype FS_HPTXFSIZ_PTXSA_Field is STM32F40x.UInt16; + subtype FS_HPTXFSIZ_PTXFSIZ_Field is STM32F40x.UInt16; - subtype DIEPEMPMSK_INEPTXFEM_Field is STM32F40x.Short; - - -- OTG_FS device IN endpoint FIFO empty interrupt mask register - type DIEPEMPMSK_Register is record - -- IN EP Tx FIFO empty interrupt mask bits - INEPTXFEM : DIEPEMPMSK_INEPTXFEM_Field := 16#0#; - -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + -- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + type FS_HPTXFSIZ_Register is record + -- Host periodic TxFIFO start address + PTXSA : FS_HPTXFSIZ_PTXSA_Field := 16#600#; + -- Host periodic TxFIFO depth + PTXFSIZ : FS_HPTXFSIZ_PTXFSIZ_Field := 16#200#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPEMPMSK_Register use record - INEPTXFEM at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_HPTXFSIZ_Register use record + PTXSA at 0 range 0 .. 15; + PTXFSIZ at 0 range 16 .. 31; end record; - -------------------------- - -- FS_DIEPCTL0_Register -- - -------------------------- + subtype FS_DIEPTXF_INEPTXSA_Field is STM32F40x.UInt16; + subtype FS_DIEPTXF_INEPTXFD_Field is STM32F40x.UInt16; - subtype FS_DIEPCTL0_MPSIZ_Field is STM32F40x.UInt2; - subtype FS_DIEPCTL0_USBAEP_Field is STM32F40x.Bit; - subtype FS_DIEPCTL0_NAKSTS_Field is STM32F40x.Bit; - subtype FS_DIEPCTL0_EPTYP_Field is STM32F40x.UInt2; - subtype FS_DIEPCTL0_STALL_Field is STM32F40x.Bit; - subtype FS_DIEPCTL0_TXFNUM_Field is STM32F40x.UInt4; - subtype FS_DIEPCTL0_CNAK_Field is STM32F40x.Bit; - subtype FS_DIEPCTL0_SNAK_Field is STM32F40x.Bit; - subtype FS_DIEPCTL0_EPDIS_Field is STM32F40x.Bit; - subtype FS_DIEPCTL0_EPENA_Field is STM32F40x.Bit; + -- OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + type FS_DIEPTXF_Register is record + -- IN endpoint FIFO2 transmit RAM start address + INEPTXSA : FS_DIEPTXF_INEPTXSA_Field := 16#400#; + -- IN endpoint TxFIFO depth + INEPTXFD : FS_DIEPTXF_INEPTXFD_Field := 16#200#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) - type FS_DIEPCTL0_Register is record - -- Maximum packet size - MPSIZ : FS_DIEPCTL0_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_2_14 : STM32F40x.UInt13 := 16#0#; - -- Read-only. USB active endpoint - USBAEP : FS_DIEPCTL0_USBAEP_Field := 16#0#; - -- unspecified - Reserved_16_16 : STM32F40x.Bit := 16#0#; - -- Read-only. NAK status - NAKSTS : FS_DIEPCTL0_NAKSTS_Field := 16#0#; - -- Read-only. Endpoint type - EPTYP : FS_DIEPCTL0_EPTYP_Field := 16#0#; - -- unspecified - Reserved_20_20 : STM32F40x.Bit := 16#0#; - -- STALL handshake - STALL : FS_DIEPCTL0_STALL_Field := 16#0#; - -- TxFIFO number - TXFNUM : FS_DIEPCTL0_TXFNUM_Field := 16#0#; - -- Write-only. Clear NAK - CNAK : FS_DIEPCTL0_CNAK_Field := 16#0#; - -- Write-only. Set NAK - SNAK : FS_DIEPCTL0_SNAK_Field := 16#0#; + for FS_DIEPTXF_Register use record + INEPTXSA at 0 range 0 .. 15; + INEPTXFD at 0 range 16 .. 31; + end record; + + subtype FS_HCFG_FSLSPCS_Field is STM32F40x.UInt2; + subtype FS_HCFG_FSLSS_Field is STM32F40x.Bit; + + -- OTG_FS host configuration register (OTG_FS_HCFG) + type FS_HCFG_Register is record + -- FS/LS PHY clock select + FSLSPCS : FS_HCFG_FSLSPCS_Field := 16#0#; + -- Read-only. FS- and LS-only support + FSLSS : FS_HCFG_FSLSS_Field := 16#0#; -- unspecified - Reserved_28_29 : STM32F40x.UInt2 := 16#0#; - -- Read-only. Endpoint disable - EPDIS : FS_DIEPCTL0_EPDIS_Field := 16#0#; - -- Read-only. Endpoint enable - EPENA : FS_DIEPCTL0_EPENA_Field := 16#0#; + Reserved_3_31 : STM32F40x.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DIEPCTL0_Register use record - MPSIZ at 0 range 0 .. 1; - Reserved_2_14 at 0 range 2 .. 14; - USBAEP at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - Reserved_20_20 at 0 range 20 .. 20; - STALL at 0 range 21 .. 21; - TXFNUM at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - Reserved_28_29 at 0 range 28 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for FS_HCFG_Register use record + FSLSPCS at 0 range 0 .. 1; + FSLSS at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; end record; - ---------------------- - -- DIEPINT_Register -- - ---------------------- + subtype HFIR_FRIVL_Field is STM32F40x.UInt16; - subtype DIEPINT0_XFRC_Field is STM32F40x.Bit; - subtype DIEPINT0_EPDISD_Field is STM32F40x.Bit; - subtype DIEPINT0_TOC_Field is STM32F40x.Bit; - subtype DIEPINT0_ITTXFE_Field is STM32F40x.Bit; - subtype DIEPINT0_INEPNE_Field is STM32F40x.Bit; - subtype DIEPINT0_TXFE_Field is STM32F40x.Bit; - - -- device endpoint-x interrupt register - type DIEPINT_Register is record - -- XFRC - XFRC : DIEPINT0_XFRC_Field := 16#0#; - -- EPDISD - EPDISD : DIEPINT0_EPDISD_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- TOC - TOC : DIEPINT0_TOC_Field := 16#0#; - -- ITTXFE - ITTXFE : DIEPINT0_ITTXFE_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F40x.Bit := 16#0#; - -- INEPNE - INEPNE : DIEPINT0_INEPNE_Field := 16#0#; - -- Read-only. TXFE - TXFE : DIEPINT0_TXFE_Field := 16#1#; + -- OTG_FS Host frame interval register + type HFIR_Register is record + -- Frame interval + FRIVL : HFIR_FRIVL_Field := 16#EA60#; -- unspecified - Reserved_8_31 : STM32F40x.UInt24 := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPINT_Register use record - XFRC at 0 range 0 .. 0; - EPDISD at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOC at 0 range 3 .. 3; - ITTXFE at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - INEPNE at 0 range 6 .. 6; - TXFE at 0 range 7 .. 7; - Reserved_8_31 at 0 range 8 .. 31; + for HFIR_Register use record + FRIVL at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------------ - -- DIEPTSIZ0_Register -- - ------------------------ - - subtype DIEPTSIZ0_XFRSIZ_Field is STM32F40x.UInt7; - subtype DIEPTSIZ0_PKTCNT_Field is STM32F40x.UInt2; + subtype FS_HFNUM_FRNUM_Field is STM32F40x.UInt16; + subtype FS_HFNUM_FTREM_Field is STM32F40x.UInt16; - -- device endpoint-0 transfer size register - type DIEPTSIZ0_Register is record - -- Transfer size - XFRSIZ : DIEPTSIZ0_XFRSIZ_Field := 16#0#; - -- unspecified - Reserved_7_18 : STM32F40x.UInt12 := 16#0#; - -- Packet count - PKTCNT : DIEPTSIZ0_PKTCNT_Field := 16#0#; - -- unspecified - Reserved_21_31 : STM32F40x.UInt11 := 16#0#; + -- OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + type FS_HFNUM_Register is record + -- Read-only. Frame number + FRNUM : FS_HFNUM_FRNUM_Field; + -- Read-only. Frame time remaining + FTREM : FS_HFNUM_FTREM_Field; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPTSIZ0_Register use record - XFRSIZ at 0 range 0 .. 6; - Reserved_7_18 at 0 range 7 .. 18; - PKTCNT at 0 range 19 .. 20; - Reserved_21_31 at 0 range 21 .. 31; + for FS_HFNUM_Register use record + FRNUM at 0 range 0 .. 15; + FTREM at 0 range 16 .. 31; end record; - ---------------------- - -- DTXFSTS_Register -- - ---------------------- - - subtype DTXFSTS0_INEPTFSAV_Field is STM32F40x.Short; + subtype FS_HPTXSTS_PTXFSAVL_Field is STM32F40x.UInt16; + subtype FS_HPTXSTS_PTXQSAV_Field is STM32F40x.Byte; + subtype FS_HPTXSTS_PTXQTOP_Field is STM32F40x.Byte; - -- OTG_FS device IN endpoint transmit FIFO status register - type DTXFSTS_Register is record - -- Read-only. IN endpoint TxFIFO space available - INEPTFSAV : DTXFSTS0_INEPTFSAV_Field := 16#0#; - -- unspecified - Reserved_16_31 : STM32F40x.Short; + -- OTG_FS_Host periodic transmit FIFO/queue status register + -- (OTG_FS_HPTXSTS) + type FS_HPTXSTS_Register is record + -- Periodic transmit data FIFO space available + PTXFSAVL : FS_HPTXSTS_PTXFSAVL_Field := 16#100#; + -- Read-only. Periodic transmit request queue space available + PTXQSAV : FS_HPTXSTS_PTXQSAV_Field := 16#8#; + -- Read-only. Top of the periodic transmit request queue + PTXQTOP : FS_HPTXSTS_PTXQTOP_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DTXFSTS_Register use record - INEPTFSAV at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_HPTXSTS_Register use record + PTXFSAVL at 0 range 0 .. 15; + PTXQSAV at 0 range 16 .. 23; + PTXQTOP at 0 range 24 .. 31; end record; - ---------------------- - -- DIEPCTL_Register -- - ---------------------- - - subtype DIEPCTL1_MPSIZ_Field is STM32F40x.UInt11; - subtype DIEPCTL1_USBAEP_Field is STM32F40x.Bit; - subtype DIEPCTL1_EONUM_DPID_Field is STM32F40x.Bit; - subtype DIEPCTL1_NAKSTS_Field is STM32F40x.Bit; - subtype DIEPCTL1_EPTYP_Field is STM32F40x.UInt2; - subtype DIEPCTL1_Stall_Field is STM32F40x.Bit; - subtype DIEPCTL1_TXFNUM_Field is STM32F40x.UInt4; - subtype DIEPCTL1_CNAK_Field is STM32F40x.Bit; - subtype DIEPCTL1_SNAK_Field is STM32F40x.Bit; - subtype DIEPCTL1_SD0PID_SEVNFRM_Field is STM32F40x.Bit; - subtype DIEPCTL1_SODDFRM_SD1PID_Field is STM32F40x.Bit; - subtype DIEPCTL1_EPDIS_Field is STM32F40x.Bit; - subtype DIEPCTL1_EPENA_Field is STM32F40x.Bit; + subtype HAINT_HAINT_Field is STM32F40x.UInt16; - -- OTG device endpoint-1 control register - type DIEPCTL_Register is record - -- MPSIZ - MPSIZ : DIEPCTL1_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_11_14 : STM32F40x.UInt4 := 16#0#; - -- USBAEP - USBAEP : DIEPCTL1_USBAEP_Field := 16#0#; - -- Read-only. EONUM/DPID - EONUM_DPID : DIEPCTL1_EONUM_DPID_Field := 16#0#; - -- Read-only. NAKSTS - NAKSTS : DIEPCTL1_NAKSTS_Field := 16#0#; - -- EPTYP - EPTYP : DIEPCTL1_EPTYP_Field := 16#0#; + -- OTG_FS Host all channels interrupt register + type HAINT_Register is record + -- Read-only. Channel interrupts + HAINT : HAINT_HAINT_Field; -- unspecified - Reserved_20_20 : STM32F40x.Bit := 16#0#; - -- Stall - Stall : DIEPCTL1_Stall_Field := 16#0#; - -- TXFNUM - TXFNUM : DIEPCTL1_TXFNUM_Field := 16#0#; - -- Write-only. CNAK - CNAK : DIEPCTL1_CNAK_Field := 16#0#; - -- Write-only. SNAK - SNAK : DIEPCTL1_SNAK_Field := 16#0#; - -- Write-only. SD0PID/SEVNFRM - SD0PID_SEVNFRM : DIEPCTL1_SD0PID_SEVNFRM_Field := 16#0#; - -- Write-only. SODDFRM/SD1PID - SODDFRM_SD1PID : DIEPCTL1_SODDFRM_SD1PID_Field := 16#0#; - -- EPDIS - EPDIS : DIEPCTL1_EPDIS_Field := 16#0#; - -- EPENA - EPENA : DIEPCTL1_EPENA_Field := 16#0#; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPCTL_Register use record - MPSIZ at 0 range 0 .. 10; - Reserved_11_14 at 0 range 11 .. 14; - USBAEP at 0 range 15 .. 15; - EONUM_DPID at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - Reserved_20_20 at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - TXFNUM at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - SD0PID_SEVNFRM at 0 range 28 .. 28; - SODDFRM_SD1PID at 0 range 29 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for HAINT_Register use record + HAINT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------- - -- DIEPTSIZ_Register -- - ----------------------- + subtype HAINTMSK_HAINTM_Field is STM32F40x.UInt16; - subtype DIEPTSIZ1_XFRSIZ_Field is STM32F40x.UInt19; - subtype DIEPTSIZ1_PKTCNT_Field is STM32F40x.UInt10; - subtype DIEPTSIZ1_MCNT_Field is STM32F40x.UInt2; - - -- device endpoint-1 transfer size register - type DIEPTSIZ_Register is record - -- Transfer size - XFRSIZ : DIEPTSIZ1_XFRSIZ_Field := 16#0#; - -- Packet count - PKTCNT : DIEPTSIZ1_PKTCNT_Field := 16#0#; - -- Multi count - MCNT : DIEPTSIZ1_MCNT_Field := 16#0#; + -- OTG_FS host all channels interrupt mask register + type HAINTMSK_Register is record + -- Channel interrupt mask + HAINTM : HAINTMSK_HAINTM_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F40x.Bit := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPTSIZ_Register use record - XFRSIZ at 0 range 0 .. 18; - PKTCNT at 0 range 19 .. 28; - MCNT at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for HAINTMSK_Register use record + HAINTM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------- - -- DOEPCTL0_Register -- - ----------------------- - - subtype DOEPCTL0_MPSIZ_Field is STM32F40x.UInt2; - subtype DOEPCTL0_USBAEP_Field is STM32F40x.Bit; - subtype DOEPCTL0_NAKSTS_Field is STM32F40x.Bit; - subtype DOEPCTL0_EPTYP_Field is STM32F40x.UInt2; - subtype DOEPCTL0_SNPM_Field is STM32F40x.Bit; - subtype DOEPCTL0_Stall_Field is STM32F40x.Bit; - subtype DOEPCTL0_CNAK_Field is STM32F40x.Bit; - subtype DOEPCTL0_SNAK_Field is STM32F40x.Bit; - subtype DOEPCTL0_EPDIS_Field is STM32F40x.Bit; - subtype DOEPCTL0_EPENA_Field is STM32F40x.Bit; + subtype FS_HPRT_PCSTS_Field is STM32F40x.Bit; + subtype FS_HPRT_PCDET_Field is STM32F40x.Bit; + subtype FS_HPRT_PENA_Field is STM32F40x.Bit; + subtype FS_HPRT_PENCHNG_Field is STM32F40x.Bit; + subtype FS_HPRT_POCA_Field is STM32F40x.Bit; + subtype FS_HPRT_POCCHNG_Field is STM32F40x.Bit; + subtype FS_HPRT_PRES_Field is STM32F40x.Bit; + subtype FS_HPRT_PSUSP_Field is STM32F40x.Bit; + subtype FS_HPRT_PRST_Field is STM32F40x.Bit; + subtype FS_HPRT_PLSTS_Field is STM32F40x.UInt2; + subtype FS_HPRT_PPWR_Field is STM32F40x.Bit; + subtype FS_HPRT_PTCTL_Field is STM32F40x.UInt4; + subtype FS_HPRT_PSPD_Field is STM32F40x.UInt2; - -- device endpoint-0 control register - type DOEPCTL0_Register is record - -- Read-only. MPSIZ - MPSIZ : DOEPCTL0_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_2_14 : STM32F40x.UInt13 := 16#0#; - -- Read-only. USBAEP - USBAEP : DOEPCTL0_USBAEP_Field := 16#1#; - -- unspecified - Reserved_16_16 : STM32F40x.Bit := 16#0#; - -- Read-only. NAKSTS - NAKSTS : DOEPCTL0_NAKSTS_Field := 16#0#; - -- Read-only. EPTYP - EPTYP : DOEPCTL0_EPTYP_Field := 16#0#; - -- SNPM - SNPM : DOEPCTL0_SNPM_Field := 16#0#; - -- Stall - Stall : DOEPCTL0_Stall_Field := 16#0#; + -- OTG_FS host port control and status register (OTG_FS_HPRT) + type FS_HPRT_Register is record + -- Read-only. Port connect status + PCSTS : FS_HPRT_PCSTS_Field := 16#0#; + -- Port connect detected + PCDET : FS_HPRT_PCDET_Field := 16#0#; + -- Port enable + PENA : FS_HPRT_PENA_Field := 16#0#; + -- Port enable/disable change + PENCHNG : FS_HPRT_PENCHNG_Field := 16#0#; + -- Read-only. Port overcurrent active + POCA : FS_HPRT_POCA_Field := 16#0#; + -- Port overcurrent change + POCCHNG : FS_HPRT_POCCHNG_Field := 16#0#; + -- Port resume + PRES : FS_HPRT_PRES_Field := 16#0#; + -- Port suspend + PSUSP : FS_HPRT_PSUSP_Field := 16#0#; + -- Port reset + PRST : FS_HPRT_PRST_Field := 16#0#; -- unspecified - Reserved_22_25 : STM32F40x.UInt4 := 16#0#; - -- Write-only. CNAK - CNAK : DOEPCTL0_CNAK_Field := 16#0#; - -- Write-only. SNAK - SNAK : DOEPCTL0_SNAK_Field := 16#0#; + Reserved_9_9 : STM32F40x.Bit := 16#0#; + -- Read-only. Port line status + PLSTS : FS_HPRT_PLSTS_Field := 16#0#; + -- Port power + PPWR : FS_HPRT_PPWR_Field := 16#0#; + -- Port test control + PTCTL : FS_HPRT_PTCTL_Field := 16#0#; + -- Read-only. Port speed + PSPD : FS_HPRT_PSPD_Field := 16#0#; -- unspecified - Reserved_28_29 : STM32F40x.UInt2 := 16#0#; - -- Read-only. EPDIS - EPDIS : DOEPCTL0_EPDIS_Field := 16#0#; - -- Write-only. EPENA - EPENA : DOEPCTL0_EPENA_Field := 16#0#; + Reserved_19_31 : STM32F40x.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPCTL0_Register use record - MPSIZ at 0 range 0 .. 1; - Reserved_2_14 at 0 range 2 .. 14; - USBAEP at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - SNPM at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - Reserved_22_25 at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - Reserved_28_29 at 0 range 28 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for FS_HPRT_Register use record + PCSTS at 0 range 0 .. 0; + PCDET at 0 range 1 .. 1; + PENA at 0 range 2 .. 2; + PENCHNG at 0 range 3 .. 3; + POCA at 0 range 4 .. 4; + POCCHNG at 0 range 5 .. 5; + PRES at 0 range 6 .. 6; + PSUSP at 0 range 7 .. 7; + PRST at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PLSTS at 0 range 10 .. 11; + PPWR at 0 range 12 .. 12; + PTCTL at 0 range 13 .. 16; + PSPD at 0 range 17 .. 18; + Reserved_19_31 at 0 range 19 .. 31; end record; - ---------------------- - -- DOEPINT_Register -- - ---------------------- + subtype FS_HCCHAR_MPSIZ_Field is STM32F40x.UInt11; + subtype FS_HCCHAR_EPNUM_Field is STM32F40x.UInt4; + subtype FS_HCCHAR_EPDIR_Field is STM32F40x.Bit; + subtype FS_HCCHAR_LSDEV_Field is STM32F40x.Bit; + subtype FS_HCCHAR_EPTYP_Field is STM32F40x.UInt2; + subtype FS_HCCHAR_MCNT_Field is STM32F40x.UInt2; + subtype FS_HCCHAR_DAD_Field is STM32F40x.UInt7; + subtype FS_HCCHAR_ODDFRM_Field is STM32F40x.Bit; + subtype FS_HCCHAR_CHDIS_Field is STM32F40x.Bit; + subtype FS_HCCHAR_CHENA_Field is STM32F40x.Bit; - subtype DOEPINT0_XFRC_Field is STM32F40x.Bit; - subtype DOEPINT0_EPDISD_Field is STM32F40x.Bit; - subtype DOEPINT0_STUP_Field is STM32F40x.Bit; - subtype DOEPINT0_OTEPDIS_Field is STM32F40x.Bit; - subtype DOEPINT0_B2BSTUP_Field is STM32F40x.Bit; - - -- device endpoint-0 interrupt register - type DOEPINT_Register is record - -- XFRC - XFRC : DOEPINT0_XFRC_Field := 16#0#; - -- EPDISD - EPDISD : DOEPINT0_EPDISD_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- STUP - STUP : DOEPINT0_STUP_Field := 16#0#; - -- OTEPDIS - OTEPDIS : DOEPINT0_OTEPDIS_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F40x.Bit := 16#0#; - -- B2BSTUP - B2BSTUP : DOEPINT0_B2BSTUP_Field := 16#0#; + -- OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + type FS_HCCHAR_Register is record + -- Maximum packet size + MPSIZ : FS_HCCHAR_MPSIZ_Field := 16#0#; + -- Endpoint number + EPNUM : FS_HCCHAR_EPNUM_Field := 16#0#; + -- Endpoint direction + EPDIR : FS_HCCHAR_EPDIR_Field := 16#0#; -- unspecified - Reserved_7_31 : STM32F40x.UInt25 := 16#1#; + Reserved_16_16 : STM32F40x.Bit := 16#0#; + -- Low-speed device + LSDEV : FS_HCCHAR_LSDEV_Field := 16#0#; + -- Endpoint type + EPTYP : FS_HCCHAR_EPTYP_Field := 16#0#; + -- Multicount + MCNT : FS_HCCHAR_MCNT_Field := 16#0#; + -- Device address + DAD : FS_HCCHAR_DAD_Field := 16#0#; + -- Odd frame + ODDFRM : FS_HCCHAR_ODDFRM_Field := 16#0#; + -- Channel disable + CHDIS : FS_HCCHAR_CHDIS_Field := 16#0#; + -- Channel enable + CHENA : FS_HCCHAR_CHENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPINT_Register use record - XFRC at 0 range 0 .. 0; - EPDISD at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STUP at 0 range 3 .. 3; - OTEPDIS at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - B2BSTUP at 0 range 6 .. 6; - Reserved_7_31 at 0 range 7 .. 31; + for FS_HCCHAR_Register use record + MPSIZ at 0 range 0 .. 10; + EPNUM at 0 range 11 .. 14; + EPDIR at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + LSDEV at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + MCNT at 0 range 20 .. 21; + DAD at 0 range 22 .. 28; + ODDFRM at 0 range 29 .. 29; + CHDIS at 0 range 30 .. 30; + CHENA at 0 range 31 .. 31; end record; - ------------------------ - -- DOEPTSIZ0_Register -- - ------------------------ - - subtype DOEPTSIZ0_XFRSIZ_Field is STM32F40x.UInt7; - subtype DOEPTSIZ0_PKTCNT_Field is STM32F40x.Bit; - subtype DOEPTSIZ0_STUPCNT_Field is STM32F40x.UInt2; + subtype FS_HCINT_XFRC_Field is STM32F40x.Bit; + subtype FS_HCINT_CHH_Field is STM32F40x.Bit; + subtype FS_HCINT_STALL_Field is STM32F40x.Bit; + subtype FS_HCINT_NAK_Field is STM32F40x.Bit; + subtype FS_HCINT_ACK_Field is STM32F40x.Bit; + subtype FS_HCINT_TXERR_Field is STM32F40x.Bit; + subtype FS_HCINT_BBERR_Field is STM32F40x.Bit; + subtype FS_HCINT_FRMOR_Field is STM32F40x.Bit; + subtype FS_HCINT_DTERR_Field is STM32F40x.Bit; - -- device OUT endpoint-0 transfer size register - type DOEPTSIZ0_Register is record - -- Transfer size - XFRSIZ : DOEPTSIZ0_XFRSIZ_Field := 16#0#; + -- OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + type FS_HCINT_Register is record + -- Transfer completed + XFRC : FS_HCINT_XFRC_Field := 16#0#; + -- Channel halted + CHH : FS_HCINT_CHH_Field := 16#0#; -- unspecified - Reserved_7_18 : STM32F40x.UInt12 := 16#0#; - -- Packet count - PKTCNT : DOEPTSIZ0_PKTCNT_Field := 16#0#; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- STALL response received interrupt + STALL : FS_HCINT_STALL_Field := 16#0#; + -- NAK response received interrupt + NAK : FS_HCINT_NAK_Field := 16#0#; + -- ACK response received/transmitted interrupt + ACK : FS_HCINT_ACK_Field := 16#0#; -- unspecified - Reserved_20_28 : STM32F40x.UInt9 := 16#0#; - -- SETUP packet count - STUPCNT : DOEPTSIZ0_STUPCNT_Field := 16#0#; + Reserved_6_6 : STM32F40x.Bit := 16#0#; + -- Transaction error + TXERR : FS_HCINT_TXERR_Field := 16#0#; + -- Babble error + BBERR : FS_HCINT_BBERR_Field := 16#0#; + -- Frame overrun + FRMOR : FS_HCINT_FRMOR_Field := 16#0#; + -- Data toggle error + DTERR : FS_HCINT_DTERR_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F40x.Bit := 16#0#; + Reserved_11_31 : STM32F40x.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPTSIZ0_Register use record - XFRSIZ at 0 range 0 .. 6; - Reserved_7_18 at 0 range 7 .. 18; - PKTCNT at 0 range 19 .. 19; - Reserved_20_28 at 0 range 20 .. 28; - STUPCNT at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for FS_HCINT_Register use record + XFRC at 0 range 0 .. 0; + CHH at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STALL at 0 range 3 .. 3; + NAK at 0 range 4 .. 4; + ACK at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + TXERR at 0 range 7 .. 7; + BBERR at 0 range 8 .. 8; + FRMOR at 0 range 9 .. 9; + DTERR at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; end record; - ---------------------- - -- DOEPCTL_Register -- - ---------------------- - - subtype DOEPCTL1_MPSIZ_Field is STM32F40x.UInt11; - subtype DOEPCTL1_USBAEP_Field is STM32F40x.Bit; - subtype DOEPCTL1_EONUM_DPID_Field is STM32F40x.Bit; - subtype DOEPCTL1_NAKSTS_Field is STM32F40x.Bit; - subtype DOEPCTL1_EPTYP_Field is STM32F40x.UInt2; - subtype DOEPCTL1_SNPM_Field is STM32F40x.Bit; - subtype DOEPCTL1_Stall_Field is STM32F40x.Bit; - subtype DOEPCTL1_CNAK_Field is STM32F40x.Bit; - subtype DOEPCTL1_SNAK_Field is STM32F40x.Bit; - subtype DOEPCTL1_SD0PID_SEVNFRM_Field is STM32F40x.Bit; - subtype DOEPCTL1_SODDFRM_Field is STM32F40x.Bit; - subtype DOEPCTL1_EPDIS_Field is STM32F40x.Bit; - subtype DOEPCTL1_EPENA_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_XFRCM_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_CHHM_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_STALLM_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_NAKM_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_ACKM_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_NYET_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_TXERRM_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_BBERRM_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_FRMORM_Field is STM32F40x.Bit; + subtype FS_HCINTMSK_DTERRM_Field is STM32F40x.Bit; - -- device endpoint-1 control register - type DOEPCTL_Register is record - -- MPSIZ - MPSIZ : DOEPCTL1_MPSIZ_Field := 16#0#; + -- OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + type FS_HCINTMSK_Register is record + -- Transfer completed mask + XFRCM : FS_HCINTMSK_XFRCM_Field := 16#0#; + -- Channel halted mask + CHHM : FS_HCINTMSK_CHHM_Field := 16#0#; -- unspecified - Reserved_11_14 : STM32F40x.UInt4 := 16#0#; - -- USBAEP - USBAEP : DOEPCTL1_USBAEP_Field := 16#0#; - -- Read-only. EONUM/DPID - EONUM_DPID : DOEPCTL1_EONUM_DPID_Field := 16#0#; - -- Read-only. NAKSTS - NAKSTS : DOEPCTL1_NAKSTS_Field := 16#0#; - -- EPTYP - EPTYP : DOEPCTL1_EPTYP_Field := 16#0#; - -- SNPM - SNPM : DOEPCTL1_SNPM_Field := 16#0#; - -- Stall - Stall : DOEPCTL1_Stall_Field := 16#0#; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- STALL response received interrupt mask + STALLM : FS_HCINTMSK_STALLM_Field := 16#0#; + -- NAK response received interrupt mask + NAKM : FS_HCINTMSK_NAKM_Field := 16#0#; + -- ACK response received/transmitted interrupt mask + ACKM : FS_HCINTMSK_ACKM_Field := 16#0#; + -- response received interrupt mask + NYET : FS_HCINTMSK_NYET_Field := 16#0#; + -- Transaction error mask + TXERRM : FS_HCINTMSK_TXERRM_Field := 16#0#; + -- Babble error mask + BBERRM : FS_HCINTMSK_BBERRM_Field := 16#0#; + -- Frame overrun mask + FRMORM : FS_HCINTMSK_FRMORM_Field := 16#0#; + -- Data toggle error mask + DTERRM : FS_HCINTMSK_DTERRM_Field := 16#0#; -- unspecified - Reserved_22_25 : STM32F40x.UInt4 := 16#0#; - -- Write-only. CNAK - CNAK : DOEPCTL1_CNAK_Field := 16#0#; - -- Write-only. SNAK - SNAK : DOEPCTL1_SNAK_Field := 16#0#; - -- Write-only. SD0PID/SEVNFRM - SD0PID_SEVNFRM : DOEPCTL1_SD0PID_SEVNFRM_Field := 16#0#; - -- Write-only. SODDFRM - SODDFRM : DOEPCTL1_SODDFRM_Field := 16#0#; - -- EPDIS - EPDIS : DOEPCTL1_EPDIS_Field := 16#0#; - -- EPENA - EPENA : DOEPCTL1_EPENA_Field := 16#0#; + Reserved_11_31 : STM32F40x.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPCTL_Register use record - MPSIZ at 0 range 0 .. 10; - Reserved_11_14 at 0 range 11 .. 14; - USBAEP at 0 range 15 .. 15; - EONUM_DPID at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - SNPM at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - Reserved_22_25 at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - SD0PID_SEVNFRM at 0 range 28 .. 28; - SODDFRM at 0 range 29 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for FS_HCINTMSK_Register use record + XFRCM at 0 range 0 .. 0; + CHHM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STALLM at 0 range 3 .. 3; + NAKM at 0 range 4 .. 4; + ACKM at 0 range 5 .. 5; + NYET at 0 range 6 .. 6; + TXERRM at 0 range 7 .. 7; + BBERRM at 0 range 8 .. 8; + FRMORM at 0 range 9 .. 9; + DTERRM at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------- - -- DOEPTSIZ_Register -- - ----------------------- + subtype FS_HCTSIZ_XFRSIZ_Field is STM32F40x.UInt19; + subtype FS_HCTSIZ_PKTCNT_Field is STM32F40x.UInt10; + subtype FS_HCTSIZ_DPID_Field is STM32F40x.UInt2; - subtype DOEPTSIZ1_XFRSIZ_Field is STM32F40x.UInt19; - subtype DOEPTSIZ1_PKTCNT_Field is STM32F40x.UInt10; - subtype DOEPTSIZ1_RXDPID_STUPCNT_Field is STM32F40x.UInt2; - - -- device OUT endpoint-1 transfer size register - type DOEPTSIZ_Register is record + -- OTG_FS host channel-0 transfer size register + type FS_HCTSIZ_Register is record -- Transfer size - XFRSIZ : DOEPTSIZ1_XFRSIZ_Field := 16#0#; + XFRSIZ : FS_HCTSIZ_XFRSIZ_Field := 16#0#; -- Packet count - PKTCNT : DOEPTSIZ1_PKTCNT_Field := 16#0#; - -- Received data PID/SETUP packet count - RXDPID_STUPCNT : DOEPTSIZ1_RXDPID_STUPCNT_Field := 16#0#; + PKTCNT : FS_HCTSIZ_PKTCNT_Field := 16#0#; + -- Data PID + DPID : FS_HCTSIZ_DPID_Field := 16#0#; -- unspecified Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPTSIZ_Register use record + for FS_HCTSIZ_Register use record XFRSIZ at 0 range 0 .. 18; PKTCNT at 0 range 19 .. 28; - RXDPID_STUPCNT at 0 range 29 .. 30; + DPID at 0 range 29 .. 30; Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------- - -- FS_PCGCCTL_Register -- - ------------------------- - subtype FS_PCGCCTL_STPPCLK_Field is STM32F40x.Bit; subtype FS_PCGCCTL_GATEHCLK_Field is STM32F40x.Bit; subtype FS_PCGCCTL_PHYSUSP_Field is STM32F40x.Bit; @@ -2031,8 +1855,7 @@ package STM32F40x.USB_OTG_FS is -- unspecified Reserved_5_31 : STM32F40x.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FS_PCGCCTL_Register use record STPPCLK at 0 range 0 .. 0; @@ -2046,84 +1869,268 @@ package STM32F40x.USB_OTG_FS is -- Peripherals -- ----------------- - type OTG_FS_Mode is - ( - Host, - Device); + -- USB on the go full speed + type OTG_FS_DEVICE_Peripheral is record + -- OTG_FS device configuration register (OTG_FS_DCFG) + FS_DCFG : aliased FS_DCFG_Register; + pragma Volatile_Full_Access (FS_DCFG); + -- OTG_FS device control register (OTG_FS_DCTL) + FS_DCTL : aliased FS_DCTL_Register; + pragma Volatile_Full_Access (FS_DCTL); + -- OTG_FS device status register (OTG_FS_DSTS) + FS_DSTS : aliased FS_DSTS_Register; + pragma Volatile_Full_Access (FS_DSTS); + -- OTG_FS device IN endpoint common interrupt mask register + -- (OTG_FS_DIEPMSK) + FS_DIEPMSK : aliased FS_DIEPMSK_Register; + pragma Volatile_Full_Access (FS_DIEPMSK); + -- OTG_FS device OUT endpoint common interrupt mask register + -- (OTG_FS_DOEPMSK) + FS_DOEPMSK : aliased FS_DOEPMSK_Register; + pragma Volatile_Full_Access (FS_DOEPMSK); + -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + FS_DAINT : aliased FS_DAINT_Register; + pragma Volatile_Full_Access (FS_DAINT); + -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + FS_DAINTMSK : aliased FS_DAINTMSK_Register; + pragma Volatile_Full_Access (FS_DAINTMSK); + -- OTG_FS device VBUS discharge time register + DVBUSDIS : aliased DVBUSDIS_Register; + pragma Volatile_Full_Access (DVBUSDIS); + -- OTG_FS device VBUS pulsing time register + DVBUSPULSE : aliased DVBUSPULSE_Register; + pragma Volatile_Full_Access (DVBUSPULSE); + -- OTG_FS device IN endpoint FIFO empty interrupt mask register + DIEPEMPMSK : aliased DIEPEMPMSK_Register; + pragma Volatile_Full_Access (DIEPEMPMSK); + -- OTG_FS device control IN endpoint 0 control register + -- (OTG_FS_DIEPCTL0) + FS_DIEPCTL0 : aliased FS_DIEPCTL0_Register; + pragma Volatile_Full_Access (FS_DIEPCTL0); + -- device endpoint-x interrupt register + DIEPINT0 : aliased DIEPINT_Register; + pragma Volatile_Full_Access (DIEPINT0); + -- device endpoint-0 transfer size register + DIEPTSIZ0 : aliased DIEPTSIZ0_Register; + pragma Volatile_Full_Access (DIEPTSIZ0); + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS0 : aliased DTXFSTS_Register; + pragma Volatile_Full_Access (DTXFSTS0); + -- OTG device endpoint-1 control register + DIEPCTL1 : aliased DIEPCTL1_Register; + pragma Volatile_Full_Access (DIEPCTL1); + -- device endpoint-1 interrupt register + DIEPINT1 : aliased DIEPINT_Register; + pragma Volatile_Full_Access (DIEPINT1); + -- device endpoint-1 transfer size register + DIEPTSIZ1 : aliased DIEPTSIZ_Register; + pragma Volatile_Full_Access (DIEPTSIZ1); + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS1 : aliased DTXFSTS_Register; + pragma Volatile_Full_Access (DTXFSTS1); + -- OTG device endpoint-2 control register + DIEPCTL2 : aliased DIEPCTL_Register; + pragma Volatile_Full_Access (DIEPCTL2); + -- device endpoint-2 interrupt register + DIEPINT2 : aliased DIEPINT_Register; + pragma Volatile_Full_Access (DIEPINT2); + -- device endpoint-2 transfer size register + DIEPTSIZ2 : aliased DIEPTSIZ_Register; + pragma Volatile_Full_Access (DIEPTSIZ2); + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS2 : aliased DTXFSTS_Register; + pragma Volatile_Full_Access (DTXFSTS2); + -- OTG device endpoint-3 control register + DIEPCTL3 : aliased DIEPCTL_Register; + pragma Volatile_Full_Access (DIEPCTL3); + -- device endpoint-3 interrupt register + DIEPINT3 : aliased DIEPINT_Register; + pragma Volatile_Full_Access (DIEPINT3); + -- device endpoint-3 transfer size register + DIEPTSIZ3 : aliased DIEPTSIZ_Register; + pragma Volatile_Full_Access (DIEPTSIZ3); + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS3 : aliased DTXFSTS_Register; + pragma Volatile_Full_Access (DTXFSTS3); + -- device endpoint-0 control register + DOEPCTL0 : aliased DOEPCTL0_Register; + pragma Volatile_Full_Access (DOEPCTL0); + -- device endpoint-0 interrupt register + DOEPINT0 : aliased DOEPINT_Register; + pragma Volatile_Full_Access (DOEPINT0); + -- device OUT endpoint-0 transfer size register + DOEPTSIZ0 : aliased DOEPTSIZ0_Register; + pragma Volatile_Full_Access (DOEPTSIZ0); + -- device endpoint-1 control register + DOEPCTL1 : aliased DOEPCTL_Register; + pragma Volatile_Full_Access (DOEPCTL1); + -- device endpoint-1 interrupt register + DOEPINT1 : aliased DOEPINT_Register; + pragma Volatile_Full_Access (DOEPINT1); + -- device OUT endpoint-1 transfer size register + DOEPTSIZ1 : aliased DOEPTSIZ_Register; + pragma Volatile_Full_Access (DOEPTSIZ1); + -- device endpoint-2 control register + DOEPCTL2 : aliased DOEPCTL_Register; + pragma Volatile_Full_Access (DOEPCTL2); + -- device endpoint-2 interrupt register + DOEPINT2 : aliased DOEPINT_Register; + pragma Volatile_Full_Access (DOEPINT2); + -- device OUT endpoint-2 transfer size register + DOEPTSIZ2 : aliased DOEPTSIZ_Register; + pragma Volatile_Full_Access (DOEPTSIZ2); + -- device endpoint-3 control register + DOEPCTL3 : aliased DOEPCTL_Register; + pragma Volatile_Full_Access (DOEPCTL3); + -- device endpoint-3 interrupt register + DOEPINT3 : aliased DOEPINT_Register; + pragma Volatile_Full_Access (DOEPINT3); + -- device OUT endpoint-3 transfer size register + DOEPTSIZ3 : aliased DOEPTSIZ_Register; + pragma Volatile_Full_Access (DOEPTSIZ3); + end record + with Volatile; + + for OTG_FS_DEVICE_Peripheral use record + FS_DCFG at 16#0# range 0 .. 31; + FS_DCTL at 16#4# range 0 .. 31; + FS_DSTS at 16#8# range 0 .. 31; + FS_DIEPMSK at 16#10# range 0 .. 31; + FS_DOEPMSK at 16#14# range 0 .. 31; + FS_DAINT at 16#18# range 0 .. 31; + FS_DAINTMSK at 16#1C# range 0 .. 31; + DVBUSDIS at 16#28# range 0 .. 31; + DVBUSPULSE at 16#2C# range 0 .. 31; + DIEPEMPMSK at 16#34# range 0 .. 31; + FS_DIEPCTL0 at 16#100# range 0 .. 31; + DIEPINT0 at 16#108# range 0 .. 31; + DIEPTSIZ0 at 16#110# range 0 .. 31; + DTXFSTS0 at 16#118# range 0 .. 31; + DIEPCTL1 at 16#120# range 0 .. 31; + DIEPINT1 at 16#128# range 0 .. 31; + DIEPTSIZ1 at 16#130# range 0 .. 31; + DTXFSTS1 at 16#138# range 0 .. 31; + DIEPCTL2 at 16#140# range 0 .. 31; + DIEPINT2 at 16#148# range 0 .. 31; + DIEPTSIZ2 at 16#150# range 0 .. 31; + DTXFSTS2 at 16#158# range 0 .. 31; + DIEPCTL3 at 16#160# range 0 .. 31; + DIEPINT3 at 16#168# range 0 .. 31; + DIEPTSIZ3 at 16#170# range 0 .. 31; + DTXFSTS3 at 16#178# range 0 .. 31; + DOEPCTL0 at 16#300# range 0 .. 31; + DOEPINT0 at 16#308# range 0 .. 31; + DOEPTSIZ0 at 16#310# range 0 .. 31; + DOEPCTL1 at 16#320# range 0 .. 31; + DOEPINT1 at 16#328# range 0 .. 31; + DOEPTSIZ1 at 16#330# range 0 .. 31; + DOEPCTL2 at 16#340# range 0 .. 31; + DOEPINT2 at 16#348# range 0 .. 31; + DOEPTSIZ2 at 16#350# range 0 .. 31; + DOEPCTL3 at 16#360# range 0 .. 31; + DOEPINT3 at 16#368# range 0 .. 31; + DOEPTSIZ3 at 16#370# range 0 .. 31; + end record; + + -- USB on the go full speed + OTG_FS_DEVICE_Periph : aliased OTG_FS_DEVICE_Peripheral + with Import, Address => OTG_FS_DEVICE_Base; + + type OTG_FS_GLOBAL_Disc is + (Device, + Host); -- USB on the go full speed type OTG_FS_GLOBAL_Peripheral - (Mode : OTG_FS_Mode := Host) + (Discriminent : OTG_FS_GLOBAL_Disc := Device) is record -- OTG_FS control and status register (OTG_FS_GOTGCTL) - FS_GOTGCTL : FS_GOTGCTL_Register; + FS_GOTGCTL : aliased FS_GOTGCTL_Register; + pragma Volatile_Full_Access (FS_GOTGCTL); -- OTG_FS interrupt register (OTG_FS_GOTGINT) - FS_GOTGINT : FS_GOTGINT_Register; + FS_GOTGINT : aliased FS_GOTGINT_Register; + pragma Volatile_Full_Access (FS_GOTGINT); -- OTG_FS AHB configuration register (OTG_FS_GAHBCFG) - FS_GAHBCFG : FS_GAHBCFG_Register; + FS_GAHBCFG : aliased FS_GAHBCFG_Register; + pragma Volatile_Full_Access (FS_GAHBCFG); -- OTG_FS USB configuration register (OTG_FS_GUSBCFG) - FS_GUSBCFG : FS_GUSBCFG_Register; + FS_GUSBCFG : aliased FS_GUSBCFG_Register; + pragma Volatile_Full_Access (FS_GUSBCFG); -- OTG_FS reset register (OTG_FS_GRSTCTL) - FS_GRSTCTL : FS_GRSTCTL_Register; + FS_GRSTCTL : aliased FS_GRSTCTL_Register; + pragma Volatile_Full_Access (FS_GRSTCTL); -- OTG_FS core interrupt register (OTG_FS_GINTSTS) - FS_GINTSTS : FS_GINTSTS_Register; + FS_GINTSTS : aliased FS_GINTSTS_Register; + pragma Volatile_Full_Access (FS_GINTSTS); -- OTG_FS interrupt mask register (OTG_FS_GINTMSK) - FS_GINTMSK : FS_GINTMSK_Register; + FS_GINTMSK : aliased FS_GINTMSK_Register; + pragma Volatile_Full_Access (FS_GINTMSK); -- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) - FS_GRXFSIZ : FS_GRXFSIZ_Register; + FS_GRXFSIZ : aliased FS_GRXFSIZ_Register; + pragma Volatile_Full_Access (FS_GRXFSIZ); -- OTG_FS non-periodic transmit FIFO/queue status register -- (OTG_FS_GNPTXSTS) - FS_GNPTXSTS : FS_GNPTXSTS_Register; + FS_GNPTXSTS : aliased FS_GNPTXSTS_Register; + pragma Volatile_Full_Access (FS_GNPTXSTS); -- OTG_FS general core configuration register (OTG_FS_GCCFG) - FS_GCCFG : FS_GCCFG_Register; + FS_GCCFG : aliased FS_GCCFG_Register; + pragma Volatile_Full_Access (FS_GCCFG); -- core ID register - FS_CID : STM32F40x.Word; + FS_CID : aliased STM32F40x.UInt32; -- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) - FS_HPTXFSIZ : FS_HPTXFSIZ_Register; + FS_HPTXFSIZ : aliased FS_HPTXFSIZ_Register; + pragma Volatile_Full_Access (FS_HPTXFSIZ); -- OTG_FS device IN endpoint transmit FIFO size register -- (OTG_FS_DIEPTXF2) - FS_DIEPTXF1 : FS_DIEPTXF_Register; + FS_DIEPTXF1 : aliased FS_DIEPTXF_Register; + pragma Volatile_Full_Access (FS_DIEPTXF1); -- OTG_FS device IN endpoint transmit FIFO size register -- (OTG_FS_DIEPTXF3) - FS_DIEPTXF2 : FS_DIEPTXF_Register; + FS_DIEPTXF2 : aliased FS_DIEPTXF_Register; + pragma Volatile_Full_Access (FS_DIEPTXF2); -- OTG_FS device IN endpoint transmit FIFO size register -- (OTG_FS_DIEPTXF4) - FS_DIEPTXF3 : FS_DIEPTXF_Register; - case Mode is - when Host => - -- OTG_FS Receive status debug read(Host mode) - FS_GRXSTSR_Host : FS_GRXSTSR_Host_Register; - -- OTG_FS non-periodic transmit FIFO size register (Host mode) - FS_GNPTXFSIZ_Host : FS_GNPTXFSIZ_Host_Register; + FS_DIEPTXF3 : aliased FS_DIEPTXF_Register; + pragma Volatile_Full_Access (FS_DIEPTXF3); + case Discriminent is when Device => -- OTG_FS Receive status debug read(Device mode) - FS_GRXSTSR_Device : FS_GRXSTSR_Device_Register; + FS_GRXSTSR_Device : aliased FS_GRXSTSR_Device_Register; + pragma Volatile_Full_Access (FS_GRXSTSR_Device); -- OTG_FS non-periodic transmit FIFO size register (Device mode) - FS_GNPTXFSIZ_Device : FS_GNPTXFSIZ_Device_Register; + FS_GNPTXFSIZ_Device : aliased FS_GNPTXFSIZ_Device_Register; + pragma Volatile_Full_Access (FS_GNPTXFSIZ_Device); + when Host => + -- OTG_FS Receive status debug read(Host mode) + FS_GRXSTSR_Host : aliased FS_GRXSTSR_Host_Register; + pragma Volatile_Full_Access (FS_GRXSTSR_Host); + -- OTG_FS non-periodic transmit FIFO size register (Host mode) + FS_GNPTXFSIZ_Host : aliased FS_GNPTXFSIZ_Host_Register; + pragma Volatile_Full_Access (FS_GNPTXFSIZ_Host); end case; end record with Unchecked_Union, Volatile; for OTG_FS_GLOBAL_Peripheral use record - FS_GOTGCTL at 0 range 0 .. 31; - FS_GOTGINT at 4 range 0 .. 31; - FS_GAHBCFG at 8 range 0 .. 31; - FS_GUSBCFG at 12 range 0 .. 31; - FS_GRSTCTL at 16 range 0 .. 31; - FS_GINTSTS at 20 range 0 .. 31; - FS_GINTMSK at 24 range 0 .. 31; - FS_GRXFSIZ at 36 range 0 .. 31; - FS_GNPTXSTS at 44 range 0 .. 31; - FS_GCCFG at 56 range 0 .. 31; - FS_CID at 60 range 0 .. 31; - FS_HPTXFSIZ at 256 range 0 .. 31; - FS_DIEPTXF1 at 260 range 0 .. 31; - FS_DIEPTXF2 at 264 range 0 .. 31; - FS_DIEPTXF3 at 268 range 0 .. 31; - FS_GRXSTSR_Host at 28 range 0 .. 31; - FS_GNPTXFSIZ_Host at 40 range 0 .. 31; - FS_GRXSTSR_Device at 28 range 0 .. 31; - FS_GNPTXFSIZ_Device at 40 range 0 .. 31; + FS_GOTGCTL at 16#0# range 0 .. 31; + FS_GOTGINT at 16#4# range 0 .. 31; + FS_GAHBCFG at 16#8# range 0 .. 31; + FS_GUSBCFG at 16#C# range 0 .. 31; + FS_GRSTCTL at 16#10# range 0 .. 31; + FS_GINTSTS at 16#14# range 0 .. 31; + FS_GINTMSK at 16#18# range 0 .. 31; + FS_GRXFSIZ at 16#24# range 0 .. 31; + FS_GNPTXSTS at 16#2C# range 0 .. 31; + FS_GCCFG at 16#38# range 0 .. 31; + FS_CID at 16#3C# range 0 .. 31; + FS_HPTXFSIZ at 16#100# range 0 .. 31; + FS_DIEPTXF1 at 16#104# range 0 .. 31; + FS_DIEPTXF2 at 16#108# range 0 .. 31; + FS_DIEPTXF3 at 16#10C# range 0 .. 31; + FS_GRXSTSR_Device at 16#1C# range 0 .. 31; + FS_GNPTXFSIZ_Device at 16#28# range 0 .. 31; + FS_GRXSTSR_Host at 16#1C# range 0 .. 31; + FS_GNPTXFSIZ_Host at 16#28# range 0 .. 31; end record; -- USB on the go full speed @@ -2133,266 +2140,177 @@ package STM32F40x.USB_OTG_FS is -- USB on the go full speed type OTG_FS_HOST_Peripheral is record -- OTG_FS host configuration register (OTG_FS_HCFG) - FS_HCFG : FS_HCFG_Register; + FS_HCFG : aliased FS_HCFG_Register; + pragma Volatile_Full_Access (FS_HCFG); -- OTG_FS Host frame interval register - HFIR : HFIR_Register; + HFIR : aliased HFIR_Register; + pragma Volatile_Full_Access (HFIR); -- OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) - FS_HFNUM : FS_HFNUM_Register; + FS_HFNUM : aliased FS_HFNUM_Register; + pragma Volatile_Full_Access (FS_HFNUM); -- OTG_FS_Host periodic transmit FIFO/queue status register -- (OTG_FS_HPTXSTS) - FS_HPTXSTS : FS_HPTXSTS_Register; + FS_HPTXSTS : aliased FS_HPTXSTS_Register; + pragma Volatile_Full_Access (FS_HPTXSTS); -- OTG_FS Host all channels interrupt register - HAINT : HAINT_Register; + HAINT : aliased HAINT_Register; + pragma Volatile_Full_Access (HAINT); -- OTG_FS host all channels interrupt mask register - HAINTMSK : HAINTMSK_Register; + HAINTMSK : aliased HAINTMSK_Register; + pragma Volatile_Full_Access (HAINTMSK); -- OTG_FS host port control and status register (OTG_FS_HPRT) - FS_HPRT : FS_HPRT_Register; + FS_HPRT : aliased FS_HPRT_Register; + pragma Volatile_Full_Access (FS_HPRT); -- OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) - FS_HCCHAR0 : FS_HCCHAR_Register; + FS_HCCHAR0 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR0); -- OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) - FS_HCINT0 : FS_HCINT_Register; + FS_HCINT0 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT0); -- OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) - FS_HCINTMSK0 : FS_HCINTMSK_Register; + FS_HCINTMSK0 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK0); -- OTG_FS host channel-0 transfer size register - FS_HCTSIZ0 : FS_HCTSIZ_Register; + FS_HCTSIZ0 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ0); -- OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) - FS_HCCHAR1 : FS_HCCHAR_Register; + FS_HCCHAR1 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR1); -- OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) - FS_HCINT1 : FS_HCINT_Register; + FS_HCINT1 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT1); -- OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) - FS_HCINTMSK1 : FS_HCINTMSK_Register; + FS_HCINTMSK1 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK1); -- OTG_FS host channel-1 transfer size register - FS_HCTSIZ1 : FS_HCTSIZ_Register; + FS_HCTSIZ1 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ1); -- OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) - FS_HCCHAR2 : FS_HCCHAR_Register; + FS_HCCHAR2 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR2); -- OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) - FS_HCINT2 : FS_HCINT_Register; + FS_HCINT2 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT2); -- OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) - FS_HCINTMSK2 : FS_HCINTMSK_Register; + FS_HCINTMSK2 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK2); -- OTG_FS host channel-2 transfer size register - FS_HCTSIZ2 : FS_HCTSIZ_Register; + FS_HCTSIZ2 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ2); -- OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) - FS_HCCHAR3 : FS_HCCHAR_Register; + FS_HCCHAR3 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR3); -- OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) - FS_HCINT3 : FS_HCINT_Register; + FS_HCINT3 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT3); -- OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) - FS_HCINTMSK3 : FS_HCINTMSK_Register; + FS_HCINTMSK3 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK3); -- OTG_FS host channel-3 transfer size register - FS_HCTSIZ3 : FS_HCTSIZ_Register; + FS_HCTSIZ3 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ3); -- OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) - FS_HCCHAR4 : FS_HCCHAR_Register; + FS_HCCHAR4 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR4); -- OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) - FS_HCINT4 : FS_HCINT_Register; + FS_HCINT4 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT4); -- OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) - FS_HCINTMSK4 : FS_HCINTMSK_Register; + FS_HCINTMSK4 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK4); -- OTG_FS host channel-x transfer size register - FS_HCTSIZ4 : FS_HCTSIZ_Register; + FS_HCTSIZ4 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ4); -- OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) - FS_HCCHAR5 : FS_HCCHAR_Register; + FS_HCCHAR5 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR5); -- OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) - FS_HCINT5 : FS_HCINT_Register; + FS_HCINT5 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT5); -- OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) - FS_HCINTMSK5 : FS_HCINTMSK_Register; + FS_HCINTMSK5 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK5); -- OTG_FS host channel-5 transfer size register - FS_HCTSIZ5 : FS_HCTSIZ_Register; + FS_HCTSIZ5 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ5); -- OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) - FS_HCCHAR6 : FS_HCCHAR_Register; + FS_HCCHAR6 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR6); -- OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) - FS_HCINT6 : FS_HCINT_Register; + FS_HCINT6 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT6); -- OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) - FS_HCINTMSK6 : FS_HCINTMSK_Register; + FS_HCINTMSK6 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK6); -- OTG_FS host channel-6 transfer size register - FS_HCTSIZ6 : FS_HCTSIZ_Register; + FS_HCTSIZ6 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ6); -- OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) - FS_HCCHAR7 : FS_HCCHAR_Register; + FS_HCCHAR7 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR7); -- OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) - FS_HCINT7 : FS_HCINT_Register; + FS_HCINT7 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT7); -- OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) - FS_HCINTMSK7 : FS_HCINTMSK_Register; + FS_HCINTMSK7 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK7); -- OTG_FS host channel-7 transfer size register - FS_HCTSIZ7 : FS_HCTSIZ_Register; + FS_HCTSIZ7 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ7); end record with Volatile; for OTG_FS_HOST_Peripheral use record - FS_HCFG at 0 range 0 .. 31; - HFIR at 4 range 0 .. 31; - FS_HFNUM at 8 range 0 .. 31; - FS_HPTXSTS at 16 range 0 .. 31; - HAINT at 20 range 0 .. 31; - HAINTMSK at 24 range 0 .. 31; - FS_HPRT at 64 range 0 .. 31; - FS_HCCHAR0 at 256 range 0 .. 31; - FS_HCINT0 at 264 range 0 .. 31; - FS_HCINTMSK0 at 268 range 0 .. 31; - FS_HCTSIZ0 at 272 range 0 .. 31; - FS_HCCHAR1 at 288 range 0 .. 31; - FS_HCINT1 at 296 range 0 .. 31; - FS_HCINTMSK1 at 300 range 0 .. 31; - FS_HCTSIZ1 at 304 range 0 .. 31; - FS_HCCHAR2 at 320 range 0 .. 31; - FS_HCINT2 at 328 range 0 .. 31; - FS_HCINTMSK2 at 332 range 0 .. 31; - FS_HCTSIZ2 at 336 range 0 .. 31; - FS_HCCHAR3 at 352 range 0 .. 31; - FS_HCINT3 at 360 range 0 .. 31; - FS_HCINTMSK3 at 364 range 0 .. 31; - FS_HCTSIZ3 at 368 range 0 .. 31; - FS_HCCHAR4 at 384 range 0 .. 31; - FS_HCINT4 at 392 range 0 .. 31; - FS_HCINTMSK4 at 396 range 0 .. 31; - FS_HCTSIZ4 at 400 range 0 .. 31; - FS_HCCHAR5 at 416 range 0 .. 31; - FS_HCINT5 at 424 range 0 .. 31; - FS_HCINTMSK5 at 428 range 0 .. 31; - FS_HCTSIZ5 at 432 range 0 .. 31; - FS_HCCHAR6 at 448 range 0 .. 31; - FS_HCINT6 at 456 range 0 .. 31; - FS_HCINTMSK6 at 460 range 0 .. 31; - FS_HCTSIZ6 at 464 range 0 .. 31; - FS_HCCHAR7 at 480 range 0 .. 31; - FS_HCINT7 at 488 range 0 .. 31; - FS_HCINTMSK7 at 492 range 0 .. 31; - FS_HCTSIZ7 at 496 range 0 .. 31; + FS_HCFG at 16#0# range 0 .. 31; + HFIR at 16#4# range 0 .. 31; + FS_HFNUM at 16#8# range 0 .. 31; + FS_HPTXSTS at 16#10# range 0 .. 31; + HAINT at 16#14# range 0 .. 31; + HAINTMSK at 16#18# range 0 .. 31; + FS_HPRT at 16#40# range 0 .. 31; + FS_HCCHAR0 at 16#100# range 0 .. 31; + FS_HCINT0 at 16#108# range 0 .. 31; + FS_HCINTMSK0 at 16#10C# range 0 .. 31; + FS_HCTSIZ0 at 16#110# range 0 .. 31; + FS_HCCHAR1 at 16#120# range 0 .. 31; + FS_HCINT1 at 16#128# range 0 .. 31; + FS_HCINTMSK1 at 16#12C# range 0 .. 31; + FS_HCTSIZ1 at 16#130# range 0 .. 31; + FS_HCCHAR2 at 16#140# range 0 .. 31; + FS_HCINT2 at 16#148# range 0 .. 31; + FS_HCINTMSK2 at 16#14C# range 0 .. 31; + FS_HCTSIZ2 at 16#150# range 0 .. 31; + FS_HCCHAR3 at 16#160# range 0 .. 31; + FS_HCINT3 at 16#168# range 0 .. 31; + FS_HCINTMSK3 at 16#16C# range 0 .. 31; + FS_HCTSIZ3 at 16#170# range 0 .. 31; + FS_HCCHAR4 at 16#180# range 0 .. 31; + FS_HCINT4 at 16#188# range 0 .. 31; + FS_HCINTMSK4 at 16#18C# range 0 .. 31; + FS_HCTSIZ4 at 16#190# range 0 .. 31; + FS_HCCHAR5 at 16#1A0# range 0 .. 31; + FS_HCINT5 at 16#1A8# range 0 .. 31; + FS_HCINTMSK5 at 16#1AC# range 0 .. 31; + FS_HCTSIZ5 at 16#1B0# range 0 .. 31; + FS_HCCHAR6 at 16#1C0# range 0 .. 31; + FS_HCINT6 at 16#1C8# range 0 .. 31; + FS_HCINTMSK6 at 16#1CC# range 0 .. 31; + FS_HCTSIZ6 at 16#1D0# range 0 .. 31; + FS_HCCHAR7 at 16#1E0# range 0 .. 31; + FS_HCINT7 at 16#1E8# range 0 .. 31; + FS_HCINTMSK7 at 16#1EC# range 0 .. 31; + FS_HCTSIZ7 at 16#1F0# range 0 .. 31; end record; -- USB on the go full speed OTG_FS_HOST_Periph : aliased OTG_FS_HOST_Peripheral with Import, Address => OTG_FS_HOST_Base; - -- USB on the go full speed - type OTG_FS_DEVICE_Peripheral is record - -- OTG_FS device configuration register (OTG_FS_DCFG) - FS_DCFG : FS_DCFG_Register; - -- OTG_FS device control register (OTG_FS_DCTL) - FS_DCTL : FS_DCTL_Register; - -- OTG_FS device status register (OTG_FS_DSTS) - FS_DSTS : FS_DSTS_Register; - -- OTG_FS device IN endpoint common interrupt mask register - -- (OTG_FS_DIEPMSK) - FS_DIEPMSK : FS_DIEPMSK_Register; - -- OTG_FS device OUT endpoint common interrupt mask register - -- (OTG_FS_DOEPMSK) - FS_DOEPMSK : FS_DOEPMSK_Register; - -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) - FS_DAINT : FS_DAINT_Register; - -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) - FS_DAINTMSK : FS_DAINTMSK_Register; - -- OTG_FS device VBUS discharge time register - DVBUSDIS : DVBUSDIS_Register; - -- OTG_FS device VBUS pulsing time register - DVBUSPULSE : DVBUSPULSE_Register; - -- OTG_FS device IN endpoint FIFO empty interrupt mask register - DIEPEMPMSK : DIEPEMPMSK_Register; - -- OTG_FS device control IN endpoint 0 control register - -- (OTG_FS_DIEPCTL0) - FS_DIEPCTL0 : FS_DIEPCTL0_Register; - -- device endpoint-x interrupt register - DIEPINT0 : DIEPINT_Register; - -- device endpoint-0 transfer size register - DIEPTSIZ0 : DIEPTSIZ0_Register; - -- OTG_FS device IN endpoint transmit FIFO status register - DTXFSTS0 : DTXFSTS_Register; - -- OTG device endpoint-1 control register - DIEPCTL1 : DIEPCTL_Register; - -- device endpoint-1 interrupt register - DIEPINT1 : DIEPINT_Register; - -- device endpoint-1 transfer size register - DIEPTSIZ1 : DIEPTSIZ_Register; - -- OTG_FS device IN endpoint transmit FIFO status register - DTXFSTS1 : DTXFSTS_Register; - -- OTG device endpoint-2 control register - DIEPCTL2 : DIEPCTL_Register; - -- device endpoint-2 interrupt register - DIEPINT2 : DIEPINT_Register; - -- device endpoint-2 transfer size register - DIEPTSIZ2 : DIEPTSIZ_Register; - -- OTG_FS device IN endpoint transmit FIFO status register - DTXFSTS2 : DTXFSTS_Register; - -- OTG device endpoint-3 control register - DIEPCTL3 : DIEPCTL_Register; - -- device endpoint-3 interrupt register - DIEPINT3 : DIEPINT_Register; - -- device endpoint-3 transfer size register - DIEPTSIZ3 : DIEPTSIZ_Register; - -- OTG_FS device IN endpoint transmit FIFO status register - DTXFSTS3 : DTXFSTS_Register; - -- device endpoint-0 control register - DOEPCTL0 : DOEPCTL0_Register; - -- device endpoint-0 interrupt register - DOEPINT0 : DOEPINT_Register; - -- device OUT endpoint-0 transfer size register - DOEPTSIZ0 : DOEPTSIZ0_Register; - -- device endpoint-1 control register - DOEPCTL1 : DOEPCTL_Register; - -- device endpoint-1 interrupt register - DOEPINT1 : DOEPINT_Register; - -- device OUT endpoint-1 transfer size register - DOEPTSIZ1 : DOEPTSIZ_Register; - -- device endpoint-2 control register - DOEPCTL2 : DOEPCTL_Register; - -- device endpoint-2 interrupt register - DOEPINT2 : DOEPINT_Register; - -- device OUT endpoint-2 transfer size register - DOEPTSIZ2 : DOEPTSIZ_Register; - -- device endpoint-3 control register - DOEPCTL3 : DOEPCTL_Register; - -- device endpoint-3 interrupt register - DOEPINT3 : DOEPINT_Register; - -- device OUT endpoint-3 transfer size register - DOEPTSIZ3 : DOEPTSIZ_Register; - end record - with Volatile; - - for OTG_FS_DEVICE_Peripheral use record - FS_DCFG at 0 range 0 .. 31; - FS_DCTL at 4 range 0 .. 31; - FS_DSTS at 8 range 0 .. 31; - FS_DIEPMSK at 16 range 0 .. 31; - FS_DOEPMSK at 20 range 0 .. 31; - FS_DAINT at 24 range 0 .. 31; - FS_DAINTMSK at 28 range 0 .. 31; - DVBUSDIS at 40 range 0 .. 31; - DVBUSPULSE at 44 range 0 .. 31; - DIEPEMPMSK at 52 range 0 .. 31; - FS_DIEPCTL0 at 256 range 0 .. 31; - DIEPINT0 at 264 range 0 .. 31; - DIEPTSIZ0 at 272 range 0 .. 31; - DTXFSTS0 at 280 range 0 .. 31; - DIEPCTL1 at 288 range 0 .. 31; - DIEPINT1 at 296 range 0 .. 31; - DIEPTSIZ1 at 304 range 0 .. 31; - DTXFSTS1 at 312 range 0 .. 31; - DIEPCTL2 at 320 range 0 .. 31; - DIEPINT2 at 328 range 0 .. 31; - DIEPTSIZ2 at 336 range 0 .. 31; - DTXFSTS2 at 344 range 0 .. 31; - DIEPCTL3 at 352 range 0 .. 31; - DIEPINT3 at 360 range 0 .. 31; - DIEPTSIZ3 at 368 range 0 .. 31; - DTXFSTS3 at 376 range 0 .. 31; - DOEPCTL0 at 768 range 0 .. 31; - DOEPINT0 at 776 range 0 .. 31; - DOEPTSIZ0 at 784 range 0 .. 31; - DOEPCTL1 at 800 range 0 .. 31; - DOEPINT1 at 808 range 0 .. 31; - DOEPTSIZ1 at 816 range 0 .. 31; - DOEPCTL2 at 832 range 0 .. 31; - DOEPINT2 at 840 range 0 .. 31; - DOEPTSIZ2 at 848 range 0 .. 31; - DOEPCTL3 at 864 range 0 .. 31; - DOEPINT3 at 872 range 0 .. 31; - DOEPTSIZ3 at 880 range 0 .. 31; - end record; - - -- USB on the go full speed - OTG_FS_DEVICE_Periph : aliased OTG_FS_DEVICE_Peripheral - with Import, Address => OTG_FS_DEVICE_Base; - -- USB on the go full speed type OTG_FS_PWRCLK_Peripheral is record -- OTG_FS power and clock gating control register - FS_PCGCCTL : FS_PCGCCTL_Register; + FS_PCGCCTL : aliased FS_PCGCCTL_Register; + pragma Volatile_Full_Access (FS_PCGCCTL); end record with Volatile; diff --git a/stm32f4/stm32f40x/stm32f40x-usb_otg_hs.ads b/stm32f4/stm32f40x/stm32f40x-usb_otg_hs.ads index a369a7e..e44f037 100644 --- a/stm32f4/stm32f40x/stm32f40x-usb_otg_hs.ads +++ b/stm32f4/stm32f40x/stm32f40x-usb_otg_hs.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,2420 +14,2141 @@ package STM32F40x.USB_OTG_HS is -- Registers -- --------------- - ----------------------------- - -- OTG_HS_GOTGCTL_Register -- - ----------------------------- - - subtype OTG_HS_GOTGCTL_SRQSCS_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_SRQ_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_HNGSCS_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_HNPRQ_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_HSHNPEN_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_DHNPEN_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_CIDSTS_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_DBCT_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_ASVLD_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGCTL_BSVLD_Field is STM32F40x.Bit; + subtype OTG_HS_DCFG_DSPD_Field is STM32F40x.UInt2; + subtype OTG_HS_DCFG_NZLSOHSK_Field is STM32F40x.Bit; + subtype OTG_HS_DCFG_DAD_Field is STM32F40x.UInt7; + subtype OTG_HS_DCFG_PFIVL_Field is STM32F40x.UInt2; + subtype OTG_HS_DCFG_PERSCHIVL_Field is STM32F40x.UInt2; - -- OTG_HS control and status register - type OTG_HS_GOTGCTL_Register is record - -- Read-only. Session request success - SRQSCS : OTG_HS_GOTGCTL_SRQSCS_Field := 16#0#; - -- Session request - SRQ : OTG_HS_GOTGCTL_SRQ_Field := 16#0#; + -- OTG_HS device configuration register + type OTG_HS_DCFG_Register is record + -- Device speed + DSPD : OTG_HS_DCFG_DSPD_Field := 16#0#; + -- Nonzero-length status OUT handshake + NZLSOHSK : OTG_HS_DCFG_NZLSOHSK_Field := 16#0#; -- unspecified - Reserved_2_7 : STM32F40x.UInt6 := 16#0#; - -- Read-only. Host negotiation success - HNGSCS : OTG_HS_GOTGCTL_HNGSCS_Field := 16#0#; - -- HNP request - HNPRQ : OTG_HS_GOTGCTL_HNPRQ_Field := 16#0#; - -- Host set HNP enable - HSHNPEN : OTG_HS_GOTGCTL_HSHNPEN_Field := 16#0#; - -- Device HNP enabled - DHNPEN : OTG_HS_GOTGCTL_DHNPEN_Field := 16#1#; + Reserved_3_3 : STM32F40x.Bit := 16#0#; + -- Device address + DAD : OTG_HS_DCFG_DAD_Field := 16#0#; + -- Periodic (micro)frame interval + PFIVL : OTG_HS_DCFG_PFIVL_Field := 16#0#; -- unspecified - Reserved_12_15 : STM32F40x.UInt4 := 16#0#; - -- Read-only. Connector ID status - CIDSTS : OTG_HS_GOTGCTL_CIDSTS_Field := 16#0#; - -- Read-only. Long/short debounce time - DBCT : OTG_HS_GOTGCTL_DBCT_Field := 16#0#; - -- Read-only. A-session valid - ASVLD : OTG_HS_GOTGCTL_ASVLD_Field := 16#0#; - -- Read-only. B-session valid - BSVLD : OTG_HS_GOTGCTL_BSVLD_Field := 16#0#; + Reserved_13_23 : STM32F40x.UInt11 := 16#100#; + -- Periodic scheduling interval + PERSCHIVL : OTG_HS_DCFG_PERSCHIVL_Field := 16#2#; -- unspecified - Reserved_20_31 : STM32F40x.UInt12 := 16#0#; + Reserved_26_31 : STM32F40x.UInt6 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GOTGCTL_Register use record - SRQSCS at 0 range 0 .. 0; - SRQ at 0 range 1 .. 1; - Reserved_2_7 at 0 range 2 .. 7; - HNGSCS at 0 range 8 .. 8; - HNPRQ at 0 range 9 .. 9; - HSHNPEN at 0 range 10 .. 10; - DHNPEN at 0 range 11 .. 11; - Reserved_12_15 at 0 range 12 .. 15; - CIDSTS at 0 range 16 .. 16; - DBCT at 0 range 17 .. 17; - ASVLD at 0 range 18 .. 18; - BSVLD at 0 range 19 .. 19; - Reserved_20_31 at 0 range 20 .. 31; + for OTG_HS_DCFG_Register use record + DSPD at 0 range 0 .. 1; + NZLSOHSK at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DAD at 0 range 4 .. 10; + PFIVL at 0 range 11 .. 12; + Reserved_13_23 at 0 range 13 .. 23; + PERSCHIVL at 0 range 24 .. 25; + Reserved_26_31 at 0 range 26 .. 31; end record; - ----------------------------- - -- OTG_HS_GOTGINT_Register -- - ----------------------------- - - subtype OTG_HS_GOTGINT_SEDET_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGINT_SRSSCHG_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGINT_HNSSCHG_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGINT_HNGDET_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGINT_ADTOCHG_Field is STM32F40x.Bit; - subtype OTG_HS_GOTGINT_DBCDNE_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_RWUSIG_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_SDIS_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_GINSTS_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_GONSTS_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_TCTL_Field is STM32F40x.UInt3; + subtype OTG_HS_DCTL_SGINAK_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_CGINAK_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_SGONAK_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_CGONAK_Field is STM32F40x.Bit; + subtype OTG_HS_DCTL_POPRGDNE_Field is STM32F40x.Bit; - -- OTG_HS interrupt register - type OTG_HS_GOTGINT_Register is record - -- unspecified - Reserved_0_1 : STM32F40x.UInt2 := 16#0#; - -- Session end detected - SEDET : OTG_HS_GOTGINT_SEDET_Field := 16#0#; - -- unspecified - Reserved_3_7 : STM32F40x.UInt5 := 16#0#; - -- Session request success status change - SRSSCHG : OTG_HS_GOTGINT_SRSSCHG_Field := 16#0#; - -- Host negotiation success status change - HNSSCHG : OTG_HS_GOTGINT_HNSSCHG_Field := 16#0#; - -- unspecified - Reserved_10_16 : STM32F40x.UInt7 := 16#0#; - -- Host negotiation detected - HNGDET : OTG_HS_GOTGINT_HNGDET_Field := 16#0#; - -- A-device timeout change - ADTOCHG : OTG_HS_GOTGINT_ADTOCHG_Field := 16#0#; - -- Debounce done - DBCDNE : OTG_HS_GOTGINT_DBCDNE_Field := 16#0#; + -- OTG_HS device control register + type OTG_HS_DCTL_Register is record + -- Remote wakeup signaling + RWUSIG : OTG_HS_DCTL_RWUSIG_Field := 16#0#; + -- Soft disconnect + SDIS : OTG_HS_DCTL_SDIS_Field := 16#0#; + -- Read-only. Global IN NAK status + GINSTS : OTG_HS_DCTL_GINSTS_Field := 16#0#; + -- Read-only. Global OUT NAK status + GONSTS : OTG_HS_DCTL_GONSTS_Field := 16#0#; + -- Test control + TCTL : OTG_HS_DCTL_TCTL_Field := 16#0#; + -- Write-only. Set global IN NAK + SGINAK : OTG_HS_DCTL_SGINAK_Field := 16#0#; + -- Write-only. Clear global IN NAK + CGINAK : OTG_HS_DCTL_CGINAK_Field := 16#0#; + -- Write-only. Set global OUT NAK + SGONAK : OTG_HS_DCTL_SGONAK_Field := 16#0#; + -- Write-only. Clear global OUT NAK + CGONAK : OTG_HS_DCTL_CGONAK_Field := 16#0#; + -- Power-on programming done + POPRGDNE : OTG_HS_DCTL_POPRGDNE_Field := 16#0#; -- unspecified - Reserved_20_31 : STM32F40x.UInt12 := 16#0#; + Reserved_12_31 : STM32F40x.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GOTGINT_Register use record - Reserved_0_1 at 0 range 0 .. 1; - SEDET at 0 range 2 .. 2; - Reserved_3_7 at 0 range 3 .. 7; - SRSSCHG at 0 range 8 .. 8; - HNSSCHG at 0 range 9 .. 9; - Reserved_10_16 at 0 range 10 .. 16; - HNGDET at 0 range 17 .. 17; - ADTOCHG at 0 range 18 .. 18; - DBCDNE at 0 range 19 .. 19; - Reserved_20_31 at 0 range 20 .. 31; + for OTG_HS_DCTL_Register use record + RWUSIG at 0 range 0 .. 0; + SDIS at 0 range 1 .. 1; + GINSTS at 0 range 2 .. 2; + GONSTS at 0 range 3 .. 3; + TCTL at 0 range 4 .. 6; + SGINAK at 0 range 7 .. 7; + CGINAK at 0 range 8 .. 8; + SGONAK at 0 range 9 .. 9; + CGONAK at 0 range 10 .. 10; + POPRGDNE at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------------------- - -- OTG_HS_GAHBCFG_Register -- - ----------------------------- - - subtype OTG_HS_GAHBCFG_GINT_Field is STM32F40x.Bit; - subtype OTG_HS_GAHBCFG_HBSTLEN_Field is STM32F40x.UInt4; - subtype OTG_HS_GAHBCFG_DMAEN_Field is STM32F40x.Bit; - subtype OTG_HS_GAHBCFG_TXFELVL_Field is STM32F40x.Bit; - subtype OTG_HS_GAHBCFG_PTXFELVL_Field is STM32F40x.Bit; + subtype OTG_HS_DSTS_SUSPSTS_Field is STM32F40x.Bit; + subtype OTG_HS_DSTS_ENUMSPD_Field is STM32F40x.UInt2; + subtype OTG_HS_DSTS_EERR_Field is STM32F40x.Bit; + subtype OTG_HS_DSTS_FNSOF_Field is STM32F40x.UInt14; - -- OTG_HS AHB configuration register - type OTG_HS_GAHBCFG_Register is record - -- Global interrupt mask - GINT : OTG_HS_GAHBCFG_GINT_Field := 16#0#; - -- Burst length/type - HBSTLEN : OTG_HS_GAHBCFG_HBSTLEN_Field := 16#0#; - -- DMA enable - DMAEN : OTG_HS_GAHBCFG_DMAEN_Field := 16#0#; + -- OTG_HS device status register + type OTG_HS_DSTS_Register is record + -- Read-only. Suspend status + SUSPSTS : OTG_HS_DSTS_SUSPSTS_Field; + -- Read-only. Enumerated speed + ENUMSPD : OTG_HS_DSTS_ENUMSPD_Field; + -- Read-only. Erratic error + EERR : OTG_HS_DSTS_EERR_Field; -- unspecified - Reserved_6_6 : STM32F40x.Bit := 16#0#; - -- TxFIFO empty level - TXFELVL : OTG_HS_GAHBCFG_TXFELVL_Field := 16#0#; - -- Periodic TxFIFO empty level - PTXFELVL : OTG_HS_GAHBCFG_PTXFELVL_Field := 16#0#; + Reserved_4_7 : STM32F40x.UInt4; + -- Read-only. Frame number of the received SOF + FNSOF : OTG_HS_DSTS_FNSOF_Field; -- unspecified - Reserved_9_31 : STM32F40x.UInt23 := 16#0#; + Reserved_22_31 : STM32F40x.UInt10; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GAHBCFG_Register use record - GINT at 0 range 0 .. 0; - HBSTLEN at 0 range 1 .. 4; - DMAEN at 0 range 5 .. 5; - Reserved_6_6 at 0 range 6 .. 6; - TXFELVL at 0 range 7 .. 7; - PTXFELVL at 0 range 8 .. 8; - Reserved_9_31 at 0 range 9 .. 31; + for OTG_HS_DSTS_Register use record + SUSPSTS at 0 range 0 .. 0; + ENUMSPD at 0 range 1 .. 2; + EERR at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + FNSOF at 0 range 8 .. 21; + Reserved_22_31 at 0 range 22 .. 31; end record; - ----------------------------- - -- OTG_HS_GUSBCFG_Register -- - ----------------------------- - - subtype OTG_HS_GUSBCFG_TOCAL_Field is STM32F40x.UInt3; - subtype OTG_HS_GUSBCFG_PHYSEL_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_SRPCAP_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_HNPCAP_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_TRDT_Field is STM32F40x.UInt4; - subtype OTG_HS_GUSBCFG_PHYLPCS_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_ULPIFSLS_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_ULPIAR_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_ULPICSM_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_ULPIEVBUSD_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_ULPIEVBUSI_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_TSDPS_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_PCCI_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_PTCI_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_ULPIIPD_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_FHMOD_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_FDMOD_Field is STM32F40x.Bit; - subtype OTG_HS_GUSBCFG_CTXPKT_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPMSK_XFRCM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPMSK_EPDM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPMSK_TOM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPMSK_ITTXFEMSK_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPMSK_INEPNMM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPMSK_INEPNEM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPMSK_TXFURM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPMSK_BIM_Field is STM32F40x.Bit; - -- OTG_HS USB configuration register - type OTG_HS_GUSBCFG_Register is record - -- FS timeout calibration - TOCAL : OTG_HS_GUSBCFG_TOCAL_Field := 16#0#; - -- unspecified - Reserved_3_5 : STM32F40x.UInt3 := 16#0#; - -- Write-only. USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial - -- transceiver select - PHYSEL : OTG_HS_GUSBCFG_PHYSEL_Field := 16#0#; + -- OTG_HS device IN endpoint common interrupt mask register + type OTG_HS_DIEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : OTG_HS_DIEPMSK_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : OTG_HS_DIEPMSK_EPDM_Field := 16#0#; -- unspecified - Reserved_7_7 : STM32F40x.Bit := 16#0#; - -- SRP-capable - SRPCAP : OTG_HS_GUSBCFG_SRPCAP_Field := 16#0#; - -- HNP-capable - HNPCAP : OTG_HS_GUSBCFG_HNPCAP_Field := 16#1#; - -- USB turnaround time - TRDT : OTG_HS_GUSBCFG_TRDT_Field := 16#2#; - -- unspecified - Reserved_14_14 : STM32F40x.Bit := 16#0#; - -- PHY Low-power clock select - PHYLPCS : OTG_HS_GUSBCFG_PHYLPCS_Field := 16#0#; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- Timeout condition mask (nonisochronous endpoints) + TOM : OTG_HS_DIEPMSK_TOM_Field := 16#0#; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : OTG_HS_DIEPMSK_ITTXFEMSK_Field := 16#0#; + -- IN token received with EP mismatch mask + INEPNMM : OTG_HS_DIEPMSK_INEPNMM_Field := 16#0#; + -- IN endpoint NAK effective mask + INEPNEM : OTG_HS_DIEPMSK_INEPNEM_Field := 16#0#; -- unspecified - Reserved_16_16 : STM32F40x.Bit := 16#0#; - -- ULPI FS/LS select - ULPIFSLS : OTG_HS_GUSBCFG_ULPIFSLS_Field := 16#0#; - -- ULPI Auto-resume - ULPIAR : OTG_HS_GUSBCFG_ULPIAR_Field := 16#0#; - -- ULPI Clock SuspendM - ULPICSM : OTG_HS_GUSBCFG_ULPICSM_Field := 16#0#; - -- ULPI External VBUS Drive - ULPIEVBUSD : OTG_HS_GUSBCFG_ULPIEVBUSD_Field := 16#0#; - -- ULPI external VBUS indicator - ULPIEVBUSI : OTG_HS_GUSBCFG_ULPIEVBUSI_Field := 16#0#; - -- TermSel DLine pulsing selection - TSDPS : OTG_HS_GUSBCFG_TSDPS_Field := 16#0#; - -- Indicator complement - PCCI : OTG_HS_GUSBCFG_PCCI_Field := 16#0#; - -- Indicator pass through - PTCI : OTG_HS_GUSBCFG_PTCI_Field := 16#0#; - -- ULPI interface protect disable - ULPIIPD : OTG_HS_GUSBCFG_ULPIIPD_Field := 16#0#; + Reserved_7_7 : STM32F40x.Bit := 16#0#; + -- FIFO underrun mask + TXFURM : OTG_HS_DIEPMSK_TXFURM_Field := 16#0#; + -- BNA interrupt mask + BIM : OTG_HS_DIEPMSK_BIM_Field := 16#0#; -- unspecified - Reserved_26_28 : STM32F40x.UInt3 := 16#0#; - -- Forced host mode - FHMOD : OTG_HS_GUSBCFG_FHMOD_Field := 16#0#; - -- Forced peripheral mode - FDMOD : OTG_HS_GUSBCFG_FDMOD_Field := 16#0#; - -- Corrupt Tx packet - CTXPKT : OTG_HS_GUSBCFG_CTXPKT_Field := 16#0#; + Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GUSBCFG_Register use record - TOCAL at 0 range 0 .. 2; - Reserved_3_5 at 0 range 3 .. 5; - PHYSEL at 0 range 6 .. 6; + for OTG_HS_DIEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; Reserved_7_7 at 0 range 7 .. 7; - SRPCAP at 0 range 8 .. 8; - HNPCAP at 0 range 9 .. 9; - TRDT at 0 range 10 .. 13; - Reserved_14_14 at 0 range 14 .. 14; - PHYLPCS at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - ULPIFSLS at 0 range 17 .. 17; - ULPIAR at 0 range 18 .. 18; - ULPICSM at 0 range 19 .. 19; - ULPIEVBUSD at 0 range 20 .. 20; - ULPIEVBUSI at 0 range 21 .. 21; - TSDPS at 0 range 22 .. 22; - PCCI at 0 range 23 .. 23; - PTCI at 0 range 24 .. 24; - ULPIIPD at 0 range 25 .. 25; - Reserved_26_28 at 0 range 26 .. 28; - FHMOD at 0 range 29 .. 29; - FDMOD at 0 range 30 .. 30; - CTXPKT at 0 range 31 .. 31; + TXFURM at 0 range 8 .. 8; + BIM at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; end record; - ----------------------------- - -- OTG_HS_GRSTCTL_Register -- - ----------------------------- - - subtype OTG_HS_GRSTCTL_CSRST_Field is STM32F40x.Bit; - subtype OTG_HS_GRSTCTL_HSRST_Field is STM32F40x.Bit; - subtype OTG_HS_GRSTCTL_FCRST_Field is STM32F40x.Bit; - subtype OTG_HS_GRSTCTL_RXFFLSH_Field is STM32F40x.Bit; - subtype OTG_HS_GRSTCTL_TXFFLSH_Field is STM32F40x.Bit; - subtype OTG_HS_GRSTCTL_TXFNUM_Field is STM32F40x.UInt5; - subtype OTG_HS_GRSTCTL_DMAREQ_Field is STM32F40x.Bit; - subtype OTG_HS_GRSTCTL_AHBIDL_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPMSK_XFRCM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPMSK_EPDM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPMSK_STUPM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPMSK_OTEPDM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPMSK_B2BSTUP_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPMSK_OPEM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPMSK_BOIM_Field is STM32F40x.Bit; - -- OTG_HS reset register - type OTG_HS_GRSTCTL_Register is record - -- Core soft reset - CSRST : OTG_HS_GRSTCTL_CSRST_Field := 16#0#; - -- HCLK soft reset - HSRST : OTG_HS_GRSTCTL_HSRST_Field := 16#0#; - -- Host frame counter reset - FCRST : OTG_HS_GRSTCTL_FCRST_Field := 16#0#; + -- OTG_HS device OUT endpoint common interrupt mask register + type OTG_HS_DOEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : OTG_HS_DOEPMSK_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : OTG_HS_DOEPMSK_EPDM_Field := 16#0#; -- unspecified - Reserved_3_3 : STM32F40x.Bit := 16#0#; - -- RxFIFO flush - RXFFLSH : OTG_HS_GRSTCTL_RXFFLSH_Field := 16#0#; - -- TxFIFO flush - TXFFLSH : OTG_HS_GRSTCTL_TXFFLSH_Field := 16#0#; - -- TxFIFO number - TXFNUM : OTG_HS_GRSTCTL_TXFNUM_Field := 16#0#; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- SETUP phase done mask + STUPM : OTG_HS_DOEPMSK_STUPM_Field := 16#0#; + -- OUT token received when endpoint disabled mask + OTEPDM : OTG_HS_DOEPMSK_OTEPDM_Field := 16#0#; -- unspecified - Reserved_11_29 : STM32F40x.UInt19 := 16#40000#; - -- Read-only. DMA request signal - DMAREQ : OTG_HS_GRSTCTL_DMAREQ_Field := 16#0#; - -- Read-only. AHB master idle - AHBIDL : OTG_HS_GRSTCTL_AHBIDL_Field := 16#0#; + Reserved_5_5 : STM32F40x.Bit := 16#0#; + -- Back-to-back SETUP packets received mask + B2BSTUP : OTG_HS_DOEPMSK_B2BSTUP_Field := 16#0#; + -- unspecified + Reserved_7_7 : STM32F40x.Bit := 16#0#; + -- OUT packet error mask + OPEM : OTG_HS_DOEPMSK_OPEM_Field := 16#0#; + -- BNA interrupt mask + BOIM : OTG_HS_DOEPMSK_BOIM_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRSTCTL_Register use record - CSRST at 0 range 0 .. 0; - HSRST at 0 range 1 .. 1; - FCRST at 0 range 2 .. 2; - Reserved_3_3 at 0 range 3 .. 3; - RXFFLSH at 0 range 4 .. 4; - TXFFLSH at 0 range 5 .. 5; - TXFNUM at 0 range 6 .. 10; - Reserved_11_29 at 0 range 11 .. 29; - DMAREQ at 0 range 30 .. 30; - AHBIDL at 0 range 31 .. 31; + for OTG_HS_DOEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUPM at 0 range 3 .. 3; + OTEPDM at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + B2BSTUP at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + OPEM at 0 range 8 .. 8; + BOIM at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; end record; - ----------------------------- - -- OTG_HS_GINTSTS_Register -- - ----------------------------- + subtype OTG_HS_DAINT_IEPINT_Field is STM32F40x.UInt16; + subtype OTG_HS_DAINT_OEPINT_Field is STM32F40x.UInt16; - subtype OTG_HS_GINTSTS_CMOD_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_MMIS_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_OTGINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_SOF_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_RXFLVL_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_NPTXFE_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_GINAKEFF_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_BOUTNAKEFF_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_ESUSP_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_USBSUSP_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_USBRST_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_ENUMDNE_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_ISOODRP_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_EOPF_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_IEPINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_OEPINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_IISOIXFR_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_DATAFSUSP_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_HPRTINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_HCINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_PTXFE_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_CIDSCHG_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_DISCINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_SRQINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTSTS_WKUINT_Field is STM32F40x.Bit; + -- OTG_HS device all endpoints interrupt register + type OTG_HS_DAINT_Register is record + -- Read-only. IN endpoint interrupt bits + IEPINT : OTG_HS_DAINT_IEPINT_Field; + -- Read-only. OUT endpoint interrupt bits + OEPINT : OTG_HS_DAINT_OEPINT_Field; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG_HS core interrupt register - type OTG_HS_GINTSTS_Register is record - -- Read-only. Current mode of operation - CMOD : OTG_HS_GINTSTS_CMOD_Field := 16#0#; - -- Mode mismatch interrupt - MMIS : OTG_HS_GINTSTS_MMIS_Field := 16#0#; - -- Read-only. OTG interrupt - OTGINT : OTG_HS_GINTSTS_OTGINT_Field := 16#0#; - -- Start of frame - SOF : OTG_HS_GINTSTS_SOF_Field := 16#0#; - -- Read-only. RxFIFO nonempty - RXFLVL : OTG_HS_GINTSTS_RXFLVL_Field := 16#0#; - -- Read-only. Nonperiodic TxFIFO empty - NPTXFE : OTG_HS_GINTSTS_NPTXFE_Field := 16#1#; - -- Read-only. Global IN nonperiodic NAK effective - GINAKEFF : OTG_HS_GINTSTS_GINAKEFF_Field := 16#0#; - -- Read-only. Global OUT NAK effective - BOUTNAKEFF : OTG_HS_GINTSTS_BOUTNAKEFF_Field := 16#0#; - -- unspecified - Reserved_8_9 : STM32F40x.UInt2 := 16#0#; - -- Early suspend - ESUSP : OTG_HS_GINTSTS_ESUSP_Field := 16#0#; - -- USB suspend - USBSUSP : OTG_HS_GINTSTS_USBSUSP_Field := 16#0#; - -- USB reset - USBRST : OTG_HS_GINTSTS_USBRST_Field := 16#0#; - -- Enumeration done - ENUMDNE : OTG_HS_GINTSTS_ENUMDNE_Field := 16#0#; - -- Isochronous OUT packet dropped interrupt - ISOODRP : OTG_HS_GINTSTS_ISOODRP_Field := 16#0#; - -- End of periodic frame interrupt - EOPF : OTG_HS_GINTSTS_EOPF_Field := 16#0#; + for OTG_HS_DAINT_Register use record + IEPINT at 0 range 0 .. 15; + OEPINT at 0 range 16 .. 31; + end record; + + subtype OTG_HS_DAINTMSK_IEPM_Field is STM32F40x.UInt16; + subtype OTG_HS_DAINTMSK_OEPM_Field is STM32F40x.UInt16; + + -- OTG_HS all endpoints interrupt mask register + type OTG_HS_DAINTMSK_Register is record + -- IN EP interrupt mask bits + IEPM : OTG_HS_DAINTMSK_IEPM_Field := 16#0#; + -- OUT EP interrupt mask bits + OEPM : OTG_HS_DAINTMSK_OEPM_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for OTG_HS_DAINTMSK_Register use record + IEPM at 0 range 0 .. 15; + OEPM at 0 range 16 .. 31; + end record; + + subtype OTG_HS_DVBUSDIS_VBUSDT_Field is STM32F40x.UInt16; + + -- OTG_HS device VBUS discharge time register + type OTG_HS_DVBUSDIS_Register is record + -- Device VBUS discharge time + VBUSDT : OTG_HS_DVBUSDIS_VBUSDT_Field := 16#17D7#; -- unspecified - Reserved_16_17 : STM32F40x.UInt2 := 16#0#; - -- Read-only. IN endpoint interrupt - IEPINT : OTG_HS_GINTSTS_IEPINT_Field := 16#0#; - -- Read-only. OUT endpoint interrupt - OEPINT : OTG_HS_GINTSTS_OEPINT_Field := 16#0#; - -- Incomplete isochronous IN transfer - IISOIXFR : OTG_HS_GINTSTS_IISOIXFR_Field := 16#0#; - -- Incomplete periodic transfer - PXFR_INCOMPISOOUT : OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Field := 16#0#; - -- Data fetch suspended - DATAFSUSP : OTG_HS_GINTSTS_DATAFSUSP_Field := 16#0#; - -- unspecified - Reserved_23_23 : STM32F40x.Bit := 16#0#; - -- Read-only. Host port interrupt - HPRTINT : OTG_HS_GINTSTS_HPRTINT_Field := 16#0#; - -- Read-only. Host channels interrupt - HCINT : OTG_HS_GINTSTS_HCINT_Field := 16#0#; - -- Read-only. Periodic TxFIFO empty - PTXFE : OTG_HS_GINTSTS_PTXFE_Field := 16#1#; - -- unspecified - Reserved_27_27 : STM32F40x.Bit := 16#0#; - -- Connector ID status change - CIDSCHG : OTG_HS_GINTSTS_CIDSCHG_Field := 16#0#; - -- Disconnect detected interrupt - DISCINT : OTG_HS_GINTSTS_DISCINT_Field := 16#0#; - -- Session request/new session detected interrupt - SRQINT : OTG_HS_GINTSTS_SRQINT_Field := 16#0#; - -- Resume/remote wakeup detected interrupt - WKUINT : OTG_HS_GINTSTS_WKUINT_Field := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GINTSTS_Register use record - CMOD at 0 range 0 .. 0; - MMIS at 0 range 1 .. 1; - OTGINT at 0 range 2 .. 2; - SOF at 0 range 3 .. 3; - RXFLVL at 0 range 4 .. 4; - NPTXFE at 0 range 5 .. 5; - GINAKEFF at 0 range 6 .. 6; - BOUTNAKEFF at 0 range 7 .. 7; - Reserved_8_9 at 0 range 8 .. 9; - ESUSP at 0 range 10 .. 10; - USBSUSP at 0 range 11 .. 11; - USBRST at 0 range 12 .. 12; - ENUMDNE at 0 range 13 .. 13; - ISOODRP at 0 range 14 .. 14; - EOPF at 0 range 15 .. 15; - Reserved_16_17 at 0 range 16 .. 17; - IEPINT at 0 range 18 .. 18; - OEPINT at 0 range 19 .. 19; - IISOIXFR at 0 range 20 .. 20; - PXFR_INCOMPISOOUT at 0 range 21 .. 21; - DATAFSUSP at 0 range 22 .. 22; - Reserved_23_23 at 0 range 23 .. 23; - HPRTINT at 0 range 24 .. 24; - HCINT at 0 range 25 .. 25; - PTXFE at 0 range 26 .. 26; - Reserved_27_27 at 0 range 27 .. 27; - CIDSCHG at 0 range 28 .. 28; - DISCINT at 0 range 29 .. 29; - SRQINT at 0 range 30 .. 30; - WKUINT at 0 range 31 .. 31; + for OTG_HS_DVBUSDIS_Register use record + VBUSDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_GINTMSK_Register -- - ----------------------------- - - subtype OTG_HS_GINTMSK_MMISM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_OTGINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_SOFM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_RXFLVLM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_NPTXFEM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_GINAKEFFM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_GONAKEFFM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_ESUSPM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_USBSUSPM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_USBRST_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_ENUMDNEM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_ISOODRPM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_EOPFM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_EPMISM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_IEPINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_OEPINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_IISOIXFRM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_FSUSPM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_PRTIM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_HCIM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_PTXFEM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_CIDSCHGM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_DISCINT_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_SRQIM_Field is STM32F40x.Bit; - subtype OTG_HS_GINTMSK_WUIM_Field is STM32F40x.Bit; + subtype OTG_HS_DVBUSPULSE_DVBUSP_Field is STM32F40x.UInt12; - -- OTG_HS interrupt mask register - type OTG_HS_GINTMSK_Register is record - -- unspecified - Reserved_0_0 : STM32F40x.Bit := 16#0#; - -- Mode mismatch interrupt mask - MMISM : OTG_HS_GINTMSK_MMISM_Field := 16#0#; - -- OTG interrupt mask - OTGINT : OTG_HS_GINTMSK_OTGINT_Field := 16#0#; - -- Start of frame mask - SOFM : OTG_HS_GINTMSK_SOFM_Field := 16#0#; - -- Receive FIFO nonempty mask - RXFLVLM : OTG_HS_GINTMSK_RXFLVLM_Field := 16#0#; - -- Nonperiodic TxFIFO empty mask - NPTXFEM : OTG_HS_GINTMSK_NPTXFEM_Field := 16#0#; - -- Global nonperiodic IN NAK effective mask - GINAKEFFM : OTG_HS_GINTMSK_GINAKEFFM_Field := 16#0#; - -- Global OUT NAK effective mask - GONAKEFFM : OTG_HS_GINTMSK_GONAKEFFM_Field := 16#0#; + -- OTG_HS device VBUS pulsing time register + type OTG_HS_DVBUSPULSE_Register is record + -- Device VBUS pulsing time + DVBUSP : OTG_HS_DVBUSPULSE_DVBUSP_Field := 16#5B8#; -- unspecified - Reserved_8_9 : STM32F40x.UInt2 := 16#0#; - -- Early suspend mask - ESUSPM : OTG_HS_GINTMSK_ESUSPM_Field := 16#0#; - -- USB suspend mask - USBSUSPM : OTG_HS_GINTMSK_USBSUSPM_Field := 16#0#; - -- USB reset mask - USBRST : OTG_HS_GINTMSK_USBRST_Field := 16#0#; - -- Enumeration done mask - ENUMDNEM : OTG_HS_GINTMSK_ENUMDNEM_Field := 16#0#; - -- Isochronous OUT packet dropped interrupt mask - ISOODRPM : OTG_HS_GINTMSK_ISOODRPM_Field := 16#0#; - -- End of periodic frame interrupt mask - EOPFM : OTG_HS_GINTMSK_EOPFM_Field := 16#0#; + Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for OTG_HS_DVBUSPULSE_Register use record + DVBUSP at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype OTG_HS_DTHRCTL_NONISOTHREN_Field is STM32F40x.Bit; + subtype OTG_HS_DTHRCTL_ISOTHREN_Field is STM32F40x.Bit; + subtype OTG_HS_DTHRCTL_TXTHRLEN_Field is STM32F40x.UInt9; + subtype OTG_HS_DTHRCTL_RXTHREN_Field is STM32F40x.Bit; + subtype OTG_HS_DTHRCTL_RXTHRLEN_Field is STM32F40x.UInt9; + subtype OTG_HS_DTHRCTL_ARPEN_Field is STM32F40x.Bit; + + -- OTG_HS Device threshold control register + type OTG_HS_DTHRCTL_Register is record + -- Nonisochronous IN endpoints threshold enable + NONISOTHREN : OTG_HS_DTHRCTL_NONISOTHREN_Field := 16#0#; + -- ISO IN endpoint threshold enable + ISOTHREN : OTG_HS_DTHRCTL_ISOTHREN_Field := 16#0#; + -- Transmit threshold length + TXTHRLEN : OTG_HS_DTHRCTL_TXTHRLEN_Field := 16#0#; -- unspecified - Reserved_16_16 : STM32F40x.Bit := 16#0#; - -- Endpoint mismatch interrupt mask - EPMISM : OTG_HS_GINTMSK_EPMISM_Field := 16#0#; - -- IN endpoints interrupt mask - IEPINT : OTG_HS_GINTMSK_IEPINT_Field := 16#0#; - -- OUT endpoints interrupt mask - OEPINT : OTG_HS_GINTMSK_OEPINT_Field := 16#0#; - -- Incomplete isochronous IN transfer mask - IISOIXFRM : OTG_HS_GINTMSK_IISOIXFRM_Field := 16#0#; - -- Incomplete periodic transfer mask - PXFRM_IISOOXFRM : OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Field := 16#0#; - -- Data fetch suspended mask - FSUSPM : OTG_HS_GINTMSK_FSUSPM_Field := 16#0#; + Reserved_11_15 : STM32F40x.UInt5 := 16#0#; + -- Receive threshold enable + RXTHREN : OTG_HS_DTHRCTL_RXTHREN_Field := 16#0#; + -- Receive threshold length + RXTHRLEN : OTG_HS_DTHRCTL_RXTHRLEN_Field := 16#0#; -- unspecified - Reserved_23_23 : STM32F40x.Bit := 16#0#; - -- Read-only. Host port interrupt mask - PRTIM : OTG_HS_GINTMSK_PRTIM_Field := 16#0#; - -- Host channels interrupt mask - HCIM : OTG_HS_GINTMSK_HCIM_Field := 16#0#; - -- Periodic TxFIFO empty mask - PTXFEM : OTG_HS_GINTMSK_PTXFEM_Field := 16#0#; + Reserved_26_26 : STM32F40x.Bit := 16#0#; + -- Arbiter parking enable + ARPEN : OTG_HS_DTHRCTL_ARPEN_Field := 16#0#; -- unspecified - Reserved_27_27 : STM32F40x.Bit := 16#0#; - -- Connector ID status change mask - CIDSCHGM : OTG_HS_GINTMSK_CIDSCHGM_Field := 16#0#; - -- Disconnect detected interrupt mask - DISCINT : OTG_HS_GINTMSK_DISCINT_Field := 16#0#; - -- Session request/new session detected interrupt mask - SRQIM : OTG_HS_GINTMSK_SRQIM_Field := 16#0#; - -- Resume/remote wakeup detected interrupt mask - WUIM : OTG_HS_GINTMSK_WUIM_Field := 16#0#; + Reserved_28_31 : STM32F40x.UInt4 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GINTMSK_Register use record - Reserved_0_0 at 0 range 0 .. 0; - MMISM at 0 range 1 .. 1; - OTGINT at 0 range 2 .. 2; - SOFM at 0 range 3 .. 3; - RXFLVLM at 0 range 4 .. 4; - NPTXFEM at 0 range 5 .. 5; - GINAKEFFM at 0 range 6 .. 6; - GONAKEFFM at 0 range 7 .. 7; - Reserved_8_9 at 0 range 8 .. 9; - ESUSPM at 0 range 10 .. 10; - USBSUSPM at 0 range 11 .. 11; - USBRST at 0 range 12 .. 12; - ENUMDNEM at 0 range 13 .. 13; - ISOODRPM at 0 range 14 .. 14; - EOPFM at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - EPMISM at 0 range 17 .. 17; - IEPINT at 0 range 18 .. 18; - OEPINT at 0 range 19 .. 19; - IISOIXFRM at 0 range 20 .. 20; - PXFRM_IISOOXFRM at 0 range 21 .. 21; - FSUSPM at 0 range 22 .. 22; - Reserved_23_23 at 0 range 23 .. 23; - PRTIM at 0 range 24 .. 24; - HCIM at 0 range 25 .. 25; - PTXFEM at 0 range 26 .. 26; - Reserved_27_27 at 0 range 27 .. 27; - CIDSCHGM at 0 range 28 .. 28; - DISCINT at 0 range 29 .. 29; - SRQIM at 0 range 30 .. 30; - WUIM at 0 range 31 .. 31; + for OTG_HS_DTHRCTL_Register use record + NONISOTHREN at 0 range 0 .. 0; + ISOTHREN at 0 range 1 .. 1; + TXTHRLEN at 0 range 2 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + RXTHREN at 0 range 16 .. 16; + RXTHRLEN at 0 range 17 .. 25; + Reserved_26_26 at 0 range 26 .. 26; + ARPEN at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; end record; - ---------------------------------- - -- OTG_HS_GRXSTSR_Host_Register -- - ---------------------------------- - - subtype OTG_HS_GRXSTSR_Host_CHNUM_Field is STM32F40x.UInt4; - subtype OTG_HS_GRXSTSR_Host_BCNT_Field is STM32F40x.UInt11; - subtype OTG_HS_GRXSTSR_Host_DPID_Field is STM32F40x.UInt2; - subtype OTG_HS_GRXSTSR_Host_PKTSTS_Field is STM32F40x.UInt4; + subtype OTG_HS_DIEPEMPMSK_INEPTXFEM_Field is STM32F40x.UInt16; - -- OTG_HS Receive status debug read register (host mode) - type OTG_HS_GRXSTSR_Host_Register is record - -- Read-only. Channel number - CHNUM : OTG_HS_GRXSTSR_Host_CHNUM_Field := 16#0#; - -- Read-only. Byte count - BCNT : OTG_HS_GRXSTSR_Host_BCNT_Field := 16#0#; - -- Read-only. Data PID - DPID : OTG_HS_GRXSTSR_Host_DPID_Field := 16#0#; - -- Read-only. Packet status - PKTSTS : OTG_HS_GRXSTSR_Host_PKTSTS_Field := 16#0#; + -- OTG_HS device IN endpoint FIFO empty interrupt mask register + type OTG_HS_DIEPEMPMSK_Register is record + -- IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM : OTG_HS_DIEPEMPMSK_INEPTXFEM_Field := 16#0#; -- unspecified - Reserved_21_31 : STM32F40x.UInt11; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXSTSR_Host_Register use record - CHNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - Reserved_21_31 at 0 range 21 .. 31; + for OTG_HS_DIEPEMPMSK_Register use record + INEPTXFEM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------------------------- - -- OTG_HS_GRXSTSR_Peripheral_Register -- - ---------------------------------------- + subtype OTG_HS_DEACHINT_IEP1INT_Field is STM32F40x.Bit; + subtype OTG_HS_DEACHINT_OEP1INT_Field is STM32F40x.Bit; - subtype OTG_HS_GRXSTSR_Peripheral_EPNUM_Field is STM32F40x.UInt4; - subtype OTG_HS_GRXSTSR_Peripheral_BCNT_Field is STM32F40x.UInt11; - subtype OTG_HS_GRXSTSR_Peripheral_DPID_Field is STM32F40x.UInt2; - subtype OTG_HS_GRXSTSR_Peripheral_PKTSTS_Field is STM32F40x.UInt4; - subtype OTG_HS_GRXSTSR_Peripheral_FRMNUM_Field is STM32F40x.UInt4; - - -- OTG_HS Receive status debug read register (peripheral mode mode) - type OTG_HS_GRXSTSR_Peripheral_Register is record - -- Read-only. Endpoint number - EPNUM : OTG_HS_GRXSTSR_Peripheral_EPNUM_Field := 16#0#; - -- Read-only. Byte count - BCNT : OTG_HS_GRXSTSR_Peripheral_BCNT_Field := 16#0#; - -- Read-only. Data PID - DPID : OTG_HS_GRXSTSR_Peripheral_DPID_Field := 16#0#; - -- Read-only. Packet status - PKTSTS : OTG_HS_GRXSTSR_Peripheral_PKTSTS_Field := 16#0#; - -- Read-only. Frame number - FRMNUM : OTG_HS_GRXSTSR_Peripheral_FRMNUM_Field := 16#0#; + -- OTG_HS device each endpoint interrupt register + type OTG_HS_DEACHINT_Register is record -- unspecified - Reserved_25_31 : STM32F40x.UInt7; + Reserved_0_0 : STM32F40x.Bit := 16#0#; + -- IN endpoint 1interrupt bit + IEP1INT : OTG_HS_DEACHINT_IEP1INT_Field := 16#0#; + -- unspecified + Reserved_2_16 : STM32F40x.UInt15 := 16#0#; + -- OUT endpoint 1 interrupt bit + OEP1INT : OTG_HS_DEACHINT_OEP1INT_Field := 16#0#; + -- unspecified + Reserved_18_31 : STM32F40x.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXSTSR_Peripheral_Register use record - EPNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - FRMNUM at 0 range 21 .. 24; - Reserved_25_31 at 0 range 25 .. 31; + for OTG_HS_DEACHINT_Register use record + Reserved_0_0 at 0 range 0 .. 0; + IEP1INT at 0 range 1 .. 1; + Reserved_2_16 at 0 range 2 .. 16; + OEP1INT at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; end record; - ---------------------------------- - -- OTG_HS_GRXSTSP_Host_Register -- - ---------------------------------- - - subtype OTG_HS_GRXSTSP_Host_CHNUM_Field is STM32F40x.UInt4; - subtype OTG_HS_GRXSTSP_Host_BCNT_Field is STM32F40x.UInt11; - subtype OTG_HS_GRXSTSP_Host_DPID_Field is STM32F40x.UInt2; - subtype OTG_HS_GRXSTSP_Host_PKTSTS_Field is STM32F40x.UInt4; + subtype OTG_HS_DEACHINTMSK_IEP1INTM_Field is STM32F40x.Bit; + subtype OTG_HS_DEACHINTMSK_OEP1INTM_Field is STM32F40x.Bit; - -- OTG_HS status read and pop register (host mode) - type OTG_HS_GRXSTSP_Host_Register is record - -- Read-only. Channel number - CHNUM : OTG_HS_GRXSTSP_Host_CHNUM_Field := 16#0#; - -- Read-only. Byte count - BCNT : OTG_HS_GRXSTSP_Host_BCNT_Field := 16#0#; - -- Read-only. Data PID - DPID : OTG_HS_GRXSTSP_Host_DPID_Field := 16#0#; - -- Read-only. Packet status - PKTSTS : OTG_HS_GRXSTSP_Host_PKTSTS_Field := 16#0#; + -- OTG_HS device each endpoint interrupt register mask + type OTG_HS_DEACHINTMSK_Register is record -- unspecified - Reserved_21_31 : STM32F40x.UInt11; + Reserved_0_0 : STM32F40x.Bit := 16#0#; + -- IN Endpoint 1 interrupt mask bit + IEP1INTM : OTG_HS_DEACHINTMSK_IEP1INTM_Field := 16#0#; + -- unspecified + Reserved_2_16 : STM32F40x.UInt15 := 16#0#; + -- OUT Endpoint 1 interrupt mask bit + OEP1INTM : OTG_HS_DEACHINTMSK_OEP1INTM_Field := 16#0#; + -- unspecified + Reserved_18_31 : STM32F40x.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXSTSP_Host_Register use record - CHNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - Reserved_21_31 at 0 range 21 .. 31; + for OTG_HS_DEACHINTMSK_Register use record + Reserved_0_0 at 0 range 0 .. 0; + IEP1INTM at 0 range 1 .. 1; + Reserved_2_16 at 0 range 2 .. 16; + OEP1INTM at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; end record; - ---------------------------------------- - -- OTG_HS_GRXSTSP_Peripheral_Register -- - ---------------------------------------- - - subtype OTG_HS_GRXSTSP_Peripheral_EPNUM_Field is STM32F40x.UInt4; - subtype OTG_HS_GRXSTSP_Peripheral_BCNT_Field is STM32F40x.UInt11; - subtype OTG_HS_GRXSTSP_Peripheral_DPID_Field is STM32F40x.UInt2; - subtype OTG_HS_GRXSTSP_Peripheral_PKTSTS_Field is STM32F40x.UInt4; - subtype OTG_HS_GRXSTSP_Peripheral_FRMNUM_Field is STM32F40x.UInt4; + subtype OTG_HS_DIEPEACHMSK1_XFRCM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPEACHMSK1_EPDM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPEACHMSK1_TOM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPEACHMSK1_INEPNMM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPEACHMSK1_INEPNEM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPEACHMSK1_TXFURM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPEACHMSK1_BIM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPEACHMSK1_NAKM_Field is STM32F40x.Bit; - -- OTG_HS status read and pop register (peripheral mode) - type OTG_HS_GRXSTSP_Peripheral_Register is record - -- Read-only. Endpoint number - EPNUM : OTG_HS_GRXSTSP_Peripheral_EPNUM_Field := 16#0#; - -- Read-only. Byte count - BCNT : OTG_HS_GRXSTSP_Peripheral_BCNT_Field := 16#0#; - -- Read-only. Data PID - DPID : OTG_HS_GRXSTSP_Peripheral_DPID_Field := 16#0#; - -- Read-only. Packet status - PKTSTS : OTG_HS_GRXSTSP_Peripheral_PKTSTS_Field := 16#0#; - -- Read-only. Frame number - FRMNUM : OTG_HS_GRXSTSP_Peripheral_FRMNUM_Field := 16#0#; + -- OTG_HS device each in endpoint-1 interrupt register + type OTG_HS_DIEPEACHMSK1_Register is record + -- Transfer completed interrupt mask + XFRCM : OTG_HS_DIEPEACHMSK1_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : OTG_HS_DIEPEACHMSK1_EPDM_Field := 16#0#; -- unspecified - Reserved_25_31 : STM32F40x.UInt7; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- Timeout condition mask (nonisochronous endpoints) + TOM : OTG_HS_DIEPEACHMSK1_TOM_Field := 16#0#; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Field := 16#0#; + -- IN token received with EP mismatch mask + INEPNMM : OTG_HS_DIEPEACHMSK1_INEPNMM_Field := 16#0#; + -- IN endpoint NAK effective mask + INEPNEM : OTG_HS_DIEPEACHMSK1_INEPNEM_Field := 16#0#; + -- unspecified + Reserved_7_7 : STM32F40x.Bit := 16#0#; + -- FIFO underrun mask + TXFURM : OTG_HS_DIEPEACHMSK1_TXFURM_Field := 16#0#; + -- BNA interrupt mask + BIM : OTG_HS_DIEPEACHMSK1_BIM_Field := 16#0#; + -- unspecified + Reserved_10_12 : STM32F40x.UInt3 := 16#0#; + -- NAK interrupt mask + NAKM : OTG_HS_DIEPEACHMSK1_NAKM_Field := 16#0#; + -- unspecified + Reserved_14_31 : STM32F40x.UInt18 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXSTSP_Peripheral_Register use record - EPNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - FRMNUM at 0 range 21 .. 24; - Reserved_25_31 at 0 range 25 .. 31; + for OTG_HS_DIEPEACHMSK1_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + TXFURM at 0 range 8 .. 8; + BIM at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + NAKM at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; end record; - ----------------------------- - -- OTG_HS_GRXFSIZ_Register -- - ----------------------------- - - subtype OTG_HS_GRXFSIZ_RXFD_Field is STM32F40x.Short; + subtype OTG_HS_DOEPEACHMSK1_XFRCM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_EPDM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_TOM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_ITTXFEMSK_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_INEPNMM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_INEPNEM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_TXFURM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_BIM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_BERRM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_NAKM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPEACHMSK1_NYETM_Field is STM32F40x.Bit; - -- OTG_HS Receive FIFO size register - type OTG_HS_GRXFSIZ_Register is record - -- RxFIFO depth - RXFD : OTG_HS_GRXFSIZ_RXFD_Field := 16#200#; + -- OTG_HS device each OUT endpoint-1 interrupt register + type OTG_HS_DOEPEACHMSK1_Register is record + -- Transfer completed interrupt mask + XFRCM : OTG_HS_DOEPEACHMSK1_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : OTG_HS_DOEPEACHMSK1_EPDM_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- Timeout condition mask + TOM : OTG_HS_DOEPEACHMSK1_TOM_Field := 16#0#; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : OTG_HS_DOEPEACHMSK1_ITTXFEMSK_Field := 16#0#; + -- IN token received with EP mismatch mask + INEPNMM : OTG_HS_DOEPEACHMSK1_INEPNMM_Field := 16#0#; + -- IN endpoint NAK effective mask + INEPNEM : OTG_HS_DOEPEACHMSK1_INEPNEM_Field := 16#0#; + -- unspecified + Reserved_7_7 : STM32F40x.Bit := 16#0#; + -- OUT packet error mask + TXFURM : OTG_HS_DOEPEACHMSK1_TXFURM_Field := 16#0#; + -- BNA interrupt mask + BIM : OTG_HS_DOEPEACHMSK1_BIM_Field := 16#0#; + -- unspecified + Reserved_10_11 : STM32F40x.UInt2 := 16#0#; + -- Bubble error interrupt mask + BERRM : OTG_HS_DOEPEACHMSK1_BERRM_Field := 16#0#; + -- NAK interrupt mask + NAKM : OTG_HS_DOEPEACHMSK1_NAKM_Field := 16#0#; + -- NYET interrupt mask + NYETM : OTG_HS_DOEPEACHMSK1_NYETM_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXFSIZ_Register use record - RXFD at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_DOEPEACHMSK1_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + TXFURM at 0 range 8 .. 8; + BIM at 0 range 9 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + BERRM at 0 range 12 .. 12; + NAKM at 0 range 13 .. 13; + NYETM at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------------------------ - -- OTG_HS_GNPTXFSIZ_Host_Register -- - ------------------------------------ - - subtype OTG_HS_GNPTXFSIZ_Host_NPTXFSA_Field is STM32F40x.Short; - subtype OTG_HS_GNPTXFSIZ_Host_NPTXFD_Field is STM32F40x.Short; + subtype OTG_HS_DIEPCTL_MPSIZ_Field is STM32F40x.UInt11; + subtype OTG_HS_DIEPCTL_USBAEP_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_EONUM_DPID_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_NAKSTS_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_EPTYP_Field is STM32F40x.UInt2; + subtype OTG_HS_DIEPCTL_Stall_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_TXFNUM_Field is STM32F40x.UInt4; + subtype OTG_HS_DIEPCTL_CNAK_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_SNAK_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_SD0PID_SEVNFRM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_SODDFRM_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_EPDIS_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPCTL_EPENA_Field is STM32F40x.Bit; - -- OTG_HS nonperiodic transmit FIFO size register (host mode) - type OTG_HS_GNPTXFSIZ_Host_Register is record - -- Nonperiodic transmit RAM start address - NPTXFSA : OTG_HS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; - -- Nonperiodic TxFIFO depth - NPTXFD : OTG_HS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; + -- OTG device endpoint-0 control register + type OTG_HS_DIEPCTL_Register is record + -- Maximum packet size + MPSIZ : OTG_HS_DIEPCTL_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : STM32F40x.UInt4 := 16#0#; + -- USB active endpoint + USBAEP : OTG_HS_DIEPCTL_USBAEP_Field := 16#0#; + -- Read-only. Even/odd frame + EONUM_DPID : OTG_HS_DIEPCTL_EONUM_DPID_Field := 16#0#; + -- Read-only. NAK status + NAKSTS : OTG_HS_DIEPCTL_NAKSTS_Field := 16#0#; + -- Endpoint type + EPTYP : OTG_HS_DIEPCTL_EPTYP_Field := 16#0#; + -- unspecified + Reserved_20_20 : STM32F40x.Bit := 16#0#; + -- STALL handshake + Stall : OTG_HS_DIEPCTL_Stall_Field := 16#0#; + -- TxFIFO number + TXFNUM : OTG_HS_DIEPCTL_TXFNUM_Field := 16#0#; + -- Write-only. Clear NAK + CNAK : OTG_HS_DIEPCTL_CNAK_Field := 16#0#; + -- Write-only. Set NAK + SNAK : OTG_HS_DIEPCTL_SNAK_Field := 16#0#; + -- Write-only. Set DATA0 PID + SD0PID_SEVNFRM : OTG_HS_DIEPCTL_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. Set odd frame + SODDFRM : OTG_HS_DIEPCTL_SODDFRM_Field := 16#0#; + -- Endpoint disable + EPDIS : OTG_HS_DIEPCTL_EPDIS_Field := 16#0#; + -- Endpoint enable + EPENA : OTG_HS_DIEPCTL_EPENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GNPTXFSIZ_Host_Register use record - NPTXFSA at 0 range 0 .. 15; - NPTXFD at 0 range 16 .. 31; + for OTG_HS_DIEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - ---------------------------------------- - -- OTG_HS_TX0FSIZ_Peripheral_Register -- - ---------------------------------------- + subtype OTG_HS_DIEPINT_XFRC_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_EPDISD_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_TOC_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_ITTXFE_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_INEPNE_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_TXFE_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_TXFIFOUDRN_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_BNA_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_PKTDRPSTS_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_BERR_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPINT_NAK_Field is STM32F40x.Bit; - subtype OTG_HS_TX0FSIZ_Peripheral_TX0FSA_Field is STM32F40x.Short; - subtype OTG_HS_TX0FSIZ_Peripheral_TX0FD_Field is STM32F40x.Short; - - -- Endpoint 0 transmit FIFO size (peripheral mode) - type OTG_HS_TX0FSIZ_Peripheral_Register is record - -- Endpoint 0 transmit RAM start address - TX0FSA : OTG_HS_TX0FSIZ_Peripheral_TX0FSA_Field := 16#200#; - -- Endpoint 0 TxFIFO depth - TX0FD : OTG_HS_TX0FSIZ_Peripheral_TX0FD_Field := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for OTG_HS_TX0FSIZ_Peripheral_Register use record - TX0FSA at 0 range 0 .. 15; - TX0FD at 0 range 16 .. 31; - end record; - - ------------------------------ - -- OTG_HS_GNPTXSTS_Register -- - ------------------------------ - - subtype OTG_HS_GNPTXSTS_NPTXFSAV_Field is STM32F40x.Short; - subtype OTG_HS_GNPTXSTS_NPTQXSAV_Field is STM32F40x.Byte; - subtype OTG_HS_GNPTXSTS_NPTXQTOP_Field is STM32F40x.UInt7; - - -- OTG_HS nonperiodic transmit FIFO/queue status register - type OTG_HS_GNPTXSTS_Register is record - -- Read-only. Nonperiodic TxFIFO space available - NPTXFSAV : OTG_HS_GNPTXSTS_NPTXFSAV_Field := 16#200#; - -- Read-only. Nonperiodic transmit request queue space available - NPTQXSAV : OTG_HS_GNPTXSTS_NPTQXSAV_Field := 16#8#; - -- Read-only. Top of the nonperiodic transmit request queue - NPTXQTOP : OTG_HS_GNPTXSTS_NPTXQTOP_Field := 16#0#; + -- OTG device endpoint-0 interrupt register + type OTG_HS_DIEPINT_Register is record + -- Transfer completed interrupt + XFRC : OTG_HS_DIEPINT_XFRC_Field := 16#0#; + -- Endpoint disabled interrupt + EPDISD : OTG_HS_DIEPINT_EPDISD_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F40x.Bit; + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- Timeout condition + TOC : OTG_HS_DIEPINT_TOC_Field := 16#0#; + -- IN token received when TxFIFO is empty + ITTXFE : OTG_HS_DIEPINT_ITTXFE_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F40x.Bit := 16#0#; + -- IN endpoint NAK effective + INEPNE : OTG_HS_DIEPINT_INEPNE_Field := 16#0#; + -- Read-only. Transmit FIFO empty + TXFE : OTG_HS_DIEPINT_TXFE_Field := 16#1#; + -- Transmit Fifo Underrun + TXFIFOUDRN : OTG_HS_DIEPINT_TXFIFOUDRN_Field := 16#0#; + -- Buffer not available interrupt + BNA : OTG_HS_DIEPINT_BNA_Field := 16#0#; + -- unspecified + Reserved_10_10 : STM32F40x.Bit := 16#0#; + -- Packet dropped status + PKTDRPSTS : OTG_HS_DIEPINT_PKTDRPSTS_Field := 16#0#; + -- Babble error interrupt + BERR : OTG_HS_DIEPINT_BERR_Field := 16#0#; + -- NAK interrupt + NAK : OTG_HS_DIEPINT_NAK_Field := 16#0#; + -- unspecified + Reserved_14_31 : STM32F40x.UInt18 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GNPTXSTS_Register use record - NPTXFSAV at 0 range 0 .. 15; - NPTQXSAV at 0 range 16 .. 23; - NPTXQTOP at 0 range 24 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for OTG_HS_DIEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOC at 0 range 3 .. 3; + ITTXFE at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + INEPNE at 0 range 6 .. 6; + TXFE at 0 range 7 .. 7; + TXFIFOUDRN at 0 range 8 .. 8; + BNA at 0 range 9 .. 9; + Reserved_10_10 at 0 range 10 .. 10; + PKTDRPSTS at 0 range 11 .. 11; + BERR at 0 range 12 .. 12; + NAK at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; end record; - --------------------------- - -- OTG_HS_GCCFG_Register -- - --------------------------- - - subtype OTG_HS_GCCFG_PWRDWN_Field is STM32F40x.Bit; - subtype OTG_HS_GCCFG_I2CPADEN_Field is STM32F40x.Bit; - subtype OTG_HS_GCCFG_VBUSASEN_Field is STM32F40x.Bit; - subtype OTG_HS_GCCFG_VBUSBSEN_Field is STM32F40x.Bit; - subtype OTG_HS_GCCFG_SOFOUTEN_Field is STM32F40x.Bit; - subtype OTG_HS_GCCFG_NOVBUSSENS_Field is STM32F40x.Bit; + subtype OTG_HS_DIEPTSIZ0_XFRSIZ_Field is STM32F40x.UInt7; + subtype OTG_HS_DIEPTSIZ0_PKTCNT_Field is STM32F40x.UInt2; - -- OTG_HS general core configuration register - type OTG_HS_GCCFG_Register is record + -- OTG_HS device IN endpoint 0 transfer size register + type OTG_HS_DIEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : OTG_HS_DIEPTSIZ0_XFRSIZ_Field := 16#0#; -- unspecified - Reserved_0_15 : STM32F40x.Short := 16#0#; - -- Power down - PWRDWN : OTG_HS_GCCFG_PWRDWN_Field := 16#0#; - -- Enable I2C bus connection for the external I2C PHY interface - I2CPADEN : OTG_HS_GCCFG_I2CPADEN_Field := 16#0#; - -- Enable the VBUS sensing device - VBUSASEN : OTG_HS_GCCFG_VBUSASEN_Field := 16#0#; - -- Enable the VBUS sensing device - VBUSBSEN : OTG_HS_GCCFG_VBUSBSEN_Field := 16#0#; - -- SOF output enable - SOFOUTEN : OTG_HS_GCCFG_SOFOUTEN_Field := 16#0#; - -- VBUS sensing disable option - NOVBUSSENS : OTG_HS_GCCFG_NOVBUSSENS_Field := 16#0#; + Reserved_7_18 : STM32F40x.UInt12 := 16#0#; + -- Packet count + PKTCNT : OTG_HS_DIEPTSIZ0_PKTCNT_Field := 16#0#; -- unspecified - Reserved_22_31 : STM32F40x.UInt10 := 16#0#; + Reserved_21_31 : STM32F40x.UInt11 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GCCFG_Register use record - Reserved_0_15 at 0 range 0 .. 15; - PWRDWN at 0 range 16 .. 16; - I2CPADEN at 0 range 17 .. 17; - VBUSASEN at 0 range 18 .. 18; - VBUSBSEN at 0 range 19 .. 19; - SOFOUTEN at 0 range 20 .. 20; - NOVBUSSENS at 0 range 21 .. 21; - Reserved_22_31 at 0 range 22 .. 31; + for OTG_HS_DIEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------------------ - -- OTG_HS_HPTXFSIZ_Register -- - ------------------------------ - - subtype OTG_HS_HPTXFSIZ_PTXSA_Field is STM32F40x.Short; - subtype OTG_HS_HPTXFSIZ_PTXFD_Field is STM32F40x.Short; + subtype OTG_HS_DTXFSTS_INEPTFSAV_Field is STM32F40x.UInt16; - -- OTG_HS Host periodic transmit FIFO size register - type OTG_HS_HPTXFSIZ_Register is record - -- Host periodic TxFIFO start address - PTXSA : OTG_HS_HPTXFSIZ_PTXSA_Field := 16#600#; - -- Host periodic TxFIFO depth - PTXFD : OTG_HS_HPTXFSIZ_PTXFD_Field := 16#200#; + -- OTG_HS device IN endpoint transmit FIFO status register + type OTG_HS_DTXFSTS_Register is record + -- Read-only. IN endpoint TxFIFO space avail + INEPTFSAV : OTG_HS_DTXFSTS_INEPTFSAV_Field; + -- unspecified + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HPTXFSIZ_Register use record - PTXSA at 0 range 0 .. 15; - PTXFD at 0 range 16 .. 31; + for OTG_HS_DTXFSTS_Register use record + INEPTFSAV at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_DIEPTXF_Register -- - ----------------------------- + subtype OTG_HS_DIEPTSIZ_XFRSIZ_Field is STM32F40x.UInt19; + subtype OTG_HS_DIEPTSIZ_PKTCNT_Field is STM32F40x.UInt10; + subtype OTG_HS_DIEPTSIZ_MCNT_Field is STM32F40x.UInt2; - subtype OTG_HS_DIEPTXF1_INEPTXSA_Field is STM32F40x.Short; - subtype OTG_HS_DIEPTXF1_INEPTXFD_Field is STM32F40x.Short; - - -- OTG_HS device IN endpoint transmit FIFO size register - type OTG_HS_DIEPTXF_Register is record - -- IN endpoint FIFOx transmit RAM start address - INEPTXSA : OTG_HS_DIEPTXF1_INEPTXSA_Field := 16#400#; - -- IN endpoint TxFIFO depth - INEPTXFD : OTG_HS_DIEPTXF1_INEPTXFD_Field := 16#200#; + -- OTG_HS device endpoint transfer size register + type OTG_HS_DIEPTSIZ_Register is record + -- Transfer size + XFRSIZ : OTG_HS_DIEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : OTG_HS_DIEPTSIZ_PKTCNT_Field := 16#0#; + -- Multi count + MCNT : OTG_HS_DIEPTSIZ_MCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPTXF_Register use record - INEPTXSA at 0 range 0 .. 15; - INEPTXFD at 0 range 16 .. 31; + for OTG_HS_DIEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + MCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - -------------------------- - -- OTG_HS_HCFG_Register -- - -------------------------- - - subtype OTG_HS_HCFG_FSLSPCS_Field is STM32F40x.UInt2; - subtype OTG_HS_HCFG_FSLSS_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL0_MPSIZ_Field is STM32F40x.UInt2; + subtype OTG_HS_DOEPCTL0_USBAEP_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL0_NAKSTS_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL0_EPTYP_Field is STM32F40x.UInt2; + subtype OTG_HS_DOEPCTL0_SNPM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL0_Stall_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL0_CNAK_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL0_SNAK_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL0_EPDIS_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL0_EPENA_Field is STM32F40x.Bit; - -- OTG_HS host configuration register - type OTG_HS_HCFG_Register is record - -- FS/LS PHY clock select - FSLSPCS : OTG_HS_HCFG_FSLSPCS_Field := 16#0#; - -- Read-only. FS- and LS-only support - FSLSS : OTG_HS_HCFG_FSLSS_Field := 16#0#; + -- OTG_HS device control OUT endpoint 0 control register + type OTG_HS_DOEPCTL0_Register is record + -- Read-only. Maximum packet size + MPSIZ : OTG_HS_DOEPCTL0_MPSIZ_Field := 16#0#; -- unspecified - Reserved_3_31 : STM32F40x.UInt29 := 16#0#; + Reserved_2_14 : STM32F40x.UInt13 := 16#0#; + -- Read-only. USB active endpoint + USBAEP : OTG_HS_DOEPCTL0_USBAEP_Field := 16#1#; + -- unspecified + Reserved_16_16 : STM32F40x.Bit := 16#0#; + -- Read-only. NAK status + NAKSTS : OTG_HS_DOEPCTL0_NAKSTS_Field := 16#0#; + -- Read-only. Endpoint type + EPTYP : OTG_HS_DOEPCTL0_EPTYP_Field := 16#0#; + -- Snoop mode + SNPM : OTG_HS_DOEPCTL0_SNPM_Field := 16#0#; + -- STALL handshake + Stall : OTG_HS_DOEPCTL0_Stall_Field := 16#0#; + -- unspecified + Reserved_22_25 : STM32F40x.UInt4 := 16#0#; + -- Write-only. Clear NAK + CNAK : OTG_HS_DOEPCTL0_CNAK_Field := 16#0#; + -- Write-only. Set NAK + SNAK : OTG_HS_DOEPCTL0_SNAK_Field := 16#0#; + -- unspecified + Reserved_28_29 : STM32F40x.UInt2 := 16#0#; + -- Read-only. Endpoint disable + EPDIS : OTG_HS_DOEPCTL0_EPDIS_Field := 16#0#; + -- Write-only. Endpoint enable + EPENA : OTG_HS_DOEPCTL0_EPENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HCFG_Register use record - FSLSPCS at 0 range 0 .. 1; - FSLSS at 0 range 2 .. 2; - Reserved_3_31 at 0 range 3 .. 31; + for OTG_HS_DOEPCTL0_Register use record + MPSIZ at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + USBAEP at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - -------------------------- - -- OTG_HS_HFIR_Register -- - -------------------------- + subtype OTG_HS_DOEPINT_XFRC_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPINT_EPDISD_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPINT_STUP_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPINT_OTEPDIS_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPINT_B2BSTUP_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPINT_NYET_Field is STM32F40x.Bit; - subtype OTG_HS_HFIR_FRIVL_Field is STM32F40x.Short; - - -- OTG_HS Host frame interval register - type OTG_HS_HFIR_Register is record - -- Frame interval - FRIVL : OTG_HS_HFIR_FRIVL_Field := 16#EA60#; + -- OTG_HS device endpoint-0 interrupt register + type OTG_HS_DOEPINT_Register is record + -- Transfer completed interrupt + XFRC : OTG_HS_DOEPINT_XFRC_Field := 16#0#; + -- Endpoint disabled interrupt + EPDISD : OTG_HS_DOEPINT_EPDISD_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F40x.Bit := 16#0#; + -- SETUP phase done + STUP : OTG_HS_DOEPINT_STUP_Field := 16#0#; + -- OUT token received when endpoint disabled + OTEPDIS : OTG_HS_DOEPINT_OTEPDIS_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F40x.Bit := 16#0#; + -- Back-to-back SETUP packets received + B2BSTUP : OTG_HS_DOEPINT_B2BSTUP_Field := 16#0#; + -- unspecified + Reserved_7_13 : STM32F40x.UInt7 := 16#1#; + -- NYET interrupt + NYET : OTG_HS_DOEPINT_NYET_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_15_31 : STM32F40x.UInt17 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HFIR_Register use record - FRIVL at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_DOEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUP at 0 range 3 .. 3; + OTEPDIS at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + B2BSTUP at 0 range 6 .. 6; + Reserved_7_13 at 0 range 7 .. 13; + NYET at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; end record; - --------------------------- - -- OTG_HS_HFNUM_Register -- - --------------------------- - - subtype OTG_HS_HFNUM_FRNUM_Field is STM32F40x.Short; - subtype OTG_HS_HFNUM_FTREM_Field is STM32F40x.Short; + subtype OTG_HS_DOEPTSIZ0_XFRSIZ_Field is STM32F40x.UInt7; + subtype OTG_HS_DOEPTSIZ0_PKTCNT_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPTSIZ0_STUPCNT_Field is STM32F40x.UInt2; - -- OTG_HS host frame number/frame time remaining register - type OTG_HS_HFNUM_Register is record - -- Read-only. Frame number - FRNUM : OTG_HS_HFNUM_FRNUM_Field := 16#3FFF#; - -- Read-only. Frame time remaining - FTREM : OTG_HS_HFNUM_FTREM_Field := 16#0#; + -- OTG_HS device endpoint-1 transfer size register + type OTG_HS_DOEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : OTG_HS_DOEPTSIZ0_XFRSIZ_Field := 16#0#; + -- unspecified + Reserved_7_18 : STM32F40x.UInt12 := 16#0#; + -- Packet count + PKTCNT : OTG_HS_DOEPTSIZ0_PKTCNT_Field := 16#0#; + -- unspecified + Reserved_20_28 : STM32F40x.UInt9 := 16#0#; + -- SETUP packet count + STUPCNT : OTG_HS_DOEPTSIZ0_STUPCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HFNUM_Register use record - FRNUM at 0 range 0 .. 15; - FTREM at 0 range 16 .. 31; + for OTG_HS_DOEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 19; + Reserved_20_28 at 0 range 20 .. 28; + STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - ----------------------------- - -- OTG_HS_HPTXSTS_Register -- - ----------------------------- + subtype OTG_HS_DOEPCTL_MPSIZ_Field is STM32F40x.UInt11; + subtype OTG_HS_DOEPCTL_USBAEP_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_EONUM_DPID_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_NAKSTS_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_EPTYP_Field is STM32F40x.UInt2; + subtype OTG_HS_DOEPCTL_SNPM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_Stall_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_CNAK_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_SNAK_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_SD0PID_SEVNFRM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_SODDFRM_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_EPDIS_Field is STM32F40x.Bit; + subtype OTG_HS_DOEPCTL_EPENA_Field is STM32F40x.Bit; - subtype OTG_HS_HPTXSTS_PTXFSAVL_Field is STM32F40x.Short; - subtype OTG_HS_HPTXSTS_PTXQSAV_Field is STM32F40x.Byte; - subtype OTG_HS_HPTXSTS_PTXQTOP_Field is STM32F40x.Byte; - - -- OTG_HS_Host periodic transmit FIFO/queue status register - type OTG_HS_HPTXSTS_Register is record - -- Periodic transmit data FIFO space available - PTXFSAVL : OTG_HS_HPTXSTS_PTXFSAVL_Field := 16#100#; - -- Read-only. Periodic transmit request queue space available - PTXQSAV : OTG_HS_HPTXSTS_PTXQSAV_Field := 16#8#; - -- Read-only. Top of the periodic transmit request queue - PTXQTOP : OTG_HS_HPTXSTS_PTXQTOP_Field := 16#0#; + -- OTG device endpoint-1 control register + type OTG_HS_DOEPCTL_Register is record + -- Maximum packet size + MPSIZ : OTG_HS_DOEPCTL_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : STM32F40x.UInt4 := 16#0#; + -- USB active endpoint + USBAEP : OTG_HS_DOEPCTL_USBAEP_Field := 16#0#; + -- Read-only. Even odd frame/Endpoint data PID + EONUM_DPID : OTG_HS_DOEPCTL_EONUM_DPID_Field := 16#0#; + -- Read-only. NAK status + NAKSTS : OTG_HS_DOEPCTL_NAKSTS_Field := 16#0#; + -- Endpoint type + EPTYP : OTG_HS_DOEPCTL_EPTYP_Field := 16#0#; + -- Snoop mode + SNPM : OTG_HS_DOEPCTL_SNPM_Field := 16#0#; + -- STALL handshake + Stall : OTG_HS_DOEPCTL_Stall_Field := 16#0#; + -- unspecified + Reserved_22_25 : STM32F40x.UInt4 := 16#0#; + -- Write-only. Clear NAK + CNAK : OTG_HS_DOEPCTL_CNAK_Field := 16#0#; + -- Write-only. Set NAK + SNAK : OTG_HS_DOEPCTL_SNAK_Field := 16#0#; + -- Write-only. Set DATA0 PID/Set even frame + SD0PID_SEVNFRM : OTG_HS_DOEPCTL_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. Set odd frame + SODDFRM : OTG_HS_DOEPCTL_SODDFRM_Field := 16#0#; + -- Endpoint disable + EPDIS : OTG_HS_DOEPCTL_EPDIS_Field := 16#0#; + -- Endpoint enable + EPENA : OTG_HS_DOEPCTL_EPENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HPTXSTS_Register use record - PTXFSAVL at 0 range 0 .. 15; - PTXQSAV at 0 range 16 .. 23; - PTXQTOP at 0 range 24 .. 31; + for OTG_HS_DOEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - --------------------------- - -- OTG_HS_HAINT_Register -- - --------------------------- + subtype OTG_HS_DOEPTSIZ_XFRSIZ_Field is STM32F40x.UInt19; + subtype OTG_HS_DOEPTSIZ_PKTCNT_Field is STM32F40x.UInt10; + subtype OTG_HS_DOEPTSIZ_RXDPID_STUPCNT_Field is STM32F40x.UInt2; - subtype OTG_HS_HAINT_HAINT_Field is STM32F40x.Short; - - -- OTG_HS Host all channels interrupt register - type OTG_HS_HAINT_Register is record - -- Read-only. Channel interrupts - HAINT : OTG_HS_HAINT_HAINT_Field := 16#0#; + -- OTG_HS device endpoint-2 transfer size register + type OTG_HS_DOEPTSIZ_Register is record + -- Transfer size + XFRSIZ : OTG_HS_DOEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : OTG_HS_DOEPTSIZ_PKTCNT_Field := 16#0#; + -- Received data PID/SETUP packet count + RXDPID_STUPCNT : OTG_HS_DOEPTSIZ_RXDPID_STUPCNT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HAINT_Register use record - HAINT at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_DOEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + RXDPID_STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------------ - -- OTG_HS_HAINTMSK_Register -- - ------------------------------ - - subtype OTG_HS_HAINTMSK_HAINTM_Field is STM32F40x.Short; + subtype OTG_HS_GOTGCTL_SRQSCS_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_SRQ_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_HNGSCS_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_HNPRQ_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_HSHNPEN_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_DHNPEN_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_CIDSTS_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_DBCT_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_ASVLD_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGCTL_BSVLD_Field is STM32F40x.Bit; - -- OTG_HS host all channels interrupt mask register - type OTG_HS_HAINTMSK_Register is record - -- Channel interrupt mask - HAINTM : OTG_HS_HAINTMSK_HAINTM_Field := 16#0#; + -- OTG_HS control and status register + type OTG_HS_GOTGCTL_Register is record + -- Read-only. Session request success + SRQSCS : OTG_HS_GOTGCTL_SRQSCS_Field := 16#0#; + -- Session request + SRQ : OTG_HS_GOTGCTL_SRQ_Field := 16#0#; + -- unspecified + Reserved_2_7 : STM32F40x.UInt6 := 16#0#; + -- Read-only. Host negotiation success + HNGSCS : OTG_HS_GOTGCTL_HNGSCS_Field := 16#0#; + -- HNP request + HNPRQ : OTG_HS_GOTGCTL_HNPRQ_Field := 16#0#; + -- Host set HNP enable + HSHNPEN : OTG_HS_GOTGCTL_HSHNPEN_Field := 16#0#; + -- Device HNP enabled + DHNPEN : OTG_HS_GOTGCTL_DHNPEN_Field := 16#1#; + -- unspecified + Reserved_12_15 : STM32F40x.UInt4 := 16#0#; + -- Read-only. Connector ID status + CIDSTS : OTG_HS_GOTGCTL_CIDSTS_Field := 16#0#; + -- Read-only. Long/short debounce time + DBCT : OTG_HS_GOTGCTL_DBCT_Field := 16#0#; + -- Read-only. A-session valid + ASVLD : OTG_HS_GOTGCTL_ASVLD_Field := 16#0#; + -- Read-only. B-session valid + BSVLD : OTG_HS_GOTGCTL_BSVLD_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_20_31 : STM32F40x.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HAINTMSK_Register use record - HAINTM at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_GOTGCTL_Register use record + SRQSCS at 0 range 0 .. 0; + SRQ at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + HNGSCS at 0 range 8 .. 8; + HNPRQ at 0 range 9 .. 9; + HSHNPEN at 0 range 10 .. 10; + DHNPEN at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + CIDSTS at 0 range 16 .. 16; + DBCT at 0 range 17 .. 17; + ASVLD at 0 range 18 .. 18; + BSVLD at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - -------------------------- - -- OTG_HS_HPRT_Register -- - -------------------------- - - subtype OTG_HS_HPRT_PCSTS_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_PCDET_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_PENA_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_PENCHNG_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_POCA_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_POCCHNG_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_PRES_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_PSUSP_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_PRST_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_PLSTS_Field is STM32F40x.UInt2; - subtype OTG_HS_HPRT_PPWR_Field is STM32F40x.Bit; - subtype OTG_HS_HPRT_PTCTL_Field is STM32F40x.UInt4; - subtype OTG_HS_HPRT_PSPD_Field is STM32F40x.UInt2; + subtype OTG_HS_GOTGINT_SEDET_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGINT_SRSSCHG_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGINT_HNSSCHG_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGINT_HNGDET_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGINT_ADTOCHG_Field is STM32F40x.Bit; + subtype OTG_HS_GOTGINT_DBCDNE_Field is STM32F40x.Bit; - -- OTG_HS host port control and status register - type OTG_HS_HPRT_Register is record - -- Read-only. Port connect status - PCSTS : OTG_HS_HPRT_PCSTS_Field := 16#0#; - -- Port connect detected - PCDET : OTG_HS_HPRT_PCDET_Field := 16#0#; - -- Port enable - PENA : OTG_HS_HPRT_PENA_Field := 16#0#; - -- Port enable/disable change - PENCHNG : OTG_HS_HPRT_PENCHNG_Field := 16#0#; - -- Read-only. Port overcurrent active - POCA : OTG_HS_HPRT_POCA_Field := 16#0#; - -- Port overcurrent change - POCCHNG : OTG_HS_HPRT_POCCHNG_Field := 16#0#; - -- Port resume - PRES : OTG_HS_HPRT_PRES_Field := 16#0#; - -- Port suspend - PSUSP : OTG_HS_HPRT_PSUSP_Field := 16#0#; - -- Port reset - PRST : OTG_HS_HPRT_PRST_Field := 16#0#; + -- OTG_HS interrupt register + type OTG_HS_GOTGINT_Register is record -- unspecified - Reserved_9_9 : STM32F40x.Bit := 16#0#; - -- Read-only. Port line status - PLSTS : OTG_HS_HPRT_PLSTS_Field := 16#0#; - -- Port power - PPWR : OTG_HS_HPRT_PPWR_Field := 16#0#; - -- Port test control - PTCTL : OTG_HS_HPRT_PTCTL_Field := 16#0#; - -- Read-only. Port speed - PSPD : OTG_HS_HPRT_PSPD_Field := 16#0#; + Reserved_0_1 : STM32F40x.UInt2 := 16#0#; + -- Session end detected + SEDET : OTG_HS_GOTGINT_SEDET_Field := 16#0#; -- unspecified - Reserved_19_31 : STM32F40x.UInt13 := 16#0#; + Reserved_3_7 : STM32F40x.UInt5 := 16#0#; + -- Session request success status change + SRSSCHG : OTG_HS_GOTGINT_SRSSCHG_Field := 16#0#; + -- Host negotiation success status change + HNSSCHG : OTG_HS_GOTGINT_HNSSCHG_Field := 16#0#; + -- unspecified + Reserved_10_16 : STM32F40x.UInt7 := 16#0#; + -- Host negotiation detected + HNGDET : OTG_HS_GOTGINT_HNGDET_Field := 16#0#; + -- A-device timeout change + ADTOCHG : OTG_HS_GOTGINT_ADTOCHG_Field := 16#0#; + -- Debounce done + DBCDNE : OTG_HS_GOTGINT_DBCDNE_Field := 16#0#; + -- unspecified + Reserved_20_31 : STM32F40x.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HPRT_Register use record - PCSTS at 0 range 0 .. 0; - PCDET at 0 range 1 .. 1; - PENA at 0 range 2 .. 2; - PENCHNG at 0 range 3 .. 3; - POCA at 0 range 4 .. 4; - POCCHNG at 0 range 5 .. 5; - PRES at 0 range 6 .. 6; - PSUSP at 0 range 7 .. 7; - PRST at 0 range 8 .. 8; - Reserved_9_9 at 0 range 9 .. 9; - PLSTS at 0 range 10 .. 11; - PPWR at 0 range 12 .. 12; - PTCTL at 0 range 13 .. 16; - PSPD at 0 range 17 .. 18; - Reserved_19_31 at 0 range 19 .. 31; + for OTG_HS_GOTGINT_Register use record + Reserved_0_1 at 0 range 0 .. 1; + SEDET at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + SRSSCHG at 0 range 8 .. 8; + HNSSCHG at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + HNGDET at 0 range 17 .. 17; + ADTOCHG at 0 range 18 .. 18; + DBCDNE at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - ---------------------------- - -- OTG_HS_HCCHAR_Register -- - ---------------------------- - - subtype OTG_HS_HCCHAR0_MPSIZ_Field is STM32F40x.UInt11; - subtype OTG_HS_HCCHAR0_EPNUM_Field is STM32F40x.UInt4; - subtype OTG_HS_HCCHAR0_EPDIR_Field is STM32F40x.Bit; - subtype OTG_HS_HCCHAR0_LSDEV_Field is STM32F40x.Bit; - subtype OTG_HS_HCCHAR0_EPTYP_Field is STM32F40x.UInt2; - subtype OTG_HS_HCCHAR0_MC_Field is STM32F40x.UInt2; - subtype OTG_HS_HCCHAR0_DAD_Field is STM32F40x.UInt7; - subtype OTG_HS_HCCHAR0_ODDFRM_Field is STM32F40x.Bit; - subtype OTG_HS_HCCHAR0_CHDIS_Field is STM32F40x.Bit; - subtype OTG_HS_HCCHAR0_CHENA_Field is STM32F40x.Bit; + subtype OTG_HS_GAHBCFG_GINT_Field is STM32F40x.Bit; + subtype OTG_HS_GAHBCFG_HBSTLEN_Field is STM32F40x.UInt4; + subtype OTG_HS_GAHBCFG_DMAEN_Field is STM32F40x.Bit; + subtype OTG_HS_GAHBCFG_TXFELVL_Field is STM32F40x.Bit; + subtype OTG_HS_GAHBCFG_PTXFELVL_Field is STM32F40x.Bit; - -- OTG_HS host channel-0 characteristics register - type OTG_HS_HCCHAR_Register is record - -- Maximum packet size - MPSIZ : OTG_HS_HCCHAR0_MPSIZ_Field := 16#0#; - -- Endpoint number - EPNUM : OTG_HS_HCCHAR0_EPNUM_Field := 16#0#; - -- Endpoint direction - EPDIR : OTG_HS_HCCHAR0_EPDIR_Field := 16#0#; + -- OTG_HS AHB configuration register + type OTG_HS_GAHBCFG_Register is record + -- Global interrupt mask + GINT : OTG_HS_GAHBCFG_GINT_Field := 16#0#; + -- Burst length/type + HBSTLEN : OTG_HS_GAHBCFG_HBSTLEN_Field := 16#0#; + -- DMA enable + DMAEN : OTG_HS_GAHBCFG_DMAEN_Field := 16#0#; -- unspecified - Reserved_16_16 : STM32F40x.Bit := 16#0#; - -- Low-speed device - LSDEV : OTG_HS_HCCHAR0_LSDEV_Field := 16#0#; - -- Endpoint type - EPTYP : OTG_HS_HCCHAR0_EPTYP_Field := 16#0#; - -- Multi Count (MC) / Error Count (EC) - MC : OTG_HS_HCCHAR0_MC_Field := 16#0#; - -- Device address - DAD : OTG_HS_HCCHAR0_DAD_Field := 16#0#; - -- Odd frame - ODDFRM : OTG_HS_HCCHAR0_ODDFRM_Field := 16#0#; - -- Channel disable - CHDIS : OTG_HS_HCCHAR0_CHDIS_Field := 16#0#; - -- Channel enable - CHENA : OTG_HS_HCCHAR0_CHENA_Field := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for OTG_HS_HCCHAR_Register use record - MPSIZ at 0 range 0 .. 10; - EPNUM at 0 range 11 .. 14; - EPDIR at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - LSDEV at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - MC at 0 range 20 .. 21; - DAD at 0 range 22 .. 28; - ODDFRM at 0 range 29 .. 29; - CHDIS at 0 range 30 .. 30; - CHENA at 0 range 31 .. 31; - end record; - - ---------------------------- - -- OTG_HS_HCSPLT_Register -- - ---------------------------- - - subtype OTG_HS_HCSPLT0_PRTADDR_Field is STM32F40x.UInt7; - subtype OTG_HS_HCSPLT0_HUBADDR_Field is STM32F40x.UInt7; - subtype OTG_HS_HCSPLT0_XACTPOS_Field is STM32F40x.UInt2; - subtype OTG_HS_HCSPLT0_COMPLSPLT_Field is STM32F40x.Bit; - subtype OTG_HS_HCSPLT0_SPLITEN_Field is STM32F40x.Bit; - - -- OTG_HS host channel-0 split control register - type OTG_HS_HCSPLT_Register is record - -- Port address - PRTADDR : OTG_HS_HCSPLT0_PRTADDR_Field := 16#0#; - -- Hub address - HUBADDR : OTG_HS_HCSPLT0_HUBADDR_Field := 16#0#; - -- XACTPOS - XACTPOS : OTG_HS_HCSPLT0_XACTPOS_Field := 16#0#; - -- Do complete split - COMPLSPLT : OTG_HS_HCSPLT0_COMPLSPLT_Field := 16#0#; + Reserved_6_6 : STM32F40x.Bit := 16#0#; + -- TxFIFO empty level + TXFELVL : OTG_HS_GAHBCFG_TXFELVL_Field := 16#0#; + -- Periodic TxFIFO empty level + PTXFELVL : OTG_HS_GAHBCFG_PTXFELVL_Field := 16#0#; -- unspecified - Reserved_17_30 : STM32F40x.UInt14 := 16#0#; - -- Split enable - SPLITEN : OTG_HS_HCSPLT0_SPLITEN_Field := 16#0#; + Reserved_9_31 : STM32F40x.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HCSPLT_Register use record - PRTADDR at 0 range 0 .. 6; - HUBADDR at 0 range 7 .. 13; - XACTPOS at 0 range 14 .. 15; - COMPLSPLT at 0 range 16 .. 16; - Reserved_17_30 at 0 range 17 .. 30; - SPLITEN at 0 range 31 .. 31; + for OTG_HS_GAHBCFG_Register use record + GINT at 0 range 0 .. 0; + HBSTLEN at 0 range 1 .. 4; + DMAEN at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + TXFELVL at 0 range 7 .. 7; + PTXFELVL at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; end record; - --------------------------- - -- OTG_HS_HCINT_Register -- - --------------------------- - - subtype OTG_HS_HCINT0_XFRC_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_CHH_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_AHBERR_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_STALL_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_NAK_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_ACK_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_NYET_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_TXERR_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_BBERR_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_FRMOR_Field is STM32F40x.Bit; - subtype OTG_HS_HCINT0_DTERR_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_TOCAL_Field is STM32F40x.UInt3; + subtype OTG_HS_GUSBCFG_PHYSEL_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_SRPCAP_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_HNPCAP_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_TRDT_Field is STM32F40x.UInt4; + subtype OTG_HS_GUSBCFG_PHYLPCS_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_ULPIFSLS_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_ULPIAR_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_ULPICSM_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_ULPIEVBUSD_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_ULPIEVBUSI_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_TSDPS_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_PCCI_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_PTCI_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_ULPIIPD_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_FHMOD_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_FDMOD_Field is STM32F40x.Bit; + subtype OTG_HS_GUSBCFG_CTXPKT_Field is STM32F40x.Bit; - -- OTG_HS host channel-11 interrupt register - type OTG_HS_HCINT_Register is record - -- Transfer completed - XFRC : OTG_HS_HCINT0_XFRC_Field := 16#0#; - -- Channel halted - CHH : OTG_HS_HCINT0_CHH_Field := 16#0#; - -- AHB error - AHBERR : OTG_HS_HCINT0_AHBERR_Field := 16#0#; - -- STALL response received interrupt - STALL : OTG_HS_HCINT0_STALL_Field := 16#0#; - -- NAK response received interrupt - NAK : OTG_HS_HCINT0_NAK_Field := 16#0#; - -- ACK response received/transmitted interrupt - ACK : OTG_HS_HCINT0_ACK_Field := 16#0#; - -- Response received interrupt - NYET : OTG_HS_HCINT0_NYET_Field := 16#0#; - -- Transaction error - TXERR : OTG_HS_HCINT0_TXERR_Field := 16#0#; - -- Babble error - BBERR : OTG_HS_HCINT0_BBERR_Field := 16#0#; - -- Frame overrun - FRMOR : OTG_HS_HCINT0_FRMOR_Field := 16#0#; - -- Data toggle error - DTERR : OTG_HS_HCINT0_DTERR_Field := 16#0#; + -- OTG_HS USB configuration register + type OTG_HS_GUSBCFG_Register is record + -- FS timeout calibration + TOCAL : OTG_HS_GUSBCFG_TOCAL_Field := 16#0#; -- unspecified - Reserved_11_31 : STM32F40x.UInt21 := 16#0#; + Reserved_3_5 : STM32F40x.UInt3 := 16#0#; + -- Write-only. USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial + -- transceiver select + PHYSEL : OTG_HS_GUSBCFG_PHYSEL_Field := 16#0#; + -- unspecified + Reserved_7_7 : STM32F40x.Bit := 16#0#; + -- SRP-capable + SRPCAP : OTG_HS_GUSBCFG_SRPCAP_Field := 16#0#; + -- HNP-capable + HNPCAP : OTG_HS_GUSBCFG_HNPCAP_Field := 16#1#; + -- USB turnaround time + TRDT : OTG_HS_GUSBCFG_TRDT_Field := 16#2#; + -- unspecified + Reserved_14_14 : STM32F40x.Bit := 16#0#; + -- PHY Low-power clock select + PHYLPCS : OTG_HS_GUSBCFG_PHYLPCS_Field := 16#0#; + -- unspecified + Reserved_16_16 : STM32F40x.Bit := 16#0#; + -- ULPI FS/LS select + ULPIFSLS : OTG_HS_GUSBCFG_ULPIFSLS_Field := 16#0#; + -- ULPI Auto-resume + ULPIAR : OTG_HS_GUSBCFG_ULPIAR_Field := 16#0#; + -- ULPI Clock SuspendM + ULPICSM : OTG_HS_GUSBCFG_ULPICSM_Field := 16#0#; + -- ULPI External VBUS Drive + ULPIEVBUSD : OTG_HS_GUSBCFG_ULPIEVBUSD_Field := 16#0#; + -- ULPI external VBUS indicator + ULPIEVBUSI : OTG_HS_GUSBCFG_ULPIEVBUSI_Field := 16#0#; + -- TermSel DLine pulsing selection + TSDPS : OTG_HS_GUSBCFG_TSDPS_Field := 16#0#; + -- Indicator complement + PCCI : OTG_HS_GUSBCFG_PCCI_Field := 16#0#; + -- Indicator pass through + PTCI : OTG_HS_GUSBCFG_PTCI_Field := 16#0#; + -- ULPI interface protect disable + ULPIIPD : OTG_HS_GUSBCFG_ULPIIPD_Field := 16#0#; + -- unspecified + Reserved_26_28 : STM32F40x.UInt3 := 16#0#; + -- Forced host mode + FHMOD : OTG_HS_GUSBCFG_FHMOD_Field := 16#0#; + -- Forced peripheral mode + FDMOD : OTG_HS_GUSBCFG_FDMOD_Field := 16#0#; + -- Corrupt Tx packet + CTXPKT : OTG_HS_GUSBCFG_CTXPKT_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HCINT_Register use record - XFRC at 0 range 0 .. 0; - CHH at 0 range 1 .. 1; - AHBERR at 0 range 2 .. 2; - STALL at 0 range 3 .. 3; - NAK at 0 range 4 .. 4; - ACK at 0 range 5 .. 5; - NYET at 0 range 6 .. 6; - TXERR at 0 range 7 .. 7; - BBERR at 0 range 8 .. 8; - FRMOR at 0 range 9 .. 9; - DTERR at 0 range 10 .. 10; - Reserved_11_31 at 0 range 11 .. 31; + for OTG_HS_GUSBCFG_Register use record + TOCAL at 0 range 0 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + PHYSEL at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + SRPCAP at 0 range 8 .. 8; + HNPCAP at 0 range 9 .. 9; + TRDT at 0 range 10 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + PHYLPCS at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + ULPIFSLS at 0 range 17 .. 17; + ULPIAR at 0 range 18 .. 18; + ULPICSM at 0 range 19 .. 19; + ULPIEVBUSD at 0 range 20 .. 20; + ULPIEVBUSI at 0 range 21 .. 21; + TSDPS at 0 range 22 .. 22; + PCCI at 0 range 23 .. 23; + PTCI at 0 range 24 .. 24; + ULPIIPD at 0 range 25 .. 25; + Reserved_26_28 at 0 range 26 .. 28; + FHMOD at 0 range 29 .. 29; + FDMOD at 0 range 30 .. 30; + CTXPKT at 0 range 31 .. 31; end record; - ------------------------------ - -- OTG_HS_HCINTMSK_Register -- - ------------------------------ - - subtype OTG_HS_HCINTMSK0_XFRCM_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_CHHM_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_AHBERR_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_STALLM_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_NAKM_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_ACKM_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_NYET_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_TXERRM_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_BBERRM_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_FRMORM_Field is STM32F40x.Bit; - subtype OTG_HS_HCINTMSK0_DTERRM_Field is STM32F40x.Bit; + subtype OTG_HS_GRSTCTL_CSRST_Field is STM32F40x.Bit; + subtype OTG_HS_GRSTCTL_HSRST_Field is STM32F40x.Bit; + subtype OTG_HS_GRSTCTL_FCRST_Field is STM32F40x.Bit; + subtype OTG_HS_GRSTCTL_RXFFLSH_Field is STM32F40x.Bit; + subtype OTG_HS_GRSTCTL_TXFFLSH_Field is STM32F40x.Bit; + subtype OTG_HS_GRSTCTL_TXFNUM_Field is STM32F40x.UInt5; + subtype OTG_HS_GRSTCTL_DMAREQ_Field is STM32F40x.Bit; + subtype OTG_HS_GRSTCTL_AHBIDL_Field is STM32F40x.Bit; - -- OTG_HS host channel-11 interrupt mask register - type OTG_HS_HCINTMSK_Register is record - -- Transfer completed mask - XFRCM : OTG_HS_HCINTMSK0_XFRCM_Field := 16#0#; - -- Channel halted mask - CHHM : OTG_HS_HCINTMSK0_CHHM_Field := 16#0#; - -- AHB error - AHBERR : OTG_HS_HCINTMSK0_AHBERR_Field := 16#0#; - -- STALL response received interrupt mask - STALLM : OTG_HS_HCINTMSK0_STALLM_Field := 16#0#; - -- NAK response received interrupt mask - NAKM : OTG_HS_HCINTMSK0_NAKM_Field := 16#0#; - -- ACK response received/transmitted interrupt mask - ACKM : OTG_HS_HCINTMSK0_ACKM_Field := 16#0#; - -- response received interrupt mask - NYET : OTG_HS_HCINTMSK0_NYET_Field := 16#0#; - -- Transaction error mask - TXERRM : OTG_HS_HCINTMSK0_TXERRM_Field := 16#0#; - -- Babble error mask - BBERRM : OTG_HS_HCINTMSK0_BBERRM_Field := 16#0#; - -- Frame overrun mask - FRMORM : OTG_HS_HCINTMSK0_FRMORM_Field := 16#0#; - -- Data toggle error mask - DTERRM : OTG_HS_HCINTMSK0_DTERRM_Field := 16#0#; + -- OTG_HS reset register + type OTG_HS_GRSTCTL_Register is record + -- Core soft reset + CSRST : OTG_HS_GRSTCTL_CSRST_Field := 16#0#; + -- HCLK soft reset + HSRST : OTG_HS_GRSTCTL_HSRST_Field := 16#0#; + -- Host frame counter reset + FCRST : OTG_HS_GRSTCTL_FCRST_Field := 16#0#; -- unspecified - Reserved_11_31 : STM32F40x.UInt21 := 16#0#; + Reserved_3_3 : STM32F40x.Bit := 16#0#; + -- RxFIFO flush + RXFFLSH : OTG_HS_GRSTCTL_RXFFLSH_Field := 16#0#; + -- TxFIFO flush + TXFFLSH : OTG_HS_GRSTCTL_TXFFLSH_Field := 16#0#; + -- TxFIFO number + TXFNUM : OTG_HS_GRSTCTL_TXFNUM_Field := 16#0#; + -- unspecified + Reserved_11_29 : STM32F40x.UInt19 := 16#40000#; + -- Read-only. DMA request signal + DMAREQ : OTG_HS_GRSTCTL_DMAREQ_Field := 16#0#; + -- Read-only. AHB master idle + AHBIDL : OTG_HS_GRSTCTL_AHBIDL_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HCINTMSK_Register use record - XFRCM at 0 range 0 .. 0; - CHHM at 0 range 1 .. 1; - AHBERR at 0 range 2 .. 2; - STALLM at 0 range 3 .. 3; - NAKM at 0 range 4 .. 4; - ACKM at 0 range 5 .. 5; - NYET at 0 range 6 .. 6; - TXERRM at 0 range 7 .. 7; - BBERRM at 0 range 8 .. 8; - FRMORM at 0 range 9 .. 9; - DTERRM at 0 range 10 .. 10; - Reserved_11_31 at 0 range 11 .. 31; + for OTG_HS_GRSTCTL_Register use record + CSRST at 0 range 0 .. 0; + HSRST at 0 range 1 .. 1; + FCRST at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + RXFFLSH at 0 range 4 .. 4; + TXFFLSH at 0 range 5 .. 5; + TXFNUM at 0 range 6 .. 10; + Reserved_11_29 at 0 range 11 .. 29; + DMAREQ at 0 range 30 .. 30; + AHBIDL at 0 range 31 .. 31; end record; - ---------------------------- - -- OTG_HS_HCTSIZ_Register -- - ---------------------------- - - subtype OTG_HS_HCTSIZ0_XFRSIZ_Field is STM32F40x.UInt19; - subtype OTG_HS_HCTSIZ0_PKTCNT_Field is STM32F40x.UInt10; - subtype OTG_HS_HCTSIZ0_DPID_Field is STM32F40x.UInt2; - - -- OTG_HS host channel-11 transfer size register - type OTG_HS_HCTSIZ_Register is record - -- Transfer size - XFRSIZ : OTG_HS_HCTSIZ0_XFRSIZ_Field := 16#0#; - -- Packet count - PKTCNT : OTG_HS_HCTSIZ0_PKTCNT_Field := 16#0#; - -- Data PID - DPID : OTG_HS_HCTSIZ0_DPID_Field := 16#0#; - -- unspecified - Reserved_31_31 : STM32F40x.Bit := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for OTG_HS_HCTSIZ_Register use record - XFRSIZ at 0 range 0 .. 18; - PKTCNT at 0 range 19 .. 28; - DPID at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; - end record; - - -------------------------- - -- OTG_HS_DCFG_Register -- - -------------------------- - - subtype OTG_HS_DCFG_DSPD_Field is STM32F40x.UInt2; - subtype OTG_HS_DCFG_NZLSOHSK_Field is STM32F40x.Bit; - subtype OTG_HS_DCFG_DAD_Field is STM32F40x.UInt7; - subtype OTG_HS_DCFG_PFIVL_Field is STM32F40x.UInt2; - subtype OTG_HS_DCFG_PERSCHIVL_Field is STM32F40x.UInt2; + subtype OTG_HS_GINTSTS_CMOD_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_MMIS_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_OTGINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_SOF_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_RXFLVL_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_NPTXFE_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_GINAKEFF_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_BOUTNAKEFF_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_ESUSP_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_USBSUSP_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_USBRST_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_ENUMDNE_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_ISOODRP_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_EOPF_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_IEPINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_OEPINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_IISOIXFR_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_DATAFSUSP_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_HPRTINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_HCINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_PTXFE_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_CIDSCHG_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_DISCINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_SRQINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTSTS_WKUINT_Field is STM32F40x.Bit; - -- OTG_HS device configuration register - type OTG_HS_DCFG_Register is record - -- Device speed - DSPD : OTG_HS_DCFG_DSPD_Field := 16#0#; - -- Nonzero-length status OUT handshake - NZLSOHSK : OTG_HS_DCFG_NZLSOHSK_Field := 16#0#; + -- OTG_HS core interrupt register + type OTG_HS_GINTSTS_Register is record + -- Read-only. Current mode of operation + CMOD : OTG_HS_GINTSTS_CMOD_Field := 16#0#; + -- Mode mismatch interrupt + MMIS : OTG_HS_GINTSTS_MMIS_Field := 16#0#; + -- Read-only. OTG interrupt + OTGINT : OTG_HS_GINTSTS_OTGINT_Field := 16#0#; + -- Start of frame + SOF : OTG_HS_GINTSTS_SOF_Field := 16#0#; + -- Read-only. RxFIFO nonempty + RXFLVL : OTG_HS_GINTSTS_RXFLVL_Field := 16#0#; + -- Read-only. Nonperiodic TxFIFO empty + NPTXFE : OTG_HS_GINTSTS_NPTXFE_Field := 16#1#; + -- Read-only. Global IN nonperiodic NAK effective + GINAKEFF : OTG_HS_GINTSTS_GINAKEFF_Field := 16#0#; + -- Read-only. Global OUT NAK effective + BOUTNAKEFF : OTG_HS_GINTSTS_BOUTNAKEFF_Field := 16#0#; -- unspecified - Reserved_3_3 : STM32F40x.Bit := 16#0#; - -- Device address - DAD : OTG_HS_DCFG_DAD_Field := 16#0#; - -- Periodic (micro)frame interval - PFIVL : OTG_HS_DCFG_PFIVL_Field := 16#0#; + Reserved_8_9 : STM32F40x.UInt2 := 16#0#; + -- Early suspend + ESUSP : OTG_HS_GINTSTS_ESUSP_Field := 16#0#; + -- USB suspend + USBSUSP : OTG_HS_GINTSTS_USBSUSP_Field := 16#0#; + -- USB reset + USBRST : OTG_HS_GINTSTS_USBRST_Field := 16#0#; + -- Enumeration done + ENUMDNE : OTG_HS_GINTSTS_ENUMDNE_Field := 16#0#; + -- Isochronous OUT packet dropped interrupt + ISOODRP : OTG_HS_GINTSTS_ISOODRP_Field := 16#0#; + -- End of periodic frame interrupt + EOPF : OTG_HS_GINTSTS_EOPF_Field := 16#0#; -- unspecified - Reserved_13_23 : STM32F40x.UInt11 := 16#100#; - -- Periodic scheduling interval - PERSCHIVL : OTG_HS_DCFG_PERSCHIVL_Field := 16#2#; + Reserved_16_17 : STM32F40x.UInt2 := 16#0#; + -- Read-only. IN endpoint interrupt + IEPINT : OTG_HS_GINTSTS_IEPINT_Field := 16#0#; + -- Read-only. OUT endpoint interrupt + OEPINT : OTG_HS_GINTSTS_OEPINT_Field := 16#0#; + -- Incomplete isochronous IN transfer + IISOIXFR : OTG_HS_GINTSTS_IISOIXFR_Field := 16#0#; + -- Incomplete periodic transfer + PXFR_INCOMPISOOUT : OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Field := 16#0#; + -- Data fetch suspended + DATAFSUSP : OTG_HS_GINTSTS_DATAFSUSP_Field := 16#0#; -- unspecified - Reserved_26_31 : STM32F40x.UInt6 := 16#0#; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for OTG_HS_DCFG_Register use record - DSPD at 0 range 0 .. 1; - NZLSOHSK at 0 range 2 .. 2; - Reserved_3_3 at 0 range 3 .. 3; - DAD at 0 range 4 .. 10; - PFIVL at 0 range 11 .. 12; - Reserved_13_23 at 0 range 13 .. 23; - PERSCHIVL at 0 range 24 .. 25; - Reserved_26_31 at 0 range 26 .. 31; - end record; - - -------------------------- - -- OTG_HS_DCTL_Register -- - -------------------------- - - subtype OTG_HS_DCTL_RWUSIG_Field is STM32F40x.Bit; - subtype OTG_HS_DCTL_SDIS_Field is STM32F40x.Bit; - subtype OTG_HS_DCTL_GINSTS_Field is STM32F40x.Bit; - subtype OTG_HS_DCTL_GONSTS_Field is STM32F40x.Bit; - subtype OTG_HS_DCTL_TCTL_Field is STM32F40x.UInt3; - subtype OTG_HS_DCTL_SGINAK_Field is STM32F40x.Bit; - subtype OTG_HS_DCTL_CGINAK_Field is STM32F40x.Bit; - subtype OTG_HS_DCTL_SGONAK_Field is STM32F40x.Bit; - subtype OTG_HS_DCTL_CGONAK_Field is STM32F40x.Bit; - subtype OTG_HS_DCTL_POPRGDNE_Field is STM32F40x.Bit; - - -- OTG_HS device control register - type OTG_HS_DCTL_Register is record - -- Remote wakeup signaling - RWUSIG : OTG_HS_DCTL_RWUSIG_Field := 16#0#; - -- Soft disconnect - SDIS : OTG_HS_DCTL_SDIS_Field := 16#0#; - -- Read-only. Global IN NAK status - GINSTS : OTG_HS_DCTL_GINSTS_Field := 16#0#; - -- Read-only. Global OUT NAK status - GONSTS : OTG_HS_DCTL_GONSTS_Field := 16#0#; - -- Test control - TCTL : OTG_HS_DCTL_TCTL_Field := 16#0#; - -- Write-only. Set global IN NAK - SGINAK : OTG_HS_DCTL_SGINAK_Field := 16#0#; - -- Write-only. Clear global IN NAK - CGINAK : OTG_HS_DCTL_CGINAK_Field := 16#0#; - -- Write-only. Set global OUT NAK - SGONAK : OTG_HS_DCTL_SGONAK_Field := 16#0#; - -- Write-only. Clear global OUT NAK - CGONAK : OTG_HS_DCTL_CGONAK_Field := 16#0#; - -- Power-on programming done - POPRGDNE : OTG_HS_DCTL_POPRGDNE_Field := 16#0#; + Reserved_23_23 : STM32F40x.Bit := 16#0#; + -- Read-only. Host port interrupt + HPRTINT : OTG_HS_GINTSTS_HPRTINT_Field := 16#0#; + -- Read-only. Host channels interrupt + HCINT : OTG_HS_GINTSTS_HCINT_Field := 16#0#; + -- Read-only. Periodic TxFIFO empty + PTXFE : OTG_HS_GINTSTS_PTXFE_Field := 16#1#; -- unspecified - Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + Reserved_27_27 : STM32F40x.Bit := 16#0#; + -- Connector ID status change + CIDSCHG : OTG_HS_GINTSTS_CIDSCHG_Field := 16#0#; + -- Disconnect detected interrupt + DISCINT : OTG_HS_GINTSTS_DISCINT_Field := 16#0#; + -- Session request/new session detected interrupt + SRQINT : OTG_HS_GINTSTS_SRQINT_Field := 16#0#; + -- Resume/remote wakeup detected interrupt + WKUINT : OTG_HS_GINTSTS_WKUINT_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DCTL_Register use record - RWUSIG at 0 range 0 .. 0; - SDIS at 0 range 1 .. 1; - GINSTS at 0 range 2 .. 2; - GONSTS at 0 range 3 .. 3; - TCTL at 0 range 4 .. 6; - SGINAK at 0 range 7 .. 7; - CGINAK at 0 range 8 .. 8; - SGONAK at 0 range 9 .. 9; - CGONAK at 0 range 10 .. 10; - POPRGDNE at 0 range 11 .. 11; - Reserved_12_31 at 0 range 12 .. 31; + for OTG_HS_GINTSTS_Register use record + CMOD at 0 range 0 .. 0; + MMIS at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOF at 0 range 3 .. 3; + RXFLVL at 0 range 4 .. 4; + NPTXFE at 0 range 5 .. 5; + GINAKEFF at 0 range 6 .. 6; + BOUTNAKEFF at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSP at 0 range 10 .. 10; + USBSUSP at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNE at 0 range 13 .. 13; + ISOODRP at 0 range 14 .. 14; + EOPF at 0 range 15 .. 15; + Reserved_16_17 at 0 range 16 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFR at 0 range 20 .. 20; + PXFR_INCOMPISOOUT at 0 range 21 .. 21; + DATAFSUSP at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + HPRTINT at 0 range 24 .. 24; + HCINT at 0 range 25 .. 25; + PTXFE at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHG at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQINT at 0 range 30 .. 30; + WKUINT at 0 range 31 .. 31; end record; - -------------------------- - -- OTG_HS_DSTS_Register -- - -------------------------- - - subtype OTG_HS_DSTS_SUSPSTS_Field is STM32F40x.Bit; - subtype OTG_HS_DSTS_ENUMSPD_Field is STM32F40x.UInt2; - subtype OTG_HS_DSTS_EERR_Field is STM32F40x.Bit; - subtype OTG_HS_DSTS_FNSOF_Field is STM32F40x.UInt14; + subtype OTG_HS_GINTMSK_MMISM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_OTGINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_SOFM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_RXFLVLM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_NPTXFEM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_GINAKEFFM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_GONAKEFFM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_ESUSPM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_USBSUSPM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_USBRST_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_ENUMDNEM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_ISOODRPM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_EOPFM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_EPMISM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_IEPINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_OEPINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_IISOIXFRM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_FSUSPM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_PRTIM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_HCIM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_PTXFEM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_CIDSCHGM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_DISCINT_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_SRQIM_Field is STM32F40x.Bit; + subtype OTG_HS_GINTMSK_WUIM_Field is STM32F40x.Bit; - -- OTG_HS device status register - type OTG_HS_DSTS_Register is record - -- Read-only. Suspend status - SUSPSTS : OTG_HS_DSTS_SUSPSTS_Field := 16#0#; - -- Read-only. Enumerated speed - ENUMSPD : OTG_HS_DSTS_ENUMSPD_Field := 16#0#; - -- Read-only. Erratic error - EERR : OTG_HS_DSTS_EERR_Field := 16#0#; + -- OTG_HS interrupt mask register + type OTG_HS_GINTMSK_Register is record -- unspecified - Reserved_4_7 : STM32F40x.UInt4; - -- Read-only. Frame number of the received SOF - FNSOF : OTG_HS_DSTS_FNSOF_Field := 16#0#; + Reserved_0_0 : STM32F40x.Bit := 16#0#; + -- Mode mismatch interrupt mask + MMISM : OTG_HS_GINTMSK_MMISM_Field := 16#0#; + -- OTG interrupt mask + OTGINT : OTG_HS_GINTMSK_OTGINT_Field := 16#0#; + -- Start of frame mask + SOFM : OTG_HS_GINTMSK_SOFM_Field := 16#0#; + -- Receive FIFO nonempty mask + RXFLVLM : OTG_HS_GINTMSK_RXFLVLM_Field := 16#0#; + -- Nonperiodic TxFIFO empty mask + NPTXFEM : OTG_HS_GINTMSK_NPTXFEM_Field := 16#0#; + -- Global nonperiodic IN NAK effective mask + GINAKEFFM : OTG_HS_GINTMSK_GINAKEFFM_Field := 16#0#; + -- Global OUT NAK effective mask + GONAKEFFM : OTG_HS_GINTMSK_GONAKEFFM_Field := 16#0#; -- unspecified - Reserved_22_31 : STM32F40x.UInt10; - end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; - - for OTG_HS_DSTS_Register use record - SUSPSTS at 0 range 0 .. 0; - ENUMSPD at 0 range 1 .. 2; - EERR at 0 range 3 .. 3; - Reserved_4_7 at 0 range 4 .. 7; - FNSOF at 0 range 8 .. 21; - Reserved_22_31 at 0 range 22 .. 31; - end record; - - ----------------------------- - -- OTG_HS_DIEPMSK_Register -- - ----------------------------- - - subtype OTG_HS_DIEPMSK_XFRCM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPMSK_EPDM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPMSK_TOM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPMSK_ITTXFEMSK_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPMSK_INEPNMM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPMSK_INEPNEM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPMSK_TXFURM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPMSK_BIM_Field is STM32F40x.Bit; - - -- OTG_HS device IN endpoint common interrupt mask register - type OTG_HS_DIEPMSK_Register is record - -- Transfer completed interrupt mask - XFRCM : OTG_HS_DIEPMSK_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : OTG_HS_DIEPMSK_EPDM_Field := 16#0#; + Reserved_8_9 : STM32F40x.UInt2 := 16#0#; + -- Early suspend mask + ESUSPM : OTG_HS_GINTMSK_ESUSPM_Field := 16#0#; + -- USB suspend mask + USBSUSPM : OTG_HS_GINTMSK_USBSUSPM_Field := 16#0#; + -- USB reset mask + USBRST : OTG_HS_GINTMSK_USBRST_Field := 16#0#; + -- Enumeration done mask + ENUMDNEM : OTG_HS_GINTMSK_ENUMDNEM_Field := 16#0#; + -- Isochronous OUT packet dropped interrupt mask + ISOODRPM : OTG_HS_GINTMSK_ISOODRPM_Field := 16#0#; + -- End of periodic frame interrupt mask + EOPFM : OTG_HS_GINTMSK_EOPFM_Field := 16#0#; -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- Timeout condition mask (nonisochronous endpoints) - TOM : OTG_HS_DIEPMSK_TOM_Field := 16#0#; - -- IN token received when TxFIFO empty mask - ITTXFEMSK : OTG_HS_DIEPMSK_ITTXFEMSK_Field := 16#0#; - -- IN token received with EP mismatch mask - INEPNMM : OTG_HS_DIEPMSK_INEPNMM_Field := 16#0#; - -- IN endpoint NAK effective mask - INEPNEM : OTG_HS_DIEPMSK_INEPNEM_Field := 16#0#; + Reserved_16_16 : STM32F40x.Bit := 16#0#; + -- Endpoint mismatch interrupt mask + EPMISM : OTG_HS_GINTMSK_EPMISM_Field := 16#0#; + -- IN endpoints interrupt mask + IEPINT : OTG_HS_GINTMSK_IEPINT_Field := 16#0#; + -- OUT endpoints interrupt mask + OEPINT : OTG_HS_GINTMSK_OEPINT_Field := 16#0#; + -- Incomplete isochronous IN transfer mask + IISOIXFRM : OTG_HS_GINTMSK_IISOIXFRM_Field := 16#0#; + -- Incomplete periodic transfer mask + PXFRM_IISOOXFRM : OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Field := 16#0#; + -- Data fetch suspended mask + FSUSPM : OTG_HS_GINTMSK_FSUSPM_Field := 16#0#; -- unspecified - Reserved_7_7 : STM32F40x.Bit := 16#0#; - -- FIFO underrun mask - TXFURM : OTG_HS_DIEPMSK_TXFURM_Field := 16#0#; - -- BNA interrupt mask - BIM : OTG_HS_DIEPMSK_BIM_Field := 16#0#; + Reserved_23_23 : STM32F40x.Bit := 16#0#; + -- Read-only. Host port interrupt mask + PRTIM : OTG_HS_GINTMSK_PRTIM_Field := 16#0#; + -- Host channels interrupt mask + HCIM : OTG_HS_GINTMSK_HCIM_Field := 16#0#; + -- Periodic TxFIFO empty mask + PTXFEM : OTG_HS_GINTMSK_PTXFEM_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F40x.UInt22 := 16#0#; + Reserved_27_27 : STM32F40x.Bit := 16#0#; + -- Connector ID status change mask + CIDSCHGM : OTG_HS_GINTMSK_CIDSCHGM_Field := 16#0#; + -- Disconnect detected interrupt mask + DISCINT : OTG_HS_GINTMSK_DISCINT_Field := 16#0#; + -- Session request/new session detected interrupt mask + SRQIM : OTG_HS_GINTMSK_SRQIM_Field := 16#0#; + -- Resume/remote wakeup detected interrupt mask + WUIM : OTG_HS_GINTMSK_WUIM_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPMSK_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOM at 0 range 3 .. 3; - ITTXFEMSK at 0 range 4 .. 4; - INEPNMM at 0 range 5 .. 5; - INEPNEM at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - TXFURM at 0 range 8 .. 8; - BIM at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + for OTG_HS_GINTMSK_Register use record + Reserved_0_0 at 0 range 0 .. 0; + MMISM at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOFM at 0 range 3 .. 3; + RXFLVLM at 0 range 4 .. 4; + NPTXFEM at 0 range 5 .. 5; + GINAKEFFM at 0 range 6 .. 6; + GONAKEFFM at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSPM at 0 range 10 .. 10; + USBSUSPM at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNEM at 0 range 13 .. 13; + ISOODRPM at 0 range 14 .. 14; + EOPFM at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + EPMISM at 0 range 17 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFRM at 0 range 20 .. 20; + PXFRM_IISOOXFRM at 0 range 21 .. 21; + FSUSPM at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + PRTIM at 0 range 24 .. 24; + HCIM at 0 range 25 .. 25; + PTXFEM at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHGM at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQIM at 0 range 30 .. 30; + WUIM at 0 range 31 .. 31; end record; - ----------------------------- - -- OTG_HS_DOEPMSK_Register -- - ----------------------------- - - subtype OTG_HS_DOEPMSK_XFRCM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPMSK_EPDM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPMSK_STUPM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPMSK_OTEPDM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPMSK_B2BSTUP_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPMSK_OPEM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPMSK_BOIM_Field is STM32F40x.Bit; - - -- OTG_HS device OUT endpoint common interrupt mask register - type OTG_HS_DOEPMSK_Register is record - -- Transfer completed interrupt mask - XFRCM : OTG_HS_DOEPMSK_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : OTG_HS_DOEPMSK_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- SETUP phase done mask - STUPM : OTG_HS_DOEPMSK_STUPM_Field := 16#0#; - -- OUT token received when endpoint disabled mask - OTEPDM : OTG_HS_DOEPMSK_OTEPDM_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F40x.Bit := 16#0#; - -- Back-to-back SETUP packets received mask - B2BSTUP : OTG_HS_DOEPMSK_B2BSTUP_Field := 16#0#; - -- unspecified - Reserved_7_7 : STM32F40x.Bit := 16#0#; - -- OUT packet error mask - OPEM : OTG_HS_DOEPMSK_OPEM_Field := 16#0#; - -- BNA interrupt mask - BOIM : OTG_HS_DOEPMSK_BOIM_Field := 16#0#; + subtype OTG_HS_GRXSTSR_Host_CHNUM_Field is STM32F40x.UInt4; + subtype OTG_HS_GRXSTSR_Host_BCNT_Field is STM32F40x.UInt11; + subtype OTG_HS_GRXSTSR_Host_DPID_Field is STM32F40x.UInt2; + subtype OTG_HS_GRXSTSR_Host_PKTSTS_Field is STM32F40x.UInt4; + + -- OTG_HS Receive status debug read register (host mode) + type OTG_HS_GRXSTSR_Host_Register is record + -- Read-only. Channel number + CHNUM : OTG_HS_GRXSTSR_Host_CHNUM_Field; + -- Read-only. Byte count + BCNT : OTG_HS_GRXSTSR_Host_BCNT_Field; + -- Read-only. Data PID + DPID : OTG_HS_GRXSTSR_Host_DPID_Field; + -- Read-only. Packet status + PKTSTS : OTG_HS_GRXSTSR_Host_PKTSTS_Field; -- unspecified - Reserved_10_31 : STM32F40x.UInt22 := 16#0#; + Reserved_21_31 : STM32F40x.UInt11; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPMSK_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STUPM at 0 range 3 .. 3; - OTEPDM at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - B2BSTUP at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - OPEM at 0 range 8 .. 8; - BOIM at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + for OTG_HS_GRXSTSR_Host_Register use record + CHNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - --------------------------- - -- OTG_HS_DAINT_Register -- - --------------------------- - - subtype OTG_HS_DAINT_IEPINT_Field is STM32F40x.Short; - subtype OTG_HS_DAINT_OEPINT_Field is STM32F40x.Short; + subtype OTG_HS_GRXSTSR_Peripheral_EPNUM_Field is STM32F40x.UInt4; + subtype OTG_HS_GRXSTSR_Peripheral_BCNT_Field is STM32F40x.UInt11; + subtype OTG_HS_GRXSTSR_Peripheral_DPID_Field is STM32F40x.UInt2; + subtype OTG_HS_GRXSTSR_Peripheral_PKTSTS_Field is STM32F40x.UInt4; + subtype OTG_HS_GRXSTSR_Peripheral_FRMNUM_Field is STM32F40x.UInt4; - -- OTG_HS device all endpoints interrupt register - type OTG_HS_DAINT_Register is record - -- Read-only. IN endpoint interrupt bits - IEPINT : OTG_HS_DAINT_IEPINT_Field := 16#0#; - -- Read-only. OUT endpoint interrupt bits - OEPINT : OTG_HS_DAINT_OEPINT_Field := 16#0#; + -- OTG_HS Receive status debug read register (peripheral mode mode) + type OTG_HS_GRXSTSR_Peripheral_Register is record + -- Read-only. Endpoint number + EPNUM : OTG_HS_GRXSTSR_Peripheral_EPNUM_Field; + -- Read-only. Byte count + BCNT : OTG_HS_GRXSTSR_Peripheral_BCNT_Field; + -- Read-only. Data PID + DPID : OTG_HS_GRXSTSR_Peripheral_DPID_Field; + -- Read-only. Packet status + PKTSTS : OTG_HS_GRXSTSR_Peripheral_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : OTG_HS_GRXSTSR_Peripheral_FRMNUM_Field; + -- unspecified + Reserved_25_31 : STM32F40x.UInt7; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DAINT_Register use record - IEPINT at 0 range 0 .. 15; - OEPINT at 0 range 16 .. 31; + for OTG_HS_GRXSTSR_Peripheral_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------------------ - -- OTG_HS_DAINTMSK_Register -- - ------------------------------ - - subtype OTG_HS_DAINTMSK_IEPM_Field is STM32F40x.Short; - subtype OTG_HS_DAINTMSK_OEPM_Field is STM32F40x.Short; + subtype OTG_HS_GRXSTSP_Host_CHNUM_Field is STM32F40x.UInt4; + subtype OTG_HS_GRXSTSP_Host_BCNT_Field is STM32F40x.UInt11; + subtype OTG_HS_GRXSTSP_Host_DPID_Field is STM32F40x.UInt2; + subtype OTG_HS_GRXSTSP_Host_PKTSTS_Field is STM32F40x.UInt4; - -- OTG_HS all endpoints interrupt mask register - type OTG_HS_DAINTMSK_Register is record - -- IN EP interrupt mask bits - IEPM : OTG_HS_DAINTMSK_IEPM_Field := 16#0#; - -- OUT EP interrupt mask bits - OEPM : OTG_HS_DAINTMSK_OEPM_Field := 16#0#; + -- OTG_HS status read and pop register (host mode) + type OTG_HS_GRXSTSP_Host_Register is record + -- Read-only. Channel number + CHNUM : OTG_HS_GRXSTSP_Host_CHNUM_Field; + -- Read-only. Byte count + BCNT : OTG_HS_GRXSTSP_Host_BCNT_Field; + -- Read-only. Data PID + DPID : OTG_HS_GRXSTSP_Host_DPID_Field; + -- Read-only. Packet status + PKTSTS : OTG_HS_GRXSTSP_Host_PKTSTS_Field; + -- unspecified + Reserved_21_31 : STM32F40x.UInt11; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DAINTMSK_Register use record - IEPM at 0 range 0 .. 15; - OEPM at 0 range 16 .. 31; + for OTG_HS_GRXSTSP_Host_Register use record + CHNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------------------ - -- OTG_HS_DVBUSDIS_Register -- - ------------------------------ - - subtype OTG_HS_DVBUSDIS_VBUSDT_Field is STM32F40x.Short; + subtype OTG_HS_GRXSTSP_Peripheral_EPNUM_Field is STM32F40x.UInt4; + subtype OTG_HS_GRXSTSP_Peripheral_BCNT_Field is STM32F40x.UInt11; + subtype OTG_HS_GRXSTSP_Peripheral_DPID_Field is STM32F40x.UInt2; + subtype OTG_HS_GRXSTSP_Peripheral_PKTSTS_Field is STM32F40x.UInt4; + subtype OTG_HS_GRXSTSP_Peripheral_FRMNUM_Field is STM32F40x.UInt4; - -- OTG_HS device VBUS discharge time register - type OTG_HS_DVBUSDIS_Register is record - -- Device VBUS discharge time - VBUSDT : OTG_HS_DVBUSDIS_VBUSDT_Field := 16#17D7#; + -- OTG_HS status read and pop register (peripheral mode) + type OTG_HS_GRXSTSP_Peripheral_Register is record + -- Read-only. Endpoint number + EPNUM : OTG_HS_GRXSTSP_Peripheral_EPNUM_Field; + -- Read-only. Byte count + BCNT : OTG_HS_GRXSTSP_Peripheral_BCNT_Field; + -- Read-only. Data PID + DPID : OTG_HS_GRXSTSP_Peripheral_DPID_Field; + -- Read-only. Packet status + PKTSTS : OTG_HS_GRXSTSP_Peripheral_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : OTG_HS_GRXSTSP_Peripheral_FRMNUM_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_25_31 : STM32F40x.UInt7; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DVBUSDIS_Register use record - VBUSDT at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_GRXSTSP_Peripheral_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; end record; - -------------------------------- - -- OTG_HS_DVBUSPULSE_Register -- - -------------------------------- - - subtype OTG_HS_DVBUSPULSE_DVBUSP_Field is STM32F40x.UInt12; + subtype OTG_HS_GRXFSIZ_RXFD_Field is STM32F40x.UInt16; - -- OTG_HS device VBUS pulsing time register - type OTG_HS_DVBUSPULSE_Register is record - -- Device VBUS pulsing time - DVBUSP : OTG_HS_DVBUSPULSE_DVBUSP_Field := 16#5B8#; + -- OTG_HS Receive FIFO size register + type OTG_HS_GRXFSIZ_Register is record + -- RxFIFO depth + RXFD : OTG_HS_GRXFSIZ_RXFD_Field := 16#200#; -- unspecified - Reserved_12_31 : STM32F40x.UInt20 := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DVBUSPULSE_Register use record - DVBUSP at 0 range 0 .. 11; - Reserved_12_31 at 0 range 12 .. 31; + for OTG_HS_GRXFSIZ_Register use record + RXFD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_DTHRCTL_Register -- - ----------------------------- - - subtype OTG_HS_DTHRCTL_NONISOTHREN_Field is STM32F40x.Bit; - subtype OTG_HS_DTHRCTL_ISOTHREN_Field is STM32F40x.Bit; - subtype OTG_HS_DTHRCTL_TXTHRLEN_Field is STM32F40x.UInt9; - subtype OTG_HS_DTHRCTL_RXTHREN_Field is STM32F40x.Bit; - subtype OTG_HS_DTHRCTL_RXTHRLEN_Field is STM32F40x.UInt9; - subtype OTG_HS_DTHRCTL_ARPEN_Field is STM32F40x.Bit; + subtype OTG_HS_GNPTXFSIZ_Host_NPTXFSA_Field is STM32F40x.UInt16; + subtype OTG_HS_GNPTXFSIZ_Host_NPTXFD_Field is STM32F40x.UInt16; - -- OTG_HS Device threshold control register - type OTG_HS_DTHRCTL_Register is record - -- Nonisochronous IN endpoints threshold enable - NONISOTHREN : OTG_HS_DTHRCTL_NONISOTHREN_Field := 16#0#; - -- ISO IN endpoint threshold enable - ISOTHREN : OTG_HS_DTHRCTL_ISOTHREN_Field := 16#0#; - -- Transmit threshold length - TXTHRLEN : OTG_HS_DTHRCTL_TXTHRLEN_Field := 16#0#; - -- unspecified - Reserved_11_15 : STM32F40x.UInt5 := 16#0#; - -- Receive threshold enable - RXTHREN : OTG_HS_DTHRCTL_RXTHREN_Field := 16#0#; - -- Receive threshold length - RXTHRLEN : OTG_HS_DTHRCTL_RXTHRLEN_Field := 16#0#; - -- unspecified - Reserved_26_26 : STM32F40x.Bit := 16#0#; - -- Arbiter parking enable - ARPEN : OTG_HS_DTHRCTL_ARPEN_Field := 16#0#; - -- unspecified - Reserved_28_31 : STM32F40x.UInt4 := 16#0#; + -- OTG_HS nonperiodic transmit FIFO size register (host mode) + type OTG_HS_GNPTXFSIZ_Host_Register is record + -- Nonperiodic transmit RAM start address + NPTXFSA : OTG_HS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; + -- Nonperiodic TxFIFO depth + NPTXFD : OTG_HS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DTHRCTL_Register use record - NONISOTHREN at 0 range 0 .. 0; - ISOTHREN at 0 range 1 .. 1; - TXTHRLEN at 0 range 2 .. 10; - Reserved_11_15 at 0 range 11 .. 15; - RXTHREN at 0 range 16 .. 16; - RXTHRLEN at 0 range 17 .. 25; - Reserved_26_26 at 0 range 26 .. 26; - ARPEN at 0 range 27 .. 27; - Reserved_28_31 at 0 range 28 .. 31; + for OTG_HS_GNPTXFSIZ_Host_Register use record + NPTXFSA at 0 range 0 .. 15; + NPTXFD at 0 range 16 .. 31; end record; - -------------------------------- - -- OTG_HS_DIEPEMPMSK_Register -- - -------------------------------- + subtype OTG_HS_TX0FSIZ_Peripheral_TX0FSA_Field is STM32F40x.UInt16; + subtype OTG_HS_TX0FSIZ_Peripheral_TX0FD_Field is STM32F40x.UInt16; - subtype OTG_HS_DIEPEMPMSK_INEPTXFEM_Field is STM32F40x.Short; + -- Endpoint 0 transmit FIFO size (peripheral mode) + type OTG_HS_TX0FSIZ_Peripheral_Register is record + -- Endpoint 0 transmit RAM start address + TX0FSA : OTG_HS_TX0FSIZ_Peripheral_TX0FSA_Field := 16#200#; + -- Endpoint 0 TxFIFO depth + TX0FD : OTG_HS_TX0FSIZ_Peripheral_TX0FD_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG_HS device IN endpoint FIFO empty interrupt mask register - type OTG_HS_DIEPEMPMSK_Register is record - -- IN EP Tx FIFO empty interrupt mask bits - INEPTXFEM : OTG_HS_DIEPEMPMSK_INEPTXFEM_Field := 16#0#; + for OTG_HS_TX0FSIZ_Peripheral_Register use record + TX0FSA at 0 range 0 .. 15; + TX0FD at 0 range 16 .. 31; + end record; + + subtype OTG_HS_GNPTXSTS_NPTXFSAV_Field is STM32F40x.UInt16; + subtype OTG_HS_GNPTXSTS_NPTQXSAV_Field is STM32F40x.Byte; + subtype OTG_HS_GNPTXSTS_NPTXQTOP_Field is STM32F40x.UInt7; + + -- OTG_HS nonperiodic transmit FIFO/queue status register + type OTG_HS_GNPTXSTS_Register is record + -- Read-only. Nonperiodic TxFIFO space available + NPTXFSAV : OTG_HS_GNPTXSTS_NPTXFSAV_Field; + -- Read-only. Nonperiodic transmit request queue space available + NPTQXSAV : OTG_HS_GNPTXSTS_NPTQXSAV_Field; + -- Read-only. Top of the nonperiodic transmit request queue + NPTXQTOP : OTG_HS_GNPTXSTS_NPTXQTOP_Field; -- unspecified - Reserved_16_31 : STM32F40x.Short := 16#0#; + Reserved_31_31 : STM32F40x.Bit; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPEMPMSK_Register use record - INEPTXFEM at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_GNPTXSTS_Register use record + NPTXFSAV at 0 range 0 .. 15; + NPTQXSAV at 0 range 16 .. 23; + NPTXQTOP at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------------ - -- OTG_HS_DEACHINT_Register -- - ------------------------------ - - subtype OTG_HS_DEACHINT_IEP1INT_Field is STM32F40x.Bit; - subtype OTG_HS_DEACHINT_OEP1INT_Field is STM32F40x.Bit; + subtype OTG_HS_GCCFG_PWRDWN_Field is STM32F40x.Bit; + subtype OTG_HS_GCCFG_I2CPADEN_Field is STM32F40x.Bit; + subtype OTG_HS_GCCFG_VBUSASEN_Field is STM32F40x.Bit; + subtype OTG_HS_GCCFG_VBUSBSEN_Field is STM32F40x.Bit; + subtype OTG_HS_GCCFG_SOFOUTEN_Field is STM32F40x.Bit; + subtype OTG_HS_GCCFG_NOVBUSSENS_Field is STM32F40x.Bit; - -- OTG_HS device each endpoint interrupt register - type OTG_HS_DEACHINT_Register is record - -- unspecified - Reserved_0_0 : STM32F40x.Bit := 16#0#; - -- IN endpoint 1interrupt bit - IEP1INT : OTG_HS_DEACHINT_IEP1INT_Field := 16#0#; + -- OTG_HS general core configuration register + type OTG_HS_GCCFG_Register is record -- unspecified - Reserved_2_16 : STM32F40x.UInt15 := 16#0#; - -- OUT endpoint 1 interrupt bit - OEP1INT : OTG_HS_DEACHINT_OEP1INT_Field := 16#0#; + Reserved_0_15 : STM32F40x.UInt16 := 16#0#; + -- Power down + PWRDWN : OTG_HS_GCCFG_PWRDWN_Field := 16#0#; + -- Enable I2C bus connection for the external I2C PHY interface + I2CPADEN : OTG_HS_GCCFG_I2CPADEN_Field := 16#0#; + -- Enable the VBUS sensing device + VBUSASEN : OTG_HS_GCCFG_VBUSASEN_Field := 16#0#; + -- Enable the VBUS sensing device + VBUSBSEN : OTG_HS_GCCFG_VBUSBSEN_Field := 16#0#; + -- SOF output enable + SOFOUTEN : OTG_HS_GCCFG_SOFOUTEN_Field := 16#0#; + -- VBUS sensing disable option + NOVBUSSENS : OTG_HS_GCCFG_NOVBUSSENS_Field := 16#0#; -- unspecified - Reserved_18_31 : STM32F40x.UInt14 := 16#0#; + Reserved_22_31 : STM32F40x.UInt10 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DEACHINT_Register use record - Reserved_0_0 at 0 range 0 .. 0; - IEP1INT at 0 range 1 .. 1; - Reserved_2_16 at 0 range 2 .. 16; - OEP1INT at 0 range 17 .. 17; - Reserved_18_31 at 0 range 18 .. 31; + for OTG_HS_GCCFG_Register use record + Reserved_0_15 at 0 range 0 .. 15; + PWRDWN at 0 range 16 .. 16; + I2CPADEN at 0 range 17 .. 17; + VBUSASEN at 0 range 18 .. 18; + VBUSBSEN at 0 range 19 .. 19; + SOFOUTEN at 0 range 20 .. 20; + NOVBUSSENS at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; end record; - --------------------------------- - -- OTG_HS_DEACHINTMSK_Register -- - --------------------------------- - - subtype OTG_HS_DEACHINTMSK_IEP1INTM_Field is STM32F40x.Bit; - subtype OTG_HS_DEACHINTMSK_OEP1INTM_Field is STM32F40x.Bit; + subtype OTG_HS_HPTXFSIZ_PTXSA_Field is STM32F40x.UInt16; + subtype OTG_HS_HPTXFSIZ_PTXFD_Field is STM32F40x.UInt16; - -- OTG_HS device each endpoint interrupt register mask - type OTG_HS_DEACHINTMSK_Register is record - -- unspecified - Reserved_0_0 : STM32F40x.Bit := 16#0#; - -- IN Endpoint 1 interrupt mask bit - IEP1INTM : OTG_HS_DEACHINTMSK_IEP1INTM_Field := 16#0#; - -- unspecified - Reserved_2_16 : STM32F40x.UInt15 := 16#0#; - -- OUT Endpoint 1 interrupt mask bit - OEP1INTM : OTG_HS_DEACHINTMSK_OEP1INTM_Field := 16#0#; - -- unspecified - Reserved_18_31 : STM32F40x.UInt14 := 16#0#; + -- OTG_HS Host periodic transmit FIFO size register + type OTG_HS_HPTXFSIZ_Register is record + -- Host periodic TxFIFO start address + PTXSA : OTG_HS_HPTXFSIZ_PTXSA_Field := 16#600#; + -- Host periodic TxFIFO depth + PTXFD : OTG_HS_HPTXFSIZ_PTXFD_Field := 16#200#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DEACHINTMSK_Register use record - Reserved_0_0 at 0 range 0 .. 0; - IEP1INTM at 0 range 1 .. 1; - Reserved_2_16 at 0 range 2 .. 16; - OEP1INTM at 0 range 17 .. 17; - Reserved_18_31 at 0 range 18 .. 31; + for OTG_HS_HPTXFSIZ_Register use record + PTXSA at 0 range 0 .. 15; + PTXFD at 0 range 16 .. 31; end record; - ---------------------------------- - -- OTG_HS_DIEPEACHMSK1_Register -- - ---------------------------------- + subtype OTG_HS_DIEPTXF_INEPTXSA_Field is STM32F40x.UInt16; + subtype OTG_HS_DIEPTXF_INEPTXFD_Field is STM32F40x.UInt16; - subtype OTG_HS_DIEPEACHMSK1_XFRCM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPEACHMSK1_EPDM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPEACHMSK1_TOM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPEACHMSK1_INEPNMM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPEACHMSK1_INEPNEM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPEACHMSK1_TXFURM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPEACHMSK1_BIM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPEACHMSK1_NAKM_Field is STM32F40x.Bit; - - -- OTG_HS device each in endpoint-1 interrupt register - type OTG_HS_DIEPEACHMSK1_Register is record - -- Transfer completed interrupt mask - XFRCM : OTG_HS_DIEPEACHMSK1_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : OTG_HS_DIEPEACHMSK1_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- Timeout condition mask (nonisochronous endpoints) - TOM : OTG_HS_DIEPEACHMSK1_TOM_Field := 16#0#; - -- IN token received when TxFIFO empty mask - ITTXFEMSK : OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Field := 16#0#; - -- IN token received with EP mismatch mask - INEPNMM : OTG_HS_DIEPEACHMSK1_INEPNMM_Field := 16#0#; - -- IN endpoint NAK effective mask - INEPNEM : OTG_HS_DIEPEACHMSK1_INEPNEM_Field := 16#0#; - -- unspecified - Reserved_7_7 : STM32F40x.Bit := 16#0#; - -- FIFO underrun mask - TXFURM : OTG_HS_DIEPEACHMSK1_TXFURM_Field := 16#0#; - -- BNA interrupt mask - BIM : OTG_HS_DIEPEACHMSK1_BIM_Field := 16#0#; - -- unspecified - Reserved_10_12 : STM32F40x.UInt3 := 16#0#; - -- NAK interrupt mask - NAKM : OTG_HS_DIEPEACHMSK1_NAKM_Field := 16#0#; - -- unspecified - Reserved_14_31 : STM32F40x.UInt18 := 16#0#; + -- OTG_HS device IN endpoint transmit FIFO size register + type OTG_HS_DIEPTXF_Register is record + -- IN endpoint FIFOx transmit RAM start address + INEPTXSA : OTG_HS_DIEPTXF_INEPTXSA_Field := 16#400#; + -- IN endpoint TxFIFO depth + INEPTXFD : OTG_HS_DIEPTXF_INEPTXFD_Field := 16#200#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPEACHMSK1_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOM at 0 range 3 .. 3; - ITTXFEMSK at 0 range 4 .. 4; - INEPNMM at 0 range 5 .. 5; - INEPNEM at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - TXFURM at 0 range 8 .. 8; - BIM at 0 range 9 .. 9; - Reserved_10_12 at 0 range 10 .. 12; - NAKM at 0 range 13 .. 13; - Reserved_14_31 at 0 range 14 .. 31; + for OTG_HS_DIEPTXF_Register use record + INEPTXSA at 0 range 0 .. 15; + INEPTXFD at 0 range 16 .. 31; end record; - ---------------------------------- - -- OTG_HS_DOEPEACHMSK1_Register -- - ---------------------------------- - - subtype OTG_HS_DOEPEACHMSK1_XFRCM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_EPDM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_TOM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_ITTXFEMSK_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_INEPNMM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_INEPNEM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_TXFURM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_BIM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_BERRM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_NAKM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPEACHMSK1_NYETM_Field is STM32F40x.Bit; + subtype OTG_HS_HCFG_FSLSPCS_Field is STM32F40x.UInt2; + subtype OTG_HS_HCFG_FSLSS_Field is STM32F40x.Bit; - -- OTG_HS device each OUT endpoint-1 interrupt register - type OTG_HS_DOEPEACHMSK1_Register is record - -- Transfer completed interrupt mask - XFRCM : OTG_HS_DOEPEACHMSK1_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : OTG_HS_DOEPEACHMSK1_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- Timeout condition mask - TOM : OTG_HS_DOEPEACHMSK1_TOM_Field := 16#0#; - -- IN token received when TxFIFO empty mask - ITTXFEMSK : OTG_HS_DOEPEACHMSK1_ITTXFEMSK_Field := 16#0#; - -- IN token received with EP mismatch mask - INEPNMM : OTG_HS_DOEPEACHMSK1_INEPNMM_Field := 16#0#; - -- IN endpoint NAK effective mask - INEPNEM : OTG_HS_DOEPEACHMSK1_INEPNEM_Field := 16#0#; - -- unspecified - Reserved_7_7 : STM32F40x.Bit := 16#0#; - -- OUT packet error mask - TXFURM : OTG_HS_DOEPEACHMSK1_TXFURM_Field := 16#0#; - -- BNA interrupt mask - BIM : OTG_HS_DOEPEACHMSK1_BIM_Field := 16#0#; - -- unspecified - Reserved_10_11 : STM32F40x.UInt2 := 16#0#; - -- Bubble error interrupt mask - BERRM : OTG_HS_DOEPEACHMSK1_BERRM_Field := 16#0#; - -- NAK interrupt mask - NAKM : OTG_HS_DOEPEACHMSK1_NAKM_Field := 16#0#; - -- NYET interrupt mask - NYETM : OTG_HS_DOEPEACHMSK1_NYETM_Field := 16#0#; + -- OTG_HS host configuration register + type OTG_HS_HCFG_Register is record + -- FS/LS PHY clock select + FSLSPCS : OTG_HS_HCFG_FSLSPCS_Field := 16#0#; + -- Read-only. FS- and LS-only support + FSLSS : OTG_HS_HCFG_FSLSS_Field := 16#0#; -- unspecified - Reserved_15_31 : STM32F40x.UInt17 := 16#0#; + Reserved_3_31 : STM32F40x.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPEACHMSK1_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOM at 0 range 3 .. 3; - ITTXFEMSK at 0 range 4 .. 4; - INEPNMM at 0 range 5 .. 5; - INEPNEM at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - TXFURM at 0 range 8 .. 8; - BIM at 0 range 9 .. 9; - Reserved_10_11 at 0 range 10 .. 11; - BERRM at 0 range 12 .. 12; - NAKM at 0 range 13 .. 13; - NYETM at 0 range 14 .. 14; - Reserved_15_31 at 0 range 15 .. 31; + for OTG_HS_HCFG_Register use record + FSLSPCS at 0 range 0 .. 1; + FSLSS at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; end record; - ----------------------------- - -- OTG_HS_DIEPCTL_Register -- - ----------------------------- - - subtype OTG_HS_DIEPCTL0_MPSIZ_Field is STM32F40x.UInt11; - subtype OTG_HS_DIEPCTL0_USBAEP_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_EONUM_DPID_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_NAKSTS_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_EPTYP_Field is STM32F40x.UInt2; - subtype OTG_HS_DIEPCTL0_Stall_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_TXFNUM_Field is STM32F40x.UInt4; - subtype OTG_HS_DIEPCTL0_CNAK_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_SNAK_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_SD0PID_SEVNFRM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_SODDFRM_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_EPDIS_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPCTL0_EPENA_Field is STM32F40x.Bit; + subtype OTG_HS_HFIR_FRIVL_Field is STM32F40x.UInt16; - -- OTG device endpoint-0 control register - type OTG_HS_DIEPCTL_Register is record - -- Maximum packet size - MPSIZ : OTG_HS_DIEPCTL0_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_11_14 : STM32F40x.UInt4 := 16#0#; - -- USB active endpoint - USBAEP : OTG_HS_DIEPCTL0_USBAEP_Field := 16#0#; - -- Read-only. Even/odd frame - EONUM_DPID : OTG_HS_DIEPCTL0_EONUM_DPID_Field := 16#0#; - -- Read-only. NAK status - NAKSTS : OTG_HS_DIEPCTL0_NAKSTS_Field := 16#0#; - -- Endpoint type - EPTYP : OTG_HS_DIEPCTL0_EPTYP_Field := 16#0#; + -- OTG_HS Host frame interval register + type OTG_HS_HFIR_Register is record + -- Frame interval + FRIVL : OTG_HS_HFIR_FRIVL_Field := 16#EA60#; -- unspecified - Reserved_20_20 : STM32F40x.Bit := 16#0#; - -- STALL handshake - Stall : OTG_HS_DIEPCTL0_Stall_Field := 16#0#; - -- TxFIFO number - TXFNUM : OTG_HS_DIEPCTL0_TXFNUM_Field := 16#0#; - -- Write-only. Clear NAK - CNAK : OTG_HS_DIEPCTL0_CNAK_Field := 16#0#; - -- Write-only. Set NAK - SNAK : OTG_HS_DIEPCTL0_SNAK_Field := 16#0#; - -- Write-only. Set DATA0 PID - SD0PID_SEVNFRM : OTG_HS_DIEPCTL0_SD0PID_SEVNFRM_Field := 16#0#; - -- Write-only. Set odd frame - SODDFRM : OTG_HS_DIEPCTL0_SODDFRM_Field := 16#0#; - -- Endpoint disable - EPDIS : OTG_HS_DIEPCTL0_EPDIS_Field := 16#0#; - -- Endpoint enable - EPENA : OTG_HS_DIEPCTL0_EPENA_Field := 16#0#; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPCTL_Register use record - MPSIZ at 0 range 0 .. 10; - Reserved_11_14 at 0 range 11 .. 14; - USBAEP at 0 range 15 .. 15; - EONUM_DPID at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - Reserved_20_20 at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - TXFNUM at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - SD0PID_SEVNFRM at 0 range 28 .. 28; - SODDFRM at 0 range 29 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for OTG_HS_HFIR_Register use record + FRIVL at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_DIEPINT_Register -- - ----------------------------- - - subtype OTG_HS_DIEPINT0_XFRC_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_EPDISD_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_TOC_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_ITTXFE_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_INEPNE_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_TXFE_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_TXFIFOUDRN_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_BNA_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_PKTDRPSTS_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_BERR_Field is STM32F40x.Bit; - subtype OTG_HS_DIEPINT0_NAK_Field is STM32F40x.Bit; + subtype OTG_HS_HFNUM_FRNUM_Field is STM32F40x.UInt16; + subtype OTG_HS_HFNUM_FTREM_Field is STM32F40x.UInt16; - -- OTG device endpoint-0 interrupt register - type OTG_HS_DIEPINT_Register is record - -- Transfer completed interrupt - XFRC : OTG_HS_DIEPINT0_XFRC_Field := 16#0#; - -- Endpoint disabled interrupt - EPDISD : OTG_HS_DIEPINT0_EPDISD_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- Timeout condition - TOC : OTG_HS_DIEPINT0_TOC_Field := 16#0#; - -- IN token received when TxFIFO is empty - ITTXFE : OTG_HS_DIEPINT0_ITTXFE_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F40x.Bit := 16#0#; - -- IN endpoint NAK effective - INEPNE : OTG_HS_DIEPINT0_INEPNE_Field := 16#0#; - -- Read-only. Transmit FIFO empty - TXFE : OTG_HS_DIEPINT0_TXFE_Field := 16#1#; - -- Transmit Fifo Underrun - TXFIFOUDRN : OTG_HS_DIEPINT0_TXFIFOUDRN_Field := 16#0#; - -- Buffer not available interrupt - BNA : OTG_HS_DIEPINT0_BNA_Field := 16#0#; - -- unspecified - Reserved_10_10 : STM32F40x.Bit := 16#0#; - -- Packet dropped status - PKTDRPSTS : OTG_HS_DIEPINT0_PKTDRPSTS_Field := 16#0#; - -- Babble error interrupt - BERR : OTG_HS_DIEPINT0_BERR_Field := 16#0#; - -- NAK interrupt - NAK : OTG_HS_DIEPINT0_NAK_Field := 16#0#; - -- unspecified - Reserved_14_31 : STM32F40x.UInt18 := 16#0#; + -- OTG_HS host frame number/frame time remaining register + type OTG_HS_HFNUM_Register is record + -- Read-only. Frame number + FRNUM : OTG_HS_HFNUM_FRNUM_Field; + -- Read-only. Frame time remaining + FTREM : OTG_HS_HFNUM_FTREM_Field; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPINT_Register use record - XFRC at 0 range 0 .. 0; - EPDISD at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOC at 0 range 3 .. 3; - ITTXFE at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - INEPNE at 0 range 6 .. 6; - TXFE at 0 range 7 .. 7; - TXFIFOUDRN at 0 range 8 .. 8; - BNA at 0 range 9 .. 9; - Reserved_10_10 at 0 range 10 .. 10; - PKTDRPSTS at 0 range 11 .. 11; - BERR at 0 range 12 .. 12; - NAK at 0 range 13 .. 13; - Reserved_14_31 at 0 range 14 .. 31; + for OTG_HS_HFNUM_Register use record + FRNUM at 0 range 0 .. 15; + FTREM at 0 range 16 .. 31; end record; - ------------------------------- - -- OTG_HS_DIEPTSIZ0_Register -- - ------------------------------- + subtype OTG_HS_HPTXSTS_PTXFSAVL_Field is STM32F40x.UInt16; + subtype OTG_HS_HPTXSTS_PTXQSAV_Field is STM32F40x.Byte; + subtype OTG_HS_HPTXSTS_PTXQTOP_Field is STM32F40x.Byte; + + -- OTG_HS_Host periodic transmit FIFO/queue status register + type OTG_HS_HPTXSTS_Register is record + -- Periodic transmit data FIFO space available + PTXFSAVL : OTG_HS_HPTXSTS_PTXFSAVL_Field := 16#100#; + -- Read-only. Periodic transmit request queue space available + PTXQSAV : OTG_HS_HPTXSTS_PTXQSAV_Field := 16#8#; + -- Read-only. Top of the periodic transmit request queue + PTXQTOP : OTG_HS_HPTXSTS_PTXQTOP_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for OTG_HS_HPTXSTS_Register use record + PTXFSAVL at 0 range 0 .. 15; + PTXQSAV at 0 range 16 .. 23; + PTXQTOP at 0 range 24 .. 31; + end record; - subtype OTG_HS_DIEPTSIZ0_XFRSIZ_Field is STM32F40x.UInt7; - subtype OTG_HS_DIEPTSIZ0_PKTCNT_Field is STM32F40x.UInt2; + subtype OTG_HS_HAINT_HAINT_Field is STM32F40x.UInt16; - -- OTG_HS device IN endpoint 0 transfer size register - type OTG_HS_DIEPTSIZ0_Register is record - -- Transfer size - XFRSIZ : OTG_HS_DIEPTSIZ0_XFRSIZ_Field := 16#0#; - -- unspecified - Reserved_7_18 : STM32F40x.UInt12 := 16#0#; - -- Packet count - PKTCNT : OTG_HS_DIEPTSIZ0_PKTCNT_Field := 16#0#; + -- OTG_HS Host all channels interrupt register + type OTG_HS_HAINT_Register is record + -- Read-only. Channel interrupts + HAINT : OTG_HS_HAINT_HAINT_Field; -- unspecified - Reserved_21_31 : STM32F40x.UInt11 := 16#0#; + Reserved_16_31 : STM32F40x.UInt16; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPTSIZ0_Register use record - XFRSIZ at 0 range 0 .. 6; - Reserved_7_18 at 0 range 7 .. 18; - PKTCNT at 0 range 19 .. 20; - Reserved_21_31 at 0 range 21 .. 31; + for OTG_HS_HAINT_Register use record + HAINT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_DTXFSTS_Register -- - ----------------------------- + subtype OTG_HS_HAINTMSK_HAINTM_Field is STM32F40x.UInt16; - subtype OTG_HS_DTXFSTS0_INEPTFSAV_Field is STM32F40x.Short; - - -- OTG_HS device IN endpoint transmit FIFO status register - type OTG_HS_DTXFSTS_Register is record - -- Read-only. IN endpoint TxFIFO space avail - INEPTFSAV : OTG_HS_DTXFSTS0_INEPTFSAV_Field := 16#0#; + -- OTG_HS host all channels interrupt mask register + type OTG_HS_HAINTMSK_Register is record + -- Channel interrupt mask + HAINTM : OTG_HS_HAINTMSK_HAINTM_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F40x.Short; + Reserved_16_31 : STM32F40x.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DTXFSTS_Register use record - INEPTFSAV at 0 range 0 .. 15; + for OTG_HS_HAINTMSK_Register use record + HAINTM at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------------------ - -- OTG_HS_DIEPTSIZ_Register -- - ------------------------------ - - subtype OTG_HS_DIEPTSIZ1_XFRSIZ_Field is STM32F40x.UInt19; - subtype OTG_HS_DIEPTSIZ1_PKTCNT_Field is STM32F40x.UInt10; - subtype OTG_HS_DIEPTSIZ1_MCNT_Field is STM32F40x.UInt2; + subtype OTG_HS_HPRT_PCSTS_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_PCDET_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_PENA_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_PENCHNG_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_POCA_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_POCCHNG_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_PRES_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_PSUSP_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_PRST_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_PLSTS_Field is STM32F40x.UInt2; + subtype OTG_HS_HPRT_PPWR_Field is STM32F40x.Bit; + subtype OTG_HS_HPRT_PTCTL_Field is STM32F40x.UInt4; + subtype OTG_HS_HPRT_PSPD_Field is STM32F40x.UInt2; - -- OTG_HS device endpoint transfer size register - type OTG_HS_DIEPTSIZ_Register is record - -- Transfer size - XFRSIZ : OTG_HS_DIEPTSIZ1_XFRSIZ_Field := 16#0#; - -- Packet count - PKTCNT : OTG_HS_DIEPTSIZ1_PKTCNT_Field := 16#0#; - -- Multi count - MCNT : OTG_HS_DIEPTSIZ1_MCNT_Field := 16#0#; + -- OTG_HS host port control and status register + type OTG_HS_HPRT_Register is record + -- Read-only. Port connect status + PCSTS : OTG_HS_HPRT_PCSTS_Field := 16#0#; + -- Port connect detected + PCDET : OTG_HS_HPRT_PCDET_Field := 16#0#; + -- Port enable + PENA : OTG_HS_HPRT_PENA_Field := 16#0#; + -- Port enable/disable change + PENCHNG : OTG_HS_HPRT_PENCHNG_Field := 16#0#; + -- Read-only. Port overcurrent active + POCA : OTG_HS_HPRT_POCA_Field := 16#0#; + -- Port overcurrent change + POCCHNG : OTG_HS_HPRT_POCCHNG_Field := 16#0#; + -- Port resume + PRES : OTG_HS_HPRT_PRES_Field := 16#0#; + -- Port suspend + PSUSP : OTG_HS_HPRT_PSUSP_Field := 16#0#; + -- Port reset + PRST : OTG_HS_HPRT_PRST_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F40x.Bit := 16#0#; + Reserved_9_9 : STM32F40x.Bit := 16#0#; + -- Read-only. Port line status + PLSTS : OTG_HS_HPRT_PLSTS_Field := 16#0#; + -- Port power + PPWR : OTG_HS_HPRT_PPWR_Field := 16#0#; + -- Port test control + PTCTL : OTG_HS_HPRT_PTCTL_Field := 16#0#; + -- Read-only. Port speed + PSPD : OTG_HS_HPRT_PSPD_Field := 16#0#; + -- unspecified + Reserved_19_31 : STM32F40x.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPTSIZ_Register use record - XFRSIZ at 0 range 0 .. 18; - PKTCNT at 0 range 19 .. 28; - MCNT at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for OTG_HS_HPRT_Register use record + PCSTS at 0 range 0 .. 0; + PCDET at 0 range 1 .. 1; + PENA at 0 range 2 .. 2; + PENCHNG at 0 range 3 .. 3; + POCA at 0 range 4 .. 4; + POCCHNG at 0 range 5 .. 5; + PRES at 0 range 6 .. 6; + PSUSP at 0 range 7 .. 7; + PRST at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PLSTS at 0 range 10 .. 11; + PPWR at 0 range 12 .. 12; + PTCTL at 0 range 13 .. 16; + PSPD at 0 range 17 .. 18; + Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------------------ - -- OTG_HS_DOEPCTL0_Register -- - ------------------------------ - - subtype OTG_HS_DOEPCTL0_MPSIZ_Field is STM32F40x.UInt2; - subtype OTG_HS_DOEPCTL0_USBAEP_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL0_NAKSTS_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL0_EPTYP_Field is STM32F40x.UInt2; - subtype OTG_HS_DOEPCTL0_SNPM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL0_Stall_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL0_CNAK_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL0_SNAK_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL0_EPDIS_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL0_EPENA_Field is STM32F40x.Bit; + subtype OTG_HS_HCCHAR_MPSIZ_Field is STM32F40x.UInt11; + subtype OTG_HS_HCCHAR_EPNUM_Field is STM32F40x.UInt4; + subtype OTG_HS_HCCHAR_EPDIR_Field is STM32F40x.Bit; + subtype OTG_HS_HCCHAR_LSDEV_Field is STM32F40x.Bit; + subtype OTG_HS_HCCHAR_EPTYP_Field is STM32F40x.UInt2; + subtype OTG_HS_HCCHAR_MC_Field is STM32F40x.UInt2; + subtype OTG_HS_HCCHAR_DAD_Field is STM32F40x.UInt7; + subtype OTG_HS_HCCHAR_ODDFRM_Field is STM32F40x.Bit; + subtype OTG_HS_HCCHAR_CHDIS_Field is STM32F40x.Bit; + subtype OTG_HS_HCCHAR_CHENA_Field is STM32F40x.Bit; - -- OTG_HS device control OUT endpoint 0 control register - type OTG_HS_DOEPCTL0_Register is record - -- Read-only. Maximum packet size - MPSIZ : OTG_HS_DOEPCTL0_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_2_14 : STM32F40x.UInt13 := 16#0#; - -- Read-only. USB active endpoint - USBAEP : OTG_HS_DOEPCTL0_USBAEP_Field := 16#1#; + -- OTG_HS host channel-0 characteristics register + type OTG_HS_HCCHAR_Register is record + -- Maximum packet size + MPSIZ : OTG_HS_HCCHAR_MPSIZ_Field := 16#0#; + -- Endpoint number + EPNUM : OTG_HS_HCCHAR_EPNUM_Field := 16#0#; + -- Endpoint direction + EPDIR : OTG_HS_HCCHAR_EPDIR_Field := 16#0#; -- unspecified Reserved_16_16 : STM32F40x.Bit := 16#0#; - -- Read-only. NAK status - NAKSTS : OTG_HS_DOEPCTL0_NAKSTS_Field := 16#0#; - -- Read-only. Endpoint type - EPTYP : OTG_HS_DOEPCTL0_EPTYP_Field := 16#0#; - -- Snoop mode - SNPM : OTG_HS_DOEPCTL0_SNPM_Field := 16#0#; - -- STALL handshake - Stall : OTG_HS_DOEPCTL0_Stall_Field := 16#0#; - -- unspecified - Reserved_22_25 : STM32F40x.UInt4 := 16#0#; - -- Write-only. Clear NAK - CNAK : OTG_HS_DOEPCTL0_CNAK_Field := 16#0#; - -- Write-only. Set NAK - SNAK : OTG_HS_DOEPCTL0_SNAK_Field := 16#0#; - -- unspecified - Reserved_28_29 : STM32F40x.UInt2 := 16#0#; - -- Read-only. Endpoint disable - EPDIS : OTG_HS_DOEPCTL0_EPDIS_Field := 16#0#; - -- Write-only. Endpoint enable - EPENA : OTG_HS_DOEPCTL0_EPENA_Field := 16#0#; + -- Low-speed device + LSDEV : OTG_HS_HCCHAR_LSDEV_Field := 16#0#; + -- Endpoint type + EPTYP : OTG_HS_HCCHAR_EPTYP_Field := 16#0#; + -- Multi Count (MC) / Error Count (EC) + MC : OTG_HS_HCCHAR_MC_Field := 16#0#; + -- Device address + DAD : OTG_HS_HCCHAR_DAD_Field := 16#0#; + -- Odd frame + ODDFRM : OTG_HS_HCCHAR_ODDFRM_Field := 16#0#; + -- Channel disable + CHDIS : OTG_HS_HCCHAR_CHDIS_Field := 16#0#; + -- Channel enable + CHENA : OTG_HS_HCCHAR_CHENA_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPCTL0_Register use record - MPSIZ at 0 range 0 .. 1; - Reserved_2_14 at 0 range 2 .. 14; - USBAEP at 0 range 15 .. 15; + for OTG_HS_HCCHAR_Register use record + MPSIZ at 0 range 0 .. 10; + EPNUM at 0 range 11 .. 14; + EPDIR at 0 range 15 .. 15; Reserved_16_16 at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; + LSDEV at 0 range 17 .. 17; EPTYP at 0 range 18 .. 19; - SNPM at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - Reserved_22_25 at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - Reserved_28_29 at 0 range 28 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + MC at 0 range 20 .. 21; + DAD at 0 range 22 .. 28; + ODDFRM at 0 range 29 .. 29; + CHDIS at 0 range 30 .. 30; + CHENA at 0 range 31 .. 31; end record; - ----------------------------- - -- OTG_HS_DOEPINT_Register -- - ----------------------------- + subtype OTG_HS_HCSPLT_PRTADDR_Field is STM32F40x.UInt7; + subtype OTG_HS_HCSPLT_HUBADDR_Field is STM32F40x.UInt7; + subtype OTG_HS_HCSPLT_XACTPOS_Field is STM32F40x.UInt2; + subtype OTG_HS_HCSPLT_COMPLSPLT_Field is STM32F40x.Bit; + subtype OTG_HS_HCSPLT_SPLITEN_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPINT0_XFRC_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPINT0_EPDISD_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPINT0_STUP_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPINT0_OTEPDIS_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPINT0_B2BSTUP_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPINT0_NYET_Field is STM32F40x.Bit; - - -- OTG_HS device endpoint-0 interrupt register - type OTG_HS_DOEPINT_Register is record - -- Transfer completed interrupt - XFRC : OTG_HS_DOEPINT0_XFRC_Field := 16#0#; - -- Endpoint disabled interrupt - EPDISD : OTG_HS_DOEPINT0_EPDISD_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F40x.Bit := 16#0#; - -- SETUP phase done - STUP : OTG_HS_DOEPINT0_STUP_Field := 16#0#; - -- OUT token received when endpoint disabled - OTEPDIS : OTG_HS_DOEPINT0_OTEPDIS_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F40x.Bit := 16#0#; - -- Back-to-back SETUP packets received - B2BSTUP : OTG_HS_DOEPINT0_B2BSTUP_Field := 16#0#; - -- unspecified - Reserved_7_13 : STM32F40x.UInt7 := 16#1#; - -- NYET interrupt - NYET : OTG_HS_DOEPINT0_NYET_Field := 16#0#; + -- OTG_HS host channel-0 split control register + type OTG_HS_HCSPLT_Register is record + -- Port address + PRTADDR : OTG_HS_HCSPLT_PRTADDR_Field := 16#0#; + -- Hub address + HUBADDR : OTG_HS_HCSPLT_HUBADDR_Field := 16#0#; + -- XACTPOS + XACTPOS : OTG_HS_HCSPLT_XACTPOS_Field := 16#0#; + -- Do complete split + COMPLSPLT : OTG_HS_HCSPLT_COMPLSPLT_Field := 16#0#; -- unspecified - Reserved_15_31 : STM32F40x.UInt17 := 16#0#; + Reserved_17_30 : STM32F40x.UInt14 := 16#0#; + -- Split enable + SPLITEN : OTG_HS_HCSPLT_SPLITEN_Field := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPINT_Register use record - XFRC at 0 range 0 .. 0; - EPDISD at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STUP at 0 range 3 .. 3; - OTEPDIS at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - B2BSTUP at 0 range 6 .. 6; - Reserved_7_13 at 0 range 7 .. 13; - NYET at 0 range 14 .. 14; - Reserved_15_31 at 0 range 15 .. 31; + for OTG_HS_HCSPLT_Register use record + PRTADDR at 0 range 0 .. 6; + HUBADDR at 0 range 7 .. 13; + XACTPOS at 0 range 14 .. 15; + COMPLSPLT at 0 range 16 .. 16; + Reserved_17_30 at 0 range 17 .. 30; + SPLITEN at 0 range 31 .. 31; end record; - ------------------------------- - -- OTG_HS_DOEPTSIZ0_Register -- - ------------------------------- + subtype OTG_HS_HCINT_XFRC_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_CHH_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_AHBERR_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_STALL_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_NAK_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_ACK_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_NYET_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_TXERR_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_BBERR_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_FRMOR_Field is STM32F40x.Bit; + subtype OTG_HS_HCINT_DTERR_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPTSIZ0_XFRSIZ_Field is STM32F40x.UInt7; - subtype OTG_HS_DOEPTSIZ0_PKTCNT_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPTSIZ0_STUPCNT_Field is STM32F40x.UInt2; - - -- OTG_HS device endpoint-1 transfer size register - type OTG_HS_DOEPTSIZ0_Register is record - -- Transfer size - XFRSIZ : OTG_HS_DOEPTSIZ0_XFRSIZ_Field := 16#0#; - -- unspecified - Reserved_7_18 : STM32F40x.UInt12 := 16#0#; - -- Packet count - PKTCNT : OTG_HS_DOEPTSIZ0_PKTCNT_Field := 16#0#; - -- unspecified - Reserved_20_28 : STM32F40x.UInt9 := 16#0#; - -- SETUP packet count - STUPCNT : OTG_HS_DOEPTSIZ0_STUPCNT_Field := 16#0#; + -- OTG_HS host channel-11 interrupt register + type OTG_HS_HCINT_Register is record + -- Transfer completed + XFRC : OTG_HS_HCINT_XFRC_Field := 16#0#; + -- Channel halted + CHH : OTG_HS_HCINT_CHH_Field := 16#0#; + -- AHB error + AHBERR : OTG_HS_HCINT_AHBERR_Field := 16#0#; + -- STALL response received interrupt + STALL : OTG_HS_HCINT_STALL_Field := 16#0#; + -- NAK response received interrupt + NAK : OTG_HS_HCINT_NAK_Field := 16#0#; + -- ACK response received/transmitted interrupt + ACK : OTG_HS_HCINT_ACK_Field := 16#0#; + -- Response received interrupt + NYET : OTG_HS_HCINT_NYET_Field := 16#0#; + -- Transaction error + TXERR : OTG_HS_HCINT_TXERR_Field := 16#0#; + -- Babble error + BBERR : OTG_HS_HCINT_BBERR_Field := 16#0#; + -- Frame overrun + FRMOR : OTG_HS_HCINT_FRMOR_Field := 16#0#; + -- Data toggle error + DTERR : OTG_HS_HCINT_DTERR_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F40x.Bit := 16#0#; + Reserved_11_31 : STM32F40x.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPTSIZ0_Register use record - XFRSIZ at 0 range 0 .. 6; - Reserved_7_18 at 0 range 7 .. 18; - PKTCNT at 0 range 19 .. 19; - Reserved_20_28 at 0 range 20 .. 28; - STUPCNT at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for OTG_HS_HCINT_Register use record + XFRC at 0 range 0 .. 0; + CHH at 0 range 1 .. 1; + AHBERR at 0 range 2 .. 2; + STALL at 0 range 3 .. 3; + NAK at 0 range 4 .. 4; + ACK at 0 range 5 .. 5; + NYET at 0 range 6 .. 6; + TXERR at 0 range 7 .. 7; + BBERR at 0 range 8 .. 8; + FRMOR at 0 range 9 .. 9; + DTERR at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------------- - -- OTG_HS_DOEPCTL_Register -- - ----------------------------- - - subtype OTG_HS_DOEPCTL1_MPSIZ_Field is STM32F40x.UInt11; - subtype OTG_HS_DOEPCTL1_USBAEP_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_EONUM_DPID_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_NAKSTS_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_EPTYP_Field is STM32F40x.UInt2; - subtype OTG_HS_DOEPCTL1_SNPM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_Stall_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_CNAK_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_SNAK_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_SD0PID_SEVNFRM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_SODDFRM_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_EPDIS_Field is STM32F40x.Bit; - subtype OTG_HS_DOEPCTL1_EPENA_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_XFRCM_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_CHHM_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_AHBERR_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_STALLM_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_NAKM_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_ACKM_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_NYET_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_TXERRM_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_BBERRM_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_FRMORM_Field is STM32F40x.Bit; + subtype OTG_HS_HCINTMSK_DTERRM_Field is STM32F40x.Bit; - -- OTG device endpoint-1 control register - type OTG_HS_DOEPCTL_Register is record - -- Maximum packet size - MPSIZ : OTG_HS_DOEPCTL1_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_11_14 : STM32F40x.UInt4 := 16#0#; - -- USB active endpoint - USBAEP : OTG_HS_DOEPCTL1_USBAEP_Field := 16#0#; - -- Read-only. Even odd frame/Endpoint data PID - EONUM_DPID : OTG_HS_DOEPCTL1_EONUM_DPID_Field := 16#0#; - -- Read-only. NAK status - NAKSTS : OTG_HS_DOEPCTL1_NAKSTS_Field := 16#0#; - -- Endpoint type - EPTYP : OTG_HS_DOEPCTL1_EPTYP_Field := 16#0#; - -- Snoop mode - SNPM : OTG_HS_DOEPCTL1_SNPM_Field := 16#0#; - -- STALL handshake - Stall : OTG_HS_DOEPCTL1_Stall_Field := 16#0#; + -- OTG_HS host channel-11 interrupt mask register + type OTG_HS_HCINTMSK_Register is record + -- Transfer completed mask + XFRCM : OTG_HS_HCINTMSK_XFRCM_Field := 16#0#; + -- Channel halted mask + CHHM : OTG_HS_HCINTMSK_CHHM_Field := 16#0#; + -- AHB error + AHBERR : OTG_HS_HCINTMSK_AHBERR_Field := 16#0#; + -- STALL response received interrupt mask + STALLM : OTG_HS_HCINTMSK_STALLM_Field := 16#0#; + -- NAK response received interrupt mask + NAKM : OTG_HS_HCINTMSK_NAKM_Field := 16#0#; + -- ACK response received/transmitted interrupt mask + ACKM : OTG_HS_HCINTMSK_ACKM_Field := 16#0#; + -- response received interrupt mask + NYET : OTG_HS_HCINTMSK_NYET_Field := 16#0#; + -- Transaction error mask + TXERRM : OTG_HS_HCINTMSK_TXERRM_Field := 16#0#; + -- Babble error mask + BBERRM : OTG_HS_HCINTMSK_BBERRM_Field := 16#0#; + -- Frame overrun mask + FRMORM : OTG_HS_HCINTMSK_FRMORM_Field := 16#0#; + -- Data toggle error mask + DTERRM : OTG_HS_HCINTMSK_DTERRM_Field := 16#0#; -- unspecified - Reserved_22_25 : STM32F40x.UInt4 := 16#0#; - -- Write-only. Clear NAK - CNAK : OTG_HS_DOEPCTL1_CNAK_Field := 16#0#; - -- Write-only. Set NAK - SNAK : OTG_HS_DOEPCTL1_SNAK_Field := 16#0#; - -- Write-only. Set DATA0 PID/Set even frame - SD0PID_SEVNFRM : OTG_HS_DOEPCTL1_SD0PID_SEVNFRM_Field := 16#0#; - -- Write-only. Set odd frame - SODDFRM : OTG_HS_DOEPCTL1_SODDFRM_Field := 16#0#; - -- Endpoint disable - EPDIS : OTG_HS_DOEPCTL1_EPDIS_Field := 16#0#; - -- Endpoint enable - EPENA : OTG_HS_DOEPCTL1_EPENA_Field := 16#0#; + Reserved_11_31 : STM32F40x.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPCTL_Register use record - MPSIZ at 0 range 0 .. 10; - Reserved_11_14 at 0 range 11 .. 14; - USBAEP at 0 range 15 .. 15; - EONUM_DPID at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - SNPM at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - Reserved_22_25 at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - SD0PID_SEVNFRM at 0 range 28 .. 28; - SODDFRM at 0 range 29 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for OTG_HS_HCINTMSK_Register use record + XFRCM at 0 range 0 .. 0; + CHHM at 0 range 1 .. 1; + AHBERR at 0 range 2 .. 2; + STALLM at 0 range 3 .. 3; + NAKM at 0 range 4 .. 4; + ACKM at 0 range 5 .. 5; + NYET at 0 range 6 .. 6; + TXERRM at 0 range 7 .. 7; + BBERRM at 0 range 8 .. 8; + FRMORM at 0 range 9 .. 9; + DTERRM at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------------------ - -- OTG_HS_DOEPTSIZ_Register -- - ------------------------------ + subtype OTG_HS_HCTSIZ_XFRSIZ_Field is STM32F40x.UInt19; + subtype OTG_HS_HCTSIZ_PKTCNT_Field is STM32F40x.UInt10; + subtype OTG_HS_HCTSIZ_DPID_Field is STM32F40x.UInt2; - subtype OTG_HS_DOEPTSIZ1_XFRSIZ_Field is STM32F40x.UInt19; - subtype OTG_HS_DOEPTSIZ1_PKTCNT_Field is STM32F40x.UInt10; - subtype OTG_HS_DOEPTSIZ1_RXDPID_STUPCNT_Field is STM32F40x.UInt2; - - -- OTG_HS device endpoint-2 transfer size register - type OTG_HS_DOEPTSIZ_Register is record + -- OTG_HS host channel-11 transfer size register + type OTG_HS_HCTSIZ_Register is record -- Transfer size - XFRSIZ : OTG_HS_DOEPTSIZ1_XFRSIZ_Field := 16#0#; + XFRSIZ : OTG_HS_HCTSIZ_XFRSIZ_Field := 16#0#; -- Packet count - PKTCNT : OTG_HS_DOEPTSIZ1_PKTCNT_Field := 16#0#; - -- Received data PID/SETUP packet count - RXDPID_STUPCNT : OTG_HS_DOEPTSIZ1_RXDPID_STUPCNT_Field := 16#0#; + PKTCNT : OTG_HS_HCTSIZ_PKTCNT_Field := 16#0#; + -- Data PID + DPID : OTG_HS_HCTSIZ_DPID_Field := 16#0#; -- unspecified Reserved_31_31 : STM32F40x.Bit := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPTSIZ_Register use record + for OTG_HS_HCTSIZ_Register use record XFRSIZ at 0 range 0 .. 18; PKTCNT at 0 range 19 .. 28; - RXDPID_STUPCNT at 0 range 29 .. 30; + DPID at 0 range 29 .. 30; Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------------- - -- OTG_HS_PCGCR_Register -- - --------------------------- - subtype OTG_HS_PCGCR_STPPCLK_Field is STM32F40x.Bit; subtype OTG_HS_PCGCR_GATEHCLK_Field is STM32F40x.Bit; subtype OTG_HS_PCGCR_PHYSUSP_Field is STM32F40x.Bit; @@ -2444,8 +2166,7 @@ package STM32F40x.USB_OTG_HS is -- unspecified Reserved_5_31 : STM32F40x.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OTG_HS_PCGCR_Register use record STPPCLK at 0 range 0 .. 0; @@ -2459,99 +2180,393 @@ package STM32F40x.USB_OTG_HS is -- Peripherals -- ----------------- - type OTG_HS_Mode is - ( - Host, - Peripheral); + -- USB on the go high speed + type OTG_HS_DEVICE_Peripheral is record + -- OTG_HS device configuration register + OTG_HS_DCFG : aliased OTG_HS_DCFG_Register; + pragma Volatile_Full_Access (OTG_HS_DCFG); + -- OTG_HS device control register + OTG_HS_DCTL : aliased OTG_HS_DCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DCTL); + -- OTG_HS device status register + OTG_HS_DSTS : aliased OTG_HS_DSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DSTS); + -- OTG_HS device IN endpoint common interrupt mask register + OTG_HS_DIEPMSK : aliased OTG_HS_DIEPMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPMSK); + -- OTG_HS device OUT endpoint common interrupt mask register + OTG_HS_DOEPMSK : aliased OTG_HS_DOEPMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPMSK); + -- OTG_HS device all endpoints interrupt register + OTG_HS_DAINT : aliased OTG_HS_DAINT_Register; + pragma Volatile_Full_Access (OTG_HS_DAINT); + -- OTG_HS all endpoints interrupt mask register + OTG_HS_DAINTMSK : aliased OTG_HS_DAINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DAINTMSK); + -- OTG_HS device VBUS discharge time register + OTG_HS_DVBUSDIS : aliased OTG_HS_DVBUSDIS_Register; + pragma Volatile_Full_Access (OTG_HS_DVBUSDIS); + -- OTG_HS device VBUS pulsing time register + OTG_HS_DVBUSPULSE : aliased OTG_HS_DVBUSPULSE_Register; + pragma Volatile_Full_Access (OTG_HS_DVBUSPULSE); + -- OTG_HS Device threshold control register + OTG_HS_DTHRCTL : aliased OTG_HS_DTHRCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DTHRCTL); + -- OTG_HS device IN endpoint FIFO empty interrupt mask register + OTG_HS_DIEPEMPMSK : aliased OTG_HS_DIEPEMPMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPEMPMSK); + -- OTG_HS device each endpoint interrupt register + OTG_HS_DEACHINT : aliased OTG_HS_DEACHINT_Register; + pragma Volatile_Full_Access (OTG_HS_DEACHINT); + -- OTG_HS device each endpoint interrupt register mask + OTG_HS_DEACHINTMSK : aliased OTG_HS_DEACHINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DEACHINTMSK); + -- OTG_HS device each in endpoint-1 interrupt register + OTG_HS_DIEPEACHMSK1 : aliased OTG_HS_DIEPEACHMSK1_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPEACHMSK1); + -- OTG_HS device each OUT endpoint-1 interrupt register + OTG_HS_DOEPEACHMSK1 : aliased OTG_HS_DOEPEACHMSK1_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPEACHMSK1); + -- OTG device endpoint-0 control register + OTG_HS_DIEPCTL0 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL0); + -- OTG device endpoint-0 interrupt register + OTG_HS_DIEPINT0 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT0); + -- OTG_HS device IN endpoint 0 transfer size register + OTG_HS_DIEPTSIZ0 : aliased OTG_HS_DIEPTSIZ0_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ0); + -- OTG_HS device endpoint-1 DMA address register + OTG_HS_DIEPDMA1 : aliased STM32F40x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS0 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS0); + -- OTG device endpoint-1 control register + OTG_HS_DIEPCTL1 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL1); + -- OTG device endpoint-1 interrupt register + OTG_HS_DIEPINT1 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT1); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ1 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ1); + -- OTG_HS device endpoint-2 DMA address register + OTG_HS_DIEPDMA2 : aliased STM32F40x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS1 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS1); + -- OTG device endpoint-2 control register + OTG_HS_DIEPCTL2 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL2); + -- OTG device endpoint-2 interrupt register + OTG_HS_DIEPINT2 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT2); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ2 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ2); + -- OTG_HS device endpoint-3 DMA address register + OTG_HS_DIEPDMA3 : aliased STM32F40x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS2 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS2); + -- OTG device endpoint-3 control register + OTG_HS_DIEPCTL3 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL3); + -- OTG device endpoint-3 interrupt register + OTG_HS_DIEPINT3 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT3); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ3 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ3); + -- OTG_HS device endpoint-4 DMA address register + OTG_HS_DIEPDMA4 : aliased STM32F40x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS3 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS3); + -- OTG device endpoint-4 control register + OTG_HS_DIEPCTL4 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL4); + -- OTG device endpoint-4 interrupt register + OTG_HS_DIEPINT4 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT4); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ4 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ4); + -- OTG_HS device endpoint-5 DMA address register + OTG_HS_DIEPDMA5 : aliased STM32F40x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS4 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS4); + -- OTG device endpoint-5 control register + OTG_HS_DIEPCTL5 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL5); + -- OTG device endpoint-5 interrupt register + OTG_HS_DIEPINT5 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT5); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ5 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ5); + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS5 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS5); + -- OTG device endpoint-6 control register + OTG_HS_DIEPCTL6 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL6); + -- OTG device endpoint-6 interrupt register + OTG_HS_DIEPINT6 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT6); + -- OTG device endpoint-7 control register + OTG_HS_DIEPCTL7 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL7); + -- OTG device endpoint-7 interrupt register + OTG_HS_DIEPINT7 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT7); + -- OTG_HS device control OUT endpoint 0 control register + OTG_HS_DOEPCTL0 : aliased OTG_HS_DOEPCTL0_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPCTL0); + -- OTG_HS device endpoint-0 interrupt register + OTG_HS_DOEPINT0 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT0); + -- OTG_HS device endpoint-1 transfer size register + OTG_HS_DOEPTSIZ0 : aliased OTG_HS_DOEPTSIZ0_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ0); + -- OTG device endpoint-1 control register + OTG_HS_DOEPCTL1 : aliased OTG_HS_DOEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPCTL1); + -- OTG_HS device endpoint-1 interrupt register + OTG_HS_DOEPINT1 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT1); + -- OTG_HS device endpoint-2 transfer size register + OTG_HS_DOEPTSIZ1 : aliased OTG_HS_DOEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ1); + -- OTG device endpoint-2 control register + OTG_HS_DOEPCTL2 : aliased OTG_HS_DOEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPCTL2); + -- OTG_HS device endpoint-2 interrupt register + OTG_HS_DOEPINT2 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT2); + -- OTG_HS device endpoint-3 transfer size register + OTG_HS_DOEPTSIZ2 : aliased OTG_HS_DOEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ2); + -- OTG device endpoint-3 control register + OTG_HS_DOEPCTL3 : aliased OTG_HS_DOEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPCTL3); + -- OTG_HS device endpoint-3 interrupt register + OTG_HS_DOEPINT3 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT3); + -- OTG_HS device endpoint-4 transfer size register + OTG_HS_DOEPTSIZ3 : aliased OTG_HS_DOEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ3); + -- OTG_HS device endpoint-4 interrupt register + OTG_HS_DOEPINT4 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT4); + -- OTG_HS device endpoint-5 transfer size register + OTG_HS_DOEPTSIZ4 : aliased OTG_HS_DOEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ4); + -- OTG_HS device endpoint-5 interrupt register + OTG_HS_DOEPINT5 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT5); + -- OTG_HS device endpoint-6 interrupt register + OTG_HS_DOEPINT6 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT6); + -- OTG_HS device endpoint-7 interrupt register + OTG_HS_DOEPINT7 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT7); + end record + with Volatile; + + for OTG_HS_DEVICE_Peripheral use record + OTG_HS_DCFG at 16#0# range 0 .. 31; + OTG_HS_DCTL at 16#4# range 0 .. 31; + OTG_HS_DSTS at 16#8# range 0 .. 31; + OTG_HS_DIEPMSK at 16#10# range 0 .. 31; + OTG_HS_DOEPMSK at 16#14# range 0 .. 31; + OTG_HS_DAINT at 16#18# range 0 .. 31; + OTG_HS_DAINTMSK at 16#1C# range 0 .. 31; + OTG_HS_DVBUSDIS at 16#28# range 0 .. 31; + OTG_HS_DVBUSPULSE at 16#2C# range 0 .. 31; + OTG_HS_DTHRCTL at 16#30# range 0 .. 31; + OTG_HS_DIEPEMPMSK at 16#34# range 0 .. 31; + OTG_HS_DEACHINT at 16#38# range 0 .. 31; + OTG_HS_DEACHINTMSK at 16#3C# range 0 .. 31; + OTG_HS_DIEPEACHMSK1 at 16#40# range 0 .. 31; + OTG_HS_DOEPEACHMSK1 at 16#80# range 0 .. 31; + OTG_HS_DIEPCTL0 at 16#100# range 0 .. 31; + OTG_HS_DIEPINT0 at 16#108# range 0 .. 31; + OTG_HS_DIEPTSIZ0 at 16#110# range 0 .. 31; + OTG_HS_DIEPDMA1 at 16#114# range 0 .. 31; + OTG_HS_DTXFSTS0 at 16#118# range 0 .. 31; + OTG_HS_DIEPCTL1 at 16#120# range 0 .. 31; + OTG_HS_DIEPINT1 at 16#128# range 0 .. 31; + OTG_HS_DIEPTSIZ1 at 16#130# range 0 .. 31; + OTG_HS_DIEPDMA2 at 16#134# range 0 .. 31; + OTG_HS_DTXFSTS1 at 16#138# range 0 .. 31; + OTG_HS_DIEPCTL2 at 16#140# range 0 .. 31; + OTG_HS_DIEPINT2 at 16#148# range 0 .. 31; + OTG_HS_DIEPTSIZ2 at 16#150# range 0 .. 31; + OTG_HS_DIEPDMA3 at 16#154# range 0 .. 31; + OTG_HS_DTXFSTS2 at 16#158# range 0 .. 31; + OTG_HS_DIEPCTL3 at 16#160# range 0 .. 31; + OTG_HS_DIEPINT3 at 16#168# range 0 .. 31; + OTG_HS_DIEPTSIZ3 at 16#170# range 0 .. 31; + OTG_HS_DIEPDMA4 at 16#174# range 0 .. 31; + OTG_HS_DTXFSTS3 at 16#178# range 0 .. 31; + OTG_HS_DIEPCTL4 at 16#180# range 0 .. 31; + OTG_HS_DIEPINT4 at 16#188# range 0 .. 31; + OTG_HS_DIEPTSIZ4 at 16#190# range 0 .. 31; + OTG_HS_DIEPDMA5 at 16#194# range 0 .. 31; + OTG_HS_DTXFSTS4 at 16#198# range 0 .. 31; + OTG_HS_DIEPCTL5 at 16#1A0# range 0 .. 31; + OTG_HS_DIEPINT5 at 16#1A8# range 0 .. 31; + OTG_HS_DIEPTSIZ5 at 16#1B0# range 0 .. 31; + OTG_HS_DTXFSTS5 at 16#1B8# range 0 .. 31; + OTG_HS_DIEPCTL6 at 16#1C0# range 0 .. 31; + OTG_HS_DIEPINT6 at 16#1C8# range 0 .. 31; + OTG_HS_DIEPCTL7 at 16#1E0# range 0 .. 31; + OTG_HS_DIEPINT7 at 16#1E8# range 0 .. 31; + OTG_HS_DOEPCTL0 at 16#300# range 0 .. 31; + OTG_HS_DOEPINT0 at 16#308# range 0 .. 31; + OTG_HS_DOEPTSIZ0 at 16#310# range 0 .. 31; + OTG_HS_DOEPCTL1 at 16#320# range 0 .. 31; + OTG_HS_DOEPINT1 at 16#328# range 0 .. 31; + OTG_HS_DOEPTSIZ1 at 16#330# range 0 .. 31; + OTG_HS_DOEPCTL2 at 16#340# range 0 .. 31; + OTG_HS_DOEPINT2 at 16#348# range 0 .. 31; + OTG_HS_DOEPTSIZ2 at 16#350# range 0 .. 31; + OTG_HS_DOEPCTL3 at 16#360# range 0 .. 31; + OTG_HS_DOEPINT3 at 16#368# range 0 .. 31; + OTG_HS_DOEPTSIZ3 at 16#370# range 0 .. 31; + OTG_HS_DOEPINT4 at 16#388# range 0 .. 31; + OTG_HS_DOEPTSIZ4 at 16#390# range 0 .. 31; + OTG_HS_DOEPINT5 at 16#3A8# range 0 .. 31; + OTG_HS_DOEPINT6 at 16#3C8# range 0 .. 31; + OTG_HS_DOEPINT7 at 16#3E8# range 0 .. 31; + end record; + + -- USB on the go high speed + OTG_HS_DEVICE_Periph : aliased OTG_HS_DEVICE_Peripheral + with Import, Address => OTG_HS_DEVICE_Base; + + type OTG_HS_GLOBAL_Disc is + (Host, + Peripheral, + Gnptxfsiz_Host, + Tx0Fsiz_Peripheral); -- USB on the go high speed type OTG_HS_GLOBAL_Peripheral - (Mode : OTG_HS_Mode := Host) + (Discriminent : OTG_HS_GLOBAL_Disc := Host) is record -- OTG_HS control and status register - OTG_HS_GOTGCTL : OTG_HS_GOTGCTL_Register; + OTG_HS_GOTGCTL : aliased OTG_HS_GOTGCTL_Register; + pragma Volatile_Full_Access (OTG_HS_GOTGCTL); -- OTG_HS interrupt register - OTG_HS_GOTGINT : OTG_HS_GOTGINT_Register; + OTG_HS_GOTGINT : aliased OTG_HS_GOTGINT_Register; + pragma Volatile_Full_Access (OTG_HS_GOTGINT); -- OTG_HS AHB configuration register - OTG_HS_GAHBCFG : OTG_HS_GAHBCFG_Register; + OTG_HS_GAHBCFG : aliased OTG_HS_GAHBCFG_Register; + pragma Volatile_Full_Access (OTG_HS_GAHBCFG); -- OTG_HS USB configuration register - OTG_HS_GUSBCFG : OTG_HS_GUSBCFG_Register; + OTG_HS_GUSBCFG : aliased OTG_HS_GUSBCFG_Register; + pragma Volatile_Full_Access (OTG_HS_GUSBCFG); -- OTG_HS reset register - OTG_HS_GRSTCTL : OTG_HS_GRSTCTL_Register; + OTG_HS_GRSTCTL : aliased OTG_HS_GRSTCTL_Register; + pragma Volatile_Full_Access (OTG_HS_GRSTCTL); -- OTG_HS core interrupt register - OTG_HS_GINTSTS : OTG_HS_GINTSTS_Register; + OTG_HS_GINTSTS : aliased OTG_HS_GINTSTS_Register; + pragma Volatile_Full_Access (OTG_HS_GINTSTS); -- OTG_HS interrupt mask register - OTG_HS_GINTMSK : OTG_HS_GINTMSK_Register; + OTG_HS_GINTMSK : aliased OTG_HS_GINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_GINTMSK); -- OTG_HS Receive FIFO size register - OTG_HS_GRXFSIZ : OTG_HS_GRXFSIZ_Register; + OTG_HS_GRXFSIZ : aliased OTG_HS_GRXFSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_GRXFSIZ); -- OTG_HS nonperiodic transmit FIFO/queue status register - OTG_HS_GNPTXSTS : OTG_HS_GNPTXSTS_Register; + OTG_HS_GNPTXSTS : aliased OTG_HS_GNPTXSTS_Register; + pragma Volatile_Full_Access (OTG_HS_GNPTXSTS); -- OTG_HS general core configuration register - OTG_HS_GCCFG : OTG_HS_GCCFG_Register; + OTG_HS_GCCFG : aliased OTG_HS_GCCFG_Register; + pragma Volatile_Full_Access (OTG_HS_GCCFG); -- OTG_HS core ID register - OTG_HS_CID : STM32F40x.Word; + OTG_HS_CID : aliased STM32F40x.UInt32; -- OTG_HS Host periodic transmit FIFO size register - OTG_HS_HPTXFSIZ : OTG_HS_HPTXFSIZ_Register; + OTG_HS_HPTXFSIZ : aliased OTG_HS_HPTXFSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HPTXFSIZ); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF1 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF1 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF1); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF2 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF2 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF2); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF3 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF3 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF3); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF4 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF4 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF4); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF5 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF5 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF5); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF6 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF6 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF6); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF7 : OTG_HS_DIEPTXF_Register; - case Mode is + OTG_HS_DIEPTXF7 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF7); + case Discriminent is when Host => -- OTG_HS Receive status debug read register (host mode) - OTG_HS_GRXSTSR_Host : OTG_HS_GRXSTSR_Host_Register; + OTG_HS_GRXSTSR_Host : aliased OTG_HS_GRXSTSR_Host_Register; + pragma Volatile_Full_Access (OTG_HS_GRXSTSR_Host); -- OTG_HS status read and pop register (host mode) - OTG_HS_GRXSTSP_Host : OTG_HS_GRXSTSP_Host_Register; - -- OTG_HS nonperiodic transmit FIFO size register (host mode) - OTG_HS_GNPTXFSIZ_Host : OTG_HS_GNPTXFSIZ_Host_Register; + OTG_HS_GRXSTSP_Host : aliased OTG_HS_GRXSTSP_Host_Register; + pragma Volatile_Full_Access (OTG_HS_GRXSTSP_Host); when Peripheral => -- OTG_HS Receive status debug read register (peripheral mode -- mode) - OTG_HS_GRXSTSR_Peripheral : OTG_HS_GRXSTSR_Peripheral_Register; + OTG_HS_GRXSTSR_Peripheral : aliased OTG_HS_GRXSTSR_Peripheral_Register; + pragma Volatile_Full_Access (OTG_HS_GRXSTSR_Peripheral); -- OTG_HS status read and pop register (peripheral mode) - OTG_HS_GRXSTSP_Peripheral : OTG_HS_GRXSTSP_Peripheral_Register; + OTG_HS_GRXSTSP_Peripheral : aliased OTG_HS_GRXSTSP_Peripheral_Register; + pragma Volatile_Full_Access (OTG_HS_GRXSTSP_Peripheral); + when Gnptxfsiz_Host => + -- OTG_HS nonperiodic transmit FIFO size register (host mode) + OTG_HS_GNPTXFSIZ_Host : aliased OTG_HS_GNPTXFSIZ_Host_Register; + pragma Volatile_Full_Access (OTG_HS_GNPTXFSIZ_Host); + when Tx0Fsiz_Peripheral => -- Endpoint 0 transmit FIFO size (peripheral mode) - OTG_HS_TX0FSIZ_Peripheral : OTG_HS_TX0FSIZ_Peripheral_Register; + OTG_HS_TX0FSIZ_Peripheral : aliased OTG_HS_TX0FSIZ_Peripheral_Register; + pragma Volatile_Full_Access (OTG_HS_TX0FSIZ_Peripheral); end case; end record with Unchecked_Union, Volatile; for OTG_HS_GLOBAL_Peripheral use record - OTG_HS_GOTGCTL at 0 range 0 .. 31; - OTG_HS_GOTGINT at 4 range 0 .. 31; - OTG_HS_GAHBCFG at 8 range 0 .. 31; - OTG_HS_GUSBCFG at 12 range 0 .. 31; - OTG_HS_GRSTCTL at 16 range 0 .. 31; - OTG_HS_GINTSTS at 20 range 0 .. 31; - OTG_HS_GINTMSK at 24 range 0 .. 31; - OTG_HS_GRXFSIZ at 36 range 0 .. 31; - OTG_HS_GNPTXSTS at 44 range 0 .. 31; - OTG_HS_GCCFG at 56 range 0 .. 31; - OTG_HS_CID at 60 range 0 .. 31; - OTG_HS_HPTXFSIZ at 256 range 0 .. 31; - OTG_HS_DIEPTXF1 at 260 range 0 .. 31; - OTG_HS_DIEPTXF2 at 264 range 0 .. 31; - OTG_HS_DIEPTXF3 at 284 range 0 .. 31; - OTG_HS_DIEPTXF4 at 288 range 0 .. 31; - OTG_HS_DIEPTXF5 at 292 range 0 .. 31; - OTG_HS_DIEPTXF6 at 296 range 0 .. 31; - OTG_HS_DIEPTXF7 at 300 range 0 .. 31; - OTG_HS_GRXSTSR_Host at 28 range 0 .. 31; - OTG_HS_GRXSTSP_Host at 32 range 0 .. 31; - OTG_HS_GNPTXFSIZ_Host at 40 range 0 .. 31; - OTG_HS_GRXSTSR_Peripheral at 28 range 0 .. 31; - OTG_HS_GRXSTSP_Peripheral at 32 range 0 .. 31; - OTG_HS_TX0FSIZ_Peripheral at 40 range 0 .. 31; + OTG_HS_GOTGCTL at 16#0# range 0 .. 31; + OTG_HS_GOTGINT at 16#4# range 0 .. 31; + OTG_HS_GAHBCFG at 16#8# range 0 .. 31; + OTG_HS_GUSBCFG at 16#C# range 0 .. 31; + OTG_HS_GRSTCTL at 16#10# range 0 .. 31; + OTG_HS_GINTSTS at 16#14# range 0 .. 31; + OTG_HS_GINTMSK at 16#18# range 0 .. 31; + OTG_HS_GRXFSIZ at 16#24# range 0 .. 31; + OTG_HS_GNPTXSTS at 16#2C# range 0 .. 31; + OTG_HS_GCCFG at 16#38# range 0 .. 31; + OTG_HS_CID at 16#3C# range 0 .. 31; + OTG_HS_HPTXFSIZ at 16#100# range 0 .. 31; + OTG_HS_DIEPTXF1 at 16#104# range 0 .. 31; + OTG_HS_DIEPTXF2 at 16#108# range 0 .. 31; + OTG_HS_DIEPTXF3 at 16#11C# range 0 .. 31; + OTG_HS_DIEPTXF4 at 16#120# range 0 .. 31; + OTG_HS_DIEPTXF5 at 16#124# range 0 .. 31; + OTG_HS_DIEPTXF6 at 16#128# range 0 .. 31; + OTG_HS_DIEPTXF7 at 16#12C# range 0 .. 31; + OTG_HS_GRXSTSR_Host at 16#1C# range 0 .. 31; + OTG_HS_GRXSTSP_Host at 16#20# range 0 .. 31; + OTG_HS_GRXSTSR_Peripheral at 16#1C# range 0 .. 31; + OTG_HS_GRXSTSP_Peripheral at 16#20# range 0 .. 31; + OTG_HS_GNPTXFSIZ_Host at 16#28# range 0 .. 31; + OTG_HS_TX0FSIZ_Peripheral at 16#28# range 0 .. 31; end record; -- USB on the go high speed @@ -2561,463 +2576,324 @@ package STM32F40x.USB_OTG_HS is -- USB on the go high speed type OTG_HS_HOST_Peripheral is record -- OTG_HS host configuration register - OTG_HS_HCFG : OTG_HS_HCFG_Register; + OTG_HS_HCFG : aliased OTG_HS_HCFG_Register; + pragma Volatile_Full_Access (OTG_HS_HCFG); -- OTG_HS Host frame interval register - OTG_HS_HFIR : OTG_HS_HFIR_Register; + OTG_HS_HFIR : aliased OTG_HS_HFIR_Register; + pragma Volatile_Full_Access (OTG_HS_HFIR); -- OTG_HS host frame number/frame time remaining register - OTG_HS_HFNUM : OTG_HS_HFNUM_Register; + OTG_HS_HFNUM : aliased OTG_HS_HFNUM_Register; + pragma Volatile_Full_Access (OTG_HS_HFNUM); -- OTG_HS_Host periodic transmit FIFO/queue status register - OTG_HS_HPTXSTS : OTG_HS_HPTXSTS_Register; + OTG_HS_HPTXSTS : aliased OTG_HS_HPTXSTS_Register; + pragma Volatile_Full_Access (OTG_HS_HPTXSTS); -- OTG_HS Host all channels interrupt register - OTG_HS_HAINT : OTG_HS_HAINT_Register; + OTG_HS_HAINT : aliased OTG_HS_HAINT_Register; + pragma Volatile_Full_Access (OTG_HS_HAINT); -- OTG_HS host all channels interrupt mask register - OTG_HS_HAINTMSK : OTG_HS_HAINTMSK_Register; + OTG_HS_HAINTMSK : aliased OTG_HS_HAINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HAINTMSK); -- OTG_HS host port control and status register - OTG_HS_HPRT : OTG_HS_HPRT_Register; + OTG_HS_HPRT : aliased OTG_HS_HPRT_Register; + pragma Volatile_Full_Access (OTG_HS_HPRT); -- OTG_HS host channel-0 characteristics register - OTG_HS_HCCHAR0 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR0 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR0); -- OTG_HS host channel-0 split control register - OTG_HS_HCSPLT0 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT0 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT0); -- OTG_HS host channel-11 interrupt register - OTG_HS_HCINT0 : OTG_HS_HCINT_Register; + OTG_HS_HCINT0 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT0); -- OTG_HS host channel-11 interrupt mask register - OTG_HS_HCINTMSK0 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK0 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK0); -- OTG_HS host channel-11 transfer size register - OTG_HS_HCTSIZ0 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ0 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ0); -- OTG_HS host channel-0 DMA address register - OTG_HS_HCDMA0 : STM32F40x.Word; + OTG_HS_HCDMA0 : aliased STM32F40x.UInt32; -- OTG_HS host channel-1 characteristics register - OTG_HS_HCCHAR1 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR1 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR1); -- OTG_HS host channel-1 split control register - OTG_HS_HCSPLT1 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT1 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT1); -- OTG_HS host channel-1 interrupt register - OTG_HS_HCINT1 : OTG_HS_HCINT_Register; + OTG_HS_HCINT1 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT1); -- OTG_HS host channel-1 interrupt mask register - OTG_HS_HCINTMSK1 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK1 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK1); -- OTG_HS host channel-1 transfer size register - OTG_HS_HCTSIZ1 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ1 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ1); -- OTG_HS host channel-1 DMA address register - OTG_HS_HCDMA1 : STM32F40x.Word; + OTG_HS_HCDMA1 : aliased STM32F40x.UInt32; -- OTG_HS host channel-2 characteristics register - OTG_HS_HCCHAR2 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR2 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR2); -- OTG_HS host channel-2 split control register - OTG_HS_HCSPLT2 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT2 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT2); -- OTG_HS host channel-2 interrupt register - OTG_HS_HCINT2 : OTG_HS_HCINT_Register; + OTG_HS_HCINT2 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT2); -- OTG_HS host channel-2 interrupt mask register - OTG_HS_HCINTMSK2 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK2 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK2); -- OTG_HS host channel-2 transfer size register - OTG_HS_HCTSIZ2 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ2 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ2); -- OTG_HS host channel-2 DMA address register - OTG_HS_HCDMA2 : STM32F40x.Word; + OTG_HS_HCDMA2 : aliased STM32F40x.UInt32; -- OTG_HS host channel-3 characteristics register - OTG_HS_HCCHAR3 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR3 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR3); -- OTG_HS host channel-3 split control register - OTG_HS_HCSPLT3 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT3 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT3); -- OTG_HS host channel-3 interrupt register - OTG_HS_HCINT3 : OTG_HS_HCINT_Register; + OTG_HS_HCINT3 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT3); -- OTG_HS host channel-3 interrupt mask register - OTG_HS_HCINTMSK3 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK3 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK3); -- OTG_HS host channel-3 transfer size register - OTG_HS_HCTSIZ3 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ3 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ3); -- OTG_HS host channel-3 DMA address register - OTG_HS_HCDMA3 : STM32F40x.Word; + OTG_HS_HCDMA3 : aliased STM32F40x.UInt32; -- OTG_HS host channel-4 characteristics register - OTG_HS_HCCHAR4 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR4 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR4); -- OTG_HS host channel-4 split control register - OTG_HS_HCSPLT4 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT4 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT4); -- OTG_HS host channel-4 interrupt register - OTG_HS_HCINT4 : OTG_HS_HCINT_Register; + OTG_HS_HCINT4 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT4); -- OTG_HS host channel-4 interrupt mask register - OTG_HS_HCINTMSK4 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK4 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK4); -- OTG_HS host channel-4 transfer size register - OTG_HS_HCTSIZ4 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ4 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ4); -- OTG_HS host channel-4 DMA address register - OTG_HS_HCDMA4 : STM32F40x.Word; + OTG_HS_HCDMA4 : aliased STM32F40x.UInt32; -- OTG_HS host channel-5 characteristics register - OTG_HS_HCCHAR5 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR5 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR5); -- OTG_HS host channel-5 split control register - OTG_HS_HCSPLT5 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT5 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT5); -- OTG_HS host channel-5 interrupt register - OTG_HS_HCINT5 : OTG_HS_HCINT_Register; + OTG_HS_HCINT5 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT5); -- OTG_HS host channel-5 interrupt mask register - OTG_HS_HCINTMSK5 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK5 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK5); -- OTG_HS host channel-5 transfer size register - OTG_HS_HCTSIZ5 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ5 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ5); -- OTG_HS host channel-5 DMA address register - OTG_HS_HCDMA5 : STM32F40x.Word; + OTG_HS_HCDMA5 : aliased STM32F40x.UInt32; -- OTG_HS host channel-6 characteristics register - OTG_HS_HCCHAR6 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR6 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR6); -- OTG_HS host channel-6 split control register - OTG_HS_HCSPLT6 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT6 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT6); -- OTG_HS host channel-6 interrupt register - OTG_HS_HCINT6 : OTG_HS_HCINT_Register; + OTG_HS_HCINT6 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT6); -- OTG_HS host channel-6 interrupt mask register - OTG_HS_HCINTMSK6 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK6 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK6); -- OTG_HS host channel-6 transfer size register - OTG_HS_HCTSIZ6 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ6 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ6); -- OTG_HS host channel-6 DMA address register - OTG_HS_HCDMA6 : STM32F40x.Word; + OTG_HS_HCDMA6 : aliased STM32F40x.UInt32; -- OTG_HS host channel-7 characteristics register - OTG_HS_HCCHAR7 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR7 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR7); -- OTG_HS host channel-7 split control register - OTG_HS_HCSPLT7 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT7 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT7); -- OTG_HS host channel-7 interrupt register - OTG_HS_HCINT7 : OTG_HS_HCINT_Register; + OTG_HS_HCINT7 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT7); -- OTG_HS host channel-7 interrupt mask register - OTG_HS_HCINTMSK7 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK7 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK7); -- OTG_HS host channel-7 transfer size register - OTG_HS_HCTSIZ7 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ7 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ7); -- OTG_HS host channel-7 DMA address register - OTG_HS_HCDMA7 : STM32F40x.Word; + OTG_HS_HCDMA7 : aliased STM32F40x.UInt32; -- OTG_HS host channel-8 characteristics register - OTG_HS_HCCHAR8 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR8 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR8); -- OTG_HS host channel-8 split control register - OTG_HS_HCSPLT8 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT8 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT8); -- OTG_HS host channel-8 interrupt register - OTG_HS_HCINT8 : OTG_HS_HCINT_Register; + OTG_HS_HCINT8 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT8); -- OTG_HS host channel-8 interrupt mask register - OTG_HS_HCINTMSK8 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK8 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK8); -- OTG_HS host channel-8 transfer size register - OTG_HS_HCTSIZ8 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ8 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ8); -- OTG_HS host channel-8 DMA address register - OTG_HS_HCDMA8 : STM32F40x.Word; + OTG_HS_HCDMA8 : aliased STM32F40x.UInt32; -- OTG_HS host channel-9 characteristics register - OTG_HS_HCCHAR9 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR9 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR9); -- OTG_HS host channel-9 split control register - OTG_HS_HCSPLT9 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT9 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT9); -- OTG_HS host channel-9 interrupt register - OTG_HS_HCINT9 : OTG_HS_HCINT_Register; + OTG_HS_HCINT9 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT9); -- OTG_HS host channel-9 interrupt mask register - OTG_HS_HCINTMSK9 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK9 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK9); -- OTG_HS host channel-9 transfer size register - OTG_HS_HCTSIZ9 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ9 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ9); -- OTG_HS host channel-9 DMA address register - OTG_HS_HCDMA9 : STM32F40x.Word; + OTG_HS_HCDMA9 : aliased STM32F40x.UInt32; -- OTG_HS host channel-10 characteristics register - OTG_HS_HCCHAR10 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR10 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR10); -- OTG_HS host channel-10 split control register - OTG_HS_HCSPLT10 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT10 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT10); -- OTG_HS host channel-10 interrupt register - OTG_HS_HCINT10 : OTG_HS_HCINT_Register; + OTG_HS_HCINT10 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT10); -- OTG_HS host channel-10 interrupt mask register - OTG_HS_HCINTMSK10 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK10 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK10); -- OTG_HS host channel-10 transfer size register - OTG_HS_HCTSIZ10 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ10 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ10); -- OTG_HS host channel-10 DMA address register - OTG_HS_HCDMA10 : STM32F40x.Word; + OTG_HS_HCDMA10 : aliased STM32F40x.UInt32; -- OTG_HS host channel-11 characteristics register - OTG_HS_HCCHAR11 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR11 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR11); -- OTG_HS host channel-11 split control register - OTG_HS_HCSPLT11 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT11 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT11); -- OTG_HS host channel-11 interrupt register - OTG_HS_HCINT11 : OTG_HS_HCINT_Register; + OTG_HS_HCINT11 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT11); -- OTG_HS host channel-11 interrupt mask register - OTG_HS_HCINTMSK11 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK11 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK11); -- OTG_HS host channel-11 transfer size register - OTG_HS_HCTSIZ11 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ11 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ11); -- OTG_HS host channel-11 DMA address register - OTG_HS_HCDMA11 : STM32F40x.Word; + OTG_HS_HCDMA11 : aliased STM32F40x.UInt32; end record with Volatile; for OTG_HS_HOST_Peripheral use record - OTG_HS_HCFG at 0 range 0 .. 31; - OTG_HS_HFIR at 4 range 0 .. 31; - OTG_HS_HFNUM at 8 range 0 .. 31; - OTG_HS_HPTXSTS at 16 range 0 .. 31; - OTG_HS_HAINT at 20 range 0 .. 31; - OTG_HS_HAINTMSK at 24 range 0 .. 31; - OTG_HS_HPRT at 64 range 0 .. 31; - OTG_HS_HCCHAR0 at 256 range 0 .. 31; - OTG_HS_HCSPLT0 at 260 range 0 .. 31; - OTG_HS_HCINT0 at 264 range 0 .. 31; - OTG_HS_HCINTMSK0 at 268 range 0 .. 31; - OTG_HS_HCTSIZ0 at 272 range 0 .. 31; - OTG_HS_HCDMA0 at 276 range 0 .. 31; - OTG_HS_HCCHAR1 at 288 range 0 .. 31; - OTG_HS_HCSPLT1 at 292 range 0 .. 31; - OTG_HS_HCINT1 at 296 range 0 .. 31; - OTG_HS_HCINTMSK1 at 300 range 0 .. 31; - OTG_HS_HCTSIZ1 at 304 range 0 .. 31; - OTG_HS_HCDMA1 at 308 range 0 .. 31; - OTG_HS_HCCHAR2 at 320 range 0 .. 31; - OTG_HS_HCSPLT2 at 324 range 0 .. 31; - OTG_HS_HCINT2 at 328 range 0 .. 31; - OTG_HS_HCINTMSK2 at 332 range 0 .. 31; - OTG_HS_HCTSIZ2 at 336 range 0 .. 31; - OTG_HS_HCDMA2 at 340 range 0 .. 31; - OTG_HS_HCCHAR3 at 352 range 0 .. 31; - OTG_HS_HCSPLT3 at 356 range 0 .. 31; - OTG_HS_HCINT3 at 360 range 0 .. 31; - OTG_HS_HCINTMSK3 at 364 range 0 .. 31; - OTG_HS_HCTSIZ3 at 368 range 0 .. 31; - OTG_HS_HCDMA3 at 372 range 0 .. 31; - OTG_HS_HCCHAR4 at 384 range 0 .. 31; - OTG_HS_HCSPLT4 at 388 range 0 .. 31; - OTG_HS_HCINT4 at 392 range 0 .. 31; - OTG_HS_HCINTMSK4 at 396 range 0 .. 31; - OTG_HS_HCTSIZ4 at 400 range 0 .. 31; - OTG_HS_HCDMA4 at 404 range 0 .. 31; - OTG_HS_HCCHAR5 at 416 range 0 .. 31; - OTG_HS_HCSPLT5 at 420 range 0 .. 31; - OTG_HS_HCINT5 at 424 range 0 .. 31; - OTG_HS_HCINTMSK5 at 428 range 0 .. 31; - OTG_HS_HCTSIZ5 at 432 range 0 .. 31; - OTG_HS_HCDMA5 at 436 range 0 .. 31; - OTG_HS_HCCHAR6 at 448 range 0 .. 31; - OTG_HS_HCSPLT6 at 452 range 0 .. 31; - OTG_HS_HCINT6 at 456 range 0 .. 31; - OTG_HS_HCINTMSK6 at 460 range 0 .. 31; - OTG_HS_HCTSIZ6 at 464 range 0 .. 31; - OTG_HS_HCDMA6 at 468 range 0 .. 31; - OTG_HS_HCCHAR7 at 480 range 0 .. 31; - OTG_HS_HCSPLT7 at 484 range 0 .. 31; - OTG_HS_HCINT7 at 488 range 0 .. 31; - OTG_HS_HCINTMSK7 at 492 range 0 .. 31; - OTG_HS_HCTSIZ7 at 496 range 0 .. 31; - OTG_HS_HCDMA7 at 500 range 0 .. 31; - OTG_HS_HCCHAR8 at 512 range 0 .. 31; - OTG_HS_HCSPLT8 at 516 range 0 .. 31; - OTG_HS_HCINT8 at 520 range 0 .. 31; - OTG_HS_HCINTMSK8 at 524 range 0 .. 31; - OTG_HS_HCTSIZ8 at 528 range 0 .. 31; - OTG_HS_HCDMA8 at 532 range 0 .. 31; - OTG_HS_HCCHAR9 at 544 range 0 .. 31; - OTG_HS_HCSPLT9 at 548 range 0 .. 31; - OTG_HS_HCINT9 at 552 range 0 .. 31; - OTG_HS_HCINTMSK9 at 556 range 0 .. 31; - OTG_HS_HCTSIZ9 at 560 range 0 .. 31; - OTG_HS_HCDMA9 at 564 range 0 .. 31; - OTG_HS_HCCHAR10 at 576 range 0 .. 31; - OTG_HS_HCSPLT10 at 580 range 0 .. 31; - OTG_HS_HCINT10 at 584 range 0 .. 31; - OTG_HS_HCINTMSK10 at 588 range 0 .. 31; - OTG_HS_HCTSIZ10 at 592 range 0 .. 31; - OTG_HS_HCDMA10 at 596 range 0 .. 31; - OTG_HS_HCCHAR11 at 608 range 0 .. 31; - OTG_HS_HCSPLT11 at 612 range 0 .. 31; - OTG_HS_HCINT11 at 616 range 0 .. 31; - OTG_HS_HCINTMSK11 at 620 range 0 .. 31; - OTG_HS_HCTSIZ11 at 624 range 0 .. 31; - OTG_HS_HCDMA11 at 628 range 0 .. 31; + OTG_HS_HCFG at 16#0# range 0 .. 31; + OTG_HS_HFIR at 16#4# range 0 .. 31; + OTG_HS_HFNUM at 16#8# range 0 .. 31; + OTG_HS_HPTXSTS at 16#10# range 0 .. 31; + OTG_HS_HAINT at 16#14# range 0 .. 31; + OTG_HS_HAINTMSK at 16#18# range 0 .. 31; + OTG_HS_HPRT at 16#40# range 0 .. 31; + OTG_HS_HCCHAR0 at 16#100# range 0 .. 31; + OTG_HS_HCSPLT0 at 16#104# range 0 .. 31; + OTG_HS_HCINT0 at 16#108# range 0 .. 31; + OTG_HS_HCINTMSK0 at 16#10C# range 0 .. 31; + OTG_HS_HCTSIZ0 at 16#110# range 0 .. 31; + OTG_HS_HCDMA0 at 16#114# range 0 .. 31; + OTG_HS_HCCHAR1 at 16#120# range 0 .. 31; + OTG_HS_HCSPLT1 at 16#124# range 0 .. 31; + OTG_HS_HCINT1 at 16#128# range 0 .. 31; + OTG_HS_HCINTMSK1 at 16#12C# range 0 .. 31; + OTG_HS_HCTSIZ1 at 16#130# range 0 .. 31; + OTG_HS_HCDMA1 at 16#134# range 0 .. 31; + OTG_HS_HCCHAR2 at 16#140# range 0 .. 31; + OTG_HS_HCSPLT2 at 16#144# range 0 .. 31; + OTG_HS_HCINT2 at 16#148# range 0 .. 31; + OTG_HS_HCINTMSK2 at 16#14C# range 0 .. 31; + OTG_HS_HCTSIZ2 at 16#150# range 0 .. 31; + OTG_HS_HCDMA2 at 16#154# range 0 .. 31; + OTG_HS_HCCHAR3 at 16#160# range 0 .. 31; + OTG_HS_HCSPLT3 at 16#164# range 0 .. 31; + OTG_HS_HCINT3 at 16#168# range 0 .. 31; + OTG_HS_HCINTMSK3 at 16#16C# range 0 .. 31; + OTG_HS_HCTSIZ3 at 16#170# range 0 .. 31; + OTG_HS_HCDMA3 at 16#174# range 0 .. 31; + OTG_HS_HCCHAR4 at 16#180# range 0 .. 31; + OTG_HS_HCSPLT4 at 16#184# range 0 .. 31; + OTG_HS_HCINT4 at 16#188# range 0 .. 31; + OTG_HS_HCINTMSK4 at 16#18C# range 0 .. 31; + OTG_HS_HCTSIZ4 at 16#190# range 0 .. 31; + OTG_HS_HCDMA4 at 16#194# range 0 .. 31; + OTG_HS_HCCHAR5 at 16#1A0# range 0 .. 31; + OTG_HS_HCSPLT5 at 16#1A4# range 0 .. 31; + OTG_HS_HCINT5 at 16#1A8# range 0 .. 31; + OTG_HS_HCINTMSK5 at 16#1AC# range 0 .. 31; + OTG_HS_HCTSIZ5 at 16#1B0# range 0 .. 31; + OTG_HS_HCDMA5 at 16#1B4# range 0 .. 31; + OTG_HS_HCCHAR6 at 16#1C0# range 0 .. 31; + OTG_HS_HCSPLT6 at 16#1C4# range 0 .. 31; + OTG_HS_HCINT6 at 16#1C8# range 0 .. 31; + OTG_HS_HCINTMSK6 at 16#1CC# range 0 .. 31; + OTG_HS_HCTSIZ6 at 16#1D0# range 0 .. 31; + OTG_HS_HCDMA6 at 16#1D4# range 0 .. 31; + OTG_HS_HCCHAR7 at 16#1E0# range 0 .. 31; + OTG_HS_HCSPLT7 at 16#1E4# range 0 .. 31; + OTG_HS_HCINT7 at 16#1E8# range 0 .. 31; + OTG_HS_HCINTMSK7 at 16#1EC# range 0 .. 31; + OTG_HS_HCTSIZ7 at 16#1F0# range 0 .. 31; + OTG_HS_HCDMA7 at 16#1F4# range 0 .. 31; + OTG_HS_HCCHAR8 at 16#200# range 0 .. 31; + OTG_HS_HCSPLT8 at 16#204# range 0 .. 31; + OTG_HS_HCINT8 at 16#208# range 0 .. 31; + OTG_HS_HCINTMSK8 at 16#20C# range 0 .. 31; + OTG_HS_HCTSIZ8 at 16#210# range 0 .. 31; + OTG_HS_HCDMA8 at 16#214# range 0 .. 31; + OTG_HS_HCCHAR9 at 16#220# range 0 .. 31; + OTG_HS_HCSPLT9 at 16#224# range 0 .. 31; + OTG_HS_HCINT9 at 16#228# range 0 .. 31; + OTG_HS_HCINTMSK9 at 16#22C# range 0 .. 31; + OTG_HS_HCTSIZ9 at 16#230# range 0 .. 31; + OTG_HS_HCDMA9 at 16#234# range 0 .. 31; + OTG_HS_HCCHAR10 at 16#240# range 0 .. 31; + OTG_HS_HCSPLT10 at 16#244# range 0 .. 31; + OTG_HS_HCINT10 at 16#248# range 0 .. 31; + OTG_HS_HCINTMSK10 at 16#24C# range 0 .. 31; + OTG_HS_HCTSIZ10 at 16#250# range 0 .. 31; + OTG_HS_HCDMA10 at 16#254# range 0 .. 31; + OTG_HS_HCCHAR11 at 16#260# range 0 .. 31; + OTG_HS_HCSPLT11 at 16#264# range 0 .. 31; + OTG_HS_HCINT11 at 16#268# range 0 .. 31; + OTG_HS_HCINTMSK11 at 16#26C# range 0 .. 31; + OTG_HS_HCTSIZ11 at 16#270# range 0 .. 31; + OTG_HS_HCDMA11 at 16#274# range 0 .. 31; end record; -- USB on the go high speed OTG_HS_HOST_Periph : aliased OTG_HS_HOST_Peripheral with Import, Address => OTG_HS_HOST_Base; - -- USB on the go high speed - type OTG_HS_DEVICE_Peripheral is record - -- OTG_HS device configuration register - OTG_HS_DCFG : OTG_HS_DCFG_Register; - -- OTG_HS device control register - OTG_HS_DCTL : OTG_HS_DCTL_Register; - -- OTG_HS device status register - OTG_HS_DSTS : OTG_HS_DSTS_Register; - -- OTG_HS device IN endpoint common interrupt mask register - OTG_HS_DIEPMSK : OTG_HS_DIEPMSK_Register; - -- OTG_HS device OUT endpoint common interrupt mask register - OTG_HS_DOEPMSK : OTG_HS_DOEPMSK_Register; - -- OTG_HS device all endpoints interrupt register - OTG_HS_DAINT : OTG_HS_DAINT_Register; - -- OTG_HS all endpoints interrupt mask register - OTG_HS_DAINTMSK : OTG_HS_DAINTMSK_Register; - -- OTG_HS device VBUS discharge time register - OTG_HS_DVBUSDIS : OTG_HS_DVBUSDIS_Register; - -- OTG_HS device VBUS pulsing time register - OTG_HS_DVBUSPULSE : OTG_HS_DVBUSPULSE_Register; - -- OTG_HS Device threshold control register - OTG_HS_DTHRCTL : OTG_HS_DTHRCTL_Register; - -- OTG_HS device IN endpoint FIFO empty interrupt mask register - OTG_HS_DIEPEMPMSK : OTG_HS_DIEPEMPMSK_Register; - -- OTG_HS device each endpoint interrupt register - OTG_HS_DEACHINT : OTG_HS_DEACHINT_Register; - -- OTG_HS device each endpoint interrupt register mask - OTG_HS_DEACHINTMSK : OTG_HS_DEACHINTMSK_Register; - -- OTG_HS device each in endpoint-1 interrupt register - OTG_HS_DIEPEACHMSK1 : OTG_HS_DIEPEACHMSK1_Register; - -- OTG_HS device each OUT endpoint-1 interrupt register - OTG_HS_DOEPEACHMSK1 : OTG_HS_DOEPEACHMSK1_Register; - -- OTG device endpoint-0 control register - OTG_HS_DIEPCTL0 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-0 interrupt register - OTG_HS_DIEPINT0 : OTG_HS_DIEPINT_Register; - -- OTG_HS device IN endpoint 0 transfer size register - OTG_HS_DIEPTSIZ0 : OTG_HS_DIEPTSIZ0_Register; - -- OTG_HS device endpoint-1 DMA address register - OTG_HS_DIEPDMA1 : STM32F40x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS0 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-1 control register - OTG_HS_DIEPCTL1 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-1 interrupt register - OTG_HS_DIEPINT1 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ1 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device endpoint-2 DMA address register - OTG_HS_DIEPDMA2 : STM32F40x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS1 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-2 control register - OTG_HS_DIEPCTL2 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-2 interrupt register - OTG_HS_DIEPINT2 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ2 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device endpoint-3 DMA address register - OTG_HS_DIEPDMA3 : STM32F40x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS2 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-3 control register - OTG_HS_DIEPCTL3 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-3 interrupt register - OTG_HS_DIEPINT3 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ3 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device endpoint-4 DMA address register - OTG_HS_DIEPDMA4 : STM32F40x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS3 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-4 control register - OTG_HS_DIEPCTL4 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-4 interrupt register - OTG_HS_DIEPINT4 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ4 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device endpoint-5 DMA address register - OTG_HS_DIEPDMA5 : STM32F40x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS4 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-5 control register - OTG_HS_DIEPCTL5 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-5 interrupt register - OTG_HS_DIEPINT5 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ5 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS5 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-6 control register - OTG_HS_DIEPCTL6 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-6 interrupt register - OTG_HS_DIEPINT6 : OTG_HS_DIEPINT_Register; - -- OTG device endpoint-7 control register - OTG_HS_DIEPCTL7 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-7 interrupt register - OTG_HS_DIEPINT7 : OTG_HS_DIEPINT_Register; - -- OTG_HS device control OUT endpoint 0 control register - OTG_HS_DOEPCTL0 : OTG_HS_DOEPCTL0_Register; - -- OTG_HS device endpoint-0 interrupt register - OTG_HS_DOEPINT0 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-1 transfer size register - OTG_HS_DOEPTSIZ0 : OTG_HS_DOEPTSIZ0_Register; - -- OTG device endpoint-1 control register - OTG_HS_DOEPCTL1 : OTG_HS_DOEPCTL_Register; - -- OTG_HS device endpoint-1 interrupt register - OTG_HS_DOEPINT1 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-2 transfer size register - OTG_HS_DOEPTSIZ1 : OTG_HS_DOEPTSIZ_Register; - -- OTG device endpoint-2 control register - OTG_HS_DOEPCTL2 : OTG_HS_DOEPCTL_Register; - -- OTG_HS device endpoint-2 interrupt register - OTG_HS_DOEPINT2 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-3 transfer size register - OTG_HS_DOEPTSIZ2 : OTG_HS_DOEPTSIZ_Register; - -- OTG device endpoint-3 control register - OTG_HS_DOEPCTL3 : OTG_HS_DOEPCTL_Register; - -- OTG_HS device endpoint-3 interrupt register - OTG_HS_DOEPINT3 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-4 transfer size register - OTG_HS_DOEPTSIZ3 : OTG_HS_DOEPTSIZ_Register; - -- OTG_HS device endpoint-4 interrupt register - OTG_HS_DOEPINT4 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-5 transfer size register - OTG_HS_DOEPTSIZ4 : OTG_HS_DOEPTSIZ_Register; - -- OTG_HS device endpoint-5 interrupt register - OTG_HS_DOEPINT5 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-6 interrupt register - OTG_HS_DOEPINT6 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-7 interrupt register - OTG_HS_DOEPINT7 : OTG_HS_DOEPINT_Register; - end record - with Volatile; - - for OTG_HS_DEVICE_Peripheral use record - OTG_HS_DCFG at 0 range 0 .. 31; - OTG_HS_DCTL at 4 range 0 .. 31; - OTG_HS_DSTS at 8 range 0 .. 31; - OTG_HS_DIEPMSK at 16 range 0 .. 31; - OTG_HS_DOEPMSK at 20 range 0 .. 31; - OTG_HS_DAINT at 24 range 0 .. 31; - OTG_HS_DAINTMSK at 28 range 0 .. 31; - OTG_HS_DVBUSDIS at 40 range 0 .. 31; - OTG_HS_DVBUSPULSE at 44 range 0 .. 31; - OTG_HS_DTHRCTL at 48 range 0 .. 31; - OTG_HS_DIEPEMPMSK at 52 range 0 .. 31; - OTG_HS_DEACHINT at 56 range 0 .. 31; - OTG_HS_DEACHINTMSK at 60 range 0 .. 31; - OTG_HS_DIEPEACHMSK1 at 64 range 0 .. 31; - OTG_HS_DOEPEACHMSK1 at 128 range 0 .. 31; - OTG_HS_DIEPCTL0 at 256 range 0 .. 31; - OTG_HS_DIEPINT0 at 264 range 0 .. 31; - OTG_HS_DIEPTSIZ0 at 272 range 0 .. 31; - OTG_HS_DIEPDMA1 at 276 range 0 .. 31; - OTG_HS_DTXFSTS0 at 280 range 0 .. 31; - OTG_HS_DIEPCTL1 at 288 range 0 .. 31; - OTG_HS_DIEPINT1 at 296 range 0 .. 31; - OTG_HS_DIEPTSIZ1 at 304 range 0 .. 31; - OTG_HS_DIEPDMA2 at 308 range 0 .. 31; - OTG_HS_DTXFSTS1 at 312 range 0 .. 31; - OTG_HS_DIEPCTL2 at 320 range 0 .. 31; - OTG_HS_DIEPINT2 at 328 range 0 .. 31; - OTG_HS_DIEPTSIZ2 at 336 range 0 .. 31; - OTG_HS_DIEPDMA3 at 340 range 0 .. 31; - OTG_HS_DTXFSTS2 at 344 range 0 .. 31; - OTG_HS_DIEPCTL3 at 352 range 0 .. 31; - OTG_HS_DIEPINT3 at 360 range 0 .. 31; - OTG_HS_DIEPTSIZ3 at 368 range 0 .. 31; - OTG_HS_DIEPDMA4 at 372 range 0 .. 31; - OTG_HS_DTXFSTS3 at 376 range 0 .. 31; - OTG_HS_DIEPCTL4 at 384 range 0 .. 31; - OTG_HS_DIEPINT4 at 392 range 0 .. 31; - OTG_HS_DIEPTSIZ4 at 400 range 0 .. 31; - OTG_HS_DIEPDMA5 at 404 range 0 .. 31; - OTG_HS_DTXFSTS4 at 408 range 0 .. 31; - OTG_HS_DIEPCTL5 at 416 range 0 .. 31; - OTG_HS_DIEPINT5 at 424 range 0 .. 31; - OTG_HS_DIEPTSIZ5 at 432 range 0 .. 31; - OTG_HS_DTXFSTS5 at 440 range 0 .. 31; - OTG_HS_DIEPCTL6 at 448 range 0 .. 31; - OTG_HS_DIEPINT6 at 456 range 0 .. 31; - OTG_HS_DIEPCTL7 at 480 range 0 .. 31; - OTG_HS_DIEPINT7 at 488 range 0 .. 31; - OTG_HS_DOEPCTL0 at 768 range 0 .. 31; - OTG_HS_DOEPINT0 at 776 range 0 .. 31; - OTG_HS_DOEPTSIZ0 at 784 range 0 .. 31; - OTG_HS_DOEPCTL1 at 800 range 0 .. 31; - OTG_HS_DOEPINT1 at 808 range 0 .. 31; - OTG_HS_DOEPTSIZ1 at 816 range 0 .. 31; - OTG_HS_DOEPCTL2 at 832 range 0 .. 31; - OTG_HS_DOEPINT2 at 840 range 0 .. 31; - OTG_HS_DOEPTSIZ2 at 848 range 0 .. 31; - OTG_HS_DOEPCTL3 at 864 range 0 .. 31; - OTG_HS_DOEPINT3 at 872 range 0 .. 31; - OTG_HS_DOEPTSIZ3 at 880 range 0 .. 31; - OTG_HS_DOEPINT4 at 904 range 0 .. 31; - OTG_HS_DOEPTSIZ4 at 912 range 0 .. 31; - OTG_HS_DOEPINT5 at 936 range 0 .. 31; - OTG_HS_DOEPINT6 at 968 range 0 .. 31; - OTG_HS_DOEPINT7 at 1000 range 0 .. 31; - end record; - - -- USB on the go high speed - OTG_HS_DEVICE_Periph : aliased OTG_HS_DEVICE_Peripheral - with Import, Address => OTG_HS_DEVICE_Base; - -- USB on the go high speed type OTG_HS_PWRCLK_Peripheral is record -- Power and clock gating control register - OTG_HS_PCGCR : OTG_HS_PCGCR_Register; + OTG_HS_PCGCR : aliased OTG_HS_PCGCR_Register; + pragma Volatile_Full_Access (OTG_HS_PCGCR); end record with Volatile; diff --git a/stm32f4/stm32f40x/stm32f40x-wwdg.ads b/stm32f4/stm32f40x/stm32f40x-wwdg.ads index 70f14a8..fec3313 100644 --- a/stm32f4/stm32f40x/stm32f40x-wwdg.ads +++ b/stm32f4/stm32f40x/stm32f40x-wwdg.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with System; @@ -13,10 +14,6 @@ package STM32F40x.WWDG is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_T_Field is STM32F40x.UInt7; subtype CR_WDGA_Field is STM32F40x.Bit; @@ -29,8 +26,7 @@ package STM32F40x.WWDG is -- unspecified Reserved_8_31 : STM32F40x.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record T at 0 range 0 .. 6; @@ -38,16 +34,7 @@ package STM32F40x.WWDG is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- CFR_Register -- - ------------------ - subtype CFR_W_Field is STM32F40x.UInt7; - - --------------- - -- CFR.WDGTB -- - --------------- - -- CFR_WDGTB array element subtype CFR_WDGTB_Element is STM32F40x.Bit; @@ -88,8 +75,7 @@ package STM32F40x.WWDG is -- unspecified Reserved_10_31 : STM32F40x.UInt22 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CFR_Register use record W at 0 range 0 .. 6; @@ -98,10 +84,6 @@ package STM32F40x.WWDG is Reserved_10_31 at 0 range 10 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_EWIF_Field is STM32F40x.Bit; -- Status register @@ -111,8 +93,7 @@ package STM32F40x.WWDG is -- unspecified Reserved_1_31 : STM32F40x.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, - Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record EWIF at 0 range 0 .. 0; @@ -126,18 +107,21 @@ package STM32F40x.WWDG is -- Window watchdog type WWDG_Peripheral is record -- Control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- Configuration register - CFR : CFR_Register; + CFR : aliased CFR_Register; + pragma Volatile_Full_Access (CFR); -- Status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; for WWDG_Peripheral use record - CR at 0 range 0 .. 31; - CFR at 4 range 0 .. 31; - SR at 8 range 0 .. 31; + CR at 16#0# range 0 .. 31; + CFR at 16#4# range 0 .. 31; + SR at 16#8# range 0 .. 31; end record; -- Window watchdog diff --git a/stm32f4/stm32f40x/stm32f40x.ads b/stm32f4/stm32f40x/stm32f40x.ads index 5354496..f35bbd1 100644 --- a/stm32f4/stm32f40x/stm32f40x.ads +++ b/stm32f4/stm32f40x/stm32f40x.ads @@ -1,8 +1,9 @@ +pragma Ada_2012; +pragma Style_Checks (Off); + -- This spec has been automatically generated from STM32F40x.svd --- see https://github.com/simonjwright/svd2ada pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; with Interfaces; with System; @@ -15,9 +16,9 @@ package STM32F40x is -- Base type -- --------------- - subtype Word is Interfaces.Unsigned_32; - subtype Short is Interfaces.Unsigned_16; - subtype Byte is Interfaces.Unsigned_8; + type UInt32 is new Interfaces.Unsigned_32; + type UInt16 is new Interfaces.Unsigned_16; + type Byte is new Interfaces.Unsigned_8; type Bit is mod 2**1 with Size => 1; type UInt2 is mod 2**2 @@ -81,151 +82,78 @@ package STM32F40x is -- Base addresses -- -------------------- - RNG_Base : constant System.Address := - System'To_Address (16#50060800#); - DCMI_Base : constant System.Address := - System'To_Address (16#50050000#); - FSMC_Base : constant System.Address := - System'To_Address (16#A0000000#); - DBG_Base : constant System.Address := - System'To_Address (16#E0042000#); - DMA2_Base : constant System.Address := - System'To_Address (16#40026400#); - DMA1_Base : constant System.Address := - System'To_Address (16#40026000#); - RCC_Base : constant System.Address := - System'To_Address (16#40023800#); - GPIOI_Base : constant System.Address := - System'To_Address (16#40022000#); - GPIOH_Base : constant System.Address := - System'To_Address (16#40021C00#); - GPIOG_Base : constant System.Address := - System'To_Address (16#40021800#); - GPIOF_Base : constant System.Address := - System'To_Address (16#40021400#); - GPIOE_Base : constant System.Address := - System'To_Address (16#40021000#); - GPIOD_Base : constant System.Address := - System'To_Address (16#40020C00#); - GPIOC_Base : constant System.Address := - System'To_Address (16#40020800#); - GPIOB_Base : constant System.Address := - System'To_Address (16#40020400#); - GPIOA_Base : constant System.Address := - System'To_Address (16#40020000#); - SYSCFG_Base : constant System.Address := - System'To_Address (16#40013800#); - SPI1_Base : constant System.Address := - System'To_Address (16#40013000#); - SPI2_Base : constant System.Address := - System'To_Address (16#40003800#); - SPI3_Base : constant System.Address := - System'To_Address (16#40003C00#); - I2S2ext_Base : constant System.Address := - System'To_Address (16#40003400#); - I2S3ext_Base : constant System.Address := - System'To_Address (16#40004000#); - SDIO_Base : constant System.Address := - System'To_Address (16#40012C00#); - ADC1_Base : constant System.Address := - System'To_Address (16#40012000#); - ADC2_Base : constant System.Address := - System'To_Address (16#40012100#); - ADC3_Base : constant System.Address := - System'To_Address (16#40012200#); - USART6_Base : constant System.Address := - System'To_Address (16#40011400#); - USART1_Base : constant System.Address := - System'To_Address (16#40011000#); - USART2_Base : constant System.Address := - System'To_Address (16#40004400#); - USART3_Base : constant System.Address := - System'To_Address (16#40004800#); - DAC_Base : constant System.Address := - System'To_Address (16#40007400#); - PWR_Base : constant System.Address := - System'To_Address (16#40007000#); - I2C3_Base : constant System.Address := - System'To_Address (16#40005C00#); - I2C2_Base : constant System.Address := - System'To_Address (16#40005800#); - I2C1_Base : constant System.Address := - System'To_Address (16#40005400#); - IWDG_Base : constant System.Address := - System'To_Address (16#40003000#); - WWDG_Base : constant System.Address := - System'To_Address (16#40002C00#); - RTC_Base : constant System.Address := - System'To_Address (16#40002800#); - UART4_Base : constant System.Address := - System'To_Address (16#40004C00#); - UART5_Base : constant System.Address := - System'To_Address (16#40005000#); - C_ADC_Base : constant System.Address := - System'To_Address (16#40012300#); - TIM1_Base : constant System.Address := - System'To_Address (16#40010000#); - TIM8_Base : constant System.Address := - System'To_Address (16#40010400#); - TIM2_Base : constant System.Address := - System'To_Address (16#40000000#); - TIM3_Base : constant System.Address := - System'To_Address (16#40000400#); - TIM4_Base : constant System.Address := - System'To_Address (16#40000800#); - TIM5_Base : constant System.Address := - System'To_Address (16#40000C00#); - TIM9_Base : constant System.Address := - System'To_Address (16#40014000#); - TIM12_Base : constant System.Address := - System'To_Address (16#40001800#); - TIM10_Base : constant System.Address := - System'To_Address (16#40014400#); - TIM13_Base : constant System.Address := - System'To_Address (16#40001C00#); - TIM14_Base : constant System.Address := - System'To_Address (16#40002000#); - TIM11_Base : constant System.Address := - System'To_Address (16#40014800#); - TIM6_Base : constant System.Address := - System'To_Address (16#40001000#); - TIM7_Base : constant System.Address := - System'To_Address (16#40001400#); - Ethernet_MAC_Base : constant System.Address := - System'To_Address (16#40028000#); - Ethernet_MMC_Base : constant System.Address := - System'To_Address (16#40028100#); - Ethernet_PTP_Base : constant System.Address := - System'To_Address (16#40028700#); - Ethernet_DMA_Base : constant System.Address := - System'To_Address (16#40029000#); - CRC_Base : constant System.Address := - System'To_Address (16#40023000#); - OTG_FS_GLOBAL_Base : constant System.Address := - System'To_Address (16#50000000#); - OTG_FS_HOST_Base : constant System.Address := - System'To_Address (16#50000400#); - OTG_FS_DEVICE_Base : constant System.Address := - System'To_Address (16#50000800#); - OTG_FS_PWRCLK_Base : constant System.Address := - System'To_Address (16#50000E00#); - CAN1_Base : constant System.Address := - System'To_Address (16#40006400#); - CAN2_Base : constant System.Address := - System'To_Address (16#40006800#); - FLASH_Base : constant System.Address := - System'To_Address (16#40023C00#); - EXTI_Base : constant System.Address := - System'To_Address (16#40013C00#); - OTG_HS_GLOBAL_Base : constant System.Address := - System'To_Address (16#40040000#); - OTG_HS_HOST_Base : constant System.Address := - System'To_Address (16#40040400#); - OTG_HS_DEVICE_Base : constant System.Address := - System'To_Address (16#40040800#); - OTG_HS_PWRCLK_Base : constant System.Address := - System'To_Address (16#40040E00#); - NVIC_Base : constant System.Address := - System'To_Address (16#E000E000#); + RNG_Base : constant System.Address := System'To_Address (16#50060800#); + DCMI_Base : constant System.Address := System'To_Address (16#50050000#); + FSMC_Base : constant System.Address := System'To_Address (16#A0000000#); + DBG_Base : constant System.Address := System'To_Address (16#E0042000#); + DMA2_Base : constant System.Address := System'To_Address (16#40026400#); + DMA1_Base : constant System.Address := System'To_Address (16#40026000#); + RCC_Base : constant System.Address := System'To_Address (16#40023800#); + GPIOI_Base : constant System.Address := System'To_Address (16#40022000#); + GPIOH_Base : constant System.Address := System'To_Address (16#40021C00#); + GPIOG_Base : constant System.Address := System'To_Address (16#40021800#); + GPIOF_Base : constant System.Address := System'To_Address (16#40021400#); + GPIOE_Base : constant System.Address := System'To_Address (16#40021000#); + GPIOD_Base : constant System.Address := System'To_Address (16#40020C00#); + GPIOC_Base : constant System.Address := System'To_Address (16#40020800#); + GPIOB_Base : constant System.Address := System'To_Address (16#40020400#); + GPIOA_Base : constant System.Address := System'To_Address (16#40020000#); + SYSCFG_Base : constant System.Address := System'To_Address (16#40013800#); + SPI1_Base : constant System.Address := System'To_Address (16#40013000#); + SPI2_Base : constant System.Address := System'To_Address (16#40003800#); + SPI3_Base : constant System.Address := System'To_Address (16#40003C00#); + I2S2ext_Base : constant System.Address := System'To_Address (16#40003400#); + I2S3ext_Base : constant System.Address := System'To_Address (16#40004000#); + SDIO_Base : constant System.Address := System'To_Address (16#40012C00#); + ADC1_Base : constant System.Address := System'To_Address (16#40012000#); + ADC2_Base : constant System.Address := System'To_Address (16#40012100#); + ADC3_Base : constant System.Address := System'To_Address (16#40012200#); + USART6_Base : constant System.Address := System'To_Address (16#40011400#); + USART1_Base : constant System.Address := System'To_Address (16#40011000#); + USART2_Base : constant System.Address := System'To_Address (16#40004400#); + USART3_Base : constant System.Address := System'To_Address (16#40004800#); + DAC_Base : constant System.Address := System'To_Address (16#40007400#); + PWR_Base : constant System.Address := System'To_Address (16#40007000#); + I2C3_Base : constant System.Address := System'To_Address (16#40005C00#); + I2C2_Base : constant System.Address := System'To_Address (16#40005800#); + I2C1_Base : constant System.Address := System'To_Address (16#40005400#); + IWDG_Base : constant System.Address := System'To_Address (16#40003000#); + WWDG_Base : constant System.Address := System'To_Address (16#40002C00#); + RTC_Base : constant System.Address := System'To_Address (16#40002800#); + UART4_Base : constant System.Address := System'To_Address (16#40004C00#); + UART5_Base : constant System.Address := System'To_Address (16#40005000#); + C_ADC_Base : constant System.Address := System'To_Address (16#40012300#); + TIM1_Base : constant System.Address := System'To_Address (16#40010000#); + TIM8_Base : constant System.Address := System'To_Address (16#40010400#); + TIM2_Base : constant System.Address := System'To_Address (16#40000000#); + TIM3_Base : constant System.Address := System'To_Address (16#40000400#); + TIM4_Base : constant System.Address := System'To_Address (16#40000800#); + TIM5_Base : constant System.Address := System'To_Address (16#40000C00#); + TIM9_Base : constant System.Address := System'To_Address (16#40014000#); + TIM12_Base : constant System.Address := System'To_Address (16#40001800#); + TIM10_Base : constant System.Address := System'To_Address (16#40014400#); + TIM13_Base : constant System.Address := System'To_Address (16#40001C00#); + TIM14_Base : constant System.Address := System'To_Address (16#40002000#); + TIM11_Base : constant System.Address := System'To_Address (16#40014800#); + TIM6_Base : constant System.Address := System'To_Address (16#40001000#); + TIM7_Base : constant System.Address := System'To_Address (16#40001400#); + Ethernet_MAC_Base : constant System.Address := System'To_Address (16#40028000#); + Ethernet_MMC_Base : constant System.Address := System'To_Address (16#40028100#); + Ethernet_PTP_Base : constant System.Address := System'To_Address (16#40028700#); + Ethernet_DMA_Base : constant System.Address := System'To_Address (16#40029000#); + CRC_Base : constant System.Address := System'To_Address (16#40023000#); + OTG_FS_GLOBAL_Base : constant System.Address := System'To_Address (16#50000000#); + OTG_FS_HOST_Base : constant System.Address := System'To_Address (16#50000400#); + OTG_FS_DEVICE_Base : constant System.Address := System'To_Address (16#50000800#); + OTG_FS_PWRCLK_Base : constant System.Address := System'To_Address (16#50000E00#); + CAN1_Base : constant System.Address := System'To_Address (16#40006400#); + CAN2_Base : constant System.Address := System'To_Address (16#40006800#); + FLASH_Base : constant System.Address := System'To_Address (16#40023C00#); + EXTI_Base : constant System.Address := System'To_Address (16#40013C00#); + OTG_HS_GLOBAL_Base : constant System.Address := System'To_Address (16#40040000#); + OTG_HS_HOST_Base : constant System.Address := System'To_Address (16#40040400#); + OTG_HS_DEVICE_Base : constant System.Address := System'To_Address (16#40040800#); + OTG_HS_PWRCLK_Base : constant System.Address := System'To_Address (16#40040E00#); + NVIC_Base : constant System.Address := System'To_Address (16#E000E000#); end STM32F40x; diff --git a/stm32f429i/Makefile b/stm32f429i/Makefile index e9d0e16..6c3e793 100644 --- a/stm32f429i/Makefile +++ b/stm32f429i/Makefile @@ -1,4 +1,4 @@ -# Copyright (C) 2016, 2018 Free Software Foundation, Inc. +# Copyright (C) 2016, 2018, 2020 Free Software Foundation, Inc. # # This file is part of the Cortex GNAT RTS package. # @@ -16,13 +16,22 @@ # along with this program; see the file COPYING3. If not, see # . -all: +SVD2ADA ?= ~/adacore/svd2ada + +all: stm32f429x gprbuild -p -P build_runtime.gpr +stm32f429x: + $(SVD2ADA)/svd2ada \ + --output=stm32f429x \ + --no-vfa-on-types \ + $(SVD2ADA)/CMSIS-SVD/ST/STM32F429x.svd + install: all gprinstall -p -P build_runtime.gpr -f clean: - gprclean -P build_runtime.gpr + -gprclean -P build_runtime.gpr + rm -rf stm32f429x .PHONY: all install clean diff --git a/stm32f429i/stm32f429x/stm32f429x-adc.ads b/stm32f429i/stm32f429x/stm32f429x-adc.ads index d5fe6e3..fc30a76 100644 --- a/stm32f429i/stm32f429x/stm32f429x-adc.ads +++ b/stm32f429i/stm32f429x/stm32f429x-adc.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.ADC is -- Registers -- --------------- - ----------------- - -- SR_Register -- - ----------------- - subtype SR_AWD_Field is STM32F429x.Bit; subtype SR_EOC_Field is STM32F429x.Bit; subtype SR_JEOC_Field is STM32F429x.Bit; @@ -40,7 +38,7 @@ package STM32F429x.ADC is -- unspecified Reserved_6_31 : STM32F429x.UInt26 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record AWD at 0 range 0 .. 0; @@ -52,10 +50,6 @@ package STM32F429x.ADC is Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_AWDCH_Field is STM32F429x.UInt5; subtype CR1_EOCIE_Field is STM32F429x.Bit; subtype CR1_AWDIE_Field is STM32F429x.Bit; @@ -106,7 +100,7 @@ package STM32F429x.ADC is -- unspecified Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record AWDCH at 0 range 0 .. 4; @@ -127,10 +121,6 @@ package STM32F429x.ADC is Reserved_27_31 at 0 range 27 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_ADON_Field is STM32F429x.Bit; subtype CR2_CONT_Field is STM32F429x.Bit; subtype CR2_DMA_Field is STM32F429x.Bit; @@ -179,7 +169,7 @@ package STM32F429x.ADC is -- unspecified Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record ADON at 0 range 0 .. 0; @@ -200,29 +190,151 @@ package STM32F429x.ADC is Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------- - -- JOFR_Register -- - ------------------- + -- SMPR1_SMP array element + subtype SMPR1_SMP_Element is STM32F429x.UInt3; + + -- SMPR1_SMP array + type SMPR1_SMP_Field_Array is array (10 .. 18) of SMPR1_SMP_Element + with Component_Size => 3, Size => 27; + + -- Type definition for SMPR1_SMP + type SMPR1_SMP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SMP as a value + Val : STM32F429x.UInt27; + when True => + -- SMP as an array + Arr : SMPR1_SMP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 27; + + for SMPR1_SMP_Field use record + Val at 0 range 0 .. 26; + Arr at 0 range 0 .. 26; + end record; + + -- sample time register 1 + type SMPR1_Register is record + -- Sample time bits + SMP : SMPR1_SMP_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_27_31 : STM32F429x.UInt5 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SMPR1_Register use record + SMP at 0 range 0 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- SMPR2_SMP array element + subtype SMPR2_SMP_Element is STM32F429x.UInt3; + + -- SMPR2_SMP array + type SMPR2_SMP_Field_Array is array (0 .. 9) of SMPR2_SMP_Element + with Component_Size => 3, Size => 30; + + -- Type definition for SMPR2_SMP + type SMPR2_SMP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SMP as a value + Val : STM32F429x.UInt30; + when True => + -- SMP as an array + Arr : SMPR2_SMP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 30; + + for SMPR2_SMP_Field use record + Val at 0 range 0 .. 29; + Arr at 0 range 0 .. 29; + end record; + + -- sample time register 2 + type SMPR2_Register is record + -- Sample time bits + SMP : SMPR2_SMP_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_30_31 : STM32F429x.UInt2 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SMPR2_Register use record + SMP at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; subtype JOFR1_JOFFSET1_Field is STM32F429x.UInt12; -- injected channel data offset register x - type JOFR_Register is record + type JOFR1_Register is record -- Data offset for injected channel x JOFFSET1 : JOFR1_JOFFSET1_Field := 16#0#; -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for JOFR_Register use record + for JOFR1_Register use record JOFFSET1 at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- HTR_Register -- - ------------------ + subtype JOFR2_JOFFSET2_Field is STM32F429x.UInt12; + + -- injected channel data offset register x + type JOFR2_Register is record + -- Data offset for injected channel x + JOFFSET2 : JOFR2_JOFFSET2_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for JOFR2_Register use record + JOFFSET2 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype JOFR3_JOFFSET3_Field is STM32F429x.UInt12; + + -- injected channel data offset register x + type JOFR3_Register is record + -- Data offset for injected channel x + JOFFSET3 : JOFR3_JOFFSET3_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for JOFR3_Register use record + JOFFSET3 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype JOFR4_JOFFSET4_Field is STM32F429x.UInt12; + + -- injected channel data offset register x + type JOFR4_Register is record + -- Data offset for injected channel x + JOFFSET4 : JOFR4_JOFFSET4_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for JOFR4_Register use record + JOFFSET4 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; subtype HTR_HT_Field is STM32F429x.UInt12; @@ -233,17 +345,13 @@ package STM32F429x.ADC is -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for HTR_Register use record HT at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- LTR_Register -- - ------------------ - subtype LTR_LT_Field is STM32F429x.UInt12; -- watchdog lower threshold register @@ -253,26 +361,18 @@ package STM32F429x.ADC is -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LTR_Register use record LT at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------- - -- SQR1_Register -- - ------------------- - - ------------- - -- SQR1.SQ -- - ------------- - -- SQR1_SQ array element subtype SQR1_SQ_Element is STM32F429x.UInt5; -- SQR1_SQ array - type SQR1_SQ_Field_Array is array (0 .. 3) of SQR1_SQ_Element + type SQR1_SQ_Field_Array is array (13 .. 16) of SQR1_SQ_Element with Component_Size => 5, Size => 20; -- Type definition for SQR1_SQ @@ -306,7 +406,7 @@ package STM32F429x.ADC is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SQR1_Register use record SQ at 0 range 0 .. 19; @@ -314,19 +414,11 @@ package STM32F429x.ADC is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- SQR_Register -- - ------------------ - - ------------- - -- SQR2.SQ -- - ------------- - -- SQR2_SQ array element subtype SQR2_SQ_Element is STM32F429x.UInt5; -- SQR2_SQ array - type SQR2_SQ_Field_Array is array (0 .. 5) of SQR2_SQ_Element + type SQR2_SQ_Field_Array is array (7 .. 12) of SQR2_SQ_Element with Component_Size => 5, Size => 30; -- Type definition for SQR2_SQ @@ -350,32 +442,65 @@ package STM32F429x.ADC is end record; -- regular sequence register 2 - type SQR_Register is record + type SQR2_Register is record -- 7th conversion in regular sequence SQ : SQR2_SQ_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_30_31 : STM32F429x.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for SQR_Register use record + for SQR2_Register use record SQ at 0 range 0 .. 29; Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- JSQR_Register -- - ------------------- + -- SQR3_SQ array element + subtype SQR3_SQ_Element is STM32F429x.UInt5; + + -- SQR3_SQ array + type SQR3_SQ_Field_Array is array (1 .. 6) of SQR3_SQ_Element + with Component_Size => 5, Size => 30; + + -- Type definition for SQR3_SQ + type SQR3_SQ_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SQ as a value + Val : STM32F429x.UInt30; + when True => + -- SQ as an array + Arr : SQR3_SQ_Field_Array; + end case; + end record + with Unchecked_Union, Size => 30; + + for SQR3_SQ_Field use record + Val at 0 range 0 .. 29; + Arr at 0 range 0 .. 29; + end record; + + -- regular sequence register 3 + type SQR3_Register is record + -- 1st conversion in regular sequence + SQ : SQR3_SQ_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_30_31 : STM32F429x.UInt2 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -------------- - -- JSQR.JSQ -- - -------------- + for SQR3_Register use record + SQ at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; -- JSQR_JSQ array element subtype JSQR_JSQ_Element is STM32F429x.UInt5; -- JSQR_JSQ array - type JSQR_JSQ_Field_Array is array (0 .. 3) of JSQR_JSQ_Element + type JSQR_JSQ_Field_Array is array (1 .. 4) of JSQR_JSQ_Element with Component_Size => 5, Size => 20; -- Type definition for JSQR_JSQ @@ -409,7 +534,7 @@ package STM32F429x.ADC is -- unspecified Reserved_22_31 : STM32F429x.UInt10 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for JSQR_Register use record JSQ at 0 range 0 .. 19; @@ -417,50 +542,38 @@ package STM32F429x.ADC is Reserved_22_31 at 0 range 22 .. 31; end record; - ------------------ - -- JDR_Register -- - ------------------ - - subtype JDR1_JDATA_Field is STM32F429x.Short; + subtype JDR_JDATA_Field is STM32F429x.UInt16; -- injected data register x type JDR_Register is record - -- Injected data - JDATA : JDR1_JDATA_Field; + -- Read-only. Injected data + JDATA : JDR_JDATA_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for JDR_Register use record JDATA at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - - subtype DR_DATA_Field is STM32F429x.Short; + subtype DR_DATA_Field is STM32F429x.UInt16; -- regular data register type DR_Register is record - -- Regular data + -- Read-only. Regular data DATA : DR_DATA_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DATA at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CSR_Register -- - ------------------ - subtype CSR_AWD1_Field is STM32F429x.Bit; subtype CSR_EOC1_Field is STM32F429x.Bit; subtype CSR_JEOC1_Field is STM32F429x.Bit; @@ -482,50 +595,50 @@ package STM32F429x.ADC is -- ADC Common status register type CSR_Register is record - -- Analog watchdog flag of ADC 1 + -- Read-only. Analog watchdog flag of ADC 1 AWD1 : CSR_AWD1_Field; - -- End of conversion of ADC 1 + -- Read-only. End of conversion of ADC 1 EOC1 : CSR_EOC1_Field; - -- Injected channel end of conversion of ADC 1 + -- Read-only. Injected channel end of conversion of ADC 1 JEOC1 : CSR_JEOC1_Field; - -- Injected channel Start flag of ADC 1 + -- Read-only. Injected channel Start flag of ADC 1 JSTRT1 : CSR_JSTRT1_Field; - -- Regular channel Start flag of ADC 1 + -- Read-only. Regular channel Start flag of ADC 1 STRT1 : CSR_STRT1_Field; - -- Overrun flag of ADC 1 + -- Read-only. Overrun flag of ADC 1 OVR1 : CSR_OVR1_Field; -- unspecified Reserved_6_7 : STM32F429x.UInt2; - -- Analog watchdog flag of ADC 2 + -- Read-only. Analog watchdog flag of ADC 2 AWD2 : CSR_AWD2_Field; - -- End of conversion of ADC 2 + -- Read-only. End of conversion of ADC 2 EOC2 : CSR_EOC2_Field; - -- Injected channel end of conversion of ADC 2 + -- Read-only. Injected channel end of conversion of ADC 2 JEOC2 : CSR_JEOC2_Field; - -- Injected channel Start flag of ADC 2 + -- Read-only. Injected channel Start flag of ADC 2 JSTRT2 : CSR_JSTRT2_Field; - -- Regular channel Start flag of ADC 2 + -- Read-only. Regular channel Start flag of ADC 2 STRT2 : CSR_STRT2_Field; - -- Overrun flag of ADC 2 + -- Read-only. Overrun flag of ADC 2 OVR2 : CSR_OVR2_Field; -- unspecified Reserved_14_15 : STM32F429x.UInt2; - -- Analog watchdog flag of ADC 3 + -- Read-only. Analog watchdog flag of ADC 3 AWD3 : CSR_AWD3_Field; - -- End of conversion of ADC 3 + -- Read-only. End of conversion of ADC 3 EOC3 : CSR_EOC3_Field; - -- Injected channel end of conversion of ADC 3 + -- Read-only. Injected channel end of conversion of ADC 3 JEOC3 : CSR_JEOC3_Field; - -- Injected channel Start flag of ADC 3 + -- Read-only. Injected channel Start flag of ADC 3 JSTRT3 : CSR_JSTRT3_Field; - -- Regular channel Start flag of ADC 3 + -- Read-only. Regular channel Start flag of ADC 3 STRT3 : CSR_STRT3_Field; - -- Overrun flag of ADC3 + -- Read-only. Overrun flag of ADC3 OVR3 : CSR_OVR3_Field; -- unspecified Reserved_22_31 : STM32F429x.UInt10; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CSR_Register use record AWD1 at 0 range 0 .. 0; @@ -551,10 +664,6 @@ package STM32F429x.ADC is Reserved_22_31 at 0 range 22 .. 31; end record; - ------------------ - -- CCR_Register -- - ------------------ - subtype CCR_MULT_Field is STM32F429x.UInt5; subtype CCR_DELAY_Field is STM32F429x.UInt4; subtype CCR_DDS_Field is STM32F429x.Bit; @@ -588,7 +697,7 @@ package STM32F429x.ADC is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCR_Register use record MULT at 0 range 0 .. 4; @@ -604,15 +713,11 @@ package STM32F429x.ADC is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- CDR_Register -- - ------------------ - -- CDR_DATA array element - subtype CDR_DATA_Element is STM32F429x.Short; + subtype CDR_DATA_Element is STM32F429x.UInt16; -- CDR_DATA array - type CDR_DATA_Field_Array is array (0 .. 1) of CDR_DATA_Element + type CDR_DATA_Field_Array is array (1 .. 2) of CDR_DATA_Element with Component_Size => 16, Size => 32; -- ADC common regular data register for dual and triple modes @@ -622,13 +727,13 @@ package STM32F429x.ADC is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : CDR_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for CDR_Register use record @@ -643,102 +748,125 @@ package STM32F429x.ADC is -- Analog-to-digital converter type ADC1_Peripheral is record -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- sample time register 1 - SMPR1 : STM32F429x.Word; + SMPR1 : aliased SMPR1_Register; + pragma Volatile_Full_Access (SMPR1); -- sample time register 2 - SMPR2 : STM32F429x.Word; + SMPR2 : aliased SMPR2_Register; + pragma Volatile_Full_Access (SMPR2); -- injected channel data offset register x - JOFR1 : JOFR_Register; + JOFR1 : aliased JOFR1_Register; + pragma Volatile_Full_Access (JOFR1); -- injected channel data offset register x - JOFR2 : JOFR_Register; + JOFR2 : aliased JOFR2_Register; + pragma Volatile_Full_Access (JOFR2); -- injected channel data offset register x - JOFR3 : JOFR_Register; + JOFR3 : aliased JOFR3_Register; + pragma Volatile_Full_Access (JOFR3); -- injected channel data offset register x - JOFR4 : JOFR_Register; + JOFR4 : aliased JOFR4_Register; + pragma Volatile_Full_Access (JOFR4); -- watchdog higher threshold register - HTR : HTR_Register; + HTR : aliased HTR_Register; + pragma Volatile_Full_Access (HTR); -- watchdog lower threshold register - LTR : LTR_Register; + LTR : aliased LTR_Register; + pragma Volatile_Full_Access (LTR); -- regular sequence register 1 - SQR1 : SQR1_Register; + SQR1 : aliased SQR1_Register; + pragma Volatile_Full_Access (SQR1); -- regular sequence register 2 - SQR2 : SQR_Register; + SQR2 : aliased SQR2_Register; + pragma Volatile_Full_Access (SQR2); -- regular sequence register 3 - SQR3 : SQR_Register; + SQR3 : aliased SQR3_Register; + pragma Volatile_Full_Access (SQR3); -- injected sequence register - JSQR : JSQR_Register; + JSQR : aliased JSQR_Register; + pragma Volatile_Full_Access (JSQR); -- injected data register x - JDR1 : JDR_Register; + JDR1 : aliased JDR_Register; + pragma Volatile_Full_Access (JDR1); -- injected data register x - JDR2 : JDR_Register; + JDR2 : aliased JDR_Register; + pragma Volatile_Full_Access (JDR2); -- injected data register x - JDR3 : JDR_Register; + JDR3 : aliased JDR_Register; + pragma Volatile_Full_Access (JDR3); -- injected data register x - JDR4 : JDR_Register; + JDR4 : aliased JDR_Register; + pragma Volatile_Full_Access (JDR4); -- regular data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); end record with Volatile; for ADC1_Peripheral use record - SR at 0 range 0 .. 31; - CR1 at 4 range 0 .. 31; - CR2 at 8 range 0 .. 31; - SMPR1 at 12 range 0 .. 31; - SMPR2 at 16 range 0 .. 31; - JOFR1 at 20 range 0 .. 31; - JOFR2 at 24 range 0 .. 31; - JOFR3 at 28 range 0 .. 31; - JOFR4 at 32 range 0 .. 31; - HTR at 36 range 0 .. 31; - LTR at 40 range 0 .. 31; - SQR1 at 44 range 0 .. 31; - SQR2 at 48 range 0 .. 31; - SQR3 at 52 range 0 .. 31; - JSQR at 56 range 0 .. 31; - JDR1 at 60 range 0 .. 31; - JDR2 at 64 range 0 .. 31; - JDR3 at 68 range 0 .. 31; - JDR4 at 72 range 0 .. 31; - DR at 76 range 0 .. 31; + SR at 16#0# range 0 .. 31; + CR1 at 16#4# range 0 .. 31; + CR2 at 16#8# range 0 .. 31; + SMPR1 at 16#C# range 0 .. 31; + SMPR2 at 16#10# range 0 .. 31; + JOFR1 at 16#14# range 0 .. 31; + JOFR2 at 16#18# range 0 .. 31; + JOFR3 at 16#1C# range 0 .. 31; + JOFR4 at 16#20# range 0 .. 31; + HTR at 16#24# range 0 .. 31; + LTR at 16#28# range 0 .. 31; + SQR1 at 16#2C# range 0 .. 31; + SQR2 at 16#30# range 0 .. 31; + SQR3 at 16#34# range 0 .. 31; + JSQR at 16#38# range 0 .. 31; + JDR1 at 16#3C# range 0 .. 31; + JDR2 at 16#40# range 0 .. 31; + JDR3 at 16#44# range 0 .. 31; + JDR4 at 16#48# range 0 .. 31; + DR at 16#4C# range 0 .. 31; end record; -- Analog-to-digital converter ADC1_Periph : aliased ADC1_Peripheral - with Import, Address => System'To_Address (16#40012000#); + with Import, Address => ADC1_Base; -- Analog-to-digital converter ADC2_Periph : aliased ADC1_Peripheral - with Import, Address => System'To_Address (16#40012100#); + with Import, Address => ADC2_Base; -- Analog-to-digital converter ADC3_Periph : aliased ADC1_Peripheral - with Import, Address => System'To_Address (16#40012200#); + with Import, Address => ADC3_Base; -- Common ADC registers type C_ADC_Peripheral is record -- ADC Common status register - CSR : CSR_Register; + CSR : aliased CSR_Register; + pragma Volatile_Full_Access (CSR); -- ADC common control register - CCR : CCR_Register; + CCR : aliased CCR_Register; + pragma Volatile_Full_Access (CCR); -- ADC common regular data register for dual and triple modes - CDR : CDR_Register; + CDR : aliased CDR_Register; + pragma Volatile_Full_Access (CDR); end record with Volatile; for C_ADC_Peripheral use record - CSR at 0 range 0 .. 31; - CCR at 4 range 0 .. 31; - CDR at 8 range 0 .. 31; + CSR at 16#0# range 0 .. 31; + CCR at 16#4# range 0 .. 31; + CDR at 16#8# range 0 .. 31; end record; -- Common ADC registers C_ADC_Periph : aliased C_ADC_Peripheral - with Import, Address => System'To_Address (16#40012300#); + with Import, Address => C_ADC_Base; end STM32F429x.ADC; diff --git a/stm32f429i/stm32f429x/stm32f429x-can.ads b/stm32f429i/stm32f429x/stm32f429x-can.ads index bf58794..7374316 100644 --- a/stm32f429i/stm32f429x/stm32f429x-can.ads +++ b/stm32f429i/stm32f429x/stm32f429x-can.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.CAN is -- Registers -- --------------- - ------------------ - -- MCR_Register -- - ------------------ - subtype MCR_INRQ_Field is STM32F429x.Bit; subtype MCR_SLEEP_Field is STM32F429x.Bit; subtype MCR_TXFP_Field is STM32F429x.Bit; @@ -54,7 +52,7 @@ package STM32F429x.CAN is -- unspecified Reserved_17_31 : STM32F429x.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MCR_Register use record INRQ at 0 range 0 .. 0; @@ -71,10 +69,6 @@ package STM32F429x.CAN is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------ - -- MSR_Register -- - ------------------ - subtype MSR_INAK_Field is STM32F429x.Bit; subtype MSR_SLAK_Field is STM32F429x.Bit; subtype MSR_ERRI_Field is STM32F429x.Bit; @@ -87,9 +81,9 @@ package STM32F429x.CAN is -- master status register type MSR_Register is record - -- INAK + -- Read-only. INAK INAK : MSR_INAK_Field := 16#0#; - -- SLAK + -- Read-only. SLAK SLAK : MSR_SLAK_Field := 16#1#; -- ERRI ERRI : MSR_ERRI_Field := 16#0#; @@ -99,18 +93,18 @@ package STM32F429x.CAN is SLAKI : MSR_SLAKI_Field := 16#0#; -- unspecified Reserved_5_7 : STM32F429x.UInt3 := 16#0#; - -- TXM + -- Read-only. TXM TXM : MSR_TXM_Field := 16#0#; - -- RXM + -- Read-only. RXM RXM : MSR_RXM_Field := 16#0#; - -- SAMP + -- Read-only. SAMP SAMP : MSR_SAMP_Field := 16#1#; - -- RX + -- Read-only. RX RX : MSR_RX_Field := 16#1#; -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MSR_Register use record INAK at 0 range 0 .. 0; @@ -126,10 +120,6 @@ package STM32F429x.CAN is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- TSR_Register -- - ------------------ - subtype TSR_RQCP0_Field is STM32F429x.Bit; subtype TSR_TXOK0_Field is STM32F429x.Bit; subtype TSR_ALST0_Field is STM32F429x.Bit; @@ -146,11 +136,6 @@ package STM32F429x.CAN is subtype TSR_TERR2_Field is STM32F429x.Bit; subtype TSR_ABRQ2_Field is STM32F429x.Bit; subtype TSR_CODE_Field is STM32F429x.UInt2; - - ------------- - -- TSR.TME -- - ------------- - -- TSR_TME array element subtype TSR_TME_Element is STM32F429x.Bit; @@ -178,10 +163,6 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 2; end record; - ------------- - -- TSR.LOW -- - ------------- - -- TSR_LOW array element subtype TSR_LOW_Element is STM32F429x.Bit; @@ -247,14 +228,14 @@ package STM32F429x.CAN is Reserved_20_22 : STM32F429x.UInt3 := 16#0#; -- ABRQ2 ABRQ2 : TSR_ABRQ2_Field := 16#0#; - -- CODE + -- Read-only. CODE CODE : TSR_CODE_Field := 16#0#; - -- Lowest priority flag for mailbox 0 + -- Read-only. Lowest priority flag for mailbox 0 TME : TSR_TME_Field := (As_Array => False, Val => 16#1#); - -- Lowest priority flag for mailbox 0 + -- Read-only. Lowest priority flag for mailbox 0 LOW : TSR_LOW_Field := (As_Array => False, Val => 16#0#); end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TSR_Register use record RQCP0 at 0 range 0 .. 0; @@ -280,10 +261,6 @@ package STM32F429x.CAN is LOW at 0 range 29 .. 31; end record; - ------------------- - -- RF0R_Register -- - ------------------- - subtype RF0R_FMP0_Field is STM32F429x.UInt2; subtype RF0R_FULL0_Field is STM32F429x.Bit; subtype RF0R_FOVR0_Field is STM32F429x.Bit; @@ -291,7 +268,7 @@ package STM32F429x.CAN is -- receive FIFO 0 register type RF0R_Register is record - -- FMP0 + -- Read-only. FMP0 FMP0 : RF0R_FMP0_Field := 16#0#; -- unspecified Reserved_2_2 : STM32F429x.Bit := 16#0#; @@ -304,7 +281,7 @@ package STM32F429x.CAN is -- unspecified Reserved_6_31 : STM32F429x.UInt26 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RF0R_Register use record FMP0 at 0 range 0 .. 1; @@ -315,10 +292,6 @@ package STM32F429x.CAN is Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------- - -- RF1R_Register -- - ------------------- - subtype RF1R_FMP1_Field is STM32F429x.UInt2; subtype RF1R_FULL1_Field is STM32F429x.Bit; subtype RF1R_FOVR1_Field is STM32F429x.Bit; @@ -326,7 +299,7 @@ package STM32F429x.CAN is -- receive FIFO 1 register type RF1R_Register is record - -- FMP1 + -- Read-only. FMP1 FMP1 : RF1R_FMP1_Field := 16#0#; -- unspecified Reserved_2_2 : STM32F429x.Bit := 16#0#; @@ -339,7 +312,7 @@ package STM32F429x.CAN is -- unspecified Reserved_6_31 : STM32F429x.UInt26 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RF1R_Register use record FMP1 at 0 range 0 .. 1; @@ -350,10 +323,6 @@ package STM32F429x.CAN is Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - subtype IER_TMEIE_Field is STM32F429x.Bit; subtype IER_FMPIE0_Field is STM32F429x.Bit; subtype IER_FFIE0_Field is STM32F429x.Bit; @@ -406,7 +375,7 @@ package STM32F429x.CAN is -- unspecified Reserved_18_31 : STM32F429x.UInt14 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IER_Register use record TMEIE at 0 range 0 .. 0; @@ -428,10 +397,6 @@ package STM32F429x.CAN is Reserved_18_31 at 0 range 18 .. 31; end record; - ------------------ - -- ESR_Register -- - ------------------ - subtype ESR_EWGF_Field is STM32F429x.Bit; subtype ESR_EPVF_Field is STM32F429x.Bit; subtype ESR_BOFF_Field is STM32F429x.Bit; @@ -441,11 +406,11 @@ package STM32F429x.CAN is -- interrupt enable register type ESR_Register is record - -- EWGF + -- Read-only. EWGF EWGF : ESR_EWGF_Field := 16#0#; - -- EPVF + -- Read-only. EPVF EPVF : ESR_EPVF_Field := 16#0#; - -- BOFF + -- Read-only. BOFF BOFF : ESR_BOFF_Field := 16#0#; -- unspecified Reserved_3_3 : STM32F429x.Bit := 16#0#; @@ -453,12 +418,12 @@ package STM32F429x.CAN is LEC : ESR_LEC_Field := 16#0#; -- unspecified Reserved_7_15 : STM32F429x.UInt9 := 16#0#; - -- TEC + -- Read-only. TEC TEC : ESR_TEC_Field := 16#0#; - -- REC + -- Read-only. REC REC : ESR_REC_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ESR_Register use record EWGF at 0 range 0 .. 0; @@ -471,10 +436,6 @@ package STM32F429x.CAN is REC at 0 range 24 .. 31; end record; - ------------------ - -- BTR_Register -- - ------------------ - subtype BTR_BRP_Field is STM32F429x.UInt10; subtype BTR_TS1_Field is STM32F429x.UInt4; subtype BTR_TS2_Field is STM32F429x.UInt3; @@ -503,7 +464,7 @@ package STM32F429x.CAN is -- SILM SILM : BTR_SILM_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BTR_Register use record BRP at 0 range 0 .. 9; @@ -517,10 +478,6 @@ package STM32F429x.CAN is SILM at 0 range 31 .. 31; end record; - ------------------- - -- TI0R_Register -- - ------------------- - subtype TI0R_TXRQ_Field is STM32F429x.Bit; subtype TI0R_RTR_Field is STM32F429x.Bit; subtype TI0R_IDE_Field is STM32F429x.Bit; @@ -540,7 +497,7 @@ package STM32F429x.CAN is -- STID STID : TI0R_STID_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TI0R_Register use record TXRQ at 0 range 0 .. 0; @@ -550,13 +507,9 @@ package STM32F429x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- TDT0R_Register -- - -------------------- - subtype TDT0R_DLC_Field is STM32F429x.UInt4; subtype TDT0R_TGT_Field is STM32F429x.Bit; - subtype TDT0R_TIME_Field is STM32F429x.Short; + subtype TDT0R_TIME_Field is STM32F429x.UInt16; -- mailbox data length control and time stamp register type TDT0R_Register is record @@ -571,7 +524,7 @@ package STM32F429x.CAN is -- TIME TIME : TDT0R_TIME_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TDT0R_Register use record DLC at 0 range 0 .. 3; @@ -581,10 +534,6 @@ package STM32F429x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- TDL0R_Register -- - -------------------- - -- TDL0R_DATA array element subtype TDL0R_DATA_Element is STM32F429x.Byte; @@ -599,13 +548,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : TDL0R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDL0R_Register use record @@ -613,15 +562,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- TDH0R_Register -- - -------------------- - -- TDH0R_DATA array element subtype TDH0R_DATA_Element is STM32F429x.Byte; -- TDH0R_DATA array - type TDH0R_DATA_Field_Array is array (0 .. 3) of TDH0R_DATA_Element + type TDH0R_DATA_Field_Array is array (4 .. 7) of TDH0R_DATA_Element with Component_Size => 8, Size => 32; -- mailbox data high register @@ -631,13 +576,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : TDH0R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDH0R_Register use record @@ -645,10 +590,6 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- TI1R_Register -- - ------------------- - subtype TI1R_TXRQ_Field is STM32F429x.Bit; subtype TI1R_RTR_Field is STM32F429x.Bit; subtype TI1R_IDE_Field is STM32F429x.Bit; @@ -668,7 +609,7 @@ package STM32F429x.CAN is -- STID STID : TI1R_STID_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TI1R_Register use record TXRQ at 0 range 0 .. 0; @@ -678,13 +619,9 @@ package STM32F429x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- TDT1R_Register -- - -------------------- - subtype TDT1R_DLC_Field is STM32F429x.UInt4; subtype TDT1R_TGT_Field is STM32F429x.Bit; - subtype TDT1R_TIME_Field is STM32F429x.Short; + subtype TDT1R_TIME_Field is STM32F429x.UInt16; -- mailbox data length control and time stamp register type TDT1R_Register is record @@ -699,7 +636,7 @@ package STM32F429x.CAN is -- TIME TIME : TDT1R_TIME_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TDT1R_Register use record DLC at 0 range 0 .. 3; @@ -709,10 +646,6 @@ package STM32F429x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- TDL1R_Register -- - -------------------- - -- TDL1R_DATA array element subtype TDL1R_DATA_Element is STM32F429x.Byte; @@ -727,13 +660,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : TDL1R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDL1R_Register use record @@ -741,15 +674,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- TDH1R_Register -- - -------------------- - -- TDH1R_DATA array element subtype TDH1R_DATA_Element is STM32F429x.Byte; -- TDH1R_DATA array - type TDH1R_DATA_Field_Array is array (0 .. 3) of TDH1R_DATA_Element + type TDH1R_DATA_Field_Array is array (4 .. 7) of TDH1R_DATA_Element with Component_Size => 8, Size => 32; -- mailbox data high register @@ -759,13 +688,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : TDH1R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDH1R_Register use record @@ -773,10 +702,6 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- TI2R_Register -- - ------------------- - subtype TI2R_TXRQ_Field is STM32F429x.Bit; subtype TI2R_RTR_Field is STM32F429x.Bit; subtype TI2R_IDE_Field is STM32F429x.Bit; @@ -796,7 +721,7 @@ package STM32F429x.CAN is -- STID STID : TI2R_STID_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TI2R_Register use record TXRQ at 0 range 0 .. 0; @@ -806,13 +731,9 @@ package STM32F429x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- TDT2R_Register -- - -------------------- - subtype TDT2R_DLC_Field is STM32F429x.UInt4; subtype TDT2R_TGT_Field is STM32F429x.Bit; - subtype TDT2R_TIME_Field is STM32F429x.Short; + subtype TDT2R_TIME_Field is STM32F429x.UInt16; -- mailbox data length control and time stamp register type TDT2R_Register is record @@ -827,7 +748,7 @@ package STM32F429x.CAN is -- TIME TIME : TDT2R_TIME_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TDT2R_Register use record DLC at 0 range 0 .. 3; @@ -837,10 +758,6 @@ package STM32F429x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- TDL2R_Register -- - -------------------- - -- TDL2R_DATA array element subtype TDL2R_DATA_Element is STM32F429x.Byte; @@ -855,13 +772,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : TDL2R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDL2R_Register use record @@ -869,15 +786,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- TDH2R_Register -- - -------------------- - -- TDH2R_DATA array element subtype TDH2R_DATA_Element is STM32F429x.Byte; -- TDH2R_DATA array - type TDH2R_DATA_Field_Array is array (0 .. 3) of TDH2R_DATA_Element + type TDH2R_DATA_Field_Array is array (4 .. 7) of TDH2R_DATA_Element with Component_Size => 8, Size => 32; -- mailbox data high register @@ -887,13 +800,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : TDH2R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for TDH2R_Register use record @@ -901,10 +814,6 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- RI0R_Register -- - ------------------- - subtype RI0R_RTR_Field is STM32F429x.Bit; subtype RI0R_IDE_Field is STM32F429x.Bit; subtype RI0R_EXID_Field is STM32F429x.UInt18; @@ -914,16 +823,16 @@ package STM32F429x.CAN is type RI0R_Register is record -- unspecified Reserved_0_0 : STM32F429x.Bit; - -- RTR + -- Read-only. RTR RTR : RI0R_RTR_Field; - -- IDE + -- Read-only. IDE IDE : RI0R_IDE_Field; - -- EXID + -- Read-only. EXID EXID : RI0R_EXID_Field; - -- STID + -- Read-only. STID STID : RI0R_STID_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RI0R_Register use record Reserved_0_0 at 0 range 0 .. 0; @@ -933,26 +842,22 @@ package STM32F429x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- RDT0R_Register -- - -------------------- - subtype RDT0R_DLC_Field is STM32F429x.UInt4; subtype RDT0R_FMI_Field is STM32F429x.Byte; - subtype RDT0R_TIME_Field is STM32F429x.Short; + subtype RDT0R_TIME_Field is STM32F429x.UInt16; -- mailbox data high register type RDT0R_Register is record - -- DLC + -- Read-only. DLC DLC : RDT0R_DLC_Field; -- unspecified Reserved_4_7 : STM32F429x.UInt4; - -- FMI + -- Read-only. FMI FMI : RDT0R_FMI_Field; - -- TIME + -- Read-only. TIME TIME : RDT0R_TIME_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RDT0R_Register use record DLC at 0 range 0 .. 3; @@ -961,10 +866,6 @@ package STM32F429x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- RDL0R_Register -- - -------------------- - -- RDL0R_DATA array element subtype RDL0R_DATA_Element is STM32F429x.Byte; @@ -979,13 +880,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : RDL0R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for RDL0R_Register use record @@ -993,15 +894,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- RDH0R_Register -- - -------------------- - -- RDH0R_DATA array element subtype RDH0R_DATA_Element is STM32F429x.Byte; -- RDH0R_DATA array - type RDH0R_DATA_Field_Array is array (0 .. 3) of RDH0R_DATA_Element + type RDH0R_DATA_Field_Array is array (4 .. 7) of RDH0R_DATA_Element with Component_Size => 8, Size => 32; -- receive FIFO mailbox data high register @@ -1011,13 +908,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : RDH0R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for RDH0R_Register use record @@ -1025,10 +922,6 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- RI1R_Register -- - ------------------- - subtype RI1R_RTR_Field is STM32F429x.Bit; subtype RI1R_IDE_Field is STM32F429x.Bit; subtype RI1R_EXID_Field is STM32F429x.UInt18; @@ -1038,16 +931,16 @@ package STM32F429x.CAN is type RI1R_Register is record -- unspecified Reserved_0_0 : STM32F429x.Bit; - -- RTR + -- Read-only. RTR RTR : RI1R_RTR_Field; - -- IDE + -- Read-only. IDE IDE : RI1R_IDE_Field; - -- EXID + -- Read-only. EXID EXID : RI1R_EXID_Field; - -- STID + -- Read-only. STID STID : RI1R_STID_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RI1R_Register use record Reserved_0_0 at 0 range 0 .. 0; @@ -1057,26 +950,22 @@ package STM32F429x.CAN is STID at 0 range 21 .. 31; end record; - -------------------- - -- RDT1R_Register -- - -------------------- - subtype RDT1R_DLC_Field is STM32F429x.UInt4; subtype RDT1R_FMI_Field is STM32F429x.Byte; - subtype RDT1R_TIME_Field is STM32F429x.Short; + subtype RDT1R_TIME_Field is STM32F429x.UInt16; -- mailbox data high register type RDT1R_Register is record - -- DLC + -- Read-only. DLC DLC : RDT1R_DLC_Field; -- unspecified Reserved_4_7 : STM32F429x.UInt4; - -- FMI + -- Read-only. FMI FMI : RDT1R_FMI_Field; - -- TIME + -- Read-only. TIME TIME : RDT1R_TIME_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RDT1R_Register use record DLC at 0 range 0 .. 3; @@ -1085,10 +974,6 @@ package STM32F429x.CAN is TIME at 0 range 16 .. 31; end record; - -------------------- - -- RDL1R_Register -- - -------------------- - -- RDL1R_DATA array element subtype RDL1R_DATA_Element is STM32F429x.Byte; @@ -1103,13 +988,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : RDL1R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for RDL1R_Register use record @@ -1117,15 +1002,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - -------------------- - -- RDH1R_Register -- - -------------------- - -- RDH1R_DATA array element subtype RDH1R_DATA_Element is STM32F429x.Byte; -- RDH1R_DATA array - type RDH1R_DATA_Field_Array is array (0 .. 3) of RDH1R_DATA_Element + type RDH1R_DATA_Field_Array is array (4 .. 7) of RDH1R_DATA_Element with Component_Size => 8, Size => 32; -- mailbox data high register @@ -1135,13 +1016,13 @@ package STM32F429x.CAN is case As_Array is when False => -- DATA as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- DATA as an array Arr : RDH1R_DATA_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for RDH1R_Register use record @@ -1149,10 +1030,6 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- FMR_Register -- - ------------------ - subtype FMR_FINIT_Field is STM32F429x.Bit; subtype FMR_CAN2SB_Field is STM32F429x.UInt6; @@ -1167,7 +1044,7 @@ package STM32F429x.CAN is -- unspecified Reserved_14_31 : STM32F429x.UInt18 := 16#A870#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FMR_Register use record FINIT at 0 range 0 .. 0; @@ -1176,14 +1053,6 @@ package STM32F429x.CAN is Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------- - -- FM1R_Register -- - ------------------- - - -------------- - -- FM1R.FBM -- - -------------- - -- FM1R_FBM array element subtype FM1R_FBM_Element is STM32F429x.Bit; @@ -1218,21 +1087,13 @@ package STM32F429x.CAN is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FM1R_Register use record FBM at 0 range 0 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- FS1R_Register -- - ------------------- - - -------------- - -- FS1R.FSC -- - -------------- - -- FS1R_FSC array element subtype FS1R_FSC_Element is STM32F429x.Bit; @@ -1267,21 +1128,13 @@ package STM32F429x.CAN is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FS1R_Register use record FSC at 0 range 0 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - -------------------- - -- FFA1R_Register -- - -------------------- - - --------------- - -- FFA1R.FFA -- - --------------- - -- FFA1R_FFA array element subtype FFA1R_FFA_Element is STM32F429x.Bit; @@ -1316,21 +1169,13 @@ package STM32F429x.CAN is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FFA1R_Register use record FFA at 0 range 0 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- FA1R_Register -- - ------------------- - - --------------- - -- FA1R.FACT -- - --------------- - -- FA1R_FACT array element subtype FA1R_FACT_Element is STM32F429x.Bit; @@ -1365,22 +1210,18 @@ package STM32F429x.CAN is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FA1R_Register use record FACT at 0 range 0 .. 27; Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------ - -- F0R_Register -- - ------------------ + -- F0R_FB array element + subtype F0R_FB_Element is STM32F429x.Bit; - -- F0R1_FB array element - subtype F0R1_FB_Element is STM32F429x.Bit; - - -- F0R1_FB array - type F0R1_FB_Field_Array is array (0 .. 31) of F0R1_FB_Element + -- F0R_FB array + type F0R_FB_Field_Array is array (0 .. 31) of F0R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 0 register 1 @@ -1390,13 +1231,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F0R1_FB_Field_Array; + Arr : F0R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F0R_Register use record @@ -1404,15 +1245,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F1R_Register -- - ------------------ - - -- F1R1_FB array element - subtype F1R1_FB_Element is STM32F429x.Bit; + -- F1R_FB array element + subtype F1R_FB_Element is STM32F429x.Bit; - -- F1R1_FB array - type F1R1_FB_Field_Array is array (0 .. 31) of F1R1_FB_Element + -- F1R_FB array + type F1R_FB_Field_Array is array (0 .. 31) of F1R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 1 register 1 @@ -1422,13 +1259,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F1R1_FB_Field_Array; + Arr : F1R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F1R_Register use record @@ -1436,15 +1273,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F2R_Register -- - ------------------ + -- F2R_FB array element + subtype F2R_FB_Element is STM32F429x.Bit; - -- F2R1_FB array element - subtype F2R1_FB_Element is STM32F429x.Bit; - - -- F2R1_FB array - type F2R1_FB_Field_Array is array (0 .. 31) of F2R1_FB_Element + -- F2R_FB array + type F2R_FB_Field_Array is array (0 .. 31) of F2R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 2 register 1 @@ -1454,13 +1287,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F2R1_FB_Field_Array; + Arr : F2R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F2R_Register use record @@ -1468,15 +1301,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F3R_Register -- - ------------------ - - -- F3R1_FB array element - subtype F3R1_FB_Element is STM32F429x.Bit; + -- F3R_FB array element + subtype F3R_FB_Element is STM32F429x.Bit; - -- F3R1_FB array - type F3R1_FB_Field_Array is array (0 .. 31) of F3R1_FB_Element + -- F3R_FB array + type F3R_FB_Field_Array is array (0 .. 31) of F3R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 3 register 1 @@ -1486,13 +1315,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F3R1_FB_Field_Array; + Arr : F3R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F3R_Register use record @@ -1500,15 +1329,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F4R_Register -- - ------------------ - - -- F4R1_FB array element - subtype F4R1_FB_Element is STM32F429x.Bit; + -- F4R_FB array element + subtype F4R_FB_Element is STM32F429x.Bit; - -- F4R1_FB array - type F4R1_FB_Field_Array is array (0 .. 31) of F4R1_FB_Element + -- F4R_FB array + type F4R_FB_Field_Array is array (0 .. 31) of F4R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 4 register 1 @@ -1518,13 +1343,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F4R1_FB_Field_Array; + Arr : F4R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F4R_Register use record @@ -1532,15 +1357,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F5R_Register -- - ------------------ + -- F5R_FB array element + subtype F5R_FB_Element is STM32F429x.Bit; - -- F5R1_FB array element - subtype F5R1_FB_Element is STM32F429x.Bit; - - -- F5R1_FB array - type F5R1_FB_Field_Array is array (0 .. 31) of F5R1_FB_Element + -- F5R_FB array + type F5R_FB_Field_Array is array (0 .. 31) of F5R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 5 register 1 @@ -1550,13 +1371,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F5R1_FB_Field_Array; + Arr : F5R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F5R_Register use record @@ -1564,15 +1385,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F6R_Register -- - ------------------ - - -- F6R1_FB array element - subtype F6R1_FB_Element is STM32F429x.Bit; + -- F6R_FB array element + subtype F6R_FB_Element is STM32F429x.Bit; - -- F6R1_FB array - type F6R1_FB_Field_Array is array (0 .. 31) of F6R1_FB_Element + -- F6R_FB array + type F6R_FB_Field_Array is array (0 .. 31) of F6R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 6 register 1 @@ -1582,13 +1399,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F6R1_FB_Field_Array; + Arr : F6R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F6R_Register use record @@ -1596,15 +1413,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F7R_Register -- - ------------------ + -- F7R_FB array element + subtype F7R_FB_Element is STM32F429x.Bit; - -- F7R1_FB array element - subtype F7R1_FB_Element is STM32F429x.Bit; - - -- F7R1_FB array - type F7R1_FB_Field_Array is array (0 .. 31) of F7R1_FB_Element + -- F7R_FB array + type F7R_FB_Field_Array is array (0 .. 31) of F7R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 7 register 1 @@ -1614,13 +1427,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F7R1_FB_Field_Array; + Arr : F7R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F7R_Register use record @@ -1628,15 +1441,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F8R_Register -- - ------------------ - - -- F8R1_FB array element - subtype F8R1_FB_Element is STM32F429x.Bit; + -- F8R_FB array element + subtype F8R_FB_Element is STM32F429x.Bit; - -- F8R1_FB array - type F8R1_FB_Field_Array is array (0 .. 31) of F8R1_FB_Element + -- F8R_FB array + type F8R_FB_Field_Array is array (0 .. 31) of F8R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 8 register 1 @@ -1646,13 +1455,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F8R1_FB_Field_Array; + Arr : F8R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F8R_Register use record @@ -1660,15 +1469,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------ - -- F9R_Register -- - ------------------ - - -- F9R1_FB array element - subtype F9R1_FB_Element is STM32F429x.Bit; + -- F9R_FB array element + subtype F9R_FB_Element is STM32F429x.Bit; - -- F9R1_FB array - type F9R1_FB_Field_Array is array (0 .. 31) of F9R1_FB_Element + -- F9R_FB array + type F9R_FB_Field_Array is array (0 .. 31) of F9R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 9 register 1 @@ -1678,13 +1483,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F9R1_FB_Field_Array; + Arr : F9R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F9R_Register use record @@ -1692,15 +1497,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F10R_Register -- - ------------------- + -- F10R_FB array element + subtype F10R_FB_Element is STM32F429x.Bit; - -- F10R1_FB array element - subtype F10R1_FB_Element is STM32F429x.Bit; - - -- F10R1_FB array - type F10R1_FB_Field_Array is array (0 .. 31) of F10R1_FB_Element + -- F10R_FB array + type F10R_FB_Field_Array is array (0 .. 31) of F10R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 10 register 1 @@ -1710,13 +1511,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F10R1_FB_Field_Array; + Arr : F10R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F10R_Register use record @@ -1724,15 +1525,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F11R_Register -- - ------------------- - - -- F11R1_FB array element - subtype F11R1_FB_Element is STM32F429x.Bit; + -- F11R_FB array element + subtype F11R_FB_Element is STM32F429x.Bit; - -- F11R1_FB array - type F11R1_FB_Field_Array is array (0 .. 31) of F11R1_FB_Element + -- F11R_FB array + type F11R_FB_Field_Array is array (0 .. 31) of F11R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 11 register 1 @@ -1742,13 +1539,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F11R1_FB_Field_Array; + Arr : F11R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F11R_Register use record @@ -1756,15 +1553,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F12R_Register -- - ------------------- - - -- F12R1_FB array element - subtype F12R1_FB_Element is STM32F429x.Bit; + -- F12R_FB array element + subtype F12R_FB_Element is STM32F429x.Bit; - -- F12R1_FB array - type F12R1_FB_Field_Array is array (0 .. 31) of F12R1_FB_Element + -- F12R_FB array + type F12R_FB_Field_Array is array (0 .. 31) of F12R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 4 register 1 @@ -1774,13 +1567,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F12R1_FB_Field_Array; + Arr : F12R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F12R_Register use record @@ -1788,15 +1581,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F13R_Register -- - ------------------- + -- F13R_FB array element + subtype F13R_FB_Element is STM32F429x.Bit; - -- F13R1_FB array element - subtype F13R1_FB_Element is STM32F429x.Bit; - - -- F13R1_FB array - type F13R1_FB_Field_Array is array (0 .. 31) of F13R1_FB_Element + -- F13R_FB array + type F13R_FB_Field_Array is array (0 .. 31) of F13R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 13 register 1 @@ -1806,13 +1595,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F13R1_FB_Field_Array; + Arr : F13R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F13R_Register use record @@ -1820,15 +1609,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F14R_Register -- - ------------------- - - -- F14R1_FB array element - subtype F14R1_FB_Element is STM32F429x.Bit; + -- F14R_FB array element + subtype F14R_FB_Element is STM32F429x.Bit; - -- F14R1_FB array - type F14R1_FB_Field_Array is array (0 .. 31) of F14R1_FB_Element + -- F14R_FB array + type F14R_FB_Field_Array is array (0 .. 31) of F14R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 14 register 1 @@ -1838,13 +1623,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F14R1_FB_Field_Array; + Arr : F14R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F14R_Register use record @@ -1852,15 +1637,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F15R_Register -- - ------------------- - - -- F15R1_FB array element - subtype F15R1_FB_Element is STM32F429x.Bit; + -- F15R_FB array element + subtype F15R_FB_Element is STM32F429x.Bit; - -- F15R1_FB array - type F15R1_FB_Field_Array is array (0 .. 31) of F15R1_FB_Element + -- F15R_FB array + type F15R_FB_Field_Array is array (0 .. 31) of F15R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 15 register 1 @@ -1870,13 +1651,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F15R1_FB_Field_Array; + Arr : F15R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F15R_Register use record @@ -1884,15 +1665,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F16R_Register -- - ------------------- + -- F16R_FB array element + subtype F16R_FB_Element is STM32F429x.Bit; - -- F16R1_FB array element - subtype F16R1_FB_Element is STM32F429x.Bit; - - -- F16R1_FB array - type F16R1_FB_Field_Array is array (0 .. 31) of F16R1_FB_Element + -- F16R_FB array + type F16R_FB_Field_Array is array (0 .. 31) of F16R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 16 register 1 @@ -1902,13 +1679,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F16R1_FB_Field_Array; + Arr : F16R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F16R_Register use record @@ -1916,15 +1693,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F17R_Register -- - ------------------- - - -- F17R1_FB array element - subtype F17R1_FB_Element is STM32F429x.Bit; + -- F17R_FB array element + subtype F17R_FB_Element is STM32F429x.Bit; - -- F17R1_FB array - type F17R1_FB_Field_Array is array (0 .. 31) of F17R1_FB_Element + -- F17R_FB array + type F17R_FB_Field_Array is array (0 .. 31) of F17R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 17 register 1 @@ -1934,13 +1707,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F17R1_FB_Field_Array; + Arr : F17R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F17R_Register use record @@ -1948,15 +1721,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F18R_Register -- - ------------------- + -- F18R_FB array element + subtype F18R_FB_Element is STM32F429x.Bit; - -- F18R1_FB array element - subtype F18R1_FB_Element is STM32F429x.Bit; - - -- F18R1_FB array - type F18R1_FB_Field_Array is array (0 .. 31) of F18R1_FB_Element + -- F18R_FB array + type F18R_FB_Field_Array is array (0 .. 31) of F18R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 18 register 1 @@ -1966,13 +1735,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F18R1_FB_Field_Array; + Arr : F18R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F18R_Register use record @@ -1980,15 +1749,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F19R_Register -- - ------------------- - - -- F19R1_FB array element - subtype F19R1_FB_Element is STM32F429x.Bit; + -- F19R_FB array element + subtype F19R_FB_Element is STM32F429x.Bit; - -- F19R1_FB array - type F19R1_FB_Field_Array is array (0 .. 31) of F19R1_FB_Element + -- F19R_FB array + type F19R_FB_Field_Array is array (0 .. 31) of F19R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 19 register 1 @@ -1998,13 +1763,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F19R1_FB_Field_Array; + Arr : F19R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F19R_Register use record @@ -2012,15 +1777,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F20R_Register -- - ------------------- - - -- F20R1_FB array element - subtype F20R1_FB_Element is STM32F429x.Bit; + -- F20R_FB array element + subtype F20R_FB_Element is STM32F429x.Bit; - -- F20R1_FB array - type F20R1_FB_Field_Array is array (0 .. 31) of F20R1_FB_Element + -- F20R_FB array + type F20R_FB_Field_Array is array (0 .. 31) of F20R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 20 register 1 @@ -2030,13 +1791,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F20R1_FB_Field_Array; + Arr : F20R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F20R_Register use record @@ -2044,15 +1805,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F21R_Register -- - ------------------- + -- F21R_FB array element + subtype F21R_FB_Element is STM32F429x.Bit; - -- F21R1_FB array element - subtype F21R1_FB_Element is STM32F429x.Bit; - - -- F21R1_FB array - type F21R1_FB_Field_Array is array (0 .. 31) of F21R1_FB_Element + -- F21R_FB array + type F21R_FB_Field_Array is array (0 .. 31) of F21R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 21 register 1 @@ -2062,13 +1819,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F21R1_FB_Field_Array; + Arr : F21R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F21R_Register use record @@ -2076,15 +1833,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F22R_Register -- - ------------------- - - -- F22R1_FB array element - subtype F22R1_FB_Element is STM32F429x.Bit; + -- F22R_FB array element + subtype F22R_FB_Element is STM32F429x.Bit; - -- F22R1_FB array - type F22R1_FB_Field_Array is array (0 .. 31) of F22R1_FB_Element + -- F22R_FB array + type F22R_FB_Field_Array is array (0 .. 31) of F22R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 22 register 1 @@ -2094,13 +1847,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F22R1_FB_Field_Array; + Arr : F22R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F22R_Register use record @@ -2108,15 +1861,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F23R_Register -- - ------------------- + -- F23R_FB array element + subtype F23R_FB_Element is STM32F429x.Bit; - -- F23R1_FB array element - subtype F23R1_FB_Element is STM32F429x.Bit; - - -- F23R1_FB array - type F23R1_FB_Field_Array is array (0 .. 31) of F23R1_FB_Element + -- F23R_FB array + type F23R_FB_Field_Array is array (0 .. 31) of F23R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 23 register 1 @@ -2126,13 +1875,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F23R1_FB_Field_Array; + Arr : F23R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F23R_Register use record @@ -2140,15 +1889,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F24R_Register -- - ------------------- - - -- F24R1_FB array element - subtype F24R1_FB_Element is STM32F429x.Bit; + -- F24R_FB array element + subtype F24R_FB_Element is STM32F429x.Bit; - -- F24R1_FB array - type F24R1_FB_Field_Array is array (0 .. 31) of F24R1_FB_Element + -- F24R_FB array + type F24R_FB_Field_Array is array (0 .. 31) of F24R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 24 register 1 @@ -2158,13 +1903,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F24R1_FB_Field_Array; + Arr : F24R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F24R_Register use record @@ -2172,15 +1917,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F25R_Register -- - ------------------- - - -- F25R1_FB array element - subtype F25R1_FB_Element is STM32F429x.Bit; + -- F25R_FB array element + subtype F25R_FB_Element is STM32F429x.Bit; - -- F25R1_FB array - type F25R1_FB_Field_Array is array (0 .. 31) of F25R1_FB_Element + -- F25R_FB array + type F25R_FB_Field_Array is array (0 .. 31) of F25R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 25 register 1 @@ -2190,13 +1931,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F25R1_FB_Field_Array; + Arr : F25R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F25R_Register use record @@ -2204,15 +1945,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F26R_Register -- - ------------------- + -- F26R_FB array element + subtype F26R_FB_Element is STM32F429x.Bit; - -- F26R1_FB array element - subtype F26R1_FB_Element is STM32F429x.Bit; - - -- F26R1_FB array - type F26R1_FB_Field_Array is array (0 .. 31) of F26R1_FB_Element + -- F26R_FB array + type F26R_FB_Field_Array is array (0 .. 31) of F26R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 26 register 1 @@ -2222,13 +1959,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F26R1_FB_Field_Array; + Arr : F26R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F26R_Register use record @@ -2236,15 +1973,11 @@ package STM32F429x.CAN is Arr at 0 range 0 .. 31; end record; - ------------------- - -- F27R_Register -- - ------------------- - - -- F27R1_FB array element - subtype F27R1_FB_Element is STM32F429x.Bit; + -- F27R_FB array element + subtype F27R_FB_Element is STM32F429x.Bit; - -- F27R1_FB array - type F27R1_FB_Field_Array is array (0 .. 31) of F27R1_FB_Element + -- F27R_FB array + type F27R_FB_Field_Array is array (0 .. 31) of F27R_FB_Element with Component_Size => 1, Size => 32; -- Filter bank 27 register 1 @@ -2254,13 +1987,13 @@ package STM32F429x.CAN is case As_Array is when False => -- FB as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- FB as an array - Arr : F27R1_FB_Field_Array; + Arr : F27R_FB_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for F27R_Register use record @@ -2275,284 +2008,373 @@ package STM32F429x.CAN is -- Controller area network type CAN_Peripheral is record -- master control register - MCR : MCR_Register; + MCR : aliased MCR_Register; + pragma Volatile_Full_Access (MCR); -- master status register - MSR : MSR_Register; + MSR : aliased MSR_Register; + pragma Volatile_Full_Access (MSR); -- transmit status register - TSR : TSR_Register; + TSR : aliased TSR_Register; + pragma Volatile_Full_Access (TSR); -- receive FIFO 0 register - RF0R : RF0R_Register; + RF0R : aliased RF0R_Register; + pragma Volatile_Full_Access (RF0R); -- receive FIFO 1 register - RF1R : RF1R_Register; + RF1R : aliased RF1R_Register; + pragma Volatile_Full_Access (RF1R); -- interrupt enable register - IER : IER_Register; + IER : aliased IER_Register; + pragma Volatile_Full_Access (IER); -- interrupt enable register - ESR : ESR_Register; + ESR : aliased ESR_Register; + pragma Volatile_Full_Access (ESR); -- bit timing register - BTR : BTR_Register; + BTR : aliased BTR_Register; + pragma Volatile_Full_Access (BTR); -- TX mailbox identifier register - TI0R : TI0R_Register; + TI0R : aliased TI0R_Register; + pragma Volatile_Full_Access (TI0R); -- mailbox data length control and time stamp register - TDT0R : TDT0R_Register; + TDT0R : aliased TDT0R_Register; + pragma Volatile_Full_Access (TDT0R); -- mailbox data low register - TDL0R : TDL0R_Register; + TDL0R : aliased TDL0R_Register; + pragma Volatile_Full_Access (TDL0R); -- mailbox data high register - TDH0R : TDH0R_Register; + TDH0R : aliased TDH0R_Register; + pragma Volatile_Full_Access (TDH0R); -- mailbox identifier register - TI1R : TI1R_Register; + TI1R : aliased TI1R_Register; + pragma Volatile_Full_Access (TI1R); -- mailbox data length control and time stamp register - TDT1R : TDT1R_Register; + TDT1R : aliased TDT1R_Register; + pragma Volatile_Full_Access (TDT1R); -- mailbox data low register - TDL1R : TDL1R_Register; + TDL1R : aliased TDL1R_Register; + pragma Volatile_Full_Access (TDL1R); -- mailbox data high register - TDH1R : TDH1R_Register; + TDH1R : aliased TDH1R_Register; + pragma Volatile_Full_Access (TDH1R); -- mailbox identifier register - TI2R : TI2R_Register; + TI2R : aliased TI2R_Register; + pragma Volatile_Full_Access (TI2R); -- mailbox data length control and time stamp register - TDT2R : TDT2R_Register; + TDT2R : aliased TDT2R_Register; + pragma Volatile_Full_Access (TDT2R); -- mailbox data low register - TDL2R : TDL2R_Register; + TDL2R : aliased TDL2R_Register; + pragma Volatile_Full_Access (TDL2R); -- mailbox data high register - TDH2R : TDH2R_Register; + TDH2R : aliased TDH2R_Register; + pragma Volatile_Full_Access (TDH2R); -- receive FIFO mailbox identifier register - RI0R : RI0R_Register; + RI0R : aliased RI0R_Register; + pragma Volatile_Full_Access (RI0R); -- mailbox data high register - RDT0R : RDT0R_Register; + RDT0R : aliased RDT0R_Register; + pragma Volatile_Full_Access (RDT0R); -- mailbox data high register - RDL0R : RDL0R_Register; + RDL0R : aliased RDL0R_Register; + pragma Volatile_Full_Access (RDL0R); -- receive FIFO mailbox data high register - RDH0R : RDH0R_Register; + RDH0R : aliased RDH0R_Register; + pragma Volatile_Full_Access (RDH0R); -- mailbox data high register - RI1R : RI1R_Register; + RI1R : aliased RI1R_Register; + pragma Volatile_Full_Access (RI1R); -- mailbox data high register - RDT1R : RDT1R_Register; + RDT1R : aliased RDT1R_Register; + pragma Volatile_Full_Access (RDT1R); -- mailbox data high register - RDL1R : RDL1R_Register; + RDL1R : aliased RDL1R_Register; + pragma Volatile_Full_Access (RDL1R); -- mailbox data high register - RDH1R : RDH1R_Register; + RDH1R : aliased RDH1R_Register; + pragma Volatile_Full_Access (RDH1R); -- filter master register - FMR : FMR_Register; + FMR : aliased FMR_Register; + pragma Volatile_Full_Access (FMR); -- filter mode register - FM1R : FM1R_Register; + FM1R : aliased FM1R_Register; + pragma Volatile_Full_Access (FM1R); -- filter scale register - FS1R : FS1R_Register; + FS1R : aliased FS1R_Register; + pragma Volatile_Full_Access (FS1R); -- filter FIFO assignment register - FFA1R : FFA1R_Register; + FFA1R : aliased FFA1R_Register; + pragma Volatile_Full_Access (FFA1R); -- filter activation register - FA1R : FA1R_Register; + FA1R : aliased FA1R_Register; + pragma Volatile_Full_Access (FA1R); -- Filter bank 0 register 1 - F0R1 : F0R_Register; + F0R1 : aliased F0R_Register; + pragma Volatile_Full_Access (F0R1); -- Filter bank 0 register 2 - F0R2 : F0R_Register; + F0R2 : aliased F0R_Register; + pragma Volatile_Full_Access (F0R2); -- Filter bank 1 register 1 - F1R1 : F1R_Register; + F1R1 : aliased F1R_Register; + pragma Volatile_Full_Access (F1R1); -- Filter bank 1 register 2 - F1R2 : F1R_Register; + F1R2 : aliased F1R_Register; + pragma Volatile_Full_Access (F1R2); -- Filter bank 2 register 1 - F2R1 : F2R_Register; + F2R1 : aliased F2R_Register; + pragma Volatile_Full_Access (F2R1); -- Filter bank 2 register 2 - F2R2 : F2R_Register; + F2R2 : aliased F2R_Register; + pragma Volatile_Full_Access (F2R2); -- Filter bank 3 register 1 - F3R1 : F3R_Register; + F3R1 : aliased F3R_Register; + pragma Volatile_Full_Access (F3R1); -- Filter bank 3 register 2 - F3R2 : F3R_Register; + F3R2 : aliased F3R_Register; + pragma Volatile_Full_Access (F3R2); -- Filter bank 4 register 1 - F4R1 : F4R_Register; + F4R1 : aliased F4R_Register; + pragma Volatile_Full_Access (F4R1); -- Filter bank 4 register 2 - F4R2 : F4R_Register; + F4R2 : aliased F4R_Register; + pragma Volatile_Full_Access (F4R2); -- Filter bank 5 register 1 - F5R1 : F5R_Register; + F5R1 : aliased F5R_Register; + pragma Volatile_Full_Access (F5R1); -- Filter bank 5 register 2 - F5R2 : F5R_Register; + F5R2 : aliased F5R_Register; + pragma Volatile_Full_Access (F5R2); -- Filter bank 6 register 1 - F6R1 : F6R_Register; + F6R1 : aliased F6R_Register; + pragma Volatile_Full_Access (F6R1); -- Filter bank 6 register 2 - F6R2 : F6R_Register; + F6R2 : aliased F6R_Register; + pragma Volatile_Full_Access (F6R2); -- Filter bank 7 register 1 - F7R1 : F7R_Register; + F7R1 : aliased F7R_Register; + pragma Volatile_Full_Access (F7R1); -- Filter bank 7 register 2 - F7R2 : F7R_Register; + F7R2 : aliased F7R_Register; + pragma Volatile_Full_Access (F7R2); -- Filter bank 8 register 1 - F8R1 : F8R_Register; + F8R1 : aliased F8R_Register; + pragma Volatile_Full_Access (F8R1); -- Filter bank 8 register 2 - F8R2 : F8R_Register; + F8R2 : aliased F8R_Register; + pragma Volatile_Full_Access (F8R2); -- Filter bank 9 register 1 - F9R1 : F9R_Register; + F9R1 : aliased F9R_Register; + pragma Volatile_Full_Access (F9R1); -- Filter bank 9 register 2 - F9R2 : F9R_Register; + F9R2 : aliased F9R_Register; + pragma Volatile_Full_Access (F9R2); -- Filter bank 10 register 1 - F10R1 : F10R_Register; + F10R1 : aliased F10R_Register; + pragma Volatile_Full_Access (F10R1); -- Filter bank 10 register 2 - F10R2 : F10R_Register; + F10R2 : aliased F10R_Register; + pragma Volatile_Full_Access (F10R2); -- Filter bank 11 register 1 - F11R1 : F11R_Register; + F11R1 : aliased F11R_Register; + pragma Volatile_Full_Access (F11R1); -- Filter bank 11 register 2 - F11R2 : F11R_Register; + F11R2 : aliased F11R_Register; + pragma Volatile_Full_Access (F11R2); -- Filter bank 4 register 1 - F12R1 : F12R_Register; + F12R1 : aliased F12R_Register; + pragma Volatile_Full_Access (F12R1); -- Filter bank 12 register 2 - F12R2 : F12R_Register; + F12R2 : aliased F12R_Register; + pragma Volatile_Full_Access (F12R2); -- Filter bank 13 register 1 - F13R1 : F13R_Register; + F13R1 : aliased F13R_Register; + pragma Volatile_Full_Access (F13R1); -- Filter bank 13 register 2 - F13R2 : F13R_Register; + F13R2 : aliased F13R_Register; + pragma Volatile_Full_Access (F13R2); -- Filter bank 14 register 1 - F14R1 : F14R_Register; + F14R1 : aliased F14R_Register; + pragma Volatile_Full_Access (F14R1); -- Filter bank 14 register 2 - F14R2 : F14R_Register; + F14R2 : aliased F14R_Register; + pragma Volatile_Full_Access (F14R2); -- Filter bank 15 register 1 - F15R1 : F15R_Register; + F15R1 : aliased F15R_Register; + pragma Volatile_Full_Access (F15R1); -- Filter bank 15 register 2 - F15R2 : F15R_Register; + F15R2 : aliased F15R_Register; + pragma Volatile_Full_Access (F15R2); -- Filter bank 16 register 1 - F16R1 : F16R_Register; + F16R1 : aliased F16R_Register; + pragma Volatile_Full_Access (F16R1); -- Filter bank 16 register 2 - F16R2 : F16R_Register; + F16R2 : aliased F16R_Register; + pragma Volatile_Full_Access (F16R2); -- Filter bank 17 register 1 - F17R1 : F17R_Register; + F17R1 : aliased F17R_Register; + pragma Volatile_Full_Access (F17R1); -- Filter bank 17 register 2 - F17R2 : F17R_Register; + F17R2 : aliased F17R_Register; + pragma Volatile_Full_Access (F17R2); -- Filter bank 18 register 1 - F18R1 : F18R_Register; + F18R1 : aliased F18R_Register; + pragma Volatile_Full_Access (F18R1); -- Filter bank 18 register 2 - F18R2 : F18R_Register; + F18R2 : aliased F18R_Register; + pragma Volatile_Full_Access (F18R2); -- Filter bank 19 register 1 - F19R1 : F19R_Register; + F19R1 : aliased F19R_Register; + pragma Volatile_Full_Access (F19R1); -- Filter bank 19 register 2 - F19R2 : F19R_Register; + F19R2 : aliased F19R_Register; + pragma Volatile_Full_Access (F19R2); -- Filter bank 20 register 1 - F20R1 : F20R_Register; + F20R1 : aliased F20R_Register; + pragma Volatile_Full_Access (F20R1); -- Filter bank 20 register 2 - F20R2 : F20R_Register; + F20R2 : aliased F20R_Register; + pragma Volatile_Full_Access (F20R2); -- Filter bank 21 register 1 - F21R1 : F21R_Register; + F21R1 : aliased F21R_Register; + pragma Volatile_Full_Access (F21R1); -- Filter bank 21 register 2 - F21R2 : F21R_Register; + F21R2 : aliased F21R_Register; + pragma Volatile_Full_Access (F21R2); -- Filter bank 22 register 1 - F22R1 : F22R_Register; + F22R1 : aliased F22R_Register; + pragma Volatile_Full_Access (F22R1); -- Filter bank 22 register 2 - F22R2 : F22R_Register; + F22R2 : aliased F22R_Register; + pragma Volatile_Full_Access (F22R2); -- Filter bank 23 register 1 - F23R1 : F23R_Register; + F23R1 : aliased F23R_Register; + pragma Volatile_Full_Access (F23R1); -- Filter bank 23 register 2 - F23R2 : F23R_Register; + F23R2 : aliased F23R_Register; + pragma Volatile_Full_Access (F23R2); -- Filter bank 24 register 1 - F24R1 : F24R_Register; + F24R1 : aliased F24R_Register; + pragma Volatile_Full_Access (F24R1); -- Filter bank 24 register 2 - F24R2 : F24R_Register; + F24R2 : aliased F24R_Register; + pragma Volatile_Full_Access (F24R2); -- Filter bank 25 register 1 - F25R1 : F25R_Register; + F25R1 : aliased F25R_Register; + pragma Volatile_Full_Access (F25R1); -- Filter bank 25 register 2 - F25R2 : F25R_Register; + F25R2 : aliased F25R_Register; + pragma Volatile_Full_Access (F25R2); -- Filter bank 26 register 1 - F26R1 : F26R_Register; + F26R1 : aliased F26R_Register; + pragma Volatile_Full_Access (F26R1); -- Filter bank 26 register 2 - F26R2 : F26R_Register; + F26R2 : aliased F26R_Register; + pragma Volatile_Full_Access (F26R2); -- Filter bank 27 register 1 - F27R1 : F27R_Register; + F27R1 : aliased F27R_Register; + pragma Volatile_Full_Access (F27R1); -- Filter bank 27 register 2 - F27R2 : F27R_Register; + F27R2 : aliased F27R_Register; + pragma Volatile_Full_Access (F27R2); end record with Volatile; for CAN_Peripheral use record - MCR at 0 range 0 .. 31; - MSR at 4 range 0 .. 31; - TSR at 8 range 0 .. 31; - RF0R at 12 range 0 .. 31; - RF1R at 16 range 0 .. 31; - IER at 20 range 0 .. 31; - ESR at 24 range 0 .. 31; - BTR at 28 range 0 .. 31; - TI0R at 384 range 0 .. 31; - TDT0R at 388 range 0 .. 31; - TDL0R at 392 range 0 .. 31; - TDH0R at 396 range 0 .. 31; - TI1R at 400 range 0 .. 31; - TDT1R at 404 range 0 .. 31; - TDL1R at 408 range 0 .. 31; - TDH1R at 412 range 0 .. 31; - TI2R at 416 range 0 .. 31; - TDT2R at 420 range 0 .. 31; - TDL2R at 424 range 0 .. 31; - TDH2R at 428 range 0 .. 31; - RI0R at 432 range 0 .. 31; - RDT0R at 436 range 0 .. 31; - RDL0R at 440 range 0 .. 31; - RDH0R at 444 range 0 .. 31; - RI1R at 448 range 0 .. 31; - RDT1R at 452 range 0 .. 31; - RDL1R at 456 range 0 .. 31; - RDH1R at 460 range 0 .. 31; - FMR at 512 range 0 .. 31; - FM1R at 516 range 0 .. 31; - FS1R at 524 range 0 .. 31; - FFA1R at 532 range 0 .. 31; - FA1R at 540 range 0 .. 31; - F0R1 at 576 range 0 .. 31; - F0R2 at 580 range 0 .. 31; - F1R1 at 584 range 0 .. 31; - F1R2 at 588 range 0 .. 31; - F2R1 at 592 range 0 .. 31; - F2R2 at 596 range 0 .. 31; - F3R1 at 600 range 0 .. 31; - F3R2 at 604 range 0 .. 31; - F4R1 at 608 range 0 .. 31; - F4R2 at 612 range 0 .. 31; - F5R1 at 616 range 0 .. 31; - F5R2 at 620 range 0 .. 31; - F6R1 at 624 range 0 .. 31; - F6R2 at 628 range 0 .. 31; - F7R1 at 632 range 0 .. 31; - F7R2 at 636 range 0 .. 31; - F8R1 at 640 range 0 .. 31; - F8R2 at 644 range 0 .. 31; - F9R1 at 648 range 0 .. 31; - F9R2 at 652 range 0 .. 31; - F10R1 at 656 range 0 .. 31; - F10R2 at 660 range 0 .. 31; - F11R1 at 664 range 0 .. 31; - F11R2 at 668 range 0 .. 31; - F12R1 at 672 range 0 .. 31; - F12R2 at 676 range 0 .. 31; - F13R1 at 680 range 0 .. 31; - F13R2 at 684 range 0 .. 31; - F14R1 at 688 range 0 .. 31; - F14R2 at 692 range 0 .. 31; - F15R1 at 696 range 0 .. 31; - F15R2 at 700 range 0 .. 31; - F16R1 at 704 range 0 .. 31; - F16R2 at 708 range 0 .. 31; - F17R1 at 712 range 0 .. 31; - F17R2 at 716 range 0 .. 31; - F18R1 at 720 range 0 .. 31; - F18R2 at 724 range 0 .. 31; - F19R1 at 728 range 0 .. 31; - F19R2 at 732 range 0 .. 31; - F20R1 at 736 range 0 .. 31; - F20R2 at 740 range 0 .. 31; - F21R1 at 744 range 0 .. 31; - F21R2 at 748 range 0 .. 31; - F22R1 at 752 range 0 .. 31; - F22R2 at 756 range 0 .. 31; - F23R1 at 760 range 0 .. 31; - F23R2 at 764 range 0 .. 31; - F24R1 at 768 range 0 .. 31; - F24R2 at 772 range 0 .. 31; - F25R1 at 776 range 0 .. 31; - F25R2 at 780 range 0 .. 31; - F26R1 at 784 range 0 .. 31; - F26R2 at 788 range 0 .. 31; - F27R1 at 792 range 0 .. 31; - F27R2 at 796 range 0 .. 31; + MCR at 16#0# range 0 .. 31; + MSR at 16#4# range 0 .. 31; + TSR at 16#8# range 0 .. 31; + RF0R at 16#C# range 0 .. 31; + RF1R at 16#10# range 0 .. 31; + IER at 16#14# range 0 .. 31; + ESR at 16#18# range 0 .. 31; + BTR at 16#1C# range 0 .. 31; + TI0R at 16#180# range 0 .. 31; + TDT0R at 16#184# range 0 .. 31; + TDL0R at 16#188# range 0 .. 31; + TDH0R at 16#18C# range 0 .. 31; + TI1R at 16#190# range 0 .. 31; + TDT1R at 16#194# range 0 .. 31; + TDL1R at 16#198# range 0 .. 31; + TDH1R at 16#19C# range 0 .. 31; + TI2R at 16#1A0# range 0 .. 31; + TDT2R at 16#1A4# range 0 .. 31; + TDL2R at 16#1A8# range 0 .. 31; + TDH2R at 16#1AC# range 0 .. 31; + RI0R at 16#1B0# range 0 .. 31; + RDT0R at 16#1B4# range 0 .. 31; + RDL0R at 16#1B8# range 0 .. 31; + RDH0R at 16#1BC# range 0 .. 31; + RI1R at 16#1C0# range 0 .. 31; + RDT1R at 16#1C4# range 0 .. 31; + RDL1R at 16#1C8# range 0 .. 31; + RDH1R at 16#1CC# range 0 .. 31; + FMR at 16#200# range 0 .. 31; + FM1R at 16#204# range 0 .. 31; + FS1R at 16#20C# range 0 .. 31; + FFA1R at 16#214# range 0 .. 31; + FA1R at 16#21C# range 0 .. 31; + F0R1 at 16#240# range 0 .. 31; + F0R2 at 16#244# range 0 .. 31; + F1R1 at 16#248# range 0 .. 31; + F1R2 at 16#24C# range 0 .. 31; + F2R1 at 16#250# range 0 .. 31; + F2R2 at 16#254# range 0 .. 31; + F3R1 at 16#258# range 0 .. 31; + F3R2 at 16#25C# range 0 .. 31; + F4R1 at 16#260# range 0 .. 31; + F4R2 at 16#264# range 0 .. 31; + F5R1 at 16#268# range 0 .. 31; + F5R2 at 16#26C# range 0 .. 31; + F6R1 at 16#270# range 0 .. 31; + F6R2 at 16#274# range 0 .. 31; + F7R1 at 16#278# range 0 .. 31; + F7R2 at 16#27C# range 0 .. 31; + F8R1 at 16#280# range 0 .. 31; + F8R2 at 16#284# range 0 .. 31; + F9R1 at 16#288# range 0 .. 31; + F9R2 at 16#28C# range 0 .. 31; + F10R1 at 16#290# range 0 .. 31; + F10R2 at 16#294# range 0 .. 31; + F11R1 at 16#298# range 0 .. 31; + F11R2 at 16#29C# range 0 .. 31; + F12R1 at 16#2A0# range 0 .. 31; + F12R2 at 16#2A4# range 0 .. 31; + F13R1 at 16#2A8# range 0 .. 31; + F13R2 at 16#2AC# range 0 .. 31; + F14R1 at 16#2B0# range 0 .. 31; + F14R2 at 16#2B4# range 0 .. 31; + F15R1 at 16#2B8# range 0 .. 31; + F15R2 at 16#2BC# range 0 .. 31; + F16R1 at 16#2C0# range 0 .. 31; + F16R2 at 16#2C4# range 0 .. 31; + F17R1 at 16#2C8# range 0 .. 31; + F17R2 at 16#2CC# range 0 .. 31; + F18R1 at 16#2D0# range 0 .. 31; + F18R2 at 16#2D4# range 0 .. 31; + F19R1 at 16#2D8# range 0 .. 31; + F19R2 at 16#2DC# range 0 .. 31; + F20R1 at 16#2E0# range 0 .. 31; + F20R2 at 16#2E4# range 0 .. 31; + F21R1 at 16#2E8# range 0 .. 31; + F21R2 at 16#2EC# range 0 .. 31; + F22R1 at 16#2F0# range 0 .. 31; + F22R2 at 16#2F4# range 0 .. 31; + F23R1 at 16#2F8# range 0 .. 31; + F23R2 at 16#2FC# range 0 .. 31; + F24R1 at 16#300# range 0 .. 31; + F24R2 at 16#304# range 0 .. 31; + F25R1 at 16#308# range 0 .. 31; + F25R2 at 16#30C# range 0 .. 31; + F26R1 at 16#310# range 0 .. 31; + F26R2 at 16#314# range 0 .. 31; + F27R1 at 16#318# range 0 .. 31; + F27R2 at 16#31C# range 0 .. 31; end record; -- Controller area network CAN1_Periph : aliased CAN_Peripheral - with Import, Address => System'To_Address (16#40006400#); + with Import, Address => CAN1_Base; -- Controller area network CAN2_Periph : aliased CAN_Peripheral - with Import, Address => System'To_Address (16#40006800#); + with Import, Address => CAN2_Base; end STM32F429x.CAN; diff --git a/stm32f429i/stm32f429x/stm32f429x-crc.ads b/stm32f429i/stm32f429x/stm32f429x-crc.ads index 66c6e1f..b550d71 100644 --- a/stm32f429i/stm32f429x/stm32f429x-crc.ads +++ b/stm32f429i/stm32f429x/stm32f429x-crc.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.CRC is -- Registers -- --------------- - ------------------ - -- IDR_Register -- - ------------------ - subtype IDR_IDR_Field is STM32F429x.Byte; -- Independent Data register @@ -25,27 +23,23 @@ package STM32F429x.CRC is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IDR_Register use record IDR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- CR_Register -- - ----------------- - subtype CR_CR_Field is STM32F429x.Bit; -- Control register type CR_Register is record - -- Control regidter + -- Write-only. Control regidter CR : CR_CR_Field := 16#0#; -- unspecified Reserved_1_31 : STM32F429x.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record CR at 0 range 0 .. 0; @@ -56,25 +50,27 @@ package STM32F429x.CRC is -- Peripherals -- ----------------- - -- Cryptographic processor + -- Cyclic Redundancy Check (CRC) unit type CRC_Peripheral is record -- Data register - DR : STM32F429x.Word; + DR : aliased STM32F429x.UInt32; -- Independent Data register - IDR : IDR_Register; + IDR : aliased IDR_Register; + pragma Volatile_Full_Access (IDR); -- Control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); end record with Volatile; for CRC_Peripheral use record - DR at 0 range 0 .. 31; - IDR at 4 range 0 .. 31; - CR at 8 range 0 .. 31; + DR at 16#0# range 0 .. 31; + IDR at 16#4# range 0 .. 31; + CR at 16#8# range 0 .. 31; end record; - -- Cryptographic processor + -- Cyclic Redundancy Check (CRC) unit CRC_Periph : aliased CRC_Peripheral - with Import, Address => System'To_Address (16#40023000#); + with Import, Address => CRC_Base; end STM32F429x.CRC; diff --git a/stm32f429i/stm32f429x/stm32f429x-dac.ads b/stm32f429i/stm32f429x/stm32f429x-dac.ads index 4118300..aef79b6 100644 --- a/stm32f429i/stm32f429x/stm32f429x-dac.ads +++ b/stm32f429i/stm32f429x/stm32f429x-dac.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.DAC is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_EN1_Field is STM32F429x.Bit; subtype CR_BOFF1_Field is STM32F429x.Bit; subtype CR_TEN1_Field is STM32F429x.Bit; @@ -72,7 +70,7 @@ package STM32F429x.DAC is -- unspecified Reserved_30_31 : STM32F429x.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record EN1 at 0 range 0 .. 0; @@ -95,19 +93,11 @@ package STM32F429x.DAC is Reserved_30_31 at 0 range 30 .. 31; end record; - ---------------------- - -- SWTRIGR_Register -- - ---------------------- - - -------------------- - -- SWTRIGR.SWTRIG -- - -------------------- - -- SWTRIGR_SWTRIG array element subtype SWTRIGR_SWTRIG_Element is STM32F429x.Bit; -- SWTRIGR_SWTRIG array - type SWTRIGR_SWTRIG_Field_Array is array (0 .. 1) + type SWTRIGR_SWTRIG_Field_Array is array (1 .. 2) of SWTRIGR_SWTRIG_Element with Component_Size => 1, Size => 2; @@ -133,85 +123,120 @@ package STM32F429x.DAC is -- software trigger register type SWTRIGR_Register is record - -- DAC channel1 software trigger + -- Write-only. DAC channel1 software trigger SWTRIG : SWTRIGR_SWTRIG_Field := (As_Array => False, Val => 16#0#); -- unspecified Reserved_2_31 : STM32F429x.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SWTRIGR_Register use record SWTRIG at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - --------------------- - -- DHR12R_Register -- - --------------------- - subtype DHR12R1_DACC1DHR_Field is STM32F429x.UInt12; -- channel1 12-bit right-aligned data holding register - type DHR12R_Register is record + type DHR12R1_Register is record -- DAC channel1 12-bit right-aligned data DACC1DHR : DHR12R1_DACC1DHR_Field := 16#0#; -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DHR12R_Register use record + for DHR12R1_Register use record DACC1DHR at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - --------------------- - -- DHR12L_Register -- - --------------------- - subtype DHR12L1_DACC1DHR_Field is STM32F429x.UInt12; -- channel1 12-bit left aligned data holding register - type DHR12L_Register is record + type DHR12L1_Register is record -- unspecified Reserved_0_3 : STM32F429x.UInt4 := 16#0#; -- DAC channel1 12-bit left-aligned data DACC1DHR : DHR12L1_DACC1DHR_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DHR12L_Register use record + for DHR12L1_Register use record Reserved_0_3 at 0 range 0 .. 3; DACC1DHR at 0 range 4 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- DHR8R_Register -- - -------------------- - subtype DHR8R1_DACC1DHR_Field is STM32F429x.Byte; -- channel1 8-bit right aligned data holding register - type DHR8R_Register is record + type DHR8R1_Register is record -- DAC channel1 8-bit right-aligned data DACC1DHR : DHR8R1_DACC1DHR_Field := 16#0#; -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DHR8R_Register use record + for DHR8R1_Register use record DACC1DHR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ---------------------- - -- DHR12RD_Register -- - ---------------------- + subtype DHR12R2_DACC2DHR_Field is STM32F429x.UInt12; + + -- channel2 12-bit right aligned data holding register + type DHR12R2_Register is record + -- DAC channel2 12-bit right-aligned data + DACC2DHR : DHR12R2_DACC2DHR_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DHR12R2_Register use record + DACC2DHR at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype DHR12L2_DACC2DHR_Field is STM32F429x.UInt12; + + -- channel2 12-bit left aligned data holding register + type DHR12L2_Register is record + -- unspecified + Reserved_0_3 : STM32F429x.UInt4 := 16#0#; + -- DAC channel2 12-bit left-aligned data + DACC2DHR : DHR12L2_DACC2DHR_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DHR12L2_Register use record + Reserved_0_3 at 0 range 0 .. 3; + DACC2DHR at 0 range 4 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DHR8R2_DACC2DHR_Field is STM32F429x.Byte; + + -- channel2 8-bit right-aligned data holding register + type DHR8R2_Register is record + -- DAC channel2 8-bit right-aligned data + DACC2DHR : DHR8R2_DACC2DHR_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DHR8R2_Register use record + DACC2DHR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; subtype DHR12RD_DACC1DHR_Field is STM32F429x.UInt12; subtype DHR12RD_DACC2DHR_Field is STM32F429x.UInt12; @@ -227,7 +252,7 @@ package STM32F429x.DAC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DHR12RD_Register use record DACC1DHR at 0 range 0 .. 11; @@ -236,10 +261,6 @@ package STM32F429x.DAC is Reserved_28_31 at 0 range 28 .. 31; end record; - ---------------------- - -- DHR12LD_Register -- - ---------------------- - subtype DHR12LD_DACC1DHR_Field is STM32F429x.UInt12; subtype DHR12LD_DACC2DHR_Field is STM32F429x.UInt12; @@ -254,7 +275,7 @@ package STM32F429x.DAC is -- DAC channel2 12-bit left-aligned data DACC2DHR : DHR12LD_DACC2DHR_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DHR12LD_Register use record Reserved_0_3 at 0 range 0 .. 3; @@ -263,10 +284,6 @@ package STM32F429x.DAC is DACC2DHR at 0 range 20 .. 31; end record; - --------------------- - -- DHR8RD_Register -- - --------------------- - subtype DHR8RD_DACC1DHR_Field is STM32F429x.Byte; subtype DHR8RD_DACC2DHR_Field is STM32F429x.Byte; @@ -277,9 +294,9 @@ package STM32F429x.DAC is -- DAC channel2 8-bit right-aligned data DACC2DHR : DHR8RD_DACC2DHR_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DHR8RD_Register use record DACC1DHR at 0 range 0 .. 7; @@ -287,29 +304,37 @@ package STM32F429x.DAC is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- DOR_Register -- - ------------------ - subtype DOR1_DACC1DOR_Field is STM32F429x.UInt12; -- channel1 data output register - type DOR_Register is record - -- DAC channel1 data output + type DOR1_Register is record + -- Read-only. DAC channel1 data output DACC1DOR : DOR1_DACC1DOR_Field; -- unspecified Reserved_12_31 : STM32F429x.UInt20; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOR_Register use record + for DOR1_Register use record DACC1DOR at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- + subtype DOR2_DACC2DOR_Field is STM32F429x.UInt12; + + -- channel2 data output register + type DOR2_Register is record + -- Read-only. DAC channel2 data output + DACC2DOR : DOR2_DACC2DOR_Field; + -- unspecified + Reserved_12_31 : STM32F429x.UInt20; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DOR2_Register use record + DACC2DOR at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; subtype SR_DMAUDR1_Field is STM32F429x.Bit; subtype SR_DMAUDR2_Field is STM32F429x.Bit; @@ -327,7 +352,7 @@ package STM32F429x.DAC is -- unspecified Reserved_30_31 : STM32F429x.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record Reserved_0_12 at 0 range 0 .. 12; @@ -344,55 +369,69 @@ package STM32F429x.DAC is -- Digital-to-analog converter type DAC_Peripheral is record -- control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- software trigger register - SWTRIGR : SWTRIGR_Register; + SWTRIGR : aliased SWTRIGR_Register; + pragma Volatile_Full_Access (SWTRIGR); -- channel1 12-bit right-aligned data holding register - DHR12R1 : DHR12R_Register; + DHR12R1 : aliased DHR12R1_Register; + pragma Volatile_Full_Access (DHR12R1); -- channel1 12-bit left aligned data holding register - DHR12L1 : DHR12L_Register; + DHR12L1 : aliased DHR12L1_Register; + pragma Volatile_Full_Access (DHR12L1); -- channel1 8-bit right aligned data holding register - DHR8R1 : DHR8R_Register; + DHR8R1 : aliased DHR8R1_Register; + pragma Volatile_Full_Access (DHR8R1); -- channel2 12-bit right aligned data holding register - DHR12R2 : DHR12R_Register; + DHR12R2 : aliased DHR12R2_Register; + pragma Volatile_Full_Access (DHR12R2); -- channel2 12-bit left aligned data holding register - DHR12L2 : DHR12L_Register; + DHR12L2 : aliased DHR12L2_Register; + pragma Volatile_Full_Access (DHR12L2); -- channel2 8-bit right-aligned data holding register - DHR8R2 : DHR8R_Register; + DHR8R2 : aliased DHR8R2_Register; + pragma Volatile_Full_Access (DHR8R2); -- Dual DAC 12-bit right-aligned data holding register - DHR12RD : DHR12RD_Register; + DHR12RD : aliased DHR12RD_Register; + pragma Volatile_Full_Access (DHR12RD); -- DUAL DAC 12-bit left aligned data holding register - DHR12LD : DHR12LD_Register; + DHR12LD : aliased DHR12LD_Register; + pragma Volatile_Full_Access (DHR12LD); -- DUAL DAC 8-bit right aligned data holding register - DHR8RD : DHR8RD_Register; + DHR8RD : aliased DHR8RD_Register; + pragma Volatile_Full_Access (DHR8RD); -- channel1 data output register - DOR1 : DOR_Register; + DOR1 : aliased DOR1_Register; + pragma Volatile_Full_Access (DOR1); -- channel2 data output register - DOR2 : DOR_Register; + DOR2 : aliased DOR2_Register; + pragma Volatile_Full_Access (DOR2); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; for DAC_Peripheral use record - CR at 0 range 0 .. 31; - SWTRIGR at 4 range 0 .. 31; - DHR12R1 at 8 range 0 .. 31; - DHR12L1 at 12 range 0 .. 31; - DHR8R1 at 16 range 0 .. 31; - DHR12R2 at 20 range 0 .. 31; - DHR12L2 at 24 range 0 .. 31; - DHR8R2 at 28 range 0 .. 31; - DHR12RD at 32 range 0 .. 31; - DHR12LD at 36 range 0 .. 31; - DHR8RD at 40 range 0 .. 31; - DOR1 at 44 range 0 .. 31; - DOR2 at 48 range 0 .. 31; - SR at 52 range 0 .. 31; + CR at 16#0# range 0 .. 31; + SWTRIGR at 16#4# range 0 .. 31; + DHR12R1 at 16#8# range 0 .. 31; + DHR12L1 at 16#C# range 0 .. 31; + DHR8R1 at 16#10# range 0 .. 31; + DHR12R2 at 16#14# range 0 .. 31; + DHR12L2 at 16#18# range 0 .. 31; + DHR8R2 at 16#1C# range 0 .. 31; + DHR12RD at 16#20# range 0 .. 31; + DHR12LD at 16#24# range 0 .. 31; + DHR8RD at 16#28# range 0 .. 31; + DOR1 at 16#2C# range 0 .. 31; + DOR2 at 16#30# range 0 .. 31; + SR at 16#34# range 0 .. 31; end record; -- Digital-to-analog converter DAC_Periph : aliased DAC_Peripheral - with Import, Address => System'To_Address (16#40007400#); + with Import, Address => DAC_Base; end STM32F429x.DAC; diff --git a/stm32f429i/stm32f429x/stm32f429x-dbg.ads b/stm32f429i/stm32f429x/stm32f429x-dbg.ads index a598066..3848cfa 100644 --- a/stm32f429i/stm32f429x/stm32f429x-dbg.ads +++ b/stm32f429i/stm32f429x/stm32f429x-dbg.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,23 +14,19 @@ package STM32F429x.DBG is -- Registers -- --------------- - ---------------------------- - -- DBGMCU_IDCODE_Register -- - ---------------------------- - subtype DBGMCU_IDCODE_DEV_ID_Field is STM32F429x.UInt12; - subtype DBGMCU_IDCODE_REV_ID_Field is STM32F429x.Short; + subtype DBGMCU_IDCODE_REV_ID_Field is STM32F429x.UInt16; -- IDCODE type DBGMCU_IDCODE_Register is record - -- DEV_ID + -- Read-only. DEV_ID DEV_ID : DBGMCU_IDCODE_DEV_ID_Field; -- unspecified Reserved_12_15 : STM32F429x.UInt4; - -- REV_ID + -- Read-only. REV_ID REV_ID : DBGMCU_IDCODE_REV_ID_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DBGMCU_IDCODE_Register use record DEV_ID at 0 range 0 .. 11; @@ -36,10 +34,6 @@ package STM32F429x.DBG is REV_ID at 0 range 16 .. 31; end record; - ------------------------ - -- DBGMCU_CR_Register -- - ------------------------ - subtype DBGMCU_CR_DBG_SLEEP_Field is STM32F429x.Bit; subtype DBGMCU_CR_DBG_STOP_Field is STM32F429x.Bit; subtype DBGMCU_CR_DBG_STANDBY_Field is STM32F429x.Bit; @@ -63,7 +57,7 @@ package STM32F429x.DBG is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DBGMCU_CR_Register use record DBG_SLEEP at 0 range 0 .. 0; @@ -75,10 +69,6 @@ package STM32F429x.DBG is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------------------- - -- DBGMCU_APB1_FZ_Register -- - ----------------------------- - subtype DBGMCU_APB1_FZ_DBG_TIM2_STOP_Field is STM32F429x.Bit; subtype DBGMCU_APB1_FZ_DBG_TIM3_STOP_Field is STM32F429x.Bit; subtype DBGMCU_APB1_FZ_DBG_TIM4_STOP_Field is STM32F429x.Bit; @@ -142,7 +132,7 @@ package STM32F429x.DBG is -- unspecified Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DBGMCU_APB1_FZ_Register use record DBG_TIM2_STOP at 0 range 0 .. 0; @@ -167,10 +157,6 @@ package STM32F429x.DBG is Reserved_27_31 at 0 range 27 .. 31; end record; - ----------------------------- - -- DBGMCU_APB2_FZ_Register -- - ----------------------------- - subtype DBGMCU_APB2_FZ_DBG_TIM1_STOP_Field is STM32F429x.Bit; subtype DBGMCU_APB2_FZ_DBG_TIM8_STOP_Field is STM32F429x.Bit; subtype DBGMCU_APB2_FZ_DBG_TIM9_STOP_Field is STM32F429x.Bit; @@ -194,7 +180,7 @@ package STM32F429x.DBG is -- unspecified Reserved_19_31 : STM32F429x.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DBGMCU_APB2_FZ_Register use record DBG_TIM1_STOP at 0 range 0 .. 0; @@ -213,25 +199,29 @@ package STM32F429x.DBG is -- Debug support type DBG_Peripheral is record -- IDCODE - DBGMCU_IDCODE : DBGMCU_IDCODE_Register; + DBGMCU_IDCODE : aliased DBGMCU_IDCODE_Register; + pragma Volatile_Full_Access (DBGMCU_IDCODE); -- Control Register - DBGMCU_CR : DBGMCU_CR_Register; + DBGMCU_CR : aliased DBGMCU_CR_Register; + pragma Volatile_Full_Access (DBGMCU_CR); -- Debug MCU APB1 Freeze registe - DBGMCU_APB1_FZ : DBGMCU_APB1_FZ_Register; + DBGMCU_APB1_FZ : aliased DBGMCU_APB1_FZ_Register; + pragma Volatile_Full_Access (DBGMCU_APB1_FZ); -- Debug MCU APB2 Freeze registe - DBGMCU_APB2_FZ : DBGMCU_APB2_FZ_Register; + DBGMCU_APB2_FZ : aliased DBGMCU_APB2_FZ_Register; + pragma Volatile_Full_Access (DBGMCU_APB2_FZ); end record with Volatile; for DBG_Peripheral use record - DBGMCU_IDCODE at 0 range 0 .. 31; - DBGMCU_CR at 4 range 0 .. 31; - DBGMCU_APB1_FZ at 8 range 0 .. 31; - DBGMCU_APB2_FZ at 12 range 0 .. 31; + DBGMCU_IDCODE at 16#0# range 0 .. 31; + DBGMCU_CR at 16#4# range 0 .. 31; + DBGMCU_APB1_FZ at 16#8# range 0 .. 31; + DBGMCU_APB2_FZ at 16#C# range 0 .. 31; end record; -- Debug support DBG_Periph : aliased DBG_Peripheral - with Import, Address => System'To_Address (16#E0042000#); + with Import, Address => DBG_Base; end STM32F429x.DBG; diff --git a/stm32f429i/stm32f429x/stm32f429x-dcmi.ads b/stm32f429i/stm32f429x/stm32f429x-dcmi.ads index ef651bb..467ccda 100644 --- a/stm32f429i/stm32f429x/stm32f429x-dcmi.ads +++ b/stm32f429i/stm32f429x/stm32f429x-dcmi.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.DCMI is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_CAPTURE_Field is STM32F429x.Bit; subtype CR_CM_Field is STM32F429x.Bit; subtype CR_CROP_Field is STM32F429x.Bit; @@ -57,7 +55,7 @@ package STM32F429x.DCMI is -- unspecified Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record CAPTURE at 0 range 0 .. 0; @@ -75,26 +73,22 @@ package STM32F429x.DCMI is Reserved_15_31 at 0 range 15 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_HSYNC_Field is STM32F429x.Bit; subtype SR_VSYNC_Field is STM32F429x.Bit; subtype SR_FNE_Field is STM32F429x.Bit; -- status register type SR_Register is record - -- HSYNC + -- Read-only. HSYNC HSYNC : SR_HSYNC_Field; - -- VSYNC + -- Read-only. VSYNC VSYNC : SR_VSYNC_Field; - -- FIFO not empty + -- Read-only. FIFO not empty FNE : SR_FNE_Field; -- unspecified Reserved_3_31 : STM32F429x.UInt29; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record HSYNC at 0 range 0 .. 0; @@ -103,10 +97,6 @@ package STM32F429x.DCMI is Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- RIS_Register -- - ------------------ - subtype RIS_FRAME_RIS_Field is STM32F429x.Bit; subtype RIS_OVR_RIS_Field is STM32F429x.Bit; subtype RIS_ERR_RIS_Field is STM32F429x.Bit; @@ -115,20 +105,20 @@ package STM32F429x.DCMI is -- raw interrupt status register type RIS_Register is record - -- Capture complete raw interrupt status + -- Read-only. Capture complete raw interrupt status FRAME_RIS : RIS_FRAME_RIS_Field; - -- Overrun raw interrupt status + -- Read-only. Overrun raw interrupt status OVR_RIS : RIS_OVR_RIS_Field; - -- Synchronization error raw interrupt status + -- Read-only. Synchronization error raw interrupt status ERR_RIS : RIS_ERR_RIS_Field; - -- VSYNC raw interrupt status + -- Read-only. VSYNC raw interrupt status VSYNC_RIS : RIS_VSYNC_RIS_Field; - -- Line raw interrupt status + -- Read-only. Line raw interrupt status LINE_RIS : RIS_LINE_RIS_Field; -- unspecified Reserved_5_31 : STM32F429x.UInt27; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RIS_Register use record FRAME_RIS at 0 range 0 .. 0; @@ -139,10 +129,6 @@ package STM32F429x.DCMI is Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - subtype IER_FRAME_IE_Field is STM32F429x.Bit; subtype IER_OVR_IE_Field is STM32F429x.Bit; subtype IER_ERR_IE_Field is STM32F429x.Bit; @@ -164,7 +150,7 @@ package STM32F429x.DCMI is -- unspecified Reserved_5_31 : STM32F429x.UInt27 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IER_Register use record FRAME_IE at 0 range 0 .. 0; @@ -175,10 +161,6 @@ package STM32F429x.DCMI is Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------ - -- MIS_Register -- - ------------------ - subtype MIS_FRAME_MIS_Field is STM32F429x.Bit; subtype MIS_OVR_MIS_Field is STM32F429x.Bit; subtype MIS_ERR_MIS_Field is STM32F429x.Bit; @@ -187,20 +169,20 @@ package STM32F429x.DCMI is -- masked interrupt status register type MIS_Register is record - -- Capture complete masked interrupt status + -- Read-only. Capture complete masked interrupt status FRAME_MIS : MIS_FRAME_MIS_Field; - -- Overrun masked interrupt status + -- Read-only. Overrun masked interrupt status OVR_MIS : MIS_OVR_MIS_Field; - -- Synchronization error masked interrupt status + -- Read-only. Synchronization error masked interrupt status ERR_MIS : MIS_ERR_MIS_Field; - -- VSYNC masked interrupt status + -- Read-only. VSYNC masked interrupt status VSYNC_MIS : MIS_VSYNC_MIS_Field; - -- Line masked interrupt status + -- Read-only. Line masked interrupt status LINE_MIS : MIS_LINE_MIS_Field; -- unspecified Reserved_5_31 : STM32F429x.UInt27; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MIS_Register use record FRAME_MIS at 0 range 0 .. 0; @@ -211,10 +193,6 @@ package STM32F429x.DCMI is Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------ - -- ICR_Register -- - ------------------ - subtype ICR_FRAME_ISC_Field is STM32F429x.Bit; subtype ICR_OVR_ISC_Field is STM32F429x.Bit; subtype ICR_ERR_ISC_Field is STM32F429x.Bit; @@ -223,20 +201,20 @@ package STM32F429x.DCMI is -- interrupt clear register type ICR_Register is record - -- Capture complete interrupt status clear + -- Write-only. Capture complete interrupt status clear FRAME_ISC : ICR_FRAME_ISC_Field := 16#0#; - -- Overrun interrupt status clear + -- Write-only. Overrun interrupt status clear OVR_ISC : ICR_OVR_ISC_Field := 16#0#; - -- Synchronization error interrupt status clear + -- Write-only. Synchronization error interrupt status clear ERR_ISC : ICR_ERR_ISC_Field := 16#0#; - -- Vertical synch interrupt status clear + -- Write-only. Vertical synch interrupt status clear VSYNC_ISC : ICR_VSYNC_ISC_Field := 16#0#; - -- line interrupt status clear + -- Write-only. line interrupt status clear LINE_ISC : ICR_LINE_ISC_Field := 16#0#; -- unspecified Reserved_5_31 : STM32F429x.UInt27 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ICR_Register use record FRAME_ISC at 0 range 0 .. 0; @@ -247,10 +225,6 @@ package STM32F429x.DCMI is Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------- - -- ESCR_Register -- - ------------------- - subtype ESCR_FSC_Field is STM32F429x.Byte; subtype ESCR_LSC_Field is STM32F429x.Byte; subtype ESCR_LEC_Field is STM32F429x.Byte; @@ -267,7 +241,7 @@ package STM32F429x.DCMI is -- Frame end delimiter code FEC : ESCR_FEC_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ESCR_Register use record FSC at 0 range 0 .. 7; @@ -276,10 +250,6 @@ package STM32F429x.DCMI is FEC at 0 range 24 .. 31; end record; - ------------------- - -- ESUR_Register -- - ------------------- - subtype ESUR_FSU_Field is STM32F429x.Byte; subtype ESUR_LSU_Field is STM32F429x.Byte; subtype ESUR_LEU_Field is STM32F429x.Byte; @@ -296,7 +266,7 @@ package STM32F429x.DCMI is -- Frame end delimiter unmask FEU : ESUR_FEU_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ESUR_Register use record FSU at 0 range 0 .. 7; @@ -305,10 +275,6 @@ package STM32F429x.DCMI is FEU at 0 range 24 .. 31; end record; - --------------------- - -- CWSTRT_Register -- - --------------------- - subtype CWSTRT_HOFFCNT_Field is STM32F429x.UInt14; subtype CWSTRT_VST_Field is STM32F429x.UInt13; @@ -323,7 +289,7 @@ package STM32F429x.DCMI is -- unspecified Reserved_29_31 : STM32F429x.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CWSTRT_Register use record HOFFCNT at 0 range 0 .. 13; @@ -332,10 +298,6 @@ package STM32F429x.DCMI is Reserved_29_31 at 0 range 29 .. 31; end record; - --------------------- - -- CWSIZE_Register -- - --------------------- - subtype CWSIZE_CAPCNT_Field is STM32F429x.UInt14; subtype CWSIZE_VLINE_Field is STM32F429x.UInt14; @@ -350,7 +312,7 @@ package STM32F429x.DCMI is -- unspecified Reserved_30_31 : STM32F429x.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CWSIZE_Register use record CAPCNT at 0 range 0 .. 13; @@ -359,10 +321,6 @@ package STM32F429x.DCMI is Reserved_30_31 at 0 range 30 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - -- DR_Byte array element subtype DR_Byte_Element is STM32F429x.Byte; @@ -377,13 +335,13 @@ package STM32F429x.DCMI is case As_Array is when False => -- Byte as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- Byte as an array Arr : DR_Byte_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record @@ -398,46 +356,57 @@ package STM32F429x.DCMI is -- Digital camera interface type DCMI_Peripheral is record -- control register 1 - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- raw interrupt status register - RIS : RIS_Register; + RIS : aliased RIS_Register; + pragma Volatile_Full_Access (RIS); -- interrupt enable register - IER : IER_Register; + IER : aliased IER_Register; + pragma Volatile_Full_Access (IER); -- masked interrupt status register - MIS : MIS_Register; + MIS : aliased MIS_Register; + pragma Volatile_Full_Access (MIS); -- interrupt clear register - ICR : ICR_Register; + ICR : aliased ICR_Register; + pragma Volatile_Full_Access (ICR); -- embedded synchronization code register - ESCR : ESCR_Register; + ESCR : aliased ESCR_Register; + pragma Volatile_Full_Access (ESCR); -- embedded synchronization unmask register - ESUR : ESUR_Register; + ESUR : aliased ESUR_Register; + pragma Volatile_Full_Access (ESUR); -- crop window start - CWSTRT : CWSTRT_Register; + CWSTRT : aliased CWSTRT_Register; + pragma Volatile_Full_Access (CWSTRT); -- crop window size - CWSIZE : CWSIZE_Register; + CWSIZE : aliased CWSIZE_Register; + pragma Volatile_Full_Access (CWSIZE); -- data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); end record with Volatile; for DCMI_Peripheral use record - CR at 0 range 0 .. 31; - SR at 4 range 0 .. 31; - RIS at 8 range 0 .. 31; - IER at 12 range 0 .. 31; - MIS at 16 range 0 .. 31; - ICR at 20 range 0 .. 31; - ESCR at 24 range 0 .. 31; - ESUR at 28 range 0 .. 31; - CWSTRT at 32 range 0 .. 31; - CWSIZE at 36 range 0 .. 31; - DR at 40 range 0 .. 31; + CR at 16#0# range 0 .. 31; + SR at 16#4# range 0 .. 31; + RIS at 16#8# range 0 .. 31; + IER at 16#C# range 0 .. 31; + MIS at 16#10# range 0 .. 31; + ICR at 16#14# range 0 .. 31; + ESCR at 16#18# range 0 .. 31; + ESUR at 16#1C# range 0 .. 31; + CWSTRT at 16#20# range 0 .. 31; + CWSIZE at 16#24# range 0 .. 31; + DR at 16#28# range 0 .. 31; end record; -- Digital camera interface DCMI_Periph : aliased DCMI_Peripheral - with Import, Address => System'To_Address (16#50050000#); + with Import, Address => DCMI_Base; end STM32F429x.DCMI; diff --git a/stm32f429i/stm32f429x/stm32f429x-dma.ads b/stm32f429i/stm32f429x/stm32f429x-dma.ads index 9bd1412..290bc81 100644 --- a/stm32f429i/stm32f429x/stm32f429x-dma.ads +++ b/stm32f429i/stm32f429x/stm32f429x-dma.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.DMA is -- Registers -- --------------- - ------------------- - -- LISR_Register -- - ------------------- - subtype LISR_FEIF0_Field is STM32F429x.Bit; subtype LISR_DMEIF0_Field is STM32F429x.Bit; subtype LISR_TEIF0_Field is STM32F429x.Bit; @@ -39,60 +37,60 @@ package STM32F429x.DMA is -- low interrupt status register type LISR_Register is record - -- Stream x FIFO error interrupt flag (x=3..0) + -- Read-only. Stream x FIFO error interrupt flag (x=3..0) FEIF0 : LISR_FEIF0_Field; -- unspecified Reserved_1_1 : STM32F429x.Bit; - -- Stream x direct mode error interrupt flag (x=3..0) + -- Read-only. Stream x direct mode error interrupt flag (x=3..0) DMEIF0 : LISR_DMEIF0_Field; - -- Stream x transfer error interrupt flag (x=3..0) + -- Read-only. Stream x transfer error interrupt flag (x=3..0) TEIF0 : LISR_TEIF0_Field; - -- Stream x half transfer interrupt flag (x=3..0) + -- Read-only. Stream x half transfer interrupt flag (x=3..0) HTIF0 : LISR_HTIF0_Field; - -- Stream x transfer complete interrupt flag (x = 3..0) + -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) TCIF0 : LISR_TCIF0_Field; - -- Stream x FIFO error interrupt flag (x=3..0) + -- Read-only. Stream x FIFO error interrupt flag (x=3..0) FEIF1 : LISR_FEIF1_Field; -- unspecified Reserved_7_7 : STM32F429x.Bit; - -- Stream x direct mode error interrupt flag (x=3..0) + -- Read-only. Stream x direct mode error interrupt flag (x=3..0) DMEIF1 : LISR_DMEIF1_Field; - -- Stream x transfer error interrupt flag (x=3..0) + -- Read-only. Stream x transfer error interrupt flag (x=3..0) TEIF1 : LISR_TEIF1_Field; - -- Stream x half transfer interrupt flag (x=3..0) + -- Read-only. Stream x half transfer interrupt flag (x=3..0) HTIF1 : LISR_HTIF1_Field; - -- Stream x transfer complete interrupt flag (x = 3..0) + -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) TCIF1 : LISR_TCIF1_Field; -- unspecified Reserved_12_15 : STM32F429x.UInt4; - -- Stream x FIFO error interrupt flag (x=3..0) + -- Read-only. Stream x FIFO error interrupt flag (x=3..0) FEIF2 : LISR_FEIF2_Field; -- unspecified Reserved_17_17 : STM32F429x.Bit; - -- Stream x direct mode error interrupt flag (x=3..0) + -- Read-only. Stream x direct mode error interrupt flag (x=3..0) DMEIF2 : LISR_DMEIF2_Field; - -- Stream x transfer error interrupt flag (x=3..0) + -- Read-only. Stream x transfer error interrupt flag (x=3..0) TEIF2 : LISR_TEIF2_Field; - -- Stream x half transfer interrupt flag (x=3..0) + -- Read-only. Stream x half transfer interrupt flag (x=3..0) HTIF2 : LISR_HTIF2_Field; - -- Stream x transfer complete interrupt flag (x = 3..0) + -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) TCIF2 : LISR_TCIF2_Field; - -- Stream x FIFO error interrupt flag (x=3..0) + -- Read-only. Stream x FIFO error interrupt flag (x=3..0) FEIF3 : LISR_FEIF3_Field; -- unspecified Reserved_23_23 : STM32F429x.Bit; - -- Stream x direct mode error interrupt flag (x=3..0) + -- Read-only. Stream x direct mode error interrupt flag (x=3..0) DMEIF3 : LISR_DMEIF3_Field; - -- Stream x transfer error interrupt flag (x=3..0) + -- Read-only. Stream x transfer error interrupt flag (x=3..0) TEIF3 : LISR_TEIF3_Field; - -- Stream x half transfer interrupt flag (x=3..0) + -- Read-only. Stream x half transfer interrupt flag (x=3..0) HTIF3 : LISR_HTIF3_Field; - -- Stream x transfer complete interrupt flag (x = 3..0) + -- Read-only. Stream x transfer complete interrupt flag (x = 3..0) TCIF3 : LISR_TCIF3_Field; -- unspecified Reserved_28_31 : STM32F429x.UInt4; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LISR_Register use record FEIF0 at 0 range 0 .. 0; @@ -123,10 +121,6 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- HISR_Register -- - ------------------- - subtype HISR_FEIF4_Field is STM32F429x.Bit; subtype HISR_DMEIF4_Field is STM32F429x.Bit; subtype HISR_TEIF4_Field is STM32F429x.Bit; @@ -150,60 +144,60 @@ package STM32F429x.DMA is -- high interrupt status register type HISR_Register is record - -- Stream x FIFO error interrupt flag (x=7..4) + -- Read-only. Stream x FIFO error interrupt flag (x=7..4) FEIF4 : HISR_FEIF4_Field; -- unspecified Reserved_1_1 : STM32F429x.Bit; - -- Stream x direct mode error interrupt flag (x=7..4) + -- Read-only. Stream x direct mode error interrupt flag (x=7..4) DMEIF4 : HISR_DMEIF4_Field; - -- Stream x transfer error interrupt flag (x=7..4) + -- Read-only. Stream x transfer error interrupt flag (x=7..4) TEIF4 : HISR_TEIF4_Field; - -- Stream x half transfer interrupt flag (x=7..4) + -- Read-only. Stream x half transfer interrupt flag (x=7..4) HTIF4 : HISR_HTIF4_Field; - -- Stream x transfer complete interrupt flag (x=7..4) + -- Read-only. Stream x transfer complete interrupt flag (x=7..4) TCIF4 : HISR_TCIF4_Field; - -- Stream x FIFO error interrupt flag (x=7..4) + -- Read-only. Stream x FIFO error interrupt flag (x=7..4) FEIF5 : HISR_FEIF5_Field; -- unspecified Reserved_7_7 : STM32F429x.Bit; - -- Stream x direct mode error interrupt flag (x=7..4) + -- Read-only. Stream x direct mode error interrupt flag (x=7..4) DMEIF5 : HISR_DMEIF5_Field; - -- Stream x transfer error interrupt flag (x=7..4) + -- Read-only. Stream x transfer error interrupt flag (x=7..4) TEIF5 : HISR_TEIF5_Field; - -- Stream x half transfer interrupt flag (x=7..4) + -- Read-only. Stream x half transfer interrupt flag (x=7..4) HTIF5 : HISR_HTIF5_Field; - -- Stream x transfer complete interrupt flag (x=7..4) + -- Read-only. Stream x transfer complete interrupt flag (x=7..4) TCIF5 : HISR_TCIF5_Field; -- unspecified Reserved_12_15 : STM32F429x.UInt4; - -- Stream x FIFO error interrupt flag (x=7..4) + -- Read-only. Stream x FIFO error interrupt flag (x=7..4) FEIF6 : HISR_FEIF6_Field; -- unspecified Reserved_17_17 : STM32F429x.Bit; - -- Stream x direct mode error interrupt flag (x=7..4) + -- Read-only. Stream x direct mode error interrupt flag (x=7..4) DMEIF6 : HISR_DMEIF6_Field; - -- Stream x transfer error interrupt flag (x=7..4) + -- Read-only. Stream x transfer error interrupt flag (x=7..4) TEIF6 : HISR_TEIF6_Field; - -- Stream x half transfer interrupt flag (x=7..4) + -- Read-only. Stream x half transfer interrupt flag (x=7..4) HTIF6 : HISR_HTIF6_Field; - -- Stream x transfer complete interrupt flag (x=7..4) + -- Read-only. Stream x transfer complete interrupt flag (x=7..4) TCIF6 : HISR_TCIF6_Field; - -- Stream x FIFO error interrupt flag (x=7..4) + -- Read-only. Stream x FIFO error interrupt flag (x=7..4) FEIF7 : HISR_FEIF7_Field; -- unspecified Reserved_23_23 : STM32F429x.Bit; - -- Stream x direct mode error interrupt flag (x=7..4) + -- Read-only. Stream x direct mode error interrupt flag (x=7..4) DMEIF7 : HISR_DMEIF7_Field; - -- Stream x transfer error interrupt flag (x=7..4) + -- Read-only. Stream x transfer error interrupt flag (x=7..4) TEIF7 : HISR_TEIF7_Field; - -- Stream x half transfer interrupt flag (x=7..4) + -- Read-only. Stream x half transfer interrupt flag (x=7..4) HTIF7 : HISR_HTIF7_Field; - -- Stream x transfer complete interrupt flag (x=7..4) + -- Read-only. Stream x transfer complete interrupt flag (x=7..4) TCIF7 : HISR_TCIF7_Field; -- unspecified Reserved_28_31 : STM32F429x.UInt4; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for HISR_Register use record FEIF4 at 0 range 0 .. 0; @@ -234,10 +228,6 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - -------------------- - -- LIFCR_Register -- - -------------------- - subtype LIFCR_CFEIF0_Field is STM32F429x.Bit; subtype LIFCR_CDMEIF0_Field is STM32F429x.Bit; subtype LIFCR_CTEIF0_Field is STM32F429x.Bit; @@ -314,7 +304,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LIFCR_Register use record CFEIF0 at 0 range 0 .. 0; @@ -345,10 +335,6 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - -------------------- - -- HIFCR_Register -- - -------------------- - subtype HIFCR_CFEIF4_Field is STM32F429x.Bit; subtype HIFCR_CDMEIF4_Field is STM32F429x.Bit; subtype HIFCR_CTEIF4_Field is STM32F429x.Bit; @@ -425,7 +411,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for HIFCR_Register use record CFEIF4 at 0 range 0 .. 0; @@ -456,10 +442,6 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- S0CR_Register -- - ------------------- - subtype S0CR_EN_Field is STM32F429x.Bit; subtype S0CR_DMEIE_Field is STM32F429x.Bit; subtype S0CR_TEIE_Field is STM32F429x.Bit; @@ -525,7 +507,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S0CR_Register use record EN at 0 range 0 .. 0; @@ -551,30 +533,22 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S0NDTR_Register -- - --------------------- - - subtype S0NDTR_NDT_Field is STM32F429x.Short; + subtype S0NDTR_NDT_Field is STM32F429x.UInt16; -- stream x number of data register type S0NDTR_Register is record -- Number of data items to transfer NDT : S0NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S0NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S0FCR_Register -- - -------------------- - subtype S0FCR_FTH_Field is STM32F429x.UInt2; subtype S0FCR_DMDIS_Field is STM32F429x.Bit; subtype S0FCR_FS_Field is STM32F429x.UInt3; @@ -586,7 +560,7 @@ package STM32F429x.DMA is FTH : S0FCR_FTH_Field := 16#1#; -- Direct mode disable DMDIS : S0FCR_DMDIS_Field := 16#0#; - -- FIFO status + -- Read-only. FIFO status FS : S0FCR_FS_Field := 16#4#; -- unspecified Reserved_6_6 : STM32F429x.Bit := 16#0#; @@ -595,7 +569,7 @@ package STM32F429x.DMA is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S0FCR_Register use record FTH at 0 range 0 .. 1; @@ -606,10 +580,6 @@ package STM32F429x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S1CR_Register -- - ------------------- - subtype S1CR_EN_Field is STM32F429x.Bit; subtype S1CR_DMEIE_Field is STM32F429x.Bit; subtype S1CR_TEIE_Field is STM32F429x.Bit; @@ -676,7 +646,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S1CR_Register use record EN at 0 range 0 .. 0; @@ -702,30 +672,22 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S1NDTR_Register -- - --------------------- - - subtype S1NDTR_NDT_Field is STM32F429x.Short; + subtype S1NDTR_NDT_Field is STM32F429x.UInt16; -- stream x number of data register type S1NDTR_Register is record -- Number of data items to transfer NDT : S1NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S1NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S1FCR_Register -- - -------------------- - subtype S1FCR_FTH_Field is STM32F429x.UInt2; subtype S1FCR_DMDIS_Field is STM32F429x.Bit; subtype S1FCR_FS_Field is STM32F429x.UInt3; @@ -737,7 +699,7 @@ package STM32F429x.DMA is FTH : S1FCR_FTH_Field := 16#1#; -- Direct mode disable DMDIS : S1FCR_DMDIS_Field := 16#0#; - -- FIFO status + -- Read-only. FIFO status FS : S1FCR_FS_Field := 16#4#; -- unspecified Reserved_6_6 : STM32F429x.Bit := 16#0#; @@ -746,7 +708,7 @@ package STM32F429x.DMA is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S1FCR_Register use record FTH at 0 range 0 .. 1; @@ -757,10 +719,6 @@ package STM32F429x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S2CR_Register -- - ------------------- - subtype S2CR_EN_Field is STM32F429x.Bit; subtype S2CR_DMEIE_Field is STM32F429x.Bit; subtype S2CR_TEIE_Field is STM32F429x.Bit; @@ -827,7 +785,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S2CR_Register use record EN at 0 range 0 .. 0; @@ -853,30 +811,22 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S2NDTR_Register -- - --------------------- - - subtype S2NDTR_NDT_Field is STM32F429x.Short; + subtype S2NDTR_NDT_Field is STM32F429x.UInt16; -- stream x number of data register type S2NDTR_Register is record -- Number of data items to transfer NDT : S2NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S2NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S2FCR_Register -- - -------------------- - subtype S2FCR_FTH_Field is STM32F429x.UInt2; subtype S2FCR_DMDIS_Field is STM32F429x.Bit; subtype S2FCR_FS_Field is STM32F429x.UInt3; @@ -888,7 +838,7 @@ package STM32F429x.DMA is FTH : S2FCR_FTH_Field := 16#1#; -- Direct mode disable DMDIS : S2FCR_DMDIS_Field := 16#0#; - -- FIFO status + -- Read-only. FIFO status FS : S2FCR_FS_Field := 16#4#; -- unspecified Reserved_6_6 : STM32F429x.Bit := 16#0#; @@ -897,7 +847,7 @@ package STM32F429x.DMA is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S2FCR_Register use record FTH at 0 range 0 .. 1; @@ -908,10 +858,6 @@ package STM32F429x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S3CR_Register -- - ------------------- - subtype S3CR_EN_Field is STM32F429x.Bit; subtype S3CR_DMEIE_Field is STM32F429x.Bit; subtype S3CR_TEIE_Field is STM32F429x.Bit; @@ -978,7 +924,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S3CR_Register use record EN at 0 range 0 .. 0; @@ -1004,30 +950,22 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S3NDTR_Register -- - --------------------- - - subtype S3NDTR_NDT_Field is STM32F429x.Short; + subtype S3NDTR_NDT_Field is STM32F429x.UInt16; -- stream x number of data register type S3NDTR_Register is record -- Number of data items to transfer NDT : S3NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S3NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S3FCR_Register -- - -------------------- - subtype S3FCR_FTH_Field is STM32F429x.UInt2; subtype S3FCR_DMDIS_Field is STM32F429x.Bit; subtype S3FCR_FS_Field is STM32F429x.UInt3; @@ -1039,7 +977,7 @@ package STM32F429x.DMA is FTH : S3FCR_FTH_Field := 16#1#; -- Direct mode disable DMDIS : S3FCR_DMDIS_Field := 16#0#; - -- FIFO status + -- Read-only. FIFO status FS : S3FCR_FS_Field := 16#4#; -- unspecified Reserved_6_6 : STM32F429x.Bit := 16#0#; @@ -1048,7 +986,7 @@ package STM32F429x.DMA is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S3FCR_Register use record FTH at 0 range 0 .. 1; @@ -1059,10 +997,6 @@ package STM32F429x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S4CR_Register -- - ------------------- - subtype S4CR_EN_Field is STM32F429x.Bit; subtype S4CR_DMEIE_Field is STM32F429x.Bit; subtype S4CR_TEIE_Field is STM32F429x.Bit; @@ -1129,7 +1063,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S4CR_Register use record EN at 0 range 0 .. 0; @@ -1155,30 +1089,22 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S4NDTR_Register -- - --------------------- - - subtype S4NDTR_NDT_Field is STM32F429x.Short; + subtype S4NDTR_NDT_Field is STM32F429x.UInt16; -- stream x number of data register type S4NDTR_Register is record -- Number of data items to transfer NDT : S4NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S4NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S4FCR_Register -- - -------------------- - subtype S4FCR_FTH_Field is STM32F429x.UInt2; subtype S4FCR_DMDIS_Field is STM32F429x.Bit; subtype S4FCR_FS_Field is STM32F429x.UInt3; @@ -1190,7 +1116,7 @@ package STM32F429x.DMA is FTH : S4FCR_FTH_Field := 16#1#; -- Direct mode disable DMDIS : S4FCR_DMDIS_Field := 16#0#; - -- FIFO status + -- Read-only. FIFO status FS : S4FCR_FS_Field := 16#4#; -- unspecified Reserved_6_6 : STM32F429x.Bit := 16#0#; @@ -1199,7 +1125,7 @@ package STM32F429x.DMA is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S4FCR_Register use record FTH at 0 range 0 .. 1; @@ -1210,10 +1136,6 @@ package STM32F429x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S5CR_Register -- - ------------------- - subtype S5CR_EN_Field is STM32F429x.Bit; subtype S5CR_DMEIE_Field is STM32F429x.Bit; subtype S5CR_TEIE_Field is STM32F429x.Bit; @@ -1280,7 +1202,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S5CR_Register use record EN at 0 range 0 .. 0; @@ -1306,30 +1228,22 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S5NDTR_Register -- - --------------------- - - subtype S5NDTR_NDT_Field is STM32F429x.Short; + subtype S5NDTR_NDT_Field is STM32F429x.UInt16; -- stream x number of data register type S5NDTR_Register is record -- Number of data items to transfer NDT : S5NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S5NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S5FCR_Register -- - -------------------- - subtype S5FCR_FTH_Field is STM32F429x.UInt2; subtype S5FCR_DMDIS_Field is STM32F429x.Bit; subtype S5FCR_FS_Field is STM32F429x.UInt3; @@ -1341,7 +1255,7 @@ package STM32F429x.DMA is FTH : S5FCR_FTH_Field := 16#1#; -- Direct mode disable DMDIS : S5FCR_DMDIS_Field := 16#0#; - -- FIFO status + -- Read-only. FIFO status FS : S5FCR_FS_Field := 16#4#; -- unspecified Reserved_6_6 : STM32F429x.Bit := 16#0#; @@ -1350,7 +1264,7 @@ package STM32F429x.DMA is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S5FCR_Register use record FTH at 0 range 0 .. 1; @@ -1361,10 +1275,6 @@ package STM32F429x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S6CR_Register -- - ------------------- - subtype S6CR_EN_Field is STM32F429x.Bit; subtype S6CR_DMEIE_Field is STM32F429x.Bit; subtype S6CR_TEIE_Field is STM32F429x.Bit; @@ -1431,7 +1341,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S6CR_Register use record EN at 0 range 0 .. 0; @@ -1457,30 +1367,22 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S6NDTR_Register -- - --------------------- - - subtype S6NDTR_NDT_Field is STM32F429x.Short; + subtype S6NDTR_NDT_Field is STM32F429x.UInt16; -- stream x number of data register type S6NDTR_Register is record -- Number of data items to transfer NDT : S6NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S6NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S6FCR_Register -- - -------------------- - subtype S6FCR_FTH_Field is STM32F429x.UInt2; subtype S6FCR_DMDIS_Field is STM32F429x.Bit; subtype S6FCR_FS_Field is STM32F429x.UInt3; @@ -1492,7 +1394,7 @@ package STM32F429x.DMA is FTH : S6FCR_FTH_Field := 16#1#; -- Direct mode disable DMDIS : S6FCR_DMDIS_Field := 16#0#; - -- FIFO status + -- Read-only. FIFO status FS : S6FCR_FS_Field := 16#4#; -- unspecified Reserved_6_6 : STM32F429x.Bit := 16#0#; @@ -1501,7 +1403,7 @@ package STM32F429x.DMA is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S6FCR_Register use record FTH at 0 range 0 .. 1; @@ -1512,10 +1414,6 @@ package STM32F429x.DMA is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------- - -- S7CR_Register -- - ------------------- - subtype S7CR_EN_Field is STM32F429x.Bit; subtype S7CR_DMEIE_Field is STM32F429x.Bit; subtype S7CR_TEIE_Field is STM32F429x.Bit; @@ -1582,7 +1480,7 @@ package STM32F429x.DMA is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S7CR_Register use record EN at 0 range 0 .. 0; @@ -1608,30 +1506,22 @@ package STM32F429x.DMA is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- S7NDTR_Register -- - --------------------- - - subtype S7NDTR_NDT_Field is STM32F429x.Short; + subtype S7NDTR_NDT_Field is STM32F429x.UInt16; -- stream x number of data register type S7NDTR_Register is record -- Number of data items to transfer NDT : S7NDTR_NDT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S7NDTR_Register use record NDT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- S7FCR_Register -- - -------------------- - subtype S7FCR_FTH_Field is STM32F429x.UInt2; subtype S7FCR_DMDIS_Field is STM32F429x.Bit; subtype S7FCR_FS_Field is STM32F429x.UInt3; @@ -1643,7 +1533,7 @@ package STM32F429x.DMA is FTH : S7FCR_FTH_Field := 16#1#; -- Direct mode disable DMDIS : S7FCR_DMDIS_Field := 16#0#; - -- FIFO status + -- Read-only. FIFO status FS : S7FCR_FS_Field := 16#4#; -- unspecified Reserved_6_6 : STM32F429x.Bit := 16#0#; @@ -1652,7 +1542,7 @@ package STM32F429x.DMA is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for S7FCR_Register use record FTH at 0 range 0 .. 1; @@ -1670,173 +1560,201 @@ package STM32F429x.DMA is -- DMA controller type DMA_Peripheral is record -- low interrupt status register - LISR : LISR_Register; + LISR : aliased LISR_Register; + pragma Volatile_Full_Access (LISR); -- high interrupt status register - HISR : HISR_Register; + HISR : aliased HISR_Register; + pragma Volatile_Full_Access (HISR); -- low interrupt flag clear register - LIFCR : LIFCR_Register; + LIFCR : aliased LIFCR_Register; + pragma Volatile_Full_Access (LIFCR); -- high interrupt flag clear register - HIFCR : HIFCR_Register; + HIFCR : aliased HIFCR_Register; + pragma Volatile_Full_Access (HIFCR); -- stream x configuration register - S0CR : S0CR_Register; + S0CR : aliased S0CR_Register; + pragma Volatile_Full_Access (S0CR); -- stream x number of data register - S0NDTR : S0NDTR_Register; + S0NDTR : aliased S0NDTR_Register; + pragma Volatile_Full_Access (S0NDTR); -- stream x peripheral address register - S0PAR : STM32F429x.Word; + S0PAR : aliased STM32F429x.UInt32; -- stream x memory 0 address register - S0M0AR : STM32F429x.Word; + S0M0AR : aliased STM32F429x.UInt32; -- stream x memory 1 address register - S0M1AR : STM32F429x.Word; + S0M1AR : aliased STM32F429x.UInt32; -- stream x FIFO control register - S0FCR : S0FCR_Register; + S0FCR : aliased S0FCR_Register; + pragma Volatile_Full_Access (S0FCR); -- stream x configuration register - S1CR : S1CR_Register; + S1CR : aliased S1CR_Register; + pragma Volatile_Full_Access (S1CR); -- stream x number of data register - S1NDTR : S1NDTR_Register; + S1NDTR : aliased S1NDTR_Register; + pragma Volatile_Full_Access (S1NDTR); -- stream x peripheral address register - S1PAR : STM32F429x.Word; + S1PAR : aliased STM32F429x.UInt32; -- stream x memory 0 address register - S1M0AR : STM32F429x.Word; + S1M0AR : aliased STM32F429x.UInt32; -- stream x memory 1 address register - S1M1AR : STM32F429x.Word; + S1M1AR : aliased STM32F429x.UInt32; -- stream x FIFO control register - S1FCR : S1FCR_Register; + S1FCR : aliased S1FCR_Register; + pragma Volatile_Full_Access (S1FCR); -- stream x configuration register - S2CR : S2CR_Register; + S2CR : aliased S2CR_Register; + pragma Volatile_Full_Access (S2CR); -- stream x number of data register - S2NDTR : S2NDTR_Register; + S2NDTR : aliased S2NDTR_Register; + pragma Volatile_Full_Access (S2NDTR); -- stream x peripheral address register - S2PAR : STM32F429x.Word; + S2PAR : aliased STM32F429x.UInt32; -- stream x memory 0 address register - S2M0AR : STM32F429x.Word; + S2M0AR : aliased STM32F429x.UInt32; -- stream x memory 1 address register - S2M1AR : STM32F429x.Word; + S2M1AR : aliased STM32F429x.UInt32; -- stream x FIFO control register - S2FCR : S2FCR_Register; + S2FCR : aliased S2FCR_Register; + pragma Volatile_Full_Access (S2FCR); -- stream x configuration register - S3CR : S3CR_Register; + S3CR : aliased S3CR_Register; + pragma Volatile_Full_Access (S3CR); -- stream x number of data register - S3NDTR : S3NDTR_Register; + S3NDTR : aliased S3NDTR_Register; + pragma Volatile_Full_Access (S3NDTR); -- stream x peripheral address register - S3PAR : STM32F429x.Word; + S3PAR : aliased STM32F429x.UInt32; -- stream x memory 0 address register - S3M0AR : STM32F429x.Word; + S3M0AR : aliased STM32F429x.UInt32; -- stream x memory 1 address register - S3M1AR : STM32F429x.Word; + S3M1AR : aliased STM32F429x.UInt32; -- stream x FIFO control register - S3FCR : S3FCR_Register; + S3FCR : aliased S3FCR_Register; + pragma Volatile_Full_Access (S3FCR); -- stream x configuration register - S4CR : S4CR_Register; + S4CR : aliased S4CR_Register; + pragma Volatile_Full_Access (S4CR); -- stream x number of data register - S4NDTR : S4NDTR_Register; + S4NDTR : aliased S4NDTR_Register; + pragma Volatile_Full_Access (S4NDTR); -- stream x peripheral address register - S4PAR : STM32F429x.Word; + S4PAR : aliased STM32F429x.UInt32; -- stream x memory 0 address register - S4M0AR : STM32F429x.Word; + S4M0AR : aliased STM32F429x.UInt32; -- stream x memory 1 address register - S4M1AR : STM32F429x.Word; + S4M1AR : aliased STM32F429x.UInt32; -- stream x FIFO control register - S4FCR : S4FCR_Register; + S4FCR : aliased S4FCR_Register; + pragma Volatile_Full_Access (S4FCR); -- stream x configuration register - S5CR : S5CR_Register; + S5CR : aliased S5CR_Register; + pragma Volatile_Full_Access (S5CR); -- stream x number of data register - S5NDTR : S5NDTR_Register; + S5NDTR : aliased S5NDTR_Register; + pragma Volatile_Full_Access (S5NDTR); -- stream x peripheral address register - S5PAR : STM32F429x.Word; + S5PAR : aliased STM32F429x.UInt32; -- stream x memory 0 address register - S5M0AR : STM32F429x.Word; + S5M0AR : aliased STM32F429x.UInt32; -- stream x memory 1 address register - S5M1AR : STM32F429x.Word; + S5M1AR : aliased STM32F429x.UInt32; -- stream x FIFO control register - S5FCR : S5FCR_Register; + S5FCR : aliased S5FCR_Register; + pragma Volatile_Full_Access (S5FCR); -- stream x configuration register - S6CR : S6CR_Register; + S6CR : aliased S6CR_Register; + pragma Volatile_Full_Access (S6CR); -- stream x number of data register - S6NDTR : S6NDTR_Register; + S6NDTR : aliased S6NDTR_Register; + pragma Volatile_Full_Access (S6NDTR); -- stream x peripheral address register - S6PAR : STM32F429x.Word; + S6PAR : aliased STM32F429x.UInt32; -- stream x memory 0 address register - S6M0AR : STM32F429x.Word; + S6M0AR : aliased STM32F429x.UInt32; -- stream x memory 1 address register - S6M1AR : STM32F429x.Word; + S6M1AR : aliased STM32F429x.UInt32; -- stream x FIFO control register - S6FCR : S6FCR_Register; + S6FCR : aliased S6FCR_Register; + pragma Volatile_Full_Access (S6FCR); -- stream x configuration register - S7CR : S7CR_Register; + S7CR : aliased S7CR_Register; + pragma Volatile_Full_Access (S7CR); -- stream x number of data register - S7NDTR : S7NDTR_Register; + S7NDTR : aliased S7NDTR_Register; + pragma Volatile_Full_Access (S7NDTR); -- stream x peripheral address register - S7PAR : STM32F429x.Word; + S7PAR : aliased STM32F429x.UInt32; -- stream x memory 0 address register - S7M0AR : STM32F429x.Word; + S7M0AR : aliased STM32F429x.UInt32; -- stream x memory 1 address register - S7M1AR : STM32F429x.Word; + S7M1AR : aliased STM32F429x.UInt32; -- stream x FIFO control register - S7FCR : S7FCR_Register; + S7FCR : aliased S7FCR_Register; + pragma Volatile_Full_Access (S7FCR); end record with Volatile; for DMA_Peripheral use record - LISR at 0 range 0 .. 31; - HISR at 4 range 0 .. 31; - LIFCR at 8 range 0 .. 31; - HIFCR at 12 range 0 .. 31; - S0CR at 16 range 0 .. 31; - S0NDTR at 20 range 0 .. 31; - S0PAR at 24 range 0 .. 31; - S0M0AR at 28 range 0 .. 31; - S0M1AR at 32 range 0 .. 31; - S0FCR at 36 range 0 .. 31; - S1CR at 40 range 0 .. 31; - S1NDTR at 44 range 0 .. 31; - S1PAR at 48 range 0 .. 31; - S1M0AR at 52 range 0 .. 31; - S1M1AR at 56 range 0 .. 31; - S1FCR at 60 range 0 .. 31; - S2CR at 64 range 0 .. 31; - S2NDTR at 68 range 0 .. 31; - S2PAR at 72 range 0 .. 31; - S2M0AR at 76 range 0 .. 31; - S2M1AR at 80 range 0 .. 31; - S2FCR at 84 range 0 .. 31; - S3CR at 88 range 0 .. 31; - S3NDTR at 92 range 0 .. 31; - S3PAR at 96 range 0 .. 31; - S3M0AR at 100 range 0 .. 31; - S3M1AR at 104 range 0 .. 31; - S3FCR at 108 range 0 .. 31; - S4CR at 112 range 0 .. 31; - S4NDTR at 116 range 0 .. 31; - S4PAR at 120 range 0 .. 31; - S4M0AR at 124 range 0 .. 31; - S4M1AR at 128 range 0 .. 31; - S4FCR at 132 range 0 .. 31; - S5CR at 136 range 0 .. 31; - S5NDTR at 140 range 0 .. 31; - S5PAR at 144 range 0 .. 31; - S5M0AR at 148 range 0 .. 31; - S5M1AR at 152 range 0 .. 31; - S5FCR at 156 range 0 .. 31; - S6CR at 160 range 0 .. 31; - S6NDTR at 164 range 0 .. 31; - S6PAR at 168 range 0 .. 31; - S6M0AR at 172 range 0 .. 31; - S6M1AR at 176 range 0 .. 31; - S6FCR at 180 range 0 .. 31; - S7CR at 184 range 0 .. 31; - S7NDTR at 188 range 0 .. 31; - S7PAR at 192 range 0 .. 31; - S7M0AR at 196 range 0 .. 31; - S7M1AR at 200 range 0 .. 31; - S7FCR at 204 range 0 .. 31; + LISR at 16#0# range 0 .. 31; + HISR at 16#4# range 0 .. 31; + LIFCR at 16#8# range 0 .. 31; + HIFCR at 16#C# range 0 .. 31; + S0CR at 16#10# range 0 .. 31; + S0NDTR at 16#14# range 0 .. 31; + S0PAR at 16#18# range 0 .. 31; + S0M0AR at 16#1C# range 0 .. 31; + S0M1AR at 16#20# range 0 .. 31; + S0FCR at 16#24# range 0 .. 31; + S1CR at 16#28# range 0 .. 31; + S1NDTR at 16#2C# range 0 .. 31; + S1PAR at 16#30# range 0 .. 31; + S1M0AR at 16#34# range 0 .. 31; + S1M1AR at 16#38# range 0 .. 31; + S1FCR at 16#3C# range 0 .. 31; + S2CR at 16#40# range 0 .. 31; + S2NDTR at 16#44# range 0 .. 31; + S2PAR at 16#48# range 0 .. 31; + S2M0AR at 16#4C# range 0 .. 31; + S2M1AR at 16#50# range 0 .. 31; + S2FCR at 16#54# range 0 .. 31; + S3CR at 16#58# range 0 .. 31; + S3NDTR at 16#5C# range 0 .. 31; + S3PAR at 16#60# range 0 .. 31; + S3M0AR at 16#64# range 0 .. 31; + S3M1AR at 16#68# range 0 .. 31; + S3FCR at 16#6C# range 0 .. 31; + S4CR at 16#70# range 0 .. 31; + S4NDTR at 16#74# range 0 .. 31; + S4PAR at 16#78# range 0 .. 31; + S4M0AR at 16#7C# range 0 .. 31; + S4M1AR at 16#80# range 0 .. 31; + S4FCR at 16#84# range 0 .. 31; + S5CR at 16#88# range 0 .. 31; + S5NDTR at 16#8C# range 0 .. 31; + S5PAR at 16#90# range 0 .. 31; + S5M0AR at 16#94# range 0 .. 31; + S5M1AR at 16#98# range 0 .. 31; + S5FCR at 16#9C# range 0 .. 31; + S6CR at 16#A0# range 0 .. 31; + S6NDTR at 16#A4# range 0 .. 31; + S6PAR at 16#A8# range 0 .. 31; + S6M0AR at 16#AC# range 0 .. 31; + S6M1AR at 16#B0# range 0 .. 31; + S6FCR at 16#B4# range 0 .. 31; + S7CR at 16#B8# range 0 .. 31; + S7NDTR at 16#BC# range 0 .. 31; + S7PAR at 16#C0# range 0 .. 31; + S7M0AR at 16#C4# range 0 .. 31; + S7M1AR at 16#C8# range 0 .. 31; + S7FCR at 16#CC# range 0 .. 31; end record; -- DMA controller DMA1_Periph : aliased DMA_Peripheral - with Import, Address => System'To_Address (16#40026000#); + with Import, Address => DMA1_Base; -- DMA controller DMA2_Periph : aliased DMA_Peripheral - with Import, Address => System'To_Address (16#40026400#); + with Import, Address => DMA2_Base; end STM32F429x.DMA; diff --git a/stm32f429i/stm32f429x/stm32f429x-dma2d.ads b/stm32f429i/stm32f429x/stm32f429x-dma2d.ads index 4dd2666..1ae412e 100644 --- a/stm32f429i/stm32f429x/stm32f429x-dma2d.ads +++ b/stm32f429i/stm32f429x/stm32f429x-dma2d.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.DMA2D is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_START_Field is STM32F429x.Bit; subtype CR_SUSP_Field is STM32F429x.Bit; subtype CR_ABORT_Field is STM32F429x.Bit; @@ -56,7 +54,7 @@ package STM32F429x.DMA2D is -- unspecified Reserved_18_31 : STM32F429x.UInt14 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record START at 0 range 0 .. 0; @@ -74,10 +72,6 @@ package STM32F429x.DMA2D is Reserved_18_31 at 0 range 18 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ - subtype ISR_TEIF_Field is STM32F429x.Bit; subtype ISR_TCIF_Field is STM32F429x.Bit; subtype ISR_TWIF_Field is STM32F429x.Bit; @@ -87,22 +81,22 @@ package STM32F429x.DMA2D is -- Interrupt Status Register type ISR_Register is record - -- Transfer error interrupt flag + -- Read-only. Transfer error interrupt flag TEIF : ISR_TEIF_Field; - -- Transfer complete interrupt flag + -- Read-only. Transfer complete interrupt flag TCIF : ISR_TCIF_Field; - -- Transfer watermark interrupt flag + -- Read-only. Transfer watermark interrupt flag TWIF : ISR_TWIF_Field; - -- CLUT access error interrupt flag + -- Read-only. CLUT access error interrupt flag CAEIF : ISR_CAEIF_Field; - -- CLUT transfer complete interrupt flag + -- Read-only. CLUT transfer complete interrupt flag CTCIF : ISR_CTCIF_Field; - -- Configuration error interrupt flag + -- Read-only. Configuration error interrupt flag CEIF : ISR_CEIF_Field; -- unspecified Reserved_6_31 : STM32F429x.UInt26; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ISR_Register use record TEIF at 0 range 0 .. 0; @@ -114,10 +108,6 @@ package STM32F429x.DMA2D is Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------- - -- IFCR_Register -- - ------------------- - subtype IFCR_CTEIF_Field is STM32F429x.Bit; subtype IFCR_CTCIF_Field is STM32F429x.Bit; subtype IFCR_CTWIF_Field is STM32F429x.Bit; @@ -142,7 +132,7 @@ package STM32F429x.DMA2D is -- unspecified Reserved_6_31 : STM32F429x.UInt26 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IFCR_Register use record CTEIF at 0 range 0 .. 0; @@ -154,10 +144,6 @@ package STM32F429x.DMA2D is Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------- - -- FGOR_Register -- - ------------------- - subtype FGOR_LO_Field is STM32F429x.UInt14; -- foreground offset register @@ -167,17 +153,13 @@ package STM32F429x.DMA2D is -- unspecified Reserved_14_31 : STM32F429x.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FGOR_Register use record LO at 0 range 0 .. 13; Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------- - -- BGOR_Register -- - ------------------- - subtype BGOR_LO_Field is STM32F429x.UInt14; -- background offset register @@ -187,17 +169,13 @@ package STM32F429x.DMA2D is -- unspecified Reserved_14_31 : STM32F429x.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BGOR_Register use record LO at 0 range 0 .. 13; Reserved_14_31 at 0 range 14 .. 31; end record; - ---------------------- - -- FGPFCCR_Register -- - ---------------------- - subtype FGPFCCR_CM_Field is STM32F429x.UInt4; subtype FGPFCCR_CCM_Field is STM32F429x.Bit; subtype FGPFCCR_START_Field is STM32F429x.Bit; @@ -224,7 +202,7 @@ package STM32F429x.DMA2D is -- Alpha value ALPHA : FGPFCCR_ALPHA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FGPFCCR_Register use record CM at 0 range 0 .. 3; @@ -237,10 +215,6 @@ package STM32F429x.DMA2D is ALPHA at 0 range 24 .. 31; end record; - --------------------- - -- FGCOLR_Register -- - --------------------- - subtype FGCOLR_BLUE_Field is STM32F429x.Byte; subtype FGCOLR_GREEN_Field is STM32F429x.Byte; subtype FGCOLR_RED_Field is STM32F429x.Byte; @@ -256,7 +230,7 @@ package STM32F429x.DMA2D is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FGCOLR_Register use record BLUE at 0 range 0 .. 7; @@ -265,10 +239,6 @@ package STM32F429x.DMA2D is Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------- - -- BGPFCCR_Register -- - ---------------------- - subtype BGPFCCR_CM_Field is STM32F429x.UInt4; subtype BGPFCCR_CCM_Field is STM32F429x.Bit; subtype BGPFCCR_START_Field is STM32F429x.Bit; @@ -295,7 +265,7 @@ package STM32F429x.DMA2D is -- Alpha value ALPHA : BGPFCCR_ALPHA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BGPFCCR_Register use record CM at 0 range 0 .. 3; @@ -308,10 +278,6 @@ package STM32F429x.DMA2D is ALPHA at 0 range 24 .. 31; end record; - --------------------- - -- BGCOLR_Register -- - --------------------- - subtype BGCOLR_BLUE_Field is STM32F429x.Byte; subtype BGCOLR_GREEN_Field is STM32F429x.Byte; subtype BGCOLR_RED_Field is STM32F429x.Byte; @@ -327,7 +293,7 @@ package STM32F429x.DMA2D is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BGCOLR_Register use record BLUE at 0 range 0 .. 7; @@ -336,10 +302,6 @@ package STM32F429x.DMA2D is Reserved_24_31 at 0 range 24 .. 31; end record; - --------------------- - -- OPFCCR_Register -- - --------------------- - subtype OPFCCR_CM_Field is STM32F429x.UInt3; -- output PFC control register @@ -349,17 +311,13 @@ package STM32F429x.DMA2D is -- unspecified Reserved_3_31 : STM32F429x.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OPFCCR_Register use record CM at 0 range 0 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - -------------------- - -- OCOLR_Register -- - -------------------- - subtype OCOLR_BLUE_Field is STM32F429x.Byte; subtype OCOLR_GREEN_Field is STM32F429x.Byte; subtype OCOLR_RED_Field is STM32F429x.Byte; @@ -376,7 +334,7 @@ package STM32F429x.DMA2D is -- Alpha Channel Value APLHA : OCOLR_APLHA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OCOLR_Register use record BLUE at 0 range 0 .. 7; @@ -385,10 +343,6 @@ package STM32F429x.DMA2D is APLHA at 0 range 24 .. 31; end record; - ------------------ - -- OOR_Register -- - ------------------ - subtype OOR_LO_Field is STM32F429x.UInt14; -- output offset register @@ -398,18 +352,14 @@ package STM32F429x.DMA2D is -- unspecified Reserved_14_31 : STM32F429x.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OOR_Register use record LO at 0 range 0 .. 13; Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------ - -- NLR_Register -- - ------------------ - - subtype NLR_NL_Field is STM32F429x.Short; + subtype NLR_NL_Field is STM32F429x.UInt16; subtype NLR_PL_Field is STM32F429x.UInt14; -- number of line register @@ -421,7 +371,7 @@ package STM32F429x.DMA2D is -- unspecified Reserved_30_31 : STM32F429x.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for NLR_Register use record NL at 0 range 0 .. 15; @@ -429,30 +379,22 @@ package STM32F429x.DMA2D is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- LWR_Register -- - ------------------ - - subtype LWR_LW_Field is STM32F429x.Short; + subtype LWR_LW_Field is STM32F429x.UInt16; -- line watermark register type LWR_Register is record -- Line watermark LW : LWR_LW_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LWR_Register use record LW at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- AMTCR_Register -- - -------------------- - subtype AMTCR_EN_Field is STM32F429x.Bit; subtype AMTCR_DT_Field is STM32F429x.Byte; @@ -465,9 +407,9 @@ package STM32F429x.DMA2D is -- Dead Time DT : AMTCR_DT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AMTCR_Register use record EN at 0 range 0 .. 0; @@ -476,10 +418,6 @@ package STM32F429x.DMA2D is Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- FGCLUT_Register -- - --------------------- - subtype FGCLUT_BLUE_Field is STM32F429x.Byte; subtype FGCLUT_GREEN_Field is STM32F429x.Byte; subtype FGCLUT_RED_Field is STM32F429x.Byte; @@ -496,7 +434,7 @@ package STM32F429x.DMA2D is -- APLHA APLHA : FGCLUT_APLHA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FGCLUT_Register use record BLUE at 0 range 0 .. 7; @@ -505,10 +443,6 @@ package STM32F429x.DMA2D is APLHA at 0 range 24 .. 31; end record; - --------------------- - -- BGCLUT_Register -- - --------------------- - subtype BGCLUT_BLUE_Field is STM32F429x.Byte; subtype BGCLUT_GREEN_Field is STM32F429x.Byte; subtype BGCLUT_RED_Field is STM32F429x.Byte; @@ -525,7 +459,7 @@ package STM32F429x.DMA2D is -- APLHA APLHA : BGCLUT_APLHA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BGCLUT_Register use record BLUE at 0 range 0 .. 7; @@ -541,79 +475,96 @@ package STM32F429x.DMA2D is -- DMA2D controller type DMA2D_Peripheral is record -- control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- Interrupt Status Register - ISR : ISR_Register; + ISR : aliased ISR_Register; + pragma Volatile_Full_Access (ISR); -- interrupt flag clear register - IFCR : IFCR_Register; + IFCR : aliased IFCR_Register; + pragma Volatile_Full_Access (IFCR); -- foreground memory address register - FGMAR : STM32F429x.Word; + FGMAR : aliased STM32F429x.UInt32; -- foreground offset register - FGOR : FGOR_Register; + FGOR : aliased FGOR_Register; + pragma Volatile_Full_Access (FGOR); -- background memory address register - BGMAR : STM32F429x.Word; + BGMAR : aliased STM32F429x.UInt32; -- background offset register - BGOR : BGOR_Register; + BGOR : aliased BGOR_Register; + pragma Volatile_Full_Access (BGOR); -- foreground PFC control register - FGPFCCR : FGPFCCR_Register; + FGPFCCR : aliased FGPFCCR_Register; + pragma Volatile_Full_Access (FGPFCCR); -- foreground color register - FGCOLR : FGCOLR_Register; + FGCOLR : aliased FGCOLR_Register; + pragma Volatile_Full_Access (FGCOLR); -- background PFC control register - BGPFCCR : BGPFCCR_Register; + BGPFCCR : aliased BGPFCCR_Register; + pragma Volatile_Full_Access (BGPFCCR); -- background color register - BGCOLR : BGCOLR_Register; + BGCOLR : aliased BGCOLR_Register; + pragma Volatile_Full_Access (BGCOLR); -- foreground CLUT memory address register - FGCMAR : STM32F429x.Word; + FGCMAR : aliased STM32F429x.UInt32; -- background CLUT memory address register - BGCMAR : STM32F429x.Word; + BGCMAR : aliased STM32F429x.UInt32; -- output PFC control register - OPFCCR : OPFCCR_Register; + OPFCCR : aliased OPFCCR_Register; + pragma Volatile_Full_Access (OPFCCR); -- output color register - OCOLR : OCOLR_Register; + OCOLR : aliased OCOLR_Register; + pragma Volatile_Full_Access (OCOLR); -- output memory address register - OMAR : STM32F429x.Word; + OMAR : aliased STM32F429x.UInt32; -- output offset register - OOR : OOR_Register; + OOR : aliased OOR_Register; + pragma Volatile_Full_Access (OOR); -- number of line register - NLR : NLR_Register; + NLR : aliased NLR_Register; + pragma Volatile_Full_Access (NLR); -- line watermark register - LWR : LWR_Register; + LWR : aliased LWR_Register; + pragma Volatile_Full_Access (LWR); -- AHB master timer configuration register - AMTCR : AMTCR_Register; + AMTCR : aliased AMTCR_Register; + pragma Volatile_Full_Access (AMTCR); -- FGCLUT - FGCLUT : FGCLUT_Register; + FGCLUT : aliased FGCLUT_Register; + pragma Volatile_Full_Access (FGCLUT); -- BGCLUT - BGCLUT : BGCLUT_Register; + BGCLUT : aliased BGCLUT_Register; + pragma Volatile_Full_Access (BGCLUT); end record with Volatile; for DMA2D_Peripheral use record - CR at 0 range 0 .. 31; - ISR at 4 range 0 .. 31; - IFCR at 8 range 0 .. 31; - FGMAR at 12 range 0 .. 31; - FGOR at 16 range 0 .. 31; - BGMAR at 20 range 0 .. 31; - BGOR at 24 range 0 .. 31; - FGPFCCR at 28 range 0 .. 31; - FGCOLR at 32 range 0 .. 31; - BGPFCCR at 36 range 0 .. 31; - BGCOLR at 40 range 0 .. 31; - FGCMAR at 44 range 0 .. 31; - BGCMAR at 48 range 0 .. 31; - OPFCCR at 52 range 0 .. 31; - OCOLR at 56 range 0 .. 31; - OMAR at 60 range 0 .. 31; - OOR at 64 range 0 .. 31; - NLR at 68 range 0 .. 31; - LWR at 72 range 0 .. 31; - AMTCR at 76 range 0 .. 31; - FGCLUT at 1024 range 0 .. 31; - BGCLUT at 2048 range 0 .. 31; + CR at 16#0# range 0 .. 31; + ISR at 16#4# range 0 .. 31; + IFCR at 16#8# range 0 .. 31; + FGMAR at 16#C# range 0 .. 31; + FGOR at 16#10# range 0 .. 31; + BGMAR at 16#14# range 0 .. 31; + BGOR at 16#18# range 0 .. 31; + FGPFCCR at 16#1C# range 0 .. 31; + FGCOLR at 16#20# range 0 .. 31; + BGPFCCR at 16#24# range 0 .. 31; + BGCOLR at 16#28# range 0 .. 31; + FGCMAR at 16#2C# range 0 .. 31; + BGCMAR at 16#30# range 0 .. 31; + OPFCCR at 16#34# range 0 .. 31; + OCOLR at 16#38# range 0 .. 31; + OMAR at 16#3C# range 0 .. 31; + OOR at 16#40# range 0 .. 31; + NLR at 16#44# range 0 .. 31; + LWR at 16#48# range 0 .. 31; + AMTCR at 16#4C# range 0 .. 31; + FGCLUT at 16#400# range 0 .. 31; + BGCLUT at 16#800# range 0 .. 31; end record; -- DMA2D controller DMA2D_Periph : aliased DMA2D_Peripheral - with Import, Address => System'To_Address (16#4002B000#); + with Import, Address => DMA2D_Base; end STM32F429x.DMA2D; diff --git a/stm32f429i/stm32f429x/stm32f429x-ethernet.ads b/stm32f429i/stm32f429x/stm32f429x-ethernet.ads index aaed00d..a6112fa 100644 --- a/stm32f429i/stm32f429x/stm32f429x-ethernet.ads +++ b/stm32f429i/stm32f429x/stm32f429x-ethernet.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,483 +14,791 @@ package STM32F429x.Ethernet is -- Registers -- --------------- - -------------------- - -- MACCR_Register -- - -------------------- - - subtype MACCR_RE_Field is STM32F429x.Bit; - subtype MACCR_TE_Field is STM32F429x.Bit; - subtype MACCR_DC_Field is STM32F429x.Bit; - subtype MACCR_BL_Field is STM32F429x.UInt2; - subtype MACCR_APCS_Field is STM32F429x.Bit; - subtype MACCR_RD_Field is STM32F429x.Bit; - subtype MACCR_IPCO_Field is STM32F429x.Bit; - subtype MACCR_DM_Field is STM32F429x.Bit; - subtype MACCR_LM_Field is STM32F429x.Bit; - subtype MACCR_ROD_Field is STM32F429x.Bit; - subtype MACCR_FES_Field is STM32F429x.Bit; - subtype MACCR_CSD_Field is STM32F429x.Bit; - subtype MACCR_IFG_Field is STM32F429x.UInt3; - subtype MACCR_JD_Field is STM32F429x.Bit; - subtype MACCR_WD_Field is STM32F429x.Bit; - subtype MACCR_CSTF_Field is STM32F429x.Bit; - - -- Ethernet MAC configuration register - type MACCR_Register is record - -- unspecified - Reserved_0_1 : STM32F429x.UInt2 := 16#0#; - -- RE - RE : MACCR_RE_Field := 16#0#; - -- TE - TE : MACCR_TE_Field := 16#0#; - -- DC - DC : MACCR_DC_Field := 16#0#; - -- BL - BL : MACCR_BL_Field := 16#0#; - -- APCS - APCS : MACCR_APCS_Field := 16#0#; - -- unspecified - Reserved_8_8 : STM32F429x.Bit := 16#0#; - -- RD - RD : MACCR_RD_Field := 16#0#; - -- IPCO - IPCO : MACCR_IPCO_Field := 16#0#; - -- DM - DM : MACCR_DM_Field := 16#0#; - -- LM - LM : MACCR_LM_Field := 16#0#; - -- ROD - ROD : MACCR_ROD_Field := 16#0#; - -- FES - FES : MACCR_FES_Field := 16#0#; - -- unspecified - Reserved_15_15 : STM32F429x.Bit := 16#1#; - -- CSD - CSD : MACCR_CSD_Field := 16#0#; - -- IFG - IFG : MACCR_IFG_Field := 16#0#; - -- unspecified - Reserved_20_21 : STM32F429x.UInt2 := 16#0#; - -- JD - JD : MACCR_JD_Field := 16#0#; - -- WD - WD : MACCR_WD_Field := 16#0#; - -- unspecified - Reserved_24_24 : STM32F429x.Bit := 16#0#; - -- CSTF - CSTF : MACCR_CSTF_Field := 16#0#; - -- unspecified - Reserved_26_31 : STM32F429x.UInt6 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for MACCR_Register use record - Reserved_0_1 at 0 range 0 .. 1; - RE at 0 range 2 .. 2; - TE at 0 range 3 .. 3; - DC at 0 range 4 .. 4; - BL at 0 range 5 .. 6; - APCS at 0 range 7 .. 7; - Reserved_8_8 at 0 range 8 .. 8; - RD at 0 range 9 .. 9; - IPCO at 0 range 10 .. 10; - DM at 0 range 11 .. 11; - LM at 0 range 12 .. 12; - ROD at 0 range 13 .. 13; - FES at 0 range 14 .. 14; - Reserved_15_15 at 0 range 15 .. 15; - CSD at 0 range 16 .. 16; - IFG at 0 range 17 .. 19; - Reserved_20_21 at 0 range 20 .. 21; - JD at 0 range 22 .. 22; - WD at 0 range 23 .. 23; - Reserved_24_24 at 0 range 24 .. 24; - CSTF at 0 range 25 .. 25; - Reserved_26_31 at 0 range 26 .. 31; - end record; - - --------------------- - -- MACFFR_Register -- - --------------------- - - subtype MACFFR_PM_Field is STM32F429x.Bit; - subtype MACFFR_HU_Field is STM32F429x.Bit; - subtype MACFFR_HM_Field is STM32F429x.Bit; - subtype MACFFR_DAIF_Field is STM32F429x.Bit; - subtype MACFFR_RAM_Field is STM32F429x.Bit; - subtype MACFFR_BFD_Field is STM32F429x.Bit; - subtype MACFFR_PCF_Field is STM32F429x.Bit; - subtype MACFFR_SAIF_Field is STM32F429x.Bit; - subtype MACFFR_SAF_Field is STM32F429x.Bit; - subtype MACFFR_HPF_Field is STM32F429x.Bit; - subtype MACFFR_RA_Field is STM32F429x.Bit; + subtype DMABMR_SR_Field is STM32F429x.Bit; + subtype DMABMR_DA_Field is STM32F429x.Bit; + subtype DMABMR_DSL_Field is STM32F429x.UInt5; + subtype DMABMR_EDFE_Field is STM32F429x.Bit; + subtype DMABMR_PBL_Field is STM32F429x.UInt6; + subtype DMABMR_RTPR_Field is STM32F429x.UInt2; + subtype DMABMR_FB_Field is STM32F429x.Bit; + subtype DMABMR_RDP_Field is STM32F429x.UInt6; + subtype DMABMR_USP_Field is STM32F429x.Bit; + subtype DMABMR_FPM_Field is STM32F429x.Bit; + subtype DMABMR_AAB_Field is STM32F429x.Bit; + subtype DMABMR_MB_Field is STM32F429x.Bit; - -- Ethernet MAC frame filter register - type MACFFR_Register is record + -- Ethernet DMA bus mode register + type DMABMR_Register is record -- no description available - PM : MACFFR_PM_Field := 16#0#; + SR : DMABMR_SR_Field := 16#1#; -- no description available - HU : MACFFR_HU_Field := 16#0#; + DA : DMABMR_DA_Field := 16#0#; -- no description available - HM : MACFFR_HM_Field := 16#0#; + DSL : DMABMR_DSL_Field := 16#0#; -- no description available - DAIF : MACFFR_DAIF_Field := 16#0#; + EDFE : DMABMR_EDFE_Field := 16#0#; -- no description available - RAM : MACFFR_RAM_Field := 16#0#; + PBL : DMABMR_PBL_Field := 16#21#; -- no description available - BFD : MACFFR_BFD_Field := 16#0#; + RTPR : DMABMR_RTPR_Field := 16#0#; -- no description available - PCF : MACFFR_PCF_Field := 16#0#; + FB : DMABMR_FB_Field := 16#0#; -- no description available - SAIF : MACFFR_SAIF_Field := 16#0#; + RDP : DMABMR_RDP_Field := 16#0#; -- no description available - SAF : MACFFR_SAF_Field := 16#0#; + USP : DMABMR_USP_Field := 16#0#; -- no description available - HPF : MACFFR_HPF_Field := 16#0#; - -- unspecified - Reserved_10_30 : STM32F429x.UInt21 := 16#0#; + FPM : DMABMR_FPM_Field := 16#0#; -- no description available - RA : MACFFR_RA_Field := 16#0#; + AAB : DMABMR_AAB_Field := 16#0#; + -- no description available + MB : DMABMR_MB_Field := 16#0#; + -- unspecified + Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACFFR_Register use record - PM at 0 range 0 .. 0; - HU at 0 range 1 .. 1; - HM at 0 range 2 .. 2; - DAIF at 0 range 3 .. 3; - RAM at 0 range 4 .. 4; - BFD at 0 range 5 .. 5; - PCF at 0 range 6 .. 6; - SAIF at 0 range 7 .. 7; - SAF at 0 range 8 .. 8; - HPF at 0 range 9 .. 9; - Reserved_10_30 at 0 range 10 .. 30; - RA at 0 range 31 .. 31; + for DMABMR_Register use record + SR at 0 range 0 .. 0; + DA at 0 range 1 .. 1; + DSL at 0 range 2 .. 6; + EDFE at 0 range 7 .. 7; + PBL at 0 range 8 .. 13; + RTPR at 0 range 14 .. 15; + FB at 0 range 16 .. 16; + RDP at 0 range 17 .. 22; + USP at 0 range 23 .. 23; + FPM at 0 range 24 .. 24; + AAB at 0 range 25 .. 25; + MB at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; end record; - ----------------------- - -- MACMIIAR_Register -- - ----------------------- - - subtype MACMIIAR_MB_Field is STM32F429x.Bit; - subtype MACMIIAR_MW_Field is STM32F429x.Bit; - subtype MACMIIAR_CR_Field is STM32F429x.UInt3; - subtype MACMIIAR_MR_Field is STM32F429x.UInt5; - subtype MACMIIAR_PA_Field is STM32F429x.UInt5; + subtype DMASR_TS_Field is STM32F429x.Bit; + subtype DMASR_TPSS_Field is STM32F429x.Bit; + subtype DMASR_TBUS_Field is STM32F429x.Bit; + subtype DMASR_TJTS_Field is STM32F429x.Bit; + subtype DMASR_ROS_Field is STM32F429x.Bit; + subtype DMASR_TUS_Field is STM32F429x.Bit; + subtype DMASR_RS_Field is STM32F429x.Bit; + subtype DMASR_RBUS_Field is STM32F429x.Bit; + subtype DMASR_RPSS_Field is STM32F429x.Bit; + subtype DMASR_PWTS_Field is STM32F429x.Bit; + subtype DMASR_ETS_Field is STM32F429x.Bit; + subtype DMASR_FBES_Field is STM32F429x.Bit; + subtype DMASR_ERS_Field is STM32F429x.Bit; + subtype DMASR_AIS_Field is STM32F429x.Bit; + subtype DMASR_NIS_Field is STM32F429x.Bit; + subtype DMASR_RPS_Field is STM32F429x.UInt3; + subtype DMASR_TPS_Field is STM32F429x.UInt3; + subtype DMASR_EBS_Field is STM32F429x.UInt3; + subtype DMASR_MMCS_Field is STM32F429x.Bit; + subtype DMASR_PMTS_Field is STM32F429x.Bit; + subtype DMASR_TSTS_Field is STM32F429x.Bit; - -- Ethernet MAC MII address register - type MACMIIAR_Register is record + -- Ethernet DMA status register + type DMASR_Register is record -- no description available - MB : MACMIIAR_MB_Field := 16#0#; + TS : DMASR_TS_Field := 16#0#; -- no description available - MW : MACMIIAR_MW_Field := 16#0#; + TPSS : DMASR_TPSS_Field := 16#0#; -- no description available - CR : MACMIIAR_CR_Field := 16#0#; + TBUS : DMASR_TBUS_Field := 16#0#; + -- no description available + TJTS : DMASR_TJTS_Field := 16#0#; + -- no description available + ROS : DMASR_ROS_Field := 16#0#; + -- no description available + TUS : DMASR_TUS_Field := 16#0#; + -- no description available + RS : DMASR_RS_Field := 16#0#; + -- no description available + RBUS : DMASR_RBUS_Field := 16#0#; + -- no description available + RPSS : DMASR_RPSS_Field := 16#0#; + -- no description available + PWTS : DMASR_PWTS_Field := 16#0#; + -- no description available + ETS : DMASR_ETS_Field := 16#0#; -- unspecified - Reserved_5_5 : STM32F429x.Bit := 16#0#; + Reserved_11_12 : STM32F429x.UInt2 := 16#0#; -- no description available - MR : MACMIIAR_MR_Field := 16#0#; + FBES : DMASR_FBES_Field := 16#0#; -- no description available - PA : MACMIIAR_PA_Field := 16#0#; + ERS : DMASR_ERS_Field := 16#0#; + -- no description available + AIS : DMASR_AIS_Field := 16#0#; + -- no description available + NIS : DMASR_NIS_Field := 16#0#; + -- Read-only. no description available + RPS : DMASR_RPS_Field := 16#0#; + -- Read-only. no description available + TPS : DMASR_TPS_Field := 16#0#; + -- Read-only. no description available + EBS : DMASR_EBS_Field := 16#0#; + -- unspecified + Reserved_26_26 : STM32F429x.Bit := 16#0#; + -- Read-only. no description available + MMCS : DMASR_MMCS_Field := 16#0#; + -- Read-only. no description available + PMTS : DMASR_PMTS_Field := 16#0#; + -- Read-only. no description available + TSTS : DMASR_TSTS_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_30_31 : STM32F429x.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACMIIAR_Register use record - MB at 0 range 0 .. 0; - MW at 0 range 1 .. 1; - CR at 0 range 2 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - MR at 0 range 6 .. 10; - PA at 0 range 11 .. 15; - Reserved_16_31 at 0 range 16 .. 31; - end record; - - ----------------------- - -- MACMIIDR_Register -- - ----------------------- + for DMASR_Register use record + TS at 0 range 0 .. 0; + TPSS at 0 range 1 .. 1; + TBUS at 0 range 2 .. 2; + TJTS at 0 range 3 .. 3; + ROS at 0 range 4 .. 4; + TUS at 0 range 5 .. 5; + RS at 0 range 6 .. 6; + RBUS at 0 range 7 .. 7; + RPSS at 0 range 8 .. 8; + PWTS at 0 range 9 .. 9; + ETS at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + FBES at 0 range 13 .. 13; + ERS at 0 range 14 .. 14; + AIS at 0 range 15 .. 15; + NIS at 0 range 16 .. 16; + RPS at 0 range 17 .. 19; + TPS at 0 range 20 .. 22; + EBS at 0 range 23 .. 25; + Reserved_26_26 at 0 range 26 .. 26; + MMCS at 0 range 27 .. 27; + PMTS at 0 range 28 .. 28; + TSTS at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; - subtype MACMIIDR_TD_Field is STM32F429x.Short; + subtype DMAOMR_SR_Field is STM32F429x.Bit; + subtype DMAOMR_OSF_Field is STM32F429x.Bit; + subtype DMAOMR_RTC_Field is STM32F429x.UInt2; + subtype DMAOMR_FUGF_Field is STM32F429x.Bit; + subtype DMAOMR_FEF_Field is STM32F429x.Bit; + subtype DMAOMR_ST_Field is STM32F429x.Bit; + subtype DMAOMR_TTC_Field is STM32F429x.UInt3; + subtype DMAOMR_FTF_Field is STM32F429x.Bit; + subtype DMAOMR_TSF_Field is STM32F429x.Bit; + subtype DMAOMR_DFRF_Field is STM32F429x.Bit; + subtype DMAOMR_RSF_Field is STM32F429x.Bit; + subtype DMAOMR_DTCEFD_Field is STM32F429x.Bit; - -- Ethernet MAC MII data register - type MACMIIDR_Register is record - -- no description available - TD : MACMIIDR_TD_Field := 16#0#; + -- Ethernet DMA operation mode register + type DMAOMR_Register is record + -- unspecified + Reserved_0_0 : STM32F429x.Bit := 16#0#; + -- SR + SR : DMAOMR_SR_Field := 16#0#; + -- OSF + OSF : DMAOMR_OSF_Field := 16#0#; + -- RTC + RTC : DMAOMR_RTC_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- FUGF + FUGF : DMAOMR_FUGF_Field := 16#0#; + -- FEF + FEF : DMAOMR_FEF_Field := 16#0#; + -- unspecified + Reserved_8_12 : STM32F429x.UInt5 := 16#0#; + -- ST + ST : DMAOMR_ST_Field := 16#0#; + -- TTC + TTC : DMAOMR_TTC_Field := 16#0#; + -- unspecified + Reserved_17_19 : STM32F429x.UInt3 := 16#0#; + -- FTF + FTF : DMAOMR_FTF_Field := 16#0#; + -- TSF + TSF : DMAOMR_TSF_Field := 16#0#; + -- unspecified + Reserved_22_23 : STM32F429x.UInt2 := 16#0#; + -- DFRF + DFRF : DMAOMR_DFRF_Field := 16#0#; + -- RSF + RSF : DMAOMR_RSF_Field := 16#0#; + -- DTCEFD + DTCEFD : DMAOMR_DTCEFD_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACMIIDR_Register use record - TD at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for DMAOMR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + SR at 0 range 1 .. 1; + OSF at 0 range 2 .. 2; + RTC at 0 range 3 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + FUGF at 0 range 6 .. 6; + FEF at 0 range 7 .. 7; + Reserved_8_12 at 0 range 8 .. 12; + ST at 0 range 13 .. 13; + TTC at 0 range 14 .. 16; + Reserved_17_19 at 0 range 17 .. 19; + FTF at 0 range 20 .. 20; + TSF at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + DFRF at 0 range 24 .. 24; + RSF at 0 range 25 .. 25; + DTCEFD at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; end record; - --------------------- - -- MACFCR_Register -- - --------------------- - - subtype MACFCR_FCB_Field is STM32F429x.Bit; - subtype MACFCR_TFCE_Field is STM32F429x.Bit; - subtype MACFCR_RFCE_Field is STM32F429x.Bit; - subtype MACFCR_UPFD_Field is STM32F429x.Bit; - subtype MACFCR_PLT_Field is STM32F429x.UInt2; - subtype MACFCR_ZQPD_Field is STM32F429x.Bit; - subtype MACFCR_PT_Field is STM32F429x.Short; + subtype DMAIER_TIE_Field is STM32F429x.Bit; + subtype DMAIER_TPSIE_Field is STM32F429x.Bit; + subtype DMAIER_TBUIE_Field is STM32F429x.Bit; + subtype DMAIER_TJTIE_Field is STM32F429x.Bit; + subtype DMAIER_ROIE_Field is STM32F429x.Bit; + subtype DMAIER_TUIE_Field is STM32F429x.Bit; + subtype DMAIER_RIE_Field is STM32F429x.Bit; + subtype DMAIER_RBUIE_Field is STM32F429x.Bit; + subtype DMAIER_RPSIE_Field is STM32F429x.Bit; + subtype DMAIER_RWTIE_Field is STM32F429x.Bit; + subtype DMAIER_ETIE_Field is STM32F429x.Bit; + subtype DMAIER_FBEIE_Field is STM32F429x.Bit; + subtype DMAIER_ERIE_Field is STM32F429x.Bit; + subtype DMAIER_AISE_Field is STM32F429x.Bit; + subtype DMAIER_NISE_Field is STM32F429x.Bit; - -- Ethernet MAC flow control register - type MACFCR_Register is record + -- Ethernet DMA interrupt enable register + type DMAIER_Register is record -- no description available - FCB : MACFCR_FCB_Field := 16#0#; + TIE : DMAIER_TIE_Field := 16#0#; -- no description available - TFCE : MACFCR_TFCE_Field := 16#0#; + TPSIE : DMAIER_TPSIE_Field := 16#0#; -- no description available - RFCE : MACFCR_RFCE_Field := 16#0#; + TBUIE : DMAIER_TBUIE_Field := 16#0#; -- no description available - UPFD : MACFCR_UPFD_Field := 16#0#; + TJTIE : DMAIER_TJTIE_Field := 16#0#; -- no description available - PLT : MACFCR_PLT_Field := 16#0#; - -- unspecified - Reserved_6_6 : STM32F429x.Bit := 16#0#; + ROIE : DMAIER_ROIE_Field := 16#0#; -- no description available - ZQPD : MACFCR_ZQPD_Field := 16#0#; + TUIE : DMAIER_TUIE_Field := 16#0#; + -- no description available + RIE : DMAIER_RIE_Field := 16#0#; + -- no description available + RBUIE : DMAIER_RBUIE_Field := 16#0#; + -- no description available + RPSIE : DMAIER_RPSIE_Field := 16#0#; + -- no description available + RWTIE : DMAIER_RWTIE_Field := 16#0#; + -- no description available + ETIE : DMAIER_ETIE_Field := 16#0#; -- unspecified - Reserved_8_15 : STM32F429x.Byte := 16#0#; + Reserved_11_12 : STM32F429x.UInt2 := 16#0#; -- no description available - PT : MACFCR_PT_Field := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for MACFCR_Register use record - FCB at 0 range 0 .. 0; - TFCE at 0 range 1 .. 1; - RFCE at 0 range 2 .. 2; - UPFD at 0 range 3 .. 3; - PLT at 0 range 4 .. 5; - Reserved_6_6 at 0 range 6 .. 6; - ZQPD at 0 range 7 .. 7; - Reserved_8_15 at 0 range 8 .. 15; - PT at 0 range 16 .. 31; - end record; - - ------------------------ - -- MACVLANTR_Register -- - ------------------------ - - subtype MACVLANTR_VLANTI_Field is STM32F429x.Short; - subtype MACVLANTR_VLANTC_Field is STM32F429x.Bit; - - -- Ethernet MAC VLAN tag register - type MACVLANTR_Register is record + FBEIE : DMAIER_FBEIE_Field := 16#0#; -- no description available - VLANTI : MACVLANTR_VLANTI_Field := 16#0#; + ERIE : DMAIER_ERIE_Field := 16#0#; -- no description available - VLANTC : MACVLANTR_VLANTC_Field := 16#0#; + AISE : DMAIER_AISE_Field := 16#0#; + -- no description available + NISE : DMAIER_NISE_Field := 16#0#; -- unspecified Reserved_17_31 : STM32F429x.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACVLANTR_Register use record - VLANTI at 0 range 0 .. 15; - VLANTC at 0 range 16 .. 16; + for DMAIER_Register use record + TIE at 0 range 0 .. 0; + TPSIE at 0 range 1 .. 1; + TBUIE at 0 range 2 .. 2; + TJTIE at 0 range 3 .. 3; + ROIE at 0 range 4 .. 4; + TUIE at 0 range 5 .. 5; + RIE at 0 range 6 .. 6; + RBUIE at 0 range 7 .. 7; + RPSIE at 0 range 8 .. 8; + RWTIE at 0 range 9 .. 9; + ETIE at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + FBEIE at 0 range 13 .. 13; + ERIE at 0 range 14 .. 14; + AISE at 0 range 15 .. 15; + NISE at 0 range 16 .. 16; Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------------ - -- MACPMTCSR_Register -- - ------------------------ - - subtype MACPMTCSR_PD_Field is STM32F429x.Bit; - subtype MACPMTCSR_MPE_Field is STM32F429x.Bit; - subtype MACPMTCSR_WFE_Field is STM32F429x.Bit; - subtype MACPMTCSR_MPR_Field is STM32F429x.Bit; - subtype MACPMTCSR_WFR_Field is STM32F429x.Bit; - subtype MACPMTCSR_GU_Field is STM32F429x.Bit; - subtype MACPMTCSR_WFFRPR_Field is STM32F429x.Bit; + subtype DMAMFBOCR_MFC_Field is STM32F429x.UInt16; + subtype DMAMFBOCR_OMFC_Field is STM32F429x.Bit; + subtype DMAMFBOCR_MFA_Field is STM32F429x.UInt11; + subtype DMAMFBOCR_OFOC_Field is STM32F429x.Bit; - -- Ethernet MAC PMT control and status register - type MACPMTCSR_Register is record - -- no description available - PD : MACPMTCSR_PD_Field := 16#0#; - -- no description available - MPE : MACPMTCSR_MPE_Field := 16#0#; + -- Ethernet DMA missed frame and buffer overflow counter register + type DMAMFBOCR_Register is record -- no description available - WFE : MACPMTCSR_WFE_Field := 16#0#; - -- unspecified - Reserved_3_4 : STM32F429x.UInt2 := 16#0#; + MFC : DMAMFBOCR_MFC_Field := 16#0#; -- no description available - MPR : MACPMTCSR_MPR_Field := 16#0#; + OMFC : DMAMFBOCR_OMFC_Field := 16#0#; -- no description available - WFR : MACPMTCSR_WFR_Field := 16#0#; - -- unspecified - Reserved_7_8 : STM32F429x.UInt2 := 16#0#; + MFA : DMAMFBOCR_MFA_Field := 16#0#; -- no description available - GU : MACPMTCSR_GU_Field := 16#0#; + OFOC : DMAMFBOCR_OFOC_Field := 16#0#; -- unspecified - Reserved_10_30 : STM32F429x.UInt21 := 16#0#; - -- no description available - WFFRPR : MACPMTCSR_WFFRPR_Field := 16#0#; + Reserved_29_31 : STM32F429x.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACPMTCSR_Register use record - PD at 0 range 0 .. 0; - MPE at 0 range 1 .. 1; - WFE at 0 range 2 .. 2; - Reserved_3_4 at 0 range 3 .. 4; - MPR at 0 range 5 .. 5; - WFR at 0 range 6 .. 6; - Reserved_7_8 at 0 range 7 .. 8; - GU at 0 range 9 .. 9; - Reserved_10_30 at 0 range 10 .. 30; - WFFRPR at 0 range 31 .. 31; + for DMAMFBOCR_Register use record + MFC at 0 range 0 .. 15; + OMFC at 0 range 16 .. 16; + MFA at 0 range 17 .. 27; + OFOC at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; end record; - ---------------------- - -- MACDBGR_Register -- - ---------------------- + subtype DMARSWTR_RSWTC_Field is STM32F429x.Byte; - subtype MACDBGR_CR_Field is STM32F429x.Bit; - subtype MACDBGR_CSR_Field is STM32F429x.Bit; - subtype MACDBGR_ROR_Field is STM32F429x.Bit; - subtype MACDBGR_MCF_Field is STM32F429x.Bit; - subtype MACDBGR_MCP_Field is STM32F429x.Bit; - subtype MACDBGR_MCFHP_Field is STM32F429x.Bit; - - -- Ethernet MAC debug register - type MACDBGR_Register is record - -- CR - CR : MACDBGR_CR_Field; - -- CSR - CSR : MACDBGR_CSR_Field; - -- ROR - ROR : MACDBGR_ROR_Field; - -- MCF - MCF : MACDBGR_MCF_Field; - -- MCP - MCP : MACDBGR_MCP_Field; - -- MCFHP - MCFHP : MACDBGR_MCFHP_Field; + -- Ethernet DMA receive status watchdog timer register + type DMARSWTR_Register is record + -- RSWTC + RSWTC : DMARSWTR_RSWTC_Field := 16#0#; -- unspecified - Reserved_6_31 : STM32F429x.UInt26; + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACDBGR_Register use record - CR at 0 range 0 .. 0; - CSR at 0 range 1 .. 1; - ROR at 0 range 2 .. 2; - MCF at 0 range 3 .. 3; - MCP at 0 range 4 .. 4; - MCFHP at 0 range 5 .. 5; - Reserved_6_31 at 0 range 6 .. 31; + for DMARSWTR_Register use record + RSWTC at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; end record; - -------------------- - -- MACSR_Register -- - -------------------- - - subtype MACSR_PMTS_Field is STM32F429x.Bit; - subtype MACSR_MMCS_Field is STM32F429x.Bit; - subtype MACSR_MMCRS_Field is STM32F429x.Bit; - subtype MACSR_MMCTS_Field is STM32F429x.Bit; - subtype MACSR_TSTS_Field is STM32F429x.Bit; + subtype MACCR_RE_Field is STM32F429x.Bit; + subtype MACCR_TE_Field is STM32F429x.Bit; + subtype MACCR_DC_Field is STM32F429x.Bit; + subtype MACCR_BL_Field is STM32F429x.UInt2; + subtype MACCR_APCS_Field is STM32F429x.Bit; + subtype MACCR_RD_Field is STM32F429x.Bit; + subtype MACCR_IPCO_Field is STM32F429x.Bit; + subtype MACCR_DM_Field is STM32F429x.Bit; + subtype MACCR_LM_Field is STM32F429x.Bit; + subtype MACCR_ROD_Field is STM32F429x.Bit; + subtype MACCR_FES_Field is STM32F429x.Bit; + subtype MACCR_CSD_Field is STM32F429x.Bit; + subtype MACCR_IFG_Field is STM32F429x.UInt3; + subtype MACCR_JD_Field is STM32F429x.Bit; + subtype MACCR_WD_Field is STM32F429x.Bit; + subtype MACCR_CSTF_Field is STM32F429x.Bit; - -- Ethernet MAC interrupt status register - type MACSR_Register is record + -- Ethernet MAC configuration register + type MACCR_Register is record -- unspecified - Reserved_0_2 : STM32F429x.UInt3 := 16#0#; + Reserved_0_1 : STM32F429x.UInt2 := 16#0#; + -- RE + RE : MACCR_RE_Field := 16#0#; + -- TE + TE : MACCR_TE_Field := 16#0#; + -- DC + DC : MACCR_DC_Field := 16#0#; + -- BL + BL : MACCR_BL_Field := 16#0#; + -- APCS + APCS : MACCR_APCS_Field := 16#0#; + -- unspecified + Reserved_8_8 : STM32F429x.Bit := 16#0#; + -- RD + RD : MACCR_RD_Field := 16#0#; + -- IPCO + IPCO : MACCR_IPCO_Field := 16#0#; + -- DM + DM : MACCR_DM_Field := 16#0#; + -- LM + LM : MACCR_LM_Field := 16#0#; + -- ROD + ROD : MACCR_ROD_Field := 16#0#; + -- FES + FES : MACCR_FES_Field := 16#0#; + -- unspecified + Reserved_15_15 : STM32F429x.Bit := 16#1#; + -- CSD + CSD : MACCR_CSD_Field := 16#0#; + -- IFG + IFG : MACCR_IFG_Field := 16#0#; + -- unspecified + Reserved_20_21 : STM32F429x.UInt2 := 16#0#; + -- JD + JD : MACCR_JD_Field := 16#0#; + -- WD + WD : MACCR_WD_Field := 16#0#; + -- unspecified + Reserved_24_24 : STM32F429x.Bit := 16#0#; + -- CSTF + CSTF : MACCR_CSTF_Field := 16#0#; + -- unspecified + Reserved_26_31 : STM32F429x.UInt6 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACCR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + RE at 0 range 2 .. 2; + TE at 0 range 3 .. 3; + DC at 0 range 4 .. 4; + BL at 0 range 5 .. 6; + APCS at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + RD at 0 range 9 .. 9; + IPCO at 0 range 10 .. 10; + DM at 0 range 11 .. 11; + LM at 0 range 12 .. 12; + ROD at 0 range 13 .. 13; + FES at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + CSD at 0 range 16 .. 16; + IFG at 0 range 17 .. 19; + Reserved_20_21 at 0 range 20 .. 21; + JD at 0 range 22 .. 22; + WD at 0 range 23 .. 23; + Reserved_24_24 at 0 range 24 .. 24; + CSTF at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype MACFFR_PM_Field is STM32F429x.Bit; + subtype MACFFR_HU_Field is STM32F429x.Bit; + subtype MACFFR_HM_Field is STM32F429x.Bit; + subtype MACFFR_DAIF_Field is STM32F429x.Bit; + subtype MACFFR_RAM_Field is STM32F429x.Bit; + subtype MACFFR_BFD_Field is STM32F429x.Bit; + subtype MACFFR_PCF_Field is STM32F429x.Bit; + subtype MACFFR_SAIF_Field is STM32F429x.Bit; + subtype MACFFR_SAF_Field is STM32F429x.Bit; + subtype MACFFR_HPF_Field is STM32F429x.Bit; + subtype MACFFR_RA_Field is STM32F429x.Bit; + + -- Ethernet MAC frame filter register + type MACFFR_Register is record -- no description available - PMTS : MACSR_PMTS_Field := 16#0#; + PM : MACFFR_PM_Field := 16#0#; -- no description available - MMCS : MACSR_MMCS_Field := 16#0#; + HU : MACFFR_HU_Field := 16#0#; -- no description available - MMCRS : MACSR_MMCRS_Field := 16#0#; + HM : MACFFR_HM_Field := 16#0#; -- no description available - MMCTS : MACSR_MMCTS_Field := 16#0#; - -- unspecified - Reserved_7_8 : STM32F429x.UInt2 := 16#0#; + DAIF : MACFFR_DAIF_Field := 16#0#; -- no description available - TSTS : MACSR_TSTS_Field := 16#0#; + RAM : MACFFR_RAM_Field := 16#0#; + -- no description available + BFD : MACFFR_BFD_Field := 16#0#; + -- no description available + PCF : MACFFR_PCF_Field := 16#0#; + -- no description available + SAIF : MACFFR_SAIF_Field := 16#0#; + -- no description available + SAF : MACFFR_SAF_Field := 16#0#; + -- no description available + HPF : MACFFR_HPF_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + Reserved_10_30 : STM32F429x.UInt21 := 16#0#; + -- no description available + RA : MACFFR_RA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACSR_Register use record - Reserved_0_2 at 0 range 0 .. 2; - PMTS at 0 range 3 .. 3; - MMCS at 0 range 4 .. 4; - MMCRS at 0 range 5 .. 5; - MMCTS at 0 range 6 .. 6; - Reserved_7_8 at 0 range 7 .. 8; - TSTS at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + for MACFFR_Register use record + PM at 0 range 0 .. 0; + HU at 0 range 1 .. 1; + HM at 0 range 2 .. 2; + DAIF at 0 range 3 .. 3; + RAM at 0 range 4 .. 4; + BFD at 0 range 5 .. 5; + PCF at 0 range 6 .. 6; + SAIF at 0 range 7 .. 7; + SAF at 0 range 8 .. 8; + HPF at 0 range 9 .. 9; + Reserved_10_30 at 0 range 10 .. 30; + RA at 0 range 31 .. 31; end record; - --------------------- - -- MACIMR_Register -- - --------------------- - - subtype MACIMR_PMTIM_Field is STM32F429x.Bit; - subtype MACIMR_TSTIM_Field is STM32F429x.Bit; + subtype MACMIIAR_MB_Field is STM32F429x.Bit; + subtype MACMIIAR_MW_Field is STM32F429x.Bit; + subtype MACMIIAR_CR_Field is STM32F429x.UInt3; + subtype MACMIIAR_MR_Field is STM32F429x.UInt5; + subtype MACMIIAR_PA_Field is STM32F429x.UInt5; - -- Ethernet MAC interrupt mask register - type MACIMR_Register is record - -- unspecified - Reserved_0_2 : STM32F429x.UInt3 := 16#0#; + -- Ethernet MAC MII address register + type MACMIIAR_Register is record -- no description available - PMTIM : MACIMR_PMTIM_Field := 16#0#; + MB : MACMIIAR_MB_Field := 16#0#; + -- no description available + MW : MACMIIAR_MW_Field := 16#0#; + -- no description available + CR : MACMIIAR_CR_Field := 16#0#; -- unspecified - Reserved_4_8 : STM32F429x.UInt5 := 16#0#; + Reserved_5_5 : STM32F429x.Bit := 16#0#; -- no description available - TSTIM : MACIMR_TSTIM_Field := 16#0#; + MR : MACMIIAR_MR_Field := 16#0#; + -- no description available + PA : MACMIIAR_PA_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACIMR_Register use record - Reserved_0_2 at 0 range 0 .. 2; - PMTIM at 0 range 3 .. 3; - Reserved_4_8 at 0 range 4 .. 8; - TSTIM at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + for MACMIIAR_Register use record + MB at 0 range 0 .. 0; + MW at 0 range 1 .. 1; + CR at 0 range 2 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + MR at 0 range 6 .. 10; + PA at 0 range 11 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- MACA0HR_Register -- - ---------------------- - - subtype MACA0HR_MACA0H_Field is STM32F429x.Short; - subtype MACA0HR_MO_Field is STM32F429x.Bit; + subtype MACMIIDR_TD_Field is STM32F429x.UInt16; - -- Ethernet MAC address 0 high register - type MACA0HR_Register is record - -- MAC address0 high - MACA0H : MACA0HR_MACA0H_Field := 16#FFFF#; + -- Ethernet MAC MII data register + type MACMIIDR_Register is record + -- no description available + TD : MACMIIDR_TD_Field := 16#0#; -- unspecified - Reserved_16_30 : STM32F429x.UInt15 := 16#10#; - -- Always 1 - MO : MACA0HR_MO_Field := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for MACA0HR_Register use record - MACA0H at 0 range 0 .. 15; - Reserved_16_30 at 0 range 16 .. 30; - MO at 0 range 31 .. 31; + for MACMIIDR_Register use record + TD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- MACA1HR_Register -- - ---------------------- + subtype MACFCR_FCB_Field is STM32F429x.Bit; + subtype MACFCR_TFCE_Field is STM32F429x.Bit; + subtype MACFCR_RFCE_Field is STM32F429x.Bit; + subtype MACFCR_UPFD_Field is STM32F429x.Bit; + subtype MACFCR_PLT_Field is STM32F429x.UInt2; + subtype MACFCR_ZQPD_Field is STM32F429x.Bit; + subtype MACFCR_PT_Field is STM32F429x.UInt16; - subtype MACA1HR_MACA1H_Field is STM32F429x.Short; - subtype MACA1HR_MBC_Field is STM32F429x.UInt6; + -- Ethernet MAC flow control register + type MACFCR_Register is record + -- no description available + FCB : MACFCR_FCB_Field := 16#0#; + -- no description available + TFCE : MACFCR_TFCE_Field := 16#0#; + -- no description available + RFCE : MACFCR_RFCE_Field := 16#0#; + -- no description available + UPFD : MACFCR_UPFD_Field := 16#0#; + -- no description available + PLT : MACFCR_PLT_Field := 16#0#; + -- unspecified + Reserved_6_6 : STM32F429x.Bit := 16#0#; + -- no description available + ZQPD : MACFCR_ZQPD_Field := 16#0#; + -- unspecified + Reserved_8_15 : STM32F429x.Byte := 16#0#; + -- no description available + PT : MACFCR_PT_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACFCR_Register use record + FCB at 0 range 0 .. 0; + TFCE at 0 range 1 .. 1; + RFCE at 0 range 2 .. 2; + UPFD at 0 range 3 .. 3; + PLT at 0 range 4 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + ZQPD at 0 range 7 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + PT at 0 range 16 .. 31; + end record; + + subtype MACVLANTR_VLANTI_Field is STM32F429x.UInt16; + subtype MACVLANTR_VLANTC_Field is STM32F429x.Bit; + + -- Ethernet MAC VLAN tag register + type MACVLANTR_Register is record + -- no description available + VLANTI : MACVLANTR_VLANTI_Field := 16#0#; + -- no description available + VLANTC : MACVLANTR_VLANTC_Field := 16#0#; + -- unspecified + Reserved_17_31 : STM32F429x.UInt15 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACVLANTR_Register use record + VLANTI at 0 range 0 .. 15; + VLANTC at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype MACPMTCSR_PD_Field is STM32F429x.Bit; + subtype MACPMTCSR_MPE_Field is STM32F429x.Bit; + subtype MACPMTCSR_WFE_Field is STM32F429x.Bit; + subtype MACPMTCSR_MPR_Field is STM32F429x.Bit; + subtype MACPMTCSR_WFR_Field is STM32F429x.Bit; + subtype MACPMTCSR_GU_Field is STM32F429x.Bit; + subtype MACPMTCSR_WFFRPR_Field is STM32F429x.Bit; + + -- Ethernet MAC PMT control and status register + type MACPMTCSR_Register is record + -- no description available + PD : MACPMTCSR_PD_Field := 16#0#; + -- no description available + MPE : MACPMTCSR_MPE_Field := 16#0#; + -- no description available + WFE : MACPMTCSR_WFE_Field := 16#0#; + -- unspecified + Reserved_3_4 : STM32F429x.UInt2 := 16#0#; + -- no description available + MPR : MACPMTCSR_MPR_Field := 16#0#; + -- no description available + WFR : MACPMTCSR_WFR_Field := 16#0#; + -- unspecified + Reserved_7_8 : STM32F429x.UInt2 := 16#0#; + -- no description available + GU : MACPMTCSR_GU_Field := 16#0#; + -- unspecified + Reserved_10_30 : STM32F429x.UInt21 := 16#0#; + -- no description available + WFFRPR : MACPMTCSR_WFFRPR_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACPMTCSR_Register use record + PD at 0 range 0 .. 0; + MPE at 0 range 1 .. 1; + WFE at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + MPR at 0 range 5 .. 5; + WFR at 0 range 6 .. 6; + Reserved_7_8 at 0 range 7 .. 8; + GU at 0 range 9 .. 9; + Reserved_10_30 at 0 range 10 .. 30; + WFFRPR at 0 range 31 .. 31; + end record; + + subtype MACDBGR_CR_Field is STM32F429x.Bit; + subtype MACDBGR_CSR_Field is STM32F429x.Bit; + subtype MACDBGR_ROR_Field is STM32F429x.Bit; + subtype MACDBGR_MCF_Field is STM32F429x.Bit; + subtype MACDBGR_MCP_Field is STM32F429x.Bit; + subtype MACDBGR_MCFHP_Field is STM32F429x.Bit; + + -- Ethernet MAC debug register + type MACDBGR_Register is record + -- Read-only. CR + CR : MACDBGR_CR_Field; + -- Read-only. CSR + CSR : MACDBGR_CSR_Field; + -- Read-only. ROR + ROR : MACDBGR_ROR_Field; + -- Read-only. MCF + MCF : MACDBGR_MCF_Field; + -- Read-only. MCP + MCP : MACDBGR_MCP_Field; + -- Read-only. MCFHP + MCFHP : MACDBGR_MCFHP_Field; + -- unspecified + Reserved_6_31 : STM32F429x.UInt26; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACDBGR_Register use record + CR at 0 range 0 .. 0; + CSR at 0 range 1 .. 1; + ROR at 0 range 2 .. 2; + MCF at 0 range 3 .. 3; + MCP at 0 range 4 .. 4; + MCFHP at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype MACSR_PMTS_Field is STM32F429x.Bit; + subtype MACSR_MMCS_Field is STM32F429x.Bit; + subtype MACSR_MMCRS_Field is STM32F429x.Bit; + subtype MACSR_MMCTS_Field is STM32F429x.Bit; + subtype MACSR_TSTS_Field is STM32F429x.Bit; + + -- Ethernet MAC interrupt status register + type MACSR_Register is record + -- unspecified + Reserved_0_2 : STM32F429x.UInt3 := 16#0#; + -- Read-only. no description available + PMTS : MACSR_PMTS_Field := 16#0#; + -- Read-only. no description available + MMCS : MACSR_MMCS_Field := 16#0#; + -- Read-only. no description available + MMCRS : MACSR_MMCRS_Field := 16#0#; + -- Read-only. no description available + MMCTS : MACSR_MMCTS_Field := 16#0#; + -- unspecified + Reserved_7_8 : STM32F429x.UInt2 := 16#0#; + -- no description available + TSTS : MACSR_TSTS_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACSR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + PMTS at 0 range 3 .. 3; + MMCS at 0 range 4 .. 4; + MMCRS at 0 range 5 .. 5; + MMCTS at 0 range 6 .. 6; + Reserved_7_8 at 0 range 7 .. 8; + TSTS at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype MACIMR_PMTIM_Field is STM32F429x.Bit; + subtype MACIMR_TSTIM_Field is STM32F429x.Bit; + + -- Ethernet MAC interrupt mask register + type MACIMR_Register is record + -- unspecified + Reserved_0_2 : STM32F429x.UInt3 := 16#0#; + -- no description available + PMTIM : MACIMR_PMTIM_Field := 16#0#; + -- unspecified + Reserved_4_8 : STM32F429x.UInt5 := 16#0#; + -- no description available + TSTIM : MACIMR_TSTIM_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACIMR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + PMTIM at 0 range 3 .. 3; + Reserved_4_8 at 0 range 4 .. 8; + TSTIM at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype MACA0HR_MACA0H_Field is STM32F429x.UInt16; + subtype MACA0HR_MO_Field is STM32F429x.Bit; + + -- Ethernet MAC address 0 high register + type MACA0HR_Register is record + -- MAC address0 high + MACA0H : MACA0HR_MACA0H_Field := 16#FFFF#; + -- unspecified + Reserved_16_30 : STM32F429x.UInt15 := 16#10#; + -- Read-only. Always 1 + MO : MACA0HR_MO_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for MACA0HR_Register use record + MACA0H at 0 range 0 .. 15; + Reserved_16_30 at 0 range 16 .. 30; + MO at 0 range 31 .. 31; + end record; + + subtype MACA1HR_MACA1H_Field is STM32F429x.UInt16; + subtype MACA1HR_MBC_Field is STM32F429x.UInt6; subtype MACA1HR_SA_Field is STM32F429x.Bit; subtype MACA1HR_AE_Field is STM32F429x.Bit; @@ -505,7 +815,7 @@ package STM32F429x.Ethernet is -- no description available AE : MACA1HR_AE_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MACA1HR_Register use record MACA1H at 0 range 0 .. 15; @@ -515,11 +825,7 @@ package STM32F429x.Ethernet is AE at 0 range 31 .. 31; end record; - ---------------------- - -- MACA2HR_Register -- - ---------------------- - - subtype MACA2HR_MAC2AH_Field is STM32F429x.Short; + subtype MACA2HR_MAC2AH_Field is STM32F429x.UInt16; subtype MACA2HR_MBC_Field is STM32F429x.UInt6; subtype MACA2HR_SA_Field is STM32F429x.Bit; subtype MACA2HR_AE_Field is STM32F429x.Bit; @@ -537,7 +843,7 @@ package STM32F429x.Ethernet is -- no description available AE : MACA2HR_AE_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MACA2HR_Register use record MAC2AH at 0 range 0 .. 15; @@ -547,10 +853,6 @@ package STM32F429x.Ethernet is AE at 0 range 31 .. 31; end record; - ---------------------- - -- MACA2LR_Register -- - ---------------------- - subtype MACA2LR_MACA2L_Field is STM32F429x.UInt31; -- Ethernet MAC address 2 low register @@ -560,18 +862,14 @@ package STM32F429x.Ethernet is -- unspecified Reserved_31_31 : STM32F429x.Bit := 16#1#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MACA2LR_Register use record MACA2L at 0 range 0 .. 30; Reserved_31_31 at 0 range 31 .. 31; end record; - ---------------------- - -- MACA3HR_Register -- - ---------------------- - - subtype MACA3HR_MACA3H_Field is STM32F429x.Short; + subtype MACA3HR_MACA3H_Field is STM32F429x.UInt16; subtype MACA3HR_MBC_Field is STM32F429x.UInt6; subtype MACA3HR_SA_Field is STM32F429x.Bit; subtype MACA3HR_AE_Field is STM32F429x.Bit; @@ -589,7 +887,7 @@ package STM32F429x.Ethernet is -- no description available AE : MACA3HR_AE_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MACA3HR_Register use record MACA3H at 0 range 0 .. 15; @@ -599,10 +897,6 @@ package STM32F429x.Ethernet is AE at 0 range 31 .. 31; end record; - -------------------- - -- MMCCR_Register -- - -------------------- - subtype MMCCR_CR_Field is STM32F429x.Bit; subtype MMCCR_CSR_Field is STM32F429x.Bit; subtype MMCCR_ROR_Field is STM32F429x.Bit; @@ -627,7 +921,7 @@ package STM32F429x.Ethernet is -- unspecified Reserved_6_31 : STM32F429x.UInt26 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MMCCR_Register use record CR at 0 range 0 .. 0; @@ -639,10 +933,6 @@ package STM32F429x.Ethernet is Reserved_6_31 at 0 range 6 .. 31; end record; - --------------------- - -- MMCRIR_Register -- - --------------------- - subtype MMCRIR_RFCES_Field is STM32F429x.Bit; subtype MMCRIR_RFAES_Field is STM32F429x.Bit; subtype MMCRIR_RGUFS_Field is STM32F429x.Bit; @@ -662,7 +952,7 @@ package STM32F429x.Ethernet is -- unspecified Reserved_18_31 : STM32F429x.UInt14 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MMCRIR_Register use record Reserved_0_4 at 0 range 0 .. 4; @@ -673,10 +963,6 @@ package STM32F429x.Ethernet is Reserved_18_31 at 0 range 18 .. 31; end record; - --------------------- - -- MMCTIR_Register -- - --------------------- - subtype MMCTIR_TGFSCS_Field is STM32F429x.Bit; subtype MMCTIR_TGFMSCS_Field is STM32F429x.Bit; subtype MMCTIR_TGFS_Field is STM32F429x.Bit; @@ -685,18 +971,18 @@ package STM32F429x.Ethernet is type MMCTIR_Register is record -- unspecified Reserved_0_13 : STM32F429x.UInt14; - -- no description available + -- Read-only. no description available TGFSCS : MMCTIR_TGFSCS_Field; - -- no description available + -- Read-only. no description available TGFMSCS : MMCTIR_TGFMSCS_Field; -- unspecified Reserved_16_20 : STM32F429x.UInt5; - -- no description available + -- Read-only. no description available TGFS : MMCTIR_TGFS_Field; -- unspecified Reserved_22_31 : STM32F429x.UInt10; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MMCTIR_Register use record Reserved_0_13 at 0 range 0 .. 13; @@ -707,10 +993,6 @@ package STM32F429x.Ethernet is Reserved_22_31 at 0 range 22 .. 31; end record; - ---------------------- - -- MMCRIMR_Register -- - ---------------------- - subtype MMCRIMR_RFCEM_Field is STM32F429x.Bit; subtype MMCRIMR_RFAEM_Field is STM32F429x.Bit; subtype MMCRIMR_RGUFM_Field is STM32F429x.Bit; @@ -730,7 +1012,7 @@ package STM32F429x.Ethernet is -- unspecified Reserved_18_31 : STM32F429x.UInt14 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MMCRIMR_Register use record Reserved_0_4 at 0 range 0 .. 4; @@ -741,10 +1023,6 @@ package STM32F429x.Ethernet is Reserved_18_31 at 0 range 18 .. 31; end record; - ---------------------- - -- MMCTIMR_Register -- - ---------------------- - subtype MMCTIMR_TGFSCM_Field is STM32F429x.Bit; subtype MMCTIMR_TGFMSCM_Field is STM32F429x.Bit; subtype MMCTIMR_TGFM_Field is STM32F429x.Bit; @@ -762,808 +1040,436 @@ package STM32F429x.Ethernet is -- unspecified Reserved_17_31 : STM32F429x.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MMCTIMR_Register use record Reserved_0_13 at 0 range 0 .. 13; TGFSCM at 0 range 14 .. 14; - TGFMSCM at 0 range 15 .. 15; - TGFM at 0 range 16 .. 16; - Reserved_17_31 at 0 range 17 .. 31; - end record; - - ---------------------- - -- PTPTSCR_Register -- - ---------------------- - - subtype PTPTSCR_TSE_Field is STM32F429x.Bit; - subtype PTPTSCR_TSFCU_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSTI_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSTU_Field is STM32F429x.Bit; - subtype PTPTSCR_TSITE_Field is STM32F429x.Bit; - subtype PTPTSCR_TTSARU_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSARFE_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSSR_Field is STM32F429x.Bit; - subtype PTPTSCR_TSPTPPSV2E_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSPTPOEFE_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSIPV6FE_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSIPV4FE_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSEME_Field is STM32F429x.Bit; - subtype PTPTSCR_TSSMRME_Field is STM32F429x.Bit; - subtype PTPTSCR_TSCNT_Field is STM32F429x.UInt2; - subtype PTPTSCR_TSPFFMAE_Field is STM32F429x.Bit; - - -- Ethernet PTP time stamp control register - type PTPTSCR_Register is record - -- no description available - TSE : PTPTSCR_TSE_Field := 16#0#; - -- no description available - TSFCU : PTPTSCR_TSFCU_Field := 16#0#; - -- no description available - TSSTI : PTPTSCR_TSSTI_Field := 16#0#; - -- no description available - TSSTU : PTPTSCR_TSSTU_Field := 16#0#; - -- no description available - TSITE : PTPTSCR_TSITE_Field := 16#0#; - -- no description available - TTSARU : PTPTSCR_TTSARU_Field := 16#0#; - -- unspecified - Reserved_6_7 : STM32F429x.UInt2 := 16#0#; - -- no description available - TSSARFE : PTPTSCR_TSSARFE_Field := 16#0#; - -- no description available - TSSSR : PTPTSCR_TSSSR_Field := 16#0#; - -- no description available - TSPTPPSV2E : PTPTSCR_TSPTPPSV2E_Field := 16#0#; - -- no description available - TSSPTPOEFE : PTPTSCR_TSSPTPOEFE_Field := 16#0#; - -- no description available - TSSIPV6FE : PTPTSCR_TSSIPV6FE_Field := 16#0#; - -- no description available - TSSIPV4FE : PTPTSCR_TSSIPV4FE_Field := 16#1#; - -- no description available - TSSEME : PTPTSCR_TSSEME_Field := 16#0#; - -- no description available - TSSMRME : PTPTSCR_TSSMRME_Field := 16#0#; - -- no description available - TSCNT : PTPTSCR_TSCNT_Field := 16#0#; - -- no description available - TSPFFMAE : PTPTSCR_TSPFFMAE_Field := 16#0#; - -- unspecified - Reserved_19_31 : STM32F429x.UInt13 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for PTPTSCR_Register use record - TSE at 0 range 0 .. 0; - TSFCU at 0 range 1 .. 1; - TSSTI at 0 range 2 .. 2; - TSSTU at 0 range 3 .. 3; - TSITE at 0 range 4 .. 4; - TTSARU at 0 range 5 .. 5; - Reserved_6_7 at 0 range 6 .. 7; - TSSARFE at 0 range 8 .. 8; - TSSSR at 0 range 9 .. 9; - TSPTPPSV2E at 0 range 10 .. 10; - TSSPTPOEFE at 0 range 11 .. 11; - TSSIPV6FE at 0 range 12 .. 12; - TSSIPV4FE at 0 range 13 .. 13; - TSSEME at 0 range 14 .. 14; - TSSMRME at 0 range 15 .. 15; - TSCNT at 0 range 16 .. 17; - TSPFFMAE at 0 range 18 .. 18; - Reserved_19_31 at 0 range 19 .. 31; - end record; - - ---------------------- - -- PTPSSIR_Register -- - ---------------------- - - subtype PTPSSIR_STSSI_Field is STM32F429x.Byte; - - -- Ethernet PTP subsecond increment register - type PTPSSIR_Register is record - -- no description available - STSSI : PTPSSIR_STSSI_Field := 16#0#; - -- unspecified - Reserved_8_31 : STM32F429x.UInt24 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for PTPSSIR_Register use record - STSSI at 0 range 0 .. 7; - Reserved_8_31 at 0 range 8 .. 31; - end record; - - ---------------------- - -- PTPTSLR_Register -- - ---------------------- - - subtype PTPTSLR_STSS_Field is STM32F429x.UInt31; - subtype PTPTSLR_STPNS_Field is STM32F429x.Bit; - - -- Ethernet PTP time stamp low register - type PTPTSLR_Register is record - -- no description available - STSS : PTPTSLR_STSS_Field; - -- no description available - STPNS : PTPTSLR_STPNS_Field; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for PTPTSLR_Register use record - STSS at 0 range 0 .. 30; - STPNS at 0 range 31 .. 31; - end record; - - ----------------------- - -- PTPTSLUR_Register -- - ----------------------- - - subtype PTPTSLUR_TSUSS_Field is STM32F429x.UInt31; - subtype PTPTSLUR_TSUPNS_Field is STM32F429x.Bit; - - -- Ethernet PTP time stamp low update register - type PTPTSLUR_Register is record - -- no description available - TSUSS : PTPTSLUR_TSUSS_Field := 16#0#; - -- no description available - TSUPNS : PTPTSLUR_TSUPNS_Field := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for PTPTSLUR_Register use record - TSUSS at 0 range 0 .. 30; - TSUPNS at 0 range 31 .. 31; - end record; - - ---------------------- - -- PTPTSSR_Register -- - ---------------------- - - subtype PTPTSSR_TSSO_Field is STM32F429x.Bit; - subtype PTPTSSR_TSTTR_Field is STM32F429x.Bit; - - -- Ethernet PTP time stamp status register - type PTPTSSR_Register is record - -- no description available - TSSO : PTPTSSR_TSSO_Field; - -- no description available - TSTTR : PTPTSSR_TSTTR_Field; - -- unspecified - Reserved_2_31 : STM32F429x.UInt30; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for PTPTSSR_Register use record - TSSO at 0 range 0 .. 0; - TSTTR at 0 range 1 .. 1; - Reserved_2_31 at 0 range 2 .. 31; - end record; - - ----------------------- - -- PTPPPSCR_Register -- - ----------------------- - - subtype PTPPPSCR_TSSO_Field is STM32F429x.Bit; - subtype PTPPPSCR_TSTTR_Field is STM32F429x.Bit; - - -- Ethernet PTP PPS control register - type PTPPPSCR_Register is record - -- TSSO - TSSO : PTPPPSCR_TSSO_Field; - -- TSTTR - TSTTR : PTPPPSCR_TSTTR_Field; - -- unspecified - Reserved_2_31 : STM32F429x.UInt30; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for PTPPPSCR_Register use record - TSSO at 0 range 0 .. 0; - TSTTR at 0 range 1 .. 1; - Reserved_2_31 at 0 range 2 .. 31; - end record; - - --------------------- - -- DMABMR_Register -- - --------------------- - - subtype DMABMR_SR_Field is STM32F429x.Bit; - subtype DMABMR_DA_Field is STM32F429x.Bit; - subtype DMABMR_DSL_Field is STM32F429x.UInt5; - subtype DMABMR_EDFE_Field is STM32F429x.Bit; - subtype DMABMR_PBL_Field is STM32F429x.UInt6; - subtype DMABMR_RTPR_Field is STM32F429x.UInt2; - subtype DMABMR_FB_Field is STM32F429x.Bit; - subtype DMABMR_RDP_Field is STM32F429x.UInt6; - subtype DMABMR_USP_Field is STM32F429x.Bit; - subtype DMABMR_FPM_Field is STM32F429x.Bit; - subtype DMABMR_AAB_Field is STM32F429x.Bit; - subtype DMABMR_MB_Field is STM32F429x.Bit; - - -- Ethernet DMA bus mode register - type DMABMR_Register is record - -- no description available - SR : DMABMR_SR_Field := 16#1#; - -- no description available - DA : DMABMR_DA_Field := 16#0#; - -- no description available - DSL : DMABMR_DSL_Field := 16#0#; - -- no description available - EDFE : DMABMR_EDFE_Field := 16#0#; - -- no description available - PBL : DMABMR_PBL_Field := 16#21#; - -- no description available - RTPR : DMABMR_RTPR_Field := 16#0#; - -- no description available - FB : DMABMR_FB_Field := 16#0#; - -- no description available - RDP : DMABMR_RDP_Field := 16#0#; - -- no description available - USP : DMABMR_USP_Field := 16#0#; - -- no description available - FPM : DMABMR_FPM_Field := 16#0#; - -- no description available - AAB : DMABMR_AAB_Field := 16#0#; - -- no description available - MB : DMABMR_MB_Field := 16#0#; - -- unspecified - Reserved_27_31 : STM32F429x.UInt5 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for DMABMR_Register use record - SR at 0 range 0 .. 0; - DA at 0 range 1 .. 1; - DSL at 0 range 2 .. 6; - EDFE at 0 range 7 .. 7; - PBL at 0 range 8 .. 13; - RTPR at 0 range 14 .. 15; - FB at 0 range 16 .. 16; - RDP at 0 range 17 .. 22; - USP at 0 range 23 .. 23; - FPM at 0 range 24 .. 24; - AAB at 0 range 25 .. 25; - MB at 0 range 26 .. 26; - Reserved_27_31 at 0 range 27 .. 31; - end record; - - -------------------- - -- DMASR_Register -- - -------------------- - - subtype DMASR_TS_Field is STM32F429x.Bit; - subtype DMASR_TPSS_Field is STM32F429x.Bit; - subtype DMASR_TBUS_Field is STM32F429x.Bit; - subtype DMASR_TJTS_Field is STM32F429x.Bit; - subtype DMASR_ROS_Field is STM32F429x.Bit; - subtype DMASR_TUS_Field is STM32F429x.Bit; - subtype DMASR_RS_Field is STM32F429x.Bit; - subtype DMASR_RBUS_Field is STM32F429x.Bit; - subtype DMASR_RPSS_Field is STM32F429x.Bit; - subtype DMASR_PWTS_Field is STM32F429x.Bit; - subtype DMASR_ETS_Field is STM32F429x.Bit; - subtype DMASR_FBES_Field is STM32F429x.Bit; - subtype DMASR_ERS_Field is STM32F429x.Bit; - subtype DMASR_AIS_Field is STM32F429x.Bit; - subtype DMASR_NIS_Field is STM32F429x.Bit; - subtype DMASR_RPS_Field is STM32F429x.UInt3; - subtype DMASR_TPS_Field is STM32F429x.UInt3; - subtype DMASR_EBS_Field is STM32F429x.UInt3; - subtype DMASR_MMCS_Field is STM32F429x.Bit; - subtype DMASR_PMTS_Field is STM32F429x.Bit; - subtype DMASR_TSTS_Field is STM32F429x.Bit; - - -- Ethernet DMA status register - type DMASR_Register is record - -- no description available - TS : DMASR_TS_Field := 16#0#; - -- no description available - TPSS : DMASR_TPSS_Field := 16#0#; - -- no description available - TBUS : DMASR_TBUS_Field := 16#0#; - -- no description available - TJTS : DMASR_TJTS_Field := 16#0#; - -- no description available - ROS : DMASR_ROS_Field := 16#0#; - -- no description available - TUS : DMASR_TUS_Field := 16#0#; - -- no description available - RS : DMASR_RS_Field := 16#0#; - -- no description available - RBUS : DMASR_RBUS_Field := 16#0#; - -- no description available - RPSS : DMASR_RPSS_Field := 16#0#; - -- no description available - PWTS : DMASR_PWTS_Field := 16#0#; - -- no description available - ETS : DMASR_ETS_Field := 16#0#; - -- unspecified - Reserved_11_12 : STM32F429x.UInt2 := 16#0#; - -- no description available - FBES : DMASR_FBES_Field := 16#0#; - -- no description available - ERS : DMASR_ERS_Field := 16#0#; - -- no description available - AIS : DMASR_AIS_Field := 16#0#; - -- no description available - NIS : DMASR_NIS_Field := 16#0#; - -- no description available - RPS : DMASR_RPS_Field := 16#0#; - -- no description available - TPS : DMASR_TPS_Field := 16#0#; - -- no description available - EBS : DMASR_EBS_Field := 16#0#; - -- unspecified - Reserved_26_26 : STM32F429x.Bit := 16#0#; - -- no description available - MMCS : DMASR_MMCS_Field := 16#0#; - -- no description available - PMTS : DMASR_PMTS_Field := 16#0#; - -- no description available - TSTS : DMASR_TSTS_Field := 16#0#; - -- unspecified - Reserved_30_31 : STM32F429x.UInt2 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for DMASR_Register use record - TS at 0 range 0 .. 0; - TPSS at 0 range 1 .. 1; - TBUS at 0 range 2 .. 2; - TJTS at 0 range 3 .. 3; - ROS at 0 range 4 .. 4; - TUS at 0 range 5 .. 5; - RS at 0 range 6 .. 6; - RBUS at 0 range 7 .. 7; - RPSS at 0 range 8 .. 8; - PWTS at 0 range 9 .. 9; - ETS at 0 range 10 .. 10; - Reserved_11_12 at 0 range 11 .. 12; - FBES at 0 range 13 .. 13; - ERS at 0 range 14 .. 14; - AIS at 0 range 15 .. 15; - NIS at 0 range 16 .. 16; - RPS at 0 range 17 .. 19; - TPS at 0 range 20 .. 22; - EBS at 0 range 23 .. 25; - Reserved_26_26 at 0 range 26 .. 26; - MMCS at 0 range 27 .. 27; - PMTS at 0 range 28 .. 28; - TSTS at 0 range 29 .. 29; - Reserved_30_31 at 0 range 30 .. 31; - end record; - - --------------------- - -- DMAOMR_Register -- - --------------------- - - subtype DMAOMR_SR_Field is STM32F429x.Bit; - subtype DMAOMR_OSF_Field is STM32F429x.Bit; - subtype DMAOMR_RTC_Field is STM32F429x.UInt2; - subtype DMAOMR_FUGF_Field is STM32F429x.Bit; - subtype DMAOMR_FEF_Field is STM32F429x.Bit; - subtype DMAOMR_ST_Field is STM32F429x.Bit; - subtype DMAOMR_TTC_Field is STM32F429x.UInt3; - subtype DMAOMR_FTF_Field is STM32F429x.Bit; - subtype DMAOMR_TSF_Field is STM32F429x.Bit; - subtype DMAOMR_DFRF_Field is STM32F429x.Bit; - subtype DMAOMR_RSF_Field is STM32F429x.Bit; - subtype DMAOMR_DTCEFD_Field is STM32F429x.Bit; - - -- Ethernet DMA operation mode register - type DMAOMR_Register is record - -- unspecified - Reserved_0_0 : STM32F429x.Bit := 16#0#; - -- SR - SR : DMAOMR_SR_Field := 16#0#; - -- OSF - OSF : DMAOMR_OSF_Field := 16#0#; - -- RTC - RTC : DMAOMR_RTC_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F429x.Bit := 16#0#; - -- FUGF - FUGF : DMAOMR_FUGF_Field := 16#0#; - -- FEF - FEF : DMAOMR_FEF_Field := 16#0#; - -- unspecified - Reserved_8_12 : STM32F429x.UInt5 := 16#0#; - -- ST - ST : DMAOMR_ST_Field := 16#0#; - -- TTC - TTC : DMAOMR_TTC_Field := 16#0#; - -- unspecified - Reserved_17_19 : STM32F429x.UInt3 := 16#0#; - -- FTF - FTF : DMAOMR_FTF_Field := 16#0#; - -- TSF - TSF : DMAOMR_TSF_Field := 16#0#; - -- unspecified - Reserved_22_23 : STM32F429x.UInt2 := 16#0#; - -- DFRF - DFRF : DMAOMR_DFRF_Field := 16#0#; - -- RSF - RSF : DMAOMR_RSF_Field := 16#0#; - -- DTCEFD - DTCEFD : DMAOMR_DTCEFD_Field := 16#0#; - -- unspecified - Reserved_27_31 : STM32F429x.UInt5 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for DMAOMR_Register use record - Reserved_0_0 at 0 range 0 .. 0; - SR at 0 range 1 .. 1; - OSF at 0 range 2 .. 2; - RTC at 0 range 3 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - FUGF at 0 range 6 .. 6; - FEF at 0 range 7 .. 7; - Reserved_8_12 at 0 range 8 .. 12; - ST at 0 range 13 .. 13; - TTC at 0 range 14 .. 16; - Reserved_17_19 at 0 range 17 .. 19; - FTF at 0 range 20 .. 20; - TSF at 0 range 21 .. 21; - Reserved_22_23 at 0 range 22 .. 23; - DFRF at 0 range 24 .. 24; - RSF at 0 range 25 .. 25; - DTCEFD at 0 range 26 .. 26; - Reserved_27_31 at 0 range 27 .. 31; + TGFMSCM at 0 range 15 .. 15; + TGFM at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; end record; - --------------------- - -- DMAIER_Register -- - --------------------- - - subtype DMAIER_TIE_Field is STM32F429x.Bit; - subtype DMAIER_TPSIE_Field is STM32F429x.Bit; - subtype DMAIER_TBUIE_Field is STM32F429x.Bit; - subtype DMAIER_TJTIE_Field is STM32F429x.Bit; - subtype DMAIER_ROIE_Field is STM32F429x.Bit; - subtype DMAIER_TUIE_Field is STM32F429x.Bit; - subtype DMAIER_RIE_Field is STM32F429x.Bit; - subtype DMAIER_RBUIE_Field is STM32F429x.Bit; - subtype DMAIER_RPSIE_Field is STM32F429x.Bit; - subtype DMAIER_RWTIE_Field is STM32F429x.Bit; - subtype DMAIER_ETIE_Field is STM32F429x.Bit; - subtype DMAIER_FBEIE_Field is STM32F429x.Bit; - subtype DMAIER_ERIE_Field is STM32F429x.Bit; - subtype DMAIER_AISE_Field is STM32F429x.Bit; - subtype DMAIER_NISE_Field is STM32F429x.Bit; + subtype PTPTSCR_TSE_Field is STM32F429x.Bit; + subtype PTPTSCR_TSFCU_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSTI_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSTU_Field is STM32F429x.Bit; + subtype PTPTSCR_TSITE_Field is STM32F429x.Bit; + subtype PTPTSCR_TTSARU_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSARFE_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSSR_Field is STM32F429x.Bit; + subtype PTPTSCR_TSPTPPSV2E_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSPTPOEFE_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSIPV6FE_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSIPV4FE_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSEME_Field is STM32F429x.Bit; + subtype PTPTSCR_TSSMRME_Field is STM32F429x.Bit; + subtype PTPTSCR_TSCNT_Field is STM32F429x.UInt2; + subtype PTPTSCR_TSPFFMAE_Field is STM32F429x.Bit; - -- Ethernet DMA interrupt enable register - type DMAIER_Register is record + -- Ethernet PTP time stamp control register + type PTPTSCR_Register is record -- no description available - TIE : DMAIER_TIE_Field := 16#0#; + TSE : PTPTSCR_TSE_Field := 16#0#; -- no description available - TPSIE : DMAIER_TPSIE_Field := 16#0#; + TSFCU : PTPTSCR_TSFCU_Field := 16#0#; -- no description available - TBUIE : DMAIER_TBUIE_Field := 16#0#; + TSSTI : PTPTSCR_TSSTI_Field := 16#0#; -- no description available - TJTIE : DMAIER_TJTIE_Field := 16#0#; + TSSTU : PTPTSCR_TSSTU_Field := 16#0#; -- no description available - ROIE : DMAIER_ROIE_Field := 16#0#; + TSITE : PTPTSCR_TSITE_Field := 16#0#; -- no description available - TUIE : DMAIER_TUIE_Field := 16#0#; + TTSARU : PTPTSCR_TTSARU_Field := 16#0#; + -- unspecified + Reserved_6_7 : STM32F429x.UInt2 := 16#0#; -- no description available - RIE : DMAIER_RIE_Field := 16#0#; + TSSARFE : PTPTSCR_TSSARFE_Field := 16#0#; -- no description available - RBUIE : DMAIER_RBUIE_Field := 16#0#; + TSSSR : PTPTSCR_TSSSR_Field := 16#0#; -- no description available - RPSIE : DMAIER_RPSIE_Field := 16#0#; + TSPTPPSV2E : PTPTSCR_TSPTPPSV2E_Field := 16#0#; -- no description available - RWTIE : DMAIER_RWTIE_Field := 16#0#; + TSSPTPOEFE : PTPTSCR_TSSPTPOEFE_Field := 16#0#; -- no description available - ETIE : DMAIER_ETIE_Field := 16#0#; - -- unspecified - Reserved_11_12 : STM32F429x.UInt2 := 16#0#; + TSSIPV6FE : PTPTSCR_TSSIPV6FE_Field := 16#0#; -- no description available - FBEIE : DMAIER_FBEIE_Field := 16#0#; + TSSIPV4FE : PTPTSCR_TSSIPV4FE_Field := 16#1#; -- no description available - ERIE : DMAIER_ERIE_Field := 16#0#; + TSSEME : PTPTSCR_TSSEME_Field := 16#0#; -- no description available - AISE : DMAIER_AISE_Field := 16#0#; + TSSMRME : PTPTSCR_TSSMRME_Field := 16#0#; -- no description available - NISE : DMAIER_NISE_Field := 16#0#; + TSCNT : PTPTSCR_TSCNT_Field := 16#0#; + -- no description available + TSPFFMAE : PTPTSCR_TSPFFMAE_Field := 16#0#; -- unspecified - Reserved_17_31 : STM32F429x.UInt15 := 16#0#; + Reserved_19_31 : STM32F429x.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMAIER_Register use record - TIE at 0 range 0 .. 0; - TPSIE at 0 range 1 .. 1; - TBUIE at 0 range 2 .. 2; - TJTIE at 0 range 3 .. 3; - ROIE at 0 range 4 .. 4; - TUIE at 0 range 5 .. 5; - RIE at 0 range 6 .. 6; - RBUIE at 0 range 7 .. 7; - RPSIE at 0 range 8 .. 8; - RWTIE at 0 range 9 .. 9; - ETIE at 0 range 10 .. 10; - Reserved_11_12 at 0 range 11 .. 12; - FBEIE at 0 range 13 .. 13; - ERIE at 0 range 14 .. 14; - AISE at 0 range 15 .. 15; - NISE at 0 range 16 .. 16; - Reserved_17_31 at 0 range 17 .. 31; + for PTPTSCR_Register use record + TSE at 0 range 0 .. 0; + TSFCU at 0 range 1 .. 1; + TSSTI at 0 range 2 .. 2; + TSSTU at 0 range 3 .. 3; + TSITE at 0 range 4 .. 4; + TTSARU at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + TSSARFE at 0 range 8 .. 8; + TSSSR at 0 range 9 .. 9; + TSPTPPSV2E at 0 range 10 .. 10; + TSSPTPOEFE at 0 range 11 .. 11; + TSSIPV6FE at 0 range 12 .. 12; + TSSIPV4FE at 0 range 13 .. 13; + TSSEME at 0 range 14 .. 14; + TSSMRME at 0 range 15 .. 15; + TSCNT at 0 range 16 .. 17; + TSPFFMAE at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------------ - -- DMAMFBOCR_Register -- - ------------------------ - - subtype DMAMFBOCR_MFC_Field is STM32F429x.Short; - subtype DMAMFBOCR_OMFC_Field is STM32F429x.Bit; - subtype DMAMFBOCR_MFA_Field is STM32F429x.UInt11; - subtype DMAMFBOCR_OFOC_Field is STM32F429x.Bit; + subtype PTPSSIR_STSSI_Field is STM32F429x.Byte; - -- Ethernet DMA missed frame and buffer overflow counter register - type DMAMFBOCR_Register is record - -- no description available - MFC : DMAMFBOCR_MFC_Field := 16#0#; + -- Ethernet PTP subsecond increment register + type PTPSSIR_Register is record -- no description available - OMFC : DMAMFBOCR_OMFC_Field := 16#0#; + STSSI : PTPSSIR_STSSI_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for PTPSSIR_Register use record + STSSI at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PTPTSLR_STSS_Field is STM32F429x.UInt31; + subtype PTPTSLR_STPNS_Field is STM32F429x.Bit; + + -- Ethernet PTP time stamp low register + type PTPTSLR_Register is record + -- Read-only. no description available + STSS : PTPTSLR_STSS_Field; + -- Read-only. no description available + STPNS : PTPTSLR_STPNS_Field; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for PTPTSLR_Register use record + STSS at 0 range 0 .. 30; + STPNS at 0 range 31 .. 31; + end record; + + subtype PTPTSLUR_TSUSS_Field is STM32F429x.UInt31; + subtype PTPTSLUR_TSUPNS_Field is STM32F429x.Bit; + + -- Ethernet PTP time stamp low update register + type PTPTSLUR_Register is record -- no description available - MFA : DMAMFBOCR_MFA_Field := 16#0#; + TSUSS : PTPTSLUR_TSUSS_Field := 16#0#; -- no description available - OFOC : DMAMFBOCR_OFOC_Field := 16#0#; - -- unspecified - Reserved_29_31 : STM32F429x.UInt3 := 16#0#; + TSUPNS : PTPTSLUR_TSUPNS_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMAMFBOCR_Register use record - MFC at 0 range 0 .. 15; - OMFC at 0 range 16 .. 16; - MFA at 0 range 17 .. 27; - OFOC at 0 range 28 .. 28; - Reserved_29_31 at 0 range 29 .. 31; + for PTPTSLUR_Register use record + TSUSS at 0 range 0 .. 30; + TSUPNS at 0 range 31 .. 31; end record; - ----------------------- - -- DMARSWTR_Register -- - ----------------------- + subtype PTPTSSR_TSSO_Field is STM32F429x.Bit; + subtype PTPTSSR_TSTTR_Field is STM32F429x.Bit; - subtype DMARSWTR_RSWTC_Field is STM32F429x.Byte; + -- Ethernet PTP time stamp status register + type PTPTSSR_Register is record + -- Read-only. no description available + TSSO : PTPTSSR_TSSO_Field; + -- Read-only. no description available + TSTTR : PTPTSSR_TSTTR_Field; + -- unspecified + Reserved_2_31 : STM32F429x.UInt30; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- Ethernet DMA receive status watchdog timer register - type DMARSWTR_Register is record - -- RSWTC - RSWTC : DMARSWTR_RSWTC_Field := 16#0#; + for PTPTSSR_Register use record + TSSO at 0 range 0 .. 0; + TSTTR at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype PTPPPSCR_TSSO_Field is STM32F429x.Bit; + subtype PTPPPSCR_TSTTR_Field is STM32F429x.Bit; + + -- Ethernet PTP PPS control register + type PTPPPSCR_Register is record + -- Read-only. TSSO + TSSO : PTPPPSCR_TSSO_Field; + -- Read-only. TSTTR + TSTTR : PTPPPSCR_TSTTR_Field; -- unspecified - Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + Reserved_2_31 : STM32F429x.UInt30; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DMARSWTR_Register use record - RSWTC at 0 range 0 .. 7; - Reserved_8_31 at 0 range 8 .. 31; + for PTPPPSCR_Register use record + TSSO at 0 range 0 .. 0; + TSTTR at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; end record; ----------------- -- Peripherals -- ----------------- + -- Ethernet: DMA controller operation + type Ethernet_DMA_Peripheral is record + -- Ethernet DMA bus mode register + DMABMR : aliased DMABMR_Register; + pragma Volatile_Full_Access (DMABMR); + -- Ethernet DMA transmit poll demand register + DMATPDR : aliased STM32F429x.UInt32; + -- EHERNET DMA receive poll demand register + DMARPDR : aliased STM32F429x.UInt32; + -- Ethernet DMA receive descriptor list address register + DMARDLAR : aliased STM32F429x.UInt32; + -- Ethernet DMA transmit descriptor list address register + DMATDLAR : aliased STM32F429x.UInt32; + -- Ethernet DMA status register + DMASR : aliased DMASR_Register; + pragma Volatile_Full_Access (DMASR); + -- Ethernet DMA operation mode register + DMAOMR : aliased DMAOMR_Register; + pragma Volatile_Full_Access (DMAOMR); + -- Ethernet DMA interrupt enable register + DMAIER : aliased DMAIER_Register; + pragma Volatile_Full_Access (DMAIER); + -- Ethernet DMA missed frame and buffer overflow counter register + DMAMFBOCR : aliased DMAMFBOCR_Register; + pragma Volatile_Full_Access (DMAMFBOCR); + -- Ethernet DMA receive status watchdog timer register + DMARSWTR : aliased DMARSWTR_Register; + pragma Volatile_Full_Access (DMARSWTR); + -- Ethernet DMA current host transmit descriptor register + DMACHTDR : aliased STM32F429x.UInt32; + -- Ethernet DMA current host receive descriptor register + DMACHRDR : aliased STM32F429x.UInt32; + -- Ethernet DMA current host transmit buffer address register + DMACHTBAR : aliased STM32F429x.UInt32; + -- Ethernet DMA current host receive buffer address register + DMACHRBAR : aliased STM32F429x.UInt32; + end record + with Volatile; + + for Ethernet_DMA_Peripheral use record + DMABMR at 16#0# range 0 .. 31; + DMATPDR at 16#4# range 0 .. 31; + DMARPDR at 16#8# range 0 .. 31; + DMARDLAR at 16#C# range 0 .. 31; + DMATDLAR at 16#10# range 0 .. 31; + DMASR at 16#14# range 0 .. 31; + DMAOMR at 16#18# range 0 .. 31; + DMAIER at 16#1C# range 0 .. 31; + DMAMFBOCR at 16#20# range 0 .. 31; + DMARSWTR at 16#24# range 0 .. 31; + DMACHTDR at 16#48# range 0 .. 31; + DMACHRDR at 16#4C# range 0 .. 31; + DMACHTBAR at 16#50# range 0 .. 31; + DMACHRBAR at 16#54# range 0 .. 31; + end record; + + -- Ethernet: DMA controller operation + Ethernet_DMA_Periph : aliased Ethernet_DMA_Peripheral + with Import, Address => Ethernet_DMA_Base; + -- Ethernet: media access control (MAC) type Ethernet_MAC_Peripheral is record -- Ethernet MAC configuration register - MACCR : MACCR_Register; + MACCR : aliased MACCR_Register; + pragma Volatile_Full_Access (MACCR); -- Ethernet MAC frame filter register - MACFFR : MACFFR_Register; + MACFFR : aliased MACFFR_Register; + pragma Volatile_Full_Access (MACFFR); -- Ethernet MAC hash table high register - MACHTHR : STM32F429x.Word; + MACHTHR : aliased STM32F429x.UInt32; -- Ethernet MAC hash table low register - MACHTLR : STM32F429x.Word; + MACHTLR : aliased STM32F429x.UInt32; -- Ethernet MAC MII address register - MACMIIAR : MACMIIAR_Register; + MACMIIAR : aliased MACMIIAR_Register; + pragma Volatile_Full_Access (MACMIIAR); -- Ethernet MAC MII data register - MACMIIDR : MACMIIDR_Register; + MACMIIDR : aliased MACMIIDR_Register; + pragma Volatile_Full_Access (MACMIIDR); -- Ethernet MAC flow control register - MACFCR : MACFCR_Register; + MACFCR : aliased MACFCR_Register; + pragma Volatile_Full_Access (MACFCR); -- Ethernet MAC VLAN tag register - MACVLANTR : MACVLANTR_Register; + MACVLANTR : aliased MACVLANTR_Register; + pragma Volatile_Full_Access (MACVLANTR); -- Ethernet MAC PMT control and status register - MACPMTCSR : MACPMTCSR_Register; + MACPMTCSR : aliased MACPMTCSR_Register; + pragma Volatile_Full_Access (MACPMTCSR); -- Ethernet MAC debug register - MACDBGR : MACDBGR_Register; + MACDBGR : aliased MACDBGR_Register; + pragma Volatile_Full_Access (MACDBGR); -- Ethernet MAC interrupt status register - MACSR : MACSR_Register; + MACSR : aliased MACSR_Register; + pragma Volatile_Full_Access (MACSR); -- Ethernet MAC interrupt mask register - MACIMR : MACIMR_Register; + MACIMR : aliased MACIMR_Register; + pragma Volatile_Full_Access (MACIMR); -- Ethernet MAC address 0 high register - MACA0HR : MACA0HR_Register; + MACA0HR : aliased MACA0HR_Register; + pragma Volatile_Full_Access (MACA0HR); -- Ethernet MAC address 0 low register - MACA0LR : STM32F429x.Word; + MACA0LR : aliased STM32F429x.UInt32; -- Ethernet MAC address 1 high register - MACA1HR : MACA1HR_Register; + MACA1HR : aliased MACA1HR_Register; + pragma Volatile_Full_Access (MACA1HR); -- Ethernet MAC address1 low register - MACA1LR : STM32F429x.Word; + MACA1LR : aliased STM32F429x.UInt32; -- Ethernet MAC address 2 high register - MACA2HR : MACA2HR_Register; + MACA2HR : aliased MACA2HR_Register; + pragma Volatile_Full_Access (MACA2HR); -- Ethernet MAC address 2 low register - MACA2LR : MACA2LR_Register; + MACA2LR : aliased MACA2LR_Register; + pragma Volatile_Full_Access (MACA2LR); -- Ethernet MAC address 3 high register - MACA3HR : MACA3HR_Register; + MACA3HR : aliased MACA3HR_Register; + pragma Volatile_Full_Access (MACA3HR); -- Ethernet MAC address 3 low register - MACA3LR : STM32F429x.Word; + MACA3LR : aliased STM32F429x.UInt32; end record with Volatile; for Ethernet_MAC_Peripheral use record - MACCR at 0 range 0 .. 31; - MACFFR at 4 range 0 .. 31; - MACHTHR at 8 range 0 .. 31; - MACHTLR at 12 range 0 .. 31; - MACMIIAR at 16 range 0 .. 31; - MACMIIDR at 20 range 0 .. 31; - MACFCR at 24 range 0 .. 31; - MACVLANTR at 28 range 0 .. 31; - MACPMTCSR at 44 range 0 .. 31; - MACDBGR at 52 range 0 .. 31; - MACSR at 56 range 0 .. 31; - MACIMR at 60 range 0 .. 31; - MACA0HR at 64 range 0 .. 31; - MACA0LR at 68 range 0 .. 31; - MACA1HR at 72 range 0 .. 31; - MACA1LR at 76 range 0 .. 31; - MACA2HR at 80 range 0 .. 31; - MACA2LR at 84 range 0 .. 31; - MACA3HR at 88 range 0 .. 31; - MACA3LR at 92 range 0 .. 31; + MACCR at 16#0# range 0 .. 31; + MACFFR at 16#4# range 0 .. 31; + MACHTHR at 16#8# range 0 .. 31; + MACHTLR at 16#C# range 0 .. 31; + MACMIIAR at 16#10# range 0 .. 31; + MACMIIDR at 16#14# range 0 .. 31; + MACFCR at 16#18# range 0 .. 31; + MACVLANTR at 16#1C# range 0 .. 31; + MACPMTCSR at 16#2C# range 0 .. 31; + MACDBGR at 16#34# range 0 .. 31; + MACSR at 16#38# range 0 .. 31; + MACIMR at 16#3C# range 0 .. 31; + MACA0HR at 16#40# range 0 .. 31; + MACA0LR at 16#44# range 0 .. 31; + MACA1HR at 16#48# range 0 .. 31; + MACA1LR at 16#4C# range 0 .. 31; + MACA2HR at 16#50# range 0 .. 31; + MACA2LR at 16#54# range 0 .. 31; + MACA3HR at 16#58# range 0 .. 31; + MACA3LR at 16#5C# range 0 .. 31; end record; -- Ethernet: media access control (MAC) Ethernet_MAC_Periph : aliased Ethernet_MAC_Peripheral - with Import, Address => System'To_Address (16#40028000#); + with Import, Address => Ethernet_MAC_Base; -- Ethernet: MAC management counters type Ethernet_MMC_Peripheral is record -- Ethernet MMC control register - MMCCR : MMCCR_Register; + MMCCR : aliased MMCCR_Register; + pragma Volatile_Full_Access (MMCCR); -- Ethernet MMC receive interrupt register - MMCRIR : MMCRIR_Register; + MMCRIR : aliased MMCRIR_Register; + pragma Volatile_Full_Access (MMCRIR); -- Ethernet MMC transmit interrupt register - MMCTIR : MMCTIR_Register; + MMCTIR : aliased MMCTIR_Register; + pragma Volatile_Full_Access (MMCTIR); -- Ethernet MMC receive interrupt mask register - MMCRIMR : MMCRIMR_Register; + MMCRIMR : aliased MMCRIMR_Register; + pragma Volatile_Full_Access (MMCRIMR); -- Ethernet MMC transmit interrupt mask register - MMCTIMR : MMCTIMR_Register; + MMCTIMR : aliased MMCTIMR_Register; + pragma Volatile_Full_Access (MMCTIMR); -- Ethernet MMC transmitted good frames after a single collision counter - MMCTGFSCCR : STM32F429x.Word; + MMCTGFSCCR : aliased STM32F429x.UInt32; -- Ethernet MMC transmitted good frames after more than a single -- collision - MMCTGFMSCCR : STM32F429x.Word; + MMCTGFMSCCR : aliased STM32F429x.UInt32; -- Ethernet MMC transmitted good frames counter register - MMCTGFCR : STM32F429x.Word; + MMCTGFCR : aliased STM32F429x.UInt32; -- Ethernet MMC received frames with CRC error counter register - MMCRFCECR : STM32F429x.Word; + MMCRFCECR : aliased STM32F429x.UInt32; -- Ethernet MMC received frames with alignment error counter register - MMCRFAECR : STM32F429x.Word; + MMCRFAECR : aliased STM32F429x.UInt32; -- MMC received good unicast frames counter register - MMCRGUFCR : STM32F429x.Word; + MMCRGUFCR : aliased STM32F429x.UInt32; end record with Volatile; for Ethernet_MMC_Peripheral use record - MMCCR at 0 range 0 .. 31; - MMCRIR at 4 range 0 .. 31; - MMCTIR at 8 range 0 .. 31; - MMCRIMR at 12 range 0 .. 31; - MMCTIMR at 16 range 0 .. 31; - MMCTGFSCCR at 76 range 0 .. 31; - MMCTGFMSCCR at 80 range 0 .. 31; - MMCTGFCR at 104 range 0 .. 31; - MMCRFCECR at 148 range 0 .. 31; - MMCRFAECR at 152 range 0 .. 31; - MMCRGUFCR at 196 range 0 .. 31; + MMCCR at 16#0# range 0 .. 31; + MMCRIR at 16#4# range 0 .. 31; + MMCTIR at 16#8# range 0 .. 31; + MMCRIMR at 16#C# range 0 .. 31; + MMCTIMR at 16#10# range 0 .. 31; + MMCTGFSCCR at 16#4C# range 0 .. 31; + MMCTGFMSCCR at 16#50# range 0 .. 31; + MMCTGFCR at 16#68# range 0 .. 31; + MMCRFCECR at 16#94# range 0 .. 31; + MMCRFAECR at 16#98# range 0 .. 31; + MMCRGUFCR at 16#C4# range 0 .. 31; end record; -- Ethernet: MAC management counters Ethernet_MMC_Periph : aliased Ethernet_MMC_Peripheral - with Import, Address => System'To_Address (16#40028100#); + with Import, Address => Ethernet_MMC_Base; -- Ethernet: Precision time protocol type Ethernet_PTP_Peripheral is record -- Ethernet PTP time stamp control register - PTPTSCR : PTPTSCR_Register; + PTPTSCR : aliased PTPTSCR_Register; + pragma Volatile_Full_Access (PTPTSCR); -- Ethernet PTP subsecond increment register - PTPSSIR : PTPSSIR_Register; + PTPSSIR : aliased PTPSSIR_Register; + pragma Volatile_Full_Access (PTPSSIR); -- Ethernet PTP time stamp high register - PTPTSHR : STM32F429x.Word; + PTPTSHR : aliased STM32F429x.UInt32; -- Ethernet PTP time stamp low register - PTPTSLR : PTPTSLR_Register; + PTPTSLR : aliased PTPTSLR_Register; + pragma Volatile_Full_Access (PTPTSLR); -- Ethernet PTP time stamp high update register - PTPTSHUR : STM32F429x.Word; + PTPTSHUR : aliased STM32F429x.UInt32; -- Ethernet PTP time stamp low update register - PTPTSLUR : PTPTSLUR_Register; + PTPTSLUR : aliased PTPTSLUR_Register; + pragma Volatile_Full_Access (PTPTSLUR); -- Ethernet PTP time stamp addend register - PTPTSAR : STM32F429x.Word; + PTPTSAR : aliased STM32F429x.UInt32; -- Ethernet PTP target time high register - PTPTTHR : STM32F429x.Word; + PTPTTHR : aliased STM32F429x.UInt32; -- Ethernet PTP target time low register - PTPTTLR : STM32F429x.Word; + PTPTTLR : aliased STM32F429x.UInt32; -- Ethernet PTP time stamp status register - PTPTSSR : PTPTSSR_Register; + PTPTSSR : aliased PTPTSSR_Register; + pragma Volatile_Full_Access (PTPTSSR); -- Ethernet PTP PPS control register - PTPPPSCR : PTPPPSCR_Register; + PTPPPSCR : aliased PTPPPSCR_Register; + pragma Volatile_Full_Access (PTPPPSCR); end record with Volatile; for Ethernet_PTP_Peripheral use record - PTPTSCR at 0 range 0 .. 31; - PTPSSIR at 4 range 0 .. 31; - PTPTSHR at 8 range 0 .. 31; - PTPTSLR at 12 range 0 .. 31; - PTPTSHUR at 16 range 0 .. 31; - PTPTSLUR at 20 range 0 .. 31; - PTPTSAR at 24 range 0 .. 31; - PTPTTHR at 28 range 0 .. 31; - PTPTTLR at 32 range 0 .. 31; - PTPTSSR at 40 range 0 .. 31; - PTPPPSCR at 44 range 0 .. 31; + PTPTSCR at 16#0# range 0 .. 31; + PTPSSIR at 16#4# range 0 .. 31; + PTPTSHR at 16#8# range 0 .. 31; + PTPTSLR at 16#C# range 0 .. 31; + PTPTSHUR at 16#10# range 0 .. 31; + PTPTSLUR at 16#14# range 0 .. 31; + PTPTSAR at 16#18# range 0 .. 31; + PTPTTHR at 16#1C# range 0 .. 31; + PTPTTLR at 16#20# range 0 .. 31; + PTPTSSR at 16#28# range 0 .. 31; + PTPPPSCR at 16#2C# range 0 .. 31; end record; -- Ethernet: Precision time protocol Ethernet_PTP_Periph : aliased Ethernet_PTP_Peripheral - with Import, Address => System'To_Address (16#40028700#); - - -- Ethernet: DMA controller operation - type Ethernet_DMA_Peripheral is record - -- Ethernet DMA bus mode register - DMABMR : DMABMR_Register; - -- Ethernet DMA transmit poll demand register - DMATPDR : STM32F429x.Word; - -- EHERNET DMA receive poll demand register - DMARPDR : STM32F429x.Word; - -- Ethernet DMA receive descriptor list address register - DMARDLAR : STM32F429x.Word; - -- Ethernet DMA transmit descriptor list address register - DMATDLAR : STM32F429x.Word; - -- Ethernet DMA status register - DMASR : DMASR_Register; - -- Ethernet DMA operation mode register - DMAOMR : DMAOMR_Register; - -- Ethernet DMA interrupt enable register - DMAIER : DMAIER_Register; - -- Ethernet DMA missed frame and buffer overflow counter register - DMAMFBOCR : DMAMFBOCR_Register; - -- Ethernet DMA receive status watchdog timer register - DMARSWTR : DMARSWTR_Register; - -- Ethernet DMA current host transmit descriptor register - DMACHTDR : STM32F429x.Word; - -- Ethernet DMA current host receive descriptor register - DMACHRDR : STM32F429x.Word; - -- Ethernet DMA current host transmit buffer address register - DMACHTBAR : STM32F429x.Word; - -- Ethernet DMA current host receive buffer address register - DMACHRBAR : STM32F429x.Word; - end record - with Volatile; - - for Ethernet_DMA_Peripheral use record - DMABMR at 0 range 0 .. 31; - DMATPDR at 4 range 0 .. 31; - DMARPDR at 8 range 0 .. 31; - DMARDLAR at 12 range 0 .. 31; - DMATDLAR at 16 range 0 .. 31; - DMASR at 20 range 0 .. 31; - DMAOMR at 24 range 0 .. 31; - DMAIER at 28 range 0 .. 31; - DMAMFBOCR at 32 range 0 .. 31; - DMARSWTR at 36 range 0 .. 31; - DMACHTDR at 72 range 0 .. 31; - DMACHRDR at 76 range 0 .. 31; - DMACHTBAR at 80 range 0 .. 31; - DMACHRBAR at 84 range 0 .. 31; - end record; - - -- Ethernet: DMA controller operation - Ethernet_DMA_Periph : aliased Ethernet_DMA_Peripheral - with Import, Address => System'To_Address (16#40029000#); + with Import, Address => Ethernet_PTP_Base; end STM32F429x.Ethernet; diff --git a/stm32f429i/stm32f429x/stm32f429x-exti.ads b/stm32f429i/stm32f429x/stm32f429x-exti.ads index ba830dd..d450395 100644 --- a/stm32f429i/stm32f429x/stm32f429x-exti.ads +++ b/stm32f429i/stm32f429x/stm32f429x-exti.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,14 +14,6 @@ package STM32F429x.EXTI is -- Registers -- --------------- - ------------------ - -- IMR_Register -- - ------------------ - - ------------ - -- IMR.MR -- - ------------ - -- IMR_MR array element subtype IMR_MR_Element is STM32F429x.Bit; @@ -54,21 +48,13 @@ package STM32F429x.EXTI is -- unspecified Reserved_23_31 : STM32F429x.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IMR_Register use record MR at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------ - -- EMR_Register -- - ------------------ - - ------------ - -- EMR.MR -- - ------------ - -- EMR_MR array element subtype EMR_MR_Element is STM32F429x.Bit; @@ -103,21 +89,13 @@ package STM32F429x.EXTI is -- unspecified Reserved_23_31 : STM32F429x.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for EMR_Register use record MR at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- RTSR_Register -- - ------------------- - - ------------- - -- RTSR.TR -- - ------------- - -- RTSR_TR array element subtype RTSR_TR_Element is STM32F429x.Bit; @@ -152,21 +130,13 @@ package STM32F429x.EXTI is -- unspecified Reserved_23_31 : STM32F429x.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RTSR_Register use record TR at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- FTSR_Register -- - ------------------- - - ------------- - -- FTSR.TR -- - ------------- - -- FTSR_TR array element subtype FTSR_TR_Element is STM32F429x.Bit; @@ -201,21 +171,13 @@ package STM32F429x.EXTI is -- unspecified Reserved_23_31 : STM32F429x.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FTSR_Register use record TR at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - -------------------- - -- SWIER_Register -- - -------------------- - - ----------------- - -- SWIER.SWIER -- - ----------------- - -- SWIER array element subtype SWIER_Element is STM32F429x.Bit; @@ -250,21 +212,13 @@ package STM32F429x.EXTI is -- unspecified Reserved_23_31 : STM32F429x.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SWIER_Register use record SWIER at 0 range 0 .. 22; Reserved_23_31 at 0 range 23 .. 31; end record; - ----------------- - -- PR_Register -- - ----------------- - - ----------- - -- PR.PR -- - ----------- - -- PR array element subtype PR_Element is STM32F429x.Bit; @@ -299,7 +253,7 @@ package STM32F429x.EXTI is -- unspecified Reserved_23_31 : STM32F429x.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PR_Register use record PR at 0 range 0 .. 22; @@ -313,31 +267,37 @@ package STM32F429x.EXTI is -- External interrupt/event controller type EXTI_Peripheral is record -- Interrupt mask register (EXTI_IMR) - IMR : IMR_Register; + IMR : aliased IMR_Register; + pragma Volatile_Full_Access (IMR); -- Event mask register (EXTI_EMR) - EMR : EMR_Register; + EMR : aliased EMR_Register; + pragma Volatile_Full_Access (EMR); -- Rising Trigger selection register (EXTI_RTSR) - RTSR : RTSR_Register; + RTSR : aliased RTSR_Register; + pragma Volatile_Full_Access (RTSR); -- Falling Trigger selection register (EXTI_FTSR) - FTSR : FTSR_Register; + FTSR : aliased FTSR_Register; + pragma Volatile_Full_Access (FTSR); -- Software interrupt event register (EXTI_SWIER) - SWIER : SWIER_Register; + SWIER : aliased SWIER_Register; + pragma Volatile_Full_Access (SWIER); -- Pending register (EXTI_PR) - PR : PR_Register; + PR : aliased PR_Register; + pragma Volatile_Full_Access (PR); end record with Volatile; for EXTI_Peripheral use record - IMR at 0 range 0 .. 31; - EMR at 4 range 0 .. 31; - RTSR at 8 range 0 .. 31; - FTSR at 12 range 0 .. 31; - SWIER at 16 range 0 .. 31; - PR at 20 range 0 .. 31; + IMR at 16#0# range 0 .. 31; + EMR at 16#4# range 0 .. 31; + RTSR at 16#8# range 0 .. 31; + FTSR at 16#C# range 0 .. 31; + SWIER at 16#10# range 0 .. 31; + PR at 16#14# range 0 .. 31; end record; -- External interrupt/event controller EXTI_Periph : aliased EXTI_Peripheral - with Import, Address => System'To_Address (16#40013C00#); + with Import, Address => EXTI_Base; end STM32F429x.EXTI; diff --git a/stm32f429i/stm32f429x/stm32f429x-flash.ads b/stm32f429i/stm32f429x/stm32f429x-flash.ads index cbc42b1..b74cd93 100644 --- a/stm32f429i/stm32f429x/stm32f429x-flash.ads +++ b/stm32f429i/stm32f429x/stm32f429x-flash.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.FLASH is -- Registers -- --------------- - ------------------ - -- ACR_Register -- - ------------------ - subtype ACR_LATENCY_Field is STM32F429x.UInt3; subtype ACR_PRFTEN_Field is STM32F429x.Bit; subtype ACR_ICEN_Field is STM32F429x.Bit; @@ -35,14 +33,14 @@ package STM32F429x.FLASH is ICEN : ACR_ICEN_Field := 16#0#; -- Data cache enable DCEN : ACR_DCEN_Field := 16#0#; - -- Instruction cache reset + -- Write-only. Instruction cache reset ICRST : ACR_ICRST_Field := 16#0#; -- Data cache reset DCRST : ACR_DCRST_Field := 16#0#; -- unspecified Reserved_13_31 : STM32F429x.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ACR_Register use record LATENCY at 0 range 0 .. 2; @@ -55,10 +53,6 @@ package STM32F429x.FLASH is Reserved_13_31 at 0 range 13 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_EOP_Field is STM32F429x.Bit; subtype SR_OPERR_Field is STM32F429x.Bit; subtype SR_WRPERR_Field is STM32F429x.Bit; @@ -85,12 +79,12 @@ package STM32F429x.FLASH is PGSERR : SR_PGSERR_Field := 16#0#; -- unspecified Reserved_8_15 : STM32F429x.Byte := 16#0#; - -- Busy + -- Read-only. Busy BSY : SR_BSY_Field := 16#0#; -- unspecified Reserved_17_31 : STM32F429x.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record EOP at 0 range 0 .. 0; @@ -105,10 +99,6 @@ package STM32F429x.FLASH is Reserved_17_31 at 0 range 17 .. 31; end record; - ----------------- - -- CR_Register -- - ----------------- - subtype CR_PG_Field is STM32F429x.Bit; subtype CR_SER_Field is STM32F429x.Bit; subtype CR_MER_Field is STM32F429x.Bit; @@ -149,7 +139,7 @@ package STM32F429x.FLASH is -- Lock LOCK : CR_LOCK_Field := 16#1#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record PG at 0 range 0 .. 0; @@ -167,10 +157,6 @@ package STM32F429x.FLASH is LOCK at 0 range 31 .. 31; end record; - -------------------- - -- OPTCR_Register -- - -------------------- - subtype OPTCR_OPTLOCK_Field is STM32F429x.Bit; subtype OPTCR_OPTSTRT_Field is STM32F429x.Bit; subtype OPTCR_BOR_LEV_Field is STM32F429x.UInt2; @@ -203,7 +189,7 @@ package STM32F429x.FLASH is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OPTCR_Register use record OPTLOCK at 0 range 0 .. 0; @@ -218,22 +204,18 @@ package STM32F429x.FLASH is Reserved_28_31 at 0 range 28 .. 31; end record; - --------------------- - -- OPTCR1_Register -- - --------------------- - subtype OPTCR1_nWRP_Field is STM32F429x.UInt12; -- Flash option control register 1 type OPTCR1_Register is record -- unspecified - Reserved_0_15 : STM32F429x.Short := 16#0#; + Reserved_0_15 : STM32F429x.UInt16 := 16#0#; -- Not write protect nWRP : OPTCR1_nWRP_Field := 16#FFF#; -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OPTCR1_Register use record Reserved_0_15 at 0 range 0 .. 15; @@ -248,34 +230,39 @@ package STM32F429x.FLASH is -- FLASH type FLASH_Peripheral is record -- Flash access control register - ACR : ACR_Register; + ACR : aliased ACR_Register; + pragma Volatile_Full_Access (ACR); -- Flash key register - KEYR : STM32F429x.Word; + KEYR : aliased STM32F429x.UInt32; -- Flash option key register - OPTKEYR : STM32F429x.Word; + OPTKEYR : aliased STM32F429x.UInt32; -- Status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- Control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- Flash option control register - OPTCR : OPTCR_Register; + OPTCR : aliased OPTCR_Register; + pragma Volatile_Full_Access (OPTCR); -- Flash option control register 1 - OPTCR1 : OPTCR1_Register; + OPTCR1 : aliased OPTCR1_Register; + pragma Volatile_Full_Access (OPTCR1); end record with Volatile; for FLASH_Peripheral use record - ACR at 0 range 0 .. 31; - KEYR at 4 range 0 .. 31; - OPTKEYR at 8 range 0 .. 31; - SR at 12 range 0 .. 31; - CR at 16 range 0 .. 31; - OPTCR at 20 range 0 .. 31; - OPTCR1 at 24 range 0 .. 31; + ACR at 16#0# range 0 .. 31; + KEYR at 16#4# range 0 .. 31; + OPTKEYR at 16#8# range 0 .. 31; + SR at 16#C# range 0 .. 31; + CR at 16#10# range 0 .. 31; + OPTCR at 16#14# range 0 .. 31; + OPTCR1 at 16#18# range 0 .. 31; end record; -- FLASH FLASH_Periph : aliased FLASH_Peripheral - with Import, Address => System'To_Address (16#40023C00#); + with Import, Address => FLASH_Base; end STM32F429x.FLASH; diff --git a/stm32f429i/stm32f429x/stm32f429x-fsmc.ads b/stm32f429i/stm32f429x/stm32f429x-fsmc.ads index 3d1798c..d281e90 100644 --- a/stm32f429i/stm32f429x/stm32f429x-fsmc.ads +++ b/stm32f429i/stm32f429x/stm32f429x-fsmc.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.FSMC is -- Registers -- --------------- - ------------------- - -- BCR1_Register -- - ------------------- - subtype BCR1_MBKEN_Field is STM32F429x.Bit; subtype BCR1_MUXEN_Field is STM32F429x.Bit; subtype BCR1_MTYP_Field is STM32F429x.UInt2; @@ -70,7 +68,7 @@ package STM32F429x.FSMC is -- unspecified Reserved_21_31 : STM32F429x.UInt11 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BCR1_Register use record MBKEN at 0 range 0 .. 0; @@ -93,38 +91,34 @@ package STM32F429x.FSMC is Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------ - -- BTR_Register -- - ------------------ - - subtype BTR1_ADDSET_Field is STM32F429x.UInt4; - subtype BTR1_ADDHLD_Field is STM32F429x.UInt4; - subtype BTR1_DATAST_Field is STM32F429x.Byte; - subtype BTR1_BUSTURN_Field is STM32F429x.UInt4; - subtype BTR1_CLKDIV_Field is STM32F429x.UInt4; - subtype BTR1_DATLAT_Field is STM32F429x.UInt4; - subtype BTR1_ACCMOD_Field is STM32F429x.UInt2; + subtype BTR_ADDSET_Field is STM32F429x.UInt4; + subtype BTR_ADDHLD_Field is STM32F429x.UInt4; + subtype BTR_DATAST_Field is STM32F429x.Byte; + subtype BTR_BUSTURN_Field is STM32F429x.UInt4; + subtype BTR_CLKDIV_Field is STM32F429x.UInt4; + subtype BTR_DATLAT_Field is STM32F429x.UInt4; + subtype BTR_ACCMOD_Field is STM32F429x.UInt2; -- SRAM/NOR-Flash chip-select timing register 1 type BTR_Register is record -- ADDSET - ADDSET : BTR1_ADDSET_Field := 16#F#; + ADDSET : BTR_ADDSET_Field := 16#F#; -- ADDHLD - ADDHLD : BTR1_ADDHLD_Field := 16#F#; + ADDHLD : BTR_ADDHLD_Field := 16#F#; -- DATAST - DATAST : BTR1_DATAST_Field := 16#FF#; + DATAST : BTR_DATAST_Field := 16#FF#; -- BUSTURN - BUSTURN : BTR1_BUSTURN_Field := 16#F#; + BUSTURN : BTR_BUSTURN_Field := 16#F#; -- CLKDIV - CLKDIV : BTR1_CLKDIV_Field := 16#F#; + CLKDIV : BTR_CLKDIV_Field := 16#F#; -- DATLAT - DATLAT : BTR1_DATLAT_Field := 16#F#; + DATLAT : BTR_DATLAT_Field := 16#F#; -- ACCMOD - ACCMOD : BTR1_ACCMOD_Field := 16#3#; + ACCMOD : BTR_ACCMOD_Field := 16#3#; -- unspecified Reserved_30_31 : STM32F429x.UInt2 := 16#3#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BTR_Register use record ADDSET at 0 range 0 .. 3; @@ -137,63 +131,59 @@ package STM32F429x.FSMC is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------ - -- BCR_Register -- - ------------------ - - subtype BCR2_MBKEN_Field is STM32F429x.Bit; - subtype BCR2_MUXEN_Field is STM32F429x.Bit; - subtype BCR2_MTYP_Field is STM32F429x.UInt2; - subtype BCR2_MWID_Field is STM32F429x.UInt2; - subtype BCR2_FACCEN_Field is STM32F429x.Bit; - subtype BCR2_BURSTEN_Field is STM32F429x.Bit; - subtype BCR2_WAITPOL_Field is STM32F429x.Bit; - subtype BCR2_WRAPMOD_Field is STM32F429x.Bit; - subtype BCR2_WAITCFG_Field is STM32F429x.Bit; - subtype BCR2_WREN_Field is STM32F429x.Bit; - subtype BCR2_WAITEN_Field is STM32F429x.Bit; - subtype BCR2_EXTMOD_Field is STM32F429x.Bit; - subtype BCR2_ASYNCWAIT_Field is STM32F429x.Bit; - subtype BCR2_CBURSTRW_Field is STM32F429x.Bit; + subtype BCR_MBKEN_Field is STM32F429x.Bit; + subtype BCR_MUXEN_Field is STM32F429x.Bit; + subtype BCR_MTYP_Field is STM32F429x.UInt2; + subtype BCR_MWID_Field is STM32F429x.UInt2; + subtype BCR_FACCEN_Field is STM32F429x.Bit; + subtype BCR_BURSTEN_Field is STM32F429x.Bit; + subtype BCR_WAITPOL_Field is STM32F429x.Bit; + subtype BCR_WRAPMOD_Field is STM32F429x.Bit; + subtype BCR_WAITCFG_Field is STM32F429x.Bit; + subtype BCR_WREN_Field is STM32F429x.Bit; + subtype BCR_WAITEN_Field is STM32F429x.Bit; + subtype BCR_EXTMOD_Field is STM32F429x.Bit; + subtype BCR_ASYNCWAIT_Field is STM32F429x.Bit; + subtype BCR_CBURSTRW_Field is STM32F429x.Bit; -- SRAM/NOR-Flash chip-select control register 2 type BCR_Register is record -- MBKEN - MBKEN : BCR2_MBKEN_Field := 16#0#; + MBKEN : BCR_MBKEN_Field := 16#0#; -- MUXEN - MUXEN : BCR2_MUXEN_Field := 16#0#; + MUXEN : BCR_MUXEN_Field := 16#0#; -- MTYP - MTYP : BCR2_MTYP_Field := 16#0#; + MTYP : BCR_MTYP_Field := 16#0#; -- MWID - MWID : BCR2_MWID_Field := 16#1#; + MWID : BCR_MWID_Field := 16#1#; -- FACCEN - FACCEN : BCR2_FACCEN_Field := 16#1#; + FACCEN : BCR_FACCEN_Field := 16#1#; -- unspecified Reserved_7_7 : STM32F429x.Bit := 16#1#; -- BURSTEN - BURSTEN : BCR2_BURSTEN_Field := 16#0#; + BURSTEN : BCR_BURSTEN_Field := 16#0#; -- WAITPOL - WAITPOL : BCR2_WAITPOL_Field := 16#0#; + WAITPOL : BCR_WAITPOL_Field := 16#0#; -- WRAPMOD - WRAPMOD : BCR2_WRAPMOD_Field := 16#0#; + WRAPMOD : BCR_WRAPMOD_Field := 16#0#; -- WAITCFG - WAITCFG : BCR2_WAITCFG_Field := 16#0#; + WAITCFG : BCR_WAITCFG_Field := 16#0#; -- WREN - WREN : BCR2_WREN_Field := 16#1#; + WREN : BCR_WREN_Field := 16#1#; -- WAITEN - WAITEN : BCR2_WAITEN_Field := 16#1#; + WAITEN : BCR_WAITEN_Field := 16#1#; -- EXTMOD - EXTMOD : BCR2_EXTMOD_Field := 16#0#; + EXTMOD : BCR_EXTMOD_Field := 16#0#; -- ASYNCWAIT - ASYNCWAIT : BCR2_ASYNCWAIT_Field := 16#0#; + ASYNCWAIT : BCR_ASYNCWAIT_Field := 16#0#; -- unspecified Reserved_16_18 : STM32F429x.UInt3 := 16#0#; -- CBURSTRW - CBURSTRW : BCR2_CBURSTRW_Field := 16#0#; + CBURSTRW : BCR_CBURSTRW_Field := 16#0#; -- unspecified Reserved_20_31 : STM32F429x.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BCR_Register use record MBKEN at 0 range 0 .. 0; @@ -215,45 +205,41 @@ package STM32F429x.FSMC is Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------ - -- PCR_Register -- - ------------------ - - subtype PCR2_PWAITEN_Field is STM32F429x.Bit; - subtype PCR2_PBKEN_Field is STM32F429x.Bit; - subtype PCR2_PTYP_Field is STM32F429x.Bit; - subtype PCR2_PWID_Field is STM32F429x.UInt2; - subtype PCR2_ECCEN_Field is STM32F429x.Bit; - subtype PCR2_TCLR_Field is STM32F429x.UInt4; - subtype PCR2_TAR_Field is STM32F429x.UInt4; - subtype PCR2_ECCPS_Field is STM32F429x.UInt3; + subtype PCR_PWAITEN_Field is STM32F429x.Bit; + subtype PCR_PBKEN_Field is STM32F429x.Bit; + subtype PCR_PTYP_Field is STM32F429x.Bit; + subtype PCR_PWID_Field is STM32F429x.UInt2; + subtype PCR_ECCEN_Field is STM32F429x.Bit; + subtype PCR_TCLR_Field is STM32F429x.UInt4; + subtype PCR_TAR_Field is STM32F429x.UInt4; + subtype PCR_ECCPS_Field is STM32F429x.UInt3; -- PC Card/NAND Flash control register 2 type PCR_Register is record -- unspecified Reserved_0_0 : STM32F429x.Bit := 16#0#; -- PWAITEN - PWAITEN : PCR2_PWAITEN_Field := 16#0#; + PWAITEN : PCR_PWAITEN_Field := 16#0#; -- PBKEN - PBKEN : PCR2_PBKEN_Field := 16#0#; + PBKEN : PCR_PBKEN_Field := 16#0#; -- PTYP - PTYP : PCR2_PTYP_Field := 16#1#; + PTYP : PCR_PTYP_Field := 16#1#; -- PWID - PWID : PCR2_PWID_Field := 16#1#; + PWID : PCR_PWID_Field := 16#1#; -- ECCEN - ECCEN : PCR2_ECCEN_Field := 16#0#; + ECCEN : PCR_ECCEN_Field := 16#0#; -- unspecified Reserved_7_8 : STM32F429x.UInt2 := 16#0#; -- TCLR - TCLR : PCR2_TCLR_Field := 16#0#; + TCLR : PCR_TCLR_Field := 16#0#; -- TAR - TAR : PCR2_TAR_Field := 16#0#; + TAR : PCR_TAR_Field := 16#0#; -- ECCPS - ECCPS : PCR2_ECCPS_Field := 16#0#; + ECCPS : PCR_ECCPS_Field := 16#0#; -- unspecified Reserved_20_31 : STM32F429x.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PCR_Register use record Reserved_0_0 at 0 range 0 .. 0; @@ -269,38 +255,34 @@ package STM32F429x.FSMC is Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - - subtype SR2_IRS_Field is STM32F429x.Bit; - subtype SR2_ILS_Field is STM32F429x.Bit; - subtype SR2_IFS_Field is STM32F429x.Bit; - subtype SR2_IREN_Field is STM32F429x.Bit; - subtype SR2_ILEN_Field is STM32F429x.Bit; - subtype SR2_IFEN_Field is STM32F429x.Bit; - subtype SR2_FEMPT_Field is STM32F429x.Bit; + subtype SR_IRS_Field is STM32F429x.Bit; + subtype SR_ILS_Field is STM32F429x.Bit; + subtype SR_IFS_Field is STM32F429x.Bit; + subtype SR_IREN_Field is STM32F429x.Bit; + subtype SR_ILEN_Field is STM32F429x.Bit; + subtype SR_IFEN_Field is STM32F429x.Bit; + subtype SR_FEMPT_Field is STM32F429x.Bit; -- FIFO status and interrupt register 2 type SR_Register is record -- IRS - IRS : SR2_IRS_Field := 16#0#; + IRS : SR_IRS_Field := 16#0#; -- ILS - ILS : SR2_ILS_Field := 16#0#; + ILS : SR_ILS_Field := 16#0#; -- IFS - IFS : SR2_IFS_Field := 16#0#; + IFS : SR_IFS_Field := 16#0#; -- IREN - IREN : SR2_IREN_Field := 16#0#; + IREN : SR_IREN_Field := 16#0#; -- ILEN - ILEN : SR2_ILEN_Field := 16#0#; + ILEN : SR_ILEN_Field := 16#0#; -- IFEN - IFEN : SR2_IFEN_Field := 16#0#; - -- FEMPT - FEMPT : SR2_FEMPT_Field := 16#1#; + IFEN : SR_IFEN_Field := 16#0#; + -- Read-only. FEMPT + FEMPT : SR_FEMPT_Field := 16#1#; -- unspecified Reserved_7_31 : STM32F429x.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record IRS at 0 range 0 .. 0; @@ -313,27 +295,23 @@ package STM32F429x.FSMC is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------- - -- PMEM_Register -- - ------------------- - - subtype PMEM2_MEMSETx_Field is STM32F429x.Byte; - subtype PMEM2_MEMWAITx_Field is STM32F429x.Byte; - subtype PMEM2_MEMHOLDx_Field is STM32F429x.Byte; - subtype PMEM2_MEMHIZx_Field is STM32F429x.Byte; + subtype PMEM_MEMSETx_Field is STM32F429x.Byte; + subtype PMEM_MEMWAITx_Field is STM32F429x.Byte; + subtype PMEM_MEMHOLDx_Field is STM32F429x.Byte; + subtype PMEM_MEMHIZx_Field is STM32F429x.Byte; -- Common memory space timing register 2 type PMEM_Register is record -- MEMSETx - MEMSETx : PMEM2_MEMSETx_Field := 16#FC#; + MEMSETx : PMEM_MEMSETx_Field := 16#FC#; -- MEMWAITx - MEMWAITx : PMEM2_MEMWAITx_Field := 16#FC#; + MEMWAITx : PMEM_MEMWAITx_Field := 16#FC#; -- MEMHOLDx - MEMHOLDx : PMEM2_MEMHOLDx_Field := 16#FC#; + MEMHOLDx : PMEM_MEMHOLDx_Field := 16#FC#; -- MEMHIZx - MEMHIZx : PMEM2_MEMHIZx_Field := 16#FC#; + MEMHIZx : PMEM_MEMHIZx_Field := 16#FC#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMEM_Register use record MEMSETx at 0 range 0 .. 7; @@ -342,27 +320,23 @@ package STM32F429x.FSMC is MEMHIZx at 0 range 24 .. 31; end record; - ------------------- - -- PATT_Register -- - ------------------- - - subtype PATT2_ATTSETx_Field is STM32F429x.Byte; - subtype PATT2_ATTWAITx_Field is STM32F429x.Byte; - subtype PATT2_ATTHOLDx_Field is STM32F429x.Byte; - subtype PATT2_ATTHIZx_Field is STM32F429x.Byte; + subtype PATT_ATTSETx_Field is STM32F429x.Byte; + subtype PATT_ATTWAITx_Field is STM32F429x.Byte; + subtype PATT_ATTHOLDx_Field is STM32F429x.Byte; + subtype PATT_ATTHIZx_Field is STM32F429x.Byte; -- Attribute memory space timing register 2 type PATT_Register is record -- ATTSETx - ATTSETx : PATT2_ATTSETx_Field := 16#FC#; + ATTSETx : PATT_ATTSETx_Field := 16#FC#; -- ATTWAITx - ATTWAITx : PATT2_ATTWAITx_Field := 16#FC#; + ATTWAITx : PATT_ATTWAITx_Field := 16#FC#; -- ATTHOLDx - ATTHOLDx : PATT2_ATTHOLDx_Field := 16#FC#; + ATTHOLDx : PATT_ATTHOLDx_Field := 16#FC#; -- ATTHIZx - ATTHIZx : PATT2_ATTHIZx_Field := 16#FC#; + ATTHIZx : PATT_ATTHIZx_Field := 16#FC#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PATT_Register use record ATTSETx at 0 range 0 .. 7; @@ -371,10 +345,6 @@ package STM32F429x.FSMC is ATTHIZx at 0 range 24 .. 31; end record; - ------------------- - -- PIO4_Register -- - ------------------- - subtype PIO4_IOSETx_Field is STM32F429x.Byte; subtype PIO4_IOWAITx_Field is STM32F429x.Byte; subtype PIO4_IOHOLDx_Field is STM32F429x.Byte; @@ -391,7 +361,7 @@ package STM32F429x.FSMC is -- IOHIZx IOHIZx : PIO4_IOHIZx_Field := 16#FC#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PIO4_Register use record IOSETx at 0 range 0 .. 7; @@ -400,37 +370,33 @@ package STM32F429x.FSMC is IOHIZx at 0 range 24 .. 31; end record; - ------------------- - -- BWTR_Register -- - ------------------- - - subtype BWTR1_ADDSET_Field is STM32F429x.UInt4; - subtype BWTR1_ADDHLD_Field is STM32F429x.UInt4; - subtype BWTR1_DATAST_Field is STM32F429x.Byte; - subtype BWTR1_CLKDIV_Field is STM32F429x.UInt4; - subtype BWTR1_DATLAT_Field is STM32F429x.UInt4; - subtype BWTR1_ACCMOD_Field is STM32F429x.UInt2; + subtype BWTR_ADDSET_Field is STM32F429x.UInt4; + subtype BWTR_ADDHLD_Field is STM32F429x.UInt4; + subtype BWTR_DATAST_Field is STM32F429x.Byte; + subtype BWTR_CLKDIV_Field is STM32F429x.UInt4; + subtype BWTR_DATLAT_Field is STM32F429x.UInt4; + subtype BWTR_ACCMOD_Field is STM32F429x.UInt2; -- SRAM/NOR-Flash write timing registers 1 type BWTR_Register is record -- ADDSET - ADDSET : BWTR1_ADDSET_Field := 16#F#; + ADDSET : BWTR_ADDSET_Field := 16#F#; -- ADDHLD - ADDHLD : BWTR1_ADDHLD_Field := 16#F#; + ADDHLD : BWTR_ADDHLD_Field := 16#F#; -- DATAST - DATAST : BWTR1_DATAST_Field := 16#FF#; + DATAST : BWTR_DATAST_Field := 16#FF#; -- unspecified Reserved_16_19 : STM32F429x.UInt4 := 16#F#; -- CLKDIV - CLKDIV : BWTR1_CLKDIV_Field := 16#F#; + CLKDIV : BWTR_CLKDIV_Field := 16#F#; -- DATLAT - DATLAT : BWTR1_DATLAT_Field := 16#F#; + DATLAT : BWTR_DATLAT_Field := 16#F#; -- ACCMOD - ACCMOD : BWTR1_ACCMOD_Field := 16#0#; + ACCMOD : BWTR_ACCMOD_Field := 16#0#; -- unspecified Reserved_30_31 : STM32F429x.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BWTR_Register use record ADDSET at 0 range 0 .. 3; @@ -443,44 +409,40 @@ package STM32F429x.FSMC is Reserved_30_31 at 0 range 30 .. 31; end record; - ------------------- - -- SDCR_Register -- - ------------------- - - subtype SDCR1_NC_Field is STM32F429x.UInt2; - subtype SDCR1_NR_Field is STM32F429x.UInt2; - subtype SDCR1_MWID_Field is STM32F429x.UInt2; - subtype SDCR1_NB_Field is STM32F429x.Bit; - subtype SDCR1_CAS_Field is STM32F429x.UInt2; - subtype SDCR1_WP_Field is STM32F429x.Bit; - subtype SDCR1_SDCLK_Field is STM32F429x.UInt2; - subtype SDCR1_RBURST_Field is STM32F429x.Bit; - subtype SDCR1_RPIPE_Field is STM32F429x.UInt2; + subtype SDCR_NC_Field is STM32F429x.UInt2; + subtype SDCR_NR_Field is STM32F429x.UInt2; + subtype SDCR_MWID_Field is STM32F429x.UInt2; + subtype SDCR_NB_Field is STM32F429x.Bit; + subtype SDCR_CAS_Field is STM32F429x.UInt2; + subtype SDCR_WP_Field is STM32F429x.Bit; + subtype SDCR_SDCLK_Field is STM32F429x.UInt2; + subtype SDCR_RBURST_Field is STM32F429x.Bit; + subtype SDCR_RPIPE_Field is STM32F429x.UInt2; -- SDRAM Control Register 1 type SDCR_Register is record -- Number of column address bits - NC : SDCR1_NC_Field := 16#0#; + NC : SDCR_NC_Field := 16#0#; -- Number of row address bits - NR : SDCR1_NR_Field := 16#0#; + NR : SDCR_NR_Field := 16#0#; -- Memory data bus width - MWID : SDCR1_MWID_Field := 16#1#; + MWID : SDCR_MWID_Field := 16#1#; -- Number of internal banks - NB : SDCR1_NB_Field := 16#1#; + NB : SDCR_NB_Field := 16#1#; -- CAS latency - CAS : SDCR1_CAS_Field := 16#1#; + CAS : SDCR_CAS_Field := 16#1#; -- Write protection - WP : SDCR1_WP_Field := 16#1#; + WP : SDCR_WP_Field := 16#1#; -- SDRAM clock configuration - SDCLK : SDCR1_SDCLK_Field := 16#0#; + SDCLK : SDCR_SDCLK_Field := 16#0#; -- Burst read - RBURST : SDCR1_RBURST_Field := 16#0#; + RBURST : SDCR_RBURST_Field := 16#0#; -- Read pipe - RPIPE : SDCR1_RPIPE_Field := 16#0#; + RPIPE : SDCR_RPIPE_Field := 16#0#; -- unspecified Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SDCR_Register use record NC at 0 range 0 .. 1; @@ -495,38 +457,34 @@ package STM32F429x.FSMC is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------- - -- SDTR_Register -- - ------------------- - - subtype SDTR1_TMRD_Field is STM32F429x.UInt4; - subtype SDTR1_TXSR_Field is STM32F429x.UInt4; - subtype SDTR1_TRAS_Field is STM32F429x.UInt4; - subtype SDTR1_TRC_Field is STM32F429x.UInt4; - subtype SDTR1_TWR_Field is STM32F429x.UInt4; - subtype SDTR1_TRP_Field is STM32F429x.UInt4; - subtype SDTR1_TRCD_Field is STM32F429x.UInt4; + subtype SDTR_TMRD_Field is STM32F429x.UInt4; + subtype SDTR_TXSR_Field is STM32F429x.UInt4; + subtype SDTR_TRAS_Field is STM32F429x.UInt4; + subtype SDTR_TRC_Field is STM32F429x.UInt4; + subtype SDTR_TWR_Field is STM32F429x.UInt4; + subtype SDTR_TRP_Field is STM32F429x.UInt4; + subtype SDTR_TRCD_Field is STM32F429x.UInt4; -- SDRAM Timing register 1 type SDTR_Register is record -- Load Mode Register to Active - TMRD : SDTR1_TMRD_Field := 16#F#; + TMRD : SDTR_TMRD_Field := 16#F#; -- Exit self-refresh delay - TXSR : SDTR1_TXSR_Field := 16#F#; + TXSR : SDTR_TXSR_Field := 16#F#; -- Self refresh time - TRAS : SDTR1_TRAS_Field := 16#F#; + TRAS : SDTR_TRAS_Field := 16#F#; -- Row cycle delay - TRC : SDTR1_TRC_Field := 16#F#; + TRC : SDTR_TRC_Field := 16#F#; -- Recovery delay - TWR : SDTR1_TWR_Field := 16#F#; + TWR : SDTR_TWR_Field := 16#F#; -- Row precharge delay - TRP : SDTR1_TRP_Field := 16#F#; + TRP : SDTR_TRP_Field := 16#F#; -- Row to column delay - TRCD : SDTR1_TRCD_Field := 16#F#; + TRCD : SDTR_TRCD_Field := 16#F#; -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SDTR_Register use record TMRD at 0 range 0 .. 3; @@ -539,52 +497,20 @@ package STM32F429x.FSMC is Reserved_28_31 at 0 range 28 .. 31; end record; - -------------------- - -- SDCMR_Register -- - -------------------- - subtype SDCMR_MODE_Field is STM32F429x.UInt3; - - --------------- - -- SDCMR.CTB -- - --------------- - - -- SDCMR_CTB array element - subtype SDCMR_CTB_Element is STM32F429x.Bit; - - -- SDCMR_CTB array - type SDCMR_CTB_Field_Array is array (0 .. 1) of SDCMR_CTB_Element - with Component_Size => 1, Size => 2; - - -- Type definition for SDCMR_CTB - type SDCMR_CTB_Field - (As_Array : Boolean := False) - is record - case As_Array is - when False => - -- CTB as a value - Val : STM32F429x.UInt2; - when True => - -- CTB as an array - Arr : SDCMR_CTB_Field_Array; - end case; - end record - with Unchecked_Union, Size => 2; - - for SDCMR_CTB_Field use record - Val at 0 range 0 .. 1; - Arr at 0 range 0 .. 1; - end record; - + subtype SDCMR_CTB2_Field is STM32F429x.Bit; + subtype SDCMR_CTB1_Field is STM32F429x.Bit; subtype SDCMR_NRFS_Field is STM32F429x.UInt4; subtype SDCMR_MRD_Field is STM32F429x.UInt13; -- SDRAM Command Mode register type SDCMR_Register is record - -- Command mode + -- Write-only. Command mode MODE : SDCMR_MODE_Field := 16#0#; - -- Command target bank 2 - CTB : SDCMR_CTB_Field := (As_Array => False, Val => 16#0#); + -- Write-only. Command target bank 2 + CTB2 : SDCMR_CTB2_Field := 16#0#; + -- Write-only. Command target bank 1 + CTB1 : SDCMR_CTB1_Field := 16#0#; -- Number of Auto-refresh NRFS : SDCMR_NRFS_Field := 16#0#; -- Mode Register definition @@ -592,27 +518,24 @@ package STM32F429x.FSMC is -- unspecified Reserved_22_31 : STM32F429x.UInt10 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SDCMR_Register use record MODE at 0 range 0 .. 2; - CTB at 0 range 3 .. 4; + CTB2 at 0 range 3 .. 3; + CTB1 at 0 range 4 .. 4; NRFS at 0 range 5 .. 8; MRD at 0 range 9 .. 21; Reserved_22_31 at 0 range 22 .. 31; end record; - -------------------- - -- SDRTR_Register -- - -------------------- - subtype SDRTR_CRE_Field is STM32F429x.Bit; subtype SDRTR_COUNT_Field is STM32F429x.UInt13; subtype SDRTR_REIE_Field is STM32F429x.Bit; -- SDRAM Refresh Timer register type SDRTR_Register is record - -- Clear Refresh error flag + -- Write-only. Clear Refresh error flag CRE : SDRTR_CRE_Field := 16#0#; -- Refresh Timer Count COUNT : SDRTR_COUNT_Field := 16#0#; @@ -621,7 +544,7 @@ package STM32F429x.FSMC is -- unspecified Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SDRTR_Register use record CRE at 0 range 0 .. 0; @@ -630,21 +553,12 @@ package STM32F429x.FSMC is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------- - -- SDSR_Register -- - ------------------- - subtype SDSR_RE_Field is STM32F429x.Bit; - - ---------------- - -- SDSR.MODES -- - ---------------- - -- SDSR_MODES array element subtype SDSR_MODES_Element is STM32F429x.UInt2; -- SDSR_MODES array - type SDSR_MODES_Field_Array is array (0 .. 1) of SDSR_MODES_Element + type SDSR_MODES_Field_Array is array (1 .. 2) of SDSR_MODES_Element with Component_Size => 2, Size => 4; -- Type definition for SDSR_MODES @@ -671,16 +585,16 @@ package STM32F429x.FSMC is -- SDRAM Status register type SDSR_Register is record - -- Refresh error flag + -- Read-only. Refresh error flag RE : SDSR_RE_Field; - -- Status Mode for Bank 1 + -- Read-only. Status Mode for Bank 1 MODES : SDSR_MODES_Field; - -- Busy status + -- Read-only. Busy status BUSY : SDSR_BUSY_Field; -- unspecified Reserved_6_31 : STM32F429x.UInt26; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SDSR_Register use record RE at 0 range 0 .. 0; @@ -696,115 +610,147 @@ package STM32F429x.FSMC is -- Flexible memory controller type FMC_Peripheral is record -- SRAM/NOR-Flash chip-select control register 1 - BCR1 : BCR1_Register; + BCR1 : aliased BCR1_Register; + pragma Volatile_Full_Access (BCR1); -- SRAM/NOR-Flash chip-select timing register 1 - BTR1 : BTR_Register; + BTR1 : aliased BTR_Register; + pragma Volatile_Full_Access (BTR1); -- SRAM/NOR-Flash chip-select control register 2 - BCR2 : BCR_Register; + BCR2 : aliased BCR_Register; + pragma Volatile_Full_Access (BCR2); -- SRAM/NOR-Flash chip-select timing register 2 - BTR2 : BTR_Register; + BTR2 : aliased BTR_Register; + pragma Volatile_Full_Access (BTR2); -- SRAM/NOR-Flash chip-select control register 3 - BCR3 : BCR_Register; + BCR3 : aliased BCR_Register; + pragma Volatile_Full_Access (BCR3); -- SRAM/NOR-Flash chip-select timing register 3 - BTR3 : BTR_Register; + BTR3 : aliased BTR_Register; + pragma Volatile_Full_Access (BTR3); -- SRAM/NOR-Flash chip-select control register 4 - BCR4 : BCR_Register; + BCR4 : aliased BCR_Register; + pragma Volatile_Full_Access (BCR4); -- SRAM/NOR-Flash chip-select timing register 4 - BTR4 : BTR_Register; + BTR4 : aliased BTR_Register; + pragma Volatile_Full_Access (BTR4); -- PC Card/NAND Flash control register 2 - PCR2 : PCR_Register; + PCR2 : aliased PCR_Register; + pragma Volatile_Full_Access (PCR2); -- FIFO status and interrupt register 2 - SR2 : SR_Register; + SR2 : aliased SR_Register; + pragma Volatile_Full_Access (SR2); -- Common memory space timing register 2 - PMEM2 : PMEM_Register; + PMEM2 : aliased PMEM_Register; + pragma Volatile_Full_Access (PMEM2); -- Attribute memory space timing register 2 - PATT2 : PATT_Register; + PATT2 : aliased PATT_Register; + pragma Volatile_Full_Access (PATT2); -- ECC result register 2 - ECCR2 : STM32F429x.Word; + ECCR2 : aliased STM32F429x.UInt32; -- PC Card/NAND Flash control register 3 - PCR3 : PCR_Register; + PCR3 : aliased PCR_Register; + pragma Volatile_Full_Access (PCR3); -- FIFO status and interrupt register 3 - SR3 : SR_Register; + SR3 : aliased SR_Register; + pragma Volatile_Full_Access (SR3); -- Common memory space timing register 3 - PMEM3 : PMEM_Register; + PMEM3 : aliased PMEM_Register; + pragma Volatile_Full_Access (PMEM3); -- Attribute memory space timing register 3 - PATT3 : PATT_Register; + PATT3 : aliased PATT_Register; + pragma Volatile_Full_Access (PATT3); -- ECC result register 3 - ECCR3 : STM32F429x.Word; + ECCR3 : aliased STM32F429x.UInt32; -- PC Card/NAND Flash control register 4 - PCR4 : PCR_Register; + PCR4 : aliased PCR_Register; + pragma Volatile_Full_Access (PCR4); -- FIFO status and interrupt register 4 - SR4 : SR_Register; + SR4 : aliased SR_Register; + pragma Volatile_Full_Access (SR4); -- Common memory space timing register 4 - PMEM4 : PMEM_Register; + PMEM4 : aliased PMEM_Register; + pragma Volatile_Full_Access (PMEM4); -- Attribute memory space timing register 4 - PATT4 : PATT_Register; + PATT4 : aliased PATT_Register; + pragma Volatile_Full_Access (PATT4); -- I/O space timing register 4 - PIO4 : PIO4_Register; + PIO4 : aliased PIO4_Register; + pragma Volatile_Full_Access (PIO4); -- SRAM/NOR-Flash write timing registers 1 - BWTR1 : BWTR_Register; + BWTR1 : aliased BWTR_Register; + pragma Volatile_Full_Access (BWTR1); -- SRAM/NOR-Flash write timing registers 2 - BWTR2 : BWTR_Register; + BWTR2 : aliased BWTR_Register; + pragma Volatile_Full_Access (BWTR2); -- SRAM/NOR-Flash write timing registers 3 - BWTR3 : BWTR_Register; + BWTR3 : aliased BWTR_Register; + pragma Volatile_Full_Access (BWTR3); -- SRAM/NOR-Flash write timing registers 4 - BWTR4 : BWTR_Register; + BWTR4 : aliased BWTR_Register; + pragma Volatile_Full_Access (BWTR4); -- SDRAM Control Register 1 - SDCR1 : SDCR_Register; + SDCR1 : aliased SDCR_Register; + pragma Volatile_Full_Access (SDCR1); -- SDRAM Control Register 2 - SDCR2 : SDCR_Register; + SDCR2 : aliased SDCR_Register; + pragma Volatile_Full_Access (SDCR2); -- SDRAM Timing register 1 - SDTR1 : SDTR_Register; + SDTR1 : aliased SDTR_Register; + pragma Volatile_Full_Access (SDTR1); -- SDRAM Timing register 2 - SDTR2 : SDTR_Register; + SDTR2 : aliased SDTR_Register; + pragma Volatile_Full_Access (SDTR2); -- SDRAM Command Mode register - SDCMR : SDCMR_Register; + SDCMR : aliased SDCMR_Register; + pragma Volatile_Full_Access (SDCMR); -- SDRAM Refresh Timer register - SDRTR : SDRTR_Register; + SDRTR : aliased SDRTR_Register; + pragma Volatile_Full_Access (SDRTR); -- SDRAM Status register - SDSR : SDSR_Register; + SDSR : aliased SDSR_Register; + pragma Volatile_Full_Access (SDSR); end record with Volatile; for FMC_Peripheral use record - BCR1 at 0 range 0 .. 31; - BTR1 at 4 range 0 .. 31; - BCR2 at 8 range 0 .. 31; - BTR2 at 12 range 0 .. 31; - BCR3 at 16 range 0 .. 31; - BTR3 at 20 range 0 .. 31; - BCR4 at 24 range 0 .. 31; - BTR4 at 28 range 0 .. 31; - PCR2 at 96 range 0 .. 31; - SR2 at 100 range 0 .. 31; - PMEM2 at 104 range 0 .. 31; - PATT2 at 108 range 0 .. 31; - ECCR2 at 116 range 0 .. 31; - PCR3 at 128 range 0 .. 31; - SR3 at 132 range 0 .. 31; - PMEM3 at 136 range 0 .. 31; - PATT3 at 140 range 0 .. 31; - ECCR3 at 148 range 0 .. 31; - PCR4 at 160 range 0 .. 31; - SR4 at 164 range 0 .. 31; - PMEM4 at 168 range 0 .. 31; - PATT4 at 172 range 0 .. 31; - PIO4 at 176 range 0 .. 31; - BWTR1 at 260 range 0 .. 31; - BWTR2 at 268 range 0 .. 31; - BWTR3 at 276 range 0 .. 31; - BWTR4 at 284 range 0 .. 31; - SDCR1 at 320 range 0 .. 31; - SDCR2 at 324 range 0 .. 31; - SDTR1 at 328 range 0 .. 31; - SDTR2 at 332 range 0 .. 31; - SDCMR at 336 range 0 .. 31; - SDRTR at 340 range 0 .. 31; - SDSR at 344 range 0 .. 31; + BCR1 at 16#0# range 0 .. 31; + BTR1 at 16#4# range 0 .. 31; + BCR2 at 16#8# range 0 .. 31; + BTR2 at 16#C# range 0 .. 31; + BCR3 at 16#10# range 0 .. 31; + BTR3 at 16#14# range 0 .. 31; + BCR4 at 16#18# range 0 .. 31; + BTR4 at 16#1C# range 0 .. 31; + PCR2 at 16#60# range 0 .. 31; + SR2 at 16#64# range 0 .. 31; + PMEM2 at 16#68# range 0 .. 31; + PATT2 at 16#6C# range 0 .. 31; + ECCR2 at 16#74# range 0 .. 31; + PCR3 at 16#80# range 0 .. 31; + SR3 at 16#84# range 0 .. 31; + PMEM3 at 16#88# range 0 .. 31; + PATT3 at 16#8C# range 0 .. 31; + ECCR3 at 16#94# range 0 .. 31; + PCR4 at 16#A0# range 0 .. 31; + SR4 at 16#A4# range 0 .. 31; + PMEM4 at 16#A8# range 0 .. 31; + PATT4 at 16#AC# range 0 .. 31; + PIO4 at 16#B0# range 0 .. 31; + BWTR1 at 16#104# range 0 .. 31; + BWTR2 at 16#10C# range 0 .. 31; + BWTR3 at 16#114# range 0 .. 31; + BWTR4 at 16#11C# range 0 .. 31; + SDCR1 at 16#140# range 0 .. 31; + SDCR2 at 16#144# range 0 .. 31; + SDTR1 at 16#148# range 0 .. 31; + SDTR2 at 16#14C# range 0 .. 31; + SDCMR at 16#150# range 0 .. 31; + SDRTR at 16#154# range 0 .. 31; + SDSR at 16#158# range 0 .. 31; end record; -- Flexible memory controller FMC_Periph : aliased FMC_Peripheral - with Import, Address => System'To_Address (16#A0000000#); + with Import, Address => FMC_Base; end STM32F429x.FSMC; diff --git a/stm32f429i/stm32f429x/stm32f429x-gpio.ads b/stm32f429i/stm32f429x/stm32f429x-gpio.ads index a8c492c..daeb186 100644 --- a/stm32f429i/stm32f429x/stm32f429x-gpio.ads +++ b/stm32f429i/stm32f429x/stm32f429x-gpio.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.GPIO is -- Registers -- --------------- - -------------------- - -- MODER_Register -- - -------------------- - -- MODER array element subtype MODER_Element is STM32F429x.UInt2; @@ -30,13 +28,13 @@ package STM32F429x.GPIO is case As_Array is when False => -- MODER as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- MODER as an array Arr : MODER_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for MODER_Register use record @@ -44,14 +42,6 @@ package STM32F429x.GPIO is Arr at 0 range 0 .. 31; end record; - --------------------- - -- OTYPER_Register -- - --------------------- - - --------------- - -- OTYPER.OT -- - --------------- - -- OTYPER_OT array element subtype OTYPER_OT_Element is STM32F429x.Bit; @@ -66,7 +56,7 @@ package STM32F429x.GPIO is case As_Array is when False => -- OT as a value - Val : STM32F429x.Short; + Val : STM32F429x.UInt16; when True => -- OT as an array Arr : OTYPER_OT_Field_Array; @@ -84,19 +74,15 @@ package STM32F429x.GPIO is -- Port x configuration bits (y = 0..15) OT : OTYPER_OT_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OTYPER_Register use record OT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- OSPEEDR_Register -- - ---------------------- - -- OSPEEDR array element subtype OSPEEDR_Element is STM32F429x.UInt2; @@ -111,13 +97,13 @@ package STM32F429x.GPIO is case As_Array is when False => -- OSPEEDR as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- OSPEEDR as an array Arr : OSPEEDR_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for OSPEEDR_Register use record @@ -125,10 +111,6 @@ package STM32F429x.GPIO is Arr at 0 range 0 .. 31; end record; - -------------------- - -- PUPDR_Register -- - -------------------- - -- PUPDR array element subtype PUPDR_Element is STM32F429x.UInt2; @@ -143,13 +125,13 @@ package STM32F429x.GPIO is case As_Array is when False => -- PUPDR as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- PUPDR as an array Arr : PUPDR_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for PUPDR_Register use record @@ -157,14 +139,6 @@ package STM32F429x.GPIO is Arr at 0 range 0 .. 31; end record; - ------------------ - -- IDR_Register -- - ------------------ - - ------------- - -- IDR.IDR -- - ------------- - -- IDR array element subtype IDR_Element is STM32F429x.Bit; @@ -179,7 +153,7 @@ package STM32F429x.GPIO is case As_Array is when False => -- IDR as a value - Val : STM32F429x.Short; + Val : STM32F429x.UInt16; when True => -- IDR as an array Arr : IDR_Field_Array; @@ -194,26 +168,18 @@ package STM32F429x.GPIO is -- GPIO port input data register type IDR_Register is record - -- Port input data (y = 0..15) + -- Read-only. Port input data (y = 0..15) IDR : IDR_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IDR_Register use record IDR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- ODR_Register -- - ------------------ - - ------------- - -- ODR.ODR -- - ------------- - -- ODR array element subtype ODR_Element is STM32F429x.Bit; @@ -228,7 +194,7 @@ package STM32F429x.GPIO is case As_Array is when False => -- ODR as a value - Val : STM32F429x.Short; + Val : STM32F429x.UInt16; when True => -- ODR as an array Arr : ODR_Field_Array; @@ -246,23 +212,15 @@ package STM32F429x.GPIO is -- Port output data (y = 0..15) ODR : ODR_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ODR_Register use record ODR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- BSRR_Register -- - ------------------- - - ------------- - -- BSRR.BS -- - ------------- - -- BSRR_BS array element subtype BSRR_BS_Element is STM32F429x.Bit; @@ -277,7 +235,7 @@ package STM32F429x.GPIO is case As_Array is when False => -- BS as a value - Val : STM32F429x.Short; + Val : STM32F429x.UInt16; when True => -- BS as an array Arr : BSRR_BS_Field_Array; @@ -290,10 +248,6 @@ package STM32F429x.GPIO is Arr at 0 range 0 .. 15; end record; - ------------- - -- BSRR.BR -- - ------------- - -- BSRR_BR array element subtype BSRR_BR_Element is STM32F429x.Bit; @@ -308,7 +262,7 @@ package STM32F429x.GPIO is case As_Array is when False => -- BR as a value - Val : STM32F429x.Short; + Val : STM32F429x.UInt16; when True => -- BR as an array Arr : BSRR_BR_Field_Array; @@ -323,26 +277,18 @@ package STM32F429x.GPIO is -- GPIO port bit set/reset register type BSRR_Register is record - -- Port x set bit y (y= 0..15) + -- Write-only. Port x set bit y (y= 0..15) BS : BSRR_BS_Field := (As_Array => False, Val => 16#0#); - -- Port x set bit y (y= 0..15) + -- Write-only. Port x set bit y (y= 0..15) BR : BSRR_BR_Field := (As_Array => False, Val => 16#0#); end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BSRR_Register use record BS at 0 range 0 .. 15; BR at 0 range 16 .. 31; end record; - ------------------- - -- LCKR_Register -- - ------------------- - - -------------- - -- LCKR.LCK -- - -------------- - -- LCKR_LCK array element subtype LCKR_LCK_Element is STM32F429x.Bit; @@ -357,7 +303,7 @@ package STM32F429x.GPIO is case As_Array is when False => -- LCK as a value - Val : STM32F429x.Short; + Val : STM32F429x.UInt16; when True => -- LCK as an array Arr : LCKR_LCK_Field_Array; @@ -381,7 +327,7 @@ package STM32F429x.GPIO is -- unspecified Reserved_17_31 : STM32F429x.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LCKR_Register use record LCK at 0 range 0 .. 15; @@ -389,10 +335,6 @@ package STM32F429x.GPIO is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------- - -- AFRL_Register -- - ------------------- - -- AFRL array element subtype AFRL_Element is STM32F429x.UInt4; @@ -407,13 +349,13 @@ package STM32F429x.GPIO is case As_Array is when False => -- AFRL as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- AFRL as an array Arr : AFRL_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for AFRL_Register use record @@ -421,15 +363,11 @@ package STM32F429x.GPIO is Arr at 0 range 0 .. 31; end record; - ------------------- - -- AFRH_Register -- - ------------------- - -- AFRH array element subtype AFRH_Element is STM32F429x.UInt4; -- AFRH array - type AFRH_Field_Array is array (0 .. 7) of AFRH_Element + type AFRH_Field_Array is array (8 .. 15) of AFRH_Element with Component_Size => 4, Size => 32; -- GPIO alternate function high register @@ -439,13 +377,13 @@ package STM32F429x.GPIO is case As_Array is when False => -- AFRH as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- AFRH as an array Arr : AFRH_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for AFRH_Register use record @@ -460,83 +398,93 @@ package STM32F429x.GPIO is -- General-purpose I/Os type GPIO_Peripheral is record -- GPIO port mode register - MODER : MODER_Register; + MODER : aliased MODER_Register; + pragma Volatile_Full_Access (MODER); -- GPIO port output type register - OTYPER : OTYPER_Register; + OTYPER : aliased OTYPER_Register; + pragma Volatile_Full_Access (OTYPER); -- GPIO port output speed register - OSPEEDR : OSPEEDR_Register; + OSPEEDR : aliased OSPEEDR_Register; + pragma Volatile_Full_Access (OSPEEDR); -- GPIO port pull-up/pull-down register - PUPDR : PUPDR_Register; + PUPDR : aliased PUPDR_Register; + pragma Volatile_Full_Access (PUPDR); -- GPIO port input data register - IDR : IDR_Register; + IDR : aliased IDR_Register; + pragma Volatile_Full_Access (IDR); -- GPIO port output data register - ODR : ODR_Register; + ODR : aliased ODR_Register; + pragma Volatile_Full_Access (ODR); -- GPIO port bit set/reset register - BSRR : BSRR_Register; + BSRR : aliased BSRR_Register; + pragma Volatile_Full_Access (BSRR); -- GPIO port configuration lock register - LCKR : LCKR_Register; + LCKR : aliased LCKR_Register; + pragma Volatile_Full_Access (LCKR); -- GPIO alternate function low register - AFRL : AFRL_Register; + AFRL : aliased AFRL_Register; + pragma Volatile_Full_Access (AFRL); -- GPIO alternate function high register - AFRH : AFRH_Register; + AFRH : aliased AFRH_Register; + pragma Volatile_Full_Access (AFRH); end record with Volatile; for GPIO_Peripheral use record - MODER at 0 range 0 .. 31; - OTYPER at 4 range 0 .. 31; - OSPEEDR at 8 range 0 .. 31; - PUPDR at 12 range 0 .. 31; - IDR at 16 range 0 .. 31; - ODR at 20 range 0 .. 31; - BSRR at 24 range 0 .. 31; - LCKR at 28 range 0 .. 31; - AFRL at 32 range 0 .. 31; - AFRH at 36 range 0 .. 31; + MODER at 16#0# range 0 .. 31; + OTYPER at 16#4# range 0 .. 31; + OSPEEDR at 16#8# range 0 .. 31; + PUPDR at 16#C# range 0 .. 31; + IDR at 16#10# range 0 .. 31; + ODR at 16#14# range 0 .. 31; + BSRR at 16#18# range 0 .. 31; + LCKR at 16#1C# range 0 .. 31; + AFRL at 16#20# range 0 .. 31; + AFRH at 16#24# range 0 .. 31; end record; -- General-purpose I/Os GPIOA_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40020000#); + with Import, Address => GPIOA_Base; -- General-purpose I/Os GPIOB_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40020400#); + with Import, Address => GPIOB_Base; -- General-purpose I/Os GPIOC_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40020800#); + with Import, Address => GPIOC_Base; -- General-purpose I/Os GPIOD_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40020C00#); + with Import, Address => GPIOD_Base; -- General-purpose I/Os GPIOE_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40021000#); + with Import, Address => GPIOE_Base; -- General-purpose I/Os GPIOF_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40021400#); + with Import, Address => GPIOF_Base; -- General-purpose I/Os GPIOG_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40021800#); + with Import, Address => GPIOG_Base; -- General-purpose I/Os GPIOH_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40021C00#); + with Import, Address => GPIOH_Base; -- General-purpose I/Os GPIOI_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40022000#); + with Import, Address => GPIOI_Base; -- General-purpose I/Os GPIOJ_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40022400#); + with Import, Address => GPIOJ_Base; -- General-purpose I/Os GPIOK_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#40022800#); + with Import, Address => GPIOK_Base; end STM32F429x.GPIO; diff --git a/stm32f429i/stm32f429x/stm32f429x-i2c.ads b/stm32f429i/stm32f429x/stm32f429x-i2c.ads index cd00265..6adc6e9 100644 --- a/stm32f429i/stm32f429x/stm32f429x-i2c.ads +++ b/stm32f429i/stm32f429x/stm32f429x-i2c.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.I2C is -- Registers -- --------------- - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_PE_Field is STM32F429x.Bit; subtype CR1_SMBUS_Field is STM32F429x.Bit; subtype CR1_SMBTYPE_Field is STM32F429x.Bit; @@ -66,9 +64,9 @@ package STM32F429x.I2C is -- Software reset SWRST : CR1_SWRST_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record PE at 0 range 0 .. 0; @@ -90,10 +88,6 @@ package STM32F429x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_FREQ_Field is STM32F429x.UInt6; subtype CR2_ITERREN_Field is STM32F429x.Bit; subtype CR2_ITEVTEN_Field is STM32F429x.Bit; @@ -120,7 +114,7 @@ package STM32F429x.I2C is -- unspecified Reserved_13_31 : STM32F429x.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record FREQ at 0 range 0 .. 5; @@ -133,10 +127,6 @@ package STM32F429x.I2C is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------- - -- OAR1_Register -- - ------------------- - subtype OAR1_ADD0_Field is STM32F429x.Bit; subtype OAR1_ADD7_Field is STM32F429x.UInt7; subtype OAR1_ADD10_Field is STM32F429x.UInt2; @@ -155,9 +145,9 @@ package STM32F429x.I2C is -- Addressing mode (slave mode) ADDMODE : OAR1_ADDMODE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OAR1_Register use record ADD0 at 0 range 0 .. 0; @@ -168,10 +158,6 @@ package STM32F429x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- OAR2_Register -- - ------------------- - subtype OAR2_ENDUAL_Field is STM32F429x.Bit; subtype OAR2_ADD2_Field is STM32F429x.UInt7; @@ -184,7 +170,7 @@ package STM32F429x.I2C is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OAR2_Register use record ENDUAL at 0 range 0 .. 0; @@ -192,10 +178,6 @@ package STM32F429x.I2C is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - subtype DR_DR_Field is STM32F429x.Byte; -- Data register @@ -205,17 +187,13 @@ package STM32F429x.I2C is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DR at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- SR1_Register -- - ------------------ - subtype SR1_SB_Field is STM32F429x.Bit; subtype SR1_ADDR_Field is STM32F429x.Bit; subtype SR1_BTF_Field is STM32F429x.Bit; @@ -233,21 +211,21 @@ package STM32F429x.I2C is -- Status register 1 type SR1_Register is record - -- Start bit (Master mode) + -- Read-only. Start bit (Master mode) SB : SR1_SB_Field := 16#0#; - -- Address sent (master mode)/matched (slave mode) + -- Read-only. Address sent (master mode)/matched (slave mode) ADDR : SR1_ADDR_Field := 16#0#; - -- Byte transfer finished + -- Read-only. Byte transfer finished BTF : SR1_BTF_Field := 16#0#; - -- 10-bit header sent (Master mode) + -- Read-only. 10-bit header sent (Master mode) ADD10 : SR1_ADD10_Field := 16#0#; - -- Stop detection (slave mode) + -- Read-only. Stop detection (slave mode) STOPF : SR1_STOPF_Field := 16#0#; -- unspecified Reserved_5_5 : STM32F429x.Bit := 16#0#; - -- Data register not empty (receivers) + -- Read-only. Data register not empty (receivers) RxNE : SR1_RxNE_Field := 16#0#; - -- Data register empty (transmitters) + -- Read-only. Data register empty (transmitters) TxE : SR1_TxE_Field := 16#0#; -- Bus error BERR : SR1_BERR_Field := 16#0#; @@ -266,9 +244,9 @@ package STM32F429x.I2C is -- SMBus alert SMBALERT : SR1_SMBALERT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR1_Register use record SB at 0 range 0 .. 0; @@ -290,10 +268,6 @@ package STM32F429x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- SR2_Register -- - ------------------ - subtype SR2_MSL_Field is STM32F429x.Bit; subtype SR2_BUSY_Field is STM32F429x.Bit; subtype SR2_TRA_Field is STM32F429x.Bit; @@ -305,28 +279,28 @@ package STM32F429x.I2C is -- Status register 2 type SR2_Register is record - -- Master/slave + -- Read-only. Master/slave MSL : SR2_MSL_Field; - -- Bus busy + -- Read-only. Bus busy BUSY : SR2_BUSY_Field; - -- Transmitter/receiver + -- Read-only. Transmitter/receiver TRA : SR2_TRA_Field; -- unspecified Reserved_3_3 : STM32F429x.Bit; - -- General call address (Slave mode) + -- Read-only. General call address (Slave mode) GENCALL : SR2_GENCALL_Field; - -- SMBus device default address (Slave mode) + -- Read-only. SMBus device default address (Slave mode) SMBDEFAULT : SR2_SMBDEFAULT_Field; - -- SMBus host header (Slave mode) + -- Read-only. SMBus host header (Slave mode) SMBHOST : SR2_SMBHOST_Field; - -- Dual flag (Slave mode) + -- Read-only. Dual flag (Slave mode) DUALF : SR2_DUALF_Field; - -- acket error checking register + -- Read-only. acket error checking register PEC : SR2_PEC_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR2_Register use record MSL at 0 range 0 .. 0; @@ -341,10 +315,6 @@ package STM32F429x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CCR_Register -- - ------------------ - subtype CCR_CCR_Field is STM32F429x.UInt12; subtype CCR_DUTY_Field is STM32F429x.Bit; subtype CCR_F_S_Field is STM32F429x.Bit; @@ -360,9 +330,9 @@ package STM32F429x.I2C is -- I2C master mode selection F_S : CCR_F_S_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCR_Register use record CCR at 0 range 0 .. 11; @@ -372,10 +342,6 @@ package STM32F429x.I2C is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- TRISE_Register -- - -------------------- - subtype TRISE_TRISE_Field is STM32F429x.UInt6; -- TRISE register @@ -385,13 +351,34 @@ package STM32F429x.I2C is -- unspecified Reserved_6_31 : STM32F429x.UInt26 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TRISE_Register use record TRISE at 0 range 0 .. 5; Reserved_6_31 at 0 range 6 .. 31; end record; + subtype FLTR_DNF_Field is STM32F429x.UInt4; + subtype FLTR_ANOFF_Field is STM32F429x.Bit; + + -- FLTR register + type FLTR_Register is record + -- Digital Noise Filter. 0 to disable, or filtering capability up to N * + -- TPCLK1 + DNF : FLTR_DNF_Field := 16#0#; + -- Analog noise filter OFF + ANOFF : FLTR_ANOFF_Field := 16#0#; + -- unspecified + Reserved_5_31 : STM32F429x.UInt27 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for FLTR_Register use record + DNF at 0 range 0 .. 3; + ANOFF at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + ----------------- -- Peripherals -- ----------------- @@ -399,48 +386,61 @@ package STM32F429x.I2C is -- Inter-integrated circuit type I2C_Peripheral is record -- Control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- Control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- Own address register 1 - OAR1 : OAR1_Register; + OAR1 : aliased OAR1_Register; + pragma Volatile_Full_Access (OAR1); -- Own address register 2 - OAR2 : OAR2_Register; + OAR2 : aliased OAR2_Register; + pragma Volatile_Full_Access (OAR2); -- Data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- Status register 1 - SR1 : SR1_Register; + SR1 : aliased SR1_Register; + pragma Volatile_Full_Access (SR1); -- Status register 2 - SR2 : SR2_Register; + SR2 : aliased SR2_Register; + pragma Volatile_Full_Access (SR2); -- Clock control register - CCR : CCR_Register; + CCR : aliased CCR_Register; + pragma Volatile_Full_Access (CCR); -- TRISE register - TRISE : TRISE_Register; + TRISE : aliased TRISE_Register; + pragma Volatile_Full_Access (TRISE); + -- FLTR register + FLTR : aliased FLTR_Register; + pragma Volatile_Full_Access (FLTR); end record with Volatile; for I2C_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - OAR1 at 8 range 0 .. 31; - OAR2 at 12 range 0 .. 31; - DR at 16 range 0 .. 31; - SR1 at 20 range 0 .. 31; - SR2 at 24 range 0 .. 31; - CCR at 28 range 0 .. 31; - TRISE at 32 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + OAR1 at 16#8# range 0 .. 31; + OAR2 at 16#C# range 0 .. 31; + DR at 16#10# range 0 .. 31; + SR1 at 16#14# range 0 .. 31; + SR2 at 16#18# range 0 .. 31; + CCR at 16#1C# range 0 .. 31; + TRISE at 16#20# range 0 .. 31; + FLTR at 16#24# range 0 .. 31; end record; -- Inter-integrated circuit I2C1_Periph : aliased I2C_Peripheral - with Import, Address => System'To_Address (16#40005400#); + with Import, Address => I2C1_Base; -- Inter-integrated circuit I2C2_Periph : aliased I2C_Peripheral - with Import, Address => System'To_Address (16#40005800#); + with Import, Address => I2C2_Base; -- Inter-integrated circuit I2C3_Periph : aliased I2C_Peripheral - with Import, Address => System'To_Address (16#40005C00#); + with Import, Address => I2C3_Base; end STM32F429x.I2C; diff --git a/stm32f429i/stm32f429x/stm32f429x-iwdg.ads b/stm32f429i/stm32f429x/stm32f429x-iwdg.ads index cdecef4..596fa16 100644 --- a/stm32f429i/stm32f429x/stm32f429x-iwdg.ads +++ b/stm32f429i/stm32f429x/stm32f429x-iwdg.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,30 +14,22 @@ package STM32F429x.IWDG is -- Registers -- --------------- - ----------------- - -- KR_Register -- - ----------------- - - subtype KR_KEY_Field is STM32F429x.Short; + subtype KR_KEY_Field is STM32F429x.UInt16; -- Key register type KR_Register is record - -- Key value (write only, read 0000h) + -- Write-only. Key value (write only, read 0000h) KEY : KR_KEY_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for KR_Register use record KEY at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------- - -- PR_Register -- - ----------------- - subtype PR_PR_Field is STM32F429x.UInt3; -- Prescaler register @@ -45,17 +39,13 @@ package STM32F429x.IWDG is -- unspecified Reserved_3_31 : STM32F429x.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PR_Register use record PR at 0 range 0 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - ------------------ - -- RLR_Register -- - ------------------ - subtype RLR_RL_Field is STM32F429x.UInt12; -- Reload register @@ -65,30 +55,26 @@ package STM32F429x.IWDG is -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RLR_Register use record RL at 0 range 0 .. 11; Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_PVU_Field is STM32F429x.Bit; subtype SR_RVU_Field is STM32F429x.Bit; -- Status register type SR_Register is record - -- Watchdog prescaler value update + -- Read-only. Watchdog prescaler value update PVU : SR_PVU_Field; - -- Watchdog counter reload value update + -- Read-only. Watchdog counter reload value update RVU : SR_RVU_Field; -- unspecified Reserved_2_31 : STM32F429x.UInt30; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record PVU at 0 range 0 .. 0; @@ -103,25 +89,29 @@ package STM32F429x.IWDG is -- Independent watchdog type IWDG_Peripheral is record -- Key register - KR : KR_Register; + KR : aliased KR_Register; + pragma Volatile_Full_Access (KR); -- Prescaler register - PR : PR_Register; + PR : aliased PR_Register; + pragma Volatile_Full_Access (PR); -- Reload register - RLR : RLR_Register; + RLR : aliased RLR_Register; + pragma Volatile_Full_Access (RLR); -- Status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; for IWDG_Peripheral use record - KR at 0 range 0 .. 31; - PR at 4 range 0 .. 31; - RLR at 8 range 0 .. 31; - SR at 12 range 0 .. 31; + KR at 16#0# range 0 .. 31; + PR at 16#4# range 0 .. 31; + RLR at 16#8# range 0 .. 31; + SR at 16#C# range 0 .. 31; end record; -- Independent watchdog IWDG_Periph : aliased IWDG_Peripheral - with Import, Address => System'To_Address (16#40003000#); + with Import, Address => IWDG_Base; end STM32F429x.IWDG; diff --git a/stm32f429i/stm32f429x/stm32f429x-ltdc.ads b/stm32f429i/stm32f429x/stm32f429x-ltdc.ads index cc0d20f..37b1760 100644 --- a/stm32f429i/stm32f429x/stm32f429x-ltdc.ads +++ b/stm32f429i/stm32f429x/stm32f429x-ltdc.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.LTDC is -- Registers -- --------------- - ------------------- - -- SSCR_Register -- - ------------------- - subtype SSCR_VSH_Field is STM32F429x.UInt11; subtype SSCR_HSW_Field is STM32F429x.UInt12; @@ -30,7 +28,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SSCR_Register use record VSH at 0 range 0 .. 10; @@ -39,10 +37,6 @@ package STM32F429x.LTDC is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- BPCR_Register -- - ------------------- - subtype BPCR_AVBP_Field is STM32F429x.UInt11; subtype BPCR_AHBP_Field is STM32F429x.UInt12; @@ -57,7 +51,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BPCR_Register use record AVBP at 0 range 0 .. 10; @@ -66,10 +60,6 @@ package STM32F429x.LTDC is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- AWCR_Register -- - ------------------- - subtype AWCR_AAH_Field is STM32F429x.UInt11; subtype AWCR_AAW_Field is STM32F429x.UInt12; @@ -84,7 +74,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AWCR_Register use record AAH at 0 range 0 .. 10; @@ -93,10 +83,6 @@ package STM32F429x.LTDC is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- TWCR_Register -- - ------------------- - subtype TWCR_TOTALH_Field is STM32F429x.UInt11; subtype TWCR_TOTALW_Field is STM32F429x.UInt12; @@ -111,7 +97,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TWCR_Register use record TOTALH at 0 range 0 .. 10; @@ -120,10 +106,6 @@ package STM32F429x.LTDC is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------ - -- GCR_Register -- - ------------------ - subtype GCR_LTDCEN_Field is STM32F429x.Bit; subtype GCR_DBW_Field is STM32F429x.UInt3; subtype GCR_DGW_Field is STM32F429x.UInt3; @@ -140,15 +122,15 @@ package STM32F429x.LTDC is LTDCEN : GCR_LTDCEN_Field := 16#0#; -- unspecified Reserved_1_3 : STM32F429x.UInt3 := 16#0#; - -- Dither Blue Width + -- Read-only. Dither Blue Width DBW : GCR_DBW_Field := 16#2#; -- unspecified Reserved_7_7 : STM32F429x.Bit := 16#0#; - -- Dither Green Width + -- Read-only. Dither Green Width DGW : GCR_DGW_Field := 16#2#; -- unspecified Reserved_11_11 : STM32F429x.Bit := 16#0#; - -- Dither Red Width + -- Read-only. Dither Red Width DRW : GCR_DRW_Field := 16#2#; -- unspecified Reserved_15_15 : STM32F429x.Bit := 16#0#; @@ -165,7 +147,7 @@ package STM32F429x.LTDC is -- Horizontal Synchronization Polarity HSPOL : GCR_HSPOL_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for GCR_Register use record LTDCEN at 0 range 0 .. 0; @@ -184,10 +166,6 @@ package STM32F429x.LTDC is HSPOL at 0 range 31 .. 31; end record; - ------------------- - -- SRCR_Register -- - ------------------- - subtype SRCR_IMR_Field is STM32F429x.Bit; subtype SRCR_VBR_Field is STM32F429x.Bit; @@ -200,7 +178,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_2_31 : STM32F429x.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SRCR_Register use record IMR at 0 range 0 .. 0; @@ -208,10 +186,6 @@ package STM32F429x.LTDC is Reserved_2_31 at 0 range 2 .. 31; end record; - ------------------- - -- BCCR_Register -- - ------------------- - subtype BCCR_BC_Field is STM32F429x.UInt24; -- Background Color Configuration Register @@ -221,17 +195,13 @@ package STM32F429x.LTDC is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BCCR_Register use record BC at 0 range 0 .. 23; Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- IER_Register -- - ------------------ - subtype IER_LIE_Field is STM32F429x.Bit; subtype IER_FUIE_Field is STM32F429x.Bit; subtype IER_TERRIE_Field is STM32F429x.Bit; @@ -250,7 +220,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_4_31 : STM32F429x.UInt28 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for IER_Register use record LIE at 0 range 0 .. 0; @@ -260,10 +230,6 @@ package STM32F429x.LTDC is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ - subtype ISR_LIF_Field is STM32F429x.Bit; subtype ISR_FUIF_Field is STM32F429x.Bit; subtype ISR_TERRIF_Field is STM32F429x.Bit; @@ -271,18 +237,18 @@ package STM32F429x.LTDC is -- Interrupt Status Register type ISR_Register is record - -- Line Interrupt flag + -- Read-only. Line Interrupt flag LIF : ISR_LIF_Field; - -- FIFO Underrun Interrupt flag + -- Read-only. FIFO Underrun Interrupt flag FUIF : ISR_FUIF_Field; - -- Transfer Error interrupt flag + -- Read-only. Transfer Error interrupt flag TERRIF : ISR_TERRIF_Field; - -- Register Reload Interrupt Flag + -- Read-only. Register Reload Interrupt Flag RRIF : ISR_RRIF_Field; -- unspecified Reserved_4_31 : STM32F429x.UInt28; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ISR_Register use record LIF at 0 range 0 .. 0; @@ -292,10 +258,6 @@ package STM32F429x.LTDC is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------ - -- ICR_Register -- - ------------------ - subtype ICR_CLIF_Field is STM32F429x.Bit; subtype ICR_CFUIF_Field is STM32F429x.Bit; subtype ICR_CTERRIF_Field is STM32F429x.Bit; @@ -303,18 +265,18 @@ package STM32F429x.LTDC is -- Interrupt Clear Register type ICR_Register is record - -- Clears the Line Interrupt Flag + -- Write-only. Clears the Line Interrupt Flag CLIF : ICR_CLIF_Field := 16#0#; - -- Clears the FIFO Underrun Interrupt flag + -- Write-only. Clears the FIFO Underrun Interrupt flag CFUIF : ICR_CFUIF_Field := 16#0#; - -- Clears the Transfer Error Interrupt Flag + -- Write-only. Clears the Transfer Error Interrupt Flag CTERRIF : ICR_CTERRIF_Field := 16#0#; - -- Clears Register Reload Interrupt Flag + -- Write-only. Clears Register Reload Interrupt Flag CRRIF : ICR_CRRIF_Field := 16#0#; -- unspecified Reserved_4_31 : STM32F429x.UInt28 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ICR_Register use record CLIF at 0 range 0 .. 0; @@ -324,10 +286,6 @@ package STM32F429x.LTDC is Reserved_4_31 at 0 range 4 .. 31; end record; - -------------------- - -- LIPCR_Register -- - -------------------- - subtype LIPCR_LIPOS_Field is STM32F429x.UInt11; -- Line Interrupt Position Configuration Register @@ -337,38 +295,30 @@ package STM32F429x.LTDC is -- unspecified Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for LIPCR_Register use record LIPOS at 0 range 0 .. 10; Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------- - -- CPSR_Register -- - ------------------- - - subtype CPSR_CYPOS_Field is STM32F429x.Short; - subtype CPSR_CXPOS_Field is STM32F429x.Short; + subtype CPSR_CYPOS_Field is STM32F429x.UInt16; + subtype CPSR_CXPOS_Field is STM32F429x.UInt16; -- Current Position Status Register type CPSR_Register is record - -- Current Y Position + -- Read-only. Current Y Position CYPOS : CPSR_CYPOS_Field; - -- Current X Position + -- Read-only. Current X Position CXPOS : CPSR_CXPOS_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CPSR_Register use record CYPOS at 0 range 0 .. 15; CXPOS at 0 range 16 .. 31; end record; - ------------------- - -- CDSR_Register -- - ------------------- - subtype CDSR_VDES_Field is STM32F429x.Bit; subtype CDSR_HDES_Field is STM32F429x.Bit; subtype CDSR_VSYNCS_Field is STM32F429x.Bit; @@ -376,18 +326,18 @@ package STM32F429x.LTDC is -- Current Display Status Register type CDSR_Register is record - -- Vertical Data Enable display Status + -- Read-only. Vertical Data Enable display Status VDES : CDSR_VDES_Field; - -- Horizontal Data Enable display Status + -- Read-only. Horizontal Data Enable display Status HDES : CDSR_HDES_Field; - -- Vertical Synchronization display Status + -- Read-only. Vertical Synchronization display Status VSYNCS : CDSR_VSYNCS_Field; - -- Horizontal Synchronization display Status + -- Read-only. Horizontal Synchronization display Status HSYNCS : CDSR_HSYNCS_Field; -- unspecified Reserved_4_31 : STM32F429x.UInt28; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CDSR_Register use record VDES at 0 range 0 .. 0; @@ -397,10 +347,6 @@ package STM32F429x.LTDC is Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------- - -- L1CR_Register -- - ------------------- - subtype L1CR_LEN_Field is STM32F429x.Bit; subtype L1CR_COLKEN_Field is STM32F429x.Bit; subtype L1CR_CLUTEN_Field is STM32F429x.Bit; @@ -418,7 +364,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_5_31 : STM32F429x.UInt27 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1CR_Register use record LEN at 0 range 0 .. 0; @@ -428,10 +374,6 @@ package STM32F429x.LTDC is Reserved_5_31 at 0 range 5 .. 31; end record; - ---------------------- - -- L1WHPCR_Register -- - ---------------------- - subtype L1WHPCR_WHSTPOS_Field is STM32F429x.UInt12; subtype L1WHPCR_WHSPPOS_Field is STM32F429x.UInt12; @@ -446,7 +388,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1WHPCR_Register use record WHSTPOS at 0 range 0 .. 11; @@ -455,10 +397,6 @@ package STM32F429x.LTDC is Reserved_28_31 at 0 range 28 .. 31; end record; - ---------------------- - -- L1WVPCR_Register -- - ---------------------- - subtype L1WVPCR_WVSTPOS_Field is STM32F429x.UInt11; subtype L1WVPCR_WVSPPOS_Field is STM32F429x.UInt11; @@ -473,7 +411,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1WVPCR_Register use record WVSTPOS at 0 range 0 .. 10; @@ -482,10 +420,6 @@ package STM32F429x.LTDC is Reserved_27_31 at 0 range 27 .. 31; end record; - --------------------- - -- L1CKCR_Register -- - --------------------- - subtype L1CKCR_CKBLUE_Field is STM32F429x.Byte; subtype L1CKCR_CKGREEN_Field is STM32F429x.Byte; subtype L1CKCR_CKRED_Field is STM32F429x.Byte; @@ -501,7 +435,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1CKCR_Register use record CKBLUE at 0 range 0 .. 7; @@ -510,10 +444,6 @@ package STM32F429x.LTDC is Reserved_24_31 at 0 range 24 .. 31; end record; - --------------------- - -- L1PFCR_Register -- - --------------------- - subtype L1PFCR_PF_Field is STM32F429x.UInt3; -- Layerx Pixel Format Configuration Register @@ -523,17 +453,13 @@ package STM32F429x.LTDC is -- unspecified Reserved_3_31 : STM32F429x.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1PFCR_Register use record PF at 0 range 0 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - --------------------- - -- L1CACR_Register -- - --------------------- - subtype L1CACR_CONSTA_Field is STM32F429x.Byte; -- Layerx Constant Alpha Configuration Register @@ -543,17 +469,13 @@ package STM32F429x.LTDC is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1CACR_Register use record CONSTA at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- L1DCCR_Register -- - --------------------- - subtype L1DCCR_DCBLUE_Field is STM32F429x.Byte; subtype L1DCCR_DCGREEN_Field is STM32F429x.Byte; subtype L1DCCR_DCRED_Field is STM32F429x.Byte; @@ -570,7 +492,7 @@ package STM32F429x.LTDC is -- Default Color Alpha DCALPHA : L1DCCR_DCALPHA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1DCCR_Register use record DCBLUE at 0 range 0 .. 7; @@ -579,10 +501,6 @@ package STM32F429x.LTDC is DCALPHA at 0 range 24 .. 31; end record; - --------------------- - -- L1BFCR_Register -- - --------------------- - subtype L1BFCR_BF2_Field is STM32F429x.UInt3; subtype L1BFCR_BF1_Field is STM32F429x.UInt3; @@ -597,7 +515,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1BFCR_Register use record BF2 at 0 range 0 .. 2; @@ -606,10 +524,6 @@ package STM32F429x.LTDC is Reserved_11_31 at 0 range 11 .. 31; end record; - ---------------------- - -- L1CFBLR_Register -- - ---------------------- - subtype L1CFBLR_CFBLL_Field is STM32F429x.UInt13; subtype L1CFBLR_CFBP_Field is STM32F429x.UInt13; @@ -624,7 +538,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_29_31 : STM32F429x.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1CFBLR_Register use record CFBLL at 0 range 0 .. 12; @@ -633,10 +547,6 @@ package STM32F429x.LTDC is Reserved_29_31 at 0 range 29 .. 31; end record; - ----------------------- - -- L1CFBLNR_Register -- - ----------------------- - subtype L1CFBLNR_CFBLNBR_Field is STM32F429x.UInt11; -- Layerx ColorFrame Buffer Line Number Register @@ -646,17 +556,13 @@ package STM32F429x.LTDC is -- unspecified Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1CFBLNR_Register use record CFBLNBR at 0 range 0 .. 10; Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------- - -- L1CLUTWR_Register -- - ----------------------- - subtype L1CLUTWR_BLUE_Field is STM32F429x.Byte; subtype L1CLUTWR_GREEN_Field is STM32F429x.Byte; subtype L1CLUTWR_RED_Field is STM32F429x.Byte; @@ -664,16 +570,16 @@ package STM32F429x.LTDC is -- Layerx CLUT Write Register type L1CLUTWR_Register is record - -- Blue value + -- Write-only. Blue value BLUE : L1CLUTWR_BLUE_Field := 16#0#; - -- Green value + -- Write-only. Green value GREEN : L1CLUTWR_GREEN_Field := 16#0#; - -- Red value + -- Write-only. Red value RED : L1CLUTWR_RED_Field := 16#0#; - -- CLUT Address + -- Write-only. CLUT Address CLUTADD : L1CLUTWR_CLUTADD_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L1CLUTWR_Register use record BLUE at 0 range 0 .. 7; @@ -682,10 +588,6 @@ package STM32F429x.LTDC is CLUTADD at 0 range 24 .. 31; end record; - ------------------- - -- L2CR_Register -- - ------------------- - subtype L2CR_LEN_Field is STM32F429x.Bit; subtype L2CR_COLKEN_Field is STM32F429x.Bit; subtype L2CR_CLUTEN_Field is STM32F429x.Bit; @@ -703,7 +605,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_5_31 : STM32F429x.UInt27 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2CR_Register use record LEN at 0 range 0 .. 0; @@ -713,10 +615,6 @@ package STM32F429x.LTDC is Reserved_5_31 at 0 range 5 .. 31; end record; - ---------------------- - -- L2WHPCR_Register -- - ---------------------- - subtype L2WHPCR_WHSTPOS_Field is STM32F429x.UInt12; subtype L2WHPCR_WHSPPOS_Field is STM32F429x.UInt12; @@ -731,7 +629,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2WHPCR_Register use record WHSTPOS at 0 range 0 .. 11; @@ -740,10 +638,6 @@ package STM32F429x.LTDC is Reserved_28_31 at 0 range 28 .. 31; end record; - ---------------------- - -- L2WVPCR_Register -- - ---------------------- - subtype L2WVPCR_WVSTPOS_Field is STM32F429x.UInt11; subtype L2WVPCR_WVSPPOS_Field is STM32F429x.UInt11; @@ -758,7 +652,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2WVPCR_Register use record WVSTPOS at 0 range 0 .. 10; @@ -767,10 +661,6 @@ package STM32F429x.LTDC is Reserved_27_31 at 0 range 27 .. 31; end record; - --------------------- - -- L2CKCR_Register -- - --------------------- - subtype L2CKCR_CKBLUE_Field is STM32F429x.Byte; subtype L2CKCR_CKGREEN_Field is STM32F429x.UInt7; subtype L2CKCR_CKRED_Field is STM32F429x.UInt9; @@ -786,7 +676,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2CKCR_Register use record CKBLUE at 0 range 0 .. 7; @@ -795,10 +685,6 @@ package STM32F429x.LTDC is Reserved_24_31 at 0 range 24 .. 31; end record; - --------------------- - -- L2PFCR_Register -- - --------------------- - subtype L2PFCR_PF_Field is STM32F429x.UInt3; -- Layerx Pixel Format Configuration Register @@ -808,17 +694,13 @@ package STM32F429x.LTDC is -- unspecified Reserved_3_31 : STM32F429x.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2PFCR_Register use record PF at 0 range 0 .. 2; Reserved_3_31 at 0 range 3 .. 31; end record; - --------------------- - -- L2CACR_Register -- - --------------------- - subtype L2CACR_CONSTA_Field is STM32F429x.Byte; -- Layerx Constant Alpha Configuration Register @@ -828,17 +710,13 @@ package STM32F429x.LTDC is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2CACR_Register use record CONSTA at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- L2DCCR_Register -- - --------------------- - subtype L2DCCR_DCBLUE_Field is STM32F429x.Byte; subtype L2DCCR_DCGREEN_Field is STM32F429x.Byte; subtype L2DCCR_DCRED_Field is STM32F429x.Byte; @@ -855,7 +733,7 @@ package STM32F429x.LTDC is -- Default Color Alpha DCALPHA : L2DCCR_DCALPHA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2DCCR_Register use record DCBLUE at 0 range 0 .. 7; @@ -864,10 +742,6 @@ package STM32F429x.LTDC is DCALPHA at 0 range 24 .. 31; end record; - --------------------- - -- L2BFCR_Register -- - --------------------- - subtype L2BFCR_BF2_Field is STM32F429x.UInt3; subtype L2BFCR_BF1_Field is STM32F429x.UInt3; @@ -882,7 +756,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2BFCR_Register use record BF2 at 0 range 0 .. 2; @@ -891,10 +765,6 @@ package STM32F429x.LTDC is Reserved_11_31 at 0 range 11 .. 31; end record; - ---------------------- - -- L2CFBLR_Register -- - ---------------------- - subtype L2CFBLR_CFBLL_Field is STM32F429x.UInt13; subtype L2CFBLR_CFBP_Field is STM32F429x.UInt13; @@ -909,7 +779,7 @@ package STM32F429x.LTDC is -- unspecified Reserved_29_31 : STM32F429x.UInt3 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2CFBLR_Register use record CFBLL at 0 range 0 .. 12; @@ -918,10 +788,6 @@ package STM32F429x.LTDC is Reserved_29_31 at 0 range 29 .. 31; end record; - ----------------------- - -- L2CFBLNR_Register -- - ----------------------- - subtype L2CFBLNR_CFBLNBR_Field is STM32F429x.UInt11; -- Layerx ColorFrame Buffer Line Number Register @@ -931,17 +797,13 @@ package STM32F429x.LTDC is -- unspecified Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2CFBLNR_Register use record CFBLNBR at 0 range 0 .. 10; Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------- - -- L2CLUTWR_Register -- - ----------------------- - subtype L2CLUTWR_BLUE_Field is STM32F429x.Byte; subtype L2CLUTWR_GREEN_Field is STM32F429x.Byte; subtype L2CLUTWR_RED_Field is STM32F429x.Byte; @@ -949,16 +811,16 @@ package STM32F429x.LTDC is -- Layerx CLUT Write Register type L2CLUTWR_Register is record - -- Blue value + -- Write-only. Blue value BLUE : L2CLUTWR_BLUE_Field := 16#0#; - -- Green value + -- Write-only. Green value GREEN : L2CLUTWR_GREEN_Field := 16#0#; - -- Red value + -- Write-only. Red value RED : L2CLUTWR_RED_Field := 16#0#; - -- CLUT Address + -- Write-only. CLUT Address CLUTADD : L2CLUTWR_CLUTADD_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for L2CLUTWR_Register use record BLUE at 0 range 0 .. 7; @@ -974,124 +836,159 @@ package STM32F429x.LTDC is -- LCD-TFT Controller type LTDC_Peripheral is record -- Synchronization Size Configuration Register - SSCR : SSCR_Register; + SSCR : aliased SSCR_Register; + pragma Volatile_Full_Access (SSCR); -- Back Porch Configuration Register - BPCR : BPCR_Register; + BPCR : aliased BPCR_Register; + pragma Volatile_Full_Access (BPCR); -- Active Width Configuration Register - AWCR : AWCR_Register; + AWCR : aliased AWCR_Register; + pragma Volatile_Full_Access (AWCR); -- Total Width Configuration Register - TWCR : TWCR_Register; + TWCR : aliased TWCR_Register; + pragma Volatile_Full_Access (TWCR); -- Global Control Register - GCR : GCR_Register; + GCR : aliased GCR_Register; + pragma Volatile_Full_Access (GCR); -- Shadow Reload Configuration Register - SRCR : SRCR_Register; + SRCR : aliased SRCR_Register; + pragma Volatile_Full_Access (SRCR); -- Background Color Configuration Register - BCCR : BCCR_Register; + BCCR : aliased BCCR_Register; + pragma Volatile_Full_Access (BCCR); -- Interrupt Enable Register - IER : IER_Register; + IER : aliased IER_Register; + pragma Volatile_Full_Access (IER); -- Interrupt Status Register - ISR : ISR_Register; + ISR : aliased ISR_Register; + pragma Volatile_Full_Access (ISR); -- Interrupt Clear Register - ICR : ICR_Register; + ICR : aliased ICR_Register; + pragma Volatile_Full_Access (ICR); -- Line Interrupt Position Configuration Register - LIPCR : LIPCR_Register; + LIPCR : aliased LIPCR_Register; + pragma Volatile_Full_Access (LIPCR); -- Current Position Status Register - CPSR : CPSR_Register; + CPSR : aliased CPSR_Register; + pragma Volatile_Full_Access (CPSR); -- Current Display Status Register - CDSR : CDSR_Register; + CDSR : aliased CDSR_Register; + pragma Volatile_Full_Access (CDSR); -- Layerx Control Register - L1CR : L1CR_Register; + L1CR : aliased L1CR_Register; + pragma Volatile_Full_Access (L1CR); -- Layerx Window Horizontal Position Configuration Register - L1WHPCR : L1WHPCR_Register; + L1WHPCR : aliased L1WHPCR_Register; + pragma Volatile_Full_Access (L1WHPCR); -- Layerx Window Vertical Position Configuration Register - L1WVPCR : L1WVPCR_Register; + L1WVPCR : aliased L1WVPCR_Register; + pragma Volatile_Full_Access (L1WVPCR); -- Layerx Color Keying Configuration Register - L1CKCR : L1CKCR_Register; + L1CKCR : aliased L1CKCR_Register; + pragma Volatile_Full_Access (L1CKCR); -- Layerx Pixel Format Configuration Register - L1PFCR : L1PFCR_Register; + L1PFCR : aliased L1PFCR_Register; + pragma Volatile_Full_Access (L1PFCR); -- Layerx Constant Alpha Configuration Register - L1CACR : L1CACR_Register; + L1CACR : aliased L1CACR_Register; + pragma Volatile_Full_Access (L1CACR); -- Layerx Default Color Configuration Register - L1DCCR : L1DCCR_Register; + L1DCCR : aliased L1DCCR_Register; + pragma Volatile_Full_Access (L1DCCR); -- Layerx Blending Factors Configuration Register - L1BFCR : L1BFCR_Register; + L1BFCR : aliased L1BFCR_Register; + pragma Volatile_Full_Access (L1BFCR); -- Layerx Color Frame Buffer Address Register - L1CFBAR : STM32F429x.Word; + L1CFBAR : aliased STM32F429x.UInt32; -- Layerx Color Frame Buffer Length Register - L1CFBLR : L1CFBLR_Register; + L1CFBLR : aliased L1CFBLR_Register; + pragma Volatile_Full_Access (L1CFBLR); -- Layerx ColorFrame Buffer Line Number Register - L1CFBLNR : L1CFBLNR_Register; + L1CFBLNR : aliased L1CFBLNR_Register; + pragma Volatile_Full_Access (L1CFBLNR); -- Layerx CLUT Write Register - L1CLUTWR : L1CLUTWR_Register; + L1CLUTWR : aliased L1CLUTWR_Register; + pragma Volatile_Full_Access (L1CLUTWR); -- Layerx Control Register - L2CR : L2CR_Register; + L2CR : aliased L2CR_Register; + pragma Volatile_Full_Access (L2CR); -- Layerx Window Horizontal Position Configuration Register - L2WHPCR : L2WHPCR_Register; + L2WHPCR : aliased L2WHPCR_Register; + pragma Volatile_Full_Access (L2WHPCR); -- Layerx Window Vertical Position Configuration Register - L2WVPCR : L2WVPCR_Register; + L2WVPCR : aliased L2WVPCR_Register; + pragma Volatile_Full_Access (L2WVPCR); -- Layerx Color Keying Configuration Register - L2CKCR : L2CKCR_Register; + L2CKCR : aliased L2CKCR_Register; + pragma Volatile_Full_Access (L2CKCR); -- Layerx Pixel Format Configuration Register - L2PFCR : L2PFCR_Register; + L2PFCR : aliased L2PFCR_Register; + pragma Volatile_Full_Access (L2PFCR); -- Layerx Constant Alpha Configuration Register - L2CACR : L2CACR_Register; + L2CACR : aliased L2CACR_Register; + pragma Volatile_Full_Access (L2CACR); -- Layerx Default Color Configuration Register - L2DCCR : L2DCCR_Register; + L2DCCR : aliased L2DCCR_Register; + pragma Volatile_Full_Access (L2DCCR); -- Layerx Blending Factors Configuration Register - L2BFCR : L2BFCR_Register; + L2BFCR : aliased L2BFCR_Register; + pragma Volatile_Full_Access (L2BFCR); -- Layerx Color Frame Buffer Address Register - L2CFBAR : STM32F429x.Word; + L2CFBAR : aliased STM32F429x.UInt32; -- Layerx Color Frame Buffer Length Register - L2CFBLR : L2CFBLR_Register; + L2CFBLR : aliased L2CFBLR_Register; + pragma Volatile_Full_Access (L2CFBLR); -- Layerx ColorFrame Buffer Line Number Register - L2CFBLNR : L2CFBLNR_Register; + L2CFBLNR : aliased L2CFBLNR_Register; + pragma Volatile_Full_Access (L2CFBLNR); -- Layerx CLUT Write Register - L2CLUTWR : L2CLUTWR_Register; + L2CLUTWR : aliased L2CLUTWR_Register; + pragma Volatile_Full_Access (L2CLUTWR); end record with Volatile; for LTDC_Peripheral use record - SSCR at 8 range 0 .. 31; - BPCR at 12 range 0 .. 31; - AWCR at 16 range 0 .. 31; - TWCR at 20 range 0 .. 31; - GCR at 24 range 0 .. 31; - SRCR at 36 range 0 .. 31; - BCCR at 44 range 0 .. 31; - IER at 52 range 0 .. 31; - ISR at 56 range 0 .. 31; - ICR at 60 range 0 .. 31; - LIPCR at 64 range 0 .. 31; - CPSR at 68 range 0 .. 31; - CDSR at 72 range 0 .. 31; - L1CR at 132 range 0 .. 31; - L1WHPCR at 136 range 0 .. 31; - L1WVPCR at 140 range 0 .. 31; - L1CKCR at 144 range 0 .. 31; - L1PFCR at 148 range 0 .. 31; - L1CACR at 152 range 0 .. 31; - L1DCCR at 156 range 0 .. 31; - L1BFCR at 160 range 0 .. 31; - L1CFBAR at 172 range 0 .. 31; - L1CFBLR at 176 range 0 .. 31; - L1CFBLNR at 180 range 0 .. 31; - L1CLUTWR at 196 range 0 .. 31; - L2CR at 260 range 0 .. 31; - L2WHPCR at 264 range 0 .. 31; - L2WVPCR at 268 range 0 .. 31; - L2CKCR at 272 range 0 .. 31; - L2PFCR at 276 range 0 .. 31; - L2CACR at 280 range 0 .. 31; - L2DCCR at 284 range 0 .. 31; - L2BFCR at 288 range 0 .. 31; - L2CFBAR at 300 range 0 .. 31; - L2CFBLR at 304 range 0 .. 31; - L2CFBLNR at 308 range 0 .. 31; - L2CLUTWR at 324 range 0 .. 31; + SSCR at 16#8# range 0 .. 31; + BPCR at 16#C# range 0 .. 31; + AWCR at 16#10# range 0 .. 31; + TWCR at 16#14# range 0 .. 31; + GCR at 16#18# range 0 .. 31; + SRCR at 16#24# range 0 .. 31; + BCCR at 16#2C# range 0 .. 31; + IER at 16#34# range 0 .. 31; + ISR at 16#38# range 0 .. 31; + ICR at 16#3C# range 0 .. 31; + LIPCR at 16#40# range 0 .. 31; + CPSR at 16#44# range 0 .. 31; + CDSR at 16#48# range 0 .. 31; + L1CR at 16#84# range 0 .. 31; + L1WHPCR at 16#88# range 0 .. 31; + L1WVPCR at 16#8C# range 0 .. 31; + L1CKCR at 16#90# range 0 .. 31; + L1PFCR at 16#94# range 0 .. 31; + L1CACR at 16#98# range 0 .. 31; + L1DCCR at 16#9C# range 0 .. 31; + L1BFCR at 16#A0# range 0 .. 31; + L1CFBAR at 16#AC# range 0 .. 31; + L1CFBLR at 16#B0# range 0 .. 31; + L1CFBLNR at 16#B4# range 0 .. 31; + L1CLUTWR at 16#C4# range 0 .. 31; + L2CR at 16#104# range 0 .. 31; + L2WHPCR at 16#108# range 0 .. 31; + L2WVPCR at 16#10C# range 0 .. 31; + L2CKCR at 16#110# range 0 .. 31; + L2PFCR at 16#114# range 0 .. 31; + L2CACR at 16#118# range 0 .. 31; + L2DCCR at 16#11C# range 0 .. 31; + L2BFCR at 16#120# range 0 .. 31; + L2CFBAR at 16#12C# range 0 .. 31; + L2CFBLR at 16#130# range 0 .. 31; + L2CFBLNR at 16#134# range 0 .. 31; + L2CLUTWR at 16#144# range 0 .. 31; end record; -- LCD-TFT Controller LTDC_Periph : aliased LTDC_Peripheral - with Import, Address => System'To_Address (16#40016800#); + with Import, Address => LTDC_Base; end STM32F429x.LTDC; diff --git a/stm32f429i/stm32f429x/stm32f429x-nvic.ads b/stm32f429i/stm32f429x/stm32f429x-nvic.ads index a1165d5..617bf06 100644 --- a/stm32f429i/stm32f429x/stm32f429x-nvic.ads +++ b/stm32f429i/stm32f429x/stm32f429x-nvic.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,35 +14,27 @@ package STM32F429x.NVIC is -- Registers -- --------------- - ------------------- - -- ICTR_Register -- - ------------------- - subtype ICTR_INTLINESNUM_Field is STM32F429x.UInt4; -- Interrupt Controller Type Register type ICTR_Register is record - -- Total number of interrupt lines in groups + -- Read-only. Total number of interrupt lines in groups INTLINESNUM : ICTR_INTLINESNUM_Field; -- unspecified Reserved_4_31 : STM32F429x.UInt28; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ICTR_Register use record INTLINESNUM at 0 range 0 .. 3; Reserved_4_31 at 0 range 4 .. 31; end record; - ------------------ - -- IPR_Register -- - ------------------ + -- IPR_IPR_N array element + subtype IPR_IPR_N_Element is STM32F429x.Byte; - -- IPR0_IPR_N array element - subtype IPR0_IPR_N_Element is STM32F429x.Byte; - - -- IPR0_IPR_N array - type IPR0_IPR_N_Field_Array is array (0 .. 3) of IPR0_IPR_N_Element + -- IPR_IPR_N array + type IPR_IPR_N_Field_Array is array (0 .. 3) of IPR_IPR_N_Element with Component_Size => 8, Size => 32; -- Interrupt Priority Register @@ -50,13 +44,13 @@ package STM32F429x.NVIC is case As_Array is when False => -- IPR_N as a value - Val : STM32F429x.Word; + Val : STM32F429x.UInt32; when True => -- IPR_N as an array - Arr : IPR0_IPR_N_Field_Array; + Arr : IPR_IPR_N_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile, + with Unchecked_Union, Size => 32, Object_Size => 32, Bit_Order => System.Low_Order_First; for IPR_Register use record @@ -64,20 +58,16 @@ package STM32F429x.NVIC is Arr at 0 range 0 .. 31; end record; - ------------------- - -- STIR_Register -- - ------------------- - subtype STIR_INTID_Field is STM32F429x.UInt9; -- Software Triggered Interrupt Register type STIR_Register is record - -- interrupt to be triggered + -- Write-only. interrupt to be triggered INTID : STIR_INTID_Field := 16#0#; -- unspecified Reserved_9_31 : STM32F429x.UInt23 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for STIR_Register use record INTID at 0 range 0 .. 8; @@ -91,127 +81,150 @@ package STM32F429x.NVIC is -- Nested Vectored Interrupt Controller type NVIC_Peripheral is record -- Interrupt Controller Type Register - ICTR : ICTR_Register; + ICTR : aliased ICTR_Register; + pragma Volatile_Full_Access (ICTR); -- Interrupt Set-Enable Register - ISER0 : STM32F429x.Word; + ISER0 : aliased STM32F429x.UInt32; -- Interrupt Set-Enable Register - ISER1 : STM32F429x.Word; + ISER1 : aliased STM32F429x.UInt32; -- Interrupt Set-Enable Register - ISER2 : STM32F429x.Word; + ISER2 : aliased STM32F429x.UInt32; -- Interrupt Clear-Enable Register - ICER0 : STM32F429x.Word; + ICER0 : aliased STM32F429x.UInt32; -- Interrupt Clear-Enable Register - ICER1 : STM32F429x.Word; + ICER1 : aliased STM32F429x.UInt32; -- Interrupt Clear-Enable Register - ICER2 : STM32F429x.Word; + ICER2 : aliased STM32F429x.UInt32; -- Interrupt Set-Pending Register - ISPR0 : STM32F429x.Word; + ISPR0 : aliased STM32F429x.UInt32; -- Interrupt Set-Pending Register - ISPR1 : STM32F429x.Word; + ISPR1 : aliased STM32F429x.UInt32; -- Interrupt Set-Pending Register - ISPR2 : STM32F429x.Word; + ISPR2 : aliased STM32F429x.UInt32; -- Interrupt Clear-Pending Register - ICPR0 : STM32F429x.Word; + ICPR0 : aliased STM32F429x.UInt32; -- Interrupt Clear-Pending Register - ICPR1 : STM32F429x.Word; + ICPR1 : aliased STM32F429x.UInt32; -- Interrupt Clear-Pending Register - ICPR2 : STM32F429x.Word; + ICPR2 : aliased STM32F429x.UInt32; -- Interrupt Active Bit Register - IABR0 : STM32F429x.Word; + IABR0 : aliased STM32F429x.UInt32; -- Interrupt Active Bit Register - IABR1 : STM32F429x.Word; + IABR1 : aliased STM32F429x.UInt32; -- Interrupt Active Bit Register - IABR2 : STM32F429x.Word; + IABR2 : aliased STM32F429x.UInt32; -- Interrupt Priority Register - IPR0 : IPR_Register; + IPR0 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR0); -- Interrupt Priority Register - IPR1 : IPR_Register; + IPR1 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR1); -- Interrupt Priority Register - IPR2 : IPR_Register; + IPR2 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR2); -- Interrupt Priority Register - IPR3 : IPR_Register; + IPR3 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR3); -- Interrupt Priority Register - IPR4 : IPR_Register; + IPR4 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR4); -- Interrupt Priority Register - IPR5 : IPR_Register; + IPR5 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR5); -- Interrupt Priority Register - IPR6 : IPR_Register; + IPR6 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR6); -- Interrupt Priority Register - IPR7 : IPR_Register; + IPR7 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR7); -- Interrupt Priority Register - IPR8 : IPR_Register; + IPR8 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR8); -- Interrupt Priority Register - IPR9 : IPR_Register; + IPR9 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR9); -- Interrupt Priority Register - IPR10 : IPR_Register; + IPR10 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR10); -- Interrupt Priority Register - IPR11 : IPR_Register; + IPR11 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR11); -- Interrupt Priority Register - IPR12 : IPR_Register; + IPR12 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR12); -- Interrupt Priority Register - IPR13 : IPR_Register; + IPR13 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR13); -- Interrupt Priority Register - IPR14 : IPR_Register; + IPR14 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR14); -- Interrupt Priority Register - IPR15 : IPR_Register; + IPR15 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR15); -- Interrupt Priority Register - IPR16 : IPR_Register; + IPR16 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR16); -- Interrupt Priority Register - IPR17 : IPR_Register; + IPR17 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR17); -- Interrupt Priority Register - IPR18 : IPR_Register; + IPR18 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR18); -- Interrupt Priority Register - IPR19 : IPR_Register; + IPR19 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR19); -- Interrupt Priority Register - IPR20 : IPR_Register; + IPR20 : aliased IPR_Register; + pragma Volatile_Full_Access (IPR20); -- Software Triggered Interrupt Register - STIR : STIR_Register; + STIR : aliased STIR_Register; + pragma Volatile_Full_Access (STIR); end record with Volatile; for NVIC_Peripheral use record - ICTR at 4 range 0 .. 31; - ISER0 at 256 range 0 .. 31; - ISER1 at 260 range 0 .. 31; - ISER2 at 264 range 0 .. 31; - ICER0 at 384 range 0 .. 31; - ICER1 at 388 range 0 .. 31; - ICER2 at 392 range 0 .. 31; - ISPR0 at 512 range 0 .. 31; - ISPR1 at 516 range 0 .. 31; - ISPR2 at 520 range 0 .. 31; - ICPR0 at 640 range 0 .. 31; - ICPR1 at 644 range 0 .. 31; - ICPR2 at 648 range 0 .. 31; - IABR0 at 768 range 0 .. 31; - IABR1 at 772 range 0 .. 31; - IABR2 at 776 range 0 .. 31; - IPR0 at 1024 range 0 .. 31; - IPR1 at 1028 range 0 .. 31; - IPR2 at 1032 range 0 .. 31; - IPR3 at 1036 range 0 .. 31; - IPR4 at 1040 range 0 .. 31; - IPR5 at 1044 range 0 .. 31; - IPR6 at 1048 range 0 .. 31; - IPR7 at 1052 range 0 .. 31; - IPR8 at 1056 range 0 .. 31; - IPR9 at 1060 range 0 .. 31; - IPR10 at 1064 range 0 .. 31; - IPR11 at 1068 range 0 .. 31; - IPR12 at 1072 range 0 .. 31; - IPR13 at 1076 range 0 .. 31; - IPR14 at 1080 range 0 .. 31; - IPR15 at 1084 range 0 .. 31; - IPR16 at 1088 range 0 .. 31; - IPR17 at 1092 range 0 .. 31; - IPR18 at 1096 range 0 .. 31; - IPR19 at 1100 range 0 .. 31; - IPR20 at 1104 range 0 .. 31; - STIR at 3840 range 0 .. 31; + ICTR at 16#4# range 0 .. 31; + ISER0 at 16#100# range 0 .. 31; + ISER1 at 16#104# range 0 .. 31; + ISER2 at 16#108# range 0 .. 31; + ICER0 at 16#180# range 0 .. 31; + ICER1 at 16#184# range 0 .. 31; + ICER2 at 16#188# range 0 .. 31; + ISPR0 at 16#200# range 0 .. 31; + ISPR1 at 16#204# range 0 .. 31; + ISPR2 at 16#208# range 0 .. 31; + ICPR0 at 16#280# range 0 .. 31; + ICPR1 at 16#284# range 0 .. 31; + ICPR2 at 16#288# range 0 .. 31; + IABR0 at 16#300# range 0 .. 31; + IABR1 at 16#304# range 0 .. 31; + IABR2 at 16#308# range 0 .. 31; + IPR0 at 16#400# range 0 .. 31; + IPR1 at 16#404# range 0 .. 31; + IPR2 at 16#408# range 0 .. 31; + IPR3 at 16#40C# range 0 .. 31; + IPR4 at 16#410# range 0 .. 31; + IPR5 at 16#414# range 0 .. 31; + IPR6 at 16#418# range 0 .. 31; + IPR7 at 16#41C# range 0 .. 31; + IPR8 at 16#420# range 0 .. 31; + IPR9 at 16#424# range 0 .. 31; + IPR10 at 16#428# range 0 .. 31; + IPR11 at 16#42C# range 0 .. 31; + IPR12 at 16#430# range 0 .. 31; + IPR13 at 16#434# range 0 .. 31; + IPR14 at 16#438# range 0 .. 31; + IPR15 at 16#43C# range 0 .. 31; + IPR16 at 16#440# range 0 .. 31; + IPR17 at 16#444# range 0 .. 31; + IPR18 at 16#448# range 0 .. 31; + IPR19 at 16#44C# range 0 .. 31; + IPR20 at 16#450# range 0 .. 31; + STIR at 16#F00# range 0 .. 31; end record; -- Nested Vectored Interrupt Controller NVIC_Periph : aliased NVIC_Peripheral - with Import, Address => System'To_Address (16#E000E000#); + with Import, Address => NVIC_Base; end STM32F429x.NVIC; diff --git a/stm32f429i/stm32f429x/stm32f429x-pwr.ads b/stm32f429i/stm32f429x/stm32f429x-pwr.ads index 928aa38..f3a6604 100644 --- a/stm32f429i/stm32f429x/stm32f429x-pwr.ads +++ b/stm32f429i/stm32f429x/stm32f429x-pwr.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.PWR is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_LPDS_Field is STM32F429x.Bit; subtype CR_PDDS_Field is STM32F429x.Bit; subtype CR_CWUF_Field is STM32F429x.Bit; @@ -24,8 +22,13 @@ package STM32F429x.PWR is subtype CR_PLS_Field is STM32F429x.UInt3; subtype CR_DBP_Field is STM32F429x.Bit; subtype CR_FPDS_Field is STM32F429x.Bit; + subtype CR_LPLVDS_Field is STM32F429x.Bit; + subtype CR_MRLVDS_Field is STM32F429x.Bit; subtype CR_ADCDC1_Field is STM32F429x.Bit; subtype CR_VOS_Field is STM32F429x.UInt2; + subtype CR_ODEN_Field is STM32F429x.Bit; + subtype CR_ODSWEN_Field is STM32F429x.Bit; + subtype CR_UDEN_Field is STM32F429x.UInt2; -- power control register type CR_Register is record @@ -45,16 +48,26 @@ package STM32F429x.PWR is DBP : CR_DBP_Field := 16#0#; -- Flash power down in Stop mode FPDS : CR_FPDS_Field := 16#0#; + -- Low-Power Regulator Low Voltage in deepsleep + LPLVDS : CR_LPLVDS_Field := 16#0#; + -- Main regulator low voltage in deepsleep mode + MRLVDS : CR_MRLVDS_Field := 16#0#; -- unspecified - Reserved_10_12 : STM32F429x.UInt3 := 16#0#; + Reserved_12_12 : STM32F429x.Bit := 16#0#; -- ADCDC1 ADCDC1 : CR_ADCDC1_Field := 16#0#; -- Regulator voltage scaling output selection VOS : CR_VOS_Field := 16#3#; + -- Over-drive enable + ODEN : CR_ODEN_Field := 16#0#; + -- Over-drive switching enabled + ODSWEN : CR_ODSWEN_Field := 16#0#; + -- Under-drive enable in stop mode + UDEN : CR_UDEN_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_20_31 : STM32F429x.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record LPDS at 0 range 0 .. 0; @@ -65,16 +78,17 @@ package STM32F429x.PWR is PLS at 0 range 5 .. 7; DBP at 0 range 8 .. 8; FPDS at 0 range 9 .. 9; - Reserved_10_12 at 0 range 10 .. 12; + LPLVDS at 0 range 10 .. 10; + MRLVDS at 0 range 11 .. 11; + Reserved_12_12 at 0 range 12 .. 12; ADCDC1 at 0 range 13 .. 13; VOS at 0 range 14 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + ODEN at 0 range 16 .. 16; + ODSWEN at 0 range 17 .. 17; + UDEN at 0 range 18 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - ------------------ - -- CSR_Register -- - ------------------ - subtype CSR_WUF_Field is STM32F429x.Bit; subtype CSR_SBF_Field is STM32F429x.Bit; subtype CSR_PVDO_Field is STM32F429x.Bit; @@ -82,16 +96,19 @@ package STM32F429x.PWR is subtype CSR_EWUP_Field is STM32F429x.Bit; subtype CSR_BRE_Field is STM32F429x.Bit; subtype CSR_VOSRDY_Field is STM32F429x.Bit; + subtype CSR_ODRDY_Field is STM32F429x.Bit; + subtype CSR_ODSWRDY_Field is STM32F429x.Bit; + subtype CSR_UDRDY_Field is STM32F429x.UInt2; -- power control/status register type CSR_Register is record - -- Wakeup flag + -- Read-only. Wakeup flag WUF : CSR_WUF_Field := 16#0#; - -- Standby flag + -- Read-only. Standby flag SBF : CSR_SBF_Field := 16#0#; - -- PVD output + -- Read-only. PVD output PVDO : CSR_PVDO_Field := 16#0#; - -- Backup regulator ready + -- Read-only. Backup regulator ready BRR : CSR_BRR_Field := 16#0#; -- unspecified Reserved_4_7 : STM32F429x.UInt4 := 16#0#; @@ -104,9 +121,17 @@ package STM32F429x.PWR is -- Regulator voltage scaling output selection ready bit VOSRDY : CSR_VOSRDY_Field := 16#0#; -- unspecified - Reserved_15_31 : STM32F429x.UInt17 := 16#0#; + Reserved_15_15 : STM32F429x.Bit := 16#0#; + -- Read-only. Over-drive mode ready + ODRDY : CSR_ODRDY_Field := 16#0#; + -- Read-only. Over-drive mode switching ready + ODSWRDY : CSR_ODSWRDY_Field := 16#0#; + -- Under-drive ready flag + UDRDY : CSR_UDRDY_Field := 16#0#; + -- unspecified + Reserved_20_31 : STM32F429x.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CSR_Register use record WUF at 0 range 0 .. 0; @@ -118,7 +143,11 @@ package STM32F429x.PWR is BRE at 0 range 9 .. 9; Reserved_10_13 at 0 range 10 .. 13; VOSRDY at 0 range 14 .. 14; - Reserved_15_31 at 0 range 15 .. 31; + Reserved_15_15 at 0 range 15 .. 15; + ODRDY at 0 range 16 .. 16; + ODSWRDY at 0 range 17 .. 17; + UDRDY at 0 range 18 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; ----------------- @@ -128,19 +157,21 @@ package STM32F429x.PWR is -- Power control type PWR_Peripheral is record -- power control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- power control/status register - CSR : CSR_Register; + CSR : aliased CSR_Register; + pragma Volatile_Full_Access (CSR); end record with Volatile; for PWR_Peripheral use record - CR at 0 range 0 .. 31; - CSR at 4 range 0 .. 31; + CR at 16#0# range 0 .. 31; + CSR at 16#4# range 0 .. 31; end record; -- Power control PWR_Periph : aliased PWR_Peripheral - with Import, Address => System'To_Address (16#40007000#); + with Import, Address => PWR_Base; end STM32F429x.PWR; diff --git a/stm32f429i/stm32f429x/stm32f429x-rcc.ads b/stm32f429i/stm32f429x/stm32f429x-rcc.ads index 7673362..738f250 100644 --- a/stm32f429i/stm32f429x/stm32f429x-rcc.ads +++ b/stm32f429i/stm32f429x/stm32f429x-rcc.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.RCC is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_HSION_Field is STM32F429x.Bit; subtype CR_HSIRDY_Field is STM32F429x.Bit; subtype CR_HSITRIM_Field is STM32F429x.UInt5; @@ -33,17 +31,17 @@ package STM32F429x.RCC is type CR_Register is record -- Internal high-speed clock enable HSION : CR_HSION_Field := 16#1#; - -- Internal high-speed clock ready flag + -- Read-only. Internal high-speed clock ready flag HSIRDY : CR_HSIRDY_Field := 16#1#; -- unspecified Reserved_2_2 : STM32F429x.Bit := 16#0#; -- Internal high-speed clock trimming HSITRIM : CR_HSITRIM_Field := 16#10#; - -- Internal high-speed clock calibration + -- Read-only. Internal high-speed clock calibration HSICAL : CR_HSICAL_Field := 16#0#; -- HSE clock enable HSEON : CR_HSEON_Field := 16#0#; - -- HSE clock ready flag + -- Read-only. HSE clock ready flag HSERDY : CR_HSERDY_Field := 16#0#; -- HSE clock bypass HSEBYP : CR_HSEBYP_Field := 16#0#; @@ -53,16 +51,16 @@ package STM32F429x.RCC is Reserved_20_23 : STM32F429x.UInt4 := 16#0#; -- Main PLL (PLL) enable PLLON : CR_PLLON_Field := 16#0#; - -- Main PLL (PLL) clock ready flag + -- Read-only. Main PLL (PLL) clock ready flag PLLRDY : CR_PLLRDY_Field := 16#0#; -- PLLI2S enable PLLI2SON : CR_PLLI2SON_Field := 16#0#; - -- PLLI2S clock ready flag + -- Read-only. PLLI2S clock ready flag PLLI2SRDY : CR_PLLI2SRDY_Field := 16#0#; -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record HSION at 0 range 0 .. 0; @@ -82,10 +80,6 @@ package STM32F429x.RCC is Reserved_28_31 at 0 range 28 .. 31; end record; - ---------------------- - -- PLLCFGR_Register -- - ---------------------- - subtype PLLCFGR_PLLM_Field is STM32F429x.UInt6; subtype PLLCFGR_PLLN_Field is STM32F429x.UInt9; subtype PLLCFGR_PLLP_Field is STM32F429x.UInt2; @@ -115,7 +109,7 @@ package STM32F429x.RCC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#2#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PLLCFGR_Register use record PLLM at 0 range 0 .. 5; @@ -129,23 +123,14 @@ package STM32F429x.RCC is Reserved_28_31 at 0 range 28 .. 31; end record; - ------------------- - -- CFGR_Register -- - ------------------- - subtype CFGR_SW_Field is STM32F429x.UInt2; subtype CFGR_SWS_Field is STM32F429x.UInt2; subtype CFGR_HPRE_Field is STM32F429x.UInt4; - - --------------- - -- CFGR.PPRE -- - --------------- - -- CFGR_PPRE array element subtype CFGR_PPRE_Element is STM32F429x.UInt3; -- CFGR_PPRE array - type CFGR_PPRE_Field_Array is array (0 .. 1) of CFGR_PPRE_Element + type CFGR_PPRE_Field_Array is array (1 .. 2) of CFGR_PPRE_Element with Component_Size => 3, Size => 6; -- Type definition for CFGR_PPRE @@ -179,7 +164,7 @@ package STM32F429x.RCC is type CFGR_Register is record -- System clock switch SW : CFGR_SW_Field := 16#0#; - -- System clock switch status + -- Read-only. System clock switch status SWS : CFGR_SWS_Field := 16#0#; -- AHB prescaler HPRE : CFGR_HPRE_Field := 16#0#; @@ -200,7 +185,7 @@ package STM32F429x.RCC is -- Microcontroller clock output 2 MCO2 : CFGR_MCO2_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CFGR_Register use record SW at 0 range 0 .. 1; @@ -216,10 +201,6 @@ package STM32F429x.RCC is MCO2 at 0 range 30 .. 31; end record; - ------------------ - -- CIR_Register -- - ------------------ - subtype CIR_LSIRDYF_Field is STM32F429x.Bit; subtype CIR_LSERDYF_Field is STM32F429x.Bit; subtype CIR_HSIRDYF_Field is STM32F429x.Bit; @@ -246,21 +227,21 @@ package STM32F429x.RCC is -- clock interrupt register type CIR_Register is record - -- LSI ready interrupt flag + -- Read-only. LSI ready interrupt flag LSIRDYF : CIR_LSIRDYF_Field := 16#0#; - -- LSE ready interrupt flag + -- Read-only. LSE ready interrupt flag LSERDYF : CIR_LSERDYF_Field := 16#0#; - -- HSI ready interrupt flag + -- Read-only. HSI ready interrupt flag HSIRDYF : CIR_HSIRDYF_Field := 16#0#; - -- HSE ready interrupt flag + -- Read-only. HSE ready interrupt flag HSERDYF : CIR_HSERDYF_Field := 16#0#; - -- Main PLL (PLL) ready interrupt flag + -- Read-only. Main PLL (PLL) ready interrupt flag PLLRDYF : CIR_PLLRDYF_Field := 16#0#; - -- PLLI2S ready interrupt flag + -- Read-only. PLLI2S ready interrupt flag PLLI2SRDYF : CIR_PLLI2SRDYF_Field := 16#0#; - -- PLLSAI ready interrupt flag + -- Read-only. PLLSAI ready interrupt flag PLLSAIRDYF : CIR_PLLSAIRDYF_Field := 16#0#; - -- Clock security system interrupt flag + -- Read-only. Clock security system interrupt flag CSSF : CIR_CSSF_Field := 16#0#; -- LSI ready interrupt enable LSIRDYIE : CIR_LSIRDYIE_Field := 16#0#; @@ -278,26 +259,26 @@ package STM32F429x.RCC is PLLSAIRDYIE : CIR_PLLSAIRDYIE_Field := 16#0#; -- unspecified Reserved_15_15 : STM32F429x.Bit := 16#0#; - -- LSI ready interrupt clear + -- Write-only. LSI ready interrupt clear LSIRDYC : CIR_LSIRDYC_Field := 16#0#; - -- LSE ready interrupt clear + -- Write-only. LSE ready interrupt clear LSERDYC : CIR_LSERDYC_Field := 16#0#; - -- HSI ready interrupt clear + -- Write-only. HSI ready interrupt clear HSIRDYC : CIR_HSIRDYC_Field := 16#0#; - -- HSE ready interrupt clear + -- Write-only. HSE ready interrupt clear HSERDYC : CIR_HSERDYC_Field := 16#0#; - -- Main PLL(PLL) ready interrupt clear + -- Write-only. Main PLL(PLL) ready interrupt clear PLLRDYC : CIR_PLLRDYC_Field := 16#0#; - -- PLLI2S ready interrupt clear + -- Write-only. PLLI2S ready interrupt clear PLLI2SRDYC : CIR_PLLI2SRDYC_Field := 16#0#; - -- PLLSAI Ready Interrupt Clear + -- Write-only. PLLSAI Ready Interrupt Clear PLLSAIRDYC : CIR_PLLSAIRDYC_Field := 16#0#; - -- Clock security system interrupt clear + -- Write-only. Clock security system interrupt clear CSSC : CIR_CSSC_Field := 16#0#; -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CIR_Register use record LSIRDYF at 0 range 0 .. 0; @@ -327,10 +308,6 @@ package STM32F429x.RCC is Reserved_24_31 at 0 range 24 .. 31; end record; - ----------------------- - -- AHB1RSTR_Register -- - ----------------------- - subtype AHB1RSTR_GPIOARST_Field is STM32F429x.Bit; subtype AHB1RSTR_GPIOBRST_Field is STM32F429x.Bit; subtype AHB1RSTR_GPIOCRST_Field is STM32F429x.Bit; @@ -396,7 +373,7 @@ package STM32F429x.RCC is -- unspecified Reserved_30_31 : STM32F429x.UInt2 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB1RSTR_Register use record GPIOARST at 0 range 0 .. 0; @@ -423,10 +400,6 @@ package STM32F429x.RCC is Reserved_30_31 at 0 range 30 .. 31; end record; - ----------------------- - -- AHB2RSTR_Register -- - ----------------------- - subtype AHB2RSTR_DCMIRST_Field is STM32F429x.Bit; subtype AHB2RSTR_RNGRST_Field is STM32F429x.Bit; subtype AHB2RSTR_OTGFSRST_Field is STM32F429x.Bit; @@ -444,7 +417,7 @@ package STM32F429x.RCC is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB2RSTR_Register use record DCMIRST at 0 range 0 .. 0; @@ -454,10 +427,6 @@ package STM32F429x.RCC is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------------- - -- AHB3RSTR_Register -- - ----------------------- - subtype AHB3RSTR_FMCRST_Field is STM32F429x.Bit; -- AHB3 peripheral reset register @@ -467,17 +436,13 @@ package STM32F429x.RCC is -- unspecified Reserved_1_31 : STM32F429x.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB3RSTR_Register use record FMCRST at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ----------------------- - -- APB1RSTR_Register -- - ----------------------- - subtype APB1RSTR_TIM2RST_Field is STM32F429x.Bit; subtype APB1RSTR_TIM3RST_Field is STM32F429x.Bit; subtype APB1RSTR_TIM4RST_Field is STM32F429x.Bit; @@ -567,7 +532,7 @@ package STM32F429x.RCC is -- UART8 reset UART8RST : APB1RSTR_UART8RST_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB1RSTR_Register use record TIM2RST at 0 range 0 .. 0; @@ -602,10 +567,6 @@ package STM32F429x.RCC is UART8RST at 0 range 31 .. 31; end record; - ----------------------- - -- APB2RSTR_Register -- - ----------------------- - subtype APB2RSTR_TIM1RST_Field is STM32F429x.Bit; subtype APB2RSTR_TIM8RST_Field is STM32F429x.Bit; subtype APB2RSTR_USART1RST_Field is STM32F429x.Bit; @@ -672,7 +633,7 @@ package STM32F429x.RCC is -- unspecified Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB2RSTR_Register use record TIM1RST at 0 range 0 .. 0; @@ -700,10 +661,6 @@ package STM32F429x.RCC is Reserved_27_31 at 0 range 27 .. 31; end record; - ---------------------- - -- AHB1ENR_Register -- - ---------------------- - subtype AHB1ENR_GPIOAEN_Field is STM32F429x.Bit; subtype AHB1ENR_GPIOBEN_Field is STM32F429x.Bit; subtype AHB1ENR_GPIOCEN_Field is STM32F429x.Bit; @@ -787,7 +744,7 @@ package STM32F429x.RCC is -- unspecified Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB1ENR_Register use record GPIOAEN at 0 range 0 .. 0; @@ -820,10 +777,6 @@ package STM32F429x.RCC is Reserved_31_31 at 0 range 31 .. 31; end record; - ---------------------- - -- AHB2ENR_Register -- - ---------------------- - subtype AHB2ENR_DCMIEN_Field is STM32F429x.Bit; subtype AHB2ENR_RNGEN_Field is STM32F429x.Bit; subtype AHB2ENR_OTGFSEN_Field is STM32F429x.Bit; @@ -841,7 +794,7 @@ package STM32F429x.RCC is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB2ENR_Register use record DCMIEN at 0 range 0 .. 0; @@ -851,10 +804,6 @@ package STM32F429x.RCC is Reserved_8_31 at 0 range 8 .. 31; end record; - ---------------------- - -- AHB3ENR_Register -- - ---------------------- - subtype AHB3ENR_FMCEN_Field is STM32F429x.Bit; -- AHB3 peripheral clock enable register @@ -864,17 +813,13 @@ package STM32F429x.RCC is -- unspecified Reserved_1_31 : STM32F429x.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB3ENR_Register use record FMCEN at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ---------------------- - -- APB1ENR_Register -- - ---------------------- - subtype APB1ENR_TIM2EN_Field is STM32F429x.Bit; subtype APB1ENR_TIM3EN_Field is STM32F429x.Bit; subtype APB1ENR_TIM4EN_Field is STM32F429x.Bit; @@ -964,7 +909,7 @@ package STM32F429x.RCC is -- UART8 clock enable UART8ENR : APB1ENR_UART8ENR_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB1ENR_Register use record TIM2EN at 0 range 0 .. 0; @@ -999,10 +944,6 @@ package STM32F429x.RCC is UART8ENR at 0 range 31 .. 31; end record; - ---------------------- - -- APB2ENR_Register -- - ---------------------- - subtype APB2ENR_TIM1EN_Field is STM32F429x.Bit; subtype APB2ENR_TIM8EN_Field is STM32F429x.Bit; subtype APB2ENR_USART1EN_Field is STM32F429x.Bit; @@ -1073,7 +1014,7 @@ package STM32F429x.RCC is -- unspecified Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB2ENR_Register use record TIM1EN at 0 range 0 .. 0; @@ -1102,10 +1043,6 @@ package STM32F429x.RCC is Reserved_27_31 at 0 range 27 .. 31; end record; - ------------------------ - -- AHB1LPENR_Register -- - ------------------------ - subtype AHB1LPENR_GPIOALPEN_Field is STM32F429x.Bit; subtype AHB1LPENR_GPIOBLPEN_Field is STM32F429x.Bit; subtype AHB1LPENR_GPIOCLPEN_Field is STM32F429x.Bit; @@ -1198,7 +1135,7 @@ package STM32F429x.RCC is -- unspecified Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB1LPENR_Register use record GPIOALPEN at 0 range 0 .. 0; @@ -1234,10 +1171,6 @@ package STM32F429x.RCC is Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------ - -- AHB2LPENR_Register -- - ------------------------ - subtype AHB2LPENR_DCMILPEN_Field is STM32F429x.Bit; subtype AHB2LPENR_RNGLPEN_Field is STM32F429x.Bit; subtype AHB2LPENR_OTGFSLPEN_Field is STM32F429x.Bit; @@ -1255,7 +1188,7 @@ package STM32F429x.RCC is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB2LPENR_Register use record DCMILPEN at 0 range 0 .. 0; @@ -1265,10 +1198,6 @@ package STM32F429x.RCC is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------------ - -- AHB3LPENR_Register -- - ------------------------ - subtype AHB3LPENR_FMCLPEN_Field is STM32F429x.Bit; -- AHB3 peripheral clock enable in low power mode register @@ -1278,17 +1207,13 @@ package STM32F429x.RCC is -- unspecified Reserved_1_31 : STM32F429x.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AHB3LPENR_Register use record FMCLPEN at 0 range 0 .. 0; Reserved_1_31 at 0 range 1 .. 31; end record; - ------------------------ - -- APB1LPENR_Register -- - ------------------------ - subtype APB1LPENR_TIM2LPEN_Field is STM32F429x.Bit; subtype APB1LPENR_TIM3LPEN_Field is STM32F429x.Bit; subtype APB1LPENR_TIM4LPEN_Field is STM32F429x.Bit; @@ -1378,7 +1303,7 @@ package STM32F429x.RCC is -- UART8 clock enable during Sleep mode UART8LPEN : APB1LPENR_UART8LPEN_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB1LPENR_Register use record TIM2LPEN at 0 range 0 .. 0; @@ -1413,10 +1338,6 @@ package STM32F429x.RCC is UART8LPEN at 0 range 31 .. 31; end record; - ------------------------ - -- APB2LPENR_Register -- - ------------------------ - subtype APB2LPENR_TIM1LPEN_Field is STM32F429x.Bit; subtype APB2LPENR_TIM8LPEN_Field is STM32F429x.Bit; subtype APB2LPENR_USART1LPEN_Field is STM32F429x.Bit; @@ -1487,7 +1408,7 @@ package STM32F429x.RCC is -- unspecified Reserved_27_31 : STM32F429x.UInt5 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for APB2LPENR_Register use record TIM1LPEN at 0 range 0 .. 0; @@ -1516,18 +1437,9 @@ package STM32F429x.RCC is Reserved_27_31 at 0 range 27 .. 31; end record; - ------------------- - -- BDCR_Register -- - ------------------- - subtype BDCR_LSEON_Field is STM32F429x.Bit; subtype BDCR_LSERDY_Field is STM32F429x.Bit; subtype BDCR_LSEBYP_Field is STM32F429x.Bit; - - ----------------- - -- BDCR.RTCSEL -- - ----------------- - -- BDCR_RTCSEL array element subtype BDCR_RTCSEL_Element is STM32F429x.Bit; @@ -1562,7 +1474,7 @@ package STM32F429x.RCC is type BDCR_Register is record -- External low-speed oscillator enable LSEON : BDCR_LSEON_Field := 16#0#; - -- External low-speed oscillator ready + -- Read-only. External low-speed oscillator ready LSERDY : BDCR_LSERDY_Field := 16#0#; -- External low-speed oscillator bypass LSEBYP : BDCR_LSEBYP_Field := 16#0#; @@ -1579,7 +1491,7 @@ package STM32F429x.RCC is -- unspecified Reserved_17_31 : STM32F429x.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BDCR_Register use record LSEON at 0 range 0 .. 0; @@ -1593,10 +1505,6 @@ package STM32F429x.RCC is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------ - -- CSR_Register -- - ------------------ - subtype CSR_LSION_Field is STM32F429x.Bit; subtype CSR_LSIRDY_Field is STM32F429x.Bit; subtype CSR_RMVF_Field is STM32F429x.Bit; @@ -1612,7 +1520,7 @@ package STM32F429x.RCC is type CSR_Register is record -- Internal low-speed oscillator enable LSION : CSR_LSION_Field := 16#0#; - -- Internal low-speed oscillator ready + -- Read-only. Internal low-speed oscillator ready LSIRDY : CSR_LSIRDY_Field := 16#0#; -- unspecified Reserved_2_23 : STM32F429x.UInt22 := 16#0#; @@ -1633,7 +1541,7 @@ package STM32F429x.RCC is -- Low-power reset flag LPWRRSTF : CSR_LPWRRSTF_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CSR_Register use record LSION at 0 range 0 .. 0; @@ -1649,10 +1557,6 @@ package STM32F429x.RCC is LPWRRSTF at 0 range 31 .. 31; end record; - -------------------- - -- SSCGR_Register -- - -------------------- - subtype SSCGR_MODPER_Field is STM32F429x.UInt13; subtype SSCGR_INCSTEP_Field is STM32F429x.UInt15; subtype SSCGR_SPREADSEL_Field is STM32F429x.Bit; @@ -1671,7 +1575,7 @@ package STM32F429x.RCC is -- Spread spectrum modulation enable SSCGEN : SSCGR_SSCGEN_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SSCGR_Register use record MODPER at 0 range 0 .. 12; @@ -1681,10 +1585,6 @@ package STM32F429x.RCC is SSCGEN at 0 range 31 .. 31; end record; - ------------------------- - -- PLLI2SCFGR_Register -- - ------------------------- - subtype PLLI2SCFGR_PLLI2SN_Field is STM32F429x.UInt9; subtype PLLI2SCFGR_PLLI2SQ_Field is STM32F429x.UInt4; subtype PLLI2SCFGR_PLLI2SR_Field is STM32F429x.UInt3; @@ -1704,7 +1604,7 @@ package STM32F429x.RCC is -- unspecified Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PLLI2SCFGR_Register use record Reserved_0_5 at 0 range 0 .. 5; @@ -1715,10 +1615,6 @@ package STM32F429x.RCC is Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------- - -- PLLSAICFGR_Register -- - ------------------------- - subtype PLLSAICFGR_PLLSAIN_Field is STM32F429x.UInt9; subtype PLLSAICFGR_PLLSAIQ_Field is STM32F429x.UInt4; subtype PLLSAICFGR_PLLSAIR_Field is STM32F429x.UInt3; @@ -1738,7 +1634,7 @@ package STM32F429x.RCC is -- unspecified Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PLLSAICFGR_Register use record Reserved_0_5 at 0 range 0 .. 5; @@ -1749,10 +1645,6 @@ package STM32F429x.RCC is Reserved_31_31 at 0 range 31 .. 31; end record; - ---------------------- - -- DCKCFGR_Register -- - ---------------------- - subtype DCKCFGR_PLLI2SDIVQ_Field is STM32F429x.UInt5; subtype DCKCFGR_PLLSAIDIVQ_Field is STM32F429x.UInt5; subtype DCKCFGR_PLLSAIDIVR_Field is STM32F429x.UInt2; @@ -1783,7 +1675,7 @@ package STM32F429x.RCC is -- unspecified Reserved_25_31 : STM32F429x.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DCKCFGR_Register use record PLLI2SDIVQ at 0 range 0 .. 4; @@ -1805,88 +1697,113 @@ package STM32F429x.RCC is -- Reset and clock control type RCC_Peripheral is record -- clock control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- PLL configuration register - PLLCFGR : PLLCFGR_Register; + PLLCFGR : aliased PLLCFGR_Register; + pragma Volatile_Full_Access (PLLCFGR); -- clock configuration register - CFGR : CFGR_Register; + CFGR : aliased CFGR_Register; + pragma Volatile_Full_Access (CFGR); -- clock interrupt register - CIR : CIR_Register; + CIR : aliased CIR_Register; + pragma Volatile_Full_Access (CIR); -- AHB1 peripheral reset register - AHB1RSTR : AHB1RSTR_Register; + AHB1RSTR : aliased AHB1RSTR_Register; + pragma Volatile_Full_Access (AHB1RSTR); -- AHB2 peripheral reset register - AHB2RSTR : AHB2RSTR_Register; + AHB2RSTR : aliased AHB2RSTR_Register; + pragma Volatile_Full_Access (AHB2RSTR); -- AHB3 peripheral reset register - AHB3RSTR : AHB3RSTR_Register; + AHB3RSTR : aliased AHB3RSTR_Register; + pragma Volatile_Full_Access (AHB3RSTR); -- APB1 peripheral reset register - APB1RSTR : APB1RSTR_Register; + APB1RSTR : aliased APB1RSTR_Register; + pragma Volatile_Full_Access (APB1RSTR); -- APB2 peripheral reset register - APB2RSTR : APB2RSTR_Register; + APB2RSTR : aliased APB2RSTR_Register; + pragma Volatile_Full_Access (APB2RSTR); -- AHB1 peripheral clock register - AHB1ENR : AHB1ENR_Register; + AHB1ENR : aliased AHB1ENR_Register; + pragma Volatile_Full_Access (AHB1ENR); -- AHB2 peripheral clock enable register - AHB2ENR : AHB2ENR_Register; + AHB2ENR : aliased AHB2ENR_Register; + pragma Volatile_Full_Access (AHB2ENR); -- AHB3 peripheral clock enable register - AHB3ENR : AHB3ENR_Register; + AHB3ENR : aliased AHB3ENR_Register; + pragma Volatile_Full_Access (AHB3ENR); -- APB1 peripheral clock enable register - APB1ENR : APB1ENR_Register; + APB1ENR : aliased APB1ENR_Register; + pragma Volatile_Full_Access (APB1ENR); -- APB2 peripheral clock enable register - APB2ENR : APB2ENR_Register; + APB2ENR : aliased APB2ENR_Register; + pragma Volatile_Full_Access (APB2ENR); -- AHB1 peripheral clock enable in low power mode register - AHB1LPENR : AHB1LPENR_Register; + AHB1LPENR : aliased AHB1LPENR_Register; + pragma Volatile_Full_Access (AHB1LPENR); -- AHB2 peripheral clock enable in low power mode register - AHB2LPENR : AHB2LPENR_Register; + AHB2LPENR : aliased AHB2LPENR_Register; + pragma Volatile_Full_Access (AHB2LPENR); -- AHB3 peripheral clock enable in low power mode register - AHB3LPENR : AHB3LPENR_Register; + AHB3LPENR : aliased AHB3LPENR_Register; + pragma Volatile_Full_Access (AHB3LPENR); -- APB1 peripheral clock enable in low power mode register - APB1LPENR : APB1LPENR_Register; + APB1LPENR : aliased APB1LPENR_Register; + pragma Volatile_Full_Access (APB1LPENR); -- APB2 peripheral clock enabled in low power mode register - APB2LPENR : APB2LPENR_Register; + APB2LPENR : aliased APB2LPENR_Register; + pragma Volatile_Full_Access (APB2LPENR); -- Backup domain control register - BDCR : BDCR_Register; + BDCR : aliased BDCR_Register; + pragma Volatile_Full_Access (BDCR); -- clock control & status register - CSR : CSR_Register; + CSR : aliased CSR_Register; + pragma Volatile_Full_Access (CSR); -- spread spectrum clock generation register - SSCGR : SSCGR_Register; + SSCGR : aliased SSCGR_Register; + pragma Volatile_Full_Access (SSCGR); -- PLLI2S configuration register - PLLI2SCFGR : PLLI2SCFGR_Register; + PLLI2SCFGR : aliased PLLI2SCFGR_Register; + pragma Volatile_Full_Access (PLLI2SCFGR); -- PLLSAICFGR - PLLSAICFGR : PLLSAICFGR_Register; + PLLSAICFGR : aliased PLLSAICFGR_Register; + pragma Volatile_Full_Access (PLLSAICFGR); -- DCKCFGR - DCKCFGR : DCKCFGR_Register; + DCKCFGR : aliased DCKCFGR_Register; + pragma Volatile_Full_Access (DCKCFGR); end record with Volatile; for RCC_Peripheral use record - CR at 0 range 0 .. 31; - PLLCFGR at 4 range 0 .. 31; - CFGR at 8 range 0 .. 31; - CIR at 12 range 0 .. 31; - AHB1RSTR at 16 range 0 .. 31; - AHB2RSTR at 20 range 0 .. 31; - AHB3RSTR at 24 range 0 .. 31; - APB1RSTR at 32 range 0 .. 31; - APB2RSTR at 36 range 0 .. 31; - AHB1ENR at 48 range 0 .. 31; - AHB2ENR at 52 range 0 .. 31; - AHB3ENR at 56 range 0 .. 31; - APB1ENR at 64 range 0 .. 31; - APB2ENR at 68 range 0 .. 31; - AHB1LPENR at 80 range 0 .. 31; - AHB2LPENR at 84 range 0 .. 31; - AHB3LPENR at 88 range 0 .. 31; - APB1LPENR at 96 range 0 .. 31; - APB2LPENR at 100 range 0 .. 31; - BDCR at 112 range 0 .. 31; - CSR at 116 range 0 .. 31; - SSCGR at 128 range 0 .. 31; - PLLI2SCFGR at 132 range 0 .. 31; - PLLSAICFGR at 136 range 0 .. 31; - DCKCFGR at 140 range 0 .. 31; + CR at 16#0# range 0 .. 31; + PLLCFGR at 16#4# range 0 .. 31; + CFGR at 16#8# range 0 .. 31; + CIR at 16#C# range 0 .. 31; + AHB1RSTR at 16#10# range 0 .. 31; + AHB2RSTR at 16#14# range 0 .. 31; + AHB3RSTR at 16#18# range 0 .. 31; + APB1RSTR at 16#20# range 0 .. 31; + APB2RSTR at 16#24# range 0 .. 31; + AHB1ENR at 16#30# range 0 .. 31; + AHB2ENR at 16#34# range 0 .. 31; + AHB3ENR at 16#38# range 0 .. 31; + APB1ENR at 16#40# range 0 .. 31; + APB2ENR at 16#44# range 0 .. 31; + AHB1LPENR at 16#50# range 0 .. 31; + AHB2LPENR at 16#54# range 0 .. 31; + AHB3LPENR at 16#58# range 0 .. 31; + APB1LPENR at 16#60# range 0 .. 31; + APB2LPENR at 16#64# range 0 .. 31; + BDCR at 16#70# range 0 .. 31; + CSR at 16#74# range 0 .. 31; + SSCGR at 16#80# range 0 .. 31; + PLLI2SCFGR at 16#84# range 0 .. 31; + PLLSAICFGR at 16#88# range 0 .. 31; + DCKCFGR at 16#8C# range 0 .. 31; end record; -- Reset and clock control RCC_Periph : aliased RCC_Peripheral - with Import, Address => System'To_Address (16#40023800#); + with Import, Address => RCC_Base; end STM32F429x.RCC; diff --git a/stm32f429i/stm32f429x/stm32f429x-rng.ads b/stm32f429i/stm32f429x/stm32f429x-rng.ads index 132922b..a639813 100644 --- a/stm32f429i/stm32f429x/stm32f429x-rng.ads +++ b/stm32f429i/stm32f429x/stm32f429x-rng.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.RNG is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_RNGEN_Field is STM32F429x.Bit; subtype CR_IE_Field is STM32F429x.Bit; @@ -30,7 +28,7 @@ package STM32F429x.RNG is -- unspecified Reserved_4_31 : STM32F429x.UInt28 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record Reserved_0_1 at 0 range 0 .. 1; @@ -39,10 +37,6 @@ package STM32F429x.RNG is Reserved_4_31 at 0 range 4 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_DRDY_Field is STM32F429x.Bit; subtype SR_CECS_Field is STM32F429x.Bit; subtype SR_SECS_Field is STM32F429x.Bit; @@ -51,11 +45,11 @@ package STM32F429x.RNG is -- status register type SR_Register is record - -- Data ready + -- Read-only. Data ready DRDY : SR_DRDY_Field := 16#0#; - -- Clock error current status + -- Read-only. Clock error current status CECS : SR_CECS_Field := 16#0#; - -- Seed error current status + -- Read-only. Seed error current status SECS : SR_SECS_Field := 16#0#; -- unspecified Reserved_3_4 : STM32F429x.UInt2 := 16#0#; @@ -66,7 +60,7 @@ package STM32F429x.RNG is -- unspecified Reserved_7_31 : STM32F429x.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record DRDY at 0 range 0 .. 0; @@ -85,22 +79,24 @@ package STM32F429x.RNG is -- Random number generator type RNG_Peripheral is record -- control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- data register - DR : STM32F429x.Word; + DR : aliased STM32F429x.UInt32; end record with Volatile; for RNG_Peripheral use record - CR at 0 range 0 .. 31; - SR at 4 range 0 .. 31; - DR at 8 range 0 .. 31; + CR at 16#0# range 0 .. 31; + SR at 16#4# range 0 .. 31; + DR at 16#8# range 0 .. 31; end record; -- Random number generator RNG_Periph : aliased RNG_Peripheral - with Import, Address => System'To_Address (16#50060800#); + with Import, Address => RNG_Base; end STM32F429x.RNG; diff --git a/stm32f429i/stm32f429x/stm32f429x-rtc.ads b/stm32f429i/stm32f429x/stm32f429x-rtc.ads index 8ff0fef..912de9e 100644 --- a/stm32f429i/stm32f429x/stm32f429x-rtc.ads +++ b/stm32f429i/stm32f429x/stm32f429x-rtc.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.RTC is -- Registers -- --------------- - ----------------- - -- TR_Register -- - ----------------- - subtype TR_SU_Field is STM32F429x.UInt4; subtype TR_ST_Field is STM32F429x.UInt3; subtype TR_MNU_Field is STM32F429x.UInt4; @@ -47,7 +45,7 @@ package STM32F429x.RTC is -- unspecified Reserved_23_31 : STM32F429x.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TR_Register use record SU at 0 range 0 .. 3; @@ -62,10 +60,6 @@ package STM32F429x.RTC is Reserved_23_31 at 0 range 23 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - subtype DR_DU_Field is STM32F429x.UInt4; subtype DR_DT_Field is STM32F429x.UInt2; subtype DR_MU_Field is STM32F429x.UInt4; @@ -95,7 +89,7 @@ package STM32F429x.RTC is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DU at 0 range 0 .. 3; @@ -109,10 +103,6 @@ package STM32F429x.RTC is Reserved_24_31 at 0 range 24 .. 31; end record; - ----------------- - -- CR_Register -- - ----------------- - subtype CR_WCKSEL_Field is STM32F429x.UInt3; subtype CR_TSEDGE_Field is STM32F429x.Bit; subtype CR_REFCKON_Field is STM32F429x.Bit; @@ -180,7 +170,7 @@ package STM32F429x.RTC is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record WCKSEL at 0 range 0 .. 2; @@ -207,10 +197,6 @@ package STM32F429x.RTC is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- ISR_Register -- - ------------------ - subtype ISR_ALRAWF_Field is STM32F429x.Bit; subtype ISR_ALRBWF_Field is STM32F429x.Bit; subtype ISR_WUTWF_Field is STM32F429x.Bit; @@ -230,19 +216,19 @@ package STM32F429x.RTC is -- initialization and status register type ISR_Register is record - -- Alarm A write flag + -- Read-only. Alarm A write flag ALRAWF : ISR_ALRAWF_Field := 16#1#; - -- Alarm B write flag + -- Read-only. Alarm B write flag ALRBWF : ISR_ALRBWF_Field := 16#1#; - -- Wakeup timer write flag + -- Read-only. Wakeup timer write flag WUTWF : ISR_WUTWF_Field := 16#1#; -- Shift operation pending SHPF : ISR_SHPF_Field := 16#0#; - -- Initialization status flag + -- Read-only. Initialization status flag INITS : ISR_INITS_Field := 16#0#; -- Registers synchronization flag RSF : ISR_RSF_Field := 16#0#; - -- Initialization flag + -- Read-only. Initialization flag INITF : ISR_INITF_Field := 16#0#; -- Initialization mode INIT : ISR_INIT_Field := 16#0#; @@ -262,12 +248,12 @@ package STM32F429x.RTC is TAMP2F : ISR_TAMP2F_Field := 16#0#; -- unspecified Reserved_15_15 : STM32F429x.Bit := 16#0#; - -- Recalibration pending Flag + -- Read-only. Recalibration pending Flag RECALPF : ISR_RECALPF_Field := 16#0#; -- unspecified Reserved_17_31 : STM32F429x.UInt15 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ISR_Register use record ALRAWF at 0 range 0 .. 0; @@ -290,10 +276,6 @@ package STM32F429x.RTC is Reserved_17_31 at 0 range 17 .. 31; end record; - ------------------- - -- PRER_Register -- - ------------------- - subtype PRER_PREDIV_S_Field is STM32F429x.UInt15; subtype PRER_PREDIV_A_Field is STM32F429x.UInt7; @@ -308,7 +290,7 @@ package STM32F429x.RTC is -- unspecified Reserved_23_31 : STM32F429x.UInt9 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PRER_Register use record PREDIV_S at 0 range 0 .. 14; @@ -317,30 +299,22 @@ package STM32F429x.RTC is Reserved_23_31 at 0 range 23 .. 31; end record; - ------------------- - -- WUTR_Register -- - ------------------- - - subtype WUTR_WUT_Field is STM32F429x.Short; + subtype WUTR_WUT_Field is STM32F429x.UInt16; -- wakeup timer register type WUTR_Register is record -- Wakeup auto-reload value bits WUT : WUTR_WUT_Field := 16#FFFF#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for WUTR_Register use record WUT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- CALIBR_Register -- - --------------------- - subtype CALIBR_DC_Field is STM32F429x.UInt5; subtype CALIBR_DCS_Field is STM32F429x.Bit; @@ -355,7 +329,7 @@ package STM32F429x.RTC is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CALIBR_Register use record DC at 0 range 0 .. 4; @@ -364,10 +338,6 @@ package STM32F429x.RTC is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------- - -- ALRMAR_Register -- - --------------------- - subtype ALRMAR_SU_Field is STM32F429x.UInt4; subtype ALRMAR_ST_Field is STM32F429x.UInt3; subtype ALRMAR_MSK1_Field is STM32F429x.Bit; @@ -414,7 +384,7 @@ package STM32F429x.RTC is -- Alarm A date mask MSK4 : ALRMAR_MSK4_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ALRMAR_Register use record SU at 0 range 0 .. 3; @@ -433,10 +403,6 @@ package STM32F429x.RTC is MSK4 at 0 range 31 .. 31; end record; - --------------------- - -- ALRMBR_Register -- - --------------------- - subtype ALRMBR_SU_Field is STM32F429x.UInt4; subtype ALRMBR_ST_Field is STM32F429x.UInt3; subtype ALRMBR_MSK1_Field is STM32F429x.Bit; @@ -483,7 +449,7 @@ package STM32F429x.RTC is -- Alarm B date mask MSK4 : ALRMBR_MSK4_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ALRMBR_Register use record SU at 0 range 0 .. 3; @@ -502,63 +468,51 @@ package STM32F429x.RTC is MSK4 at 0 range 31 .. 31; end record; - ------------------ - -- WPR_Register -- - ------------------ - subtype WPR_KEY_Field is STM32F429x.Byte; -- write protection register type WPR_Register is record - -- Write protection key + -- Write-only. Write protection key KEY : WPR_KEY_Field := 16#0#; -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for WPR_Register use record KEY at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- SSR_Register -- - ------------------ - - subtype SSR_SS_Field is STM32F429x.Short; + subtype SSR_SS_Field is STM32F429x.UInt16; -- sub second register type SSR_Register is record - -- Sub second value + -- Read-only. Sub second value SS : SSR_SS_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SSR_Register use record SS at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- SHIFTR_Register -- - --------------------- - subtype SHIFTR_SUBFS_Field is STM32F429x.UInt15; subtype SHIFTR_ADD1S_Field is STM32F429x.Bit; -- shift control register type SHIFTR_Register is record - -- Subtract a fraction of a second + -- Write-only. Subtract a fraction of a second SUBFS : SHIFTR_SUBFS_Field := 16#0#; -- unspecified - Reserved_15_30 : STM32F429x.Short := 16#0#; - -- Add one second + Reserved_15_30 : STM32F429x.UInt16 := 16#0#; + -- Write-only. Add one second ADD1S : SHIFTR_ADD1S_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SHIFTR_Register use record SUBFS at 0 range 0 .. 14; @@ -566,10 +520,6 @@ package STM32F429x.RTC is ADD1S at 0 range 31 .. 31; end record; - ------------------- - -- TSTR_Register -- - ------------------- - subtype TSTR_TAMP1E_Field is STM32F429x.Bit; subtype TSTR_TAMP1TRG_Field is STM32F429x.Bit; subtype TSTR_TAMPIE_Field is STM32F429x.Bit; @@ -579,24 +529,24 @@ package STM32F429x.RTC is -- time stamp time register type TSTR_Register is record - -- Tamper 1 detection enable + -- Read-only. Tamper 1 detection enable TAMP1E : TSTR_TAMP1E_Field; - -- Active level for tamper 1 + -- Read-only. Active level for tamper 1 TAMP1TRG : TSTR_TAMP1TRG_Field; - -- Tamper interrupt enable + -- Read-only. Tamper interrupt enable TAMPIE : TSTR_TAMPIE_Field; -- unspecified Reserved_3_15 : STM32F429x.UInt13; - -- TAMPER1 mapping + -- Read-only. TAMPER1 mapping TAMP1INSEL : TSTR_TAMP1INSEL_Field; - -- TIMESTAMP mapping + -- Read-only. TIMESTAMP mapping TSINSEL : TSTR_TSINSEL_Field; - -- AFO_ALARM output type + -- Read-only. AFO_ALARM output type ALARMOUTTYPE : TSTR_ALARMOUTTYPE_Field; -- unspecified Reserved_19_31 : STM32F429x.UInt13; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TSTR_Register use record TAMP1E at 0 range 0 .. 0; @@ -609,10 +559,6 @@ package STM32F429x.RTC is Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------- - -- TSDR_Register -- - ------------------- - subtype TSDR_DU_Field is STM32F429x.UInt4; subtype TSDR_DT_Field is STM32F429x.UInt2; subtype TSDR_MU_Field is STM32F429x.UInt4; @@ -621,22 +567,22 @@ package STM32F429x.RTC is -- time stamp date register type TSDR_Register is record - -- Date units in BCD format + -- Read-only. Date units in BCD format DU : TSDR_DU_Field; - -- Date tens in BCD format + -- Read-only. Date tens in BCD format DT : TSDR_DT_Field; -- unspecified Reserved_6_7 : STM32F429x.UInt2; - -- Month units in BCD format + -- Read-only. Month units in BCD format MU : TSDR_MU_Field; - -- Month tens in BCD format + -- Read-only. Month tens in BCD format MT : TSDR_MT_Field; - -- Week day units + -- Read-only. Week day units WDU : TSDR_WDU_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TSDR_Register use record DU at 0 range 0 .. 3; @@ -648,63 +594,25 @@ package STM32F429x.RTC is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- TSSSR_Register -- - -------------------- - - subtype TSSSR_SS_Field is STM32F429x.Short; + subtype TSSSR_SS_Field is STM32F429x.UInt16; -- timestamp sub second register type TSSSR_Register is record - -- Sub second value + -- Read-only. Sub second value SS : TSSSR_SS_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TSSSR_Register use record SS at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- CALR_Register -- - ------------------- - subtype CALR_CALM_Field is STM32F429x.UInt9; - - --------------- - -- CALR.CALW -- - --------------- - - -- CALR_CALW array element - subtype CALR_CALW_Element is STM32F429x.Bit; - - -- CALR_CALW array - type CALR_CALW_Field_Array is array (0 .. 1) of CALR_CALW_Element - with Component_Size => 1, Size => 2; - - -- Type definition for CALR_CALW - type CALR_CALW_Field - (As_Array : Boolean := False) - is record - case As_Array is - when False => - -- CALW as a value - Val : STM32F429x.UInt2; - when True => - -- CALW as an array - Arr : CALR_CALW_Field_Array; - end case; - end record - with Unchecked_Union, Size => 2; - - for CALR_CALW_Field use record - Val at 0 range 0 .. 1; - Arr at 0 range 0 .. 1; - end record; - + subtype CALR_CALW16_Field is STM32F429x.Bit; + subtype CALR_CALW8_Field is STM32F429x.Bit; subtype CALR_CALP_Field is STM32F429x.Bit; -- calibration register @@ -714,26 +622,25 @@ package STM32F429x.RTC is -- unspecified Reserved_9_12 : STM32F429x.UInt4 := 16#0#; -- Use a 16-second calibration cycle period - CALW : CALR_CALW_Field := (As_Array => False, Val => 16#0#); + CALW16 : CALR_CALW16_Field := 16#0#; + -- Use an 8-second calibration cycle period + CALW8 : CALR_CALW8_Field := 16#0#; -- Increase frequency of RTC by 488.5 ppm CALP : CALR_CALP_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CALR_Register use record CALM at 0 range 0 .. 8; Reserved_9_12 at 0 range 9 .. 12; - CALW at 0 range 13 .. 14; + CALW16 at 0 range 13 .. 13; + CALW8 at 0 range 14 .. 14; CALP at 0 range 15 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- TAFCR_Register -- - -------------------- - subtype TAFCR_TAMP1E_Field is STM32F429x.Bit; subtype TAFCR_TAMP1TRG_Field is STM32F429x.Bit; subtype TAFCR_TAMPIE_Field is STM32F429x.Bit; @@ -781,7 +688,7 @@ package STM32F429x.RTC is -- unspecified Reserved_19_31 : STM32F429x.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TAFCR_Register use record TAMP1E at 0 range 0 .. 0; @@ -801,10 +708,6 @@ package STM32F429x.RTC is Reserved_19_31 at 0 range 19 .. 31; end record; - ----------------------- - -- ALRMASSR_Register -- - ----------------------- - subtype ALRMASSR_SS_Field is STM32F429x.UInt15; subtype ALRMASSR_MASKSS_Field is STM32F429x.UInt4; @@ -819,7 +722,7 @@ package STM32F429x.RTC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ALRMASSR_Register use record SS at 0 range 0 .. 14; @@ -828,10 +731,6 @@ package STM32F429x.RTC is Reserved_28_31 at 0 range 28 .. 31; end record; - ----------------------- - -- ALRMBSSR_Register -- - ----------------------- - subtype ALRMBSSR_SS_Field is STM32F429x.UInt15; subtype ALRMBSSR_MASKSS_Field is STM32F429x.UInt4; @@ -846,7 +745,7 @@ package STM32F429x.RTC is -- unspecified Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ALRMBSSR_Register use record SS at 0 range 0 .. 14; @@ -862,130 +761,149 @@ package STM32F429x.RTC is -- Real-time clock type RTC_Peripheral is record -- time register - TR : TR_Register; + TR : aliased TR_Register; + pragma Volatile_Full_Access (TR); -- date register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- initialization and status register - ISR : ISR_Register; + ISR : aliased ISR_Register; + pragma Volatile_Full_Access (ISR); -- prescaler register - PRER : PRER_Register; + PRER : aliased PRER_Register; + pragma Volatile_Full_Access (PRER); -- wakeup timer register - WUTR : WUTR_Register; + WUTR : aliased WUTR_Register; + pragma Volatile_Full_Access (WUTR); -- calibration register - CALIBR : CALIBR_Register; + CALIBR : aliased CALIBR_Register; + pragma Volatile_Full_Access (CALIBR); -- alarm A register - ALRMAR : ALRMAR_Register; + ALRMAR : aliased ALRMAR_Register; + pragma Volatile_Full_Access (ALRMAR); -- alarm B register - ALRMBR : ALRMBR_Register; + ALRMBR : aliased ALRMBR_Register; + pragma Volatile_Full_Access (ALRMBR); -- write protection register - WPR : WPR_Register; + WPR : aliased WPR_Register; + pragma Volatile_Full_Access (WPR); -- sub second register - SSR : SSR_Register; + SSR : aliased SSR_Register; + pragma Volatile_Full_Access (SSR); -- shift control register - SHIFTR : SHIFTR_Register; + SHIFTR : aliased SHIFTR_Register; + pragma Volatile_Full_Access (SHIFTR); -- time stamp time register - TSTR : TSTR_Register; + TSTR : aliased TSTR_Register; + pragma Volatile_Full_Access (TSTR); -- time stamp date register - TSDR : TSDR_Register; + TSDR : aliased TSDR_Register; + pragma Volatile_Full_Access (TSDR); -- timestamp sub second register - TSSSR : TSSSR_Register; + TSSSR : aliased TSSSR_Register; + pragma Volatile_Full_Access (TSSSR); -- calibration register - CALR : CALR_Register; + CALR : aliased CALR_Register; + pragma Volatile_Full_Access (CALR); -- tamper and alternate function configuration register - TAFCR : TAFCR_Register; + TAFCR : aliased TAFCR_Register; + pragma Volatile_Full_Access (TAFCR); -- alarm A sub second register - ALRMASSR : ALRMASSR_Register; + ALRMASSR : aliased ALRMASSR_Register; + pragma Volatile_Full_Access (ALRMASSR); -- alarm B sub second register - ALRMBSSR : ALRMBSSR_Register; + ALRMBSSR : aliased ALRMBSSR_Register; + pragma Volatile_Full_Access (ALRMBSSR); -- backup register - BKP0R : STM32F429x.Word; + BKP0R : aliased STM32F429x.UInt32; -- backup register - BKP1R : STM32F429x.Word; + BKP1R : aliased STM32F429x.UInt32; -- backup register - BKP2R : STM32F429x.Word; + BKP2R : aliased STM32F429x.UInt32; -- backup register - BKP3R : STM32F429x.Word; + BKP3R : aliased STM32F429x.UInt32; -- backup register - BKP4R : STM32F429x.Word; + BKP4R : aliased STM32F429x.UInt32; -- backup register - BKP5R : STM32F429x.Word; + BKP5R : aliased STM32F429x.UInt32; -- backup register - BKP6R : STM32F429x.Word; + BKP6R : aliased STM32F429x.UInt32; -- backup register - BKP7R : STM32F429x.Word; + BKP7R : aliased STM32F429x.UInt32; -- backup register - BKP8R : STM32F429x.Word; + BKP8R : aliased STM32F429x.UInt32; -- backup register - BKP9R : STM32F429x.Word; + BKP9R : aliased STM32F429x.UInt32; -- backup register - BKP10R : STM32F429x.Word; + BKP10R : aliased STM32F429x.UInt32; -- backup register - BKP11R : STM32F429x.Word; + BKP11R : aliased STM32F429x.UInt32; -- backup register - BKP12R : STM32F429x.Word; + BKP12R : aliased STM32F429x.UInt32; -- backup register - BKP13R : STM32F429x.Word; + BKP13R : aliased STM32F429x.UInt32; -- backup register - BKP14R : STM32F429x.Word; + BKP14R : aliased STM32F429x.UInt32; -- backup register - BKP15R : STM32F429x.Word; + BKP15R : aliased STM32F429x.UInt32; -- backup register - BKP16R : STM32F429x.Word; + BKP16R : aliased STM32F429x.UInt32; -- backup register - BKP17R : STM32F429x.Word; + BKP17R : aliased STM32F429x.UInt32; -- backup register - BKP18R : STM32F429x.Word; + BKP18R : aliased STM32F429x.UInt32; -- backup register - BKP19R : STM32F429x.Word; + BKP19R : aliased STM32F429x.UInt32; end record with Volatile; for RTC_Peripheral use record - TR at 0 range 0 .. 31; - DR at 4 range 0 .. 31; - CR at 8 range 0 .. 31; - ISR at 12 range 0 .. 31; - PRER at 16 range 0 .. 31; - WUTR at 20 range 0 .. 31; - CALIBR at 24 range 0 .. 31; - ALRMAR at 28 range 0 .. 31; - ALRMBR at 32 range 0 .. 31; - WPR at 36 range 0 .. 31; - SSR at 40 range 0 .. 31; - SHIFTR at 44 range 0 .. 31; - TSTR at 48 range 0 .. 31; - TSDR at 52 range 0 .. 31; - TSSSR at 56 range 0 .. 31; - CALR at 60 range 0 .. 31; - TAFCR at 64 range 0 .. 31; - ALRMASSR at 68 range 0 .. 31; - ALRMBSSR at 72 range 0 .. 31; - BKP0R at 80 range 0 .. 31; - BKP1R at 84 range 0 .. 31; - BKP2R at 88 range 0 .. 31; - BKP3R at 92 range 0 .. 31; - BKP4R at 96 range 0 .. 31; - BKP5R at 100 range 0 .. 31; - BKP6R at 104 range 0 .. 31; - BKP7R at 108 range 0 .. 31; - BKP8R at 112 range 0 .. 31; - BKP9R at 116 range 0 .. 31; - BKP10R at 120 range 0 .. 31; - BKP11R at 124 range 0 .. 31; - BKP12R at 128 range 0 .. 31; - BKP13R at 132 range 0 .. 31; - BKP14R at 136 range 0 .. 31; - BKP15R at 140 range 0 .. 31; - BKP16R at 144 range 0 .. 31; - BKP17R at 148 range 0 .. 31; - BKP18R at 152 range 0 .. 31; - BKP19R at 156 range 0 .. 31; + TR at 16#0# range 0 .. 31; + DR at 16#4# range 0 .. 31; + CR at 16#8# range 0 .. 31; + ISR at 16#C# range 0 .. 31; + PRER at 16#10# range 0 .. 31; + WUTR at 16#14# range 0 .. 31; + CALIBR at 16#18# range 0 .. 31; + ALRMAR at 16#1C# range 0 .. 31; + ALRMBR at 16#20# range 0 .. 31; + WPR at 16#24# range 0 .. 31; + SSR at 16#28# range 0 .. 31; + SHIFTR at 16#2C# range 0 .. 31; + TSTR at 16#30# range 0 .. 31; + TSDR at 16#34# range 0 .. 31; + TSSSR at 16#38# range 0 .. 31; + CALR at 16#3C# range 0 .. 31; + TAFCR at 16#40# range 0 .. 31; + ALRMASSR at 16#44# range 0 .. 31; + ALRMBSSR at 16#48# range 0 .. 31; + BKP0R at 16#50# range 0 .. 31; + BKP1R at 16#54# range 0 .. 31; + BKP2R at 16#58# range 0 .. 31; + BKP3R at 16#5C# range 0 .. 31; + BKP4R at 16#60# range 0 .. 31; + BKP5R at 16#64# range 0 .. 31; + BKP6R at 16#68# range 0 .. 31; + BKP7R at 16#6C# range 0 .. 31; + BKP8R at 16#70# range 0 .. 31; + BKP9R at 16#74# range 0 .. 31; + BKP10R at 16#78# range 0 .. 31; + BKP11R at 16#7C# range 0 .. 31; + BKP12R at 16#80# range 0 .. 31; + BKP13R at 16#84# range 0 .. 31; + BKP14R at 16#88# range 0 .. 31; + BKP15R at 16#8C# range 0 .. 31; + BKP16R at 16#90# range 0 .. 31; + BKP17R at 16#94# range 0 .. 31; + BKP18R at 16#98# range 0 .. 31; + BKP19R at 16#9C# range 0 .. 31; end record; -- Real-time clock RTC_Periph : aliased RTC_Peripheral - with Import, Address => System'To_Address (16#40002800#); + with Import, Address => RTC_Base; end STM32F429x.RTC; diff --git a/stm32f429i/stm32f429x/stm32f429x-sai.ads b/stm32f429i/stm32f429x/stm32f429x-sai.ads index e771e65..12e7e33 100644 --- a/stm32f429i/stm32f429x/stm32f429x-sai.ads +++ b/stm32f429i/stm32f429x/stm32f429x-sai.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.SAI is -- Registers -- --------------- - ------------------- - -- ACR1_Register -- - ------------------- - subtype ACR1_MODE_Field is STM32F429x.UInt2; subtype ACR1_PRTCFG_Field is STM32F429x.UInt2; subtype ACR1_DS_Field is STM32F429x.UInt3; @@ -64,7 +62,7 @@ package STM32F429x.SAI is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ACR1_Register use record MODE at 0 range 0 .. 1; @@ -85,10 +83,6 @@ package STM32F429x.SAI is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- ACR2_Register -- - ------------------- - subtype ACR2_FTH_Field is STM32F429x.UInt3; subtype ACR2_FFLUS_Field is STM32F429x.Bit; subtype ACR2_TRIS_Field is STM32F429x.Bit; @@ -117,9 +111,9 @@ package STM32F429x.SAI is -- Companding mode COMP : ACR2_COMP_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ACR2_Register use record FTH at 0 range 0 .. 2; @@ -133,10 +127,6 @@ package STM32F429x.SAI is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- AFRCR_Register -- - -------------------- - subtype AFRCR_FRL_Field is STM32F429x.Byte; subtype AFRCR_FSALL_Field is STM32F429x.UInt7; subtype AFRCR_FSDEF_Field is STM32F429x.Bit; @@ -160,7 +150,7 @@ package STM32F429x.SAI is -- unspecified Reserved_19_31 : STM32F429x.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AFRCR_Register use record FRL at 0 range 0 .. 7; @@ -172,14 +162,10 @@ package STM32F429x.SAI is Reserved_19_31 at 0 range 19 .. 31; end record; - --------------------- - -- ASLOTR_Register -- - --------------------- - subtype ASLOTR_FBOFF_Field is STM32F429x.UInt5; subtype ASLOTR_SLOTSZ_Field is STM32F429x.UInt2; subtype ASLOTR_NBSLOT_Field is STM32F429x.UInt4; - subtype ASLOTR_SLOTEN_Field is STM32F429x.Short; + subtype ASLOTR_SLOTEN_Field is STM32F429x.UInt16; -- ASlot register type ASLOTR_Register is record @@ -196,7 +182,7 @@ package STM32F429x.SAI is -- Slot enable SLOTEN : ASLOTR_SLOTEN_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ASLOTR_Register use record FBOFF at 0 range 0 .. 4; @@ -207,10 +193,6 @@ package STM32F429x.SAI is SLOTEN at 0 range 16 .. 31; end record; - ------------------ - -- AIM_Register -- - ------------------ - subtype AIM_OVRUDRIE_Field is STM32F429x.Bit; subtype AIM_MUTEDET_Field is STM32F429x.Bit; subtype AIM_WCKCFG_Field is STM32F429x.Bit; @@ -238,7 +220,7 @@ package STM32F429x.SAI is -- unspecified Reserved_7_31 : STM32F429x.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for AIM_Register use record OVRUDRIE at 0 range 0 .. 0; @@ -251,10 +233,6 @@ package STM32F429x.SAI is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------ - -- ASR_Register -- - ------------------ - subtype ASR_OVRUDR_Field is STM32F429x.Bit; subtype ASR_MUTEDET_Field is STM32F429x.Bit; subtype ASR_WCKCFG_Field is STM32F429x.Bit; @@ -287,7 +265,7 @@ package STM32F429x.SAI is -- unspecified Reserved_19_31 : STM32F429x.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ASR_Register use record OVRUDR at 0 range 0 .. 0; @@ -302,10 +280,6 @@ package STM32F429x.SAI is Reserved_19_31 at 0 range 19 .. 31; end record; - --------------------- - -- ACLRFR_Register -- - --------------------- - subtype ACLRFR_OVRUDR_Field is STM32F429x.Bit; subtype ACLRFR_MUTEDET_Field is STM32F429x.Bit; subtype ACLRFR_WCKCFG_Field is STM32F429x.Bit; @@ -332,7 +306,7 @@ package STM32F429x.SAI is -- unspecified Reserved_7_31 : STM32F429x.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ACLRFR_Register use record OVRUDR at 0 range 0 .. 0; @@ -345,10 +319,6 @@ package STM32F429x.SAI is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------- - -- BCR1_Register -- - ------------------- - subtype BCR1_MODE_Field is STM32F429x.UInt2; subtype BCR1_PRTCFG_Field is STM32F429x.UInt2; subtype BCR1_DS_Field is STM32F429x.UInt3; @@ -397,7 +367,7 @@ package STM32F429x.SAI is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BCR1_Register use record MODE at 0 range 0 .. 1; @@ -418,10 +388,6 @@ package STM32F429x.SAI is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- BCR2_Register -- - ------------------- - subtype BCR2_FTH_Field is STM32F429x.UInt3; subtype BCR2_FFLUS_Field is STM32F429x.Bit; subtype BCR2_TRIS_Field is STM32F429x.Bit; @@ -450,9 +416,9 @@ package STM32F429x.SAI is -- Companding mode COMP : BCR2_COMP_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BCR2_Register use record FTH at 0 range 0 .. 2; @@ -466,10 +432,6 @@ package STM32F429x.SAI is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- BFRCR_Register -- - -------------------- - subtype BFRCR_FRL_Field is STM32F429x.Byte; subtype BFRCR_FSALL_Field is STM32F429x.UInt7; subtype BFRCR_FSDEF_Field is STM32F429x.Bit; @@ -493,7 +455,7 @@ package STM32F429x.SAI is -- unspecified Reserved_19_31 : STM32F429x.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BFRCR_Register use record FRL at 0 range 0 .. 7; @@ -505,14 +467,10 @@ package STM32F429x.SAI is Reserved_19_31 at 0 range 19 .. 31; end record; - --------------------- - -- BSLOTR_Register -- - --------------------- - subtype BSLOTR_FBOFF_Field is STM32F429x.UInt5; subtype BSLOTR_SLOTSZ_Field is STM32F429x.UInt2; subtype BSLOTR_NBSLOT_Field is STM32F429x.UInt4; - subtype BSLOTR_SLOTEN_Field is STM32F429x.Short; + subtype BSLOTR_SLOTEN_Field is STM32F429x.UInt16; -- BSlot register type BSLOTR_Register is record @@ -529,7 +487,7 @@ package STM32F429x.SAI is -- Slot enable SLOTEN : BSLOTR_SLOTEN_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BSLOTR_Register use record FBOFF at 0 range 0 .. 4; @@ -540,10 +498,6 @@ package STM32F429x.SAI is SLOTEN at 0 range 16 .. 31; end record; - ------------------ - -- BIM_Register -- - ------------------ - subtype BIM_OVRUDRIE_Field is STM32F429x.Bit; subtype BIM_MUTEDET_Field is STM32F429x.Bit; subtype BIM_WCKCFG_Field is STM32F429x.Bit; @@ -571,7 +525,7 @@ package STM32F429x.SAI is -- unspecified Reserved_7_31 : STM32F429x.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BIM_Register use record OVRUDRIE at 0 range 0 .. 0; @@ -584,10 +538,6 @@ package STM32F429x.SAI is Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------ - -- BSR_Register -- - ------------------ - subtype BSR_OVRUDR_Field is STM32F429x.Bit; subtype BSR_MUTEDET_Field is STM32F429x.Bit; subtype BSR_WCKCFG_Field is STM32F429x.Bit; @@ -599,28 +549,28 @@ package STM32F429x.SAI is -- BStatus register type BSR_Register is record - -- Overrun / underrun + -- Read-only. Overrun / underrun OVRUDR : BSR_OVRUDR_Field; - -- Mute detection + -- Read-only. Mute detection MUTEDET : BSR_MUTEDET_Field; - -- Wrong clock configuration flag + -- Read-only. Wrong clock configuration flag WCKCFG : BSR_WCKCFG_Field; - -- FIFO request + -- Read-only. FIFO request FREQ : BSR_FREQ_Field; - -- Codec not ready + -- Read-only. Codec not ready CNRDY : BSR_CNRDY_Field; - -- Anticipated frame synchronization detection + -- Read-only. Anticipated frame synchronization detection AFSDET : BSR_AFSDET_Field; - -- Late frame synchronization detection + -- Read-only. Late frame synchronization detection LFSDET : BSR_LFSDET_Field; -- unspecified Reserved_7_15 : STM32F429x.UInt9; - -- FIFO level threshold + -- Read-only. FIFO level threshold FLVL : BSR_FLVL_Field; -- unspecified Reserved_19_31 : STM32F429x.UInt13; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BSR_Register use record OVRUDR at 0 range 0 .. 0; @@ -635,10 +585,6 @@ package STM32F429x.SAI is Reserved_19_31 at 0 range 19 .. 31; end record; - --------------------- - -- BCLRFR_Register -- - --------------------- - subtype BCLRFR_OVRUDR_Field is STM32F429x.Bit; subtype BCLRFR_MUTEDET_Field is STM32F429x.Bit; subtype BCLRFR_WCKCFG_Field is STM32F429x.Bit; @@ -648,24 +594,24 @@ package STM32F429x.SAI is -- BClear flag register type BCLRFR_Register is record - -- Clear overrun / underrun + -- Write-only. Clear overrun / underrun OVRUDR : BCLRFR_OVRUDR_Field := 16#0#; - -- Mute detection flag + -- Write-only. Mute detection flag MUTEDET : BCLRFR_MUTEDET_Field := 16#0#; - -- Clear wrong clock configuration flag + -- Write-only. Clear wrong clock configuration flag WCKCFG : BCLRFR_WCKCFG_Field := 16#0#; -- unspecified Reserved_3_3 : STM32F429x.Bit := 16#0#; - -- Clear codec not ready flag + -- Write-only. Clear codec not ready flag CNRDY : BCLRFR_CNRDY_Field := 16#0#; - -- Clear anticipated frame synchronization detection flag + -- Write-only. Clear anticipated frame synchronization detection flag CAFSDET : BCLRFR_CAFSDET_Field := 16#0#; - -- Clear late frame synchronization detection flag + -- Write-only. Clear late frame synchronization detection flag LFSDET : BCLRFR_LFSDET_Field := 16#0#; -- unspecified Reserved_7_31 : STM32F429x.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BCLRFR_Register use record OVRUDR at 0 range 0 .. 0; @@ -685,61 +631,75 @@ package STM32F429x.SAI is -- Serial audio interface type SAI_Peripheral is record -- AConfiguration register 1 - ACR1 : ACR1_Register; + ACR1 : aliased ACR1_Register; + pragma Volatile_Full_Access (ACR1); -- AConfiguration register 2 - ACR2 : ACR2_Register; + ACR2 : aliased ACR2_Register; + pragma Volatile_Full_Access (ACR2); -- AFRCR - AFRCR : AFRCR_Register; + AFRCR : aliased AFRCR_Register; + pragma Volatile_Full_Access (AFRCR); -- ASlot register - ASLOTR : ASLOTR_Register; + ASLOTR : aliased ASLOTR_Register; + pragma Volatile_Full_Access (ASLOTR); -- AInterrupt mask register2 - AIM : AIM_Register; + AIM : aliased AIM_Register; + pragma Volatile_Full_Access (AIM); -- AStatus register - ASR : ASR_Register; + ASR : aliased ASR_Register; + pragma Volatile_Full_Access (ASR); -- AClear flag register - ACLRFR : ACLRFR_Register; + ACLRFR : aliased ACLRFR_Register; + pragma Volatile_Full_Access (ACLRFR); -- AData register - ADR : STM32F429x.Word; + ADR : aliased STM32F429x.UInt32; -- BConfiguration register 1 - BCR1 : BCR1_Register; + BCR1 : aliased BCR1_Register; + pragma Volatile_Full_Access (BCR1); -- BConfiguration register 2 - BCR2 : BCR2_Register; + BCR2 : aliased BCR2_Register; + pragma Volatile_Full_Access (BCR2); -- BFRCR - BFRCR : BFRCR_Register; + BFRCR : aliased BFRCR_Register; + pragma Volatile_Full_Access (BFRCR); -- BSlot register - BSLOTR : BSLOTR_Register; + BSLOTR : aliased BSLOTR_Register; + pragma Volatile_Full_Access (BSLOTR); -- BInterrupt mask register2 - BIM : BIM_Register; + BIM : aliased BIM_Register; + pragma Volatile_Full_Access (BIM); -- BStatus register - BSR : BSR_Register; + BSR : aliased BSR_Register; + pragma Volatile_Full_Access (BSR); -- BClear flag register - BCLRFR : BCLRFR_Register; + BCLRFR : aliased BCLRFR_Register; + pragma Volatile_Full_Access (BCLRFR); -- BData register - BDR : STM32F429x.Word; + BDR : aliased STM32F429x.UInt32; end record with Volatile; for SAI_Peripheral use record - ACR1 at 4 range 0 .. 31; - ACR2 at 8 range 0 .. 31; - AFRCR at 12 range 0 .. 31; - ASLOTR at 16 range 0 .. 31; - AIM at 20 range 0 .. 31; - ASR at 24 range 0 .. 31; - ACLRFR at 28 range 0 .. 31; - ADR at 32 range 0 .. 31; - BCR1 at 36 range 0 .. 31; - BCR2 at 40 range 0 .. 31; - BFRCR at 44 range 0 .. 31; - BSLOTR at 48 range 0 .. 31; - BIM at 52 range 0 .. 31; - BSR at 56 range 0 .. 31; - BCLRFR at 60 range 0 .. 31; - BDR at 64 range 0 .. 31; + ACR1 at 16#4# range 0 .. 31; + ACR2 at 16#8# range 0 .. 31; + AFRCR at 16#C# range 0 .. 31; + ASLOTR at 16#10# range 0 .. 31; + AIM at 16#14# range 0 .. 31; + ASR at 16#18# range 0 .. 31; + ACLRFR at 16#1C# range 0 .. 31; + ADR at 16#20# range 0 .. 31; + BCR1 at 16#24# range 0 .. 31; + BCR2 at 16#28# range 0 .. 31; + BFRCR at 16#2C# range 0 .. 31; + BSLOTR at 16#30# range 0 .. 31; + BIM at 16#34# range 0 .. 31; + BSR at 16#38# range 0 .. 31; + BCLRFR at 16#3C# range 0 .. 31; + BDR at 16#40# range 0 .. 31; end record; -- Serial audio interface SAI_Periph : aliased SAI_Peripheral - with Import, Address => System'To_Address (16#40015800#); + with Import, Address => SAI_Base; end STM32F429x.SAI; diff --git a/stm32f429i/stm32f429x/stm32f429x-sdio.ads b/stm32f429i/stm32f429x/stm32f429x-sdio.ads index 12b15f0..0dd263c 100644 --- a/stm32f429i/stm32f429x/stm32f429x-sdio.ads +++ b/stm32f429i/stm32f429x/stm32f429x-sdio.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,36 +14,62 @@ package STM32F429x.SDIO is -- Registers -- --------------- - -------------------- - -- POWER_Register -- - -------------------- - - subtype POWER_PWRCTRL_Field is STM32F429x.UInt2; + -- PWRCTRL + type POWER_PWRCTRL_Field is + (-- The clock to card is stopped. + Power_Off, + -- The card is clocked. + Power_On) + with Size => 2; + for POWER_PWRCTRL_Field use + (Power_Off => 0, + Power_On => 3); -- power control register type POWER_Register is record -- PWRCTRL - PWRCTRL : POWER_PWRCTRL_Field := 16#0#; + PWRCTRL : POWER_PWRCTRL_Field := STM32F429x.SDIO.Power_Off; -- unspecified Reserved_2_31 : STM32F429x.UInt30 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record PWRCTRL at 0 range 0 .. 1; Reserved_2_31 at 0 range 2 .. 31; end record; - -------------------- - -- CLKCR_Register -- - -------------------- - subtype CLKCR_CLKDIV_Field is STM32F429x.Byte; subtype CLKCR_CLKEN_Field is STM32F429x.Bit; subtype CLKCR_PWRSAV_Field is STM32F429x.Bit; subtype CLKCR_BYPASS_Field is STM32F429x.Bit; - subtype CLKCR_WIDBUS_Field is STM32F429x.UInt2; - subtype CLKCR_NEGEDGE_Field is STM32F429x.Bit; + + -- Wide bus mode enable bit + type CLKCR_WIDBUS_Field is + (-- Default bus mode: SDMMC_D0 is used. + Bus_Wide_1B, + -- 4-wide bus mode: SDMMC_D[3:0] used. + Bus_Wide_4B, + -- 8-wide bus mode: SDMMC_D[7:0] used. + Bus_Wide_8B) + with Size => 2; + for CLKCR_WIDBUS_Field use + (Bus_Wide_1B => 0, + Bus_Wide_4B => 1, + Bus_Wide_8B => 2); + + -- SDIO_CK dephasing selection bit + type CLKCR_NEGEDGE_Field is + (-- Cmd and Data changed on the SDMMCCLK falling edge succeeding the rising +-- edge of SDMMC_CK. + Edge_Rising, + -- Cmd and Data changed on the SDMMC_CK falling edge. + Edge_Falling) + with Size => 1; + for CLKCR_NEGEDGE_Field use + (Edge_Rising => 0, + Edge_Falling => 1); + subtype CLKCR_HWFC_EN_Field is STM32F429x.Bit; -- SDI clock control register @@ -55,15 +83,15 @@ package STM32F429x.SDIO is -- Clock divider bypass enable bit BYPASS : CLKCR_BYPASS_Field := 16#0#; -- Wide bus mode enable bit - WIDBUS : CLKCR_WIDBUS_Field := 16#0#; + WIDBUS : CLKCR_WIDBUS_Field := STM32F429x.SDIO.Bus_Wide_1B; -- SDIO_CK dephasing selection bit - NEGEDGE : CLKCR_NEGEDGE_Field := 16#0#; + NEGEDGE : CLKCR_NEGEDGE_Field := STM32F429x.SDIO.Edge_Rising; -- HW Flow Control enable HWFC_EN : CLKCR_HWFC_EN_Field := 16#0#; -- unspecified Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CLKCR_Register use record CLKDIV at 0 range 0 .. 7; @@ -76,12 +104,22 @@ package STM32F429x.SDIO is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------ - -- CMD_Register -- - ------------------ - subtype CMD_CMDINDEX_Field is STM32F429x.UInt6; - subtype CMD_WAITRESP_Field is STM32F429x.UInt2; + + -- Wait for response bits + type CMD_WAITRESP_Field is + (-- No response, expect CMDSENT flag. + No_Response, + -- Short response, expect CMDREND or CCRCFAIL flag. + Short_Response, + -- Long response, expect CMDREND or CCRCFAIL flag. + Long_Response) + with Size => 2; + for CMD_WAITRESP_Field use + (No_Response => 0, + Short_Response => 1, + Long_Response => 3); + subtype CMD_WAITINT_Field is STM32F429x.Bit; subtype CMD_WAITPEND_Field is STM32F429x.Bit; subtype CMD_CPSMEN_Field is STM32F429x.Bit; @@ -95,7 +133,7 @@ package STM32F429x.SDIO is -- Command index CMDINDEX : CMD_CMDINDEX_Field := 16#0#; -- Wait for response bits - WAITRESP : CMD_WAITRESP_Field := 16#0#; + WAITRESP : CMD_WAITRESP_Field := STM32F429x.SDIO.No_Response; -- CPSM waits for interrupt request WAITINT : CMD_WAITINT_Field := 16#0#; -- CPSM Waits for ends of data transfer (CmdPend internal signal). @@ -113,7 +151,7 @@ package STM32F429x.SDIO is -- unspecified Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMD_Register use record CMDINDEX at 0 range 0 .. 5; @@ -128,30 +166,22 @@ package STM32F429x.SDIO is Reserved_15_31 at 0 range 15 .. 31; end record; - ---------------------- - -- RESPCMD_Register -- - ---------------------- - subtype RESPCMD_RESPCMD_Field is STM32F429x.UInt6; -- command response register type RESPCMD_Register is record - -- Response command index + -- Read-only. Response command index RESPCMD : RESPCMD_RESPCMD_Field; -- unspecified Reserved_6_31 : STM32F429x.UInt26; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RESPCMD_Register use record RESPCMD at 0 range 0 .. 5; Reserved_6_31 at 0 range 6 .. 31; end record; - ------------------- - -- DLEN_Register -- - ------------------- - subtype DLEN_DATALENGTH_Field is STM32F429x.UInt25; -- data length register @@ -161,22 +191,89 @@ package STM32F429x.SDIO is -- unspecified Reserved_25_31 : STM32F429x.UInt7 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DLEN_Register use record DATALENGTH at 0 range 0 .. 24; Reserved_25_31 at 0 range 25 .. 31; end record; - -------------------- - -- DCTRL_Register -- - -------------------- - subtype DCTRL_DTEN_Field is STM32F429x.Bit; - subtype DCTRL_DTDIR_Field is STM32F429x.Bit; - subtype DCTRL_DTMODE_Field is STM32F429x.Bit; + + -- Data transfer direction selection + type DCTRL_DTDIR_Field is + (-- Data is sent to the card + Controller_To_Card, + -- Data is read from the card + Card_To_Controller) + with Size => 1; + for DCTRL_DTDIR_Field use + (Controller_To_Card => 0, + Card_To_Controller => 1); + + -- Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + type DCTRL_DTMODE_Field is + (-- Block data transfer + Block, + -- Stream or SDIO multibyte data transfer + Stream) + with Size => 1; + for DCTRL_DTMODE_Field use + (Block => 0, + Stream => 1); + subtype DCTRL_DMAEN_Field is STM32F429x.Bit; - subtype DCTRL_DBLOCKSIZE_Field is STM32F429x.UInt4; + + -- Data block size + type DCTRL_DBLOCKSIZE_Field is + (-- Block length = 2**0 = 1 byte + Block_1B, + -- Block length = 2**1 = 2 byte + Block_2B, + -- Block length = 2**2 = 4 byte + Block_4B, + -- Block length = 2**3 = 8 byte + Block_8B, + -- Block length = 2**4 = 16 byte + Block_16B, + -- Block length = 2**5 = 32 byte + Block_32B, + -- Block length = 2**6 = 64 byte + Block_64B, + -- Block length = 2**7 = 128 byte + Block_128B, + -- Block length = 2**8 = 256 byte + Block_256B, + -- Block length = 2**9 = 512 byte + Block_512B, + -- Block length = 2**10 = 1024 byte + Block_1024B, + -- Block length = 2**11 = 2048 byte + Block_2048B, + -- Block length = 2**12 = 4096 byte + Block_4096B, + -- Block length = 2**13 = 8192 byte + Block_8192B, + -- Block length = 2**14 = 16384 byte + Block_16384B) + with Size => 4; + for DCTRL_DBLOCKSIZE_Field use + (Block_1B => 0, + Block_2B => 1, + Block_4B => 2, + Block_8B => 3, + Block_16B => 4, + Block_32B => 5, + Block_64B => 6, + Block_128B => 7, + Block_256B => 8, + Block_512B => 9, + Block_1024B => 10, + Block_2048B => 11, + Block_4096B => 12, + Block_8192B => 13, + Block_16384B => 14); + subtype DCTRL_RWSTART_Field is STM32F429x.Bit; subtype DCTRL_RWSTOP_Field is STM32F429x.Bit; subtype DCTRL_RWMOD_Field is STM32F429x.Bit; @@ -187,14 +284,15 @@ package STM32F429x.SDIO is -- DTEN DTEN : DCTRL_DTEN_Field := 16#0#; -- Data transfer direction selection - DTDIR : DCTRL_DTDIR_Field := 16#0#; + DTDIR : DCTRL_DTDIR_Field := + STM32F429x.SDIO.Controller_To_Card; -- Data transfer mode selection 1: Stream or SDIO multibyte data -- transfer. - DTMODE : DCTRL_DTMODE_Field := 16#0#; + DTMODE : DCTRL_DTMODE_Field := STM32F429x.SDIO.Block; -- DMA enable bit DMAEN : DCTRL_DMAEN_Field := 16#0#; -- Data block size - DBLOCKSIZE : DCTRL_DBLOCKSIZE_Field := 16#0#; + DBLOCKSIZE : DCTRL_DBLOCKSIZE_Field := STM32F429x.SDIO.Block_1B; -- Read wait start RWSTART : DCTRL_RWSTART_Field := 16#0#; -- Read wait stop @@ -206,7 +304,7 @@ package STM32F429x.SDIO is -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DCTRL_Register use record DTEN at 0 range 0 .. 0; @@ -221,30 +319,22 @@ package STM32F429x.SDIO is Reserved_12_31 at 0 range 12 .. 31; end record; - --------------------- - -- DCOUNT_Register -- - --------------------- - subtype DCOUNT_DATACOUNT_Field is STM32F429x.UInt25; -- data counter register type DCOUNT_Register is record - -- Data count value + -- Read-only. Data count value DATACOUNT : DCOUNT_DATACOUNT_Field; -- unspecified Reserved_25_31 : STM32F429x.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DCOUNT_Register use record DATACOUNT at 0 range 0 .. 24; Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------ - -- STA_Register -- - ------------------ - subtype STA_CCRCFAIL_Field is STM32F429x.Bit; subtype STA_DCRCFAIL_Field is STM32F429x.Bit; subtype STA_CTIMEOUT_Field is STM32F429x.Bit; @@ -272,59 +362,61 @@ package STM32F429x.SDIO is -- status register type STA_Register is record - -- Command response received (CRC check failed) + -- Read-only. Command response received (CRC check failed) CCRCFAIL : STA_CCRCFAIL_Field; - -- Data block sent/received (CRC check failed) + -- Read-only. Data block sent/received (CRC check failed) DCRCFAIL : STA_DCRCFAIL_Field; - -- Command response timeout + -- Read-only. Command response timeout CTIMEOUT : STA_CTIMEOUT_Field; - -- Data timeout + -- Read-only. Data timeout DTIMEOUT : STA_DTIMEOUT_Field; - -- Transmit FIFO underrun error + -- Read-only. Transmit FIFO underrun error TXUNDERR : STA_TXUNDERR_Field; - -- Received FIFO overrun error + -- Read-only. Received FIFO overrun error RXOVERR : STA_RXOVERR_Field; - -- Command response received (CRC check passed) + -- Read-only. Command response received (CRC check passed) CMDREND : STA_CMDREND_Field; - -- Command sent (no response required) + -- Read-only. Command sent (no response required) CMDSENT : STA_CMDSENT_Field; - -- Data end (data counter, SDIDCOUNT, is zero) + -- Read-only. Data end (data counter, SDIDCOUNT, is zero) DATAEND : STA_DATAEND_Field; - -- Start bit not detected on all data signals in wide bus mode + -- Read-only. Start bit not detected on all data signals in wide bus + -- mode STBITERR : STA_STBITERR_Field; - -- Data block sent/received (CRC check passed) + -- Read-only. Data block sent/received (CRC check passed) DBCKEND : STA_DBCKEND_Field; - -- Command transfer in progress + -- Read-only. Command transfer in progress CMDACT : STA_CMDACT_Field; - -- Data transmit in progress + -- Read-only. Data transmit in progress TXACT : STA_TXACT_Field; - -- Data receive in progress + -- Read-only. Data receive in progress RXACT : STA_RXACT_Field; - -- Transmit FIFO half empty: at least 8 words can be written into the - -- FIFO + -- Read-only. Transmit FIFO half empty: at least 8 words can be written + -- into the FIFO TXFIFOHE : STA_TXFIFOHE_Field; - -- Receive FIFO half full: there are at least 8 words in the FIFO + -- Read-only. Receive FIFO half full: there are at least 8 words in the + -- FIFO RXFIFOHF : STA_RXFIFOHF_Field; - -- Transmit FIFO full + -- Read-only. Transmit FIFO full TXFIFOF : STA_TXFIFOF_Field; - -- Receive FIFO full + -- Read-only. Receive FIFO full RXFIFOF : STA_RXFIFOF_Field; - -- Transmit FIFO empty + -- Read-only. Transmit FIFO empty TXFIFOE : STA_TXFIFOE_Field; - -- Receive FIFO empty + -- Read-only. Receive FIFO empty RXFIFOE : STA_RXFIFOE_Field; - -- Data available in transmit FIFO + -- Read-only. Data available in transmit FIFO TXDAVL : STA_TXDAVL_Field; - -- Data available in receive FIFO + -- Read-only. Data available in receive FIFO RXDAVL : STA_RXDAVL_Field; - -- SDIO interrupt received + -- Read-only. SDIO interrupt received SDIOIT : STA_SDIOIT_Field; - -- CE-ATA command completion signal received for CMD61 + -- Read-only. CE-ATA command completion signal received for CMD61 CEATAEND : STA_CEATAEND_Field; -- unspecified Reserved_24_31 : STM32F429x.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for STA_Register use record CCRCFAIL at 0 range 0 .. 0; @@ -354,10 +446,6 @@ package STM32F429x.SDIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------ - -- ICR_Register -- - ------------------ - subtype ICR_CCRCFAILC_Field is STM32F429x.Bit; subtype ICR_DCRCFAILC_Field is STM32F429x.Bit; subtype ICR_CTIMEOUTC_Field is STM32F429x.Bit; @@ -405,7 +493,7 @@ package STM32F429x.SDIO is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ICR_Register use record CCRCFAILC at 0 range 0 .. 0; @@ -425,10 +513,6 @@ package STM32F429x.SDIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ------------------- - -- MASK_Register -- - ------------------- - subtype MASK_CCRCFAILIE_Field is STM32F429x.Bit; subtype MASK_DCRCFAILIE_Field is STM32F429x.Bit; subtype MASK_CTIMEOUTIE_Field is STM32F429x.Bit; @@ -507,7 +591,7 @@ package STM32F429x.SDIO is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MASK_Register use record CCRCFAILIE at 0 range 0 .. 0; @@ -537,20 +621,17 @@ package STM32F429x.SDIO is Reserved_24_31 at 0 range 24 .. 31; end record; - ---------------------- - -- FIFOCNT_Register -- - ---------------------- - subtype FIFOCNT_FIFOCOUNT_Field is STM32F429x.UInt24; -- FIFO counter register type FIFOCNT_Register is record - -- Remaining number of words to be written to or read from the FIFO. + -- Read-only. Remaining number of words to be written to or read from + -- the FIFO. FIFOCOUNT : FIFOCNT_FIFOCOUNT_Field; -- unspecified Reserved_24_31 : STM32F429x.Byte; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FIFOCNT_Register use record FIFOCOUNT at 0 range 0 .. 23; @@ -564,67 +645,78 @@ package STM32F429x.SDIO is -- Secure digital input/output interface type SDIO_Peripheral is record -- power control register - POWER : POWER_Register; + POWER : aliased POWER_Register; + pragma Volatile_Full_Access (POWER); -- SDI clock control register - CLKCR : CLKCR_Register; + CLKCR : aliased CLKCR_Register; + pragma Volatile_Full_Access (CLKCR); -- argument register - ARG : STM32F429x.Word; + ARG : aliased STM32F429x.UInt32; -- command register - CMD : CMD_Register; + CMD : aliased CMD_Register; + pragma Volatile_Full_Access (CMD); -- command response register - RESPCMD : RESPCMD_Register; + RESPCMD : aliased RESPCMD_Register; + pragma Volatile_Full_Access (RESPCMD); -- response 1..4 register - RESP1 : STM32F429x.Word; + RESP1 : aliased STM32F429x.UInt32; -- response 1..4 register - RESP2 : STM32F429x.Word; + RESP2 : aliased STM32F429x.UInt32; -- response 1..4 register - RESP3 : STM32F429x.Word; + RESP3 : aliased STM32F429x.UInt32; -- response 1..4 register - RESP4 : STM32F429x.Word; + RESP4 : aliased STM32F429x.UInt32; -- data timer register - DTIMER : STM32F429x.Word; + DTIMER : aliased STM32F429x.UInt32; -- data length register - DLEN : DLEN_Register; + DLEN : aliased DLEN_Register; + pragma Volatile_Full_Access (DLEN); -- data control register - DCTRL : DCTRL_Register; + DCTRL : aliased DCTRL_Register; + pragma Volatile_Full_Access (DCTRL); -- data counter register - DCOUNT : DCOUNT_Register; + DCOUNT : aliased DCOUNT_Register; + pragma Volatile_Full_Access (DCOUNT); -- status register - STA : STA_Register; + STA : aliased STA_Register; + pragma Volatile_Full_Access (STA); -- interrupt clear register - ICR : ICR_Register; + ICR : aliased ICR_Register; + pragma Volatile_Full_Access (ICR); -- mask register - MASK : MASK_Register; + MASK : aliased MASK_Register; + pragma Volatile_Full_Access (MASK); -- FIFO counter register - FIFOCNT : FIFOCNT_Register; + FIFOCNT : aliased FIFOCNT_Register; + pragma Volatile_Full_Access (FIFOCNT); -- data FIFO register - FIFO : STM32F429x.Word; + FIFO : aliased STM32F429x.UInt32; end record with Volatile; for SDIO_Peripheral use record - POWER at 0 range 0 .. 31; - CLKCR at 4 range 0 .. 31; - ARG at 8 range 0 .. 31; - CMD at 12 range 0 .. 31; - RESPCMD at 16 range 0 .. 31; - RESP1 at 20 range 0 .. 31; - RESP2 at 24 range 0 .. 31; - RESP3 at 28 range 0 .. 31; - RESP4 at 32 range 0 .. 31; - DTIMER at 36 range 0 .. 31; - DLEN at 40 range 0 .. 31; - DCTRL at 44 range 0 .. 31; - DCOUNT at 48 range 0 .. 31; - STA at 52 range 0 .. 31; - ICR at 56 range 0 .. 31; - MASK at 60 range 0 .. 31; - FIFOCNT at 72 range 0 .. 31; - FIFO at 128 range 0 .. 31; + POWER at 16#0# range 0 .. 31; + CLKCR at 16#4# range 0 .. 31; + ARG at 16#8# range 0 .. 31; + CMD at 16#C# range 0 .. 31; + RESPCMD at 16#10# range 0 .. 31; + RESP1 at 16#14# range 0 .. 31; + RESP2 at 16#18# range 0 .. 31; + RESP3 at 16#1C# range 0 .. 31; + RESP4 at 16#20# range 0 .. 31; + DTIMER at 16#24# range 0 .. 31; + DLEN at 16#28# range 0 .. 31; + DCTRL at 16#2C# range 0 .. 31; + DCOUNT at 16#30# range 0 .. 31; + STA at 16#34# range 0 .. 31; + ICR at 16#38# range 0 .. 31; + MASK at 16#3C# range 0 .. 31; + FIFOCNT at 16#48# range 0 .. 31; + FIFO at 16#80# range 0 .. 31; end record; -- Secure digital input/output interface SDIO_Periph : aliased SDIO_Peripheral - with Import, Address => System'To_Address (16#40012C00#); + with Import, Address => SDIO_Base; end STM32F429x.SDIO; diff --git a/stm32f429i/stm32f429x/stm32f429x-spi.ads b/stm32f429i/stm32f429x/stm32f429x-spi.ads index 5580f34..000e17e 100644 --- a/stm32f429i/stm32f429x/stm32f429x-spi.ads +++ b/stm32f429i/stm32f429x/stm32f429x-spi.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.SPI is -- Registers -- --------------- - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_CPHA_Field is STM32F429x.Bit; subtype CR1_CPOL_Field is STM32F429x.Bit; subtype CR1_MSTR_Field is STM32F429x.Bit; @@ -62,9 +60,9 @@ package STM32F429x.SPI is -- Bidirectional data mode enable BIDIMODE : CR1_BIDIMODE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record CPHA at 0 range 0 .. 0; @@ -84,10 +82,6 @@ package STM32F429x.SPI is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_RXDMAEN_Field is STM32F429x.Bit; subtype CR2_TXDMAEN_Field is STM32F429x.Bit; subtype CR2_SSOE_Field is STM32F429x.Bit; @@ -117,7 +111,7 @@ package STM32F429x.SPI is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record RXDMAEN at 0 range 0 .. 0; @@ -131,10 +125,6 @@ package STM32F429x.SPI is Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_RXNE_Field is STM32F429x.Bit; subtype SR_TXE_Field is STM32F429x.Bit; subtype SR_CHSIDE_Field is STM32F429x.Bit; @@ -147,28 +137,28 @@ package STM32F429x.SPI is -- status register type SR_Register is record - -- Receive buffer not empty + -- Read-only. Receive buffer not empty RXNE : SR_RXNE_Field := 16#0#; - -- Transmit buffer empty + -- Read-only. Transmit buffer empty TXE : SR_TXE_Field := 16#1#; - -- Channel side + -- Read-only. Channel side CHSIDE : SR_CHSIDE_Field := 16#0#; - -- Underrun flag + -- Read-only. Underrun flag UDR : SR_UDR_Field := 16#0#; -- CRC error flag CRCERR : SR_CRCERR_Field := 16#0#; - -- Mode fault + -- Read-only. Mode fault MODF : SR_MODF_Field := 16#0#; - -- Overrun flag + -- Read-only. Overrun flag OVR : SR_OVR_Field := 16#0#; - -- Busy flag + -- Read-only. Busy flag BSY : SR_BSY_Field := 16#0#; - -- TI frame format error + -- Read-only. TI frame format error TIFRFE : SR_TIFRFE_Field := 16#0#; -- unspecified Reserved_9_31 : STM32F429x.UInt23 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record RXNE at 0 range 0 .. 0; @@ -183,90 +173,70 @@ package STM32F429x.SPI is Reserved_9_31 at 0 range 9 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - - subtype DR_DR_Field is STM32F429x.Short; + subtype DR_DR_Field is STM32F429x.UInt16; -- data register type DR_Register is record -- Data register DR : DR_DR_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- CRCPR_Register -- - -------------------- - - subtype CRCPR_CRCPOLY_Field is STM32F429x.Short; + subtype CRCPR_CRCPOLY_Field is STM32F429x.UInt16; -- CRC polynomial register type CRCPR_Register is record -- CRC polynomial register CRCPOLY : CRCPR_CRCPOLY_Field := 16#7#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCPR_Register use record CRCPOLY at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- RXCRCR_Register -- - --------------------- - - subtype RXCRCR_RxCRC_Field is STM32F429x.Short; + subtype RXCRCR_RxCRC_Field is STM32F429x.UInt16; -- RX CRC register type RXCRCR_Register is record - -- Rx CRC register + -- Read-only. Rx CRC register RxCRC : RXCRCR_RxCRC_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RXCRCR_Register use record RxCRC at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------- - -- TXCRCR_Register -- - --------------------- - - subtype TXCRCR_TxCRC_Field is STM32F429x.Short; + subtype TXCRCR_TxCRC_Field is STM32F429x.UInt16; -- TX CRC register type TXCRCR_Register is record - -- Tx CRC register + -- Read-only. Tx CRC register TxCRC : TXCRCR_TxCRC_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for TXCRCR_Register use record TxCRC at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- I2SCFGR_Register -- - ---------------------- - subtype I2SCFGR_CHLEN_Field is STM32F429x.Bit; subtype I2SCFGR_DATLEN_Field is STM32F429x.UInt2; subtype I2SCFGR_CKPOL_Field is STM32F429x.Bit; @@ -299,7 +269,7 @@ package STM32F429x.SPI is -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for I2SCFGR_Register use record CHLEN at 0 range 0 .. 0; @@ -314,10 +284,6 @@ package STM32F429x.SPI is Reserved_12_31 at 0 range 12 .. 31; end record; - -------------------- - -- I2SPR_Register -- - -------------------- - subtype I2SPR_I2SDIV_Field is STM32F429x.Byte; subtype I2SPR_ODD_Field is STM32F429x.Bit; subtype I2SPR_MCKOE_Field is STM32F429x.Bit; @@ -333,7 +299,7 @@ package STM32F429x.SPI is -- unspecified Reserved_10_31 : STM32F429x.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for I2SPR_Register use record I2SDIV at 0 range 0 .. 7; @@ -349,68 +315,77 @@ package STM32F429x.SPI is -- Serial peripheral interface type SPI_Peripheral is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- CRC polynomial register - CRCPR : CRCPR_Register; + CRCPR : aliased CRCPR_Register; + pragma Volatile_Full_Access (CRCPR); -- RX CRC register - RXCRCR : RXCRCR_Register; + RXCRCR : aliased RXCRCR_Register; + pragma Volatile_Full_Access (RXCRCR); -- TX CRC register - TXCRCR : TXCRCR_Register; + TXCRCR : aliased TXCRCR_Register; + pragma Volatile_Full_Access (TXCRCR); -- I2S configuration register - I2SCFGR : I2SCFGR_Register; + I2SCFGR : aliased I2SCFGR_Register; + pragma Volatile_Full_Access (I2SCFGR); -- I2S prescaler register - I2SPR : I2SPR_Register; + I2SPR : aliased I2SPR_Register; + pragma Volatile_Full_Access (I2SPR); end record with Volatile; for SPI_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SR at 8 range 0 .. 31; - DR at 12 range 0 .. 31; - CRCPR at 16 range 0 .. 31; - RXCRCR at 20 range 0 .. 31; - TXCRCR at 24 range 0 .. 31; - I2SCFGR at 28 range 0 .. 31; - I2SPR at 32 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SR at 16#8# range 0 .. 31; + DR at 16#C# range 0 .. 31; + CRCPR at 16#10# range 0 .. 31; + RXCRCR at 16#14# range 0 .. 31; + TXCRCR at 16#18# range 0 .. 31; + I2SCFGR at 16#1C# range 0 .. 31; + I2SPR at 16#20# range 0 .. 31; end record; -- Serial peripheral interface I2S2ext_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40003400#); + with Import, Address => I2S2ext_Base; -- Serial peripheral interface - SPI2_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40003800#); + I2S3ext_Periph : aliased SPI_Peripheral + with Import, Address => I2S3ext_Base; -- Serial peripheral interface - SPI3_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40003C00#); + SPI1_Periph : aliased SPI_Peripheral + with Import, Address => SPI1_Base; -- Serial peripheral interface - I2S3ext_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40004000#); + SPI2_Periph : aliased SPI_Peripheral + with Import, Address => SPI2_Base; -- Serial peripheral interface - SPI1_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40013000#); + SPI3_Periph : aliased SPI_Peripheral + with Import, Address => SPI3_Base; -- Serial peripheral interface SPI4_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40013400#); + with Import, Address => SPI4_Base; -- Serial peripheral interface SPI5_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40015000#); + with Import, Address => SPI5_Base; -- Serial peripheral interface SPI6_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40015400#); + with Import, Address => SPI6_Base; end STM32F429x.SPI; diff --git a/stm32f429i/stm32f429x/stm32f429x-syscfg.ads b/stm32f429i/stm32f429x/stm32f429x-syscfg.ads index 0e70df1..d1e79d4 100644 --- a/stm32f429i/stm32f429x/stm32f429x-syscfg.ads +++ b/stm32f429i/stm32f429x/stm32f429x-syscfg.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.SYSCFG is -- Registers -- --------------- - -------------------- - -- MEMRM_Register -- - -------------------- - subtype MEMRM_MEM_MODE_Field is STM32F429x.UInt3; subtype MEMRM_FB_MODE_Field is STM32F429x.Bit; subtype MEMRM_SWP_FMC_Field is STM32F429x.UInt2; @@ -35,7 +33,7 @@ package STM32F429x.SYSCFG is -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for MEMRM_Register use record MEM_MODE at 0 range 0 .. 2; @@ -46,10 +44,6 @@ package STM32F429x.SYSCFG is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------ - -- PMC_Register -- - ------------------ - subtype PMC_ADC1DC2_Field is STM32F429x.Bit; subtype PMC_ADC2DC2_Field is STM32F429x.Bit; subtype PMC_ADC3DC2_Field is STM32F429x.Bit; @@ -58,7 +52,7 @@ package STM32F429x.SYSCFG is -- peripheral mode configuration register type PMC_Register is record -- unspecified - Reserved_0_15 : STM32F429x.Short := 16#0#; + Reserved_0_15 : STM32F429x.UInt16 := 16#0#; -- ADC1DC2 ADC1DC2 : PMC_ADC1DC2_Field := 16#0#; -- ADC2DC2 @@ -72,7 +66,7 @@ package STM32F429x.SYSCFG is -- unspecified Reserved_24_31 : STM32F429x.Byte := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PMC_Register use record Reserved_0_15 at 0 range 0 .. 15; @@ -84,14 +78,6 @@ package STM32F429x.SYSCFG is Reserved_24_31 at 0 range 24 .. 31; end record; - --------------------- - -- EXTICR_Register -- - --------------------- - - ------------------ - -- EXTICR1.EXTI -- - ------------------ - -- EXTICR1_EXTI array element subtype EXTICR1_EXTI_Element is STM32F429x.UInt4; @@ -106,7 +92,7 @@ package STM32F429x.SYSCFG is case As_Array is when False => -- EXTI as a value - Val : STM32F429x.Short; + Val : STM32F429x.UInt16; when True => -- EXTI as an array Arr : EXTICR1_EXTI_Field_Array; @@ -120,39 +106,161 @@ package STM32F429x.SYSCFG is end record; -- external interrupt configuration register 1 - type EXTICR_Register is record + type EXTICR1_Register is record -- EXTI x configuration (x = 0 to 3) EXTI : EXTICR1_EXTI_Field := (As_Array => False, Val => 16#0#); -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EXTICR1_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- EXTICR2_EXTI array element + subtype EXTICR2_EXTI_Element is STM32F429x.UInt4; + + -- EXTICR2_EXTI array + type EXTICR2_EXTI_Field_Array is array (4 .. 7) of EXTICR2_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR2_EXTI + type EXTICR2_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : STM32F429x.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR2_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR2_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 2 + type EXTICR2_Register is record + -- EXTI x configuration (x = 4 to 7) + EXTI : EXTICR2_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EXTICR2_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- EXTICR3_EXTI array element + subtype EXTICR3_EXTI_Element is STM32F429x.UInt4; + + -- EXTICR3_EXTI array + type EXTICR3_EXTI_Field_Array is array (8 .. 11) of EXTICR3_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR3_EXTI + type EXTICR3_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : STM32F429x.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR3_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR3_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 3 + type EXTICR3_Register is record + -- EXTI x configuration (x = 8 to 11) + EXTI : EXTICR3_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for EXTICR_Register use record + for EXTICR3_Register use record EXTI at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------- - -- CMPCR_Register -- - -------------------- + -- EXTICR4_EXTI array element + subtype EXTICR4_EXTI_Element is STM32F429x.UInt4; + + -- EXTICR4_EXTI array + type EXTICR4_EXTI_Field_Array is array (12 .. 15) of EXTICR4_EXTI_Element + with Component_Size => 4, Size => 16; + + -- Type definition for EXTICR4_EXTI + type EXTICR4_EXTI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EXTI as a value + Val : STM32F429x.UInt16; + when True => + -- EXTI as an array + Arr : EXTICR4_EXTI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for EXTICR4_EXTI_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- external interrupt configuration register 4 + type EXTICR4_Register is record + -- EXTI x configuration (x = 12 to 15) + EXTI : EXTICR4_EXTI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EXTICR4_Register use record + EXTI at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; subtype CMPCR_CMP_PD_Field is STM32F429x.Bit; subtype CMPCR_READY_Field is STM32F429x.Bit; -- Compensation cell control register type CMPCR_Register is record - -- Compensation cell power-down + -- Read-only. Compensation cell power-down CMP_PD : CMPCR_CMP_PD_Field; -- unspecified Reserved_1_7 : STM32F429x.UInt7; - -- READY + -- Read-only. READY READY : CMPCR_READY_Field; -- unspecified Reserved_9_31 : STM32F429x.UInt23; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CMPCR_Register use record CMP_PD at 0 range 0 .. 0; @@ -168,34 +276,41 @@ package STM32F429x.SYSCFG is -- System configuration controller type SYSCFG_Peripheral is record -- memory remap register - MEMRM : MEMRM_Register; + MEMRM : aliased MEMRM_Register; + pragma Volatile_Full_Access (MEMRM); -- peripheral mode configuration register - PMC : PMC_Register; + PMC : aliased PMC_Register; + pragma Volatile_Full_Access (PMC); -- external interrupt configuration register 1 - EXTICR1 : EXTICR_Register; + EXTICR1 : aliased EXTICR1_Register; + pragma Volatile_Full_Access (EXTICR1); -- external interrupt configuration register 2 - EXTICR2 : EXTICR_Register; + EXTICR2 : aliased EXTICR2_Register; + pragma Volatile_Full_Access (EXTICR2); -- external interrupt configuration register 3 - EXTICR3 : EXTICR_Register; + EXTICR3 : aliased EXTICR3_Register; + pragma Volatile_Full_Access (EXTICR3); -- external interrupt configuration register 4 - EXTICR4 : EXTICR_Register; + EXTICR4 : aliased EXTICR4_Register; + pragma Volatile_Full_Access (EXTICR4); -- Compensation cell control register - CMPCR : CMPCR_Register; + CMPCR : aliased CMPCR_Register; + pragma Volatile_Full_Access (CMPCR); end record with Volatile; for SYSCFG_Peripheral use record - MEMRM at 0 range 0 .. 31; - PMC at 4 range 0 .. 31; - EXTICR1 at 8 range 0 .. 31; - EXTICR2 at 12 range 0 .. 31; - EXTICR3 at 16 range 0 .. 31; - EXTICR4 at 20 range 0 .. 31; - CMPCR at 32 range 0 .. 31; + MEMRM at 16#0# range 0 .. 31; + PMC at 16#4# range 0 .. 31; + EXTICR1 at 16#8# range 0 .. 31; + EXTICR2 at 16#C# range 0 .. 31; + EXTICR3 at 16#10# range 0 .. 31; + EXTICR4 at 16#14# range 0 .. 31; + CMPCR at 16#20# range 0 .. 31; end record; -- System configuration controller SYSCFG_Periph : aliased SYSCFG_Peripheral - with Import, Address => System'To_Address (16#40013800#); + with Import, Address => SYSCFG_Base; end STM32F429x.SYSCFG; diff --git a/stm32f429i/stm32f429x/stm32f429x-tim.ads b/stm32f429i/stm32f429x/stm32f429x-tim.ads index 959aae9..2be5b4f 100644 --- a/stm32f429i/stm32f429x/stm32f429x-tim.ads +++ b/stm32f429i/stm32f429x/stm32f429x-tim.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.TIM is -- Registers -- --------------- - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_CEN_Field is STM32F429x.Bit; subtype CR1_UDIS_Field is STM32F429x.Bit; subtype CR1_URS_Field is STM32F429x.Bit; @@ -46,7 +44,7 @@ package STM32F429x.TIM is -- unspecified Reserved_10_31 : STM32F429x.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record CEN at 0 range 0 .. 0; @@ -60,10 +58,6 @@ package STM32F429x.TIM is Reserved_10_31 at 0 range 10 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_CCPC_Field is STM32F429x.Bit; subtype CR2_CCUS_Field is STM32F429x.Bit; subtype CR2_CCDS_Field is STM32F429x.Bit; @@ -108,7 +102,7 @@ package STM32F429x.TIM is -- unspecified Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR2_Register use record CCPC at 0 range 0 .. 0; @@ -127,10 +121,6 @@ package STM32F429x.TIM is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------- - -- SMCR_Register -- - ------------------- - subtype SMCR_SMS_Field is STM32F429x.UInt3; subtype SMCR_TS_Field is STM32F429x.UInt3; subtype SMCR_MSM_Field is STM32F429x.Bit; @@ -158,9 +148,9 @@ package STM32F429x.TIM is -- External trigger polarity ETP : SMCR_ETP_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SMCR_Register use record SMS at 0 range 0 .. 2; @@ -174,10 +164,6 @@ package STM32F429x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- DIER_Register -- - ------------------- - subtype DIER_UIE_Field is STM32F429x.Bit; subtype DIER_CC1IE_Field is STM32F429x.Bit; subtype DIER_CC2IE_Field is STM32F429x.Bit; @@ -229,7 +215,7 @@ package STM32F429x.TIM is -- unspecified Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DIER_Register use record UIE at 0 range 0 .. 0; @@ -250,10 +236,6 @@ package STM32F429x.TIM is Reserved_15_31 at 0 range 15 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_UIF_Field is STM32F429x.Bit; subtype SR_CC1IF_Field is STM32F429x.Bit; subtype SR_CC2IF_Field is STM32F429x.Bit; @@ -298,7 +280,7 @@ package STM32F429x.TIM is -- unspecified Reserved_13_31 : STM32F429x.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record UIF at 0 range 0 .. 0; @@ -317,10 +299,6 @@ package STM32F429x.TIM is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------ - -- EGR_Register -- - ------------------ - subtype EGR_UG_Field is STM32F429x.Bit; subtype EGR_CC1G_Field is STM32F429x.Bit; subtype EGR_CC2G_Field is STM32F429x.Bit; @@ -332,26 +310,26 @@ package STM32F429x.TIM is -- event generation register type EGR_Register is record - -- Update generation + -- Write-only. Update generation UG : EGR_UG_Field := 16#0#; - -- Capture/compare 1 generation + -- Write-only. Capture/compare 1 generation CC1G : EGR_CC1G_Field := 16#0#; - -- Capture/compare 2 generation + -- Write-only. Capture/compare 2 generation CC2G : EGR_CC2G_Field := 16#0#; - -- Capture/compare 3 generation + -- Write-only. Capture/compare 3 generation CC3G : EGR_CC3G_Field := 16#0#; - -- Capture/compare 4 generation + -- Write-only. Capture/compare 4 generation CC4G : EGR_CC4G_Field := 16#0#; - -- Capture/Compare control update generation + -- Write-only. Capture/Compare control update generation COMG : EGR_COMG_Field := 16#0#; - -- Trigger generation + -- Write-only. Trigger generation TG : EGR_TG_Field := 16#0#; - -- Break generation + -- Write-only. Break generation BG : EGR_BG_Field := 16#0#; -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for EGR_Register use record UG at 0 range 0 .. 0; @@ -365,10 +343,6 @@ package STM32F429x.TIM is Reserved_8_31 at 0 range 8 .. 31; end record; - --------------------------- - -- CCMR1_Output_Register -- - --------------------------- - subtype CCMR1_Output_CC1S_Field is STM32F429x.UInt2; subtype CCMR1_Output_OC1FE_Field is STM32F429x.Bit; subtype CCMR1_Output_OC1PE_Field is STM32F429x.Bit; @@ -403,9 +377,9 @@ package STM32F429x.TIM is -- Output Compare 2 clear enable OC2CE : CCMR1_Output_OC2CE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR1_Output_Register use record CC1S at 0 range 0 .. 1; @@ -421,10 +395,6 @@ package STM32F429x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------------- - -- CCMR1_Input_Register -- - -------------------------- - subtype CCMR1_Input_CC1S_Field is STM32F429x.UInt2; subtype CCMR1_Input_ICPCS_Field is STM32F429x.UInt2; subtype CCMR1_Input_IC1F_Field is STM32F429x.UInt4; @@ -447,9 +417,9 @@ package STM32F429x.TIM is -- Input capture 2 filter IC2F : CCMR1_Input_IC2F_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR1_Input_Register use record CC1S at 0 range 0 .. 1; @@ -461,10 +431,6 @@ package STM32F429x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - --------------------------- - -- CCMR2_Output_Register -- - --------------------------- - subtype CCMR2_Output_CC3S_Field is STM32F429x.UInt2; subtype CCMR2_Output_OC3FE_Field is STM32F429x.Bit; subtype CCMR2_Output_OC3PE_Field is STM32F429x.Bit; @@ -499,9 +465,9 @@ package STM32F429x.TIM is -- Output compare 4 clear enable OC4CE : CCMR2_Output_OC4CE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR2_Output_Register use record CC3S at 0 range 0 .. 1; @@ -517,10 +483,6 @@ package STM32F429x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------------- - -- CCMR2_Input_Register -- - -------------------------- - subtype CCMR2_Input_CC3S_Field is STM32F429x.UInt2; subtype CCMR2_Input_IC3PSC_Field is STM32F429x.UInt2; subtype CCMR2_Input_IC3F_Field is STM32F429x.UInt4; @@ -543,9 +505,9 @@ package STM32F429x.TIM is -- Input capture 4 filter IC4F : CCMR2_Input_IC4F_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCMR2_Input_Register use record CC3S at 0 range 0 .. 1; @@ -557,10 +519,6 @@ package STM32F429x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- CCER_Register -- - ------------------- - subtype CCER_CC1E_Field is STM32F429x.Bit; subtype CCER_CC1P_Field is STM32F429x.Bit; subtype CCER_CC1NE_Field is STM32F429x.Bit; @@ -609,7 +567,7 @@ package STM32F429x.TIM is -- unspecified Reserved_14_31 : STM32F429x.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CCER_Register use record CC1E at 0 range 0 .. 0; @@ -629,70 +587,54 @@ package STM32F429x.TIM is Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------ - -- CNT_Register -- - ------------------ - - subtype CNT_CNT_Field is STM32F429x.Short; + subtype CNT_CNT_Field is STM32F429x.UInt16; -- counter type CNT_Register is record -- counter value CNT : CNT_CNT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CNT_Register use record CNT at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- PSC_Register -- - ------------------ - - subtype PSC_PSC_Field is STM32F429x.Short; + subtype PSC_PSC_Field is STM32F429x.UInt16; -- prescaler type PSC_Register is record -- Prescaler value PSC : PSC_PSC_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for PSC_Register use record PSC at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- ARR_Register -- - ------------------ - - subtype ARR_ARR_Field is STM32F429x.Short; + subtype ARR_ARR_Field is STM32F429x.UInt16; -- auto-reload register type ARR_Register is record -- Auto-reload value ARR : ARR_ARR_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for ARR_Register use record ARR at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- RCR_Register -- - ------------------ - subtype RCR_REP_Field is STM32F429x.Byte; -- repetition counter register @@ -702,36 +644,76 @@ package STM32F429x.TIM is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for RCR_Register use record REP at 0 range 0 .. 7; Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- CCR_Register -- - ------------------ - - subtype CCR1_CCR1_Field is STM32F429x.Short; + subtype CCR1_CCR1_Field is STM32F429x.UInt16; -- capture/compare register 1 - type CCR_Register is record + type CCR1_Register is record -- Capture/Compare 1 value CCR1 : CCR1_CCR1_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CCR_Register use record + for CCR1_Register use record CCR1 at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------- - -- BDTR_Register -- - ------------------- + subtype CCR2_CCR2_Field is STM32F429x.UInt16; + + -- capture/compare register 2 + type CCR2_Register is record + -- Capture/Compare 2 value + CCR2 : CCR2_CCR2_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR2_Register use record + CCR2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCR3_CCR3_Field is STM32F429x.UInt16; + + -- capture/compare register 3 + type CCR3_Register is record + -- Capture/Compare value + CCR3 : CCR3_CCR3_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR3_Register use record + CCR3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CCR4_CCR4_Field is STM32F429x.UInt16; + + -- capture/compare register 4 + type CCR4_Register is record + -- Capture/Compare value + CCR4 : CCR4_CCR4_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR4_Register use record + CCR4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; subtype BDTR_DTG_Field is STM32F429x.Byte; subtype BDTR_LOCK_Field is STM32F429x.UInt2; @@ -761,9 +743,9 @@ package STM32F429x.TIM is -- Main output enable MOE : BDTR_MOE_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BDTR_Register use record DTG at 0 range 0 .. 7; @@ -777,10 +759,6 @@ package STM32F429x.TIM is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- DCR_Register -- - ------------------ - subtype DCR_DBA_Field is STM32F429x.UInt5; subtype DCR_DBL_Field is STM32F429x.UInt5; @@ -795,7 +773,7 @@ package STM32F429x.TIM is -- unspecified Reserved_13_31 : STM32F429x.UInt19 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DCR_Register use record DBA at 0 range 0 .. 4; @@ -804,481 +782,1644 @@ package STM32F429x.TIM is Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------- - -- DMAR_Register -- - ------------------- - - subtype DMAR_DMAB_Field is STM32F429x.Short; + subtype DMAR_DMAB_Field is STM32F429x.UInt16; -- DMA address for full transfer type DMAR_Register is record -- DMA register for burst accesses DMAB : DMAR_DMAB_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DMAR_Register use record DMAB at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CCR_Register -- - ------------------ - - subtype CCR2_CCR2_L_Field is STM32F429x.Short; - subtype CCR2_CCR2_H_Field is STM32F429x.Short; - - -- capture/compare register 2 - type CCR_Register_1 is record - -- Low Capture/Compare 2 value - CCR2_L : CCR2_CCR2_L_Field := 16#0#; - -- High Capture/Compare 2 value - CCR2_H : CCR2_CCR2_H_Field := 16#0#; + -- control register 2 + type CR2_Register_1 is record + -- unspecified + Reserved_0_2 : STM32F429x.UInt3 := 16#0#; + -- Capture/compare DMA selection + CCDS : CR2_CCDS_Field := 16#0#; + -- Master mode selection + MMS : CR2_MMS_Field := 16#0#; + -- TI1 selection + TI1S : CR2_TI1S_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CCR_Register_1 use record - CCR2_L at 0 range 0 .. 15; - CCR2_H at 0 range 16 .. 31; + for CR2_Register_1 use record + Reserved_0_2 at 0 range 0 .. 2; + CCDS at 0 range 3 .. 3; + MMS at 0 range 4 .. 6; + TI1S at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; end record; - ----------------- - -- OR_Register -- - ----------------- - - subtype OR_ITR1_RMP_Field is STM32F429x.UInt2; - - -- TIM5 option register - type OR_Register is record + -- DMA/Interrupt enable register + type DIER_Register_1 is record + -- Update interrupt enable + UIE : DIER_UIE_Field := 16#0#; + -- Capture/Compare 1 interrupt enable + CC1IE : DIER_CC1IE_Field := 16#0#; + -- Capture/Compare 2 interrupt enable + CC2IE : DIER_CC2IE_Field := 16#0#; + -- Capture/Compare 3 interrupt enable + CC3IE : DIER_CC3IE_Field := 16#0#; + -- Capture/Compare 4 interrupt enable + CC4IE : DIER_CC4IE_Field := 16#0#; -- unspecified - Reserved_0_9 : STM32F429x.UInt10 := 16#0#; - -- Timer Input 4 remap - ITR1_RMP : OR_ITR1_RMP_Field := 16#0#; + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- Trigger interrupt enable + TIE : DIER_TIE_Field := 16#0#; -- unspecified - Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + Reserved_7_7 : STM32F429x.Bit := 16#0#; + -- Update DMA request enable + UDE : DIER_UDE_Field := 16#0#; + -- Capture/Compare 1 DMA request enable + CC1DE : DIER_CC1DE_Field := 16#0#; + -- Capture/Compare 2 DMA request enable + CC2DE : DIER_CC2DE_Field := 16#0#; + -- Capture/Compare 3 DMA request enable + CC3DE : DIER_CC3DE_Field := 16#0#; + -- Capture/Compare 4 DMA request enable + CC4DE : DIER_CC4DE_Field := 16#0#; + -- unspecified + Reserved_13_13 : STM32F429x.Bit := 16#0#; + -- Trigger DMA request enable + TDE : DIER_TDE_Field := 16#0#; + -- unspecified + Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OR_Register use record - Reserved_0_9 at 0 range 0 .. 9; - ITR1_RMP at 0 range 10 .. 11; - Reserved_12_31 at 0 range 12 .. 31; + for DIER_Register_1 use record + UIE at 0 range 0 .. 0; + CC1IE at 0 range 1 .. 1; + CC2IE at 0 range 2 .. 2; + CC3IE at 0 range 3 .. 3; + CC4IE at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + TIE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + UDE at 0 range 8 .. 8; + CC1DE at 0 range 9 .. 9; + CC2DE at 0 range 10 .. 10; + CC3DE at 0 range 11 .. 11; + CC4DE at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + TDE at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; end record; - ----------------- - -- Peripherals -- - ----------------- - - -- General purpose timers - type TIM2_Peripheral is record - -- control register 1 - CR1 : CR1_Register; - -- control register 2 - CR2 : CR2_Register; - -- slave mode control register - SMCR : SMCR_Register; - -- DMA/Interrupt enable register - DIER : DIER_Register; - -- status register - SR : SR_Register; - -- event generation register - EGR : EGR_Register; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Output_Register; - -- capture/compare mode register 2 (output mode) - CCMR2 : CCMR2_Output_Register; - -- capture/compare enable register - CCER : CCER_Register; - -- counter - CNT : CNT_Register; - -- prescaler - PSC : PSC_Register; - -- auto-reload register - ARR : ARR_Register; - -- capture/compare register 1 - CCR1 : CCR_Register; - -- capture/compare register 2 - CCR2 : CCR_Register_1; - -- capture/compare register 3 - CCR3 : CCR_Register_1; - -- capture/compare register 4 - CCR4 : CCR_Register_1; - -- DMA control register - DCR : DCR_Register; - -- DMA address for full transfer - DMAR : DMAR_Register; - -- TIM5 option register - OR_k : OR_Register; + -- status register + type SR_Register_1 is record + -- Update interrupt flag + UIF : SR_UIF_Field := 16#0#; + -- Capture/compare 1 interrupt flag + CC1IF : SR_CC1IF_Field := 16#0#; + -- Capture/Compare 2 interrupt flag + CC2IF : SR_CC2IF_Field := 16#0#; + -- Capture/Compare 3 interrupt flag + CC3IF : SR_CC3IF_Field := 16#0#; + -- Capture/Compare 4 interrupt flag + CC4IF : SR_CC4IF_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- Trigger interrupt flag + TIF : SR_TIF_Field := 16#0#; + -- unspecified + Reserved_7_8 : STM32F429x.UInt2 := 16#0#; + -- Capture/Compare 1 overcapture flag + CC1OF : SR_CC1OF_Field := 16#0#; + -- Capture/compare 2 overcapture flag + CC2OF : SR_CC2OF_Field := 16#0#; + -- Capture/Compare 3 overcapture flag + CC3OF : SR_CC3OF_Field := 16#0#; + -- Capture/Compare 4 overcapture flag + CC4OF : SR_CC4OF_Field := 16#0#; + -- unspecified + Reserved_13_31 : STM32F429x.UInt19 := 16#0#; end record - with Volatile; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TIM2_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCMR2 at 28 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; - CCR3 at 60 range 0 .. 31; - CCR4 at 64 range 0 .. 31; - DCR at 72 range 0 .. 31; - DMAR at 76 range 0 .. 31; - OR_k at 80 range 0 .. 31; + for SR_Register_1 use record + UIF at 0 range 0 .. 0; + CC1IF at 0 range 1 .. 1; + CC2IF at 0 range 2 .. 2; + CC3IF at 0 range 3 .. 3; + CC4IF at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + TIF at 0 range 6 .. 6; + Reserved_7_8 at 0 range 7 .. 8; + CC1OF at 0 range 9 .. 9; + CC2OF at 0 range 10 .. 10; + CC3OF at 0 range 11 .. 11; + CC4OF at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; end record; - -- General purpose timers - TIM2_Periph : aliased TIM2_Peripheral - with Import, Address => System'To_Address (16#40000000#); - - -- General-purpose-timers - TIM5_Periph : aliased TIM2_Peripheral - with Import, Address => System'To_Address (16#40000C00#); - - -- General purpose timers - type TIM3_Peripheral is record - -- control register 1 - CR1 : CR1_Register; - -- control register 2 - CR2 : CR2_Register; - -- slave mode control register - SMCR : SMCR_Register; - -- DMA/Interrupt enable register - DIER : DIER_Register; - -- status register - SR : SR_Register; - -- event generation register - EGR : EGR_Register; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Output_Register; - -- capture/compare mode register 2 (output mode) - CCMR2 : CCMR2_Output_Register; - -- capture/compare enable register - CCER : CCER_Register; - -- counter - CNT : CNT_Register; - -- prescaler - PSC : PSC_Register; - -- auto-reload register - ARR : ARR_Register; - -- capture/compare register 1 - CCR1 : CCR_Register_1; - -- capture/compare register 2 - CCR2 : CCR_Register_1; - -- capture/compare register 3 - CCR3 : CCR_Register_1; - -- capture/compare register 4 - CCR4 : CCR_Register_1; - -- DMA control register - DCR : DCR_Register; - -- DMA address for full transfer - DMAR : DMAR_Register; + -- event generation register + type EGR_Register_1 is record + -- Write-only. Update generation + UG : EGR_UG_Field := 16#0#; + -- Write-only. Capture/compare 1 generation + CC1G : EGR_CC1G_Field := 16#0#; + -- Write-only. Capture/compare 2 generation + CC2G : EGR_CC2G_Field := 16#0#; + -- Write-only. Capture/compare 3 generation + CC3G : EGR_CC3G_Field := 16#0#; + -- Write-only. Capture/compare 4 generation + CC4G : EGR_CC4G_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- Write-only. Trigger generation + TG : EGR_TG_Field := 16#0#; + -- unspecified + Reserved_7_31 : STM32F429x.UInt25 := 16#0#; end record - with Volatile; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TIM3_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCMR2 at 28 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; - CCR3 at 60 range 0 .. 31; - CCR4 at 64 range 0 .. 31; - DCR at 72 range 0 .. 31; - DMAR at 76 range 0 .. 31; + for EGR_Register_1 use record + UG at 0 range 0 .. 0; + CC1G at 0 range 1 .. 1; + CC2G at 0 range 2 .. 2; + CC3G at 0 range 3 .. 3; + CC4G at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + TG at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; end record; - -- General purpose timers - TIM3_Periph : aliased TIM3_Peripheral - with Import, Address => System'To_Address (16#40000400#); - - -- General purpose timers - TIM4_Periph : aliased TIM3_Peripheral - with Import, Address => System'To_Address (16#40000800#); + subtype CCMR2_Output_O24CE_Field is STM32F429x.Bit; - -- Basic timers - type TIM6_Peripheral is record - -- control register 1 - CR1 : CR1_Register; - -- control register 2 - CR2 : CR2_Register; - -- DMA/Interrupt enable register - DIER : DIER_Register; - -- status register - SR : SR_Register; - -- event generation register - EGR : EGR_Register; - -- counter - CNT : CNT_Register; - -- prescaler - PSC : PSC_Register; - -- auto-reload register - ARR : ARR_Register; + -- capture/compare mode register 2 (output mode) + type CCMR2_Output_Register_1 is record + -- CC3S + CC3S : CCMR2_Output_CC3S_Field := 16#0#; + -- OC3FE + OC3FE : CCMR2_Output_OC3FE_Field := 16#0#; + -- OC3PE + OC3PE : CCMR2_Output_OC3PE_Field := 16#0#; + -- OC3M + OC3M : CCMR2_Output_OC3M_Field := 16#0#; + -- OC3CE + OC3CE : CCMR2_Output_OC3CE_Field := 16#0#; + -- CC4S + CC4S : CCMR2_Output_CC4S_Field := 16#0#; + -- OC4FE + OC4FE : CCMR2_Output_OC4FE_Field := 16#0#; + -- OC4PE + OC4PE : CCMR2_Output_OC4PE_Field := 16#0#; + -- OC4M + OC4M : CCMR2_Output_OC4M_Field := 16#0#; + -- O24CE + O24CE : CCMR2_Output_O24CE_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for TIM6_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; + for CCMR2_Output_Register_1 use record + CC3S at 0 range 0 .. 1; + OC3FE at 0 range 2 .. 2; + OC3PE at 0 range 3 .. 3; + OC3M at 0 range 4 .. 6; + OC3CE at 0 range 7 .. 7; + CC4S at 0 range 8 .. 9; + OC4FE at 0 range 10 .. 10; + OC4PE at 0 range 11 .. 11; + OC4M at 0 range 12 .. 14; + O24CE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - -- Basic timers - TIM6_Periph : aliased TIM6_Peripheral - with Import, Address => System'To_Address (16#40001000#); + subtype CCER_CC4NP_Field is STM32F429x.Bit; - -- Basic timers - TIM7_Periph : aliased TIM6_Peripheral - with Import, Address => System'To_Address (16#40001400#); + -- capture/compare enable register + type CCER_Register_1 is record + -- Capture/Compare 1 output enable + CC1E : CCER_CC1E_Field := 16#0#; + -- Capture/Compare 1 output Polarity + CC1P : CCER_CC1P_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 1 output Polarity + CC1NP : CCER_CC1NP_Field := 16#0#; + -- Capture/Compare 2 output enable + CC2E : CCER_CC2E_Field := 16#0#; + -- Capture/Compare 2 output Polarity + CC2P : CCER_CC2P_Field := 16#0#; + -- unspecified + Reserved_6_6 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 2 output Polarity + CC2NP : CCER_CC2NP_Field := 16#0#; + -- Capture/Compare 3 output enable + CC3E : CCER_CC3E_Field := 16#0#; + -- Capture/Compare 3 output Polarity + CC3P : CCER_CC3P_Field := 16#0#; + -- unspecified + Reserved_10_10 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 3 output Polarity + CC3NP : CCER_CC3NP_Field := 16#0#; + -- Capture/Compare 4 output enable + CC4E : CCER_CC4E_Field := 16#0#; + -- Capture/Compare 3 output Polarity + CC4P : CCER_CC4P_Field := 16#0#; + -- unspecified + Reserved_14_14 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 4 output Polarity + CC4NP : CCER_CC4NP_Field := 16#0#; + -- unspecified + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCER_Register_1 use record + CC1E at 0 range 0 .. 0; + CC1P at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + CC1NP at 0 range 3 .. 3; + CC2E at 0 range 4 .. 4; + CC2P at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + CC2NP at 0 range 7 .. 7; + CC3E at 0 range 8 .. 8; + CC3P at 0 range 9 .. 9; + Reserved_10_10 at 0 range 10 .. 10; + CC3NP at 0 range 11 .. 11; + CC4E at 0 range 12 .. 12; + CC4P at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + CC4NP at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CNT_CNT_L_Field is STM32F429x.UInt16; + subtype CNT_CNT_H_Field is STM32F429x.UInt16; + + -- counter + type CNT_Register_1 is record + -- Low counter value + CNT_L : CNT_CNT_L_Field := 16#0#; + -- High counter value + CNT_H : CNT_CNT_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CNT_Register_1 use record + CNT_L at 0 range 0 .. 15; + CNT_H at 0 range 16 .. 31; + end record; + + subtype ARR_ARR_L_Field is STM32F429x.UInt16; + subtype ARR_ARR_H_Field is STM32F429x.UInt16; + + -- auto-reload register + type ARR_Register_1 is record + -- Low Auto-reload value + ARR_L : ARR_ARR_L_Field := 16#0#; + -- High Auto-reload value + ARR_H : ARR_ARR_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for ARR_Register_1 use record + ARR_L at 0 range 0 .. 15; + ARR_H at 0 range 16 .. 31; + end record; + + subtype CCR1_CCR1_L_Field is STM32F429x.UInt16; + subtype CCR1_CCR1_H_Field is STM32F429x.UInt16; + + -- capture/compare register 1 + type CCR1_Register_1 is record + -- Low Capture/Compare 1 value + CCR1_L : CCR1_CCR1_L_Field := 16#0#; + -- High Capture/Compare 1 value + CCR1_H : CCR1_CCR1_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR1_Register_1 use record + CCR1_L at 0 range 0 .. 15; + CCR1_H at 0 range 16 .. 31; + end record; + + subtype CCR2_CCR2_L_Field is STM32F429x.UInt16; + subtype CCR2_CCR2_H_Field is STM32F429x.UInt16; + + -- capture/compare register 2 + type CCR2_Register_1 is record + -- Low Capture/Compare 2 value + CCR2_L : CCR2_CCR2_L_Field := 16#0#; + -- High Capture/Compare 2 value + CCR2_H : CCR2_CCR2_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR2_Register_1 use record + CCR2_L at 0 range 0 .. 15; + CCR2_H at 0 range 16 .. 31; + end record; + + subtype CCR3_CCR3_L_Field is STM32F429x.UInt16; + subtype CCR3_CCR3_H_Field is STM32F429x.UInt16; + + -- capture/compare register 3 + type CCR3_Register_1 is record + -- Low Capture/Compare value + CCR3_L : CCR3_CCR3_L_Field := 16#0#; + -- High Capture/Compare value + CCR3_H : CCR3_CCR3_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR3_Register_1 use record + CCR3_L at 0 range 0 .. 15; + CCR3_H at 0 range 16 .. 31; + end record; + + subtype CCR4_CCR4_L_Field is STM32F429x.UInt16; + subtype CCR4_CCR4_H_Field is STM32F429x.UInt16; + + -- capture/compare register 4 + type CCR4_Register_1 is record + -- Low Capture/Compare value + CCR4_L : CCR4_CCR4_L_Field := 16#0#; + -- High Capture/Compare value + CCR4_H : CCR4_CCR4_H_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCR4_Register_1 use record + CCR4_L at 0 range 0 .. 15; + CCR4_H at 0 range 16 .. 31; + end record; + + subtype OR_ITR1_RMP_Field is STM32F429x.UInt2; + + -- TIM5 option register + type OR_Register is record + -- unspecified + Reserved_0_9 : STM32F429x.UInt10 := 16#0#; + -- Timer Input 4 remap + ITR1_RMP : OR_ITR1_RMP_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for OR_Register use record + Reserved_0_9 at 0 range 0 .. 9; + ITR1_RMP at 0 range 10 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype OR_IT4_RMP_Field is STM32F429x.UInt2; + + -- TIM5 option register + type OR_Register_1 is record + -- unspecified + Reserved_0_5 : STM32F429x.UInt6 := 16#0#; + -- Timer Input 4 remap + IT4_RMP : OR_IT4_RMP_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for OR_Register_1 use record + Reserved_0_5 at 0 range 0 .. 5; + IT4_RMP at 0 range 6 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- control register 1 + type CR1_Register_1 is record + -- Counter enable + CEN : CR1_CEN_Field := 16#0#; + -- Update disable + UDIS : CR1_UDIS_Field := 16#0#; + -- Update request source + URS : CR1_URS_Field := 16#0#; + -- One-pulse mode + OPM : CR1_OPM_Field := 16#0#; + -- unspecified + Reserved_4_6 : STM32F429x.UInt3 := 16#0#; + -- Auto-reload preload enable + ARPE : CR1_ARPE_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CR1_Register_1 use record + CEN at 0 range 0 .. 0; + UDIS at 0 range 1 .. 1; + URS at 0 range 2 .. 2; + OPM at 0 range 3 .. 3; + Reserved_4_6 at 0 range 4 .. 6; + ARPE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- control register 2 + type CR2_Register_2 is record + -- unspecified + Reserved_0_3 : STM32F429x.UInt4 := 16#0#; + -- Master mode selection + MMS : CR2_MMS_Field := 16#0#; + -- unspecified + Reserved_7_31 : STM32F429x.UInt25 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CR2_Register_2 use record + Reserved_0_3 at 0 range 0 .. 3; + MMS at 0 range 4 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- DMA/Interrupt enable register + type DIER_Register_2 is record + -- Update interrupt enable + UIE : DIER_UIE_Field := 16#0#; + -- unspecified + Reserved_1_7 : STM32F429x.UInt7 := 16#0#; + -- Update DMA request enable + UDE : DIER_UDE_Field := 16#0#; + -- unspecified + Reserved_9_31 : STM32F429x.UInt23 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DIER_Register_2 use record + UIE at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + UDE at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- status register + type SR_Register_2 is record + -- Update interrupt flag + UIF : SR_UIF_Field := 16#0#; + -- unspecified + Reserved_1_31 : STM32F429x.UInt31 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SR_Register_2 use record + UIF at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- event generation register + type EGR_Register_2 is record + -- Write-only. Update generation + UG : EGR_UG_Field := 16#0#; + -- unspecified + Reserved_1_31 : STM32F429x.UInt31 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EGR_Register_2 use record + UG at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- control register 1 + type CR1_Register_2 is record + -- Counter enable + CEN : CR1_CEN_Field := 16#0#; + -- Update disable + UDIS : CR1_UDIS_Field := 16#0#; + -- Update request source + URS : CR1_URS_Field := 16#0#; + -- One-pulse mode + OPM : CR1_OPM_Field := 16#0#; + -- unspecified + Reserved_4_6 : STM32F429x.UInt3 := 16#0#; + -- Auto-reload preload enable + ARPE : CR1_ARPE_Field := 16#0#; + -- Clock division + CKD : CR1_CKD_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CR1_Register_2 use record + CEN at 0 range 0 .. 0; + UDIS at 0 range 1 .. 1; + URS at 0 range 2 .. 2; + OPM at 0 range 3 .. 3; + Reserved_4_6 at 0 range 4 .. 6; + ARPE at 0 range 7 .. 7; + CKD at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- slave mode control register + type SMCR_Register_1 is record + -- Slave mode selection + SMS : SMCR_SMS_Field := 16#0#; + -- unspecified + Reserved_3_3 : STM32F429x.Bit := 16#0#; + -- Trigger selection + TS : SMCR_TS_Field := 16#0#; + -- Master/Slave mode + MSM : SMCR_MSM_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SMCR_Register_1 use record + SMS at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + TS at 0 range 4 .. 6; + MSM at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- DMA/Interrupt enable register + type DIER_Register_3 is record + -- Update interrupt enable + UIE : DIER_UIE_Field := 16#0#; + -- Capture/Compare 1 interrupt enable + CC1IE : DIER_CC1IE_Field := 16#0#; + -- Capture/Compare 2 interrupt enable + CC2IE : DIER_CC2IE_Field := 16#0#; + -- unspecified + Reserved_3_5 : STM32F429x.UInt3 := 16#0#; + -- Trigger interrupt enable + TIE : DIER_TIE_Field := 16#0#; + -- unspecified + Reserved_7_31 : STM32F429x.UInt25 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DIER_Register_3 use record + UIE at 0 range 0 .. 0; + CC1IE at 0 range 1 .. 1; + CC2IE at 0 range 2 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + TIE at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- status register + type SR_Register_3 is record + -- Update interrupt flag + UIF : SR_UIF_Field := 16#0#; + -- Capture/compare 1 interrupt flag + CC1IF : SR_CC1IF_Field := 16#0#; + -- Capture/Compare 2 interrupt flag + CC2IF : SR_CC2IF_Field := 16#0#; + -- unspecified + Reserved_3_5 : STM32F429x.UInt3 := 16#0#; + -- Trigger interrupt flag + TIF : SR_TIF_Field := 16#0#; + -- unspecified + Reserved_7_8 : STM32F429x.UInt2 := 16#0#; + -- Capture/Compare 1 overcapture flag + CC1OF : SR_CC1OF_Field := 16#0#; + -- Capture/compare 2 overcapture flag + CC2OF : SR_CC2OF_Field := 16#0#; + -- unspecified + Reserved_11_31 : STM32F429x.UInt21 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SR_Register_3 use record + UIF at 0 range 0 .. 0; + CC1IF at 0 range 1 .. 1; + CC2IF at 0 range 2 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + TIF at 0 range 6 .. 6; + Reserved_7_8 at 0 range 7 .. 8; + CC1OF at 0 range 9 .. 9; + CC2OF at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- event generation register + type EGR_Register_3 is record + -- Write-only. Update generation + UG : EGR_UG_Field := 16#0#; + -- Write-only. Capture/compare 1 generation + CC1G : EGR_CC1G_Field := 16#0#; + -- Write-only. Capture/compare 2 generation + CC2G : EGR_CC2G_Field := 16#0#; + -- unspecified + Reserved_3_5 : STM32F429x.UInt3 := 16#0#; + -- Write-only. Trigger generation + TG : EGR_TG_Field := 16#0#; + -- unspecified + Reserved_7_31 : STM32F429x.UInt25 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EGR_Register_3 use record + UG at 0 range 0 .. 0; + CC1G at 0 range 1 .. 1; + CC2G at 0 range 2 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + TG at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- capture/compare mode register 1 (output mode) + type CCMR1_Output_Register_1 is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Output_CC1S_Field := 16#0#; + -- Output Compare 1 fast enable + OC1FE : CCMR1_Output_OC1FE_Field := 16#0#; + -- Output Compare 1 preload enable + OC1PE : CCMR1_Output_OC1PE_Field := 16#0#; + -- Output Compare 1 mode + OC1M : CCMR1_Output_OC1M_Field := 16#0#; + -- unspecified + Reserved_7_7 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 2 selection + CC2S : CCMR1_Output_CC2S_Field := 16#0#; + -- Output Compare 2 fast enable + OC2FE : CCMR1_Output_OC2FE_Field := 16#0#; + -- Output Compare 2 preload enable + OC2PE : CCMR1_Output_OC2PE_Field := 16#0#; + -- Output Compare 2 mode + OC2M : CCMR1_Output_OC2M_Field := 16#0#; + -- unspecified + Reserved_15_31 : STM32F429x.UInt17 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCMR1_Output_Register_1 use record + CC1S at 0 range 0 .. 1; + OC1FE at 0 range 2 .. 2; + OC1PE at 0 range 3 .. 3; + OC1M at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + CC2S at 0 range 8 .. 9; + OC2FE at 0 range 10 .. 10; + OC2PE at 0 range 11 .. 11; + OC2M at 0 range 12 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype CCMR1_Input_IC1F_Field_1 is STM32F429x.UInt3; + subtype CCMR1_Input_IC2F_Field_1 is STM32F429x.UInt3; + + -- capture/compare mode register 1 (input mode) + type CCMR1_Input_Register_1 is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Input_CC1S_Field := 16#0#; + -- Input capture 1 prescaler + ICPCS : CCMR1_Input_ICPCS_Field := 16#0#; + -- Input capture 1 filter + IC1F : CCMR1_Input_IC1F_Field_1 := 16#0#; + -- unspecified + Reserved_7_7 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 2 selection + CC2S : CCMR1_Input_CC2S_Field := 16#0#; + -- Input capture 2 prescaler + IC2PCS : CCMR1_Input_IC2PCS_Field := 16#0#; + -- Input capture 2 filter + IC2F : CCMR1_Input_IC2F_Field_1 := 16#0#; + -- unspecified + Reserved_15_31 : STM32F429x.UInt17 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- General purpose timers - type TIM12_Peripheral is record + for CCMR1_Input_Register_1 use record + CC1S at 0 range 0 .. 1; + ICPCS at 0 range 2 .. 3; + IC1F at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + CC2S at 0 range 8 .. 9; + IC2PCS at 0 range 10 .. 11; + IC2F at 0 range 12 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- capture/compare enable register + type CCER_Register_2 is record + -- Capture/Compare 1 output enable + CC1E : CCER_CC1E_Field := 16#0#; + -- Capture/Compare 1 output Polarity + CC1P : CCER_CC1P_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 1 output Polarity + CC1NP : CCER_CC1NP_Field := 16#0#; + -- Capture/Compare 2 output enable + CC2E : CCER_CC2E_Field := 16#0#; + -- Capture/Compare 2 output Polarity + CC2P : CCER_CC2P_Field := 16#0#; + -- unspecified + Reserved_6_6 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 2 output Polarity + CC2NP : CCER_CC2NP_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCER_Register_2 use record + CC1E at 0 range 0 .. 0; + CC1P at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + CC1NP at 0 range 3 .. 3; + CC2E at 0 range 4 .. 4; + CC2P at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + CC2NP at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- control register 1 + type CR1_Register_3 is record + -- Counter enable + CEN : CR1_CEN_Field := 16#0#; + -- Update disable + UDIS : CR1_UDIS_Field := 16#0#; + -- Update request source + URS : CR1_URS_Field := 16#0#; + -- unspecified + Reserved_3_6 : STM32F429x.UInt4 := 16#0#; + -- Auto-reload preload enable + ARPE : CR1_ARPE_Field := 16#0#; + -- Clock division + CKD : CR1_CKD_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CR1_Register_3 use record + CEN at 0 range 0 .. 0; + UDIS at 0 range 1 .. 1; + URS at 0 range 2 .. 2; + Reserved_3_6 at 0 range 3 .. 6; + ARPE at 0 range 7 .. 7; + CKD at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- DMA/Interrupt enable register + type DIER_Register_4 is record + -- Update interrupt enable + UIE : DIER_UIE_Field := 16#0#; + -- Capture/Compare 1 interrupt enable + CC1IE : DIER_CC1IE_Field := 16#0#; + -- unspecified + Reserved_2_31 : STM32F429x.UInt30 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for DIER_Register_4 use record + UIE at 0 range 0 .. 0; + CC1IE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- status register + type SR_Register_4 is record + -- Update interrupt flag + UIF : SR_UIF_Field := 16#0#; + -- Capture/compare 1 interrupt flag + CC1IF : SR_CC1IF_Field := 16#0#; + -- unspecified + Reserved_2_8 : STM32F429x.UInt7 := 16#0#; + -- Capture/Compare 1 overcapture flag + CC1OF : SR_CC1OF_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SR_Register_4 use record + UIF at 0 range 0 .. 0; + CC1IF at 0 range 1 .. 1; + Reserved_2_8 at 0 range 2 .. 8; + CC1OF at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- event generation register + type EGR_Register_4 is record + -- Write-only. Update generation + UG : EGR_UG_Field := 16#0#; + -- Write-only. Capture/compare 1 generation + CC1G : EGR_CC1G_Field := 16#0#; + -- unspecified + Reserved_2_31 : STM32F429x.UInt30 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for EGR_Register_4 use record + UG at 0 range 0 .. 0; + CC1G at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- capture/compare mode register 1 (output mode) + type CCMR1_Output_Register_2 is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Output_CC1S_Field := 16#0#; + -- Output Compare 1 fast enable + OC1FE : CCMR1_Output_OC1FE_Field := 16#0#; + -- Output Compare 1 preload enable + OC1PE : CCMR1_Output_OC1PE_Field := 16#0#; + -- Output Compare 1 mode + OC1M : CCMR1_Output_OC1M_Field := 16#0#; + -- unspecified + Reserved_7_31 : STM32F429x.UInt25 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCMR1_Output_Register_2 use record + CC1S at 0 range 0 .. 1; + OC1FE at 0 range 2 .. 2; + OC1PE at 0 range 3 .. 3; + OC1M at 0 range 4 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- capture/compare mode register 1 (input mode) + type CCMR1_Input_Register_2 is record + -- Capture/Compare 1 selection + CC1S : CCMR1_Input_CC1S_Field := 16#0#; + -- Input capture 1 prescaler + ICPCS : CCMR1_Input_ICPCS_Field := 16#0#; + -- Input capture 1 filter + IC1F : CCMR1_Input_IC1F_Field := 16#0#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCMR1_Input_Register_2 use record + CC1S at 0 range 0 .. 1; + ICPCS at 0 range 2 .. 3; + IC1F at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- capture/compare enable register + type CCER_Register_3 is record + -- Capture/Compare 1 output enable + CC1E : CCER_CC1E_Field := 16#0#; + -- Capture/Compare 1 output Polarity + CC1P : CCER_CC1P_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- Capture/Compare 1 output Polarity + CC1NP : CCER_CC1NP_Field := 16#0#; + -- unspecified + Reserved_4_31 : STM32F429x.UInt28 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CCER_Register_3 use record + CC1E at 0 range 0 .. 0; + CC1P at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + CC1NP at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype OR_RMP_Field is STM32F429x.UInt2; + + -- option register + type OR_Register_2 is record + -- Input 1 remapping capability + RMP : OR_RMP_Field := 16#0#; + -- unspecified + Reserved_2_31 : STM32F429x.UInt30 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for OR_Register_2 use record + RMP at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type TIM1_Disc is + (Output, + Input); + + -- Advanced-timers + type TIM1_Peripheral + (Discriminent : TIM1_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- slave mode control register - SMCR : SMCR_Register; + SMCR : aliased SMCR_Register; + pragma Volatile_Full_Access (SMCR); -- DMA/Interrupt enable register - DIER : DIER_Register; + DIER : aliased DIER_Register; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Output_Register; + EGR : aliased EGR_Register; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register; + CCER : aliased CCER_Register; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register; + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register; + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); + -- repetition counter register + RCR : aliased RCR_Register; + pragma Volatile_Full_Access (RCR); -- capture/compare register 1 - CCR1 : CCR_Register; + CCR1 : aliased CCR1_Register; + pragma Volatile_Full_Access (CCR1); -- capture/compare register 2 - CCR2 : CCR_Register_1; + CCR2 : aliased CCR2_Register; + pragma Volatile_Full_Access (CCR2); + -- capture/compare register 3 + CCR3 : aliased CCR3_Register; + pragma Volatile_Full_Access (CCR3); + -- capture/compare register 4 + CCR4 : aliased CCR4_Register; + pragma Volatile_Full_Access (CCR4); + -- break and dead-time register + BDTR : aliased BDTR_Register; + pragma Volatile_Full_Access (BDTR); + -- DMA control register + DCR : aliased DCR_Register; + pragma Volatile_Full_Access (DCR); + -- DMA address for full transfer + DMAR : aliased DMAR_Register; + pragma Volatile_Full_Access (DMAR); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + pragma Volatile_Full_Access (CCMR1_Output); + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register; + pragma Volatile_Full_Access (CCMR2_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + pragma Volatile_Full_Access (CCMR1_Input); + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + pragma Volatile_Full_Access (CCMR2_Input); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; - for TIM12_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; + for TIM1_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + RCR at 16#30# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + BDTR at 16#44# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; end record; + -- Advanced-timers + TIM1_Periph : aliased TIM1_Peripheral + with Import, Address => TIM1_Base; + + -- Advanced-timers + TIM8_Periph : aliased TIM1_Peripheral + with Import, Address => TIM8_Base; + + type TIM2_Disc is + (Output, + Input); + -- General purpose timers - TIM12_Periph : aliased TIM12_Peripheral - with Import, Address => System'To_Address (16#40001800#); + type TIM2_Peripheral + (Discriminent : TIM2_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); + -- control register 2 + CR2 : aliased CR2_Register_1; + pragma Volatile_Full_Access (CR2); + -- slave mode control register + SMCR : aliased SMCR_Register; + pragma Volatile_Full_Access (SMCR); + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_1; + pragma Volatile_Full_Access (DIER); + -- status register + SR : aliased SR_Register_1; + pragma Volatile_Full_Access (SR); + -- event generation register + EGR : aliased EGR_Register_1; + pragma Volatile_Full_Access (EGR); + -- capture/compare enable register + CCER : aliased CCER_Register_1; + pragma Volatile_Full_Access (CCER); + -- counter + CNT : aliased CNT_Register_1; + pragma Volatile_Full_Access (CNT); + -- prescaler + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); + -- auto-reload register + ARR : aliased ARR_Register_1; + pragma Volatile_Full_Access (ARR); + -- capture/compare register 1 + CCR1 : aliased CCR1_Register_1; + pragma Volatile_Full_Access (CCR1); + -- capture/compare register 2 + CCR2 : aliased CCR2_Register_1; + pragma Volatile_Full_Access (CCR2); + -- capture/compare register 3 + CCR3 : aliased CCR3_Register_1; + pragma Volatile_Full_Access (CCR3); + -- capture/compare register 4 + CCR4 : aliased CCR4_Register_1; + pragma Volatile_Full_Access (CCR4); + -- DMA control register + DCR : aliased DCR_Register; + pragma Volatile_Full_Access (DCR); + -- DMA address for full transfer + DMAR : aliased DMAR_Register; + pragma Volatile_Full_Access (DMAR); + -- TIM5 option register + OR_k : aliased OR_Register; + pragma Volatile_Full_Access (OR_k); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + pragma Volatile_Full_Access (CCMR1_Output); + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + pragma Volatile_Full_Access (CCMR2_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + pragma Volatile_Full_Access (CCMR1_Input); + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + pragma Volatile_Full_Access (CCMR2_Input); + end case; + end record + with Unchecked_Union, Volatile; + + for TIM2_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; + end record; -- General purpose timers - TIM9_Periph : aliased TIM12_Peripheral - with Import, Address => System'To_Address (16#40014000#); + TIM2_Periph : aliased TIM2_Peripheral + with Import, Address => TIM2_Base; - -- General-purpose-timers - type TIM13_Peripheral is record + type TIM3_Disc is + (Output, + Input); + + -- General purpose timers + type TIM3_Peripheral + (Discriminent : TIM3_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); + -- control register 2 + CR2 : aliased CR2_Register_1; + pragma Volatile_Full_Access (CR2); + -- slave mode control register + SMCR : aliased SMCR_Register; + pragma Volatile_Full_Access (SMCR); -- DMA/Interrupt enable register - DIER : DIER_Register; + DIER : aliased DIER_Register_1; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register; + SR : aliased SR_Register_1; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Output_Register; + EGR : aliased EGR_Register_1; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register; + CCER : aliased CCER_Register_1; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register; + CNT : aliased CNT_Register_1; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register; + ARR : aliased ARR_Register_1; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register; + CCR1 : aliased CCR1_Register_1; + pragma Volatile_Full_Access (CCR1); + -- capture/compare register 2 + CCR2 : aliased CCR2_Register_1; + pragma Volatile_Full_Access (CCR2); + -- capture/compare register 3 + CCR3 : aliased CCR3_Register_1; + pragma Volatile_Full_Access (CCR3); + -- capture/compare register 4 + CCR4 : aliased CCR4_Register_1; + pragma Volatile_Full_Access (CCR4); + -- DMA control register + DCR : aliased DCR_Register; + pragma Volatile_Full_Access (DCR); + -- DMA address for full transfer + DMAR : aliased DMAR_Register; + pragma Volatile_Full_Access (DMAR); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + pragma Volatile_Full_Access (CCMR1_Output); + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + pragma Volatile_Full_Access (CCMR2_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + pragma Volatile_Full_Access (CCMR1_Input); + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + pragma Volatile_Full_Access (CCMR2_Input); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; - for TIM13_Peripheral use record - CR1 at 0 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; + for TIM3_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; end record; - -- General-purpose-timers - TIM13_Periph : aliased TIM13_Peripheral - with Import, Address => System'To_Address (16#40001C00#); + -- General purpose timers + TIM3_Periph : aliased TIM3_Peripheral + with Import, Address => TIM3_Base; - -- General-purpose-timers - TIM14_Periph : aliased TIM13_Peripheral - with Import, Address => System'To_Address (16#40002000#); + -- General purpose timers + TIM4_Periph : aliased TIM3_Peripheral + with Import, Address => TIM4_Base; - -- General-purpose-timers - TIM10_Periph : aliased TIM13_Peripheral - with Import, Address => System'To_Address (16#40014400#); + type TIM5_Disc is + (Output, + Input); - -- Advanced-timers - type TIM1_Peripheral is record + -- General-purpose-timers + type TIM5_Peripheral + (Discriminent : TIM5_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register_1; + pragma Volatile_Full_Access (CR2); -- slave mode control register - SMCR : SMCR_Register; + SMCR : aliased SMCR_Register; + pragma Volatile_Full_Access (SMCR); -- DMA/Interrupt enable register - DIER : DIER_Register; + DIER : aliased DIER_Register_1; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register; + SR : aliased SR_Register_1; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Output_Register; - -- capture/compare mode register 2 (output mode) - CCMR2 : CCMR2_Output_Register; + EGR : aliased EGR_Register_1; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register; + CCER : aliased CCER_Register_1; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register; + CNT : aliased CNT_Register_1; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register; - -- repetition counter register - RCR : RCR_Register; + ARR : aliased ARR_Register_1; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register; + CCR1 : aliased CCR1_Register_1; + pragma Volatile_Full_Access (CCR1); -- capture/compare register 2 - CCR2 : CCR_Register; + CCR2 : aliased CCR2_Register_1; + pragma Volatile_Full_Access (CCR2); -- capture/compare register 3 - CCR3 : CCR_Register; + CCR3 : aliased CCR3_Register_1; + pragma Volatile_Full_Access (CCR3); -- capture/compare register 4 - CCR4 : CCR_Register; - -- break and dead-time register - BDTR : BDTR_Register; + CCR4 : aliased CCR4_Register_1; + pragma Volatile_Full_Access (CCR4); -- DMA control register - DCR : DCR_Register; + DCR : aliased DCR_Register; + pragma Volatile_Full_Access (DCR); -- DMA address for full transfer - DMAR : DMAR_Register; + DMAR : aliased DMAR_Register; + pragma Volatile_Full_Access (DMAR); + -- TIM5 option register + OR_k : aliased OR_Register_1; + pragma Volatile_Full_Access (OR_k); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register; + pragma Volatile_Full_Access (CCMR1_Output); + -- capture/compare mode register 2 (output mode) + CCMR2_Output : aliased CCMR2_Output_Register_1; + pragma Volatile_Full_Access (CCMR2_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register; + pragma Volatile_Full_Access (CCMR1_Input); + -- capture/compare mode register 2 (input mode) + CCMR2_Input : aliased CCMR2_Input_Register; + pragma Volatile_Full_Access (CCMR2_Input); + end case; + end record + with Unchecked_Union, Volatile; + + for TIM5_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCR3 at 16#3C# range 0 .. 31; + CCR4 at 16#40# range 0 .. 31; + DCR at 16#48# range 0 .. 31; + DMAR at 16#4C# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR2_Output at 16#1C# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + CCMR2_Input at 16#1C# range 0 .. 31; + end record; + + -- General-purpose-timers + TIM5_Periph : aliased TIM5_Peripheral + with Import, Address => TIM5_Base; + + -- Basic timers + type TIM6_Peripheral is record + -- control register 1 + CR1 : aliased CR1_Register_1; + pragma Volatile_Full_Access (CR1); + -- control register 2 + CR2 : aliased CR2_Register_2; + pragma Volatile_Full_Access (CR2); + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_2; + pragma Volatile_Full_Access (DIER); + -- status register + SR : aliased SR_Register_2; + pragma Volatile_Full_Access (SR); + -- event generation register + EGR : aliased EGR_Register_2; + pragma Volatile_Full_Access (EGR); + -- counter + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); + -- prescaler + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); + -- auto-reload register + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); end record with Volatile; - for TIM1_Peripheral use record - CR1 at 0 range 0 .. 31; - CR2 at 4 range 0 .. 31; - SMCR at 8 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCMR2 at 28 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - RCR at 48 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - CCR2 at 56 range 0 .. 31; - CCR3 at 60 range 0 .. 31; - CCR4 at 64 range 0 .. 31; - BDTR at 68 range 0 .. 31; - DCR at 72 range 0 .. 31; - DMAR at 76 range 0 .. 31; + for TIM6_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; end record; - -- Advanced-timers - TIM1_Periph : aliased TIM1_Peripheral - with Import, Address => System'To_Address (16#40010000#); + -- Basic timers + TIM6_Periph : aliased TIM6_Peripheral + with Import, Address => TIM6_Base; - -- Advanced-timers - TIM8_Periph : aliased TIM1_Peripheral - with Import, Address => System'To_Address (16#40010400#); + -- Basic timers + TIM7_Periph : aliased TIM6_Peripheral + with Import, Address => TIM7_Base; + + type TIM9_Disc is + (Output, + Input); + + -- General purpose timers + type TIM9_Peripheral + (Discriminent : TIM9_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register_2; + pragma Volatile_Full_Access (CR1); + -- control register 2 + CR2 : aliased CR2_Register_2; + pragma Volatile_Full_Access (CR2); + -- slave mode control register + SMCR : aliased SMCR_Register_1; + pragma Volatile_Full_Access (SMCR); + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_3; + pragma Volatile_Full_Access (DIER); + -- status register + SR : aliased SR_Register_3; + pragma Volatile_Full_Access (SR); + -- event generation register + EGR : aliased EGR_Register_3; + pragma Volatile_Full_Access (EGR); + -- capture/compare enable register + CCER : aliased CCER_Register_2; + pragma Volatile_Full_Access (CCER); + -- counter + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); + -- prescaler + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); + -- auto-reload register + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); + -- capture/compare register 1 + CCR1 : aliased CCR1_Register; + pragma Volatile_Full_Access (CCR1); + -- capture/compare register 2 + CCR2 : aliased CCR2_Register; + pragma Volatile_Full_Access (CCR2); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_1; + pragma Volatile_Full_Access (CCMR1_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_1; + pragma Volatile_Full_Access (CCMR1_Input); + end case; + end record + with Unchecked_Union, Volatile; + + for TIM9_Peripheral use record + CR1 at 16#0# range 0 .. 31; + CR2 at 16#4# range 0 .. 31; + SMCR at 16#8# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCR2 at 16#38# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + end record; + + -- General purpose timers + TIM9_Periph : aliased TIM9_Peripheral + with Import, Address => TIM9_Base; + + -- General purpose timers + TIM12_Periph : aliased TIM9_Peripheral + with Import, Address => TIM12_Base; + + type TIM10_Disc is + (Output, + Input); + + -- General-purpose-timers + type TIM10_Peripheral + (Discriminent : TIM10_Disc := Output) + is record + -- control register 1 + CR1 : aliased CR1_Register_3; + pragma Volatile_Full_Access (CR1); + -- DMA/Interrupt enable register + DIER : aliased DIER_Register_4; + pragma Volatile_Full_Access (DIER); + -- status register + SR : aliased SR_Register_4; + pragma Volatile_Full_Access (SR); + -- event generation register + EGR : aliased EGR_Register_4; + pragma Volatile_Full_Access (EGR); + -- capture/compare enable register + CCER : aliased CCER_Register_3; + pragma Volatile_Full_Access (CCER); + -- counter + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); + -- prescaler + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); + -- auto-reload register + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); + -- capture/compare register 1 + CCR1 : aliased CCR1_Register; + pragma Volatile_Full_Access (CCR1); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_2; + pragma Volatile_Full_Access (CCMR1_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_2; + pragma Volatile_Full_Access (CCMR1_Input); + end case; + end record + with Unchecked_Union, Volatile; + + for TIM10_Peripheral use record + CR1 at 16#0# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; + end record; -- General-purpose-timers - type TIM11_Peripheral is record + TIM10_Periph : aliased TIM10_Peripheral + with Import, Address => TIM10_Base; + + -- General-purpose-timers + TIM13_Periph : aliased TIM10_Peripheral + with Import, Address => TIM13_Base; + + -- General-purpose-timers + TIM14_Periph : aliased TIM10_Peripheral + with Import, Address => TIM14_Base; + + type TIM11_Disc is + (Output, + Input); + + -- General-purpose-timers + type TIM11_Peripheral + (Discriminent : TIM11_Disc := Output) + is record -- control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register_3; + pragma Volatile_Full_Access (CR1); -- DMA/Interrupt enable register - DIER : DIER_Register; + DIER : aliased DIER_Register_4; + pragma Volatile_Full_Access (DIER); -- status register - SR : SR_Register; + SR : aliased SR_Register_4; + pragma Volatile_Full_Access (SR); -- event generation register - EGR : EGR_Register; - -- capture/compare mode register 1 (output mode) - CCMR1 : CCMR1_Output_Register; + EGR : aliased EGR_Register_4; + pragma Volatile_Full_Access (EGR); -- capture/compare enable register - CCER : CCER_Register; + CCER : aliased CCER_Register_3; + pragma Volatile_Full_Access (CCER); -- counter - CNT : CNT_Register; + CNT : aliased CNT_Register; + pragma Volatile_Full_Access (CNT); -- prescaler - PSC : PSC_Register; + PSC : aliased PSC_Register; + pragma Volatile_Full_Access (PSC); -- auto-reload register - ARR : ARR_Register; + ARR : aliased ARR_Register; + pragma Volatile_Full_Access (ARR); -- capture/compare register 1 - CCR1 : CCR_Register; + CCR1 : aliased CCR1_Register; + pragma Volatile_Full_Access (CCR1); -- option register - OR_k : OR_Register; + OR_k : aliased OR_Register_2; + pragma Volatile_Full_Access (OR_k); + case Discriminent is + when Output => + -- capture/compare mode register 1 (output mode) + CCMR1_Output : aliased CCMR1_Output_Register_2; + pragma Volatile_Full_Access (CCMR1_Output); + when Input => + -- capture/compare mode register 1 (input mode) + CCMR1_Input : aliased CCMR1_Input_Register_2; + pragma Volatile_Full_Access (CCMR1_Input); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for TIM11_Peripheral use record - CR1 at 0 range 0 .. 31; - DIER at 12 range 0 .. 31; - SR at 16 range 0 .. 31; - EGR at 20 range 0 .. 31; - CCMR1 at 24 range 0 .. 31; - CCER at 32 range 0 .. 31; - CNT at 36 range 0 .. 31; - PSC at 40 range 0 .. 31; - ARR at 44 range 0 .. 31; - CCR1 at 52 range 0 .. 31; - OR_k at 80 range 0 .. 31; + CR1 at 16#0# range 0 .. 31; + DIER at 16#C# range 0 .. 31; + SR at 16#10# range 0 .. 31; + EGR at 16#14# range 0 .. 31; + CCER at 16#20# range 0 .. 31; + CNT at 16#24# range 0 .. 31; + PSC at 16#28# range 0 .. 31; + ARR at 16#2C# range 0 .. 31; + CCR1 at 16#34# range 0 .. 31; + OR_k at 16#50# range 0 .. 31; + CCMR1_Output at 16#18# range 0 .. 31; + CCMR1_Input at 16#18# range 0 .. 31; end record; -- General-purpose-timers TIM11_Periph : aliased TIM11_Peripheral - with Import, Address => System'To_Address (16#40014800#); + with Import, Address => TIM11_Base; end STM32F429x.TIM; diff --git a/stm32f429i/stm32f429x/stm32f429x-usart.ads b/stm32f429i/stm32f429x/stm32f429x-usart.ads index 803f956..4bbd7c0 100644 --- a/stm32f429i/stm32f429x/stm32f429x-usart.ads +++ b/stm32f429i/stm32f429x/stm32f429x-usart.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.USART is -- Registers -- --------------- - ----------------- - -- SR_Register -- - ----------------- - subtype SR_PE_Field is STM32F429x.Bit; subtype SR_FE_Field is STM32F429x.Bit; subtype SR_NF_Field is STM32F429x.Bit; @@ -25,53 +23,45 @@ package STM32F429x.USART is subtype SR_TC_Field is STM32F429x.Bit; subtype SR_TXE_Field is STM32F429x.Bit; subtype SR_LBD_Field is STM32F429x.Bit; - subtype SR_CTS_Field is STM32F429x.Bit; -- Status register type SR_Register is record - -- Parity error - PE : SR_PE_Field := 16#0#; - -- Framing error - FE : SR_FE_Field := 16#0#; - -- Noise detected flag - NF : SR_NF_Field := 16#0#; - -- Overrun error - ORE : SR_ORE_Field := 16#0#; - -- IDLE line detected - IDLE : SR_IDLE_Field := 16#0#; + -- Read-only. Parity error + PE : SR_PE_Field := 16#0#; + -- Read-only. Framing error + FE : SR_FE_Field := 16#0#; + -- Read-only. Noise detected flag + NF : SR_NF_Field := 16#0#; + -- Read-only. Overrun error + ORE : SR_ORE_Field := 16#0#; + -- Read-only. IDLE line detected + IDLE : SR_IDLE_Field := 16#0#; -- Read data register not empty - RXNE : SR_RXNE_Field := 16#0#; + RXNE : SR_RXNE_Field := 16#0#; -- Transmission complete - TC : SR_TC_Field := 16#0#; - -- Transmit data register empty - TXE : SR_TXE_Field := 16#0#; + TC : SR_TC_Field := 16#0#; + -- Read-only. Transmit data register empty + TXE : SR_TXE_Field := 16#0#; -- LIN break detection flag - LBD : SR_LBD_Field := 16#0#; - -- CTS flag - CTS : SR_CTS_Field := 16#0#; + LBD : SR_LBD_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F429x.UInt22 := 16#3000#; + Reserved_9_31 : STM32F429x.UInt23 := 16#6000#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record - PE at 0 range 0 .. 0; - FE at 0 range 1 .. 1; - NF at 0 range 2 .. 2; - ORE at 0 range 3 .. 3; - IDLE at 0 range 4 .. 4; - RXNE at 0 range 5 .. 5; - TC at 0 range 6 .. 6; - TXE at 0 range 7 .. 7; - LBD at 0 range 8 .. 8; - CTS at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + PE at 0 range 0 .. 0; + FE at 0 range 1 .. 1; + NF at 0 range 2 .. 2; + ORE at 0 range 3 .. 3; + IDLE at 0 range 4 .. 4; + RXNE at 0 range 5 .. 5; + TC at 0 range 6 .. 6; + TXE at 0 range 7 .. 7; + LBD at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; end record; - ----------------- - -- DR_Register -- - ----------------- - subtype DR_DR_Field is STM32F429x.UInt9; -- Data register @@ -81,17 +71,13 @@ package STM32F429x.USART is -- unspecified Reserved_9_31 : STM32F429x.UInt23 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for DR_Register use record DR at 0 range 0 .. 8; Reserved_9_31 at 0 range 9 .. 31; end record; - ------------------ - -- BRR_Register -- - ------------------ - subtype BRR_DIV_Fraction_Field is STM32F429x.UInt4; subtype BRR_DIV_Mantissa_Field is STM32F429x.UInt12; @@ -102,9 +88,9 @@ package STM32F429x.USART is -- mantissa of USARTDIV DIV_Mantissa : BRR_DIV_Mantissa_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for BRR_Register use record DIV_Fraction at 0 range 0 .. 3; @@ -112,10 +98,6 @@ package STM32F429x.USART is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR1_Register -- - ------------------ - subtype CR1_SBK_Field is STM32F429x.Bit; subtype CR1_RWU_Field is STM32F429x.Bit; subtype CR1_RE_Field is STM32F429x.Bit; @@ -167,9 +149,9 @@ package STM32F429x.USART is -- Oversampling mode OVER8 : CR1_OVER8_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR1_Register use record SBK at 0 range 0 .. 0; @@ -191,22 +173,140 @@ package STM32F429x.USART is Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------ - -- CR2_Register -- - ------------------ - subtype CR2_ADD_Field is STM32F429x.UInt4; subtype CR2_LBDL_Field is STM32F429x.Bit; subtype CR2_LBDIE_Field is STM32F429x.Bit; + subtype CR2_STOP_Field is STM32F429x.UInt2; + subtype CR2_LINEN_Field is STM32F429x.Bit; + + -- Control register 2 + type CR2_Register is record + -- Address of the USART node + ADD : CR2_ADD_Field := 16#0#; + -- unspecified + Reserved_4_4 : STM32F429x.Bit := 16#0#; + -- lin break detection length + LBDL : CR2_LBDL_Field := 16#0#; + -- LIN break detection interrupt enable + LBDIE : CR2_LBDIE_Field := 16#0#; + -- unspecified + Reserved_7_11 : STM32F429x.UInt5 := 16#0#; + -- STOP bits + STOP : CR2_STOP_Field := 16#0#; + -- LIN mode enable + LINEN : CR2_LINEN_Field := 16#0#; + -- unspecified + Reserved_15_31 : STM32F429x.UInt17 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CR2_Register use record + ADD at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + LBDL at 0 range 5 .. 5; + LBDIE at 0 range 6 .. 6; + Reserved_7_11 at 0 range 7 .. 11; + STOP at 0 range 12 .. 13; + LINEN at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype CR3_EIE_Field is STM32F429x.Bit; + subtype CR3_IREN_Field is STM32F429x.Bit; + subtype CR3_IRLP_Field is STM32F429x.Bit; + subtype CR3_HDSEL_Field is STM32F429x.Bit; + subtype CR3_DMAR_Field is STM32F429x.Bit; + subtype CR3_DMAT_Field is STM32F429x.Bit; + subtype CR3_ONEBIT_Field is STM32F429x.Bit; + + -- Control register 3 + type CR3_Register is record + -- Error interrupt enable + EIE : CR3_EIE_Field := 16#0#; + -- IrDA mode enable + IREN : CR3_IREN_Field := 16#0#; + -- IrDA low-power + IRLP : CR3_IRLP_Field := 16#0#; + -- Half-duplex selection + HDSEL : CR3_HDSEL_Field := 16#0#; + -- unspecified + Reserved_4_5 : STM32F429x.UInt2 := 16#0#; + -- DMA enable receiver + DMAR : CR3_DMAR_Field := 16#0#; + -- DMA enable transmitter + DMAT : CR3_DMAT_Field := 16#0#; + -- unspecified + Reserved_8_10 : STM32F429x.UInt3 := 16#0#; + -- One sample bit method enable + ONEBIT : CR3_ONEBIT_Field := 16#0#; + -- unspecified + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for CR3_Register use record + EIE at 0 range 0 .. 0; + IREN at 0 range 1 .. 1; + IRLP at 0 range 2 .. 2; + HDSEL at 0 range 3 .. 3; + Reserved_4_5 at 0 range 4 .. 5; + DMAR at 0 range 6 .. 6; + DMAT at 0 range 7 .. 7; + Reserved_8_10 at 0 range 8 .. 10; + ONEBIT at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype SR_CTS_Field is STM32F429x.Bit; + + -- Status register + type SR_Register_1 is record + -- Read-only. Parity error + PE : SR_PE_Field := 16#0#; + -- Read-only. Framing error + FE : SR_FE_Field := 16#0#; + -- Read-only. Noise detected flag + NF : SR_NF_Field := 16#0#; + -- Read-only. Overrun error + ORE : SR_ORE_Field := 16#0#; + -- Read-only. IDLE line detected + IDLE : SR_IDLE_Field := 16#0#; + -- Read data register not empty + RXNE : SR_RXNE_Field := 16#0#; + -- Transmission complete + TC : SR_TC_Field := 16#0#; + -- Read-only. Transmit data register empty + TXE : SR_TXE_Field := 16#0#; + -- LIN break detection flag + LBD : SR_LBD_Field := 16#0#; + -- CTS flag + CTS : SR_CTS_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F429x.UInt22 := 16#3000#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for SR_Register_1 use record + PE at 0 range 0 .. 0; + FE at 0 range 1 .. 1; + NF at 0 range 2 .. 2; + ORE at 0 range 3 .. 3; + IDLE at 0 range 4 .. 4; + RXNE at 0 range 5 .. 5; + TC at 0 range 6 .. 6; + TXE at 0 range 7 .. 7; + LBD at 0 range 8 .. 8; + CTS at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + subtype CR2_LBCL_Field is STM32F429x.Bit; subtype CR2_CPHA_Field is STM32F429x.Bit; subtype CR2_CPOL_Field is STM32F429x.Bit; subtype CR2_CLKEN_Field is STM32F429x.Bit; - subtype CR2_STOP_Field is STM32F429x.UInt2; - subtype CR2_LINEN_Field is STM32F429x.Bit; -- Control register 2 - type CR2_Register is record + type CR2_Register_1 is record -- Address of the USART node ADD : CR2_ADD_Field := 16#0#; -- unspecified @@ -232,9 +332,9 @@ package STM32F429x.USART is -- unspecified Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR2_Register use record + for CR2_Register_1 use record ADD at 0 range 0 .. 3; Reserved_4_4 at 0 range 4 .. 4; LBDL at 0 range 5 .. 5; @@ -249,25 +349,14 @@ package STM32F429x.USART is Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------ - -- CR3_Register -- - ------------------ - - subtype CR3_EIE_Field is STM32F429x.Bit; - subtype CR3_IREN_Field is STM32F429x.Bit; - subtype CR3_IRLP_Field is STM32F429x.Bit; - subtype CR3_HDSEL_Field is STM32F429x.Bit; subtype CR3_NACK_Field is STM32F429x.Bit; subtype CR3_SCEN_Field is STM32F429x.Bit; - subtype CR3_DMAR_Field is STM32F429x.Bit; - subtype CR3_DMAT_Field is STM32F429x.Bit; subtype CR3_RTSE_Field is STM32F429x.Bit; subtype CR3_CTSE_Field is STM32F429x.Bit; subtype CR3_CTSIE_Field is STM32F429x.Bit; - subtype CR3_ONEBIT_Field is STM32F429x.Bit; -- Control register 3 - type CR3_Register is record + type CR3_Register_1 is record -- Error interrupt enable EIE : CR3_EIE_Field := 16#0#; -- IrDA mode enable @@ -295,9 +384,9 @@ package STM32F429x.USART is -- unspecified Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for CR3_Register use record + for CR3_Register_1 use record EIE at 0 range 0 .. 0; IREN at 0 range 1 .. 1; IRLP at 0 range 2 .. 2; @@ -313,10 +402,6 @@ package STM32F429x.USART is Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------- - -- GTPR_Register -- - ------------------- - subtype GTPR_PSC_Field is STM32F429x.Byte; subtype GTPR_GT_Field is STM32F429x.Byte; @@ -327,9 +412,9 @@ package STM32F429x.USART is -- Guard time value GT : GTPR_GT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for GTPR_Register use record PSC at 0 range 0 .. 7; @@ -342,90 +427,103 @@ package STM32F429x.USART is ----------------- -- Universal synchronous asynchronous receiver transmitter - type USART2_Peripheral is record + type UART4_Peripheral is record -- Status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); -- Data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- Baud rate register - BRR : BRR_Register; + BRR : aliased BRR_Register; + pragma Volatile_Full_Access (BRR); -- Control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- Control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register; + pragma Volatile_Full_Access (CR2); -- Control register 3 - CR3 : CR3_Register; - -- Guard time and prescaler register - GTPR : GTPR_Register; + CR3 : aliased CR3_Register; + pragma Volatile_Full_Access (CR3); end record with Volatile; - for USART2_Peripheral use record - SR at 0 range 0 .. 31; - DR at 4 range 0 .. 31; - BRR at 8 range 0 .. 31; - CR1 at 12 range 0 .. 31; - CR2 at 16 range 0 .. 31; - CR3 at 20 range 0 .. 31; - GTPR at 24 range 0 .. 31; + for UART4_Peripheral use record + SR at 16#0# range 0 .. 31; + DR at 16#4# range 0 .. 31; + BRR at 16#8# range 0 .. 31; + CR1 at 16#C# range 0 .. 31; + CR2 at 16#10# range 0 .. 31; + CR3 at 16#14# range 0 .. 31; end record; -- Universal synchronous asynchronous receiver transmitter - USART2_Periph : aliased USART2_Peripheral - with Import, Address => System'To_Address (16#40004400#); - - -- Universal synchronous asynchronous receiver transmitter - USART3_Periph : aliased USART2_Peripheral - with Import, Address => System'To_Address (16#40004800#); - - -- Universal synchronous asynchronous receiver transmitter - UART7_Periph : aliased USART2_Peripheral - with Import, Address => System'To_Address (16#40007800#); + UART4_Periph : aliased UART4_Peripheral + with Import, Address => UART4_Base; -- Universal synchronous asynchronous receiver transmitter - UART8_Periph : aliased USART2_Peripheral - with Import, Address => System'To_Address (16#40007C00#); + UART5_Periph : aliased UART4_Peripheral + with Import, Address => UART5_Base; -- Universal synchronous asynchronous receiver transmitter - USART1_Periph : aliased USART2_Peripheral - with Import, Address => System'To_Address (16#40011000#); + UART7_Periph : aliased UART4_Peripheral + with Import, Address => UART7_Base; -- Universal synchronous asynchronous receiver transmitter - USART6_Periph : aliased USART2_Peripheral - with Import, Address => System'To_Address (16#40011400#); + UART8_Periph : aliased UART4_Peripheral + with Import, Address => UART8_Base; -- Universal synchronous asynchronous receiver transmitter - type UART4_Peripheral is record + type USART1_Peripheral is record -- Status register - SR : SR_Register; + SR : aliased SR_Register_1; + pragma Volatile_Full_Access (SR); -- Data register - DR : DR_Register; + DR : aliased DR_Register; + pragma Volatile_Full_Access (DR); -- Baud rate register - BRR : BRR_Register; + BRR : aliased BRR_Register; + pragma Volatile_Full_Access (BRR); -- Control register 1 - CR1 : CR1_Register; + CR1 : aliased CR1_Register; + pragma Volatile_Full_Access (CR1); -- Control register 2 - CR2 : CR2_Register; + CR2 : aliased CR2_Register_1; + pragma Volatile_Full_Access (CR2); -- Control register 3 - CR3 : CR3_Register; + CR3 : aliased CR3_Register_1; + pragma Volatile_Full_Access (CR3); + -- Guard time and prescaler register + GTPR : aliased GTPR_Register; + pragma Volatile_Full_Access (GTPR); end record with Volatile; - for UART4_Peripheral use record - SR at 0 range 0 .. 31; - DR at 4 range 0 .. 31; - BRR at 8 range 0 .. 31; - CR1 at 12 range 0 .. 31; - CR2 at 16 range 0 .. 31; - CR3 at 20 range 0 .. 31; + for USART1_Peripheral use record + SR at 16#0# range 0 .. 31; + DR at 16#4# range 0 .. 31; + BRR at 16#8# range 0 .. 31; + CR1 at 16#C# range 0 .. 31; + CR2 at 16#10# range 0 .. 31; + CR3 at 16#14# range 0 .. 31; + GTPR at 16#18# range 0 .. 31; end record; -- Universal synchronous asynchronous receiver transmitter - UART4_Periph : aliased UART4_Peripheral - with Import, Address => System'To_Address (16#40004C00#); + USART1_Periph : aliased USART1_Peripheral + with Import, Address => USART1_Base; -- Universal synchronous asynchronous receiver transmitter - UART5_Periph : aliased UART4_Peripheral - with Import, Address => System'To_Address (16#40005000#); + USART2_Periph : aliased USART1_Peripheral + with Import, Address => USART2_Base; + + -- Universal synchronous asynchronous receiver transmitter + USART3_Periph : aliased USART1_Peripheral + with Import, Address => USART3_Base; + + -- Universal synchronous asynchronous receiver transmitter + USART6_Periph : aliased USART1_Peripheral + with Import, Address => USART6_Base; end STM32F429x.USART; diff --git a/stm32f429i/stm32f429x/stm32f429x-usb_otg_fs.ads b/stm32f429i/stm32f429x/stm32f429x-usb_otg_fs.ads index e758c6d..46610fd 100644 --- a/stm32f429i/stm32f429x/stm32f429x-usb_otg_fs.ads +++ b/stm32f429i/stm32f429x/stm32f429x-usb_otg_fs.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,1959 +14,1830 @@ package STM32F429x.USB_OTG_FS is -- Registers -- --------------- - ------------------------- - -- FS_GOTGCTL_Register -- - ------------------------- - - subtype FS_GOTGCTL_SRQSCS_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_SRQ_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_HNGSCS_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_HNPRQ_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_HSHNPEN_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_DHNPEN_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_CIDSTS_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_DBCT_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_ASVLD_Field is STM32F429x.Bit; - subtype FS_GOTGCTL_BSVLD_Field is STM32F429x.Bit; + subtype FS_DCFG_DSPD_Field is STM32F429x.UInt2; + subtype FS_DCFG_NZLSOHSK_Field is STM32F429x.Bit; + subtype FS_DCFG_DAD_Field is STM32F429x.UInt7; + subtype FS_DCFG_PFIVL_Field is STM32F429x.UInt2; - -- OTG_FS control and status register (OTG_FS_GOTGCTL) - type FS_GOTGCTL_Register is record - -- Session request success - SRQSCS : FS_GOTGCTL_SRQSCS_Field := 16#0#; - -- Session request - SRQ : FS_GOTGCTL_SRQ_Field := 16#0#; - -- unspecified - Reserved_2_7 : STM32F429x.UInt6 := 16#0#; - -- Host negotiation success - HNGSCS : FS_GOTGCTL_HNGSCS_Field := 16#0#; - -- HNP request - HNPRQ : FS_GOTGCTL_HNPRQ_Field := 16#0#; - -- Host set HNP enable - HSHNPEN : FS_GOTGCTL_HSHNPEN_Field := 16#0#; - -- Device HNP enabled - DHNPEN : FS_GOTGCTL_DHNPEN_Field := 16#1#; + -- OTG_FS device configuration register (OTG_FS_DCFG) + type FS_DCFG_Register is record + -- Device speed + DSPD : FS_DCFG_DSPD_Field := 16#0#; + -- Non-zero-length status OUT handshake + NZLSOHSK : FS_DCFG_NZLSOHSK_Field := 16#0#; -- unspecified - Reserved_12_15 : STM32F429x.UInt4 := 16#0#; - -- Connector ID status - CIDSTS : FS_GOTGCTL_CIDSTS_Field := 16#0#; - -- Long/short debounce time - DBCT : FS_GOTGCTL_DBCT_Field := 16#0#; - -- A-session valid - ASVLD : FS_GOTGCTL_ASVLD_Field := 16#0#; - -- B-session valid - BSVLD : FS_GOTGCTL_BSVLD_Field := 16#0#; + Reserved_3_3 : STM32F429x.Bit := 16#0#; + -- Device address + DAD : FS_DCFG_DAD_Field := 16#0#; + -- Periodic frame interval + PFIVL : FS_DCFG_PFIVL_Field := 16#0#; -- unspecified - Reserved_20_31 : STM32F429x.UInt12 := 16#0#; + Reserved_13_31 : STM32F429x.UInt19 := 16#1100#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GOTGCTL_Register use record - SRQSCS at 0 range 0 .. 0; - SRQ at 0 range 1 .. 1; - Reserved_2_7 at 0 range 2 .. 7; - HNGSCS at 0 range 8 .. 8; - HNPRQ at 0 range 9 .. 9; - HSHNPEN at 0 range 10 .. 10; - DHNPEN at 0 range 11 .. 11; - Reserved_12_15 at 0 range 12 .. 15; - CIDSTS at 0 range 16 .. 16; - DBCT at 0 range 17 .. 17; - ASVLD at 0 range 18 .. 18; - BSVLD at 0 range 19 .. 19; - Reserved_20_31 at 0 range 20 .. 31; + for FS_DCFG_Register use record + DSPD at 0 range 0 .. 1; + NZLSOHSK at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DAD at 0 range 4 .. 10; + PFIVL at 0 range 11 .. 12; + Reserved_13_31 at 0 range 13 .. 31; end record; - ------------------------- - -- FS_GOTGINT_Register -- - ------------------------- - - subtype FS_GOTGINT_SEDET_Field is STM32F429x.Bit; - subtype FS_GOTGINT_SRSSCHG_Field is STM32F429x.Bit; - subtype FS_GOTGINT_HNSSCHG_Field is STM32F429x.Bit; - subtype FS_GOTGINT_HNGDET_Field is STM32F429x.Bit; - subtype FS_GOTGINT_ADTOCHG_Field is STM32F429x.Bit; - subtype FS_GOTGINT_DBCDNE_Field is STM32F429x.Bit; + subtype FS_DCTL_RWUSIG_Field is STM32F429x.Bit; + subtype FS_DCTL_SDIS_Field is STM32F429x.Bit; + subtype FS_DCTL_GINSTS_Field is STM32F429x.Bit; + subtype FS_DCTL_GONSTS_Field is STM32F429x.Bit; + subtype FS_DCTL_TCTL_Field is STM32F429x.UInt3; + subtype FS_DCTL_SGINAK_Field is STM32F429x.Bit; + subtype FS_DCTL_CGINAK_Field is STM32F429x.Bit; + subtype FS_DCTL_SGONAK_Field is STM32F429x.Bit; + subtype FS_DCTL_CGONAK_Field is STM32F429x.Bit; + subtype FS_DCTL_POPRGDNE_Field is STM32F429x.Bit; - -- OTG_FS interrupt register (OTG_FS_GOTGINT) - type FS_GOTGINT_Register is record - -- unspecified - Reserved_0_1 : STM32F429x.UInt2 := 16#0#; - -- Session end detected - SEDET : FS_GOTGINT_SEDET_Field := 16#0#; - -- unspecified - Reserved_3_7 : STM32F429x.UInt5 := 16#0#; - -- Session request success status change - SRSSCHG : FS_GOTGINT_SRSSCHG_Field := 16#0#; - -- Host negotiation success status change - HNSSCHG : FS_GOTGINT_HNSSCHG_Field := 16#0#; - -- unspecified - Reserved_10_16 : STM32F429x.UInt7 := 16#0#; - -- Host negotiation detected - HNGDET : FS_GOTGINT_HNGDET_Field := 16#0#; - -- A-device timeout change - ADTOCHG : FS_GOTGINT_ADTOCHG_Field := 16#0#; - -- Debounce done - DBCDNE : FS_GOTGINT_DBCDNE_Field := 16#0#; + -- OTG_FS device control register (OTG_FS_DCTL) + type FS_DCTL_Register is record + -- Remote wakeup signaling + RWUSIG : FS_DCTL_RWUSIG_Field := 16#0#; + -- Soft disconnect + SDIS : FS_DCTL_SDIS_Field := 16#0#; + -- Read-only. Global IN NAK status + GINSTS : FS_DCTL_GINSTS_Field := 16#0#; + -- Read-only. Global OUT NAK status + GONSTS : FS_DCTL_GONSTS_Field := 16#0#; + -- Test control + TCTL : FS_DCTL_TCTL_Field := 16#0#; + -- Set global IN NAK + SGINAK : FS_DCTL_SGINAK_Field := 16#0#; + -- Clear global IN NAK + CGINAK : FS_DCTL_CGINAK_Field := 16#0#; + -- Set global OUT NAK + SGONAK : FS_DCTL_SGONAK_Field := 16#0#; + -- Clear global OUT NAK + CGONAK : FS_DCTL_CGONAK_Field := 16#0#; + -- Power-on programming done + POPRGDNE : FS_DCTL_POPRGDNE_Field := 16#0#; -- unspecified - Reserved_20_31 : STM32F429x.UInt12 := 16#0#; + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GOTGINT_Register use record - Reserved_0_1 at 0 range 0 .. 1; - SEDET at 0 range 2 .. 2; - Reserved_3_7 at 0 range 3 .. 7; - SRSSCHG at 0 range 8 .. 8; - HNSSCHG at 0 range 9 .. 9; - Reserved_10_16 at 0 range 10 .. 16; - HNGDET at 0 range 17 .. 17; - ADTOCHG at 0 range 18 .. 18; - DBCDNE at 0 range 19 .. 19; - Reserved_20_31 at 0 range 20 .. 31; + for FS_DCTL_Register use record + RWUSIG at 0 range 0 .. 0; + SDIS at 0 range 1 .. 1; + GINSTS at 0 range 2 .. 2; + GONSTS at 0 range 3 .. 3; + TCTL at 0 range 4 .. 6; + SGINAK at 0 range 7 .. 7; + CGINAK at 0 range 8 .. 8; + SGONAK at 0 range 9 .. 9; + CGONAK at 0 range 10 .. 10; + POPRGDNE at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; end record; - ------------------------- - -- FS_GAHBCFG_Register -- - ------------------------- - - subtype FS_GAHBCFG_GINT_Field is STM32F429x.Bit; - subtype FS_GAHBCFG_TXFELVL_Field is STM32F429x.Bit; - subtype FS_GAHBCFG_PTXFELVL_Field is STM32F429x.Bit; + subtype FS_DSTS_SUSPSTS_Field is STM32F429x.Bit; + subtype FS_DSTS_ENUMSPD_Field is STM32F429x.UInt2; + subtype FS_DSTS_EERR_Field is STM32F429x.Bit; + subtype FS_DSTS_FNSOF_Field is STM32F429x.UInt14; - -- OTG_FS AHB configuration register (OTG_FS_GAHBCFG) - type FS_GAHBCFG_Register is record - -- Global interrupt mask - GINT : FS_GAHBCFG_GINT_Field := 16#0#; + -- OTG_FS device status register (OTG_FS_DSTS) + type FS_DSTS_Register is record + -- Read-only. Suspend status + SUSPSTS : FS_DSTS_SUSPSTS_Field; + -- Read-only. Enumerated speed + ENUMSPD : FS_DSTS_ENUMSPD_Field; + -- Read-only. Erratic error + EERR : FS_DSTS_EERR_Field; -- unspecified - Reserved_1_6 : STM32F429x.UInt6 := 16#0#; - -- TxFIFO empty level - TXFELVL : FS_GAHBCFG_TXFELVL_Field := 16#0#; - -- Periodic TxFIFO empty level - PTXFELVL : FS_GAHBCFG_PTXFELVL_Field := 16#0#; + Reserved_4_7 : STM32F429x.UInt4; + -- Read-only. Frame number of the received SOF + FNSOF : FS_DSTS_FNSOF_Field; -- unspecified - Reserved_9_31 : STM32F429x.UInt23 := 16#0#; + Reserved_22_31 : STM32F429x.UInt10; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GAHBCFG_Register use record - GINT at 0 range 0 .. 0; - Reserved_1_6 at 0 range 1 .. 6; - TXFELVL at 0 range 7 .. 7; - PTXFELVL at 0 range 8 .. 8; - Reserved_9_31 at 0 range 9 .. 31; + for FS_DSTS_Register use record + SUSPSTS at 0 range 0 .. 0; + ENUMSPD at 0 range 1 .. 2; + EERR at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + FNSOF at 0 range 8 .. 21; + Reserved_22_31 at 0 range 22 .. 31; end record; - ------------------------- - -- FS_GUSBCFG_Register -- - ------------------------- - - subtype FS_GUSBCFG_TOCAL_Field is STM32F429x.UInt3; - subtype FS_GUSBCFG_PHYSEL_Field is STM32F429x.Bit; - subtype FS_GUSBCFG_SRPCAP_Field is STM32F429x.Bit; - subtype FS_GUSBCFG_HNPCAP_Field is STM32F429x.Bit; - subtype FS_GUSBCFG_TRDT_Field is STM32F429x.UInt4; - subtype FS_GUSBCFG_FHMOD_Field is STM32F429x.Bit; - subtype FS_GUSBCFG_FDMOD_Field is STM32F429x.Bit; - subtype FS_GUSBCFG_CTXPKT_Field is STM32F429x.Bit; + subtype FS_DIEPMSK_XFRCM_Field is STM32F429x.Bit; + subtype FS_DIEPMSK_EPDM_Field is STM32F429x.Bit; + subtype FS_DIEPMSK_TOM_Field is STM32F429x.Bit; + subtype FS_DIEPMSK_ITTXFEMSK_Field is STM32F429x.Bit; + subtype FS_DIEPMSK_INEPNMM_Field is STM32F429x.Bit; + subtype FS_DIEPMSK_INEPNEM_Field is STM32F429x.Bit; - -- OTG_FS USB configuration register (OTG_FS_GUSBCFG) - type FS_GUSBCFG_Register is record - -- FS timeout calibration - TOCAL : FS_GUSBCFG_TOCAL_Field := 16#0#; - -- unspecified - Reserved_3_5 : STM32F429x.UInt3 := 16#0#; - -- Full Speed serial transceiver select - PHYSEL : FS_GUSBCFG_PHYSEL_Field := 16#0#; + -- OTG_FS device IN endpoint common interrupt mask register + -- (OTG_FS_DIEPMSK) + type FS_DIEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : FS_DIEPMSK_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : FS_DIEPMSK_EPDM_Field := 16#0#; -- unspecified - Reserved_7_7 : STM32F429x.Bit := 16#0#; - -- SRP-capable - SRPCAP : FS_GUSBCFG_SRPCAP_Field := 16#0#; - -- HNP-capable - HNPCAP : FS_GUSBCFG_HNPCAP_Field := 16#1#; - -- USB turnaround time - TRDT : FS_GUSBCFG_TRDT_Field := 16#2#; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- Timeout condition mask (Non-isochronous endpoints) + TOM : FS_DIEPMSK_TOM_Field := 16#0#; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : FS_DIEPMSK_ITTXFEMSK_Field := 16#0#; + -- IN token received with EP mismatch mask + INEPNMM : FS_DIEPMSK_INEPNMM_Field := 16#0#; + -- IN endpoint NAK effective mask + INEPNEM : FS_DIEPMSK_INEPNEM_Field := 16#0#; -- unspecified - Reserved_14_28 : STM32F429x.UInt15 := 16#0#; - -- Force host mode - FHMOD : FS_GUSBCFG_FHMOD_Field := 16#0#; - -- Force device mode - FDMOD : FS_GUSBCFG_FDMOD_Field := 16#0#; - -- Corrupt Tx packet - CTXPKT : FS_GUSBCFG_CTXPKT_Field := 16#0#; + Reserved_7_31 : STM32F429x.UInt25 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GUSBCFG_Register use record - TOCAL at 0 range 0 .. 2; - Reserved_3_5 at 0 range 3 .. 5; - PHYSEL at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - SRPCAP at 0 range 8 .. 8; - HNPCAP at 0 range 9 .. 9; - TRDT at 0 range 10 .. 13; - Reserved_14_28 at 0 range 14 .. 28; - FHMOD at 0 range 29 .. 29; - FDMOD at 0 range 30 .. 30; - CTXPKT at 0 range 31 .. 31; - end record; - - ------------------------- - -- FS_GRSTCTL_Register -- - ------------------------- + for FS_DIEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; - subtype FS_GRSTCTL_CSRST_Field is STM32F429x.Bit; - subtype FS_GRSTCTL_HSRST_Field is STM32F429x.Bit; - subtype FS_GRSTCTL_FCRST_Field is STM32F429x.Bit; - subtype FS_GRSTCTL_RXFFLSH_Field is STM32F429x.Bit; - subtype FS_GRSTCTL_TXFFLSH_Field is STM32F429x.Bit; - subtype FS_GRSTCTL_TXFNUM_Field is STM32F429x.UInt5; - subtype FS_GRSTCTL_AHBIDL_Field is STM32F429x.Bit; + subtype FS_DOEPMSK_XFRCM_Field is STM32F429x.Bit; + subtype FS_DOEPMSK_EPDM_Field is STM32F429x.Bit; + subtype FS_DOEPMSK_STUPM_Field is STM32F429x.Bit; + subtype FS_DOEPMSK_OTEPDM_Field is STM32F429x.Bit; - -- OTG_FS reset register (OTG_FS_GRSTCTL) - type FS_GRSTCTL_Register is record - -- Core soft reset - CSRST : FS_GRSTCTL_CSRST_Field := 16#0#; - -- HCLK soft reset - HSRST : FS_GRSTCTL_HSRST_Field := 16#0#; - -- Host frame counter reset - FCRST : FS_GRSTCTL_FCRST_Field := 16#0#; + -- OTG_FS device OUT endpoint common interrupt mask register + -- (OTG_FS_DOEPMSK) + type FS_DOEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : FS_DOEPMSK_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : FS_DOEPMSK_EPDM_Field := 16#0#; -- unspecified - Reserved_3_3 : STM32F429x.Bit := 16#0#; - -- RxFIFO flush - RXFFLSH : FS_GRSTCTL_RXFFLSH_Field := 16#0#; - -- TxFIFO flush - TXFFLSH : FS_GRSTCTL_TXFFLSH_Field := 16#0#; - -- TxFIFO number - TXFNUM : FS_GRSTCTL_TXFNUM_Field := 16#0#; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- SETUP phase done mask + STUPM : FS_DOEPMSK_STUPM_Field := 16#0#; + -- OUT token received when endpoint disabled mask + OTEPDM : FS_DOEPMSK_OTEPDM_Field := 16#0#; -- unspecified - Reserved_11_30 : STM32F429x.UInt20 := 16#40000#; - -- AHB master idle - AHBIDL : FS_GRSTCTL_AHBIDL_Field := 16#0#; + Reserved_5_31 : STM32F429x.UInt27 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GRSTCTL_Register use record - CSRST at 0 range 0 .. 0; - HSRST at 0 range 1 .. 1; - FCRST at 0 range 2 .. 2; - Reserved_3_3 at 0 range 3 .. 3; - RXFFLSH at 0 range 4 .. 4; - TXFFLSH at 0 range 5 .. 5; - TXFNUM at 0 range 6 .. 10; - Reserved_11_30 at 0 range 11 .. 30; - AHBIDL at 0 range 31 .. 31; + for FS_DOEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUPM at 0 range 3 .. 3; + OTEPDM at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; end record; - ------------------------- - -- FS_GINTSTS_Register -- - ------------------------- + subtype FS_DAINT_IEPINT_Field is STM32F429x.UInt16; + subtype FS_DAINT_OEPINT_Field is STM32F429x.UInt16; - subtype FS_GINTSTS_CMOD_Field is STM32F429x.Bit; - subtype FS_GINTSTS_MMIS_Field is STM32F429x.Bit; - subtype FS_GINTSTS_OTGINT_Field is STM32F429x.Bit; - subtype FS_GINTSTS_SOF_Field is STM32F429x.Bit; - subtype FS_GINTSTS_RXFLVL_Field is STM32F429x.Bit; - subtype FS_GINTSTS_NPTXFE_Field is STM32F429x.Bit; - subtype FS_GINTSTS_GINAKEFF_Field is STM32F429x.Bit; - subtype FS_GINTSTS_GOUTNAKEFF_Field is STM32F429x.Bit; - subtype FS_GINTSTS_ESUSP_Field is STM32F429x.Bit; - subtype FS_GINTSTS_USBSUSP_Field is STM32F429x.Bit; - subtype FS_GINTSTS_USBRST_Field is STM32F429x.Bit; - subtype FS_GINTSTS_ENUMDNE_Field is STM32F429x.Bit; - subtype FS_GINTSTS_ISOODRP_Field is STM32F429x.Bit; - subtype FS_GINTSTS_EOPF_Field is STM32F429x.Bit; - subtype FS_GINTSTS_IEPINT_Field is STM32F429x.Bit; - subtype FS_GINTSTS_OEPINT_Field is STM32F429x.Bit; - subtype FS_GINTSTS_IISOIXFR_Field is STM32F429x.Bit; - subtype FS_GINTSTS_IPXFR_INCOMPISOOUT_Field is STM32F429x.Bit; - subtype FS_GINTSTS_HPRTINT_Field is STM32F429x.Bit; - subtype FS_GINTSTS_HCINT_Field is STM32F429x.Bit; - subtype FS_GINTSTS_PTXFE_Field is STM32F429x.Bit; - subtype FS_GINTSTS_CIDSCHG_Field is STM32F429x.Bit; - subtype FS_GINTSTS_DISCINT_Field is STM32F429x.Bit; - subtype FS_GINTSTS_SRQINT_Field is STM32F429x.Bit; - subtype FS_GINTSTS_WKUPINT_Field is STM32F429x.Bit; + -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + type FS_DAINT_Register is record + -- Read-only. IN endpoint interrupt bits + IEPINT : FS_DAINT_IEPINT_Field; + -- Read-only. OUT endpoint interrupt bits + OEPINT : FS_DAINT_OEPINT_Field; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG_FS core interrupt register (OTG_FS_GINTSTS) - type FS_GINTSTS_Register is record - -- Current mode of operation - CMOD : FS_GINTSTS_CMOD_Field := 16#0#; - -- Mode mismatch interrupt - MMIS : FS_GINTSTS_MMIS_Field := 16#0#; - -- OTG interrupt - OTGINT : FS_GINTSTS_OTGINT_Field := 16#0#; - -- Start of frame - SOF : FS_GINTSTS_SOF_Field := 16#0#; - -- RxFIFO non-empty - RXFLVL : FS_GINTSTS_RXFLVL_Field := 16#0#; - -- Non-periodic TxFIFO empty - NPTXFE : FS_GINTSTS_NPTXFE_Field := 16#1#; - -- Global IN non-periodic NAK effective - GINAKEFF : FS_GINTSTS_GINAKEFF_Field := 16#0#; - -- Global OUT NAK effective - GOUTNAKEFF : FS_GINTSTS_GOUTNAKEFF_Field := 16#0#; - -- unspecified - Reserved_8_9 : STM32F429x.UInt2 := 16#0#; - -- Early suspend - ESUSP : FS_GINTSTS_ESUSP_Field := 16#0#; - -- USB suspend - USBSUSP : FS_GINTSTS_USBSUSP_Field := 16#0#; - -- USB reset - USBRST : FS_GINTSTS_USBRST_Field := 16#0#; - -- Enumeration done - ENUMDNE : FS_GINTSTS_ENUMDNE_Field := 16#0#; - -- Isochronous OUT packet dropped interrupt - ISOODRP : FS_GINTSTS_ISOODRP_Field := 16#0#; - -- End of periodic frame interrupt - EOPF : FS_GINTSTS_EOPF_Field := 16#0#; - -- unspecified - Reserved_16_17 : STM32F429x.UInt2 := 16#0#; - -- IN endpoint interrupt - IEPINT : FS_GINTSTS_IEPINT_Field := 16#0#; - -- OUT endpoint interrupt - OEPINT : FS_GINTSTS_OEPINT_Field := 16#0#; - -- Incomplete isochronous IN transfer - IISOIXFR : FS_GINTSTS_IISOIXFR_Field := 16#0#; - -- Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT - -- transfer(Device mode) - IPXFR_INCOMPISOOUT : FS_GINTSTS_IPXFR_INCOMPISOOUT_Field := 16#0#; - -- unspecified - Reserved_22_23 : STM32F429x.UInt2 := 16#0#; - -- Host port interrupt - HPRTINT : FS_GINTSTS_HPRTINT_Field := 16#0#; - -- Host channels interrupt - HCINT : FS_GINTSTS_HCINT_Field := 16#0#; - -- Periodic TxFIFO empty - PTXFE : FS_GINTSTS_PTXFE_Field := 16#1#; + for FS_DAINT_Register use record + IEPINT at 0 range 0 .. 15; + OEPINT at 0 range 16 .. 31; + end record; + + subtype FS_DAINTMSK_IEPM_Field is STM32F429x.UInt16; + subtype FS_DAINTMSK_OEPM_Field is STM32F429x.UInt16; + + -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + type FS_DAINTMSK_Register is record + -- IN EP interrupt mask bits + IEPM : FS_DAINTMSK_IEPM_Field := 16#0#; + -- OUT EP interrupt mask bits + OEPM : FS_DAINTMSK_OEPM_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for FS_DAINTMSK_Register use record + IEPM at 0 range 0 .. 15; + OEPM at 0 range 16 .. 31; + end record; + + subtype DVBUSDIS_VBUSDT_Field is STM32F429x.UInt16; + + -- OTG_FS device VBUS discharge time register + type DVBUSDIS_Register is record + -- Device VBUS discharge time + VBUSDT : DVBUSDIS_VBUSDT_Field := 16#17D7#; -- unspecified - Reserved_27_27 : STM32F429x.Bit := 16#0#; - -- Connector ID status change - CIDSCHG : FS_GINTSTS_CIDSCHG_Field := 16#0#; - -- Disconnect detected interrupt - DISCINT : FS_GINTSTS_DISCINT_Field := 16#0#; - -- Session request/new session detected interrupt - SRQINT : FS_GINTSTS_SRQINT_Field := 16#0#; - -- Resume/remote wakeup detected interrupt - WKUPINT : FS_GINTSTS_WKUPINT_Field := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GINTSTS_Register use record - CMOD at 0 range 0 .. 0; - MMIS at 0 range 1 .. 1; - OTGINT at 0 range 2 .. 2; - SOF at 0 range 3 .. 3; - RXFLVL at 0 range 4 .. 4; - NPTXFE at 0 range 5 .. 5; - GINAKEFF at 0 range 6 .. 6; - GOUTNAKEFF at 0 range 7 .. 7; - Reserved_8_9 at 0 range 8 .. 9; - ESUSP at 0 range 10 .. 10; - USBSUSP at 0 range 11 .. 11; - USBRST at 0 range 12 .. 12; - ENUMDNE at 0 range 13 .. 13; - ISOODRP at 0 range 14 .. 14; - EOPF at 0 range 15 .. 15; - Reserved_16_17 at 0 range 16 .. 17; - IEPINT at 0 range 18 .. 18; - OEPINT at 0 range 19 .. 19; - IISOIXFR at 0 range 20 .. 20; - IPXFR_INCOMPISOOUT at 0 range 21 .. 21; - Reserved_22_23 at 0 range 22 .. 23; - HPRTINT at 0 range 24 .. 24; - HCINT at 0 range 25 .. 25; - PTXFE at 0 range 26 .. 26; - Reserved_27_27 at 0 range 27 .. 27; - CIDSCHG at 0 range 28 .. 28; - DISCINT at 0 range 29 .. 29; - SRQINT at 0 range 30 .. 30; - WKUPINT at 0 range 31 .. 31; + for DVBUSDIS_Register use record + VBUSDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------------- - -- FS_GINTMSK_Register -- - ------------------------- + subtype DVBUSPULSE_DVBUSP_Field is STM32F429x.UInt12; - subtype FS_GINTMSK_MMISM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_OTGINT_Field is STM32F429x.Bit; - subtype FS_GINTMSK_SOFM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_RXFLVLM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_NPTXFEM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_GINAKEFFM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_GONAKEFFM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_ESUSPM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_USBSUSPM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_USBRST_Field is STM32F429x.Bit; - subtype FS_GINTMSK_ENUMDNEM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_ISOODRPM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_EOPFM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_EPMISM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_IEPINT_Field is STM32F429x.Bit; - subtype FS_GINTMSK_OEPINT_Field is STM32F429x.Bit; - subtype FS_GINTMSK_IISOIXFRM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_IPXFRM_IISOOXFRM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_PRTIM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_HCIM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_PTXFEM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_CIDSCHGM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_DISCINT_Field is STM32F429x.Bit; - subtype FS_GINTMSK_SRQIM_Field is STM32F429x.Bit; - subtype FS_GINTMSK_WUIM_Field is STM32F429x.Bit; + -- OTG_FS device VBUS pulsing time register + type DVBUSPULSE_Register is record + -- Device VBUS pulsing time + DVBUSP : DVBUSPULSE_DVBUSP_Field := 16#5B8#; + -- unspecified + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG_FS interrupt mask register (OTG_FS_GINTMSK) - type FS_GINTMSK_Register is record + for DVBUSPULSE_Register use record + DVBUSP at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype DIEPEMPMSK_INEPTXFEM_Field is STM32F429x.UInt16; + + -- OTG_FS device IN endpoint FIFO empty interrupt mask register + type DIEPEMPMSK_Register is record + -- IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM : DIEPEMPMSK_INEPTXFEM_Field := 16#0#; -- unspecified - Reserved_0_0 : STM32F429x.Bit := 16#0#; - -- Mode mismatch interrupt mask - MMISM : FS_GINTMSK_MMISM_Field := 16#0#; - -- OTG interrupt mask - OTGINT : FS_GINTMSK_OTGINT_Field := 16#0#; - -- Start of frame mask - SOFM : FS_GINTMSK_SOFM_Field := 16#0#; - -- Receive FIFO non-empty mask - RXFLVLM : FS_GINTMSK_RXFLVLM_Field := 16#0#; - -- Non-periodic TxFIFO empty mask - NPTXFEM : FS_GINTMSK_NPTXFEM_Field := 16#0#; - -- Global non-periodic IN NAK effective mask - GINAKEFFM : FS_GINTMSK_GINAKEFFM_Field := 16#0#; - -- Global OUT NAK effective mask - GONAKEFFM : FS_GINTMSK_GONAKEFFM_Field := 16#0#; - -- unspecified - Reserved_8_9 : STM32F429x.UInt2 := 16#0#; - -- Early suspend mask - ESUSPM : FS_GINTMSK_ESUSPM_Field := 16#0#; - -- USB suspend mask - USBSUSPM : FS_GINTMSK_USBSUSPM_Field := 16#0#; - -- USB reset mask - USBRST : FS_GINTMSK_USBRST_Field := 16#0#; - -- Enumeration done mask - ENUMDNEM : FS_GINTMSK_ENUMDNEM_Field := 16#0#; - -- Isochronous OUT packet dropped interrupt mask - ISOODRPM : FS_GINTMSK_ISOODRPM_Field := 16#0#; - -- End of periodic frame interrupt mask - EOPFM : FS_GINTMSK_EOPFM_Field := 16#0#; - -- unspecified - Reserved_16_16 : STM32F429x.Bit := 16#0#; - -- Endpoint mismatch interrupt mask - EPMISM : FS_GINTMSK_EPMISM_Field := 16#0#; - -- IN endpoints interrupt mask - IEPINT : FS_GINTMSK_IEPINT_Field := 16#0#; - -- OUT endpoints interrupt mask - OEPINT : FS_GINTMSK_OEPINT_Field := 16#0#; - -- Incomplete isochronous IN transfer mask - IISOIXFRM : FS_GINTMSK_IISOIXFRM_Field := 16#0#; - -- Incomplete periodic transfer mask(Host mode)/Incomplete isochronous - -- OUT transfer mask(Device mode) - IPXFRM_IISOOXFRM : FS_GINTMSK_IPXFRM_IISOOXFRM_Field := 16#0#; - -- unspecified - Reserved_22_23 : STM32F429x.UInt2 := 16#0#; - -- Host port interrupt mask - PRTIM : FS_GINTMSK_PRTIM_Field := 16#0#; - -- Host channels interrupt mask - HCIM : FS_GINTMSK_HCIM_Field := 16#0#; - -- Periodic TxFIFO empty mask - PTXFEM : FS_GINTMSK_PTXFEM_Field := 16#0#; - -- unspecified - Reserved_27_27 : STM32F429x.Bit := 16#0#; - -- Connector ID status change mask - CIDSCHGM : FS_GINTMSK_CIDSCHGM_Field := 16#0#; - -- Disconnect detected interrupt mask - DISCINT : FS_GINTMSK_DISCINT_Field := 16#0#; - -- Session request/new session detected interrupt mask - SRQIM : FS_GINTMSK_SRQIM_Field := 16#0#; - -- Resume/remote wakeup detected interrupt mask - WUIM : FS_GINTMSK_WUIM_Field := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GINTMSK_Register use record - Reserved_0_0 at 0 range 0 .. 0; - MMISM at 0 range 1 .. 1; - OTGINT at 0 range 2 .. 2; - SOFM at 0 range 3 .. 3; - RXFLVLM at 0 range 4 .. 4; - NPTXFEM at 0 range 5 .. 5; - GINAKEFFM at 0 range 6 .. 6; - GONAKEFFM at 0 range 7 .. 7; - Reserved_8_9 at 0 range 8 .. 9; - ESUSPM at 0 range 10 .. 10; - USBSUSPM at 0 range 11 .. 11; - USBRST at 0 range 12 .. 12; - ENUMDNEM at 0 range 13 .. 13; - ISOODRPM at 0 range 14 .. 14; - EOPFM at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - EPMISM at 0 range 17 .. 17; - IEPINT at 0 range 18 .. 18; - OEPINT at 0 range 19 .. 19; - IISOIXFRM at 0 range 20 .. 20; - IPXFRM_IISOOXFRM at 0 range 21 .. 21; - Reserved_22_23 at 0 range 22 .. 23; - PRTIM at 0 range 24 .. 24; - HCIM at 0 range 25 .. 25; - PTXFEM at 0 range 26 .. 26; - Reserved_27_27 at 0 range 27 .. 27; - CIDSCHGM at 0 range 28 .. 28; - DISCINT at 0 range 29 .. 29; - SRQIM at 0 range 30 .. 30; - WUIM at 0 range 31 .. 31; + for DIEPEMPMSK_Register use record + INEPTXFEM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------------------- - -- FS_GRXSTSR_Device_Register -- - -------------------------------- - - subtype FS_GRXSTSR_Device_EPNUM_Field is STM32F429x.UInt4; - subtype FS_GRXSTSR_Device_BCNT_Field is STM32F429x.UInt11; - subtype FS_GRXSTSR_Device_DPID_Field is STM32F429x.UInt2; - subtype FS_GRXSTSR_Device_PKTSTS_Field is STM32F429x.UInt4; - subtype FS_GRXSTSR_Device_FRMNUM_Field is STM32F429x.UInt4; + subtype FS_DIEPCTL0_MPSIZ_Field is STM32F429x.UInt2; + subtype FS_DIEPCTL0_USBAEP_Field is STM32F429x.Bit; + subtype FS_DIEPCTL0_NAKSTS_Field is STM32F429x.Bit; + subtype FS_DIEPCTL0_EPTYP_Field is STM32F429x.UInt2; + subtype FS_DIEPCTL0_STALL_Field is STM32F429x.Bit; + subtype FS_DIEPCTL0_TXFNUM_Field is STM32F429x.UInt4; + subtype FS_DIEPCTL0_CNAK_Field is STM32F429x.Bit; + subtype FS_DIEPCTL0_SNAK_Field is STM32F429x.Bit; + subtype FS_DIEPCTL0_EPDIS_Field is STM32F429x.Bit; + subtype FS_DIEPCTL0_EPENA_Field is STM32F429x.Bit; - -- OTG_FS Receive status debug read(Device mode) - type FS_GRXSTSR_Device_Register is record - -- Endpoint number - EPNUM : FS_GRXSTSR_Device_EPNUM_Field; - -- Byte count - BCNT : FS_GRXSTSR_Device_BCNT_Field; - -- Data PID - DPID : FS_GRXSTSR_Device_DPID_Field; - -- Packet status - PKTSTS : FS_GRXSTSR_Device_PKTSTS_Field; - -- Frame number - FRMNUM : FS_GRXSTSR_Device_FRMNUM_Field; + -- OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + type FS_DIEPCTL0_Register is record + -- Maximum packet size + MPSIZ : FS_DIEPCTL0_MPSIZ_Field := 16#0#; -- unspecified - Reserved_25_31 : STM32F429x.UInt7; + Reserved_2_14 : STM32F429x.UInt13 := 16#0#; + -- Read-only. USB active endpoint + USBAEP : FS_DIEPCTL0_USBAEP_Field := 16#0#; + -- unspecified + Reserved_16_16 : STM32F429x.Bit := 16#0#; + -- Read-only. NAK status + NAKSTS : FS_DIEPCTL0_NAKSTS_Field := 16#0#; + -- Read-only. Endpoint type + EPTYP : FS_DIEPCTL0_EPTYP_Field := 16#0#; + -- unspecified + Reserved_20_20 : STM32F429x.Bit := 16#0#; + -- STALL handshake + STALL : FS_DIEPCTL0_STALL_Field := 16#0#; + -- TxFIFO number + TXFNUM : FS_DIEPCTL0_TXFNUM_Field := 16#0#; + -- Write-only. Clear NAK + CNAK : FS_DIEPCTL0_CNAK_Field := 16#0#; + -- Write-only. Set NAK + SNAK : FS_DIEPCTL0_SNAK_Field := 16#0#; + -- unspecified + Reserved_28_29 : STM32F429x.UInt2 := 16#0#; + -- Read-only. Endpoint disable + EPDIS : FS_DIEPCTL0_EPDIS_Field := 16#0#; + -- Read-only. Endpoint enable + EPENA : FS_DIEPCTL0_EPENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GRXSTSR_Device_Register use record - EPNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - FRMNUM at 0 range 21 .. 24; - Reserved_25_31 at 0 range 25 .. 31; + for FS_DIEPCTL0_Register use record + MPSIZ at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + USBAEP at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + STALL at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - ------------------------------ - -- FS_GRXSTSR_Host_Register -- - ------------------------------ + subtype DIEPINT_XFRC_Field is STM32F429x.Bit; + subtype DIEPINT_EPDISD_Field is STM32F429x.Bit; + subtype DIEPINT_TOC_Field is STM32F429x.Bit; + subtype DIEPINT_ITTXFE_Field is STM32F429x.Bit; + subtype DIEPINT_INEPNE_Field is STM32F429x.Bit; + subtype DIEPINT_TXFE_Field is STM32F429x.Bit; - subtype FS_GRXSTSR_Host_EPNUM_Field is STM32F429x.UInt4; - subtype FS_GRXSTSR_Host_BCNT_Field is STM32F429x.UInt11; - subtype FS_GRXSTSR_Host_DPID_Field is STM32F429x.UInt2; - subtype FS_GRXSTSR_Host_PKTSTS_Field is STM32F429x.UInt4; - subtype FS_GRXSTSR_Host_FRMNUM_Field is STM32F429x.UInt4; - - -- OTG_FS Receive status debug read(Host mode) - type FS_GRXSTSR_Host_Register is record - -- Endpoint number - EPNUM : FS_GRXSTSR_Host_EPNUM_Field; - -- Byte count - BCNT : FS_GRXSTSR_Host_BCNT_Field; - -- Data PID - DPID : FS_GRXSTSR_Host_DPID_Field; - -- Packet status - PKTSTS : FS_GRXSTSR_Host_PKTSTS_Field; - -- Frame number - FRMNUM : FS_GRXSTSR_Host_FRMNUM_Field; + -- device endpoint-x interrupt register + type DIEPINT_Register is record + -- XFRC + XFRC : DIEPINT_XFRC_Field := 16#0#; + -- EPDISD + EPDISD : DIEPINT_EPDISD_Field := 16#0#; -- unspecified - Reserved_25_31 : STM32F429x.UInt7; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- TOC + TOC : DIEPINT_TOC_Field := 16#0#; + -- ITTXFE + ITTXFE : DIEPINT_ITTXFE_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- INEPNE + INEPNE : DIEPINT_INEPNE_Field := 16#0#; + -- Read-only. TXFE + TXFE : DIEPINT_TXFE_Field := 16#1#; + -- unspecified + Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GRXSTSR_Host_Register use record - EPNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - FRMNUM at 0 range 21 .. 24; - Reserved_25_31 at 0 range 25 .. 31; + for DIEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOC at 0 range 3 .. 3; + ITTXFE at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + INEPNE at 0 range 6 .. 6; + TXFE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------------- - -- FS_GRXFSIZ_Register -- - ------------------------- - - subtype FS_GRXFSIZ_RXFD_Field is STM32F429x.Short; + subtype DIEPTSIZ0_XFRSIZ_Field is STM32F429x.UInt7; + subtype DIEPTSIZ0_PKTCNT_Field is STM32F429x.UInt2; - -- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) - type FS_GRXFSIZ_Register is record - -- RxFIFO depth - RXFD : FS_GRXFSIZ_RXFD_Field := 16#200#; + -- device endpoint-0 transfer size register + type DIEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : DIEPTSIZ0_XFRSIZ_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_7_18 : STM32F429x.UInt12 := 16#0#; + -- Packet count + PKTCNT : DIEPTSIZ0_PKTCNT_Field := 16#0#; + -- unspecified + Reserved_21_31 : STM32F429x.UInt11 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GRXFSIZ_Register use record - RXFD at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for DIEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - ---------------------------------- - -- FS_GNPTXFSIZ_Device_Register -- - ---------------------------------- - - subtype FS_GNPTXFSIZ_Device_TX0FSA_Field is STM32F429x.Short; - subtype FS_GNPTXFSIZ_Device_TX0FD_Field is STM32F429x.Short; + subtype DTXFSTS_INEPTFSAV_Field is STM32F429x.UInt16; - -- OTG_FS non-periodic transmit FIFO size register (Device mode) - type FS_GNPTXFSIZ_Device_Register is record - -- Endpoint 0 transmit RAM start address - TX0FSA : FS_GNPTXFSIZ_Device_TX0FSA_Field := 16#200#; - -- Endpoint 0 TxFIFO depth - TX0FD : FS_GNPTXFSIZ_Device_TX0FD_Field := 16#0#; + -- OTG_FS device IN endpoint transmit FIFO status register + type DTXFSTS_Register is record + -- Read-only. IN endpoint TxFIFO space available + INEPTFSAV : DTXFSTS_INEPTFSAV_Field; + -- unspecified + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GNPTXFSIZ_Device_Register use record - TX0FSA at 0 range 0 .. 15; - TX0FD at 0 range 16 .. 31; + for DTXFSTS_Register use record + INEPTFSAV at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------------------- - -- FS_GNPTXFSIZ_Host_Register -- - -------------------------------- - - subtype FS_GNPTXFSIZ_Host_NPTXFSA_Field is STM32F429x.Short; - subtype FS_GNPTXFSIZ_Host_NPTXFD_Field is STM32F429x.Short; + subtype DIEPCTL1_MPSIZ_Field is STM32F429x.UInt11; + subtype DIEPCTL1_USBAEP_Field is STM32F429x.Bit; + subtype DIEPCTL1_EONUM_DPID_Field is STM32F429x.Bit; + subtype DIEPCTL1_NAKSTS_Field is STM32F429x.Bit; + subtype DIEPCTL1_EPTYP_Field is STM32F429x.UInt2; + subtype DIEPCTL1_Stall_Field is STM32F429x.Bit; + subtype DIEPCTL1_TXFNUM_Field is STM32F429x.UInt4; + subtype DIEPCTL1_CNAK_Field is STM32F429x.Bit; + subtype DIEPCTL1_SNAK_Field is STM32F429x.Bit; + subtype DIEPCTL1_SD0PID_SEVNFRM_Field is STM32F429x.Bit; + subtype DIEPCTL1_SODDFRM_SD1PID_Field is STM32F429x.Bit; + subtype DIEPCTL1_EPDIS_Field is STM32F429x.Bit; + subtype DIEPCTL1_EPENA_Field is STM32F429x.Bit; - -- OTG_FS non-periodic transmit FIFO size register (Host mode) - type FS_GNPTXFSIZ_Host_Register is record - -- Non-periodic transmit RAM start address - NPTXFSA : FS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; - -- Non-periodic TxFIFO depth - NPTXFD : FS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; + -- OTG device endpoint-1 control register + type DIEPCTL1_Register is record + -- MPSIZ + MPSIZ : DIEPCTL1_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : STM32F429x.UInt4 := 16#0#; + -- USBAEP + USBAEP : DIEPCTL1_USBAEP_Field := 16#0#; + -- Read-only. EONUM/DPID + EONUM_DPID : DIEPCTL1_EONUM_DPID_Field := 16#0#; + -- Read-only. NAKSTS + NAKSTS : DIEPCTL1_NAKSTS_Field := 16#0#; + -- EPTYP + EPTYP : DIEPCTL1_EPTYP_Field := 16#0#; + -- unspecified + Reserved_20_20 : STM32F429x.Bit := 16#0#; + -- Stall + Stall : DIEPCTL1_Stall_Field := 16#0#; + -- TXFNUM + TXFNUM : DIEPCTL1_TXFNUM_Field := 16#0#; + -- Write-only. CNAK + CNAK : DIEPCTL1_CNAK_Field := 16#0#; + -- Write-only. SNAK + SNAK : DIEPCTL1_SNAK_Field := 16#0#; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : DIEPCTL1_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. SODDFRM/SD1PID + SODDFRM_SD1PID : DIEPCTL1_SODDFRM_SD1PID_Field := 16#0#; + -- EPDIS + EPDIS : DIEPCTL1_EPDIS_Field := 16#0#; + -- EPENA + EPENA : DIEPCTL1_EPENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GNPTXFSIZ_Host_Register use record - NPTXFSA at 0 range 0 .. 15; - NPTXFD at 0 range 16 .. 31; + for DIEPCTL1_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM_SD1PID at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - -------------------------- - -- FS_GNPTXSTS_Register -- - -------------------------- + subtype DIEPTSIZ_XFRSIZ_Field is STM32F429x.UInt19; + subtype DIEPTSIZ_PKTCNT_Field is STM32F429x.UInt10; + subtype DIEPTSIZ_MCNT_Field is STM32F429x.UInt2; - subtype FS_GNPTXSTS_NPTXFSAV_Field is STM32F429x.Short; - subtype FS_GNPTXSTS_NPTQXSAV_Field is STM32F429x.Byte; - subtype FS_GNPTXSTS_NPTXQTOP_Field is STM32F429x.UInt7; - - -- OTG_FS non-periodic transmit FIFO/queue status register - -- (OTG_FS_GNPTXSTS) - type FS_GNPTXSTS_Register is record - -- Non-periodic TxFIFO space available - NPTXFSAV : FS_GNPTXSTS_NPTXFSAV_Field; - -- Non-periodic transmit request queue space available - NPTQXSAV : FS_GNPTXSTS_NPTQXSAV_Field; - -- Top of the non-periodic transmit request queue - NPTXQTOP : FS_GNPTXSTS_NPTXQTOP_Field; + -- device endpoint-1 transfer size register + type DIEPTSIZ_Register is record + -- Transfer size + XFRSIZ : DIEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : DIEPTSIZ_PKTCNT_Field := 16#0#; + -- Multi count + MCNT : DIEPTSIZ_MCNT_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F429x.Bit; + Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_GNPTXSTS_Register use record - NPTXFSAV at 0 range 0 .. 15; - NPTQXSAV at 0 range 16 .. 23; - NPTXQTOP at 0 range 24 .. 30; + for DIEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + MCNT at 0 range 29 .. 30; Reserved_31_31 at 0 range 31 .. 31; end record; - ----------------------- - -- FS_GCCFG_Register -- - ----------------------- - - subtype FS_GCCFG_PWRDWN_Field is STM32F429x.Bit; - subtype FS_GCCFG_VBUSASEN_Field is STM32F429x.Bit; - subtype FS_GCCFG_VBUSBSEN_Field is STM32F429x.Bit; - subtype FS_GCCFG_SOFOUTEN_Field is STM32F429x.Bit; - - -- OTG_FS general core configuration register (OTG_FS_GCCFG) - type FS_GCCFG_Register is record - -- unspecified - Reserved_0_15 : STM32F429x.Short := 16#0#; - -- Power down - PWRDWN : FS_GCCFG_PWRDWN_Field := 16#0#; + subtype DIEPCTL_MPSIZ_Field is STM32F429x.UInt11; + subtype DIEPCTL_USBAEP_Field is STM32F429x.Bit; + subtype DIEPCTL_EONUM_DPID_Field is STM32F429x.Bit; + subtype DIEPCTL_NAKSTS_Field is STM32F429x.Bit; + subtype DIEPCTL_EPTYP_Field is STM32F429x.UInt2; + subtype DIEPCTL_Stall_Field is STM32F429x.Bit; + subtype DIEPCTL_TXFNUM_Field is STM32F429x.UInt4; + subtype DIEPCTL_CNAK_Field is STM32F429x.Bit; + subtype DIEPCTL_SNAK_Field is STM32F429x.Bit; + subtype DIEPCTL_SD0PID_SEVNFRM_Field is STM32F429x.Bit; + subtype DIEPCTL_SODDFRM_Field is STM32F429x.Bit; + subtype DIEPCTL_EPDIS_Field is STM32F429x.Bit; + subtype DIEPCTL_EPENA_Field is STM32F429x.Bit; + + -- OTG device endpoint-2 control register + type DIEPCTL_Register is record + -- MPSIZ + MPSIZ : DIEPCTL_MPSIZ_Field := 16#0#; -- unspecified - Reserved_17_17 : STM32F429x.Bit := 16#0#; - -- Enable the VBUS sensing device - VBUSASEN : FS_GCCFG_VBUSASEN_Field := 16#0#; - -- Enable the VBUS sensing device - VBUSBSEN : FS_GCCFG_VBUSBSEN_Field := 16#0#; - -- SOF output enable - SOFOUTEN : FS_GCCFG_SOFOUTEN_Field := 16#0#; + Reserved_11_14 : STM32F429x.UInt4 := 16#0#; + -- USBAEP + USBAEP : DIEPCTL_USBAEP_Field := 16#0#; + -- Read-only. EONUM/DPID + EONUM_DPID : DIEPCTL_EONUM_DPID_Field := 16#0#; + -- Read-only. NAKSTS + NAKSTS : DIEPCTL_NAKSTS_Field := 16#0#; + -- EPTYP + EPTYP : DIEPCTL_EPTYP_Field := 16#0#; -- unspecified - Reserved_21_31 : STM32F429x.UInt11 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for FS_GCCFG_Register use record - Reserved_0_15 at 0 range 0 .. 15; - PWRDWN at 0 range 16 .. 16; - Reserved_17_17 at 0 range 17 .. 17; - VBUSASEN at 0 range 18 .. 18; - VBUSBSEN at 0 range 19 .. 19; - SOFOUTEN at 0 range 20 .. 20; - Reserved_21_31 at 0 range 21 .. 31; - end record; - - -------------------------- - -- FS_HPTXFSIZ_Register -- - -------------------------- - - subtype FS_HPTXFSIZ_PTXSA_Field is STM32F429x.Short; - subtype FS_HPTXFSIZ_PTXFSIZ_Field is STM32F429x.Short; - - -- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) - type FS_HPTXFSIZ_Register is record - -- Host periodic TxFIFO start address - PTXSA : FS_HPTXFSIZ_PTXSA_Field := 16#600#; - -- Host periodic TxFIFO depth - PTXFSIZ : FS_HPTXFSIZ_PTXFSIZ_Field := 16#200#; + Reserved_20_20 : STM32F429x.Bit := 16#0#; + -- Stall + Stall : DIEPCTL_Stall_Field := 16#0#; + -- TXFNUM + TXFNUM : DIEPCTL_TXFNUM_Field := 16#0#; + -- Write-only. CNAK + CNAK : DIEPCTL_CNAK_Field := 16#0#; + -- Write-only. SNAK + SNAK : DIEPCTL_SNAK_Field := 16#0#; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : DIEPCTL_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. SODDFRM + SODDFRM : DIEPCTL_SODDFRM_Field := 16#0#; + -- EPDIS + EPDIS : DIEPCTL_EPDIS_Field := 16#0#; + -- EPENA + EPENA : DIEPCTL_EPENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HPTXFSIZ_Register use record - PTXSA at 0 range 0 .. 15; - PTXFSIZ at 0 range 16 .. 31; + for DIEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - ------------------------- - -- FS_DIEPTXF_Register -- - ------------------------- - - subtype FS_DIEPTXF1_INEPTXSA_Field is STM32F429x.Short; - subtype FS_DIEPTXF1_INEPTXFD_Field is STM32F429x.Short; + subtype DOEPCTL0_MPSIZ_Field is STM32F429x.UInt2; + subtype DOEPCTL0_USBAEP_Field is STM32F429x.Bit; + subtype DOEPCTL0_NAKSTS_Field is STM32F429x.Bit; + subtype DOEPCTL0_EPTYP_Field is STM32F429x.UInt2; + subtype DOEPCTL0_SNPM_Field is STM32F429x.Bit; + subtype DOEPCTL0_Stall_Field is STM32F429x.Bit; + subtype DOEPCTL0_CNAK_Field is STM32F429x.Bit; + subtype DOEPCTL0_SNAK_Field is STM32F429x.Bit; + subtype DOEPCTL0_EPDIS_Field is STM32F429x.Bit; + subtype DOEPCTL0_EPENA_Field is STM32F429x.Bit; - -- OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) - type FS_DIEPTXF_Register is record - -- IN endpoint FIFO2 transmit RAM start address - INEPTXSA : FS_DIEPTXF1_INEPTXSA_Field := 16#400#; - -- IN endpoint TxFIFO depth - INEPTXFD : FS_DIEPTXF1_INEPTXFD_Field := 16#200#; + -- device endpoint-0 control register + type DOEPCTL0_Register is record + -- Read-only. MPSIZ + MPSIZ : DOEPCTL0_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_2_14 : STM32F429x.UInt13 := 16#0#; + -- Read-only. USBAEP + USBAEP : DOEPCTL0_USBAEP_Field := 16#1#; + -- unspecified + Reserved_16_16 : STM32F429x.Bit := 16#0#; + -- Read-only. NAKSTS + NAKSTS : DOEPCTL0_NAKSTS_Field := 16#0#; + -- Read-only. EPTYP + EPTYP : DOEPCTL0_EPTYP_Field := 16#0#; + -- SNPM + SNPM : DOEPCTL0_SNPM_Field := 16#0#; + -- Stall + Stall : DOEPCTL0_Stall_Field := 16#0#; + -- unspecified + Reserved_22_25 : STM32F429x.UInt4 := 16#0#; + -- Write-only. CNAK + CNAK : DOEPCTL0_CNAK_Field := 16#0#; + -- Write-only. SNAK + SNAK : DOEPCTL0_SNAK_Field := 16#0#; + -- unspecified + Reserved_28_29 : STM32F429x.UInt2 := 16#0#; + -- Read-only. EPDIS + EPDIS : DOEPCTL0_EPDIS_Field := 16#0#; + -- Write-only. EPENA + EPENA : DOEPCTL0_EPENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DIEPTXF_Register use record - INEPTXSA at 0 range 0 .. 15; - INEPTXFD at 0 range 16 .. 31; + for DOEPCTL0_Register use record + MPSIZ at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + USBAEP at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - ---------------------- - -- FS_HCFG_Register -- - ---------------------- - - subtype FS_HCFG_FSLSPCS_Field is STM32F429x.UInt2; - subtype FS_HCFG_FSLSS_Field is STM32F429x.Bit; + subtype DOEPINT_XFRC_Field is STM32F429x.Bit; + subtype DOEPINT_EPDISD_Field is STM32F429x.Bit; + subtype DOEPINT_STUP_Field is STM32F429x.Bit; + subtype DOEPINT_OTEPDIS_Field is STM32F429x.Bit; + subtype DOEPINT_B2BSTUP_Field is STM32F429x.Bit; - -- OTG_FS host configuration register (OTG_FS_HCFG) - type FS_HCFG_Register is record - -- FS/LS PHY clock select - FSLSPCS : FS_HCFG_FSLSPCS_Field := 16#0#; - -- FS- and LS-only support - FSLSS : FS_HCFG_FSLSS_Field := 16#0#; + -- device endpoint-0 interrupt register + type DOEPINT_Register is record + -- XFRC + XFRC : DOEPINT_XFRC_Field := 16#0#; + -- EPDISD + EPDISD : DOEPINT_EPDISD_Field := 16#0#; -- unspecified - Reserved_3_31 : STM32F429x.UInt29 := 16#0#; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- STUP + STUP : DOEPINT_STUP_Field := 16#0#; + -- OTEPDIS + OTEPDIS : DOEPINT_OTEPDIS_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- B2BSTUP + B2BSTUP : DOEPINT_B2BSTUP_Field := 16#0#; + -- unspecified + Reserved_7_31 : STM32F429x.UInt25 := 16#1#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HCFG_Register use record - FSLSPCS at 0 range 0 .. 1; - FSLSS at 0 range 2 .. 2; - Reserved_3_31 at 0 range 3 .. 31; + for DOEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUP at 0 range 3 .. 3; + OTEPDIS at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + B2BSTUP at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; end record; - ------------------- - -- HFIR_Register -- - ------------------- - - subtype HFIR_FRIVL_Field is STM32F429x.Short; + subtype DOEPTSIZ0_XFRSIZ_Field is STM32F429x.UInt7; + subtype DOEPTSIZ0_PKTCNT_Field is STM32F429x.Bit; + subtype DOEPTSIZ0_STUPCNT_Field is STM32F429x.UInt2; - -- OTG_FS Host frame interval register - type HFIR_Register is record - -- Frame interval - FRIVL : HFIR_FRIVL_Field := 16#EA60#; + -- device OUT endpoint-0 transfer size register + type DOEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : DOEPTSIZ0_XFRSIZ_Field := 16#0#; + -- unspecified + Reserved_7_18 : STM32F429x.UInt12 := 16#0#; + -- Packet count + PKTCNT : DOEPTSIZ0_PKTCNT_Field := 16#0#; + -- unspecified + Reserved_20_28 : STM32F429x.UInt9 := 16#0#; + -- SETUP packet count + STUPCNT : DOEPTSIZ0_STUPCNT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HFIR_Register use record - FRIVL at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for DOEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 19; + Reserved_20_28 at 0 range 20 .. 28; + STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - ----------------------- - -- FS_HFNUM_Register -- - ----------------------- + subtype DOEPCTL_MPSIZ_Field is STM32F429x.UInt11; + subtype DOEPCTL_USBAEP_Field is STM32F429x.Bit; + subtype DOEPCTL_EONUM_DPID_Field is STM32F429x.Bit; + subtype DOEPCTL_NAKSTS_Field is STM32F429x.Bit; + subtype DOEPCTL_EPTYP_Field is STM32F429x.UInt2; + subtype DOEPCTL_SNPM_Field is STM32F429x.Bit; + subtype DOEPCTL_Stall_Field is STM32F429x.Bit; + subtype DOEPCTL_CNAK_Field is STM32F429x.Bit; + subtype DOEPCTL_SNAK_Field is STM32F429x.Bit; + subtype DOEPCTL_SD0PID_SEVNFRM_Field is STM32F429x.Bit; + subtype DOEPCTL_SODDFRM_Field is STM32F429x.Bit; + subtype DOEPCTL_EPDIS_Field is STM32F429x.Bit; + subtype DOEPCTL_EPENA_Field is STM32F429x.Bit; - subtype FS_HFNUM_FRNUM_Field is STM32F429x.Short; - subtype FS_HFNUM_FTREM_Field is STM32F429x.Short; - - -- OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) - type FS_HFNUM_Register is record - -- Frame number - FRNUM : FS_HFNUM_FRNUM_Field; - -- Frame time remaining - FTREM : FS_HFNUM_FTREM_Field; + -- device endpoint-1 control register + type DOEPCTL_Register is record + -- MPSIZ + MPSIZ : DOEPCTL_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : STM32F429x.UInt4 := 16#0#; + -- USBAEP + USBAEP : DOEPCTL_USBAEP_Field := 16#0#; + -- Read-only. EONUM/DPID + EONUM_DPID : DOEPCTL_EONUM_DPID_Field := 16#0#; + -- Read-only. NAKSTS + NAKSTS : DOEPCTL_NAKSTS_Field := 16#0#; + -- EPTYP + EPTYP : DOEPCTL_EPTYP_Field := 16#0#; + -- SNPM + SNPM : DOEPCTL_SNPM_Field := 16#0#; + -- Stall + Stall : DOEPCTL_Stall_Field := 16#0#; + -- unspecified + Reserved_22_25 : STM32F429x.UInt4 := 16#0#; + -- Write-only. CNAK + CNAK : DOEPCTL_CNAK_Field := 16#0#; + -- Write-only. SNAK + SNAK : DOEPCTL_SNAK_Field := 16#0#; + -- Write-only. SD0PID/SEVNFRM + SD0PID_SEVNFRM : DOEPCTL_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. SODDFRM + SODDFRM : DOEPCTL_SODDFRM_Field := 16#0#; + -- EPDIS + EPDIS : DOEPCTL_EPDIS_Field := 16#0#; + -- EPENA + EPENA : DOEPCTL_EPENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HFNUM_Register use record - FRNUM at 0 range 0 .. 15; - FTREM at 0 range 16 .. 31; + for DOEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - ------------------------- - -- FS_HPTXSTS_Register -- - ------------------------- - - subtype FS_HPTXSTS_PTXFSAVL_Field is STM32F429x.Short; - subtype FS_HPTXSTS_PTXQSAV_Field is STM32F429x.Byte; - subtype FS_HPTXSTS_PTXQTOP_Field is STM32F429x.Byte; + subtype DOEPTSIZ_XFRSIZ_Field is STM32F429x.UInt19; + subtype DOEPTSIZ_PKTCNT_Field is STM32F429x.UInt10; + subtype DOEPTSIZ_RXDPID_STUPCNT_Field is STM32F429x.UInt2; - -- OTG_FS_Host periodic transmit FIFO/queue status register - -- (OTG_FS_HPTXSTS) - type FS_HPTXSTS_Register is record - -- Periodic transmit data FIFO space available - PTXFSAVL : FS_HPTXSTS_PTXFSAVL_Field := 16#100#; - -- Periodic transmit request queue space available - PTXQSAV : FS_HPTXSTS_PTXQSAV_Field := 16#8#; - -- Top of the periodic transmit request queue - PTXQTOP : FS_HPTXSTS_PTXQTOP_Field := 16#0#; + -- device OUT endpoint-1 transfer size register + type DOEPTSIZ_Register is record + -- Transfer size + XFRSIZ : DOEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : DOEPTSIZ_PKTCNT_Field := 16#0#; + -- Received data PID/SETUP packet count + RXDPID_STUPCNT : DOEPTSIZ_RXDPID_STUPCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HPTXSTS_Register use record - PTXFSAVL at 0 range 0 .. 15; - PTXQSAV at 0 range 16 .. 23; - PTXQTOP at 0 range 24 .. 31; + for DOEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + RXDPID_STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - -------------------- - -- HAINT_Register -- - -------------------- - - subtype HAINT_HAINT_Field is STM32F429x.Short; + subtype FS_GOTGCTL_SRQSCS_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_SRQ_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_HNGSCS_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_HNPRQ_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_HSHNPEN_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_DHNPEN_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_CIDSTS_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_DBCT_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_ASVLD_Field is STM32F429x.Bit; + subtype FS_GOTGCTL_BSVLD_Field is STM32F429x.Bit; - -- OTG_FS Host all channels interrupt register - type HAINT_Register is record - -- Channel interrupts - HAINT : HAINT_HAINT_Field; + -- OTG_FS control and status register (OTG_FS_GOTGCTL) + type FS_GOTGCTL_Register is record + -- Read-only. Session request success + SRQSCS : FS_GOTGCTL_SRQSCS_Field := 16#0#; + -- Session request + SRQ : FS_GOTGCTL_SRQ_Field := 16#0#; + -- unspecified + Reserved_2_7 : STM32F429x.UInt6 := 16#0#; + -- Read-only. Host negotiation success + HNGSCS : FS_GOTGCTL_HNGSCS_Field := 16#0#; + -- HNP request + HNPRQ : FS_GOTGCTL_HNPRQ_Field := 16#0#; + -- Host set HNP enable + HSHNPEN : FS_GOTGCTL_HSHNPEN_Field := 16#0#; + -- Device HNP enabled + DHNPEN : FS_GOTGCTL_DHNPEN_Field := 16#1#; + -- unspecified + Reserved_12_15 : STM32F429x.UInt4 := 16#0#; + -- Read-only. Connector ID status + CIDSTS : FS_GOTGCTL_CIDSTS_Field := 16#0#; + -- Read-only. Long/short debounce time + DBCT : FS_GOTGCTL_DBCT_Field := 16#0#; + -- Read-only. A-session valid + ASVLD : FS_GOTGCTL_ASVLD_Field := 16#0#; + -- Read-only. B-session valid + BSVLD : FS_GOTGCTL_BSVLD_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_20_31 : STM32F429x.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HAINT_Register use record - HAINT at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_GOTGCTL_Register use record + SRQSCS at 0 range 0 .. 0; + SRQ at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + HNGSCS at 0 range 8 .. 8; + HNPRQ at 0 range 9 .. 9; + HSHNPEN at 0 range 10 .. 10; + DHNPEN at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + CIDSTS at 0 range 16 .. 16; + DBCT at 0 range 17 .. 17; + ASVLD at 0 range 18 .. 18; + BSVLD at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - ----------------------- - -- HAINTMSK_Register -- - ----------------------- - - subtype HAINTMSK_HAINTM_Field is STM32F429x.Short; + subtype FS_GOTGINT_SEDET_Field is STM32F429x.Bit; + subtype FS_GOTGINT_SRSSCHG_Field is STM32F429x.Bit; + subtype FS_GOTGINT_HNSSCHG_Field is STM32F429x.Bit; + subtype FS_GOTGINT_HNGDET_Field is STM32F429x.Bit; + subtype FS_GOTGINT_ADTOCHG_Field is STM32F429x.Bit; + subtype FS_GOTGINT_DBCDNE_Field is STM32F429x.Bit; - -- OTG_FS host all channels interrupt mask register - type HAINTMSK_Register is record - -- Channel interrupt mask - HAINTM : HAINTMSK_HAINTM_Field := 16#0#; + -- OTG_FS interrupt register (OTG_FS_GOTGINT) + type FS_GOTGINT_Register is record -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_0_1 : STM32F429x.UInt2 := 16#0#; + -- Session end detected + SEDET : FS_GOTGINT_SEDET_Field := 16#0#; + -- unspecified + Reserved_3_7 : STM32F429x.UInt5 := 16#0#; + -- Session request success status change + SRSSCHG : FS_GOTGINT_SRSSCHG_Field := 16#0#; + -- Host negotiation success status change + HNSSCHG : FS_GOTGINT_HNSSCHG_Field := 16#0#; + -- unspecified + Reserved_10_16 : STM32F429x.UInt7 := 16#0#; + -- Host negotiation detected + HNGDET : FS_GOTGINT_HNGDET_Field := 16#0#; + -- A-device timeout change + ADTOCHG : FS_GOTGINT_ADTOCHG_Field := 16#0#; + -- Debounce done + DBCDNE : FS_GOTGINT_DBCDNE_Field := 16#0#; + -- unspecified + Reserved_20_31 : STM32F429x.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for HAINTMSK_Register use record - HAINTM at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_GOTGINT_Register use record + Reserved_0_1 at 0 range 0 .. 1; + SEDET at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + SRSSCHG at 0 range 8 .. 8; + HNSSCHG at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + HNGDET at 0 range 17 .. 17; + ADTOCHG at 0 range 18 .. 18; + DBCDNE at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - ---------------------- - -- FS_HPRT_Register -- - ---------------------- - - subtype FS_HPRT_PCSTS_Field is STM32F429x.Bit; - subtype FS_HPRT_PCDET_Field is STM32F429x.Bit; - subtype FS_HPRT_PENA_Field is STM32F429x.Bit; - subtype FS_HPRT_PENCHNG_Field is STM32F429x.Bit; - subtype FS_HPRT_POCA_Field is STM32F429x.Bit; - subtype FS_HPRT_POCCHNG_Field is STM32F429x.Bit; - subtype FS_HPRT_PRES_Field is STM32F429x.Bit; - subtype FS_HPRT_PSUSP_Field is STM32F429x.Bit; - subtype FS_HPRT_PRST_Field is STM32F429x.Bit; - subtype FS_HPRT_PLSTS_Field is STM32F429x.UInt2; - subtype FS_HPRT_PPWR_Field is STM32F429x.Bit; - subtype FS_HPRT_PTCTL_Field is STM32F429x.UInt4; - subtype FS_HPRT_PSPD_Field is STM32F429x.UInt2; + subtype FS_GAHBCFG_GINT_Field is STM32F429x.Bit; + subtype FS_GAHBCFG_TXFELVL_Field is STM32F429x.Bit; + subtype FS_GAHBCFG_PTXFELVL_Field is STM32F429x.Bit; - -- OTG_FS host port control and status register (OTG_FS_HPRT) - type FS_HPRT_Register is record - -- Port connect status - PCSTS : FS_HPRT_PCSTS_Field := 16#0#; - -- Port connect detected - PCDET : FS_HPRT_PCDET_Field := 16#0#; - -- Port enable - PENA : FS_HPRT_PENA_Field := 16#0#; - -- Port enable/disable change - PENCHNG : FS_HPRT_PENCHNG_Field := 16#0#; - -- Port overcurrent active - POCA : FS_HPRT_POCA_Field := 16#0#; - -- Port overcurrent change - POCCHNG : FS_HPRT_POCCHNG_Field := 16#0#; - -- Port resume - PRES : FS_HPRT_PRES_Field := 16#0#; - -- Port suspend - PSUSP : FS_HPRT_PSUSP_Field := 16#0#; - -- Port reset - PRST : FS_HPRT_PRST_Field := 16#0#; + -- OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + type FS_GAHBCFG_Register is record + -- Global interrupt mask + GINT : FS_GAHBCFG_GINT_Field := 16#0#; -- unspecified - Reserved_9_9 : STM32F429x.Bit := 16#0#; - -- Port line status - PLSTS : FS_HPRT_PLSTS_Field := 16#0#; - -- Port power - PPWR : FS_HPRT_PPWR_Field := 16#0#; - -- Port test control - PTCTL : FS_HPRT_PTCTL_Field := 16#0#; - -- Port speed - PSPD : FS_HPRT_PSPD_Field := 16#0#; + Reserved_1_6 : STM32F429x.UInt6 := 16#0#; + -- TxFIFO empty level + TXFELVL : FS_GAHBCFG_TXFELVL_Field := 16#0#; + -- Periodic TxFIFO empty level + PTXFELVL : FS_GAHBCFG_PTXFELVL_Field := 16#0#; -- unspecified - Reserved_19_31 : STM32F429x.UInt13 := 16#0#; + Reserved_9_31 : STM32F429x.UInt23 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HPRT_Register use record - PCSTS at 0 range 0 .. 0; - PCDET at 0 range 1 .. 1; - PENA at 0 range 2 .. 2; - PENCHNG at 0 range 3 .. 3; - POCA at 0 range 4 .. 4; - POCCHNG at 0 range 5 .. 5; - PRES at 0 range 6 .. 6; - PSUSP at 0 range 7 .. 7; - PRST at 0 range 8 .. 8; - Reserved_9_9 at 0 range 9 .. 9; - PLSTS at 0 range 10 .. 11; - PPWR at 0 range 12 .. 12; - PTCTL at 0 range 13 .. 16; - PSPD at 0 range 17 .. 18; - Reserved_19_31 at 0 range 19 .. 31; + for FS_GAHBCFG_Register use record + GINT at 0 range 0 .. 0; + Reserved_1_6 at 0 range 1 .. 6; + TXFELVL at 0 range 7 .. 7; + PTXFELVL at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; end record; - ------------------------ - -- FS_HCCHAR_Register -- - ------------------------ - - subtype FS_HCCHAR0_MPSIZ_Field is STM32F429x.UInt11; - subtype FS_HCCHAR0_EPNUM_Field is STM32F429x.UInt4; - subtype FS_HCCHAR0_EPDIR_Field is STM32F429x.Bit; - subtype FS_HCCHAR0_LSDEV_Field is STM32F429x.Bit; - subtype FS_HCCHAR0_EPTYP_Field is STM32F429x.UInt2; - subtype FS_HCCHAR0_MCNT_Field is STM32F429x.UInt2; - subtype FS_HCCHAR0_DAD_Field is STM32F429x.UInt7; - subtype FS_HCCHAR0_ODDFRM_Field is STM32F429x.Bit; - subtype FS_HCCHAR0_CHDIS_Field is STM32F429x.Bit; - subtype FS_HCCHAR0_CHENA_Field is STM32F429x.Bit; + subtype FS_GUSBCFG_TOCAL_Field is STM32F429x.UInt3; + subtype FS_GUSBCFG_PHYSEL_Field is STM32F429x.Bit; + subtype FS_GUSBCFG_SRPCAP_Field is STM32F429x.Bit; + subtype FS_GUSBCFG_HNPCAP_Field is STM32F429x.Bit; + subtype FS_GUSBCFG_TRDT_Field is STM32F429x.UInt4; + subtype FS_GUSBCFG_FHMOD_Field is STM32F429x.Bit; + subtype FS_GUSBCFG_FDMOD_Field is STM32F429x.Bit; + subtype FS_GUSBCFG_CTXPKT_Field is STM32F429x.Bit; - -- OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) - type FS_HCCHAR_Register is record - -- Maximum packet size - MPSIZ : FS_HCCHAR0_MPSIZ_Field := 16#0#; - -- Endpoint number - EPNUM : FS_HCCHAR0_EPNUM_Field := 16#0#; - -- Endpoint direction - EPDIR : FS_HCCHAR0_EPDIR_Field := 16#0#; + -- OTG_FS USB configuration register (OTG_FS_GUSBCFG) + type FS_GUSBCFG_Register is record + -- FS timeout calibration + TOCAL : FS_GUSBCFG_TOCAL_Field := 16#0#; -- unspecified - Reserved_16_16 : STM32F429x.Bit := 16#0#; - -- Low-speed device - LSDEV : FS_HCCHAR0_LSDEV_Field := 16#0#; - -- Endpoint type - EPTYP : FS_HCCHAR0_EPTYP_Field := 16#0#; - -- Multicount - MCNT : FS_HCCHAR0_MCNT_Field := 16#0#; - -- Device address - DAD : FS_HCCHAR0_DAD_Field := 16#0#; - -- Odd frame - ODDFRM : FS_HCCHAR0_ODDFRM_Field := 16#0#; - -- Channel disable - CHDIS : FS_HCCHAR0_CHDIS_Field := 16#0#; - -- Channel enable - CHENA : FS_HCCHAR0_CHENA_Field := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for FS_HCCHAR_Register use record - MPSIZ at 0 range 0 .. 10; - EPNUM at 0 range 11 .. 14; - EPDIR at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - LSDEV at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - MCNT at 0 range 20 .. 21; - DAD at 0 range 22 .. 28; - ODDFRM at 0 range 29 .. 29; - CHDIS at 0 range 30 .. 30; - CHENA at 0 range 31 .. 31; - end record; - - ----------------------- - -- FS_HCINT_Register -- - ----------------------- - - subtype FS_HCINT0_XFRC_Field is STM32F429x.Bit; - subtype FS_HCINT0_CHH_Field is STM32F429x.Bit; - subtype FS_HCINT0_STALL_Field is STM32F429x.Bit; - subtype FS_HCINT0_NAK_Field is STM32F429x.Bit; - subtype FS_HCINT0_ACK_Field is STM32F429x.Bit; - subtype FS_HCINT0_TXERR_Field is STM32F429x.Bit; - subtype FS_HCINT0_BBERR_Field is STM32F429x.Bit; - subtype FS_HCINT0_FRMOR_Field is STM32F429x.Bit; - subtype FS_HCINT0_DTERR_Field is STM32F429x.Bit; - - -- OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) - type FS_HCINT_Register is record - -- Transfer completed - XFRC : FS_HCINT0_XFRC_Field := 16#0#; - -- Channel halted - CHH : FS_HCINT0_CHH_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- STALL response received interrupt - STALL : FS_HCINT0_STALL_Field := 16#0#; - -- NAK response received interrupt - NAK : FS_HCINT0_NAK_Field := 16#0#; - -- ACK response received/transmitted interrupt - ACK : FS_HCINT0_ACK_Field := 16#0#; + Reserved_3_5 : STM32F429x.UInt3 := 16#0#; + -- Write-only. Full Speed serial transceiver select + PHYSEL : FS_GUSBCFG_PHYSEL_Field := 16#0#; -- unspecified - Reserved_6_6 : STM32F429x.Bit := 16#0#; - -- Transaction error - TXERR : FS_HCINT0_TXERR_Field := 16#0#; - -- Babble error - BBERR : FS_HCINT0_BBERR_Field := 16#0#; - -- Frame overrun - FRMOR : FS_HCINT0_FRMOR_Field := 16#0#; - -- Data toggle error - DTERR : FS_HCINT0_DTERR_Field := 16#0#; + Reserved_7_7 : STM32F429x.Bit := 16#0#; + -- SRP-capable + SRPCAP : FS_GUSBCFG_SRPCAP_Field := 16#0#; + -- HNP-capable + HNPCAP : FS_GUSBCFG_HNPCAP_Field := 16#1#; + -- USB turnaround time + TRDT : FS_GUSBCFG_TRDT_Field := 16#2#; -- unspecified - Reserved_11_31 : STM32F429x.UInt21 := 16#0#; + Reserved_14_28 : STM32F429x.UInt15 := 16#0#; + -- Force host mode + FHMOD : FS_GUSBCFG_FHMOD_Field := 16#0#; + -- Force device mode + FDMOD : FS_GUSBCFG_FDMOD_Field := 16#0#; + -- Corrupt Tx packet + CTXPKT : FS_GUSBCFG_CTXPKT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HCINT_Register use record - XFRC at 0 range 0 .. 0; - CHH at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STALL at 0 range 3 .. 3; - NAK at 0 range 4 .. 4; - ACK at 0 range 5 .. 5; - Reserved_6_6 at 0 range 6 .. 6; - TXERR at 0 range 7 .. 7; - BBERR at 0 range 8 .. 8; - FRMOR at 0 range 9 .. 9; - DTERR at 0 range 10 .. 10; - Reserved_11_31 at 0 range 11 .. 31; + for FS_GUSBCFG_Register use record + TOCAL at 0 range 0 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + PHYSEL at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + SRPCAP at 0 range 8 .. 8; + HNPCAP at 0 range 9 .. 9; + TRDT at 0 range 10 .. 13; + Reserved_14_28 at 0 range 14 .. 28; + FHMOD at 0 range 29 .. 29; + FDMOD at 0 range 30 .. 30; + CTXPKT at 0 range 31 .. 31; end record; - -------------------------- - -- FS_HCINTMSK_Register -- - -------------------------- - - subtype FS_HCINTMSK0_XFRCM_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_CHHM_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_STALLM_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_NAKM_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_ACKM_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_NYET_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_TXERRM_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_BBERRM_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_FRMORM_Field is STM32F429x.Bit; - subtype FS_HCINTMSK0_DTERRM_Field is STM32F429x.Bit; + subtype FS_GRSTCTL_CSRST_Field is STM32F429x.Bit; + subtype FS_GRSTCTL_HSRST_Field is STM32F429x.Bit; + subtype FS_GRSTCTL_FCRST_Field is STM32F429x.Bit; + subtype FS_GRSTCTL_RXFFLSH_Field is STM32F429x.Bit; + subtype FS_GRSTCTL_TXFFLSH_Field is STM32F429x.Bit; + subtype FS_GRSTCTL_TXFNUM_Field is STM32F429x.UInt5; + subtype FS_GRSTCTL_AHBIDL_Field is STM32F429x.Bit; - -- OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) - type FS_HCINTMSK_Register is record - -- Transfer completed mask - XFRCM : FS_HCINTMSK0_XFRCM_Field := 16#0#; - -- Channel halted mask - CHHM : FS_HCINTMSK0_CHHM_Field := 16#0#; + -- OTG_FS reset register (OTG_FS_GRSTCTL) + type FS_GRSTCTL_Register is record + -- Core soft reset + CSRST : FS_GRSTCTL_CSRST_Field := 16#0#; + -- HCLK soft reset + HSRST : FS_GRSTCTL_HSRST_Field := 16#0#; + -- Host frame counter reset + FCRST : FS_GRSTCTL_FCRST_Field := 16#0#; -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- STALL response received interrupt mask - STALLM : FS_HCINTMSK0_STALLM_Field := 16#0#; - -- NAK response received interrupt mask - NAKM : FS_HCINTMSK0_NAKM_Field := 16#0#; - -- ACK response received/transmitted interrupt mask - ACKM : FS_HCINTMSK0_ACKM_Field := 16#0#; - -- response received interrupt mask - NYET : FS_HCINTMSK0_NYET_Field := 16#0#; - -- Transaction error mask - TXERRM : FS_HCINTMSK0_TXERRM_Field := 16#0#; - -- Babble error mask - BBERRM : FS_HCINTMSK0_BBERRM_Field := 16#0#; - -- Frame overrun mask - FRMORM : FS_HCINTMSK0_FRMORM_Field := 16#0#; - -- Data toggle error mask - DTERRM : FS_HCINTMSK0_DTERRM_Field := 16#0#; + Reserved_3_3 : STM32F429x.Bit := 16#0#; + -- RxFIFO flush + RXFFLSH : FS_GRSTCTL_RXFFLSH_Field := 16#0#; + -- TxFIFO flush + TXFFLSH : FS_GRSTCTL_TXFFLSH_Field := 16#0#; + -- TxFIFO number + TXFNUM : FS_GRSTCTL_TXFNUM_Field := 16#0#; -- unspecified - Reserved_11_31 : STM32F429x.UInt21 := 16#0#; + Reserved_11_30 : STM32F429x.UInt20 := 16#40000#; + -- Read-only. AHB master idle + AHBIDL : FS_GRSTCTL_AHBIDL_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_HCINTMSK_Register use record - XFRCM at 0 range 0 .. 0; - CHHM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STALLM at 0 range 3 .. 3; - NAKM at 0 range 4 .. 4; - ACKM at 0 range 5 .. 5; - NYET at 0 range 6 .. 6; - TXERRM at 0 range 7 .. 7; - BBERRM at 0 range 8 .. 8; - FRMORM at 0 range 9 .. 9; - DTERRM at 0 range 10 .. 10; - Reserved_11_31 at 0 range 11 .. 31; + for FS_GRSTCTL_Register use record + CSRST at 0 range 0 .. 0; + HSRST at 0 range 1 .. 1; + FCRST at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + RXFFLSH at 0 range 4 .. 4; + TXFFLSH at 0 range 5 .. 5; + TXFNUM at 0 range 6 .. 10; + Reserved_11_30 at 0 range 11 .. 30; + AHBIDL at 0 range 31 .. 31; end record; - ------------------------ - -- FS_HCTSIZ_Register -- - ------------------------ - - subtype FS_HCTSIZ0_XFRSIZ_Field is STM32F429x.UInt19; - subtype FS_HCTSIZ0_PKTCNT_Field is STM32F429x.UInt10; - subtype FS_HCTSIZ0_DPID_Field is STM32F429x.UInt2; + subtype FS_GINTSTS_CMOD_Field is STM32F429x.Bit; + subtype FS_GINTSTS_MMIS_Field is STM32F429x.Bit; + subtype FS_GINTSTS_OTGINT_Field is STM32F429x.Bit; + subtype FS_GINTSTS_SOF_Field is STM32F429x.Bit; + subtype FS_GINTSTS_RXFLVL_Field is STM32F429x.Bit; + subtype FS_GINTSTS_NPTXFE_Field is STM32F429x.Bit; + subtype FS_GINTSTS_GINAKEFF_Field is STM32F429x.Bit; + subtype FS_GINTSTS_GOUTNAKEFF_Field is STM32F429x.Bit; + subtype FS_GINTSTS_ESUSP_Field is STM32F429x.Bit; + subtype FS_GINTSTS_USBSUSP_Field is STM32F429x.Bit; + subtype FS_GINTSTS_USBRST_Field is STM32F429x.Bit; + subtype FS_GINTSTS_ENUMDNE_Field is STM32F429x.Bit; + subtype FS_GINTSTS_ISOODRP_Field is STM32F429x.Bit; + subtype FS_GINTSTS_EOPF_Field is STM32F429x.Bit; + subtype FS_GINTSTS_IEPINT_Field is STM32F429x.Bit; + subtype FS_GINTSTS_OEPINT_Field is STM32F429x.Bit; + subtype FS_GINTSTS_IISOIXFR_Field is STM32F429x.Bit; + subtype FS_GINTSTS_IPXFR_INCOMPISOOUT_Field is STM32F429x.Bit; + subtype FS_GINTSTS_HPRTINT_Field is STM32F429x.Bit; + subtype FS_GINTSTS_HCINT_Field is STM32F429x.Bit; + subtype FS_GINTSTS_PTXFE_Field is STM32F429x.Bit; + subtype FS_GINTSTS_CIDSCHG_Field is STM32F429x.Bit; + subtype FS_GINTSTS_DISCINT_Field is STM32F429x.Bit; + subtype FS_GINTSTS_SRQINT_Field is STM32F429x.Bit; + subtype FS_GINTSTS_WKUPINT_Field is STM32F429x.Bit; - -- OTG_FS host channel-0 transfer size register - type FS_HCTSIZ_Register is record - -- Transfer size - XFRSIZ : FS_HCTSIZ0_XFRSIZ_Field := 16#0#; - -- Packet count - PKTCNT : FS_HCTSIZ0_PKTCNT_Field := 16#0#; - -- Data PID - DPID : FS_HCTSIZ0_DPID_Field := 16#0#; + -- OTG_FS core interrupt register (OTG_FS_GINTSTS) + type FS_GINTSTS_Register is record + -- Read-only. Current mode of operation + CMOD : FS_GINTSTS_CMOD_Field := 16#0#; + -- Mode mismatch interrupt + MMIS : FS_GINTSTS_MMIS_Field := 16#0#; + -- Read-only. OTG interrupt + OTGINT : FS_GINTSTS_OTGINT_Field := 16#0#; + -- Start of frame + SOF : FS_GINTSTS_SOF_Field := 16#0#; + -- Read-only. RxFIFO non-empty + RXFLVL : FS_GINTSTS_RXFLVL_Field := 16#0#; + -- Read-only. Non-periodic TxFIFO empty + NPTXFE : FS_GINTSTS_NPTXFE_Field := 16#1#; + -- Read-only. Global IN non-periodic NAK effective + GINAKEFF : FS_GINTSTS_GINAKEFF_Field := 16#0#; + -- Read-only. Global OUT NAK effective + GOUTNAKEFF : FS_GINTSTS_GOUTNAKEFF_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F429x.Bit := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for FS_HCTSIZ_Register use record - XFRSIZ at 0 range 0 .. 18; - PKTCNT at 0 range 19 .. 28; - DPID at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; - end record; - - ---------------------- - -- FS_DCFG_Register -- - ---------------------- - - subtype FS_DCFG_DSPD_Field is STM32F429x.UInt2; - subtype FS_DCFG_NZLSOHSK_Field is STM32F429x.Bit; - subtype FS_DCFG_DAD_Field is STM32F429x.UInt7; - subtype FS_DCFG_PFIVL_Field is STM32F429x.UInt2; - - -- OTG_FS device configuration register (OTG_FS_DCFG) - type FS_DCFG_Register is record - -- Device speed - DSPD : FS_DCFG_DSPD_Field := 16#0#; - -- Non-zero-length status OUT handshake - NZLSOHSK : FS_DCFG_NZLSOHSK_Field := 16#0#; + Reserved_8_9 : STM32F429x.UInt2 := 16#0#; + -- Early suspend + ESUSP : FS_GINTSTS_ESUSP_Field := 16#0#; + -- USB suspend + USBSUSP : FS_GINTSTS_USBSUSP_Field := 16#0#; + -- USB reset + USBRST : FS_GINTSTS_USBRST_Field := 16#0#; + -- Enumeration done + ENUMDNE : FS_GINTSTS_ENUMDNE_Field := 16#0#; + -- Isochronous OUT packet dropped interrupt + ISOODRP : FS_GINTSTS_ISOODRP_Field := 16#0#; + -- End of periodic frame interrupt + EOPF : FS_GINTSTS_EOPF_Field := 16#0#; -- unspecified - Reserved_3_3 : STM32F429x.Bit := 16#0#; - -- Device address - DAD : FS_DCFG_DAD_Field := 16#0#; - -- Periodic frame interval - PFIVL : FS_DCFG_PFIVL_Field := 16#0#; + Reserved_16_17 : STM32F429x.UInt2 := 16#0#; + -- Read-only. IN endpoint interrupt + IEPINT : FS_GINTSTS_IEPINT_Field := 16#0#; + -- Read-only. OUT endpoint interrupt + OEPINT : FS_GINTSTS_OEPINT_Field := 16#0#; + -- Incomplete isochronous IN transfer + IISOIXFR : FS_GINTSTS_IISOIXFR_Field := 16#0#; + -- Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT + -- transfer(Device mode) + IPXFR_INCOMPISOOUT : FS_GINTSTS_IPXFR_INCOMPISOOUT_Field := 16#0#; -- unspecified - Reserved_13_31 : STM32F429x.UInt19 := 16#1100#; + Reserved_22_23 : STM32F429x.UInt2 := 16#0#; + -- Read-only. Host port interrupt + HPRTINT : FS_GINTSTS_HPRTINT_Field := 16#0#; + -- Read-only. Host channels interrupt + HCINT : FS_GINTSTS_HCINT_Field := 16#0#; + -- Read-only. Periodic TxFIFO empty + PTXFE : FS_GINTSTS_PTXFE_Field := 16#1#; + -- unspecified + Reserved_27_27 : STM32F429x.Bit := 16#0#; + -- Connector ID status change + CIDSCHG : FS_GINTSTS_CIDSCHG_Field := 16#0#; + -- Disconnect detected interrupt + DISCINT : FS_GINTSTS_DISCINT_Field := 16#0#; + -- Session request/new session detected interrupt + SRQINT : FS_GINTSTS_SRQINT_Field := 16#0#; + -- Resume/remote wakeup detected interrupt + WKUPINT : FS_GINTSTS_WKUPINT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for FS_DCFG_Register use record - DSPD at 0 range 0 .. 1; - NZLSOHSK at 0 range 2 .. 2; - Reserved_3_3 at 0 range 3 .. 3; - DAD at 0 range 4 .. 10; - PFIVL at 0 range 11 .. 12; - Reserved_13_31 at 0 range 13 .. 31; - end record; - - ---------------------- - -- FS_DCTL_Register -- - ---------------------- + with Object_Size => 32, Bit_Order => System.Low_Order_First; - subtype FS_DCTL_RWUSIG_Field is STM32F429x.Bit; - subtype FS_DCTL_SDIS_Field is STM32F429x.Bit; - subtype FS_DCTL_GINSTS_Field is STM32F429x.Bit; - subtype FS_DCTL_GONSTS_Field is STM32F429x.Bit; - subtype FS_DCTL_TCTL_Field is STM32F429x.UInt3; - subtype FS_DCTL_SGINAK_Field is STM32F429x.Bit; - subtype FS_DCTL_CGINAK_Field is STM32F429x.Bit; - subtype FS_DCTL_SGONAK_Field is STM32F429x.Bit; - subtype FS_DCTL_CGONAK_Field is STM32F429x.Bit; - subtype FS_DCTL_POPRGDNE_Field is STM32F429x.Bit; + for FS_GINTSTS_Register use record + CMOD at 0 range 0 .. 0; + MMIS at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOF at 0 range 3 .. 3; + RXFLVL at 0 range 4 .. 4; + NPTXFE at 0 range 5 .. 5; + GINAKEFF at 0 range 6 .. 6; + GOUTNAKEFF at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSP at 0 range 10 .. 10; + USBSUSP at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNE at 0 range 13 .. 13; + ISOODRP at 0 range 14 .. 14; + EOPF at 0 range 15 .. 15; + Reserved_16_17 at 0 range 16 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFR at 0 range 20 .. 20; + IPXFR_INCOMPISOOUT at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + HPRTINT at 0 range 24 .. 24; + HCINT at 0 range 25 .. 25; + PTXFE at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHG at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQINT at 0 range 30 .. 30; + WKUPINT at 0 range 31 .. 31; + end record; - -- OTG_FS device control register (OTG_FS_DCTL) - type FS_DCTL_Register is record - -- Remote wakeup signaling - RWUSIG : FS_DCTL_RWUSIG_Field := 16#0#; - -- Soft disconnect - SDIS : FS_DCTL_SDIS_Field := 16#0#; - -- Global IN NAK status - GINSTS : FS_DCTL_GINSTS_Field := 16#0#; - -- Global OUT NAK status - GONSTS : FS_DCTL_GONSTS_Field := 16#0#; - -- Test control - TCTL : FS_DCTL_TCTL_Field := 16#0#; - -- Set global IN NAK - SGINAK : FS_DCTL_SGINAK_Field := 16#0#; - -- Clear global IN NAK - CGINAK : FS_DCTL_CGINAK_Field := 16#0#; - -- Set global OUT NAK - SGONAK : FS_DCTL_SGONAK_Field := 16#0#; - -- Clear global OUT NAK - CGONAK : FS_DCTL_CGONAK_Field := 16#0#; - -- Power-on programming done - POPRGDNE : FS_DCTL_POPRGDNE_Field := 16#0#; + subtype FS_GINTMSK_MMISM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_OTGINT_Field is STM32F429x.Bit; + subtype FS_GINTMSK_SOFM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_RXFLVLM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_NPTXFEM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_GINAKEFFM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_GONAKEFFM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_ESUSPM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_USBSUSPM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_USBRST_Field is STM32F429x.Bit; + subtype FS_GINTMSK_ENUMDNEM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_ISOODRPM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_EOPFM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_EPMISM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_IEPINT_Field is STM32F429x.Bit; + subtype FS_GINTMSK_OEPINT_Field is STM32F429x.Bit; + subtype FS_GINTMSK_IISOIXFRM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_IPXFRM_IISOOXFRM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_PRTIM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_HCIM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_PTXFEM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_CIDSCHGM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_DISCINT_Field is STM32F429x.Bit; + subtype FS_GINTMSK_SRQIM_Field is STM32F429x.Bit; + subtype FS_GINTMSK_WUIM_Field is STM32F429x.Bit; + + -- OTG_FS interrupt mask register (OTG_FS_GINTMSK) + type FS_GINTMSK_Register is record -- unspecified - Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + Reserved_0_0 : STM32F429x.Bit := 16#0#; + -- Mode mismatch interrupt mask + MMISM : FS_GINTMSK_MMISM_Field := 16#0#; + -- OTG interrupt mask + OTGINT : FS_GINTMSK_OTGINT_Field := 16#0#; + -- Start of frame mask + SOFM : FS_GINTMSK_SOFM_Field := 16#0#; + -- Receive FIFO non-empty mask + RXFLVLM : FS_GINTMSK_RXFLVLM_Field := 16#0#; + -- Non-periodic TxFIFO empty mask + NPTXFEM : FS_GINTMSK_NPTXFEM_Field := 16#0#; + -- Global non-periodic IN NAK effective mask + GINAKEFFM : FS_GINTMSK_GINAKEFFM_Field := 16#0#; + -- Global OUT NAK effective mask + GONAKEFFM : FS_GINTMSK_GONAKEFFM_Field := 16#0#; + -- unspecified + Reserved_8_9 : STM32F429x.UInt2 := 16#0#; + -- Early suspend mask + ESUSPM : FS_GINTMSK_ESUSPM_Field := 16#0#; + -- USB suspend mask + USBSUSPM : FS_GINTMSK_USBSUSPM_Field := 16#0#; + -- USB reset mask + USBRST : FS_GINTMSK_USBRST_Field := 16#0#; + -- Enumeration done mask + ENUMDNEM : FS_GINTMSK_ENUMDNEM_Field := 16#0#; + -- Isochronous OUT packet dropped interrupt mask + ISOODRPM : FS_GINTMSK_ISOODRPM_Field := 16#0#; + -- End of periodic frame interrupt mask + EOPFM : FS_GINTMSK_EOPFM_Field := 16#0#; + -- unspecified + Reserved_16_16 : STM32F429x.Bit := 16#0#; + -- Endpoint mismatch interrupt mask + EPMISM : FS_GINTMSK_EPMISM_Field := 16#0#; + -- IN endpoints interrupt mask + IEPINT : FS_GINTMSK_IEPINT_Field := 16#0#; + -- OUT endpoints interrupt mask + OEPINT : FS_GINTMSK_OEPINT_Field := 16#0#; + -- Incomplete isochronous IN transfer mask + IISOIXFRM : FS_GINTMSK_IISOIXFRM_Field := 16#0#; + -- Incomplete periodic transfer mask(Host mode)/Incomplete isochronous + -- OUT transfer mask(Device mode) + IPXFRM_IISOOXFRM : FS_GINTMSK_IPXFRM_IISOOXFRM_Field := 16#0#; + -- unspecified + Reserved_22_23 : STM32F429x.UInt2 := 16#0#; + -- Read-only. Host port interrupt mask + PRTIM : FS_GINTMSK_PRTIM_Field := 16#0#; + -- Host channels interrupt mask + HCIM : FS_GINTMSK_HCIM_Field := 16#0#; + -- Periodic TxFIFO empty mask + PTXFEM : FS_GINTMSK_PTXFEM_Field := 16#0#; + -- unspecified + Reserved_27_27 : STM32F429x.Bit := 16#0#; + -- Connector ID status change mask + CIDSCHGM : FS_GINTMSK_CIDSCHGM_Field := 16#0#; + -- Disconnect detected interrupt mask + DISCINT : FS_GINTMSK_DISCINT_Field := 16#0#; + -- Session request/new session detected interrupt mask + SRQIM : FS_GINTMSK_SRQIM_Field := 16#0#; + -- Resume/remote wakeup detected interrupt mask + WUIM : FS_GINTMSK_WUIM_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DCTL_Register use record - RWUSIG at 0 range 0 .. 0; - SDIS at 0 range 1 .. 1; - GINSTS at 0 range 2 .. 2; - GONSTS at 0 range 3 .. 3; - TCTL at 0 range 4 .. 6; - SGINAK at 0 range 7 .. 7; - CGINAK at 0 range 8 .. 8; - SGONAK at 0 range 9 .. 9; - CGONAK at 0 range 10 .. 10; - POPRGDNE at 0 range 11 .. 11; - Reserved_12_31 at 0 range 12 .. 31; + for FS_GINTMSK_Register use record + Reserved_0_0 at 0 range 0 .. 0; + MMISM at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOFM at 0 range 3 .. 3; + RXFLVLM at 0 range 4 .. 4; + NPTXFEM at 0 range 5 .. 5; + GINAKEFFM at 0 range 6 .. 6; + GONAKEFFM at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSPM at 0 range 10 .. 10; + USBSUSPM at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNEM at 0 range 13 .. 13; + ISOODRPM at 0 range 14 .. 14; + EOPFM at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + EPMISM at 0 range 17 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFRM at 0 range 20 .. 20; + IPXFRM_IISOOXFRM at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PRTIM at 0 range 24 .. 24; + HCIM at 0 range 25 .. 25; + PTXFEM at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHGM at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQIM at 0 range 30 .. 30; + WUIM at 0 range 31 .. 31; end record; - ---------------------- - -- FS_DSTS_Register -- - ---------------------- - - subtype FS_DSTS_SUSPSTS_Field is STM32F429x.Bit; - subtype FS_DSTS_ENUMSPD_Field is STM32F429x.UInt2; - subtype FS_DSTS_EERR_Field is STM32F429x.Bit; - subtype FS_DSTS_FNSOF_Field is STM32F429x.UInt14; + subtype FS_GRXSTSR_Device_EPNUM_Field is STM32F429x.UInt4; + subtype FS_GRXSTSR_Device_BCNT_Field is STM32F429x.UInt11; + subtype FS_GRXSTSR_Device_DPID_Field is STM32F429x.UInt2; + subtype FS_GRXSTSR_Device_PKTSTS_Field is STM32F429x.UInt4; + subtype FS_GRXSTSR_Device_FRMNUM_Field is STM32F429x.UInt4; - -- OTG_FS device status register (OTG_FS_DSTS) - type FS_DSTS_Register is record - -- Suspend status - SUSPSTS : FS_DSTS_SUSPSTS_Field; - -- Enumerated speed - ENUMSPD : FS_DSTS_ENUMSPD_Field; - -- Erratic error - EERR : FS_DSTS_EERR_Field; - -- unspecified - Reserved_4_7 : STM32F429x.UInt4; - -- Frame number of the received SOF - FNSOF : FS_DSTS_FNSOF_Field; + -- OTG_FS Receive status debug read(Device mode) + type FS_GRXSTSR_Device_Register is record + -- Read-only. Endpoint number + EPNUM : FS_GRXSTSR_Device_EPNUM_Field; + -- Read-only. Byte count + BCNT : FS_GRXSTSR_Device_BCNT_Field; + -- Read-only. Data PID + DPID : FS_GRXSTSR_Device_DPID_Field; + -- Read-only. Packet status + PKTSTS : FS_GRXSTSR_Device_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : FS_GRXSTSR_Device_FRMNUM_Field; -- unspecified - Reserved_22_31 : STM32F429x.UInt10; + Reserved_25_31 : STM32F429x.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DSTS_Register use record - SUSPSTS at 0 range 0 .. 0; - ENUMSPD at 0 range 1 .. 2; - EERR at 0 range 3 .. 3; - Reserved_4_7 at 0 range 4 .. 7; - FNSOF at 0 range 8 .. 21; - Reserved_22_31 at 0 range 22 .. 31; + for FS_GRXSTSR_Device_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------------- - -- FS_DIEPMSK_Register -- - ------------------------- - - subtype FS_DIEPMSK_XFRCM_Field is STM32F429x.Bit; - subtype FS_DIEPMSK_EPDM_Field is STM32F429x.Bit; - subtype FS_DIEPMSK_TOM_Field is STM32F429x.Bit; - subtype FS_DIEPMSK_ITTXFEMSK_Field is STM32F429x.Bit; - subtype FS_DIEPMSK_INEPNMM_Field is STM32F429x.Bit; - subtype FS_DIEPMSK_INEPNEM_Field is STM32F429x.Bit; + subtype FS_GRXSTSR_Host_EPNUM_Field is STM32F429x.UInt4; + subtype FS_GRXSTSR_Host_BCNT_Field is STM32F429x.UInt11; + subtype FS_GRXSTSR_Host_DPID_Field is STM32F429x.UInt2; + subtype FS_GRXSTSR_Host_PKTSTS_Field is STM32F429x.UInt4; + subtype FS_GRXSTSR_Host_FRMNUM_Field is STM32F429x.UInt4; - -- OTG_FS device IN endpoint common interrupt mask register - -- (OTG_FS_DIEPMSK) - type FS_DIEPMSK_Register is record - -- Transfer completed interrupt mask - XFRCM : FS_DIEPMSK_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : FS_DIEPMSK_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- Timeout condition mask (Non-isochronous endpoints) - TOM : FS_DIEPMSK_TOM_Field := 16#0#; - -- IN token received when TxFIFO empty mask - ITTXFEMSK : FS_DIEPMSK_ITTXFEMSK_Field := 16#0#; - -- IN token received with EP mismatch mask - INEPNMM : FS_DIEPMSK_INEPNMM_Field := 16#0#; - -- IN endpoint NAK effective mask - INEPNEM : FS_DIEPMSK_INEPNEM_Field := 16#0#; + -- OTG_FS Receive status debug read(Host mode) + type FS_GRXSTSR_Host_Register is record + -- Read-only. Endpoint number + EPNUM : FS_GRXSTSR_Host_EPNUM_Field; + -- Read-only. Byte count + BCNT : FS_GRXSTSR_Host_BCNT_Field; + -- Read-only. Data PID + DPID : FS_GRXSTSR_Host_DPID_Field; + -- Read-only. Packet status + PKTSTS : FS_GRXSTSR_Host_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : FS_GRXSTSR_Host_FRMNUM_Field; -- unspecified - Reserved_7_31 : STM32F429x.UInt25 := 16#0#; + Reserved_25_31 : STM32F429x.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DIEPMSK_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOM at 0 range 3 .. 3; - ITTXFEMSK at 0 range 4 .. 4; - INEPNMM at 0 range 5 .. 5; - INEPNEM at 0 range 6 .. 6; - Reserved_7_31 at 0 range 7 .. 31; + for FS_GRXSTSR_Host_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------------- - -- FS_DOEPMSK_Register -- - ------------------------- - - subtype FS_DOEPMSK_XFRCM_Field is STM32F429x.Bit; - subtype FS_DOEPMSK_EPDM_Field is STM32F429x.Bit; - subtype FS_DOEPMSK_STUPM_Field is STM32F429x.Bit; - subtype FS_DOEPMSK_OTEPDM_Field is STM32F429x.Bit; + subtype FS_GRXFSIZ_RXFD_Field is STM32F429x.UInt16; - -- OTG_FS device OUT endpoint common interrupt mask register - -- (OTG_FS_DOEPMSK) - type FS_DOEPMSK_Register is record - -- Transfer completed interrupt mask - XFRCM : FS_DOEPMSK_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : FS_DOEPMSK_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- SETUP phase done mask - STUPM : FS_DOEPMSK_STUPM_Field := 16#0#; - -- OUT token received when endpoint disabled mask - OTEPDM : FS_DOEPMSK_OTEPDM_Field := 16#0#; + -- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + type FS_GRXFSIZ_Register is record + -- RxFIFO depth + RXFD : FS_GRXFSIZ_RXFD_Field := 16#200#; -- unspecified - Reserved_5_31 : STM32F429x.UInt27 := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DOEPMSK_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STUPM at 0 range 3 .. 3; - OTEPDM at 0 range 4 .. 4; - Reserved_5_31 at 0 range 5 .. 31; + for FS_GRXFSIZ_Register use record + RXFD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------- - -- FS_DAINT_Register -- - ----------------------- + subtype FS_GNPTXFSIZ_Device_TX0FSA_Field is STM32F429x.UInt16; + subtype FS_GNPTXFSIZ_Device_TX0FD_Field is STM32F429x.UInt16; - subtype FS_DAINT_IEPINT_Field is STM32F429x.Short; - subtype FS_DAINT_OEPINT_Field is STM32F429x.Short; - - -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) - type FS_DAINT_Register is record - -- IN endpoint interrupt bits - IEPINT : FS_DAINT_IEPINT_Field; - -- OUT endpoint interrupt bits - OEPINT : FS_DAINT_OEPINT_Field; + -- OTG_FS non-periodic transmit FIFO size register (Device mode) + type FS_GNPTXFSIZ_Device_Register is record + -- Endpoint 0 transmit RAM start address + TX0FSA : FS_GNPTXFSIZ_Device_TX0FSA_Field := 16#200#; + -- Endpoint 0 TxFIFO depth + TX0FD : FS_GNPTXFSIZ_Device_TX0FD_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DAINT_Register use record - IEPINT at 0 range 0 .. 15; - OEPINT at 0 range 16 .. 31; + for FS_GNPTXFSIZ_Device_Register use record + TX0FSA at 0 range 0 .. 15; + TX0FD at 0 range 16 .. 31; end record; - -------------------------- - -- FS_DAINTMSK_Register -- - -------------------------- - - subtype FS_DAINTMSK_IEPM_Field is STM32F429x.Short; - subtype FS_DAINTMSK_OEPINT_Field is STM32F429x.Short; + subtype FS_GNPTXFSIZ_Host_NPTXFSA_Field is STM32F429x.UInt16; + subtype FS_GNPTXFSIZ_Host_NPTXFD_Field is STM32F429x.UInt16; - -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) - type FS_DAINTMSK_Register is record - -- IN EP interrupt mask bits - IEPM : FS_DAINTMSK_IEPM_Field := 16#0#; - -- OUT endpoint interrupt bits - OEPINT : FS_DAINTMSK_OEPINT_Field := 16#0#; + -- OTG_FS non-periodic transmit FIFO size register (Host mode) + type FS_GNPTXFSIZ_Host_Register is record + -- Non-periodic transmit RAM start address + NPTXFSA : FS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; + -- Non-periodic TxFIFO depth + NPTXFD : FS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DAINTMSK_Register use record - IEPM at 0 range 0 .. 15; - OEPINT at 0 range 16 .. 31; + for FS_GNPTXFSIZ_Host_Register use record + NPTXFSA at 0 range 0 .. 15; + NPTXFD at 0 range 16 .. 31; end record; - ----------------------- - -- DVBUSDIS_Register -- - ----------------------- - - subtype DVBUSDIS_VBUSDT_Field is STM32F429x.Short; + subtype FS_GNPTXSTS_NPTXFSAV_Field is STM32F429x.UInt16; + subtype FS_GNPTXSTS_NPTQXSAV_Field is STM32F429x.Byte; + subtype FS_GNPTXSTS_NPTXQTOP_Field is STM32F429x.UInt7; - -- OTG_FS device VBUS discharge time register - type DVBUSDIS_Register is record - -- Device VBUS discharge time - VBUSDT : DVBUSDIS_VBUSDT_Field := 16#17D7#; + -- OTG_FS non-periodic transmit FIFO/queue status register + -- (OTG_FS_GNPTXSTS) + type FS_GNPTXSTS_Register is record + -- Read-only. Non-periodic TxFIFO space available + NPTXFSAV : FS_GNPTXSTS_NPTXFSAV_Field; + -- Read-only. Non-periodic transmit request queue space available + NPTQXSAV : FS_GNPTXSTS_NPTQXSAV_Field; + -- Read-only. Top of the non-periodic transmit request queue + NPTXQTOP : FS_GNPTXSTS_NPTXQTOP_Field; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_31_31 : STM32F429x.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DVBUSDIS_Register use record - VBUSDT at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_GNPTXSTS_Register use record + NPTXFSAV at 0 range 0 .. 15; + NPTQXSAV at 0 range 16 .. 23; + NPTXQTOP at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------- - -- DVBUSPULSE_Register -- - ------------------------- - - subtype DVBUSPULSE_DVBUSP_Field is STM32F429x.UInt12; + subtype FS_GCCFG_PWRDWN_Field is STM32F429x.Bit; + subtype FS_GCCFG_VBUSASEN_Field is STM32F429x.Bit; + subtype FS_GCCFG_VBUSBSEN_Field is STM32F429x.Bit; + subtype FS_GCCFG_SOFOUTEN_Field is STM32F429x.Bit; - -- OTG_FS device VBUS pulsing time register - type DVBUSPULSE_Register is record - -- Device VBUS pulsing time - DVBUSP : DVBUSPULSE_DVBUSP_Field := 16#5B8#; + -- OTG_FS general core configuration register (OTG_FS_GCCFG) + type FS_GCCFG_Register is record -- unspecified - Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + Reserved_0_15 : STM32F429x.UInt16 := 16#0#; + -- Power down + PWRDWN : FS_GCCFG_PWRDWN_Field := 16#0#; + -- unspecified + Reserved_17_17 : STM32F429x.Bit := 16#0#; + -- Enable the VBUS sensing device + VBUSASEN : FS_GCCFG_VBUSASEN_Field := 16#0#; + -- Enable the VBUS sensing device + VBUSBSEN : FS_GCCFG_VBUSBSEN_Field := 16#0#; + -- SOF output enable + SOFOUTEN : FS_GCCFG_SOFOUTEN_Field := 16#0#; + -- unspecified + Reserved_21_31 : STM32F429x.UInt11 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DVBUSPULSE_Register use record - DVBUSP at 0 range 0 .. 11; - Reserved_12_31 at 0 range 12 .. 31; + for FS_GCCFG_Register use record + Reserved_0_15 at 0 range 0 .. 15; + PWRDWN at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + VBUSASEN at 0 range 18 .. 18; + VBUSBSEN at 0 range 19 .. 19; + SOFOUTEN at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------------- - -- DIEPEMPMSK_Register -- - ------------------------- + subtype FS_HPTXFSIZ_PTXSA_Field is STM32F429x.UInt16; + subtype FS_HPTXFSIZ_PTXFSIZ_Field is STM32F429x.UInt16; - subtype DIEPEMPMSK_INEPTXFEM_Field is STM32F429x.Short; - - -- OTG_FS device IN endpoint FIFO empty interrupt mask register - type DIEPEMPMSK_Register is record - -- IN EP Tx FIFO empty interrupt mask bits - INEPTXFEM : DIEPEMPMSK_INEPTXFEM_Field := 16#0#; - -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + -- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + type FS_HPTXFSIZ_Register is record + -- Host periodic TxFIFO start address + PTXSA : FS_HPTXFSIZ_PTXSA_Field := 16#600#; + -- Host periodic TxFIFO depth + PTXFSIZ : FS_HPTXFSIZ_PTXFSIZ_Field := 16#200#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPEMPMSK_Register use record - INEPTXFEM at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_HPTXFSIZ_Register use record + PTXSA at 0 range 0 .. 15; + PTXFSIZ at 0 range 16 .. 31; end record; - -------------------------- - -- FS_DIEPCTL0_Register -- - -------------------------- - - subtype FS_DIEPCTL0_MPSIZ_Field is STM32F429x.UInt2; - subtype FS_DIEPCTL0_USBAEP_Field is STM32F429x.Bit; - subtype FS_DIEPCTL0_NAKSTS_Field is STM32F429x.Bit; - subtype FS_DIEPCTL0_EPTYP_Field is STM32F429x.UInt2; - subtype FS_DIEPCTL0_STALL_Field is STM32F429x.Bit; - subtype FS_DIEPCTL0_TXFNUM_Field is STM32F429x.UInt4; - subtype FS_DIEPCTL0_CNAK_Field is STM32F429x.Bit; - subtype FS_DIEPCTL0_SNAK_Field is STM32F429x.Bit; - subtype FS_DIEPCTL0_EPDIS_Field is STM32F429x.Bit; - subtype FS_DIEPCTL0_EPENA_Field is STM32F429x.Bit; + subtype FS_DIEPTXF_INEPTXSA_Field is STM32F429x.UInt16; + subtype FS_DIEPTXF_INEPTXFD_Field is STM32F429x.UInt16; - -- OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) - type FS_DIEPCTL0_Register is record - -- Maximum packet size - MPSIZ : FS_DIEPCTL0_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_2_14 : STM32F429x.UInt13 := 16#0#; - -- USB active endpoint - USBAEP : FS_DIEPCTL0_USBAEP_Field := 16#0#; - -- unspecified - Reserved_16_16 : STM32F429x.Bit := 16#0#; - -- NAK status - NAKSTS : FS_DIEPCTL0_NAKSTS_Field := 16#0#; - -- Endpoint type - EPTYP : FS_DIEPCTL0_EPTYP_Field := 16#0#; - -- unspecified - Reserved_20_20 : STM32F429x.Bit := 16#0#; - -- STALL handshake - STALL : FS_DIEPCTL0_STALL_Field := 16#0#; - -- TxFIFO number - TXFNUM : FS_DIEPCTL0_TXFNUM_Field := 16#0#; - -- Clear NAK - CNAK : FS_DIEPCTL0_CNAK_Field := 16#0#; - -- Set NAK - SNAK : FS_DIEPCTL0_SNAK_Field := 16#0#; - -- unspecified - Reserved_28_29 : STM32F429x.UInt2 := 16#0#; - -- Endpoint disable - EPDIS : FS_DIEPCTL0_EPDIS_Field := 16#0#; - -- Endpoint enable - EPENA : FS_DIEPCTL0_EPENA_Field := 16#0#; + -- OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + type FS_DIEPTXF_Register is record + -- IN endpoint FIFO2 transmit RAM start address + INEPTXSA : FS_DIEPTXF_INEPTXSA_Field := 16#400#; + -- IN endpoint TxFIFO depth + INEPTXFD : FS_DIEPTXF_INEPTXFD_Field := 16#200#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for FS_DIEPCTL0_Register use record - MPSIZ at 0 range 0 .. 1; - Reserved_2_14 at 0 range 2 .. 14; - USBAEP at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - Reserved_20_20 at 0 range 20 .. 20; - STALL at 0 range 21 .. 21; - TXFNUM at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - Reserved_28_29 at 0 range 28 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for FS_DIEPTXF_Register use record + INEPTXSA at 0 range 0 .. 15; + INEPTXFD at 0 range 16 .. 31; end record; - ---------------------- - -- DIEPINT_Register -- - ---------------------- - - subtype DIEPINT0_XFRC_Field is STM32F429x.Bit; - subtype DIEPINT0_EPDISD_Field is STM32F429x.Bit; - subtype DIEPINT0_TOC_Field is STM32F429x.Bit; - subtype DIEPINT0_ITTXFE_Field is STM32F429x.Bit; - subtype DIEPINT0_INEPNE_Field is STM32F429x.Bit; - subtype DIEPINT0_TXFE_Field is STM32F429x.Bit; + subtype FS_HCFG_FSLSPCS_Field is STM32F429x.UInt2; + subtype FS_HCFG_FSLSS_Field is STM32F429x.Bit; - -- device endpoint-x interrupt register - type DIEPINT_Register is record - -- XFRC - XFRC : DIEPINT0_XFRC_Field := 16#0#; - -- EPDISD - EPDISD : DIEPINT0_EPDISD_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- TOC - TOC : DIEPINT0_TOC_Field := 16#0#; - -- ITTXFE - ITTXFE : DIEPINT0_ITTXFE_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F429x.Bit := 16#0#; - -- INEPNE - INEPNE : DIEPINT0_INEPNE_Field := 16#0#; - -- TXFE - TXFE : DIEPINT0_TXFE_Field := 16#1#; + -- OTG_FS host configuration register (OTG_FS_HCFG) + type FS_HCFG_Register is record + -- FS/LS PHY clock select + FSLSPCS : FS_HCFG_FSLSPCS_Field := 16#0#; + -- Read-only. FS- and LS-only support + FSLSS : FS_HCFG_FSLSS_Field := 16#0#; -- unspecified - Reserved_8_31 : STM32F429x.UInt24 := 16#0#; + Reserved_3_31 : STM32F429x.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for DIEPINT_Register use record - XFRC at 0 range 0 .. 0; - EPDISD at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOC at 0 range 3 .. 3; - ITTXFE at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - INEPNE at 0 range 6 .. 6; - TXFE at 0 range 7 .. 7; - Reserved_8_31 at 0 range 8 .. 31; - end record; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - ------------------------ - -- DIEPTSIZ0_Register -- - ------------------------ + for FS_HCFG_Register use record + FSLSPCS at 0 range 0 .. 1; + FSLSS at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; - subtype DIEPTSIZ0_XFRSIZ_Field is STM32F429x.UInt7; - subtype DIEPTSIZ0_PKTCNT_Field is STM32F429x.UInt2; + subtype HFIR_FRIVL_Field is STM32F429x.UInt16; - -- device endpoint-0 transfer size register - type DIEPTSIZ0_Register is record - -- Transfer size - XFRSIZ : DIEPTSIZ0_XFRSIZ_Field := 16#0#; - -- unspecified - Reserved_7_18 : STM32F429x.UInt12 := 16#0#; - -- Packet count - PKTCNT : DIEPTSIZ0_PKTCNT_Field := 16#0#; + -- OTG_FS Host frame interval register + type HFIR_Register is record + -- Frame interval + FRIVL : HFIR_FRIVL_Field := 16#EA60#; -- unspecified - Reserved_21_31 : STM32F429x.UInt11 := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPTSIZ0_Register use record - XFRSIZ at 0 range 0 .. 6; - Reserved_7_18 at 0 range 7 .. 18; - PKTCNT at 0 range 19 .. 20; - Reserved_21_31 at 0 range 21 .. 31; + for HFIR_Register use record + FRIVL at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------- - -- DTXFSTS_Register -- - ---------------------- + subtype FS_HFNUM_FRNUM_Field is STM32F429x.UInt16; + subtype FS_HFNUM_FTREM_Field is STM32F429x.UInt16; - subtype DTXFSTS0_INEPTFSAV_Field is STM32F429x.Short; - - -- OTG_FS device IN endpoint transmit FIFO status register - type DTXFSTS_Register is record - -- IN endpoint TxFIFO space available - INEPTFSAV : DTXFSTS0_INEPTFSAV_Field; - -- unspecified - Reserved_16_31 : STM32F429x.Short; + -- OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + type FS_HFNUM_Register is record + -- Read-only. Frame number + FRNUM : FS_HFNUM_FRNUM_Field; + -- Read-only. Frame time remaining + FTREM : FS_HFNUM_FTREM_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DTXFSTS_Register use record - INEPTFSAV at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for FS_HFNUM_Register use record + FRNUM at 0 range 0 .. 15; + FTREM at 0 range 16 .. 31; end record; - ---------------------- - -- DIEPCTL_Register -- - ---------------------- + subtype FS_HPTXSTS_PTXFSAVL_Field is STM32F429x.UInt16; + subtype FS_HPTXSTS_PTXQSAV_Field is STM32F429x.Byte; + subtype FS_HPTXSTS_PTXQTOP_Field is STM32F429x.Byte; - subtype DIEPCTL1_MPSIZ_Field is STM32F429x.UInt11; - subtype DIEPCTL1_USBAEP_Field is STM32F429x.Bit; - subtype DIEPCTL1_EONUM_DPID_Field is STM32F429x.Bit; - subtype DIEPCTL1_NAKSTS_Field is STM32F429x.Bit; - subtype DIEPCTL1_EPTYP_Field is STM32F429x.UInt2; - subtype DIEPCTL1_Stall_Field is STM32F429x.Bit; - subtype DIEPCTL1_TXFNUM_Field is STM32F429x.UInt4; - subtype DIEPCTL1_CNAK_Field is STM32F429x.Bit; - subtype DIEPCTL1_SNAK_Field is STM32F429x.Bit; - subtype DIEPCTL1_SD0PID_SEVNFRM_Field is STM32F429x.Bit; - subtype DIEPCTL1_SODDFRM_SD1PID_Field is STM32F429x.Bit; - subtype DIEPCTL1_EPDIS_Field is STM32F429x.Bit; - subtype DIEPCTL1_EPENA_Field is STM32F429x.Bit; + -- OTG_FS_Host periodic transmit FIFO/queue status register + -- (OTG_FS_HPTXSTS) + type FS_HPTXSTS_Register is record + -- Periodic transmit data FIFO space available + PTXFSAVL : FS_HPTXSTS_PTXFSAVL_Field := 16#100#; + -- Read-only. Periodic transmit request queue space available + PTXQSAV : FS_HPTXSTS_PTXQSAV_Field := 16#8#; + -- Read-only. Top of the periodic transmit request queue + PTXQTOP : FS_HPTXSTS_PTXQTOP_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG device endpoint-1 control register - type DIEPCTL_Register is record - -- MPSIZ - MPSIZ : DIEPCTL1_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_11_14 : STM32F429x.UInt4 := 16#0#; - -- USBAEP - USBAEP : DIEPCTL1_USBAEP_Field := 16#0#; - -- EONUM/DPID - EONUM_DPID : DIEPCTL1_EONUM_DPID_Field := 16#0#; - -- NAKSTS - NAKSTS : DIEPCTL1_NAKSTS_Field := 16#0#; - -- EPTYP - EPTYP : DIEPCTL1_EPTYP_Field := 16#0#; + for FS_HPTXSTS_Register use record + PTXFSAVL at 0 range 0 .. 15; + PTXQSAV at 0 range 16 .. 23; + PTXQTOP at 0 range 24 .. 31; + end record; + + subtype HAINT_HAINT_Field is STM32F429x.UInt16; + + -- OTG_FS Host all channels interrupt register + type HAINT_Register is record + -- Read-only. Channel interrupts + HAINT : HAINT_HAINT_Field; -- unspecified - Reserved_20_20 : STM32F429x.Bit := 16#0#; - -- Stall - Stall : DIEPCTL1_Stall_Field := 16#0#; - -- TXFNUM - TXFNUM : DIEPCTL1_TXFNUM_Field := 16#0#; - -- CNAK - CNAK : DIEPCTL1_CNAK_Field := 16#0#; - -- SNAK - SNAK : DIEPCTL1_SNAK_Field := 16#0#; - -- SD0PID/SEVNFRM - SD0PID_SEVNFRM : DIEPCTL1_SD0PID_SEVNFRM_Field := 16#0#; - -- SODDFRM/SD1PID - SODDFRM_SD1PID : DIEPCTL1_SODDFRM_SD1PID_Field := 16#0#; - -- EPDIS - EPDIS : DIEPCTL1_EPDIS_Field := 16#0#; - -- EPENA - EPENA : DIEPCTL1_EPENA_Field := 16#0#; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPCTL_Register use record - MPSIZ at 0 range 0 .. 10; - Reserved_11_14 at 0 range 11 .. 14; - USBAEP at 0 range 15 .. 15; - EONUM_DPID at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - Reserved_20_20 at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - TXFNUM at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - SD0PID_SEVNFRM at 0 range 28 .. 28; - SODDFRM_SD1PID at 0 range 29 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for HAINT_Register use record + HAINT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------- - -- DIEPTSIZ_Register -- - ----------------------- - - subtype DIEPTSIZ1_XFRSIZ_Field is STM32F429x.UInt19; - subtype DIEPTSIZ1_PKTCNT_Field is STM32F429x.UInt10; - subtype DIEPTSIZ1_MCNT_Field is STM32F429x.UInt2; + subtype HAINTMSK_HAINTM_Field is STM32F429x.UInt16; - -- device endpoint-1 transfer size register - type DIEPTSIZ_Register is record - -- Transfer size - XFRSIZ : DIEPTSIZ1_XFRSIZ_Field := 16#0#; - -- Packet count - PKTCNT : DIEPTSIZ1_PKTCNT_Field := 16#0#; - -- Multi count - MCNT : DIEPTSIZ1_MCNT_Field := 16#0#; + -- OTG_FS host all channels interrupt mask register + type HAINTMSK_Register is record + -- Channel interrupt mask + HAINTM : HAINTMSK_HAINTM_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F429x.Bit := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DIEPTSIZ_Register use record - XFRSIZ at 0 range 0 .. 18; - PKTCNT at 0 range 19 .. 28; - MCNT at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for HAINTMSK_Register use record + HAINTM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------- - -- DOEPCTL0_Register -- - ----------------------- - - subtype DOEPCTL0_MPSIZ_Field is STM32F429x.UInt2; - subtype DOEPCTL0_USBAEP_Field is STM32F429x.Bit; - subtype DOEPCTL0_NAKSTS_Field is STM32F429x.Bit; - subtype DOEPCTL0_EPTYP_Field is STM32F429x.UInt2; - subtype DOEPCTL0_SNPM_Field is STM32F429x.Bit; - subtype DOEPCTL0_Stall_Field is STM32F429x.Bit; - subtype DOEPCTL0_CNAK_Field is STM32F429x.Bit; - subtype DOEPCTL0_SNAK_Field is STM32F429x.Bit; - subtype DOEPCTL0_EPDIS_Field is STM32F429x.Bit; - subtype DOEPCTL0_EPENA_Field is STM32F429x.Bit; + subtype FS_HPRT_PCSTS_Field is STM32F429x.Bit; + subtype FS_HPRT_PCDET_Field is STM32F429x.Bit; + subtype FS_HPRT_PENA_Field is STM32F429x.Bit; + subtype FS_HPRT_PENCHNG_Field is STM32F429x.Bit; + subtype FS_HPRT_POCA_Field is STM32F429x.Bit; + subtype FS_HPRT_POCCHNG_Field is STM32F429x.Bit; + subtype FS_HPRT_PRES_Field is STM32F429x.Bit; + subtype FS_HPRT_PSUSP_Field is STM32F429x.Bit; + subtype FS_HPRT_PRST_Field is STM32F429x.Bit; + subtype FS_HPRT_PLSTS_Field is STM32F429x.UInt2; + subtype FS_HPRT_PPWR_Field is STM32F429x.Bit; + subtype FS_HPRT_PTCTL_Field is STM32F429x.UInt4; + subtype FS_HPRT_PSPD_Field is STM32F429x.UInt2; - -- device endpoint-0 control register - type DOEPCTL0_Register is record - -- MPSIZ - MPSIZ : DOEPCTL0_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_2_14 : STM32F429x.UInt13 := 16#0#; - -- USBAEP - USBAEP : DOEPCTL0_USBAEP_Field := 16#1#; - -- unspecified - Reserved_16_16 : STM32F429x.Bit := 16#0#; - -- NAKSTS - NAKSTS : DOEPCTL0_NAKSTS_Field := 16#0#; - -- EPTYP - EPTYP : DOEPCTL0_EPTYP_Field := 16#0#; - -- SNPM - SNPM : DOEPCTL0_SNPM_Field := 16#0#; - -- Stall - Stall : DOEPCTL0_Stall_Field := 16#0#; + -- OTG_FS host port control and status register (OTG_FS_HPRT) + type FS_HPRT_Register is record + -- Read-only. Port connect status + PCSTS : FS_HPRT_PCSTS_Field := 16#0#; + -- Port connect detected + PCDET : FS_HPRT_PCDET_Field := 16#0#; + -- Port enable + PENA : FS_HPRT_PENA_Field := 16#0#; + -- Port enable/disable change + PENCHNG : FS_HPRT_PENCHNG_Field := 16#0#; + -- Read-only. Port overcurrent active + POCA : FS_HPRT_POCA_Field := 16#0#; + -- Port overcurrent change + POCCHNG : FS_HPRT_POCCHNG_Field := 16#0#; + -- Port resume + PRES : FS_HPRT_PRES_Field := 16#0#; + -- Port suspend + PSUSP : FS_HPRT_PSUSP_Field := 16#0#; + -- Port reset + PRST : FS_HPRT_PRST_Field := 16#0#; -- unspecified - Reserved_22_25 : STM32F429x.UInt4 := 16#0#; - -- CNAK - CNAK : DOEPCTL0_CNAK_Field := 16#0#; - -- SNAK - SNAK : DOEPCTL0_SNAK_Field := 16#0#; + Reserved_9_9 : STM32F429x.Bit := 16#0#; + -- Read-only. Port line status + PLSTS : FS_HPRT_PLSTS_Field := 16#0#; + -- Port power + PPWR : FS_HPRT_PPWR_Field := 16#0#; + -- Port test control + PTCTL : FS_HPRT_PTCTL_Field := 16#0#; + -- Read-only. Port speed + PSPD : FS_HPRT_PSPD_Field := 16#0#; -- unspecified - Reserved_28_29 : STM32F429x.UInt2 := 16#0#; - -- EPDIS - EPDIS : DOEPCTL0_EPDIS_Field := 16#0#; - -- EPENA - EPENA : DOEPCTL0_EPENA_Field := 16#0#; + Reserved_19_31 : STM32F429x.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPCTL0_Register use record - MPSIZ at 0 range 0 .. 1; - Reserved_2_14 at 0 range 2 .. 14; - USBAEP at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - SNPM at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - Reserved_22_25 at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - Reserved_28_29 at 0 range 28 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for FS_HPRT_Register use record + PCSTS at 0 range 0 .. 0; + PCDET at 0 range 1 .. 1; + PENA at 0 range 2 .. 2; + PENCHNG at 0 range 3 .. 3; + POCA at 0 range 4 .. 4; + POCCHNG at 0 range 5 .. 5; + PRES at 0 range 6 .. 6; + PSUSP at 0 range 7 .. 7; + PRST at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PLSTS at 0 range 10 .. 11; + PPWR at 0 range 12 .. 12; + PTCTL at 0 range 13 .. 16; + PSPD at 0 range 17 .. 18; + Reserved_19_31 at 0 range 19 .. 31; end record; - ---------------------- - -- DOEPINT_Register -- - ---------------------- + subtype FS_HCCHAR_MPSIZ_Field is STM32F429x.UInt11; + subtype FS_HCCHAR_EPNUM_Field is STM32F429x.UInt4; + subtype FS_HCCHAR_EPDIR_Field is STM32F429x.Bit; + subtype FS_HCCHAR_LSDEV_Field is STM32F429x.Bit; + subtype FS_HCCHAR_EPTYP_Field is STM32F429x.UInt2; + subtype FS_HCCHAR_MCNT_Field is STM32F429x.UInt2; + subtype FS_HCCHAR_DAD_Field is STM32F429x.UInt7; + subtype FS_HCCHAR_ODDFRM_Field is STM32F429x.Bit; + subtype FS_HCCHAR_CHDIS_Field is STM32F429x.Bit; + subtype FS_HCCHAR_CHENA_Field is STM32F429x.Bit; - subtype DOEPINT0_XFRC_Field is STM32F429x.Bit; - subtype DOEPINT0_EPDISD_Field is STM32F429x.Bit; - subtype DOEPINT0_STUP_Field is STM32F429x.Bit; - subtype DOEPINT0_OTEPDIS_Field is STM32F429x.Bit; - subtype DOEPINT0_B2BSTUP_Field is STM32F429x.Bit; - - -- device endpoint-0 interrupt register - type DOEPINT_Register is record - -- XFRC - XFRC : DOEPINT0_XFRC_Field := 16#0#; - -- EPDISD - EPDISD : DOEPINT0_EPDISD_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- STUP - STUP : DOEPINT0_STUP_Field := 16#0#; - -- OTEPDIS - OTEPDIS : DOEPINT0_OTEPDIS_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F429x.Bit := 16#0#; - -- B2BSTUP - B2BSTUP : DOEPINT0_B2BSTUP_Field := 16#0#; + -- OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + type FS_HCCHAR_Register is record + -- Maximum packet size + MPSIZ : FS_HCCHAR_MPSIZ_Field := 16#0#; + -- Endpoint number + EPNUM : FS_HCCHAR_EPNUM_Field := 16#0#; + -- Endpoint direction + EPDIR : FS_HCCHAR_EPDIR_Field := 16#0#; -- unspecified - Reserved_7_31 : STM32F429x.UInt25 := 16#1#; + Reserved_16_16 : STM32F429x.Bit := 16#0#; + -- Low-speed device + LSDEV : FS_HCCHAR_LSDEV_Field := 16#0#; + -- Endpoint type + EPTYP : FS_HCCHAR_EPTYP_Field := 16#0#; + -- Multicount + MCNT : FS_HCCHAR_MCNT_Field := 16#0#; + -- Device address + DAD : FS_HCCHAR_DAD_Field := 16#0#; + -- Odd frame + ODDFRM : FS_HCCHAR_ODDFRM_Field := 16#0#; + -- Channel disable + CHDIS : FS_HCCHAR_CHDIS_Field := 16#0#; + -- Channel enable + CHENA : FS_HCCHAR_CHENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPINT_Register use record - XFRC at 0 range 0 .. 0; - EPDISD at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STUP at 0 range 3 .. 3; - OTEPDIS at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - B2BSTUP at 0 range 6 .. 6; - Reserved_7_31 at 0 range 7 .. 31; + for FS_HCCHAR_Register use record + MPSIZ at 0 range 0 .. 10; + EPNUM at 0 range 11 .. 14; + EPDIR at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + LSDEV at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + MCNT at 0 range 20 .. 21; + DAD at 0 range 22 .. 28; + ODDFRM at 0 range 29 .. 29; + CHDIS at 0 range 30 .. 30; + CHENA at 0 range 31 .. 31; end record; - ------------------------ - -- DOEPTSIZ0_Register -- - ------------------------ - - subtype DOEPTSIZ0_XFRSIZ_Field is STM32F429x.UInt7; - subtype DOEPTSIZ0_PKTCNT_Field is STM32F429x.Bit; - subtype DOEPTSIZ0_STUPCNT_Field is STM32F429x.UInt2; + subtype FS_HCINT_XFRC_Field is STM32F429x.Bit; + subtype FS_HCINT_CHH_Field is STM32F429x.Bit; + subtype FS_HCINT_STALL_Field is STM32F429x.Bit; + subtype FS_HCINT_NAK_Field is STM32F429x.Bit; + subtype FS_HCINT_ACK_Field is STM32F429x.Bit; + subtype FS_HCINT_TXERR_Field is STM32F429x.Bit; + subtype FS_HCINT_BBERR_Field is STM32F429x.Bit; + subtype FS_HCINT_FRMOR_Field is STM32F429x.Bit; + subtype FS_HCINT_DTERR_Field is STM32F429x.Bit; - -- device OUT endpoint-0 transfer size register - type DOEPTSIZ0_Register is record - -- Transfer size - XFRSIZ : DOEPTSIZ0_XFRSIZ_Field := 16#0#; + -- OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + type FS_HCINT_Register is record + -- Transfer completed + XFRC : FS_HCINT_XFRC_Field := 16#0#; + -- Channel halted + CHH : FS_HCINT_CHH_Field := 16#0#; -- unspecified - Reserved_7_18 : STM32F429x.UInt12 := 16#0#; - -- Packet count - PKTCNT : DOEPTSIZ0_PKTCNT_Field := 16#0#; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- STALL response received interrupt + STALL : FS_HCINT_STALL_Field := 16#0#; + -- NAK response received interrupt + NAK : FS_HCINT_NAK_Field := 16#0#; + -- ACK response received/transmitted interrupt + ACK : FS_HCINT_ACK_Field := 16#0#; -- unspecified - Reserved_20_28 : STM32F429x.UInt9 := 16#0#; - -- SETUP packet count - STUPCNT : DOEPTSIZ0_STUPCNT_Field := 16#0#; + Reserved_6_6 : STM32F429x.Bit := 16#0#; + -- Transaction error + TXERR : FS_HCINT_TXERR_Field := 16#0#; + -- Babble error + BBERR : FS_HCINT_BBERR_Field := 16#0#; + -- Frame overrun + FRMOR : FS_HCINT_FRMOR_Field := 16#0#; + -- Data toggle error + DTERR : FS_HCINT_DTERR_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F429x.Bit := 16#0#; + Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPTSIZ0_Register use record - XFRSIZ at 0 range 0 .. 6; - Reserved_7_18 at 0 range 7 .. 18; - PKTCNT at 0 range 19 .. 19; - Reserved_20_28 at 0 range 20 .. 28; - STUPCNT at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for FS_HCINT_Register use record + XFRC at 0 range 0 .. 0; + CHH at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STALL at 0 range 3 .. 3; + NAK at 0 range 4 .. 4; + ACK at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + TXERR at 0 range 7 .. 7; + BBERR at 0 range 8 .. 8; + FRMOR at 0 range 9 .. 9; + DTERR at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; end record; - ---------------------- - -- DOEPCTL_Register -- - ---------------------- - - subtype DOEPCTL1_MPSIZ_Field is STM32F429x.UInt11; - subtype DOEPCTL1_USBAEP_Field is STM32F429x.Bit; - subtype DOEPCTL1_EONUM_DPID_Field is STM32F429x.Bit; - subtype DOEPCTL1_NAKSTS_Field is STM32F429x.Bit; - subtype DOEPCTL1_EPTYP_Field is STM32F429x.UInt2; - subtype DOEPCTL1_SNPM_Field is STM32F429x.Bit; - subtype DOEPCTL1_Stall_Field is STM32F429x.Bit; - subtype DOEPCTL1_CNAK_Field is STM32F429x.Bit; - subtype DOEPCTL1_SNAK_Field is STM32F429x.Bit; - subtype DOEPCTL1_SD0PID_SEVNFRM_Field is STM32F429x.Bit; - subtype DOEPCTL1_SODDFRM_Field is STM32F429x.Bit; - subtype DOEPCTL1_EPDIS_Field is STM32F429x.Bit; - subtype DOEPCTL1_EPENA_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_XFRCM_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_CHHM_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_STALLM_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_NAKM_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_ACKM_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_NYET_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_TXERRM_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_BBERRM_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_FRMORM_Field is STM32F429x.Bit; + subtype FS_HCINTMSK_DTERRM_Field is STM32F429x.Bit; - -- device endpoint-1 control register - type DOEPCTL_Register is record - -- MPSIZ - MPSIZ : DOEPCTL1_MPSIZ_Field := 16#0#; + -- OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + type FS_HCINTMSK_Register is record + -- Transfer completed mask + XFRCM : FS_HCINTMSK_XFRCM_Field := 16#0#; + -- Channel halted mask + CHHM : FS_HCINTMSK_CHHM_Field := 16#0#; -- unspecified - Reserved_11_14 : STM32F429x.UInt4 := 16#0#; - -- USBAEP - USBAEP : DOEPCTL1_USBAEP_Field := 16#0#; - -- EONUM/DPID - EONUM_DPID : DOEPCTL1_EONUM_DPID_Field := 16#0#; - -- NAKSTS - NAKSTS : DOEPCTL1_NAKSTS_Field := 16#0#; - -- EPTYP - EPTYP : DOEPCTL1_EPTYP_Field := 16#0#; - -- SNPM - SNPM : DOEPCTL1_SNPM_Field := 16#0#; - -- Stall - Stall : DOEPCTL1_Stall_Field := 16#0#; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- STALL response received interrupt mask + STALLM : FS_HCINTMSK_STALLM_Field := 16#0#; + -- NAK response received interrupt mask + NAKM : FS_HCINTMSK_NAKM_Field := 16#0#; + -- ACK response received/transmitted interrupt mask + ACKM : FS_HCINTMSK_ACKM_Field := 16#0#; + -- response received interrupt mask + NYET : FS_HCINTMSK_NYET_Field := 16#0#; + -- Transaction error mask + TXERRM : FS_HCINTMSK_TXERRM_Field := 16#0#; + -- Babble error mask + BBERRM : FS_HCINTMSK_BBERRM_Field := 16#0#; + -- Frame overrun mask + FRMORM : FS_HCINTMSK_FRMORM_Field := 16#0#; + -- Data toggle error mask + DTERRM : FS_HCINTMSK_DTERRM_Field := 16#0#; -- unspecified - Reserved_22_25 : STM32F429x.UInt4 := 16#0#; - -- CNAK - CNAK : DOEPCTL1_CNAK_Field := 16#0#; - -- SNAK - SNAK : DOEPCTL1_SNAK_Field := 16#0#; - -- SD0PID/SEVNFRM - SD0PID_SEVNFRM : DOEPCTL1_SD0PID_SEVNFRM_Field := 16#0#; - -- SODDFRM - SODDFRM : DOEPCTL1_SODDFRM_Field := 16#0#; - -- EPDIS - EPDIS : DOEPCTL1_EPDIS_Field := 16#0#; - -- EPENA - EPENA : DOEPCTL1_EPENA_Field := 16#0#; + Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPCTL_Register use record - MPSIZ at 0 range 0 .. 10; - Reserved_11_14 at 0 range 11 .. 14; - USBAEP at 0 range 15 .. 15; - EONUM_DPID at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - SNPM at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - Reserved_22_25 at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - SD0PID_SEVNFRM at 0 range 28 .. 28; - SODDFRM at 0 range 29 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for FS_HCINTMSK_Register use record + XFRCM at 0 range 0 .. 0; + CHHM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STALLM at 0 range 3 .. 3; + NAKM at 0 range 4 .. 4; + ACKM at 0 range 5 .. 5; + NYET at 0 range 6 .. 6; + TXERRM at 0 range 7 .. 7; + BBERRM at 0 range 8 .. 8; + FRMORM at 0 range 9 .. 9; + DTERRM at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------- - -- DOEPTSIZ_Register -- - ----------------------- + subtype FS_HCTSIZ_XFRSIZ_Field is STM32F429x.UInt19; + subtype FS_HCTSIZ_PKTCNT_Field is STM32F429x.UInt10; + subtype FS_HCTSIZ_DPID_Field is STM32F429x.UInt2; - subtype DOEPTSIZ1_XFRSIZ_Field is STM32F429x.UInt19; - subtype DOEPTSIZ1_PKTCNT_Field is STM32F429x.UInt10; - subtype DOEPTSIZ1_RXDPID_STUPCNT_Field is STM32F429x.UInt2; - - -- device OUT endpoint-1 transfer size register - type DOEPTSIZ_Register is record + -- OTG_FS host channel-0 transfer size register + type FS_HCTSIZ_Register is record -- Transfer size - XFRSIZ : DOEPTSIZ1_XFRSIZ_Field := 16#0#; + XFRSIZ : FS_HCTSIZ_XFRSIZ_Field := 16#0#; -- Packet count - PKTCNT : DOEPTSIZ1_PKTCNT_Field := 16#0#; - -- Received data PID/SETUP packet count - RXDPID_STUPCNT : DOEPTSIZ1_RXDPID_STUPCNT_Field := 16#0#; + PKTCNT : FS_HCTSIZ_PKTCNT_Field := 16#0#; + -- Data PID + DPID : FS_HCTSIZ_DPID_Field := 16#0#; -- unspecified Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for DOEPTSIZ_Register use record + for FS_HCTSIZ_Register use record XFRSIZ at 0 range 0 .. 18; PKTCNT at 0 range 19 .. 28; - RXDPID_STUPCNT at 0 range 29 .. 30; + DPID at 0 range 29 .. 30; Reserved_31_31 at 0 range 31 .. 31; end record; - ------------------------- - -- FS_PCGCCTL_Register -- - ------------------------- - subtype FS_PCGCCTL_STPPCLK_Field is STM32F429x.Bit; subtype FS_PCGCCTL_GATEHCLK_Field is STM32F429x.Bit; subtype FS_PCGCCTL_PHYSUSP_Field is STM32F429x.Bit; @@ -1982,7 +1855,7 @@ package STM32F429x.USB_OTG_FS is -- unspecified Reserved_5_31 : STM32F429x.UInt27 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for FS_PCGCCTL_Register use record STPPCLK at 0 range 0 .. 0; @@ -1997,335 +1870,447 @@ package STM32F429x.USB_OTG_FS is ----------------- -- USB on the go full speed - type OTG_FS_GLOBAL_Peripheral is record + type OTG_FS_DEVICE_Peripheral is record + -- OTG_FS device configuration register (OTG_FS_DCFG) + FS_DCFG : aliased FS_DCFG_Register; + pragma Volatile_Full_Access (FS_DCFG); + -- OTG_FS device control register (OTG_FS_DCTL) + FS_DCTL : aliased FS_DCTL_Register; + pragma Volatile_Full_Access (FS_DCTL); + -- OTG_FS device status register (OTG_FS_DSTS) + FS_DSTS : aliased FS_DSTS_Register; + pragma Volatile_Full_Access (FS_DSTS); + -- OTG_FS device IN endpoint common interrupt mask register + -- (OTG_FS_DIEPMSK) + FS_DIEPMSK : aliased FS_DIEPMSK_Register; + pragma Volatile_Full_Access (FS_DIEPMSK); + -- OTG_FS device OUT endpoint common interrupt mask register + -- (OTG_FS_DOEPMSK) + FS_DOEPMSK : aliased FS_DOEPMSK_Register; + pragma Volatile_Full_Access (FS_DOEPMSK); + -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + FS_DAINT : aliased FS_DAINT_Register; + pragma Volatile_Full_Access (FS_DAINT); + -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + FS_DAINTMSK : aliased FS_DAINTMSK_Register; + pragma Volatile_Full_Access (FS_DAINTMSK); + -- OTG_FS device VBUS discharge time register + DVBUSDIS : aliased DVBUSDIS_Register; + pragma Volatile_Full_Access (DVBUSDIS); + -- OTG_FS device VBUS pulsing time register + DVBUSPULSE : aliased DVBUSPULSE_Register; + pragma Volatile_Full_Access (DVBUSPULSE); + -- OTG_FS device IN endpoint FIFO empty interrupt mask register + DIEPEMPMSK : aliased DIEPEMPMSK_Register; + pragma Volatile_Full_Access (DIEPEMPMSK); + -- OTG_FS device control IN endpoint 0 control register + -- (OTG_FS_DIEPCTL0) + FS_DIEPCTL0 : aliased FS_DIEPCTL0_Register; + pragma Volatile_Full_Access (FS_DIEPCTL0); + -- device endpoint-x interrupt register + DIEPINT0 : aliased DIEPINT_Register; + pragma Volatile_Full_Access (DIEPINT0); + -- device endpoint-0 transfer size register + DIEPTSIZ0 : aliased DIEPTSIZ0_Register; + pragma Volatile_Full_Access (DIEPTSIZ0); + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS0 : aliased DTXFSTS_Register; + pragma Volatile_Full_Access (DTXFSTS0); + -- OTG device endpoint-1 control register + DIEPCTL1 : aliased DIEPCTL1_Register; + pragma Volatile_Full_Access (DIEPCTL1); + -- device endpoint-1 interrupt register + DIEPINT1 : aliased DIEPINT_Register; + pragma Volatile_Full_Access (DIEPINT1); + -- device endpoint-1 transfer size register + DIEPTSIZ1 : aliased DIEPTSIZ_Register; + pragma Volatile_Full_Access (DIEPTSIZ1); + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS1 : aliased DTXFSTS_Register; + pragma Volatile_Full_Access (DTXFSTS1); + -- OTG device endpoint-2 control register + DIEPCTL2 : aliased DIEPCTL_Register; + pragma Volatile_Full_Access (DIEPCTL2); + -- device endpoint-2 interrupt register + DIEPINT2 : aliased DIEPINT_Register; + pragma Volatile_Full_Access (DIEPINT2); + -- device endpoint-2 transfer size register + DIEPTSIZ2 : aliased DIEPTSIZ_Register; + pragma Volatile_Full_Access (DIEPTSIZ2); + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS2 : aliased DTXFSTS_Register; + pragma Volatile_Full_Access (DTXFSTS2); + -- OTG device endpoint-3 control register + DIEPCTL3 : aliased DIEPCTL_Register; + pragma Volatile_Full_Access (DIEPCTL3); + -- device endpoint-3 interrupt register + DIEPINT3 : aliased DIEPINT_Register; + pragma Volatile_Full_Access (DIEPINT3); + -- device endpoint-3 transfer size register + DIEPTSIZ3 : aliased DIEPTSIZ_Register; + pragma Volatile_Full_Access (DIEPTSIZ3); + -- OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS3 : aliased DTXFSTS_Register; + pragma Volatile_Full_Access (DTXFSTS3); + -- device endpoint-0 control register + DOEPCTL0 : aliased DOEPCTL0_Register; + pragma Volatile_Full_Access (DOEPCTL0); + -- device endpoint-0 interrupt register + DOEPINT0 : aliased DOEPINT_Register; + pragma Volatile_Full_Access (DOEPINT0); + -- device OUT endpoint-0 transfer size register + DOEPTSIZ0 : aliased DOEPTSIZ0_Register; + pragma Volatile_Full_Access (DOEPTSIZ0); + -- device endpoint-1 control register + DOEPCTL1 : aliased DOEPCTL_Register; + pragma Volatile_Full_Access (DOEPCTL1); + -- device endpoint-1 interrupt register + DOEPINT1 : aliased DOEPINT_Register; + pragma Volatile_Full_Access (DOEPINT1); + -- device OUT endpoint-1 transfer size register + DOEPTSIZ1 : aliased DOEPTSIZ_Register; + pragma Volatile_Full_Access (DOEPTSIZ1); + -- device endpoint-2 control register + DOEPCTL2 : aliased DOEPCTL_Register; + pragma Volatile_Full_Access (DOEPCTL2); + -- device endpoint-2 interrupt register + DOEPINT2 : aliased DOEPINT_Register; + pragma Volatile_Full_Access (DOEPINT2); + -- device OUT endpoint-2 transfer size register + DOEPTSIZ2 : aliased DOEPTSIZ_Register; + pragma Volatile_Full_Access (DOEPTSIZ2); + -- device endpoint-3 control register + DOEPCTL3 : aliased DOEPCTL_Register; + pragma Volatile_Full_Access (DOEPCTL3); + -- device endpoint-3 interrupt register + DOEPINT3 : aliased DOEPINT_Register; + pragma Volatile_Full_Access (DOEPINT3); + -- device OUT endpoint-3 transfer size register + DOEPTSIZ3 : aliased DOEPTSIZ_Register; + pragma Volatile_Full_Access (DOEPTSIZ3); + end record + with Volatile; + + for OTG_FS_DEVICE_Peripheral use record + FS_DCFG at 16#0# range 0 .. 31; + FS_DCTL at 16#4# range 0 .. 31; + FS_DSTS at 16#8# range 0 .. 31; + FS_DIEPMSK at 16#10# range 0 .. 31; + FS_DOEPMSK at 16#14# range 0 .. 31; + FS_DAINT at 16#18# range 0 .. 31; + FS_DAINTMSK at 16#1C# range 0 .. 31; + DVBUSDIS at 16#28# range 0 .. 31; + DVBUSPULSE at 16#2C# range 0 .. 31; + DIEPEMPMSK at 16#34# range 0 .. 31; + FS_DIEPCTL0 at 16#100# range 0 .. 31; + DIEPINT0 at 16#108# range 0 .. 31; + DIEPTSIZ0 at 16#110# range 0 .. 31; + DTXFSTS0 at 16#118# range 0 .. 31; + DIEPCTL1 at 16#120# range 0 .. 31; + DIEPINT1 at 16#128# range 0 .. 31; + DIEPTSIZ1 at 16#130# range 0 .. 31; + DTXFSTS1 at 16#138# range 0 .. 31; + DIEPCTL2 at 16#140# range 0 .. 31; + DIEPINT2 at 16#148# range 0 .. 31; + DIEPTSIZ2 at 16#150# range 0 .. 31; + DTXFSTS2 at 16#158# range 0 .. 31; + DIEPCTL3 at 16#160# range 0 .. 31; + DIEPINT3 at 16#168# range 0 .. 31; + DIEPTSIZ3 at 16#170# range 0 .. 31; + DTXFSTS3 at 16#178# range 0 .. 31; + DOEPCTL0 at 16#300# range 0 .. 31; + DOEPINT0 at 16#308# range 0 .. 31; + DOEPTSIZ0 at 16#310# range 0 .. 31; + DOEPCTL1 at 16#320# range 0 .. 31; + DOEPINT1 at 16#328# range 0 .. 31; + DOEPTSIZ1 at 16#330# range 0 .. 31; + DOEPCTL2 at 16#340# range 0 .. 31; + DOEPINT2 at 16#348# range 0 .. 31; + DOEPTSIZ2 at 16#350# range 0 .. 31; + DOEPCTL3 at 16#360# range 0 .. 31; + DOEPINT3 at 16#368# range 0 .. 31; + DOEPTSIZ3 at 16#370# range 0 .. 31; + end record; + + -- USB on the go full speed + OTG_FS_DEVICE_Periph : aliased OTG_FS_DEVICE_Peripheral + with Import, Address => OTG_FS_DEVICE_Base; + + type OTG_FS_GLOBAL_Disc is + (Device, + Host); + + -- USB on the go full speed + type OTG_FS_GLOBAL_Peripheral + (Discriminent : OTG_FS_GLOBAL_Disc := Device) + is record -- OTG_FS control and status register (OTG_FS_GOTGCTL) - FS_GOTGCTL : FS_GOTGCTL_Register; + FS_GOTGCTL : aliased FS_GOTGCTL_Register; + pragma Volatile_Full_Access (FS_GOTGCTL); -- OTG_FS interrupt register (OTG_FS_GOTGINT) - FS_GOTGINT : FS_GOTGINT_Register; + FS_GOTGINT : aliased FS_GOTGINT_Register; + pragma Volatile_Full_Access (FS_GOTGINT); -- OTG_FS AHB configuration register (OTG_FS_GAHBCFG) - FS_GAHBCFG : FS_GAHBCFG_Register; + FS_GAHBCFG : aliased FS_GAHBCFG_Register; + pragma Volatile_Full_Access (FS_GAHBCFG); -- OTG_FS USB configuration register (OTG_FS_GUSBCFG) - FS_GUSBCFG : FS_GUSBCFG_Register; + FS_GUSBCFG : aliased FS_GUSBCFG_Register; + pragma Volatile_Full_Access (FS_GUSBCFG); -- OTG_FS reset register (OTG_FS_GRSTCTL) - FS_GRSTCTL : FS_GRSTCTL_Register; + FS_GRSTCTL : aliased FS_GRSTCTL_Register; + pragma Volatile_Full_Access (FS_GRSTCTL); -- OTG_FS core interrupt register (OTG_FS_GINTSTS) - FS_GINTSTS : FS_GINTSTS_Register; + FS_GINTSTS : aliased FS_GINTSTS_Register; + pragma Volatile_Full_Access (FS_GINTSTS); -- OTG_FS interrupt mask register (OTG_FS_GINTMSK) - FS_GINTMSK : FS_GINTMSK_Register; - -- OTG_FS Receive status debug read(Device mode) - FS_GRXSTSR : FS_GRXSTSR_Device_Register; + FS_GINTMSK : aliased FS_GINTMSK_Register; + pragma Volatile_Full_Access (FS_GINTMSK); -- OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) - FS_GRXFSIZ : FS_GRXFSIZ_Register; - -- OTG_FS non-periodic transmit FIFO size register (Device mode) - FS_GNPTXFSIZ : FS_GNPTXFSIZ_Device_Register; + FS_GRXFSIZ : aliased FS_GRXFSIZ_Register; + pragma Volatile_Full_Access (FS_GRXFSIZ); -- OTG_FS non-periodic transmit FIFO/queue status register -- (OTG_FS_GNPTXSTS) - FS_GNPTXSTS : FS_GNPTXSTS_Register; + FS_GNPTXSTS : aliased FS_GNPTXSTS_Register; + pragma Volatile_Full_Access (FS_GNPTXSTS); -- OTG_FS general core configuration register (OTG_FS_GCCFG) - FS_GCCFG : FS_GCCFG_Register; + FS_GCCFG : aliased FS_GCCFG_Register; + pragma Volatile_Full_Access (FS_GCCFG); -- core ID register - FS_CID : STM32F429x.Word; + FS_CID : aliased STM32F429x.UInt32; -- OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) - FS_HPTXFSIZ : FS_HPTXFSIZ_Register; + FS_HPTXFSIZ : aliased FS_HPTXFSIZ_Register; + pragma Volatile_Full_Access (FS_HPTXFSIZ); -- OTG_FS device IN endpoint transmit FIFO size register -- (OTG_FS_DIEPTXF2) - FS_DIEPTXF1 : FS_DIEPTXF_Register; + FS_DIEPTXF1 : aliased FS_DIEPTXF_Register; + pragma Volatile_Full_Access (FS_DIEPTXF1); -- OTG_FS device IN endpoint transmit FIFO size register -- (OTG_FS_DIEPTXF3) - FS_DIEPTXF2 : FS_DIEPTXF_Register; + FS_DIEPTXF2 : aliased FS_DIEPTXF_Register; + pragma Volatile_Full_Access (FS_DIEPTXF2); -- OTG_FS device IN endpoint transmit FIFO size register -- (OTG_FS_DIEPTXF4) - FS_DIEPTXF3 : FS_DIEPTXF_Register; + FS_DIEPTXF3 : aliased FS_DIEPTXF_Register; + pragma Volatile_Full_Access (FS_DIEPTXF3); + case Discriminent is + when Device => + -- OTG_FS Receive status debug read(Device mode) + FS_GRXSTSR_Device : aliased FS_GRXSTSR_Device_Register; + pragma Volatile_Full_Access (FS_GRXSTSR_Device); + -- OTG_FS non-periodic transmit FIFO size register (Device mode) + FS_GNPTXFSIZ_Device : aliased FS_GNPTXFSIZ_Device_Register; + pragma Volatile_Full_Access (FS_GNPTXFSIZ_Device); + when Host => + -- OTG_FS Receive status debug read(Host mode) + FS_GRXSTSR_Host : aliased FS_GRXSTSR_Host_Register; + pragma Volatile_Full_Access (FS_GRXSTSR_Host); + -- OTG_FS non-periodic transmit FIFO size register (Host mode) + FS_GNPTXFSIZ_Host : aliased FS_GNPTXFSIZ_Host_Register; + pragma Volatile_Full_Access (FS_GNPTXFSIZ_Host); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for OTG_FS_GLOBAL_Peripheral use record - FS_GOTGCTL at 0 range 0 .. 31; - FS_GOTGINT at 4 range 0 .. 31; - FS_GAHBCFG at 8 range 0 .. 31; - FS_GUSBCFG at 12 range 0 .. 31; - FS_GRSTCTL at 16 range 0 .. 31; - FS_GINTSTS at 20 range 0 .. 31; - FS_GINTMSK at 24 range 0 .. 31; - FS_GRXSTSR at 28 range 0 .. 31; - FS_GRXFSIZ at 36 range 0 .. 31; - FS_GNPTXFSIZ at 40 range 0 .. 31; - FS_GNPTXSTS at 44 range 0 .. 31; - FS_GCCFG at 56 range 0 .. 31; - FS_CID at 60 range 0 .. 31; - FS_HPTXFSIZ at 256 range 0 .. 31; - FS_DIEPTXF1 at 260 range 0 .. 31; - FS_DIEPTXF2 at 264 range 0 .. 31; - FS_DIEPTXF3 at 268 range 0 .. 31; + FS_GOTGCTL at 16#0# range 0 .. 31; + FS_GOTGINT at 16#4# range 0 .. 31; + FS_GAHBCFG at 16#8# range 0 .. 31; + FS_GUSBCFG at 16#C# range 0 .. 31; + FS_GRSTCTL at 16#10# range 0 .. 31; + FS_GINTSTS at 16#14# range 0 .. 31; + FS_GINTMSK at 16#18# range 0 .. 31; + FS_GRXFSIZ at 16#24# range 0 .. 31; + FS_GNPTXSTS at 16#2C# range 0 .. 31; + FS_GCCFG at 16#38# range 0 .. 31; + FS_CID at 16#3C# range 0 .. 31; + FS_HPTXFSIZ at 16#100# range 0 .. 31; + FS_DIEPTXF1 at 16#104# range 0 .. 31; + FS_DIEPTXF2 at 16#108# range 0 .. 31; + FS_DIEPTXF3 at 16#10C# range 0 .. 31; + FS_GRXSTSR_Device at 16#1C# range 0 .. 31; + FS_GNPTXFSIZ_Device at 16#28# range 0 .. 31; + FS_GRXSTSR_Host at 16#1C# range 0 .. 31; + FS_GNPTXFSIZ_Host at 16#28# range 0 .. 31; end record; -- USB on the go full speed OTG_FS_GLOBAL_Periph : aliased OTG_FS_GLOBAL_Peripheral - with Import, Address => System'To_Address (16#50000000#); + with Import, Address => OTG_FS_GLOBAL_Base; -- USB on the go full speed type OTG_FS_HOST_Peripheral is record -- OTG_FS host configuration register (OTG_FS_HCFG) - FS_HCFG : FS_HCFG_Register; + FS_HCFG : aliased FS_HCFG_Register; + pragma Volatile_Full_Access (FS_HCFG); -- OTG_FS Host frame interval register - HFIR : HFIR_Register; + HFIR : aliased HFIR_Register; + pragma Volatile_Full_Access (HFIR); -- OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) - FS_HFNUM : FS_HFNUM_Register; + FS_HFNUM : aliased FS_HFNUM_Register; + pragma Volatile_Full_Access (FS_HFNUM); -- OTG_FS_Host periodic transmit FIFO/queue status register -- (OTG_FS_HPTXSTS) - FS_HPTXSTS : FS_HPTXSTS_Register; + FS_HPTXSTS : aliased FS_HPTXSTS_Register; + pragma Volatile_Full_Access (FS_HPTXSTS); -- OTG_FS Host all channels interrupt register - HAINT : HAINT_Register; + HAINT : aliased HAINT_Register; + pragma Volatile_Full_Access (HAINT); -- OTG_FS host all channels interrupt mask register - HAINTMSK : HAINTMSK_Register; + HAINTMSK : aliased HAINTMSK_Register; + pragma Volatile_Full_Access (HAINTMSK); -- OTG_FS host port control and status register (OTG_FS_HPRT) - FS_HPRT : FS_HPRT_Register; + FS_HPRT : aliased FS_HPRT_Register; + pragma Volatile_Full_Access (FS_HPRT); -- OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) - FS_HCCHAR0 : FS_HCCHAR_Register; + FS_HCCHAR0 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR0); -- OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) - FS_HCINT0 : FS_HCINT_Register; + FS_HCINT0 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT0); -- OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) - FS_HCINTMSK0 : FS_HCINTMSK_Register; + FS_HCINTMSK0 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK0); -- OTG_FS host channel-0 transfer size register - FS_HCTSIZ0 : FS_HCTSIZ_Register; + FS_HCTSIZ0 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ0); -- OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) - FS_HCCHAR1 : FS_HCCHAR_Register; + FS_HCCHAR1 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR1); -- OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) - FS_HCINT1 : FS_HCINT_Register; + FS_HCINT1 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT1); -- OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) - FS_HCINTMSK1 : FS_HCINTMSK_Register; + FS_HCINTMSK1 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK1); -- OTG_FS host channel-1 transfer size register - FS_HCTSIZ1 : FS_HCTSIZ_Register; + FS_HCTSIZ1 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ1); -- OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) - FS_HCCHAR2 : FS_HCCHAR_Register; + FS_HCCHAR2 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR2); -- OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) - FS_HCINT2 : FS_HCINT_Register; + FS_HCINT2 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT2); -- OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) - FS_HCINTMSK2 : FS_HCINTMSK_Register; + FS_HCINTMSK2 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK2); -- OTG_FS host channel-2 transfer size register - FS_HCTSIZ2 : FS_HCTSIZ_Register; + FS_HCTSIZ2 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ2); -- OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) - FS_HCCHAR3 : FS_HCCHAR_Register; + FS_HCCHAR3 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR3); -- OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) - FS_HCINT3 : FS_HCINT_Register; + FS_HCINT3 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT3); -- OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) - FS_HCINTMSK3 : FS_HCINTMSK_Register; + FS_HCINTMSK3 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK3); -- OTG_FS host channel-3 transfer size register - FS_HCTSIZ3 : FS_HCTSIZ_Register; + FS_HCTSIZ3 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ3); -- OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) - FS_HCCHAR4 : FS_HCCHAR_Register; + FS_HCCHAR4 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR4); -- OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) - FS_HCINT4 : FS_HCINT_Register; + FS_HCINT4 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT4); -- OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) - FS_HCINTMSK4 : FS_HCINTMSK_Register; + FS_HCINTMSK4 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK4); -- OTG_FS host channel-x transfer size register - FS_HCTSIZ4 : FS_HCTSIZ_Register; + FS_HCTSIZ4 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ4); -- OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) - FS_HCCHAR5 : FS_HCCHAR_Register; + FS_HCCHAR5 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR5); -- OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) - FS_HCINT5 : FS_HCINT_Register; + FS_HCINT5 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT5); -- OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) - FS_HCINTMSK5 : FS_HCINTMSK_Register; + FS_HCINTMSK5 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK5); -- OTG_FS host channel-5 transfer size register - FS_HCTSIZ5 : FS_HCTSIZ_Register; + FS_HCTSIZ5 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ5); -- OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) - FS_HCCHAR6 : FS_HCCHAR_Register; + FS_HCCHAR6 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR6); -- OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) - FS_HCINT6 : FS_HCINT_Register; + FS_HCINT6 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT6); -- OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) - FS_HCINTMSK6 : FS_HCINTMSK_Register; + FS_HCINTMSK6 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK6); -- OTG_FS host channel-6 transfer size register - FS_HCTSIZ6 : FS_HCTSIZ_Register; + FS_HCTSIZ6 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ6); -- OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) - FS_HCCHAR7 : FS_HCCHAR_Register; + FS_HCCHAR7 : aliased FS_HCCHAR_Register; + pragma Volatile_Full_Access (FS_HCCHAR7); -- OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) - FS_HCINT7 : FS_HCINT_Register; + FS_HCINT7 : aliased FS_HCINT_Register; + pragma Volatile_Full_Access (FS_HCINT7); -- OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) - FS_HCINTMSK7 : FS_HCINTMSK_Register; + FS_HCINTMSK7 : aliased FS_HCINTMSK_Register; + pragma Volatile_Full_Access (FS_HCINTMSK7); -- OTG_FS host channel-7 transfer size register - FS_HCTSIZ7 : FS_HCTSIZ_Register; + FS_HCTSIZ7 : aliased FS_HCTSIZ_Register; + pragma Volatile_Full_Access (FS_HCTSIZ7); end record with Volatile; for OTG_FS_HOST_Peripheral use record - FS_HCFG at 0 range 0 .. 31; - HFIR at 4 range 0 .. 31; - FS_HFNUM at 8 range 0 .. 31; - FS_HPTXSTS at 16 range 0 .. 31; - HAINT at 20 range 0 .. 31; - HAINTMSK at 24 range 0 .. 31; - FS_HPRT at 64 range 0 .. 31; - FS_HCCHAR0 at 256 range 0 .. 31; - FS_HCINT0 at 264 range 0 .. 31; - FS_HCINTMSK0 at 268 range 0 .. 31; - FS_HCTSIZ0 at 272 range 0 .. 31; - FS_HCCHAR1 at 288 range 0 .. 31; - FS_HCINT1 at 296 range 0 .. 31; - FS_HCINTMSK1 at 300 range 0 .. 31; - FS_HCTSIZ1 at 304 range 0 .. 31; - FS_HCCHAR2 at 320 range 0 .. 31; - FS_HCINT2 at 328 range 0 .. 31; - FS_HCINTMSK2 at 332 range 0 .. 31; - FS_HCTSIZ2 at 336 range 0 .. 31; - FS_HCCHAR3 at 352 range 0 .. 31; - FS_HCINT3 at 360 range 0 .. 31; - FS_HCINTMSK3 at 364 range 0 .. 31; - FS_HCTSIZ3 at 368 range 0 .. 31; - FS_HCCHAR4 at 384 range 0 .. 31; - FS_HCINT4 at 392 range 0 .. 31; - FS_HCINTMSK4 at 396 range 0 .. 31; - FS_HCTSIZ4 at 400 range 0 .. 31; - FS_HCCHAR5 at 416 range 0 .. 31; - FS_HCINT5 at 424 range 0 .. 31; - FS_HCINTMSK5 at 428 range 0 .. 31; - FS_HCTSIZ5 at 432 range 0 .. 31; - FS_HCCHAR6 at 448 range 0 .. 31; - FS_HCINT6 at 456 range 0 .. 31; - FS_HCINTMSK6 at 460 range 0 .. 31; - FS_HCTSIZ6 at 464 range 0 .. 31; - FS_HCCHAR7 at 480 range 0 .. 31; - FS_HCINT7 at 488 range 0 .. 31; - FS_HCINTMSK7 at 492 range 0 .. 31; - FS_HCTSIZ7 at 496 range 0 .. 31; + FS_HCFG at 16#0# range 0 .. 31; + HFIR at 16#4# range 0 .. 31; + FS_HFNUM at 16#8# range 0 .. 31; + FS_HPTXSTS at 16#10# range 0 .. 31; + HAINT at 16#14# range 0 .. 31; + HAINTMSK at 16#18# range 0 .. 31; + FS_HPRT at 16#40# range 0 .. 31; + FS_HCCHAR0 at 16#100# range 0 .. 31; + FS_HCINT0 at 16#108# range 0 .. 31; + FS_HCINTMSK0 at 16#10C# range 0 .. 31; + FS_HCTSIZ0 at 16#110# range 0 .. 31; + FS_HCCHAR1 at 16#120# range 0 .. 31; + FS_HCINT1 at 16#128# range 0 .. 31; + FS_HCINTMSK1 at 16#12C# range 0 .. 31; + FS_HCTSIZ1 at 16#130# range 0 .. 31; + FS_HCCHAR2 at 16#140# range 0 .. 31; + FS_HCINT2 at 16#148# range 0 .. 31; + FS_HCINTMSK2 at 16#14C# range 0 .. 31; + FS_HCTSIZ2 at 16#150# range 0 .. 31; + FS_HCCHAR3 at 16#160# range 0 .. 31; + FS_HCINT3 at 16#168# range 0 .. 31; + FS_HCINTMSK3 at 16#16C# range 0 .. 31; + FS_HCTSIZ3 at 16#170# range 0 .. 31; + FS_HCCHAR4 at 16#180# range 0 .. 31; + FS_HCINT4 at 16#188# range 0 .. 31; + FS_HCINTMSK4 at 16#18C# range 0 .. 31; + FS_HCTSIZ4 at 16#190# range 0 .. 31; + FS_HCCHAR5 at 16#1A0# range 0 .. 31; + FS_HCINT5 at 16#1A8# range 0 .. 31; + FS_HCINTMSK5 at 16#1AC# range 0 .. 31; + FS_HCTSIZ5 at 16#1B0# range 0 .. 31; + FS_HCCHAR6 at 16#1C0# range 0 .. 31; + FS_HCINT6 at 16#1C8# range 0 .. 31; + FS_HCINTMSK6 at 16#1CC# range 0 .. 31; + FS_HCTSIZ6 at 16#1D0# range 0 .. 31; + FS_HCCHAR7 at 16#1E0# range 0 .. 31; + FS_HCINT7 at 16#1E8# range 0 .. 31; + FS_HCINTMSK7 at 16#1EC# range 0 .. 31; + FS_HCTSIZ7 at 16#1F0# range 0 .. 31; end record; -- USB on the go full speed OTG_FS_HOST_Periph : aliased OTG_FS_HOST_Peripheral - with Import, Address => System'To_Address (16#50000400#); - - -- USB on the go full speed - type OTG_FS_DEVICE_Peripheral is record - -- OTG_FS device configuration register (OTG_FS_DCFG) - FS_DCFG : FS_DCFG_Register; - -- OTG_FS device control register (OTG_FS_DCTL) - FS_DCTL : FS_DCTL_Register; - -- OTG_FS device status register (OTG_FS_DSTS) - FS_DSTS : FS_DSTS_Register; - -- OTG_FS device IN endpoint common interrupt mask register - -- (OTG_FS_DIEPMSK) - FS_DIEPMSK : FS_DIEPMSK_Register; - -- OTG_FS device OUT endpoint common interrupt mask register - -- (OTG_FS_DOEPMSK) - FS_DOEPMSK : FS_DOEPMSK_Register; - -- OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) - FS_DAINT : FS_DAINT_Register; - -- OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) - FS_DAINTMSK : FS_DAINTMSK_Register; - -- OTG_FS device VBUS discharge time register - DVBUSDIS : DVBUSDIS_Register; - -- OTG_FS device VBUS pulsing time register - DVBUSPULSE : DVBUSPULSE_Register; - -- OTG_FS device IN endpoint FIFO empty interrupt mask register - DIEPEMPMSK : DIEPEMPMSK_Register; - -- OTG_FS device control IN endpoint 0 control register - -- (OTG_FS_DIEPCTL0) - FS_DIEPCTL0 : FS_DIEPCTL0_Register; - -- device endpoint-x interrupt register - DIEPINT0 : DIEPINT_Register; - -- device endpoint-0 transfer size register - DIEPTSIZ0 : DIEPTSIZ0_Register; - -- OTG_FS device IN endpoint transmit FIFO status register - DTXFSTS0 : DTXFSTS_Register; - -- OTG device endpoint-1 control register - DIEPCTL1 : DIEPCTL_Register; - -- device endpoint-1 interrupt register - DIEPINT1 : DIEPINT_Register; - -- device endpoint-1 transfer size register - DIEPTSIZ1 : DIEPTSIZ_Register; - -- OTG_FS device IN endpoint transmit FIFO status register - DTXFSTS1 : DTXFSTS_Register; - -- OTG device endpoint-2 control register - DIEPCTL2 : DIEPCTL_Register; - -- device endpoint-2 interrupt register - DIEPINT2 : DIEPINT_Register; - -- device endpoint-2 transfer size register - DIEPTSIZ2 : DIEPTSIZ_Register; - -- OTG_FS device IN endpoint transmit FIFO status register - DTXFSTS2 : DTXFSTS_Register; - -- OTG device endpoint-3 control register - DIEPCTL3 : DIEPCTL_Register; - -- device endpoint-3 interrupt register - DIEPINT3 : DIEPINT_Register; - -- device endpoint-3 transfer size register - DIEPTSIZ3 : DIEPTSIZ_Register; - -- OTG_FS device IN endpoint transmit FIFO status register - DTXFSTS3 : DTXFSTS_Register; - -- device endpoint-0 control register - DOEPCTL0 : DOEPCTL0_Register; - -- device endpoint-0 interrupt register - DOEPINT0 : DOEPINT_Register; - -- device OUT endpoint-0 transfer size register - DOEPTSIZ0 : DOEPTSIZ0_Register; - -- device endpoint-1 control register - DOEPCTL1 : DOEPCTL_Register; - -- device endpoint-1 interrupt register - DOEPINT1 : DOEPINT_Register; - -- device OUT endpoint-1 transfer size register - DOEPTSIZ1 : DOEPTSIZ_Register; - -- device endpoint-2 control register - DOEPCTL2 : DOEPCTL_Register; - -- device endpoint-2 interrupt register - DOEPINT2 : DOEPINT_Register; - -- device OUT endpoint-2 transfer size register - DOEPTSIZ2 : DOEPTSIZ_Register; - -- device endpoint-3 control register - DOEPCTL3 : DOEPCTL_Register; - -- device endpoint-3 interrupt register - DOEPINT3 : DOEPINT_Register; - -- device OUT endpoint-3 transfer size register - DOEPTSIZ3 : DOEPTSIZ_Register; - end record - with Volatile; - - for OTG_FS_DEVICE_Peripheral use record - FS_DCFG at 0 range 0 .. 31; - FS_DCTL at 4 range 0 .. 31; - FS_DSTS at 8 range 0 .. 31; - FS_DIEPMSK at 16 range 0 .. 31; - FS_DOEPMSK at 20 range 0 .. 31; - FS_DAINT at 24 range 0 .. 31; - FS_DAINTMSK at 28 range 0 .. 31; - DVBUSDIS at 40 range 0 .. 31; - DVBUSPULSE at 44 range 0 .. 31; - DIEPEMPMSK at 52 range 0 .. 31; - FS_DIEPCTL0 at 256 range 0 .. 31; - DIEPINT0 at 264 range 0 .. 31; - DIEPTSIZ0 at 272 range 0 .. 31; - DTXFSTS0 at 280 range 0 .. 31; - DIEPCTL1 at 288 range 0 .. 31; - DIEPINT1 at 296 range 0 .. 31; - DIEPTSIZ1 at 304 range 0 .. 31; - DTXFSTS1 at 312 range 0 .. 31; - DIEPCTL2 at 320 range 0 .. 31; - DIEPINT2 at 328 range 0 .. 31; - DIEPTSIZ2 at 336 range 0 .. 31; - DTXFSTS2 at 344 range 0 .. 31; - DIEPCTL3 at 352 range 0 .. 31; - DIEPINT3 at 360 range 0 .. 31; - DIEPTSIZ3 at 368 range 0 .. 31; - DTXFSTS3 at 376 range 0 .. 31; - DOEPCTL0 at 768 range 0 .. 31; - DOEPINT0 at 776 range 0 .. 31; - DOEPTSIZ0 at 784 range 0 .. 31; - DOEPCTL1 at 800 range 0 .. 31; - DOEPINT1 at 808 range 0 .. 31; - DOEPTSIZ1 at 816 range 0 .. 31; - DOEPCTL2 at 832 range 0 .. 31; - DOEPINT2 at 840 range 0 .. 31; - DOEPTSIZ2 at 848 range 0 .. 31; - DOEPCTL3 at 864 range 0 .. 31; - DOEPINT3 at 872 range 0 .. 31; - DOEPTSIZ3 at 880 range 0 .. 31; - end record; - - -- USB on the go full speed - OTG_FS_DEVICE_Periph : aliased OTG_FS_DEVICE_Peripheral - with Import, Address => System'To_Address (16#50000800#); + with Import, Address => OTG_FS_HOST_Base; -- USB on the go full speed type OTG_FS_PWRCLK_Peripheral is record -- OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) - FS_PCGCCTL : FS_PCGCCTL_Register; + FS_PCGCCTL : aliased FS_PCGCCTL_Register; + pragma Volatile_Full_Access (FS_PCGCCTL); end record with Volatile; @@ -2335,6 +2320,6 @@ package STM32F429x.USB_OTG_FS is -- USB on the go full speed OTG_FS_PWRCLK_Periph : aliased OTG_FS_PWRCLK_Peripheral - with Import, Address => System'To_Address (16#50000E00#); + with Import, Address => OTG_FS_PWRCLK_Base; end STM32F429x.USB_OTG_FS; diff --git a/stm32f429i/stm32f429x/stm32f429x-usb_otg_hs.ads b/stm32f429i/stm32f429x/stm32f429x-usb_otg_hs.ads index 28d509b..bfa6a39 100644 --- a/stm32f429i/stm32f429x/stm32f429x-usb_otg_hs.ads +++ b/stm32f429i/stm32f429x/stm32f429x-usb_otg_hs.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,2365 +14,2141 @@ package STM32F429x.USB_OTG_HS is -- Registers -- --------------- - ----------------------------- - -- OTG_HS_GOTGCTL_Register -- - ----------------------------- - - subtype OTG_HS_GOTGCTL_SRQSCS_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_SRQ_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_HNGSCS_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_HNPRQ_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_HSHNPEN_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_DHNPEN_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_CIDSTS_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_DBCT_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_ASVLD_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGCTL_BSVLD_Field is STM32F429x.Bit; + subtype OTG_HS_DCFG_DSPD_Field is STM32F429x.UInt2; + subtype OTG_HS_DCFG_NZLSOHSK_Field is STM32F429x.Bit; + subtype OTG_HS_DCFG_DAD_Field is STM32F429x.UInt7; + subtype OTG_HS_DCFG_PFIVL_Field is STM32F429x.UInt2; + subtype OTG_HS_DCFG_PERSCHIVL_Field is STM32F429x.UInt2; - -- OTG_HS control and status register - type OTG_HS_GOTGCTL_Register is record - -- Session request success - SRQSCS : OTG_HS_GOTGCTL_SRQSCS_Field := 16#0#; - -- Session request - SRQ : OTG_HS_GOTGCTL_SRQ_Field := 16#0#; + -- OTG_HS device configuration register + type OTG_HS_DCFG_Register is record + -- Device speed + DSPD : OTG_HS_DCFG_DSPD_Field := 16#0#; + -- Nonzero-length status OUT handshake + NZLSOHSK : OTG_HS_DCFG_NZLSOHSK_Field := 16#0#; -- unspecified - Reserved_2_7 : STM32F429x.UInt6 := 16#0#; - -- Host negotiation success - HNGSCS : OTG_HS_GOTGCTL_HNGSCS_Field := 16#0#; - -- HNP request - HNPRQ : OTG_HS_GOTGCTL_HNPRQ_Field := 16#0#; - -- Host set HNP enable - HSHNPEN : OTG_HS_GOTGCTL_HSHNPEN_Field := 16#0#; - -- Device HNP enabled - DHNPEN : OTG_HS_GOTGCTL_DHNPEN_Field := 16#1#; + Reserved_3_3 : STM32F429x.Bit := 16#0#; + -- Device address + DAD : OTG_HS_DCFG_DAD_Field := 16#0#; + -- Periodic (micro)frame interval + PFIVL : OTG_HS_DCFG_PFIVL_Field := 16#0#; -- unspecified - Reserved_12_15 : STM32F429x.UInt4 := 16#0#; - -- Connector ID status - CIDSTS : OTG_HS_GOTGCTL_CIDSTS_Field := 16#0#; - -- Long/short debounce time - DBCT : OTG_HS_GOTGCTL_DBCT_Field := 16#0#; - -- A-session valid - ASVLD : OTG_HS_GOTGCTL_ASVLD_Field := 16#0#; - -- B-session valid - BSVLD : OTG_HS_GOTGCTL_BSVLD_Field := 16#0#; + Reserved_13_23 : STM32F429x.UInt11 := 16#100#; + -- Periodic scheduling interval + PERSCHIVL : OTG_HS_DCFG_PERSCHIVL_Field := 16#2#; -- unspecified - Reserved_20_31 : STM32F429x.UInt12 := 16#0#; + Reserved_26_31 : STM32F429x.UInt6 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GOTGCTL_Register use record - SRQSCS at 0 range 0 .. 0; - SRQ at 0 range 1 .. 1; - Reserved_2_7 at 0 range 2 .. 7; - HNGSCS at 0 range 8 .. 8; - HNPRQ at 0 range 9 .. 9; - HSHNPEN at 0 range 10 .. 10; - DHNPEN at 0 range 11 .. 11; - Reserved_12_15 at 0 range 12 .. 15; - CIDSTS at 0 range 16 .. 16; - DBCT at 0 range 17 .. 17; - ASVLD at 0 range 18 .. 18; - BSVLD at 0 range 19 .. 19; - Reserved_20_31 at 0 range 20 .. 31; + for OTG_HS_DCFG_Register use record + DSPD at 0 range 0 .. 1; + NZLSOHSK at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DAD at 0 range 4 .. 10; + PFIVL at 0 range 11 .. 12; + Reserved_13_23 at 0 range 13 .. 23; + PERSCHIVL at 0 range 24 .. 25; + Reserved_26_31 at 0 range 26 .. 31; end record; - ----------------------------- - -- OTG_HS_GOTGINT_Register -- - ----------------------------- - - subtype OTG_HS_GOTGINT_SEDET_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGINT_SRSSCHG_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGINT_HNSSCHG_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGINT_HNGDET_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGINT_ADTOCHG_Field is STM32F429x.Bit; - subtype OTG_HS_GOTGINT_DBCDNE_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_RWUSIG_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_SDIS_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_GINSTS_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_GONSTS_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_TCTL_Field is STM32F429x.UInt3; + subtype OTG_HS_DCTL_SGINAK_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_CGINAK_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_SGONAK_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_CGONAK_Field is STM32F429x.Bit; + subtype OTG_HS_DCTL_POPRGDNE_Field is STM32F429x.Bit; - -- OTG_HS interrupt register - type OTG_HS_GOTGINT_Register is record - -- unspecified - Reserved_0_1 : STM32F429x.UInt2 := 16#0#; - -- Session end detected - SEDET : OTG_HS_GOTGINT_SEDET_Field := 16#0#; - -- unspecified - Reserved_3_7 : STM32F429x.UInt5 := 16#0#; - -- Session request success status change - SRSSCHG : OTG_HS_GOTGINT_SRSSCHG_Field := 16#0#; - -- Host negotiation success status change - HNSSCHG : OTG_HS_GOTGINT_HNSSCHG_Field := 16#0#; - -- unspecified - Reserved_10_16 : STM32F429x.UInt7 := 16#0#; - -- Host negotiation detected - HNGDET : OTG_HS_GOTGINT_HNGDET_Field := 16#0#; - -- A-device timeout change - ADTOCHG : OTG_HS_GOTGINT_ADTOCHG_Field := 16#0#; - -- Debounce done - DBCDNE : OTG_HS_GOTGINT_DBCDNE_Field := 16#0#; + -- OTG_HS device control register + type OTG_HS_DCTL_Register is record + -- Remote wakeup signaling + RWUSIG : OTG_HS_DCTL_RWUSIG_Field := 16#0#; + -- Soft disconnect + SDIS : OTG_HS_DCTL_SDIS_Field := 16#0#; + -- Read-only. Global IN NAK status + GINSTS : OTG_HS_DCTL_GINSTS_Field := 16#0#; + -- Read-only. Global OUT NAK status + GONSTS : OTG_HS_DCTL_GONSTS_Field := 16#0#; + -- Test control + TCTL : OTG_HS_DCTL_TCTL_Field := 16#0#; + -- Write-only. Set global IN NAK + SGINAK : OTG_HS_DCTL_SGINAK_Field := 16#0#; + -- Write-only. Clear global IN NAK + CGINAK : OTG_HS_DCTL_CGINAK_Field := 16#0#; + -- Write-only. Set global OUT NAK + SGONAK : OTG_HS_DCTL_SGONAK_Field := 16#0#; + -- Write-only. Clear global OUT NAK + CGONAK : OTG_HS_DCTL_CGONAK_Field := 16#0#; + -- Power-on programming done + POPRGDNE : OTG_HS_DCTL_POPRGDNE_Field := 16#0#; -- unspecified - Reserved_20_31 : STM32F429x.UInt12 := 16#0#; + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GOTGINT_Register use record - Reserved_0_1 at 0 range 0 .. 1; - SEDET at 0 range 2 .. 2; - Reserved_3_7 at 0 range 3 .. 7; - SRSSCHG at 0 range 8 .. 8; - HNSSCHG at 0 range 9 .. 9; - Reserved_10_16 at 0 range 10 .. 16; - HNGDET at 0 range 17 .. 17; - ADTOCHG at 0 range 18 .. 18; - DBCDNE at 0 range 19 .. 19; - Reserved_20_31 at 0 range 20 .. 31; + for OTG_HS_DCTL_Register use record + RWUSIG at 0 range 0 .. 0; + SDIS at 0 range 1 .. 1; + GINSTS at 0 range 2 .. 2; + GONSTS at 0 range 3 .. 3; + TCTL at 0 range 4 .. 6; + SGINAK at 0 range 7 .. 7; + CGINAK at 0 range 8 .. 8; + SGONAK at 0 range 9 .. 9; + CGONAK at 0 range 10 .. 10; + POPRGDNE at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; end record; - ----------------------------- - -- OTG_HS_GAHBCFG_Register -- - ----------------------------- - - subtype OTG_HS_GAHBCFG_GINT_Field is STM32F429x.Bit; - subtype OTG_HS_GAHBCFG_HBSTLEN_Field is STM32F429x.UInt4; - subtype OTG_HS_GAHBCFG_DMAEN_Field is STM32F429x.Bit; - subtype OTG_HS_GAHBCFG_TXFELVL_Field is STM32F429x.Bit; - subtype OTG_HS_GAHBCFG_PTXFELVL_Field is STM32F429x.Bit; + subtype OTG_HS_DSTS_SUSPSTS_Field is STM32F429x.Bit; + subtype OTG_HS_DSTS_ENUMSPD_Field is STM32F429x.UInt2; + subtype OTG_HS_DSTS_EERR_Field is STM32F429x.Bit; + subtype OTG_HS_DSTS_FNSOF_Field is STM32F429x.UInt14; - -- OTG_HS AHB configuration register - type OTG_HS_GAHBCFG_Register is record - -- Global interrupt mask - GINT : OTG_HS_GAHBCFG_GINT_Field := 16#0#; - -- Burst length/type - HBSTLEN : OTG_HS_GAHBCFG_HBSTLEN_Field := 16#0#; - -- DMA enable - DMAEN : OTG_HS_GAHBCFG_DMAEN_Field := 16#0#; + -- OTG_HS device status register + type OTG_HS_DSTS_Register is record + -- Read-only. Suspend status + SUSPSTS : OTG_HS_DSTS_SUSPSTS_Field; + -- Read-only. Enumerated speed + ENUMSPD : OTG_HS_DSTS_ENUMSPD_Field; + -- Read-only. Erratic error + EERR : OTG_HS_DSTS_EERR_Field; -- unspecified - Reserved_6_6 : STM32F429x.Bit := 16#0#; - -- TxFIFO empty level - TXFELVL : OTG_HS_GAHBCFG_TXFELVL_Field := 16#0#; - -- Periodic TxFIFO empty level - PTXFELVL : OTG_HS_GAHBCFG_PTXFELVL_Field := 16#0#; + Reserved_4_7 : STM32F429x.UInt4; + -- Read-only. Frame number of the received SOF + FNSOF : OTG_HS_DSTS_FNSOF_Field; -- unspecified - Reserved_9_31 : STM32F429x.UInt23 := 16#0#; + Reserved_22_31 : STM32F429x.UInt10; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GAHBCFG_Register use record - GINT at 0 range 0 .. 0; - HBSTLEN at 0 range 1 .. 4; - DMAEN at 0 range 5 .. 5; - Reserved_6_6 at 0 range 6 .. 6; - TXFELVL at 0 range 7 .. 7; - PTXFELVL at 0 range 8 .. 8; - Reserved_9_31 at 0 range 9 .. 31; + for OTG_HS_DSTS_Register use record + SUSPSTS at 0 range 0 .. 0; + ENUMSPD at 0 range 1 .. 2; + EERR at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + FNSOF at 0 range 8 .. 21; + Reserved_22_31 at 0 range 22 .. 31; end record; - ----------------------------- - -- OTG_HS_GUSBCFG_Register -- - ----------------------------- - - subtype OTG_HS_GUSBCFG_TOCAL_Field is STM32F429x.UInt3; - subtype OTG_HS_GUSBCFG_PHYSEL_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_SRPCAP_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_HNPCAP_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_TRDT_Field is STM32F429x.UInt4; - subtype OTG_HS_GUSBCFG_PHYLPCS_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_ULPIFSLS_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_ULPIAR_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_ULPICSM_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_ULPIEVBUSD_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_ULPIEVBUSI_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_TSDPS_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_PCCI_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_PTCI_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_ULPIIPD_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_FHMOD_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_FDMOD_Field is STM32F429x.Bit; - subtype OTG_HS_GUSBCFG_CTXPKT_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPMSK_XFRCM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPMSK_EPDM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPMSK_TOM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPMSK_ITTXFEMSK_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPMSK_INEPNMM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPMSK_INEPNEM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPMSK_TXFURM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPMSK_BIM_Field is STM32F429x.Bit; - -- OTG_HS USB configuration register - type OTG_HS_GUSBCFG_Register is record - -- FS timeout calibration - TOCAL : OTG_HS_GUSBCFG_TOCAL_Field := 16#0#; + -- OTG_HS device IN endpoint common interrupt mask register + type OTG_HS_DIEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : OTG_HS_DIEPMSK_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : OTG_HS_DIEPMSK_EPDM_Field := 16#0#; -- unspecified - Reserved_3_5 : STM32F429x.UInt3 := 16#0#; - -- USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver - -- select - PHYSEL : OTG_HS_GUSBCFG_PHYSEL_Field := 16#0#; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- Timeout condition mask (nonisochronous endpoints) + TOM : OTG_HS_DIEPMSK_TOM_Field := 16#0#; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : OTG_HS_DIEPMSK_ITTXFEMSK_Field := 16#0#; + -- IN token received with EP mismatch mask + INEPNMM : OTG_HS_DIEPMSK_INEPNMM_Field := 16#0#; + -- IN endpoint NAK effective mask + INEPNEM : OTG_HS_DIEPMSK_INEPNEM_Field := 16#0#; -- unspecified Reserved_7_7 : STM32F429x.Bit := 16#0#; - -- SRP-capable - SRPCAP : OTG_HS_GUSBCFG_SRPCAP_Field := 16#0#; - -- HNP-capable - HNPCAP : OTG_HS_GUSBCFG_HNPCAP_Field := 16#1#; - -- USB turnaround time - TRDT : OTG_HS_GUSBCFG_TRDT_Field := 16#2#; - -- unspecified - Reserved_14_14 : STM32F429x.Bit := 16#0#; - -- PHY Low-power clock select - PHYLPCS : OTG_HS_GUSBCFG_PHYLPCS_Field := 16#0#; - -- unspecified - Reserved_16_16 : STM32F429x.Bit := 16#0#; - -- ULPI FS/LS select - ULPIFSLS : OTG_HS_GUSBCFG_ULPIFSLS_Field := 16#0#; - -- ULPI Auto-resume - ULPIAR : OTG_HS_GUSBCFG_ULPIAR_Field := 16#0#; - -- ULPI Clock SuspendM - ULPICSM : OTG_HS_GUSBCFG_ULPICSM_Field := 16#0#; - -- ULPI External VBUS Drive - ULPIEVBUSD : OTG_HS_GUSBCFG_ULPIEVBUSD_Field := 16#0#; - -- ULPI external VBUS indicator - ULPIEVBUSI : OTG_HS_GUSBCFG_ULPIEVBUSI_Field := 16#0#; - -- TermSel DLine pulsing selection - TSDPS : OTG_HS_GUSBCFG_TSDPS_Field := 16#0#; - -- Indicator complement - PCCI : OTG_HS_GUSBCFG_PCCI_Field := 16#0#; - -- Indicator pass through - PTCI : OTG_HS_GUSBCFG_PTCI_Field := 16#0#; - -- ULPI interface protect disable - ULPIIPD : OTG_HS_GUSBCFG_ULPIIPD_Field := 16#0#; + -- FIFO underrun mask + TXFURM : OTG_HS_DIEPMSK_TXFURM_Field := 16#0#; + -- BNA interrupt mask + BIM : OTG_HS_DIEPMSK_BIM_Field := 16#0#; -- unspecified - Reserved_26_28 : STM32F429x.UInt3 := 16#0#; - -- Forced host mode - FHMOD : OTG_HS_GUSBCFG_FHMOD_Field := 16#0#; - -- Forced peripheral mode - FDMOD : OTG_HS_GUSBCFG_FDMOD_Field := 16#0#; - -- Corrupt Tx packet - CTXPKT : OTG_HS_GUSBCFG_CTXPKT_Field := 16#0#; + Reserved_10_31 : STM32F429x.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GUSBCFG_Register use record - TOCAL at 0 range 0 .. 2; - Reserved_3_5 at 0 range 3 .. 5; - PHYSEL at 0 range 6 .. 6; + for OTG_HS_DIEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; Reserved_7_7 at 0 range 7 .. 7; - SRPCAP at 0 range 8 .. 8; - HNPCAP at 0 range 9 .. 9; - TRDT at 0 range 10 .. 13; - Reserved_14_14 at 0 range 14 .. 14; - PHYLPCS at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - ULPIFSLS at 0 range 17 .. 17; - ULPIAR at 0 range 18 .. 18; - ULPICSM at 0 range 19 .. 19; - ULPIEVBUSD at 0 range 20 .. 20; - ULPIEVBUSI at 0 range 21 .. 21; - TSDPS at 0 range 22 .. 22; - PCCI at 0 range 23 .. 23; - PTCI at 0 range 24 .. 24; - ULPIIPD at 0 range 25 .. 25; - Reserved_26_28 at 0 range 26 .. 28; - FHMOD at 0 range 29 .. 29; - FDMOD at 0 range 30 .. 30; - CTXPKT at 0 range 31 .. 31; + TXFURM at 0 range 8 .. 8; + BIM at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; end record; - ----------------------------- - -- OTG_HS_GRSTCTL_Register -- - ----------------------------- - - subtype OTG_HS_GRSTCTL_CSRST_Field is STM32F429x.Bit; - subtype OTG_HS_GRSTCTL_HSRST_Field is STM32F429x.Bit; - subtype OTG_HS_GRSTCTL_FCRST_Field is STM32F429x.Bit; - subtype OTG_HS_GRSTCTL_RXFFLSH_Field is STM32F429x.Bit; - subtype OTG_HS_GRSTCTL_TXFFLSH_Field is STM32F429x.Bit; - subtype OTG_HS_GRSTCTL_TXFNUM_Field is STM32F429x.UInt5; - subtype OTG_HS_GRSTCTL_DMAREQ_Field is STM32F429x.Bit; - subtype OTG_HS_GRSTCTL_AHBIDL_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPMSK_XFRCM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPMSK_EPDM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPMSK_STUPM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPMSK_OTEPDM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPMSK_B2BSTUP_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPMSK_OPEM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPMSK_BOIM_Field is STM32F429x.Bit; - -- OTG_HS reset register - type OTG_HS_GRSTCTL_Register is record - -- Core soft reset - CSRST : OTG_HS_GRSTCTL_CSRST_Field := 16#0#; - -- HCLK soft reset - HSRST : OTG_HS_GRSTCTL_HSRST_Field := 16#0#; - -- Host frame counter reset - FCRST : OTG_HS_GRSTCTL_FCRST_Field := 16#0#; + -- OTG_HS device OUT endpoint common interrupt mask register + type OTG_HS_DOEPMSK_Register is record + -- Transfer completed interrupt mask + XFRCM : OTG_HS_DOEPMSK_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : OTG_HS_DOEPMSK_EPDM_Field := 16#0#; -- unspecified - Reserved_3_3 : STM32F429x.Bit := 16#0#; - -- RxFIFO flush - RXFFLSH : OTG_HS_GRSTCTL_RXFFLSH_Field := 16#0#; - -- TxFIFO flush - TXFFLSH : OTG_HS_GRSTCTL_TXFFLSH_Field := 16#0#; - -- TxFIFO number - TXFNUM : OTG_HS_GRSTCTL_TXFNUM_Field := 16#0#; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- SETUP phase done mask + STUPM : OTG_HS_DOEPMSK_STUPM_Field := 16#0#; + -- OUT token received when endpoint disabled mask + OTEPDM : OTG_HS_DOEPMSK_OTEPDM_Field := 16#0#; -- unspecified - Reserved_11_29 : STM32F429x.UInt19 := 16#40000#; - -- DMA request signal - DMAREQ : OTG_HS_GRSTCTL_DMAREQ_Field := 16#0#; - -- AHB master idle - AHBIDL : OTG_HS_GRSTCTL_AHBIDL_Field := 16#0#; + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- Back-to-back SETUP packets received mask + B2BSTUP : OTG_HS_DOEPMSK_B2BSTUP_Field := 16#0#; + -- unspecified + Reserved_7_7 : STM32F429x.Bit := 16#0#; + -- OUT packet error mask + OPEM : OTG_HS_DOEPMSK_OPEM_Field := 16#0#; + -- BNA interrupt mask + BOIM : OTG_HS_DOEPMSK_BOIM_Field := 16#0#; + -- unspecified + Reserved_10_31 : STM32F429x.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRSTCTL_Register use record - CSRST at 0 range 0 .. 0; - HSRST at 0 range 1 .. 1; - FCRST at 0 range 2 .. 2; - Reserved_3_3 at 0 range 3 .. 3; - RXFFLSH at 0 range 4 .. 4; - TXFFLSH at 0 range 5 .. 5; - TXFNUM at 0 range 6 .. 10; - Reserved_11_29 at 0 range 11 .. 29; - DMAREQ at 0 range 30 .. 30; - AHBIDL at 0 range 31 .. 31; + for OTG_HS_DOEPMSK_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUPM at 0 range 3 .. 3; + OTEPDM at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + B2BSTUP at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + OPEM at 0 range 8 .. 8; + BOIM at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; end record; - ----------------------------- - -- OTG_HS_GINTSTS_Register -- - ----------------------------- + subtype OTG_HS_DAINT_IEPINT_Field is STM32F429x.UInt16; + subtype OTG_HS_DAINT_OEPINT_Field is STM32F429x.UInt16; - subtype OTG_HS_GINTSTS_CMOD_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_MMIS_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_OTGINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_SOF_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_RXFLVL_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_NPTXFE_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_GINAKEFF_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_BOUTNAKEFF_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_ESUSP_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_USBSUSP_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_USBRST_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_ENUMDNE_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_ISOODRP_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_EOPF_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_IEPINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_OEPINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_IISOIXFR_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_DATAFSUSP_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_HPRTINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_HCINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_PTXFE_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_CIDSCHG_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_DISCINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_SRQINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTSTS_WKUINT_Field is STM32F429x.Bit; + -- OTG_HS device all endpoints interrupt register + type OTG_HS_DAINT_Register is record + -- Read-only. IN endpoint interrupt bits + IEPINT : OTG_HS_DAINT_IEPINT_Field; + -- Read-only. OUT endpoint interrupt bits + OEPINT : OTG_HS_DAINT_OEPINT_Field; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG_HS core interrupt register - type OTG_HS_GINTSTS_Register is record - -- Current mode of operation - CMOD : OTG_HS_GINTSTS_CMOD_Field := 16#0#; - -- Mode mismatch interrupt - MMIS : OTG_HS_GINTSTS_MMIS_Field := 16#0#; - -- OTG interrupt - OTGINT : OTG_HS_GINTSTS_OTGINT_Field := 16#0#; - -- Start of frame - SOF : OTG_HS_GINTSTS_SOF_Field := 16#0#; - -- RxFIFO nonempty - RXFLVL : OTG_HS_GINTSTS_RXFLVL_Field := 16#0#; - -- Nonperiodic TxFIFO empty - NPTXFE : OTG_HS_GINTSTS_NPTXFE_Field := 16#1#; - -- Global IN nonperiodic NAK effective - GINAKEFF : OTG_HS_GINTSTS_GINAKEFF_Field := 16#0#; - -- Global OUT NAK effective - BOUTNAKEFF : OTG_HS_GINTSTS_BOUTNAKEFF_Field := 16#0#; - -- unspecified - Reserved_8_9 : STM32F429x.UInt2 := 16#0#; - -- Early suspend - ESUSP : OTG_HS_GINTSTS_ESUSP_Field := 16#0#; - -- USB suspend - USBSUSP : OTG_HS_GINTSTS_USBSUSP_Field := 16#0#; - -- USB reset - USBRST : OTG_HS_GINTSTS_USBRST_Field := 16#0#; - -- Enumeration done - ENUMDNE : OTG_HS_GINTSTS_ENUMDNE_Field := 16#0#; - -- Isochronous OUT packet dropped interrupt - ISOODRP : OTG_HS_GINTSTS_ISOODRP_Field := 16#0#; - -- End of periodic frame interrupt - EOPF : OTG_HS_GINTSTS_EOPF_Field := 16#0#; - -- unspecified - Reserved_16_17 : STM32F429x.UInt2 := 16#0#; - -- IN endpoint interrupt - IEPINT : OTG_HS_GINTSTS_IEPINT_Field := 16#0#; - -- OUT endpoint interrupt - OEPINT : OTG_HS_GINTSTS_OEPINT_Field := 16#0#; - -- Incomplete isochronous IN transfer - IISOIXFR : OTG_HS_GINTSTS_IISOIXFR_Field := 16#0#; - -- Incomplete periodic transfer - PXFR_INCOMPISOOUT : OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Field := 16#0#; - -- Data fetch suspended - DATAFSUSP : OTG_HS_GINTSTS_DATAFSUSP_Field := 16#0#; - -- unspecified - Reserved_23_23 : STM32F429x.Bit := 16#0#; - -- Host port interrupt - HPRTINT : OTG_HS_GINTSTS_HPRTINT_Field := 16#0#; - -- Host channels interrupt - HCINT : OTG_HS_GINTSTS_HCINT_Field := 16#0#; - -- Periodic TxFIFO empty - PTXFE : OTG_HS_GINTSTS_PTXFE_Field := 16#1#; + for OTG_HS_DAINT_Register use record + IEPINT at 0 range 0 .. 15; + OEPINT at 0 range 16 .. 31; + end record; + + subtype OTG_HS_DAINTMSK_IEPM_Field is STM32F429x.UInt16; + subtype OTG_HS_DAINTMSK_OEPM_Field is STM32F429x.UInt16; + + -- OTG_HS all endpoints interrupt mask register + type OTG_HS_DAINTMSK_Register is record + -- IN EP interrupt mask bits + IEPM : OTG_HS_DAINTMSK_IEPM_Field := 16#0#; + -- OUT EP interrupt mask bits + OEPM : OTG_HS_DAINTMSK_OEPM_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for OTG_HS_DAINTMSK_Register use record + IEPM at 0 range 0 .. 15; + OEPM at 0 range 16 .. 31; + end record; + + subtype OTG_HS_DVBUSDIS_VBUSDT_Field is STM32F429x.UInt16; + + -- OTG_HS device VBUS discharge time register + type OTG_HS_DVBUSDIS_Register is record + -- Device VBUS discharge time + VBUSDT : OTG_HS_DVBUSDIS_VBUSDT_Field := 16#17D7#; -- unspecified - Reserved_27_27 : STM32F429x.Bit := 16#0#; - -- Connector ID status change - CIDSCHG : OTG_HS_GINTSTS_CIDSCHG_Field := 16#0#; - -- Disconnect detected interrupt - DISCINT : OTG_HS_GINTSTS_DISCINT_Field := 16#0#; - -- Session request/new session detected interrupt - SRQINT : OTG_HS_GINTSTS_SRQINT_Field := 16#0#; - -- Resume/remote wakeup detected interrupt - WKUINT : OTG_HS_GINTSTS_WKUINT_Field := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GINTSTS_Register use record - CMOD at 0 range 0 .. 0; - MMIS at 0 range 1 .. 1; - OTGINT at 0 range 2 .. 2; - SOF at 0 range 3 .. 3; - RXFLVL at 0 range 4 .. 4; - NPTXFE at 0 range 5 .. 5; - GINAKEFF at 0 range 6 .. 6; - BOUTNAKEFF at 0 range 7 .. 7; - Reserved_8_9 at 0 range 8 .. 9; - ESUSP at 0 range 10 .. 10; - USBSUSP at 0 range 11 .. 11; - USBRST at 0 range 12 .. 12; - ENUMDNE at 0 range 13 .. 13; - ISOODRP at 0 range 14 .. 14; - EOPF at 0 range 15 .. 15; - Reserved_16_17 at 0 range 16 .. 17; - IEPINT at 0 range 18 .. 18; - OEPINT at 0 range 19 .. 19; - IISOIXFR at 0 range 20 .. 20; - PXFR_INCOMPISOOUT at 0 range 21 .. 21; - DATAFSUSP at 0 range 22 .. 22; - Reserved_23_23 at 0 range 23 .. 23; - HPRTINT at 0 range 24 .. 24; - HCINT at 0 range 25 .. 25; - PTXFE at 0 range 26 .. 26; - Reserved_27_27 at 0 range 27 .. 27; - CIDSCHG at 0 range 28 .. 28; - DISCINT at 0 range 29 .. 29; - SRQINT at 0 range 30 .. 30; - WKUINT at 0 range 31 .. 31; + for OTG_HS_DVBUSDIS_Register use record + VBUSDT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_GINTMSK_Register -- - ----------------------------- - - subtype OTG_HS_GINTMSK_MMISM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_OTGINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_SOFM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_RXFLVLM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_NPTXFEM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_GINAKEFFM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_GONAKEFFM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_ESUSPM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_USBSUSPM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_USBRST_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_ENUMDNEM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_ISOODRPM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_EOPFM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_EPMISM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_IEPINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_OEPINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_IISOIXFRM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_FSUSPM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_PRTIM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_HCIM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_PTXFEM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_CIDSCHGM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_DISCINT_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_SRQIM_Field is STM32F429x.Bit; - subtype OTG_HS_GINTMSK_WUIM_Field is STM32F429x.Bit; + subtype OTG_HS_DVBUSPULSE_DVBUSP_Field is STM32F429x.UInt12; - -- OTG_HS interrupt mask register - type OTG_HS_GINTMSK_Register is record - -- unspecified - Reserved_0_0 : STM32F429x.Bit := 16#0#; - -- Mode mismatch interrupt mask - MMISM : OTG_HS_GINTMSK_MMISM_Field := 16#0#; - -- OTG interrupt mask - OTGINT : OTG_HS_GINTMSK_OTGINT_Field := 16#0#; - -- Start of frame mask - SOFM : OTG_HS_GINTMSK_SOFM_Field := 16#0#; - -- Receive FIFO nonempty mask - RXFLVLM : OTG_HS_GINTMSK_RXFLVLM_Field := 16#0#; - -- Nonperiodic TxFIFO empty mask - NPTXFEM : OTG_HS_GINTMSK_NPTXFEM_Field := 16#0#; - -- Global nonperiodic IN NAK effective mask - GINAKEFFM : OTG_HS_GINTMSK_GINAKEFFM_Field := 16#0#; - -- Global OUT NAK effective mask - GONAKEFFM : OTG_HS_GINTMSK_GONAKEFFM_Field := 16#0#; - -- unspecified - Reserved_8_9 : STM32F429x.UInt2 := 16#0#; - -- Early suspend mask - ESUSPM : OTG_HS_GINTMSK_ESUSPM_Field := 16#0#; - -- USB suspend mask - USBSUSPM : OTG_HS_GINTMSK_USBSUSPM_Field := 16#0#; - -- USB reset mask - USBRST : OTG_HS_GINTMSK_USBRST_Field := 16#0#; - -- Enumeration done mask - ENUMDNEM : OTG_HS_GINTMSK_ENUMDNEM_Field := 16#0#; - -- Isochronous OUT packet dropped interrupt mask - ISOODRPM : OTG_HS_GINTMSK_ISOODRPM_Field := 16#0#; - -- End of periodic frame interrupt mask - EOPFM : OTG_HS_GINTMSK_EOPFM_Field := 16#0#; - -- unspecified - Reserved_16_16 : STM32F429x.Bit := 16#0#; - -- Endpoint mismatch interrupt mask - EPMISM : OTG_HS_GINTMSK_EPMISM_Field := 16#0#; - -- IN endpoints interrupt mask - IEPINT : OTG_HS_GINTMSK_IEPINT_Field := 16#0#; - -- OUT endpoints interrupt mask - OEPINT : OTG_HS_GINTMSK_OEPINT_Field := 16#0#; - -- Incomplete isochronous IN transfer mask - IISOIXFRM : OTG_HS_GINTMSK_IISOIXFRM_Field := 16#0#; - -- Incomplete periodic transfer mask - PXFRM_IISOOXFRM : OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Field := 16#0#; - -- Data fetch suspended mask - FSUSPM : OTG_HS_GINTMSK_FSUSPM_Field := 16#0#; - -- unspecified - Reserved_23_23 : STM32F429x.Bit := 16#0#; - -- Host port interrupt mask - PRTIM : OTG_HS_GINTMSK_PRTIM_Field := 16#0#; - -- Host channels interrupt mask - HCIM : OTG_HS_GINTMSK_HCIM_Field := 16#0#; - -- Periodic TxFIFO empty mask - PTXFEM : OTG_HS_GINTMSK_PTXFEM_Field := 16#0#; + -- OTG_HS device VBUS pulsing time register + type OTG_HS_DVBUSPULSE_Register is record + -- Device VBUS pulsing time + DVBUSP : OTG_HS_DVBUSPULSE_DVBUSP_Field := 16#5B8#; -- unspecified - Reserved_27_27 : STM32F429x.Bit := 16#0#; - -- Connector ID status change mask - CIDSCHGM : OTG_HS_GINTMSK_CIDSCHGM_Field := 16#0#; - -- Disconnect detected interrupt mask - DISCINT : OTG_HS_GINTMSK_DISCINT_Field := 16#0#; - -- Session request/new session detected interrupt mask - SRQIM : OTG_HS_GINTMSK_SRQIM_Field := 16#0#; - -- Resume/remote wakeup detected interrupt mask - WUIM : OTG_HS_GINTMSK_WUIM_Field := 16#0#; + Reserved_12_31 : STM32F429x.UInt20 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GINTMSK_Register use record - Reserved_0_0 at 0 range 0 .. 0; - MMISM at 0 range 1 .. 1; - OTGINT at 0 range 2 .. 2; - SOFM at 0 range 3 .. 3; - RXFLVLM at 0 range 4 .. 4; - NPTXFEM at 0 range 5 .. 5; - GINAKEFFM at 0 range 6 .. 6; - GONAKEFFM at 0 range 7 .. 7; - Reserved_8_9 at 0 range 8 .. 9; - ESUSPM at 0 range 10 .. 10; - USBSUSPM at 0 range 11 .. 11; - USBRST at 0 range 12 .. 12; - ENUMDNEM at 0 range 13 .. 13; - ISOODRPM at 0 range 14 .. 14; - EOPFM at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - EPMISM at 0 range 17 .. 17; - IEPINT at 0 range 18 .. 18; - OEPINT at 0 range 19 .. 19; - IISOIXFRM at 0 range 20 .. 20; - PXFRM_IISOOXFRM at 0 range 21 .. 21; - FSUSPM at 0 range 22 .. 22; - Reserved_23_23 at 0 range 23 .. 23; - PRTIM at 0 range 24 .. 24; - HCIM at 0 range 25 .. 25; - PTXFEM at 0 range 26 .. 26; - Reserved_27_27 at 0 range 27 .. 27; - CIDSCHGM at 0 range 28 .. 28; - DISCINT at 0 range 29 .. 29; - SRQIM at 0 range 30 .. 30; - WUIM at 0 range 31 .. 31; + for OTG_HS_DVBUSPULSE_Register use record + DVBUSP at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; end record; - ---------------------------------- - -- OTG_HS_GRXSTSR_Host_Register -- - ---------------------------------- - - subtype OTG_HS_GRXSTSR_Host_CHNUM_Field is STM32F429x.UInt4; - subtype OTG_HS_GRXSTSR_Host_BCNT_Field is STM32F429x.UInt11; - subtype OTG_HS_GRXSTSR_Host_DPID_Field is STM32F429x.UInt2; - subtype OTG_HS_GRXSTSR_Host_PKTSTS_Field is STM32F429x.UInt4; + subtype OTG_HS_DTHRCTL_NONISOTHREN_Field is STM32F429x.Bit; + subtype OTG_HS_DTHRCTL_ISOTHREN_Field is STM32F429x.Bit; + subtype OTG_HS_DTHRCTL_TXTHRLEN_Field is STM32F429x.UInt9; + subtype OTG_HS_DTHRCTL_RXTHREN_Field is STM32F429x.Bit; + subtype OTG_HS_DTHRCTL_RXTHRLEN_Field is STM32F429x.UInt9; + subtype OTG_HS_DTHRCTL_ARPEN_Field is STM32F429x.Bit; - -- OTG_HS Receive status debug read register (host mode) - type OTG_HS_GRXSTSR_Host_Register is record - -- Channel number - CHNUM : OTG_HS_GRXSTSR_Host_CHNUM_Field; - -- Byte count - BCNT : OTG_HS_GRXSTSR_Host_BCNT_Field; - -- Data PID - DPID : OTG_HS_GRXSTSR_Host_DPID_Field; - -- Packet status - PKTSTS : OTG_HS_GRXSTSR_Host_PKTSTS_Field; + -- OTG_HS Device threshold control register + type OTG_HS_DTHRCTL_Register is record + -- Nonisochronous IN endpoints threshold enable + NONISOTHREN : OTG_HS_DTHRCTL_NONISOTHREN_Field := 16#0#; + -- ISO IN endpoint threshold enable + ISOTHREN : OTG_HS_DTHRCTL_ISOTHREN_Field := 16#0#; + -- Transmit threshold length + TXTHRLEN : OTG_HS_DTHRCTL_TXTHRLEN_Field := 16#0#; -- unspecified - Reserved_21_31 : STM32F429x.UInt11; + Reserved_11_15 : STM32F429x.UInt5 := 16#0#; + -- Receive threshold enable + RXTHREN : OTG_HS_DTHRCTL_RXTHREN_Field := 16#0#; + -- Receive threshold length + RXTHRLEN : OTG_HS_DTHRCTL_RXTHRLEN_Field := 16#0#; + -- unspecified + Reserved_26_26 : STM32F429x.Bit := 16#0#; + -- Arbiter parking enable + ARPEN : OTG_HS_DTHRCTL_ARPEN_Field := 16#0#; + -- unspecified + Reserved_28_31 : STM32F429x.UInt4 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXSTSR_Host_Register use record - CHNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - Reserved_21_31 at 0 range 21 .. 31; + for OTG_HS_DTHRCTL_Register use record + NONISOTHREN at 0 range 0 .. 0; + ISOTHREN at 0 range 1 .. 1; + TXTHRLEN at 0 range 2 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + RXTHREN at 0 range 16 .. 16; + RXTHRLEN at 0 range 17 .. 25; + Reserved_26_26 at 0 range 26 .. 26; + ARPEN at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; end record; - ---------------------------------------- - -- OTG_HS_GRXSTSR_Peripheral_Register -- - ---------------------------------------- - - subtype OTG_HS_GRXSTSR_Peripheral_EPNUM_Field is STM32F429x.UInt4; - subtype OTG_HS_GRXSTSR_Peripheral_BCNT_Field is STM32F429x.UInt11; - subtype OTG_HS_GRXSTSR_Peripheral_DPID_Field is STM32F429x.UInt2; - subtype OTG_HS_GRXSTSR_Peripheral_PKTSTS_Field is STM32F429x.UInt4; - subtype OTG_HS_GRXSTSR_Peripheral_FRMNUM_Field is STM32F429x.UInt4; + subtype OTG_HS_DIEPEMPMSK_INEPTXFEM_Field is STM32F429x.UInt16; - -- OTG_HS Receive status debug read register (peripheral mode mode) - type OTG_HS_GRXSTSR_Peripheral_Register is record - -- Endpoint number - EPNUM : OTG_HS_GRXSTSR_Peripheral_EPNUM_Field; - -- Byte count - BCNT : OTG_HS_GRXSTSR_Peripheral_BCNT_Field; - -- Data PID - DPID : OTG_HS_GRXSTSR_Peripheral_DPID_Field; - -- Packet status - PKTSTS : OTG_HS_GRXSTSR_Peripheral_PKTSTS_Field; - -- Frame number - FRMNUM : OTG_HS_GRXSTSR_Peripheral_FRMNUM_Field; + -- OTG_HS device IN endpoint FIFO empty interrupt mask register + type OTG_HS_DIEPEMPMSK_Register is record + -- IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM : OTG_HS_DIEPEMPMSK_INEPTXFEM_Field := 16#0#; -- unspecified - Reserved_25_31 : STM32F429x.UInt7; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXSTSR_Peripheral_Register use record - EPNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - FRMNUM at 0 range 21 .. 24; - Reserved_25_31 at 0 range 25 .. 31; + for OTG_HS_DIEPEMPMSK_Register use record + INEPTXFEM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ---------------------------------- - -- OTG_HS_GRXSTSP_Host_Register -- - ---------------------------------- - - subtype OTG_HS_GRXSTSP_Host_CHNUM_Field is STM32F429x.UInt4; - subtype OTG_HS_GRXSTSP_Host_BCNT_Field is STM32F429x.UInt11; - subtype OTG_HS_GRXSTSP_Host_DPID_Field is STM32F429x.UInt2; - subtype OTG_HS_GRXSTSP_Host_PKTSTS_Field is STM32F429x.UInt4; + subtype OTG_HS_DEACHINT_IEP1INT_Field is STM32F429x.Bit; + subtype OTG_HS_DEACHINT_OEP1INT_Field is STM32F429x.Bit; - -- OTG_HS status read and pop register (host mode) - type OTG_HS_GRXSTSP_Host_Register is record - -- Channel number - CHNUM : OTG_HS_GRXSTSP_Host_CHNUM_Field; - -- Byte count - BCNT : OTG_HS_GRXSTSP_Host_BCNT_Field; - -- Data PID - DPID : OTG_HS_GRXSTSP_Host_DPID_Field; - -- Packet status - PKTSTS : OTG_HS_GRXSTSP_Host_PKTSTS_Field; + -- OTG_HS device each endpoint interrupt register + type OTG_HS_DEACHINT_Register is record -- unspecified - Reserved_21_31 : STM32F429x.UInt11; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for OTG_HS_GRXSTSP_Host_Register use record - CHNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - Reserved_21_31 at 0 range 21 .. 31; - end record; - - ---------------------------------------- - -- OTG_HS_GRXSTSP_Peripheral_Register -- - ---------------------------------------- - - subtype OTG_HS_GRXSTSP_Peripheral_EPNUM_Field is STM32F429x.UInt4; - subtype OTG_HS_GRXSTSP_Peripheral_BCNT_Field is STM32F429x.UInt11; - subtype OTG_HS_GRXSTSP_Peripheral_DPID_Field is STM32F429x.UInt2; - subtype OTG_HS_GRXSTSP_Peripheral_PKTSTS_Field is STM32F429x.UInt4; - subtype OTG_HS_GRXSTSP_Peripheral_FRMNUM_Field is STM32F429x.UInt4; - - -- OTG_HS status read and pop register (peripheral mode) - type OTG_HS_GRXSTSP_Peripheral_Register is record - -- Endpoint number - EPNUM : OTG_HS_GRXSTSP_Peripheral_EPNUM_Field; - -- Byte count - BCNT : OTG_HS_GRXSTSP_Peripheral_BCNT_Field; - -- Data PID - DPID : OTG_HS_GRXSTSP_Peripheral_DPID_Field; - -- Packet status - PKTSTS : OTG_HS_GRXSTSP_Peripheral_PKTSTS_Field; - -- Frame number - FRMNUM : OTG_HS_GRXSTSP_Peripheral_FRMNUM_Field; + Reserved_0_0 : STM32F429x.Bit := 16#0#; + -- IN endpoint 1interrupt bit + IEP1INT : OTG_HS_DEACHINT_IEP1INT_Field := 16#0#; -- unspecified - Reserved_25_31 : STM32F429x.UInt7; + Reserved_2_16 : STM32F429x.UInt15 := 16#0#; + -- OUT endpoint 1 interrupt bit + OEP1INT : OTG_HS_DEACHINT_OEP1INT_Field := 16#0#; + -- unspecified + Reserved_18_31 : STM32F429x.UInt14 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXSTSP_Peripheral_Register use record - EPNUM at 0 range 0 .. 3; - BCNT at 0 range 4 .. 14; - DPID at 0 range 15 .. 16; - PKTSTS at 0 range 17 .. 20; - FRMNUM at 0 range 21 .. 24; - Reserved_25_31 at 0 range 25 .. 31; + for OTG_HS_DEACHINT_Register use record + Reserved_0_0 at 0 range 0 .. 0; + IEP1INT at 0 range 1 .. 1; + Reserved_2_16 at 0 range 2 .. 16; + OEP1INT at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; end record; - ----------------------------- - -- OTG_HS_GRXFSIZ_Register -- - ----------------------------- - - subtype OTG_HS_GRXFSIZ_RXFD_Field is STM32F429x.Short; + subtype OTG_HS_DEACHINTMSK_IEP1INTM_Field is STM32F429x.Bit; + subtype OTG_HS_DEACHINTMSK_OEP1INTM_Field is STM32F429x.Bit; - -- OTG_HS Receive FIFO size register - type OTG_HS_GRXFSIZ_Register is record - -- RxFIFO depth - RXFD : OTG_HS_GRXFSIZ_RXFD_Field := 16#200#; + -- OTG_HS device each endpoint interrupt register mask + type OTG_HS_DEACHINTMSK_Register is record + -- unspecified + Reserved_0_0 : STM32F429x.Bit := 16#0#; + -- IN Endpoint 1 interrupt mask bit + IEP1INTM : OTG_HS_DEACHINTMSK_IEP1INTM_Field := 16#0#; + -- unspecified + Reserved_2_16 : STM32F429x.UInt15 := 16#0#; + -- OUT Endpoint 1 interrupt mask bit + OEP1INTM : OTG_HS_DEACHINTMSK_OEP1INTM_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_18_31 : STM32F429x.UInt14 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GRXFSIZ_Register use record - RXFD at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_DEACHINTMSK_Register use record + Reserved_0_0 at 0 range 0 .. 0; + IEP1INTM at 0 range 1 .. 1; + Reserved_2_16 at 0 range 2 .. 16; + OEP1INTM at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; end record; - ------------------------------------ - -- OTG_HS_GNPTXFSIZ_Host_Register -- - ------------------------------------ - - subtype OTG_HS_GNPTXFSIZ_Host_NPTXFSA_Field is STM32F429x.Short; - subtype OTG_HS_GNPTXFSIZ_Host_NPTXFD_Field is STM32F429x.Short; + subtype OTG_HS_DIEPEACHMSK1_XFRCM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPEACHMSK1_EPDM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPEACHMSK1_TOM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPEACHMSK1_INEPNMM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPEACHMSK1_INEPNEM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPEACHMSK1_TXFURM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPEACHMSK1_BIM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPEACHMSK1_NAKM_Field is STM32F429x.Bit; - -- OTG_HS nonperiodic transmit FIFO size register (host mode) - type OTG_HS_GNPTXFSIZ_Host_Register is record - -- Nonperiodic transmit RAM start address - NPTXFSA : OTG_HS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; - -- Nonperiodic TxFIFO depth - NPTXFD : OTG_HS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; + -- OTG_HS device each in endpoint-1 interrupt register + type OTG_HS_DIEPEACHMSK1_Register is record + -- Transfer completed interrupt mask + XFRCM : OTG_HS_DIEPEACHMSK1_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : OTG_HS_DIEPEACHMSK1_EPDM_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- Timeout condition mask (nonisochronous endpoints) + TOM : OTG_HS_DIEPEACHMSK1_TOM_Field := 16#0#; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Field := 16#0#; + -- IN token received with EP mismatch mask + INEPNMM : OTG_HS_DIEPEACHMSK1_INEPNMM_Field := 16#0#; + -- IN endpoint NAK effective mask + INEPNEM : OTG_HS_DIEPEACHMSK1_INEPNEM_Field := 16#0#; + -- unspecified + Reserved_7_7 : STM32F429x.Bit := 16#0#; + -- FIFO underrun mask + TXFURM : OTG_HS_DIEPEACHMSK1_TXFURM_Field := 16#0#; + -- BNA interrupt mask + BIM : OTG_HS_DIEPEACHMSK1_BIM_Field := 16#0#; + -- unspecified + Reserved_10_12 : STM32F429x.UInt3 := 16#0#; + -- NAK interrupt mask + NAKM : OTG_HS_DIEPEACHMSK1_NAKM_Field := 16#0#; + -- unspecified + Reserved_14_31 : STM32F429x.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GNPTXFSIZ_Host_Register use record - NPTXFSA at 0 range 0 .. 15; - NPTXFD at 0 range 16 .. 31; + for OTG_HS_DIEPEACHMSK1_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + TXFURM at 0 range 8 .. 8; + BIM at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + NAKM at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; end record; - ---------------------------------------- - -- OTG_HS_TX0FSIZ_Peripheral_Register -- - ---------------------------------------- - - subtype OTG_HS_TX0FSIZ_Peripheral_TX0FSA_Field is STM32F429x.Short; - subtype OTG_HS_TX0FSIZ_Peripheral_TX0FD_Field is STM32F429x.Short; + subtype OTG_HS_DOEPEACHMSK1_XFRCM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_EPDM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_TOM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_ITTXFEMSK_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_INEPNMM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_INEPNEM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_TXFURM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_BIM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_BERRM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_NAKM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPEACHMSK1_NYETM_Field is STM32F429x.Bit; - -- Endpoint 0 transmit FIFO size (peripheral mode) - type OTG_HS_TX0FSIZ_Peripheral_Register is record - -- Endpoint 0 transmit RAM start address - TX0FSA : OTG_HS_TX0FSIZ_Peripheral_TX0FSA_Field := 16#200#; - -- Endpoint 0 TxFIFO depth - TX0FD : OTG_HS_TX0FSIZ_Peripheral_TX0FD_Field := 16#0#; + -- OTG_HS device each OUT endpoint-1 interrupt register + type OTG_HS_DOEPEACHMSK1_Register is record + -- Transfer completed interrupt mask + XFRCM : OTG_HS_DOEPEACHMSK1_XFRCM_Field := 16#0#; + -- Endpoint disabled interrupt mask + EPDM : OTG_HS_DOEPEACHMSK1_EPDM_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- Timeout condition mask + TOM : OTG_HS_DOEPEACHMSK1_TOM_Field := 16#0#; + -- IN token received when TxFIFO empty mask + ITTXFEMSK : OTG_HS_DOEPEACHMSK1_ITTXFEMSK_Field := 16#0#; + -- IN token received with EP mismatch mask + INEPNMM : OTG_HS_DOEPEACHMSK1_INEPNMM_Field := 16#0#; + -- IN endpoint NAK effective mask + INEPNEM : OTG_HS_DOEPEACHMSK1_INEPNEM_Field := 16#0#; + -- unspecified + Reserved_7_7 : STM32F429x.Bit := 16#0#; + -- OUT packet error mask + TXFURM : OTG_HS_DOEPEACHMSK1_TXFURM_Field := 16#0#; + -- BNA interrupt mask + BIM : OTG_HS_DOEPEACHMSK1_BIM_Field := 16#0#; + -- unspecified + Reserved_10_11 : STM32F429x.UInt2 := 16#0#; + -- Bubble error interrupt mask + BERRM : OTG_HS_DOEPEACHMSK1_BERRM_Field := 16#0#; + -- NAK interrupt mask + NAKM : OTG_HS_DOEPEACHMSK1_NAKM_Field := 16#0#; + -- NYET interrupt mask + NYETM : OTG_HS_DOEPEACHMSK1_NYETM_Field := 16#0#; + -- unspecified + Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_TX0FSIZ_Peripheral_Register use record - TX0FSA at 0 range 0 .. 15; - TX0FD at 0 range 16 .. 31; + for OTG_HS_DOEPEACHMSK1_Register use record + XFRCM at 0 range 0 .. 0; + EPDM at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOM at 0 range 3 .. 3; + ITTXFEMSK at 0 range 4 .. 4; + INEPNMM at 0 range 5 .. 5; + INEPNEM at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + TXFURM at 0 range 8 .. 8; + BIM at 0 range 9 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + BERRM at 0 range 12 .. 12; + NAKM at 0 range 13 .. 13; + NYETM at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; end record; - ------------------------------ - -- OTG_HS_GNPTXSTS_Register -- - ------------------------------ - - subtype OTG_HS_GNPTXSTS_NPTXFSAV_Field is STM32F429x.Short; - subtype OTG_HS_GNPTXSTS_NPTQXSAV_Field is STM32F429x.Byte; - subtype OTG_HS_GNPTXSTS_NPTXQTOP_Field is STM32F429x.UInt7; + subtype OTG_HS_DIEPCTL_MPSIZ_Field is STM32F429x.UInt11; + subtype OTG_HS_DIEPCTL_USBAEP_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_EONUM_DPID_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_NAKSTS_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_EPTYP_Field is STM32F429x.UInt2; + subtype OTG_HS_DIEPCTL_Stall_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_TXFNUM_Field is STM32F429x.UInt4; + subtype OTG_HS_DIEPCTL_CNAK_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_SNAK_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_SD0PID_SEVNFRM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_SODDFRM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_EPDIS_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPCTL_EPENA_Field is STM32F429x.Bit; - -- OTG_HS nonperiodic transmit FIFO/queue status register - type OTG_HS_GNPTXSTS_Register is record - -- Nonperiodic TxFIFO space available - NPTXFSAV : OTG_HS_GNPTXSTS_NPTXFSAV_Field; - -- Nonperiodic transmit request queue space available - NPTQXSAV : OTG_HS_GNPTXSTS_NPTQXSAV_Field; - -- Top of the nonperiodic transmit request queue - NPTXQTOP : OTG_HS_GNPTXSTS_NPTXQTOP_Field; + -- OTG device endpoint-0 control register + type OTG_HS_DIEPCTL_Register is record + -- Maximum packet size + MPSIZ : OTG_HS_DIEPCTL_MPSIZ_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F429x.Bit; + Reserved_11_14 : STM32F429x.UInt4 := 16#0#; + -- USB active endpoint + USBAEP : OTG_HS_DIEPCTL_USBAEP_Field := 16#0#; + -- Read-only. Even/odd frame + EONUM_DPID : OTG_HS_DIEPCTL_EONUM_DPID_Field := 16#0#; + -- Read-only. NAK status + NAKSTS : OTG_HS_DIEPCTL_NAKSTS_Field := 16#0#; + -- Endpoint type + EPTYP : OTG_HS_DIEPCTL_EPTYP_Field := 16#0#; + -- unspecified + Reserved_20_20 : STM32F429x.Bit := 16#0#; + -- STALL handshake + Stall : OTG_HS_DIEPCTL_Stall_Field := 16#0#; + -- TxFIFO number + TXFNUM : OTG_HS_DIEPCTL_TXFNUM_Field := 16#0#; + -- Write-only. Clear NAK + CNAK : OTG_HS_DIEPCTL_CNAK_Field := 16#0#; + -- Write-only. Set NAK + SNAK : OTG_HS_DIEPCTL_SNAK_Field := 16#0#; + -- Write-only. Set DATA0 PID + SD0PID_SEVNFRM : OTG_HS_DIEPCTL_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. Set odd frame + SODDFRM : OTG_HS_DIEPCTL_SODDFRM_Field := 16#0#; + -- Endpoint disable + EPDIS : OTG_HS_DIEPCTL_EPDIS_Field := 16#0#; + -- Endpoint enable + EPENA : OTG_HS_DIEPCTL_EPENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GNPTXSTS_Register use record - NPTXFSAV at 0 range 0 .. 15; - NPTQXSAV at 0 range 16 .. 23; - NPTXQTOP at 0 range 24 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for OTG_HS_DIEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + TXFNUM at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - --------------------------- - -- OTG_HS_GCCFG_Register -- - --------------------------- + subtype OTG_HS_DIEPINT_XFRC_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_EPDISD_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_TOC_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_ITTXFE_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_INEPNE_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_TXFE_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_TXFIFOUDRN_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_BNA_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_PKTDRPSTS_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_BERR_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPINT_NAK_Field is STM32F429x.Bit; - subtype OTG_HS_GCCFG_PWRDWN_Field is STM32F429x.Bit; - subtype OTG_HS_GCCFG_I2CPADEN_Field is STM32F429x.Bit; - subtype OTG_HS_GCCFG_VBUSASEN_Field is STM32F429x.Bit; - subtype OTG_HS_GCCFG_VBUSBSEN_Field is STM32F429x.Bit; - subtype OTG_HS_GCCFG_SOFOUTEN_Field is STM32F429x.Bit; - subtype OTG_HS_GCCFG_NOVBUSSENS_Field is STM32F429x.Bit; - - -- OTG_HS general core configuration register - type OTG_HS_GCCFG_Register is record + -- OTG device endpoint-0 interrupt register + type OTG_HS_DIEPINT_Register is record + -- Transfer completed interrupt + XFRC : OTG_HS_DIEPINT_XFRC_Field := 16#0#; + -- Endpoint disabled interrupt + EPDISD : OTG_HS_DIEPINT_EPDISD_Field := 16#0#; -- unspecified - Reserved_0_15 : STM32F429x.Short := 16#0#; - -- Power down - PWRDWN : OTG_HS_GCCFG_PWRDWN_Field := 16#0#; - -- Enable I2C bus connection for the external I2C PHY interface - I2CPADEN : OTG_HS_GCCFG_I2CPADEN_Field := 16#0#; - -- Enable the VBUS sensing device - VBUSASEN : OTG_HS_GCCFG_VBUSASEN_Field := 16#0#; - -- Enable the VBUS sensing device - VBUSBSEN : OTG_HS_GCCFG_VBUSBSEN_Field := 16#0#; - -- SOF output enable - SOFOUTEN : OTG_HS_GCCFG_SOFOUTEN_Field := 16#0#; - -- VBUS sensing disable option - NOVBUSSENS : OTG_HS_GCCFG_NOVBUSSENS_Field := 16#0#; + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- Timeout condition + TOC : OTG_HS_DIEPINT_TOC_Field := 16#0#; + -- IN token received when TxFIFO is empty + ITTXFE : OTG_HS_DIEPINT_ITTXFE_Field := 16#0#; -- unspecified - Reserved_22_31 : STM32F429x.UInt10 := 16#0#; + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- IN endpoint NAK effective + INEPNE : OTG_HS_DIEPINT_INEPNE_Field := 16#0#; + -- Read-only. Transmit FIFO empty + TXFE : OTG_HS_DIEPINT_TXFE_Field := 16#1#; + -- Transmit Fifo Underrun + TXFIFOUDRN : OTG_HS_DIEPINT_TXFIFOUDRN_Field := 16#0#; + -- Buffer not available interrupt + BNA : OTG_HS_DIEPINT_BNA_Field := 16#0#; + -- unspecified + Reserved_10_10 : STM32F429x.Bit := 16#0#; + -- Packet dropped status + PKTDRPSTS : OTG_HS_DIEPINT_PKTDRPSTS_Field := 16#0#; + -- Babble error interrupt + BERR : OTG_HS_DIEPINT_BERR_Field := 16#0#; + -- NAK interrupt + NAK : OTG_HS_DIEPINT_NAK_Field := 16#0#; + -- unspecified + Reserved_14_31 : STM32F429x.UInt18 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_GCCFG_Register use record - Reserved_0_15 at 0 range 0 .. 15; - PWRDWN at 0 range 16 .. 16; - I2CPADEN at 0 range 17 .. 17; - VBUSASEN at 0 range 18 .. 18; - VBUSBSEN at 0 range 19 .. 19; - SOFOUTEN at 0 range 20 .. 20; - NOVBUSSENS at 0 range 21 .. 21; - Reserved_22_31 at 0 range 22 .. 31; + for OTG_HS_DIEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + TOC at 0 range 3 .. 3; + ITTXFE at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + INEPNE at 0 range 6 .. 6; + TXFE at 0 range 7 .. 7; + TXFIFOUDRN at 0 range 8 .. 8; + BNA at 0 range 9 .. 9; + Reserved_10_10 at 0 range 10 .. 10; + PKTDRPSTS at 0 range 11 .. 11; + BERR at 0 range 12 .. 12; + NAK at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; end record; - ------------------------------ - -- OTG_HS_HPTXFSIZ_Register -- - ------------------------------ - - subtype OTG_HS_HPTXFSIZ_PTXSA_Field is STM32F429x.Short; - subtype OTG_HS_HPTXFSIZ_PTXFD_Field is STM32F429x.Short; + subtype OTG_HS_DIEPTSIZ0_XFRSIZ_Field is STM32F429x.UInt7; + subtype OTG_HS_DIEPTSIZ0_PKTCNT_Field is STM32F429x.UInt2; - -- OTG_HS Host periodic transmit FIFO size register - type OTG_HS_HPTXFSIZ_Register is record - -- Host periodic TxFIFO start address - PTXSA : OTG_HS_HPTXFSIZ_PTXSA_Field := 16#600#; - -- Host periodic TxFIFO depth - PTXFD : OTG_HS_HPTXFSIZ_PTXFD_Field := 16#200#; + -- OTG_HS device IN endpoint 0 transfer size register + type OTG_HS_DIEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : OTG_HS_DIEPTSIZ0_XFRSIZ_Field := 16#0#; + -- unspecified + Reserved_7_18 : STM32F429x.UInt12 := 16#0#; + -- Packet count + PKTCNT : OTG_HS_DIEPTSIZ0_PKTCNT_Field := 16#0#; + -- unspecified + Reserved_21_31 : STM32F429x.UInt11 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HPTXFSIZ_Register use record - PTXSA at 0 range 0 .. 15; - PTXFD at 0 range 16 .. 31; + for OTG_HS_DIEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - ----------------------------- - -- OTG_HS_DIEPTXF_Register -- - ----------------------------- - - subtype OTG_HS_DIEPTXF1_INEPTXSA_Field is STM32F429x.Short; - subtype OTG_HS_DIEPTXF1_INEPTXFD_Field is STM32F429x.Short; + subtype OTG_HS_DTXFSTS_INEPTFSAV_Field is STM32F429x.UInt16; - -- OTG_HS device IN endpoint transmit FIFO size register - type OTG_HS_DIEPTXF_Register is record - -- IN endpoint FIFOx transmit RAM start address - INEPTXSA : OTG_HS_DIEPTXF1_INEPTXSA_Field := 16#400#; - -- IN endpoint TxFIFO depth - INEPTXFD : OTG_HS_DIEPTXF1_INEPTXFD_Field := 16#200#; + -- OTG_HS device IN endpoint transmit FIFO status register + type OTG_HS_DTXFSTS_Register is record + -- Read-only. IN endpoint TxFIFO space avail + INEPTFSAV : OTG_HS_DTXFSTS_INEPTFSAV_Field; + -- unspecified + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPTXF_Register use record - INEPTXSA at 0 range 0 .. 15; - INEPTXFD at 0 range 16 .. 31; + for OTG_HS_DTXFSTS_Register use record + INEPTFSAV at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------------- - -- OTG_HS_HCFG_Register -- - -------------------------- - - subtype OTG_HS_HCFG_FSLSPCS_Field is STM32F429x.UInt2; - subtype OTG_HS_HCFG_FSLSS_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPTSIZ_XFRSIZ_Field is STM32F429x.UInt19; + subtype OTG_HS_DIEPTSIZ_PKTCNT_Field is STM32F429x.UInt10; + subtype OTG_HS_DIEPTSIZ_MCNT_Field is STM32F429x.UInt2; - -- OTG_HS host configuration register - type OTG_HS_HCFG_Register is record - -- FS/LS PHY clock select - FSLSPCS : OTG_HS_HCFG_FSLSPCS_Field := 16#0#; - -- FS- and LS-only support - FSLSS : OTG_HS_HCFG_FSLSS_Field := 16#0#; + -- OTG_HS device endpoint transfer size register + type OTG_HS_DIEPTSIZ_Register is record + -- Transfer size + XFRSIZ : OTG_HS_DIEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : OTG_HS_DIEPTSIZ_PKTCNT_Field := 16#0#; + -- Multi count + MCNT : OTG_HS_DIEPTSIZ_MCNT_Field := 16#0#; -- unspecified - Reserved_3_31 : STM32F429x.UInt29 := 16#0#; + Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HCFG_Register use record - FSLSPCS at 0 range 0 .. 1; - FSLSS at 0 range 2 .. 2; - Reserved_3_31 at 0 range 3 .. 31; + for OTG_HS_DIEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + MCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - -------------------------- - -- OTG_HS_HFIR_Register -- - -------------------------- - - subtype OTG_HS_HFIR_FRIVL_Field is STM32F429x.Short; + subtype OTG_HS_DOEPCTL0_MPSIZ_Field is STM32F429x.UInt2; + subtype OTG_HS_DOEPCTL0_USBAEP_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL0_NAKSTS_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL0_EPTYP_Field is STM32F429x.UInt2; + subtype OTG_HS_DOEPCTL0_SNPM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL0_Stall_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL0_CNAK_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL0_SNAK_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL0_EPDIS_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL0_EPENA_Field is STM32F429x.Bit; - -- OTG_HS Host frame interval register - type OTG_HS_HFIR_Register is record - -- Frame interval - FRIVL : OTG_HS_HFIR_FRIVL_Field := 16#EA60#; + -- OTG_HS device control OUT endpoint 0 control register + type OTG_HS_DOEPCTL0_Register is record + -- Read-only. Maximum packet size + MPSIZ : OTG_HS_DOEPCTL0_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_2_14 : STM32F429x.UInt13 := 16#0#; + -- Read-only. USB active endpoint + USBAEP : OTG_HS_DOEPCTL0_USBAEP_Field := 16#1#; + -- unspecified + Reserved_16_16 : STM32F429x.Bit := 16#0#; + -- Read-only. NAK status + NAKSTS : OTG_HS_DOEPCTL0_NAKSTS_Field := 16#0#; + -- Read-only. Endpoint type + EPTYP : OTG_HS_DOEPCTL0_EPTYP_Field := 16#0#; + -- Snoop mode + SNPM : OTG_HS_DOEPCTL0_SNPM_Field := 16#0#; + -- STALL handshake + Stall : OTG_HS_DOEPCTL0_Stall_Field := 16#0#; + -- unspecified + Reserved_22_25 : STM32F429x.UInt4 := 16#0#; + -- Write-only. Clear NAK + CNAK : OTG_HS_DOEPCTL0_CNAK_Field := 16#0#; + -- Write-only. Set NAK + SNAK : OTG_HS_DOEPCTL0_SNAK_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_28_29 : STM32F429x.UInt2 := 16#0#; + -- Read-only. Endpoint disable + EPDIS : OTG_HS_DOEPCTL0_EPDIS_Field := 16#0#; + -- Write-only. Endpoint enable + EPENA : OTG_HS_DOEPCTL0_EPENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HFIR_Register use record - FRIVL at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_DOEPCTL0_Register use record + MPSIZ at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + USBAEP at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + Reserved_28_29 at 0 range 28 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - --------------------------- - -- OTG_HS_HFNUM_Register -- - --------------------------- - - subtype OTG_HS_HFNUM_FRNUM_Field is STM32F429x.Short; - subtype OTG_HS_HFNUM_FTREM_Field is STM32F429x.Short; + subtype OTG_HS_DOEPINT_XFRC_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPINT_EPDISD_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPINT_STUP_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPINT_OTEPDIS_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPINT_B2BSTUP_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPINT_NYET_Field is STM32F429x.Bit; - -- OTG_HS host frame number/frame time remaining register - type OTG_HS_HFNUM_Register is record - -- Frame number - FRNUM : OTG_HS_HFNUM_FRNUM_Field; - -- Frame time remaining - FTREM : OTG_HS_HFNUM_FTREM_Field; + -- OTG_HS device endpoint-0 interrupt register + type OTG_HS_DOEPINT_Register is record + -- Transfer completed interrupt + XFRC : OTG_HS_DOEPINT_XFRC_Field := 16#0#; + -- Endpoint disabled interrupt + EPDISD : OTG_HS_DOEPINT_EPDISD_Field := 16#0#; + -- unspecified + Reserved_2_2 : STM32F429x.Bit := 16#0#; + -- SETUP phase done + STUP : OTG_HS_DOEPINT_STUP_Field := 16#0#; + -- OUT token received when endpoint disabled + OTEPDIS : OTG_HS_DOEPINT_OTEPDIS_Field := 16#0#; + -- unspecified + Reserved_5_5 : STM32F429x.Bit := 16#0#; + -- Back-to-back SETUP packets received + B2BSTUP : OTG_HS_DOEPINT_B2BSTUP_Field := 16#0#; + -- unspecified + Reserved_7_13 : STM32F429x.UInt7 := 16#1#; + -- NYET interrupt + NYET : OTG_HS_DOEPINT_NYET_Field := 16#0#; + -- unspecified + Reserved_15_31 : STM32F429x.UInt17 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HFNUM_Register use record - FRNUM at 0 range 0 .. 15; - FTREM at 0 range 16 .. 31; + for OTG_HS_DOEPINT_Register use record + XFRC at 0 range 0 .. 0; + EPDISD at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + STUP at 0 range 3 .. 3; + OTEPDIS at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + B2BSTUP at 0 range 6 .. 6; + Reserved_7_13 at 0 range 7 .. 13; + NYET at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; end record; - ----------------------------- - -- OTG_HS_HPTXSTS_Register -- - ----------------------------- - - subtype OTG_HS_HPTXSTS_PTXFSAVL_Field is STM32F429x.Short; - subtype OTG_HS_HPTXSTS_PTXQSAV_Field is STM32F429x.Byte; - subtype OTG_HS_HPTXSTS_PTXQTOP_Field is STM32F429x.Byte; + subtype OTG_HS_DOEPTSIZ0_XFRSIZ_Field is STM32F429x.UInt7; + subtype OTG_HS_DOEPTSIZ0_PKTCNT_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPTSIZ0_STUPCNT_Field is STM32F429x.UInt2; - -- OTG_HS_Host periodic transmit FIFO/queue status register - type OTG_HS_HPTXSTS_Register is record - -- Periodic transmit data FIFO space available - PTXFSAVL : OTG_HS_HPTXSTS_PTXFSAVL_Field := 16#100#; - -- Periodic transmit request queue space available - PTXQSAV : OTG_HS_HPTXSTS_PTXQSAV_Field := 16#8#; - -- Top of the periodic transmit request queue - PTXQTOP : OTG_HS_HPTXSTS_PTXQTOP_Field := 16#0#; + -- OTG_HS device endpoint-1 transfer size register + type OTG_HS_DOEPTSIZ0_Register is record + -- Transfer size + XFRSIZ : OTG_HS_DOEPTSIZ0_XFRSIZ_Field := 16#0#; + -- unspecified + Reserved_7_18 : STM32F429x.UInt12 := 16#0#; + -- Packet count + PKTCNT : OTG_HS_DOEPTSIZ0_PKTCNT_Field := 16#0#; + -- unspecified + Reserved_20_28 : STM32F429x.UInt9 := 16#0#; + -- SETUP packet count + STUPCNT : OTG_HS_DOEPTSIZ0_STUPCNT_Field := 16#0#; + -- unspecified + Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HPTXSTS_Register use record - PTXFSAVL at 0 range 0 .. 15; - PTXQSAV at 0 range 16 .. 23; - PTXQTOP at 0 range 24 .. 31; + for OTG_HS_DOEPTSIZ0_Register use record + XFRSIZ at 0 range 0 .. 6; + Reserved_7_18 at 0 range 7 .. 18; + PKTCNT at 0 range 19 .. 19; + Reserved_20_28 at 0 range 20 .. 28; + STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------------- - -- OTG_HS_HAINT_Register -- - --------------------------- - - subtype OTG_HS_HAINT_HAINT_Field is STM32F429x.Short; + subtype OTG_HS_DOEPCTL_MPSIZ_Field is STM32F429x.UInt11; + subtype OTG_HS_DOEPCTL_USBAEP_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_EONUM_DPID_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_NAKSTS_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_EPTYP_Field is STM32F429x.UInt2; + subtype OTG_HS_DOEPCTL_SNPM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_Stall_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_CNAK_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_SNAK_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_SD0PID_SEVNFRM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_SODDFRM_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_EPDIS_Field is STM32F429x.Bit; + subtype OTG_HS_DOEPCTL_EPENA_Field is STM32F429x.Bit; - -- OTG_HS Host all channels interrupt register - type OTG_HS_HAINT_Register is record - -- Channel interrupts - HAINT : OTG_HS_HAINT_HAINT_Field; - -- unspecified - Reserved_16_31 : STM32F429x.Short; + -- OTG device endpoint-1 control register + type OTG_HS_DOEPCTL_Register is record + -- Maximum packet size + MPSIZ : OTG_HS_DOEPCTL_MPSIZ_Field := 16#0#; + -- unspecified + Reserved_11_14 : STM32F429x.UInt4 := 16#0#; + -- USB active endpoint + USBAEP : OTG_HS_DOEPCTL_USBAEP_Field := 16#0#; + -- Read-only. Even odd frame/Endpoint data PID + EONUM_DPID : OTG_HS_DOEPCTL_EONUM_DPID_Field := 16#0#; + -- Read-only. NAK status + NAKSTS : OTG_HS_DOEPCTL_NAKSTS_Field := 16#0#; + -- Endpoint type + EPTYP : OTG_HS_DOEPCTL_EPTYP_Field := 16#0#; + -- Snoop mode + SNPM : OTG_HS_DOEPCTL_SNPM_Field := 16#0#; + -- STALL handshake + Stall : OTG_HS_DOEPCTL_Stall_Field := 16#0#; + -- unspecified + Reserved_22_25 : STM32F429x.UInt4 := 16#0#; + -- Write-only. Clear NAK + CNAK : OTG_HS_DOEPCTL_CNAK_Field := 16#0#; + -- Write-only. Set NAK + SNAK : OTG_HS_DOEPCTL_SNAK_Field := 16#0#; + -- Write-only. Set DATA0 PID/Set even frame + SD0PID_SEVNFRM : OTG_HS_DOEPCTL_SD0PID_SEVNFRM_Field := 16#0#; + -- Write-only. Set odd frame + SODDFRM : OTG_HS_DOEPCTL_SODDFRM_Field := 16#0#; + -- Endpoint disable + EPDIS : OTG_HS_DOEPCTL_EPDIS_Field := 16#0#; + -- Endpoint enable + EPENA : OTG_HS_DOEPCTL_EPENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HAINT_Register use record - HAINT at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_DOEPCTL_Register use record + MPSIZ at 0 range 0 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + USBAEP at 0 range 15 .. 15; + EONUM_DPID at 0 range 16 .. 16; + NAKSTS at 0 range 17 .. 17; + EPTYP at 0 range 18 .. 19; + SNPM at 0 range 20 .. 20; + Stall at 0 range 21 .. 21; + Reserved_22_25 at 0 range 22 .. 25; + CNAK at 0 range 26 .. 26; + SNAK at 0 range 27 .. 27; + SD0PID_SEVNFRM at 0 range 28 .. 28; + SODDFRM at 0 range 29 .. 29; + EPDIS at 0 range 30 .. 30; + EPENA at 0 range 31 .. 31; end record; - ------------------------------ - -- OTG_HS_HAINTMSK_Register -- - ------------------------------ + subtype OTG_HS_DOEPTSIZ_XFRSIZ_Field is STM32F429x.UInt19; + subtype OTG_HS_DOEPTSIZ_PKTCNT_Field is STM32F429x.UInt10; + subtype OTG_HS_DOEPTSIZ_RXDPID_STUPCNT_Field is STM32F429x.UInt2; - subtype OTG_HS_HAINTMSK_HAINTM_Field is STM32F429x.Short; - - -- OTG_HS host all channels interrupt mask register - type OTG_HS_HAINTMSK_Register is record - -- Channel interrupt mask - HAINTM : OTG_HS_HAINTMSK_HAINTM_Field := 16#0#; + -- OTG_HS device endpoint-2 transfer size register + type OTG_HS_DOEPTSIZ_Register is record + -- Transfer size + XFRSIZ : OTG_HS_DOEPTSIZ_XFRSIZ_Field := 16#0#; + -- Packet count + PKTCNT : OTG_HS_DOEPTSIZ_PKTCNT_Field := 16#0#; + -- Received data PID/SETUP packet count + RXDPID_STUPCNT : OTG_HS_DOEPTSIZ_RXDPID_STUPCNT_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HAINTMSK_Register use record - HAINTM at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_DOEPTSIZ_Register use record + XFRSIZ at 0 range 0 .. 18; + PKTCNT at 0 range 19 .. 28; + RXDPID_STUPCNT at 0 range 29 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - -------------------------- - -- OTG_HS_HPRT_Register -- - -------------------------- - - subtype OTG_HS_HPRT_PCSTS_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_PCDET_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_PENA_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_PENCHNG_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_POCA_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_POCCHNG_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_PRES_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_PSUSP_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_PRST_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_PLSTS_Field is STM32F429x.UInt2; - subtype OTG_HS_HPRT_PPWR_Field is STM32F429x.Bit; - subtype OTG_HS_HPRT_PTCTL_Field is STM32F429x.UInt4; - subtype OTG_HS_HPRT_PSPD_Field is STM32F429x.UInt2; + subtype OTG_HS_GOTGCTL_SRQSCS_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_SRQ_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_HNGSCS_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_HNPRQ_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_HSHNPEN_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_DHNPEN_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_CIDSTS_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_DBCT_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_ASVLD_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGCTL_BSVLD_Field is STM32F429x.Bit; - -- OTG_HS host port control and status register - type OTG_HS_HPRT_Register is record - -- Port connect status - PCSTS : OTG_HS_HPRT_PCSTS_Field := 16#0#; - -- Port connect detected - PCDET : OTG_HS_HPRT_PCDET_Field := 16#0#; - -- Port enable - PENA : OTG_HS_HPRT_PENA_Field := 16#0#; - -- Port enable/disable change - PENCHNG : OTG_HS_HPRT_PENCHNG_Field := 16#0#; - -- Port overcurrent active - POCA : OTG_HS_HPRT_POCA_Field := 16#0#; - -- Port overcurrent change - POCCHNG : OTG_HS_HPRT_POCCHNG_Field := 16#0#; - -- Port resume - PRES : OTG_HS_HPRT_PRES_Field := 16#0#; - -- Port suspend - PSUSP : OTG_HS_HPRT_PSUSP_Field := 16#0#; - -- Port reset - PRST : OTG_HS_HPRT_PRST_Field := 16#0#; + -- OTG_HS control and status register + type OTG_HS_GOTGCTL_Register is record + -- Read-only. Session request success + SRQSCS : OTG_HS_GOTGCTL_SRQSCS_Field := 16#0#; + -- Session request + SRQ : OTG_HS_GOTGCTL_SRQ_Field := 16#0#; -- unspecified - Reserved_9_9 : STM32F429x.Bit := 16#0#; - -- Port line status - PLSTS : OTG_HS_HPRT_PLSTS_Field := 16#0#; - -- Port power - PPWR : OTG_HS_HPRT_PPWR_Field := 16#0#; - -- Port test control - PTCTL : OTG_HS_HPRT_PTCTL_Field := 16#0#; - -- Port speed - PSPD : OTG_HS_HPRT_PSPD_Field := 16#0#; + Reserved_2_7 : STM32F429x.UInt6 := 16#0#; + -- Read-only. Host negotiation success + HNGSCS : OTG_HS_GOTGCTL_HNGSCS_Field := 16#0#; + -- HNP request + HNPRQ : OTG_HS_GOTGCTL_HNPRQ_Field := 16#0#; + -- Host set HNP enable + HSHNPEN : OTG_HS_GOTGCTL_HSHNPEN_Field := 16#0#; + -- Device HNP enabled + DHNPEN : OTG_HS_GOTGCTL_DHNPEN_Field := 16#1#; -- unspecified - Reserved_19_31 : STM32F429x.UInt13 := 16#0#; + Reserved_12_15 : STM32F429x.UInt4 := 16#0#; + -- Read-only. Connector ID status + CIDSTS : OTG_HS_GOTGCTL_CIDSTS_Field := 16#0#; + -- Read-only. Long/short debounce time + DBCT : OTG_HS_GOTGCTL_DBCT_Field := 16#0#; + -- Read-only. A-session valid + ASVLD : OTG_HS_GOTGCTL_ASVLD_Field := 16#0#; + -- Read-only. B-session valid + BSVLD : OTG_HS_GOTGCTL_BSVLD_Field := 16#0#; + -- unspecified + Reserved_20_31 : STM32F429x.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HPRT_Register use record - PCSTS at 0 range 0 .. 0; - PCDET at 0 range 1 .. 1; - PENA at 0 range 2 .. 2; - PENCHNG at 0 range 3 .. 3; - POCA at 0 range 4 .. 4; - POCCHNG at 0 range 5 .. 5; - PRES at 0 range 6 .. 6; - PSUSP at 0 range 7 .. 7; - PRST at 0 range 8 .. 8; - Reserved_9_9 at 0 range 9 .. 9; - PLSTS at 0 range 10 .. 11; - PPWR at 0 range 12 .. 12; - PTCTL at 0 range 13 .. 16; - PSPD at 0 range 17 .. 18; - Reserved_19_31 at 0 range 19 .. 31; + for OTG_HS_GOTGCTL_Register use record + SRQSCS at 0 range 0 .. 0; + SRQ at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + HNGSCS at 0 range 8 .. 8; + HNPRQ at 0 range 9 .. 9; + HSHNPEN at 0 range 10 .. 10; + DHNPEN at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + CIDSTS at 0 range 16 .. 16; + DBCT at 0 range 17 .. 17; + ASVLD at 0 range 18 .. 18; + BSVLD at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - ---------------------------- - -- OTG_HS_HCCHAR_Register -- - ---------------------------- - - subtype OTG_HS_HCCHAR0_MPSIZ_Field is STM32F429x.UInt11; - subtype OTG_HS_HCCHAR0_EPNUM_Field is STM32F429x.UInt4; - subtype OTG_HS_HCCHAR0_EPDIR_Field is STM32F429x.Bit; - subtype OTG_HS_HCCHAR0_LSDEV_Field is STM32F429x.Bit; - subtype OTG_HS_HCCHAR0_EPTYP_Field is STM32F429x.UInt2; - subtype OTG_HS_HCCHAR0_MC_Field is STM32F429x.UInt2; - subtype OTG_HS_HCCHAR0_DAD_Field is STM32F429x.UInt7; - subtype OTG_HS_HCCHAR0_ODDFRM_Field is STM32F429x.Bit; - subtype OTG_HS_HCCHAR0_CHDIS_Field is STM32F429x.Bit; - subtype OTG_HS_HCCHAR0_CHENA_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGINT_SEDET_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGINT_SRSSCHG_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGINT_HNSSCHG_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGINT_HNGDET_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGINT_ADTOCHG_Field is STM32F429x.Bit; + subtype OTG_HS_GOTGINT_DBCDNE_Field is STM32F429x.Bit; - -- OTG_HS host channel-0 characteristics register - type OTG_HS_HCCHAR_Register is record - -- Maximum packet size - MPSIZ : OTG_HS_HCCHAR0_MPSIZ_Field := 16#0#; - -- Endpoint number - EPNUM : OTG_HS_HCCHAR0_EPNUM_Field := 16#0#; - -- Endpoint direction - EPDIR : OTG_HS_HCCHAR0_EPDIR_Field := 16#0#; + -- OTG_HS interrupt register + type OTG_HS_GOTGINT_Register is record -- unspecified - Reserved_16_16 : STM32F429x.Bit := 16#0#; - -- Low-speed device - LSDEV : OTG_HS_HCCHAR0_LSDEV_Field := 16#0#; - -- Endpoint type - EPTYP : OTG_HS_HCCHAR0_EPTYP_Field := 16#0#; - -- Multi Count (MC) / Error Count (EC) - MC : OTG_HS_HCCHAR0_MC_Field := 16#0#; - -- Device address - DAD : OTG_HS_HCCHAR0_DAD_Field := 16#0#; - -- Odd frame - ODDFRM : OTG_HS_HCCHAR0_ODDFRM_Field := 16#0#; - -- Channel disable - CHDIS : OTG_HS_HCCHAR0_CHDIS_Field := 16#0#; - -- Channel enable - CHENA : OTG_HS_HCCHAR0_CHENA_Field := 16#0#; + Reserved_0_1 : STM32F429x.UInt2 := 16#0#; + -- Session end detected + SEDET : OTG_HS_GOTGINT_SEDET_Field := 16#0#; + -- unspecified + Reserved_3_7 : STM32F429x.UInt5 := 16#0#; + -- Session request success status change + SRSSCHG : OTG_HS_GOTGINT_SRSSCHG_Field := 16#0#; + -- Host negotiation success status change + HNSSCHG : OTG_HS_GOTGINT_HNSSCHG_Field := 16#0#; + -- unspecified + Reserved_10_16 : STM32F429x.UInt7 := 16#0#; + -- Host negotiation detected + HNGDET : OTG_HS_GOTGINT_HNGDET_Field := 16#0#; + -- A-device timeout change + ADTOCHG : OTG_HS_GOTGINT_ADTOCHG_Field := 16#0#; + -- Debounce done + DBCDNE : OTG_HS_GOTGINT_DBCDNE_Field := 16#0#; + -- unspecified + Reserved_20_31 : STM32F429x.UInt12 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HCCHAR_Register use record - MPSIZ at 0 range 0 .. 10; - EPNUM at 0 range 11 .. 14; - EPDIR at 0 range 15 .. 15; - Reserved_16_16 at 0 range 16 .. 16; - LSDEV at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - MC at 0 range 20 .. 21; - DAD at 0 range 22 .. 28; - ODDFRM at 0 range 29 .. 29; - CHDIS at 0 range 30 .. 30; - CHENA at 0 range 31 .. 31; + for OTG_HS_GOTGINT_Register use record + Reserved_0_1 at 0 range 0 .. 1; + SEDET at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + SRSSCHG at 0 range 8 .. 8; + HNSSCHG at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + HNGDET at 0 range 17 .. 17; + ADTOCHG at 0 range 18 .. 18; + DBCDNE at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; end record; - ---------------------------- - -- OTG_HS_HCSPLT_Register -- - ---------------------------- - - subtype OTG_HS_HCSPLT0_PRTADDR_Field is STM32F429x.UInt7; - subtype OTG_HS_HCSPLT0_HUBADDR_Field is STM32F429x.UInt7; - subtype OTG_HS_HCSPLT0_XACTPOS_Field is STM32F429x.UInt2; - subtype OTG_HS_HCSPLT0_COMPLSPLT_Field is STM32F429x.Bit; - subtype OTG_HS_HCSPLT0_SPLITEN_Field is STM32F429x.Bit; + subtype OTG_HS_GAHBCFG_GINT_Field is STM32F429x.Bit; + subtype OTG_HS_GAHBCFG_HBSTLEN_Field is STM32F429x.UInt4; + subtype OTG_HS_GAHBCFG_DMAEN_Field is STM32F429x.Bit; + subtype OTG_HS_GAHBCFG_TXFELVL_Field is STM32F429x.Bit; + subtype OTG_HS_GAHBCFG_PTXFELVL_Field is STM32F429x.Bit; - -- OTG_HS host channel-0 split control register - type OTG_HS_HCSPLT_Register is record - -- Port address - PRTADDR : OTG_HS_HCSPLT0_PRTADDR_Field := 16#0#; - -- Hub address - HUBADDR : OTG_HS_HCSPLT0_HUBADDR_Field := 16#0#; - -- XACTPOS - XACTPOS : OTG_HS_HCSPLT0_XACTPOS_Field := 16#0#; - -- Do complete split - COMPLSPLT : OTG_HS_HCSPLT0_COMPLSPLT_Field := 16#0#; + -- OTG_HS AHB configuration register + type OTG_HS_GAHBCFG_Register is record + -- Global interrupt mask + GINT : OTG_HS_GAHBCFG_GINT_Field := 16#0#; + -- Burst length/type + HBSTLEN : OTG_HS_GAHBCFG_HBSTLEN_Field := 16#0#; + -- DMA enable + DMAEN : OTG_HS_GAHBCFG_DMAEN_Field := 16#0#; -- unspecified - Reserved_17_30 : STM32F429x.UInt14 := 16#0#; - -- Split enable - SPLITEN : OTG_HS_HCSPLT0_SPLITEN_Field := 16#0#; + Reserved_6_6 : STM32F429x.Bit := 16#0#; + -- TxFIFO empty level + TXFELVL : OTG_HS_GAHBCFG_TXFELVL_Field := 16#0#; + -- Periodic TxFIFO empty level + PTXFELVL : OTG_HS_GAHBCFG_PTXFELVL_Field := 16#0#; + -- unspecified + Reserved_9_31 : STM32F429x.UInt23 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for OTG_HS_HCSPLT_Register use record - PRTADDR at 0 range 0 .. 6; - HUBADDR at 0 range 7 .. 13; - XACTPOS at 0 range 14 .. 15; - COMPLSPLT at 0 range 16 .. 16; - Reserved_17_30 at 0 range 17 .. 30; - SPLITEN at 0 range 31 .. 31; - end record; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - --------------------------- - -- OTG_HS_HCINT_Register -- - --------------------------- - - subtype OTG_HS_HCINT0_XFRC_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_CHH_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_AHBERR_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_STALL_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_NAK_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_ACK_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_NYET_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_TXERR_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_BBERR_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_FRMOR_Field is STM32F429x.Bit; - subtype OTG_HS_HCINT0_DTERR_Field is STM32F429x.Bit; - - -- OTG_HS host channel-11 interrupt register - type OTG_HS_HCINT_Register is record - -- Transfer completed - XFRC : OTG_HS_HCINT0_XFRC_Field := 16#0#; - -- Channel halted - CHH : OTG_HS_HCINT0_CHH_Field := 16#0#; - -- AHB error - AHBERR : OTG_HS_HCINT0_AHBERR_Field := 16#0#; - -- STALL response received interrupt - STALL : OTG_HS_HCINT0_STALL_Field := 16#0#; - -- NAK response received interrupt - NAK : OTG_HS_HCINT0_NAK_Field := 16#0#; - -- ACK response received/transmitted interrupt - ACK : OTG_HS_HCINT0_ACK_Field := 16#0#; - -- Response received interrupt - NYET : OTG_HS_HCINT0_NYET_Field := 16#0#; - -- Transaction error - TXERR : OTG_HS_HCINT0_TXERR_Field := 16#0#; - -- Babble error - BBERR : OTG_HS_HCINT0_BBERR_Field := 16#0#; - -- Frame overrun - FRMOR : OTG_HS_HCINT0_FRMOR_Field := 16#0#; - -- Data toggle error - DTERR : OTG_HS_HCINT0_DTERR_Field := 16#0#; - -- unspecified - Reserved_11_31 : STM32F429x.UInt21 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for OTG_HS_HCINT_Register use record - XFRC at 0 range 0 .. 0; - CHH at 0 range 1 .. 1; - AHBERR at 0 range 2 .. 2; - STALL at 0 range 3 .. 3; - NAK at 0 range 4 .. 4; - ACK at 0 range 5 .. 5; - NYET at 0 range 6 .. 6; - TXERR at 0 range 7 .. 7; - BBERR at 0 range 8 .. 8; - FRMOR at 0 range 9 .. 9; - DTERR at 0 range 10 .. 10; - Reserved_11_31 at 0 range 11 .. 31; + for OTG_HS_GAHBCFG_Register use record + GINT at 0 range 0 .. 0; + HBSTLEN at 0 range 1 .. 4; + DMAEN at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + TXFELVL at 0 range 7 .. 7; + PTXFELVL at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; end record; - ------------------------------ - -- OTG_HS_HCINTMSK_Register -- - ------------------------------ - - subtype OTG_HS_HCINTMSK0_XFRCM_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_CHHM_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_AHBERR_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_STALLM_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_NAKM_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_ACKM_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_NYET_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_TXERRM_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_BBERRM_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_FRMORM_Field is STM32F429x.Bit; - subtype OTG_HS_HCINTMSK0_DTERRM_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_TOCAL_Field is STM32F429x.UInt3; + subtype OTG_HS_GUSBCFG_PHYSEL_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_SRPCAP_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_HNPCAP_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_TRDT_Field is STM32F429x.UInt4; + subtype OTG_HS_GUSBCFG_PHYLPCS_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_ULPIFSLS_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_ULPIAR_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_ULPICSM_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_ULPIEVBUSD_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_ULPIEVBUSI_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_TSDPS_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_PCCI_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_PTCI_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_ULPIIPD_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_FHMOD_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_FDMOD_Field is STM32F429x.Bit; + subtype OTG_HS_GUSBCFG_CTXPKT_Field is STM32F429x.Bit; - -- OTG_HS host channel-11 interrupt mask register - type OTG_HS_HCINTMSK_Register is record - -- Transfer completed mask - XFRCM : OTG_HS_HCINTMSK0_XFRCM_Field := 16#0#; - -- Channel halted mask - CHHM : OTG_HS_HCINTMSK0_CHHM_Field := 16#0#; - -- AHB error - AHBERR : OTG_HS_HCINTMSK0_AHBERR_Field := 16#0#; - -- STALL response received interrupt mask - STALLM : OTG_HS_HCINTMSK0_STALLM_Field := 16#0#; - -- NAK response received interrupt mask - NAKM : OTG_HS_HCINTMSK0_NAKM_Field := 16#0#; - -- ACK response received/transmitted interrupt mask - ACKM : OTG_HS_HCINTMSK0_ACKM_Field := 16#0#; - -- response received interrupt mask - NYET : OTG_HS_HCINTMSK0_NYET_Field := 16#0#; - -- Transaction error mask - TXERRM : OTG_HS_HCINTMSK0_TXERRM_Field := 16#0#; - -- Babble error mask - BBERRM : OTG_HS_HCINTMSK0_BBERRM_Field := 16#0#; - -- Frame overrun mask - FRMORM : OTG_HS_HCINTMSK0_FRMORM_Field := 16#0#; - -- Data toggle error mask - DTERRM : OTG_HS_HCINTMSK0_DTERRM_Field := 16#0#; + -- OTG_HS USB configuration register + type OTG_HS_GUSBCFG_Register is record + -- FS timeout calibration + TOCAL : OTG_HS_GUSBCFG_TOCAL_Field := 16#0#; -- unspecified - Reserved_11_31 : STM32F429x.UInt21 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for OTG_HS_HCINTMSK_Register use record - XFRCM at 0 range 0 .. 0; - CHHM at 0 range 1 .. 1; - AHBERR at 0 range 2 .. 2; - STALLM at 0 range 3 .. 3; - NAKM at 0 range 4 .. 4; - ACKM at 0 range 5 .. 5; - NYET at 0 range 6 .. 6; - TXERRM at 0 range 7 .. 7; - BBERRM at 0 range 8 .. 8; - FRMORM at 0 range 9 .. 9; - DTERRM at 0 range 10 .. 10; - Reserved_11_31 at 0 range 11 .. 31; - end record; - - ---------------------------- - -- OTG_HS_HCTSIZ_Register -- - ---------------------------- - - subtype OTG_HS_HCTSIZ0_XFRSIZ_Field is STM32F429x.UInt19; - subtype OTG_HS_HCTSIZ0_PKTCNT_Field is STM32F429x.UInt10; - subtype OTG_HS_HCTSIZ0_DPID_Field is STM32F429x.UInt2; - - -- OTG_HS host channel-11 transfer size register - type OTG_HS_HCTSIZ_Register is record - -- Transfer size - XFRSIZ : OTG_HS_HCTSIZ0_XFRSIZ_Field := 16#0#; - -- Packet count - PKTCNT : OTG_HS_HCTSIZ0_PKTCNT_Field := 16#0#; - -- Data PID - DPID : OTG_HS_HCTSIZ0_DPID_Field := 16#0#; + Reserved_3_5 : STM32F429x.UInt3 := 16#0#; + -- Write-only. USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial + -- transceiver select + PHYSEL : OTG_HS_GUSBCFG_PHYSEL_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F429x.Bit := 16#0#; + Reserved_7_7 : STM32F429x.Bit := 16#0#; + -- SRP-capable + SRPCAP : OTG_HS_GUSBCFG_SRPCAP_Field := 16#0#; + -- HNP-capable + HNPCAP : OTG_HS_GUSBCFG_HNPCAP_Field := 16#1#; + -- USB turnaround time + TRDT : OTG_HS_GUSBCFG_TRDT_Field := 16#2#; + -- unspecified + Reserved_14_14 : STM32F429x.Bit := 16#0#; + -- PHY Low-power clock select + PHYLPCS : OTG_HS_GUSBCFG_PHYLPCS_Field := 16#0#; + -- unspecified + Reserved_16_16 : STM32F429x.Bit := 16#0#; + -- ULPI FS/LS select + ULPIFSLS : OTG_HS_GUSBCFG_ULPIFSLS_Field := 16#0#; + -- ULPI Auto-resume + ULPIAR : OTG_HS_GUSBCFG_ULPIAR_Field := 16#0#; + -- ULPI Clock SuspendM + ULPICSM : OTG_HS_GUSBCFG_ULPICSM_Field := 16#0#; + -- ULPI External VBUS Drive + ULPIEVBUSD : OTG_HS_GUSBCFG_ULPIEVBUSD_Field := 16#0#; + -- ULPI external VBUS indicator + ULPIEVBUSI : OTG_HS_GUSBCFG_ULPIEVBUSI_Field := 16#0#; + -- TermSel DLine pulsing selection + TSDPS : OTG_HS_GUSBCFG_TSDPS_Field := 16#0#; + -- Indicator complement + PCCI : OTG_HS_GUSBCFG_PCCI_Field := 16#0#; + -- Indicator pass through + PTCI : OTG_HS_GUSBCFG_PTCI_Field := 16#0#; + -- ULPI interface protect disable + ULPIIPD : OTG_HS_GUSBCFG_ULPIIPD_Field := 16#0#; + -- unspecified + Reserved_26_28 : STM32F429x.UInt3 := 16#0#; + -- Forced host mode + FHMOD : OTG_HS_GUSBCFG_FHMOD_Field := 16#0#; + -- Forced peripheral mode + FDMOD : OTG_HS_GUSBCFG_FDMOD_Field := 16#0#; + -- Corrupt Tx packet + CTXPKT : OTG_HS_GUSBCFG_CTXPKT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_HCTSIZ_Register use record - XFRSIZ at 0 range 0 .. 18; - PKTCNT at 0 range 19 .. 28; - DPID at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for OTG_HS_GUSBCFG_Register use record + TOCAL at 0 range 0 .. 2; + Reserved_3_5 at 0 range 3 .. 5; + PHYSEL at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + SRPCAP at 0 range 8 .. 8; + HNPCAP at 0 range 9 .. 9; + TRDT at 0 range 10 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + PHYLPCS at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + ULPIFSLS at 0 range 17 .. 17; + ULPIAR at 0 range 18 .. 18; + ULPICSM at 0 range 19 .. 19; + ULPIEVBUSD at 0 range 20 .. 20; + ULPIEVBUSI at 0 range 21 .. 21; + TSDPS at 0 range 22 .. 22; + PCCI at 0 range 23 .. 23; + PTCI at 0 range 24 .. 24; + ULPIIPD at 0 range 25 .. 25; + Reserved_26_28 at 0 range 26 .. 28; + FHMOD at 0 range 29 .. 29; + FDMOD at 0 range 30 .. 30; + CTXPKT at 0 range 31 .. 31; end record; - -------------------------- - -- OTG_HS_DCFG_Register -- - -------------------------- - - subtype OTG_HS_DCFG_DSPD_Field is STM32F429x.UInt2; - subtype OTG_HS_DCFG_NZLSOHSK_Field is STM32F429x.Bit; - subtype OTG_HS_DCFG_DAD_Field is STM32F429x.UInt7; - subtype OTG_HS_DCFG_PFIVL_Field is STM32F429x.UInt2; - subtype OTG_HS_DCFG_PERSCHIVL_Field is STM32F429x.UInt2; + subtype OTG_HS_GRSTCTL_CSRST_Field is STM32F429x.Bit; + subtype OTG_HS_GRSTCTL_HSRST_Field is STM32F429x.Bit; + subtype OTG_HS_GRSTCTL_FCRST_Field is STM32F429x.Bit; + subtype OTG_HS_GRSTCTL_RXFFLSH_Field is STM32F429x.Bit; + subtype OTG_HS_GRSTCTL_TXFFLSH_Field is STM32F429x.Bit; + subtype OTG_HS_GRSTCTL_TXFNUM_Field is STM32F429x.UInt5; + subtype OTG_HS_GRSTCTL_DMAREQ_Field is STM32F429x.Bit; + subtype OTG_HS_GRSTCTL_AHBIDL_Field is STM32F429x.Bit; - -- OTG_HS device configuration register - type OTG_HS_DCFG_Register is record - -- Device speed - DSPD : OTG_HS_DCFG_DSPD_Field := 16#0#; - -- Nonzero-length status OUT handshake - NZLSOHSK : OTG_HS_DCFG_NZLSOHSK_Field := 16#0#; + -- OTG_HS reset register + type OTG_HS_GRSTCTL_Register is record + -- Core soft reset + CSRST : OTG_HS_GRSTCTL_CSRST_Field := 16#0#; + -- HCLK soft reset + HSRST : OTG_HS_GRSTCTL_HSRST_Field := 16#0#; + -- Host frame counter reset + FCRST : OTG_HS_GRSTCTL_FCRST_Field := 16#0#; -- unspecified Reserved_3_3 : STM32F429x.Bit := 16#0#; - -- Device address - DAD : OTG_HS_DCFG_DAD_Field := 16#0#; - -- Periodic (micro)frame interval - PFIVL : OTG_HS_DCFG_PFIVL_Field := 16#0#; - -- unspecified - Reserved_13_23 : STM32F429x.UInt11 := 16#100#; - -- Periodic scheduling interval - PERSCHIVL : OTG_HS_DCFG_PERSCHIVL_Field := 16#2#; + -- RxFIFO flush + RXFFLSH : OTG_HS_GRSTCTL_RXFFLSH_Field := 16#0#; + -- TxFIFO flush + TXFFLSH : OTG_HS_GRSTCTL_TXFFLSH_Field := 16#0#; + -- TxFIFO number + TXFNUM : OTG_HS_GRSTCTL_TXFNUM_Field := 16#0#; -- unspecified - Reserved_26_31 : STM32F429x.UInt6 := 16#0#; + Reserved_11_29 : STM32F429x.UInt19 := 16#40000#; + -- Read-only. DMA request signal + DMAREQ : OTG_HS_GRSTCTL_DMAREQ_Field := 16#0#; + -- Read-only. AHB master idle + AHBIDL : OTG_HS_GRSTCTL_AHBIDL_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DCFG_Register use record - DSPD at 0 range 0 .. 1; - NZLSOHSK at 0 range 2 .. 2; + for OTG_HS_GRSTCTL_Register use record + CSRST at 0 range 0 .. 0; + HSRST at 0 range 1 .. 1; + FCRST at 0 range 2 .. 2; Reserved_3_3 at 0 range 3 .. 3; - DAD at 0 range 4 .. 10; - PFIVL at 0 range 11 .. 12; - Reserved_13_23 at 0 range 13 .. 23; - PERSCHIVL at 0 range 24 .. 25; - Reserved_26_31 at 0 range 26 .. 31; + RXFFLSH at 0 range 4 .. 4; + TXFFLSH at 0 range 5 .. 5; + TXFNUM at 0 range 6 .. 10; + Reserved_11_29 at 0 range 11 .. 29; + DMAREQ at 0 range 30 .. 30; + AHBIDL at 0 range 31 .. 31; end record; - -------------------------- - -- OTG_HS_DCTL_Register -- - -------------------------- + subtype OTG_HS_GINTSTS_CMOD_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_MMIS_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_OTGINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_SOF_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_RXFLVL_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_NPTXFE_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_GINAKEFF_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_BOUTNAKEFF_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_ESUSP_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_USBSUSP_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_USBRST_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_ENUMDNE_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_ISOODRP_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_EOPF_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_IEPINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_OEPINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_IISOIXFR_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_DATAFSUSP_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_HPRTINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_HCINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_PTXFE_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_CIDSCHG_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_DISCINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_SRQINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTSTS_WKUINT_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_RWUSIG_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_SDIS_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_GINSTS_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_GONSTS_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_TCTL_Field is STM32F429x.UInt3; - subtype OTG_HS_DCTL_SGINAK_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_CGINAK_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_SGONAK_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_CGONAK_Field is STM32F429x.Bit; - subtype OTG_HS_DCTL_POPRGDNE_Field is STM32F429x.Bit; - - -- OTG_HS device control register - type OTG_HS_DCTL_Register is record - -- Remote wakeup signaling - RWUSIG : OTG_HS_DCTL_RWUSIG_Field := 16#0#; - -- Soft disconnect - SDIS : OTG_HS_DCTL_SDIS_Field := 16#0#; - -- Global IN NAK status - GINSTS : OTG_HS_DCTL_GINSTS_Field := 16#0#; - -- Global OUT NAK status - GONSTS : OTG_HS_DCTL_GONSTS_Field := 16#0#; - -- Test control - TCTL : OTG_HS_DCTL_TCTL_Field := 16#0#; - -- Set global IN NAK - SGINAK : OTG_HS_DCTL_SGINAK_Field := 16#0#; - -- Clear global IN NAK - CGINAK : OTG_HS_DCTL_CGINAK_Field := 16#0#; - -- Set global OUT NAK - SGONAK : OTG_HS_DCTL_SGONAK_Field := 16#0#; - -- Clear global OUT NAK - CGONAK : OTG_HS_DCTL_CGONAK_Field := 16#0#; - -- Power-on programming done - POPRGDNE : OTG_HS_DCTL_POPRGDNE_Field := 16#0#; + -- OTG_HS core interrupt register + type OTG_HS_GINTSTS_Register is record + -- Read-only. Current mode of operation + CMOD : OTG_HS_GINTSTS_CMOD_Field := 16#0#; + -- Mode mismatch interrupt + MMIS : OTG_HS_GINTSTS_MMIS_Field := 16#0#; + -- Read-only. OTG interrupt + OTGINT : OTG_HS_GINTSTS_OTGINT_Field := 16#0#; + -- Start of frame + SOF : OTG_HS_GINTSTS_SOF_Field := 16#0#; + -- Read-only. RxFIFO nonempty + RXFLVL : OTG_HS_GINTSTS_RXFLVL_Field := 16#0#; + -- Read-only. Nonperiodic TxFIFO empty + NPTXFE : OTG_HS_GINTSTS_NPTXFE_Field := 16#1#; + -- Read-only. Global IN nonperiodic NAK effective + GINAKEFF : OTG_HS_GINTSTS_GINAKEFF_Field := 16#0#; + -- Read-only. Global OUT NAK effective + BOUTNAKEFF : OTG_HS_GINTSTS_BOUTNAKEFF_Field := 16#0#; -- unspecified - Reserved_12_31 : STM32F429x.UInt20 := 16#0#; - end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; - - for OTG_HS_DCTL_Register use record - RWUSIG at 0 range 0 .. 0; - SDIS at 0 range 1 .. 1; - GINSTS at 0 range 2 .. 2; - GONSTS at 0 range 3 .. 3; - TCTL at 0 range 4 .. 6; - SGINAK at 0 range 7 .. 7; - CGINAK at 0 range 8 .. 8; - SGONAK at 0 range 9 .. 9; - CGONAK at 0 range 10 .. 10; - POPRGDNE at 0 range 11 .. 11; - Reserved_12_31 at 0 range 12 .. 31; - end record; - - -------------------------- - -- OTG_HS_DSTS_Register -- - -------------------------- - - subtype OTG_HS_DSTS_SUSPSTS_Field is STM32F429x.Bit; - subtype OTG_HS_DSTS_ENUMSPD_Field is STM32F429x.UInt2; - subtype OTG_HS_DSTS_EERR_Field is STM32F429x.Bit; - subtype OTG_HS_DSTS_FNSOF_Field is STM32F429x.UInt14; - - -- OTG_HS device status register - type OTG_HS_DSTS_Register is record - -- Suspend status - SUSPSTS : OTG_HS_DSTS_SUSPSTS_Field; - -- Enumerated speed - ENUMSPD : OTG_HS_DSTS_ENUMSPD_Field; - -- Erratic error - EERR : OTG_HS_DSTS_EERR_Field; + Reserved_8_9 : STM32F429x.UInt2 := 16#0#; + -- Early suspend + ESUSP : OTG_HS_GINTSTS_ESUSP_Field := 16#0#; + -- USB suspend + USBSUSP : OTG_HS_GINTSTS_USBSUSP_Field := 16#0#; + -- USB reset + USBRST : OTG_HS_GINTSTS_USBRST_Field := 16#0#; + -- Enumeration done + ENUMDNE : OTG_HS_GINTSTS_ENUMDNE_Field := 16#0#; + -- Isochronous OUT packet dropped interrupt + ISOODRP : OTG_HS_GINTSTS_ISOODRP_Field := 16#0#; + -- End of periodic frame interrupt + EOPF : OTG_HS_GINTSTS_EOPF_Field := 16#0#; -- unspecified - Reserved_4_7 : STM32F429x.UInt4; - -- Frame number of the received SOF - FNSOF : OTG_HS_DSTS_FNSOF_Field; + Reserved_16_17 : STM32F429x.UInt2 := 16#0#; + -- Read-only. IN endpoint interrupt + IEPINT : OTG_HS_GINTSTS_IEPINT_Field := 16#0#; + -- Read-only. OUT endpoint interrupt + OEPINT : OTG_HS_GINTSTS_OEPINT_Field := 16#0#; + -- Incomplete isochronous IN transfer + IISOIXFR : OTG_HS_GINTSTS_IISOIXFR_Field := 16#0#; + -- Incomplete periodic transfer + PXFR_INCOMPISOOUT : OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Field := 16#0#; + -- Data fetch suspended + DATAFSUSP : OTG_HS_GINTSTS_DATAFSUSP_Field := 16#0#; -- unspecified - Reserved_22_31 : STM32F429x.UInt10; + Reserved_23_23 : STM32F429x.Bit := 16#0#; + -- Read-only. Host port interrupt + HPRTINT : OTG_HS_GINTSTS_HPRTINT_Field := 16#0#; + -- Read-only. Host channels interrupt + HCINT : OTG_HS_GINTSTS_HCINT_Field := 16#0#; + -- Read-only. Periodic TxFIFO empty + PTXFE : OTG_HS_GINTSTS_PTXFE_Field := 16#1#; + -- unspecified + Reserved_27_27 : STM32F429x.Bit := 16#0#; + -- Connector ID status change + CIDSCHG : OTG_HS_GINTSTS_CIDSCHG_Field := 16#0#; + -- Disconnect detected interrupt + DISCINT : OTG_HS_GINTSTS_DISCINT_Field := 16#0#; + -- Session request/new session detected interrupt + SRQINT : OTG_HS_GINTSTS_SRQINT_Field := 16#0#; + -- Resume/remote wakeup detected interrupt + WKUINT : OTG_HS_GINTSTS_WKUINT_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DSTS_Register use record - SUSPSTS at 0 range 0 .. 0; - ENUMSPD at 0 range 1 .. 2; - EERR at 0 range 3 .. 3; - Reserved_4_7 at 0 range 4 .. 7; - FNSOF at 0 range 8 .. 21; - Reserved_22_31 at 0 range 22 .. 31; + for OTG_HS_GINTSTS_Register use record + CMOD at 0 range 0 .. 0; + MMIS at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOF at 0 range 3 .. 3; + RXFLVL at 0 range 4 .. 4; + NPTXFE at 0 range 5 .. 5; + GINAKEFF at 0 range 6 .. 6; + BOUTNAKEFF at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSP at 0 range 10 .. 10; + USBSUSP at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNE at 0 range 13 .. 13; + ISOODRP at 0 range 14 .. 14; + EOPF at 0 range 15 .. 15; + Reserved_16_17 at 0 range 16 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFR at 0 range 20 .. 20; + PXFR_INCOMPISOOUT at 0 range 21 .. 21; + DATAFSUSP at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + HPRTINT at 0 range 24 .. 24; + HCINT at 0 range 25 .. 25; + PTXFE at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHG at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQINT at 0 range 30 .. 30; + WKUINT at 0 range 31 .. 31; end record; - ----------------------------- - -- OTG_HS_DIEPMSK_Register -- - ----------------------------- - - subtype OTG_HS_DIEPMSK_XFRCM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPMSK_EPDM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPMSK_TOM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPMSK_ITTXFEMSK_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPMSK_INEPNMM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPMSK_INEPNEM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPMSK_TXFURM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPMSK_BIM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_MMISM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_OTGINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_SOFM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_RXFLVLM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_NPTXFEM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_GINAKEFFM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_GONAKEFFM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_ESUSPM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_USBSUSPM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_USBRST_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_ENUMDNEM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_ISOODRPM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_EOPFM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_EPMISM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_IEPINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_OEPINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_IISOIXFRM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_FSUSPM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_PRTIM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_HCIM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_PTXFEM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_CIDSCHGM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_DISCINT_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_SRQIM_Field is STM32F429x.Bit; + subtype OTG_HS_GINTMSK_WUIM_Field is STM32F429x.Bit; - -- OTG_HS device IN endpoint common interrupt mask register - type OTG_HS_DIEPMSK_Register is record - -- Transfer completed interrupt mask - XFRCM : OTG_HS_DIEPMSK_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : OTG_HS_DIEPMSK_EPDM_Field := 16#0#; + -- OTG_HS interrupt mask register + type OTG_HS_GINTMSK_Register is record -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- Timeout condition mask (nonisochronous endpoints) - TOM : OTG_HS_DIEPMSK_TOM_Field := 16#0#; - -- IN token received when TxFIFO empty mask - ITTXFEMSK : OTG_HS_DIEPMSK_ITTXFEMSK_Field := 16#0#; - -- IN token received with EP mismatch mask - INEPNMM : OTG_HS_DIEPMSK_INEPNMM_Field := 16#0#; - -- IN endpoint NAK effective mask - INEPNEM : OTG_HS_DIEPMSK_INEPNEM_Field := 16#0#; + Reserved_0_0 : STM32F429x.Bit := 16#0#; + -- Mode mismatch interrupt mask + MMISM : OTG_HS_GINTMSK_MMISM_Field := 16#0#; + -- OTG interrupt mask + OTGINT : OTG_HS_GINTMSK_OTGINT_Field := 16#0#; + -- Start of frame mask + SOFM : OTG_HS_GINTMSK_SOFM_Field := 16#0#; + -- Receive FIFO nonempty mask + RXFLVLM : OTG_HS_GINTMSK_RXFLVLM_Field := 16#0#; + -- Nonperiodic TxFIFO empty mask + NPTXFEM : OTG_HS_GINTMSK_NPTXFEM_Field := 16#0#; + -- Global nonperiodic IN NAK effective mask + GINAKEFFM : OTG_HS_GINTMSK_GINAKEFFM_Field := 16#0#; + -- Global OUT NAK effective mask + GONAKEFFM : OTG_HS_GINTMSK_GONAKEFFM_Field := 16#0#; -- unspecified - Reserved_7_7 : STM32F429x.Bit := 16#0#; - -- FIFO underrun mask - TXFURM : OTG_HS_DIEPMSK_TXFURM_Field := 16#0#; - -- BNA interrupt mask - BIM : OTG_HS_DIEPMSK_BIM_Field := 16#0#; + Reserved_8_9 : STM32F429x.UInt2 := 16#0#; + -- Early suspend mask + ESUSPM : OTG_HS_GINTMSK_ESUSPM_Field := 16#0#; + -- USB suspend mask + USBSUSPM : OTG_HS_GINTMSK_USBSUSPM_Field := 16#0#; + -- USB reset mask + USBRST : OTG_HS_GINTMSK_USBRST_Field := 16#0#; + -- Enumeration done mask + ENUMDNEM : OTG_HS_GINTMSK_ENUMDNEM_Field := 16#0#; + -- Isochronous OUT packet dropped interrupt mask + ISOODRPM : OTG_HS_GINTMSK_ISOODRPM_Field := 16#0#; + -- End of periodic frame interrupt mask + EOPFM : OTG_HS_GINTMSK_EOPFM_Field := 16#0#; -- unspecified - Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + Reserved_16_16 : STM32F429x.Bit := 16#0#; + -- Endpoint mismatch interrupt mask + EPMISM : OTG_HS_GINTMSK_EPMISM_Field := 16#0#; + -- IN endpoints interrupt mask + IEPINT : OTG_HS_GINTMSK_IEPINT_Field := 16#0#; + -- OUT endpoints interrupt mask + OEPINT : OTG_HS_GINTMSK_OEPINT_Field := 16#0#; + -- Incomplete isochronous IN transfer mask + IISOIXFRM : OTG_HS_GINTMSK_IISOIXFRM_Field := 16#0#; + -- Incomplete periodic transfer mask + PXFRM_IISOOXFRM : OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Field := 16#0#; + -- Data fetch suspended mask + FSUSPM : OTG_HS_GINTMSK_FSUSPM_Field := 16#0#; + -- unspecified + Reserved_23_23 : STM32F429x.Bit := 16#0#; + -- Read-only. Host port interrupt mask + PRTIM : OTG_HS_GINTMSK_PRTIM_Field := 16#0#; + -- Host channels interrupt mask + HCIM : OTG_HS_GINTMSK_HCIM_Field := 16#0#; + -- Periodic TxFIFO empty mask + PTXFEM : OTG_HS_GINTMSK_PTXFEM_Field := 16#0#; + -- unspecified + Reserved_27_27 : STM32F429x.Bit := 16#0#; + -- Connector ID status change mask + CIDSCHGM : OTG_HS_GINTMSK_CIDSCHGM_Field := 16#0#; + -- Disconnect detected interrupt mask + DISCINT : OTG_HS_GINTMSK_DISCINT_Field := 16#0#; + -- Session request/new session detected interrupt mask + SRQIM : OTG_HS_GINTMSK_SRQIM_Field := 16#0#; + -- Resume/remote wakeup detected interrupt mask + WUIM : OTG_HS_GINTMSK_WUIM_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPMSK_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOM at 0 range 3 .. 3; - ITTXFEMSK at 0 range 4 .. 4; - INEPNMM at 0 range 5 .. 5; - INEPNEM at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - TXFURM at 0 range 8 .. 8; - BIM at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + for OTG_HS_GINTMSK_Register use record + Reserved_0_0 at 0 range 0 .. 0; + MMISM at 0 range 1 .. 1; + OTGINT at 0 range 2 .. 2; + SOFM at 0 range 3 .. 3; + RXFLVLM at 0 range 4 .. 4; + NPTXFEM at 0 range 5 .. 5; + GINAKEFFM at 0 range 6 .. 6; + GONAKEFFM at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ESUSPM at 0 range 10 .. 10; + USBSUSPM at 0 range 11 .. 11; + USBRST at 0 range 12 .. 12; + ENUMDNEM at 0 range 13 .. 13; + ISOODRPM at 0 range 14 .. 14; + EOPFM at 0 range 15 .. 15; + Reserved_16_16 at 0 range 16 .. 16; + EPMISM at 0 range 17 .. 17; + IEPINT at 0 range 18 .. 18; + OEPINT at 0 range 19 .. 19; + IISOIXFRM at 0 range 20 .. 20; + PXFRM_IISOOXFRM at 0 range 21 .. 21; + FSUSPM at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + PRTIM at 0 range 24 .. 24; + HCIM at 0 range 25 .. 25; + PTXFEM at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + CIDSCHGM at 0 range 28 .. 28; + DISCINT at 0 range 29 .. 29; + SRQIM at 0 range 30 .. 30; + WUIM at 0 range 31 .. 31; end record; - ----------------------------- - -- OTG_HS_DOEPMSK_Register -- - ----------------------------- + subtype OTG_HS_GRXSTSR_Host_CHNUM_Field is STM32F429x.UInt4; + subtype OTG_HS_GRXSTSR_Host_BCNT_Field is STM32F429x.UInt11; + subtype OTG_HS_GRXSTSR_Host_DPID_Field is STM32F429x.UInt2; + subtype OTG_HS_GRXSTSR_Host_PKTSTS_Field is STM32F429x.UInt4; + + -- OTG_HS Receive status debug read register (host mode) + type OTG_HS_GRXSTSR_Host_Register is record + -- Read-only. Channel number + CHNUM : OTG_HS_GRXSTSR_Host_CHNUM_Field; + -- Read-only. Byte count + BCNT : OTG_HS_GRXSTSR_Host_BCNT_Field; + -- Read-only. Data PID + DPID : OTG_HS_GRXSTSR_Host_DPID_Field; + -- Read-only. Packet status + PKTSTS : OTG_HS_GRXSTSR_Host_PKTSTS_Field; + -- unspecified + Reserved_21_31 : STM32F429x.UInt11; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; + + for OTG_HS_GRXSTSR_Host_Register use record + CHNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; - subtype OTG_HS_DOEPMSK_XFRCM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPMSK_EPDM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPMSK_STUPM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPMSK_OTEPDM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPMSK_B2BSTUP_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPMSK_OPEM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPMSK_BOIM_Field is STM32F429x.Bit; + subtype OTG_HS_GRXSTSR_Peripheral_EPNUM_Field is STM32F429x.UInt4; + subtype OTG_HS_GRXSTSR_Peripheral_BCNT_Field is STM32F429x.UInt11; + subtype OTG_HS_GRXSTSR_Peripheral_DPID_Field is STM32F429x.UInt2; + subtype OTG_HS_GRXSTSR_Peripheral_PKTSTS_Field is STM32F429x.UInt4; + subtype OTG_HS_GRXSTSR_Peripheral_FRMNUM_Field is STM32F429x.UInt4; - -- OTG_HS device OUT endpoint common interrupt mask register - type OTG_HS_DOEPMSK_Register is record - -- Transfer completed interrupt mask - XFRCM : OTG_HS_DOEPMSK_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : OTG_HS_DOEPMSK_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- SETUP phase done mask - STUPM : OTG_HS_DOEPMSK_STUPM_Field := 16#0#; - -- OUT token received when endpoint disabled mask - OTEPDM : OTG_HS_DOEPMSK_OTEPDM_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F429x.Bit := 16#0#; - -- Back-to-back SETUP packets received mask - B2BSTUP : OTG_HS_DOEPMSK_B2BSTUP_Field := 16#0#; - -- unspecified - Reserved_7_7 : STM32F429x.Bit := 16#0#; - -- OUT packet error mask - OPEM : OTG_HS_DOEPMSK_OPEM_Field := 16#0#; - -- BNA interrupt mask - BOIM : OTG_HS_DOEPMSK_BOIM_Field := 16#0#; + -- OTG_HS Receive status debug read register (peripheral mode mode) + type OTG_HS_GRXSTSR_Peripheral_Register is record + -- Read-only. Endpoint number + EPNUM : OTG_HS_GRXSTSR_Peripheral_EPNUM_Field; + -- Read-only. Byte count + BCNT : OTG_HS_GRXSTSR_Peripheral_BCNT_Field; + -- Read-only. Data PID + DPID : OTG_HS_GRXSTSR_Peripheral_DPID_Field; + -- Read-only. Packet status + PKTSTS : OTG_HS_GRXSTSR_Peripheral_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : OTG_HS_GRXSTSR_Peripheral_FRMNUM_Field; -- unspecified - Reserved_10_31 : STM32F429x.UInt22 := 16#0#; + Reserved_25_31 : STM32F429x.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPMSK_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STUPM at 0 range 3 .. 3; - OTEPDM at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - B2BSTUP at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - OPEM at 0 range 8 .. 8; - BOIM at 0 range 9 .. 9; - Reserved_10_31 at 0 range 10 .. 31; + for OTG_HS_GRXSTSR_Peripheral_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; end record; - --------------------------- - -- OTG_HS_DAINT_Register -- - --------------------------- - - subtype OTG_HS_DAINT_IEPINT_Field is STM32F429x.Short; - subtype OTG_HS_DAINT_OEPINT_Field is STM32F429x.Short; + subtype OTG_HS_GRXSTSP_Host_CHNUM_Field is STM32F429x.UInt4; + subtype OTG_HS_GRXSTSP_Host_BCNT_Field is STM32F429x.UInt11; + subtype OTG_HS_GRXSTSP_Host_DPID_Field is STM32F429x.UInt2; + subtype OTG_HS_GRXSTSP_Host_PKTSTS_Field is STM32F429x.UInt4; - -- OTG_HS device all endpoints interrupt register - type OTG_HS_DAINT_Register is record - -- IN endpoint interrupt bits - IEPINT : OTG_HS_DAINT_IEPINT_Field; - -- OUT endpoint interrupt bits - OEPINT : OTG_HS_DAINT_OEPINT_Field; + -- OTG_HS status read and pop register (host mode) + type OTG_HS_GRXSTSP_Host_Register is record + -- Read-only. Channel number + CHNUM : OTG_HS_GRXSTSP_Host_CHNUM_Field; + -- Read-only. Byte count + BCNT : OTG_HS_GRXSTSP_Host_BCNT_Field; + -- Read-only. Data PID + DPID : OTG_HS_GRXSTSP_Host_DPID_Field; + -- Read-only. Packet status + PKTSTS : OTG_HS_GRXSTSP_Host_PKTSTS_Field; + -- unspecified + Reserved_21_31 : STM32F429x.UInt11; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DAINT_Register use record - IEPINT at 0 range 0 .. 15; - OEPINT at 0 range 16 .. 31; + for OTG_HS_GRXSTSP_Host_Register use record + CHNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + Reserved_21_31 at 0 range 21 .. 31; end record; - ------------------------------ - -- OTG_HS_DAINTMSK_Register -- - ------------------------------ - - subtype OTG_HS_DAINTMSK_IEPM_Field is STM32F429x.Short; - subtype OTG_HS_DAINTMSK_OEPM_Field is STM32F429x.Short; + subtype OTG_HS_GRXSTSP_Peripheral_EPNUM_Field is STM32F429x.UInt4; + subtype OTG_HS_GRXSTSP_Peripheral_BCNT_Field is STM32F429x.UInt11; + subtype OTG_HS_GRXSTSP_Peripheral_DPID_Field is STM32F429x.UInt2; + subtype OTG_HS_GRXSTSP_Peripheral_PKTSTS_Field is STM32F429x.UInt4; + subtype OTG_HS_GRXSTSP_Peripheral_FRMNUM_Field is STM32F429x.UInt4; - -- OTG_HS all endpoints interrupt mask register - type OTG_HS_DAINTMSK_Register is record - -- IN EP interrupt mask bits - IEPM : OTG_HS_DAINTMSK_IEPM_Field := 16#0#; - -- OUT EP interrupt mask bits - OEPM : OTG_HS_DAINTMSK_OEPM_Field := 16#0#; + -- OTG_HS status read and pop register (peripheral mode) + type OTG_HS_GRXSTSP_Peripheral_Register is record + -- Read-only. Endpoint number + EPNUM : OTG_HS_GRXSTSP_Peripheral_EPNUM_Field; + -- Read-only. Byte count + BCNT : OTG_HS_GRXSTSP_Peripheral_BCNT_Field; + -- Read-only. Data PID + DPID : OTG_HS_GRXSTSP_Peripheral_DPID_Field; + -- Read-only. Packet status + PKTSTS : OTG_HS_GRXSTSP_Peripheral_PKTSTS_Field; + -- Read-only. Frame number + FRMNUM : OTG_HS_GRXSTSP_Peripheral_FRMNUM_Field; + -- unspecified + Reserved_25_31 : STM32F429x.UInt7; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DAINTMSK_Register use record - IEPM at 0 range 0 .. 15; - OEPM at 0 range 16 .. 31; + for OTG_HS_GRXSTSP_Peripheral_Register use record + EPNUM at 0 range 0 .. 3; + BCNT at 0 range 4 .. 14; + DPID at 0 range 15 .. 16; + PKTSTS at 0 range 17 .. 20; + FRMNUM at 0 range 21 .. 24; + Reserved_25_31 at 0 range 25 .. 31; end record; - ------------------------------ - -- OTG_HS_DVBUSDIS_Register -- - ------------------------------ - - subtype OTG_HS_DVBUSDIS_VBUSDT_Field is STM32F429x.Short; + subtype OTG_HS_GRXFSIZ_RXFD_Field is STM32F429x.UInt16; - -- OTG_HS device VBUS discharge time register - type OTG_HS_DVBUSDIS_Register is record - -- Device VBUS discharge time - VBUSDT : OTG_HS_DVBUSDIS_VBUSDT_Field := 16#17D7#; + -- OTG_HS Receive FIFO size register + type OTG_HS_GRXFSIZ_Register is record + -- RxFIFO depth + RXFD : OTG_HS_GRXFSIZ_RXFD_Field := 16#200#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DVBUSDIS_Register use record - VBUSDT at 0 range 0 .. 15; + for OTG_HS_GRXFSIZ_Register use record + RXFD at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - -------------------------------- - -- OTG_HS_DVBUSPULSE_Register -- - -------------------------------- + subtype OTG_HS_GNPTXFSIZ_Host_NPTXFSA_Field is STM32F429x.UInt16; + subtype OTG_HS_GNPTXFSIZ_Host_NPTXFD_Field is STM32F429x.UInt16; - subtype OTG_HS_DVBUSPULSE_DVBUSP_Field is STM32F429x.UInt12; - - -- OTG_HS device VBUS pulsing time register - type OTG_HS_DVBUSPULSE_Register is record - -- Device VBUS pulsing time - DVBUSP : OTG_HS_DVBUSPULSE_DVBUSP_Field := 16#5B8#; - -- unspecified - Reserved_12_31 : STM32F429x.UInt20 := 16#0#; + -- OTG_HS nonperiodic transmit FIFO size register (host mode) + type OTG_HS_GNPTXFSIZ_Host_Register is record + -- Nonperiodic transmit RAM start address + NPTXFSA : OTG_HS_GNPTXFSIZ_Host_NPTXFSA_Field := 16#200#; + -- Nonperiodic TxFIFO depth + NPTXFD : OTG_HS_GNPTXFSIZ_Host_NPTXFD_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DVBUSPULSE_Register use record - DVBUSP at 0 range 0 .. 11; - Reserved_12_31 at 0 range 12 .. 31; + for OTG_HS_GNPTXFSIZ_Host_Register use record + NPTXFSA at 0 range 0 .. 15; + NPTXFD at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_DTHRCTL_Register -- - ----------------------------- + subtype OTG_HS_TX0FSIZ_Peripheral_TX0FSA_Field is STM32F429x.UInt16; + subtype OTG_HS_TX0FSIZ_Peripheral_TX0FD_Field is STM32F429x.UInt16; - subtype OTG_HS_DTHRCTL_NONISOTHREN_Field is STM32F429x.Bit; - subtype OTG_HS_DTHRCTL_ISOTHREN_Field is STM32F429x.Bit; - subtype OTG_HS_DTHRCTL_TXTHRLEN_Field is STM32F429x.UInt9; - subtype OTG_HS_DTHRCTL_RXTHREN_Field is STM32F429x.Bit; - subtype OTG_HS_DTHRCTL_RXTHRLEN_Field is STM32F429x.UInt9; - subtype OTG_HS_DTHRCTL_ARPEN_Field is STM32F429x.Bit; + -- Endpoint 0 transmit FIFO size (peripheral mode) + type OTG_HS_TX0FSIZ_Peripheral_Register is record + -- Endpoint 0 transmit RAM start address + TX0FSA : OTG_HS_TX0FSIZ_Peripheral_TX0FSA_Field := 16#200#; + -- Endpoint 0 TxFIFO depth + TX0FD : OTG_HS_TX0FSIZ_Peripheral_TX0FD_Field := 16#0#; + end record + with Object_Size => 32, Bit_Order => System.Low_Order_First; - -- OTG_HS Device threshold control register - type OTG_HS_DTHRCTL_Register is record - -- Nonisochronous IN endpoints threshold enable - NONISOTHREN : OTG_HS_DTHRCTL_NONISOTHREN_Field := 16#0#; - -- ISO IN endpoint threshold enable - ISOTHREN : OTG_HS_DTHRCTL_ISOTHREN_Field := 16#0#; - -- Transmit threshold length - TXTHRLEN : OTG_HS_DTHRCTL_TXTHRLEN_Field := 16#0#; - -- unspecified - Reserved_11_15 : STM32F429x.UInt5 := 16#0#; - -- Receive threshold enable - RXTHREN : OTG_HS_DTHRCTL_RXTHREN_Field := 16#0#; - -- Receive threshold length - RXTHRLEN : OTG_HS_DTHRCTL_RXTHRLEN_Field := 16#0#; - -- unspecified - Reserved_26_26 : STM32F429x.Bit := 16#0#; - -- Arbiter parking enable - ARPEN : OTG_HS_DTHRCTL_ARPEN_Field := 16#0#; + for OTG_HS_TX0FSIZ_Peripheral_Register use record + TX0FSA at 0 range 0 .. 15; + TX0FD at 0 range 16 .. 31; + end record; + + subtype OTG_HS_GNPTXSTS_NPTXFSAV_Field is STM32F429x.UInt16; + subtype OTG_HS_GNPTXSTS_NPTQXSAV_Field is STM32F429x.Byte; + subtype OTG_HS_GNPTXSTS_NPTXQTOP_Field is STM32F429x.UInt7; + + -- OTG_HS nonperiodic transmit FIFO/queue status register + type OTG_HS_GNPTXSTS_Register is record + -- Read-only. Nonperiodic TxFIFO space available + NPTXFSAV : OTG_HS_GNPTXSTS_NPTXFSAV_Field; + -- Read-only. Nonperiodic transmit request queue space available + NPTQXSAV : OTG_HS_GNPTXSTS_NPTQXSAV_Field; + -- Read-only. Top of the nonperiodic transmit request queue + NPTXQTOP : OTG_HS_GNPTXSTS_NPTXQTOP_Field; -- unspecified - Reserved_28_31 : STM32F429x.UInt4 := 16#0#; + Reserved_31_31 : STM32F429x.Bit; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DTHRCTL_Register use record - NONISOTHREN at 0 range 0 .. 0; - ISOTHREN at 0 range 1 .. 1; - TXTHRLEN at 0 range 2 .. 10; - Reserved_11_15 at 0 range 11 .. 15; - RXTHREN at 0 range 16 .. 16; - RXTHRLEN at 0 range 17 .. 25; - Reserved_26_26 at 0 range 26 .. 26; - ARPEN at 0 range 27 .. 27; - Reserved_28_31 at 0 range 28 .. 31; + for OTG_HS_GNPTXSTS_Register use record + NPTXFSAV at 0 range 0 .. 15; + NPTQXSAV at 0 range 16 .. 23; + NPTXQTOP at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; end record; - -------------------------------- - -- OTG_HS_DIEPEMPMSK_Register -- - -------------------------------- - - subtype OTG_HS_DIEPEMPMSK_INEPTXFEM_Field is STM32F429x.Short; + subtype OTG_HS_GCCFG_PWRDWN_Field is STM32F429x.Bit; + subtype OTG_HS_GCCFG_I2CPADEN_Field is STM32F429x.Bit; + subtype OTG_HS_GCCFG_VBUSASEN_Field is STM32F429x.Bit; + subtype OTG_HS_GCCFG_VBUSBSEN_Field is STM32F429x.Bit; + subtype OTG_HS_GCCFG_SOFOUTEN_Field is STM32F429x.Bit; + subtype OTG_HS_GCCFG_NOVBUSSENS_Field is STM32F429x.Bit; - -- OTG_HS device IN endpoint FIFO empty interrupt mask register - type OTG_HS_DIEPEMPMSK_Register is record - -- IN EP Tx FIFO empty interrupt mask bits - INEPTXFEM : OTG_HS_DIEPEMPMSK_INEPTXFEM_Field := 16#0#; + -- OTG_HS general core configuration register + type OTG_HS_GCCFG_Register is record + -- unspecified + Reserved_0_15 : STM32F429x.UInt16 := 16#0#; + -- Power down + PWRDWN : OTG_HS_GCCFG_PWRDWN_Field := 16#0#; + -- Enable I2C bus connection for the external I2C PHY interface + I2CPADEN : OTG_HS_GCCFG_I2CPADEN_Field := 16#0#; + -- Enable the VBUS sensing device + VBUSASEN : OTG_HS_GCCFG_VBUSASEN_Field := 16#0#; + -- Enable the VBUS sensing device + VBUSBSEN : OTG_HS_GCCFG_VBUSBSEN_Field := 16#0#; + -- SOF output enable + SOFOUTEN : OTG_HS_GCCFG_SOFOUTEN_Field := 16#0#; + -- VBUS sensing disable option + NOVBUSSENS : OTG_HS_GCCFG_NOVBUSSENS_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short := 16#0#; + Reserved_22_31 : STM32F429x.UInt10 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPEMPMSK_Register use record - INEPTXFEM at 0 range 0 .. 15; - Reserved_16_31 at 0 range 16 .. 31; + for OTG_HS_GCCFG_Register use record + Reserved_0_15 at 0 range 0 .. 15; + PWRDWN at 0 range 16 .. 16; + I2CPADEN at 0 range 17 .. 17; + VBUSASEN at 0 range 18 .. 18; + VBUSBSEN at 0 range 19 .. 19; + SOFOUTEN at 0 range 20 .. 20; + NOVBUSSENS at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; end record; - ------------------------------ - -- OTG_HS_DEACHINT_Register -- - ------------------------------ + subtype OTG_HS_HPTXFSIZ_PTXSA_Field is STM32F429x.UInt16; + subtype OTG_HS_HPTXFSIZ_PTXFD_Field is STM32F429x.UInt16; - subtype OTG_HS_DEACHINT_IEP1INT_Field is STM32F429x.Bit; - subtype OTG_HS_DEACHINT_OEP1INT_Field is STM32F429x.Bit; - - -- OTG_HS device each endpoint interrupt register - type OTG_HS_DEACHINT_Register is record - -- unspecified - Reserved_0_0 : STM32F429x.Bit := 16#0#; - -- IN endpoint 1interrupt bit - IEP1INT : OTG_HS_DEACHINT_IEP1INT_Field := 16#0#; - -- unspecified - Reserved_2_16 : STM32F429x.UInt15 := 16#0#; - -- OUT endpoint 1 interrupt bit - OEP1INT : OTG_HS_DEACHINT_OEP1INT_Field := 16#0#; - -- unspecified - Reserved_18_31 : STM32F429x.UInt14 := 16#0#; + -- OTG_HS Host periodic transmit FIFO size register + type OTG_HS_HPTXFSIZ_Register is record + -- Host periodic TxFIFO start address + PTXSA : OTG_HS_HPTXFSIZ_PTXSA_Field := 16#600#; + -- Host periodic TxFIFO depth + PTXFD : OTG_HS_HPTXFSIZ_PTXFD_Field := 16#200#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DEACHINT_Register use record - Reserved_0_0 at 0 range 0 .. 0; - IEP1INT at 0 range 1 .. 1; - Reserved_2_16 at 0 range 2 .. 16; - OEP1INT at 0 range 17 .. 17; - Reserved_18_31 at 0 range 18 .. 31; + for OTG_HS_HPTXFSIZ_Register use record + PTXSA at 0 range 0 .. 15; + PTXFD at 0 range 16 .. 31; end record; - --------------------------------- - -- OTG_HS_DEACHINTMSK_Register -- - --------------------------------- - - subtype OTG_HS_DEACHINTMSK_IEP1INTM_Field is STM32F429x.Bit; - subtype OTG_HS_DEACHINTMSK_OEP1INTM_Field is STM32F429x.Bit; + subtype OTG_HS_DIEPTXF_INEPTXSA_Field is STM32F429x.UInt16; + subtype OTG_HS_DIEPTXF_INEPTXFD_Field is STM32F429x.UInt16; - -- OTG_HS device each endpoint interrupt register mask - type OTG_HS_DEACHINTMSK_Register is record - -- unspecified - Reserved_0_0 : STM32F429x.Bit := 16#0#; - -- IN Endpoint 1 interrupt mask bit - IEP1INTM : OTG_HS_DEACHINTMSK_IEP1INTM_Field := 16#0#; - -- unspecified - Reserved_2_16 : STM32F429x.UInt15 := 16#0#; - -- OUT Endpoint 1 interrupt mask bit - OEP1INTM : OTG_HS_DEACHINTMSK_OEP1INTM_Field := 16#0#; - -- unspecified - Reserved_18_31 : STM32F429x.UInt14 := 16#0#; + -- OTG_HS device IN endpoint transmit FIFO size register + type OTG_HS_DIEPTXF_Register is record + -- IN endpoint FIFOx transmit RAM start address + INEPTXSA : OTG_HS_DIEPTXF_INEPTXSA_Field := 16#400#; + -- IN endpoint TxFIFO depth + INEPTXFD : OTG_HS_DIEPTXF_INEPTXFD_Field := 16#200#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DEACHINTMSK_Register use record - Reserved_0_0 at 0 range 0 .. 0; - IEP1INTM at 0 range 1 .. 1; - Reserved_2_16 at 0 range 2 .. 16; - OEP1INTM at 0 range 17 .. 17; - Reserved_18_31 at 0 range 18 .. 31; + for OTG_HS_DIEPTXF_Register use record + INEPTXSA at 0 range 0 .. 15; + INEPTXFD at 0 range 16 .. 31; end record; - ---------------------------------- - -- OTG_HS_DIEPEACHMSK1_Register -- - ---------------------------------- - - subtype OTG_HS_DIEPEACHMSK1_XFRCM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPEACHMSK1_EPDM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPEACHMSK1_TOM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPEACHMSK1_INEPNMM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPEACHMSK1_INEPNEM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPEACHMSK1_TXFURM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPEACHMSK1_BIM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPEACHMSK1_NAKM_Field is STM32F429x.Bit; + subtype OTG_HS_HCFG_FSLSPCS_Field is STM32F429x.UInt2; + subtype OTG_HS_HCFG_FSLSS_Field is STM32F429x.Bit; - -- OTG_HS device each in endpoint-1 interrupt register - type OTG_HS_DIEPEACHMSK1_Register is record - -- Transfer completed interrupt mask - XFRCM : OTG_HS_DIEPEACHMSK1_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : OTG_HS_DIEPEACHMSK1_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- Timeout condition mask (nonisochronous endpoints) - TOM : OTG_HS_DIEPEACHMSK1_TOM_Field := 16#0#; - -- IN token received when TxFIFO empty mask - ITTXFEMSK : OTG_HS_DIEPEACHMSK1_ITTXFEMSK_Field := 16#0#; - -- IN token received with EP mismatch mask - INEPNMM : OTG_HS_DIEPEACHMSK1_INEPNMM_Field := 16#0#; - -- IN endpoint NAK effective mask - INEPNEM : OTG_HS_DIEPEACHMSK1_INEPNEM_Field := 16#0#; - -- unspecified - Reserved_7_7 : STM32F429x.Bit := 16#0#; - -- FIFO underrun mask - TXFURM : OTG_HS_DIEPEACHMSK1_TXFURM_Field := 16#0#; - -- BNA interrupt mask - BIM : OTG_HS_DIEPEACHMSK1_BIM_Field := 16#0#; - -- unspecified - Reserved_10_12 : STM32F429x.UInt3 := 16#0#; - -- NAK interrupt mask - NAKM : OTG_HS_DIEPEACHMSK1_NAKM_Field := 16#0#; + -- OTG_HS host configuration register + type OTG_HS_HCFG_Register is record + -- FS/LS PHY clock select + FSLSPCS : OTG_HS_HCFG_FSLSPCS_Field := 16#0#; + -- Read-only. FS- and LS-only support + FSLSS : OTG_HS_HCFG_FSLSS_Field := 16#0#; -- unspecified - Reserved_14_31 : STM32F429x.UInt18 := 16#0#; + Reserved_3_31 : STM32F429x.UInt29 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPEACHMSK1_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOM at 0 range 3 .. 3; - ITTXFEMSK at 0 range 4 .. 4; - INEPNMM at 0 range 5 .. 5; - INEPNEM at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - TXFURM at 0 range 8 .. 8; - BIM at 0 range 9 .. 9; - Reserved_10_12 at 0 range 10 .. 12; - NAKM at 0 range 13 .. 13; - Reserved_14_31 at 0 range 14 .. 31; + for OTG_HS_HCFG_Register use record + FSLSPCS at 0 range 0 .. 1; + FSLSS at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; end record; - ---------------------------------- - -- OTG_HS_DOEPEACHMSK1_Register -- - ---------------------------------- - - subtype OTG_HS_DOEPEACHMSK1_XFRCM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_EPDM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_TOM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_ITTXFEMSK_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_INEPNMM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_INEPNEM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_TXFURM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_BIM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_BERRM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_NAKM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPEACHMSK1_NYETM_Field is STM32F429x.Bit; + subtype OTG_HS_HFIR_FRIVL_Field is STM32F429x.UInt16; - -- OTG_HS device each OUT endpoint-1 interrupt register - type OTG_HS_DOEPEACHMSK1_Register is record - -- Transfer completed interrupt mask - XFRCM : OTG_HS_DOEPEACHMSK1_XFRCM_Field := 16#0#; - -- Endpoint disabled interrupt mask - EPDM : OTG_HS_DOEPEACHMSK1_EPDM_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- Timeout condition mask - TOM : OTG_HS_DOEPEACHMSK1_TOM_Field := 16#0#; - -- IN token received when TxFIFO empty mask - ITTXFEMSK : OTG_HS_DOEPEACHMSK1_ITTXFEMSK_Field := 16#0#; - -- IN token received with EP mismatch mask - INEPNMM : OTG_HS_DOEPEACHMSK1_INEPNMM_Field := 16#0#; - -- IN endpoint NAK effective mask - INEPNEM : OTG_HS_DOEPEACHMSK1_INEPNEM_Field := 16#0#; - -- unspecified - Reserved_7_7 : STM32F429x.Bit := 16#0#; - -- OUT packet error mask - TXFURM : OTG_HS_DOEPEACHMSK1_TXFURM_Field := 16#0#; - -- BNA interrupt mask - BIM : OTG_HS_DOEPEACHMSK1_BIM_Field := 16#0#; - -- unspecified - Reserved_10_11 : STM32F429x.UInt2 := 16#0#; - -- Bubble error interrupt mask - BERRM : OTG_HS_DOEPEACHMSK1_BERRM_Field := 16#0#; - -- NAK interrupt mask - NAKM : OTG_HS_DOEPEACHMSK1_NAKM_Field := 16#0#; - -- NYET interrupt mask - NYETM : OTG_HS_DOEPEACHMSK1_NYETM_Field := 16#0#; + -- OTG_HS Host frame interval register + type OTG_HS_HFIR_Register is record + -- Frame interval + FRIVL : OTG_HS_HFIR_FRIVL_Field := 16#EA60#; -- unspecified - Reserved_15_31 : STM32F429x.UInt17 := 16#0#; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPEACHMSK1_Register use record - XFRCM at 0 range 0 .. 0; - EPDM at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOM at 0 range 3 .. 3; - ITTXFEMSK at 0 range 4 .. 4; - INEPNMM at 0 range 5 .. 5; - INEPNEM at 0 range 6 .. 6; - Reserved_7_7 at 0 range 7 .. 7; - TXFURM at 0 range 8 .. 8; - BIM at 0 range 9 .. 9; - Reserved_10_11 at 0 range 10 .. 11; - BERRM at 0 range 12 .. 12; - NAKM at 0 range 13 .. 13; - NYETM at 0 range 14 .. 14; - Reserved_15_31 at 0 range 15 .. 31; + for OTG_HS_HFIR_Register use record + FRIVL at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_DIEPCTL_Register -- - ----------------------------- - - subtype OTG_HS_DIEPCTL0_MPSIZ_Field is STM32F429x.UInt11; - subtype OTG_HS_DIEPCTL0_USBAEP_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_EONUM_DPID_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_NAKSTS_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_EPTYP_Field is STM32F429x.UInt2; - subtype OTG_HS_DIEPCTL0_Stall_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_TXFNUM_Field is STM32F429x.UInt4; - subtype OTG_HS_DIEPCTL0_CNAK_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_SNAK_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_SD0PID_SEVNFRM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_SODDFRM_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_EPDIS_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPCTL0_EPENA_Field is STM32F429x.Bit; + subtype OTG_HS_HFNUM_FRNUM_Field is STM32F429x.UInt16; + subtype OTG_HS_HFNUM_FTREM_Field is STM32F429x.UInt16; - -- OTG device endpoint-0 control register - type OTG_HS_DIEPCTL_Register is record - -- Maximum packet size - MPSIZ : OTG_HS_DIEPCTL0_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_11_14 : STM32F429x.UInt4 := 16#0#; - -- USB active endpoint - USBAEP : OTG_HS_DIEPCTL0_USBAEP_Field := 16#0#; - -- Even/odd frame - EONUM_DPID : OTG_HS_DIEPCTL0_EONUM_DPID_Field := 16#0#; - -- NAK status - NAKSTS : OTG_HS_DIEPCTL0_NAKSTS_Field := 16#0#; - -- Endpoint type - EPTYP : OTG_HS_DIEPCTL0_EPTYP_Field := 16#0#; - -- unspecified - Reserved_20_20 : STM32F429x.Bit := 16#0#; - -- STALL handshake - Stall : OTG_HS_DIEPCTL0_Stall_Field := 16#0#; - -- TxFIFO number - TXFNUM : OTG_HS_DIEPCTL0_TXFNUM_Field := 16#0#; - -- Clear NAK - CNAK : OTG_HS_DIEPCTL0_CNAK_Field := 16#0#; - -- Set NAK - SNAK : OTG_HS_DIEPCTL0_SNAK_Field := 16#0#; - -- Set DATA0 PID - SD0PID_SEVNFRM : OTG_HS_DIEPCTL0_SD0PID_SEVNFRM_Field := 16#0#; - -- Set odd frame - SODDFRM : OTG_HS_DIEPCTL0_SODDFRM_Field := 16#0#; - -- Endpoint disable - EPDIS : OTG_HS_DIEPCTL0_EPDIS_Field := 16#0#; - -- Endpoint enable - EPENA : OTG_HS_DIEPCTL0_EPENA_Field := 16#0#; + -- OTG_HS host frame number/frame time remaining register + type OTG_HS_HFNUM_Register is record + -- Read-only. Frame number + FRNUM : OTG_HS_HFNUM_FRNUM_Field; + -- Read-only. Frame time remaining + FTREM : OTG_HS_HFNUM_FTREM_Field; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPCTL_Register use record - MPSIZ at 0 range 0 .. 10; - Reserved_11_14 at 0 range 11 .. 14; - USBAEP at 0 range 15 .. 15; - EONUM_DPID at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - Reserved_20_20 at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - TXFNUM at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - SD0PID_SEVNFRM at 0 range 28 .. 28; - SODDFRM at 0 range 29 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for OTG_HS_HFNUM_Register use record + FRNUM at 0 range 0 .. 15; + FTREM at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_DIEPINT_Register -- - ----------------------------- - - subtype OTG_HS_DIEPINT0_XFRC_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_EPDISD_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_TOC_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_ITTXFE_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_INEPNE_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_TXFE_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_TXFIFOUDRN_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_BNA_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_PKTDRPSTS_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_BERR_Field is STM32F429x.Bit; - subtype OTG_HS_DIEPINT0_NAK_Field is STM32F429x.Bit; - - -- OTG device endpoint-0 interrupt register - type OTG_HS_DIEPINT_Register is record - -- Transfer completed interrupt - XFRC : OTG_HS_DIEPINT0_XFRC_Field := 16#0#; - -- Endpoint disabled interrupt - EPDISD : OTG_HS_DIEPINT0_EPDISD_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- Timeout condition - TOC : OTG_HS_DIEPINT0_TOC_Field := 16#0#; - -- IN token received when TxFIFO is empty - ITTXFE : OTG_HS_DIEPINT0_ITTXFE_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F429x.Bit := 16#0#; - -- IN endpoint NAK effective - INEPNE : OTG_HS_DIEPINT0_INEPNE_Field := 16#0#; - -- Transmit FIFO empty - TXFE : OTG_HS_DIEPINT0_TXFE_Field := 16#1#; - -- Transmit Fifo Underrun - TXFIFOUDRN : OTG_HS_DIEPINT0_TXFIFOUDRN_Field := 16#0#; - -- Buffer not available interrupt - BNA : OTG_HS_DIEPINT0_BNA_Field := 16#0#; - -- unspecified - Reserved_10_10 : STM32F429x.Bit := 16#0#; - -- Packet dropped status - PKTDRPSTS : OTG_HS_DIEPINT0_PKTDRPSTS_Field := 16#0#; - -- Babble error interrupt - BERR : OTG_HS_DIEPINT0_BERR_Field := 16#0#; - -- NAK interrupt - NAK : OTG_HS_DIEPINT0_NAK_Field := 16#0#; - -- unspecified - Reserved_14_31 : STM32F429x.UInt18 := 16#0#; + subtype OTG_HS_HPTXSTS_PTXFSAVL_Field is STM32F429x.UInt16; + subtype OTG_HS_HPTXSTS_PTXQSAV_Field is STM32F429x.Byte; + subtype OTG_HS_HPTXSTS_PTXQTOP_Field is STM32F429x.Byte; + + -- OTG_HS_Host periodic transmit FIFO/queue status register + type OTG_HS_HPTXSTS_Register is record + -- Periodic transmit data FIFO space available + PTXFSAVL : OTG_HS_HPTXSTS_PTXFSAVL_Field := 16#100#; + -- Read-only. Periodic transmit request queue space available + PTXQSAV : OTG_HS_HPTXSTS_PTXQSAV_Field := 16#8#; + -- Read-only. Top of the periodic transmit request queue + PTXQTOP : OTG_HS_HPTXSTS_PTXQTOP_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPINT_Register use record - XFRC at 0 range 0 .. 0; - EPDISD at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - TOC at 0 range 3 .. 3; - ITTXFE at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - INEPNE at 0 range 6 .. 6; - TXFE at 0 range 7 .. 7; - TXFIFOUDRN at 0 range 8 .. 8; - BNA at 0 range 9 .. 9; - Reserved_10_10 at 0 range 10 .. 10; - PKTDRPSTS at 0 range 11 .. 11; - BERR at 0 range 12 .. 12; - NAK at 0 range 13 .. 13; - Reserved_14_31 at 0 range 14 .. 31; + for OTG_HS_HPTXSTS_Register use record + PTXFSAVL at 0 range 0 .. 15; + PTXQSAV at 0 range 16 .. 23; + PTXQTOP at 0 range 24 .. 31; end record; - ------------------------------- - -- OTG_HS_DIEPTSIZ0_Register -- - ------------------------------- - - subtype OTG_HS_DIEPTSIZ0_XFRSIZ_Field is STM32F429x.UInt7; - subtype OTG_HS_DIEPTSIZ0_PKTCNT_Field is STM32F429x.UInt2; + subtype OTG_HS_HAINT_HAINT_Field is STM32F429x.UInt16; - -- OTG_HS device IN endpoint 0 transfer size register - type OTG_HS_DIEPTSIZ0_Register is record - -- Transfer size - XFRSIZ : OTG_HS_DIEPTSIZ0_XFRSIZ_Field := 16#0#; - -- unspecified - Reserved_7_18 : STM32F429x.UInt12 := 16#0#; - -- Packet count - PKTCNT : OTG_HS_DIEPTSIZ0_PKTCNT_Field := 16#0#; + -- OTG_HS Host all channels interrupt register + type OTG_HS_HAINT_Register is record + -- Read-only. Channel interrupts + HAINT : OTG_HS_HAINT_HAINT_Field; -- unspecified - Reserved_21_31 : STM32F429x.UInt11 := 16#0#; + Reserved_16_31 : STM32F429x.UInt16; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPTSIZ0_Register use record - XFRSIZ at 0 range 0 .. 6; - Reserved_7_18 at 0 range 7 .. 18; - PKTCNT at 0 range 19 .. 20; - Reserved_21_31 at 0 range 21 .. 31; + for OTG_HS_HAINT_Register use record + HAINT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; end record; - ----------------------------- - -- OTG_HS_DTXFSTS_Register -- - ----------------------------- + subtype OTG_HS_HAINTMSK_HAINTM_Field is STM32F429x.UInt16; - subtype OTG_HS_DTXFSTS0_INEPTFSAV_Field is STM32F429x.Short; - - -- OTG_HS device IN endpoint transmit FIFO status register - type OTG_HS_DTXFSTS_Register is record - -- IN endpoint TxFIFO space avail - INEPTFSAV : OTG_HS_DTXFSTS0_INEPTFSAV_Field; + -- OTG_HS host all channels interrupt mask register + type OTG_HS_HAINTMSK_Register is record + -- Channel interrupt mask + HAINTM : OTG_HS_HAINTMSK_HAINTM_Field := 16#0#; -- unspecified - Reserved_16_31 : STM32F429x.Short; + Reserved_16_31 : STM32F429x.UInt16 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DTXFSTS_Register use record - INEPTFSAV at 0 range 0 .. 15; + for OTG_HS_HAINTMSK_Register use record + HAINTM at 0 range 0 .. 15; Reserved_16_31 at 0 range 16 .. 31; end record; - ------------------------------ - -- OTG_HS_DIEPTSIZ_Register -- - ------------------------------ - - subtype OTG_HS_DIEPTSIZ1_XFRSIZ_Field is STM32F429x.UInt19; - subtype OTG_HS_DIEPTSIZ1_PKTCNT_Field is STM32F429x.UInt10; - subtype OTG_HS_DIEPTSIZ1_MCNT_Field is STM32F429x.UInt2; + subtype OTG_HS_HPRT_PCSTS_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_PCDET_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_PENA_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_PENCHNG_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_POCA_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_POCCHNG_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_PRES_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_PSUSP_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_PRST_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_PLSTS_Field is STM32F429x.UInt2; + subtype OTG_HS_HPRT_PPWR_Field is STM32F429x.Bit; + subtype OTG_HS_HPRT_PTCTL_Field is STM32F429x.UInt4; + subtype OTG_HS_HPRT_PSPD_Field is STM32F429x.UInt2; - -- OTG_HS device endpoint transfer size register - type OTG_HS_DIEPTSIZ_Register is record - -- Transfer size - XFRSIZ : OTG_HS_DIEPTSIZ1_XFRSIZ_Field := 16#0#; - -- Packet count - PKTCNT : OTG_HS_DIEPTSIZ1_PKTCNT_Field := 16#0#; - -- Multi count - MCNT : OTG_HS_DIEPTSIZ1_MCNT_Field := 16#0#; + -- OTG_HS host port control and status register + type OTG_HS_HPRT_Register is record + -- Read-only. Port connect status + PCSTS : OTG_HS_HPRT_PCSTS_Field := 16#0#; + -- Port connect detected + PCDET : OTG_HS_HPRT_PCDET_Field := 16#0#; + -- Port enable + PENA : OTG_HS_HPRT_PENA_Field := 16#0#; + -- Port enable/disable change + PENCHNG : OTG_HS_HPRT_PENCHNG_Field := 16#0#; + -- Read-only. Port overcurrent active + POCA : OTG_HS_HPRT_POCA_Field := 16#0#; + -- Port overcurrent change + POCCHNG : OTG_HS_HPRT_POCCHNG_Field := 16#0#; + -- Port resume + PRES : OTG_HS_HPRT_PRES_Field := 16#0#; + -- Port suspend + PSUSP : OTG_HS_HPRT_PSUSP_Field := 16#0#; + -- Port reset + PRST : OTG_HS_HPRT_PRST_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F429x.Bit := 16#0#; + Reserved_9_9 : STM32F429x.Bit := 16#0#; + -- Read-only. Port line status + PLSTS : OTG_HS_HPRT_PLSTS_Field := 16#0#; + -- Port power + PPWR : OTG_HS_HPRT_PPWR_Field := 16#0#; + -- Port test control + PTCTL : OTG_HS_HPRT_PTCTL_Field := 16#0#; + -- Read-only. Port speed + PSPD : OTG_HS_HPRT_PSPD_Field := 16#0#; + -- unspecified + Reserved_19_31 : STM32F429x.UInt13 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DIEPTSIZ_Register use record - XFRSIZ at 0 range 0 .. 18; - PKTCNT at 0 range 19 .. 28; - MCNT at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for OTG_HS_HPRT_Register use record + PCSTS at 0 range 0 .. 0; + PCDET at 0 range 1 .. 1; + PENA at 0 range 2 .. 2; + PENCHNG at 0 range 3 .. 3; + POCA at 0 range 4 .. 4; + POCCHNG at 0 range 5 .. 5; + PRES at 0 range 6 .. 6; + PSUSP at 0 range 7 .. 7; + PRST at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PLSTS at 0 range 10 .. 11; + PPWR at 0 range 12 .. 12; + PTCTL at 0 range 13 .. 16; + PSPD at 0 range 17 .. 18; + Reserved_19_31 at 0 range 19 .. 31; end record; - ------------------------------ - -- OTG_HS_DOEPCTL0_Register -- - ------------------------------ - - subtype OTG_HS_DOEPCTL0_MPSIZ_Field is STM32F429x.UInt2; - subtype OTG_HS_DOEPCTL0_USBAEP_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL0_NAKSTS_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL0_EPTYP_Field is STM32F429x.UInt2; - subtype OTG_HS_DOEPCTL0_SNPM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL0_Stall_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL0_CNAK_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL0_SNAK_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL0_EPDIS_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL0_EPENA_Field is STM32F429x.Bit; + subtype OTG_HS_HCCHAR_MPSIZ_Field is STM32F429x.UInt11; + subtype OTG_HS_HCCHAR_EPNUM_Field is STM32F429x.UInt4; + subtype OTG_HS_HCCHAR_EPDIR_Field is STM32F429x.Bit; + subtype OTG_HS_HCCHAR_LSDEV_Field is STM32F429x.Bit; + subtype OTG_HS_HCCHAR_EPTYP_Field is STM32F429x.UInt2; + subtype OTG_HS_HCCHAR_MC_Field is STM32F429x.UInt2; + subtype OTG_HS_HCCHAR_DAD_Field is STM32F429x.UInt7; + subtype OTG_HS_HCCHAR_ODDFRM_Field is STM32F429x.Bit; + subtype OTG_HS_HCCHAR_CHDIS_Field is STM32F429x.Bit; + subtype OTG_HS_HCCHAR_CHENA_Field is STM32F429x.Bit; - -- OTG_HS device control OUT endpoint 0 control register - type OTG_HS_DOEPCTL0_Register is record + -- OTG_HS host channel-0 characteristics register + type OTG_HS_HCCHAR_Register is record -- Maximum packet size - MPSIZ : OTG_HS_DOEPCTL0_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_2_14 : STM32F429x.UInt13 := 16#0#; - -- USB active endpoint - USBAEP : OTG_HS_DOEPCTL0_USBAEP_Field := 16#1#; + MPSIZ : OTG_HS_HCCHAR_MPSIZ_Field := 16#0#; + -- Endpoint number + EPNUM : OTG_HS_HCCHAR_EPNUM_Field := 16#0#; + -- Endpoint direction + EPDIR : OTG_HS_HCCHAR_EPDIR_Field := 16#0#; -- unspecified Reserved_16_16 : STM32F429x.Bit := 16#0#; - -- NAK status - NAKSTS : OTG_HS_DOEPCTL0_NAKSTS_Field := 16#0#; + -- Low-speed device + LSDEV : OTG_HS_HCCHAR_LSDEV_Field := 16#0#; -- Endpoint type - EPTYP : OTG_HS_DOEPCTL0_EPTYP_Field := 16#0#; - -- Snoop mode - SNPM : OTG_HS_DOEPCTL0_SNPM_Field := 16#0#; - -- STALL handshake - Stall : OTG_HS_DOEPCTL0_Stall_Field := 16#0#; - -- unspecified - Reserved_22_25 : STM32F429x.UInt4 := 16#0#; - -- Clear NAK - CNAK : OTG_HS_DOEPCTL0_CNAK_Field := 16#0#; - -- Set NAK - SNAK : OTG_HS_DOEPCTL0_SNAK_Field := 16#0#; - -- unspecified - Reserved_28_29 : STM32F429x.UInt2 := 16#0#; - -- Endpoint disable - EPDIS : OTG_HS_DOEPCTL0_EPDIS_Field := 16#0#; - -- Endpoint enable - EPENA : OTG_HS_DOEPCTL0_EPENA_Field := 16#0#; + EPTYP : OTG_HS_HCCHAR_EPTYP_Field := 16#0#; + -- Multi Count (MC) / Error Count (EC) + MC : OTG_HS_HCCHAR_MC_Field := 16#0#; + -- Device address + DAD : OTG_HS_HCCHAR_DAD_Field := 16#0#; + -- Odd frame + ODDFRM : OTG_HS_HCCHAR_ODDFRM_Field := 16#0#; + -- Channel disable + CHDIS : OTG_HS_HCCHAR_CHDIS_Field := 16#0#; + -- Channel enable + CHENA : OTG_HS_HCCHAR_CHENA_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPCTL0_Register use record - MPSIZ at 0 range 0 .. 1; - Reserved_2_14 at 0 range 2 .. 14; - USBAEP at 0 range 15 .. 15; + for OTG_HS_HCCHAR_Register use record + MPSIZ at 0 range 0 .. 10; + EPNUM at 0 range 11 .. 14; + EPDIR at 0 range 15 .. 15; Reserved_16_16 at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; + LSDEV at 0 range 17 .. 17; EPTYP at 0 range 18 .. 19; - SNPM at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - Reserved_22_25 at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - Reserved_28_29 at 0 range 28 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + MC at 0 range 20 .. 21; + DAD at 0 range 22 .. 28; + ODDFRM at 0 range 29 .. 29; + CHDIS at 0 range 30 .. 30; + CHENA at 0 range 31 .. 31; end record; - ----------------------------- - -- OTG_HS_DOEPINT_Register -- - ----------------------------- + subtype OTG_HS_HCSPLT_PRTADDR_Field is STM32F429x.UInt7; + subtype OTG_HS_HCSPLT_HUBADDR_Field is STM32F429x.UInt7; + subtype OTG_HS_HCSPLT_XACTPOS_Field is STM32F429x.UInt2; + subtype OTG_HS_HCSPLT_COMPLSPLT_Field is STM32F429x.Bit; + subtype OTG_HS_HCSPLT_SPLITEN_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPINT0_XFRC_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPINT0_EPDISD_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPINT0_STUP_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPINT0_OTEPDIS_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPINT0_B2BSTUP_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPINT0_NYET_Field is STM32F429x.Bit; - - -- OTG_HS device endpoint-0 interrupt register - type OTG_HS_DOEPINT_Register is record - -- Transfer completed interrupt - XFRC : OTG_HS_DOEPINT0_XFRC_Field := 16#0#; - -- Endpoint disabled interrupt - EPDISD : OTG_HS_DOEPINT0_EPDISD_Field := 16#0#; - -- unspecified - Reserved_2_2 : STM32F429x.Bit := 16#0#; - -- SETUP phase done - STUP : OTG_HS_DOEPINT0_STUP_Field := 16#0#; - -- OUT token received when endpoint disabled - OTEPDIS : OTG_HS_DOEPINT0_OTEPDIS_Field := 16#0#; - -- unspecified - Reserved_5_5 : STM32F429x.Bit := 16#0#; - -- Back-to-back SETUP packets received - B2BSTUP : OTG_HS_DOEPINT0_B2BSTUP_Field := 16#0#; - -- unspecified - Reserved_7_13 : STM32F429x.UInt7 := 16#1#; - -- NYET interrupt - NYET : OTG_HS_DOEPINT0_NYET_Field := 16#0#; + -- OTG_HS host channel-0 split control register + type OTG_HS_HCSPLT_Register is record + -- Port address + PRTADDR : OTG_HS_HCSPLT_PRTADDR_Field := 16#0#; + -- Hub address + HUBADDR : OTG_HS_HCSPLT_HUBADDR_Field := 16#0#; + -- XACTPOS + XACTPOS : OTG_HS_HCSPLT_XACTPOS_Field := 16#0#; + -- Do complete split + COMPLSPLT : OTG_HS_HCSPLT_COMPLSPLT_Field := 16#0#; -- unspecified - Reserved_15_31 : STM32F429x.UInt17 := 16#0#; + Reserved_17_30 : STM32F429x.UInt14 := 16#0#; + -- Split enable + SPLITEN : OTG_HS_HCSPLT_SPLITEN_Field := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPINT_Register use record - XFRC at 0 range 0 .. 0; - EPDISD at 0 range 1 .. 1; - Reserved_2_2 at 0 range 2 .. 2; - STUP at 0 range 3 .. 3; - OTEPDIS at 0 range 4 .. 4; - Reserved_5_5 at 0 range 5 .. 5; - B2BSTUP at 0 range 6 .. 6; - Reserved_7_13 at 0 range 7 .. 13; - NYET at 0 range 14 .. 14; - Reserved_15_31 at 0 range 15 .. 31; + for OTG_HS_HCSPLT_Register use record + PRTADDR at 0 range 0 .. 6; + HUBADDR at 0 range 7 .. 13; + XACTPOS at 0 range 14 .. 15; + COMPLSPLT at 0 range 16 .. 16; + Reserved_17_30 at 0 range 17 .. 30; + SPLITEN at 0 range 31 .. 31; end record; - ------------------------------- - -- OTG_HS_DOEPTSIZ0_Register -- - ------------------------------- + subtype OTG_HS_HCINT_XFRC_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_CHH_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_AHBERR_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_STALL_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_NAK_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_ACK_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_NYET_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_TXERR_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_BBERR_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_FRMOR_Field is STM32F429x.Bit; + subtype OTG_HS_HCINT_DTERR_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPTSIZ0_XFRSIZ_Field is STM32F429x.UInt7; - subtype OTG_HS_DOEPTSIZ0_PKTCNT_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPTSIZ0_STUPCNT_Field is STM32F429x.UInt2; - - -- OTG_HS device endpoint-1 transfer size register - type OTG_HS_DOEPTSIZ0_Register is record - -- Transfer size - XFRSIZ : OTG_HS_DOEPTSIZ0_XFRSIZ_Field := 16#0#; - -- unspecified - Reserved_7_18 : STM32F429x.UInt12 := 16#0#; - -- Packet count - PKTCNT : OTG_HS_DOEPTSIZ0_PKTCNT_Field := 16#0#; - -- unspecified - Reserved_20_28 : STM32F429x.UInt9 := 16#0#; - -- SETUP packet count - STUPCNT : OTG_HS_DOEPTSIZ0_STUPCNT_Field := 16#0#; + -- OTG_HS host channel-11 interrupt register + type OTG_HS_HCINT_Register is record + -- Transfer completed + XFRC : OTG_HS_HCINT_XFRC_Field := 16#0#; + -- Channel halted + CHH : OTG_HS_HCINT_CHH_Field := 16#0#; + -- AHB error + AHBERR : OTG_HS_HCINT_AHBERR_Field := 16#0#; + -- STALL response received interrupt + STALL : OTG_HS_HCINT_STALL_Field := 16#0#; + -- NAK response received interrupt + NAK : OTG_HS_HCINT_NAK_Field := 16#0#; + -- ACK response received/transmitted interrupt + ACK : OTG_HS_HCINT_ACK_Field := 16#0#; + -- Response received interrupt + NYET : OTG_HS_HCINT_NYET_Field := 16#0#; + -- Transaction error + TXERR : OTG_HS_HCINT_TXERR_Field := 16#0#; + -- Babble error + BBERR : OTG_HS_HCINT_BBERR_Field := 16#0#; + -- Frame overrun + FRMOR : OTG_HS_HCINT_FRMOR_Field := 16#0#; + -- Data toggle error + DTERR : OTG_HS_HCINT_DTERR_Field := 16#0#; -- unspecified - Reserved_31_31 : STM32F429x.Bit := 16#0#; + Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPTSIZ0_Register use record - XFRSIZ at 0 range 0 .. 6; - Reserved_7_18 at 0 range 7 .. 18; - PKTCNT at 0 range 19 .. 19; - Reserved_20_28 at 0 range 20 .. 28; - STUPCNT at 0 range 29 .. 30; - Reserved_31_31 at 0 range 31 .. 31; + for OTG_HS_HCINT_Register use record + XFRC at 0 range 0 .. 0; + CHH at 0 range 1 .. 1; + AHBERR at 0 range 2 .. 2; + STALL at 0 range 3 .. 3; + NAK at 0 range 4 .. 4; + ACK at 0 range 5 .. 5; + NYET at 0 range 6 .. 6; + TXERR at 0 range 7 .. 7; + BBERR at 0 range 8 .. 8; + FRMOR at 0 range 9 .. 9; + DTERR at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; end record; - ----------------------------- - -- OTG_HS_DOEPCTL_Register -- - ----------------------------- - - subtype OTG_HS_DOEPCTL1_MPSIZ_Field is STM32F429x.UInt11; - subtype OTG_HS_DOEPCTL1_USBAEP_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_EONUM_DPID_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_NAKSTS_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_EPTYP_Field is STM32F429x.UInt2; - subtype OTG_HS_DOEPCTL1_SNPM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_Stall_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_CNAK_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_SNAK_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_SD0PID_SEVNFRM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_SODDFRM_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_EPDIS_Field is STM32F429x.Bit; - subtype OTG_HS_DOEPCTL1_EPENA_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_XFRCM_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_CHHM_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_AHBERR_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_STALLM_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_NAKM_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_ACKM_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_NYET_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_TXERRM_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_BBERRM_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_FRMORM_Field is STM32F429x.Bit; + subtype OTG_HS_HCINTMSK_DTERRM_Field is STM32F429x.Bit; - -- OTG device endpoint-1 control register - type OTG_HS_DOEPCTL_Register is record - -- Maximum packet size - MPSIZ : OTG_HS_DOEPCTL1_MPSIZ_Field := 16#0#; - -- unspecified - Reserved_11_14 : STM32F429x.UInt4 := 16#0#; - -- USB active endpoint - USBAEP : OTG_HS_DOEPCTL1_USBAEP_Field := 16#0#; - -- Even odd frame/Endpoint data PID - EONUM_DPID : OTG_HS_DOEPCTL1_EONUM_DPID_Field := 16#0#; - -- NAK status - NAKSTS : OTG_HS_DOEPCTL1_NAKSTS_Field := 16#0#; - -- Endpoint type - EPTYP : OTG_HS_DOEPCTL1_EPTYP_Field := 16#0#; - -- Snoop mode - SNPM : OTG_HS_DOEPCTL1_SNPM_Field := 16#0#; - -- STALL handshake - Stall : OTG_HS_DOEPCTL1_Stall_Field := 16#0#; + -- OTG_HS host channel-11 interrupt mask register + type OTG_HS_HCINTMSK_Register is record + -- Transfer completed mask + XFRCM : OTG_HS_HCINTMSK_XFRCM_Field := 16#0#; + -- Channel halted mask + CHHM : OTG_HS_HCINTMSK_CHHM_Field := 16#0#; + -- AHB error + AHBERR : OTG_HS_HCINTMSK_AHBERR_Field := 16#0#; + -- STALL response received interrupt mask + STALLM : OTG_HS_HCINTMSK_STALLM_Field := 16#0#; + -- NAK response received interrupt mask + NAKM : OTG_HS_HCINTMSK_NAKM_Field := 16#0#; + -- ACK response received/transmitted interrupt mask + ACKM : OTG_HS_HCINTMSK_ACKM_Field := 16#0#; + -- response received interrupt mask + NYET : OTG_HS_HCINTMSK_NYET_Field := 16#0#; + -- Transaction error mask + TXERRM : OTG_HS_HCINTMSK_TXERRM_Field := 16#0#; + -- Babble error mask + BBERRM : OTG_HS_HCINTMSK_BBERRM_Field := 16#0#; + -- Frame overrun mask + FRMORM : OTG_HS_HCINTMSK_FRMORM_Field := 16#0#; + -- Data toggle error mask + DTERRM : OTG_HS_HCINTMSK_DTERRM_Field := 16#0#; -- unspecified - Reserved_22_25 : STM32F429x.UInt4 := 16#0#; - -- Clear NAK - CNAK : OTG_HS_DOEPCTL1_CNAK_Field := 16#0#; - -- Set NAK - SNAK : OTG_HS_DOEPCTL1_SNAK_Field := 16#0#; - -- Set DATA0 PID/Set even frame - SD0PID_SEVNFRM : OTG_HS_DOEPCTL1_SD0PID_SEVNFRM_Field := 16#0#; - -- Set odd frame - SODDFRM : OTG_HS_DOEPCTL1_SODDFRM_Field := 16#0#; - -- Endpoint disable - EPDIS : OTG_HS_DOEPCTL1_EPDIS_Field := 16#0#; - -- Endpoint enable - EPENA : OTG_HS_DOEPCTL1_EPENA_Field := 16#0#; + Reserved_11_31 : STM32F429x.UInt21 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPCTL_Register use record - MPSIZ at 0 range 0 .. 10; - Reserved_11_14 at 0 range 11 .. 14; - USBAEP at 0 range 15 .. 15; - EONUM_DPID at 0 range 16 .. 16; - NAKSTS at 0 range 17 .. 17; - EPTYP at 0 range 18 .. 19; - SNPM at 0 range 20 .. 20; - Stall at 0 range 21 .. 21; - Reserved_22_25 at 0 range 22 .. 25; - CNAK at 0 range 26 .. 26; - SNAK at 0 range 27 .. 27; - SD0PID_SEVNFRM at 0 range 28 .. 28; - SODDFRM at 0 range 29 .. 29; - EPDIS at 0 range 30 .. 30; - EPENA at 0 range 31 .. 31; + for OTG_HS_HCINTMSK_Register use record + XFRCM at 0 range 0 .. 0; + CHHM at 0 range 1 .. 1; + AHBERR at 0 range 2 .. 2; + STALLM at 0 range 3 .. 3; + NAKM at 0 range 4 .. 4; + ACKM at 0 range 5 .. 5; + NYET at 0 range 6 .. 6; + TXERRM at 0 range 7 .. 7; + BBERRM at 0 range 8 .. 8; + FRMORM at 0 range 9 .. 9; + DTERRM at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; end record; - ------------------------------ - -- OTG_HS_DOEPTSIZ_Register -- - ------------------------------ + subtype OTG_HS_HCTSIZ_XFRSIZ_Field is STM32F429x.UInt19; + subtype OTG_HS_HCTSIZ_PKTCNT_Field is STM32F429x.UInt10; + subtype OTG_HS_HCTSIZ_DPID_Field is STM32F429x.UInt2; - subtype OTG_HS_DOEPTSIZ1_XFRSIZ_Field is STM32F429x.UInt19; - subtype OTG_HS_DOEPTSIZ1_PKTCNT_Field is STM32F429x.UInt10; - subtype OTG_HS_DOEPTSIZ1_RXDPID_STUPCNT_Field is STM32F429x.UInt2; - - -- OTG_HS device endpoint-2 transfer size register - type OTG_HS_DOEPTSIZ_Register is record + -- OTG_HS host channel-11 transfer size register + type OTG_HS_HCTSIZ_Register is record -- Transfer size - XFRSIZ : OTG_HS_DOEPTSIZ1_XFRSIZ_Field := 16#0#; + XFRSIZ : OTG_HS_HCTSIZ_XFRSIZ_Field := 16#0#; -- Packet count - PKTCNT : OTG_HS_DOEPTSIZ1_PKTCNT_Field := 16#0#; - -- Received data PID/SETUP packet count - RXDPID_STUPCNT : OTG_HS_DOEPTSIZ1_RXDPID_STUPCNT_Field := 16#0#; + PKTCNT : OTG_HS_HCTSIZ_PKTCNT_Field := 16#0#; + -- Data PID + DPID : OTG_HS_HCTSIZ_DPID_Field := 16#0#; -- unspecified Reserved_31_31 : STM32F429x.Bit := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; - for OTG_HS_DOEPTSIZ_Register use record + for OTG_HS_HCTSIZ_Register use record XFRSIZ at 0 range 0 .. 18; PKTCNT at 0 range 19 .. 28; - RXDPID_STUPCNT at 0 range 29 .. 30; + DPID at 0 range 29 .. 30; Reserved_31_31 at 0 range 31 .. 31; end record; - --------------------------- - -- OTG_HS_PCGCR_Register -- - --------------------------- - subtype OTG_HS_PCGCR_STPPCLK_Field is STM32F429x.Bit; subtype OTG_HS_PCGCR_GATEHCLK_Field is STM32F429x.Bit; subtype OTG_HS_PCGCR_PHYSUSP_Field is STM32F429x.Bit; @@ -2388,7 +2166,7 @@ package STM32F429x.USB_OTG_HS is -- unspecified Reserved_5_31 : STM32F429x.UInt27 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for OTG_HS_PCGCR_Register use record STPPCLK at 0 range 0 .. 0; @@ -2403,543 +2181,719 @@ package STM32F429x.USB_OTG_HS is ----------------- -- USB on the go high speed - type OTG_HS_GLOBAL_Peripheral is record + type OTG_HS_DEVICE_Peripheral is record + -- OTG_HS device configuration register + OTG_HS_DCFG : aliased OTG_HS_DCFG_Register; + pragma Volatile_Full_Access (OTG_HS_DCFG); + -- OTG_HS device control register + OTG_HS_DCTL : aliased OTG_HS_DCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DCTL); + -- OTG_HS device status register + OTG_HS_DSTS : aliased OTG_HS_DSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DSTS); + -- OTG_HS device IN endpoint common interrupt mask register + OTG_HS_DIEPMSK : aliased OTG_HS_DIEPMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPMSK); + -- OTG_HS device OUT endpoint common interrupt mask register + OTG_HS_DOEPMSK : aliased OTG_HS_DOEPMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPMSK); + -- OTG_HS device all endpoints interrupt register + OTG_HS_DAINT : aliased OTG_HS_DAINT_Register; + pragma Volatile_Full_Access (OTG_HS_DAINT); + -- OTG_HS all endpoints interrupt mask register + OTG_HS_DAINTMSK : aliased OTG_HS_DAINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DAINTMSK); + -- OTG_HS device VBUS discharge time register + OTG_HS_DVBUSDIS : aliased OTG_HS_DVBUSDIS_Register; + pragma Volatile_Full_Access (OTG_HS_DVBUSDIS); + -- OTG_HS device VBUS pulsing time register + OTG_HS_DVBUSPULSE : aliased OTG_HS_DVBUSPULSE_Register; + pragma Volatile_Full_Access (OTG_HS_DVBUSPULSE); + -- OTG_HS Device threshold control register + OTG_HS_DTHRCTL : aliased OTG_HS_DTHRCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DTHRCTL); + -- OTG_HS device IN endpoint FIFO empty interrupt mask register + OTG_HS_DIEPEMPMSK : aliased OTG_HS_DIEPEMPMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPEMPMSK); + -- OTG_HS device each endpoint interrupt register + OTG_HS_DEACHINT : aliased OTG_HS_DEACHINT_Register; + pragma Volatile_Full_Access (OTG_HS_DEACHINT); + -- OTG_HS device each endpoint interrupt register mask + OTG_HS_DEACHINTMSK : aliased OTG_HS_DEACHINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_DEACHINTMSK); + -- OTG_HS device each in endpoint-1 interrupt register + OTG_HS_DIEPEACHMSK1 : aliased OTG_HS_DIEPEACHMSK1_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPEACHMSK1); + -- OTG_HS device each OUT endpoint-1 interrupt register + OTG_HS_DOEPEACHMSK1 : aliased OTG_HS_DOEPEACHMSK1_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPEACHMSK1); + -- OTG device endpoint-0 control register + OTG_HS_DIEPCTL0 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL0); + -- OTG device endpoint-0 interrupt register + OTG_HS_DIEPINT0 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT0); + -- OTG_HS device IN endpoint 0 transfer size register + OTG_HS_DIEPTSIZ0 : aliased OTG_HS_DIEPTSIZ0_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ0); + -- OTG_HS device endpoint-1 DMA address register + OTG_HS_DIEPDMA1 : aliased STM32F429x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS0 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS0); + -- OTG device endpoint-1 control register + OTG_HS_DIEPCTL1 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL1); + -- OTG device endpoint-1 interrupt register + OTG_HS_DIEPINT1 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT1); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ1 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ1); + -- OTG_HS device endpoint-2 DMA address register + OTG_HS_DIEPDMA2 : aliased STM32F429x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS1 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS1); + -- OTG device endpoint-2 control register + OTG_HS_DIEPCTL2 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL2); + -- OTG device endpoint-2 interrupt register + OTG_HS_DIEPINT2 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT2); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ2 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ2); + -- OTG_HS device endpoint-3 DMA address register + OTG_HS_DIEPDMA3 : aliased STM32F429x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS2 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS2); + -- OTG device endpoint-3 control register + OTG_HS_DIEPCTL3 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL3); + -- OTG device endpoint-3 interrupt register + OTG_HS_DIEPINT3 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT3); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ3 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ3); + -- OTG_HS device endpoint-4 DMA address register + OTG_HS_DIEPDMA4 : aliased STM32F429x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS3 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS3); + -- OTG device endpoint-4 control register + OTG_HS_DIEPCTL4 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL4); + -- OTG device endpoint-4 interrupt register + OTG_HS_DIEPINT4 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT4); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ4 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ4); + -- OTG_HS device endpoint-5 DMA address register + OTG_HS_DIEPDMA5 : aliased STM32F429x.UInt32; + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS4 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS4); + -- OTG device endpoint-5 control register + OTG_HS_DIEPCTL5 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL5); + -- OTG device endpoint-5 interrupt register + OTG_HS_DIEPINT5 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT5); + -- OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ5 : aliased OTG_HS_DIEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTSIZ5); + -- OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS5 : aliased OTG_HS_DTXFSTS_Register; + pragma Volatile_Full_Access (OTG_HS_DTXFSTS5); + -- OTG device endpoint-6 control register + OTG_HS_DIEPCTL6 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL6); + -- OTG device endpoint-6 interrupt register + OTG_HS_DIEPINT6 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT6); + -- OTG device endpoint-7 control register + OTG_HS_DIEPCTL7 : aliased OTG_HS_DIEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPCTL7); + -- OTG device endpoint-7 interrupt register + OTG_HS_DIEPINT7 : aliased OTG_HS_DIEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPINT7); + -- OTG_HS device control OUT endpoint 0 control register + OTG_HS_DOEPCTL0 : aliased OTG_HS_DOEPCTL0_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPCTL0); + -- OTG_HS device endpoint-0 interrupt register + OTG_HS_DOEPINT0 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT0); + -- OTG_HS device endpoint-1 transfer size register + OTG_HS_DOEPTSIZ0 : aliased OTG_HS_DOEPTSIZ0_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ0); + -- OTG device endpoint-1 control register + OTG_HS_DOEPCTL1 : aliased OTG_HS_DOEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPCTL1); + -- OTG_HS device endpoint-1 interrupt register + OTG_HS_DOEPINT1 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT1); + -- OTG_HS device endpoint-2 transfer size register + OTG_HS_DOEPTSIZ1 : aliased OTG_HS_DOEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ1); + -- OTG device endpoint-2 control register + OTG_HS_DOEPCTL2 : aliased OTG_HS_DOEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPCTL2); + -- OTG_HS device endpoint-2 interrupt register + OTG_HS_DOEPINT2 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT2); + -- OTG_HS device endpoint-3 transfer size register + OTG_HS_DOEPTSIZ2 : aliased OTG_HS_DOEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ2); + -- OTG device endpoint-3 control register + OTG_HS_DOEPCTL3 : aliased OTG_HS_DOEPCTL_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPCTL3); + -- OTG_HS device endpoint-3 interrupt register + OTG_HS_DOEPINT3 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT3); + -- OTG_HS device endpoint-4 transfer size register + OTG_HS_DOEPTSIZ3 : aliased OTG_HS_DOEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ3); + -- OTG_HS device endpoint-4 interrupt register + OTG_HS_DOEPINT4 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT4); + -- OTG_HS device endpoint-5 transfer size register + OTG_HS_DOEPTSIZ4 : aliased OTG_HS_DOEPTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPTSIZ4); + -- OTG_HS device endpoint-5 interrupt register + OTG_HS_DOEPINT5 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT5); + -- OTG_HS device endpoint-6 interrupt register + OTG_HS_DOEPINT6 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT6); + -- OTG_HS device endpoint-7 interrupt register + OTG_HS_DOEPINT7 : aliased OTG_HS_DOEPINT_Register; + pragma Volatile_Full_Access (OTG_HS_DOEPINT7); + end record + with Volatile; + + for OTG_HS_DEVICE_Peripheral use record + OTG_HS_DCFG at 16#0# range 0 .. 31; + OTG_HS_DCTL at 16#4# range 0 .. 31; + OTG_HS_DSTS at 16#8# range 0 .. 31; + OTG_HS_DIEPMSK at 16#10# range 0 .. 31; + OTG_HS_DOEPMSK at 16#14# range 0 .. 31; + OTG_HS_DAINT at 16#18# range 0 .. 31; + OTG_HS_DAINTMSK at 16#1C# range 0 .. 31; + OTG_HS_DVBUSDIS at 16#28# range 0 .. 31; + OTG_HS_DVBUSPULSE at 16#2C# range 0 .. 31; + OTG_HS_DTHRCTL at 16#30# range 0 .. 31; + OTG_HS_DIEPEMPMSK at 16#34# range 0 .. 31; + OTG_HS_DEACHINT at 16#38# range 0 .. 31; + OTG_HS_DEACHINTMSK at 16#3C# range 0 .. 31; + OTG_HS_DIEPEACHMSK1 at 16#40# range 0 .. 31; + OTG_HS_DOEPEACHMSK1 at 16#80# range 0 .. 31; + OTG_HS_DIEPCTL0 at 16#100# range 0 .. 31; + OTG_HS_DIEPINT0 at 16#108# range 0 .. 31; + OTG_HS_DIEPTSIZ0 at 16#110# range 0 .. 31; + OTG_HS_DIEPDMA1 at 16#114# range 0 .. 31; + OTG_HS_DTXFSTS0 at 16#118# range 0 .. 31; + OTG_HS_DIEPCTL1 at 16#120# range 0 .. 31; + OTG_HS_DIEPINT1 at 16#128# range 0 .. 31; + OTG_HS_DIEPTSIZ1 at 16#130# range 0 .. 31; + OTG_HS_DIEPDMA2 at 16#134# range 0 .. 31; + OTG_HS_DTXFSTS1 at 16#138# range 0 .. 31; + OTG_HS_DIEPCTL2 at 16#140# range 0 .. 31; + OTG_HS_DIEPINT2 at 16#148# range 0 .. 31; + OTG_HS_DIEPTSIZ2 at 16#150# range 0 .. 31; + OTG_HS_DIEPDMA3 at 16#154# range 0 .. 31; + OTG_HS_DTXFSTS2 at 16#158# range 0 .. 31; + OTG_HS_DIEPCTL3 at 16#160# range 0 .. 31; + OTG_HS_DIEPINT3 at 16#168# range 0 .. 31; + OTG_HS_DIEPTSIZ3 at 16#170# range 0 .. 31; + OTG_HS_DIEPDMA4 at 16#174# range 0 .. 31; + OTG_HS_DTXFSTS3 at 16#178# range 0 .. 31; + OTG_HS_DIEPCTL4 at 16#180# range 0 .. 31; + OTG_HS_DIEPINT4 at 16#188# range 0 .. 31; + OTG_HS_DIEPTSIZ4 at 16#190# range 0 .. 31; + OTG_HS_DIEPDMA5 at 16#194# range 0 .. 31; + OTG_HS_DTXFSTS4 at 16#198# range 0 .. 31; + OTG_HS_DIEPCTL5 at 16#1A0# range 0 .. 31; + OTG_HS_DIEPINT5 at 16#1A8# range 0 .. 31; + OTG_HS_DIEPTSIZ5 at 16#1B0# range 0 .. 31; + OTG_HS_DTXFSTS5 at 16#1B8# range 0 .. 31; + OTG_HS_DIEPCTL6 at 16#1C0# range 0 .. 31; + OTG_HS_DIEPINT6 at 16#1C8# range 0 .. 31; + OTG_HS_DIEPCTL7 at 16#1E0# range 0 .. 31; + OTG_HS_DIEPINT7 at 16#1E8# range 0 .. 31; + OTG_HS_DOEPCTL0 at 16#300# range 0 .. 31; + OTG_HS_DOEPINT0 at 16#308# range 0 .. 31; + OTG_HS_DOEPTSIZ0 at 16#310# range 0 .. 31; + OTG_HS_DOEPCTL1 at 16#320# range 0 .. 31; + OTG_HS_DOEPINT1 at 16#328# range 0 .. 31; + OTG_HS_DOEPTSIZ1 at 16#330# range 0 .. 31; + OTG_HS_DOEPCTL2 at 16#340# range 0 .. 31; + OTG_HS_DOEPINT2 at 16#348# range 0 .. 31; + OTG_HS_DOEPTSIZ2 at 16#350# range 0 .. 31; + OTG_HS_DOEPCTL3 at 16#360# range 0 .. 31; + OTG_HS_DOEPINT3 at 16#368# range 0 .. 31; + OTG_HS_DOEPTSIZ3 at 16#370# range 0 .. 31; + OTG_HS_DOEPINT4 at 16#388# range 0 .. 31; + OTG_HS_DOEPTSIZ4 at 16#390# range 0 .. 31; + OTG_HS_DOEPINT5 at 16#3A8# range 0 .. 31; + OTG_HS_DOEPINT6 at 16#3C8# range 0 .. 31; + OTG_HS_DOEPINT7 at 16#3E8# range 0 .. 31; + end record; + + -- USB on the go high speed + OTG_HS_DEVICE_Periph : aliased OTG_HS_DEVICE_Peripheral + with Import, Address => OTG_HS_DEVICE_Base; + + type OTG_HS_GLOBAL_Disc is + (Host, + Peripheral, + Gnptxfsiz_Host, + Tx0Fsiz_Peripheral); + + -- USB on the go high speed + type OTG_HS_GLOBAL_Peripheral + (Discriminent : OTG_HS_GLOBAL_Disc := Host) + is record -- OTG_HS control and status register - OTG_HS_GOTGCTL : OTG_HS_GOTGCTL_Register; + OTG_HS_GOTGCTL : aliased OTG_HS_GOTGCTL_Register; + pragma Volatile_Full_Access (OTG_HS_GOTGCTL); -- OTG_HS interrupt register - OTG_HS_GOTGINT : OTG_HS_GOTGINT_Register; + OTG_HS_GOTGINT : aliased OTG_HS_GOTGINT_Register; + pragma Volatile_Full_Access (OTG_HS_GOTGINT); -- OTG_HS AHB configuration register - OTG_HS_GAHBCFG : OTG_HS_GAHBCFG_Register; + OTG_HS_GAHBCFG : aliased OTG_HS_GAHBCFG_Register; + pragma Volatile_Full_Access (OTG_HS_GAHBCFG); -- OTG_HS USB configuration register - OTG_HS_GUSBCFG : OTG_HS_GUSBCFG_Register; + OTG_HS_GUSBCFG : aliased OTG_HS_GUSBCFG_Register; + pragma Volatile_Full_Access (OTG_HS_GUSBCFG); -- OTG_HS reset register - OTG_HS_GRSTCTL : OTG_HS_GRSTCTL_Register; + OTG_HS_GRSTCTL : aliased OTG_HS_GRSTCTL_Register; + pragma Volatile_Full_Access (OTG_HS_GRSTCTL); -- OTG_HS core interrupt register - OTG_HS_GINTSTS : OTG_HS_GINTSTS_Register; + OTG_HS_GINTSTS : aliased OTG_HS_GINTSTS_Register; + pragma Volatile_Full_Access (OTG_HS_GINTSTS); -- OTG_HS interrupt mask register - OTG_HS_GINTMSK : OTG_HS_GINTMSK_Register; - -- OTG_HS Receive status debug read register (host mode) - OTG_HS_GRXSTSR : OTG_HS_GRXSTSR_Host_Register; - -- OTG_HS status read and pop register (host mode) - OTG_HS_GRXSTSP : OTG_HS_GRXSTSP_Host_Register; + OTG_HS_GINTMSK : aliased OTG_HS_GINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_GINTMSK); -- OTG_HS Receive FIFO size register - OTG_HS_GRXFSIZ : OTG_HS_GRXFSIZ_Register; - -- OTG_HS nonperiodic transmit FIFO size register (host mode) - OTG_HS : OTG_HS_GNPTXFSIZ_Host_Register; + OTG_HS_GRXFSIZ : aliased OTG_HS_GRXFSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_GRXFSIZ); -- OTG_HS nonperiodic transmit FIFO/queue status register - OTG_HS_GNPTXSTS : OTG_HS_GNPTXSTS_Register; + OTG_HS_GNPTXSTS : aliased OTG_HS_GNPTXSTS_Register; + pragma Volatile_Full_Access (OTG_HS_GNPTXSTS); -- OTG_HS general core configuration register - OTG_HS_GCCFG : OTG_HS_GCCFG_Register; + OTG_HS_GCCFG : aliased OTG_HS_GCCFG_Register; + pragma Volatile_Full_Access (OTG_HS_GCCFG); -- OTG_HS core ID register - OTG_HS_CID : STM32F429x.Word; + OTG_HS_CID : aliased STM32F429x.UInt32; -- OTG_HS Host periodic transmit FIFO size register - OTG_HS_HPTXFSIZ : OTG_HS_HPTXFSIZ_Register; + OTG_HS_HPTXFSIZ : aliased OTG_HS_HPTXFSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HPTXFSIZ); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF1 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF1 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF1); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF2 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF2 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF2); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF3 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF3 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF3); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF4 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF4 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF4); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF5 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF5 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF5); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF6 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF6 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF6); -- OTG_HS device IN endpoint transmit FIFO size register - OTG_HS_DIEPTXF7 : OTG_HS_DIEPTXF_Register; + OTG_HS_DIEPTXF7 : aliased OTG_HS_DIEPTXF_Register; + pragma Volatile_Full_Access (OTG_HS_DIEPTXF7); + case Discriminent is + when Host => + -- OTG_HS Receive status debug read register (host mode) + OTG_HS_GRXSTSR_Host : aliased OTG_HS_GRXSTSR_Host_Register; + pragma Volatile_Full_Access (OTG_HS_GRXSTSR_Host); + -- OTG_HS status read and pop register (host mode) + OTG_HS_GRXSTSP_Host : aliased OTG_HS_GRXSTSP_Host_Register; + pragma Volatile_Full_Access (OTG_HS_GRXSTSP_Host); + when Peripheral => + -- OTG_HS Receive status debug read register (peripheral mode + -- mode) + OTG_HS_GRXSTSR_Peripheral : aliased OTG_HS_GRXSTSR_Peripheral_Register; + pragma Volatile_Full_Access (OTG_HS_GRXSTSR_Peripheral); + -- OTG_HS status read and pop register (peripheral mode) + OTG_HS_GRXSTSP_Peripheral : aliased OTG_HS_GRXSTSP_Peripheral_Register; + pragma Volatile_Full_Access (OTG_HS_GRXSTSP_Peripheral); + when Gnptxfsiz_Host => + -- OTG_HS nonperiodic transmit FIFO size register (host mode) + OTG_HS_GNPTXFSIZ_Host : aliased OTG_HS_GNPTXFSIZ_Host_Register; + pragma Volatile_Full_Access (OTG_HS_GNPTXFSIZ_Host); + when Tx0Fsiz_Peripheral => + -- Endpoint 0 transmit FIFO size (peripheral mode) + OTG_HS_TX0FSIZ_Peripheral : aliased OTG_HS_TX0FSIZ_Peripheral_Register; + pragma Volatile_Full_Access (OTG_HS_TX0FSIZ_Peripheral); + end case; end record - with Volatile; + with Unchecked_Union, Volatile; for OTG_HS_GLOBAL_Peripheral use record - OTG_HS_GOTGCTL at 0 range 0 .. 31; - OTG_HS_GOTGINT at 4 range 0 .. 31; - OTG_HS_GAHBCFG at 8 range 0 .. 31; - OTG_HS_GUSBCFG at 12 range 0 .. 31; - OTG_HS_GRSTCTL at 16 range 0 .. 31; - OTG_HS_GINTSTS at 20 range 0 .. 31; - OTG_HS_GINTMSK at 24 range 0 .. 31; - OTG_HS_GRXSTSR at 28 range 0 .. 31; - OTG_HS_GRXSTSP at 32 range 0 .. 31; - OTG_HS_GRXFSIZ at 36 range 0 .. 31; - OTG_HS at 40 range 0 .. 31; - OTG_HS_GNPTXSTS at 44 range 0 .. 31; - OTG_HS_GCCFG at 56 range 0 .. 31; - OTG_HS_CID at 60 range 0 .. 31; - OTG_HS_HPTXFSIZ at 256 range 0 .. 31; - OTG_HS_DIEPTXF1 at 260 range 0 .. 31; - OTG_HS_DIEPTXF2 at 264 range 0 .. 31; - OTG_HS_DIEPTXF3 at 284 range 0 .. 31; - OTG_HS_DIEPTXF4 at 288 range 0 .. 31; - OTG_HS_DIEPTXF5 at 292 range 0 .. 31; - OTG_HS_DIEPTXF6 at 296 range 0 .. 31; - OTG_HS_DIEPTXF7 at 300 range 0 .. 31; + OTG_HS_GOTGCTL at 16#0# range 0 .. 31; + OTG_HS_GOTGINT at 16#4# range 0 .. 31; + OTG_HS_GAHBCFG at 16#8# range 0 .. 31; + OTG_HS_GUSBCFG at 16#C# range 0 .. 31; + OTG_HS_GRSTCTL at 16#10# range 0 .. 31; + OTG_HS_GINTSTS at 16#14# range 0 .. 31; + OTG_HS_GINTMSK at 16#18# range 0 .. 31; + OTG_HS_GRXFSIZ at 16#24# range 0 .. 31; + OTG_HS_GNPTXSTS at 16#2C# range 0 .. 31; + OTG_HS_GCCFG at 16#38# range 0 .. 31; + OTG_HS_CID at 16#3C# range 0 .. 31; + OTG_HS_HPTXFSIZ at 16#100# range 0 .. 31; + OTG_HS_DIEPTXF1 at 16#104# range 0 .. 31; + OTG_HS_DIEPTXF2 at 16#108# range 0 .. 31; + OTG_HS_DIEPTXF3 at 16#11C# range 0 .. 31; + OTG_HS_DIEPTXF4 at 16#120# range 0 .. 31; + OTG_HS_DIEPTXF5 at 16#124# range 0 .. 31; + OTG_HS_DIEPTXF6 at 16#128# range 0 .. 31; + OTG_HS_DIEPTXF7 at 16#12C# range 0 .. 31; + OTG_HS_GRXSTSR_Host at 16#1C# range 0 .. 31; + OTG_HS_GRXSTSP_Host at 16#20# range 0 .. 31; + OTG_HS_GRXSTSR_Peripheral at 16#1C# range 0 .. 31; + OTG_HS_GRXSTSP_Peripheral at 16#20# range 0 .. 31; + OTG_HS_GNPTXFSIZ_Host at 16#28# range 0 .. 31; + OTG_HS_TX0FSIZ_Peripheral at 16#28# range 0 .. 31; end record; -- USB on the go high speed OTG_HS_GLOBAL_Periph : aliased OTG_HS_GLOBAL_Peripheral - with Import, Address => System'To_Address (16#40040000#); + with Import, Address => OTG_HS_GLOBAL_Base; -- USB on the go high speed type OTG_HS_HOST_Peripheral is record -- OTG_HS host configuration register - OTG_HS_HCFG : OTG_HS_HCFG_Register; + OTG_HS_HCFG : aliased OTG_HS_HCFG_Register; + pragma Volatile_Full_Access (OTG_HS_HCFG); -- OTG_HS Host frame interval register - OTG_HS_HFIR : OTG_HS_HFIR_Register; + OTG_HS_HFIR : aliased OTG_HS_HFIR_Register; + pragma Volatile_Full_Access (OTG_HS_HFIR); -- OTG_HS host frame number/frame time remaining register - OTG_HS_HFNUM : OTG_HS_HFNUM_Register; + OTG_HS_HFNUM : aliased OTG_HS_HFNUM_Register; + pragma Volatile_Full_Access (OTG_HS_HFNUM); -- OTG_HS_Host periodic transmit FIFO/queue status register - OTG_HS_HPTXSTS : OTG_HS_HPTXSTS_Register; + OTG_HS_HPTXSTS : aliased OTG_HS_HPTXSTS_Register; + pragma Volatile_Full_Access (OTG_HS_HPTXSTS); -- OTG_HS Host all channels interrupt register - OTG_HS_HAINT : OTG_HS_HAINT_Register; + OTG_HS_HAINT : aliased OTG_HS_HAINT_Register; + pragma Volatile_Full_Access (OTG_HS_HAINT); -- OTG_HS host all channels interrupt mask register - OTG_HS_HAINTMSK : OTG_HS_HAINTMSK_Register; + OTG_HS_HAINTMSK : aliased OTG_HS_HAINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HAINTMSK); -- OTG_HS host port control and status register - OTG_HS_HPRT : OTG_HS_HPRT_Register; + OTG_HS_HPRT : aliased OTG_HS_HPRT_Register; + pragma Volatile_Full_Access (OTG_HS_HPRT); -- OTG_HS host channel-0 characteristics register - OTG_HS_HCCHAR0 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR0 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR0); -- OTG_HS host channel-0 split control register - OTG_HS_HCSPLT0 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT0 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT0); -- OTG_HS host channel-11 interrupt register - OTG_HS_HCINT0 : OTG_HS_HCINT_Register; + OTG_HS_HCINT0 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT0); -- OTG_HS host channel-11 interrupt mask register - OTG_HS_HCINTMSK0 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK0 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK0); -- OTG_HS host channel-11 transfer size register - OTG_HS_HCTSIZ0 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ0 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ0); -- OTG_HS host channel-0 DMA address register - OTG_HS_HCDMA0 : STM32F429x.Word; + OTG_HS_HCDMA0 : aliased STM32F429x.UInt32; -- OTG_HS host channel-1 characteristics register - OTG_HS_HCCHAR1 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR1 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR1); -- OTG_HS host channel-1 split control register - OTG_HS_HCSPLT1 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT1 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT1); -- OTG_HS host channel-1 interrupt register - OTG_HS_HCINT1 : OTG_HS_HCINT_Register; + OTG_HS_HCINT1 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT1); -- OTG_HS host channel-1 interrupt mask register - OTG_HS_HCINTMSK1 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK1 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK1); -- OTG_HS host channel-1 transfer size register - OTG_HS_HCTSIZ1 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ1 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ1); -- OTG_HS host channel-1 DMA address register - OTG_HS_HCDMA1 : STM32F429x.Word; + OTG_HS_HCDMA1 : aliased STM32F429x.UInt32; -- OTG_HS host channel-2 characteristics register - OTG_HS_HCCHAR2 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR2 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR2); -- OTG_HS host channel-2 split control register - OTG_HS_HCSPLT2 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT2 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT2); -- OTG_HS host channel-2 interrupt register - OTG_HS_HCINT2 : OTG_HS_HCINT_Register; + OTG_HS_HCINT2 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT2); -- OTG_HS host channel-2 interrupt mask register - OTG_HS_HCINTMSK2 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK2 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK2); -- OTG_HS host channel-2 transfer size register - OTG_HS_HCTSIZ2 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ2 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ2); -- OTG_HS host channel-2 DMA address register - OTG_HS_HCDMA2 : STM32F429x.Word; + OTG_HS_HCDMA2 : aliased STM32F429x.UInt32; -- OTG_HS host channel-3 characteristics register - OTG_HS_HCCHAR3 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR3 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR3); -- OTG_HS host channel-3 split control register - OTG_HS_HCSPLT3 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT3 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT3); -- OTG_HS host channel-3 interrupt register - OTG_HS_HCINT3 : OTG_HS_HCINT_Register; + OTG_HS_HCINT3 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT3); -- OTG_HS host channel-3 interrupt mask register - OTG_HS_HCINTMSK3 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK3 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK3); -- OTG_HS host channel-3 transfer size register - OTG_HS_HCTSIZ3 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ3 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ3); -- OTG_HS host channel-3 DMA address register - OTG_HS_HCDMA3 : STM32F429x.Word; + OTG_HS_HCDMA3 : aliased STM32F429x.UInt32; -- OTG_HS host channel-4 characteristics register - OTG_HS_HCCHAR4 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR4 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR4); -- OTG_HS host channel-4 split control register - OTG_HS_HCSPLT4 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT4 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT4); -- OTG_HS host channel-4 interrupt register - OTG_HS_HCINT4 : OTG_HS_HCINT_Register; + OTG_HS_HCINT4 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT4); -- OTG_HS host channel-4 interrupt mask register - OTG_HS_HCINTMSK4 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK4 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK4); -- OTG_HS host channel-4 transfer size register - OTG_HS_HCTSIZ4 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ4 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ4); -- OTG_HS host channel-4 DMA address register - OTG_HS_HCDMA4 : STM32F429x.Word; + OTG_HS_HCDMA4 : aliased STM32F429x.UInt32; -- OTG_HS host channel-5 characteristics register - OTG_HS_HCCHAR5 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR5 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR5); -- OTG_HS host channel-5 split control register - OTG_HS_HCSPLT5 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT5 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT5); -- OTG_HS host channel-5 interrupt register - OTG_HS_HCINT5 : OTG_HS_HCINT_Register; + OTG_HS_HCINT5 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT5); -- OTG_HS host channel-5 interrupt mask register - OTG_HS_HCINTMSK5 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK5 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK5); -- OTG_HS host channel-5 transfer size register - OTG_HS_HCTSIZ5 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ5 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ5); -- OTG_HS host channel-5 DMA address register - OTG_HS_HCDMA5 : STM32F429x.Word; + OTG_HS_HCDMA5 : aliased STM32F429x.UInt32; -- OTG_HS host channel-6 characteristics register - OTG_HS_HCCHAR6 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR6 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR6); -- OTG_HS host channel-6 split control register - OTG_HS_HCSPLT6 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT6 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT6); -- OTG_HS host channel-6 interrupt register - OTG_HS_HCINT6 : OTG_HS_HCINT_Register; + OTG_HS_HCINT6 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT6); -- OTG_HS host channel-6 interrupt mask register - OTG_HS_HCINTMSK6 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK6 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK6); -- OTG_HS host channel-6 transfer size register - OTG_HS_HCTSIZ6 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ6 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ6); -- OTG_HS host channel-6 DMA address register - OTG_HS_HCDMA6 : STM32F429x.Word; + OTG_HS_HCDMA6 : aliased STM32F429x.UInt32; -- OTG_HS host channel-7 characteristics register - OTG_HS_HCCHAR7 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR7 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR7); -- OTG_HS host channel-7 split control register - OTG_HS_HCSPLT7 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT7 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT7); -- OTG_HS host channel-7 interrupt register - OTG_HS_HCINT7 : OTG_HS_HCINT_Register; + OTG_HS_HCINT7 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT7); -- OTG_HS host channel-7 interrupt mask register - OTG_HS_HCINTMSK7 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK7 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK7); -- OTG_HS host channel-7 transfer size register - OTG_HS_HCTSIZ7 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ7 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ7); -- OTG_HS host channel-7 DMA address register - OTG_HS_HCDMA7 : STM32F429x.Word; + OTG_HS_HCDMA7 : aliased STM32F429x.UInt32; -- OTG_HS host channel-8 characteristics register - OTG_HS_HCCHAR8 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR8 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR8); -- OTG_HS host channel-8 split control register - OTG_HS_HCSPLT8 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT8 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT8); -- OTG_HS host channel-8 interrupt register - OTG_HS_HCINT8 : OTG_HS_HCINT_Register; + OTG_HS_HCINT8 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT8); -- OTG_HS host channel-8 interrupt mask register - OTG_HS_HCINTMSK8 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK8 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK8); -- OTG_HS host channel-8 transfer size register - OTG_HS_HCTSIZ8 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ8 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ8); -- OTG_HS host channel-8 DMA address register - OTG_HS_HCDMA8 : STM32F429x.Word; + OTG_HS_HCDMA8 : aliased STM32F429x.UInt32; -- OTG_HS host channel-9 characteristics register - OTG_HS_HCCHAR9 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR9 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR9); -- OTG_HS host channel-9 split control register - OTG_HS_HCSPLT9 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT9 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT9); -- OTG_HS host channel-9 interrupt register - OTG_HS_HCINT9 : OTG_HS_HCINT_Register; + OTG_HS_HCINT9 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT9); -- OTG_HS host channel-9 interrupt mask register - OTG_HS_HCINTMSK9 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK9 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK9); -- OTG_HS host channel-9 transfer size register - OTG_HS_HCTSIZ9 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ9 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ9); -- OTG_HS host channel-9 DMA address register - OTG_HS_HCDMA9 : STM32F429x.Word; + OTG_HS_HCDMA9 : aliased STM32F429x.UInt32; -- OTG_HS host channel-10 characteristics register - OTG_HS_HCCHAR10 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR10 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR10); -- OTG_HS host channel-10 split control register - OTG_HS_HCSPLT10 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT10 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT10); -- OTG_HS host channel-10 interrupt register - OTG_HS_HCINT10 : OTG_HS_HCINT_Register; + OTG_HS_HCINT10 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT10); -- OTG_HS host channel-10 interrupt mask register - OTG_HS_HCINTMSK10 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK10 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK10); -- OTG_HS host channel-10 transfer size register - OTG_HS_HCTSIZ10 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ10 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ10); -- OTG_HS host channel-10 DMA address register - OTG_HS_HCDMA10 : STM32F429x.Word; + OTG_HS_HCDMA10 : aliased STM32F429x.UInt32; -- OTG_HS host channel-11 characteristics register - OTG_HS_HCCHAR11 : OTG_HS_HCCHAR_Register; + OTG_HS_HCCHAR11 : aliased OTG_HS_HCCHAR_Register; + pragma Volatile_Full_Access (OTG_HS_HCCHAR11); -- OTG_HS host channel-11 split control register - OTG_HS_HCSPLT11 : OTG_HS_HCSPLT_Register; + OTG_HS_HCSPLT11 : aliased OTG_HS_HCSPLT_Register; + pragma Volatile_Full_Access (OTG_HS_HCSPLT11); -- OTG_HS host channel-11 interrupt register - OTG_HS_HCINT11 : OTG_HS_HCINT_Register; + OTG_HS_HCINT11 : aliased OTG_HS_HCINT_Register; + pragma Volatile_Full_Access (OTG_HS_HCINT11); -- OTG_HS host channel-11 interrupt mask register - OTG_HS_HCINTMSK11 : OTG_HS_HCINTMSK_Register; + OTG_HS_HCINTMSK11 : aliased OTG_HS_HCINTMSK_Register; + pragma Volatile_Full_Access (OTG_HS_HCINTMSK11); -- OTG_HS host channel-11 transfer size register - OTG_HS_HCTSIZ11 : OTG_HS_HCTSIZ_Register; + OTG_HS_HCTSIZ11 : aliased OTG_HS_HCTSIZ_Register; + pragma Volatile_Full_Access (OTG_HS_HCTSIZ11); -- OTG_HS host channel-11 DMA address register - OTG_HS_HCDMA11 : STM32F429x.Word; + OTG_HS_HCDMA11 : aliased STM32F429x.UInt32; end record with Volatile; for OTG_HS_HOST_Peripheral use record - OTG_HS_HCFG at 0 range 0 .. 31; - OTG_HS_HFIR at 4 range 0 .. 31; - OTG_HS_HFNUM at 8 range 0 .. 31; - OTG_HS_HPTXSTS at 16 range 0 .. 31; - OTG_HS_HAINT at 20 range 0 .. 31; - OTG_HS_HAINTMSK at 24 range 0 .. 31; - OTG_HS_HPRT at 64 range 0 .. 31; - OTG_HS_HCCHAR0 at 256 range 0 .. 31; - OTG_HS_HCSPLT0 at 260 range 0 .. 31; - OTG_HS_HCINT0 at 264 range 0 .. 31; - OTG_HS_HCINTMSK0 at 268 range 0 .. 31; - OTG_HS_HCTSIZ0 at 272 range 0 .. 31; - OTG_HS_HCDMA0 at 276 range 0 .. 31; - OTG_HS_HCCHAR1 at 288 range 0 .. 31; - OTG_HS_HCSPLT1 at 292 range 0 .. 31; - OTG_HS_HCINT1 at 296 range 0 .. 31; - OTG_HS_HCINTMSK1 at 300 range 0 .. 31; - OTG_HS_HCTSIZ1 at 304 range 0 .. 31; - OTG_HS_HCDMA1 at 308 range 0 .. 31; - OTG_HS_HCCHAR2 at 320 range 0 .. 31; - OTG_HS_HCSPLT2 at 324 range 0 .. 31; - OTG_HS_HCINT2 at 328 range 0 .. 31; - OTG_HS_HCINTMSK2 at 332 range 0 .. 31; - OTG_HS_HCTSIZ2 at 336 range 0 .. 31; - OTG_HS_HCDMA2 at 340 range 0 .. 31; - OTG_HS_HCCHAR3 at 352 range 0 .. 31; - OTG_HS_HCSPLT3 at 356 range 0 .. 31; - OTG_HS_HCINT3 at 360 range 0 .. 31; - OTG_HS_HCINTMSK3 at 364 range 0 .. 31; - OTG_HS_HCTSIZ3 at 368 range 0 .. 31; - OTG_HS_HCDMA3 at 372 range 0 .. 31; - OTG_HS_HCCHAR4 at 384 range 0 .. 31; - OTG_HS_HCSPLT4 at 388 range 0 .. 31; - OTG_HS_HCINT4 at 392 range 0 .. 31; - OTG_HS_HCINTMSK4 at 396 range 0 .. 31; - OTG_HS_HCTSIZ4 at 400 range 0 .. 31; - OTG_HS_HCDMA4 at 404 range 0 .. 31; - OTG_HS_HCCHAR5 at 416 range 0 .. 31; - OTG_HS_HCSPLT5 at 420 range 0 .. 31; - OTG_HS_HCINT5 at 424 range 0 .. 31; - OTG_HS_HCINTMSK5 at 428 range 0 .. 31; - OTG_HS_HCTSIZ5 at 432 range 0 .. 31; - OTG_HS_HCDMA5 at 436 range 0 .. 31; - OTG_HS_HCCHAR6 at 448 range 0 .. 31; - OTG_HS_HCSPLT6 at 452 range 0 .. 31; - OTG_HS_HCINT6 at 456 range 0 .. 31; - OTG_HS_HCINTMSK6 at 460 range 0 .. 31; - OTG_HS_HCTSIZ6 at 464 range 0 .. 31; - OTG_HS_HCDMA6 at 468 range 0 .. 31; - OTG_HS_HCCHAR7 at 480 range 0 .. 31; - OTG_HS_HCSPLT7 at 484 range 0 .. 31; - OTG_HS_HCINT7 at 488 range 0 .. 31; - OTG_HS_HCINTMSK7 at 492 range 0 .. 31; - OTG_HS_HCTSIZ7 at 496 range 0 .. 31; - OTG_HS_HCDMA7 at 500 range 0 .. 31; - OTG_HS_HCCHAR8 at 512 range 0 .. 31; - OTG_HS_HCSPLT8 at 516 range 0 .. 31; - OTG_HS_HCINT8 at 520 range 0 .. 31; - OTG_HS_HCINTMSK8 at 524 range 0 .. 31; - OTG_HS_HCTSIZ8 at 528 range 0 .. 31; - OTG_HS_HCDMA8 at 532 range 0 .. 31; - OTG_HS_HCCHAR9 at 544 range 0 .. 31; - OTG_HS_HCSPLT9 at 548 range 0 .. 31; - OTG_HS_HCINT9 at 552 range 0 .. 31; - OTG_HS_HCINTMSK9 at 556 range 0 .. 31; - OTG_HS_HCTSIZ9 at 560 range 0 .. 31; - OTG_HS_HCDMA9 at 564 range 0 .. 31; - OTG_HS_HCCHAR10 at 576 range 0 .. 31; - OTG_HS_HCSPLT10 at 580 range 0 .. 31; - OTG_HS_HCINT10 at 584 range 0 .. 31; - OTG_HS_HCINTMSK10 at 588 range 0 .. 31; - OTG_HS_HCTSIZ10 at 592 range 0 .. 31; - OTG_HS_HCDMA10 at 596 range 0 .. 31; - OTG_HS_HCCHAR11 at 608 range 0 .. 31; - OTG_HS_HCSPLT11 at 612 range 0 .. 31; - OTG_HS_HCINT11 at 616 range 0 .. 31; - OTG_HS_HCINTMSK11 at 620 range 0 .. 31; - OTG_HS_HCTSIZ11 at 624 range 0 .. 31; - OTG_HS_HCDMA11 at 628 range 0 .. 31; + OTG_HS_HCFG at 16#0# range 0 .. 31; + OTG_HS_HFIR at 16#4# range 0 .. 31; + OTG_HS_HFNUM at 16#8# range 0 .. 31; + OTG_HS_HPTXSTS at 16#10# range 0 .. 31; + OTG_HS_HAINT at 16#14# range 0 .. 31; + OTG_HS_HAINTMSK at 16#18# range 0 .. 31; + OTG_HS_HPRT at 16#40# range 0 .. 31; + OTG_HS_HCCHAR0 at 16#100# range 0 .. 31; + OTG_HS_HCSPLT0 at 16#104# range 0 .. 31; + OTG_HS_HCINT0 at 16#108# range 0 .. 31; + OTG_HS_HCINTMSK0 at 16#10C# range 0 .. 31; + OTG_HS_HCTSIZ0 at 16#110# range 0 .. 31; + OTG_HS_HCDMA0 at 16#114# range 0 .. 31; + OTG_HS_HCCHAR1 at 16#120# range 0 .. 31; + OTG_HS_HCSPLT1 at 16#124# range 0 .. 31; + OTG_HS_HCINT1 at 16#128# range 0 .. 31; + OTG_HS_HCINTMSK1 at 16#12C# range 0 .. 31; + OTG_HS_HCTSIZ1 at 16#130# range 0 .. 31; + OTG_HS_HCDMA1 at 16#134# range 0 .. 31; + OTG_HS_HCCHAR2 at 16#140# range 0 .. 31; + OTG_HS_HCSPLT2 at 16#144# range 0 .. 31; + OTG_HS_HCINT2 at 16#148# range 0 .. 31; + OTG_HS_HCINTMSK2 at 16#14C# range 0 .. 31; + OTG_HS_HCTSIZ2 at 16#150# range 0 .. 31; + OTG_HS_HCDMA2 at 16#154# range 0 .. 31; + OTG_HS_HCCHAR3 at 16#160# range 0 .. 31; + OTG_HS_HCSPLT3 at 16#164# range 0 .. 31; + OTG_HS_HCINT3 at 16#168# range 0 .. 31; + OTG_HS_HCINTMSK3 at 16#16C# range 0 .. 31; + OTG_HS_HCTSIZ3 at 16#170# range 0 .. 31; + OTG_HS_HCDMA3 at 16#174# range 0 .. 31; + OTG_HS_HCCHAR4 at 16#180# range 0 .. 31; + OTG_HS_HCSPLT4 at 16#184# range 0 .. 31; + OTG_HS_HCINT4 at 16#188# range 0 .. 31; + OTG_HS_HCINTMSK4 at 16#18C# range 0 .. 31; + OTG_HS_HCTSIZ4 at 16#190# range 0 .. 31; + OTG_HS_HCDMA4 at 16#194# range 0 .. 31; + OTG_HS_HCCHAR5 at 16#1A0# range 0 .. 31; + OTG_HS_HCSPLT5 at 16#1A4# range 0 .. 31; + OTG_HS_HCINT5 at 16#1A8# range 0 .. 31; + OTG_HS_HCINTMSK5 at 16#1AC# range 0 .. 31; + OTG_HS_HCTSIZ5 at 16#1B0# range 0 .. 31; + OTG_HS_HCDMA5 at 16#1B4# range 0 .. 31; + OTG_HS_HCCHAR6 at 16#1C0# range 0 .. 31; + OTG_HS_HCSPLT6 at 16#1C4# range 0 .. 31; + OTG_HS_HCINT6 at 16#1C8# range 0 .. 31; + OTG_HS_HCINTMSK6 at 16#1CC# range 0 .. 31; + OTG_HS_HCTSIZ6 at 16#1D0# range 0 .. 31; + OTG_HS_HCDMA6 at 16#1D4# range 0 .. 31; + OTG_HS_HCCHAR7 at 16#1E0# range 0 .. 31; + OTG_HS_HCSPLT7 at 16#1E4# range 0 .. 31; + OTG_HS_HCINT7 at 16#1E8# range 0 .. 31; + OTG_HS_HCINTMSK7 at 16#1EC# range 0 .. 31; + OTG_HS_HCTSIZ7 at 16#1F0# range 0 .. 31; + OTG_HS_HCDMA7 at 16#1F4# range 0 .. 31; + OTG_HS_HCCHAR8 at 16#200# range 0 .. 31; + OTG_HS_HCSPLT8 at 16#204# range 0 .. 31; + OTG_HS_HCINT8 at 16#208# range 0 .. 31; + OTG_HS_HCINTMSK8 at 16#20C# range 0 .. 31; + OTG_HS_HCTSIZ8 at 16#210# range 0 .. 31; + OTG_HS_HCDMA8 at 16#214# range 0 .. 31; + OTG_HS_HCCHAR9 at 16#220# range 0 .. 31; + OTG_HS_HCSPLT9 at 16#224# range 0 .. 31; + OTG_HS_HCINT9 at 16#228# range 0 .. 31; + OTG_HS_HCINTMSK9 at 16#22C# range 0 .. 31; + OTG_HS_HCTSIZ9 at 16#230# range 0 .. 31; + OTG_HS_HCDMA9 at 16#234# range 0 .. 31; + OTG_HS_HCCHAR10 at 16#240# range 0 .. 31; + OTG_HS_HCSPLT10 at 16#244# range 0 .. 31; + OTG_HS_HCINT10 at 16#248# range 0 .. 31; + OTG_HS_HCINTMSK10 at 16#24C# range 0 .. 31; + OTG_HS_HCTSIZ10 at 16#250# range 0 .. 31; + OTG_HS_HCDMA10 at 16#254# range 0 .. 31; + OTG_HS_HCCHAR11 at 16#260# range 0 .. 31; + OTG_HS_HCSPLT11 at 16#264# range 0 .. 31; + OTG_HS_HCINT11 at 16#268# range 0 .. 31; + OTG_HS_HCINTMSK11 at 16#26C# range 0 .. 31; + OTG_HS_HCTSIZ11 at 16#270# range 0 .. 31; + OTG_HS_HCDMA11 at 16#274# range 0 .. 31; end record; -- USB on the go high speed OTG_HS_HOST_Periph : aliased OTG_HS_HOST_Peripheral - with Import, Address => System'To_Address (16#40040400#); - - -- USB on the go high speed - type OTG_HS_DEVICE_Peripheral is record - -- OTG_HS device configuration register - OTG_HS_DCFG : OTG_HS_DCFG_Register; - -- OTG_HS device control register - OTG_HS_DCTL : OTG_HS_DCTL_Register; - -- OTG_HS device status register - OTG_HS_DSTS : OTG_HS_DSTS_Register; - -- OTG_HS device IN endpoint common interrupt mask register - OTG_HS_DIEPMSK : OTG_HS_DIEPMSK_Register; - -- OTG_HS device OUT endpoint common interrupt mask register - OTG_HS_DOEPMSK : OTG_HS_DOEPMSK_Register; - -- OTG_HS device all endpoints interrupt register - OTG_HS_DAINT : OTG_HS_DAINT_Register; - -- OTG_HS all endpoints interrupt mask register - OTG_HS_DAINTMSK : OTG_HS_DAINTMSK_Register; - -- OTG_HS device VBUS discharge time register - OTG_HS_DVBUSDIS : OTG_HS_DVBUSDIS_Register; - -- OTG_HS device VBUS pulsing time register - OTG_HS_DVBUSPULSE : OTG_HS_DVBUSPULSE_Register; - -- OTG_HS Device threshold control register - OTG_HS_DTHRCTL : OTG_HS_DTHRCTL_Register; - -- OTG_HS device IN endpoint FIFO empty interrupt mask register - OTG_HS_DIEPEMPMSK : OTG_HS_DIEPEMPMSK_Register; - -- OTG_HS device each endpoint interrupt register - OTG_HS_DEACHINT : OTG_HS_DEACHINT_Register; - -- OTG_HS device each endpoint interrupt register mask - OTG_HS_DEACHINTMSK : OTG_HS_DEACHINTMSK_Register; - -- OTG_HS device each in endpoint-1 interrupt register - OTG_HS_DIEPEACHMSK1 : OTG_HS_DIEPEACHMSK1_Register; - -- OTG_HS device each OUT endpoint-1 interrupt register - OTG_HS_DOEPEACHMSK1 : OTG_HS_DOEPEACHMSK1_Register; - -- OTG device endpoint-0 control register - OTG_HS_DIEPCTL0 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-0 interrupt register - OTG_HS_DIEPINT0 : OTG_HS_DIEPINT_Register; - -- OTG_HS device IN endpoint 0 transfer size register - OTG_HS_DIEPTSIZ0 : OTG_HS_DIEPTSIZ0_Register; - -- OTG_HS device endpoint-1 DMA address register - OTG_HS_DIEPDMA1 : STM32F429x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS0 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-1 control register - OTG_HS_DIEPCTL1 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-1 interrupt register - OTG_HS_DIEPINT1 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ1 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device endpoint-2 DMA address register - OTG_HS_DIEPDMA2 : STM32F429x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS1 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-2 control register - OTG_HS_DIEPCTL2 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-2 interrupt register - OTG_HS_DIEPINT2 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ2 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device endpoint-3 DMA address register - OTG_HS_DIEPDMA3 : STM32F429x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS2 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-3 control register - OTG_HS_DIEPCTL3 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-3 interrupt register - OTG_HS_DIEPINT3 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ3 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device endpoint-4 DMA address register - OTG_HS_DIEPDMA4 : STM32F429x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS3 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-4 control register - OTG_HS_DIEPCTL4 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-4 interrupt register - OTG_HS_DIEPINT4 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ4 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device endpoint-5 DMA address register - OTG_HS_DIEPDMA5 : STM32F429x.Word; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS4 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-5 control register - OTG_HS_DIEPCTL5 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-5 interrupt register - OTG_HS_DIEPINT5 : OTG_HS_DIEPINT_Register; - -- OTG_HS device endpoint transfer size register - OTG_HS_DIEPTSIZ5 : OTG_HS_DIEPTSIZ_Register; - -- OTG_HS device IN endpoint transmit FIFO status register - OTG_HS_DTXFSTS5 : OTG_HS_DTXFSTS_Register; - -- OTG device endpoint-6 control register - OTG_HS_DIEPCTL6 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-6 interrupt register - OTG_HS_DIEPINT6 : OTG_HS_DIEPINT_Register; - -- OTG device endpoint-7 control register - OTG_HS_DIEPCTL7 : OTG_HS_DIEPCTL_Register; - -- OTG device endpoint-7 interrupt register - OTG_HS_DIEPINT7 : OTG_HS_DIEPINT_Register; - -- OTG_HS device control OUT endpoint 0 control register - OTG_HS_DOEPCTL0 : OTG_HS_DOEPCTL0_Register; - -- OTG_HS device endpoint-0 interrupt register - OTG_HS_DOEPINT0 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-1 transfer size register - OTG_HS_DOEPTSIZ0 : OTG_HS_DOEPTSIZ0_Register; - -- OTG device endpoint-1 control register - OTG_HS_DOEPCTL1 : OTG_HS_DOEPCTL_Register; - -- OTG_HS device endpoint-1 interrupt register - OTG_HS_DOEPINT1 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-2 transfer size register - OTG_HS_DOEPTSIZ1 : OTG_HS_DOEPTSIZ_Register; - -- OTG device endpoint-2 control register - OTG_HS_DOEPCTL2 : OTG_HS_DOEPCTL_Register; - -- OTG_HS device endpoint-2 interrupt register - OTG_HS_DOEPINT2 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-3 transfer size register - OTG_HS_DOEPTSIZ2 : OTG_HS_DOEPTSIZ_Register; - -- OTG device endpoint-3 control register - OTG_HS_DOEPCTL3 : OTG_HS_DOEPCTL_Register; - -- OTG_HS device endpoint-3 interrupt register - OTG_HS_DOEPINT3 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-4 transfer size register - OTG_HS_DOEPTSIZ3 : OTG_HS_DOEPTSIZ_Register; - -- OTG_HS device endpoint-4 interrupt register - OTG_HS_DOEPINT4 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-5 transfer size register - OTG_HS_DOEPTSIZ4 : OTG_HS_DOEPTSIZ_Register; - -- OTG_HS device endpoint-5 interrupt register - OTG_HS_DOEPINT5 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-6 interrupt register - OTG_HS_DOEPINT6 : OTG_HS_DOEPINT_Register; - -- OTG_HS device endpoint-7 interrupt register - OTG_HS_DOEPINT7 : OTG_HS_DOEPINT_Register; - end record - with Volatile; - - for OTG_HS_DEVICE_Peripheral use record - OTG_HS_DCFG at 0 range 0 .. 31; - OTG_HS_DCTL at 4 range 0 .. 31; - OTG_HS_DSTS at 8 range 0 .. 31; - OTG_HS_DIEPMSK at 16 range 0 .. 31; - OTG_HS_DOEPMSK at 20 range 0 .. 31; - OTG_HS_DAINT at 24 range 0 .. 31; - OTG_HS_DAINTMSK at 28 range 0 .. 31; - OTG_HS_DVBUSDIS at 40 range 0 .. 31; - OTG_HS_DVBUSPULSE at 44 range 0 .. 31; - OTG_HS_DTHRCTL at 48 range 0 .. 31; - OTG_HS_DIEPEMPMSK at 52 range 0 .. 31; - OTG_HS_DEACHINT at 56 range 0 .. 31; - OTG_HS_DEACHINTMSK at 60 range 0 .. 31; - OTG_HS_DIEPEACHMSK1 at 64 range 0 .. 31; - OTG_HS_DOEPEACHMSK1 at 128 range 0 .. 31; - OTG_HS_DIEPCTL0 at 256 range 0 .. 31; - OTG_HS_DIEPINT0 at 264 range 0 .. 31; - OTG_HS_DIEPTSIZ0 at 272 range 0 .. 31; - OTG_HS_DIEPDMA1 at 276 range 0 .. 31; - OTG_HS_DTXFSTS0 at 280 range 0 .. 31; - OTG_HS_DIEPCTL1 at 288 range 0 .. 31; - OTG_HS_DIEPINT1 at 296 range 0 .. 31; - OTG_HS_DIEPTSIZ1 at 304 range 0 .. 31; - OTG_HS_DIEPDMA2 at 308 range 0 .. 31; - OTG_HS_DTXFSTS1 at 312 range 0 .. 31; - OTG_HS_DIEPCTL2 at 320 range 0 .. 31; - OTG_HS_DIEPINT2 at 328 range 0 .. 31; - OTG_HS_DIEPTSIZ2 at 336 range 0 .. 31; - OTG_HS_DIEPDMA3 at 340 range 0 .. 31; - OTG_HS_DTXFSTS2 at 344 range 0 .. 31; - OTG_HS_DIEPCTL3 at 352 range 0 .. 31; - OTG_HS_DIEPINT3 at 360 range 0 .. 31; - OTG_HS_DIEPTSIZ3 at 368 range 0 .. 31; - OTG_HS_DIEPDMA4 at 372 range 0 .. 31; - OTG_HS_DTXFSTS3 at 376 range 0 .. 31; - OTG_HS_DIEPCTL4 at 384 range 0 .. 31; - OTG_HS_DIEPINT4 at 392 range 0 .. 31; - OTG_HS_DIEPTSIZ4 at 400 range 0 .. 31; - OTG_HS_DIEPDMA5 at 404 range 0 .. 31; - OTG_HS_DTXFSTS4 at 408 range 0 .. 31; - OTG_HS_DIEPCTL5 at 416 range 0 .. 31; - OTG_HS_DIEPINT5 at 424 range 0 .. 31; - OTG_HS_DIEPTSIZ5 at 432 range 0 .. 31; - OTG_HS_DTXFSTS5 at 440 range 0 .. 31; - OTG_HS_DIEPCTL6 at 448 range 0 .. 31; - OTG_HS_DIEPINT6 at 456 range 0 .. 31; - OTG_HS_DIEPCTL7 at 480 range 0 .. 31; - OTG_HS_DIEPINT7 at 488 range 0 .. 31; - OTG_HS_DOEPCTL0 at 768 range 0 .. 31; - OTG_HS_DOEPINT0 at 776 range 0 .. 31; - OTG_HS_DOEPTSIZ0 at 784 range 0 .. 31; - OTG_HS_DOEPCTL1 at 800 range 0 .. 31; - OTG_HS_DOEPINT1 at 808 range 0 .. 31; - OTG_HS_DOEPTSIZ1 at 816 range 0 .. 31; - OTG_HS_DOEPCTL2 at 832 range 0 .. 31; - OTG_HS_DOEPINT2 at 840 range 0 .. 31; - OTG_HS_DOEPTSIZ2 at 848 range 0 .. 31; - OTG_HS_DOEPCTL3 at 864 range 0 .. 31; - OTG_HS_DOEPINT3 at 872 range 0 .. 31; - OTG_HS_DOEPTSIZ3 at 880 range 0 .. 31; - OTG_HS_DOEPINT4 at 904 range 0 .. 31; - OTG_HS_DOEPTSIZ4 at 912 range 0 .. 31; - OTG_HS_DOEPINT5 at 936 range 0 .. 31; - OTG_HS_DOEPINT6 at 968 range 0 .. 31; - OTG_HS_DOEPINT7 at 1000 range 0 .. 31; - end record; - - -- USB on the go high speed - OTG_HS_DEVICE_Periph : aliased OTG_HS_DEVICE_Peripheral - with Import, Address => System'To_Address (16#40040800#); + with Import, Address => OTG_HS_HOST_Base; -- USB on the go high speed type OTG_HS_PWRCLK_Peripheral is record -- Power and clock gating control register - OTG_HS_PCGCR : OTG_HS_PCGCR_Register; + OTG_HS_PCGCR : aliased OTG_HS_PCGCR_Register; + pragma Volatile_Full_Access (OTG_HS_PCGCR); end record with Volatile; @@ -2949,6 +2903,6 @@ package STM32F429x.USB_OTG_HS is -- USB on the go high speed OTG_HS_PWRCLK_Periph : aliased OTG_HS_PWRCLK_Peripheral - with Import, Address => System'To_Address (16#40040E00#); + with Import, Address => OTG_HS_PWRCLK_Base; end STM32F429x.USB_OTG_HS; diff --git a/stm32f429i/stm32f429x/stm32f429x-wwdg.ads b/stm32f429i/stm32f429x/stm32f429x-wwdg.ads index 30f1ce1..9fbc8a6 100644 --- a/stm32f429i/stm32f429x/stm32f429x-wwdg.ads +++ b/stm32f429i/stm32f429x/stm32f429x-wwdg.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -12,10 +14,6 @@ package STM32F429x.WWDG is -- Registers -- --------------- - ----------------- - -- CR_Register -- - ----------------- - subtype CR_T_Field is STM32F429x.UInt7; subtype CR_WDGA_Field is STM32F429x.Bit; @@ -28,7 +26,7 @@ package STM32F429x.WWDG is -- unspecified Reserved_8_31 : STM32F429x.UInt24 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CR_Register use record T at 0 range 0 .. 6; @@ -36,16 +34,7 @@ package STM32F429x.WWDG is Reserved_8_31 at 0 range 8 .. 31; end record; - ------------------ - -- CFR_Register -- - ------------------ - subtype CFR_W_Field is STM32F429x.UInt7; - - --------------- - -- CFR.WDGTB -- - --------------- - -- CFR_WDGTB array element subtype CFR_WDGTB_Element is STM32F429x.Bit; @@ -86,7 +75,7 @@ package STM32F429x.WWDG is -- unspecified Reserved_10_31 : STM32F429x.UInt22 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for CFR_Register use record W at 0 range 0 .. 6; @@ -95,10 +84,6 @@ package STM32F429x.WWDG is Reserved_10_31 at 0 range 10 .. 31; end record; - ----------------- - -- SR_Register -- - ----------------- - subtype SR_EWIF_Field is STM32F429x.Bit; -- Status register @@ -108,7 +93,7 @@ package STM32F429x.WWDG is -- unspecified Reserved_1_31 : STM32F429x.UInt31 := 16#0#; end record - with Volatile, Size => 32, Bit_Order => System.Low_Order_First; + with Object_Size => 32, Bit_Order => System.Low_Order_First; for SR_Register use record EWIF at 0 range 0 .. 0; @@ -122,22 +107,25 @@ package STM32F429x.WWDG is -- Window watchdog type WWDG_Peripheral is record -- Control register - CR : CR_Register; + CR : aliased CR_Register; + pragma Volatile_Full_Access (CR); -- Configuration register - CFR : CFR_Register; + CFR : aliased CFR_Register; + pragma Volatile_Full_Access (CFR); -- Status register - SR : SR_Register; + SR : aliased SR_Register; + pragma Volatile_Full_Access (SR); end record with Volatile; for WWDG_Peripheral use record - CR at 0 range 0 .. 31; - CFR at 4 range 0 .. 31; - SR at 8 range 0 .. 31; + CR at 16#0# range 0 .. 31; + CFR at 16#4# range 0 .. 31; + SR at 16#8# range 0 .. 31; end record; -- Window watchdog WWDG_Periph : aliased WWDG_Peripheral - with Import, Address => System'To_Address (16#40002C00#); + with Import, Address => WWDG_Base; end STM32F429x.WWDG; diff --git a/stm32f429i/stm32f429x/stm32f429x.ads b/stm32f429i/stm32f429x/stm32f429x.ads index 04eb915..08385d8 100644 --- a/stm32f429i/stm32f429x/stm32f429x.ads +++ b/stm32f429i/stm32f429x/stm32f429x.ads @@ -1,5 +1,7 @@ --- Automatically generated from STM32F429x.svd by SVD2Ada --- see https://github.com/simonjwright/svd2ada +pragma Ada_2012; +pragma Style_Checks (Off); + +-- This spec has been automatically generated from STM32F429x.svd pragma Restrictions (No_Elaboration_Code); @@ -9,16 +11,14 @@ with System; -- STM32F429x package STM32F429x is pragma Preelaborate; - Version : constant String := - "1.0"; --------------- -- Base type -- --------------- - subtype Word is Interfaces.Unsigned_32; - subtype Short is Interfaces.Unsigned_16; - subtype Byte is Interfaces.Unsigned_8; + type UInt32 is new Interfaces.Unsigned_32; + type UInt16 is new Interfaces.Unsigned_16; + type Byte is new Interfaces.Unsigned_8; type Bit is mod 2**1 with Size => 1; type UInt2 is mod 2**2 @@ -82,171 +82,88 @@ package STM32F429x is -- Base addresses -- -------------------- - RNG_Base : constant System.Address := - System'To_Address (16#50060800#); - DCMI_Base : constant System.Address := - System'To_Address (16#50050000#); - FMC_Base : constant System.Address := - System'To_Address (16#A0000000#); - DBG_Base : constant System.Address := - System'To_Address (16#E0042000#); - DMA2_Base : constant System.Address := - System'To_Address (16#40026400#); - DMA1_Base : constant System.Address := - System'To_Address (16#40026000#); - RCC_Base : constant System.Address := - System'To_Address (16#40023800#); - GPIOK_Base : constant System.Address := - System'To_Address (16#40022800#); - GPIOJ_Base : constant System.Address := - System'To_Address (16#40022400#); - GPIOI_Base : constant System.Address := - System'To_Address (16#40022000#); - GPIOH_Base : constant System.Address := - System'To_Address (16#40021C00#); - GPIOG_Base : constant System.Address := - System'To_Address (16#40021800#); - GPIOF_Base : constant System.Address := - System'To_Address (16#40021400#); - GPIOE_Base : constant System.Address := - System'To_Address (16#40021000#); - GPIOD_Base : constant System.Address := - System'To_Address (16#40020C00#); - GPIOC_Base : constant System.Address := - System'To_Address (16#40020800#); - GPIOB_Base : constant System.Address := - System'To_Address (16#40020400#); - GPIOA_Base : constant System.Address := - System'To_Address (16#40020000#); - SYSCFG_Base : constant System.Address := - System'To_Address (16#40013800#); - SPI1_Base : constant System.Address := - System'To_Address (16#40013000#); - SPI2_Base : constant System.Address := - System'To_Address (16#40003800#); - SPI3_Base : constant System.Address := - System'To_Address (16#40003C00#); - I2S2ext_Base : constant System.Address := - System'To_Address (16#40003400#); - I2S3ext_Base : constant System.Address := - System'To_Address (16#40004000#); - SPI4_Base : constant System.Address := - System'To_Address (16#40013400#); - SPI5_Base : constant System.Address := - System'To_Address (16#40015000#); - SPI6_Base : constant System.Address := - System'To_Address (16#40015400#); - SDIO_Base : constant System.Address := - System'To_Address (16#40012C00#); - ADC1_Base : constant System.Address := - System'To_Address (16#40012000#); - ADC2_Base : constant System.Address := - System'To_Address (16#40012100#); - ADC3_Base : constant System.Address := - System'To_Address (16#40012200#); - USART6_Base : constant System.Address := - System'To_Address (16#40011400#); - USART1_Base : constant System.Address := - System'To_Address (16#40011000#); - USART2_Base : constant System.Address := - System'To_Address (16#40004400#); - USART3_Base : constant System.Address := - System'To_Address (16#40004800#); - UART7_Base : constant System.Address := - System'To_Address (16#40007800#); - UART8_Base : constant System.Address := - System'To_Address (16#40007C00#); - DAC_Base : constant System.Address := - System'To_Address (16#40007400#); - PWR_Base : constant System.Address := - System'To_Address (16#40007000#); - I2C3_Base : constant System.Address := - System'To_Address (16#40005C00#); - I2C2_Base : constant System.Address := - System'To_Address (16#40005800#); - I2C1_Base : constant System.Address := - System'To_Address (16#40005400#); - IWDG_Base : constant System.Address := - System'To_Address (16#40003000#); - WWDG_Base : constant System.Address := - System'To_Address (16#40002C00#); - RTC_Base : constant System.Address := - System'To_Address (16#40002800#); - UART4_Base : constant System.Address := - System'To_Address (16#40004C00#); - UART5_Base : constant System.Address := - System'To_Address (16#40005000#); - C_ADC_Base : constant System.Address := - System'To_Address (16#40012300#); - TIM1_Base : constant System.Address := - System'To_Address (16#40010000#); - TIM8_Base : constant System.Address := - System'To_Address (16#40010400#); - TIM2_Base : constant System.Address := - System'To_Address (16#40000000#); - TIM3_Base : constant System.Address := - System'To_Address (16#40000400#); - TIM4_Base : constant System.Address := - System'To_Address (16#40000800#); - TIM5_Base : constant System.Address := - System'To_Address (16#40000C00#); - TIM9_Base : constant System.Address := - System'To_Address (16#40014000#); - TIM12_Base : constant System.Address := - System'To_Address (16#40001800#); - TIM10_Base : constant System.Address := - System'To_Address (16#40014400#); - TIM13_Base : constant System.Address := - System'To_Address (16#40001C00#); - TIM14_Base : constant System.Address := - System'To_Address (16#40002000#); - TIM11_Base : constant System.Address := - System'To_Address (16#40014800#); - TIM6_Base : constant System.Address := - System'To_Address (16#40001000#); - TIM7_Base : constant System.Address := - System'To_Address (16#40001400#); - Ethernet_MAC_Base : constant System.Address := - System'To_Address (16#40028000#); - Ethernet_MMC_Base : constant System.Address := - System'To_Address (16#40028100#); - Ethernet_PTP_Base : constant System.Address := - System'To_Address (16#40028700#); - Ethernet_DMA_Base : constant System.Address := - System'To_Address (16#40029000#); - CRC_Base : constant System.Address := - System'To_Address (16#40023000#); - OTG_FS_GLOBAL_Base : constant System.Address := - System'To_Address (16#50000000#); - OTG_FS_HOST_Base : constant System.Address := - System'To_Address (16#50000400#); - OTG_FS_DEVICE_Base : constant System.Address := - System'To_Address (16#50000800#); - OTG_FS_PWRCLK_Base : constant System.Address := - System'To_Address (16#50000E00#); - CAN1_Base : constant System.Address := - System'To_Address (16#40006400#); - CAN2_Base : constant System.Address := - System'To_Address (16#40006800#); - NVIC_Base : constant System.Address := - System'To_Address (16#E000E000#); - FLASH_Base : constant System.Address := - System'To_Address (16#40023C00#); - EXTI_Base : constant System.Address := - System'To_Address (16#40013C00#); - OTG_HS_GLOBAL_Base : constant System.Address := - System'To_Address (16#40040000#); - OTG_HS_HOST_Base : constant System.Address := - System'To_Address (16#40040400#); - OTG_HS_DEVICE_Base : constant System.Address := - System'To_Address (16#40040800#); - OTG_HS_PWRCLK_Base : constant System.Address := - System'To_Address (16#40040E00#); - LTDC_Base : constant System.Address := - System'To_Address (16#40016800#); - SAI_Base : constant System.Address := - System'To_Address (16#40015800#); - DMA2D_Base : constant System.Address := - System'To_Address (16#4002B000#); + RNG_Base : constant System.Address := System'To_Address (16#50060800#); + DCMI_Base : constant System.Address := System'To_Address (16#50050000#); + FMC_Base : constant System.Address := System'To_Address (16#A0000000#); + DBG_Base : constant System.Address := System'To_Address (16#E0042000#); + DMA2_Base : constant System.Address := System'To_Address (16#40026400#); + DMA1_Base : constant System.Address := System'To_Address (16#40026000#); + RCC_Base : constant System.Address := System'To_Address (16#40023800#); + GPIOK_Base : constant System.Address := System'To_Address (16#40022800#); + GPIOJ_Base : constant System.Address := System'To_Address (16#40022400#); + GPIOI_Base : constant System.Address := System'To_Address (16#40022000#); + GPIOH_Base : constant System.Address := System'To_Address (16#40021C00#); + GPIOG_Base : constant System.Address := System'To_Address (16#40021800#); + GPIOF_Base : constant System.Address := System'To_Address (16#40021400#); + GPIOE_Base : constant System.Address := System'To_Address (16#40021000#); + GPIOD_Base : constant System.Address := System'To_Address (16#40020C00#); + GPIOC_Base : constant System.Address := System'To_Address (16#40020800#); + GPIOB_Base : constant System.Address := System'To_Address (16#40020400#); + GPIOA_Base : constant System.Address := System'To_Address (16#40020000#); + SYSCFG_Base : constant System.Address := System'To_Address (16#40013800#); + SPI1_Base : constant System.Address := System'To_Address (16#40013000#); + SPI2_Base : constant System.Address := System'To_Address (16#40003800#); + SPI3_Base : constant System.Address := System'To_Address (16#40003C00#); + I2S2ext_Base : constant System.Address := System'To_Address (16#40003400#); + I2S3ext_Base : constant System.Address := System'To_Address (16#40004000#); + SPI4_Base : constant System.Address := System'To_Address (16#40013400#); + SPI5_Base : constant System.Address := System'To_Address (16#40015000#); + SPI6_Base : constant System.Address := System'To_Address (16#40015400#); + SDIO_Base : constant System.Address := System'To_Address (16#40012C00#); + ADC1_Base : constant System.Address := System'To_Address (16#40012000#); + ADC2_Base : constant System.Address := System'To_Address (16#40012100#); + ADC3_Base : constant System.Address := System'To_Address (16#40012200#); + USART6_Base : constant System.Address := System'To_Address (16#40011400#); + USART1_Base : constant System.Address := System'To_Address (16#40011000#); + USART2_Base : constant System.Address := System'To_Address (16#40004400#); + USART3_Base : constant System.Address := System'To_Address (16#40004800#); + DAC_Base : constant System.Address := System'To_Address (16#40007400#); + PWR_Base : constant System.Address := System'To_Address (16#40007000#); + I2C3_Base : constant System.Address := System'To_Address (16#40005C00#); + I2C2_Base : constant System.Address := System'To_Address (16#40005800#); + I2C1_Base : constant System.Address := System'To_Address (16#40005400#); + IWDG_Base : constant System.Address := System'To_Address (16#40003000#); + WWDG_Base : constant System.Address := System'To_Address (16#40002C00#); + RTC_Base : constant System.Address := System'To_Address (16#40002800#); + UART4_Base : constant System.Address := System'To_Address (16#40004C00#); + UART5_Base : constant System.Address := System'To_Address (16#40005000#); + UART7_Base : constant System.Address := System'To_Address (16#40007800#); + UART8_Base : constant System.Address := System'To_Address (16#40007C00#); + C_ADC_Base : constant System.Address := System'To_Address (16#40012300#); + TIM1_Base : constant System.Address := System'To_Address (16#40010000#); + TIM8_Base : constant System.Address := System'To_Address (16#40010400#); + TIM2_Base : constant System.Address := System'To_Address (16#40000000#); + TIM3_Base : constant System.Address := System'To_Address (16#40000400#); + TIM4_Base : constant System.Address := System'To_Address (16#40000800#); + TIM5_Base : constant System.Address := System'To_Address (16#40000C00#); + TIM9_Base : constant System.Address := System'To_Address (16#40014000#); + TIM12_Base : constant System.Address := System'To_Address (16#40001800#); + TIM10_Base : constant System.Address := System'To_Address (16#40014400#); + TIM13_Base : constant System.Address := System'To_Address (16#40001C00#); + TIM14_Base : constant System.Address := System'To_Address (16#40002000#); + TIM11_Base : constant System.Address := System'To_Address (16#40014800#); + TIM6_Base : constant System.Address := System'To_Address (16#40001000#); + TIM7_Base : constant System.Address := System'To_Address (16#40001400#); + Ethernet_MAC_Base : constant System.Address := System'To_Address (16#40028000#); + Ethernet_MMC_Base : constant System.Address := System'To_Address (16#40028100#); + Ethernet_PTP_Base : constant System.Address := System'To_Address (16#40028700#); + Ethernet_DMA_Base : constant System.Address := System'To_Address (16#40029000#); + CRC_Base : constant System.Address := System'To_Address (16#40023000#); + OTG_FS_GLOBAL_Base : constant System.Address := System'To_Address (16#50000000#); + OTG_FS_HOST_Base : constant System.Address := System'To_Address (16#50000400#); + OTG_FS_DEVICE_Base : constant System.Address := System'To_Address (16#50000800#); + OTG_FS_PWRCLK_Base : constant System.Address := System'To_Address (16#50000E00#); + CAN1_Base : constant System.Address := System'To_Address (16#40006400#); + CAN2_Base : constant System.Address := System'To_Address (16#40006800#); + NVIC_Base : constant System.Address := System'To_Address (16#E000E000#); + FLASH_Base : constant System.Address := System'To_Address (16#40023C00#); + EXTI_Base : constant System.Address := System'To_Address (16#40013C00#); + OTG_HS_GLOBAL_Base : constant System.Address := System'To_Address (16#40040000#); + OTG_HS_HOST_Base : constant System.Address := System'To_Address (16#40040400#); + OTG_HS_DEVICE_Base : constant System.Address := System'To_Address (16#40040800#); + OTG_HS_PWRCLK_Base : constant System.Address := System'To_Address (16#40040E00#); + LTDC_Base : constant System.Address := System'To_Address (16#40016800#); + SAI_Base : constant System.Address := System'To_Address (16#40015800#); + DMA2D_Base : constant System.Address := System'To_Address (16#4002B000#); end STM32F429x;