Compact PCI Serial EEM ecosystem

There were several discussions about possible backplane specification. Compact PCI Serial (CPCIS) standard seems to fit the EEM ecosystem quite nicely. There are however several constraints:

• The CPCIS defines slots as 4HP only, this means that 8HP EEM modules would waste precious slots or would have to be modified to support MCX connectors.
• Another is I2C support. CPCIS defines common bus across the backplane, EEM assumes individual buses between modules and the carrier board.
• CPCIS defines boards as 160mm long but existing EEM modules are also 160mm long, so all of them would have to support CPCIS connectors which makes them incompatible with the existing EEM ecosystem. Dual-connector boards are possible but can be implemented only on the new product releases.
• we have 8 LVDS and 16 LVDS (dual EEM) modules. Both modes need to be supported.

CERN plans to implement a slightly modified CPCIS chassis for their Distributed IO Tier system. The idea is to unify an essential part of the accelerator instrumentation. The only modification to existing CPCI backplane is the assembly of the backplane on 220mm depths. Such modified chassis can be ordered directly from Schroff nVent. The user can also modify it by using longer guide rails. The 24579-416 backplane has additional space that can be used for the installation of DIO modules or adapters using ribbon cables with IDC connectors. CERN also wants to develop custom CPCIS components that better match their need:

• radiation hard 100W power supply, compatible with CPCIS specification
• 84HP backplane compatible with CPCIS chassis, utilizing 8x 8HP CPCIS modules
• Controllers based on Rad-Tolerant FPGAs and standard SoCs like Zynq.

There goals seem to be nearly identical as ours. To overcom the constraints we propose following CPSIs ecosystem:

• standard CPCIS chassis with backplane mounted on 220mm depth. The Power supply has dedicated backplane mounted on 160mm.
• Existing EEM modules can be used in such 220mm chassis with Adapter.
• I2C access will be ensured by using PCI_EN lines which are dedicated to every CPCIS slot. Each module has 220Ohm pulldown to GND on PCI_EN line. The same line is used to enable analog multiplexer that connects EEM I2C bus with backplane I2C bus. The controller will first probe status of the line with weak pullup. If low state is detected, it will overdrive the line with 3.3V signal and read the unique ID and board FRU content that describes module features like unique name.
• to support both single EEM and dual EEM modules, the CPCIS Adapter modul will have 2 connectors. Lower, P1 for first 8 LVDS links and upper, P6 for next 6 LVDS links.
• DRTIO clock can be distributed using dedicated backplane line foreseen for PCI clock distribution. Every adapter can convert it to sinle ended mode and route it to MMCX connector. The EEM modules that need that clock can source it either from Clocker module or from the adapter depending on required noise performance.
• Existing 8HP modules can be used with CPCIS Adapter on the right most slot without wasting CPCIS slots.