Today goal:
- get ZCU LED demo running
- Flash FPGA with Neha's firmware
- Drive a pin of FPGA with spacely -> changed to see the clock produced by FPGA on scope
- Understand exactly the test goal for the v0 chip
- Adam included some i2c writes for communicating with the car board. The ZCU LED demo peary code does not have the functions defined, nor does it need it. Therefore, while spacely was running it was trying to call functions that did not exist. Specifically in /asic/projects/C/CMS_PIX_28/testing/spacely/PySpacely/src/Spacely_Caribou.py on L101 the function self.car_i2c_write is called. Inside of the SpacelyCaribouBasic peary device this function is defined https://gitlab.cern.ch/adquinn/peary/-/blob/aq_dev/devices/SpacelyCaribouBasic/SpacelyCaribouBasicDevice.cpp?ref_type=heads#L93. In the ZCU102_LED_Demo this function is not defined, nor needed. A quick fix is commenting out the car_i2c_write lines inside of the Spacely_Caribou.py file.
#Important config steps to make sure CaR board is set up to work.
def configure_car(self):
self.log.debug("~ ~ Configuring CaR board ~ ~")
self.log.debug("[Step 1] Setting PCA9539 Dir to Output")
self.log.debug("WARNING: anthony commented out car_i2c_write's to perform tests without carboard")
#self.car_i2c_write(0,0x76,6,0) # commented out by anthony to test LED demo
#self.car_i2c_write(0,0x76,7,0) # commented out by anthony to test LED demo
self.log.debug("~ ~ Done Configuring CaR board ~ ~")
- In the SPROCKET3A_Config.py file needed to comment out all of the V_XXX
- Successfully ran the candy game
- To run the game again:
- inside of Master_Config.py set
TARGET = "SPROCKET3A" - flash firmware with ZCU LED demo
- inside of Master_Config.py set
Instructions from Neha to generate bitstream locally:
git clone [email protected]:SpacelyProject/spacely-caribou-common-blocks.git
git checkout nh_cms28_pix_fw
cd vivado directory
launch vivado
open project - project_1
Here you need to choose .xpr file, this loads all settings, configuration and target for project
Then click on "Generate Bitstream" - it will run synthesis, implementation and generate bitstream
Then File --> Export --> Export Hardware --> Next --> Include Bitstream --> Create XSA
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Goal is to write to reg_wrdout and then read reg_rddin. reg_rddin[0] = status reg, reg_rddin[1] = dataout reg. We need to assign these registers so that we see them.
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From Adam: reg_rddin is the collection of all the registers in your design. Most likely what you want to do is pull out the individual registers by name. For example, see this from the SPI controller interface:
assign reg_rddin[FPGA_SPI_WR] = fpga_reg_spi_read_write;
assign reg_rddin[FPGA_SPI_ADDRESS] = fpga_reg_spi_address;
assign reg_rddin[FPGA_SPI_DATA_LEN] = fpga_reg_spi_data_len;
assign reg_rddin[FPGA_SPI_WRITE_DATA] = fpga_reg_spi_write_data;
assign reg_rddin[FPGA_SPI_READ_DATA] = fpga_reg_spi_read_data;
assign reg_rddin[FPGA_SPI_OPCODE_GROUP] = fpga_reg_spi_opcode_group;
assign reg_rddin[FPGA_CLOCK_DIVIDE_FACTOR] = fpga_reg_clock_divide_factor;
You could do reg_rddin[0] = status_reg (or whichever). This also gives you your register offsets. The offset for status_reg is just 0, and the offset for configout/dataout would be 1.
- I think I should add these lines right here https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/nh_cms28_pix_fw/configReg_interface/src/configReg_interface.sv#L156
// Register instantiation for configReg
logic status_reg, configout_dataout_reg;
// Pull out the individual registers by name
assign reg_rddin[0] = status_reg;
assign reg_rddin[1] = configout_dataout_reg;