From 1d452073438951b4fea0e1833bc04732d2cbdeb5 Mon Sep 17 00:00:00 2001 From: Dror Prital Date: Wed, 25 Dec 2024 16:58:50 +0000 Subject: [PATCH] Integrate HW-MGMT 7.0040.2101 Changes ## Patch List * 0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch : --- ...support-for-MPS-Multi-phase-mp2891-c.patch | 8 +- ...x-Introduce-support-of-Nvidia-smart-.patch | 24 +-- ...x-mlx-platform-Add-support-for-new-N.patch | 162 ++++++++++++++++++ patch/kconfig-inclusions | 1 + patch/series | 1 + 5 files changed, 180 insertions(+), 16 deletions(-) create mode 100644 patch/0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch diff --git a/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch b/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch index 3a8ece6b9..6cc2c505b 100644 --- a/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch +++ b/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch @@ -342,14 +342,14 @@ index 000000000..522c0bb5f + ret = pmbus_read_word_data(client, page, phase, MP2891_PMBUS_VOUT_MIN); + if (ret <= 0) + return ret; -+ ret = (ret & GENMASK(10, 0)) * data->vid_step[page] * 105; -+ return DIV_ROUND_CLOSEST(ret, 10000); ++ ret = (ret & GENMASK(10, 0)) * data->vid_step[page]; ++ return DIV_ROUND_CLOSEST(ret, 100); + case PMBUS_VOUT_OV_FAULT_LIMIT: + ret = pmbus_read_word_data(client, page, phase, PMBUS_VOUT_MAX); + if (ret <= 0) + return ret; -+ ret = (ret & GENMASK(10, 0)) * data->vid_step[page] * 95; -+ return DIV_ROUND_CLOSEST(ret, 10000); ++ ret = (ret & GENMASK(10, 0)) * data->vid_step[page]; ++ return DIV_ROUND_CLOSEST(ret, 100); + case PMBUS_IOUT_UC_FAULT_LIMIT: + ret = pmbus_read_word_data(client, page, phase, reg); + return ret <= 0 ? ret : DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * diff --git a/patch/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch b/patch/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch index b7435002f..98b911881 100644 --- a/patch/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch +++ b/patch/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch @@ -507,50 +507,50 @@ index cafa4f762..0949f32ad 100644 + .label = "dpu1_rst", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0200, ++ .mode = 0644, }, { - .label = "tacho10", + .label = "dpu2_rst", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu3_rst", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu4_rst", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu1_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu2_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu3_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu4_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "reset_long_pb", @@ -800,25 +800,25 @@ index cafa4f762..0949f32ad 100644 + .label = "dpu1_pwr_force", + .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu2_pwr_force", + .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu3_pwr_force", + .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "dpu4_pwr_force", + .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0200, ++ .mode = 0644, + }, + { + .label = "ufm_done", diff --git a/patch/0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch b/patch/0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch new file mode 100644 index 000000000..9c362bc89 --- /dev/null +++ b/patch/0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch @@ -0,0 +1,162 @@ +From 60e5f8cfdf6bd3a18ffef73764e59ccd53bba9ff Mon Sep 17 00:00:00 2001 +From: Oleksandr Shamray +Date: Fri, 11 Oct 2024 11:09:32 +0300 +Subject: [PATCH 1/3] platform: mellanox: mlx-platform: Add support for new + Nvidia system + +Add support for SN5640 Nvidia switch. + +SN5640 is a 51.2Tbps switch based on Nvidia SPC-5 ASIC. +It provides up-to 400Gbps full bidirectional bandwidth per port. +The system supports 64 OSFP cages and fits into standard 2U racks. + +SN5640 Features: + - 64 OSFP ports supporting 2.5Gbps - 400Gbps speeds. + - Air-cooled with 4 + 1 redundant fan units. + - 2 + 2 redundant 2000W PSUs. + - System management board based on AMD CPU with secure-boot support. + +Signed-off-by: Oleksandr Shamray +Reviewed-by: Vadim Pasternak +--- + drivers/platform/mellanox/mlx-platform.c | 96 ++++++++++++++++++++++++ + 1 file changed, 96 insertions(+) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index f94e2f2f6776..5796e4695a2a 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -2131,6 +2131,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { + }, + }; + ++ + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { + .irq = MLXPLAT_CPLD_LPC_SYSIRQ, +@@ -2941,6 +2942,60 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, + }; + ++static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = { ++ { ++ .data = mlxplat_mlxcpld_ext_psu_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = MLXPLAT_CPLD_PSU_EXT_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_modular_pwr_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = MLXPLAT_CPLD_PWR_EXT_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_fan_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_default_asic_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++}; ++ ++static ++struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_hi171_data = { ++ .items = mlxplat_mlxcpld_ng800_hi171_items, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_hi171_items), ++ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, ++ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, ++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, ++}; ++ ++ + /* Platform hotplug for NVLink blade systems family data */ + static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { + { +@@ -5115,6 +5170,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, ++ { ++ .label = "shutdown_unlock", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, + { + .label = "erot1_ap_reset", + .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, +@@ -8267,6 +8328,27 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d + return mlxplat_register_platform_device(); + } + ++static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); ++ mlxplat_mux_data = mlxplat_ng800_mux_data; ++ mlxplat_hotplug = &mlxplat_mlxcpld_ng800_hi171_data; ++ mlxplat_hotplug->deferred_nr = ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; ++ mlxplat_led = &mlxplat_xdr_led_data; ++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; ++ mlxplat_fan = &mlxplat_xdr_fan_data; ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) ++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type3[i]; ++ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; ++ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; ++ ++ return mlxplat_register_platform_device(); ++} ++ + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + { + .callback = mlxplat_dmi_default_wc_matched, +@@ -8386,6 +8468,20 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), + }, + }, ++ { ++ .callback = mlxplat_dmi_ng400_hi171_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI171"), ++ }, ++ }, ++ { ++ .callback = mlxplat_dmi_ng400_hi171_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"), ++ }, ++ }, + { + .callback = mlxplat_dmi_msn274x_matched, + .matches = { +-- +2.20.1 + diff --git a/patch/kconfig-inclusions b/patch/kconfig-inclusions index 36c7b73fb..009ccd679 100644 --- a/patch/kconfig-inclusions +++ b/patch/kconfig-inclusions @@ -125,6 +125,7 @@ CONFIG_SPI_AMD=m CONFIG_PINCTRL_AMD=y CONFIG_EDAC_AMD64=m CONFIG_AMD_XGBE_DCB=y +CONFIG_SENSORS_ISL68137=m ###-> mellanox_amd64-end # For Cisco 8000 CONFIG_PHYLIB=m diff --git a/patch/series b/patch/series index 5a2dae61a..240527254 100755 --- a/patch/series +++ b/patch/series @@ -142,6 +142,7 @@ Support-for-fullcone-nat.patch 0093-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch 0094-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch 0095-platform-mellanox-nvsw-sn2201-Add-support-for-new-sy.patch +0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch 8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch 8003-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch 8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch