From 6398086a1a87ddea78274521683ba3ad817bee82 Mon Sep 17 00:00:00 2001
From: oclyke <owen.lyke@sparkfun.com>
Date: Wed, 23 Sep 2020 13:52:46 -0400
Subject: [PATCH] regen bsps

---
 artemis_dk/bsp/am_bsp_pins.h                  |  20 +-
 artemis_dk/bsp/gcc/bin/libam_bsp.a            | Bin 28952 -> 28952 bytes
 artemis_module/bsp/am_bsp_pins.h              |  20 +-
 artemis_thing_plus/bsp/am_bsp_pins.h          |  20 +-
 artemis_thing_plus/bsp/gcc/bin/libam_bsp.a    | Bin 26542 -> 26690 bytes
 edge/bsp/am_bsp_pins.h                        | 727 ++++++++++++++++++
 edge/bsp/gcc/bin/libam_bsp.a                  | Bin 29884 -> 30032 bytes
 edge2/bsp/am_bsp_pins.h                       |  20 +-
 edge2/bsp/gcc/bin/libam_bsp.a                 | Bin 29570 -> 29718 bytes
 redboard_artemis/bsp/am_bsp_pins.h            |  20 +-
 redboard_artemis/bsp/gcc/bin/libam_bsp.a      | Bin 26210 -> 26358 bytes
 redboard_artemis_atp/bsp/am_bsp_pins.h        |  20 +-
 redboard_artemis_atp/bsp/gcc/bin/libam_bsp.a  | Bin 26210 -> 26358 bytes
 redboard_artemis_nano/bsp/am_bsp_pins.h       |  20 +-
 redboard_artemis_nano/bsp/gcc/bin/libam_bsp.a | Bin 26210 -> 26358 bytes
 15 files changed, 797 insertions(+), 70 deletions(-)

diff --git a/artemis_dk/bsp/am_bsp_pins.h b/artemis_dk/bsp/am_bsp_pins.h
index 3a49e21..272ed33 100644
--- a/artemis_dk/bsp/am_bsp_pins.h
+++ b/artemis_dk/bsp/am_bsp_pins.h
@@ -213,7 +213,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_RX;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS             	11
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
-#define AM_BSP_IOM0_CS_CHNL             0
+#define AM_BSP_GPIO_IOM0_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -222,7 +222,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS3            	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS3;
-#define AM_BSP_IOM0_CS3_CHNL            3
+#define AM_BSP_GPIO_IOM0_CS3_CHNL       3
 
 //*****************************************************************************
 //
@@ -271,7 +271,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM1_CS             	14
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_CS;
-#define AM_BSP_IOM1_CS_CHNL             2
+#define AM_BSP_GPIO_IOM1_CS_CHNL        2
 
 //*****************************************************************************
 //
@@ -320,7 +320,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM2_CS             	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_CS;
-#define AM_BSP_IOM2_CS_CHNL             3
+#define AM_BSP_GPIO_IOM2_CS_CHNL        3
 
 //*****************************************************************************
 //
@@ -369,7 +369,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM3_CS             	12
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_CS;
-#define AM_BSP_IOM3_CS_CHNL             0
+#define AM_BSP_GPIO_IOM3_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -418,7 +418,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM4_CS             	13
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_CS;
-#define AM_BSP_IOM4_CS_CHNL             1
+#define AM_BSP_GPIO_IOM4_CS_CHNL        1
 
 //*****************************************************************************
 //
@@ -467,7 +467,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM5_CS             	16
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_CS;
-#define AM_BSP_IOM5_CS_CHNL             0
+#define AM_BSP_GPIO_IOM5_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -516,7 +516,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE0            	19
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
-#define AM_BSP_MSPI_CE0_CHNL            0
+#define AM_BSP_GPIO_MSPI_CE0_CHNL       0
 
 //*****************************************************************************
 //
@@ -525,7 +525,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE1            	41
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE1;
-#define AM_BSP_MSPI_CE1_CHNL            1
+#define AM_BSP_GPIO_MSPI_CE1_CHNL       1
 
 //*****************************************************************************
 //
@@ -606,7 +606,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_SCK;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOS_CE              	3
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_CE;
-#define AM_BSP_IOS_CE_CHNL              0
+#define AM_BSP_GPIO_IOS_CE_CHNL         0
 
 //*****************************************************************************
 //
diff --git a/artemis_dk/bsp/gcc/bin/libam_bsp.a b/artemis_dk/bsp/gcc/bin/libam_bsp.a
index 0f9a38ce519f39bd2b98bf1888983b90788ac11d..c27d21c46bf3da8334f2834f213a13dac972ef65 100644
GIT binary patch
delta 52
qcmbR7h;hav#tD*~W(Ecp7RDw<W*e2>b0K(}rMTtIk+@Dy*Yp6DFAi@2

delta 52
qcmbR7h;hav#tD*~rk0lGCT1p<78{k`b0K(}rMTtIk+@Dy*Yp6KHx9P|

diff --git a/artemis_module/bsp/am_bsp_pins.h b/artemis_module/bsp/am_bsp_pins.h
index 943ee27..e781cb9 100644
--- a/artemis_module/bsp/am_bsp_pins.h
+++ b/artemis_module/bsp/am_bsp_pins.h
@@ -85,7 +85,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_RX;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS             	11
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
-#define AM_BSP_IOM0_CS_CHNL             0
+#define AM_BSP_GPIO_IOM0_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -94,7 +94,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS3            	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS3;
-#define AM_BSP_IOM0_CS3_CHNL            3
+#define AM_BSP_GPIO_IOM0_CS3_CHNL       3
 
 //*****************************************************************************
 //
@@ -143,7 +143,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM1_CS             	14
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_CS;
-#define AM_BSP_IOM1_CS_CHNL             2
+#define AM_BSP_GPIO_IOM1_CS_CHNL        2
 
 //*****************************************************************************
 //
@@ -192,7 +192,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM2_CS             	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_CS;
-#define AM_BSP_IOM2_CS_CHNL             3
+#define AM_BSP_GPIO_IOM2_CS_CHNL        3
 
 //*****************************************************************************
 //
@@ -241,7 +241,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM3_CS             	12
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_CS;
-#define AM_BSP_IOM3_CS_CHNL             0
+#define AM_BSP_GPIO_IOM3_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -290,7 +290,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM4_CS             	13
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_CS;
-#define AM_BSP_IOM4_CS_CHNL             1
+#define AM_BSP_GPIO_IOM4_CS_CHNL        1
 
 //*****************************************************************************
 //
@@ -339,7 +339,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM5_CS             	16
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_CS;
-#define AM_BSP_IOM5_CS_CHNL             0
+#define AM_BSP_GPIO_IOM5_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -388,7 +388,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE0            	19
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
-#define AM_BSP_MSPI_CE0_CHNL            0
+#define AM_BSP_GPIO_MSPI_CE0_CHNL       0
 
 //*****************************************************************************
 //
@@ -397,7 +397,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE1            	41
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE1;
-#define AM_BSP_MSPI_CE1_CHNL            1
+#define AM_BSP_GPIO_MSPI_CE1_CHNL       1
 
 //*****************************************************************************
 //
@@ -478,7 +478,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_SCK;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOS_CE              	3
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_CE;
-#define AM_BSP_IOS_CE_CHNL              0
+#define AM_BSP_GPIO_IOS_CE_CHNL         0
 
 //*****************************************************************************
 //
diff --git a/artemis_thing_plus/bsp/am_bsp_pins.h b/artemis_thing_plus/bsp/am_bsp_pins.h
index b16a8c0..a547949 100644
--- a/artemis_thing_plus/bsp/am_bsp_pins.h
+++ b/artemis_thing_plus/bsp/am_bsp_pins.h
@@ -117,7 +117,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_RX;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS             	11
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
-#define AM_BSP_IOM0_CS_CHNL             0
+#define AM_BSP_GPIO_IOM0_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -126,7 +126,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS3            	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS3;
-#define AM_BSP_IOM0_CS3_CHNL            3
+#define AM_BSP_GPIO_IOM0_CS3_CHNL       3
 
 //*****************************************************************************
 //
@@ -175,7 +175,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM1_CS             	14
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_CS;
-#define AM_BSP_IOM1_CS_CHNL             2
+#define AM_BSP_GPIO_IOM1_CS_CHNL        2
 
 //*****************************************************************************
 //
@@ -224,7 +224,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM2_CS             	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_CS;
-#define AM_BSP_IOM2_CS_CHNL             3
+#define AM_BSP_GPIO_IOM2_CS_CHNL        3
 
 //*****************************************************************************
 //
@@ -273,7 +273,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM3_CS             	12
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_CS;
-#define AM_BSP_IOM3_CS_CHNL             0
+#define AM_BSP_GPIO_IOM3_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -322,7 +322,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM4_CS             	13
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_CS;
-#define AM_BSP_IOM4_CS_CHNL             1
+#define AM_BSP_GPIO_IOM4_CS_CHNL        1
 
 //*****************************************************************************
 //
@@ -371,7 +371,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM5_CS             	16
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_CS;
-#define AM_BSP_IOM5_CS_CHNL             0
+#define AM_BSP_GPIO_IOM5_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -420,7 +420,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE0            	19
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
-#define AM_BSP_MSPI_CE0_CHNL            0
+#define AM_BSP_GPIO_MSPI_CE0_CHNL       0
 
 //*****************************************************************************
 //
@@ -429,7 +429,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE1            	41
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE1;
-#define AM_BSP_MSPI_CE1_CHNL            1
+#define AM_BSP_GPIO_MSPI_CE1_CHNL       1
 
 //*****************************************************************************
 //
@@ -510,7 +510,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_SCK;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOS_CE              	3
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_CE;
-#define AM_BSP_IOS_CE_CHNL              0
+#define AM_BSP_GPIO_IOS_CE_CHNL         0
 
 //*****************************************************************************
 //
diff --git a/artemis_thing_plus/bsp/gcc/bin/libam_bsp.a b/artemis_thing_plus/bsp/gcc/bin/libam_bsp.a
index 08d660c64fcf6f8c6de4c5f31f58268b3e94df8a..8f5621fa3ee9f9e005cb8dbe564d771e0a7ab518 100644
GIT binary patch
delta 1832
zcmc(fZ)h8J7{`CVYp+cjTQ806l1$oPlag!FrMslpHMgYcO~b6aYRY_5*~GP5Z8qCg
z(;=f1TZS)W3U)jo>sDM}?A6$$aI=cCRea$a|Fkd^*@P7-q*GrE5iKgt=k9(P69nG~
zJIL?zJl}hM&+mIrl6!B3e!5C$1MVG)l1g=|N%eGSW_njWArJ5~{QwUi8h?J+T%aq}
zt@kFvSeKGuj3pIZSVB>Ds47xTDhhm{%k)F@WA}Mlb#)`969xx7vlzNCG=KFZD=YRD
z2cccM+;zR=HGC{kxcl2*cO|2dM|DP!N3}*Jk37Z}_HIcqqU=kk^>!XPx#(^qKfg0`
zYlGYgia~K;{M6gB+-E#mh_aU5R=<|rggK;~ekLql-H>!tm$O*uyI0xBD}wBHsrw&y
zq73G}`t&EIux*r{wp!9TX9JxJ+8gOyCFd5-`;U4AO$Q3)osKCw=a`~%0^d>bFFUKa
zmGiZw3jSngOTr>_)T>R_g9Hlpu4T93jL>B`DrGQJzl0N)^r}9{_y*n9_aOG6ckp@}
zRO$V?{*#N$9=qd*goG9+ch+h{xzBR~2WNio)2N}vlS)F1zpTc`hmK4XqfF~ab|mmu
zkkArJvWvA9N5)2mCP$)d->$t+Z67L*$F=xyap>s50xOQZa(MFa#8H;)?(WhwbGYFP
zAyh}om!H&N=r5-j)nc5X=77J6(u_F~xLzgb6msku&6yP~%MS-W!-ASagsgJj;9Q5B
z%IK4fXKkDc=N`_zoY=tbGRAp~^Ht8*!PwqBeSv37oYy$Z9=_uFH=K7kH#rG)PH}Nc
zoEfBmM`p3E39YPiHlc3i_|~!9nYR<qQq5&0MMA8p)f{xDRr4YiTKOa)F{hYhkV1|S
z-6A$mnI}4%MY;;-QhB-tKc@165`v8OG~I+ZwLBewo4CFK?K|^y7Ea*00H5Q!23ym4
z!6n03I%duOOgbcP%7m=Jayl%oqn!fK$9?d7TB6^ACnJmfZbAlZZBIrLQc>8SiHP$k
zO15|w#h0RR3B^k&?zhDsP@IXvpD4QUH!x_6J9{KN-sq9V1E}R}?Nkr8jKO?QM7)6F
zAzQqG;_(>#grdts$TnMyWi3PLtSqP=V9zzeR93RWx3UonSF#aN#bVo3!?p@yeLDnU
zUpc(vvfBiEC9xl~HY@Y$Sb(POsal1b@Jz2P9J3E-c#Ss^>=uL^FK>g7u*m{uQ?Sw-
z7J?7KFTD|*_*PvObU)<uh~R36F<lP-$IDgIx|6V^x6v!+Ej{x;{}&%S(@Lk{j~Bx9
fA~cW6bRC|+wG}2tW&hVcLcXi!&xNpNWnF&*Ig{F7

delta 1469
zcmc(eVQ5oV6vxkfZBmmMmuFg=XlHMm^4^PWYLceOdp2!vht$H8MX)f3psTUAYHe96
zVKA|7jQM43-Hr@lf>mUMiL&_=+&ZnO8_X42nFGPG6$Den4}K8!gQ)j4w|@1@zyt66
z&iQlBz31Kg-ql%hc7}`xU9Cn-YbvfMQ(xB~8e^XVyuoMe4Q}4IZ~G2wg3MGjygCs|
zqtv#Nk42-&WRlWYBHEh74P7eHtV!2#;sknWUT64$XM7=C!mP)hczM~DksLPq&a?&x
zUp#sKLN-^>QsgsNifEZxE+Vg4O-~fd%rKoTI!!<Q8NG6g-=*!p{og!13_602_lJ8G
z(@f!ea;@vqypQoUry}@?T<yMJRLz>fFs<vxA7obhTd|U-exBOf)^&&J-$kELW{Y0C
z1%Hu!OHcCcN^QRvF~2<Vb{U^#ab=fTnstduN-EBHYw_Olqwb2H#TxX<EAga%oy*B3
z-5v;KxvJcE!MpLB${L@OuO59hMT}a_l?K_MN8-_#9{Dg4+1IycBp0T7bG$i5Z7~*)
zwNNeBKh)nh+8?G{2eR3S9@&xW8_o{WTz`J|=<bnW8c(L8sf2Z|YFesy!=eSijw=^a
z2!NNzkHDG;tR_Uarh<PtrKf;L=w-sJ&2>|61+VY|_fCKtg0}?!#m3mcSdGXU1e*lc
z3vLwLCb&y*STHYmQ1ElXF9p99EC^l~oGuanSX<?k_5<i(4aIj6!)fa|fTcFG04r?n
z1z4DK6hJHW@p=G>51F>f`xBNYQR^Uwu+hknas1fGNON^KZM;hgxN2R70Pf{p$4TxP
zdfGB%6K>^x98b4pq>BnZYg=O<oR+S46jXo-%%nr)7>=e@(u3b|Uyj$(s#MVML0Tcb
z=x<l0ISte83fYNSo;=j>i*`l2;==P>+k|)8RY!o|7Q>2;kW>g`Q-?yf;N}ihnh)cF
z4n_Laji<QQgMZqZ8y|6vqo#8K>q{8oc<RO@oeF=4$xf9F;$7}F^e~k)VGC0oy&ix(
zZf7Csh6g`mcHwEp2dc(fOp!iXgU^^6dd<&n7)c$wyEO8nHPV&-|GwYH?;LF)dHiZ1
n<oKQd7<ib4$Q<4oP@Qxcz)udm&FTX;{Q&<|@T(NYD;Mk~)&_x2

diff --git a/edge/bsp/am_bsp_pins.h b/edge/bsp/am_bsp_pins.h
index e69de29..c641705 100644
--- a/edge/bsp/am_bsp_pins.h
+++ b/edge/bsp/am_bsp_pins.h
@@ -0,0 +1,727 @@
+//*****************************************************************************
+//
+//  am_bsp_pins.h
+//! @file
+//!
+//! @brief BSP pin configuration definitions.
+//!
+//! @addtogroup BSP Board Support Package (BSP)
+//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB.
+//! @ingroup BSP
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2019, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// Third party software included in this distribution is subject to the
+// additional license terms as defined in the /docs/licenses directory.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_BSP_PINS_H
+#define AM_BSP_PINS_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_D0 pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_D0    	24
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_D0;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_D1 pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_D1    	25
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_D1;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_D2 pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_D2    	26
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_D2;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_D3 pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_D3    	27
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_D3;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_D4 pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_D4    	28
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_D4;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_D5 pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_D5    	5
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_D5;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_D6 pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_D6    	6
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_D6;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_D7 pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_D7    	7
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_D7;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_VSYNC pin: Also called FVLD on the HM01B0 module.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_VSYNC 	15
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_VSYNC;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_HSYNC pin: Also called LVLD on the HM01B0 module.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_HSYNC 	22
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_HSYNC;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_PCLK pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_PCLK  	23
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_PCLK;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_TRIG pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_TRIG  	12
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_TRIG;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_INT pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_INT   	4
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_INT;
+
+//*****************************************************************************
+//
+//  CAMERA_HM01B0_DVDDEN pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN	10
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_CAMERA_HM01B0_DVDDEN;
+
+//*****************************************************************************
+//
+//  MIC0 pin: Analog microphone near camera connector.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MIC0                	11
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MIC0;
+
+//*****************************************************************************
+//
+//  MIC1 pin: Analog microphone near LEDs.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MIC1                	29
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MIC1;
+
+//*****************************************************************************
+//
+//  BUTTON14 pin: Labeled 14 on the SparkFun Edge.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_BUTTON14            	14
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_BUTTON14;
+
+//*****************************************************************************
+//
+//  LED_RED pin: The RED LED labelled 46.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_LED_RED             	46
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_LED_RED;
+
+//*****************************************************************************
+//
+//  LED_BLUE pin: The BLUE LED labelled 37.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_LED_BLUE            	37
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_LED_BLUE;
+
+//*****************************************************************************
+//
+//  LED_GREEN pin: The GREEN LED labelled 44.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_LED_GREEN           	44
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_LED_GREEN;
+
+//*****************************************************************************
+//
+//  LED_YELLOW pin: The YELLOW LED labelled 47.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_LED_YELLOW          	47
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_LED_YELLOW;
+
+//*****************************************************************************
+//
+//  COM_UART_TX pin: This pin is the COM_UART transmit pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_COM_UART_TX         	48
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_TX;
+
+//*****************************************************************************
+//
+//  COM_UART_RX pin: This pin is the COM_UART receive pin.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_COM_UART_RX         	49
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_RX;
+
+//*****************************************************************************
+//
+//  IOM0_CS pin: I/O Master 0 chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM0_CS             	11
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
+#define AM_BSP_GPIO_IOM0_CS_CHNL        0
+
+//*****************************************************************************
+//
+//  IOM0_CS3 pin: I/O Master 0 chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM0_CS3            	15
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS3;
+#define AM_BSP_GPIO_IOM0_CS3_CHNL       3
+
+//*****************************************************************************
+//
+//  IOM0_MISO pin: I/O Master 0 SPI MISO signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM0_MISO           	6
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_MISO;
+
+//*****************************************************************************
+//
+//  IOM0_MOSI pin: I/O Master 0 SPI MOSI signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM0_MOSI           	7
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_MOSI;
+
+//*****************************************************************************
+//
+//  IOM0_SCK pin: I/O Master 0 SPI SCK signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM0_SCK            	5
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SCK;
+
+//*****************************************************************************
+//
+//  IOM0_SCL pin: I/O Master 0 I2C clock signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM0_SCL            	5
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SCL;
+
+//*****************************************************************************
+//
+//  IOM0_SDA pin: I/O Master 0 I2C data signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM0_SDA            	6
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SDA;
+
+//*****************************************************************************
+//
+//  IOM1_CS pin: I/O Master 1 chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM1_CS             	14
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_CS;
+#define AM_BSP_GPIO_IOM1_CS_CHNL        2
+
+//*****************************************************************************
+//
+//  IOM1_MISO pin: I/O Master 1 SPI MISO signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM1_MISO           	9
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_MISO;
+
+//*****************************************************************************
+//
+//  IOM1_MOSI pin: I/O Master 1 SPI MOSI signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM1_MOSI           	10
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_MOSI;
+
+//*****************************************************************************
+//
+//  IOM1_SCK pin: I/O Master 1 SPI SCK signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM1_SCK            	8
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SCK;
+
+//*****************************************************************************
+//
+//  IOM1_SCL pin: I/O Master 1 I2C clock signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM1_SCL            	8
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SCL;
+
+//*****************************************************************************
+//
+//  IOM1_SDA pin: I/O Master 1 I2C data signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM1_SDA            	9
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SDA;
+
+//*****************************************************************************
+//
+//  IOM2_CS pin: I/O Master 2 chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM2_CS             	15
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_CS;
+#define AM_BSP_GPIO_IOM2_CS_CHNL        3
+
+//*****************************************************************************
+//
+//  IOM2_MISO pin: I/O Master 2 SPI MISO signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM2_MISO           	25
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_MISO;
+
+//*****************************************************************************
+//
+//  IOM2_MOSI pin: I/O Master 2 SPI MOSI signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM2_MOSI           	28
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_MOSI;
+
+//*****************************************************************************
+//
+//  IOM2_SCK pin: I/O Master 2 SPI SCK signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM2_SCK            	27
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SCK;
+
+//*****************************************************************************
+//
+//  IOM2_SCL pin: I/O Master 2 I2C clock signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM2_SCL            	27
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SCL;
+
+//*****************************************************************************
+//
+//  IOM2_SDA pin: I/O Master 2 I2C data signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM2_SDA            	25
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SDA;
+
+//*****************************************************************************
+//
+//  IOM3_CS pin: I/O Master 3 chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM3_CS             	12
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_CS;
+#define AM_BSP_GPIO_IOM3_CS_CHNL        0
+
+//*****************************************************************************
+//
+//  IOM3_MISO pin: I/O Master 3 SPI MISO signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM3_MISO           	43
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_MISO;
+
+//*****************************************************************************
+//
+//  IOM3_MOSI pin: I/O Master 3 SPI MOSI signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM3_MOSI           	38
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_MOSI;
+
+//*****************************************************************************
+//
+//  IOM3_SCK pin: I/O Master 3 SPI SCK signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM3_SCK            	42
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SCK;
+
+//*****************************************************************************
+//
+//  IOM3_SCL pin: I/O Master 3 I2C clock signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM3_SCL            	42
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SCL;
+
+//*****************************************************************************
+//
+//  IOM3_SDA pin: I/O Master 3 I2C data signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM3_SDA            	43
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SDA;
+
+//*****************************************************************************
+//
+//  IOM4_CS pin: I/O Master 4 chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM4_CS             	13
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_CS;
+#define AM_BSP_GPIO_IOM4_CS_CHNL        1
+
+//*****************************************************************************
+//
+//  IOM4_MISO pin: I/O Master 4 SPI MISO signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM4_MISO           	40
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_MISO;
+
+//*****************************************************************************
+//
+//  IOM4_MOSI pin: I/O Master 4 SPI MOSI signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM4_MOSI           	44
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_MOSI;
+
+//*****************************************************************************
+//
+//  IOM4_SCK pin: I/O Master 4 SPI SCK signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM4_SCK            	39
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SCK;
+
+//*****************************************************************************
+//
+//  IOM4_SCL pin: I/O Master 4 I2C clock signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM4_SCL            	39
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SCL;
+
+//*****************************************************************************
+//
+//  IOM4_SDA pin: I/O Master 4 I2C data signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM4_SDA            	40
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SDA;
+
+//*****************************************************************************
+//
+//  IOM5_CS pin: I/O Master 5 chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM5_CS             	16
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_CS;
+#define AM_BSP_GPIO_IOM5_CS_CHNL        0
+
+//*****************************************************************************
+//
+//  IOM5_MISO pin: I/O Master 5 SPI MISO signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM5_MISO           	49
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_MISO;
+
+//*****************************************************************************
+//
+//  IOM5_MOSI pin: I/O Master 5 SPI MOSI signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM5_MOSI           	47
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_MOSI;
+
+//*****************************************************************************
+//
+//  IOM5_SCK pin: I/O Master 5 SPI SCK signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM5_SCK            	48
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SCK;
+
+//*****************************************************************************
+//
+//  IOM5_SCL pin: I/O Master 5 I2C clock signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM5_SCL            	48
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SCL;
+
+//*****************************************************************************
+//
+//  IOM5_SDA pin: I/O Master 5 I2C data signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOM5_SDA            	49
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SDA;
+
+//*****************************************************************************
+//
+//  MSPI_CE0 pin: MSPI chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_CE0            	19
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
+#define AM_BSP_GPIO_MSPI_CE0_CHNL       0
+
+//*****************************************************************************
+//
+//  MSPI_CE1 pin: MSPI chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_CE1            	41
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE1;
+#define AM_BSP_GPIO_MSPI_CE1_CHNL       1
+
+//*****************************************************************************
+//
+//  MSPI_D0 pin: MSPI data 0.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_D0             	22
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_D0;
+
+//*****************************************************************************
+//
+//  MSPI_D1 pin: MSPI data 1.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_D1             	26
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_D1;
+
+//*****************************************************************************
+//
+//  MSPI_D2 pin: MSPI data 2.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_D2             	4
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_D2;
+
+//*****************************************************************************
+//
+//  MSPI_D3 pin: MSPI data 3.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_D3             	23
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_D3;
+
+//*****************************************************************************
+//
+//  MSPI_D4 pin: MSPI data 4.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_D4             	0
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_D4;
+
+//*****************************************************************************
+//
+//  MSPI_D5 pin: MSPI data 5.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_D5             	1
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_D5;
+
+//*****************************************************************************
+//
+//  MSPI_D6 pin: MSPI data 6.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_D6             	2
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_D6;
+
+//*****************************************************************************
+//
+//  MSPI_D7 pin: MSPI data 7.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_D7             	3
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_D7;
+
+//*****************************************************************************
+//
+//  MSPI_SCK pin: MSPI clock.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_MSPI_SCK            	24
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_SCK;
+
+//*****************************************************************************
+//
+//  IOS_CE pin: I/O Slave chip select.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOS_CE              	3
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_CE;
+#define AM_BSP_GPIO_IOS_CE_CHNL         0
+
+//*****************************************************************************
+//
+//  IOS_MISO pin: I/O Slave SPI MISO signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOS_MISO            	2
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_MISO;
+
+//*****************************************************************************
+//
+//  IOS_MOSI pin: I/O Slave SPI MOSI signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOS_MOSI            	1
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_MOSI;
+
+//*****************************************************************************
+//
+//  IOS_SCK pin: I/O Slave SPI SCK signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOS_SCK             	0
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_SCK;
+
+//*****************************************************************************
+//
+//  IOS_SCL pin: I/O Slave I2C clock signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOS_SCL             	0
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_SCL;
+
+//*****************************************************************************
+//
+//  IOS_SDA pin: I/O Slave I2C data signal.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_IOS_SDA             	1
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_SDA;
+
+//*****************************************************************************
+//
+//  ITM_SWO pin: ITM Serial Wire Output.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_ITM_SWO             	33
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_ITM_SWO;
+
+//*****************************************************************************
+//
+//  SWDCK pin: Cortex Serial Wire DCK.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_SWDCK               	20
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_SWDCK;
+
+//*****************************************************************************
+//
+//  SWDIO pin: Cortex Serial Wire DIO.
+//
+//*****************************************************************************
+#define AM_BSP_GPIO_SWDIO               	21
+extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_SWDIO;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_BSP_PINS_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/edge/bsp/gcc/bin/libam_bsp.a b/edge/bsp/gcc/bin/libam_bsp.a
index 1c8dbcc5ac79e84c36eaa32301cf358146dd2f1f..2bc5fb41e5a4569207b0c760bae6e8408a74784c 100644
GIT binary patch
delta 1862
zcmc(fUrbwd6vuzR3m4n+$IGbDR)rs}_O@)rdrLbglyVDfVO|{FGLxG5Fx+rOVUt3P
zE;AtU$rr(6%<w@WS>iO#blz<biwxp}@j=NlqcOe+$&xZ-7Q%}>n9XzV{nbB-i4U6W
zCjEWR`QCHR@BB`G?dP}Yji2e9*SS|wIy%~7(YAU2%yi!?gxtr^^!?l%_tyUF>5X;z
zo%69jM#@-RQ5j=V1sA3&%HCKEiNlV<qkS^{!Jt(i(u(EH4vjGQw0aIr2bxBIO|-o1
zXg&+C?z-6dZLwCbW8U1oU+><N^m=a9=ss>$>*d_4)En6QML`d<Z;Fm(vI45K$17c#
zEjUAD``wwJHp!Mx^og1AH{X)w0a&VQiV20~O-aMjD=GbvTperPZ*J4Pzn<CjvD?M=
zzr6`F$haA}+-!Qa7_d5{^JXwzu#@P5&q}5X<(v(i9`@&UZtT*VD`gTMK{*A^vVX{|
z;O%@+T`WU0j6J_s6bf+G9cwfX<IP!FD^A^>nM1c#%3#fXwaRoV2Fw%VfF`OvaN(g&
zm-!WlmWYx&CS9o+oGmbG<aTSsFErb}y*{8Te`#OEgBeQwA*v@LQAJHeCSsBC;TKNl
z!z|GnZB_9Gs0mex##tyoGBz?iITB_^(}$mWVmLn@NkpE@51%@oWBHMnM<+*5pJLJW
z_IM&;eAV!^;IAR2$3t9bdP*)@)o3Rvv<`TTHD3j#Nw|2xYutJGT7{rd_}G7)_8X&t
zl?T0FVxa2;AvZXG<h%vxwvz`K_d=Ws=aZa=IkA9MWsGx*^DO5Za7k^NKF__YoYy%^
zJ*;v6d(JJ+9Zo{+T^yVeXA&vkmMM&D#8z%`Hll9&yX<^pDE16ZI7}x`h&esiaeHd6
z7ctQECkbh>gGmx8^b?|)#Nr*sM!ZR+TR^*pV6m$lj&u#u3@mjG37!CKcO9fJK{`1^
zFTgym1=zrK71Zt_fdpZ;`=Ah#;bwP>IsUude$j&?U5Ce00r3~?C<m8L*1@rqM0a2!
zC5uO#gk&tOkdlOK7`{ja#q%girucS`MCYKkM;0%m^sE(^L2VI+QIqg4WG!v6M-oU2
zeAW{bb13%1Qr=xF5Q0h8u@EHN0)iG4Kf(7WtRzj7=s7r~VWCPw_E_2+YCEu`$#{=8
z(hab#NkXy`wzZ%MUpgozG1lr0vS~>iM2}gSGiiyA!F*a4JiFmqI!NEa0y1tek7Zb|
zB(7rU8Ho1=#Lg;0VxUe1aFDO}%Jdj~)GG_2-Egy4{?|XwXuG0Vf1H<%eSI_k?~ko&
m-*2t-3^=i~I}n+YX$YRi^&Gr5C3|!)A<yIRN)KK+>-il8wFKn=

delta 1540
zcmc(eUrbYH6u{4Sp|!28UMz)HQNB`kFC~_><ytO+<+k-t=OvIVd(drJ1_<Imu%(jt
zBE}fwlM#<GzL=odvc*J0a>D~=jFF(h#bnHk#Jz0bOOYp*ESX!D>36vw+v6TI@k{Rc
zopbIv-#OpE`4#fb3vxB!+|}H;t0}G~l+l{=Bk5&;cleFG%i^rI_NJ>h7RiFM_TMd~
zG)m23$yhX+NF*qYDN$9$dl{Kz4dVWa*nv(hs~X<-TwPNgnz46NytL%dU>?tIxwkve
z|LTu_UX|$;)Y3$KE7vyZrCjsqmGpM8L=V&XqFwjW$)aNlrZFb&^obMBy27(xmti$v
z3)l`1d?e|56MpHfc1|se8k>4Lf<JgGT`NUduj&ue;C_7R)v6yB%bDqArdd6>KTH>j
zBKOP}J!T3z%0>4bR@F*-RK(eGWqS#0X?<p=Znf;tiRH!ZVl^tho9+$S^%&M>&f~{b
z-)_O4#YK+~&v`bKiW8o8?5L<Bc3cuGjf)i@kOOKY9*wDyoDw<Jb$l=%rfNgHAx2GS
zEFNp5b@|?ty<J1SVfx9@o}P#r>CSfz^z_qw@9?pqV}k=Uo@k0TDTd$wL<qWIefYuD
z%hyftgNNzA<4iVS?AT@}M8(v>fRU_vU>9Bj{#ElW(TvH^^ya{KEY5WV;Cs%WIDf&>
z#-k%u+^Xf=$+?%ao%1u!KF$HoVa{`$mpHF*-r)S2bC&aoMSMT*vkL_P6^y4!A8EFm
z{yc!&WDh`v$rAu;eGUQCS$QlTKwwR_nq>KkkxNwD$QX{cbPD4^eBRQ5i!G(7w6+U#
zHF%-5gHZgjwUZpe;GRzMIp&x=jWc^#^n17^*&#fWusd0AZr+t-jcrZ_7{iHVh<t%R
zCuP!)q)jGn47bU`TpfPcCXr9^EOP<gX7VIHW>Uo8%->Gjs!77>Fs3!hM%lS(cuETi
zb78!uNv!mwCKCrPX|gcuLRU&+lgCoBu<F8(Q<8}b7VcVj$|3;&Ov!8o!L%$~uE&FE
ziDWUCmPtEvRpNMBv=uf24CBLe$hN{X1()`DuVqA*Q^p>#h|L*UxLJ?g8To&oemv2f
zSbO^8#zN-&+q=?Z`~Geq!+5I@A}cskkV!4RVDdVaoss<q0swvg-FG1DV9oIw<RY%V

diff --git a/edge2/bsp/am_bsp_pins.h b/edge2/bsp/am_bsp_pins.h
index b9acdd7..b994e60 100644
--- a/edge2/bsp/am_bsp_pins.h
+++ b/edge2/bsp/am_bsp_pins.h
@@ -245,7 +245,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_RX;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS             	11
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
-#define AM_BSP_IOM0_CS_CHNL             0
+#define AM_BSP_GPIO_IOM0_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -254,7 +254,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS3            	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS3;
-#define AM_BSP_IOM0_CS3_CHNL            3
+#define AM_BSP_GPIO_IOM0_CS3_CHNL       3
 
 //*****************************************************************************
 //
@@ -303,7 +303,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM1_CS             	14
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_CS;
-#define AM_BSP_IOM1_CS_CHNL             2
+#define AM_BSP_GPIO_IOM1_CS_CHNL        2
 
 //*****************************************************************************
 //
@@ -352,7 +352,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM2_CS             	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_CS;
-#define AM_BSP_IOM2_CS_CHNL             3
+#define AM_BSP_GPIO_IOM2_CS_CHNL        3
 
 //*****************************************************************************
 //
@@ -401,7 +401,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM3_CS             	12
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_CS;
-#define AM_BSP_IOM3_CS_CHNL             0
+#define AM_BSP_GPIO_IOM3_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -450,7 +450,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM4_CS             	13
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_CS;
-#define AM_BSP_IOM4_CS_CHNL             1
+#define AM_BSP_GPIO_IOM4_CS_CHNL        1
 
 //*****************************************************************************
 //
@@ -499,7 +499,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM5_CS             	16
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_CS;
-#define AM_BSP_IOM5_CS_CHNL             0
+#define AM_BSP_GPIO_IOM5_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -548,7 +548,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE0            	19
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
-#define AM_BSP_MSPI_CE0_CHNL            0
+#define AM_BSP_GPIO_MSPI_CE0_CHNL       0
 
 //*****************************************************************************
 //
@@ -557,7 +557,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE1            	41
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE1;
-#define AM_BSP_MSPI_CE1_CHNL            1
+#define AM_BSP_GPIO_MSPI_CE1_CHNL       1
 
 //*****************************************************************************
 //
@@ -638,7 +638,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_SCK;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOS_CE              	3
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_CE;
-#define AM_BSP_IOS_CE_CHNL              0
+#define AM_BSP_GPIO_IOS_CE_CHNL         0
 
 //*****************************************************************************
 //
diff --git a/edge2/bsp/gcc/bin/libam_bsp.a b/edge2/bsp/gcc/bin/libam_bsp.a
index b93594b52634263bfd44d297297a788ed4b70365..859aa44895bee1d304bf427bb6cce3aae2cd630e 100644
GIT binary patch
delta 1936
zcmc(fZD?Cn7{|}K$xV~SbZOF;BpvlEDS4@;-lR#}yQbYu4YPW6Db){=?L)J*G#%^K
zrNs}U5-Al##BDq<-@pnhI&jnA9e!IorfAXm0=`i8#esu#A~IjVeR4kc=0s``{GhM{
zIlt#Q&;LB<InPP5RH0|K=qazQPm%@(dK2-)Y5&uuD};>P#ZT#O9*$=Z{)gLZn^d!P
z{nbszl2VK@7ME~hF-hu6B#;S7j>Eh5kg(9BZQ9?YmP=a$3SqG9IEAJaP0iO7H=Fhs
zbC7jiNPbmmR^7~7xbyoTcbsY)x0+NRw;ZaOTXwaby<QR22>T3T?%vL&vMo%0IrGeS
zTjZ8c^oe7$&z}s1M%A5#2-~$6uDjbD9wwA8Z8;T8zCH{q?snJBN<RwRD9{hwwKu}x
zvRf%#t^|xK=xKeKzS733^l_Rw+c~!<Zo!JYh1yQS6_iupH2uR)3om8GQ8DqdU#$pb
z7;i~*>1BHh#;$dnTJ4Wjt*#om*XJGr>h!>smY1=yPQ@|`6RkO;-Qp;$wff9Wk1mzr
zTI)_%gDP#SFosRhENyA3%F(zKlcUEI(b@drW5o!Qd*VGYe9@R3lj2DhE>0bp%Fj<l
z*#7kRV-Mtuvr##Eu$Vu3sKAO-PtDBF96QS5{ryQ<)?RGCD)^g7ZFoo{nx2}AmILh+
z)fRo7l%}-TIy8%*P#E*C(Tuhuu(HGZ5ega)67nVIHO?FGaeVq=#=S77#Q6y4IOini
z5zYn9Mb2gDkKJ2Z<=*?8Yn-(jKIi_ooVPe{a}rvu)ynDQOd*9LA;YNa#Jk+!?8J55
zcUAXm-}F97WvlMY5u$gkF<<Rg;|vOQ|2QGtRWV5+g$yBzPE0<aO(*RleFNrqXK5Ke
z*qs%KA6f?Y(G55>m=#z6E~1kIQz}a*;BlPi;4IE%_!Z|(cyQ=Gz4voNesLp2$aQ#W
zC?Nib<rLuOjJx@5EY^l+>F4R=9DF|%5}&}OF+J|OS{JuQATb;iS5e?J1V7aYln5-N
z;35hR7=mWu?<b5!;A<2(@jH_<N=ViT$`IHS5(^m57zrlo;?{0h*b@}bqhQhyJX<Fi
z?S>Cg;ItERzj4BQb%Jx?RzhM5<7OklO^oXgWHMTSUtK#)DnSA9f)X@zOxM9Dic>s*
zyTV4+2+Fs&ZUao|khomS+B%JKY!1QX#(1u_6Aq`HVi~;?P)Y}c?t5T09mL1`G#wI{
z2Yy3m6FNr1fq(n|jVJry9ebGOw38!?|L;$HJhRwCPrw(&fcOJmLWZ}}0onx}^C8P*
YGa+Xi;C9;YY48%V58t6S^y}*5PtPUtmH+?%

delta 1579
zcmc(fU1$_n6vxk<&2F>1SzX<AKVs0EUD?^yZrItcOx(CT8-o=_jIDXFSkxF}lGY}5
zw}e2`25eD55$ypV+K2i@DU_lxSn7ix4^c`95>PReq7RCj);<Ud`qcEy&W+F~A1rub
z&hMQ6oHOU#JHwouV+U&Nc-Wci$mH77YCd-&^7&*Mpz94@lW(#)^)9@|?u}VyI9I(q
zP0mx?T$WW*seC@qxsvI~s(9WlOAnLAtowWB0DgH+)$l9N@w(fn8O@8*4YqBg73^91
zQ!YF-|NNi%C3=8co>y-c-Xgt0cpg2-PuFaEg3r_(x{qH%#h39p<DbsnpMxi1d)WT|
zNN-Hn+wn8s%GH<Wyc#|8YEo|*^6}OU=JQ)O1h~a!{#Q+=I|;gjH+@>{dd>fz#00-n
z^9p6A<`EvH@}@I1gH?H>hTr(JD{M62LOZ8!ZJ<$SLdC!RKR3O#aUlV&BJ+mu#<I08
z2Z?HZNPO4hPkAqTHu3s7Kz&MxNUc_ESqF7Zz1)eyjrRg&_KuoNrxZ20Kb!ox@59kb
zf~#%mHies_l2$T2UK!Xo&{rKu@a=>B{Yf>syV5t(Kg25oW5d<q(Gi}`x2M{(#=YRQ
z6mh}A3W4eS7eWYuhx}(?OgFD!Of?=aHyqLnz*CVcOfz;yzgrx>MhULn0KW;|7QBbS
z%;02;h*k-{E!Zu%NpOeYUcnK;F~Khc4+<U=JSq5t;FRFBMZBmib4V2c6^w1!y{yAw
z>Yo5Knd}1ym>dSE&$%BUZq-pffJ8%fnxy)y@jU0Yvn^;V^srsHwa_D7XvK4d&1@W>
zQZN(2?#|7u5wWv}dGP^Rj+u34?w4c_<E?dT=-|FCM(pD<z$uiAQFadXqRc{ACEJAG
z7G-HXj#I@L`v4zPa3PNVQjG1xLP?gc#c@w5CjIKfqoi>(O0u2P%hK?EDJqR8utAGa
zvo)G5{gS|5EhbI5aDucDo+a&x3sZxErGH8QjkF~jUFIVB8Kn|h%5`*?V>JFpWtpjn
zWm!_)X5ErODqxgP<@MEx56ZHAj~ieN7k5SNzmu26Bh@GsZ|{;FGeLk!C;m~5u#Na*
ySNxTKj&v@cHUAu}*I2oJ;{W@;A9YW(u`%qY$sXaMs!S($p6o8XOV)<-)!@Hfx{X)>

diff --git a/redboard_artemis/bsp/am_bsp_pins.h b/redboard_artemis/bsp/am_bsp_pins.h
index 490e637..0ca6be6 100644
--- a/redboard_artemis/bsp/am_bsp_pins.h
+++ b/redboard_artemis/bsp/am_bsp_pins.h
@@ -109,7 +109,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_RX;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS             	11
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
-#define AM_BSP_IOM0_CS_CHNL             0
+#define AM_BSP_GPIO_IOM0_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -118,7 +118,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS3            	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS3;
-#define AM_BSP_IOM0_CS3_CHNL            3
+#define AM_BSP_GPIO_IOM0_CS3_CHNL       3
 
 //*****************************************************************************
 //
@@ -167,7 +167,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM1_CS             	14
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_CS;
-#define AM_BSP_IOM1_CS_CHNL             2
+#define AM_BSP_GPIO_IOM1_CS_CHNL        2
 
 //*****************************************************************************
 //
@@ -216,7 +216,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM2_CS             	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_CS;
-#define AM_BSP_IOM2_CS_CHNL             3
+#define AM_BSP_GPIO_IOM2_CS_CHNL        3
 
 //*****************************************************************************
 //
@@ -265,7 +265,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM3_CS             	12
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_CS;
-#define AM_BSP_IOM3_CS_CHNL             0
+#define AM_BSP_GPIO_IOM3_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -314,7 +314,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM4_CS             	13
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_CS;
-#define AM_BSP_IOM4_CS_CHNL             1
+#define AM_BSP_GPIO_IOM4_CS_CHNL        1
 
 //*****************************************************************************
 //
@@ -363,7 +363,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM5_CS             	16
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_CS;
-#define AM_BSP_IOM5_CS_CHNL             0
+#define AM_BSP_GPIO_IOM5_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -412,7 +412,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE0            	19
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
-#define AM_BSP_MSPI_CE0_CHNL            0
+#define AM_BSP_GPIO_MSPI_CE0_CHNL       0
 
 //*****************************************************************************
 //
@@ -421,7 +421,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE1            	41
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE1;
-#define AM_BSP_MSPI_CE1_CHNL            1
+#define AM_BSP_GPIO_MSPI_CE1_CHNL       1
 
 //*****************************************************************************
 //
@@ -502,7 +502,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_SCK;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOS_CE              	3
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_CE;
-#define AM_BSP_IOS_CE_CHNL              0
+#define AM_BSP_GPIO_IOS_CE_CHNL         0
 
 //*****************************************************************************
 //
diff --git a/redboard_artemis/bsp/gcc/bin/libam_bsp.a b/redboard_artemis/bsp/gcc/bin/libam_bsp.a
index f1dd55ac134a68b3aec6966f2862342b3a1f7e0b..8ed57ad6395a105f54156043ffd7948a6a9408e7 100644
GIT binary patch
delta 1728
zcmc(fe`p(Z6u`gVYx6tpu8Yf(Al<jQkxM$#Ub3XUThb(zGOAbCGDIsyx6}pG(QaL;
zB4f}p1d9&Lc%Vkd3fs{Bp{#f~{b#Lz%|F~^ASejpltSWP7XR49Lg%~Ow_}3fKf=Cn
z@AKZf_rCYu``+EJH|gD5v>J5vDT=D@PbJgm!)N9T&l2(oulYyx@Z!vo$+_7huNoKV
zWyjtJ6Jac^Bp72!1qDkeN?$64OeuW|Z02R*nI7Yu>ms#ZZ>R;rK=D*jb)stA@FZJX
zCMx5wx#QFHcl8e4$Aabi_qOhfx}R(9dWdUndMnpF`fhfyF6c3K3w{#!A3wX|ijqIx
zUHG{{HbS<LZEWVPcVu~3f4m%HT?ftmx(*U%k#Yu@uyVa27SOwv!${wQNI#DVvES<b
z|F{!lFx^p@|EexE3#I4HEose4ptVplk=9x{cXK}csK>DAV0k;!DvH*uqG(Ov87=>k
zY3HRZwbfgAXCKss71-)Xb()O?%gwAcmu`*FsasykU~K0#oVZx94};e??lRB8HjK5y
zFXFD0_<8%t*%j6tyHyVf3tg6NNr$dHRC59cXME<1QC*8Cm4p^Qm5R?4kDsi>nAVf*
zN#JXc&=N{A&7zgkbg4L3im{2o!%z1XD>HE|K3OTAc&W@PrPrqBrcRz<$^QPdrWxT~
zH-&IJ*<JzSMm4Z)qSl6bmKtK9lhUlw8#L@ffx`NpRXSu`W=lJQH!#3GNyu%^A34`y
zLV5W~#;qu)!ub^EVa{Wm)10qxp5c50zUkRBe}!AuI9EBhYxtJi-*awo{>e$GRjZRz
z<jf+43L!a+>%?BxIXlsB+B>a$V=D1H)tsg=ONco&chQ=bdkO<h`xGJFRxrsTg(3W5
znZ(UiV>9Wo(FJg*qqGXop}Yehqg;l2>Zm{@7}gF6ss!&N3KBH5Lv#%K517GkqWltm
zIIzzge)R=Egfd>+vP{Sw*q4#$I*evyVKEA?XCib2mNGJJz}F}*!0&j2#UPN4&`%(r
zl?5dR<!nT7x}l1`DtwWZZAbCchhXptAKcA~nCcji=@sZ5kcDVBj1OS62Nn>E-LQ;E
zdEmAMmh(e<PBc9%7qO*0ggBe~yok=M2WE2-Z126COpn1@P8Q0h%MV*Q(N@LS)8NZX
zg4+vfJ|Yyna1=oTu$Yfvw^#E~=|BE;nwnJMuY8n_7*av~f4_`NgWkRLG+Zr7wvX^N
j&>)kS@W3`pvV8+TiVtmYE*}oO?IUE>fhWutMmE>q>9FDA

delta 1455
zcmc(eUuaWT9LLYOZDNx&^TyaFk!X)e$-QAl?@iL=-X>`-n^eb@20^eQOw-!59kbPR
zD`O1vrl8_Ff1-k=*7_n0A#hP}n|~g(idO7{LLatu+e?D@P;hL8f!(>@Q(yNo@WB0j
ze!uVi{eI`i;hevo;y>o_M8MIZCOXn_C8c~9`lgbfMd&?#mG`uH@$iAZu_Fh*G$!%Y
zHSO<Cgb<0C%d)a0rBW$E<b*1x;FKnC_hZIs#}u|Ba=Wf*Ah{;qx=orf>xwrv^p2L{
zpS9OJ0z)f*zgh9<t;F(peFO78&>NZO)_vqktwE2H`I=q#l3VZ#pYS@wFBTT-XenR|
z*!GR=iRgM71W%jecAeK~&$}_$?eRHZ)&xB`6eXLx;cJi9_Mo<&hF%()+ivcTk{30e
zDf2bASpp|LeDe(5&MKR&LHD}k#s)geYG;RT&Dx}6ONGnsHn_R&qI1p8)g1VZ-vDKA
zr^8Mq#T*EJ=UW>28}3~&?+x;H+Fp7$hD?k%-YDLo#Nv{y#EvFohl`($mZL=38s91t
zQ<UR!f{5jT&j*TQ15vVnu)ja1#QMs`k^Ui49vB}U8y+1Y@l;w$CyjE;92at;)#XQ~
zzkW4De&nY9pU61q--NMZR04*bTSky1cd%x>CYRR+?$HEiA3~2ApELdn-%Ep)AdA`=
zw=iyJ+{O4QV~KHuah&lO<8j6_jOQ7zG2UmKvk0GTYq4`>gcM}Fl1o^%oB9!inoSlF
zYBf2G(AznWA|zUMG#??34w*Gc>yyT*gv*8{xS$lU1~qCYAgvZ~FPu;dTr~s>Y7bWr
zf!Nu@ErsB#&K`{5VW*kw%M|bs3}!wwPwreMWa||WnuZ@UVLS<o8G&0CpeY-{jj$~%
z(1v@d-2;`Zz)gs7js7?U&uB0$!g4mk-E#oRMQHOKIf3&#p{lmR@f=U<F67MWyHvgy
zg?cW+{p19`E5a>DL7}KS;h=?TS1U|)@upI>lm&_<=h=J&`$5PH)E1}>!b+D9&g6O9
zb{9h9a5W$1esIB~JWY1N5=GSqel3DU$ZKNwKVH15#FKDR6Y);N(3Jo03a375ZpY*B
jaVcz@!3e4FBp=2<!?z{D{)*n-OEw5<A$$TBOTK>rYN3}F

diff --git a/redboard_artemis_atp/bsp/am_bsp_pins.h b/redboard_artemis_atp/bsp/am_bsp_pins.h
index 48b229c..f94bc43 100644
--- a/redboard_artemis_atp/bsp/am_bsp_pins.h
+++ b/redboard_artemis_atp/bsp/am_bsp_pins.h
@@ -109,7 +109,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_RX;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS             	11
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
-#define AM_BSP_IOM0_CS_CHNL             0
+#define AM_BSP_GPIO_IOM0_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -118,7 +118,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS3            	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS3;
-#define AM_BSP_IOM0_CS3_CHNL            3
+#define AM_BSP_GPIO_IOM0_CS3_CHNL       3
 
 //*****************************************************************************
 //
@@ -167,7 +167,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM1_CS             	14
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_CS;
-#define AM_BSP_IOM1_CS_CHNL             2
+#define AM_BSP_GPIO_IOM1_CS_CHNL        2
 
 //*****************************************************************************
 //
@@ -216,7 +216,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM2_CS             	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_CS;
-#define AM_BSP_IOM2_CS_CHNL             3
+#define AM_BSP_GPIO_IOM2_CS_CHNL        3
 
 //*****************************************************************************
 //
@@ -265,7 +265,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM3_CS             	12
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_CS;
-#define AM_BSP_IOM3_CS_CHNL             0
+#define AM_BSP_GPIO_IOM3_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -314,7 +314,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM4_CS             	13
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_CS;
-#define AM_BSP_IOM4_CS_CHNL             1
+#define AM_BSP_GPIO_IOM4_CS_CHNL        1
 
 //*****************************************************************************
 //
@@ -363,7 +363,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM5_CS             	16
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_CS;
-#define AM_BSP_IOM5_CS_CHNL             0
+#define AM_BSP_GPIO_IOM5_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -412,7 +412,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE0            	19
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
-#define AM_BSP_MSPI_CE0_CHNL            0
+#define AM_BSP_GPIO_MSPI_CE0_CHNL       0
 
 //*****************************************************************************
 //
@@ -421,7 +421,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE1            	41
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE1;
-#define AM_BSP_MSPI_CE1_CHNL            1
+#define AM_BSP_GPIO_MSPI_CE1_CHNL       1
 
 //*****************************************************************************
 //
@@ -502,7 +502,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_SCK;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOS_CE              	3
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_CE;
-#define AM_BSP_IOS_CE_CHNL              0
+#define AM_BSP_GPIO_IOS_CE_CHNL         0
 
 //*****************************************************************************
 //
diff --git a/redboard_artemis_atp/bsp/gcc/bin/libam_bsp.a b/redboard_artemis_atp/bsp/gcc/bin/libam_bsp.a
index 2e84b19d2900362dd7d1659823cbb8c2e96d3f3b..8ed57ad6395a105f54156043ffd7948a6a9408e7 100644
GIT binary patch
delta 1728
zcmc(fe`p(Z6u`gVYx6tpu8Yf(Al<jQkxM$#Ub3XUThb(zGOAbCGDIsyx6}pG(QaL;
zB4f}p1d9&Lc%Vkd3fs{Bp{#f~{b#Lz%|F~^ASejpltSWP7XR49Lg%~Ow_}3fKf=Cn
z@AKZf_rCYu``+EJH|gD5v>J5vDT=D@PbJgm!)N9T&l2(oulYyx@Z!vo$+_7huNoKV
zWyjtJ6Jac^Bp72!1qDkeN?$64OeuW|Z02R*nI7Yu>ms#ZZ>R;rK=D*jb)stA@FZJX
zCMx5wx#QFHcl8e4$Aabi_qOhfx}R(9dWdUndMnpF`fhfyF6c3K3w{#!A3wX|ijqIx
zUHG{{HbS<LZEWVPcVu~3f4m%HT?ftmx(*U%k#Yu@uyVa27SOwv!${wQNI#DVvES<b
z|F{!lFx^p@|EexE3#I4HEose4ptVplk=9x{cXK}csK>DAV0k;!DvH*uqG(Ov87=>k
zY3HRZwbfgAXCKss71-)Xb()O?%gwAcmu`*FsasykU~K0#oVZx94};e??lRB8HjK5y
zFXFD0_<8%t*%j6tyHyVf3tg6NNr$dHRC59cXME<1QC*8Cm4p^Qm5R?4kDsi>nAVf*
zN#JXc&=N{A&7zgkbg4L3im{2o!%z1XD>HE|K3OTAc&W@PrPrqBrcRz<$^QPdrWxT~
zH-&IJ*<JzSMm4Z)qSl6bmKtK9lhUlw8#L@ffx`NpRXSu`W=lJQH!#3GNyu%^A34`y
zLV5W~#;qu)!ub^EVa{Wm)10qxp5c50zUkRBe}!AuI9EBhYxtJi-*awo{>e$GRjZRz
z<jf+43L!a+>%?BxIXlsB+B>a$V=D1H)tsg=ONco&chQ=bdkO<h`xGJFRxrsTg(3W5
znZ(UiV>9Wo(FJg*qqGXop}Yehqg;l2>Zm{@7}gF6ss!&N3KBH5Lv#%K517GkqWltm
zIIzzge)R=Egfd>+vP{Sw*q4#$I*evyVKEA?XCib2mNGJJz}F}*!0&j2#UPN4&`%(r
zl?5dR<!nT7x}l1`DtwWZZAbCchhXptAKcA~nCcji=@sZ5kcDVBj1OS62Nn>E-LQ;E
zdEmAMmh(e<PBc9%7qO*0ggBe~yok=M2WE2-Z126COpn1@P8Q0h%MV*Q(N@LS)8NZX
zg4+vfJ|Yyna1=oTu$Yfvw^#E~=|BE;nwnJMuY8n_7*av~f4_`NgWkRLG+Zr7wvX^N
j&>)kS@W3`pvV8+TiVtmYE*}oO?IUE>fhWutMmE>q>9FDA

delta 1455
zcmc(eUuaWT9LLYOZDNx&^TyaFk!X)e$-QAl?@iL=-X>`-n^eb@20^eQOw-!59kbPR
zD`O1vrl8_Ff1-k=*7_n0A#hP}n|~g(idO7{LLatu+e?D@P;hL8f!(>@Q(yNo@WB0j
ze!uVi{eI`i;hevo;y>o_M8MIZCOXn_C8d5B`lgbfMd&?#mG`uH@$iAZu_Fh*G$!%Y
zHSO<Cgb<0C%d)a0rBW$E<b*1x;FKnC_hZIs#}u|Ba=Wf*Ah{;qx=orf>xwrv^p2L{
zpS9OJ0z)f*zgh9<t;F(peFO78&>NZO)_vqktwE2H`I=q#l3VZ#pYS@wFBTT-XenR|
z*!GR=iRgM71W%jecAeK~&$}_$?eRHZ)&xB`6eXLx;cJi9_Mo<&hF%()+ivcTk{30e
zDf2bASpp|LeDe(5&MKR&LHD}k#s)geYG;RT&Dx}6ONGnsHn_R&qI1p8)g1VZ-vDKA
zr^8Mq#T*EJ=UW>28}3~&?+x;H+Fp7$hD?k%-YDLo#Nv{y#EvFohl`($mZL=38s91t
zQ<UR!f{5jT&j*TQ15vVnu)ja1#QMs`k^Ui49vB}U8y+1Y@l;w$CyjE;92at;)#XQ~
zzkW4De&nY9pU61q--NMZR04*bTSky1cd%x>CYRR+?$HEiA3~2ApELdn-%Ep)AdA`=
zw=iyJ+{O4QV~KHuah&lO<8j6_jOQ7zG2UmKvk0GTYq4`>gcM}Fl1o^%oB9!inoSlF
zYBf2G(AznWA|zUMG#??34w*Gc>yyT*gv*8{xS$lU1~qCYAgvZ~FPu;dTr~s>Y7bWr
zf!Nu@ErsB#&K`{5VW*kw%M|bs3}!wwPwreMWa||WnuZ@UVLS<o8G&0CpeY-{jj$~%
z(1v@d-2;`Zz)gs7js7?U&uB0$!g4mk-E#oRMQHOKIf3&#p{lmR@f=U<F67MWyHvgy
zg?cW+{p19`E5a>DL7}KS;h=?TS1U|)@upI>lm&_<=h=J&`$5PH)E1}>!b+D9&g6O9
zb{9h9a5W$1esIB~JWY1N5=GSqel3DU$ZKNwKVH15#FKDR6Y);N(3Jo03a375ZpY*B
jaVcz@!3e4FBp=2<!?z{D{)*n-OEw5<A$$TBOTK>rb!C?s

diff --git a/redboard_artemis_nano/bsp/am_bsp_pins.h b/redboard_artemis_nano/bsp/am_bsp_pins.h
index ffcfa56..3ed85f8 100644
--- a/redboard_artemis_nano/bsp/am_bsp_pins.h
+++ b/redboard_artemis_nano/bsp/am_bsp_pins.h
@@ -109,7 +109,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_COM_UART_RX;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS             	11
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
-#define AM_BSP_IOM0_CS_CHNL             0
+#define AM_BSP_GPIO_IOM0_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -118,7 +118,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM0_CS3            	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_CS3;
-#define AM_BSP_IOM0_CS3_CHNL            3
+#define AM_BSP_GPIO_IOM0_CS3_CHNL       3
 
 //*****************************************************************************
 //
@@ -167,7 +167,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM0_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM1_CS             	14
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_CS;
-#define AM_BSP_IOM1_CS_CHNL             2
+#define AM_BSP_GPIO_IOM1_CS_CHNL        2
 
 //*****************************************************************************
 //
@@ -216,7 +216,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM1_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM2_CS             	15
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_CS;
-#define AM_BSP_IOM2_CS_CHNL             3
+#define AM_BSP_GPIO_IOM2_CS_CHNL        3
 
 //*****************************************************************************
 //
@@ -265,7 +265,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM2_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM3_CS             	12
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_CS;
-#define AM_BSP_IOM3_CS_CHNL             0
+#define AM_BSP_GPIO_IOM3_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -314,7 +314,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM3_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM4_CS             	13
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_CS;
-#define AM_BSP_IOM4_CS_CHNL             1
+#define AM_BSP_GPIO_IOM4_CS_CHNL        1
 
 //*****************************************************************************
 //
@@ -363,7 +363,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM4_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOM5_CS             	16
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_CS;
-#define AM_BSP_IOM5_CS_CHNL             0
+#define AM_BSP_GPIO_IOM5_CS_CHNL        0
 
 //*****************************************************************************
 //
@@ -412,7 +412,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOM5_SDA;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE0            	19
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
-#define AM_BSP_MSPI_CE0_CHNL            0
+#define AM_BSP_GPIO_MSPI_CE0_CHNL       0
 
 //*****************************************************************************
 //
@@ -421,7 +421,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE0;
 //*****************************************************************************
 #define AM_BSP_GPIO_MSPI_CE1            	41
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_CE1;
-#define AM_BSP_MSPI_CE1_CHNL            1
+#define AM_BSP_GPIO_MSPI_CE1_CHNL       1
 
 //*****************************************************************************
 //
@@ -502,7 +502,7 @@ extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_MSPI_SCK;
 //*****************************************************************************
 #define AM_BSP_GPIO_IOS_CE              	3
 extern const am_hal_gpio_pincfg_t       g_AM_BSP_GPIO_IOS_CE;
-#define AM_BSP_IOS_CE_CHNL              0
+#define AM_BSP_GPIO_IOS_CE_CHNL         0
 
 //*****************************************************************************
 //
diff --git a/redboard_artemis_nano/bsp/gcc/bin/libam_bsp.a b/redboard_artemis_nano/bsp/gcc/bin/libam_bsp.a
index fd721f67417ce9ad7775bc432f7de20efb512e48..32864777f7e7ee72a7ea3a06cd4e080a04d1bb17 100644
GIT binary patch
delta 1728
zcmc(fe`p(Z6u`gVYx6tpu8Yf(Al<jQkxM$#Ub3XUThb(zGOAbCGDIsyx6}pG(QaL;
zB4f}p1d9&Lc%Vkd3fs{Bp{#f~{b#Lz%|F~^ASejpltSWP7XR49Lg%~Ow_}3fKf=Cn
z@AKZf_rCYu``+EJH|gD5v>J5vDT=D@PbJgm!)N9T&l2(oulYyx@Z!vo$+_7huNoKV
zWyjtJ6Jac^Bp72!1qDkeN?$64OeuW|Z02R*nI7Yu>ms#ZZ>R;rK=D*jb)stA@FZJX
zCMx5wx#QFHcl8e4$Aabi_qOhfx}R(9dWdUndMnpF`fhfyF6c3K3w{#!A3wX|ijqIx
zUHG{{HbS<LZEWVPcVu~3f4m%HT?ftmx(*U%k#Yu@uyVa27SOwv!${wQNI#DVvES<b
z|F{!lFx^p@|EexE3#I4HEose4ptVplk=9x{cXK}csK>DAV0k;!DvH*uqG(Ov87=>k
zY3HRZwbfgAXCKss71-)Xb()O?%gwAcmu`*FsasykU~K0#oVZx94};e??lRB8HjK5y
zFXFD0_<8%t*%j6tyHyVf3tg6NNr$dHRC59cXME<1QC*8Cm4p^Qm5R?4kDsi>nAVf*
zN#JXc&=N{A&7zgkbg4L3im{2o!%z1XD>HE|K3OTAc&W@PrPrqBrcRz<$^QPdrWxT~
zH-&IJ*<JzSMm4Z)qSl6bmKtK9lhUlw8#L@ffx`NpRXSu`W=lJQH!#3GNyu%^A34`y
zLV5W~#;qu)!ub^EVa{Wm)10qxp5c50zUkRBe}!AuI9EBhYxtJi-*awo{>e$GRjZRz
z<jf+43L!a+>%?BxIXlsB+B>a$V=D1H)tsg=ONco&chQ=bdkO<h`xGJFRxrsTg(3W5
znZ(UiV>9Wo(FJg*qqGXop}Yehqg;l2>Zm{@7}gF6ss!&N3KBH5Lv#%K517GkqWltm
zIIzzge)R=Egfd>+vP{Sw*q4#$I*evyVKEA?XCib2mNGJJz}F}*!0&j2#UPN4&`%(r
zl?5dR<!nT7x}l1`DtwWZZAbCchhXptAKcA~nCcji=@sZ5kcDVBj1OS62Nn>E-LQ;E
zdEmAMmh(e<PBc9%7qO*0ggBe~yok=M2WE2-Z126COpn1@P8Q0h%MV*Q(N@LS)8NZX
zg4+vfJ|Yyna1=oTu$Yfvw^#E~=|BE;nwnJMuY8n_7*av~f4_`NgWkRLG+Zr7wvX^N
j&>)kS@W3`pvV8+TiVtmYE*}oO?IUE>fhWutMmE>q>9FDA

delta 1455
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