diff --git a/CHANGELOG.md b/CHANGELOG.md index c615acf0..e8d16faa 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,7 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). Remove `RemapStruct`s. [#462] [#506] [#509] - Use independent `Spi` and `SpiSlave` structures instead of `OP` generic [#462] - Take `&Clocks` instead of `Clocks` [#498] -- Temporary replace `stm32f1` with `stm32f1-staging` [#503] +- Temporary replace `stm32f1` with `stm32f1-staging` v0.17.1 [#503] - `Spi` now takes `Option` for `SCK`, `MISO`, `MOSI` [#514] - move `Qei` mod inside `pwm_input` mod [#516] diff --git a/Cargo.toml b/Cargo.toml index 74f9ae7b..f858b84e 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -2,7 +2,10 @@ edition = "2021" rust-version = "1.59" -authors = ["Jorge Aparicio ", "Daniel Egger "] +authors = [ + "Jorge Aparicio ", + "Daniel Egger ", +] categories = ["embedded", "hardware-support", "no-std"] description = "HAL for the STM32F1xx family of microcontrollers" keywords = ["arm", "cortex-m", "stm32", "hal"] @@ -33,7 +36,7 @@ vcell = "0.1.3" [dependencies.stm32f1] package = "stm32f1-staging" -version = "0.16.0" +version = "0.17.1" features = ["atomics"] [dependencies.embedded-hal-02] diff --git a/src/adc.rs b/src/adc.rs index 38f02c0e..e282b8cb 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -256,7 +256,7 @@ macro_rules! adc_hal { #[inline(always)] pub fn set_external_trigger(&mut self, trigger: crate::pac::$adc::cr2::EXTSEL) { - self.rb.cr2().modify(|_, w| w.extsel().variant(trigger)) + self.rb.cr2().modify(|_, w| w.extsel().variant(trigger)); } fn power_up(&mut self) { @@ -336,7 +336,7 @@ macro_rules! adc_hal { 16 => self.rb.smpr1().modify(|_, w| w.smp16().set(sample_time)), 17 => self.rb.smpr1().modify(|_, w| w.smp17().set(sample_time)), _ => unreachable!(), - } + }; } fn set_regular_sequence (&mut self, channels: &[u8]) { diff --git a/src/crc.rs b/src/crc.rs index 72d9ced5..85740342 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -30,7 +30,7 @@ impl Crc { } pub fn write(&mut self, val: u32) { - self.crc.dr().write(|w| w.dr().set(val)) + self.crc.dr().write(|w| w.dr().set(val)); } pub fn reset(&self) { diff --git a/src/dma.rs b/src/dma.rs index 16988820..bd73630d 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -165,14 +165,14 @@ impl Ch { match event { Event::HalfTransfer => self.ch().cr().modify(|_, w| w.htie().set_bit()), Event::TransferComplete => self.ch().cr().modify(|_, w| w.tcie().set_bit()), - } + }; } pub fn unlisten(&mut self, event: Event) { match event { Event::HalfTransfer => self.ch().cr().modify(|_, w| w.htie().clear_bit()), Event::TransferComplete => self.ch().cr().modify(|_, w| w.tcie().clear_bit()), - } + }; } pub fn ch(&mut self) -> &pac::dma1::CH { diff --git a/src/gpio.rs b/src/gpio.rs index de5e53d6..75b22b52 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -532,14 +532,14 @@ impl Pin { fn _set_high(&mut self) { // NOTE(unsafe) atomic write to a stateless register let gpio = unsafe { &(*gpiox::

()) }; - gpio.bsrr().write(|w| w.bs(N).set_bit()) + gpio.bsrr().write(|w| w.bs(N).set_bit()); } #[inline(always)] fn _set_low(&mut self) { // NOTE(unsafe) atomic write to a stateless register let gpio = unsafe { &(*gpiox::

()) }; - gpio.bsrr().write(|w| w.br(N).set_bit()) + gpio.bsrr().write(|w| w.br(N).set_bit()); } #[inline(always)] @@ -966,7 +966,7 @@ where } else { w.br(N).set_bit() } - }) + }); } match N { diff --git a/src/i2c.rs b/src/i2c.rs index 102bb528..0d41215a 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -271,6 +271,9 @@ impl I2c { /// Generate START condition fn send_start(&mut self) { + // Clear all pending error bits + // NOTE(unsafe): Writing 0 clears the r/w bits and has no effect on the r bits + self.i2c.sr1().write(|w| unsafe { w.bits(0) }); self.i2c.cr1().modify(|_, w| w.start().set_bit()); } diff --git a/src/rcc.rs b/src/rcc.rs index 56ef5c2f..fccd814c 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -213,7 +213,7 @@ impl CFGR { } else { 0b010 }) - }) + }); } let rcc = unsafe { &*RCC::ptr() }; diff --git a/src/rtc.rs b/src/rtc.rs index ff177a33..ad279360 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -128,7 +128,7 @@ impl Rtc { w.rtcen().set_bit(); // Set the source of the RTC to LSE w.rtcsel().lse() - }) + }); } } @@ -202,7 +202,7 @@ impl Rtc { w.rtcen().set_bit(); // Set the source of the RTC to LSI w.rtcsel().lsi() - }) + }); } } @@ -280,7 +280,7 @@ impl Rtc { w.rtcen().set_bit(); // Set the source of the RTC to HSE/128 w.rtcsel().hse() - }) + }); } } @@ -365,22 +365,30 @@ impl Rtc { /// Enables triggering the RTC interrupt every time the RTC counter is increased pub fn listen_seconds(&mut self) { - self.perform_write(|s| s.regs.crh().modify(|_, w| w.secie().set_bit())) + self.perform_write(|s| { + s.regs.crh().modify(|_, w| w.secie().set_bit()); + }) } /// Disables the RTC second interrupt pub fn unlisten_seconds(&mut self) { - self.perform_write(|s| s.regs.crh().modify(|_, w| w.secie().clear_bit())) + self.perform_write(|s| { + s.regs.crh().modify(|_, w| w.secie().clear_bit()); + }) } /// Clears the RTC second interrupt flag pub fn clear_second_flag(&mut self) { - self.perform_write(|s| s.regs.crl().modify(|_, w| w.secf().clear_bit())) + self.perform_write(|s| { + s.regs.crl().modify(|_, w| w.secf().clear_bit()); + }) } /// Clears the RTC alarm interrupt flag pub fn clear_alarm_flag(&mut self) { - self.perform_write(|s| s.regs.crl().modify(|_, w| w.alrf().clear_bit())) + self.perform_write(|s| { + s.regs.crl().modify(|_, w| w.alrf().clear_bit()); + }) } /** diff --git a/src/timer.rs b/src/timer.rs index 997507ce..b9e5d63a 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -325,7 +325,7 @@ macro_rules! hal { } #[inline(always)] unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) { - self.arr().write(|w| w.bits(arr)) + self.arr().write(|w| w.bits(arr)); } #[inline(always)] fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> { @@ -445,7 +445,7 @@ macro_rules! with_pwm { let tim = unsafe { &*<$TIM>::ptr() }; #[allow(unused_unsafe)] if channel < Self::CH_NUMBER { - tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }) + tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }); } } @@ -493,7 +493,7 @@ macro_rules! with_pwm { let tim = unsafe { &*<$TIM>::ptr() }; #[allow(unused_unsafe)] if channel < Self::CH_NUMBER { - tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }) + tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }); } } @@ -539,7 +539,7 @@ macro_rules! with_pwm { #[inline(always)] fn set_cc_value(channel: u8, value: u32) { let tim = unsafe { &*<$TIM>::ptr() }; - tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }) + tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) }); } #[inline(always)]