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both embedded-hals for SPI
1 parent 963fe0b commit f8e1b7e

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3 files changed

+404
-152
lines changed

3 files changed

+404
-152
lines changed

src/spi.rs

+35-152
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,36 @@ use core::ptr;
44

55
use crate::dma::traits::PeriAddress;
66
use crate::gpio::{Const, NoPin, PinA, PushPull, SetAlternate};
7-
use embedded_hal::spi;
8-
pub use embedded_hal::spi::{Mode, Phase, Polarity};
7+
8+
/// Clock polarity
9+
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10+
pub enum Polarity {
11+
/// Clock signal low when idle
12+
IdleLow,
13+
/// Clock signal high when idle
14+
IdleHigh,
15+
}
16+
17+
/// Clock phase
18+
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
19+
pub enum Phase {
20+
/// Data in "captured" on the first clock transition
21+
CaptureOnFirstTransition,
22+
/// Data in "captured" on the second clock transition
23+
CaptureOnSecondTransition,
24+
}
25+
26+
/// SPI mode
27+
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
28+
pub struct Mode {
29+
/// Clock polarity
30+
pub polarity: Polarity,
31+
/// Clock phase
32+
pub phase: Phase,
33+
}
34+
35+
mod hal_02;
36+
mod hal_1;
937

1038
use crate::pac::{spi1, RCC, SPI1, SPI2};
1139
use crate::rcc;
@@ -141,7 +169,7 @@ where
141169
pub fn new(
142170
spi: SPI,
143171
mut pins: PINS,
144-
mode: Mode,
172+
mode: impl Into<Mode>,
145173
freq: impl Into<Hertz>,
146174
clocks: &Clocks,
147175
) -> Self {
@@ -155,7 +183,7 @@ where
155183
pins.set_alt_mode();
156184

157185
Self::_new(spi, pins)
158-
.pre_init(mode, freq.into(), SPI::clock(clocks))
186+
.pre_init(mode.into(), freq.into(), SPI::clock(clocks))
159187
.init()
160188
}
161189

@@ -174,7 +202,7 @@ where
174202
pub fn new_bidi(
175203
spi: SPI,
176204
mut pins: PINS,
177-
mode: Mode,
205+
mode: impl Into<Mode>,
178206
freq: impl Into<Hertz>,
179207
clocks: &Clocks,
180208
) -> Self {
@@ -188,7 +216,7 @@ where
188216
pins.set_alt_mode();
189217

190218
Self::_new(spi, pins)
191-
.pre_init(mode, freq.into(), SPI::clock(clocks))
219+
.pre_init(mode.into(), freq.into(), SPI::clock(clocks))
192220
.init()
193221
}
194222

@@ -277,7 +305,7 @@ where
277305
}
278306

279307
/// Pre initializing the SPI bus.
280-
pub fn pre_init(self, mode: Mode, freq: Hertz, clock: Hertz) -> Self {
308+
fn pre_init(self, mode: Mode, freq: Hertz, clock: Hertz) -> Self {
281309
// disable SS output
282310
self.spi.cr2.write(|w| w.ssoe().clear_bit());
283311

@@ -493,148 +521,3 @@ where
493521

494522
type MemSize = u8;
495523
}
496-
497-
impl<SPI, PINS> spi::FullDuplex<u8> for Spi<SPI, PINS, TransferModeNormal>
498-
where
499-
SPI: Instance,
500-
{
501-
type Error = Error;
502-
503-
fn read(&mut self) -> nb::Result<u8, Error> {
504-
self.check_read()
505-
}
506-
507-
fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
508-
self.check_send(byte)
509-
}
510-
}
511-
512-
impl<SPI, PINS> spi::FullDuplex<u8> for Spi<SPI, PINS, TransferModeBidi>
513-
where
514-
SPI: Instance,
515-
{
516-
type Error = Error;
517-
518-
fn read(&mut self) -> nb::Result<u8, Error> {
519-
self.spi.cr1.modify(|_, w| w.bidioe().clear_bit());
520-
self.check_read()
521-
}
522-
523-
fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
524-
self.spi.cr1.modify(|_, w| w.bidioe().set_bit());
525-
self.check_send(byte)
526-
}
527-
}
528-
529-
mod blocking {
530-
use super::{Error, Instance, Spi, TransferModeBidi, TransferModeNormal};
531-
use embedded_hal::blocking::spi::{Operation, Transactional, Transfer, Write, WriteIter};
532-
use embedded_hal::spi::FullDuplex;
533-
534-
impl<SPI, PINS, TRANSFER_MODE> Transfer<u8> for Spi<SPI, PINS, TRANSFER_MODE>
535-
where
536-
Self: FullDuplex<u8, Error = Error>,
537-
SPI: Instance,
538-
{
539-
type Error = Error;
540-
541-
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
542-
for word in words.iter_mut() {
543-
nb::block!(self.send(*word))?;
544-
*word = nb::block!(self.read())?;
545-
}
546-
547-
Ok(words)
548-
}
549-
}
550-
551-
impl<SPI, PINS> Write<u8> for Spi<SPI, PINS, TransferModeNormal>
552-
where
553-
Self: FullDuplex<u8, Error = Error>,
554-
SPI: Instance,
555-
{
556-
type Error = Error;
557-
558-
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
559-
for word in words {
560-
nb::block!(self.send(*word))?;
561-
nb::block!(self.read())?;
562-
}
563-
564-
Ok(())
565-
}
566-
}
567-
568-
impl<SPI, PINS> Write<u8> for Spi<SPI, PINS, TransferModeBidi>
569-
where
570-
Self: FullDuplex<u8, Error = Error>,
571-
SPI: Instance,
572-
{
573-
type Error = Error;
574-
575-
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
576-
for word in words {
577-
nb::block!(self.send(*word))?;
578-
}
579-
580-
Ok(())
581-
}
582-
}
583-
584-
impl<SPI, PINS> WriteIter<u8> for Spi<SPI, PINS, TransferModeNormal>
585-
where
586-
Self: FullDuplex<u8, Error = Error>,
587-
SPI: Instance,
588-
{
589-
type Error = Error;
590-
591-
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Self::Error>
592-
where
593-
WI: IntoIterator<Item = u8>,
594-
{
595-
for word in words.into_iter() {
596-
nb::block!(self.send(word))?;
597-
nb::block!(self.read())?;
598-
}
599-
600-
Ok(())
601-
}
602-
}
603-
604-
impl<SPI, PINS> WriteIter<u8> for Spi<SPI, PINS, TransferModeBidi>
605-
where
606-
Self: FullDuplex<u8, Error = Error>,
607-
SPI: Instance,
608-
{
609-
type Error = Error;
610-
611-
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Self::Error>
612-
where
613-
WI: IntoIterator<Item = u8>,
614-
{
615-
for word in words.into_iter() {
616-
nb::block!(self.send(word))?;
617-
}
618-
619-
Ok(())
620-
}
621-
}
622-
623-
impl<SPI, PINS, TRANSFER_MODE, W: 'static> Transactional<W> for Spi<SPI, PINS, TRANSFER_MODE>
624-
where
625-
Self: Write<W, Error = Error> + Transfer<W, Error = Error>,
626-
{
627-
type Error = Error;
628-
629-
fn exec<'a>(&mut self, operations: &mut [Operation<'a, W>]) -> Result<(), Error> {
630-
for op in operations {
631-
match op {
632-
Operation::Write(w) => self.write(w)?,
633-
Operation::Transfer(t) => self.transfer(t).map(|_| ())?,
634-
}
635-
}
636-
637-
Ok(())
638-
}
639-
}
640-
}

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