From 067bd015a95010e8ee55650f05e424c4b3a2408e Mon Sep 17 00:00:00 2001 From: stnolting Date: Fri, 7 Feb 2025 18:55:10 +0100 Subject: [PATCH] =?UTF-8?q?=F0=9F=9A=80=20preparing=20release=20v1.11.1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- CHANGELOG.md | 1 + docs/attrs.adoc | 2 +- rtl/core/neorv32_package.vhd | 2 +- sw/svd/neorv32.svd | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 84fc63c00..5a3119098 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 07.02.2025 | [**:rocket:1.11.1**](https://github.com/stnolting/neorv32/releases/tag/v1.11.1) | **New release** | | | 07.02.2025 | 1.11.0.10 | :warning: rename UART RTS/CTS signals | [#1180](https://github.com/stnolting/neorv32/pull/1180) | | 07.02.2025 | 1.11.0.9 | minor rtl edits and cleanups | [#1179](https://github.com/stnolting/neorv32/pull/1179) | | 03.02.2025 | 1.11.0.8 | :sparkles: add explicit memory ordering/coherence support; :warning: remove WDT "halt-on-debug" and "halt-on-sleep" options; :bug: rework cache module fixing several (minor?) design flaws | [#1176](https://github.com/stnolting/neorv32/pull/1176) | diff --git a/docs/attrs.adoc b/docs/attrs.adoc index 213505e49..58dce295c 100644 --- a/docs/attrs.adoc +++ b/docs/attrs.adoc @@ -2,7 +2,7 @@ :email: stnolting@gmail.com :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. -:revnumber: v1.11.0 +:revnumber: v1.11.1 :icons: font :source-highlighter: highlight.js :imagesdir: ../figures diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index cc282ae0f..ba78379d0 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110010"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110100"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index 2d60918a4..26c6691a1 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -4,7 +4,7 @@ stnolting neorv32 RISC-V - 1.11.0 + 1.11.1 The NEORV32 RISC-V Processor