From 085caa90d2e7a74ec4a6cbd772eb7d2367ffb855 Mon Sep 17 00:00:00 2001 From: John Slee Date: Sun, 19 Jan 2014 17:34:41 +1100 Subject: [PATCH 1/4] fix missing endif in MCU selection --- makefile.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/makefile.mk b/makefile.mk index 23525fe..3c1f5be 100644 --- a/makefile.mk +++ b/makefile.mk @@ -41,6 +41,7 @@ DMCU = m$(MCU_NAME)p MCU_DEFINE = ATMEGA$(MCU_NAME)P endif endif +endif F_CPU ?= 20000000 From de97d4bafb5c1d237a4e3b81614779e69f96b550 Mon Sep 17 00:00:00 2001 From: John Slee Date: Sun, 19 Jan 2014 17:39:59 +1100 Subject: [PATCH 2/4] missing semicolon breaks mega2560 builds --- boot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot.h b/boot.h index 87c3475..c5606eb 100755 --- a/boot.h +++ b/boot.h @@ -53,7 +53,7 @@ inline void Boot(bool init_timers) { #endif #ifdef HAS_USART3 - UCSR3B = 0 + UCSR3B = 0; #endif } From ccf0446332141c85ab8c5161bfe937c7c590b732 Mon Sep 17 00:00:00 2001 From: John Slee Date: Sun, 19 Jan 2014 18:11:34 +1100 Subject: [PATCH 3/4] add remaining ATmega2560 GPIO pin definitions --- gpio.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/gpio.h b/gpio.h index db01451..7b5af8d 100755 --- a/gpio.h +++ b/gpio.h @@ -370,6 +370,60 @@ SetupGpio(29, PortE, NoPwmChannel, 5); SetupGpio(30, PortE, NoPwmChannel, 6); SetupGpio(31, PortE, NoPwmChannel, 7); +SetupGpio(32, PortF, NoPwmChannel, 0); +SetupGpio(33, PortF, NoPwmChannel, 1); +SetupGpio(34, PortF, NoPwmChannel, 2); +SetupGpio(35, PortF, NoPwmChannel, 3); +SetupGpio(36, PortF, NoPwmChannel, 4); +SetupGpio(37, PortF, NoPwmChannel, 5); +SetupGpio(38, PortF, NoPwmChannel, 6); +SetupGpio(39, PortF, NoPwmChannel, 7); + +SetupGpio(32, PortG, NoPwmChannel, 0); +SetupGpio(33, PortG, NoPwmChannel, 1); +SetupGpio(34, PortG, NoPwmChannel, 2); +SetupGpio(35, PortG, NoPwmChannel, 3); +SetupGpio(36, PortG, NoPwmChannel, 4); +SetupGpio(37, PortG, NoPwmChannel, 5); +SetupGpio(38, PortG, NoPwmChannel, 6); +SetupGpio(39, PortG, NoPwmChannel, 7); + +SetupGpio(32, PortH, NoPwmChannel, 0); +SetupGpio(33, PortH, NoPwmChannel, 1); +SetupGpio(34, PortH, NoPwmChannel, 2); +SetupGpio(35, PortH, NoPwmChannel, 3); +SetupGpio(36, PortH, NoPwmChannel, 4); +SetupGpio(37, PortH, NoPwmChannel, 5); +SetupGpio(38, PortH, NoPwmChannel, 6); +SetupGpio(39, PortH, NoPwmChannel, 7); + +SetupGpio(40, PortJ, NoPwmChannel, 0); +SetupGpio(41, PortJ, NoPwmChannel, 1); +SetupGpio(42, PortJ, NoPwmChannel, 2); +SetupGpio(43, PortJ, NoPwmChannel, 3); +SetupGpio(44, PortJ, NoPwmChannel, 4); +SetupGpio(45, PortJ, NoPwmChannel, 5); +SetupGpio(46, PortJ, NoPwmChannel, 6); +SetupGpio(47, PortJ, NoPwmChannel, 7); + +SetupGpio(48, PortK, NoPwmChannel, 0); +SetupGpio(49, PortK, NoPwmChannel, 1); +SetupGpio(50, PortK, NoPwmChannel, 2); +SetupGpio(51, PortK, NoPwmChannel, 3); +SetupGpio(52, PortK, NoPwmChannel, 4); +SetupGpio(53, PortK, NoPwmChannel, 5); +SetupGpio(54, PortK, NoPwmChannel, 6); +SetupGpio(55, PortK, NoPwmChannel, 7); + +SetupGpio(56, PortL, NoPwmChannel, 0); +SetupGpio(57, PortL, NoPwmChannel, 1); +SetupGpio(58, PortL, NoPwmChannel, 2); +SetupGpio(59, PortL, NoPwmChannel, 3); +SetupGpio(60, PortL, NoPwmChannel, 4); +SetupGpio(61, PortL, NoPwmChannel, 5); +SetupGpio(62, PortL, NoPwmChannel, 6); +SetupGpio(63, PortL, NoPwmChannel, 7); + typedef Gpio SpiSS; typedef Gpio SpiSCK; typedef Gpio SpiMOSI; From 1fd775cb84cb44ace8c4555d97141ae8202e8e2c Mon Sep 17 00:00:00 2001 From: John Slee Date: Sun, 19 Jan 2014 18:32:26 +1100 Subject: [PATCH 4/4] fix broken gpio numbering --- gpio.h | 88 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/gpio.h b/gpio.h index 7b5af8d..259c7b8 100755 --- a/gpio.h +++ b/gpio.h @@ -379,50 +379,50 @@ SetupGpio(37, PortF, NoPwmChannel, 5); SetupGpio(38, PortF, NoPwmChannel, 6); SetupGpio(39, PortF, NoPwmChannel, 7); -SetupGpio(32, PortG, NoPwmChannel, 0); -SetupGpio(33, PortG, NoPwmChannel, 1); -SetupGpio(34, PortG, NoPwmChannel, 2); -SetupGpio(35, PortG, NoPwmChannel, 3); -SetupGpio(36, PortG, NoPwmChannel, 4); -SetupGpio(37, PortG, NoPwmChannel, 5); -SetupGpio(38, PortG, NoPwmChannel, 6); -SetupGpio(39, PortG, NoPwmChannel, 7); - -SetupGpio(32, PortH, NoPwmChannel, 0); -SetupGpio(33, PortH, NoPwmChannel, 1); -SetupGpio(34, PortH, NoPwmChannel, 2); -SetupGpio(35, PortH, NoPwmChannel, 3); -SetupGpio(36, PortH, NoPwmChannel, 4); -SetupGpio(37, PortH, NoPwmChannel, 5); -SetupGpio(38, PortH, NoPwmChannel, 6); -SetupGpio(39, PortH, NoPwmChannel, 7); - -SetupGpio(40, PortJ, NoPwmChannel, 0); -SetupGpio(41, PortJ, NoPwmChannel, 1); -SetupGpio(42, PortJ, NoPwmChannel, 2); -SetupGpio(43, PortJ, NoPwmChannel, 3); -SetupGpio(44, PortJ, NoPwmChannel, 4); -SetupGpio(45, PortJ, NoPwmChannel, 5); -SetupGpio(46, PortJ, NoPwmChannel, 6); -SetupGpio(47, PortJ, NoPwmChannel, 7); - -SetupGpio(48, PortK, NoPwmChannel, 0); -SetupGpio(49, PortK, NoPwmChannel, 1); -SetupGpio(50, PortK, NoPwmChannel, 2); -SetupGpio(51, PortK, NoPwmChannel, 3); -SetupGpio(52, PortK, NoPwmChannel, 4); -SetupGpio(53, PortK, NoPwmChannel, 5); -SetupGpio(54, PortK, NoPwmChannel, 6); -SetupGpio(55, PortK, NoPwmChannel, 7); - -SetupGpio(56, PortL, NoPwmChannel, 0); -SetupGpio(57, PortL, NoPwmChannel, 1); -SetupGpio(58, PortL, NoPwmChannel, 2); -SetupGpio(59, PortL, NoPwmChannel, 3); -SetupGpio(60, PortL, NoPwmChannel, 4); -SetupGpio(61, PortL, NoPwmChannel, 5); -SetupGpio(62, PortL, NoPwmChannel, 6); -SetupGpio(63, PortL, NoPwmChannel, 7); +SetupGpio(40, PortG, NoPwmChannel, 0); +SetupGpio(41, PortG, NoPwmChannel, 1); +SetupGpio(42, PortG, NoPwmChannel, 2); +SetupGpio(43, PortG, NoPwmChannel, 3); +SetupGpio(44, PortG, NoPwmChannel, 4); +SetupGpio(45, PortG, NoPwmChannel, 5); +SetupGpio(46, PortG, NoPwmChannel, 6); +SetupGpio(47, PortG, NoPwmChannel, 7); + +SetupGpio(48, PortH, NoPwmChannel, 0); +SetupGpio(49, PortH, NoPwmChannel, 1); +SetupGpio(50, PortH, NoPwmChannel, 2); +SetupGpio(51, PortH, NoPwmChannel, 3); +SetupGpio(52, PortH, NoPwmChannel, 4); +SetupGpio(53, PortH, NoPwmChannel, 5); +SetupGpio(54, PortH, NoPwmChannel, 6); +SetupGpio(55, PortH, NoPwmChannel, 7); + +SetupGpio(56, PortJ, NoPwmChannel, 0); +SetupGpio(57, PortJ, NoPwmChannel, 1); +SetupGpio(58, PortJ, NoPwmChannel, 2); +SetupGpio(59, PortJ, NoPwmChannel, 3); +SetupGpio(60, PortJ, NoPwmChannel, 4); +SetupGpio(61, PortJ, NoPwmChannel, 5); +SetupGpio(62, PortJ, NoPwmChannel, 6); +SetupGpio(63, PortJ, NoPwmChannel, 7); + +SetupGpio(64, PortK, NoPwmChannel, 0); +SetupGpio(65, PortK, NoPwmChannel, 1); +SetupGpio(66, PortK, NoPwmChannel, 2); +SetupGpio(67, PortK, NoPwmChannel, 3); +SetupGpio(68, PortK, NoPwmChannel, 4); +SetupGpio(69, PortK, NoPwmChannel, 5); +SetupGpio(70, PortK, NoPwmChannel, 6); +SetupGpio(71, PortK, NoPwmChannel, 7); + +SetupGpio(72, PortL, NoPwmChannel, 0); +SetupGpio(73, PortL, NoPwmChannel, 1); +SetupGpio(74, PortL, NoPwmChannel, 2); +SetupGpio(75, PortL, NoPwmChannel, 3); +SetupGpio(76, PortL, NoPwmChannel, 4); +SetupGpio(77, PortL, NoPwmChannel, 5); +SetupGpio(78, PortL, NoPwmChannel, 6); +SetupGpio(79, PortL, NoPwmChannel, 7); typedef Gpio SpiSS; typedef Gpio SpiSCK;