From 1c5dafa1a46994ac2db07ad3fa18abae5cd3cb12 Mon Sep 17 00:00:00 2001 From: Tomasz Hemperek Date: Sun, 15 Nov 2020 21:49:45 +0100 Subject: [PATCH] Create RTL_LIBRARY for questa verilog simulations --- cocotb_test/simulator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cocotb_test/simulator.py b/cocotb_test/simulator.py index 21e34b4..57fd3f2 100644 --- a/cocotb_test/simulator.py +++ b/cocotb_test/simulator.py @@ -408,7 +408,7 @@ def build_command(self): cmd.append(["vsim"] + ["-c"] + ["-do"] + [do_script]) if self.verilog_sources: - do_script = "vlog -mixedsvvh -work {RTL_LIBRARY} +define+COCOTB_SIM -sv {DEFINES} {INCDIR} {EXTRA_ARGS} {VERILOG_SOURCES}; quit".format( + do_script = "vlib {RTL_LIBRARY}; vlog -mixedsvvh -work {RTL_LIBRARY} +define+COCOTB_SIM -sv {DEFINES} {INCDIR} {EXTRA_ARGS} {VERILOG_SOURCES}; quit".format( RTL_LIBRARY=as_tcl_value(self.rtl_library), VERILOG_SOURCES=" ".join(as_tcl_value(v) for v in self.verilog_sources), DEFINES=" ".join(self.get_define_commands(self.defines)),