From eb0a524972277a0168ffd41d7ed1111361638506 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 3 Jan 2023 19:21:25 +0000 Subject: [PATCH] yamllint: indentation: fix dts/bindings/ Fix the YAML files indentation for files in dts/bindings/. Signed-off-by: Fabio Baltieri --- dts/bindings/adc/adc-controller.yaml | 268 +++---- dts/bindings/adc/arduino,uno-adc.yaml | 22 +- dts/bindings/adc/atmel,sam-afec.yaml | 26 +- dts/bindings/adc/atmel,sam0-adc.yaml | 60 +- dts/bindings/adc/gd,gd32-adc.yaml | 50 +- dts/bindings/adc/infineon,xmc4xxx-adc.yaml | 24 +- dts/bindings/adc/ite,it8xxx2-adc.yaml | 14 +- dts/bindings/adc/microchip,mcp320x-base.yaml | 6 +- dts/bindings/adc/microchip,xec-adc-v2.yaml | 38 +- dts/bindings/adc/microchip,xec-adc.yaml | 30 +- dts/bindings/adc/nordic,nrf-adc.yaml | 14 +- dts/bindings/adc/nordic,nrf-comp.yaml | 18 +- dts/bindings/adc/nordic,nrf-lpcomp.yaml | 18 +- dts/bindings/adc/nordic,nrf-saadc.yaml | 14 +- dts/bindings/adc/nxp,kinetis-adc12.yaml | 44 +- dts/bindings/adc/nxp,kinetis-adc16.yaml | 88 +-- dts/bindings/adc/raspberrypi,pico-adc.yaml | 26 +- dts/bindings/adc/st,stm32-adc.yaml | 52 +- dts/bindings/adc/telink,b91-adc.yaml | 52 +- dts/bindings/adc/ti,ads1119.yaml | 4 +- dts/bindings/adc/ti,ads1x1x-base.yaml | 6 +- dts/bindings/adc/ti,cc13xx-cc26xx-adc.yaml | 14 +- dts/bindings/adc/ti,cc32xx-adc.yaml | 14 +- dts/bindings/adc/ti,lmp90xxx-base.yaml | 14 +- dts/bindings/adc/ti,lmp90xxx-current.yaml | 6 +- dts/bindings/adc/voltage-divider.yaml | 52 +- dts/bindings/adc/zephyr,adc-emul.yaml | 66 +- dts/bindings/alh/intel,alh-dai.yaml | 4 +- dts/bindings/arc/arc,dccm.yaml | 4 +- dts/bindings/arc/arc,iccm.yaml | 4 +- dts/bindings/arc/arc,xccm.yaml | 4 +- dts/bindings/arc/arc,yccm.yaml | 4 +- dts/bindings/arm/arm,beetle-syscon.yaml | 10 +- dts/bindings/arm/arm,dtcm.yaml | 4 +- dts/bindings/arm/arm,ethos-u.yaml | 20 +- dts/bindings/arm/arm,itcm.yaml | 4 +- dts/bindings/arm/arm,scc.yaml | 4 +- dts/bindings/arm/atmel,sam-ssc.yaml | 60 +- dts/bindings/arm/atmel,sam0-id.yaml | 4 +- dts/bindings/arm/atmel,sam0-sercom.yaml | 12 +- dts/bindings/arm/atmel,samd2x-pm.yaml | 8 +- dts/bindings/arm/nordic,nrf-acl.yaml | 4 +- dts/bindings/arm/nordic,nrf-bprot.yaml | 4 +- dts/bindings/arm/nordic,nrf-ctrlapperi.yaml | 4 +- dts/bindings/arm/nordic,nrf-dcnf.yaml | 4 +- dts/bindings/arm/nordic,nrf-dppic.yaml | 4 +- dts/bindings/arm/nordic,nrf-egu.yaml | 8 +- dts/bindings/arm/nordic,nrf-ficr.yaml | 4 +- dts/bindings/arm/nordic,nrf-kmu.yaml | 8 +- dts/bindings/arm/nordic,nrf-mpu.yaml | 4 +- dts/bindings/arm/nordic,nrf-mutex.yaml | 4 +- dts/bindings/arm/nordic,nrf-mwu.yaml | 4 +- dts/bindings/arm/nordic,nrf-ppi.yaml | 4 +- dts/bindings/arm/nordic,nrf-reset.yaml | 4 +- dts/bindings/arm/nordic,nrf-spu.yaml | 8 +- dts/bindings/arm/nordic,nrf-swi.yaml | 8 +- dts/bindings/arm/nordic,nrf-uicr.yaml | 4 +- dts/bindings/arm/nxp,imx-dtcm.yaml | 4 +- dts/bindings/arm/nxp,imx-epit.yaml | 16 +- dts/bindings/arm/nxp,imx-itcm.yaml | 4 +- dts/bindings/arm/nxp,imx-mu-rev2.yaml | 10 +- dts/bindings/arm/nxp,imx-mu.yaml | 10 +- dts/bindings/arm/nxp,kinetis-ftm.yaml | 34 +- dts/bindings/arm/nxp,lpc-flexcomm.yaml | 8 +- dts/bindings/arm/st,stm32-ccm.yaml | 4 +- dts/bindings/arm/xlnx,zynq-ocm.yaml | 4 +- dts/bindings/audio/nordic,nrf-pdm.yaml | 96 +-- dts/bindings/audio/ti,tlv320dac.yaml | 6 +- dts/bindings/base/base.yaml | 178 ++--- dts/bindings/base/pm.yaml | 34 +- dts/bindings/base/power.yaml | 44 +- .../bluetooth/zephyr,bt-hci-spi-slave.yaml | 6 +- dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml | 22 +- dts/bindings/can/atmel,sam-can.yaml | 36 +- dts/bindings/can/bosch,m_can-base.yaml | 36 +- dts/bindings/can/can-controller.yaml | 104 +-- dts/bindings/can/can-fd-controller.yaml | 52 +- dts/bindings/can/espressif,esp32-twai.yaml | 32 +- dts/bindings/can/kvaser,pcican.yaml | 4 +- dts/bindings/can/microchip,mcp2515.yaml | 30 +- dts/bindings/can/nxp,kinetis-flexcan.yaml | 20 +- dts/bindings/can/nxp,lpc-mcan.yaml | 12 +- dts/bindings/can/renesas,rcar-can.yaml | 12 +- dts/bindings/can/st,stm32-can.yaml | 26 +- dts/bindings/can/st,stm32-fdcan.yaml | 62 +- dts/bindings/can/st,stm32h7-fdcan.yaml | 12 +- .../can/zephyr,native-posix-linux-can.yaml | 8 +- dts/bindings/clock/aspeed,ast10x0-clock.yaml | 4 +- dts/bindings/clock/atmel,samc2x-gclk.yaml | 8 +- dts/bindings/clock/atmel,samc2x-mclk.yaml | 8 +- dts/bindings/clock/atmel,samd2x-gclk.yaml | 8 +- dts/bindings/clock/atmel,samd5x-gclk.yaml | 8 +- dts/bindings/clock/atmel,samd5x-mclk.yaml | 8 +- dts/bindings/clock/atmel,saml2x-gclk.yaml | 8 +- dts/bindings/clock/atmel,saml2x-mclk.yaml | 8 +- dts/bindings/clock/clock-controller.yaml | 8 +- dts/bindings/clock/espressif,esp32-rtc.yaml | 22 +- dts/bindings/clock/fixed-clock.yaml | 18 +- dts/bindings/clock/fixed-factor-clock.yaml | 22 +- dts/bindings/clock/gd,gd32-cctl.yaml | 4 +- .../clock/intel,adsp-shim-clkctl.yaml | 72 +- dts/bindings/clock/intel,agilex-clock.yaml | 8 +- dts/bindings/clock/microchip,xec-pcr.yaml | 184 ++--- dts/bindings/clock/nordic,nrf-clock.yaml | 22 +- .../clock/nordic,nrf-oscillators.yaml | 4 +- dts/bindings/clock/nuvoton,npcx-pcc.yaml | 376 +++++----- dts/bindings/clock/nxp,imx-anatop.yaml | 38 +- dts/bindings/clock/nxp,imx-ccm-rev2.yaml | 8 +- dts/bindings/clock/nxp,imx-ccm.yaml | 8 +- dts/bindings/clock/nxp,kinetis-ke1xf-sim.yaml | 16 +- dts/bindings/clock/nxp,kinetis-mcg.yaml | 8 +- dts/bindings/clock/nxp,kinetis-pcc.yaml | 8 +- dts/bindings/clock/nxp,kinetis-scg.yaml | 14 +- dts/bindings/clock/nxp,kinetis-sim.yaml | 48 +- dts/bindings/clock/nxp,lpc-syscon.yaml | 8 +- dts/bindings/clock/nxp,lpc11u6x-syscon.yaml | 16 +- dts/bindings/clock/renesas,rcar-cpg-mssr.yaml | 8 +- dts/bindings/clock/st,stm32-clock-mux.yaml | 10 +- dts/bindings/clock/st,stm32-hse-clock.yaml | 10 +- dts/bindings/clock/st,stm32-lse-clock.yaml | 34 +- dts/bindings/clock/st,stm32-msi-clock.yaml | 48 +- dts/bindings/clock/st,stm32-rcc.yaml | 116 +-- dts/bindings/clock/st,stm32f0-pll-clock.yaml | 12 +- dts/bindings/clock/st,stm32f1-pll-clock.yaml | 48 +- .../clock/st,stm32f100-pll-clock.yaml | 12 +- .../clock/st,stm32f105-pll-clock.yaml | 68 +- .../clock/st,stm32f105-pll2-clock.yaml | 30 +- dts/bindings/clock/st,stm32f2-pll-clock.yaml | 72 +- dts/bindings/clock/st,stm32f4-pll-clock.yaml | 74 +- dts/bindings/clock/st,stm32f7-pll-clock.yaml | 72 +- dts/bindings/clock/st,stm32g0-hsi-clock.yaml | 32 +- dts/bindings/clock/st,stm32g0-pll-clock.yaml | 64 +- dts/bindings/clock/st,stm32g4-pll-clock.yaml | 38 +- dts/bindings/clock/st,stm32h7-hsi-clock.yaml | 20 +- dts/bindings/clock/st,stm32h7-pll-clock.yaml | 76 +- dts/bindings/clock/st,stm32h7-rcc.yaml | 174 ++--- dts/bindings/clock/st,stm32l0-msi-clock.yaml | 28 +- dts/bindings/clock/st,stm32l0-pll-clock.yaml | 74 +- dts/bindings/clock/st,stm32l4-pll-clock.yaml | 98 +-- dts/bindings/clock/st,stm32u5-msi-clock.yaml | 46 +- dts/bindings/clock/st,stm32u5-pll-clock.yaml | 82 +-- dts/bindings/clock/st,stm32u5-rcc.yaml | 18 +- dts/bindings/clock/st,stm32wb-pll-clock.yaml | 76 +- dts/bindings/clock/st,stm32wb-rcc.yaml | 112 +-- dts/bindings/clock/st,stm32wl-hse-clock.yaml | 20 +- dts/bindings/clock/st,stm32wl-rcc.yaml | 66 +- dts/bindings/coredump/zephyr,coredump.yaml | 42 +- .../counter/espressif,esp32-rtc-timer.yaml | 10 +- .../counter/espressif,esp32-timer.yaml | 58 +- .../counter/intel,ace-art-counter.yaml | 2 +- .../counter/intel,ace-rtc-counter.yaml | 2 +- dts/bindings/counter/nxp,imx-qtmr.yaml | 8 +- dts/bindings/cpu/altr,nios2f.yaml | 2 +- .../cpu/cdns,tensilica-xtensa-lx6.yaml | 6 +- .../cpu/cdns,tensilica-xtensa-lx7.yaml | 6 +- dts/bindings/cpu/cpu.yaml | 24 +- dts/bindings/cpu/espressif,riscv.yaml | 6 +- dts/bindings/cpu/qemu,nios2-zephyr.yaml | 2 +- dts/bindings/crypto/arm,cryptocell-310.yaml | 8 +- dts/bindings/crypto/arm,cryptocell-312.yaml | 8 +- dts/bindings/crypto/intel,adsp-sha.yaml | 4 +- dts/bindings/crypto/nordic,nrf-cc310.yaml | 4 +- dts/bindings/crypto/nordic,nrf-cc312.yaml | 4 +- dts/bindings/crypto/nordic,nrf-ccm.yaml | 20 +- dts/bindings/crypto/nordic,nrf-ecb.yaml | 8 +- dts/bindings/crypto/nuvoton,npcx-sha.yaml | 4 +- .../crypto/silabs,gecko-semailbox.yaml | 8 +- .../crypto/st,stm32-crypto-common.yaml | 12 +- dts/bindings/dac/atmel,sam-dac.yaml | 46 +- dts/bindings/dac/atmel,sam0-dac.yaml | 34 +- dts/bindings/dac/dac-controller.yaml | 6 +- dts/bindings/dac/espressif,esp32-dac.yaml | 6 +- dts/bindings/dac/gd,gd32-dac.yaml | 34 +- dts/bindings/dac/microchip,mcp4725.yaml | 6 +- dts/bindings/dac/microchip,mcp4728.yaml | 62 +- dts/bindings/dac/nxp,kinetis-dac.yaml | 24 +- dts/bindings/dac/nxp,kinetis-dac32.yaml | 30 +- dts/bindings/dac/st,stm32-dac.yaml | 22 +- dts/bindings/dac/ti,dacx0508-base.yaml | 114 +-- dts/bindings/dac/ti,dacx3608-base.yaml | 6 +- dts/bindings/dai/intel,dai-dmic.yaml | 16 +- dts/bindings/debug/arm,itm.yaml | 6 +- dts/bindings/dfpmcch/intel,adsp-dfpmcch.yaml | 4 +- dts/bindings/dfpmccu/intel,adsp-dfpmccu.yaml | 4 +- dts/bindings/display/display-controller.yaml | 20 +- dts/bindings/display/ftdi,ft800.yaml | 192 ++--- dts/bindings/display/ilitek,ili9340.yaml | 156 ++-- dts/bindings/display/ilitek,ili9341.yaml | 292 ++++---- dts/bindings/display/ilitek,ili9488.yaml | 136 ++-- .../display/ilitek,ili9xxx-common.yaml | 88 +-- dts/bindings/display/maxim,max7219.yaml | 82 +-- .../display/nordic,nrf-led-matrix.yaml | 124 ++-- dts/bindings/display/nxp,imx-elcdif.yaml | 178 ++--- dts/bindings/display/raydium,rm68200.yaml | 20 +- dts/bindings/display/sharp,ls0xx.yaml | 34 +- dts/bindings/display/sitronix,st7735r.yaml | 248 +++---- dts/bindings/display/sitronix,st7789v.yaml | 204 +++--- .../display/solomon,ssd1306fb-common.yaml | 88 +-- .../display/solomon,ssd1306fb-spi.yaml | 8 +- dts/bindings/display/solomon,ssd16xxfb.yaml | 174 ++--- dts/bindings/display/st,stm32-ltdc.yaml | 200 +++--- .../display/ultrachip,uc81xx-common.yaml | 60 +- dts/bindings/dma/altr,msgdma.yaml | 12 +- dts/bindings/dma/arm,dma-pl330.yaml | 16 +- dts/bindings/dma/atmel,sam-xdmac.yaml | 20 +- dts/bindings/dma/atmel,sam0-dmac.yaml | 12 +- dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml | 50 +- dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml | 50 +- dts/bindings/dma/dma-controller.yaml | 66 +- dts/bindings/dma/dmamux-controller.yaml | 34 +- dts/bindings/dma/intel,adsp-gpdma.yaml | 14 +- dts/bindings/dma/intel,adsp-hda.yaml | 24 +- dts/bindings/dma/nxp,lpc-dma.yaml | 20 +- dts/bindings/dma/nxp,mcux-edma.yaml | 36 +- dts/bindings/dma/snps,designware-dma.yaml | 12 +- dts/bindings/dma/st,stm32-dma-v1.yaml | 4 +- dts/bindings/dma/st,stm32-dma-v2.yaml | 4 +- dts/bindings/dma/st,stm32-dma-v2bis.yaml | 4 +- dts/bindings/dma/st,stm32-dma.yaml | 36 +- dts/bindings/dma/st,stm32-dmamux.yaml | 12 +- dts/bindings/dma/st,stm32u5-dma.yaml | 4 +- dts/bindings/dsa/microchip,ksz8794.yaml | 46 +- dts/bindings/dsa/microchip_dsa.yaml | 52 +- .../zephyr,ec-host-cmd-periph-espi.yaml | 12 +- .../espi/microchip,xec-espi-host-dev.yaml | 92 +-- .../espi/microchip,xec-espi-saf-v2.yaml | 70 +- dts/bindings/espi/microchip,xec-espi-saf.yaml | 42 +- dts/bindings/espi/microchip,xec-espi-v2.yaml | 48 +- .../espi/microchip,xec-espi-vw-routing.yaml | 28 +- dts/bindings/espi/microchip,xec-espi.yaml | 48 +- .../espi/nuvoton,npcx-espi-vw-conf.yaml | 28 +- dts/bindings/espi/nuvoton,npcx-espi.yaml | 34 +- dts/bindings/espi/nuvoton,npcx-host-sub.yaml | 28 +- dts/bindings/espi/nuvoton,npcx-host-uart.yaml | 8 +- .../espi/zephyr,espi-emul-controller.yaml | 4 +- dts/bindings/ethernet/atmel,gmac-common.yaml | 102 +-- dts/bindings/ethernet/atmel,sam-gmac.yaml | 16 +- .../ethernet/ethernet,fixed-link.yaml | 24 +- dts/bindings/ethernet/ethernet-phy.yaml | 38 +- dts/bindings/ethernet/ethernet.yaml | 26 +- dts/bindings/ethernet/intel,e1000.yaml | 4 +- dts/bindings/ethernet/litex,eth0.yaml | 8 +- dts/bindings/ethernet/microchip,enc28j60.yaml | 14 +- .../ethernet/microchip,enc424j600.yaml | 14 +- .../ethernet/nxp,kinetis-ethernet.yaml | 30 +- dts/bindings/ethernet/nxp,kinetis-ptp.yaml | 4 +- .../ethernet/silabs,gecko-ethernet.yaml | 180 ++--- dts/bindings/ethernet/smsc,lan9220.yaml | 8 +- .../ethernet/snps,designware-ethernet.yaml | 8 +- .../ethernet/snps,ethernet-cyclonev.yaml | 8 +- dts/bindings/ethernet/st,stm32-ethernet.yaml | 24 +- .../ethernet/ti,stellaris-ethernet.yaml | 8 +- dts/bindings/ethernet/wiznet,w5500.yaml | 26 +- dts/bindings/ethernet/xlnx,gem.yaml | 674 +++++++++--------- .../flash_controller/altr,nios2-qspi-nor.yaml | 10 +- .../atmel,sam-flash-controller.yaml | 8 +- .../flash_controller/atmel,sam0-nvmctrl.yaml | 8 +- .../flash_controller/cdns,qspi-nor.yaml | 8 +- .../flash_controller/flash-controller.yaml | 4 +- .../flash_controller/micron,mt25qu02g.yaml | 6 +- .../nordic,nrf52-flash-controller.yaml | 8 +- .../nordic,nrf53-flash-controller.yaml | 8 +- .../nordic,nrf91-flash-controller.yaml | 8 +- .../flash_controller/st,stm32-ospi-nor.yaml | 164 ++--- .../flash_controller/st,stm32-qspi-nor.yaml | 76 +- .../st,stm32wb-flash-controller.yaml | 12 +- .../flash_controller/zephyr,sim-flash.yaml | 6 +- dts/bindings/fpga/lattice,ice40-fpga.yaml | 178 ++--- dts/bindings/gpio/andestech,atcgpio100.yaml | 14 +- dts/bindings/gpio/arm,cmsdk-gpio.yaml | 12 +- dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml | 12 +- dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml | 12 +- dts/bindings/gpio/atmel,sam-gpio.yaml | 30 +- dts/bindings/gpio/atmel,sam0-gpio.yaml | 18 +- .../gpio/cypress,cy8c95xx-gpio-port.yaml | 14 +- dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml | 4 +- dts/bindings/gpio/cypress,psoc6-gpio.yaml | 22 +- dts/bindings/gpio/cypress,psoc6-hsiom.yaml | 8 +- dts/bindings/gpio/espressif,esp32-gpio.yaml | 8 +- dts/bindings/gpio/fcs,fxl6408.yaml | 4 +- dts/bindings/gpio/gd,gd32-gpio.yaml | 16 +- dts/bindings/gpio/gpio-controller.yaml | 70 +- dts/bindings/gpio/gpio-nexus.yaml | 22 +- dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml | 8 +- dts/bindings/gpio/intel,gpio.yaml | 32 +- dts/bindings/gpio/ite,it8xxx2-gpio.yaml | 4 +- dts/bindings/gpio/litex,gpio.yaml | 18 +- dts/bindings/gpio/microchip,mcp230xx.yaml | 16 +- dts/bindings/gpio/microchip,mcp23s17.yaml | 14 +- dts/bindings/gpio/microchip,mcp23sxx.yaml | 18 +- dts/bindings/gpio/microchip,mpfs-gpio.yaml | 8 +- dts/bindings/gpio/microchip,xec-gpio-v2.yaml | 24 +- dts/bindings/gpio/microchip,xec-gpio.yaml | 24 +- dts/bindings/gpio/neorv32-gpio.yaml | 22 +- dts/bindings/gpio/nordic,nrf-gpio.yaml | 34 +- dts/bindings/gpio/nordic,nrf-gpiote.yaml | 8 +- .../gpio/nuvoton,nct38xx-gpio-alert.yaml | 18 +- .../gpio/nuvoton,nct38xx-gpio-port.yaml | 52 +- dts/bindings/gpio/nuvoton,npcx-gpio.yaml | 66 +- dts/bindings/gpio/nuvoton,numicro-gpio.yaml | 12 +- dts/bindings/gpio/nxp,imx-gpio.yaml | 36 +- dts/bindings/gpio/nxp,kinetis-gpio.yaml | 20 +- dts/bindings/gpio/nxp,lpc-gpio.yaml | 34 +- dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml | 36 +- dts/bindings/gpio/nxp,pca95xx.yaml | 22 +- dts/bindings/gpio/nxp,pcal6408a.yaml | 32 +- dts/bindings/gpio/nxp,pcf8574.yaml | 18 +- dts/bindings/gpio/nxp,s32-gpio.yaml | 22 +- dts/bindings/gpio/openisa,rv32m1-gpio.yaml | 24 +- dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml | 46 +- dts/bindings/gpio/renesas,rcar-gpio.yaml | 12 +- dts/bindings/gpio/renesas,smartbond-gpio.yaml | 8 +- dts/bindings/gpio/richtek,rt1718s.yaml | 6 +- dts/bindings/gpio/semtech,sx1509b.yaml | 52 +- dts/bindings/gpio/sifive,gpio0.yaml | 12 +- dts/bindings/gpio/silabs,gecko-gpio-port.yaml | 16 +- dts/bindings/gpio/silabs,gecko-gpio.yaml | 14 +- dts/bindings/gpio/snps,creg-gpio.yaml | 26 +- dts/bindings/gpio/snps,designware-gpio.yaml | 8 +- dts/bindings/gpio/st,stm32-gpio.yaml | 12 +- dts/bindings/gpio/st,stmpe1600.yaml | 4 +- dts/bindings/gpio/telink,b91-gpio.yaml | 8 +- dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml | 12 +- dts/bindings/gpio/ti,cc32xx-gpio.yaml | 12 +- dts/bindings/gpio/ti,lmp90xxx-gpio.yaml | 4 +- dts/bindings/gpio/ti,sn74hc595.yaml | 22 +- dts/bindings/gpio/ti,stellaris-gpio.yaml | 12 +- dts/bindings/gpio/ti,tca6424a.yaml | 22 +- dts/bindings/gpio/ti,tca9538.yaml | 24 +- dts/bindings/gpio/xlnx,ps-gpio-bank.yaml | 12 +- dts/bindings/gpio/xlnx,ps-gpio.yaml | 8 +- .../gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml | 4 +- dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml | 120 ++-- dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml | 10 +- dts/bindings/gpio/zephyr,gpio-emul.yaml | 32 +- dts/bindings/hda/intel,hda-dai.yaml | 4 +- dts/bindings/hwinfo/atmel,sam4l-uid.yaml | 4 +- dts/bindings/hwinfo/cypress,psoc6-uid.yaml | 4 +- dts/bindings/hwinfo/litex,dna0.yaml | 4 +- dts/bindings/hwinfo/microchip,xec-ecs.yaml | 4 +- dts/bindings/hwinfo/nxp,lpc-uid.yaml | 4 +- dts/bindings/i2c/altr,nios2-i2c.yaml | 8 +- dts/bindings/i2c/andestech,atciic100.yaml | 10 +- dts/bindings/i2c/arm,versatile-i2c.yaml | 4 +- dts/bindings/i2c/atmel,sam-i2c-twi.yaml | 20 +- dts/bindings/i2c/atmel,sam-i2c-twihs.yaml | 20 +- dts/bindings/i2c/atmel,sam-i2c-twim.yaml | 326 ++++----- dts/bindings/i2c/atmel,sam0-i2c.yaml | 46 +- dts/bindings/i2c/espressif,esp32-i2c.yaml | 78 +- dts/bindings/i2c/fsl,imx21-i2c.yaml | 16 +- dts/bindings/i2c/gpio-i2c.yaml | 16 +- dts/bindings/i2c/i2c-controller.yaml | 18 +- dts/bindings/i2c/i2c-device.yaml | 6 +- dts/bindings/i2c/ite,common-i2c.yaml | 96 +-- dts/bindings/i2c/ite,enhance-i2c.yaml | 18 +- dts/bindings/i2c/ite,it8xxx2-i2c.yaml | 10 +- dts/bindings/i2c/litex,i2c.yaml | 4 +- dts/bindings/i2c/microchip,xec-i2c-v2.yaml | 36 +- dts/bindings/i2c/microchip,xec-i2c.yaml | 74 +- dts/bindings/i2c/nordic,nrf-twi-common.yaml | 50 +- dts/bindings/i2c/nordic,nrf-twim.yaml | 66 +- dts/bindings/i2c/nordic,nrf-twis.yaml | 12 +- dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml | 8 +- dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml | 28 +- dts/bindings/i2c/nxp,imx-lpi2c.yaml | 42 +- dts/bindings/i2c/nxp,kinetis-i2c.yaml | 14 +- dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml | 20 +- dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml | 8 +- dts/bindings/i2c/renesas,rcar-i2c.yaml | 12 +- dts/bindings/i2c/sifive,i2c0.yaml | 4 +- dts/bindings/i2c/silabs,gecko-i2c.yaml | 28 +- dts/bindings/i2c/snps,designware-i2c.yaml | 4 +- dts/bindings/i2c/st,stm32-i2c-v1.yaml | 16 +- dts/bindings/i2c/st,stm32-i2c-v2.yaml | 52 +- dts/bindings/i2c/telink,b91-i2c.yaml | 10 +- dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml | 8 +- dts/bindings/i2c/ti,cc32xx-i2c.yaml | 8 +- .../i2c/zephyr,i2c-emul-controller.yaml | 4 +- dts/bindings/i2s/i2s-controller.yaml | 12 +- dts/bindings/i2s/i2s-device.yaml | 4 +- dts/bindings/i2s/intel,cavs-i2s.yaml | 20 +- dts/bindings/i2s/intel,ssp-dai.yaml | 20 +- dts/bindings/i2s/intel,ssp-sspbase.yaml | 4 +- dts/bindings/i2s/litex,i2s.yaml | 10 +- dts/bindings/i2s/nordic,nrf-i2s.yaml | 166 ++--- dts/bindings/i2s/nxp,mcux-i2s.yaml | 104 +-- dts/bindings/i2s/st,stm32-i2s.yaml | 24 +- dts/bindings/i3c/cdns,i3c.yaml | 16 +- dts/bindings/i3c/i3c-controller.yaml | 36 +- dts/bindings/i3c/i3c-device.yaml | 106 +-- dts/bindings/i3c/nxp,mcux-i3c.yaml | 52 +- dts/bindings/ieee802154/atmel,rf2xx.yaml | 234 +++--- dts/bindings/ieee802154/decawave,dw1000.yaml | 50 +- dts/bindings/ieee802154/nxp,mcr20a.yaml | 28 +- dts/bindings/ieee802154/telink,b91-zb.yaml | 8 +- dts/bindings/ieee802154/ti,cc1200.yaml | 6 +- dts/bindings/ieee802154/ti,cc2520.yaml | 36 +- dts/bindings/iio/adc/nuvoton,npcx-adc.yaml | 42 +- dts/bindings/iio/adc/nxp,lpc-lpadc.yaml | 88 +-- dts/bindings/input/gpio-keys.yaml | 36 +- .../interrupt-controller/arm,gic-v3-its.yaml | 4 +- .../interrupt-controller/arm,gic.yaml | 4 +- .../interrupt-controller/arm,v6m-nvic.yaml | 16 +- .../interrupt-controller/arm,v7m-nvic.yaml | 16 +- .../interrupt-controller/arm,v8.1m-nvic.yaml | 16 +- .../interrupt-controller/arm,v8m-nvic.yaml | 16 +- .../cdns,xtensa-core-intc.yaml | 4 +- .../cypress,psoc6-intmux-ch.yaml | 4 +- .../cypress,psoc6-intmux.yaml | 2 +- .../espressif,esp32-intc.yaml | 2 +- .../interrupt-controller/gaisler,irqmp.yaml | 14 +- .../interrupt-controller/intel,ace-intc.yaml | 12 +- .../interrupt-controller/intel,cavs-intc.yaml | 6 +- .../interrupt-controller/intel,ioapic.yaml | 4 +- .../interrupt-controller/intel,vt-d.yaml | 4 +- .../interrupt-controller.yaml | 16 +- .../ite,it8xxx2-intc.yaml | 2 +- .../ite,it8xxx2-wuc-map.yaml | 10 +- .../microchip,xec-ecia-girq.yaml | 26 +- .../microchip,xec-ecia.yaml | 20 +- .../interrupt-controller/mti,cpu-intc.yaml | 2 +- .../interrupt-controller/nuclei,eclic.yaml | 4 +- .../nuvoton,npcx-miwu-int-map.yaml | 42 +- .../nuvoton,npcx-miwu-wui-map.yaml | 10 +- .../nuvoton,npcx-miwu.yaml | 16 +- .../openisa,rv32m1-event-unit.yaml | 4 +- .../openisa,rv32m1-intmux-ch.yaml | 4 +- .../openisa,rv32m1-intmux.yaml | 2 +- .../interrupt-controller/riscv,cpu-intc.yaml | 2 +- .../interrupt-controller/riscv,plic0.yaml | 10 +- .../interrupt-controller/shared-irq.yaml | 2 +- .../sifive,plic-1.0.0.yaml | 8 +- .../interrupt-controller/snps,arcv2-intc.yaml | 4 +- .../snps,designware-intc.yaml | 12 +- .../interrupt-controller/swerv,pic.yaml | 8 +- .../interrupt-controller/vexriscv-intc0.yaml | 10 +- dts/bindings/ipm/nordic,nrf-ipc.yaml | 8 +- dts/bindings/ipm/nxp,lpc-mailbox.yaml | 4 +- dts/bindings/kscan/focaltech,ft5336.yaml | 4 +- dts/bindings/kscan/goodix,gt911.yaml | 8 +- dts/bindings/kscan/hynitron,cst816s.yaml | 24 +- dts/bindings/kscan/ite,it8xxx2-kscan.yaml | 64 +- dts/bindings/kscan/microchip,cap1203.yaml | 4 +- dts/bindings/kscan/microchip,xec-kscan.yaml | 36 +- dts/bindings/kscan/nuvoton,npcx-kscan.yaml | 106 +-- dts/bindings/led/gpio-leds.yaml | 22 +- dts/bindings/led/holtek,ht16k33.yaml | 6 +- dts/bindings/led/led-controller.yaml | 48 +- dts/bindings/led/microchip,xec-bbled.yaml | 32 +- dts/bindings/led/pwm-leds.yaml | 22 +- dts/bindings/led/ti,lp503x.yaml | 32 +- dts/bindings/lora/semtech,sx1261.yaml | 12 +- dts/bindings/lora/semtech,sx1262.yaml | 12 +- dts/bindings/lora/semtech,sx126x-base.yaml | 108 +-- dts/bindings/lora/semtech,sx127x-base.yaml | 112 +-- .../lora/st,stm32wl-subghz-radio.yaml | 8 +- dts/bindings/mbox/mailbox-controller.yaml | 8 +- dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml | 20 +- dts/bindings/mdio/atmel,sam-mdio.yaml | 4 +- dts/bindings/mdio/espressif,esp32-mdio.yaml | 4 +- dts/bindings/mdio/mdio-controller.yaml | 26 +- .../memory-controllers/ite,it8xxx2-bbram.yaml | 4 +- .../microchip,xec-bbram.yaml | 4 +- .../nuvoton,npcx-bbram.yaml | 4 +- .../memory-controllers/nxp,imx-semc.yaml | 8 +- .../memory-controllers/st,stm32-bbram.yaml | 8 +- .../memory-controllers/st,stm32-fmc.yaml | 16 +- .../memory-controllers/st,stm32h7-fmc.yaml | 30 +- .../memory-controllers/zephyr,bbram-emul.yaml | 8 +- dts/bindings/mfd/gd,gd32-rcu.yaml | 4 +- dts/bindings/mfd/nordic,npm6001.yaml | 4 +- dts/bindings/mhu/arm,mhu.yaml | 8 +- dts/bindings/mipi-dsi/mipi-dsi-device.yaml | 24 +- dts/bindings/mipi-dsi/mipi-dsi-host.yaml | 12 +- dts/bindings/mipi-dsi/nxp,imx-mipi-dsi.yaml | 106 +-- .../misc/nuvoton,npcx-booter-variant.yaml | 10 +- dts/bindings/misc/nuvoton,npcx-soc-id.yaml | 32 +- dts/bindings/misc/skyworks,sky13351.yaml | 16 +- dts/bindings/misc/snps,arc-iot-sysconf.yaml | 4 +- dts/bindings/misc/zephyr,flash-disk.yaml | 50 +- dts/bindings/misc/zephyr,modbus-serial.yaml | 24 +- dts/bindings/mm/intel,adsp-imr.yaml | 10 +- dts/bindings/mm/intel,adsp-mtl-tlb.yaml | 24 +- dts/bindings/mm/intel,adsp-tlb.yaml | 24 +- dts/bindings/mmc/st,stm32-sdmmc.yaml | 98 +-- dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml | 14 +- dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml | 12 +- dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml | 12 +- dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml | 12 +- dts/bindings/modem/openisa,rv32m1-genfsk.yaml | 8 +- dts/bindings/modem/quectel,bg9x.yaml | 20 +- dts/bindings/modem/swir,hl7800.yaml | 52 +- dts/bindings/modem/u-blox,sara-r4.yaml | 14 +- dts/bindings/modem/wnc,m14a2a.yaml | 36 +- dts/bindings/mtd/atmel,at2x-base.yaml | 38 +- dts/bindings/mtd/eeprom-base.yaml | 12 +- dts/bindings/mtd/fixed-partitions.yaml | 38 +- .../mtd/infineon,xmc4xxx-nv-flash.yaml | 22 +- dts/bindings/mtd/microchip,xec-eeprom.yaml | 24 +- dts/bindings/mtd/nxp,imx-flexspi-device.yaml | 148 ++-- dts/bindings/mtd/soc-nv-flash.yaml | 12 +- dts/bindings/mtd/st,stm32-eeprom.yaml | 4 +- dts/bindings/mtd/st,stm32-nv-flash.yaml | 8 +- dts/bindings/mtd/zephyr,emu-eeprom.yaml | 38 +- dts/bindings/mtd/zephyr,fake-eeprom.yaml | 4 +- dts/bindings/mtd/zephyr,sim-eeprom.yaml | 4 +- .../wireless/generic-fem-two-ctrl-pins.yaml | 62 +- .../net/wireless/nordic,nrf-nfct.yaml | 8 +- .../net/wireless/nordic,nrf-radio.yaml | 232 +++--- .../net/wireless/nordic,nrf21540-fem.yaml | 138 ++-- dts/bindings/neural_net/intel,gna.yaml | 12 +- dts/bindings/ospi/st,stm32-ospi.yaml | 88 +-- .../pcie/endpoint/brcm,iproc-pcie-ep.yaml | 12 +- .../pcie/host/pci-host-ecam-generic.yaml | 34 +- dts/bindings/pcie/host/pcie-controller.yaml | 8 +- dts/bindings/pcie/host/pcie-device.yaml | 12 +- dts/bindings/peci/ite,it8xxx2-peci.yaml | 8 +- dts/bindings/peci/microchip,xec-peci.yaml | 24 +- dts/bindings/peci/nuvoton,npcx-peci.yaml | 8 +- dts/bindings/peci/peci.yaml | 16 +- dts/bindings/phy/can-transceiver-gpio.yaml | 24 +- dts/bindings/phy/can-transceiver.yaml | 14 +- dts/bindings/phy/phy-controller.yaml | 12 +- dts/bindings/phy/st,stm32-usbphyc.yaml | 8 +- dts/bindings/phy/usb-nop-xceiv.yaml | 4 +- dts/bindings/phy/usb-ulpi-phy.yaml | 14 +- dts/bindings/pinctrl/atmel,sam-pinctrl.yaml | 12 +- dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml | 12 +- dts/bindings/pinctrl/atmel,sam0-pinmux.yaml | 4 +- .../pinctrl/cypress,psoc6-pinctrl.yaml | 22 +- .../pinctrl/infineon,xmc4xxx-pinctrl.yaml | 114 +-- .../pinctrl/ite,it8xxx2-pinctrl-func.yaml | 36 +- dts/bindings/pinctrl/ite,it8xxx2-pinctrl.yaml | 58 +- .../pinctrl/microchip,xec-pinctrl.yaml | 112 +-- .../pinctrl/microchip,xec-pinmux.yaml | 22 +- .../pinctrl/nuvoton,npcx-lvolctrl-conf.yaml | 12 +- .../pinctrl/nuvoton,npcx-pinctrl-conf.yaml | 12 +- .../pinctrl/nuvoton,npcx-pinctrl-def.yaml | 8 +- .../pinctrl/nuvoton,npcx-pinctrl.yaml | 102 +-- dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml | 32 +- .../pinctrl/nuvoton,numicro-pinctrl.yaml | 66 +- dts/bindings/pinctrl/nxp,imx-gpr.yaml | 4 +- dts/bindings/pinctrl/nxp,imx-iomuxc.yaml | 6 +- dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml | 8 +- .../pinctrl/nxp,lpc-iocon-pinctrl.yaml | 12 +- dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml | 4 +- dts/bindings/pinctrl/nxp,lpc-iocon.yaml | 4 +- dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml | 14 +- .../pinctrl/openisa,rv32m1-pinmux.yaml | 8 +- dts/bindings/pinctrl/renesas,rcar-pfc.yaml | 4 +- dts/bindings/pinctrl/sifive,pinctrl.yaml | 4 +- dts/bindings/pinctrl/st,stm32-pinctrl.yaml | 158 ++-- dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml | 182 ++--- dts/bindings/pinctrl/telink,b91-pinctrl.yaml | 50 +- .../pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml | 4 +- .../power-domain/intel,adsp-power-domain.yaml | 16 +- dts/bindings/power/nordic,nrf-power.yaml | 8 +- dts/bindings/power/nordic,nrf-regulators.yaml | 4 +- dts/bindings/power/nordic,nrf-usbreg.yaml | 8 +- dts/bindings/power/nordic,nrf-vmc.yaml | 4 +- dts/bindings/power/telink,b91-power.yaml | 30 +- dts/bindings/power/zephyr,power-state.yaml | 50 +- dts/bindings/ps2/microchip,xec-ps2.yaml | 28 +- .../ps2/nuvoton,npcx-ps2-channel.yaml | 16 +- dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml | 12 +- dts/bindings/ps2/ps2.yaml | 16 +- dts/bindings/pwm/atmel,sam-pwm.yaml | 42 +- dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml | 6 +- dts/bindings/pwm/espressif,esp32-ledc.yaml | 6 +- dts/bindings/pwm/fsl,imx27-pwm.yaml | 28 +- dts/bindings/pwm/ite,it8xxx2-pwm.yaml | 86 +-- dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml | 4 +- dts/bindings/pwm/litex,pwm.yaml | 8 +- dts/bindings/pwm/microchip,xec-pwm.yaml | 20 +- dts/bindings/pwm/nordic,nrf-pwm.yaml | 204 +++--- dts/bindings/pwm/nordic,nrf-sw-pwm.yaml | 100 +-- dts/bindings/pwm/nuvoton,npcx-pwm.yaml | 48 +- dts/bindings/pwm/nxp,flexpwm.yaml | 8 +- dts/bindings/pwm/nxp,imx-pwm.yaml | 54 +- dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml | 10 +- dts/bindings/pwm/nxp,kinetis-pwt.yaml | 44 +- dts/bindings/pwm/nxp,kinetis-tpm.yaml | 18 +- dts/bindings/pwm/nxp,sctimer-pwm.yaml | 30 +- dts/bindings/pwm/openisa,rv32m1-tpm.yaml | 12 +- dts/bindings/pwm/pwm-controller.yaml | 8 +- dts/bindings/pwm/raspberrypi,pico-pwm.yaml | 188 ++--- dts/bindings/pwm/renesas,pwm-rcar.yaml | 4 +- dts/bindings/pwm/sifive,pwm0.yaml | 20 +- dts/bindings/pwm/silabs,gecko-pwm.yaml | 44 +- dts/bindings/pwm/st,stm32-pwm.yaml | 26 +- dts/bindings/pwm/telink,b91-pwm.yaml | 88 +-- .../pwm/xlnx,xps-timer-1.00.a-pwm.yaml | 16 +- dts/bindings/qspi/altr,nios2-qspi.yaml | 4 +- dts/bindings/qspi/st,stm32-qspi.yaml | 56 +- dts/bindings/regulator/nxp,pca9420.yaml | 58 +- .../reserved-memory/memory-region.yaml | 12 +- dts/bindings/reset/aspeed,ast10x0-reset.yaml | 4 +- dts/bindings/reset/gd,gd32-rctl.yaml | 4 +- .../reset/raspberrypi,pico-reset.yaml | 20 +- dts/bindings/reset/reset-controller.yaml | 8 +- dts/bindings/reset/st,stm32-rcc-rctl.yaml | 16 +- dts/bindings/riscv/openisa,rv32m1-pcc.yaml | 8 +- dts/bindings/riscv/sifive-common.yaml | 6 +- dts/bindings/rng/atmel,sam-trng.yaml | 16 +- dts/bindings/rng/espressif,esp32-trng.yaml | 4 +- dts/bindings/rng/litex,prbs.yaml | 4 +- dts/bindings/rng/neorv32-trng.yaml | 16 +- dts/bindings/rng/nordic,nrf-rng.yaml | 8 +- dts/bindings/rng/nxp,css-v2.yaml | 4 +- dts/bindings/rng/nxp,imx-caam.yaml | 8 +- dts/bindings/rng/nxp,kinetis-rnga.yaml | 8 +- dts/bindings/rng/nxp,kinetis-trng.yaml | 8 +- dts/bindings/rng/nxp,lpc-rng.yaml | 4 +- dts/bindings/rng/openisa,rv32m1-trng.yaml | 8 +- dts/bindings/rng/silabs,gecko-trng.yaml | 8 +- dts/bindings/rng/st,stm32-rng.yaml | 60 +- dts/bindings/rng/telink,b91-trng.yaml | 4 +- dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml | 8 +- dts/bindings/rtc/atmel,sam0-rtc.yaml | 16 +- dts/bindings/rtc/microchip,xec-timer.yaml | 56 +- dts/bindings/rtc/nordic,nrf-rtc.yaml | 50 +- dts/bindings/rtc/nxp,kinetis-lptmr.yaml | 32 +- dts/bindings/rtc/nxp,kinetis-pit.yaml | 20 +- dts/bindings/rtc/nxp,kinetis-rtc.yaml | 4 +- dts/bindings/rtc/nxp,lpc-rtc.yaml | 4 +- dts/bindings/rtc/rtc.yaml | 16 +- dts/bindings/rtc/silabs,gecko-rtcc.yaml | 4 +- dts/bindings/rtc/silabs,gecko-stimer.yaml | 4 +- dts/bindings/rtc/st,stm32-rtc.yaml | 4 +- dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml | 4 +- dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml | 102 +-- dts/bindings/sdhc/nxp,imx-usdhc.yaml | 2 +- dts/bindings/sensor/adi,adt7420.yaml | 10 +- dts/bindings/sensor/adi,adxl362.yaml | 34 +- dts/bindings/sensor/adi,adxl372-common.yaml | 100 +-- dts/bindings/sensor/adi,adxl372-i2c.yaml | 12 +- dts/bindings/sensor/adi,adxl372-spi.yaml | 12 +- dts/bindings/sensor/ams,as6212.yaml | 10 +- dts/bindings/sensor/ams,ccs811.yaml | 32 +- dts/bindings/sensor/atmel,sam-tc-qdec.yaml | 20 +- dts/bindings/sensor/avago,apds9960.yaml | 14 +- dts/bindings/sensor/bosch,bmc150_magn.yaml | 4 +- dts/bindings/sensor/bosch,bmg160.yaml | 4 +- dts/bindings/sensor/bosch,bmi160.yaml | 12 +- dts/bindings/sensor/bosch,bmp388.yaml | 188 ++--- dts/bindings/sensor/espressif,esp32-temp.yaml | 28 +- dts/bindings/sensor/honeywell,hmc5883l.yaml | 12 +- dts/bindings/sensor/honeywell,sm351lt.yaml | 8 +- dts/bindings/sensor/hzgrow,r502a.yaml | 36 +- dts/bindings/sensor/invensense,icm42605.yaml | 140 ++-- dts/bindings/sensor/invensense,icm42670.yaml | 130 ++-- dts/bindings/sensor/invensense,icp10125.yaml | 36 +- dts/bindings/sensor/invensense,mpu6050.yaml | 12 +- dts/bindings/sensor/invensense,mpu9250.yaml | 134 ++-- dts/bindings/sensor/isil,isl29035.yaml | 12 +- dts/bindings/sensor/lm77.yaml | 40 +- dts/bindings/sensor/maxim,ds18b20.yaml | 12 +- dts/bindings/sensor/maxim,max17055.yaml | 70 +- dts/bindings/sensor/maxim,max17262.yaml | 68 +- dts/bindings/sensor/maxim,max44009.yaml | 4 +- dts/bindings/sensor/microchip,mcp9808.yaml | 36 +- dts/bindings/sensor/nordic,nrf-qdec.yaml | 120 ++-- dts/bindings/sensor/nordic,nrf-temp.yaml | 8 +- dts/bindings/sensor/nuvoton,adc-cmp.yaml | 34 +- dts/bindings/sensor/nxp,fxas21002-common.yaml | 42 +- dts/bindings/sensor/nxp,fxos8700-common.yaml | 268 +++---- dts/bindings/sensor/nxp,kinetis-acmp.yaml | 92 +-- .../sensor/nxp,kinetis-temperature.yaml | 64 +- dts/bindings/sensor/panasonic,amg88xx.yaml | 14 +- dts/bindings/sensor/semtech,sx9500.yaml | 10 +- dts/bindings/sensor/sensirion,sgp40.yaml | 10 +- dts/bindings/sensor/sensirion,sht3xd.yaml | 14 +- dts/bindings/sensor/sensirion,sht4x.yaml | 24 +- dts/bindings/sensor/sensirion,shtcx.yaml | 8 +- dts/bindings/sensor/st,hts221-common.yaml | 12 +- dts/bindings/sensor/st,iis2dh-i2c.yaml | 12 +- dts/bindings/sensor/st,iis2dh-spi.yaml | 12 +- dts/bindings/sensor/st,iis2dlpc-common.yaml | 206 +++--- dts/bindings/sensor/st,iis2iclx-common.yaml | 88 +-- dts/bindings/sensor/st,iis2mdc-i2c.yaml | 12 +- dts/bindings/sensor/st,iis2mdc-spi.yaml | 12 +- dts/bindings/sensor/st,iis3dhhc-spi.yaml | 12 +- dts/bindings/sensor/st,ism330dhcx-common.yaml | 228 +++--- dts/bindings/sensor/st,lis2dh-common.yaml | 86 +-- dts/bindings/sensor/st,lis2ds12-common.yaml | 104 +-- dts/bindings/sensor/st,lis2dw12-common.yaml | 484 ++++++------- dts/bindings/sensor/st,lis2mdl-common.yaml | 40 +- dts/bindings/sensor/st,lis3mdl-magn.yaml | 12 +- dts/bindings/sensor/st,lps22hh-common.yaml | 44 +- dts/bindings/sensor/st,lsm6dsl-i2c.yaml | 6 +- dts/bindings/sensor/st,lsm6dsl-spi.yaml | 6 +- dts/bindings/sensor/st,lsm6dso-common.yaml | 200 +++--- dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml | 4 +- dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml | 4 +- dts/bindings/sensor/st,stm32-qdec.yaml | 116 +-- dts/bindings/sensor/st,stm32-temp-cal.yaml | 86 +-- dts/bindings/sensor/st,stm32-temp-common.yaml | 6 +- dts/bindings/sensor/st,stm32-temp.yaml | 38 +- dts/bindings/sensor/st,stm32-vbat.yaml | 14 +- dts/bindings/sensor/st,stts751-i2c.yaml | 12 +- dts/bindings/sensor/st,vl53l0x.yaml | 4 +- dts/bindings/sensor/ti,bq274xx.yaml | 68 +- dts/bindings/sensor/ti,fdc2x1x.yaml | 422 +++++------ dts/bindings/sensor/ti,hdc.yaml | 12 +- dts/bindings/sensor/ti,hdc20xx.yaml | 12 +- dts/bindings/sensor/ti,ina219.yaml | 214 +++--- dts/bindings/sensor/ti,ina230.yaml | 20 +- dts/bindings/sensor/ti,ina237.yaml | 18 +- dts/bindings/sensor/ti,ina23x-common.yaml | 70 +- dts/bindings/sensor/ti,tmp007.yaml | 10 +- dts/bindings/sensor/ti,tmp108.yaml | 10 +- dts/bindings/sensor/vishay,vcnl4040.yaml | 130 ++-- dts/bindings/sensor/we,wsen-hids-common.yaml | 30 +- dts/bindings/sensor/we,wsen-itds.yaml | 56 +- dts/bindings/serial/altr,jtag-uart.yaml | 4 +- dts/bindings/serial/arm,cmsdk-uart.yaml | 8 +- dts/bindings/serial/arm,pl011.yaml | 8 +- dts/bindings/serial/arm,sbsa-uart.yaml | 6 +- dts/bindings/serial/atmel,sam-uart.yaml | 20 +- dts/bindings/serial/atmel,sam-usart.yaml | 20 +- dts/bindings/serial/atmel,sam0-uart.yaml | 68 +- dts/bindings/serial/cdns,uart.yaml | 28 +- dts/bindings/serial/cypress,psoc6-uart.yaml | 36 +- dts/bindings/serial/espressif,esp32-uart.yaml | 12 +- dts/bindings/serial/gaisler,apbuart.yaml | 4 +- dts/bindings/serial/gd,gd32-usart.yaml | 16 +- .../serial/infineon,xmc4xxx-uart.yaml | 134 ++-- dts/bindings/serial/ite,it8xxx2-uart.yaml | 34 +- dts/bindings/serial/litex,uart0.yaml | 8 +- dts/bindings/serial/microchip,xec-uart.yaml | 40 +- dts/bindings/serial/microsemi,coreuart.yaml | 4 +- dts/bindings/serial/neorv32-uart.yaml | 26 +- .../serial/nordic,nrf-uart-common.yaml | 204 +++--- dts/bindings/serial/ns16550.yaml | 20 +- dts/bindings/serial/nuvoton,npcx-uart.yaml | 30 +- dts/bindings/serial/nuvoton,numicro-uart.yaml | 8 +- dts/bindings/serial/nxp,imx-iuart.yaml | 16 +- dts/bindings/serial/nxp,imx-uart.yaml | 32 +- dts/bindings/serial/nxp,kinetis-lpsci.yaml | 14 +- dts/bindings/serial/nxp,kinetis-lpuart.yaml | 42 +- dts/bindings/serial/nxp,kinetis-uart.yaml | 18 +- dts/bindings/serial/nxp,lpc11u6x-uart.yaml | 20 +- dts/bindings/serial/nxp,s32-linflexd.yaml | 16 +- .../serial/openisa,rv32m1-lpuart.yaml | 8 +- .../serial/quicklogic,usbserialport_s3b.yaml | 4 +- .../serial/raspberrypi,pico-uart.yaml | 8 +- dts/bindings/serial/renesas,rcar-scif.yaml | 8 +- .../serial/renesas,smartbond-uart.yaml | 58 +- dts/bindings/serial/segger,rtt-uart.yaml | 28 +- dts/bindings/serial/sifive,uart0.yaml | 8 +- dts/bindings/serial/silabs,gecko-leuart.yaml | 36 +- dts/bindings/serial/silabs,gecko-uart.yaml | 36 +- dts/bindings/serial/silabs,gecko-usart.yaml | 44 +- dts/bindings/serial/snps,nsim-uart.yaml | 4 +- dts/bindings/serial/st,stm32-uart-base.yaml | 102 +-- dts/bindings/serial/telink,b91-uart.yaml | 14 +- .../serial/ti,cc13xx-cc26xx-uart.yaml | 8 +- dts/bindings/serial/ti,cc32xx-uart.yaml | 8 +- dts/bindings/serial/ti,msp432p4xx-uart.yaml | 8 +- dts/bindings/serial/ti,stellaris-uart.yaml | 8 +- dts/bindings/serial/uart-controller.yaml | 36 +- .../serial/xlnx,xps-uartlite-1.00.a.yaml | 4 +- dts/bindings/serial/xlnx,xuartps.yaml | 4 +- dts/bindings/serial/zephyr,cdc-acm-uart.yaml | 24 +- dts/bindings/spi/andestech.atcspi200.yaml | 4 +- dts/bindings/spi/atmel,sam-spi.yaml | 72 +- dts/bindings/spi/atmel,sam0-spi.yaml | 58 +- dts/bindings/spi/cypress,psoc6-spi.yaml | 48 +- dts/bindings/spi/espressif,esp32-spi.yaml | 88 +-- dts/bindings/spi/ite,it8xxx2-sspi.yaml | 8 +- dts/bindings/spi/litex,spi.yaml | 4 +- dts/bindings/spi/microchip,mpfs-qspi.yaml | 8 +- dts/bindings/spi/microchip,xec-qmspi.yaml | 106 +-- dts/bindings/spi/microchip-xec-qmspi-v2.yaml | 192 ++--- dts/bindings/spi/nordic,nrf-spi-common.yaml | 118 +-- dts/bindings/spi/nordic,nrf-spi.yaml | 12 +- dts/bindings/spi/nordic,nrf-spim.yaml | 74 +- dts/bindings/spi/nordic,nrf-spis.yaml | 28 +- dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml | 8 +- dts/bindings/spi/nxp,imx-flexspi.yaml | 92 +-- dts/bindings/spi/nxp,imx-lpspi.yaml | 52 +- dts/bindings/spi/nxp,kinetis-dspi.yaml | 148 ++-- dts/bindings/spi/nxp,lpc-spi.yaml | 60 +- dts/bindings/spi/opencores,spi-simple.yaml | 4 +- dts/bindings/spi/openisa,rv32m1-lpspi.yaml | 8 +- dts/bindings/spi/sifive,spi0.yaml | 4 +- dts/bindings/spi/silabs,gecko-spi-usart.yaml | 56 +- dts/bindings/spi/snps,designware-spi.yaml | 8 +- dts/bindings/spi/spi-controller.yaml | 98 +-- dts/bindings/spi/spi-device.yaml | 64 +- dts/bindings/spi/st,stm32-spi-common.yaml | 16 +- dts/bindings/spi/st,stm32-spi-subghz.yaml | 12 +- dts/bindings/spi/telink,b91-spi.yaml | 88 +-- dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml | 4 +- dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml | 52 +- dts/bindings/spi/zephyr,spi-bitbang.yaml | 30 +- .../spi/zephyr,spi-emul-controller.yaml | 4 +- dts/bindings/sram/mmio-sram.yaml | 4 +- dts/bindings/sram/sifive,dtim0.yaml | 4 +- dts/bindings/syscon/syscon.yaml | 10 +- dts/bindings/tach/ite,it8xxx2-tach.yaml | 62 +- dts/bindings/tach/microchip,xec-tach.yaml | 40 +- dts/bindings/tach/nuvoton,npcx-tach.yaml | 38 +- dts/bindings/tcpc/st,stm32-ucpd.yaml | 100 +-- dts/bindings/test/vnd,adc-temp-sensor.yaml | 28 +- dts/bindings/test/vnd,adc.yaml | 6 +- dts/bindings/test/vnd,busy-sim.yaml | 18 +- dts/bindings/test/vnd,clock.yaml | 4 +- dts/bindings/test/vnd,dma.yaml | 12 +- dts/bindings/test/vnd,gpio-device.yaml | 12 +- .../test/vnd,gpio-expander-common.yaml | 8 +- dts/bindings/test/vnd,gpio-expander-i2c.yaml | 4 +- dts/bindings/test/vnd,gpio-one-cell.yaml | 8 +- dts/bindings/test/vnd,gpio.yaml | 8 +- dts/bindings/test/vnd,i2c-device.yaml | 4 +- dts/bindings/test/vnd,i2c.yaml | 4 +- dts/bindings/test/vnd,i3c-device.yaml | 4 +- dts/bindings/test/vnd,i3c-i2c-device.yaml | 4 +- dts/bindings/test/vnd,i3c.yaml | 4 +- dts/bindings/test/vnd,intc.yaml | 8 +- dts/bindings/test/vnd,interrupt-holder.yaml | 8 +- dts/bindings/test/vnd,pwm.yaml | 8 +- dts/bindings/test/vnd,reg-holder.yaml | 12 +- dts/bindings/test/vnd,reset.yaml | 10 +- dts/bindings/test/vnd,serial.yaml | 14 +- dts/bindings/test/vnd,spi-device.yaml | 4 +- dts/bindings/test/vnd,spi.yaml | 4 +- dts/bindings/timer/andestech,atcpit100.yaml | 58 +- .../timer/andestech,machine-timer.yaml | 8 +- dts/bindings/timer/arm,armv6m-systick.yaml | 4 +- dts/bindings/timer/arm,armv7m-systick.yaml | 4 +- dts/bindings/timer/arm,armv8-timer.yaml | 4 +- dts/bindings/timer/arm,armv8.1m-systick.yaml | 4 +- dts/bindings/timer/arm,armv8m-systick.yaml | 4 +- dts/bindings/timer/arm,cmsdk-dtimer.yaml | 8 +- dts/bindings/timer/arm,cmsdk-timer.yaml | 8 +- dts/bindings/timer/atmel,sam-tc.yaml | 104 +-- dts/bindings/timer/atmel,sam0-tc32.yaml | 4 +- .../timer/espressif,esp32-systimer.yaml | 8 +- dts/bindings/timer/gaisler,gptimer.yaml | 8 +- dts/bindings/timer/intel,adsp-timer.yaml | 10 +- dts/bindings/timer/intel,hpet.yaml | 14 +- dts/bindings/timer/ite,it8xxx2-timer.yaml | 8 +- dts/bindings/timer/litex,timer0.yaml | 8 +- .../timer/microchip,xec-rtos-timer.yaml | 16 +- dts/bindings/timer/neorv32-machine-timer.yaml | 8 +- dts/bindings/timer/nordic,nrf-timer.yaml | 24 +- dts/bindings/timer/nuclei,systimer.yaml | 52 +- .../timer/nuvoton,npcx-itim-timer.yaml | 8 +- dts/bindings/timer/nxp,gpt-hw-timer.yaml | 8 +- dts/bindings/timer/nxp,imx-gpt.yaml | 16 +- dts/bindings/timer/nxp,lpc-ctimer.yaml | 50 +- dts/bindings/timer/nxp,os-timer.yaml | 8 +- dts/bindings/timer/openisa,rv32m1-lptmr.yaml | 8 +- dts/bindings/timer/renesas,rcar-cmt.yaml | 20 +- dts/bindings/timer/sifive,clint0.yaml | 2 +- dts/bindings/timer/silabs,gecko-timer.yaml | 4 +- dts/bindings/timer/st,stm32-lptim.yaml | 8 +- dts/bindings/timer/st,stm32-timers.yaml | 76 +- dts/bindings/timer/telink,machine-timer.yaml | 8 +- dts/bindings/timer/xlnx,ttcps.yaml | 12 +- .../timestamp/intel,ace-timestamp.yaml | 2 +- dts/bindings/usb-c/usb-c-connector.yaml | 244 +++---- dts/bindings/usb-c/zephyr,usb-c-vbus-adc.yaml | 4 +- dts/bindings/usb/atmel,sam-usbc.yaml | 20 +- dts/bindings/usb/atmel,sam-usbhs.yaml | 20 +- dts/bindings/usb/atmel,sam0-usb.yaml | 12 +- dts/bindings/usb/maxim,max3421e_spi.yaml | 28 +- dts/bindings/usb/nordic,nrf-usbd.yaml | 24 +- dts/bindings/usb/nxp,kinetis-usbd.yaml | 8 +- dts/bindings/usb/nxp,mcux-usbd.yaml | 48 +- dts/bindings/usb/raspberrypi,pico-usbd.yaml | 8 +- dts/bindings/usb/snps,designware-usb.yaml | 8 +- dts/bindings/usb/st,stm32-otgfs.yaml | 38 +- dts/bindings/usb/st,stm32-otghs.yaml | 38 +- dts/bindings/usb/st,stm32-usb.yaml | 50 +- dts/bindings/usb/usb-audio-hp.yaml | 8 +- dts/bindings/usb/usb-audio-hs.yaml | 24 +- dts/bindings/usb/usb-audio-mic.yaml | 16 +- dts/bindings/usb/usb-controller.yaml | 30 +- dts/bindings/usb/usb-ep.yaml | 32 +- dts/bindings/video/nxp,imx-csi.yaml | 12 +- dts/bindings/video/ovti,ov2640.yaml | 10 +- dts/bindings/video/ovti,ov7725.yaml | 10 +- dts/bindings/w1/maxim,ds2477_85_common.yaml | 8 +- dts/bindings/w1/w1-master.yaml | 8 +- dts/bindings/w1/w1-slave.yaml | 22 +- dts/bindings/watchdog/arm,cmsdk-watchdog.yaml | 8 +- dts/bindings/watchdog/atmel,sam-watchdog.yaml | 16 +- .../watchdog/atmel,sam0-watchdog.yaml | 8 +- .../watchdog/espressif,esp32-watchdog.yaml | 4 +- dts/bindings/watchdog/gd,gd32-fwdgt.yaml | 36 +- dts/bindings/watchdog/gd,gd32-wwdgt.yaml | 12 +- .../watchdog/ite,it8xxx2-watchdog.yaml | 8 +- .../watchdog/microchip,xec-watchdog.yaml | 24 +- dts/bindings/watchdog/nordic,nrf-wdt.yaml | 8 +- .../watchdog/nuvoton,npcx-watchdog.yaml | 18 +- dts/bindings/watchdog/nxp,imx-wdog.yaml | 8 +- dts/bindings/watchdog/nxp,kinetis-wdog.yaml | 12 +- dts/bindings/watchdog/nxp,kinetis-wdog32.yaml | 28 +- dts/bindings/watchdog/nxp,lpc-wwdt.yaml | 16 +- .../watchdog/raspberrypi,pico-watchdog.yaml | 10 +- dts/bindings/watchdog/sifive,wdt.yaml | 8 +- dts/bindings/watchdog/silabs,gecko-wdog.yaml | 16 +- dts/bindings/watchdog/st,stm32-watchdog.yaml | 4 +- .../watchdog/st,stm32-window-watchdog.yaml | 8 +- dts/bindings/watchdog/ti,cc32xx-watchdog.yaml | 4 +- .../watchdog/zephyr,counter-watchdog.yaml | 10 +- dts/bindings/wifi/atmel,winc1500.yaml | 18 +- dts/bindings/wifi/espressif,esp-at.yaml | 18 +- dts/bindings/wifi/inventek,eswifi-uart.yaml | 10 +- dts/bindings/wifi/inventek,eswifi.yaml | 20 +- dts/bindings/xen/xen,xen-4.15.yaml | 8 +- 913 files changed, 15062 insertions(+), 15062 deletions(-) diff --git a/dts/bindings/adc/adc-controller.yaml b/dts/bindings/adc/adc-controller.yaml index 457c404641ac70..6d25065491fd37 100644 --- a/dts/bindings/adc/adc-controller.yaml +++ b/dts/bindings/adc/adc-controller.yaml @@ -7,142 +7,142 @@ include: base.yaml properties: - "#io-channel-cells": + "#io-channel-cells": + type: int + required: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +child-binding: + description: | + Channel configuration. + + All nodes using this binding must be named "channel", otherwise their + data will not be accessible for the ADC API macros. + + This is based on Linux, documentation: + https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/adc/adc.yaml + + properties: + reg: + type: array + required: true + description: Channel identifier. + + zephyr,gain: + type: string + required: true + description: | + Gain selection: + - ADC_GAIN_1_6: x 1/6 + - ADC_GAIN_1_5: x 1/5 + - ADC_GAIN_1_4: x 1/4 + - ADC_GAIN_1_3: x 1/3 + - ADC_GAIN_2_5: x 2/5 + - ADC_GAIN_1_2: x 1/2 + - ADC_GAIN_2_3: x 2/3 + - ADC_GAIN_4_5: x 4/5 + - ADC_GAIN_1: x 1 + - ADC_GAIN_2: x 2 + - ADC_GAIN_3: x 3 + - ADC_GAIN_4: x 4 + - ADC_GAIN_6: x 6 + - ADC_GAIN_8: x 8 + - ADC_GAIN_12: x 12 + - ADC_GAIN_16: x 16 + - ADC_GAIN_24: x 24 + - ADC_GAIN_32: x 32 + - ADC_GAIN_64: x 64 + - ADC_GAIN_128: x 128 + enum: + - "ADC_GAIN_1_6" + - "ADC_GAIN_1_5" + - "ADC_GAIN_1_4" + - "ADC_GAIN_1_3" + - "ADC_GAIN_2_5" + - "ADC_GAIN_1_2" + - "ADC_GAIN_2_3" + - "ADC_GAIN_4_5" + - "ADC_GAIN_1" + - "ADC_GAIN_2" + - "ADC_GAIN_3" + - "ADC_GAIN_4" + - "ADC_GAIN_6" + - "ADC_GAIN_8" + - "ADC_GAIN_12" + - "ADC_GAIN_16" + - "ADC_GAIN_24" + - "ADC_GAIN_32" + - "ADC_GAIN_64" + - "ADC_GAIN_128" + + zephyr,reference: + type: string + required: true + description: | + Reference selection: + - ADC_REF_VDD_1: VDD + - ADC_REF_VDD_1_2: VDD/2 + - ADC_REF_VDD_1_3: VDD/3 + - ADC_REF_VDD_1_4: VDD/4 + - ADC_REF_INTERNAL: Internal + - ADC_REF_EXTERNAL0: External, input 0 + - ADC_REF_EXTERNAL1: External, input 1 + enum: + - "ADC_REF_VDD_1" + - "ADC_REF_VDD_1_2" + - "ADC_REF_VDD_1_3" + - "ADC_REF_VDD_1_4" + - "ADC_REF_INTERNAL" + - "ADC_REF_EXTERNAL0" + - "ADC_REF_EXTERNAL1" + + zephyr,vref-mv: + type: int + description: | + This property can be used to specify the voltage (in millivolts) + of the reference selected for this channel, so that applications + can get that value if needed for some calculations. + For the internal reference, the voltage can be usually obtained with + a dedicated ADC API call, so there is no need to use this property + in that case, but for other references this property can be useful. + + zephyr,acquisition-time: type: int required: true + description: | + Acquisition time. + Use the ADC_ACQ_TIME macro to compose the value for this property + or pass ADC_ACQ_TIME_DEFAULT to use the default setting for a given + hardware (e.g. when the hardware does not allow to configure the + acquisition time). + + zephyr,input-positive: + type: int + description: | + Positive ADC input. Used only for drivers that select + the ADC_CONFIGURABLE_INPUTS Kconfig option. - "#address-cells": - const: 1 + zephyr,input-negative: + type: int + description: | + Negative ADC input. Used only for drivers that select + the ADC_CONFIGURABLE_INPUTS Kconfig option. + When specified, the channel is to be used in differential input mode, + otherwise, single-ended mode is used. - "#size-cells": - const: 0 + zephyr,resolution: + type: int + description: | + ADC resolution to be used for the channel. -child-binding: - description: | - Channel configuration. - - All nodes using this binding must be named "channel", otherwise their - data will not be accessible for the ADC API macros. - - This is based on Linux, documentation: - https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/adc/adc.yaml - - properties: - reg: - type: array - required: true - description: Channel identifier. - - zephyr,gain: - type: string - required: true - description: | - Gain selection: - - ADC_GAIN_1_6: x 1/6 - - ADC_GAIN_1_5: x 1/5 - - ADC_GAIN_1_4: x 1/4 - - ADC_GAIN_1_3: x 1/3 - - ADC_GAIN_2_5: x 2/5 - - ADC_GAIN_1_2: x 1/2 - - ADC_GAIN_2_3: x 2/3 - - ADC_GAIN_4_5: x 4/5 - - ADC_GAIN_1: x 1 - - ADC_GAIN_2: x 2 - - ADC_GAIN_3: x 3 - - ADC_GAIN_4: x 4 - - ADC_GAIN_6: x 6 - - ADC_GAIN_8: x 8 - - ADC_GAIN_12: x 12 - - ADC_GAIN_16: x 16 - - ADC_GAIN_24: x 24 - - ADC_GAIN_32: x 32 - - ADC_GAIN_64: x 64 - - ADC_GAIN_128: x 128 - enum: - - "ADC_GAIN_1_6" - - "ADC_GAIN_1_5" - - "ADC_GAIN_1_4" - - "ADC_GAIN_1_3" - - "ADC_GAIN_2_5" - - "ADC_GAIN_1_2" - - "ADC_GAIN_2_3" - - "ADC_GAIN_4_5" - - "ADC_GAIN_1" - - "ADC_GAIN_2" - - "ADC_GAIN_3" - - "ADC_GAIN_4" - - "ADC_GAIN_6" - - "ADC_GAIN_8" - - "ADC_GAIN_12" - - "ADC_GAIN_16" - - "ADC_GAIN_24" - - "ADC_GAIN_32" - - "ADC_GAIN_64" - - "ADC_GAIN_128" - - zephyr,reference: - type: string - required: true - description: | - Reference selection: - - ADC_REF_VDD_1: VDD - - ADC_REF_VDD_1_2: VDD/2 - - ADC_REF_VDD_1_3: VDD/3 - - ADC_REF_VDD_1_4: VDD/4 - - ADC_REF_INTERNAL: Internal - - ADC_REF_EXTERNAL0: External, input 0 - - ADC_REF_EXTERNAL1: External, input 1 - enum: - - "ADC_REF_VDD_1" - - "ADC_REF_VDD_1_2" - - "ADC_REF_VDD_1_3" - - "ADC_REF_VDD_1_4" - - "ADC_REF_INTERNAL" - - "ADC_REF_EXTERNAL0" - - "ADC_REF_EXTERNAL1" - - zephyr,vref-mv: - type: int - description: | - This property can be used to specify the voltage (in millivolts) - of the reference selected for this channel, so that applications - can get that value if needed for some calculations. - For the internal reference, the voltage can be usually obtained with - a dedicated ADC API call, so there is no need to use this property - in that case, but for other references this property can be useful. - - zephyr,acquisition-time: - type: int - required: true - description: | - Acquisition time. - Use the ADC_ACQ_TIME macro to compose the value for this property - or pass ADC_ACQ_TIME_DEFAULT to use the default setting for a given - hardware (e.g. when the hardware does not allow to configure the - acquisition time). - - zephyr,input-positive: - type: int - description: | - Positive ADC input. Used only for drivers that select - the ADC_CONFIGURABLE_INPUTS Kconfig option. - - zephyr,input-negative: - type: int - description: | - Negative ADC input. Used only for drivers that select - the ADC_CONFIGURABLE_INPUTS Kconfig option. - When specified, the channel is to be used in differential input mode, - otherwise, single-ended mode is used. - - zephyr,resolution: - type: int - description: | - ADC resolution to be used for the channel. - - zephyr,oversampling: - type: int - description: | - Oversampling setting to be used for the channel. - When specified, each sample is averaged from 2^N conversion results - (where N is the provided value). + zephyr,oversampling: + type: int + description: | + Oversampling setting to be used for the channel. + When specified, each sample is averaged from 2^N conversion results + (where N is the provided value). diff --git a/dts/bindings/adc/arduino,uno-adc.yaml b/dts/bindings/adc/arduino,uno-adc.yaml index 8c7ce9ab5e0fe7..854e640914a4f8 100644 --- a/dts/bindings/adc/arduino,uno-adc.yaml +++ b/dts/bindings/adc/arduino,uno-adc.yaml @@ -16,17 +16,17 @@ compatible: "arduino,uno-adc" include: base.yaml properties: - io-channel-map: - type: compound - required: true + io-channel-map: + type: compound + required: true - io-channel-map-mask: - type: compound + io-channel-map-mask: + type: compound - io-channel-map-pass-thru: - type: compound + io-channel-map-pass-thru: + type: compound - "#io-channel-cells": - type: int - required: true - description: Number of items to expect in an ADC specifier + "#io-channel-cells": + type: int + required: true + description: Number of items to expect in an ADC specifier diff --git a/dts/bindings/adc/atmel,sam-afec.yaml b/dts/bindings/adc/atmel,sam-afec.yaml index d0dc69d4a4f6c8..e2efbea7b947f6 100644 --- a/dts/bindings/adc/atmel,sam-afec.yaml +++ b/dts/bindings/adc/atmel,sam-afec.yaml @@ -3,23 +3,23 @@ description: Atmel SAM family AFEC compatible: "atmel,sam-afec" include: - - name: adc-controller.yaml - - name: pinctrl-device.yaml + - name: adc-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/atmel,sam0-adc.yaml b/dts/bindings/adc/atmel,sam0-adc.yaml index f90f576126f033..e403b2316b6b7f 100644 --- a/dts/bindings/adc/atmel,sam0-adc.yaml +++ b/dts/bindings/adc/atmel,sam0-adc.yaml @@ -6,44 +6,44 @@ description: Atmel SAM0 family ADC compatible: "atmel,sam0-adc" include: - - name: adc-controller.yaml - - name: pinctrl-device.yaml + - name: adc-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - clock-names: - required: true + clock-names: + required: true - gclk: - type: int - required: true - description: generic clock generator source + gclk: + type: int + required: true + description: generic clock generator source - prescaler: - type: int - required: true - description: clock prescaler divisor applied to the generic clock + prescaler: + type: int + required: true + description: clock prescaler divisor applied to the generic clock - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 - calib-offset: - type: int - description: | - bit position offset in NVM SW Calib for start of ADC0 BIASCOMP field. - This property is expected to be set on SAM{D,E}5x family of SoCs. - For ADC0 this should be 0, and for ADC1 this should be 14. - enum: - - 0 - - 14 + calib-offset: + type: int + description: | + bit position offset in NVM SW Calib for start of ADC0 BIASCOMP field. + This property is expected to be set on SAM{D,E}5x family of SoCs. + For ADC0 this should be 0, and for ADC1 this should be 14. + enum: + - 0 + - 14 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/gd,gd32-adc.yaml b/dts/bindings/adc/gd,gd32-adc.yaml index e5415635297534..18a829e3daf3ab 100644 --- a/dts/bindings/adc/gd,gd32-adc.yaml +++ b/dts/bindings/adc/gd,gd32-adc.yaml @@ -19,38 +19,38 @@ compatible: "gd,gd32-adc" include: [adc-controller.yaml, reset-device.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - resets: - required: true + resets: + required: true - clocks: - required: true + clocks: + required: true - rcu-clock-source: - type: int - description: | - Some GD32 ADC have additional clock source, like IRC14M or IRC28M. - This property used to select the clock and related prescaler, valid - values defined at 'dts-bindings/adc/gd32xxx.h' headers. + rcu-clock-source: + type: int + description: | + Some GD32 ADC have additional clock source, like IRC14M or IRC28M. + This property used to select the clock and related prescaler, valid + values defined at 'dts-bindings/adc/gd32xxx.h' headers. - channels: - type: int - description: Number of external channels - required: true + channels: + type: int + description: Number of external channels + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/infineon,xmc4xxx-adc.yaml b/dts/bindings/adc/infineon,xmc4xxx-adc.yaml index 2d0f394bb5bb6d..4d1296b1c71bb9 100644 --- a/dts/bindings/adc/infineon,xmc4xxx-adc.yaml +++ b/dts/bindings/adc/infineon,xmc4xxx-adc.yaml @@ -13,20 +13,20 @@ compatible: "infineon,xmc4xxx-adc" include: adc-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - vref-internal-mv: - type: int - required: true - description: | - This property sets the internal reference voltage (in millivolts). + vref-internal-mv: + type: int + required: true + description: | + This property sets the internal reference voltage (in millivolts). - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/ite,it8xxx2-adc.yaml b/dts/bindings/adc/ite,it8xxx2-adc.yaml index 709b60d0419b53..8bc75d90e35e91 100644 --- a/dts/bindings/adc/ite,it8xxx2-adc.yaml +++ b/dts/bindings/adc/ite,it8xxx2-adc.yaml @@ -8,14 +8,14 @@ compatible: "ite,it8xxx2-adc" include: [adc-controller.yaml, pinctrl-device.yaml] properties: - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/microchip,mcp320x-base.yaml b/dts/bindings/adc/microchip,mcp320x-base.yaml index 8ab984605f2773..c5d80c9a63732b 100644 --- a/dts/bindings/adc/microchip,mcp320x-base.yaml +++ b/dts/bindings/adc/microchip,mcp320x-base.yaml @@ -3,8 +3,8 @@ include: [adc-controller.yaml, spi-device.yaml] properties: - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - channel + - channel diff --git a/dts/bindings/adc/microchip,xec-adc-v2.yaml b/dts/bindings/adc/microchip,xec-adc-v2.yaml index a62ce58b04ed54..38039b7f15455a 100644 --- a/dts/bindings/adc/microchip,xec-adc-v2.yaml +++ b/dts/bindings/adc/microchip,xec-adc-v2.yaml @@ -9,30 +9,30 @@ compatible: "microchip,xec-adc-v2" include: [adc-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 - girqs: - type: array - required: true - description: Array of pairs of GIRQ number and bit position + girqs: + type: array + required: true + description: Array of pairs of GIRQ number and bit position - pcrs: - type: array - required: true - description: ADC PCR register index and bit position + pcrs: + type: array + required: true + description: ADC PCR register index and bit position - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/microchip,xec-adc.yaml b/dts/bindings/adc/microchip,xec-adc.yaml index ead88cec8755f5..81be1734eb7b2b 100644 --- a/dts/bindings/adc/microchip,xec-adc.yaml +++ b/dts/bindings/adc/microchip,xec-adc.yaml @@ -8,25 +8,25 @@ compatible: "microchip,xec-adc" include: [adc-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 - clktime: - type: int - required: true - description: ADC clock high & low time count value <1:255> + clktime: + type: int + required: true + description: ADC clock high & low time count value <1:255> - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/nordic,nrf-adc.yaml b/dts/bindings/adc/nordic,nrf-adc.yaml index bd42c6e248b139..7f96287b657cf6 100644 --- a/dts/bindings/adc/nordic,nrf-adc.yaml +++ b/dts/bindings/adc/nordic,nrf-adc.yaml @@ -8,14 +8,14 @@ compatible: "nordic,nrf-adc" include: adc-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/nordic,nrf-comp.yaml b/dts/bindings/adc/nordic,nrf-comp.yaml index 7ff6483beeef7a..cc964015ba1806 100644 --- a/dts/bindings/adc/nordic,nrf-comp.yaml +++ b/dts/bindings/adc/nordic,nrf-comp.yaml @@ -8,16 +8,16 @@ compatible: "nordic,nrf-comp" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - type: int - const: 1 - required: true + "#io-channel-cells": + type: int + const: 1 + required: true io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/nordic,nrf-lpcomp.yaml b/dts/bindings/adc/nordic,nrf-lpcomp.yaml index 894342ba7f0c02..132b0980ac5a61 100644 --- a/dts/bindings/adc/nordic,nrf-lpcomp.yaml +++ b/dts/bindings/adc/nordic,nrf-lpcomp.yaml @@ -8,16 +8,16 @@ compatible: "nordic,nrf-lpcomp" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - type: int - const: 1 - required: true + "#io-channel-cells": + type: int + const: 1 + required: true io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/nordic,nrf-saadc.yaml b/dts/bindings/adc/nordic,nrf-saadc.yaml index 881d620668cb13..f41cf2c048e870 100644 --- a/dts/bindings/adc/nordic,nrf-saadc.yaml +++ b/dts/bindings/adc/nordic,nrf-saadc.yaml @@ -8,14 +8,14 @@ compatible: "nordic,nrf-saadc" include: adc-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/nxp,kinetis-adc12.yaml b/dts/bindings/adc/nxp,kinetis-adc12.yaml index 7424f5bc6c16e9..e3c9b9024cf91a 100644 --- a/dts/bindings/adc/nxp,kinetis-adc12.yaml +++ b/dts/bindings/adc/nxp,kinetis-adc12.yaml @@ -8,33 +8,33 @@ compatible: "nxp,kinetis-adc12" include: [adc-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clk-source: - type: int - required: true - description: converter clock source + clk-source: + type: int + required: true + description: converter clock source - clk-divider: - type: int - required: true - description: clock divider for the converter + clk-divider: + type: int + required: true + description: clock divider for the converter - alternate-voltage-reference: - type: boolean - description: use alternate voltage reference source + alternate-voltage-reference: + type: boolean + description: use alternate voltage reference source - sample-time: - type: int - required: true - description: sample time in clock cycles + sample-time: + type: int + required: true + description: sample time in clock cycles - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/nxp,kinetis-adc16.yaml b/dts/bindings/adc/nxp,kinetis-adc16.yaml index c27474df4676d8..8f4c5b3f58f559 100644 --- a/dts/bindings/adc/nxp,kinetis-adc16.yaml +++ b/dts/bindings/adc/nxp,kinetis-adc16.yaml @@ -8,49 +8,49 @@ compatible: "nxp,kinetis-adc16" include: ["adc-controller.yaml", "pinctrl-device.yaml"] properties: - reg: - required: true - - channel-mux-b: - type: boolean - description: | - Use alternate set (b instead of a) of ADC channels - - interrupts: - required: true - - periodic-trigger: - type: boolean - description: if periodic trigger enabled - - "#io-channel-cells": - const: 1 - - clk-source: - type: int - description: use alternate clock reference source - - long-sample: - type: int - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - description: long sample mode - - continuous-convert: - type: boolean - description: If use continuous convert - - high-speed: - type: boolean - description: If use high speed - - hw-trigger-src: - type: int - description: hardware trigger source (See ADCxTRGSEL field in user manual for more details) + reg: + required: true + + channel-mux-b: + type: boolean + description: | + Use alternate set (b instead of a) of ADC channels + + interrupts: + required: true + + periodic-trigger: + type: boolean + description: if periodic trigger enabled + + "#io-channel-cells": + const: 1 + + clk-source: + type: int + description: use alternate clock reference source + + long-sample: + type: int + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + description: long sample mode + + continuous-convert: + type: boolean + description: If use continuous convert + + high-speed: + type: boolean + description: If use high speed + + hw-trigger-src: + type: int + description: hardware trigger source (See ADCxTRGSEL field in user manual for more details) io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/raspberrypi,pico-adc.yaml b/dts/bindings/adc/raspberrypi,pico-adc.yaml index 7ed44fad19011e..3fc9236cbb150b 100644 --- a/dts/bindings/adc/raspberrypi,pico-adc.yaml +++ b/dts/bindings/adc/raspberrypi,pico-adc.yaml @@ -8,20 +8,20 @@ compatible: "raspberrypi,pico-adc" include: [adc-controller.yaml, pinctrl-device.yaml, reset-device.yaml] properties: - reg: - required: true + reg: + required: true - vref-mv: - type: int - default: 3300 - description: | - Indicate the reference voltage of the ADC in mV. - Raspberry Pi has one voltage reference. - And it is usually connected to VDD. - In such case, set this property to the VDD (in mV) value. + vref-mv: + type: int + default: 3300 + description: | + Indicate the reference voltage of the ADC in mV. + Raspberry Pi has one voltage reference. + And it is usually connected to VDD. + In such case, set this property to the VDD (in mV) value. - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/st,stm32-adc.yaml b/dts/bindings/adc/st,stm32-adc.yaml index 53e1f8e20b9e9e..66afd7eddcef9e 100644 --- a/dts/bindings/adc/st,stm32-adc.yaml +++ b/dts/bindings/adc/st,stm32-adc.yaml @@ -9,40 +9,40 @@ compatible: "st,stm32-adc" include: [adc-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - vref-mv: - type: int - default: 3300 - description: Indicates the reference voltage of the ADC in mV (on the target board). + vref-mv: + type: int + default: 3300 + description: Indicates the reference voltage of the ADC in mV (on the target board). - has-temp-channel: - type: boolean - description: Indicates if the ADC has a dedicated internal temperature sensor channel. + has-temp-channel: + type: boolean + description: Indicates if the ADC has a dedicated internal temperature sensor channel. - has-vref-channel: - type: boolean - description: Indicates if the ADC has a dedicated internal voltage reference channel. + has-vref-channel: + type: boolean + description: Indicates if the ADC has a dedicated internal voltage reference channel. - has-vbat-channel: - type: boolean - description: Indicates if the ADC has a dedicated internal vbat monitoring channel. + has-vbat-channel: + type: boolean + description: Indicates if the ADC has a dedicated internal vbat monitoring channel. io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/telink,b91-adc.yaml b/dts/bindings/adc/telink,b91-adc.yaml index 4d19c26b189dad..72aa29bb613c14 100644 --- a/dts/bindings/adc/telink,b91-adc.yaml +++ b/dts/bindings/adc/telink,b91-adc.yaml @@ -8,31 +8,31 @@ compatible: "telink,b91-adc" include: adc-controller.yaml properties: - reg: - required: true - - "#io-channel-cells": - const: 1 - - sample-freq: - type: int - required: true - enum: - - 23000 - - 48000 - - 96000 - description: | - This property selects the ADC source frequency: 23 kHz, 48 kHz, or 96 kHz. - - vref-internal-mv: - type: int - required: true - enum: - - 900 - - 1200 - description: | - This property selects the internal reference voltage source (in millivolts). - The external reference source is not supported. + reg: + required: true + + "#io-channel-cells": + const: 1 + + sample-freq: + type: int + required: true + enum: + - 23000 + - 48000 + - 96000 + description: | + This property selects the ADC source frequency: 23 kHz, 48 kHz, or 96 kHz. + + vref-internal-mv: + type: int + required: true + enum: + - 900 + - 1200 + description: | + This property selects the internal reference voltage source (in millivolts). + The external reference source is not supported. io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/ti,ads1119.yaml b/dts/bindings/adc/ti,ads1119.yaml index 1c20cd00c4e6cc..07f9bd0b7b39cf 100644 --- a/dts/bindings/adc/ti,ads1119.yaml +++ b/dts/bindings/adc/ti,ads1119.yaml @@ -8,5 +8,5 @@ compatible: "ti,ads1119" include: [adc-controller.yaml, i2c-device.yaml] properties: - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 diff --git a/dts/bindings/adc/ti,ads1x1x-base.yaml b/dts/bindings/adc/ti,ads1x1x-base.yaml index 87e8f7d88eaac5..e6e28ab1925473 100644 --- a/dts/bindings/adc/ti,ads1x1x-base.yaml +++ b/dts/bindings/adc/ti,ads1x1x-base.yaml @@ -3,8 +3,8 @@ include: [adc-controller.yaml, i2c-device.yaml] properties: - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/ti,cc13xx-cc26xx-adc.yaml b/dts/bindings/adc/ti,cc13xx-cc26xx-adc.yaml index eae2613c1c5115..d1be4170324409 100644 --- a/dts/bindings/adc/ti,cc13xx-cc26xx-adc.yaml +++ b/dts/bindings/adc/ti,cc13xx-cc26xx-adc.yaml @@ -8,14 +8,14 @@ compatible: "ti,cc13xx-cc26xx-adc" include: [adc-controller.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/ti,cc32xx-adc.yaml b/dts/bindings/adc/ti,cc32xx-adc.yaml index 9a8457f32814f1..51e35f04c8d96d 100644 --- a/dts/bindings/adc/ti,cc32xx-adc.yaml +++ b/dts/bindings/adc/ti,cc32xx-adc.yaml @@ -8,14 +8,14 @@ compatible: "ti,cc32xx-adc" include: adc-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/adc/ti,lmp90xxx-base.yaml b/dts/bindings/adc/ti,lmp90xxx-base.yaml index 492d43786a5d41..4225c9b0cc347c 100644 --- a/dts/bindings/adc/ti,lmp90xxx-base.yaml +++ b/dts/bindings/adc/ti,lmp90xxx-base.yaml @@ -5,13 +5,13 @@ include: [adc-controller.yaml, spi-device.yaml] bus: lmp90xxx properties: - drdyb-gpios: - type: phandle-array - description: Data Ready Bar + drdyb-gpios: + type: phandle-array + description: Data Ready Bar - "#io-channel-cells": - const: 2 + "#io-channel-cells": + const: 2 io-channel-cells: - - positive - - negative + - positive + - negative diff --git a/dts/bindings/adc/ti,lmp90xxx-current.yaml b/dts/bindings/adc/ti,lmp90xxx-current.yaml index 98629d8d57c5f8..2bb424bc70c419 100644 --- a/dts/bindings/adc/ti,lmp90xxx-current.yaml +++ b/dts/bindings/adc/ti,lmp90xxx-current.yaml @@ -3,6 +3,6 @@ include: ti,lmp90xxx-base.yaml properties: - rtd-current: - type: int - description: RTD current in microampere + rtd-current: + type: int + description: RTD current in microampere diff --git a/dts/bindings/adc/voltage-divider.yaml b/dts/bindings/adc/voltage-divider.yaml index c29b8756af592a..3a903df3ff317e 100644 --- a/dts/bindings/adc/voltage-divider.yaml +++ b/dts/bindings/adc/voltage-divider.yaml @@ -10,29 +10,29 @@ compatible: "voltage-divider" include: base.yaml properties: - io-channels: - required: true - description: | - Channels available with this divider configuration. - - output-ohms: - type: int - required: true - description: | - Resistance of the lower leg of the voltage divider - - full-ohms: - type: int - description: | - Resistance of the full path through the voltage divider. - - If absent or zero the driver assumes that the upper leg is a - resistance-based sensor. - - power-gpios: - type: phandle-array - description: | - Control power to the voltage divider inputs. - - If present the corresponding GPIO must be set to an active level - to enable the divider input. + io-channels: + required: true + description: | + Channels available with this divider configuration. + + output-ohms: + type: int + required: true + description: | + Resistance of the lower leg of the voltage divider + + full-ohms: + type: int + description: | + Resistance of the full path through the voltage divider. + + If absent or zero the driver assumes that the upper leg is a + resistance-based sensor. + + power-gpios: + type: phandle-array + description: | + Control power to the voltage divider inputs. + + If present the corresponding GPIO must be set to an active level + to enable the divider input. diff --git a/dts/bindings/adc/zephyr,adc-emul.yaml b/dts/bindings/adc/zephyr,adc-emul.yaml index d60dcddb644591..6765cb090cbd7c 100644 --- a/dts/bindings/adc/zephyr,adc-emul.yaml +++ b/dts/bindings/adc/zephyr,adc-emul.yaml @@ -8,38 +8,38 @@ compatible: "zephyr,adc-emul" include: adc-controller.yaml properties: - nchannels: - type: int - required: true - description: Number of emulated ADC channels. Should be in 1-32 range. - - ref-internal-mv: - type: int - default: 0 - description: - Internal reference voltage in mV. If not provided or set to zero, - channel setup with ADC_REF_INTERNAL will fail. - - ref-vdd-mv: - type: int - default: 0 - description: - VDD reference voltage in mV. If not provided or set to zero, - channel setup with ADC_REF_VDD_X will fail. - - ref-external0-mv: - type: int - default: 0 - description: - External 0 reference voltage in mV. If not provided or set to zero, - channel setup with ADC_REF_EXTERNAL0 will fail. - - ref-external1-mv: - type: int - default: 0 - description: - External 1 reference voltage in mV. If not provided or set to zero, - channel setup with ADC_REF_EXTERNAL1 will fail. + nchannels: + type: int + required: true + description: Number of emulated ADC channels. Should be in 1-32 range. + + ref-internal-mv: + type: int + default: 0 + description: + Internal reference voltage in mV. If not provided or set to zero, + channel setup with ADC_REF_INTERNAL will fail. + + ref-vdd-mv: + type: int + default: 0 + description: + VDD reference voltage in mV. If not provided or set to zero, + channel setup with ADC_REF_VDD_X will fail. + + ref-external0-mv: + type: int + default: 0 + description: + External 0 reference voltage in mV. If not provided or set to zero, + channel setup with ADC_REF_EXTERNAL0 will fail. + + ref-external1-mv: + type: int + default: 0 + description: + External 1 reference voltage in mV. If not provided or set to zero, + channel setup with ADC_REF_EXTERNAL1 will fail. io-channel-cells: - - input + - input diff --git a/dts/bindings/alh/intel,alh-dai.yaml b/dts/bindings/alh/intel,alh-dai.yaml index 0eabe3cfe37a2f..627b4b241289c5 100644 --- a/dts/bindings/alh/intel,alh-dai.yaml +++ b/dts/bindings/alh/intel,alh-dai.yaml @@ -9,5 +9,5 @@ compatible: "intel,alh-dai" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arc/arc,dccm.yaml b/dts/bindings/arc/arc,dccm.yaml index 56c58fa93f811b..8c989016a427c0 100644 --- a/dts/bindings/arc/arc,dccm.yaml +++ b/dts/bindings/arc/arc,dccm.yaml @@ -8,5 +8,5 @@ compatible: "arc,dccm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arc/arc,iccm.yaml b/dts/bindings/arc/arc,iccm.yaml index 2bbc85c4682c7a..edf5e846c6190d 100644 --- a/dts/bindings/arc/arc,iccm.yaml +++ b/dts/bindings/arc/arc,iccm.yaml @@ -8,5 +8,5 @@ compatible: "arc,iccm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arc/arc,xccm.yaml b/dts/bindings/arc/arc,xccm.yaml index ea66faa4ef64b3..c43733b6d3ae5a 100644 --- a/dts/bindings/arc/arc,xccm.yaml +++ b/dts/bindings/arc/arc,xccm.yaml @@ -10,5 +10,5 @@ compatible: "arc,xccm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arc/arc,yccm.yaml b/dts/bindings/arc/arc,yccm.yaml index 6ca798e19fc58e..47b3257e0834c6 100644 --- a/dts/bindings/arc/arc,yccm.yaml +++ b/dts/bindings/arc/arc,yccm.yaml @@ -10,5 +10,5 @@ compatible: "arc,yccm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/arm,beetle-syscon.yaml b/dts/bindings/arm/arm,beetle-syscon.yaml index 50e4a7db79e0e7..76ae0784ea2dd9 100644 --- a/dts/bindings/arm/arm,beetle-syscon.yaml +++ b/dts/bindings/arm/arm,beetle-syscon.yaml @@ -8,9 +8,9 @@ compatible: "arm,beetle-syscon" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - required: true - const: 0 + "#clock-cells": + required: true + const: 0 diff --git a/dts/bindings/arm/arm,dtcm.yaml b/dts/bindings/arm/arm,dtcm.yaml index a638085abbe776..84f1c5a8579b18 100644 --- a/dts/bindings/arm/arm,dtcm.yaml +++ b/dts/bindings/arm/arm,dtcm.yaml @@ -7,5 +7,5 @@ compatible: "arm,dtcm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/arm,ethos-u.yaml b/dts/bindings/arm/arm,ethos-u.yaml index c411f50b1be0bd..a98ec1f6896fb2 100644 --- a/dts/bindings/arm/arm,ethos-u.yaml +++ b/dts/bindings/arm/arm,ethos-u.yaml @@ -17,16 +17,16 @@ compatible: "arm,ethos-u" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - secure-enable: - type: boolean - description: Configure Ethos-U NPU to operate in secure- or non-secure mode + secure-enable: + type: boolean + description: Configure Ethos-U NPU to operate in secure- or non-secure mode - privilege-enable: - type: boolean - description: Configure Ethos-U NPU to operate in privileged- or non-privileged mode + privilege-enable: + type: boolean + description: Configure Ethos-U NPU to operate in privileged- or non-privileged mode diff --git a/dts/bindings/arm/arm,itcm.yaml b/dts/bindings/arm/arm,itcm.yaml index 4b0b34799cc939..41a006453f4ede 100644 --- a/dts/bindings/arm/arm,itcm.yaml +++ b/dts/bindings/arm/arm,itcm.yaml @@ -7,5 +7,5 @@ compatible: "arm,itcm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/arm,scc.yaml b/dts/bindings/arm/arm,scc.yaml index 189b1085887b84..d12968c040d5e8 100644 --- a/dts/bindings/arm/arm,scc.yaml +++ b/dts/bindings/arm/arm,scc.yaml @@ -8,5 +8,5 @@ compatible: "arm,scc" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/atmel,sam-ssc.yaml b/dts/bindings/arm/atmel,sam-ssc.yaml index c462fdb380e929..26fff20c76243c 100644 --- a/dts/bindings/arm/atmel,sam-ssc.yaml +++ b/dts/bindings/arm/atmel,sam-ssc.yaml @@ -6,35 +6,35 @@ description: Atmel SAM SSC (Synchronous Serial Controller) controller compatible: "atmel,sam-ssc" include: - - name: base.yaml - - name: pinctrl-device.yaml + - name: base.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true - - interrupts: - required: true - - peripheral-id: - type: int - description: peripheral ID - required: true - - dmas: - required: true - description: | - TX & RX dma specifiers. Each specifier will have a phandle - reference to the dma controller, the channel number, and peripheral - trigger source. - - For example dmas for TX, RX would look like - dmas = <&xdmac 22 DMA_PERID_SSC_TX>, <&xdmac 23 DMA_PERID_SSC_RX>; - - dma-names: - required: true - description: | - This should be "tx" and "rx" to match the dmas property. - - For example - dma-names = "tx", "rx"; + reg: + required: true + + interrupts: + required: true + + peripheral-id: + type: int + description: peripheral ID + required: true + + dmas: + required: true + description: | + TX & RX dma specifiers. Each specifier will have a phandle + reference to the dma controller, the channel number, and peripheral + trigger source. + + For example dmas for TX, RX would look like + dmas = <&xdmac 22 DMA_PERID_SSC_TX>, <&xdmac 23 DMA_PERID_SSC_RX>; + + dma-names: + required: true + description: | + This should be "tx" and "rx" to match the dmas property. + + For example + dma-names = "tx", "rx"; diff --git a/dts/bindings/arm/atmel,sam0-id.yaml b/dts/bindings/arm/atmel,sam0-id.yaml index 6b5de233f00343..08061062122bbd 100644 --- a/dts/bindings/arm/atmel,sam0-id.yaml +++ b/dts/bindings/arm/atmel,sam0-id.yaml @@ -6,5 +6,5 @@ compatible: "atmel,sam0-id" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/atmel,sam0-sercom.yaml b/dts/bindings/arm/atmel,sam0-sercom.yaml index 448a4f7d7e0588..30fb3b59176f2d 100644 --- a/dts/bindings/arm/atmel,sam0-sercom.yaml +++ b/dts/bindings/arm/atmel,sam0-sercom.yaml @@ -5,11 +5,11 @@ compatible: "atmel,sam0-sercom" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/arm/atmel,samd2x-pm.yaml b/dts/bindings/arm/atmel,samd2x-pm.yaml index 88af94202cfcdf..00dfda33c034a8 100644 --- a/dts/bindings/arm/atmel,samd2x-pm.yaml +++ b/dts/bindings/arm/atmel,samd2x-pm.yaml @@ -8,11 +8,11 @@ compatible: "atmel,samd2x-pm" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 2 + "#clock-cells": + const: 2 clock-cells: - offset diff --git a/dts/bindings/arm/nordic,nrf-acl.yaml b/dts/bindings/arm/nordic,nrf-acl.yaml index f6eb87ba0002f5..4dd1764aba937e 100644 --- a/dts/bindings/arm/nordic,nrf-acl.yaml +++ b/dts/bindings/arm/nordic,nrf-acl.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-acl" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-bprot.yaml b/dts/bindings/arm/nordic,nrf-bprot.yaml index 0f97c6cc5cd3d8..652363d11cf735 100644 --- a/dts/bindings/arm/nordic,nrf-bprot.yaml +++ b/dts/bindings/arm/nordic,nrf-bprot.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-bprot" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-ctrlapperi.yaml b/dts/bindings/arm/nordic,nrf-ctrlapperi.yaml index e79dc161f0d9bc..9447af2728c605 100644 --- a/dts/bindings/arm/nordic,nrf-ctrlapperi.yaml +++ b/dts/bindings/arm/nordic,nrf-ctrlapperi.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-ctrlapperi" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-dcnf.yaml b/dts/bindings/arm/nordic,nrf-dcnf.yaml index 65fd0450d05039..b27c3ff9da4afc 100644 --- a/dts/bindings/arm/nordic,nrf-dcnf.yaml +++ b/dts/bindings/arm/nordic,nrf-dcnf.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-dcnf" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-dppic.yaml b/dts/bindings/arm/nordic,nrf-dppic.yaml index 90d3294495bf78..678b0c7a6130c1 100644 --- a/dts/bindings/arm/nordic,nrf-dppic.yaml +++ b/dts/bindings/arm/nordic,nrf-dppic.yaml @@ -9,5 +9,5 @@ compatible: "nordic,nrf-dppic" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-egu.yaml b/dts/bindings/arm/nordic,nrf-egu.yaml index 269bc8b37e59d4..2b7792b27e7b41 100644 --- a/dts/bindings/arm/nordic,nrf-egu.yaml +++ b/dts/bindings/arm/nordic,nrf-egu.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-egu" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/arm/nordic,nrf-ficr.yaml b/dts/bindings/arm/nordic,nrf-ficr.yaml index c1f7be9caaf60d..bea0762573ebb6 100644 --- a/dts/bindings/arm/nordic,nrf-ficr.yaml +++ b/dts/bindings/arm/nordic,nrf-ficr.yaml @@ -5,5 +5,5 @@ compatible: "nordic,nrf-ficr" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-kmu.yaml b/dts/bindings/arm/nordic,nrf-kmu.yaml index 34442733c521b4..cae8c4ca7e7ce2 100644 --- a/dts/bindings/arm/nordic,nrf-kmu.yaml +++ b/dts/bindings/arm/nordic,nrf-kmu.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-kmu" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/arm/nordic,nrf-mpu.yaml b/dts/bindings/arm/nordic,nrf-mpu.yaml index a68a87302c768d..6e10c88cf26531 100644 --- a/dts/bindings/arm/nordic,nrf-mpu.yaml +++ b/dts/bindings/arm/nordic,nrf-mpu.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-mpu" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-mutex.yaml b/dts/bindings/arm/nordic,nrf-mutex.yaml index f4b4bd2eb3a4da..e8064d68a5a31f 100644 --- a/dts/bindings/arm/nordic,nrf-mutex.yaml +++ b/dts/bindings/arm/nordic,nrf-mutex.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-mutex" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-mwu.yaml b/dts/bindings/arm/nordic,nrf-mwu.yaml index d5cf406304061d..c17ac2135d252b 100644 --- a/dts/bindings/arm/nordic,nrf-mwu.yaml +++ b/dts/bindings/arm/nordic,nrf-mwu.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-mwu" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-ppi.yaml b/dts/bindings/arm/nordic,nrf-ppi.yaml index afbacbe9a64cfd..0044e55cc91f36 100644 --- a/dts/bindings/arm/nordic,nrf-ppi.yaml +++ b/dts/bindings/arm/nordic,nrf-ppi.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-ppi" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-reset.yaml b/dts/bindings/arm/nordic,nrf-reset.yaml index 596d19597f31d3..caa26225e5f998 100644 --- a/dts/bindings/arm/nordic,nrf-reset.yaml +++ b/dts/bindings/arm/nordic,nrf-reset.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-reset" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nordic,nrf-spu.yaml b/dts/bindings/arm/nordic,nrf-spu.yaml index 18578d2c3474cb..cd62c95dfac36b 100644 --- a/dts/bindings/arm/nordic,nrf-spu.yaml +++ b/dts/bindings/arm/nordic,nrf-spu.yaml @@ -5,8 +5,8 @@ compatible: "nordic,nrf-spu" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/arm/nordic,nrf-swi.yaml b/dts/bindings/arm/nordic,nrf-swi.yaml index 526600c8e050a8..ce68eb848d3029 100644 --- a/dts/bindings/arm/nordic,nrf-swi.yaml +++ b/dts/bindings/arm/nordic,nrf-swi.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-swi" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/arm/nordic,nrf-uicr.yaml b/dts/bindings/arm/nordic,nrf-uicr.yaml index f149f72a7f1994..82ac8fc2089332 100644 --- a/dts/bindings/arm/nordic,nrf-uicr.yaml +++ b/dts/bindings/arm/nordic,nrf-uicr.yaml @@ -5,5 +5,5 @@ compatible: "nordic,nrf-uicr" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nxp,imx-dtcm.yaml b/dts/bindings/arm/nxp,imx-dtcm.yaml index 8c76d6bfdac2bf..87be82cf81cdc3 100644 --- a/dts/bindings/arm/nxp,imx-dtcm.yaml +++ b/dts/bindings/arm/nxp,imx-dtcm.yaml @@ -8,5 +8,5 @@ compatible: "nxp,imx-dtcm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nxp,imx-epit.yaml b/dts/bindings/arm/nxp,imx-epit.yaml index aa014fdf409fc0..9c67b17edb6bad 100644 --- a/dts/bindings/arm/nxp,imx-epit.yaml +++ b/dts/bindings/arm/nxp,imx-epit.yaml @@ -9,17 +9,17 @@ include: base.yaml properties: reg: - required: true + required: true interrupts: - required: true + required: true prescaler: - type: int - required: true - description: Set the EPIT prescaler between 0 and 4095 + type: int + required: true + description: Set the EPIT prescaler between 0 and 4095 rdc: - type: int - required: true - description: Set the RDC permission for this peripheral + type: int + required: true + description: Set the RDC permission for this peripheral diff --git a/dts/bindings/arm/nxp,imx-itcm.yaml b/dts/bindings/arm/nxp,imx-itcm.yaml index c0919e7b141552..afbef83a2a151a 100644 --- a/dts/bindings/arm/nxp,imx-itcm.yaml +++ b/dts/bindings/arm/nxp,imx-itcm.yaml @@ -8,5 +8,5 @@ compatible: "nxp,imx-itcm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/nxp,imx-mu-rev2.yaml b/dts/bindings/arm/nxp,imx-mu-rev2.yaml index 8caa2bc7f3edef..7759e52293c779 100644 --- a/dts/bindings/arm/nxp,imx-mu-rev2.yaml +++ b/dts/bindings/arm/nxp,imx-mu-rev2.yaml @@ -9,12 +9,12 @@ include: base.yaml properties: reg: - required: true + required: true interrupts: - required: true + required: true rdc: - type: int - required: true - description: Set the RDC permission for this peripheral + type: int + required: true + description: Set the RDC permission for this peripheral diff --git a/dts/bindings/arm/nxp,imx-mu.yaml b/dts/bindings/arm/nxp,imx-mu.yaml index 0fd8fb9dce1fb2..3988be6661c5d2 100644 --- a/dts/bindings/arm/nxp,imx-mu.yaml +++ b/dts/bindings/arm/nxp,imx-mu.yaml @@ -9,12 +9,12 @@ include: base.yaml properties: reg: - required: true + required: true interrupts: - required: true + required: true rdc: - type: int - required: true - description: Set the RDC permission for this peripheral + type: int + required: true + description: Set the RDC permission for this peripheral diff --git a/dts/bindings/arm/nxp,kinetis-ftm.yaml b/dts/bindings/arm/nxp,kinetis-ftm.yaml index dc895f5daf8777..d0d90e1274d1fc 100644 --- a/dts/bindings/arm/nxp,kinetis-ftm.yaml +++ b/dts/bindings/arm/nxp,kinetis-ftm.yaml @@ -8,22 +8,22 @@ compatible: "nxp,kinetis-ftm" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 - description: Input clock prescaler + prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + description: Input clock prescaler diff --git a/dts/bindings/arm/nxp,lpc-flexcomm.yaml b/dts/bindings/arm/nxp,lpc-flexcomm.yaml index 233805533837f5..ffc27753c3dcea 100644 --- a/dts/bindings/arm/nxp,lpc-flexcomm.yaml +++ b/dts/bindings/arm/nxp,lpc-flexcomm.yaml @@ -8,8 +8,8 @@ compatible: "nxp,lpc-flexcomm" include: [base.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/arm/st,stm32-ccm.yaml b/dts/bindings/arm/st,stm32-ccm.yaml index 8f45f1249aa8df..8787c11f08ae27 100644 --- a/dts/bindings/arm/st,stm32-ccm.yaml +++ b/dts/bindings/arm/st,stm32-ccm.yaml @@ -7,5 +7,5 @@ compatible: "st,stm32-ccm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/arm/xlnx,zynq-ocm.yaml b/dts/bindings/arm/xlnx,zynq-ocm.yaml index 477d54a8fa6cf6..56b574aca60168 100644 --- a/dts/bindings/arm/xlnx,zynq-ocm.yaml +++ b/dts/bindings/arm/xlnx,zynq-ocm.yaml @@ -7,5 +7,5 @@ compatible: "xlnx,zynq-ocm" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/audio/nordic,nrf-pdm.yaml b/dts/bindings/audio/nordic,nrf-pdm.yaml index a425900f139980..c7d533bac540a1 100644 --- a/dts/bindings/audio/nordic,nrf-pdm.yaml +++ b/dts/bindings/audio/nordic,nrf-pdm.yaml @@ -8,62 +8,62 @@ compatible: "nordic,nrf-pdm" include: [base.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clk-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. + clk-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. - The CLK pin to use. + The CLK pin to use. - For pins P0.0 through P0.31, use the pin number. For example, - to use P0.16 for CLK, set: + For pins P0.0 through P0.31, use the pin number. For example, + to use P0.16 for CLK, set: - clk-pin = <16>; + clk-pin = <16>; - For pins P1.0 through P1.31, add 32 to the pin number. For - example, to use P1.2 for CLK, set: + For pins P1.0 through P1.31, add 32 to the pin number. For + example, to use P1.2 for CLK, set: - clk-pin = <34>; /* 32 + 2 */ + clk-pin = <34>; /* 32 + 2 */ - din-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. + din-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. - The DIN pin to use. The pin numbering scheme is the same as - the clk-pin property's. + The DIN pin to use. The pin numbering scheme is the same as + the clk-pin property's. - clock-source: - type: string - default: "PCLK32M_HFXO" - description: | - Clock source to be used by the PDM peripheral. The following options - are available: - - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK - - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator - (HFXO) for better clock accuracy and jitter performance - - "ACLK": Audio PLL clock with configurable frequency (frequency for - this clock must be set via the "hfclkaudio-frequency" property - in the "nordic,nrf-clock" node); this clock source is only available - in the nRF53 Series SoCs and it requires the use of HFXO - enum: - - "PCLK32M" - - "PCLK32M_HFXO" - - "ACLK" + clock-source: + type: string + default: "PCLK32M_HFXO" + description: | + Clock source to be used by the PDM peripheral. The following options + are available: + - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK + - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator + (HFXO) for better clock accuracy and jitter performance + - "ACLK": Audio PLL clock with configurable frequency (frequency for + this clock must be set via the "hfclkaudio-frequency" property + in the "nordic,nrf-clock" node); this clock source is only available + in the nRF53 Series SoCs and it requires the use of HFXO + enum: + - "PCLK32M" + - "PCLK32M_HFXO" + - "ACLK" - queue-size: - type: int - default: 4 - description: | - Size of the queue of received audio data blocks to be used - by the driver. + queue-size: + type: int + default: 4 + description: | + Size of the queue of received audio data blocks to be used + by the driver. diff --git a/dts/bindings/audio/ti,tlv320dac.yaml b/dts/bindings/audio/ti,tlv320dac.yaml index 7475144f44d5b9..3d8784ad96ef74 100644 --- a/dts/bindings/audio/ti,tlv320dac.yaml +++ b/dts/bindings/audio/ti,tlv320dac.yaml @@ -8,6 +8,6 @@ compatible: "ti,tlv320dac" include: i2c-device.yaml properties: - reset-gpios: - type: phandle-array - required: true + reset-gpios: + type: phandle-array + required: true diff --git a/dts/bindings/base/base.yaml b/dts/bindings/base/base.yaml index 60c74edb3f8844..f1d1109a19921e 100644 --- a/dts/bindings/base/base.yaml +++ b/dts/bindings/base/base.yaml @@ -3,92 +3,92 @@ include: [pm.yaml] properties: - status: - type: string - description: indicates the operational status of a device - enum: - - "ok" # Deprecated form - - "okay" - - "disabled" - - "reserved" - - "fail" - - "fail-sss" - - compatible: - type: string-array - required: true - description: compatible strings - - reg: - type: array - description: register space - - reg-names: - type: string-array - description: name of each register space - - interrupts: - type: array - description: interrupts for device - - # Does not follow the 'type: phandle-array' scheme, but gets type-checked - # by the code. Declare it here just so that other bindings can make it - # 'required: true' easily if they want to. - interrupts-extended: - type: compound - description: extended interrupt specifier for device - - interrupt-names: - type: string-array - description: name of each interrupt - - interrupt-parent: - type: phandle - description: phandle to interrupt controller node - - label: - type: string - deprecated: true - description: | - Human readable string describing the device (used as device_get_binding() argument) - - clocks: - type: phandle-array - description: Clock gate information - - clock-names: - type: string-array - description: name of each clock - - "#address-cells": - type: int - description: number of address cells in reg property - - "#size-cells": - type: int - description: number of size cells in reg property - - dmas: - type: phandle-array - description: DMA channels specifiers - - dma-names: - type: string-array - description: Provided names of DMA channel specifiers - - io-channels: - type: phandle-array - description: IO channels specifiers - - io-channel-names: - type: string-array - description: Provided names of IO channel specifiers - - mboxes: - type: phandle-array - description: mailbox / IPM channels specifiers - specifier-space: mbox - - mbox-names: - type: string-array - description: Provided names of mailbox / IPM channel specifiers + status: + type: string + description: indicates the operational status of a device + enum: + - "ok" # Deprecated form + - "okay" + - "disabled" + - "reserved" + - "fail" + - "fail-sss" + + compatible: + type: string-array + required: true + description: compatible strings + + reg: + type: array + description: register space + + reg-names: + type: string-array + description: name of each register space + + interrupts: + type: array + description: interrupts for device + + # Does not follow the 'type: phandle-array' scheme, but gets type-checked + # by the code. Declare it here just so that other bindings can make it + # 'required: true' easily if they want to. + interrupts-extended: + type: compound + description: extended interrupt specifier for device + + interrupt-names: + type: string-array + description: name of each interrupt + + interrupt-parent: + type: phandle + description: phandle to interrupt controller node + + label: + type: string + deprecated: true + description: | + Human readable string describing the device (used as device_get_binding() argument) + + clocks: + type: phandle-array + description: Clock gate information + + clock-names: + type: string-array + description: name of each clock + + "#address-cells": + type: int + description: number of address cells in reg property + + "#size-cells": + type: int + description: number of size cells in reg property + + dmas: + type: phandle-array + description: DMA channels specifiers + + dma-names: + type: string-array + description: Provided names of DMA channel specifiers + + io-channels: + type: phandle-array + description: IO channels specifiers + + io-channel-names: + type: string-array + description: Provided names of IO channel specifiers + + mboxes: + type: phandle-array + description: mailbox / IPM channels specifiers + specifier-space: mbox + + mbox-names: + type: string-array + description: Provided names of mailbox / IPM channel specifiers diff --git a/dts/bindings/base/pm.yaml b/dts/bindings/base/pm.yaml index 2ceca5711666be..1926640d9a22b5 100644 --- a/dts/bindings/base/pm.yaml +++ b/dts/bindings/base/pm.yaml @@ -4,25 +4,25 @@ # Properties for Power Management (PM) properties: - wakeup-source: - required: false - type: boolean - description: | - Property to identify that a device can be used as wake up source. + wakeup-source: + required: false + type: boolean + description: | + Property to identify that a device can be used as wake up source. - When this property is provided a specific flag is set into the - device that tells the system that the device is capable of - wake up the system. + When this property is provided a specific flag is set into the + device that tells the system that the device is capable of + wake up the system. - Wake up capable devices are disabled (interruptions will not wake up - the system) by default but they can be enabled at runtime if necessary. + Wake up capable devices are disabled (interruptions will not wake up + the system) by default but they can be enabled at runtime if necessary. - power-domain: - required: false - type: phandle - description: | + power-domain: + required: false + type: phandle + description: | - Power domain the device belongs to. + Power domain the device belongs to. - The device will be notified when the power domain it belongs to is either - suspended or resumed. + The device will be notified when the power domain it belongs to is either + suspended or resumed. diff --git a/dts/bindings/base/power.yaml b/dts/bindings/base/power.yaml index 0599b8973b4523..80af26b24dff9d 100644 --- a/dts/bindings/base/power.yaml +++ b/dts/bindings/base/power.yaml @@ -4,30 +4,30 @@ # Properties for nodes with controllable power supplies. properties: - supply-gpios: - type: phandle-array - required: false - description: | - GPIO specifier that controls power to the device. + supply-gpios: + type: phandle-array + required: false + description: | + GPIO specifier that controls power to the device. - This property should be provided when the device has a dedicated - switch that controls power to the device. The supply state is - entirely the responsibility of the device driver. + This property should be provided when the device has a dedicated + switch that controls power to the device. The supply state is + entirely the responsibility of the device driver. - Contrast with vin-supply. + Contrast with vin-supply. - vin-supply: - type: phandle - required: false - description: | - Reference to the regulator that controls power to the device. - The referenced devicetree node must have a regulator compatible. + vin-supply: + type: phandle + required: false + description: | + Reference to the regulator that controls power to the device. + The referenced devicetree node must have a regulator compatible. - This property should be provided when device power is supplied - by a shared regulator. The supply state is dependent on the - request status of all devices fed by the regulator. + This property should be provided when device power is supplied + by a shared regulator. The supply state is dependent on the + request status of all devices fed by the regulator. - Contrast with supply-gpios. If both properties are provided - then the regulator must be requested before the supply GPIOS is - set to an active state, and the supply GPIOS must be set to an - inactive state before releasing the regulator. + Contrast with supply-gpios. If both properties are provided + then the regulator must be requested before the supply GPIOS is + set to an active state, and the supply GPIOS must be set to an + inactive state before releasing the regulator. diff --git a/dts/bindings/bluetooth/zephyr,bt-hci-spi-slave.yaml b/dts/bindings/bluetooth/zephyr,bt-hci-spi-slave.yaml index 6c98086254dea8..3305c757897ee8 100644 --- a/dts/bindings/bluetooth/zephyr,bt-hci-spi-slave.yaml +++ b/dts/bindings/bluetooth/zephyr,bt-hci-spi-slave.yaml @@ -29,6 +29,6 @@ include: base.yaml on-bus: spi properties: - irq-gpios: - type: phandle-array - required: true + irq-gpios: + type: phandle-array + required: true diff --git a/dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml b/dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml index ae11d621248d96..1cc5720c43d149 100644 --- a/dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml +++ b/dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml @@ -10,16 +10,16 @@ compatible: "zephyr,bt-hci-spi" include: spi-device.yaml properties: - irq-gpios: - type: phandle-array - required: true + irq-gpios: + type: phandle-array + required: true - reset-gpios: - type: phandle-array - required: true + reset-gpios: + type: phandle-array + required: true - reset-assert-duration-ms: - type: int - description: - Minimum duration to hold the reset-gpios pin low for. - If not specified no delay beyond the code path execution time is guaranteed. + reset-assert-duration-ms: + type: int + description: + Minimum duration to hold the reset-gpios pin low for. + If not specified no delay beyond the code path execution time is guaranteed. diff --git a/dts/bindings/can/atmel,sam-can.yaml b/dts/bindings/can/atmel,sam-can.yaml index 837c8615837ac1..81fca805f21478 100644 --- a/dts/bindings/can/atmel,sam-can.yaml +++ b/dts/bindings/can/atmel,sam-can.yaml @@ -3,26 +3,26 @@ description: Specialization of Bosch m_can CAN-FD controller for Atmel SAM compatible: "atmel,sam-can" include: - - name: can-fd-controller.yaml - - name: pinctrl-device.yaml + - name: can-fd-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - required: true - description: peripheral ID + peripheral-id: + type: int + required: true + description: peripheral ID - divider: - type: int - required: true - enum: - - 6 - - 12 - - 24 - description: Clock divider for the CAN core clock + divider: + type: int + required: true + enum: + - 6 + - 12 + - 24 + description: Clock divider for the CAN core clock diff --git a/dts/bindings/can/bosch,m_can-base.yaml b/dts/bindings/can/bosch,m_can-base.yaml index d0b3ec64b91b72..aff4b4aa640e4a 100644 --- a/dts/bindings/can/bosch,m_can-base.yaml +++ b/dts/bindings/can/bosch,m_can-base.yaml @@ -3,26 +3,26 @@ description: Bosch M_CAN CAN-FD controller base compatible: "bosch,m_can-base" properties: - std-filter-elements: - type: int - required: true + std-filter-elements: + type: int + required: true - ext-filter-elements: - type: int - required: true + ext-filter-elements: + type: int + required: true - rx-fifo0-elements: - type: int - required: true + rx-fifo0-elements: + type: int + required: true - rx-fifo1-elements: - type: int - required: true + rx-fifo1-elements: + type: int + required: true - rx-buffer-elements: - type: int - required: true + rx-buffer-elements: + type: int + required: true - tx-buffer-elements: - type: int - required: true + tx-buffer-elements: + type: int + required: true diff --git a/dts/bindings/can/can-controller.yaml b/dts/bindings/can/can-controller.yaml index 2444acba686130..d558a7ffc093ac 100644 --- a/dts/bindings/can/can-controller.yaml +++ b/dts/bindings/can/can-controller.yaml @@ -3,64 +3,64 @@ include: base.yaml properties: - bus-speed: - type: int - required: true - description: bus speed in Baud/s - sjw: - type: int - required: true - description: Resynchronization jump width (ISO 11898-1) - prop-seg: - type: int - description: Time quantums of propagation segment (ISO 11898-1) - phase-seg1: - type: int - description: Time quantums of phase buffer 1 segment (ISO 11898-1) - phase-seg2: - type: int - description: Time quantums of phase buffer 2 segment (ISO 11898-1) - sample-point: - type: int - description: > - Sample point in permille. - This param is required if segments are not given. - If the sample point is given, the segments are ignored. - phys: - type: phandle - description: | - Actively controlled CAN transceiver. + bus-speed: + type: int + required: true + description: bus speed in Baud/s + sjw: + type: int + required: true + description: Resynchronization jump width (ISO 11898-1) + prop-seg: + type: int + description: Time quantums of propagation segment (ISO 11898-1) + phase-seg1: + type: int + description: Time quantums of phase buffer 1 segment (ISO 11898-1) + phase-seg2: + type: int + description: Time quantums of phase buffer 2 segment (ISO 11898-1) + sample-point: + type: int + description: > + Sample point in permille. + This param is required if segments are not given. + If the sample point is given, the segments are ignored. + phys: + type: phandle + description: | + Actively controlled CAN transceiver. - Example: - transceiver0: can-phy0 { - compatible = "nxp,tja1040", "can-transceiver-gpio"; - standby-gpios = ; - max-bitrate = <1000000>; - #phy-cells = <0>; - }; + Example: + transceiver0: can-phy0 { + compatible = "nxp,tja1040", "can-transceiver-gpio"; + standby-gpios = ; + max-bitrate = <1000000>; + #phy-cells = <0>; + }; - &can0 { - status = "okay"; + &can0 { + status = "okay"; - phys = <&transceiver0>; - }; + phys = <&transceiver0>; + }; child-binding: - description: | - Passive CAN transceiver. The child node must be named "can-transceiver". + description: | + Passive CAN transceiver. The child node must be named "can-transceiver". - Example: - &can0 { - status = "okay"; + Example: + &can0 { + status = "okay"; - can-transceiver { - max-bitrate = <1000000>; - }; + can-transceiver { + max-bitrate = <1000000>; }; + }; - properties: - max-bitrate: - type: int - required: true - description: | - The maximum bitrate supported by the CAN transceiver in bits/s. + properties: + max-bitrate: + type: int + required: true + description: | + The maximum bitrate supported by the CAN transceiver in bits/s. diff --git a/dts/bindings/can/can-fd-controller.yaml b/dts/bindings/can/can-fd-controller.yaml index 5fcea517cedc50..4fdfff2b25b982 100644 --- a/dts/bindings/can/can-fd-controller.yaml +++ b/dts/bindings/can/can-fd-controller.yaml @@ -3,29 +3,29 @@ include: can-controller.yaml properties: - bus-speed-data: - type: int - required: true - description: data phase bus speed in Baud/s - sjw-data: - type: int - required: true - description: Resynchronization jump width for the data phase. (ISO11898-1:2015) - prop-seg-data: - type: int - description: Time quantums of propagation segment for the data phase. (ISO11898-1:2015) - phase-seg1-data: - type: int - description: Time quantums of phase buffer 1 segment for the data phase. (ISO11898-1:2015) - phase-seg2-data: - type: int - description: Time quantums of phase buffer 2 segment for the data phase. (ISO11898-1:2015) - sample-point-data: - type: int - description: > - Sample point in permille for the data phase. - This param is required if segments are not given. - If the sample point is given, the segments are ignored. - tx-delay-comp-offset: - type: int - default: 0 + bus-speed-data: + type: int + required: true + description: data phase bus speed in Baud/s + sjw-data: + type: int + required: true + description: Resynchronization jump width for the data phase. (ISO11898-1:2015) + prop-seg-data: + type: int + description: Time quantums of propagation segment for the data phase. (ISO11898-1:2015) + phase-seg1-data: + type: int + description: Time quantums of phase buffer 1 segment for the data phase. (ISO11898-1:2015) + phase-seg2-data: + type: int + description: Time quantums of phase buffer 2 segment for the data phase. (ISO11898-1:2015) + sample-point-data: + type: int + description: > + Sample point in permille for the data phase. + This param is required if segments are not given. + If the sample point is given, the segments are ignored. + tx-delay-comp-offset: + type: int + default: 0 diff --git a/dts/bindings/can/espressif,esp32-twai.yaml b/dts/bindings/can/espressif,esp32-twai.yaml index 8f907ae874902b..cf0d19c23ae690 100644 --- a/dts/bindings/can/espressif,esp32-twai.yaml +++ b/dts/bindings/can/espressif,esp32-twai.yaml @@ -8,25 +8,25 @@ compatible: "espressif,esp32-twai" include: [can-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - clkout-divider: - type: int - description: | - Clock divider for the CLKOUT signal. If not set, the CLKOUT signal is turned off. + clkout-divider: + type: int + description: | + Clock divider for the CLKOUT signal. If not set, the CLKOUT signal is turned off. - Valid values are 1 or any even number from 2 to 14 for ESP32 and 2 to 490 for newer - Espressif MCUs like ESP32-C3. + Valid values are 1 or any even number from 2 to 14 for ESP32 and 2 to 490 for newer + Espressif MCUs like ESP32-C3. diff --git a/dts/bindings/can/kvaser,pcican.yaml b/dts/bindings/can/kvaser,pcican.yaml index cfcb3a107a8442..3836baf74c057f 100644 --- a/dts/bindings/can/kvaser,pcican.yaml +++ b/dts/bindings/can/kvaser,pcican.yaml @@ -8,5 +8,5 @@ compatible: "kvaser,pcican" include: [can-controller.yaml, pcie-device.yaml] properties: - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/can/microchip,mcp2515.yaml b/dts/bindings/can/microchip,mcp2515.yaml index df1555a94ffb0c..ac4dc350c45fbc 100644 --- a/dts/bindings/can/microchip,mcp2515.yaml +++ b/dts/bindings/can/microchip,mcp2515.yaml @@ -8,19 +8,19 @@ compatible: "microchip,mcp2515" include: [spi-device.yaml, can-controller.yaml] properties: - osc-freq: - type: int - required: true - description: Frequency of the external oscillator - int-gpios: - type: phandle-array - required: true - description: | - Interrupt pin. + osc-freq: + type: int + required: true + description: Frequency of the external oscillator + int-gpios: + type: phandle-array + required: true + description: | + Interrupt pin. - This pin signals active low when produced by the controller. The - property value should ensure the flags properly describe the signal - that is presented to the driver. - reg: - type: array - required: true + This pin signals active low when produced by the controller. The + property value should ensure the flags properly describe the signal + that is presented to the driver. + reg: + type: array + required: true diff --git a/dts/bindings/can/nxp,kinetis-flexcan.yaml b/dts/bindings/can/nxp,kinetis-flexcan.yaml index 31e72ec594def1..92f2c547ed7c43 100644 --- a/dts/bindings/can/nxp,kinetis-flexcan.yaml +++ b/dts/bindings/can/nxp,kinetis-flexcan.yaml @@ -8,16 +8,16 @@ compatible: "nxp,kinetis-flexcan" include: ["can-controller.yaml", "pinctrl-device.yaml"] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - clk-source: - type: int - required: true - description: CAN engine clock source + clk-source: + type: int + required: true + description: CAN engine clock source diff --git a/dts/bindings/can/nxp,lpc-mcan.yaml b/dts/bindings/can/nxp,lpc-mcan.yaml index a17f50a7a95f4a..d411ed6d00151e 100644 --- a/dts/bindings/can/nxp,lpc-mcan.yaml +++ b/dts/bindings/can/nxp,lpc-mcan.yaml @@ -5,11 +5,11 @@ compatible: "nxp,lpc-mcan" include: [can-fd-controller.yaml, "bosch,m_can-base.yaml", pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/can/renesas,rcar-can.yaml b/dts/bindings/can/renesas,rcar-can.yaml index 054cf5d4aa8eaa..5e3c0194038c8b 100644 --- a/dts/bindings/can/renesas,rcar-can.yaml +++ b/dts/bindings/can/renesas,rcar-can.yaml @@ -5,11 +5,11 @@ compatible: "renesas,rcar-can" include: [can-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/can/st,stm32-can.yaml b/dts/bindings/can/st,stm32-can.yaml index 999799fbb5e41c..6f0f3db674adc1 100644 --- a/dts/bindings/can/st,stm32-can.yaml +++ b/dts/bindings/can/st,stm32-can.yaml @@ -5,21 +5,21 @@ compatible: "st,stm32-can" include: [can-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - master-can-reg: - type: int - description: master can reg when different from current instance + master-can-reg: + type: int + description: master can reg when different from current instance diff --git a/dts/bindings/can/st,stm32-fdcan.yaml b/dts/bindings/can/st,stm32-fdcan.yaml index 1e81111eebf45a..a7558265d00df3 100644 --- a/dts/bindings/can/st,stm32-fdcan.yaml +++ b/dts/bindings/can/st,stm32-fdcan.yaml @@ -5,38 +5,38 @@ compatible: "st,stm32-fdcan" include: ["can-fd-controller.yaml", "pinctrl-device.yaml"] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - clk-divider: - type: int - enum: - - 1 - - 2 - - 4 - - 6 - - 8 - - 10 - - 12 - - 14 - - 16 - - 18 - - 20 - - 22 - - 24 - - 26 - - 28 - - 30 + clk-divider: + type: int + enum: + - 1 + - 2 + - 4 + - 6 + - 8 + - 10 + - 12 + - 14 + - 16 + - 18 + - 20 + - 22 + - 24 + - 26 + - 28 + - 30 - description: | - Divides the kernel clock giving the time quanta clock that is fed to the - CAN core(FDCAN_CKDIV). - Note that the divisor is common to all 'st,stm32-fdcan' instances. - Divide by 1 is the peripherals reset value and remains set unless - this property is configured. + description: | + Divides the kernel clock giving the time quanta clock that is fed to the + CAN core(FDCAN_CKDIV). + Note that the divisor is common to all 'st,stm32-fdcan' instances. + Divide by 1 is the peripherals reset value and remains set unless + this property is configured. diff --git a/dts/bindings/can/st,stm32h7-fdcan.yaml b/dts/bindings/can/st,stm32h7-fdcan.yaml index e6c6f0ea44f104..9f9f0250312dec 100644 --- a/dts/bindings/can/st,stm32h7-fdcan.yaml +++ b/dts/bindings/can/st,stm32h7-fdcan.yaml @@ -5,11 +5,11 @@ compatible: "st,stm32h7-fdcan" include: ["can-fd-controller.yaml", "pinctrl-device.yaml"] properties: - clocks: - required: true + clocks: + required: true - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/can/zephyr,native-posix-linux-can.yaml b/dts/bindings/can/zephyr,native-posix-linux-can.yaml index 966a45fd5e51c4..275019a2c9e079 100644 --- a/dts/bindings/can/zephyr,native-posix-linux-can.yaml +++ b/dts/bindings/can/zephyr,native-posix-linux-can.yaml @@ -8,7 +8,7 @@ compatible: "zephyr,native-posix-linux-can" include: can-controller.yaml properties: - host-interface: - type: string - required: true - description: Linux host interface name (e.g. zcan0, vcan0, can0, ...) + host-interface: + type: string + required: true + description: Linux host interface name (e.g. zcan0, vcan0, can0, ...) diff --git a/dts/bindings/clock/aspeed,ast10x0-clock.yaml b/dts/bindings/clock/aspeed,ast10x0-clock.yaml index 8149435a8793d9..7bbaabc985faaa 100644 --- a/dts/bindings/clock/aspeed,ast10x0-clock.yaml +++ b/dts/bindings/clock/aspeed,ast10x0-clock.yaml @@ -8,8 +8,8 @@ compatible: "aspeed,ast10x0-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - clk_id diff --git a/dts/bindings/clock/atmel,samc2x-gclk.yaml b/dts/bindings/clock/atmel,samc2x-gclk.yaml index 95ef0638d1e4ad..d1e97272df72f4 100644 --- a/dts/bindings/clock/atmel,samc2x-gclk.yaml +++ b/dts/bindings/clock/atmel,samc2x-gclk.yaml @@ -8,11 +8,11 @@ compatible: "atmel,samc2x-gclk" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - periph_ch diff --git a/dts/bindings/clock/atmel,samc2x-mclk.yaml b/dts/bindings/clock/atmel,samc2x-mclk.yaml index e3a8b0b696b902..227fa5246c0150 100644 --- a/dts/bindings/clock/atmel,samc2x-mclk.yaml +++ b/dts/bindings/clock/atmel,samc2x-mclk.yaml @@ -8,11 +8,11 @@ compatible: "atmel,samc2x-mclk" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 2 + "#clock-cells": + const: 2 clock-cells: - offset diff --git a/dts/bindings/clock/atmel,samd2x-gclk.yaml b/dts/bindings/clock/atmel,samd2x-gclk.yaml index 29cce3b5984cbf..f5188aef05f90a 100644 --- a/dts/bindings/clock/atmel,samd2x-gclk.yaml +++ b/dts/bindings/clock/atmel,samd2x-gclk.yaml @@ -8,11 +8,11 @@ compatible: "atmel,samd2x-gclk" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - clkctrl_id diff --git a/dts/bindings/clock/atmel,samd5x-gclk.yaml b/dts/bindings/clock/atmel,samd5x-gclk.yaml index 65a9cadc551ade..68fd94b44eb82a 100644 --- a/dts/bindings/clock/atmel,samd5x-gclk.yaml +++ b/dts/bindings/clock/atmel,samd5x-gclk.yaml @@ -8,11 +8,11 @@ compatible: "atmel,samd5x-gclk" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - periph_ch diff --git a/dts/bindings/clock/atmel,samd5x-mclk.yaml b/dts/bindings/clock/atmel,samd5x-mclk.yaml index 53b1ce93c05ac5..603196570daea9 100644 --- a/dts/bindings/clock/atmel,samd5x-mclk.yaml +++ b/dts/bindings/clock/atmel,samd5x-mclk.yaml @@ -8,11 +8,11 @@ compatible: "atmel,samd5x-mclk" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 2 + "#clock-cells": + const: 2 clock-cells: - offset diff --git a/dts/bindings/clock/atmel,saml2x-gclk.yaml b/dts/bindings/clock/atmel,saml2x-gclk.yaml index 9adcb5322065ff..3c9020d505237c 100644 --- a/dts/bindings/clock/atmel,saml2x-gclk.yaml +++ b/dts/bindings/clock/atmel,saml2x-gclk.yaml @@ -8,11 +8,11 @@ compatible: "atmel,saml2x-gclk" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - periph_ch diff --git a/dts/bindings/clock/atmel,saml2x-mclk.yaml b/dts/bindings/clock/atmel,saml2x-mclk.yaml index e2a4eefcc81897..ed89ba36f12e37 100644 --- a/dts/bindings/clock/atmel,saml2x-mclk.yaml +++ b/dts/bindings/clock/atmel,saml2x-mclk.yaml @@ -8,11 +8,11 @@ compatible: "atmel,saml2x-mclk" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 2 + "#clock-cells": + const: 2 clock-cells: - offset diff --git a/dts/bindings/clock/clock-controller.yaml b/dts/bindings/clock/clock-controller.yaml index 7bb24b4505592c..45f5d6faf7125b 100644 --- a/dts/bindings/clock/clock-controller.yaml +++ b/dts/bindings/clock/clock-controller.yaml @@ -4,7 +4,7 @@ # Common fields for clock controllers properties: - "#clock-cells": - type: int - required: true - description: Number of items to expect in a Clock specifier + "#clock-cells": + type: int + required: true + description: Number of items to expect in a Clock specifier diff --git a/dts/bindings/clock/espressif,esp32-rtc.yaml b/dts/bindings/clock/espressif,esp32-rtc.yaml index ba70e541c12d72..e30b027a46660a 100644 --- a/dts/bindings/clock/espressif,esp32-rtc.yaml +++ b/dts/bindings/clock/espressif,esp32-rtc.yaml @@ -8,20 +8,20 @@ compatible: "espressif,esp32-rtc" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - xtal-freq: - type: int - required: true - description: Value of the external XTAL connected to ESP32. + xtal-freq: + type: int + required: true + description: Value of the external XTAL connected to ESP32. - xtal-div: - type: int - description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div + xtal-div: + type: int + description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - offset # Index of the peripheral in esp32 modules list (Check esp32_clock.h) diff --git a/dts/bindings/clock/fixed-clock.yaml b/dts/bindings/clock/fixed-clock.yaml index d8d4c1724dc41a..1bf6bfd4ad4127 100644 --- a/dts/bindings/clock/fixed-clock.yaml +++ b/dts/bindings/clock/fixed-clock.yaml @@ -8,14 +8,14 @@ compatible: "fixed-clock" include: clock-controller.yaml properties: - clock-frequency: - type: int - description: output clock frequency (Hz) - required: true + clock-frequency: + type: int + description: output clock frequency (Hz) + required: true - clocks: - type: array - description: input clock source + clocks: + type: array + description: input clock source - "#clock-cells": - const: 0 + "#clock-cells": + const: 0 diff --git a/dts/bindings/clock/fixed-factor-clock.yaml b/dts/bindings/clock/fixed-factor-clock.yaml index dd9f571f8198c4..9642836e20dc98 100644 --- a/dts/bindings/clock/fixed-factor-clock.yaml +++ b/dts/bindings/clock/fixed-factor-clock.yaml @@ -8,17 +8,17 @@ compatible: "fixed-factor-clock" include: clock-controller.yaml properties: - clock-div: - type: int - description: fixed clock divider + clock-div: + type: int + description: fixed clock divider - clock-mult: - type: int - description: fixed clock multiplier + clock-mult: + type: int + description: fixed clock multiplier - clocks: - type: phandle-array - description: input clock source + clocks: + type: phandle-array + description: input clock source - "#clock-cells": - const: 0 + "#clock-cells": + const: 0 diff --git a/dts/bindings/clock/gd,gd32-cctl.yaml b/dts/bindings/clock/gd,gd32-cctl.yaml index c077f452e782ad..d66f6caf086407 100644 --- a/dts/bindings/clock/gd,gd32-cctl.yaml +++ b/dts/bindings/clock/gd,gd32-cctl.yaml @@ -25,8 +25,8 @@ compatible: "gd,gd32-cctl" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - id diff --git a/dts/bindings/clock/intel,adsp-shim-clkctl.yaml b/dts/bindings/clock/intel,adsp-shim-clkctl.yaml index ea00f0c43c5177..c0c73856ed255b 100644 --- a/dts/bindings/clock/intel,adsp-shim-clkctl.yaml +++ b/dts/bindings/clock/intel,adsp-shim-clkctl.yaml @@ -6,39 +6,39 @@ description: Intel ADSP clock controlling related constants. compatible: "intel,adsp-shim-clkctl" properties: - adsp-clkctl-clk-wovcro: - type: int - description: | - Index of WOVCRO clock encoding in the encoding array (if wovcro-supported is true). - - adsp-clkctl-clk-lpro: - type: int - description: Index of LPRO clock encoding in the encoding array. - - adsp-clkctl-clk-hpro: - type: int - description: Index of HPRO clock encoding in the encoding array. - - adsp-clkctl-freq-enc: - type: array - required: true - description: Array that encodes what is needed to enable each clock. - - adsp-clkctl-freq-mask: - type: array - description: Array that encodes needed masks to enable each clock. - - adsp-clkctl-freq-default: - type: int - required: true - description: Index for the default clock. - - adsp-clkctl-freq-lowest: - type: int - required: true - description: Index for the lowest frequency clock. - - wovcro-supported: - type: boolean - description: | - If WoV clock ring oscillator is supported. + adsp-clkctl-clk-wovcro: + type: int + description: | + Index of WOVCRO clock encoding in the encoding array (if wovcro-supported is true). + + adsp-clkctl-clk-lpro: + type: int + description: Index of LPRO clock encoding in the encoding array. + + adsp-clkctl-clk-hpro: + type: int + description: Index of HPRO clock encoding in the encoding array. + + adsp-clkctl-freq-enc: + type: array + required: true + description: Array that encodes what is needed to enable each clock. + + adsp-clkctl-freq-mask: + type: array + description: Array that encodes needed masks to enable each clock. + + adsp-clkctl-freq-default: + type: int + required: true + description: Index for the default clock. + + adsp-clkctl-freq-lowest: + type: int + required: true + description: Index for the lowest frequency clock. + + wovcro-supported: + type: boolean + description: | + If WoV clock ring oscillator is supported. diff --git a/dts/bindings/clock/intel,agilex-clock.yaml b/dts/bindings/clock/intel,agilex-clock.yaml index 58820a76c18812..945c4ed049062f 100644 --- a/dts/bindings/clock/intel,agilex-clock.yaml +++ b/dts/bindings/clock/intel,agilex-clock.yaml @@ -8,11 +8,11 @@ compatible: "intel,agilex-clock" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - clkid diff --git a/dts/bindings/clock/microchip,xec-pcr.yaml b/dts/bindings/clock/microchip,xec-pcr.yaml index be2a24466085e5..5bfbcd9b44ab82 100644 --- a/dts/bindings/clock/microchip,xec-pcr.yaml +++ b/dts/bindings/clock/microchip,xec-pcr.yaml @@ -8,98 +8,98 @@ compatible: "microchip,xec-pcr" include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - reg: - required: true - - interrupts: - required: false - - core-clock-div: - type: int - required: true - description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock - - slow-clock-div: - type: int - description: | - PWM and TACH clock domain divided down from 48 MHz AHB clock. The - default value is 480 for 100 kHz. - - pll-32k-src: - type: int - required: true - description: 32 KHz clock source for PLL - - periph-32k-src: - type: int - required: true - description: 32 KHz clock source for peripherals - - xtal-single-ended: - type: boolean - description: Use single ended crystal connection to XTAL2 pin. - - clk32kmon-period-min: - type: int - required: true - description: | - 32KHz clock monitor minimum valid 32KHz period in 48MHz units - - clk32kmon-period-max: - type: int - required: true - description: | - 32KHz clock monitor maximum valid 32KHz period in 48MHz units - - clk32kmon-duty-cycle-var-max: - type: int - required: true - description: | - Maximum duty cycle variation. Difference in units of 48HMz between - the measured 32KHz high and low pulse widths. - - clk32kmon-valid-min: - type: int - required: true - description: | - Mininum number of consecutive 32KHz pulses that pass all monitor tests - - xtal-enable-delay-ms: - type: int - required: true - default: 300 - description: | - Delay in milliseconds after crystal is enabled and clock monitor is - started. - - pll-lock-timeout-ms: - type: int - required: true - default: 30 - description: | - Timeout in milliseconds waiting for PLL to lock to new clock source. - - clkmon-bypass: - type: boolean - required: false - description: Bypass clkmon check of crystal or XTAL2 single-ended clock. - - internal-osc-disable: - type: boolean - required: false - description: | - If the internal silicon 32KHz oscillator is not chosen as the source - for PLL and Periheral devices then disable the internal 32KHz - oscillator to save power. - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - "#clock-cells": - const: 2 + reg: + required: true + + interrupts: + required: false + + core-clock-div: + type: int + required: true + description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock + + slow-clock-div: + type: int + description: | + PWM and TACH clock domain divided down from 48 MHz AHB clock. The + default value is 480 for 100 kHz. + + pll-32k-src: + type: int + required: true + description: 32 KHz clock source for PLL + + periph-32k-src: + type: int + required: true + description: 32 KHz clock source for peripherals + + xtal-single-ended: + type: boolean + description: Use single ended crystal connection to XTAL2 pin. + + clk32kmon-period-min: + type: int + required: true + description: | + 32KHz clock monitor minimum valid 32KHz period in 48MHz units + + clk32kmon-period-max: + type: int + required: true + description: | + 32KHz clock monitor maximum valid 32KHz period in 48MHz units + + clk32kmon-duty-cycle-var-max: + type: int + required: true + description: | + Maximum duty cycle variation. Difference in units of 48HMz between + the measured 32KHz high and low pulse widths. + + clk32kmon-valid-min: + type: int + required: true + description: | + Mininum number of consecutive 32KHz pulses that pass all monitor tests + + xtal-enable-delay-ms: + type: int + required: true + default: 300 + description: | + Delay in milliseconds after crystal is enabled and clock monitor is + started. + + pll-lock-timeout-ms: + type: int + required: true + default: 30 + description: | + Timeout in milliseconds waiting for PLL to lock to new clock source. + + clkmon-bypass: + type: boolean + required: false + description: Bypass clkmon check of crystal or XTAL2 single-ended clock. + + internal-osc-disable: + type: boolean + required: false + description: | + If the internal silicon 32KHz oscillator is not chosen as the source + for PLL and Periheral devices then disable the internal 32KHz + oscillator to save power. + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + "#clock-cells": + const: 2 clock-cells: - regidx diff --git a/dts/bindings/clock/nordic,nrf-clock.yaml b/dts/bindings/clock/nordic,nrf-clock.yaml index 7efc36bb6763e6..22cde89bcfb1a2 100644 --- a/dts/bindings/clock/nordic,nrf-clock.yaml +++ b/dts/bindings/clock/nordic,nrf-clock.yaml @@ -8,16 +8,16 @@ compatible: "nordic,nrf-clock" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - hfclkaudio-frequency: - type: int - description: | - Frequency of the HFCLKAUDIO clock in Hz. Adjustable with 3.3 ppm - resolution in two frequency bands - 11.176 MHz to 11.402 MHz, and - 12.165 MHz to 12.411 MHz (refer to the relevant Product Specification). - The HFCLKAUDIO clock is only available in the nRF53 Series SoCs. + hfclkaudio-frequency: + type: int + description: | + Frequency of the HFCLKAUDIO clock in Hz. Adjustable with 3.3 ppm + resolution in two frequency bands - 11.176 MHz to 11.402 MHz, and + 12.165 MHz to 12.411 MHz (refer to the relevant Product Specification). + The HFCLKAUDIO clock is only available in the nRF53 Series SoCs. diff --git a/dts/bindings/clock/nordic,nrf-oscillators.yaml b/dts/bindings/clock/nordic,nrf-oscillators.yaml index 1094c263a50950..2c3a4bcc7209cd 100644 --- a/dts/bindings/clock/nordic,nrf-oscillators.yaml +++ b/dts/bindings/clock/nordic,nrf-oscillators.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-oscillators" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/clock/nuvoton,npcx-pcc.yaml b/dts/bindings/clock/nuvoton,npcx-pcc.yaml index 7678e279167780..258e5c67125e8b 100644 --- a/dts/bindings/clock/nuvoton,npcx-pcc.yaml +++ b/dts/bindings/clock/nuvoton,npcx-pcc.yaml @@ -23,200 +23,200 @@ compatible: "nuvoton,npcx-pcc" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - clock-frequency: - required: true - type: int - description: | - Default frequency in Hz for HFCG output clock (OFMCLK). Currently, - only the following values are allowed: - 100000000, 100 MHz - 96000000, 96 MHz - 90000000, 90 MHz - 80000000, 80 MHz - 66000000, 66 MHz - 50000000, 50 MHz - 48000000, 48 MHz - 40000000, 40 MHz (default value after reset) - 33000000, 33 MHz - enum: - - 100000000 - - 96000000 - - 90000000 - - 80000000 - - 66000000 - - 50000000 - - 48000000 - - 40000000 - - 33000000 + clock-frequency: + required: true + type: int + description: | + Default frequency in Hz for HFCG output clock (OFMCLK). Currently, + only the following values are allowed: + 100000000, 100 MHz + 96000000, 96 MHz + 90000000, 90 MHz + 80000000, 80 MHz + 66000000, 66 MHz + 50000000, 50 MHz + 48000000, 48 MHz + 40000000, 40 MHz (default value after reset) + 33000000, 33 MHz + enum: + - 100000000 + - 96000000 + - 90000000 + - 80000000 + - 66000000 + - 50000000 + - 48000000 + - 40000000 + - 33000000 - core-prescaler: - type: int - required: true - description: | - Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by - dividing OFMCLK(MCLK) and needs to meet the following requirements. - - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz. - = Only the following values are allowed: - 1, CORE_CLK = OFMCLK - 2, CORE_CLK = OFMCLK / 2 - 3, CORE_CLK = OFMCLK / 3 - 4, CORE_CLK = OFMCLK / 4 - 5, CORE_CLK = OFMCLK / 5 - 6, CORE_CLK = OFMCLK / 6 - 7, CORE_CLK = OFMCLK / 7 - 8, CORE_CLK = OFMCLK / 8 - 9, CORE_CLK = OFMCLK / 9 - 10, CORE_CLK = OFMCLK / 10 - enum: - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 + core-prescaler: + type: int + required: true + description: | + Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by + dividing OFMCLK(MCLK) and needs to meet the following requirements. + - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz. + = Only the following values are allowed: + 1, CORE_CLK = OFMCLK + 2, CORE_CLK = OFMCLK / 2 + 3, CORE_CLK = OFMCLK / 3 + 4, CORE_CLK = OFMCLK / 4 + 5, CORE_CLK = OFMCLK / 5 + 6, CORE_CLK = OFMCLK / 6 + 7, CORE_CLK = OFMCLK / 7 + 8, CORE_CLK = OFMCLK / 8 + 9, CORE_CLK = OFMCLK / 9 + 10, CORE_CLK = OFMCLK / 10 + enum: + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 - apb1-prescaler: - type: int - required: true - description: | - APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing - OFMCLK(MCLK) and needs to meet the following requirements. - - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz. - - APB1_CLK must be an integer division (including 1) of CORE_CLK. - = Only the following values are allowed: - 1, APB1_CLK = OFMCLK - 2, APB1_CLK = OFMCLK / 2 - 3, APB1_CLK = OFMCLK / 3 - 4, APB1_CLK = OFMCLK / 4 - 5, APB1_CLK = OFMCLK / 5 - 6, APB1_CLK = OFMCLK / 6 - 7, APB1_CLK = OFMCLK / 7 - 8, APB1_CLK = OFMCLK / 8 - 9, APB1_CLK = OFMCLK / 9 - 10, APB1_CLK = OFMCLK / 10 - enum: - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 + apb1-prescaler: + type: int + required: true + description: | + APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing + OFMCLK(MCLK) and needs to meet the following requirements. + - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz. + - APB1_CLK must be an integer division (including 1) of CORE_CLK. + = Only the following values are allowed: + 1, APB1_CLK = OFMCLK + 2, APB1_CLK = OFMCLK / 2 + 3, APB1_CLK = OFMCLK / 3 + 4, APB1_CLK = OFMCLK / 4 + 5, APB1_CLK = OFMCLK / 5 + 6, APB1_CLK = OFMCLK / 6 + 7, APB1_CLK = OFMCLK / 7 + 8, APB1_CLK = OFMCLK / 8 + 9, APB1_CLK = OFMCLK / 9 + 10, APB1_CLK = OFMCLK / 10 + enum: + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 - apb2-prescaler: - type: int - required: true - description: | - APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing - OFMCLK(MCLK) and needs to meet the following requirements. - - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz. - - APB2_CLK must be an integer division (including 1) of CORE_CLK. - = Only the following values are allowed: - 1, APB2_CLK = OFMCLK - 2, APB2_CLK = OFMCLK / 2 - 3, APB2_CLK = OFMCLK / 3 - 4, APB2_CLK = OFMCLK / 4 - 5, APB2_CLK = OFMCLK / 5 - 6, APB2_CLK = OFMCLK / 6 - 7, APB2_CLK = OFMCLK / 7 - 8, APB2_CLK = OFMCLK / 8 - 9, APB2_CLK = OFMCLK / 9 - 10, APB2_CLK = OFMCLK / 10 - enum: - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 + apb2-prescaler: + type: int + required: true + description: | + APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing + OFMCLK(MCLK) and needs to meet the following requirements. + - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz. + - APB2_CLK must be an integer division (including 1) of CORE_CLK. + = Only the following values are allowed: + 1, APB2_CLK = OFMCLK + 2, APB2_CLK = OFMCLK / 2 + 3, APB2_CLK = OFMCLK / 3 + 4, APB2_CLK = OFMCLK / 4 + 5, APB2_CLK = OFMCLK / 5 + 6, APB2_CLK = OFMCLK / 6 + 7, APB2_CLK = OFMCLK / 7 + 8, APB2_CLK = OFMCLK / 8 + 9, APB2_CLK = OFMCLK / 9 + 10, APB2_CLK = OFMCLK / 10 + enum: + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 - apb3-prescaler: - type: int - required: true - description: | - APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing - OFMCLK(MCLK) and needs to meet the following requirements. - - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz. - - APB3_CLK must be an integer division (including 1) of CORE_CLK. - = Only the following values are allowed: - 1, APB3_CLK = OFMCLK - 2, APB3_CLK = OFMCLK / 2 - 3, APB3_CLK = OFMCLK / 3 - 4, APB3_CLK = OFMCLK / 4 - 5, APB3_CLK = OFMCLK / 5 - 6, APB3_CLK = OFMCLK / 6 - 7, APB3_CLK = OFMCLK / 7 - 8, APB3_CLK = OFMCLK / 8 - 9, APB3_CLK = OFMCLK / 9 - 10, APB3_CLK = OFMCLK / 10 - enum: - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 + apb3-prescaler: + type: int + required: true + description: | + APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing + OFMCLK(MCLK) and needs to meet the following requirements. + - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz. + - APB3_CLK must be an integer division (including 1) of CORE_CLK. + = Only the following values are allowed: + 1, APB3_CLK = OFMCLK + 2, APB3_CLK = OFMCLK / 2 + 3, APB3_CLK = OFMCLK / 3 + 4, APB3_CLK = OFMCLK / 4 + 5, APB3_CLK = OFMCLK / 5 + 6, APB3_CLK = OFMCLK / 6 + 7, APB3_CLK = OFMCLK / 7 + 8, APB3_CLK = OFMCLK / 8 + 9, APB3_CLK = OFMCLK / 9 + 10, APB3_CLK = OFMCLK / 10 + enum: + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 - apb4-prescaler: - type: int - description: | - APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing - OFMCLK(MCLK) and needs to meet the following requirements. - - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz. - - APB4_CLK must be an integer division (including 1) of CORE_CLK. - = Only the following values are allowed: - 1, APB4_CLK = OFMCLK - 2, APB4_CLK = OFMCLK / 2 - 3, APB4_CLK = OFMCLK / 3 - 4, APB4_CLK = OFMCLK / 4 - 5, APB4_CLK = OFMCLK / 5 - 6, APB4_CLK = OFMCLK / 6 - 7, APB4_CLK = OFMCLK / 7 - 8, APB4_CLK = OFMCLK / 8 - 9, APB4_CLK = OFMCLK / 9 - 10, APB4_CLK = OFMCLK / 10 - enum: - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 + apb4-prescaler: + type: int + description: | + APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing + OFMCLK(MCLK) and needs to meet the following requirements. + - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz. + - APB4_CLK must be an integer division (including 1) of CORE_CLK. + = Only the following values are allowed: + 1, APB4_CLK = OFMCLK + 2, APB4_CLK = OFMCLK / 2 + 3, APB4_CLK = OFMCLK / 3 + 4, APB4_CLK = OFMCLK / 4 + 5, APB4_CLK = OFMCLK / 5 + 6, APB4_CLK = OFMCLK / 6 + 7, APB4_CLK = OFMCLK / 7 + 8, APB4_CLK = OFMCLK / 8 + 9, APB4_CLK = OFMCLK / 9 + 10, APB4_CLK = OFMCLK / 10 + enum: + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 - ram-pd-depth: - type: int - enum: - - 12 - - 15 - description: | - Valid bit-depth of RAM block Power-Down control (RAM_PD) registers. - Each bit in RAM_PDn can power down the relevant RAM block by setting - itself to 1 for better power consumption and this valid bit-depth - varies in different NPCX series. + ram-pd-depth: + type: int + enum: + - 12 + - 15 + description: | + Valid bit-depth of RAM block Power-Down control (RAM_PD) registers. + Each bit in RAM_PDn can power down the relevant RAM block by setting + itself to 1 for better power consumption and this valid bit-depth + varies in different NPCX series. clock-cells: - - bus - - ctl - - bit + - bus + - ctl + - bit diff --git a/dts/bindings/clock/nxp,imx-anatop.yaml b/dts/bindings/clock/nxp,imx-anatop.yaml index 02f42c024932fd..d75b07bab600a5 100644 --- a/dts/bindings/clock/nxp,imx-anatop.yaml +++ b/dts/bindings/clock/nxp,imx-anatop.yaml @@ -8,28 +8,28 @@ compatible: "nxp,imx-anatop" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - type: int - const: 4 - required: true - description: Number of items to expect in a clock specifier + "#clock-cells": + type: int + const: 4 + required: true + description: Number of items to expect in a clock specifier - "#pll-clock-cells": - type: int - const: 3 - required: true - description: Number of items to expect in a PLL specifier + "#pll-clock-cells": + type: int + const: 3 + required: true + description: Number of items to expect in a PLL specifier clock-cells: - - name - - offset - - bits - - value + - name + - offset + - bits + - value pll-clock-cells: - - offset - - bits - - value + - offset + - bits + - value diff --git a/dts/bindings/clock/nxp,imx-ccm-rev2.yaml b/dts/bindings/clock/nxp,imx-ccm-rev2.yaml index d6ba161605ebaa..1d4e87361916f9 100644 --- a/dts/bindings/clock/nxp,imx-ccm-rev2.yaml +++ b/dts/bindings/clock/nxp,imx-ccm-rev2.yaml @@ -8,11 +8,11 @@ compatible: "nxp,imx-ccm-rev2" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 3 + "#clock-cells": + const: 3 clock-cells: - name diff --git a/dts/bindings/clock/nxp,imx-ccm.yaml b/dts/bindings/clock/nxp,imx-ccm.yaml index 1c571683265903..9ddda734e8144b 100644 --- a/dts/bindings/clock/nxp,imx-ccm.yaml +++ b/dts/bindings/clock/nxp,imx-ccm.yaml @@ -8,11 +8,11 @@ compatible: "nxp,imx-ccm" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 3 + "#clock-cells": + const: 3 clock-cells: - name diff --git a/dts/bindings/clock/nxp,kinetis-ke1xf-sim.yaml b/dts/bindings/clock/nxp,kinetis-ke1xf-sim.yaml index 7593a75b59c4f2..06879c048b11fe 100644 --- a/dts/bindings/clock/nxp,kinetis-ke1xf-sim.yaml +++ b/dts/bindings/clock/nxp,kinetis-ke1xf-sim.yaml @@ -8,13 +8,13 @@ compatible: "nxp,kinetis-ke1xf-sim" include: base.yaml properties: - reg: - required: true + reg: + required: true - clkout-source: - type: int - description: clkout clock source + clkout-source: + type: int + description: clkout clock source - clkout-divider: - type: int - description: clkout divider + clkout-divider: + type: int + description: clkout divider diff --git a/dts/bindings/clock/nxp,kinetis-mcg.yaml b/dts/bindings/clock/nxp,kinetis-mcg.yaml index 47f547ccd4adc4..3e694bf38f185b 100644 --- a/dts/bindings/clock/nxp,kinetis-mcg.yaml +++ b/dts/bindings/clock/nxp,kinetis-mcg.yaml @@ -8,11 +8,11 @@ compatible: "nxp,kinetis-mcg" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - name diff --git a/dts/bindings/clock/nxp,kinetis-pcc.yaml b/dts/bindings/clock/nxp,kinetis-pcc.yaml index 91fa1ecdd1dc04..c8d5eee7919507 100644 --- a/dts/bindings/clock/nxp,kinetis-pcc.yaml +++ b/dts/bindings/clock/nxp,kinetis-pcc.yaml @@ -8,11 +8,11 @@ compatible: "nxp,kinetis-pcc" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 2 + "#clock-cells": + const: 2 clock-cells: - name diff --git a/dts/bindings/clock/nxp,kinetis-scg.yaml b/dts/bindings/clock/nxp,kinetis-scg.yaml index 8888bb06dafed7..bce581bf4b8392 100644 --- a/dts/bindings/clock/nxp,kinetis-scg.yaml +++ b/dts/bindings/clock/nxp,kinetis-scg.yaml @@ -8,15 +8,15 @@ compatible: "nxp,kinetis-scg" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - sosc-mode: - type: int - description: system oscillator mode + sosc-mode: + type: int + description: system oscillator mode - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - name diff --git a/dts/bindings/clock/nxp,kinetis-sim.yaml b/dts/bindings/clock/nxp,kinetis-sim.yaml index e4ac74fa230f32..5dc670f6510936 100644 --- a/dts/bindings/clock/nxp,kinetis-sim.yaml +++ b/dts/bindings/clock/nxp,kinetis-sim.yaml @@ -8,30 +8,30 @@ compatible: "nxp,kinetis-sim" include: base.yaml properties: - reg: - required: true - - pllfll-select: - type: int - required: true - description: pll/fll selection for clock system - - er32k-select: - type: int - required: true - description: er32k selection for clock system - - clkout-source: - type: int - description: clkout clock source - - clkout-divider: - type: int - description: clkout divider - - "#clock-cells": - type: int - const: 3 + reg: + required: true + + pllfll-select: + type: int + required: true + description: pll/fll selection for clock system + + er32k-select: + type: int + required: true + description: er32k selection for clock system + + clkout-source: + type: int + description: clkout clock source + + clkout-divider: + type: int + description: clkout divider + + "#clock-cells": + type: int + const: 3 clock-cells: - name diff --git a/dts/bindings/clock/nxp,lpc-syscon.yaml b/dts/bindings/clock/nxp,lpc-syscon.yaml index 7bf5a8fe8f52a2..ff151836f71d20 100644 --- a/dts/bindings/clock/nxp,lpc-syscon.yaml +++ b/dts/bindings/clock/nxp,lpc-syscon.yaml @@ -8,11 +8,11 @@ compatible: "nxp,lpc-syscon" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - name diff --git a/dts/bindings/clock/nxp,lpc11u6x-syscon.yaml b/dts/bindings/clock/nxp,lpc11u6x-syscon.yaml index 33f0a5015b6ed4..eee30e56174f7a 100644 --- a/dts/bindings/clock/nxp,lpc11u6x-syscon.yaml +++ b/dts/bindings/clock/nxp,lpc11u6x-syscon.yaml @@ -8,17 +8,17 @@ compatible: "nxp,lpc11u6x-syscon" include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - clkid diff --git a/dts/bindings/clock/renesas,rcar-cpg-mssr.yaml b/dts/bindings/clock/renesas,rcar-cpg-mssr.yaml index 99ebf374f722fb..ab2309611b8716 100644 --- a/dts/bindings/clock/renesas,rcar-cpg-mssr.yaml +++ b/dts/bindings/clock/renesas,rcar-cpg-mssr.yaml @@ -6,11 +6,11 @@ description: Renesas Clock Pulse Generator / Module Standby and Software Reset include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 2 + "#clock-cells": + const: 2 clock-cells: - domain diff --git a/dts/bindings/clock/st,stm32-clock-mux.yaml b/dts/bindings/clock/st,stm32-clock-mux.yaml index 49257e276bb5e0..1798ee686d2cec 100644 --- a/dts/bindings/clock/st,stm32-clock-mux.yaml +++ b/dts/bindings/clock/st,stm32-clock-mux.yaml @@ -15,8 +15,8 @@ description: | compatible: "st,stm32-clock-mux" include: - - name: base.yaml - property-allowlist: - - status - - compatible - - clocks + - name: base.yaml + property-allowlist: + - status + - compatible + - clocks diff --git a/dts/bindings/clock/st,stm32-hse-clock.yaml b/dts/bindings/clock/st,stm32-hse-clock.yaml index 49c8f09c4f7760..833a393595d676 100644 --- a/dts/bindings/clock/st,stm32-hse-clock.yaml +++ b/dts/bindings/clock/st,stm32-hse-clock.yaml @@ -8,8 +8,8 @@ compatible: "st,stm32-hse-clock" include: [fixed-clock.yaml] properties: - hse-bypass: - type: boolean - description: | - HSE crystal oscillator bypass - Set to the property to by-pass the oscillator with an external clock. + hse-bypass: + type: boolean + description: | + HSE crystal oscillator bypass + Set to the property to by-pass the oscillator with an external clock. diff --git a/dts/bindings/clock/st,stm32-lse-clock.yaml b/dts/bindings/clock/st,stm32-lse-clock.yaml index eb11ae9fc6e015..86fa3ab4e84da5 100644 --- a/dts/bindings/clock/st,stm32-lse-clock.yaml +++ b/dts/bindings/clock/st,stm32-lse-clock.yaml @@ -8,21 +8,21 @@ compatible: "st,stm32-lse-clock" include: [fixed-clock.yaml] properties: - driving-capability: - type: int - required: true - description: | - LSE driving capability, within the range 0 to 3. - 0 represents the lowests driving capability, 3 - the highest. - enum: - - 0 - - 1 - - 2 - - 3 + driving-capability: + type: int + required: true + description: | + LSE driving capability, within the range 0 to 3. + 0 represents the lowests driving capability, 3 + the highest. + enum: + - 0 + - 1 + - 2 + - 3 - lse-bypass: - type: boolean - description: | - LSE crystal oscillator bypass - Set the property to by-pass the oscillator with an external clock. + lse-bypass: + type: boolean + description: | + LSE crystal oscillator bypass + Set the property to by-pass the oscillator with an external clock. diff --git a/dts/bindings/clock/st,stm32-msi-clock.yaml b/dts/bindings/clock/st,stm32-msi-clock.yaml index 260b202762086e..3e8cac0f643ea5 100644 --- a/dts/bindings/clock/st,stm32-msi-clock.yaml +++ b/dts/bindings/clock/st,stm32-msi-clock.yaml @@ -8,28 +8,28 @@ compatible: "st,stm32-msi-clock" include: [clock-controller.yaml, base.yaml] properties: - msi-range: - required: true - type: int - default: 6 - description: | - MSI clock ranges - enum: - - 0 # range 0 around 100 kHz - - 1 # range 1 around 200 kHz - - 2 # range 2 around 400 kHz - - 3 # range 3 around 800 kHz - - 4 # range 4 around 1M Hz - - 5 # range 5 around 2 MHz - - 6 # range 6 around 4 MHz (reset value) - - 7 # range 7 around 8 MHz - - 8 # range 8 around 16 MHz - - 9 # range 9 around 24 MHz - - 10 # range 10 around 32 MHz - - 11 # range 11 around 48 MHz + msi-range: + required: true + type: int + default: 6 + description: | + MSI clock ranges + enum: + - 0 # range 0 around 100 kHz + - 1 # range 1 around 200 kHz + - 2 # range 2 around 400 kHz + - 3 # range 3 around 800 kHz + - 4 # range 4 around 1M Hz + - 5 # range 5 around 2 MHz + - 6 # range 6 around 4 MHz (reset value) + - 7 # range 7 around 8 MHz + - 8 # range 8 around 16 MHz + - 9 # range 9 around 24 MHz + - 10 # range 10 around 32 MHz + - 11 # range 11 around 48 MHz - msi-pll-mode: - type: boolean - description: | - MSI clock PLL enable - Enables the PLL part of the MSI clock source. + msi-pll-mode: + type: boolean + description: | + MSI clock PLL enable + Enables the PLL part of the MSI clock source. diff --git a/dts/bindings/clock/st,stm32-rcc.yaml b/dts/bindings/clock/st,stm32-rcc.yaml index ae85f077c38871..94aafc01a8509c 100644 --- a/dts/bindings/clock/st,stm32-rcc.yaml +++ b/dts/bindings/clock/st,stm32-rcc.yaml @@ -72,64 +72,64 @@ compatible: "st,stm32-rcc" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true - - "#clock-cells": - const: 2 - - clock-frequency: - required: true - type: int - description: | - default frequency in Hz for clock output - - ahb-prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 64 - - 128 - - 256 - - 512 - description: | - AHB prescaler. Defines actual core clock frequency (HCLK) - based on system frequency input. - The HCLK clocks CPU, AHB, memories and DMA. - - apb1-prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - apb2-prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - undershoot-prevention: - type: boolean - description: | - On some parts, it could be required to set up highest core frequencies - (>80MHz) in two steps in order to prevent undershoot. - This is done by applying an intermediate AHB prescaler before switching - System Clock source to PLL. Once done, prescaler is set back to expected - value. + reg: + required: true + + "#clock-cells": + const: 2 + + clock-frequency: + required: true + type: int + description: | + default frequency in Hz for clock output + + ahb-prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 64 + - 128 + - 256 + - 512 + description: | + AHB prescaler. Defines actual core clock frequency (HCLK) + based on system frequency input. + The HCLK clocks CPU, AHB, memories and DMA. + + apb1-prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + + apb2-prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + + undershoot-prevention: + type: boolean + description: | + On some parts, it could be required to set up highest core frequencies + (>80MHz) in two steps in order to prevent undershoot. + This is done by applying an intermediate AHB prescaler before switching + System Clock source to PLL. Once done, prescaler is set back to expected + value. clock-cells: - bus diff --git a/dts/bindings/clock/st,stm32f0-pll-clock.yaml b/dts/bindings/clock/st,stm32f0-pll-clock.yaml index 6f1a2350debf10..f35804b9a54b75 100644 --- a/dts/bindings/clock/st,stm32f0-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f0-pll-clock.yaml @@ -33,9 +33,9 @@ include: - otgfspre properties: - mul: - type: int - required: true - description: | - PLL multiplication factor for output clock - Valid range: 2 - 16 + mul: + type: int + required: true + description: | + PLL multiplication factor for output clock + Valid range: 2 - 16 diff --git a/dts/bindings/clock/st,stm32f1-pll-clock.yaml b/dts/bindings/clock/st,stm32f1-pll-clock.yaml index 51e8df771496ea..5b30f52d3e5c74 100644 --- a/dts/bindings/clock/st,stm32f1-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f1-pll-clock.yaml @@ -19,27 +19,27 @@ compatible: "st,stm32f1-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - mul: - type: int - required: true - description: | - Main PLL multiplication factor for VCO - Valid range: 2 - 16 - - xtpre: - type: boolean - description: | - Otpional HSE divider for PLL entry - - usbpre: - type: boolean - description: | - Otpional PLL output divisor to generate a 48MHz USB clock. - When set, PLL clock is not divided. - Otherwise, PLL output clock is divided by 1.5. + "#clock-cells": + const: 0 + + clocks: + required: true + + mul: + type: int + required: true + description: | + Main PLL multiplication factor for VCO + Valid range: 2 - 16 + + xtpre: + type: boolean + description: | + Otpional HSE divider for PLL entry + + usbpre: + type: boolean + description: | + Otpional PLL output divisor to generate a 48MHz USB clock. + When set, PLL clock is not divided. + Otherwise, PLL output clock is divided by 1.5. diff --git a/dts/bindings/clock/st,stm32f100-pll-clock.yaml b/dts/bindings/clock/st,stm32f100-pll-clock.yaml index 5789cf8cf3e85f..a861a445fefa53 100644 --- a/dts/bindings/clock/st,stm32f100-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f100-pll-clock.yaml @@ -28,9 +28,9 @@ include: - mul properties: - mul: - type: int - required: true - description: | - PLL multiplication factor for output clock - Valid range: 2 - 16 + mul: + type: int + required: true + description: | + PLL multiplication factor for output clock + Valid range: 2 - 16 diff --git a/dts/bindings/clock/st,stm32f105-pll-clock.yaml b/dts/bindings/clock/st,stm32f105-pll-clock.yaml index 73274f67aba5af..a503e247172dde 100644 --- a/dts/bindings/clock/st,stm32f105-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f105-pll-clock.yaml @@ -24,37 +24,37 @@ compatible: "st,stm32f105-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - mul: - type: int - required: true - description: | - Main PLL multiplication factor for VCO. - Note: For x6.5 multiplier value, please use "mul = <15>;" - enum: - - 4 # x4 - - 5 # x5 - - 6 # x6 - - 7 # x7 - - 8 # x8 - - 9 # x9 - - 15 # x6.5 - - prediv: - type: int - required: true - description: | - Configurable prescaler - Valid range: 1 - 16 - - otgfspre: - type: boolean - description: | - Otpional PLL output divisor to generate a 48MHz USB clock. - When set, PLL output clock is not divided. - Otherwise, PLL output clock is divided by 1.5. + "#clock-cells": + const: 0 + + clocks: + required: true + + mul: + type: int + required: true + description: | + Main PLL multiplication factor for VCO. + Note: For x6.5 multiplier value, please use "mul = <15>;" + enum: + - 4 # x4 + - 5 # x5 + - 6 # x6 + - 7 # x7 + - 8 # x8 + - 9 # x9 + - 15 # x6.5 + + prediv: + type: int + required: true + description: | + Configurable prescaler + Valid range: 1 - 16 + + otgfspre: + type: boolean + description: | + Otpional PLL output divisor to generate a 48MHz USB clock. + When set, PLL output clock is not divided. + Otherwise, PLL output clock is divided by 1.5. diff --git a/dts/bindings/clock/st,stm32f105-pll2-clock.yaml b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml index 4c5043484aa59d..b9b881d4f10743 100644 --- a/dts/bindings/clock/st,stm32f105-pll2-clock.yaml +++ b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml @@ -19,18 +19,18 @@ include: - mul properties: - mul: - type: int - required: true - description: | - PLL multiplication factor for output clock - enum: - - 8 - - 9 - - 10 - - 11 - - 12 - - 13 - - 14 - - 16 - - 20 + mul: + type: int + required: true + description: | + PLL multiplication factor for output clock + enum: + - 8 + - 9 + - 10 + - 11 + - 12 + - 13 + - 14 + - 16 + - 20 diff --git a/dts/bindings/clock/st,stm32f2-pll-clock.yaml b/dts/bindings/clock/st,stm32f2-pll-clock.yaml index 824f71cb2d047c..eda981c3e0709f 100644 --- a/dts/bindings/clock/st,stm32f2-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f2-pll-clock.yaml @@ -22,39 +22,39 @@ compatible: "st,stm32f2-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - div-m: - type: int - required: true - description: | - Division factor for the PLL input clock - Valid range: 2 - 63 - - mul-n: - type: int - required: true - description: | - PLL multiplication factor for VCO - Valid range: 192 - 432 - - div-p: - type: int - required: true - description: | - PLL division factor for PLLCLK - enum: - - 2 - - 4 - - 6 - - 8 - - div-q: - type: int - description: | - PLL division factor for PLL48CK - Valid range: 2 - 15 + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Division factor for the PLL input clock + Valid range: 2 - 63 + + mul-n: + type: int + required: true + description: | + PLL multiplication factor for VCO + Valid range: 192 - 432 + + div-p: + type: int + required: true + description: | + PLL division factor for PLLCLK + enum: + - 2 + - 4 + - 6 + - 8 + + div-q: + type: int + description: | + PLL division factor for PLL48CK + Valid range: 2 - 15 diff --git a/dts/bindings/clock/st,stm32f4-pll-clock.yaml b/dts/bindings/clock/st,stm32f4-pll-clock.yaml index 2037611bf202c3..cc7094a070abf6 100644 --- a/dts/bindings/clock/st,stm32f4-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f4-pll-clock.yaml @@ -24,40 +24,40 @@ compatible: "st,stm32f4-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - div-m: - type: int - required: true - description: | - Division factor for the PLL input clock - Valid range: 2 - 63 - - mul-n: - type: int - required: true - description: | - Main PLL multiplication factor for VCO - Valid range: 50 - 432 - - div-p: - type: int - required: true - description: | - Main PLL division factor for PLLSAI2CLK - enum: - - 2 - - 4 - - 6 - - 8 - - div-q: - type: int - description: | - Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number - generator clocks. - Valid range: 2 - 15 + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Division factor for the PLL input clock + Valid range: 2 - 63 + + mul-n: + type: int + required: true + description: | + Main PLL multiplication factor for VCO + Valid range: 50 - 432 + + div-p: + type: int + required: true + description: | + Main PLL division factor for PLLSAI2CLK + enum: + - 2 + - 4 + - 6 + - 8 + + div-q: + type: int + description: | + Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number + generator clocks. + Valid range: 2 - 15 diff --git a/dts/bindings/clock/st,stm32f7-pll-clock.yaml b/dts/bindings/clock/st,stm32f7-pll-clock.yaml index e3cac24824add8..163426ef7bd3e7 100644 --- a/dts/bindings/clock/st,stm32f7-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f7-pll-clock.yaml @@ -20,39 +20,39 @@ compatible: "st,stm32f7-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - div-m: - type: int - required: true - description: | - Division factor for the PLL input clock - Valid range: 2 - 63 - - mul-n: - type: int - required: true - description: | - PLL multiplication factor for VCO - Valid range: 50 - 432 - - div-p: - type: int - required: true - description: | - PLL division factor for PLLCLK - enum: - - 2 - - 4 - - 6 - - 8 - - div-q: - type: int - description: | - PLL division factor for PLL48CK - Valid range: 2 - 15 + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Division factor for the PLL input clock + Valid range: 2 - 63 + + mul-n: + type: int + required: true + description: | + PLL multiplication factor for VCO + Valid range: 50 - 432 + + div-p: + type: int + required: true + description: | + PLL division factor for PLLCLK + enum: + - 2 + - 4 + - 6 + - 8 + + div-q: + type: int + description: | + PLL division factor for PLL48CK + Valid range: 2 - 15 diff --git a/dts/bindings/clock/st,stm32g0-hsi-clock.yaml b/dts/bindings/clock/st,stm32g0-hsi-clock.yaml index 608395bfc8a970..a2d523fb0eb80a 100644 --- a/dts/bindings/clock/st,stm32g0-hsi-clock.yaml +++ b/dts/bindings/clock/st,stm32g0-hsi-clock.yaml @@ -23,19 +23,19 @@ compatible: "st,stm32g0-hsi-clock" include: [fixed-clock.yaml] properties: - hsi-div: - type: int - required: true - description: | - HSI clock divider. Configures the output HSI clock frequency (HSISYS), - It does not apply to HSI clk selected as peripheral source clock - (eg: RNG clk driven by HSI) - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 + hsi-div: + type: int + required: true + description: | + HSI clock divider. Configures the output HSI clock frequency (HSISYS), + It does not apply to HSI clk selected as peripheral source clock + (eg: RNG clk driven by HSI) + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 diff --git a/dts/bindings/clock/st,stm32g0-pll-clock.yaml b/dts/bindings/clock/st,stm32g0-pll-clock.yaml index c1bb6b65a319e2..c397b3c708b431 100644 --- a/dts/bindings/clock/st,stm32g0-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32g0-pll-clock.yaml @@ -24,41 +24,41 @@ compatible: "st,stm32g0-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 + "#clock-cells": + const: 0 - clocks: - required: true + clocks: + required: true - div-m: - type: int - required: true - description: | - Division factor for PLL input clock - Valid range: 1 - 8 + div-m: + type: int + required: true + description: | + Division factor for PLL input clock + Valid range: 1 - 8 - mul-n: - type: int - required: true - description: | - Main PLL multiplication factor for VCO - Valid range: 8 - 86 + mul-n: + type: int + required: true + description: | + Main PLL multiplication factor for VCO + Valid range: 8 - 86 - div-p: - type: int - description: | - PLL division factor for PLL P output - Valid range: 2 - 32 + div-p: + type: int + description: | + PLL division factor for PLL P output + Valid range: 2 - 32 - div-q: - type: int - description: | - PLL division factor for PLL Q output - Valid range: 2 - 8 + div-q: + type: int + description: | + PLL division factor for PLL Q output + Valid range: 2 - 8 - div-r: - type: int - required: true - description: | - PLL division factor for PLLCLK (system clock) - Valid range: 2 - 8 + div-r: + type: int + required: true + description: | + PLL division factor for PLLCLK (system clock) + Valid range: 2 - 8 diff --git a/dts/bindings/clock/st,stm32g4-pll-clock.yaml b/dts/bindings/clock/st,stm32g4-pll-clock.yaml index 227860830019d2..735895258ab2fe 100644 --- a/dts/bindings/clock/st,stm32g4-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32g4-pll-clock.yaml @@ -30,22 +30,22 @@ include: properties: - div-m: - type: int - required: true - description: | - Division factor for PLL input clock - Valid range: 1 - 16 - - mul-n: - type: int - required: true - description: | - Main PLL multiplication factor for VCO - Valid range: 8 - 127 - - div-p: - type: int - description: | - Main PLL division factor for ADC - Valid range: 2 - 31 + div-m: + type: int + required: true + description: | + Division factor for PLL input clock + Valid range: 1 - 16 + + mul-n: + type: int + required: true + description: | + Main PLL multiplication factor for VCO + Valid range: 8 - 127 + + div-p: + type: int + description: | + Main PLL division factor for ADC + Valid range: 2 - 31 diff --git a/dts/bindings/clock/st,stm32h7-hsi-clock.yaml b/dts/bindings/clock/st,stm32h7-hsi-clock.yaml index 4a92e86002983d..6706b5e195c20e 100644 --- a/dts/bindings/clock/st,stm32h7-hsi-clock.yaml +++ b/dts/bindings/clock/st,stm32h7-hsi-clock.yaml @@ -8,13 +8,13 @@ compatible: "st,stm32h7-hsi-clock" include: [fixed-clock.yaml] properties: - hsi-div: - type: int - required: true - description: | - HSI clock divider. Configures the output HSI clock frequency - enum: - - 1 # hsi_clk = 64MHz - - 2 # hsi_clk = 32MHz - - 4 # hsi_clk = 16MHz - - 8 # hsi_clk = 8MHz + hsi-div: + type: int + required: true + description: | + HSI clock divider. Configures the output HSI clock frequency + enum: + - 1 # hsi_clk = 64MHz + - 2 # hsi_clk = 32MHz + - 4 # hsi_clk = 16MHz + - 8 # hsi_clk = 8MHz diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml index 702e92cec71dca..ab6afacb880c08 100644 --- a/dts/bindings/clock/st,stm32h7-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml @@ -27,41 +27,41 @@ compatible: "st,stm32h7-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - div-m: - type: int - required: true - description: | - Division factor for PLLx - input clock - Valid range: 1 - 63 - - mul-n: - type: int - required: true - description: | - Main PLL multiplication factor for VCOx - Valid range: 4 - 512 - - div-p: - type: int - description: | - PLL division factor for pllx_p_ck - Valid range: 1 - 128 - - div-q: - type: int - description: | - PLL division factor for pllx_q_ck - Valid range: 1 - 128 - - div-r: - type: int - description: | - PLL division factor for pllx_r_ck - Valid range: 1 - 128 + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Division factor for PLLx + input clock + Valid range: 1 - 63 + + mul-n: + type: int + required: true + description: | + Main PLL multiplication factor for VCOx + Valid range: 4 - 512 + + div-p: + type: int + description: | + PLL division factor for pllx_p_ck + Valid range: 1 - 128 + + div-q: + type: int + description: | + PLL division factor for pllx_q_ck + Valid range: 1 - 128 + + div-r: + type: int + description: | + PLL division factor for pllx_r_ck + Valid range: 1 - 128 diff --git a/dts/bindings/clock/st,stm32h7-rcc.yaml b/dts/bindings/clock/st,stm32h7-rcc.yaml index 93a5266589b0b0..b0e6622e6d305e 100644 --- a/dts/bindings/clock/st,stm32h7-rcc.yaml +++ b/dts/bindings/clock/st,stm32h7-rcc.yaml @@ -33,93 +33,93 @@ compatible: "st,stm32h7-rcc" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true - - "#clock-cells": - const: 2 - - clock-frequency: - required: true - type: int - description: | - default frequency in Hz for clock output - - d1cpre: - type: int - required: true - enum: - - 1 - description: | - D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick) - lower than SYSCLK frequency (actual core frequency). - Zephyr doesn't make a difference today between these two clocks. - Changing this prescaler is not allowed until it is made possible to - use them independently in Zephyr clock subsystem. - - hpre: - type: int - required: true - description: | - D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 64 - - 128 - - 256 - - 512 - - d1ppre: - type: int - required: true - description: | - D1 domain, APB3 peripheral prescaler - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - d2ppre1: - type: int - required: true - description: | - D2 domain, APB1 peripheral prescaler - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - d2ppre2: - type: int - required: true - description: | - D2 domain, APB2 peripheral prescaler - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - d3ppre: - type: int - required: true - description: | - D3 domain, APB4 peripheral prescaler - enum: - - 1 - - 2 - - 4 - - 8 - - 16 + reg: + required: true + + "#clock-cells": + const: 2 + + clock-frequency: + required: true + type: int + description: | + default frequency in Hz for clock output + + d1cpre: + type: int + required: true + enum: + - 1 + description: | + D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick) + lower than SYSCLK frequency (actual core frequency). + Zephyr doesn't make a difference today between these two clocks. + Changing this prescaler is not allowed until it is made possible to + use them independently in Zephyr clock subsystem. + + hpre: + type: int + required: true + description: | + D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 64 + - 128 + - 256 + - 512 + + d1ppre: + type: int + required: true + description: | + D1 domain, APB3 peripheral prescaler + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + + d2ppre1: + type: int + required: true + description: | + D2 domain, APB1 peripheral prescaler + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + + d2ppre2: + type: int + required: true + description: | + D2 domain, APB2 peripheral prescaler + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + + d3ppre: + type: int + required: true + description: | + D3 domain, APB4 peripheral prescaler + enum: + - 1 + - 2 + - 4 + - 8 + - 16 clock-cells: - bus diff --git a/dts/bindings/clock/st,stm32l0-msi-clock.yaml b/dts/bindings/clock/st,stm32l0-msi-clock.yaml index 0d765bc9e902b0..29d8d1cdcb9c29 100644 --- a/dts/bindings/clock/st,stm32l0-msi-clock.yaml +++ b/dts/bindings/clock/st,stm32l0-msi-clock.yaml @@ -11,17 +11,17 @@ include: - msi-range properties: - msi-range: - required: true - type: int - default: 5 - description: | - MSI clock ranges - enum: - - 0 # range 0, around 65.536 kHz - - 1 # range 1, around 131.072 kHz - - 2 # range 2, around 262.144 kHz - - 3 # range 3, around 524.288 kHz - - 4 # range 4, around 1.048 MHz - - 5 # range 5, around 2.097 MHz (reset value) - - 6 # range 6, around 4.194 MHz + msi-range: + required: true + type: int + default: 5 + description: | + MSI clock ranges + enum: + - 0 # range 0, around 65.536 kHz + - 1 # range 1, around 131.072 kHz + - 2 # range 2, around 262.144 kHz + - 3 # range 3, around 524.288 kHz + - 4 # range 4, around 1.048 MHz + - 5 # range 5, around 2.097 MHz (reset value) + - 6 # range 6, around 4.194 MHz diff --git a/dts/bindings/clock/st,stm32l0-pll-clock.yaml b/dts/bindings/clock/st,stm32l0-pll-clock.yaml index c5caddd959d276..a62df8ffeae5f0 100644 --- a/dts/bindings/clock/st,stm32l0-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32l0-pll-clock.yaml @@ -20,40 +20,40 @@ compatible: "st,stm32l0-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - div: - type: int - required: true - description: | - PLL output division - enum: - - 2 - - 3 - - 4 - - mul: - type: int - required: true - description: | - PLL multiplication factor for VCO - The PLL VCO clock frequency must not exceed: - - 96 MHz when the product is in Range 1 - - 48 MHz when the product is in Range 2 - - 24 MHz when the product is in Range 3 - If the USB uses the PLL as clock source, the PLL VCO clock must be - programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2). - enum: - - 3 - - 4 - - 6 - - 8 - - 12 - - 16 - - 24 - - 32 - - 48 + "#clock-cells": + const: 0 + + clocks: + required: true + + div: + type: int + required: true + description: | + PLL output division + enum: + - 2 + - 3 + - 4 + + mul: + type: int + required: true + description: | + PLL multiplication factor for VCO + The PLL VCO clock frequency must not exceed: + - 96 MHz when the product is in Range 1 + - 48 MHz when the product is in Range 2 + - 24 MHz when the product is in Range 3 + If the USB uses the PLL as clock source, the PLL VCO clock must be + programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2). + enum: + - 3 + - 4 + - 6 + - 8 + - 12 + - 16 + - 24 + - 32 + - 48 diff --git a/dts/bindings/clock/st,stm32l4-pll-clock.yaml b/dts/bindings/clock/st,stm32l4-pll-clock.yaml index 3228e66a0eef43..32ed2c4ae13a25 100644 --- a/dts/bindings/clock/st,stm32l4-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32l4-pll-clock.yaml @@ -27,52 +27,52 @@ compatible: "st,stm32l4-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - div-m: - type: int - required: true - description: | - Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2) - input clock - Valid range: 1 - 8 - - mul-n: - type: int - required: true - description: | - Main PLL multiplication factor for VCO - Valid range: 8 - 86 - - div-p: - type: int - description: | - Main PLL division factor for PLLSAI3CLK - enum: - - 7 - - 17 - - div-q: - type: int - description: | - Main PLL division factor for PLL48M1CLK (48 MHz clock). - enum: - - 2 - - 4 - - 6 - - 8 - - div-r: - type: int - required: true - description: | - Main PLL division factor for PLLCLK (system clock) - enum: - - 2 - - 4 - - 6 - - 8 + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2) + input clock + Valid range: 1 - 8 + + mul-n: + type: int + required: true + description: | + Main PLL multiplication factor for VCO + Valid range: 8 - 86 + + div-p: + type: int + description: | + Main PLL division factor for PLLSAI3CLK + enum: + - 7 + - 17 + + div-q: + type: int + description: | + Main PLL division factor for PLL48M1CLK (48 MHz clock). + enum: + - 2 + - 4 + - 6 + - 8 + + div-r: + type: int + required: true + description: | + Main PLL division factor for PLLCLK (system clock) + enum: + - 2 + - 4 + - 6 + - 8 diff --git a/dts/bindings/clock/st,stm32u5-msi-clock.yaml b/dts/bindings/clock/st,stm32u5-msi-clock.yaml index 52398b3f5d62fd..87e72228d77caa 100644 --- a/dts/bindings/clock/st,stm32u5-msi-clock.yaml +++ b/dts/bindings/clock/st,stm32u5-msi-clock.yaml @@ -12,26 +12,26 @@ include: properties: - msi-range: - default: 4 - required: true - type: int - description: | - MSI clock ranges - enum: - - 0 # range 0 around 48 MHz - - 1 # range 1 around 24 MHz - - 2 # range 2 around 16 MHz - - 3 # range 3 around 12 MHz - - 4 # range 4 around 4 MHz (reset value) - - 5 # range 5 around 2 MHz - - 6 # range 6 around 1.33 MHz - - 7 # range 7 around 1 MHz - - 8 # range 8 around 3.072 MHz - - 9 # range 9 around 1.536 MHz - - 10 # range 10 around 1.024 MHz - - 11 # range 11 around 768 KHz - - 12 # range 12 around 400 KHz - - 13 # range 13 around 200 KHz - - 14 # range 14 around 133 KHz - - 15 # range 14 around 100 KHz + msi-range: + default: 4 + required: true + type: int + description: | + MSI clock ranges + enum: + - 0 # range 0 around 48 MHz + - 1 # range 1 around 24 MHz + - 2 # range 2 around 16 MHz + - 3 # range 3 around 12 MHz + - 4 # range 4 around 4 MHz (reset value) + - 5 # range 5 around 2 MHz + - 6 # range 6 around 1.33 MHz + - 7 # range 7 around 1 MHz + - 8 # range 8 around 3.072 MHz + - 9 # range 9 around 1.536 MHz + - 10 # range 10 around 1.024 MHz + - 11 # range 11 around 768 KHz + - 12 # range 12 around 400 KHz + - 13 # range 13 around 200 KHz + - 14 # range 14 around 133 KHz + - 15 # range 14 around 100 KHz diff --git a/dts/bindings/clock/st,stm32u5-pll-clock.yaml b/dts/bindings/clock/st,stm32u5-pll-clock.yaml index 7396d939d88dd8..6185050eac6906 100644 --- a/dts/bindings/clock/st,stm32u5-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32u5-pll-clock.yaml @@ -30,44 +30,44 @@ include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - div-m: - type: int - required: true - description: | - Prescaler for PLLx - input clock - Valid range: 1 - 16 - - mul-n: - type: int - required: true - description: | - PLLx multiplication factor for VCO - Valid range: 4 - 512 - - div-p: - type: int - description: | - PLLx DIVP division factor - Valid range: 1 - 128 - - div-q: - type: int - description: | - PLLx DIVQ division factor - Valid range: 1 - 128 - - div-r: - type: int - required: true - description: | - PLLx DIVR division factor - On PLL1, only division by 1 and even division values are allowed. - No restrictions for PLL2 and PLL3 - Valid range: 1 - 128 + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Prescaler for PLLx + input clock + Valid range: 1 - 16 + + mul-n: + type: int + required: true + description: | + PLLx multiplication factor for VCO + Valid range: 4 - 512 + + div-p: + type: int + description: | + PLLx DIVP division factor + Valid range: 1 - 128 + + div-q: + type: int + description: | + PLLx DIVQ division factor + Valid range: 1 - 128 + + div-r: + type: int + required: true + description: | + PLLx DIVR division factor + On PLL1, only division by 1 and even division values are allowed. + No restrictions for PLL2 and PLL3 + Valid range: 1 - 128 diff --git a/dts/bindings/clock/st,stm32u5-rcc.yaml b/dts/bindings/clock/st,stm32u5-rcc.yaml index 5aa4783b910eaf..3cf2aa064a3f9b 100644 --- a/dts/bindings/clock/st,stm32u5-rcc.yaml +++ b/dts/bindings/clock/st,stm32u5-rcc.yaml @@ -14,12 +14,12 @@ include: properties: - apb3-prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 + apb3-prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 diff --git a/dts/bindings/clock/st,stm32wb-pll-clock.yaml b/dts/bindings/clock/st,stm32wb-pll-clock.yaml index e7dd25c91edaee..8c20dd1350f9da 100644 --- a/dts/bindings/clock/st,stm32wb-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32wb-pll-clock.yaml @@ -29,41 +29,41 @@ compatible: "st,stm32wb-pll-clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 0 - - clocks: - required: true - - div-m: - type: int - required: true - description: | - Main PLL division factor for PLL input clock - Valid range: 1 - 8 - - mul-n: - type: int - required: true - description: | - Main PLL multiplication factor for VCO - Valid range: 6 - 127 - - div-p: - type: int - description: | - Main PLL division factor for PLLPCLK - Valid range: 2 - 32 - - div-q: - type: int - description: | - Main PLL division factor for PLLQCLK - Valid range: 2 - 8 - - div-r: - type: int - required: true - description: | - Main PLL division factor for PLLRCLK (system clock) - Valid range: 2 - 8 + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Main PLL division factor for PLL input clock + Valid range: 1 - 8 + + mul-n: + type: int + required: true + description: | + Main PLL multiplication factor for VCO + Valid range: 6 - 127 + + div-p: + type: int + description: | + Main PLL division factor for PLLPCLK + Valid range: 2 - 32 + + div-q: + type: int + description: | + Main PLL division factor for PLLQCLK + Valid range: 2 - 8 + + div-r: + type: int + required: true + description: | + Main PLL division factor for PLLRCLK (system clock) + Valid range: 2 - 8 diff --git a/dts/bindings/clock/st,stm32wb-rcc.yaml b/dts/bindings/clock/st,stm32wb-rcc.yaml index 849ef945e3b6fc..6867f97fd00c63 100644 --- a/dts/bindings/clock/st,stm32wb-rcc.yaml +++ b/dts/bindings/clock/st,stm32wb-rcc.yaml @@ -13,64 +13,64 @@ include: - ahb-prescaler properties: - cpu1-prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 8 - - 10 - - 16 - - 32 - - 64 - - 128 - - 256 - - 512 - description: | - CPU1 prescaler. Sets a HCLK1 frequency (Core frequency) - lower than SYSCLK frequency. - The HCLK1 clocks CPU1, AHB1, AHB2, AHB3 and SRAM1. + cpu1-prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 8 + - 10 + - 16 + - 32 + - 64 + - 128 + - 256 + - 512 + description: | + CPU1 prescaler. Sets a HCLK1 frequency (Core frequency) + lower than SYSCLK frequency. + The HCLK1 clocks CPU1, AHB1, AHB2, AHB3 and SRAM1. - cpu2-prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 - - 256 - - 512 - description: | - CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2. - (A.K.A C2HPRE) + cpu2-prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + - 256 + - 512 + description: | + CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2. + (A.K.A C2HPRE) - ahb4-prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 - - 256 - - 512 - description: | - HCLK4 shared prescaler (AHB4, Flash memory and SRAM2). - (A.K.A SHDHPRE) + ahb4-prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + - 256 + - 512 + description: | + HCLK4 shared prescaler (AHB4, Flash memory and SRAM2). + (A.K.A SHDHPRE) clock-cells: - bus diff --git a/dts/bindings/clock/st,stm32wl-hse-clock.yaml b/dts/bindings/clock/st,stm32wl-hse-clock.yaml index f2eb28bf1cb530..c1bc2199b79e45 100644 --- a/dts/bindings/clock/st,stm32wl-hse-clock.yaml +++ b/dts/bindings/clock/st,stm32wl-hse-clock.yaml @@ -8,14 +8,14 @@ compatible: "st,stm32wl-hse-clock" include: [fixed-clock.yaml] properties: - hse-tcxo: - type: boolean - description: | - When set, TCXO is selected as external source clock for HSE. - Otherwise, external cyrstal is selected as HSE source clock. + hse-tcxo: + type: boolean + description: | + When set, TCXO is selected as external source clock for HSE. + Otherwise, external cyrstal is selected as HSE source clock. - hse-div2: - type: boolean - description: | - When set HSE output clock is divided by 2. - Otherwise, no prescaler is used. + hse-div2: + type: boolean + description: | + When set HSE output clock is divided by 2. + Otherwise, no prescaler is used. diff --git a/dts/bindings/clock/st,stm32wl-rcc.yaml b/dts/bindings/clock/st,stm32wl-rcc.yaml index 5b2fb051b70482..882493ea8ea73f 100644 --- a/dts/bindings/clock/st,stm32wl-rcc.yaml +++ b/dts/bindings/clock/st,stm32wl-rcc.yaml @@ -14,40 +14,40 @@ include: - cpu2-prescaler properties: - cpu2-prescaler: - type: int - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 - - 256 - - 512 - description: | - CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2. - (A.K.A C2HPRE) + cpu2-prescaler: + type: int + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + - 256 + - 512 + description: | + CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2. + (A.K.A C2HPRE) - ahb3-prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 - - 256 - - 512 - description: | - HCLK3 shared prescaler (AHB3, Flash memory, SRAM1 and SRAM2). - (A.K.A SHDHPRE) + ahb3-prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + - 256 + - 512 + description: | + HCLK3 shared prescaler (AHB3, Flash memory, SRAM1 and SRAM2). + (A.K.A SHDHPRE) clock-cells: - bus diff --git a/dts/bindings/coredump/zephyr,coredump.yaml b/dts/bindings/coredump/zephyr,coredump.yaml index a24e5963c60397..7a0f95eb51aac4 100644 --- a/dts/bindings/coredump/zephyr,coredump.yaml +++ b/dts/bindings/coredump/zephyr,coredump.yaml @@ -8,25 +8,25 @@ compatible: "zephyr,coredump" description: Pseudo-device to help capturing desired data into core dumps properties: - memory-regions: - type: array - description: Start address and size of memory regions to be collected in a core dump + memory-regions: + type: array + description: Start address and size of memory regions to be collected in a core dump - coredump-type: - required: true - type: string - description: | - Designate which type of coredump device this will be. - A device of type COREDUMP_TYPE_MEMCPY can directly memcpy the provided memory-regions - into the coredump. The memory-regions array can contain 0 or more entries, and more - regions can be added at runtime through the coredump_device_register_memory API. - A device of type COREDUMP_TYPE_CALLBACK must specify exactly one entry in the - memory-regions array with a size of 0 and a desired size. The coredump device will - statically allocate a block of memory of the desired size and provide a callback with a - pointer to that memory which will be invoked at the time of a dump. This allows a consumer - to add data into the coredump that may not be directly accessible through a memcpy and/or - provides an opportunity to manipulate data for inclusion in the dump. The - coredump_device_register_memory API is not available for a device of this type. - enum: - - "COREDUMP_TYPE_MEMCPY" - - "COREDUMP_TYPE_CALLBACK" + coredump-type: + required: true + type: string + description: | + Designate which type of coredump device this will be. + A device of type COREDUMP_TYPE_MEMCPY can directly memcpy the provided memory-regions + into the coredump. The memory-regions array can contain 0 or more entries, and more + regions can be added at runtime through the coredump_device_register_memory API. + A device of type COREDUMP_TYPE_CALLBACK must specify exactly one entry in the + memory-regions array with a size of 0 and a desired size. The coredump device will + statically allocate a block of memory of the desired size and provide a callback with a + pointer to that memory which will be invoked at the time of a dump. This allows a consumer + to add data into the coredump that may not be directly accessible through a memcpy and/or + provides an opportunity to manipulate data for inclusion in the dump. The + coredump_device_register_memory API is not available for a device of this type. + enum: + - "COREDUMP_TYPE_MEMCPY" + - "COREDUMP_TYPE_CALLBACK" diff --git a/dts/bindings/counter/espressif,esp32-rtc-timer.yaml b/dts/bindings/counter/espressif,esp32-rtc-timer.yaml index cf1afec2e3d9d1..86d5cd6887630a 100644 --- a/dts/bindings/counter/espressif,esp32-rtc-timer.yaml +++ b/dts/bindings/counter/espressif,esp32-rtc-timer.yaml @@ -16,10 +16,10 @@ description: | include: base.yaml properties: - slow-clk-freq: - description: | - The slow clock input frequency for the RTC Timer. - type: int - required: true + slow-clk-freq: + description: | + The slow clock input frequency for the RTC Timer. + type: int + required: true compatible: "espressif,esp32-rtc-timer" diff --git a/dts/bindings/counter/espressif,esp32-timer.yaml b/dts/bindings/counter/espressif,esp32-timer.yaml index df66a5845d15f9..6b0056e8f34689 100644 --- a/dts/bindings/counter/espressif,esp32-timer.yaml +++ b/dts/bindings/counter/espressif,esp32-timer.yaml @@ -23,34 +23,34 @@ description: | include: base.yaml properties: - group: - description: | - The Timer Group index to which a timer belongs. - type: int - required: true - enum: - - 0 - - 1 - - index: - description: | - The index that identifies a timer within a Timer Group. - type: int - required: true - enum: - - 0 - - 1 - - prescaler: - description: | - The prescaler value defines the factor by which the APB clock will be - divided. The outcome of which serves as clock reference to the Timer - itself. - - The allowed values for this property are in the range [2..65535]. - Values above that range will be 16-bit-masked. Values 0 and 1 will be - forced to 2. - type: int - default: 2 + group: + description: | + The Timer Group index to which a timer belongs. + type: int + required: true + enum: + - 0 + - 1 + + index: + description: | + The index that identifies a timer within a Timer Group. + type: int + required: true + enum: + - 0 + - 1 + + prescaler: + description: | + The prescaler value defines the factor by which the APB clock will be + divided. The outcome of which serves as clock reference to the Timer + itself. + + The allowed values for this property are in the range [2..65535]. + Values above that range will be 16-bit-masked. Values 0 and 1 will be + forced to 2. + type: int + default: 2 compatible: "espressif,esp32-timer" diff --git a/dts/bindings/counter/intel,ace-art-counter.yaml b/dts/bindings/counter/intel,ace-art-counter.yaml index 632b952c941a04..9a5fcebcdb961f 100644 --- a/dts/bindings/counter/intel,ace-art-counter.yaml +++ b/dts/bindings/counter/intel,ace-art-counter.yaml @@ -6,4 +6,4 @@ include: base.yaml properties: reg: - required: true + required: true diff --git a/dts/bindings/counter/intel,ace-rtc-counter.yaml b/dts/bindings/counter/intel,ace-rtc-counter.yaml index 9c9f43645d54ad..b30eb5764cefe2 100644 --- a/dts/bindings/counter/intel,ace-rtc-counter.yaml +++ b/dts/bindings/counter/intel,ace-rtc-counter.yaml @@ -6,4 +6,4 @@ include: base.yaml properties: reg: - required: true + required: true diff --git a/dts/bindings/counter/nxp,imx-qtmr.yaml b/dts/bindings/counter/nxp,imx-qtmr.yaml index 22cd53d66e2fdf..c48e10ce33e281 100644 --- a/dts/bindings/counter/nxp,imx-qtmr.yaml +++ b/dts/bindings/counter/nxp,imx-qtmr.yaml @@ -8,8 +8,8 @@ compatible: "nxp,imx-qtmr" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/cpu/altr,nios2f.yaml b/dts/bindings/cpu/altr,nios2f.yaml index 6b101dcfb705e2..ab9ef796ba322e 100644 --- a/dts/bindings/cpu/altr,nios2f.yaml +++ b/dts/bindings/cpu/altr,nios2f.yaml @@ -9,7 +9,7 @@ include: [interrupt-controller.yaml, base.yaml] properties: "#interrupt-cells": - const: 1 + const: 1 interrupt-cells: - irq diff --git a/dts/bindings/cpu/cdns,tensilica-xtensa-lx6.yaml b/dts/bindings/cpu/cdns,tensilica-xtensa-lx6.yaml index 391dd22acdb18e..0896675f2638e1 100644 --- a/dts/bindings/cpu/cdns,tensilica-xtensa-lx6.yaml +++ b/dts/bindings/cpu/cdns,tensilica-xtensa-lx6.yaml @@ -8,6 +8,6 @@ compatible: "cdns,tensilica-xtensa-lx6" include: cpu.yaml properties: - clock-source: - type: int - description: cpu clock source + clock-source: + type: int + description: cpu clock source diff --git a/dts/bindings/cpu/cdns,tensilica-xtensa-lx7.yaml b/dts/bindings/cpu/cdns,tensilica-xtensa-lx7.yaml index e5cfb9caae3253..f096aa3bd19bdd 100644 --- a/dts/bindings/cpu/cdns,tensilica-xtensa-lx7.yaml +++ b/dts/bindings/cpu/cdns,tensilica-xtensa-lx7.yaml @@ -8,6 +8,6 @@ compatible: "cdns,tensilica-xtensa-lx7" include: cpu.yaml properties: - clock-source: - type: int - description: cpu clock source + clock-source: + type: int + description: cpu clock source diff --git a/dts/bindings/cpu/cpu.yaml b/dts/bindings/cpu/cpu.yaml index d16f093c411b96..71a0453b7393c3 100644 --- a/dts/bindings/cpu/cpu.yaml +++ b/dts/bindings/cpu/cpu.yaml @@ -6,15 +6,15 @@ include: base.yaml properties: - clock-frequency: - type: int - description: Clock frequency in Hz - cpu-power-states: - type: phandles - description: List of power management states supported by this cpu - i-cache-line-size: - type: int - description: i-cache line size - d-cache-line-size: - type: int - description: d-cache line size + clock-frequency: + type: int + description: Clock frequency in Hz + cpu-power-states: + type: phandles + description: List of power management states supported by this cpu + i-cache-line-size: + type: int + description: i-cache line size + d-cache-line-size: + type: int + description: d-cache line size diff --git a/dts/bindings/cpu/espressif,riscv.yaml b/dts/bindings/cpu/espressif,riscv.yaml index 055096ce6b348a..5894435c061486 100644 --- a/dts/bindings/cpu/espressif,riscv.yaml +++ b/dts/bindings/cpu/espressif,riscv.yaml @@ -8,6 +8,6 @@ compatible: "espressif,riscv" include: cpu.yaml properties: - clock-source: - type: int - description: cpu clock source + clock-source: + type: int + description: cpu clock source diff --git a/dts/bindings/cpu/qemu,nios2-zephyr.yaml b/dts/bindings/cpu/qemu,nios2-zephyr.yaml index 654bc982a9b82a..0db82f44e10658 100644 --- a/dts/bindings/cpu/qemu,nios2-zephyr.yaml +++ b/dts/bindings/cpu/qemu,nios2-zephyr.yaml @@ -9,7 +9,7 @@ include: [interrupt-controller.yaml, base.yaml] properties: "#interrupt-cells": - const: 1 + const: 1 interrupt-cells: - irq diff --git a/dts/bindings/crypto/arm,cryptocell-310.yaml b/dts/bindings/crypto/arm,cryptocell-310.yaml index 514033aac90913..010c2d08583c3b 100644 --- a/dts/bindings/crypto/arm,cryptocell-310.yaml +++ b/dts/bindings/crypto/arm,cryptocell-310.yaml @@ -8,8 +8,8 @@ compatible: "arm,cryptocell-310" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/crypto/arm,cryptocell-312.yaml b/dts/bindings/crypto/arm,cryptocell-312.yaml index d2ff9b82ae6009..76eadcf197eae8 100644 --- a/dts/bindings/crypto/arm,cryptocell-312.yaml +++ b/dts/bindings/crypto/arm,cryptocell-312.yaml @@ -8,8 +8,8 @@ compatible: "arm,cryptocell-312" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/crypto/intel,adsp-sha.yaml b/dts/bindings/crypto/intel,adsp-sha.yaml index a36a13c25141d2..abc269c14aa2ab 100644 --- a/dts/bindings/crypto/intel,adsp-sha.yaml +++ b/dts/bindings/crypto/intel,adsp-sha.yaml @@ -8,5 +8,5 @@ compatible: "intel,adsp-sha" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/crypto/nordic,nrf-cc310.yaml b/dts/bindings/crypto/nordic,nrf-cc310.yaml index c140dd817498c9..8ab48636848285 100644 --- a/dts/bindings/crypto/nordic,nrf-cc310.yaml +++ b/dts/bindings/crypto/nordic,nrf-cc310.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-cc310" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/crypto/nordic,nrf-cc312.yaml b/dts/bindings/crypto/nordic,nrf-cc312.yaml index ab0541e900916f..bc0b227e7e5b83 100644 --- a/dts/bindings/crypto/nordic,nrf-cc312.yaml +++ b/dts/bindings/crypto/nordic,nrf-cc312.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-cc312" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/crypto/nordic,nrf-ccm.yaml b/dts/bindings/crypto/nordic,nrf-ccm.yaml index d591dfc9aa58ae..6a43ebb758e091 100644 --- a/dts/bindings/crypto/nordic,nrf-ccm.yaml +++ b/dts/bindings/crypto/nordic,nrf-ccm.yaml @@ -8,15 +8,15 @@ compatible: "nordic,nrf-ccm" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - length-field-length-8-bits: - type: boolean - description: | - Indicates whether the CCM peripheral supports the extended length - (8 bits) of the LENGTH field in encrypted/decrypted packets. - If not set, only the default length (5 bits) is supported. + length-field-length-8-bits: + type: boolean + description: | + Indicates whether the CCM peripheral supports the extended length + (8 bits) of the LENGTH field in encrypted/decrypted packets. + If not set, only the default length (5 bits) is supported. diff --git a/dts/bindings/crypto/nordic,nrf-ecb.yaml b/dts/bindings/crypto/nordic,nrf-ecb.yaml index aefcaab2e71787..4df050aaa60f5a 100644 --- a/dts/bindings/crypto/nordic,nrf-ecb.yaml +++ b/dts/bindings/crypto/nordic,nrf-ecb.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-ecb" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/crypto/nuvoton,npcx-sha.yaml b/dts/bindings/crypto/nuvoton,npcx-sha.yaml index 74693a51d67b43..2670855d45b4d5 100644 --- a/dts/bindings/crypto/nuvoton,npcx-sha.yaml +++ b/dts/bindings/crypto/nuvoton,npcx-sha.yaml @@ -8,5 +8,5 @@ compatible: "nuvoton,npcx-sha" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/crypto/silabs,gecko-semailbox.yaml b/dts/bindings/crypto/silabs,gecko-semailbox.yaml index 0ee1a55e2736c7..ef194af5fe8273 100644 --- a/dts/bindings/crypto/silabs,gecko-semailbox.yaml +++ b/dts/bindings/crypto/silabs,gecko-semailbox.yaml @@ -8,8 +8,8 @@ compatible: "silabs,gecko-semailbox" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/crypto/st,stm32-crypto-common.yaml b/dts/bindings/crypto/st,stm32-crypto-common.yaml index 359997006796c0..b779982f2b5a72 100644 --- a/dts/bindings/crypto/st,stm32-crypto-common.yaml +++ b/dts/bindings/crypto/st,stm32-crypto-common.yaml @@ -4,11 +4,11 @@ include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/dac/atmel,sam-dac.yaml b/dts/bindings/dac/atmel,sam-dac.yaml index b6c1821dd806a5..6ca131438a9aea 100644 --- a/dts/bindings/dac/atmel,sam-dac.yaml +++ b/dts/bindings/dac/atmel,sam-dac.yaml @@ -6,30 +6,30 @@ description: Atmel SAM family DAC compatible: "atmel,sam-dac" include: - - name: dac-controller.yaml - - name: pinctrl-device.yaml + - name: dac-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true - - peripheral-id: - type: int - required: true - description: | - peripheral ID - - prescaler: - type: int - default: 15 - description: | - Peripheral Clock to DAC Clock Ratio. Prescaler value is calcuated as - PRESCAL = (MCK / DACClock) - 2. Should be in range from 0 to 15. The - value will be written to DACC_MR.PRESCALER bit-field. The property is - applicable only to SAME70, SAMV71 series devices. - - "#io-channel-cells": - const: 1 + reg: + required: true + + peripheral-id: + type: int + required: true + description: | + peripheral ID + + prescaler: + type: int + default: 15 + description: | + Peripheral Clock to DAC Clock Ratio. Prescaler value is calcuated as + PRESCAL = (MCK / DACClock) - 2. Should be in range from 0 to 15. The + value will be written to DACC_MR.PRESCALER bit-field. The property is + applicable only to SAME70, SAMV71 series devices. + + "#io-channel-cells": + const: 1 io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/atmel,sam0-dac.yaml b/dts/bindings/dac/atmel,sam0-dac.yaml index 6794081f06983d..05ffd62d33742a 100644 --- a/dts/bindings/dac/atmel,sam0-dac.yaml +++ b/dts/bindings/dac/atmel,sam0-dac.yaml @@ -6,26 +6,26 @@ description: Atmel SAM0 family DAC compatible: "atmel,sam0-dac" include: - - name: dac-controller.yaml - - name: pinctrl-device.yaml + - name: dac-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - clock-names: - required: true + clock-names: + required: true - reference: - type: string - description: Reference voltage source - enum: - - "intref" - - "vddana" - - "vrefa" + reference: + type: string + description: Reference voltage source + enum: + - "intref" + - "vddana" + - "vrefa" - "#io-channel-cells": - const: 0 + "#io-channel-cells": + const: 0 diff --git a/dts/bindings/dac/dac-controller.yaml b/dts/bindings/dac/dac-controller.yaml index 12121f8c5bb404..6a7d91f2dce729 100644 --- a/dts/bindings/dac/dac-controller.yaml +++ b/dts/bindings/dac/dac-controller.yaml @@ -6,6 +6,6 @@ include: base.yaml properties: - "#io-channel-cells": - type: int - required: true + "#io-channel-cells": + type: int + required: true diff --git a/dts/bindings/dac/espressif,esp32-dac.yaml b/dts/bindings/dac/espressif,esp32-dac.yaml index f86aecc15684b6..39c63d7642e715 100644 --- a/dts/bindings/dac/espressif,esp32-dac.yaml +++ b/dts/bindings/dac/espressif,esp32-dac.yaml @@ -46,8 +46,8 @@ include: [dac-controller.yaml] properties: - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/gd,gd32-dac.yaml b/dts/bindings/dac/gd,gd32-dac.yaml index a64f852fd31bbd..868b23481a6600 100644 --- a/dts/bindings/dac/gd,gd32-dac.yaml +++ b/dts/bindings/dac/gd,gd32-dac.yaml @@ -8,27 +8,27 @@ compatible: "gd,gd32-dac" include: [dac-controller.yaml, reset-device.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - resets: - required: true + resets: + required: true - clocks: - required: true + clocks: + required: true - num-channels: - type: int - description: Number of DAC output channels - required: true + num-channels: + type: int + description: Number of DAC output channels + required: true - reset-val: - type: int - default: 0 - description: Reset value of DAC output. Defaults to 0, the SoC default. + reset-val: + type: int + default: 0 + description: Reset value of DAC output. Defaults to 0, the SoC default. - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/microchip,mcp4725.yaml b/dts/bindings/dac/microchip,mcp4725.yaml index 4a33ee37a10fb7..c720b591808026 100644 --- a/dts/bindings/dac/microchip,mcp4725.yaml +++ b/dts/bindings/dac/microchip,mcp4725.yaml @@ -8,8 +8,8 @@ compatible: "microchip,mcp4725" include: [dac-controller.yaml, i2c-device.yaml] properties: - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/microchip,mcp4728.yaml b/dts/bindings/dac/microchip,mcp4728.yaml index 12e2a7b9f5c449..0a0d8d291c72b4 100644 --- a/dts/bindings/dac/microchip,mcp4728.yaml +++ b/dts/bindings/dac/microchip,mcp4728.yaml @@ -5,39 +5,39 @@ compatible: "microchip,mcp4728" include: [dac-controller.yaml, i2c-device.yaml] properties: - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 - voltage_reference: - type: array - required: true - description: | - DAC voltage reference select. - 0 - Vdd - 1 - Internal voltage reference (2.048V) - Note: array entries correspond to the successive channels + voltage_reference: + type: array + required: true + description: | + DAC voltage reference select. + 0 - Vdd + 1 - Internal voltage reference (2.048V) + Note: array entries correspond to the successive channels - power_down_mode: - type: array - required: true - description: | - Power-down mode select. - 0 - normal mode - 1 - Vout is loaded with 1 kOhm resistor to ground - 2 - Vout is loaded 100 kOhm resistor to ground - 3 - Vout is loaded with 500 kOhm resistor to ground - Note: with values bigger than 0 most of channel circuits are powered off - Note: array entries correspond to the successive channels + power_down_mode: + type: array + required: true + description: | + Power-down mode select. + 0 - normal mode + 1 - Vout is loaded with 1 kOhm resistor to ground + 2 - Vout is loaded 100 kOhm resistor to ground + 3 - Vout is loaded with 500 kOhm resistor to ground + Note: with values bigger than 0 most of channel circuits are powered off + Note: array entries correspond to the successive channels - gain: - type: array - default: [0, 0, 0, 0] - description: | - Gain selection bit. - 0 = x1 (gain of 1) - 1 = x2 (gain of 2) - Note: applicable only when internal Vref is selected - Note: array entries correspond to the successive channels + gain: + type: array + default: [0, 0, 0, 0] + description: | + Gain selection bit. + 0 = x1 (gain of 1) + 1 = x2 (gain of 2) + Note: applicable only when internal Vref is selected + Note: array entries correspond to the successive channels io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/nxp,kinetis-dac.yaml b/dts/bindings/dac/nxp,kinetis-dac.yaml index ade7f8b19db482..7c3f472a4d7640 100644 --- a/dts/bindings/dac/nxp,kinetis-dac.yaml +++ b/dts/bindings/dac/nxp,kinetis-dac.yaml @@ -8,20 +8,20 @@ compatible: "nxp,kinetis-dac" include: dac-controller.yaml properties: - reg: - required: true + reg: + required: true - voltage-reference: - type: int - required: true - description: DAC voltage reference select + voltage-reference: + type: int + required: true + description: DAC voltage reference select - low-power-mode: - type: boolean - description: Enable low-power mode + low-power-mode: + type: boolean + description: Enable low-power mode - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/nxp,kinetis-dac32.yaml b/dts/bindings/dac/nxp,kinetis-dac32.yaml index 16bfed7bee74c6..ad1e7dec643ce1 100644 --- a/dts/bindings/dac/nxp,kinetis-dac32.yaml +++ b/dts/bindings/dac/nxp,kinetis-dac32.yaml @@ -8,24 +8,24 @@ compatible: "nxp,kinetis-dac32" include: [dac-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - voltage-reference: - type: int - required: true - description: DAC voltage reference select + voltage-reference: + type: int + required: true + description: DAC voltage reference select - low-power-mode: - type: boolean - description: Enable low-power mode + low-power-mode: + type: boolean + description: Enable low-power mode - buffered: - type: boolean - description: Enable output buffer + buffered: + type: boolean + description: Enable output buffer - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/st,stm32-dac.yaml b/dts/bindings/dac/st,stm32-dac.yaml index c339bbb70a1d4b..c5c8321cbef908 100644 --- a/dts/bindings/dac/st,stm32-dac.yaml +++ b/dts/bindings/dac/st,stm32-dac.yaml @@ -8,20 +8,20 @@ compatible: "st,stm32-dac" include: [dac-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/ti,dacx0508-base.yaml b/dts/bindings/dac/ti,dacx0508-base.yaml index 6899dc90e0e876..9ee4a376092fe6 100644 --- a/dts/bindings/dac/ti,dacx0508-base.yaml +++ b/dts/bindings/dac/ti,dacx0508-base.yaml @@ -4,80 +4,80 @@ include: [dac-controller.yaml, spi-device.yaml] properties: - voltage-reference: - type: int - required: true - description: | - DAC voltage reference select + voltage-reference: + type: int + required: true + description: | + DAC voltage reference select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - channel0-gain: - type: int - required: true - description: | - Channel 0 gain select + channel0-gain: + type: int + required: true + description: | + Channel 0 gain select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - channel1-gain: - type: int - required: true - description: | - Channel 1 gain select + channel1-gain: + type: int + required: true + description: | + Channel 1 gain select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - channel2-gain: - type: int - required: true - description: | - Channel 2 gain select + channel2-gain: + type: int + required: true + description: | + Channel 2 gain select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - channel3-gain: - type: int - required: true - description: | - Channel 3 gain select + channel3-gain: + type: int + required: true + description: | + Channel 3 gain select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - channel4-gain: - type: int - required: true - description: | - Channel 4 gain select + channel4-gain: + type: int + required: true + description: | + Channel 4 gain select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - channel5-gain: - type: int - required: true - description: | - Channel 5 gain select + channel5-gain: + type: int + required: true + description: | + Channel 5 gain select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - channel6-gain: - type: int - required: true - description: | - Channel 6 gain select + channel6-gain: + type: int + required: true + description: | + Channel 6 gain select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - channel7-gain: - type: int - required: true - description: | - Channel 7 gain select + channel7-gain: + type: int + required: true + description: | + Channel 7 gain select - See constants in dt-bindings/dac/dacx0508.h. + See constants in dt-bindings/dac/dacx0508.h. - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - output + - output diff --git a/dts/bindings/dac/ti,dacx3608-base.yaml b/dts/bindings/dac/ti,dacx3608-base.yaml index 660b75d94cea26..7932427a6764e2 100644 --- a/dts/bindings/dac/ti,dacx3608-base.yaml +++ b/dts/bindings/dac/ti,dacx3608-base.yaml @@ -4,8 +4,8 @@ include: [dac-controller.yaml, i2c-device.yaml] properties: - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - output + - output diff --git a/dts/bindings/dai/intel,dai-dmic.yaml b/dts/bindings/dai/intel,dai-dmic.yaml index 1656b8a26ec642..44c886b0d6a887 100644 --- a/dts/bindings/dai/intel,dai-dmic.yaml +++ b/dts/bindings/dai/intel,dai-dmic.yaml @@ -8,13 +8,13 @@ compatible: "intel,dai-dmic" include: base.yaml properties: - reg: - required: true + reg: + required: true - shim: - type: int - required: true + shim: + type: int + required: true - fifo: - type: int - required: true + fifo: + type: int + required: true diff --git a/dts/bindings/debug/arm,itm.yaml b/dts/bindings/debug/arm,itm.yaml index 0c5dccb15babdc..9914aeb1bee7a4 100644 --- a/dts/bindings/debug/arm,itm.yaml +++ b/dts/bindings/debug/arm,itm.yaml @@ -7,6 +7,6 @@ include: [base.yaml, pinctrl-device.yaml] properties: - swo-ref-frequency: - type: int - description: Reference clock frequency for SWO if different than CPU clock. + swo-ref-frequency: + type: int + description: Reference clock frequency for SWO if different than CPU clock. diff --git a/dts/bindings/dfpmcch/intel,adsp-dfpmcch.yaml b/dts/bindings/dfpmcch/intel,adsp-dfpmcch.yaml index 7ace63b336ea21..83546c8e7c8b89 100644 --- a/dts/bindings/dfpmcch/intel,adsp-dfpmcch.yaml +++ b/dts/bindings/dfpmcch/intel,adsp-dfpmcch.yaml @@ -9,5 +9,5 @@ compatible: "intel,adsp-dfpmcch" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/dfpmccu/intel,adsp-dfpmccu.yaml b/dts/bindings/dfpmccu/intel,adsp-dfpmccu.yaml index b61c2dcc0aec6e..8fa6c92ce3d813 100644 --- a/dts/bindings/dfpmccu/intel,adsp-dfpmccu.yaml +++ b/dts/bindings/dfpmccu/intel,adsp-dfpmccu.yaml @@ -9,5 +9,5 @@ compatible: "intel,adsp-dfpmccu" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/display/display-controller.yaml b/dts/bindings/display/display-controller.yaml index d34c052246d945..71ddcbde7ee787 100644 --- a/dts/bindings/display/display-controller.yaml +++ b/dts/bindings/display/display-controller.yaml @@ -4,14 +4,14 @@ include: base.yaml properties: - height: - type: int - required: true - description: | - Height of the panel driven by the controller, with the units in pixels. + height: + type: int + required: true + description: | + Height of the panel driven by the controller, with the units in pixels. - width: - type: int - required: true - description: | - Width of the panel driven by the controller, with the units in pixels. + width: + type: int + required: true + description: | + Width of the panel driven by the controller, with the units in pixels. diff --git a/dts/bindings/display/ftdi,ft800.yaml b/dts/bindings/display/ftdi,ft800.yaml index 43fb33bfe8118d..a0753bef98c374 100644 --- a/dts/bindings/display/ftdi,ft800.yaml +++ b/dts/bindings/display/ftdi,ft800.yaml @@ -8,99 +8,99 @@ compatible: "ftdi,ft800" include: spi-device.yaml properties: - irq-gpios: - type: phandle-array - description: Optional IRQ line of FT800 controller - - pclk: - type: int - required: true - description: | - The value to divide the main clock by for PCLK. If the - typical main clock was 48MHz and this value is 5, the PCLK - will be 9.6 MHz. Must be positive value to enable the screen - - pclk_pol: - type: int - required: true - description: | - Polarity of PCLK. If it is set to zero, PCLK polarity is on - the rising edge. If it is set to one, PCLK polarity is on - the falling edge. - - cspread: - type: int - required: true - description: | - Controls the transition of RGB signals with PCLK active clock - edge. When set to 0, R[7:2],G[7:2] and B[7:2] signals change - following the active edge of PCLK. When set to 1, R[7:2] - changes a PCLK clock early and B[7:2] a PCLK clock later, - which helps reduce the system noise. - - swizzle: - type: int - required: true - description: | - Controls the arrangement of output RGB pins, which may help - support different LCD panel. Please check FT800 Programmers - Guide for details. - - vsize: - type: int - required: true - description: Number of visible lines of pixels in one frame - - voffset: - type: int - required: true - description: Number of invisible lines at the beginning of a new frame - - vcycle: - type: int - required: true - description: | - Number of all lines in a frame. It includes all visible and - invisible lines at the beginning and at the end of a frame. - - vsync0: - type: int - required: true - description: | - Number of lines for the high state of signal VSYNC at - the start of new frame. - - vsync1: - type: int - required: true - description: | - Number of lines for signal VSYNC toggle takes at the start - of new frame. - - hsize: - type: int - required: true - description: Number of PCLK cycles per visible part of horizontal line - - hoffset: - type: int - required: true - description: | - Number of PCLK cycles before pixels are scanned out for - given line - - hcycle: - type: int - required: true - description: Number of total PCLK cycles per horizontal line scan. - - hsync0: - type: int - required: true - description: Number of PCLK cycles of HSYNC high state during start of - line - - hsync1: - type: int - required: true - description: Number of PCLK cycles for HSYNC toggle during start of line. + irq-gpios: + type: phandle-array + description: Optional IRQ line of FT800 controller + + pclk: + type: int + required: true + description: | + The value to divide the main clock by for PCLK. If the + typical main clock was 48MHz and this value is 5, the PCLK + will be 9.6 MHz. Must be positive value to enable the screen + + pclk_pol: + type: int + required: true + description: | + Polarity of PCLK. If it is set to zero, PCLK polarity is on + the rising edge. If it is set to one, PCLK polarity is on + the falling edge. + + cspread: + type: int + required: true + description: | + Controls the transition of RGB signals with PCLK active clock + edge. When set to 0, R[7:2],G[7:2] and B[7:2] signals change + following the active edge of PCLK. When set to 1, R[7:2] + changes a PCLK clock early and B[7:2] a PCLK clock later, + which helps reduce the system noise. + + swizzle: + type: int + required: true + description: | + Controls the arrangement of output RGB pins, which may help + support different LCD panel. Please check FT800 Programmers + Guide for details. + + vsize: + type: int + required: true + description: Number of visible lines of pixels in one frame + + voffset: + type: int + required: true + description: Number of invisible lines at the beginning of a new frame + + vcycle: + type: int + required: true + description: | + Number of all lines in a frame. It includes all visible and + invisible lines at the beginning and at the end of a frame. + + vsync0: + type: int + required: true + description: | + Number of lines for the high state of signal VSYNC at + the start of new frame. + + vsync1: + type: int + required: true + description: | + Number of lines for signal VSYNC toggle takes at the start + of new frame. + + hsize: + type: int + required: true + description: Number of PCLK cycles per visible part of horizontal line + + hoffset: + type: int + required: true + description: | + Number of PCLK cycles before pixels are scanned out for + given line + + hcycle: + type: int + required: true + description: Number of total PCLK cycles per horizontal line scan. + + hsync0: + type: int + required: true + description: Number of PCLK cycles of HSYNC high state during start of + line + + hsync1: + type: int + required: true + description: Number of PCLK cycles for HSYNC toggle during start of line. diff --git a/dts/bindings/display/ilitek,ili9340.yaml b/dts/bindings/display/ilitek,ili9340.yaml index 4efbc846cc3857..9d503e91822a3a 100644 --- a/dts/bindings/display/ilitek,ili9340.yaml +++ b/dts/bindings/display/ilitek,ili9340.yaml @@ -9,89 +9,89 @@ compatible: "ilitek,ili9340" include: ilitek,ili9xxx-common.yaml properties: - gamset: - type: uint8-array - default: [0x01] - description: - Gamma set (GAMSET) register value. + gamset: + type: uint8-array + default: [0x01] + description: + Gamma set (GAMSET) register value. - frmctr1: - type: uint8-array - default: [0x00, 0x1b] - description: - Frame rate control (in normal mode / full colors) (FRMCTR1) register value. + frmctr1: + type: uint8-array + default: [0x00, 0x1b] + description: + Frame rate control (in normal mode / full colors) (FRMCTR1) register value. - disctrl: - type: uint8-array - default: [0x0a, 0x82, 0x27] - description: - Display function control (DISCTRL) register value. Note that changing - default SS bit value (0) may interfere with display rotation. + disctrl: + type: uint8-array + default: [0x0a, 0x82, 0x27] + description: + Display function control (DISCTRL) register value. Note that changing + default SS bit value (0) may interfere with display rotation. - pwctrl1: - type: uint8-array - default: [0x26, 0x00] - description: - Power control 1 (PWCTRL1) register values. + pwctrl1: + type: uint8-array + default: [0x26, 0x00] + description: + Power control 1 (PWCTRL1) register values. - pwctrl2: - type: uint8-array - default: [0x00] - description: - Power control 2 (PWCTRL2) register values. + pwctrl2: + type: uint8-array + default: [0x00] + description: + Power control 2 (PWCTRL2) register values. - vmctrl1: - type: uint8-array - default: [0x31, 0x3c] - description: - VCOM control 1 (VMCTRL1) register values. + vmctrl1: + type: uint8-array + default: [0x31, 0x3c] + description: + VCOM control 1 (VMCTRL1) register values. - vmctrl2: - type: uint8-array - default: [0xc0] - description: - VCOM control 2 (VMCTRL2) register values. + vmctrl2: + type: uint8-array + default: [0xc0] + description: + VCOM control 2 (VMCTRL2) register values. - pgamctrl: - type: uint8-array - default: [ - 0x0f, - 0x22, - 0x1f, - 0x0a, - 0x0e, - 0x06, - 0x4d, - 0x76, - 0x3b, - 0x03, - 0x0e, - 0x04, - 0x13, - 0x0e, - 0x0c - ] - description: - Positive gamma correction (PGAMCTRL) register values. + pgamctrl: + type: uint8-array + default: [ + 0x0f, + 0x22, + 0x1f, + 0x0a, + 0x0e, + 0x06, + 0x4d, + 0x76, + 0x3b, + 0x03, + 0x0e, + 0x04, + 0x13, + 0x0e, + 0x0c + ] + description: + Positive gamma correction (PGAMCTRL) register values. - ngamctrl: - type: uint8-array - default: [ - 0x0c, - 0x23, - 0x26, - 0x04, - 0x10, - 0x04, - 0x39, - 0x24, - 0x4b, - 0x03, - 0x0b, - 0x0b, - 0x33, - 0x37, - 0x0f - ] - description: - Negative gamma correction (NGAMCTRL) register values. + ngamctrl: + type: uint8-array + default: [ + 0x0c, + 0x23, + 0x26, + 0x04, + 0x10, + 0x04, + 0x39, + 0x24, + 0x4b, + 0x03, + 0x0b, + 0x0b, + 0x33, + 0x37, + 0x0f + ] + description: + Negative gamma correction (NGAMCTRL) register values. diff --git a/dts/bindings/display/ilitek,ili9341.yaml b/dts/bindings/display/ilitek,ili9341.yaml index 2cf61c391a95d3..515570807fb618 100644 --- a/dts/bindings/display/ilitek,ili9341.yaml +++ b/dts/bindings/display/ilitek,ili9341.yaml @@ -11,149 +11,149 @@ compatible: "ilitek,ili9341" include: ilitek,ili9xxx-common.yaml properties: - ifmode: - type: uint8-array - default: [0x40] - description: - RGB interface signal control (IFMOD) register value. - - ifctl: - type: uint8-array - default: [0x01, 0x00, 0x00] - description: - Interface control (IFCTL) register value. - - pwctrla: - type: uint8-array - default: [0x39, 0x2c, 0x00, 0x34, 0x02] - description: - Power control A (PWCTRLA) register value. - - pwctrlb: - type: uint8-array - default: [0x00, 0x8b, 0x30] - description: - Power control B (PWCTRLB) register value. - - pwseqctrl: - type: uint8-array - default: [0x55, 0x01, 0x23, 0x01] - description: - Power on sequence control (PWSEQCTRL) register value. - - timctrla: - type: uint8-array - default: [0x84, 0x11, 0x7a] - description: - Driver timing control A (TIMCTRLA) register value. - - timctrlb: - type: uint8-array - default: [0x00, 0x00] - description: - Driver timing control B (TIMCTRLB) register value. - - pumpratioctrl: - type: uint8-array - default: [0x10] - description: - Pump ratio control (PUMPRATIOCTRL) register value. - - enable3g: - type: uint8-array - default: [0x02] - description: - Enable 3G (ENABLE3G) register value. - - etmod: - type: uint8-array - default: [0x06] - description: - Entry Mode Set (ETMOD) register value. - - gamset: - type: uint8-array - default: [0x01] - description: - Gamma set (GAMSET) register value. - - frmctr1: - type: uint8-array - default: [0x00, 0x1b] - description: - Frame rate control (in normal mode / full colors) (FRMCTR1) register value. - - disctrl: - type: uint8-array - default: [0x0a, 0x82, 0x27] - description: - Display function control (DISCTRL) register value. Note that changing - default SS bit value (0) may interfere with display rotation. - - pwctrl1: - type: uint8-array - default: [0x21] - description: - Power control 1 (PWCTRL1) register values. - - pwctrl2: - type: uint8-array - default: [0x10] - description: - Power control 2 (PWCTRL2) register values. - - vmctrl1: - type: uint8-array - default: [0x31, 0x3c] - description: - VCOM control 1 (VMCTRL1) register values. - - vmctrl2: - type: uint8-array - default: [0xc0] - description: - VCOM control 2 (VMCTRL2) register values. - - pgamctrl: - type: uint8-array - default: [ - 0x0f, - 0x22, - 0x1f, - 0x0a, - 0x0e, - 0x06, - 0x4d, - 0x76, - 0x3b, - 0x03, - 0x0e, - 0x04, - 0x13, - 0x0e, - 0x0c - ] - description: - Positive gamma correction (PGAMCTRL) register values. - - ngamctrl: - type: uint8-array - default: [ - 0x0c, - 0x23, - 0x26, - 0x04, - 0x10, - 0x04, - 0x39, - 0x24, - 0x4b, - 0x03, - 0x0b, - 0x0b, - 0x33, - 0x37, - 0x0f - ] - description: - Negative gamma correction (NGAMCTRL) register values. + ifmode: + type: uint8-array + default: [0x40] + description: + RGB interface signal control (IFMOD) register value. + + ifctl: + type: uint8-array + default: [0x01, 0x00, 0x00] + description: + Interface control (IFCTL) register value. + + pwctrla: + type: uint8-array + default: [0x39, 0x2c, 0x00, 0x34, 0x02] + description: + Power control A (PWCTRLA) register value. + + pwctrlb: + type: uint8-array + default: [0x00, 0x8b, 0x30] + description: + Power control B (PWCTRLB) register value. + + pwseqctrl: + type: uint8-array + default: [0x55, 0x01, 0x23, 0x01] + description: + Power on sequence control (PWSEQCTRL) register value. + + timctrla: + type: uint8-array + default: [0x84, 0x11, 0x7a] + description: + Driver timing control A (TIMCTRLA) register value. + + timctrlb: + type: uint8-array + default: [0x00, 0x00] + description: + Driver timing control B (TIMCTRLB) register value. + + pumpratioctrl: + type: uint8-array + default: [0x10] + description: + Pump ratio control (PUMPRATIOCTRL) register value. + + enable3g: + type: uint8-array + default: [0x02] + description: + Enable 3G (ENABLE3G) register value. + + etmod: + type: uint8-array + default: [0x06] + description: + Entry Mode Set (ETMOD) register value. + + gamset: + type: uint8-array + default: [0x01] + description: + Gamma set (GAMSET) register value. + + frmctr1: + type: uint8-array + default: [0x00, 0x1b] + description: + Frame rate control (in normal mode / full colors) (FRMCTR1) register value. + + disctrl: + type: uint8-array + default: [0x0a, 0x82, 0x27] + description: + Display function control (DISCTRL) register value. Note that changing + default SS bit value (0) may interfere with display rotation. + + pwctrl1: + type: uint8-array + default: [0x21] + description: + Power control 1 (PWCTRL1) register values. + + pwctrl2: + type: uint8-array + default: [0x10] + description: + Power control 2 (PWCTRL2) register values. + + vmctrl1: + type: uint8-array + default: [0x31, 0x3c] + description: + VCOM control 1 (VMCTRL1) register values. + + vmctrl2: + type: uint8-array + default: [0xc0] + description: + VCOM control 2 (VMCTRL2) register values. + + pgamctrl: + type: uint8-array + default: [ + 0x0f, + 0x22, + 0x1f, + 0x0a, + 0x0e, + 0x06, + 0x4d, + 0x76, + 0x3b, + 0x03, + 0x0e, + 0x04, + 0x13, + 0x0e, + 0x0c + ] + description: + Positive gamma correction (PGAMCTRL) register values. + + ngamctrl: + type: uint8-array + default: [ + 0x0c, + 0x23, + 0x26, + 0x04, + 0x10, + 0x04, + 0x39, + 0x24, + 0x4b, + 0x03, + 0x0b, + 0x0b, + 0x33, + 0x37, + 0x0f + ] + description: + Negative gamma correction (NGAMCTRL) register values. diff --git a/dts/bindings/display/ilitek,ili9488.yaml b/dts/bindings/display/ilitek,ili9488.yaml index e948595bcd124c..41bbbe080ee292 100644 --- a/dts/bindings/display/ilitek,ili9488.yaml +++ b/dts/bindings/display/ilitek,ili9488.yaml @@ -8,77 +8,77 @@ compatible: "ilitek,ili9488" include: ilitek,ili9xxx-common.yaml properties: - frmctr1: - type: uint8-array - default: [0xb0, 0x11] - description: - Frame rate control (in normal mode / full colors) (FRMCTR1) register value. + frmctr1: + type: uint8-array + default: [0xb0, 0x11] + description: + Frame rate control (in normal mode / full colors) (FRMCTR1) register value. - disctrl: - type: uint8-array - default: [0x02, 0x02, 0x3b] - description: - Display function control (DISCTRL) register value. Note that changing - default SS bit value (0) may interfere with display rotation. + disctrl: + type: uint8-array + default: [0x02, 0x02, 0x3b] + description: + Display function control (DISCTRL) register value. Note that changing + default SS bit value (0) may interfere with display rotation. - pwctrl1: - type: uint8-array - default: [0x0e, 0x0e] - description: - Power control 1 (PWCTRL1) register values. + pwctrl1: + type: uint8-array + default: [0x0e, 0x0e] + description: + Power control 1 (PWCTRL1) register values. - pwctrl2: - type: uint8-array - default: [0x43] - description: - Power control 2 (PWCTRL2) register values. + pwctrl2: + type: uint8-array + default: [0x43] + description: + Power control 2 (PWCTRL2) register values. - vmctrl: - type: uint8-array - default: [0x00, 0x40, 0x00, 0x40] - description: - VCOM control (VMCTRL) register values. + vmctrl: + type: uint8-array + default: [0x00, 0x40, 0x00, 0x40] + description: + VCOM control (VMCTRL) register values. - pgamctrl: - type: uint8-array - default: [ - 0x0f, - 0x1f, - 0x1c, - 0x0b, - 0x0e, - 0x09, - 0x48, - 0x99, - 0x38, - 0x0a, - 0x14, - 0x06, - 0x11, - 0x09, - 0x00 - ] - description: - Positive gamma correction (PGAMCTRL) register values. + pgamctrl: + type: uint8-array + default: [ + 0x0f, + 0x1f, + 0x1c, + 0x0b, + 0x0e, + 0x09, + 0x48, + 0x99, + 0x38, + 0x0a, + 0x14, + 0x06, + 0x11, + 0x09, + 0x00 + ] + description: + Positive gamma correction (PGAMCTRL) register values. - ngamctrl: - type: uint8-array - default: [ - 0x0f, - 0x36, - 0x2e, - 0x09, - 0x0a, - 0x04, - 0x46, - 0x66, - 0x37, - 0x06, - 0x10, - 0x04, - 0x24, - 0x20, - 0x00 - ] - description: - Negative gamma correction (NGAMCTRL) register values. + ngamctrl: + type: uint8-array + default: [ + 0x0f, + 0x36, + 0x2e, + 0x09, + 0x0a, + 0x04, + 0x46, + 0x66, + 0x37, + 0x06, + 0x10, + 0x04, + 0x24, + 0x20, + 0x00 + ] + description: + Negative gamma correction (NGAMCTRL) register values. diff --git a/dts/bindings/display/ilitek,ili9xxx-common.yaml b/dts/bindings/display/ilitek,ili9xxx-common.yaml index 9383038c95bb61..fe1fd852f876f0 100644 --- a/dts/bindings/display/ilitek,ili9xxx-common.yaml +++ b/dts/bindings/display/ilitek,ili9xxx-common.yaml @@ -7,47 +7,47 @@ description: ILI9XXX display controllers common properties. include: [spi-device.yaml, display-controller.yaml] properties: - reset-gpios: - type: phandle-array - description: RESET pin. - - The RESET pin of ILI9340 is active low. - If connected directly the MCU pin should be configured - as active low. - - cmd-data-gpios: - type: phandle-array - required: true - description: D/CX pin. - - The D/CX pin of ILI9340 is active low (transmission command byte). - If connected directly the MCU pin should be configured - as active low. - - pixel-format: - type: int - default: 0 - enum: - - 0 # RGB565 - - 1 # RGB888 - description: - Display pixel format. Note that when RGB888 pixel format is selected - only 6 color bits are actually used being in practice equivalent to - RGB666. - - rotation: - type: int - default: 0 - enum: - - 0 - - 90 - - 180 - - 270 - description: - Display rotation (CW) in degrees. - - display-inversion: - type: boolean - description: - Display inversion mode. Every bit is inverted from the frame memory to - the display. + reset-gpios: + type: phandle-array + description: RESET pin. + + The RESET pin of ILI9340 is active low. + If connected directly the MCU pin should be configured + as active low. + + cmd-data-gpios: + type: phandle-array + required: true + description: D/CX pin. + + The D/CX pin of ILI9340 is active low (transmission command byte). + If connected directly the MCU pin should be configured + as active low. + + pixel-format: + type: int + default: 0 + enum: + - 0 # RGB565 + - 1 # RGB888 + description: + Display pixel format. Note that when RGB888 pixel format is selected + only 6 color bits are actually used being in practice equivalent to + RGB666. + + rotation: + type: int + default: 0 + enum: + - 0 + - 90 + - 180 + - 270 + description: + Display rotation (CW) in degrees. + + display-inversion: + type: boolean + description: + Display inversion mode. Every bit is inverted from the frame memory to + the display. diff --git a/dts/bindings/display/maxim,max7219.yaml b/dts/bindings/display/maxim,max7219.yaml index 8961f326ebc399..ddd34d4e931ea8 100644 --- a/dts/bindings/display/maxim,max7219.yaml +++ b/dts/bindings/display/maxim,max7219.yaml @@ -9,44 +9,44 @@ compatible: "maxim,max7219" include: spi-device.yaml properties: - scan-limit: - type: int - default: 7 - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - description: | - Number of scanned digits for MAX7219. - Display digit 0 only when scan-limit is 0, digits 0 & 1 when - scan-limit is 1, and so on. - intensity: - type: int - default: 0 - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 - - 11 - - 12 - - 13 - - 14 - - 15 - description: Intensity for MAX7219. - num-cascading: - type: int - default: 1 - description: Number of cascading MAX7219. + scan-limit: + type: int + default: 7 + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + description: | + Number of scanned digits for MAX7219. + Display digit 0 only when scan-limit is 0, digits 0 & 1 when + scan-limit is 1, and so on. + intensity: + type: int + default: 0 + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 + - 11 + - 12 + - 13 + - 14 + - 15 + description: Intensity for MAX7219. + num-cascading: + type: int + default: 1 + description: Number of cascading MAX7219. diff --git a/dts/bindings/display/nordic,nrf-led-matrix.yaml b/dts/bindings/display/nordic,nrf-led-matrix.yaml index f16e6dd9e7b026..e40a5caeb71661 100644 --- a/dts/bindings/display/nordic,nrf-led-matrix.yaml +++ b/dts/bindings/display/nordic,nrf-led-matrix.yaml @@ -8,74 +8,74 @@ compatible: "nordic,nrf-led-matrix" include: display-controller.yaml properties: - row-gpios: - type: phandle-array - required: true - description: | - Array of GPIOs to be used as rows of the matrix. + row-gpios: + type: phandle-array + required: true + description: | + Array of GPIOs to be used as rows of the matrix. - col-gpios: - type: phandle-array - required: true - description: | - Array of GPIOs to be used as columns of the matrix. + col-gpios: + type: phandle-array + required: true + description: | + Array of GPIOs to be used as columns of the matrix. - pixel-mapping: - type: uint8-array - required: true - description: | - Array of bytes that specify which rows and columns of the matrix - control its particular pixels, line by line. Each byte in this - array corresponds to one pixel of the matrix and specifies the row - index in the high nibble and the column index in the low nibble. + pixel-mapping: + type: uint8-array + required: true + description: | + Array of bytes that specify which rows and columns of the matrix + control its particular pixels, line by line. Each byte in this + array corresponds to one pixel of the matrix and specifies the row + index in the high nibble and the column index in the low nibble. - For example, the following snippet (from the bbc_microbit board DTS): + For example, the following snippet (from the bbc_microbit board DTS): - width = <5>; - height = <5>; - pixel-mapping = [00 13 01 14 02 - 23 24 25 26 27 - ... + width = <5>; + height = <5>; + pixel-mapping = [00 13 01 14 02 + 23 24 25 26 27 + ... - specifies that: - - pixel (0,0) is controlled by row 0 and column 0 - - pixel (1,0) is controlled by row 1 and column 3 - - pixel (0,1) is controlled by row 2 and column 3 - - pixel (1,1) is controlled by row 2 and column 4 - and so on. + specifies that: + - pixel (0,0) is controlled by row 0 and column 0 + - pixel (1,0) is controlled by row 1 and column 3 + - pixel (0,1) is controlled by row 2 and column 3 + - pixel (1,1) is controlled by row 2 and column 4 + and so on. - refresh-frequency: - type: int - required: true - description: | - Frequency of refreshing the matrix, in Hz. + refresh-frequency: + type: int + required: true + description: | + Frequency of refreshing the matrix, in Hz. - timer: - type: phandle - required: true - description: | - Reference to a TIMER instance for controlling refreshing of the matrix. + timer: + type: phandle + required: true + description: | + Reference to a TIMER instance for controlling refreshing of the matrix. - pwm: - type: phandle - description: | - Reference to a PWM instance for generating pulse signals on column - GPIOs. If not provided, GPIOTE and PPI channels are allocated and - used instead for generating those pulses. + pwm: + type: phandle + description: | + Reference to a PWM instance for generating pulse signals on column + GPIOs. If not provided, GPIOTE and PPI channels are allocated and + used instead for generating those pulses. - pixel-group-size: - type: int - required: true - description: | - This value specifies the maximum number of LEDs in one row that can - be lit simultaneously. - If set to 1, only a single LED is turned on in a particular time slot. - Bigger values increase the maximum achievable brightness of the LEDs - and lower the CPU load by decreasing the frequency of execution of - the timer interrupt handler. - In case GPIOTE and PPI channels are used for generating the pixel pulse - signals, the number of channels that need to be allocated is equal to - this value. - If GPIOTE and PPI channels are used, the upper limit for the value is - defined by the number of CC channels in the used timer minus one. - If PWM is used, the upper limit is the number of PWM channels. + pixel-group-size: + type: int + required: true + description: | + This value specifies the maximum number of LEDs in one row that can + be lit simultaneously. + If set to 1, only a single LED is turned on in a particular time slot. + Bigger values increase the maximum achievable brightness of the LEDs + and lower the CPU load by decreasing the frequency of execution of + the timer interrupt handler. + In case GPIOTE and PPI channels are used for generating the pixel pulse + signals, the number of channels that need to be allocated is equal to + this value. + If GPIOTE and PPI channels are used, the upper limit for the value is + defined by the number of CC channels in the used timer minus one. + If PWM is used, the upper limit is the number of PWM channels. diff --git a/dts/bindings/display/nxp,imx-elcdif.yaml b/dts/bindings/display/nxp,imx-elcdif.yaml index 672d7247901e51..1bd00729792a84 100644 --- a/dts/bindings/display/nxp,imx-elcdif.yaml +++ b/dts/bindings/display/nxp,imx-elcdif.yaml @@ -8,103 +8,103 @@ compatible: "nxp,imx-elcdif" include: [display-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - hsync: - type: int - required: true - description: HSYNC pulse width in display clock cycles + hsync: + type: int + required: true + description: HSYNC pulse width in display clock cycles - hfp: - type: int - required: true - description: Horizontal front porch in display clock cycles + hfp: + type: int + required: true + description: Horizontal front porch in display clock cycles - hbp: - type: int - required: true - description: Horizontal back porch in display clock cycles + hbp: + type: int + required: true + description: Horizontal back porch in display clock cycles - vsync: - type: int - required: true - description: VSYNC pulse width in display clock cycles + vsync: + type: int + required: true + description: VSYNC pulse width in display clock cycles - vfp: - type: int - required: true - description: Vertical front porch in display clock cycles + vfp: + type: int + required: true + description: Vertical front porch in display clock cycles - vbp: - type: int - required: true - description: Vertical back porch in display clock cycles + vbp: + type: int + required: true + description: Vertical back porch in display clock cycles - polarity: - type: int - required: true - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 - - 11 - - 12 - - 13 - - 14 - - 15 - description: - OR'ed value of elcdif_polarity_flags, used to control the signal polarity. - 0000 VSYNC active low, HSYNC active low, Drive data on falling edge, DE active low. - 0001 VSYNC active low, HSYNC active low, Drive data on falling edge, DE active high. - 0010 VSYNC active low, HSYNC active low, Drive data on rising edge, DE active low. - 0011 VSYNC active low, HSYNC active low, Drive data on rising edge, DE active high. - 0100 VSYNC active low, HSYNC active high, Drive data on falling edge, DE active low. - 0101 VSYNC active low, HSYNC active high, Drive data on falling edge, DE active high. - 0110 VSYNC active low, HSYNC active high, Drive data on rising edge, DE active low. - 0111 VSYNC active low, HSYNC active high, Drive data on rising edge, DE active high. - 1000 VSYNC active high, HSYNC active low, Drive data on falling edge, DE active low. - 1001 VSYNC active high, HSYNC active low, Drive data on falling edge, DE active high. - 1010 VSYNC active high, HSYNC active low, Drive data on rising edge, DE active low. - 1011 VSYNC active high, HSYNC active low, Drive data on rising edge, DE active high. - 1100 VSYNC active high, HSYNC active high, Drive data on falling edge, DE active low. - 1101 VSYNC active high, HSYNC active high, Drive data on falling edge, DE active high. - 1110 VSYNC active high, HSYNC active high, Drive data on rising edge, DE active low. - 1111 VSYNC active high, HSYNC active high, Drive data on rising edge, DE active high. + polarity: + type: int + required: true + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 + - 11 + - 12 + - 13 + - 14 + - 15 + description: + OR'ed value of elcdif_polarity_flags, used to control the signal polarity. + 0000 VSYNC active low, HSYNC active low, Drive data on falling edge, DE active low. + 0001 VSYNC active low, HSYNC active low, Drive data on falling edge, DE active high. + 0010 VSYNC active low, HSYNC active low, Drive data on rising edge, DE active low. + 0011 VSYNC active low, HSYNC active low, Drive data on rising edge, DE active high. + 0100 VSYNC active low, HSYNC active high, Drive data on falling edge, DE active low. + 0101 VSYNC active low, HSYNC active high, Drive data on falling edge, DE active high. + 0110 VSYNC active low, HSYNC active high, Drive data on rising edge, DE active low. + 0111 VSYNC active low, HSYNC active high, Drive data on rising edge, DE active high. + 1000 VSYNC active high, HSYNC active low, Drive data on falling edge, DE active low. + 1001 VSYNC active high, HSYNC active low, Drive data on falling edge, DE active high. + 1010 VSYNC active high, HSYNC active low, Drive data on rising edge, DE active low. + 1011 VSYNC active high, HSYNC active low, Drive data on rising edge, DE active high. + 1100 VSYNC active high, HSYNC active high, Drive data on falling edge, DE active low. + 1101 VSYNC active high, HSYNC active high, Drive data on falling edge, DE active high. + 1110 VSYNC active high, HSYNC active high, Drive data on rising edge, DE active low. + 1111 VSYNC active high, HSYNC active high, Drive data on rising edge, DE active high. - pixel-format: - type: string - required: true - enum: - - "rgb-888" - - "bgr-565" - description: - Display pixel format. + pixel-format: + type: string + required: true + enum: + - "rgb-888" + - "bgr-565" + description: + Display pixel format. - data-buswidth: - type: string - default: "16-bit" - enum: - - "16-bit" - - "8-bit" - - "18-bit" - - "24-bit" - description: - LCD data bus width. The default is set to the reset value of 16-bit + data-buswidth: + type: string + default: "16-bit" + enum: + - "16-bit" + - "8-bit" + - "18-bit" + - "24-bit" + description: + LCD data bus width. The default is set to the reset value of 16-bit - backlight-gpios: - type: phandle-array - required: true - description: - LCB backlight control gpio. Driver will initialize this GPIO to active high + backlight-gpios: + type: phandle-array + required: true + description: + LCB backlight control gpio. Driver will initialize this GPIO to active high diff --git a/dts/bindings/display/raydium,rm68200.yaml b/dts/bindings/display/raydium,rm68200.yaml index f03c4144c4534c..eb43781e6346f3 100644 --- a/dts/bindings/display/raydium,rm68200.yaml +++ b/dts/bindings/display/raydium,rm68200.yaml @@ -11,14 +11,14 @@ compatible: "raydium,rm68200" include: [mipi-dsi-device.yaml, display-controller.yaml] properties: - reset-gpios: - type: phandle-array - description: | - The RESETn pin is asserted to disable the sensor causing a hard - reset. The sensor receives this as an active-low signal. + reset-gpios: + type: phandle-array + description: | + The RESETn pin is asserted to disable the sensor causing a hard + reset. The sensor receives this as an active-low signal. - bl-gpios: - type: phandle-array - description: | - The BLn pin is asserted to control the backlight of the panel. - The sensor receives this as an active-high signal. + bl-gpios: + type: phandle-array + description: | + The BLn pin is asserted to control the backlight of the panel. + The sensor receives this as an active-high signal. diff --git a/dts/bindings/display/sharp,ls0xx.yaml b/dts/bindings/display/sharp,ls0xx.yaml index dce1bb2416a26c..662b2b9850ced5 100644 --- a/dts/bindings/display/sharp,ls0xx.yaml +++ b/dts/bindings/display/sharp,ls0xx.yaml @@ -8,25 +8,25 @@ compatible: "sharp,ls0xx" include: [spi-device.yaml, display-controller.yaml] properties: - extcomin-gpios: - type: phandle-array - description: EXTCOMIN pin + extcomin-gpios: + type: phandle-array + description: EXTCOMIN pin - The EXTCOMIN pin is where a square pulse for toggling VCOM will - be given + The EXTCOMIN pin is where a square pulse for toggling VCOM will + be given - extcomin-frequency: - type: int - description: EXTCOMIN pin toggle frequency + extcomin-frequency: + type: int + description: EXTCOMIN pin toggle frequency - The frequency with which the EXTCOMIN pin should be toggled. See - datasheet of particular display. Higher frequency gives better - contrast while low frequency saves power. + The frequency with which the EXTCOMIN pin should be toggled. See + datasheet of particular display. Higher frequency gives better + contrast while low frequency saves power. - disp-en-gpios: - type: phandle-array - description: DISPLAY pin + disp-en-gpios: + type: phandle-array + description: DISPLAY pin - The DISPLAY pin controls if the LCD displays memory contents or - white screen. If defined, the pin will be set high during driver - initialization. display blanking apis can be used to control it. + The DISPLAY pin controls if the LCD displays memory contents or + white screen. If defined, the pin will be set high during driver + initialization. display blanking apis can be used to control it. diff --git a/dts/bindings/display/sitronix,st7735r.yaml b/dts/bindings/display/sitronix,st7735r.yaml index e614915ffdf18b..008a1959fb1033 100644 --- a/dts/bindings/display/sitronix,st7735r.yaml +++ b/dts/bindings/display/sitronix,st7735r.yaml @@ -8,127 +8,127 @@ compatible: "sitronix,st7735r" include: [spi-device.yaml, display-controller.yaml] properties: - reset-gpios: - type: phandle-array - required: true - description: RESET pin. - - The RESET pin of ST7735R is active low. - If connected directly the MCU pin should be configured - as active low. - - cmd-data-gpios: - type: phandle-array - required: true - description: D/CX pin. - - The D/CX pin of ST7735R is active low (transmission command byte). - If connected directly the MCU pin should be configured - as active low. - - x-offset: - type: int - required: true - description: The column offset in pixels of the LCD to the controller memory - - y-offset: - type: int - required: true - description: The row offset in pixels of the LCD to the controller memory - - madctl: - type: int - default: 0x00 - description: Memory Data Access Control - - colmod: - type: int - default: 0x06 - description: Interface Pixel Format - - pwctr1: - type: uint8-array - default: [0xb4, 0x14, 0x04] - description: Power Control 1 Parameter - - pwctr2: - type: uint8-array - default: [0xc0] - description: Power Control 2 Parameter - - pwctr3: - type: uint8-array - default: [0x0a, 0x00] - description: Power Control 3 Parameter - - pwctr4: - type: uint8-array - default: [0x8a, 0x26] - description: Power Control 4 Parameter - - pwctr5: - type: uint8-array - default: [0x8a, 0xee] - description: Power Control 5 Parameter - - gamctrp1: - type: uint8-array - required: true - description: Positive Voltage Gamma Control Parameter - - gamctrn1: - type: uint8-array - required: true - description: Negative Voltage Gamma Control Parameter - - frmctr1: - type: uint8-array - default: [0x05, 0x3a, 0x3a] - description: Frame rate control (normal mode / full colors) - - frmctr2: - type: uint8-array - default: [0x05, 0x3a, 0x3a] - description: Frame rate control (idle mode / 8 colors) - - frmctr3: - type: uint8-array - default: [0x05, 0x3a, 0x3a, 0x05, 0x3a, 0x3a] - description: Frame rate control (partial mode / full colors) - - caset: - type: uint8-array - default: [0x00, 0x00, 0x00, 0x7f] - description: Column Address Set - - raset: - type: uint8-array - default: [0x00, 0x00, 0x00, 0x9f] - description: Row Address Set - - vmctr1: - type: int - default: 0x0a - description: VCOM Control 1 - - invctr: - type: int - default: 0x07 - description: | - Display Inversion Control - Set dot inversion or line inversion for each normal/idle/partial mode. - - inversion-on: - type: boolean - description: | - Enable Display Inversion - Make a drawing with the inverted color of the frame memory. - - rgb-is-inverted: - type: boolean - description: | - Inverting color format order (RGB->BGR or BGR->RGB) - In the case of enabling this option, API reports pixel-format in capabilities - as the inverted value of the RGB pixel-format specified in MADCTL. - This option is convenient for supporting displays with bugs - where the actual color is different from the pixel format of MADCTL. + reset-gpios: + type: phandle-array + required: true + description: RESET pin. + + The RESET pin of ST7735R is active low. + If connected directly the MCU pin should be configured + as active low. + + cmd-data-gpios: + type: phandle-array + required: true + description: D/CX pin. + + The D/CX pin of ST7735R is active low (transmission command byte). + If connected directly the MCU pin should be configured + as active low. + + x-offset: + type: int + required: true + description: The column offset in pixels of the LCD to the controller memory + + y-offset: + type: int + required: true + description: The row offset in pixels of the LCD to the controller memory + + madctl: + type: int + default: 0x00 + description: Memory Data Access Control + + colmod: + type: int + default: 0x06 + description: Interface Pixel Format + + pwctr1: + type: uint8-array + default: [0xb4, 0x14, 0x04] + description: Power Control 1 Parameter + + pwctr2: + type: uint8-array + default: [0xc0] + description: Power Control 2 Parameter + + pwctr3: + type: uint8-array + default: [0x0a, 0x00] + description: Power Control 3 Parameter + + pwctr4: + type: uint8-array + default: [0x8a, 0x26] + description: Power Control 4 Parameter + + pwctr5: + type: uint8-array + default: [0x8a, 0xee] + description: Power Control 5 Parameter + + gamctrp1: + type: uint8-array + required: true + description: Positive Voltage Gamma Control Parameter + + gamctrn1: + type: uint8-array + required: true + description: Negative Voltage Gamma Control Parameter + + frmctr1: + type: uint8-array + default: [0x05, 0x3a, 0x3a] + description: Frame rate control (normal mode / full colors) + + frmctr2: + type: uint8-array + default: [0x05, 0x3a, 0x3a] + description: Frame rate control (idle mode / 8 colors) + + frmctr3: + type: uint8-array + default: [0x05, 0x3a, 0x3a, 0x05, 0x3a, 0x3a] + description: Frame rate control (partial mode / full colors) + + caset: + type: uint8-array + default: [0x00, 0x00, 0x00, 0x7f] + description: Column Address Set + + raset: + type: uint8-array + default: [0x00, 0x00, 0x00, 0x9f] + description: Row Address Set + + vmctr1: + type: int + default: 0x0a + description: VCOM Control 1 + + invctr: + type: int + default: 0x07 + description: | + Display Inversion Control + Set dot inversion or line inversion for each normal/idle/partial mode. + + inversion-on: + type: boolean + description: | + Enable Display Inversion + Make a drawing with the inverted color of the frame memory. + + rgb-is-inverted: + type: boolean + description: | + Inverting color format order (RGB->BGR or BGR->RGB) + In the case of enabling this option, API reports pixel-format in capabilities + as the inverted value of the RGB pixel-format specified in MADCTL. + This option is convenient for supporting displays with bugs + where the actual color is different from the pixel format of MADCTL. diff --git a/dts/bindings/display/sitronix,st7789v.yaml b/dts/bindings/display/sitronix,st7789v.yaml index 94a74d417f9acf..1820bedb2464ce 100644 --- a/dts/bindings/display/sitronix,st7789v.yaml +++ b/dts/bindings/display/sitronix,st7789v.yaml @@ -9,105 +9,105 @@ compatible: "sitronix,st7789v" include: [spi-device.yaml, display-controller.yaml] properties: - reset-gpios: - type: phandle-array - description: | - RESET pin. - - The RESET pin of ST7789V is active low. - If connected directly the MCU pin should be configured - as active low. - - cmd-data-gpios: - type: phandle-array - description: | - D/CX pin. If configured, 4-lines serial interface is used, otherwise - 3-lines serial interface is used and a D/CX bit (9-bit) is added to - the protocol. - - The D/CX pin of ST7789V is active low (transmission command byte). - If connected directly the MCU pin should be configured - as active low. - - x-offset: - type: int - required: true - description: The column offset in pixels of the LCD to the controller memory - - y-offset: - type: int - required: true - description: The row offset in pixels of the LCD to the controller memory - - vcom: - type: int - required: true - description: VCOM Setting - - gctrl: - type: int - required: true - description: Gate Control - - vrhs: - type: int - description: VRH Setting - - vdvs: - type: int - description: VDV Setting - - mdac: - type: int - required: true - description: Memory Data Access Control - - lcm: - type: int - required: true - description: LCM Setting - - colmod: - type: int - required: true - description: Interface Pixel Format - - gamma: - type: int - required: true - description: Gamma Setting - - porch-param: - type: uint8-array - required: true - description: Porch Setting - - cmd2en-param: - type: uint8-array - required: true - description: Command 2 Enable Parameter - - pwctrl1-param: - type: uint8-array - required: true - description: Power Control 1 Parameter - - pvgam-param: - type: uint8-array - required: true - description: Positive Voltage Gamma Control Parameter - - nvgam-param: - type: uint8-array - required: true - description: Negative Voltage Gamma Control Parameter - - ram-param: - type: uint8-array - required: true - description: RAM Control Parameter - - rgb-param: - type: uint8-array - required: true - description: RGB Interface Control Parameter + reset-gpios: + type: phandle-array + description: | + RESET pin. + + The RESET pin of ST7789V is active low. + If connected directly the MCU pin should be configured + as active low. + + cmd-data-gpios: + type: phandle-array + description: | + D/CX pin. If configured, 4-lines serial interface is used, otherwise + 3-lines serial interface is used and a D/CX bit (9-bit) is added to + the protocol. + + The D/CX pin of ST7789V is active low (transmission command byte). + If connected directly the MCU pin should be configured + as active low. + + x-offset: + type: int + required: true + description: The column offset in pixels of the LCD to the controller memory + + y-offset: + type: int + required: true + description: The row offset in pixels of the LCD to the controller memory + + vcom: + type: int + required: true + description: VCOM Setting + + gctrl: + type: int + required: true + description: Gate Control + + vrhs: + type: int + description: VRH Setting + + vdvs: + type: int + description: VDV Setting + + mdac: + type: int + required: true + description: Memory Data Access Control + + lcm: + type: int + required: true + description: LCM Setting + + colmod: + type: int + required: true + description: Interface Pixel Format + + gamma: + type: int + required: true + description: Gamma Setting + + porch-param: + type: uint8-array + required: true + description: Porch Setting + + cmd2en-param: + type: uint8-array + required: true + description: Command 2 Enable Parameter + + pwctrl1-param: + type: uint8-array + required: true + description: Power Control 1 Parameter + + pvgam-param: + type: uint8-array + required: true + description: Positive Voltage Gamma Control Parameter + + nvgam-param: + type: uint8-array + required: true + description: Negative Voltage Gamma Control Parameter + + ram-param: + type: uint8-array + required: true + description: RAM Control Parameter + + rgb-param: + type: uint8-array + required: true + description: RGB Interface Control Parameter diff --git a/dts/bindings/display/solomon,ssd1306fb-common.yaml b/dts/bindings/display/solomon,ssd1306fb-common.yaml index d61faf503e98bf..a4949953bc65e0 100644 --- a/dts/bindings/display/solomon,ssd1306fb-common.yaml +++ b/dts/bindings/display/solomon,ssd1306fb-common.yaml @@ -4,47 +4,47 @@ include: display-controller.yaml properties: - segment-offset: - type: int - required: true - description: 8-bit column start address for Page Addressing Mode - - page-offset: - type: int - required: true - description: Start address for Page Addressing Mode - - display-offset: - type: int - required: true - description: mapping of the display start line to one of COM0 .. COM63 - - multiplex-ratio: - type: int - required: true - description: Multiplex Ratio - - segment-remap: - type: boolean - description: Last column address is mapped to first segment - - com-invdir: - type: boolean - description: Scan direction is from last COM output to first COM output - - com-sequential: - type: boolean - description: Sequential COM pin configuration - - prechargep: - type: int - required: true - description: Duration of the pre-charge period - - reset-gpios: - type: phandle-array - description: RESET pin. - - The RESET pin of SSD1306 is active low. - If connected directly the MCU pin should be configured - as active low. + segment-offset: + type: int + required: true + description: 8-bit column start address for Page Addressing Mode + + page-offset: + type: int + required: true + description: Start address for Page Addressing Mode + + display-offset: + type: int + required: true + description: mapping of the display start line to one of COM0 .. COM63 + + multiplex-ratio: + type: int + required: true + description: Multiplex Ratio + + segment-remap: + type: boolean + description: Last column address is mapped to first segment + + com-invdir: + type: boolean + description: Scan direction is from last COM output to first COM output + + com-sequential: + type: boolean + description: Sequential COM pin configuration + + prechargep: + type: int + required: true + description: Duration of the pre-charge period + + reset-gpios: + type: phandle-array + description: RESET pin. + + The RESET pin of SSD1306 is active low. + If connected directly the MCU pin should be configured + as active low. diff --git a/dts/bindings/display/solomon,ssd1306fb-spi.yaml b/dts/bindings/display/solomon,ssd1306fb-spi.yaml index a286887ac74785..e382a1a53194d4 100644 --- a/dts/bindings/display/solomon,ssd1306fb-spi.yaml +++ b/dts/bindings/display/solomon,ssd1306fb-spi.yaml @@ -8,7 +8,7 @@ compatible: "solomon,ssd1306fb" include: ["solomon,ssd1306fb-common.yaml", "spi-device.yaml"] properties: - data_cmd-gpios: - type: phandle-array - required: true - description: D/C# pin. + data_cmd-gpios: + type: phandle-array + required: true + description: D/C# pin. diff --git a/dts/bindings/display/solomon,ssd16xxfb.yaml b/dts/bindings/display/solomon,ssd16xxfb.yaml index d12334455d93a0..96d8130066c335 100644 --- a/dts/bindings/display/solomon,ssd16xxfb.yaml +++ b/dts/bindings/display/solomon,ssd16xxfb.yaml @@ -8,90 +8,90 @@ compatible: "solomon,ssd16xxfb" include: [spi-device.yaml, display-controller.yaml] properties: - pp-height-bits: - type: int - required: true - description: Number of bits used for the height parameters - - pp-width-bits: - type: int - required: true - description: Number of bits used for the width parameters - - gdv: - type: uint8-array - description: Gate driving voltage values - - sdv: - type: uint8-array - description: Source driving voltage values - - vcom: - type: int - description: VCOM voltage - - border-waveform: - type: int - description: Border waveform - - softstart: - type: uint8-array - description: Booster soft start values - - orientation-flipped: - type: boolean - description: Last column address is mapped to first segment - - reset-gpios: - type: phandle-array - required: true - description: RESET pin. - - The RESET pin of SSD16XX is active low. - If connected directly the MCU pin should be configured - as active low. - - dc-gpios: - type: phandle-array - required: true - description: DC pin. - - The DC pin of SSD16XX is active low (transmission command byte). - If connected directly the MCU pin should be configured - as active low. - - busy-gpios: - type: phandle-array - required: true - description: BUSY pin. - - The BUSY pin of SSD16XX is active high. - If connected directly the MCU pin should be configured - as active high. - - lut-initial: - type: uint8-array - description: | - Initial LUT used when initializing the device and performing - clearing the screen using a full refresh operation. The - default LUT will be loaded from OTP if this property isn't - defined. - - lut-default: - type: uint8-array - - tssv: - type: int - description: Temperature Sensor Selection Value - - Display controller can have integrated temperature sensor or - an external temperature sensor is connected to the controller. - The value selects which sensor should be used. - - dummy-line: - type: int - description: Dummy line period override. - - gate-line-width: - type: int - description: Gate line width override. + pp-height-bits: + type: int + required: true + description: Number of bits used for the height parameters + + pp-width-bits: + type: int + required: true + description: Number of bits used for the width parameters + + gdv: + type: uint8-array + description: Gate driving voltage values + + sdv: + type: uint8-array + description: Source driving voltage values + + vcom: + type: int + description: VCOM voltage + + border-waveform: + type: int + description: Border waveform + + softstart: + type: uint8-array + description: Booster soft start values + + orientation-flipped: + type: boolean + description: Last column address is mapped to first segment + + reset-gpios: + type: phandle-array + required: true + description: RESET pin. + + The RESET pin of SSD16XX is active low. + If connected directly the MCU pin should be configured + as active low. + + dc-gpios: + type: phandle-array + required: true + description: DC pin. + + The DC pin of SSD16XX is active low (transmission command byte). + If connected directly the MCU pin should be configured + as active low. + + busy-gpios: + type: phandle-array + required: true + description: BUSY pin. + + The BUSY pin of SSD16XX is active high. + If connected directly the MCU pin should be configured + as active high. + + lut-initial: + type: uint8-array + description: | + Initial LUT used when initializing the device and performing + clearing the screen using a full refresh operation. The + default LUT will be loaded from OTP if this property isn't + defined. + + lut-default: + type: uint8-array + + tssv: + type: int + description: Temperature Sensor Selection Value + + Display controller can have integrated temperature sensor or + an external temperature sensor is connected to the controller. + The value selects which sensor should be used. + + dummy-line: + type: int + description: Dummy line period override. + + gate-line-width: + type: int + description: Gate line width override. diff --git a/dts/bindings/display/st,stm32-ltdc.yaml b/dts/bindings/display/st,stm32-ltdc.yaml index 1febd33fbbc2f0..43ee5f2defebe5 100644 --- a/dts/bindings/display/st,stm32-ltdc.yaml +++ b/dts/bindings/display/st,stm32-ltdc.yaml @@ -8,103 +8,103 @@ compatible: "st,stm32-ltdc" include: [display-controller.yaml, pinctrl-device.yaml] properties: - disp-on-gpios: - type: phandle-array - description: | - Display on/off GPIO pin. - Configure the GPIO polarity (active high/active low) according to LCD datasheet. - - bl-ctrl-gpios: - type: phandle-array - description: | - Backlight on/off GPIO pin. - Configure the GPIO polarity (active high/active low) according to LCD datasheet. - - ext-sdram: - type: phandle - description: | - External SDRAM in which frame buffer will be stored. - If not defined, internal RAM will be used. - - clocks: - required: true - - interrupts: - required: true - - pinctrl-0: - required: true - - hsync-pol: - type: int - required: true - description: | - Horizontal synchronization pulse polarity. - If HSYNC is active low, use STM32_LTDC_HSPOL_ACTIVE_LOW, - otherwise use STM32_LTDC_HSPOL_ACTIVE_HIGH. - - vsync-pol: - type: int - required: true - description: | - Vertical synchronization pulse polarity. - If VSYNC is active low, use STM32_LTDC_VSPOL_ACTIVE_LOW, - otherwise use STM32_LTDC_VSPOL_ACTIVE_HIGH. - - de-pol: - type: int - required: true - description: | - Data enable pulse polarity. - If DE is active low, use STM32_LTDC_DEPOL_ACTIVE_LOW, - otherwise use STM32_LTDC_DEPOL_ACTIVE_HIGH. - - pclk-pol: - type: int - required: true - description: | - Pixel clock polarity. - If RGB data is sampled on falling edge of PCLK, use STM32_LTDC_PCPOL_ACTIVE_LOW, - otherwise use STM32_LTDC_PCPOL_ACTIVE_HIGH. - - hsync-duration: - type: int - required: true - description: Horizontal synchronization pulse duration, in pixels - - vsync-duration: - type: int - required: true - description: Vertical synchronization pulse duration, in lines - - hbp-duration: - type: int - required: true - description: Horizontal back-porch duration, in pixels - - vbp-duration: - type: int - required: true - description: Vertical back-porch duration, in lines - - hfp-duration: - type: int - required: true - description: Horizontal front porch duration, in pixels - - vfp-duration: - type: int - required: true - description: Vertical front porch duration, in lines - - def-back-color-red: - type: int - description: Default display background color - red - - def-back-color-green: - type: int - description: Default display background color - green - - def-back-color-blue: - type: int - description: Default display background color - blue + disp-on-gpios: + type: phandle-array + description: | + Display on/off GPIO pin. + Configure the GPIO polarity (active high/active low) according to LCD datasheet. + + bl-ctrl-gpios: + type: phandle-array + description: | + Backlight on/off GPIO pin. + Configure the GPIO polarity (active high/active low) according to LCD datasheet. + + ext-sdram: + type: phandle + description: | + External SDRAM in which frame buffer will be stored. + If not defined, internal RAM will be used. + + clocks: + required: true + + interrupts: + required: true + + pinctrl-0: + required: true + + hsync-pol: + type: int + required: true + description: | + Horizontal synchronization pulse polarity. + If HSYNC is active low, use STM32_LTDC_HSPOL_ACTIVE_LOW, + otherwise use STM32_LTDC_HSPOL_ACTIVE_HIGH. + + vsync-pol: + type: int + required: true + description: | + Vertical synchronization pulse polarity. + If VSYNC is active low, use STM32_LTDC_VSPOL_ACTIVE_LOW, + otherwise use STM32_LTDC_VSPOL_ACTIVE_HIGH. + + de-pol: + type: int + required: true + description: | + Data enable pulse polarity. + If DE is active low, use STM32_LTDC_DEPOL_ACTIVE_LOW, + otherwise use STM32_LTDC_DEPOL_ACTIVE_HIGH. + + pclk-pol: + type: int + required: true + description: | + Pixel clock polarity. + If RGB data is sampled on falling edge of PCLK, use STM32_LTDC_PCPOL_ACTIVE_LOW, + otherwise use STM32_LTDC_PCPOL_ACTIVE_HIGH. + + hsync-duration: + type: int + required: true + description: Horizontal synchronization pulse duration, in pixels + + vsync-duration: + type: int + required: true + description: Vertical synchronization pulse duration, in lines + + hbp-duration: + type: int + required: true + description: Horizontal back-porch duration, in pixels + + vbp-duration: + type: int + required: true + description: Vertical back-porch duration, in lines + + hfp-duration: + type: int + required: true + description: Horizontal front porch duration, in pixels + + vfp-duration: + type: int + required: true + description: Vertical front porch duration, in lines + + def-back-color-red: + type: int + description: Default display background color - red + + def-back-color-green: + type: int + description: Default display background color - green + + def-back-color-blue: + type: int + description: Default display background color - blue diff --git a/dts/bindings/display/ultrachip,uc81xx-common.yaml b/dts/bindings/display/ultrachip,uc81xx-common.yaml index 29d8c562a358e8..b2c8a4de35c13e 100644 --- a/dts/bindings/display/ultrachip,uc81xx-common.yaml +++ b/dts/bindings/display/ultrachip,uc81xx-common.yaml @@ -7,36 +7,36 @@ description: UltraChip UC81xx EPD display controller common properties include: [spi-device.yaml, display-controller.yaml] properties: - reset-gpios: - type: phandle-array - required: true - description: RESET pin. - - The RESET pin of UC81xx is active low. - If connected directly the MCU pin should be configured - as active low. - - dc-gpios: - type: phandle-array - required: true - description: DC pin. - - The DC pin of UC81xx is active low (transmission command byte). - If connected directly the MCU pin should be configured - as active low. - - busy-gpios: - type: phandle-array - required: true - description: BUSY pin. - - The BUSY pin of UC81xx is active low. - If connected directly the MCU pin should be configured - as active low. - - softstart: - type: uint8-array - description: Booster Soft Start (BTST) values + reset-gpios: + type: phandle-array + required: true + description: RESET pin. + + The RESET pin of UC81xx is active low. + If connected directly the MCU pin should be configured + as active low. + + dc-gpios: + type: phandle-array + required: true + description: DC pin. + + The DC pin of UC81xx is active low (transmission command byte). + If connected directly the MCU pin should be configured + as active low. + + busy-gpios: + type: phandle-array + required: true + description: BUSY pin. + + The BUSY pin of UC81xx is active low. + If connected directly the MCU pin should be configured + as active low. + + softstart: + type: uint8-array + description: Booster Soft Start (BTST) values child-binding: description: | diff --git a/dts/bindings/dma/altr,msgdma.yaml b/dts/bindings/dma/altr,msgdma.yaml index dd7c662de71e3a..a30ad37de53396 100644 --- a/dts/bindings/dma/altr,msgdma.yaml +++ b/dts/bindings/dma/altr,msgdma.yaml @@ -8,11 +8,11 @@ compatible: "altr,msgdma" include: dma-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#dma-cells": - const: 0 + "#dma-cells": + const: 0 diff --git a/dts/bindings/dma/arm,dma-pl330.yaml b/dts/bindings/dma/arm,dma-pl330.yaml index f43479ccd09b99..03cd65b48c51c0 100644 --- a/dts/bindings/dma/arm,dma-pl330.yaml +++ b/dts/bindings/dma/arm,dma-pl330.yaml @@ -27,14 +27,14 @@ compatible: "arm,dma-pl330" include: dma-controller.yaml properties: - reg: - required: true - microcode: - type: array - required: true - description: microcode's physical memory address - "#dma-cells": - const: 1 + reg: + required: true + microcode: + type: array + required: true + description: microcode's physical memory address + "#dma-cells": + const: 1 # Parameter syntax dma-cells: diff --git a/dts/bindings/dma/atmel,sam-xdmac.yaml b/dts/bindings/dma/atmel,sam-xdmac.yaml index 10b8ca0dd3f360..cd7a2d79b68275 100644 --- a/dts/bindings/dma/atmel,sam-xdmac.yaml +++ b/dts/bindings/dma/atmel,sam-xdmac.yaml @@ -8,19 +8,19 @@ compatible: "atmel,sam-xdmac" include: dma-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true - "#dma-cells": - const: 2 + "#dma-cells": + const: 2 dma-cells: - channel diff --git a/dts/bindings/dma/atmel,sam0-dmac.yaml b/dts/bindings/dma/atmel,sam0-dmac.yaml index 9a39b18e2d0949..06588c0adcbe39 100644 --- a/dts/bindings/dma/atmel,sam0-dmac.yaml +++ b/dts/bindings/dma/atmel,sam0-dmac.yaml @@ -5,14 +5,14 @@ compatible: "atmel,sam0-dmac" include: dma-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#dma-cells": - const: 2 + "#dma-cells": + const: 2 # #dma-cells : Must be <2>. # The 1st cell specifies the DMAC channel to be used for the data transfer. diff --git a/dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml b/dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml index 2eafbd9b7feafe..fa9f33c7468aa1 100644 --- a/dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml +++ b/dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml @@ -8,28 +8,28 @@ include: dma-controller.yaml compatible: brcm,iproc-pax-dma-v1 properties: - reg: - description: | - Register space for the memory mapped PAX DMA controller registers, - It includes data mover engine(dme), ring manager, ring manager common - registers. - required: true - bd-memory: - type: array - description: Uncached memory address to populate dma buffer descriptors - required: true - scr-addr-loc: - type: int - description: Location where address of the scratch buffer host has populated - required: true - scr-size-loc: - type: int - description: Location where size of the scratch buffer host has populated - required: true - interrupts: - type: array - description: Ring manager line interrupt number - pcie-ep: - type: phandle - description: Pcie endpoint handle - required: true + reg: + description: | + Register space for the memory mapped PAX DMA controller registers, + It includes data mover engine(dme), ring manager, ring manager common + registers. + required: true + bd-memory: + type: array + description: Uncached memory address to populate dma buffer descriptors + required: true + scr-addr-loc: + type: int + description: Location where address of the scratch buffer host has populated + required: true + scr-size-loc: + type: int + description: Location where size of the scratch buffer host has populated + required: true + interrupts: + type: array + description: Ring manager line interrupt number + pcie-ep: + type: phandle + description: Pcie endpoint handle + required: true diff --git a/dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml b/dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml index 51d9f77c85e511..5bcff4ac216cea 100644 --- a/dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml +++ b/dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml @@ -8,28 +8,28 @@ include: dma-controller.yaml compatible: brcm,iproc-pax-dma-v2 properties: - reg: - description: | - Register space for the memory mapped PAX DMA controller registers, - It includes data mover engine(dme), ring manager, ring manager common - registers. - required: true - bd-memory: - type: array - description: Uncached memory address to populate dma buffer descriptors - required: true - scr-addr-loc: - type: int - description: Location where address of the scratch buffer host has populated - required: true - scr-size-loc: - type: int - description: Location where size of the scratch buffer host has populated - required: true - interrupts: - type: array - description: Ring manager line interrupt number - pcie-ep: - type: phandle - description: Pcie endpoint handle - required: true + reg: + description: | + Register space for the memory mapped PAX DMA controller registers, + It includes data mover engine(dme), ring manager, ring manager common + registers. + required: true + bd-memory: + type: array + description: Uncached memory address to populate dma buffer descriptors + required: true + scr-addr-loc: + type: int + description: Location where address of the scratch buffer host has populated + required: true + scr-size-loc: + type: int + description: Location where size of the scratch buffer host has populated + required: true + interrupts: + type: array + description: Ring manager line interrupt number + pcie-ep: + type: phandle + description: Pcie endpoint handle + required: true diff --git a/dts/bindings/dma/dma-controller.yaml b/dts/bindings/dma/dma-controller.yaml index 3dfa80b6ac22ba..f3ae84c68b3df3 100644 --- a/dts/bindings/dma/dma-controller.yaml +++ b/dts/bindings/dma/dma-controller.yaml @@ -8,36 +8,36 @@ include: base.yaml bus: dma properties: - "#dma-cells": - type: int - required: true - description: Number of items to expect in a DMA specifier - - dma-channel-mask: - type: int - description: | - Bitmask of available DMA channels in ascending order that are - not reserved by firmware and are available to the - kernel. i.e. first channel corresponds to LSB. - - dma-channels: - type: int - description: Number of DMA channels supported by the controller - - dma-requests: - type: int - description: Number of DMA request signals supported by the controller. - - dma-buf-addr-alignment: - type: int - description: Memory address alignment requirement for DMA buffers used by the controller. - - dma-buf-size-alignment: - type: int - required: false - description: Memory size alignment requirement for DMA buffers used by the controller. - - dma-copy-alignment: - type: int - required: false - description: Minimal chunk of data possible to be copied by the controller. + "#dma-cells": + type: int + required: true + description: Number of items to expect in a DMA specifier + + dma-channel-mask: + type: int + description: | + Bitmask of available DMA channels in ascending order that are + not reserved by firmware and are available to the + kernel. i.e. first channel corresponds to LSB. + + dma-channels: + type: int + description: Number of DMA channels supported by the controller + + dma-requests: + type: int + description: Number of DMA request signals supported by the controller. + + dma-buf-addr-alignment: + type: int + description: Memory address alignment requirement for DMA buffers used by the controller. + + dma-buf-size-alignment: + type: int + required: false + description: Memory size alignment requirement for DMA buffers used by the controller. + + dma-copy-alignment: + type: int + required: false + description: Minimal chunk of data possible to be copied by the controller. diff --git a/dts/bindings/dma/dmamux-controller.yaml b/dts/bindings/dma/dmamux-controller.yaml index 5969a265e9bf38..41517a15d5f70e 100644 --- a/dts/bindings/dma/dmamux-controller.yaml +++ b/dts/bindings/dma/dmamux-controller.yaml @@ -8,23 +8,23 @@ include: base.yaml bus: dmamux properties: - "#dma-cells": - type: int - required: true - description: Number of items to expect in a DMA specifier (see dma V2) + "#dma-cells": + type: int + required: true + description: Number of items to expect in a DMA specifier (see dma V2) - dma-channels: - type: int - required: true - description: Number of DMAMUX output request channels supported by the controller + dma-channels: + type: int + required: true + description: Number of DMAMUX output request channels supported by the controller - dma-generators: - type: int - description: Number of DMAMUX Request generator supported by the controller + dma-generators: + type: int + description: Number of DMAMUX Request generator supported by the controller - dma-requests: - type: int - required: true - description: | - Number of DMAMUX Peripheral Request Line inputs supported by the controller - This is not directly the value to program in the DMAREQ_ID of the DMAMUX_CxCR + dma-requests: + type: int + required: true + description: | + Number of DMAMUX Peripheral Request Line inputs supported by the controller + This is not directly the value to program in the DMAREQ_ID of the DMAMUX_CxCR diff --git a/dts/bindings/dma/intel,adsp-gpdma.yaml b/dts/bindings/dma/intel,adsp-gpdma.yaml index 2e75511aaa21df..e71f05604ebfbc 100644 --- a/dts/bindings/dma/intel,adsp-gpdma.yaml +++ b/dts/bindings/dma/intel,adsp-gpdma.yaml @@ -8,12 +8,12 @@ compatible: "intel,adsp-gpdma" include: snps,designware-dma.yaml properties: - shim: - type: array - required: true + shim: + type: array + required: true - dma-buf-size-alignment: - required: true + dma-buf-size-alignment: + required: true - dma-copy-alignment: - required: true + dma-copy-alignment: + required: true diff --git a/dts/bindings/dma/intel,adsp-hda.yaml b/dts/bindings/dma/intel,adsp-hda.yaml index 8cb482f125c454..e9732412f1fcdc 100644 --- a/dts/bindings/dma/intel,adsp-hda.yaml +++ b/dts/bindings/dma/intel,adsp-hda.yaml @@ -6,20 +6,20 @@ include: dma-controller.yaml properties: - reg: - required: true + reg: + required: true - dma-channels: - required: true + dma-channels: + required: true - "#dma-cells": - const: 1 + "#dma-cells": + const: 1 - "dma-buf-addr-alignment": - required: true + "dma-buf-addr-alignment": + required: true - "dma-buf-size-alignment": - required: true + "dma-buf-size-alignment": + required: true - "dma-copy-alignment": - required: true + "dma-copy-alignment": + required: true diff --git a/dts/bindings/dma/nxp,lpc-dma.yaml b/dts/bindings/dma/nxp,lpc-dma.yaml index ac3db2365e155b..dd4fafd02d0194 100644 --- a/dts/bindings/dma/nxp,lpc-dma.yaml +++ b/dts/bindings/dma/nxp,lpc-dma.yaml @@ -8,19 +8,19 @@ compatible: "nxp,lpc-dma" include: dma-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - dma-channels: - required: true + dma-channels: + required: true - "#dma-cells": - type: int - required: true - description: Number of items to expect in a DMA specifier + "#dma-cells": + type: int + required: true + description: Number of items to expect in a DMA specifier # - #dma-cells : Must be <1>. # channel: the dma channel, each channel supports one DMA request line diff --git a/dts/bindings/dma/nxp,mcux-edma.yaml b/dts/bindings/dma/nxp,mcux-edma.yaml index 1994e73584bc28..2ce3b9c6eca25c 100644 --- a/dts/bindings/dma/nxp,mcux-edma.yaml +++ b/dts/bindings/dma/nxp,mcux-edma.yaml @@ -8,30 +8,30 @@ compatible: "nxp,mcux-edma" include: dma-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - dma-channels: - required: true + dma-channels: + required: true - dma-requests: - required: true + dma-requests: + required: true - nxp,mem2mem: - type: boolean - description: If the DMA controller supports memory to memory transfer + nxp,mem2mem: + type: boolean + description: If the DMA controller supports memory to memory transfer - nxp,a_on: - type: boolean - description: If the DMA controller supports always on + nxp,a_on: + type: boolean + description: If the DMA controller supports always on - "#dma-cells": - type: int - required: true - description: Number of items to expect in a DMAMUX specifier + "#dma-cells": + type: int + required: true + description: Number of items to expect in a DMAMUX specifier # Parameter syntax of NXP follows the dmamux client dts syntax # in the Linux kernel declared in diff --git a/dts/bindings/dma/snps,designware-dma.yaml b/dts/bindings/dma/snps,designware-dma.yaml index d7c9132f1e3fac..bcc85ffcc769d1 100644 --- a/dts/bindings/dma/snps,designware-dma.yaml +++ b/dts/bindings/dma/snps,designware-dma.yaml @@ -8,14 +8,14 @@ compatible: "snps,designware-dma" include: dma-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#dma-cells": - const: 1 + "#dma-cells": + const: 1 dma-cells: - channel diff --git a/dts/bindings/dma/st,stm32-dma-v1.yaml b/dts/bindings/dma/st,stm32-dma-v1.yaml index 1551a0a26e86ce..8e33887dacef64 100644 --- a/dts/bindings/dma/st,stm32-dma-v1.yaml +++ b/dts/bindings/dma/st,stm32-dma-v1.yaml @@ -75,8 +75,8 @@ compatible: "st,stm32-dma-v1" include: st,stm32-dma.yaml properties: - "#dma-cells": - const: 4 + "#dma-cells": + const: 4 # Parameter syntax of stm32 follows the dma client dts syntax # in the Linux kernel declared in diff --git a/dts/bindings/dma/st,stm32-dma-v2.yaml b/dts/bindings/dma/st,stm32-dma-v2.yaml index fbeb9c2106a3d6..d5dd9aed43d935 100644 --- a/dts/bindings/dma/st,stm32-dma-v2.yaml +++ b/dts/bindings/dma/st,stm32-dma-v2.yaml @@ -69,8 +69,8 @@ compatible: "st,stm32-dma-v2" include: st,stm32-dma.yaml properties: - "#dma-cells": - const: 3 + "#dma-cells": + const: 3 # Parameter syntax of stm32 follows the dma client dts syntax # in the Linux kernel declared in diff --git a/dts/bindings/dma/st,stm32-dma-v2bis.yaml b/dts/bindings/dma/st,stm32-dma-v2bis.yaml index 64f04c3ed7a8cf..7414d15cc3b81a 100644 --- a/dts/bindings/dma/st,stm32-dma-v2bis.yaml +++ b/dts/bindings/dma/st,stm32-dma-v2bis.yaml @@ -64,8 +64,8 @@ include: - name: st,stm32-dma.yaml properties: - "#dma-cells": - const: 2 + "#dma-cells": + const: 2 # Parameter syntax of stm32 follows the dma client dts syntax # in the Linux kernel declared in diff --git a/dts/bindings/dma/st,stm32-dma.yaml b/dts/bindings/dma/st,stm32-dma.yaml index 4548da2a69da66..eb9b49b751da51 100644 --- a/dts/bindings/dma/st,stm32-dma.yaml +++ b/dts/bindings/dma/st,stm32-dma.yaml @@ -16,21 +16,21 @@ compatible: "st,stm32-dma" include: dma-controller.yaml properties: - reg: - required: true - - interrupts: - required: true - - st,mem2mem: - type: boolean - description: If the DMA controller V1 supports memory to memory transfer - - dma-offset: - type: int - description: | - offset in the table of channels when mapping to a DMAMUX - for 1st dma instance, offset is 0, - for 2nd dma instance, offset is the nb of dma channels of the 1st dma, - for 3rd dma instance, offset is the nb of dma channels of the 2nd dma - plus the nb of dma channels of the 1st dma instance, etc. + reg: + required: true + + interrupts: + required: true + + st,mem2mem: + type: boolean + description: If the DMA controller V1 supports memory to memory transfer + + dma-offset: + type: int + description: | + offset in the table of channels when mapping to a DMAMUX + for 1st dma instance, offset is 0, + for 2nd dma instance, offset is the nb of dma channels of the 1st dma, + for 3rd dma instance, offset is the nb of dma channels of the 2nd dma + plus the nb of dma channels of the 1st dma instance, etc. diff --git a/dts/bindings/dma/st,stm32-dmamux.yaml b/dts/bindings/dma/st,stm32-dmamux.yaml index dbb03f77b084cb..5ce00b95290199 100644 --- a/dts/bindings/dma/st,stm32-dmamux.yaml +++ b/dts/bindings/dma/st,stm32-dmamux.yaml @@ -63,14 +63,14 @@ compatible: "st,stm32-dmamux" include: dmamux-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#dma-cells": - const: 3 + "#dma-cells": + const: 3 # Parameter syntax of stm32 follows the dma client dts syntax # in the Linux kernel declared in diff --git a/dts/bindings/dma/st,stm32u5-dma.yaml b/dts/bindings/dma/st,stm32u5-dma.yaml index 10a660ef20af9d..57b0ce0138ea14 100644 --- a/dts/bindings/dma/st,stm32u5-dma.yaml +++ b/dts/bindings/dma/st,stm32u5-dma.yaml @@ -55,8 +55,8 @@ compatible: "st,stm32u5-dma" include: st,stm32-dma.yaml properties: - "#dma-cells": - const: 3 + "#dma-cells": + const: 3 dma-cells: - channel diff --git a/dts/bindings/dsa/microchip,ksz8794.yaml b/dts/bindings/dsa/microchip,ksz8794.yaml index 7bc1c3d5026965..a602f41e124cd7 100644 --- a/dts/bindings/dsa/microchip,ksz8794.yaml +++ b/dts/bindings/dsa/microchip,ksz8794.yaml @@ -8,26 +8,26 @@ compatible: "microchip,ksz8794" include: [microchip_dsa.yaml] properties: - workaround: - type: int - description: | - Define the applied workaround for the switch used for - short connections. Use bitmask to select the workaround or more - 0x01: Short Cable Problems with the KSZ8795 Family - 0x02: 1) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family - 0x04: 2) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family - mii-lowspeed-drivestrength: - type: int - description: | - Define the Low-Speed Interface Drive Strength for MII and RMMI - Supported values 2,4,8,12,16,20,24,28mA - see Register 163 (0xA3): Global Control 20 for more details - enum: - - 2 - - 4 - - 8 - - 12 - - 16 - - 20 - - 24 - - 28 + workaround: + type: int + description: | + Define the applied workaround for the switch used for + short connections. Use bitmask to select the workaround or more + 0x01: Short Cable Problems with the KSZ8795 Family + 0x02: 1) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family + 0x04: 2) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family + mii-lowspeed-drivestrength: + type: int + description: | + Define the Low-Speed Interface Drive Strength for MII and RMMI + Supported values 2,4,8,12,16,20,24,28mA + see Register 163 (0xA3): Global Control 20 for more details + enum: + - 2 + - 4 + - 8 + - 12 + - 16 + - 20 + - 24 + - 28 diff --git a/dts/bindings/dsa/microchip_dsa.yaml b/dts/bindings/dsa/microchip_dsa.yaml index f77a21d34d2dcf..8762fec748ced6 100644 --- a/dts/bindings/dsa/microchip_dsa.yaml +++ b/dts/bindings/dsa/microchip_dsa.yaml @@ -6,31 +6,31 @@ description: | include: [spi-device.yaml] properties: - dsa-master-port: - type: phandle - description: Phandle to master port. - dsa-slave-ports: - type: int - description: Number of slave ports on the switch - spi-cpha: - type: boolean - description: | - Set to indicate phase starts with asserted half-phase (CPHA=1). - For this driver using this property requires also using cpol. - spi-cpol: - type: boolean - description: | - Set to indicate clock leading edge is falling (CPOL=1). - For this driver using this property requires also using cpha. - reset-gpios: - type: phandle-array - description: | - The pin is asserted for 10ms during boot to reset the KSZ8794. + dsa-master-port: + type: phandle + description: Phandle to master port. + dsa-slave-ports: + type: int + description: Number of slave ports on the switch + spi-cpha: + type: boolean + description: | + Set to indicate phase starts with asserted half-phase (CPHA=1). + For this driver using this property requires also using cpol. + spi-cpol: + type: boolean + description: | + Set to indicate clock leading edge is falling (CPOL=1). + For this driver using this property requires also using cpha. + reset-gpios: + type: phandle-array + description: | + The pin is asserted for 10ms during boot to reset the KSZ8794. child-binding: - description: Properties of slave port - properties: - local-mac-address: - type: uint8-array - description: | - Specifies the MAC address that was assigned to the port + description: Properties of slave port + properties: + local-mac-address: + type: uint8-array + description: | + Specifies the MAC address that was assigned to the port diff --git a/dts/bindings/ec_host_cmd_perhip/zephyr,ec-host-cmd-periph-espi.yaml b/dts/bindings/ec_host_cmd_perhip/zephyr,ec-host-cmd-periph-espi.yaml index 1114b3b3cd9d09..1bef0c0daeeb6b 100644 --- a/dts/bindings/ec_host_cmd_perhip/zephyr,ec-host-cmd-periph-espi.yaml +++ b/dts/bindings/ec_host_cmd_perhip/zephyr,ec-host-cmd-periph-espi.yaml @@ -7,9 +7,9 @@ compatible: "zephyr,ec-host-cmd-periph-espi" include: base.yaml properties: - bus: - required: true - type: phandle - description: - Phandle to the eSPI bus which will be used for communication with AP - by the host commands subsystem + bus: + required: true + type: phandle + description: + Phandle to the eSPI bus which will be used for communication with AP + by the host commands subsystem diff --git a/dts/bindings/espi/microchip,xec-espi-host-dev.yaml b/dts/bindings/espi/microchip,xec-espi-host-dev.yaml index 70802cb81563a4..0f8a8d62cc7211 100644 --- a/dts/bindings/espi/microchip,xec-espi-host-dev.yaml +++ b/dts/bindings/espi/microchip,xec-espi-host-dev.yaml @@ -10,59 +10,59 @@ include: [base.yaml] on-bus: espi properties: - reg: - required: true + reg: + required: true - ldn: - type: int - required: true - description: logical device number + ldn: + type: int + required: true + description: logical device number - girqs: - type: array - description: array of GIRQ and bit positions + girqs: + type: array + description: array of GIRQ and bit positions - pcrs: - type: array - description: PCR sleep register index and bit position + pcrs: + type: array + description: PCR sleep register index and bit position - # optional properties application to different host facing devices - host-io: - type: int - description: | - Logical device Host I/O (x86) base. Refer to SoC documentation for the - number of I/O decoders implemented by a device (1 or 2) and the fixed - I/O masks. + # optional properties application to different host facing devices + host-io: + type: int + description: | + Logical device Host I/O (x86) base. Refer to SoC documentation for the + number of I/O decoders implemented by a device (1 or 2) and the fixed + I/O masks. - host-io-addr-mask: - type: int - description: | - Host I/O address mask. This value is fixed for all HW and is only - used by Port80 BIOS debug alias device to specify the byte lane the - alias address is mapped to in the 80h to 83h I/O range. + host-io-addr-mask: + type: int + description: | + Host I/O address mask. This value is fixed for all HW and is only + used by Port80 BIOS debug alias device to specify the byte lane the + alias address is mapped to in the 80h to 83h I/O range. - host-mem: - type: int - description: | - Logical device Host memory (x86) base address. Refer to SoC - documentation for which logical devices implement a memory decoder - and the fixed memory address masking. + host-mem: + type: int + description: | + Logical device Host memory (x86) base address. Refer to SoC + documentation for which logical devices implement a memory decoder + and the fixed memory address masking. - emi-mems: - type: array - description: | - Each EMI host device supports Host access to two SoC data memory - regions. Each region requires three configuration parameters: - Base address in the SoC data memory, read limit, and write limit. - If bits[14:2] of the address written by the Host to the EC address - register is less than the limit value the access is allowed. Bit[15] - of the EC address selects which of the two memory regions is accessed. + emi-mems: + type: array + description: | + Each EMI host device supports Host access to two SoC data memory + regions. Each region requires three configuration parameters: + Base address in the SoC data memory, read limit, and write limit. + If bits[14:2] of the address written by the Host to the EC address + register is less than the limit value the access is allowed. Bit[15] + of the EC address selects which of the two memory regions is accessed. - "emi-mem-cells": - type: int - const: 3 + "emi-mem-cells": + type: int + const: 3 emi-mem-cells: - - base - - rdlimit - - wrlimit + - base + - rdlimit + - wrlimit diff --git a/dts/bindings/espi/microchip,xec-espi-saf-v2.yaml b/dts/bindings/espi/microchip,xec-espi-saf-v2.yaml index 8ab411910e0266..9cd163d05f8150 100644 --- a/dts/bindings/espi/microchip,xec-espi-saf-v2.yaml +++ b/dts/bindings/espi/microchip,xec-espi-saf-v2.yaml @@ -9,51 +9,51 @@ compatible: "microchip,xec-espi-saf-v2" include: espi-controller.yaml properties: - reg: - description: mmio register space - required: true + reg: + description: mmio register space + required: true - girqs: - type: array - required: true - description: Array of encoded interrupt information + girqs: + type: array + required: true + description: Array of encoded interrupt information - pcrs: - type: array - required: true - description: Array of eSPI PCR register index and bit position + pcrs: + type: array + required: true + description: Array of eSPI PCR register index and bit position - poll-timeout: - type: int - description: poll flash busy timeout in 32KHz periods + poll-timeout: + type: int + description: poll flash busy timeout in 32KHz periods - poll-interval: - type: int - description: interval between flash busy poll in 20 ns units + poll-interval: + type: int + description: interval between flash busy poll in 20 ns units - consec-rd-timeout: - type: int - description: timeout after last read to resume supended operations in 20 ns units + consec-rd-timeout: + type: int + description: timeout after last read to resume supended operations in 20 ns units - sus-chk-delay: - type: int - description: hold off poll after suspend in 20 ns units + sus-chk-delay: + type: int + description: hold off poll after suspend in 20 ns units - sus-rsm-interval: - type: int - description: force suspended erase or program to resume in 32KHz periods + sus-rsm-interval: + type: int + description: force suspended erase or program to resume in 32KHz periods - "#girq-cells": - type: int - const: 1 + "#girq-cells": + type: int + const: 1 - "#pcr-cells": - type: int - const: 2 + "#pcr-cells": + type: int + const: 2 girq-cells: - - girqinfo + - girqinfo pcr-cells: - - regidx - - bitpos + - regidx + - bitpos diff --git a/dts/bindings/espi/microchip,xec-espi-saf.yaml b/dts/bindings/espi/microchip,xec-espi-saf.yaml index a5742a4fea0bbf..995052bbf69fd5 100644 --- a/dts/bindings/espi/microchip,xec-espi-saf.yaml +++ b/dts/bindings/espi/microchip,xec-espi-saf.yaml @@ -9,30 +9,30 @@ compatible: "microchip,xec-espi-saf" include: espi-controller.yaml properties: - reg: - description: mmio register space - required: true + reg: + description: mmio register space + required: true - io_girq: - type: int - description: soc group irq index for eSPI I/O + io_girq: + type: int + description: soc group irq index for eSPI I/O - poll_timeout: - type: int - description: poll flash busy timeout in 32KHz periods + poll_timeout: + type: int + description: poll flash busy timeout in 32KHz periods - poll_interval: - type: int - description: interval between flash busy poll in 20 ns units + poll_interval: + type: int + description: interval between flash busy poll in 20 ns units - consec_rd_timeout: - type: int - description: timeout after last read to resume supended operations in 20 ns units + consec_rd_timeout: + type: int + description: timeout after last read to resume supended operations in 20 ns units - sus_chk_delay: - type: int - description: hold off poll after suspend in 20 ns units + sus_chk_delay: + type: int + description: hold off poll after suspend in 20 ns units - sus_rsm_interval: - type: int - description: force suspended erase or program to resume in 32KHz periods + sus_rsm_interval: + type: int + description: force suspended erase or program to resume in 32KHz periods diff --git a/dts/bindings/espi/microchip,xec-espi-v2.yaml b/dts/bindings/espi/microchip,xec-espi-v2.yaml index 071d639c9a72cd..2a6e2b39ae90be 100644 --- a/dts/bindings/espi/microchip,xec-espi-v2.yaml +++ b/dts/bindings/espi/microchip,xec-espi-v2.yaml @@ -9,27 +9,27 @@ compatible: "microchip,xec-espi-v2" include: [espi-controller.yaml, pinctrl-device.yaml] properties: - reg: - description: mmio register space - required: true - - reg-names: - required: true - description: Name of each register space - - girqs: - type: array - required: true - description: | - Array of encoded interrupt information - - pcrs: - type: array - required: true - description: eSPI PCR register index and bit position - - pinctrl-0: - required: true - - pinctrl-names: - required: true + reg: + description: mmio register space + required: true + + reg-names: + required: true + description: Name of each register space + + girqs: + type: array + required: true + description: | + Array of encoded interrupt information + + pcrs: + type: array + required: true + description: eSPI PCR register index and bit position + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/espi/microchip,xec-espi-vw-routing.yaml b/dts/bindings/espi/microchip,xec-espi-vw-routing.yaml index e787e33e00e443..89e2f709926aec 100644 --- a/dts/bindings/espi/microchip,xec-espi-vw-routing.yaml +++ b/dts/bindings/espi/microchip,xec-espi-vw-routing.yaml @@ -6,19 +6,19 @@ description: Microchip XEC eSPI Virtual Wire routing compatible: "microchip,xec-espi-vw-routing" child-binding: - description: | - Child node containing the routing of an eSPI virtual wire to the SoC - VW registers and ECIA GIRQ registers. - properties: - vw-reg: - type: array - required: true - description: vw signal's register index and vw bitmask. + description: | + Child node containing the routing of an eSPI virtual wire to the SoC + VW registers and ECIA GIRQ registers. + properties: + vw-reg: + type: array + required: true + description: vw signal's register index and vw bitmask. - vw-girq: - type: array - description: | - Routing of MSVW source to aggregated GIRQs + vw-girq: + type: array + description: | + Routing of MSVW source to aggregated GIRQs - Example: OOB_RST_WARN is source 2 of MSVW01 routed to GIRQ24 b[5] - vw-girq = <24 5>; + Example: OOB_RST_WARN is source 2 of MSVW01 routed to GIRQ24 b[5] + vw-girq = <24 5>; diff --git a/dts/bindings/espi/microchip,xec-espi.yaml b/dts/bindings/espi/microchip,xec-espi.yaml index d793952964832c..b3fb2474a04f0c 100644 --- a/dts/bindings/espi/microchip,xec-espi.yaml +++ b/dts/bindings/espi/microchip,xec-espi.yaml @@ -8,27 +8,27 @@ compatible: "microchip,xec-espi" include: [espi-controller.yaml, pinctrl-device.yaml] properties: - reg: - description: mmio register space - required: true - - io_girq: - type: int - description: soc group irq index for eSPI I/O - required: true - - vw_girqs: - type: array - description: soc group irq indexes for eSPI virtual wires channel - required: true - - pc_girq: - type: int - description: soc group irq index for eSPI peripheral channel - required: true - - pinctrl-0: - required: true - - pinctrl-names: - required: true + reg: + description: mmio register space + required: true + + io_girq: + type: int + description: soc group irq index for eSPI I/O + required: true + + vw_girqs: + type: array + description: soc group irq indexes for eSPI virtual wires channel + required: true + + pc_girq: + type: int + description: soc group irq index for eSPI peripheral channel + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/espi/nuvoton,npcx-espi-vw-conf.yaml b/dts/bindings/espi/nuvoton,npcx-espi-vw-conf.yaml index 1a9bc5bc805864..1b6e75028c5ef3 100644 --- a/dts/bindings/espi/nuvoton,npcx-espi-vw-conf.yaml +++ b/dts/bindings/espi/nuvoton,npcx-espi-vw-conf.yaml @@ -6,20 +6,20 @@ description: Nuvoton NPCX eSPI Virtual Wire (VW) mapping child node compatible: "nuvoton,npcx-espi-vw-conf" child-binding: - description: | - Child node to to present the mapping between VW signal, its core register and input source of - MIWU + description: | + Child node to to present the mapping between VW signal, its core register and input source of + MIWU - properties: - vw-reg: - type: array - required: true - description: vw signal's register index and vw bitmask. + properties: + vw-reg: + type: array + required: true + description: vw signal's register index and vw bitmask. - vw-wui: - type: phandle - description: | - Mapping table between Wake-Up Input (WUI) and vw input signal. + vw-wui: + type: phandle + description: | + Mapping table between Wake-Up Input (WUI) and vw input signal. - For example the WUI mapping on NPCX7 for VW_SLP5 would be - vw-wui = <&wui_vw_slp_s5>; + For example the WUI mapping on NPCX7 for VW_SLP5 would be + vw-wui = <&wui_vw_slp_s5>; diff --git a/dts/bindings/espi/nuvoton,npcx-espi.yaml b/dts/bindings/espi/nuvoton,npcx-espi.yaml index eb5cd9bdb66bdc..ebce305a3affc7 100644 --- a/dts/bindings/espi/nuvoton,npcx-espi.yaml +++ b/dts/bindings/espi/nuvoton,npcx-espi.yaml @@ -8,25 +8,25 @@ compatible: "nuvoton,npcx-espi" include: [espi-controller.yaml, pinctrl-device.yaml] properties: - reg: - description: mmio register space - required: true + reg: + description: mmio register space + required: true - clocks: - required: true - description: configurations of device source clock controller + clocks: + required: true + description: configurations of device source clock controller - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - espi-rst-wui: - type: phandle - required: true - description: | - Mapping table between Wake-Up Input (WUI) and ESPI_RST signal. + espi-rst-wui: + type: phandle + required: true + description: | + Mapping table between Wake-Up Input (WUI) and ESPI_RST signal. - For example the WUI mapping on NPCX7 would be - espi-rst-wui = <&wui_cr_sin1>; + For example the WUI mapping on NPCX7 would be + espi-rst-wui = <&wui_cr_sin1>; diff --git a/dts/bindings/espi/nuvoton,npcx-host-sub.yaml b/dts/bindings/espi/nuvoton,npcx-host-sub.yaml index c75bd0c44c59d6..d36d0f59f04413 100644 --- a/dts/bindings/espi/nuvoton,npcx-host-sub.yaml +++ b/dts/bindings/espi/nuvoton,npcx-host-sub.yaml @@ -8,20 +8,20 @@ compatible: "nuvoton,npcx-host-sub" include: [base.yaml] properties: - reg: - description: mmio register space - required: true + reg: + description: mmio register space + required: true - clocks: - required: true - description: configurations of device source clock controller + clocks: + required: true + description: configurations of device source clock controller - host-acc-wui: - type: phandle - required: true - description: | - Mapping table between Wake-Up Input (WUI) and any legacy host - access transactions. + host-acc-wui: + type: phandle + required: true + description: | + Mapping table between Wake-Up Input (WUI) and any legacy host + access transactions. - For example the WUI mapping on NPCX7 would be - host-acc-wui = <&wui_host_acc>; + For example the WUI mapping on NPCX7 would be + host-acc-wui = <&wui_host_acc>; diff --git a/dts/bindings/espi/nuvoton,npcx-host-uart.yaml b/dts/bindings/espi/nuvoton,npcx-host-uart.yaml index 0cbe841a37a9e6..f3a9fafca73a14 100644 --- a/dts/bindings/espi/nuvoton,npcx-host-uart.yaml +++ b/dts/bindings/espi/nuvoton,npcx-host-uart.yaml @@ -8,7 +8,7 @@ compatible: "nuvoton,npcx-host-uart" include: [base.yaml, pinctrl-device.yaml] properties: - pinctrl-0: - required: true - pinctrl-names: - required: true + pinctrl-0: + required: true + pinctrl-names: + required: true diff --git a/dts/bindings/espi/zephyr,espi-emul-controller.yaml b/dts/bindings/espi/zephyr,espi-emul-controller.yaml index cc6eb082823363..51e0f4881bdde1 100644 --- a/dts/bindings/espi/zephyr,espi-emul-controller.yaml +++ b/dts/bindings/espi/zephyr,espi-emul-controller.yaml @@ -8,5 +8,5 @@ compatible: "zephyr,espi-emul-controller" include: espi-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/ethernet/atmel,gmac-common.yaml b/dts/bindings/ethernet/atmel,gmac-common.yaml index 6557f8ea816a11..95e06332317866 100644 --- a/dts/bindings/ethernet/atmel,gmac-common.yaml +++ b/dts/bindings/ethernet/atmel,gmac-common.yaml @@ -3,56 +3,56 @@ # SPDX-License-Identifier: Apache-2.0 include: - - name: ethernet.yaml - - name: pinctrl-device.yaml + - name: ethernet.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true - - num-queues: - type: int - required: true - description: | - Number of hardware TX and RX queues. - - max-frame-size: - type: int - default: 1518 - description: | - Maximum ethernet frame size. The current ethernet frame sizes - supported by hardware are 1518, 1536 and 10240 (jumbo frames). This - means that normally gmac will reject any frame above max-frame-size - value. The default value is 1518, which represents an usual - IEEE 802.3 ethernet frame: - - Ethernet Frame [ 14 MAC HEADER | 1500 MTU | 4 FCS ] = 1518 bytes - - When using value 1536 it is possible extend ethernet MAC HEADER up - to 32 bytes. The hardware have support to jumbo frames and it can be - enabled by selecting the value 10240. - - max-speed: - type: int - default: 100 - description: | - This specifies maximum speed in Mbit/s supported by the device. The - gmac driver supports 10Mbit/s and 100Mbit/s. Using 100, as default - value, enables driver to configure 10 and 100Mbit/s speeds. - - phy-connection-type: - type: string - enum: - - "rmii" - - "mii" - default: "rmii" - description: | - Phy connection type define the physical interface connection between - PHY and MAC. The default value uses gmac register reset value, which - represents Reduced Media-Independent Interface (RMII) mode. - - This property must be used with pinctrl-0. - - mac-eeprom: - type: phandle - description: phandle to I2C eeprom device node. + reg: + required: true + + num-queues: + type: int + required: true + description: | + Number of hardware TX and RX queues. + + max-frame-size: + type: int + default: 1518 + description: | + Maximum ethernet frame size. The current ethernet frame sizes + supported by hardware are 1518, 1536 and 10240 (jumbo frames). This + means that normally gmac will reject any frame above max-frame-size + value. The default value is 1518, which represents an usual + IEEE 802.3 ethernet frame: + + Ethernet Frame [ 14 MAC HEADER | 1500 MTU | 4 FCS ] = 1518 bytes + + When using value 1536 it is possible extend ethernet MAC HEADER up + to 32 bytes. The hardware have support to jumbo frames and it can be + enabled by selecting the value 10240. + + max-speed: + type: int + default: 100 + description: | + This specifies maximum speed in Mbit/s supported by the device. The + gmac driver supports 10Mbit/s and 100Mbit/s. Using 100, as default + value, enables driver to configure 10 and 100Mbit/s speeds. + + phy-connection-type: + type: string + enum: + - "rmii" + - "mii" + default: "rmii" + description: | + Phy connection type define the physical interface connection between + PHY and MAC. The default value uses gmac register reset value, which + represents Reduced Media-Independent Interface (RMII) mode. + + This property must be used with pinctrl-0. + + mac-eeprom: + type: phandle + description: phandle to I2C eeprom device node. diff --git a/dts/bindings/ethernet/atmel,sam-gmac.yaml b/dts/bindings/ethernet/atmel,sam-gmac.yaml index 598a99107af488..d73210c7c7da72 100644 --- a/dts/bindings/ethernet/atmel,sam-gmac.yaml +++ b/dts/bindings/ethernet/atmel,sam-gmac.yaml @@ -8,11 +8,11 @@ compatible: "atmel,sam-gmac" include: atmel,gmac-common.yaml properties: - peripheral-id: - type: int - required: true - description: | - The peripheral identifier is required for Atmel SAMs MCUs to indicate - which is the clock line associated with a specific peripheral. This - clock line is defined at Power Management Controller (PMC) and it - enables the peripheral. + peripheral-id: + type: int + required: true + description: | + The peripheral identifier is required for Atmel SAMs MCUs to indicate + which is the clock line associated with a specific peripheral. This + clock line is defined at Power Management Controller (PMC) and it + enables the peripheral. diff --git a/dts/bindings/ethernet/ethernet,fixed-link.yaml b/dts/bindings/ethernet/ethernet,fixed-link.yaml index 6a6f9447f76df8..27c5147acfdd4d 100644 --- a/dts/bindings/ethernet/ethernet,fixed-link.yaml +++ b/dts/bindings/ethernet/ethernet,fixed-link.yaml @@ -3,15 +3,15 @@ # SPDX-License-Identifier: Apache-2.0 child-binding: - description: Fixed link ethernet node - properties: - speed: - type: int - required: true - description: The speed of fixed link - enum: - - 100 - - 10 - full-duplex: - type: boolean - description: The fixed link operates in full duplex mode + description: Fixed link ethernet node + properties: + speed: + type: int + required: true + description: The speed of fixed link + enum: + - 100 + - 10 + full-duplex: + type: boolean + description: The fixed link operates in full duplex mode diff --git a/dts/bindings/ethernet/ethernet-phy.yaml b/dts/bindings/ethernet/ethernet-phy.yaml index 0c741da781a229..6319f1b9a188fd 100644 --- a/dts/bindings/ethernet/ethernet-phy.yaml +++ b/dts/bindings/ethernet/ethernet-phy.yaml @@ -10,22 +10,22 @@ compatible: "ethernet-phy" include: phy.yaml properties: - address: - type: int - required: true - description: PHY address - mdio: - type: phandle - required: true - description: MDIO driver node - no-reset: - type: boolean - description: Do not reset the PHY during initialization - fixed-link: - type: string - description: This link is fixed and does not require PHY configuration - enum: - - "10BASE-T Half-Duplex" - - "10BASE-T Full-Duplex" - - "100BASE-T Half-Duplex" - - "100BASE-T Full-Duplex" + address: + type: int + required: true + description: PHY address + mdio: + type: phandle + required: true + description: MDIO driver node + no-reset: + type: boolean + description: Do not reset the PHY during initialization + fixed-link: + type: string + description: This link is fixed and does not require PHY configuration + enum: + - "10BASE-T Half-Duplex" + - "10BASE-T Full-Duplex" + - "100BASE-T Half-Duplex" + - "100BASE-T Full-Duplex" diff --git a/dts/bindings/ethernet/ethernet.yaml b/dts/bindings/ethernet/ethernet.yaml index c47543dfb1f9ab..cd30125ea15daa 100644 --- a/dts/bindings/ethernet/ethernet.yaml +++ b/dts/bindings/ethernet/ethernet.yaml @@ -6,18 +6,18 @@ include: base.yaml properties: - local-mac-address: - type: uint8-array - description: Specifies the MAC address that was assigned to the network device - zephyr,random-mac-address: - type: boolean - description: | - Use a random MAC address generated when the driver is initialized. - Note that using this choice and rebooting a board may leave stale - MAC address in peers' ARP caches and lead to issues and delays in - communication. (Use "ip neigh flush all" on Linux peers to clear - ARP cache.) + local-mac-address: + type: uint8-array + description: Specifies the MAC address that was assigned to the network device + zephyr,random-mac-address: + type: boolean + description: | + Use a random MAC address generated when the driver is initialized. + Note that using this choice and rebooting a board may leave stale + MAC address in peers' ARP caches and lead to issues and delays in + communication. (Use "ip neigh flush all" on Linux peers to clear + ARP cache.) - It is driver specific how the OUI octets are handled. + It is driver specific how the OUI octets are handled. - If set we ignore any setting of the local-mac-address property. + If set we ignore any setting of the local-mac-address property. diff --git a/dts/bindings/ethernet/intel,e1000.yaml b/dts/bindings/ethernet/intel,e1000.yaml index 38654c8e2dc603..a74978163c946e 100644 --- a/dts/bindings/ethernet/intel,e1000.yaml +++ b/dts/bindings/ethernet/intel,e1000.yaml @@ -8,5 +8,5 @@ compatible: "intel,e1000" include: [base.yaml, pcie-device.yaml] properties: - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/ethernet/litex,eth0.yaml b/dts/bindings/ethernet/litex,eth0.yaml index 866b40af814f99..50885777b19717 100644 --- a/dts/bindings/ethernet/litex,eth0.yaml +++ b/dts/bindings/ethernet/litex,eth0.yaml @@ -8,8 +8,8 @@ compatible: "litex,eth0" include: ethernet.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/ethernet/microchip,enc28j60.yaml b/dts/bindings/ethernet/microchip,enc28j60.yaml index 9e500e4b7d5cd0..95f93f42d9eccb 100644 --- a/dts/bindings/ethernet/microchip,enc28j60.yaml +++ b/dts/bindings/ethernet/microchip,enc28j60.yaml @@ -8,11 +8,11 @@ compatible: "microchip,enc28j60" include: [spi-device.yaml, ethernet.yaml] properties: - int-gpios: - type: phandle-array - required: true - description: Interrupt pin. + int-gpios: + type: phandle-array + required: true + description: Interrupt pin. - The interrupt pin of ENC28J60 is active low. - If connected directly the MCU pin should be configured - as active low. + The interrupt pin of ENC28J60 is active low. + If connected directly the MCU pin should be configured + as active low. diff --git a/dts/bindings/ethernet/microchip,enc424j600.yaml b/dts/bindings/ethernet/microchip,enc424j600.yaml index db1d5d7cdc5f68..767684f3a72012 100644 --- a/dts/bindings/ethernet/microchip,enc424j600.yaml +++ b/dts/bindings/ethernet/microchip,enc424j600.yaml @@ -9,11 +9,11 @@ compatible: "microchip,enc424j600" include: [spi-device.yaml, ethernet.yaml] properties: - int-gpios: - type: phandle-array - required: true - description: Interrupt pin. + int-gpios: + type: phandle-array + required: true + description: Interrupt pin. - The interrupt pin of ENC424J600 is active low. - If connected directly the MCU pin should be configured - as active low. + The interrupt pin of ENC424J600 is active low. + If connected directly the MCU pin should be configured + as active low. diff --git a/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml b/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml index fcaa479a68e766..df95dabf8fa2b0 100644 --- a/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml +++ b/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml @@ -8,18 +8,18 @@ compatible: "nxp,kinetis-ethernet" include: ["ethernet.yaml", "ethernet,fixed-link.yaml", "pinctrl-device.yaml"] properties: - reg: - required: true - interrupts: - required: true - phy-addr: - type: int - description: Address of the phy controller - required: true - reset-gpios: - type: phandle-array - description: GPIO to reset PHY. Reset signal is assumed active low. - int-gpios: - type: phandle-array - description: - interrupt GPIO for PHY. Will be pulled high before reset is asserted. + reg: + required: true + interrupts: + required: true + phy-addr: + type: int + description: Address of the phy controller + required: true + reset-gpios: + type: phandle-array + description: GPIO to reset PHY. Reset signal is assumed active low. + int-gpios: + type: phandle-array + description: + interrupt GPIO for PHY. Will be pulled high before reset is asserted. diff --git a/dts/bindings/ethernet/nxp,kinetis-ptp.yaml b/dts/bindings/ethernet/nxp,kinetis-ptp.yaml index d8f8faf288eacf..e60620642cdc3b 100644 --- a/dts/bindings/ethernet/nxp,kinetis-ptp.yaml +++ b/dts/bindings/ethernet/nxp,kinetis-ptp.yaml @@ -8,5 +8,5 @@ compatible: "nxp,kinetis-ptp" include: ["base.yaml", "pinctrl-device.yaml"] properties: - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/ethernet/silabs,gecko-ethernet.yaml b/dts/bindings/ethernet/silabs,gecko-ethernet.yaml index 40cb71d21a7dcc..1445669f41f536 100644 --- a/dts/bindings/ethernet/silabs,gecko-ethernet.yaml +++ b/dts/bindings/ethernet/silabs,gecko-ethernet.yaml @@ -9,93 +9,93 @@ compatible: "silabs,gecko-ethernet" include: ethernet.yaml properties: - reg: - required: true - description: mmio register space - - interrupts: - required: true - description: required interrupts - - # PHY address - phy-address: - type: int - required: true - description: address of the PHY on the MDIO bus - - # RMII interface location - location-rmii: - type: int - required: true - description: location of RMII pins, configuration defined as - - # PHY management interface location - location-mdio: - type: int - required: true - description: location of MDC and MDIO pins, configuration defined as - - # PHY management pins - location-phy_mdc: - type: array - required: true - description: PHY MDC individual pin configuration defined as - - location-phy_mdio: - type: array - required: true - description: PHY MDIO individual pin configuration defined as - - # RMII interface pins - location-rmii_refclk: - type: array - required: true - description: Reference clock individual pin configuration defined as - - location-rmii_crs_dv: - type: array - required: true - description: Receive data valid individual pin configuration defined as - - location-rmii_txd0: - type: array - required: true - description: Transmit data 0 individual pin configuration defined as - - location-rmii_txd1: - type: array - required: true - description: Transmit data 1 individual pin configuration defined as - - location-rmii_tx_en: - type: array - required: true - description: Transmit enable individual pin configuration defined as - - location-rmii_rxd0: - type: array - required: true - description: Receive data 0 individual pin configuration defined as - - location-rmii_rxd1: - type: array - required: true - description: Receive data 1 individual pin configuration defined as - - location-rmii_rx_er: - type: array - required: true - description: Receive error individual pin configuration defined as - - # PHY control pins - location-phy_pwr_enable: - type: array - description: PHY power enable individual pin configuration defined as - - location-phy_reset: - type: array - description: PHY reset individual pin configuration defined as - - location-phy_interrupt: - type: array - description: PHY interrupt individual pin configuration defined as + reg: + required: true + description: mmio register space + + interrupts: + required: true + description: required interrupts + + # PHY address + phy-address: + type: int + required: true + description: address of the PHY on the MDIO bus + + # RMII interface location + location-rmii: + type: int + required: true + description: location of RMII pins, configuration defined as + + # PHY management interface location + location-mdio: + type: int + required: true + description: location of MDC and MDIO pins, configuration defined as + + # PHY management pins + location-phy_mdc: + type: array + required: true + description: PHY MDC individual pin configuration defined as + + location-phy_mdio: + type: array + required: true + description: PHY MDIO individual pin configuration defined as + + # RMII interface pins + location-rmii_refclk: + type: array + required: true + description: Reference clock individual pin configuration defined as + + location-rmii_crs_dv: + type: array + required: true + description: Receive data valid individual pin configuration defined as + + location-rmii_txd0: + type: array + required: true + description: Transmit data 0 individual pin configuration defined as + + location-rmii_txd1: + type: array + required: true + description: Transmit data 1 individual pin configuration defined as + + location-rmii_tx_en: + type: array + required: true + description: Transmit enable individual pin configuration defined as + + location-rmii_rxd0: + type: array + required: true + description: Receive data 0 individual pin configuration defined as + + location-rmii_rxd1: + type: array + required: true + description: Receive data 1 individual pin configuration defined as + + location-rmii_rx_er: + type: array + required: true + description: Receive error individual pin configuration defined as + + # PHY control pins + location-phy_pwr_enable: + type: array + description: PHY power enable individual pin configuration defined as + + location-phy_reset: + type: array + description: PHY reset individual pin configuration defined as + + location-phy_interrupt: + type: array + description: PHY interrupt individual pin configuration defined as diff --git a/dts/bindings/ethernet/smsc,lan9220.yaml b/dts/bindings/ethernet/smsc,lan9220.yaml index c6fef07ed54fb4..5fea9c2ae0d9f3 100644 --- a/dts/bindings/ethernet/smsc,lan9220.yaml +++ b/dts/bindings/ethernet/smsc,lan9220.yaml @@ -8,8 +8,8 @@ compatible: "smsc,lan9220" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/ethernet/snps,designware-ethernet.yaml b/dts/bindings/ethernet/snps,designware-ethernet.yaml index 1113d4d5ba772d..b610a7c8a02b0f 100644 --- a/dts/bindings/ethernet/snps,designware-ethernet.yaml +++ b/dts/bindings/ethernet/snps,designware-ethernet.yaml @@ -8,7 +8,7 @@ compatible: "snps,designware-ethernet" include: ethernet.yaml properties: - reg: - required: true - interrupts: - required: true + reg: + required: true + interrupts: + required: true diff --git a/dts/bindings/ethernet/snps,ethernet-cyclonev.yaml b/dts/bindings/ethernet/snps,ethernet-cyclonev.yaml index f1ca4f785e79ea..2cebac1534b03b 100644 --- a/dts/bindings/ethernet/snps,ethernet-cyclonev.yaml +++ b/dts/bindings/ethernet/snps,ethernet-cyclonev.yaml @@ -8,7 +8,7 @@ compatible: "snps,ethernet-cyclonev" include: ethernet.yaml properties: - reg: - required: true - interrupts: - required: true + reg: + required: true + interrupts: + required: true diff --git a/dts/bindings/ethernet/st,stm32-ethernet.yaml b/dts/bindings/ethernet/st,stm32-ethernet.yaml index e7d5ae625fb059..4420006b9000cd 100644 --- a/dts/bindings/ethernet/st,stm32-ethernet.yaml +++ b/dts/bindings/ethernet/st,stm32-ethernet.yaml @@ -8,15 +8,15 @@ compatible: "st,stm32-ethernet" include: [ethernet.yaml, pinctrl-device.yaml] properties: - reg: - required: true - interrupts: - required: true - clocks: - required: true - clock-names: - required: true - pinctrl-0: - required: true - pinctrl-names: - required: true + reg: + required: true + interrupts: + required: true + clocks: + required: true + clock-names: + required: true + pinctrl-0: + required: true + pinctrl-names: + required: true diff --git a/dts/bindings/ethernet/ti,stellaris-ethernet.yaml b/dts/bindings/ethernet/ti,stellaris-ethernet.yaml index 5ed96eaf8ac9ef..f9310d773c64ab 100644 --- a/dts/bindings/ethernet/ti,stellaris-ethernet.yaml +++ b/dts/bindings/ethernet/ti,stellaris-ethernet.yaml @@ -8,7 +8,7 @@ compatible: "ti,stellaris-ethernet" include: ethernet.yaml properties: - reg: - required: true - interrupts: - required: true + reg: + required: true + interrupts: + required: true diff --git a/dts/bindings/ethernet/wiznet,w5500.yaml b/dts/bindings/ethernet/wiznet,w5500.yaml index fdf7b1428f6e7a..b37db750d1c443 100644 --- a/dts/bindings/ethernet/wiznet,w5500.yaml +++ b/dts/bindings/ethernet/wiznet,w5500.yaml @@ -8,18 +8,18 @@ compatible: "wiznet,w5500" include: [spi-device.yaml, ethernet.yaml] properties: - int-gpios: - type: phandle-array - required: true - description: Interrupt pin. + int-gpios: + type: phandle-array + required: true + description: Interrupt pin. - The interrupt pin of W5500 is active low. - If connected directly the MCU pin should be configured - as active low. - reset-gpios: - type: phandle-array - description: Reset pin. + The interrupt pin of W5500 is active low. + If connected directly the MCU pin should be configured + as active low. + reset-gpios: + type: phandle-array + description: Reset pin. - The reset pin of W5500 is active low. - If connected directly the MCU pin should be configured - as active low. + The reset pin of W5500 is active low. + If connected directly the MCU pin should be configured + as active low. diff --git a/dts/bindings/ethernet/xlnx,gem.yaml b/dts/bindings/ethernet/xlnx,gem.yaml index 4e27d9452dfe4e..0b1727f64de8fa 100644 --- a/dts/bindings/ethernet/xlnx,gem.yaml +++ b/dts/bindings/ethernet/xlnx,gem.yaml @@ -10,340 +10,340 @@ compatible: "xlnx,gem" include: ethernet.yaml properties: - reg: - required: true - - interrupts: - required: true - - clock-frequency: - type: int - required: true - description: | - Specifies the base clock frequency from which the GEM's TX clock - frequency will be derived using two dividers in the respective GEM's - clock control register in the CRL_APB. The GEM's TX clock frequency - is determined by the current link speed reported by the PHY, to - which it will be adjusted at run-time. Therefore, the value of this - item must be set to the clock frequency of the PLL supplying the - respective GEM's TX clock - by default, this is the IO PLL. - - mdc-divider: - type: int - required: true - description: | - The MDC clock divider for the respective GEM. This is the divider - applied to the LPD_LSBUS clock in order to derive MDIO interface - clock driving communications with the attached PHY. Refer to the - ZynqMP register documentation (ug1087), network_config (GEM) Register - Description, bits [20:18] to determine the appropriate divider for - the current target's LPD LSBUS clock frequency. - - init-mdio-phy: - type: boolean - description: | - Activates the management of a PHY associated with the controller in- - stance. If this parameter is activated at the board level, the de- - fault values of the associated parameters mdio-phy-address, phy-poll- - interval, link-speed and advertise-lower-link-speeds should be checked - and overwritten at the board level if required. - - mdio-phy-address: - type: int - required: true - description: | - The address on the MDIO bus of the PHY associated with the controller - instance. Set the address to 0 for auto-detection (first responding - PHY will be claimed by the driver, watch out in case of shared MDIO - use), or to a fixed address between 1 and 32. - - phy-poll-interval: - type: int - required: true - description: | - PHY status polling interval in milliseconds for a driver instance - managing an associated PHY. - - link-speed: - type: int - required: true - description: | - Nominal link speed. If no PHY is managed by an instance of this driver, - the respective controller will be configured to match the link speed - specified here. If a PHY is managed by the driver, advertisement of - the link speed specified here will be requested. If the optional pro- - perty advertise-lower-link-speeds is set, advertisement of the link - speed specified here plus any valid link speed below this value will - be requested. - enum: - - 1 - - 2 - - 3 - - advertise-lower-link-speeds: - type: boolean - description: | - Indicates to a driver instance which manages an associated PHY on - the MDIO bus to include link speeds lower than the nominal value - set in the link-speed property in the advertisement when requesting - link speed auto-negotiation with a peer system. - - handle-rx-in-isr: - type: boolean - description: | - Moves the handling of the frame received interrupt including the - transfer of packet data from the DMA to network packet buffers and - the subsequent propagation of the received packets to the network - stack into the context of the ISR. Due to the unpredictability of - the runtime of the ISR whenever large amounts of data are received, - handling of the RX interrupt is normally deferred to the context - of the system work queue. - - handle-tx-in-workq: - type: boolean - description: | - Moves the handling of the frame transmission done interrupt into the - context of the system work queue. By default, TX done handling is per- - formed in the context of the ISR, as it only involves a limited number - of memory accesses. This option CAN NOT be used if any component ex- - ists within the current system setup that triggers the transmission - of packets from within the context of the system work queue! - - amba-ahb-dbus-width: - type: int - required: true - description: AMBA AHB data bus width. - enum: - - 0 - - 1 - - 2 - - amba-ahb-burst-length: - type: int - required: true - description: AMBA AHB burst length for DMA operations. - enum: - - 1 - - 4 - - 8 - - 16 - - hw-rx-buffer-size: - type: int - required: true - description: | - Hardware RX buffer size, scalable between 1 kB and 8 kB, where the full - 8 kB should be the default. - enum: - - 0 - - 1 - - 2 - - 3 - - hw-rx-buffer-offset: - type: int - required: true - description: | - Data offset in the hardware RX packet buffer (in bytes). Valid range is - 0-3 bytes. - - hw-tx-buffer-size-full: - type: boolean - description: | - When set, the hardware TX data buffer will make use of the full 4 kB - that are available. If unset, the hardware TX data buffer will be - limited to 2 kB. - - rx-buffer-descriptors: - type: int - required: true - description: | - The number of descriptors to be allocated in the RX buffer descriptor - ring. Must be <= 255. - - rx-buffer-size: - type: int - required: true - description: | - The size of each receive data buffer, must be a multiple of 8, highest - valid value is 16320, values less than 64 are not really useful. - - tx-buffer-descriptors: - type: int - required: true - description: | - The number of descriptors to be allocated in the TX buffer descriptor - ring. Must be <= 255. - - tx-buffer-size: - type: int - required: true - description: | - The size of each transmit data buffer, highest valid value is 16380, - values less than 64 are not really useful. - - ignore-ipg-rxer: - type: boolean - description: | - Optional feature flag - Ignore IPG rx_er. When set, rx_er has no - effect on the GEM's operation when rx_dv is low. Set this when using - the RGMII wrapper in half-duplex mode. - - disable-reject-nsp: - type: boolean - description: | - Optional feature flag - Receive bad preamble. When set, frames with - non-standard preamble will not be rejected. - - ipg-stretch: - type: boolean - description: | - Optional feature flag - Enable IPG stretch. When set, the transmit - IPG can be increased above 96 bit times depending on the previous - frame length using the IPG stretch register. - - sgmii-mode: - type: boolean - description: | - Optional feature flag - Enable SGMII mode. Changes the behaviour of - the auto-negotiation advertisement and link partner ability registers - to meet the requirements of SGMII and reduces the duration of the link - timer from 10 ms to 1.6 ms. - - disable-reject-fcs-crc-errors: - type: boolean - description: | - Optional feature flag - Disable rejection of FCS/CRC errors. - When set, frames with FCS/CRC errors will not be rejected. FCS error - statistics will still be collected for frames with bad FCS and FCS - status will be recorded in the frame's DMA descriptor. This option - should not be activated for normal operation. - - rx-halfdup-while-tx: - type: boolean - description: | - Optional feature flag - Enable frames to be received in half-duplex - mode while transmitting. - - rx-checksum-offload: - type: boolean - description: | - Optional feature flag - Enable RX IP/TCP/UDP checksum offload to - hardware. Frames with bad IP, TCP or UDP checksums will be discarded. - This option is NOT supported by the QEMU implementation of the GEM! - - tx-checksum-offload: - type: boolean - description: | - Optional feature flag - Enable TX IP/TCP/UDP checksum offload to - hardware. This option is NOT supported by the QEMU implementation - of the GEM! - - disable-pause-copy: - type: boolean - description: | - Optional feature flag - Do not copy received pause frames to memory. - Set this option in order to prevent valid pause frames from being - copied to memory. When set, pause frames are not copied to memory - regardless of the state of the copy all frames bit, whether a hash - match is found or whether a type ID match is identified. If a desti- - nation address match is found the pause frame will be copied to - memory. Note that valid pause frames received will still increment - pause statistics and pause the transmission of frames as required. - - discard-rx-fcs: - type: boolean - description: | - Optional feature flag - Remove FCS of received frames. - When set, received frames will be written to memory without their - frame check sequence (last 4 bytes). The frame length indicated will - be reduced by four bytes in this mode. - - discard-rx-length-errors: - type: boolean - description: | - Optional feature flag - Discard frames with length field errors. - When set, frames with a measured length shorter than the extracted - length field (as indicated by bytes 13 and 14 in a non-VLAN tagged - frame) will be discarded. This only applies to frames with a length - field less than 0x0600. - - pause-frame: - type: boolean - description: | - Optional feature flag - Enable pause. When set, transmission will - pause if a non zero 802.3 classic pause frame is received and PFC - has not been negotiated. - - tbi: - type: boolean - description: | - Optional feature flag - Enable TBI. When set, the TBI interface is en- - bled instead of the GMII/MII interface. - - ext-address-match: - type: boolean - description: | - Optional feature flag - Enable external address match. When set, the - external address match interface can be used to copy frames to memory. - - long-frame-rx-support: - type: boolean - description: | - Optional feature flag - Enable reception of 1536 byte frames. - Normally, the GEM rejects any frame above 1518 bytes. - - unicast-hash: - type: boolean - description: | - Optional feature flag - Enable unicast hash. When set, unicast frames - will be accepted when the 6 bit hash function of the destination - address points to a bit that is set in the hash register. - - multicast-hash: - type: boolean - description: | - Optional feature flag - Enable multicast hash. When set, mutlicast - frames will be accepted when the 6 bit hash function of the desti- - nation address points to a bit that is set in the hash register. - - reject-broadcast: - type: boolean - description: | - Optional feature flag - Reject broadcast frames. When set, frames - addressed to the all-ones broadcast address will be rejected. - - promiscuous-mode: - type: boolean - description: | - Optional feature flag - Enable promiscuous mode. When set, all valid - frames will be accepted. - - discard-non-vlan: - type: boolean - description: Optional feature flag - Discard non-VLAN frames. When set, - only VLAN tagged frames will be passed to the address matching logic. - - full-duplex: - type: boolean - description: | - Optional feature flag - Enables full duplex reception and transmission. - - discard-rx-frame-ahb-unavail: - type: boolean - description: | - Optional feature flag - Discard received packets when no AHB resource - is available. - - ahb-packet-endian-swap: - type: boolean - description: | - Optional feature flag - Enable AHB packet data endianness swap to big - endian. If this flag is not set, data will be little endian. - - ahb-md-endian-swap: - type: boolean - description: | - Optional feature flag - Enable AHB management descriptor data endian- - ness swap to big endian. If this flag is not set, data will be little - endian. + reg: + required: true + + interrupts: + required: true + + clock-frequency: + type: int + required: true + description: | + Specifies the base clock frequency from which the GEM's TX clock + frequency will be derived using two dividers in the respective GEM's + clock control register in the CRL_APB. The GEM's TX clock frequency + is determined by the current link speed reported by the PHY, to + which it will be adjusted at run-time. Therefore, the value of this + item must be set to the clock frequency of the PLL supplying the + respective GEM's TX clock - by default, this is the IO PLL. + + mdc-divider: + type: int + required: true + description: | + The MDC clock divider for the respective GEM. This is the divider + applied to the LPD_LSBUS clock in order to derive MDIO interface + clock driving communications with the attached PHY. Refer to the + ZynqMP register documentation (ug1087), network_config (GEM) Register + Description, bits [20:18] to determine the appropriate divider for + the current target's LPD LSBUS clock frequency. + + init-mdio-phy: + type: boolean + description: | + Activates the management of a PHY associated with the controller in- + stance. If this parameter is activated at the board level, the de- + fault values of the associated parameters mdio-phy-address, phy-poll- + interval, link-speed and advertise-lower-link-speeds should be checked + and overwritten at the board level if required. + + mdio-phy-address: + type: int + required: true + description: | + The address on the MDIO bus of the PHY associated with the controller + instance. Set the address to 0 for auto-detection (first responding + PHY will be claimed by the driver, watch out in case of shared MDIO + use), or to a fixed address between 1 and 32. + + phy-poll-interval: + type: int + required: true + description: | + PHY status polling interval in milliseconds for a driver instance + managing an associated PHY. + + link-speed: + type: int + required: true + description: | + Nominal link speed. If no PHY is managed by an instance of this driver, + the respective controller will be configured to match the link speed + specified here. If a PHY is managed by the driver, advertisement of + the link speed specified here will be requested. If the optional pro- + perty advertise-lower-link-speeds is set, advertisement of the link + speed specified here plus any valid link speed below this value will + be requested. + enum: + - 1 + - 2 + - 3 + + advertise-lower-link-speeds: + type: boolean + description: | + Indicates to a driver instance which manages an associated PHY on + the MDIO bus to include link speeds lower than the nominal value + set in the link-speed property in the advertisement when requesting + link speed auto-negotiation with a peer system. + + handle-rx-in-isr: + type: boolean + description: | + Moves the handling of the frame received interrupt including the + transfer of packet data from the DMA to network packet buffers and + the subsequent propagation of the received packets to the network + stack into the context of the ISR. Due to the unpredictability of + the runtime of the ISR whenever large amounts of data are received, + handling of the RX interrupt is normally deferred to the context + of the system work queue. + + handle-tx-in-workq: + type: boolean + description: | + Moves the handling of the frame transmission done interrupt into the + context of the system work queue. By default, TX done handling is per- + formed in the context of the ISR, as it only involves a limited number + of memory accesses. This option CAN NOT be used if any component ex- + ists within the current system setup that triggers the transmission + of packets from within the context of the system work queue! + + amba-ahb-dbus-width: + type: int + required: true + description: AMBA AHB data bus width. + enum: + - 0 + - 1 + - 2 + + amba-ahb-burst-length: + type: int + required: true + description: AMBA AHB burst length for DMA operations. + enum: + - 1 + - 4 + - 8 + - 16 + + hw-rx-buffer-size: + type: int + required: true + description: | + Hardware RX buffer size, scalable between 1 kB and 8 kB, where the full + 8 kB should be the default. + enum: + - 0 + - 1 + - 2 + - 3 + + hw-rx-buffer-offset: + type: int + required: true + description: | + Data offset in the hardware RX packet buffer (in bytes). Valid range is + 0-3 bytes. + + hw-tx-buffer-size-full: + type: boolean + description: | + When set, the hardware TX data buffer will make use of the full 4 kB + that are available. If unset, the hardware TX data buffer will be + limited to 2 kB. + + rx-buffer-descriptors: + type: int + required: true + description: | + The number of descriptors to be allocated in the RX buffer descriptor + ring. Must be <= 255. + + rx-buffer-size: + type: int + required: true + description: | + The size of each receive data buffer, must be a multiple of 8, highest + valid value is 16320, values less than 64 are not really useful. + + tx-buffer-descriptors: + type: int + required: true + description: | + The number of descriptors to be allocated in the TX buffer descriptor + ring. Must be <= 255. + + tx-buffer-size: + type: int + required: true + description: | + The size of each transmit data buffer, highest valid value is 16380, + values less than 64 are not really useful. + + ignore-ipg-rxer: + type: boolean + description: | + Optional feature flag - Ignore IPG rx_er. When set, rx_er has no + effect on the GEM's operation when rx_dv is low. Set this when using + the RGMII wrapper in half-duplex mode. + + disable-reject-nsp: + type: boolean + description: | + Optional feature flag - Receive bad preamble. When set, frames with + non-standard preamble will not be rejected. + + ipg-stretch: + type: boolean + description: | + Optional feature flag - Enable IPG stretch. When set, the transmit + IPG can be increased above 96 bit times depending on the previous + frame length using the IPG stretch register. + + sgmii-mode: + type: boolean + description: | + Optional feature flag - Enable SGMII mode. Changes the behaviour of + the auto-negotiation advertisement and link partner ability registers + to meet the requirements of SGMII and reduces the duration of the link + timer from 10 ms to 1.6 ms. + + disable-reject-fcs-crc-errors: + type: boolean + description: | + Optional feature flag - Disable rejection of FCS/CRC errors. + When set, frames with FCS/CRC errors will not be rejected. FCS error + statistics will still be collected for frames with bad FCS and FCS + status will be recorded in the frame's DMA descriptor. This option + should not be activated for normal operation. + + rx-halfdup-while-tx: + type: boolean + description: | + Optional feature flag - Enable frames to be received in half-duplex + mode while transmitting. + + rx-checksum-offload: + type: boolean + description: | + Optional feature flag - Enable RX IP/TCP/UDP checksum offload to + hardware. Frames with bad IP, TCP or UDP checksums will be discarded. + This option is NOT supported by the QEMU implementation of the GEM! + + tx-checksum-offload: + type: boolean + description: | + Optional feature flag - Enable TX IP/TCP/UDP checksum offload to + hardware. This option is NOT supported by the QEMU implementation + of the GEM! + + disable-pause-copy: + type: boolean + description: | + Optional feature flag - Do not copy received pause frames to memory. + Set this option in order to prevent valid pause frames from being + copied to memory. When set, pause frames are not copied to memory + regardless of the state of the copy all frames bit, whether a hash + match is found or whether a type ID match is identified. If a desti- + nation address match is found the pause frame will be copied to + memory. Note that valid pause frames received will still increment + pause statistics and pause the transmission of frames as required. + + discard-rx-fcs: + type: boolean + description: | + Optional feature flag - Remove FCS of received frames. + When set, received frames will be written to memory without their + frame check sequence (last 4 bytes). The frame length indicated will + be reduced by four bytes in this mode. + + discard-rx-length-errors: + type: boolean + description: | + Optional feature flag - Discard frames with length field errors. + When set, frames with a measured length shorter than the extracted + length field (as indicated by bytes 13 and 14 in a non-VLAN tagged + frame) will be discarded. This only applies to frames with a length + field less than 0x0600. + + pause-frame: + type: boolean + description: | + Optional feature flag - Enable pause. When set, transmission will + pause if a non zero 802.3 classic pause frame is received and PFC + has not been negotiated. + + tbi: + type: boolean + description: | + Optional feature flag - Enable TBI. When set, the TBI interface is en- + bled instead of the GMII/MII interface. + + ext-address-match: + type: boolean + description: | + Optional feature flag - Enable external address match. When set, the + external address match interface can be used to copy frames to memory. + + long-frame-rx-support: + type: boolean + description: | + Optional feature flag - Enable reception of 1536 byte frames. + Normally, the GEM rejects any frame above 1518 bytes. + + unicast-hash: + type: boolean + description: | + Optional feature flag - Enable unicast hash. When set, unicast frames + will be accepted when the 6 bit hash function of the destination + address points to a bit that is set in the hash register. + + multicast-hash: + type: boolean + description: | + Optional feature flag - Enable multicast hash. When set, mutlicast + frames will be accepted when the 6 bit hash function of the desti- + nation address points to a bit that is set in the hash register. + + reject-broadcast: + type: boolean + description: | + Optional feature flag - Reject broadcast frames. When set, frames + addressed to the all-ones broadcast address will be rejected. + + promiscuous-mode: + type: boolean + description: | + Optional feature flag - Enable promiscuous mode. When set, all valid + frames will be accepted. + + discard-non-vlan: + type: boolean + description: Optional feature flag - Discard non-VLAN frames. When set, + only VLAN tagged frames will be passed to the address matching logic. + + full-duplex: + type: boolean + description: | + Optional feature flag - Enables full duplex reception and transmission. + + discard-rx-frame-ahb-unavail: + type: boolean + description: | + Optional feature flag - Discard received packets when no AHB resource + is available. + + ahb-packet-endian-swap: + type: boolean + description: | + Optional feature flag - Enable AHB packet data endianness swap to big + endian. If this flag is not set, data will be little endian. + + ahb-md-endian-swap: + type: boolean + description: | + Optional feature flag - Enable AHB management descriptor data endian- + ness swap to big endian. If this flag is not set, data will be little + endian. diff --git a/dts/bindings/flash_controller/altr,nios2-qspi-nor.yaml b/dts/bindings/flash_controller/altr,nios2-qspi-nor.yaml index 31a1b4bfa76d4a..c6e96dddbaa7c1 100644 --- a/dts/bindings/flash_controller/altr,nios2-qspi-nor.yaml +++ b/dts/bindings/flash_controller/altr,nios2-qspi-nor.yaml @@ -10,8 +10,8 @@ include: ["flash-controller.yaml", "jedec,jesd216.yaml"] on-bus: qspi properties: - reg: - required: true - size: - required: true - description: Flash Memory size in bits + reg: + required: true + size: + required: true + description: Flash Memory size in bits diff --git a/dts/bindings/flash_controller/atmel,sam-flash-controller.yaml b/dts/bindings/flash_controller/atmel,sam-flash-controller.yaml index 8c987423981254..1a768f6136eff2 100644 --- a/dts/bindings/flash_controller/atmel,sam-flash-controller.yaml +++ b/dts/bindings/flash_controller/atmel,sam-flash-controller.yaml @@ -8,7 +8,7 @@ compatible: "atmel,sam-flash-controller" include: flash-controller.yaml properties: - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/flash_controller/atmel,sam0-nvmctrl.yaml b/dts/bindings/flash_controller/atmel,sam0-nvmctrl.yaml index 9e24ddadd577f4..b485f1c06abdd5 100644 --- a/dts/bindings/flash_controller/atmel,sam0-nvmctrl.yaml +++ b/dts/bindings/flash_controller/atmel,sam0-nvmctrl.yaml @@ -5,7 +5,7 @@ compatible: "atmel,sam0-nvmctrl" include: flash-controller.yaml properties: - lock-regions: - type: int - required: true - description: Number of lock regions + lock-regions: + type: int + required: true + description: Number of lock regions diff --git a/dts/bindings/flash_controller/cdns,qspi-nor.yaml b/dts/bindings/flash_controller/cdns,qspi-nor.yaml index 1e65bba5d0f45d..4067f1a649dec3 100644 --- a/dts/bindings/flash_controller/cdns,qspi-nor.yaml +++ b/dts/bindings/flash_controller/cdns,qspi-nor.yaml @@ -8,7 +8,7 @@ compatible: "cdns,qspi-nor" include: flash-controller.yaml properties: - clock-frequency: - type: int - required: true - description: clock frequency information for Cadence QSPI NOR Flash + clock-frequency: + type: int + required: true + description: clock frequency information for Cadence QSPI NOR Flash diff --git a/dts/bindings/flash_controller/flash-controller.yaml b/dts/bindings/flash_controller/flash-controller.yaml index b2dc0e181ad951..638391c2526592 100644 --- a/dts/bindings/flash_controller/flash-controller.yaml +++ b/dts/bindings/flash_controller/flash-controller.yaml @@ -3,5 +3,5 @@ include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/flash_controller/micron,mt25qu02g.yaml b/dts/bindings/flash_controller/micron,mt25qu02g.yaml index 169a43c9c258b8..f542a48e6a7ebf 100644 --- a/dts/bindings/flash_controller/micron,mt25qu02g.yaml +++ b/dts/bindings/flash_controller/micron,mt25qu02g.yaml @@ -8,6 +8,6 @@ compatible: "micron,mt25qu02g" include: flash-controller.yaml properties: - size: - type: int - description: Flash memory size in bit. + size: + type: int + description: Flash memory size in bit. diff --git a/dts/bindings/flash_controller/nordic,nrf52-flash-controller.yaml b/dts/bindings/flash_controller/nordic,nrf52-flash-controller.yaml index 0aed1efb9119d2..40ae8d4c84f1e3 100644 --- a/dts/bindings/flash_controller/nordic,nrf52-flash-controller.yaml +++ b/dts/bindings/flash_controller/nordic,nrf52-flash-controller.yaml @@ -5,7 +5,7 @@ compatible: "nordic,nrf52-flash-controller" include: flash-controller.yaml properties: - partial-erase: - type: boolean - description: | - If set, indicates that the NVMC supports partial erase of flash pages. + partial-erase: + type: boolean + description: | + If set, indicates that the NVMC supports partial erase of flash pages. diff --git a/dts/bindings/flash_controller/nordic,nrf53-flash-controller.yaml b/dts/bindings/flash_controller/nordic,nrf53-flash-controller.yaml index dd8b9275ecfbca..68da2da47dd4b3 100644 --- a/dts/bindings/flash_controller/nordic,nrf53-flash-controller.yaml +++ b/dts/bindings/flash_controller/nordic,nrf53-flash-controller.yaml @@ -5,7 +5,7 @@ compatible: "nordic,nrf53-flash-controller" include: flash-controller.yaml properties: - partial-erase: - type: boolean - description: | - If set, indicates that the NVMC supports partial erase of flash pages. + partial-erase: + type: boolean + description: | + If set, indicates that the NVMC supports partial erase of flash pages. diff --git a/dts/bindings/flash_controller/nordic,nrf91-flash-controller.yaml b/dts/bindings/flash_controller/nordic,nrf91-flash-controller.yaml index 685ce648936502..e0f03a50d528a3 100644 --- a/dts/bindings/flash_controller/nordic,nrf91-flash-controller.yaml +++ b/dts/bindings/flash_controller/nordic,nrf91-flash-controller.yaml @@ -5,7 +5,7 @@ compatible: "nordic,nrf91-flash-controller" include: flash-controller.yaml properties: - partial-erase: - type: boolean - description: | - If set, indicates that the NVMC supports partial erase of flash pages. + partial-erase: + type: boolean + description: | + If set, indicates that the NVMC supports partial erase of flash pages. diff --git a/dts/bindings/flash_controller/st,stm32-ospi-nor.yaml b/dts/bindings/flash_controller/st,stm32-ospi-nor.yaml index d95433886a2c86..f8f84020f6a157 100644 --- a/dts/bindings/flash_controller/st,stm32-ospi-nor.yaml +++ b/dts/bindings/flash_controller/st,stm32-ospi-nor.yaml @@ -23,85 +23,85 @@ include: ["flash-controller.yaml", "jedec,jesd216.yaml"] on-bus: ospi properties: - reg: - required: true - ospi-max-frequency: - type: int - required: true - description: Maximum clock frequency of device's OSPI interface in Hz - size: - required: true - description: Flash Memory size in bits - reset-gpios: - type: phandle-array - description: RESETn pin - spi-bus-width: - type: int - required: true - description: | - The width of (Octo)SPI bus to which flash memory is connected. - - Possible values are : - - OSPI_SPI_MODE <1> = SPI mode on 1 data line - - OSPI_DUAL_MODE <2> = Dual mode on 2 data lines - - OSPI_QUAD_MODE <4> = Quad mode on 4 data lines - - OSPI_OPI_MODE <8> = Octo mode on 8 data lines - enum: - - 1 - - 2 - - 4 - - 8 - data-rate: - type: int - required: true - description: | - The SPI data Rate is STR or DTR - - Possible values are : - - OSPI_STR_TRANSFER <1> = Single Rate Transfer - - OSPI_DTR_TRANSFER <2> = Dual Rate Transfer (only with OSPI_OPI_MODE) - enum: - - 1 - - 2 - writeoc: - type: string - enum: - - "PP" # Page program, PP (0x02) up to 256 bytes - - "PP_1_1_2" # Dual page program, PP 1-1-2 (0xA2) - - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32) - - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38) - description: | - The value encodes number of I/O lines used for the opcode, - address, and data. - - There is no info about quad page program opcodes in the SFDP - tables, hence it has been assumed that NOR flash memory - supporting 1-4-4 mode also would support fast page programming. - - Intended for modes other than OSPI_OPI_MODE. - - If absent, then program page opcode is determined by the - `spi-bus-width`: - - * OSPI_SPI_MODE -> PP 1-1-1 (0x02) - * OSPI_DUAL_MODE -> PP 1-1-2 (0xA2) - * OSPI_QUAD_MODE -> PP 1-4-4 (0x38) - four-byte-opcodes: - type: boolean - description: | - Some NOR-Flash ICs use different opcodes when operating in - 4 byte addressing mode. - - When enabled, then 3 byte opcodes will be converted to - 4 byte opcodes. - - * PP 1-1-1 (0x02) -> PP 1-1-1 4B (0x12) - * PP 1-1-4 (0x32) -> PP 1-1-4 4B (0x34) - * PP 1-4-4 (0x38) -> PP 1-4-4 4B (0x3E) - - * READ 1-1-1 (0x03) -> READ 1-1-1 4B (0x13) - * READ FAST 1-1-1 (0x0B) -> READ FAST 1-1-1 4B (0x0C) - * DREAD 1-1-2 (0x3B) -> DREAD 1-1-2 4B (0x3C) - * 2READ 1-2-2 (0xBB) -> 2READ 1-2-2 4B (0xBC) - * QREAD 1-1-4 (0x6B) -> QREAD 1-1-4 4B (0x6C) - * 4READ 1-4-4 (0xEB) -> 4READ 1-4-4 4B (0xEC) + reg: + required: true + ospi-max-frequency: + type: int + required: true + description: Maximum clock frequency of device's OSPI interface in Hz + size: + required: true + description: Flash Memory size in bits + reset-gpios: + type: phandle-array + description: RESETn pin + spi-bus-width: + type: int + required: true + description: | + The width of (Octo)SPI bus to which flash memory is connected. + + Possible values are : + - OSPI_SPI_MODE <1> = SPI mode on 1 data line + - OSPI_DUAL_MODE <2> = Dual mode on 2 data lines + - OSPI_QUAD_MODE <4> = Quad mode on 4 data lines + - OSPI_OPI_MODE <8> = Octo mode on 8 data lines + enum: + - 1 + - 2 + - 4 + - 8 + data-rate: + type: int + required: true + description: | + The SPI data Rate is STR or DTR + + Possible values are : + - OSPI_STR_TRANSFER <1> = Single Rate Transfer + - OSPI_DTR_TRANSFER <2> = Dual Rate Transfer (only with OSPI_OPI_MODE) + enum: + - 1 + - 2 + writeoc: + type: string + enum: + - "PP" # Page program, PP (0x02) up to 256 bytes + - "PP_1_1_2" # Dual page program, PP 1-1-2 (0xA2) + - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32) + - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38) + description: | + The value encodes number of I/O lines used for the opcode, + address, and data. + + There is no info about quad page program opcodes in the SFDP + tables, hence it has been assumed that NOR flash memory + supporting 1-4-4 mode also would support fast page programming. + + Intended for modes other than OSPI_OPI_MODE. + + If absent, then program page opcode is determined by the + `spi-bus-width`: + + * OSPI_SPI_MODE -> PP 1-1-1 (0x02) + * OSPI_DUAL_MODE -> PP 1-1-2 (0xA2) + * OSPI_QUAD_MODE -> PP 1-4-4 (0x38) + four-byte-opcodes: + type: boolean + description: | + Some NOR-Flash ICs use different opcodes when operating in + 4 byte addressing mode. + + When enabled, then 3 byte opcodes will be converted to + 4 byte opcodes. + + * PP 1-1-1 (0x02) -> PP 1-1-1 4B (0x12) + * PP 1-1-4 (0x32) -> PP 1-1-4 4B (0x34) + * PP 1-4-4 (0x38) -> PP 1-4-4 4B (0x3E) + + * READ 1-1-1 (0x03) -> READ 1-1-1 4B (0x13) + * READ FAST 1-1-1 (0x0B) -> READ FAST 1-1-1 4B (0x0C) + * DREAD 1-1-2 (0x3B) -> DREAD 1-1-2 4B (0x3C) + * 2READ 1-2-2 (0xBB) -> 2READ 1-2-2 4B (0xBC) + * QREAD 1-1-4 (0x6B) -> QREAD 1-1-4 4B (0x6C) + * 4READ 1-4-4 (0xEB) -> 4READ 1-4-4 4B (0xEC) diff --git a/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml b/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml index 9a424298b22aa0..6d7bf5105e6305 100644 --- a/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml +++ b/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml @@ -24,43 +24,43 @@ include: ["flash-controller.yaml", "jedec,jesd216.yaml"] on-bus: qspi properties: - reg: - required: true - qspi-max-frequency: - type: int - required: true - description: Maximum clock frequency of device's QSPI interface in Hz - size: - required: true - description: Flash Memory size in bits - reset-gpios: - type: phandle-array - description: RESETn pin - reset-gpios-duration: - type: int - description: The duration (in ms) for the flash memory reset pulse - reset-cmd: - type: boolean - description: Send reset command on initialization - reset-cmd-wait: - type: int - default: 10 - description: The duration (in us) to wait after reset command - spi-bus-width: - type: int - description: The width of (Q)SPI bus to which flash memory is connected. - Now only value of 4 (when using SIO[0123]) is supported. - writeoc: - type: string - enum: - - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32) - - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38) - description: | - The value encodes number of I/O lines used for the opcode, - address, and data. + reg: + required: true + qspi-max-frequency: + type: int + required: true + description: Maximum clock frequency of device's QSPI interface in Hz + size: + required: true + description: Flash Memory size in bits + reset-gpios: + type: phandle-array + description: RESETn pin + reset-gpios-duration: + type: int + description: The duration (in ms) for the flash memory reset pulse + reset-cmd: + type: boolean + description: Send reset command on initialization + reset-cmd-wait: + type: int + default: 10 + description: The duration (in us) to wait after reset command + spi-bus-width: + type: int + description: The width of (Q)SPI bus to which flash memory is connected. + Now only value of 4 (when using SIO[0123]) is supported. + writeoc: + type: string + enum: + - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32) + - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38) + description: | + The value encodes number of I/O lines used for the opcode, + address, and data. - There is no info about quad page program opcodes in the SFDP - tables, hence it has been assumed that NOR flash memory - supporting 1-4-4 mode also would support fast page programming. + There is no info about quad page program opcodes in the SFDP + tables, hence it has been assumed that NOR flash memory + supporting 1-4-4 mode also would support fast page programming. - If absent, then 1-4-4 program page is used in quad mode. + If absent, then 1-4-4 program page is used in quad mode. diff --git a/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml index e558ac40c15972..3234a34d86141b 100644 --- a/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml @@ -5,10 +5,10 @@ compatible: "st,stm32wb-flash-controller" include: flash-controller.yaml properties: - single-bank: - type: boolean - description: dual-bank mode not enabled (page erase 4096k) + single-bank: + type: boolean + description: dual-bank mode not enabled (page erase 4096k) - dual-bank: - type: boolean - description: dual-bank mode enabled (page erase 2048k) + dual-bank: + type: boolean + description: dual-bank mode enabled (page erase 2048k) diff --git a/dts/bindings/flash_controller/zephyr,sim-flash.yaml b/dts/bindings/flash_controller/zephyr,sim-flash.yaml index 0dacbf79a79ecf..bee3a21728f5ff 100644 --- a/dts/bindings/flash_controller/zephyr,sim-flash.yaml +++ b/dts/bindings/flash_controller/zephyr,sim-flash.yaml @@ -7,6 +7,6 @@ compatible: "zephyr,sim-flash" include: base.yaml properties: - erase-value: - type: int - description: Value of erased flash cell + erase-value: + type: int + description: Value of erased flash cell diff --git a/dts/bindings/fpga/lattice,ice40-fpga.yaml b/dts/bindings/fpga/lattice,ice40-fpga.yaml index 5f3606fe38b43a..f306b6c3dc1292 100644 --- a/dts/bindings/fpga/lattice,ice40-fpga.yaml +++ b/dts/bindings/fpga/lattice,ice40-fpga.yaml @@ -8,92 +8,92 @@ compatible: "lattice,ice40-fpga" include: spi-device.yaml properties: - load-mode: - type: int - required: true - description: | - Configure the method used to load the bitstream. - The bitstream may be loaded via 2 separate methods: - 0 := load the FPGA via SPI transfer - 1 := load the FPGA via bit-banged GPIO - Option 0 may be suitable for some high-end microcontrollers. - Option 1 is suitable for low-end microcontrollers. This option - requires clk-gpios, pico-gpios, gpios-set-reg, and gpios-clear-reg - to be defined. - Example usage: - load-mode = <0>; - cdone-gpios: - type: phandle-array - required: true - description: | - Configuration Done output from iCE40. - Example usage: - cdone-gpios = <&gpio0 0 0>; - creset-gpios: - type: phandle-array - required: true - description: | - Configuration Reset input on iCE40. - Example usage: - creset-gpios = <&gpio0 1 GPIO_PUSH_PULL); - clk-gpios: - type: phandle-array - description: | - SPI Clock GPIO input on iCE40. - Example usage: - clk-gpios = <&gpio0 5 GPIO_PUSH_PULL>; - pico-gpios: - type: phandle-array - description: | - Peripheral-In Controller-Out GPIO input on iCE40. - Example usage: - pico-gpios = <&gpio0 7 GPIO_PUSH_PULL>; - gpios-set-reg: - type: int - description: | - Register address for setting a GPIO. - Example usage: - gpios-set-reg = <0x60004008>; - gpios-clear-reg: - type: int - description: | - Register address for clearing a GPIO. - Example usage: - gpios-clear-reg = <0x6000400c>; - mhz-delay-count: - type: int - description: | - in order to create a 1 MHz square wave in the following - process. - while(true) { - *gpios_set_reg |= BIT(n); - for(int i = mhz_delay_count; i > 0; --i); - *gpios_clear_reg |= BIT(n); - for(int i = mhz_delay_count; i > 0; --i); - } - Example usage / default: - mhz-delay-count = <0>; - creset-delay-ns: - type: int - description: | - Delay (in nanoseconds) between asserting CRESET_B and releasing CRESET_B. - Example usage / default: - creset-delay-ns = <200>; - config-delay-us: - type: int - description: | - Delay (in microseconds) after releasing CRESET_B to clear internal configuration memory. - Example usage / default: - config-delay-us = <300>; - leading-clocks: - type: int - description: | - Prior to sending the bitstream, issue this number of leading clocks with SPI_CS pulled high. - Example usage / default: - leading-clocks = <8>; - trailing-clocks: - type: int - description: | - After sending the bitstream, issue this number of trailing clocks with SPI_CS pulled high. - Example usage / default: - trailing-clocks = <49>; + load-mode: + type: int + required: true + description: | + Configure the method used to load the bitstream. + The bitstream may be loaded via 2 separate methods: + 0 := load the FPGA via SPI transfer + 1 := load the FPGA via bit-banged GPIO + Option 0 may be suitable for some high-end microcontrollers. + Option 1 is suitable for low-end microcontrollers. This option + requires clk-gpios, pico-gpios, gpios-set-reg, and gpios-clear-reg + to be defined. + Example usage: + load-mode = <0>; + cdone-gpios: + type: phandle-array + required: true + description: | + Configuration Done output from iCE40. + Example usage: + cdone-gpios = <&gpio0 0 0>; + creset-gpios: + type: phandle-array + required: true + description: | + Configuration Reset input on iCE40. + Example usage: + creset-gpios = <&gpio0 1 GPIO_PUSH_PULL); + clk-gpios: + type: phandle-array + description: | + SPI Clock GPIO input on iCE40. + Example usage: + clk-gpios = <&gpio0 5 GPIO_PUSH_PULL>; + pico-gpios: + type: phandle-array + description: | + Peripheral-In Controller-Out GPIO input on iCE40. + Example usage: + pico-gpios = <&gpio0 7 GPIO_PUSH_PULL>; + gpios-set-reg: + type: int + description: | + Register address for setting a GPIO. + Example usage: + gpios-set-reg = <0x60004008>; + gpios-clear-reg: + type: int + description: | + Register address for clearing a GPIO. + Example usage: + gpios-clear-reg = <0x6000400c>; + mhz-delay-count: + type: int + description: | + in order to create a 1 MHz square wave in the following + process. + while(true) { + *gpios_set_reg |= BIT(n); + for(int i = mhz_delay_count; i > 0; --i); + *gpios_clear_reg |= BIT(n); + for(int i = mhz_delay_count; i > 0; --i); + } + Example usage / default: + mhz-delay-count = <0>; + creset-delay-ns: + type: int + description: | + Delay (in nanoseconds) between asserting CRESET_B and releasing CRESET_B. + Example usage / default: + creset-delay-ns = <200>; + config-delay-us: + type: int + description: | + Delay (in microseconds) after releasing CRESET_B to clear internal configuration memory. + Example usage / default: + config-delay-us = <300>; + leading-clocks: + type: int + description: | + Prior to sending the bitstream, issue this number of leading clocks with SPI_CS pulled high. + Example usage / default: + leading-clocks = <8>; + trailing-clocks: + type: int + description: | + After sending the bitstream, issue this number of trailing clocks with SPI_CS pulled high. + Example usage / default: + trailing-clocks = <49>; diff --git a/dts/bindings/gpio/andestech,atcgpio100.yaml b/dts/bindings/gpio/andestech,atcgpio100.yaml index 53a549a63e90d1..88a7d990a390ae 100644 --- a/dts/bindings/gpio/andestech,atcgpio100.yaml +++ b/dts/bindings/gpio/andestech,atcgpio100.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: - This is a representation of Andes Technology atcgpio100 GPIO node + This is a representation of Andes Technology atcgpio100 GPIO node compatible: "andestech,atcgpio100" @@ -10,14 +10,14 @@ include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/arm,cmsdk-gpio.yaml b/dts/bindings/gpio/arm,cmsdk-gpio.yaml index faaad21461996b..3806c6151ff88e 100644 --- a/dts/bindings/gpio/arm,cmsdk-gpio.yaml +++ b/dts/bindings/gpio/arm,cmsdk-gpio.yaml @@ -5,14 +5,14 @@ compatible: "arm,cmsdk-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml b/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml index f4e9f50583a9c4..1c91ef9ca2a5aa 100644 --- a/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml +++ b/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml @@ -5,14 +5,14 @@ compatible: "arm,mps2-fpgaio-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - ngpios: - required: true + ngpios: + required: true - "#gpio-cells": - const: 1 + "#gpio-cells": + const: 1 gpio-cells: - pin diff --git a/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml b/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml index 4d6db2f203a367..8d93742f9edc78 100644 --- a/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml +++ b/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml @@ -5,14 +5,14 @@ compatible: "arm,mps3-fpgaio-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - ngpios: - required: true + ngpios: + required: true - "#gpio-cells": - const: 1 + "#gpio-cells": + const: 1 gpio-cells: - pin diff --git a/dts/bindings/gpio/atmel,sam-gpio.yaml b/dts/bindings/gpio/atmel,sam-gpio.yaml index ba90cd651e62b2..3be0b79449488b 100644 --- a/dts/bindings/gpio/atmel,sam-gpio.yaml +++ b/dts/bindings/gpio/atmel,sam-gpio.yaml @@ -5,25 +5,25 @@ compatible: "atmel,sam-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - "#atmel,pin-cells": - type: int - required: true - const: 2 - description: Number of items to expect in a atmel,pins specifier + "#atmel,pin-cells": + type: int + required: true + const: 2 + description: Number of items to expect in a atmel,pins specifier gpio-cells: diff --git a/dts/bindings/gpio/atmel,sam0-gpio.yaml b/dts/bindings/gpio/atmel,sam0-gpio.yaml index 14a4458476a53b..f4f50a5e385ce1 100644 --- a/dts/bindings/gpio/atmel,sam0-gpio.yaml +++ b/dts/bindings/gpio/atmel,sam0-gpio.yaml @@ -5,17 +5,17 @@ compatible: "atmel,sam0-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - "#atmel,pin-cells": - type: int - required: true - const: 2 - description: Number of items to expect in a atmel,pins specifier + "#atmel,pin-cells": + type: int + required: true + const: 2 + description: Number of items to expect in a atmel,pins specifier gpio-cells: - pin diff --git a/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml b/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml index 81d9f0aebf22d2..544621f74e4660 100644 --- a/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml +++ b/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml @@ -8,15 +8,15 @@ compatible: "cypress,cy8c95xx-gpio-port" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - ngpios: - required: true - const: 8 + ngpios: + required: true + const: 8 gpio-cells: - pin diff --git a/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml b/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml index 35efa4ff7fbac1..1f97f9a141f339 100644 --- a/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml +++ b/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml @@ -8,5 +8,5 @@ compatible: "cypress,cy8c95xx-gpio" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/gpio/cypress,psoc6-gpio.yaml b/dts/bindings/gpio/cypress,psoc6-gpio.yaml index 2daf4fa8d94728..ac16d9341a3adf 100644 --- a/dts/bindings/gpio/cypress,psoc6-gpio.yaml +++ b/dts/bindings/gpio/cypress,psoc6-gpio.yaml @@ -8,20 +8,20 @@ compatible: "cypress,psoc6-gpio" include: ["gpio-controller.yaml", "base.yaml"] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - "#cypress,pin-cells": - type: int - required: true - const: 2 - description: Number of items to expect in a cypress,pins specifier + "#cypress,pin-cells": + type: int + required: true + const: 2 + description: Number of items to expect in a cypress,pins specifier gpio-cells: - pin diff --git a/dts/bindings/gpio/cypress,psoc6-hsiom.yaml b/dts/bindings/gpio/cypress,psoc6-hsiom.yaml index ae76503c0298c6..88619cb08ccd29 100644 --- a/dts/bindings/gpio/cypress,psoc6-hsiom.yaml +++ b/dts/bindings/gpio/cypress,psoc6-hsiom.yaml @@ -8,8 +8,8 @@ compatible: "cypress,psoc6-hsiom" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/gpio/espressif,esp32-gpio.yaml b/dts/bindings/gpio/espressif,esp32-gpio.yaml index 9d88804a5ece1b..0711bc8f4cd10d 100644 --- a/dts/bindings/gpio/espressif,esp32-gpio.yaml +++ b/dts/bindings/gpio/espressif,esp32-gpio.yaml @@ -8,11 +8,11 @@ compatible: "espressif,esp32-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/fcs,fxl6408.yaml b/dts/bindings/gpio/fcs,fxl6408.yaml index 607a6e8e338f1e..893fe82e2d5c4b 100644 --- a/dts/bindings/gpio/fcs,fxl6408.yaml +++ b/dts/bindings/gpio/fcs,fxl6408.yaml @@ -8,8 +8,8 @@ compatible: "fcs,fxl6408" include: [gpio-controller.yaml, i2c-device.yaml] properties: - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/gd,gd32-gpio.yaml b/dts/bindings/gpio/gd,gd32-gpio.yaml index be46d810df7d82..c2b8c91820452e 100644 --- a/dts/bindings/gpio/gd,gd32-gpio.yaml +++ b/dts/bindings/gpio/gd,gd32-gpio.yaml @@ -8,17 +8,17 @@ compatible: "gd,gd32-gpio" include: [gpio-controller.yaml, reset-device.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - resets: - required: true + resets: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/gpio-controller.yaml b/dts/bindings/gpio/gpio-controller.yaml index e5e0512ab596b3..034aec3534aeea 100644 --- a/dts/bindings/gpio/gpio-controller.yaml +++ b/dts/bindings/gpio/gpio-controller.yaml @@ -4,39 +4,39 @@ # Common fields for GPIO controllers properties: - "gpio-controller": - type: boolean - required: true - description: Convey's this node is a GPIO controller - "#gpio-cells": - type: int - required: true - description: Number of items to expect in a GPIO specifier - ngpios: - type: int - default: 32 - description: | - This property indicates the number of in-use slots of available slots - for GPIOs. The typical example is something like this: the hardware - register is 32 bits wide, but only 18 of the bits have a physical - counterpart. The driver is generally written so that all 32 bits can - be used, but the IP block is reused in a lot of designs, some using - all 32 bits, some using 18 and some using 12. In this case, setting - "ngpios = <18>;" informs the driver that only the first 18 GPIOs, at - local offset 0 .. 17, are in use. For cases in which there might be - holes in the slot range, this value should be the max slot number-1. - gpio-reserved-ranges: - type: array - description: | - If not all the GPIOs at offsets 0...N-1 are usable for ngpios = , then - this property contains an additional set of tuples which specify which GPIOs - are unusable. This property indicates the start and size of the GPIOs - that can't be used. + "gpio-controller": + type: boolean + required: true + description: Convey's this node is a GPIO controller + "#gpio-cells": + type: int + required: true + description: Number of items to expect in a GPIO specifier + ngpios: + type: int + default: 32 + description: | + This property indicates the number of in-use slots of available slots + for GPIOs. The typical example is something like this: the hardware + register is 32 bits wide, but only 18 of the bits have a physical + counterpart. The driver is generally written so that all 32 bits can + be used, but the IP block is reused in a lot of designs, some using + all 32 bits, some using 18 and some using 12. In this case, setting + "ngpios = <18>;" informs the driver that only the first 18 GPIOs, at + local offset 0 .. 17, are in use. For cases in which there might be + holes in the slot range, this value should be the max slot number-1. + gpio-reserved-ranges: + type: array + description: | + If not all the GPIOs at offsets 0...N-1 are usable for ngpios = , then + this property contains an additional set of tuples which specify which GPIOs + are unusable. This property indicates the start and size of the GPIOs + that can't be used. - For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that - GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>. - gpio-line-names: - type: string-array - description: | - This is an array of strings defining the names of the GPIO lines - going out of the GPIO controller + For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that + GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>. + gpio-line-names: + type: string-array + description: | + This is an array of strings defining the names of the GPIO lines + going out of the GPIO controller diff --git a/dts/bindings/gpio/gpio-nexus.yaml b/dts/bindings/gpio/gpio-nexus.yaml index df735877fbb7a1..a1bcbc61e5ae00 100644 --- a/dts/bindings/gpio/gpio-nexus.yaml +++ b/dts/bindings/gpio/gpio-nexus.yaml @@ -4,17 +4,17 @@ # Common fields for GPIO nexus nodes properties: - gpio-map: - type: compound - required: true + gpio-map: + type: compound + required: true - gpio-map-mask: - type: compound + gpio-map-mask: + type: compound - gpio-map-pass-thru: - type: compound + gpio-map-pass-thru: + type: compound - "#gpio-cells": - type: int - required: true - description: Number of items to expect in a GPIO specifier + "#gpio-cells": + type: int + required: true + description: Number of items to expect in a GPIO specifier diff --git a/dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml b/dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml index 17317492e1eb48..a6b28c3af8940a 100644 --- a/dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml +++ b/dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml @@ -5,11 +5,11 @@ compatible: "infineon,xmc4xxx-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/intel,gpio.yaml b/dts/bindings/gpio/intel,gpio.yaml index 9df61963a332c8..f702e57204b71c 100644 --- a/dts/bindings/gpio/intel,gpio.yaml +++ b/dts/bindings/gpio/intel,gpio.yaml @@ -8,27 +8,27 @@ compatible: "intel,gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - group-index: - type: int - description: Group number for this GPIO entry + group-index: + type: int + description: Group number for this GPIO entry - interrupts: - required: true + interrupts: + required: true - ngpios: - required: true - description: Number of pins for this GPIO entry + ngpios: + required: true + description: Number of pins for this GPIO entry - pin-offset: - type: int - required: true - description: Pin offset of this GPIO entry + pin-offset: + type: int + required: true + description: Pin offset of this GPIO entry - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/ite,it8xxx2-gpio.yaml b/dts/bindings/gpio/ite,it8xxx2-gpio.yaml index 868d1c888e5397..366c72f12f5180 100644 --- a/dts/bindings/gpio/ite,it8xxx2-gpio.yaml +++ b/dts/bindings/gpio/ite,it8xxx2-gpio.yaml @@ -8,8 +8,8 @@ compatible: "ite,it8xxx2-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true gpio-cells: - pin diff --git a/dts/bindings/gpio/litex,gpio.yaml b/dts/bindings/gpio/litex,gpio.yaml index 2f927dbea84a03..ad5a85e420b00e 100644 --- a/dts/bindings/gpio/litex,gpio.yaml +++ b/dts/bindings/gpio/litex,gpio.yaml @@ -11,18 +11,18 @@ compatible: "litex,gpio" include: [gpio-controller.yaml, base.yaml] properties: - port-is-output: - type: boolean - description: Indicates if the port is an output port + port-is-output: + type: boolean + description: Indicates if the port is an output port - reg: - required: true + reg: + required: true - ngpios: - required: true + ngpios: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/microchip,mcp230xx.yaml b/dts/bindings/gpio/microchip,mcp230xx.yaml index 03ab6dca802e69..7fcb455d0c05e0 100644 --- a/dts/bindings/gpio/microchip,mcp230xx.yaml +++ b/dts/bindings/gpio/microchip,mcp230xx.yaml @@ -12,14 +12,14 @@ compatible: "microchip,mcp230xx" include: [gpio-controller.yaml, i2c-device.yaml] properties: - ngpios: - type: int - enum: - - 8 - - 16 - required: true - description: | - Number of gpios supported by the chip. + ngpios: + type: int + enum: + - 8 + - 16 + required: true + description: | + Number of gpios supported by the chip. gpio-cells: - pin diff --git a/dts/bindings/gpio/microchip,mcp23s17.yaml b/dts/bindings/gpio/microchip,mcp23s17.yaml index a6c8699bcfb4b5..b6f5279910c0dd 100644 --- a/dts/bindings/gpio/microchip,mcp23s17.yaml +++ b/dts/bindings/gpio/microchip,mcp23s17.yaml @@ -12,14 +12,14 @@ compatible: "microchip,mcp23s17" include: [gpio-controller.yaml, spi-device.yaml] properties: - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - ngpios: - type: int - required: true - const: 16 - description: Number of gpios supported + ngpios: + type: int + required: true + const: 16 + description: Number of gpios supported gpio-cells: - pin diff --git a/dts/bindings/gpio/microchip,mcp23sxx.yaml b/dts/bindings/gpio/microchip,mcp23sxx.yaml index 82b4ef48ccf8b9..cf7ff1c3d2f860 100644 --- a/dts/bindings/gpio/microchip,mcp23sxx.yaml +++ b/dts/bindings/gpio/microchip,mcp23sxx.yaml @@ -13,16 +13,16 @@ compatible: "microchip,mcp23sxx" include: [gpio-controller.yaml, spi-device.yaml] properties: - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - ngpios: - type: int - required: true - enum: - - 8 - - 16 - description: Number of gpios supported + ngpios: + type: int + required: true + enum: + - 8 + - 16 + description: Number of gpios supported gpio-cells: - pin diff --git a/dts/bindings/gpio/microchip,mpfs-gpio.yaml b/dts/bindings/gpio/microchip,mpfs-gpio.yaml index 9e403921c0e9fc..f5381133dc126b 100644 --- a/dts/bindings/gpio/microchip,mpfs-gpio.yaml +++ b/dts/bindings/gpio/microchip,mpfs-gpio.yaml @@ -8,11 +8,11 @@ compatible: "microchip,mpfs-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/microchip,xec-gpio-v2.yaml b/dts/bindings/gpio/microchip,xec-gpio-v2.yaml index affcc0e94b1d4e..22af68ce120dba 100644 --- a/dts/bindings/gpio/microchip,xec-gpio-v2.yaml +++ b/dts/bindings/gpio/microchip,xec-gpio-v2.yaml @@ -8,21 +8,21 @@ compatible: "microchip,xec-gpio-v2" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - port-id: - type: int - required: true - description: Zero based GPIO port number + port-id: + type: int + required: true + description: Zero based GPIO port number - girq-id: - type: int - required: true - description: Aggregated GIRQ number for this bank of 32 GPIO pins. + girq-id: + type: int + required: true + description: Aggregated GIRQ number for this bank of 32 GPIO pins. - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/microchip,xec-gpio.yaml b/dts/bindings/gpio/microchip,xec-gpio.yaml index 9e81a930ee9f66..21bbabf12a5851 100644 --- a/dts/bindings/gpio/microchip,xec-gpio.yaml +++ b/dts/bindings/gpio/microchip,xec-gpio.yaml @@ -8,21 +8,21 @@ compatible: "microchip,xec-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - port-id: - type: int - required: true - description: Zero based GPIO port number + port-id: + type: int + required: true + description: Zero based GPIO port number - girq-id: - type: int - required: true - description: Aggregated GIRQ number for this bank of 32 GPIO pins. + girq-id: + type: int + required: true + description: Aggregated GIRQ number for this bank of 32 GPIO pins. - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/neorv32-gpio.yaml b/dts/bindings/gpio/neorv32-gpio.yaml index 1cb175d7409b11..a357cd5eea9c09 100644 --- a/dts/bindings/gpio/neorv32-gpio.yaml +++ b/dts/bindings/gpio/neorv32-gpio.yaml @@ -5,20 +5,20 @@ compatible: "neorv32-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - reg-names: - required: true + reg-names: + required: true - syscon: - type: phandle - required: true - description: | - phandle to syscon (NEORV32 SYSINFO) node. + syscon: + type: phandle + required: true + description: | + phandle to syscon (NEORV32 SYSINFO) node. - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/nordic,nrf-gpio.yaml b/dts/bindings/gpio/nordic,nrf-gpio.yaml index 7bcba7a792abb3..550acd1a865cfe 100644 --- a/dts/bindings/gpio/nordic,nrf-gpio.yaml +++ b/dts/bindings/gpio/nordic,nrf-gpio.yaml @@ -8,29 +8,29 @@ compatible: "nordic,nrf-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - sense-edge-mask: - type: int - description: | - Mask of pins that use the GPIO sense mechanism for edge detection. - Pins not included in the mask use GPIOTE channels in the event mode. + sense-edge-mask: + type: int + description: | + Mask of pins that use the GPIO sense mechanism for edge detection. + Pins not included in the mask use GPIOTE channels in the event mode. - port: - type: int - required: true - description: | - The GPIO port number. GPIO port P0 has: + port: + type: int + required: true + description: | + The GPIO port number. GPIO port P0 has: - port = <0>; + port = <0>; - And P1 has: + And P1 has: - port = <1>; + port = <1>; gpio-cells: - pin diff --git a/dts/bindings/gpio/nordic,nrf-gpiote.yaml b/dts/bindings/gpio/nordic,nrf-gpiote.yaml index 3fc68bacbc50c1..49ddba3595ba42 100644 --- a/dts/bindings/gpio/nordic,nrf-gpiote.yaml +++ b/dts/bindings/gpio/nordic,nrf-gpiote.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-gpiote" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/gpio/nuvoton,nct38xx-gpio-alert.yaml b/dts/bindings/gpio/nuvoton,nct38xx-gpio-alert.yaml index 9160fcbbef5bad..c6043983b28646 100644 --- a/dts/bindings/gpio/nuvoton,nct38xx-gpio-alert.yaml +++ b/dts/bindings/gpio/nuvoton,nct38xx-gpio-alert.yaml @@ -16,13 +16,13 @@ compatible: "nuvoton,nct38xx-gpio-alert" include: [base.yaml] properties: - irq-gpios: - type: phandle-array - required: true - description: Interrupt GPIO pin + irq-gpios: + type: phandle-array + required: true + description: Interrupt GPIO pin - nct38xx-dev: - type: phandles - required: true - description: | - NCT38XX devices which alert are handled by this alert handler. + nct38xx-dev: + type: phandles + required: true + description: | + NCT38XX devices which alert are handled by this alert handler. diff --git a/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml b/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml index 4ccb5f20008075..af2d5eff200402 100644 --- a/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml +++ b/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml @@ -8,32 +8,32 @@ compatible: "nuvoton,nct38xx-gpio-port" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true - - pin_mask: - type: int - required: true - description: | - Not every GPIOs are usable for different NCT38XX series. This property - indicates the usable GPIO mask. - - NCT3808: <0xdc> - others: <0xff> - - pinmux_mask: - type: int - description: | - NCT38XX series port 0 has Pin Multiplexing functionality. However, not - every GPIOs have pinmux controller functionality. This property - indicates the usable GPIO pinmux mask. For port 1, this property is - ignored. - - NCT3807 port 0: <0xf7> - others: <0xff> - - "#gpio-cells": - const: 2 + reg: + required: true + + pin_mask: + type: int + required: true + description: | + Not every GPIOs are usable for different NCT38XX series. This property + indicates the usable GPIO mask. + + NCT3808: <0xdc> + others: <0xff> + + pinmux_mask: + type: int + description: | + NCT38XX series port 0 has Pin Multiplexing functionality. However, not + every GPIOs have pinmux controller functionality. This property + indicates the usable GPIO pinmux mask. For port 1, this property is + ignored. + + NCT3807 port 0: <0xf7> + others: <0xff> + + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/nuvoton,npcx-gpio.yaml b/dts/bindings/gpio/nuvoton,npcx-gpio.yaml index 22eb2f7679ea03..b1e307e237c86e 100644 --- a/dts/bindings/gpio/nuvoton,npcx-gpio.yaml +++ b/dts/bindings/gpio/nuvoton,npcx-gpio.yaml @@ -8,39 +8,39 @@ compatible: "nuvoton,npcx-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true - - index: - type: int - required: true - description: index of gpio device - - wui-maps: - type: phandles - required: true - description: | - Mapping table between Wake-Up Input (WUI) and 8 IOs belong to this device. - Please notice not all IOs connect to WUIs. - In this case, it will be presented by wui_none. - - For example the WUI mapping on NPCX7 GPIO8 would be - wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83 - &wui_none &wui_none &wui_io86 &wui_io87>; - - lvol-maps: - type: phandles - description: | - Mapping table between Low-Voltage controllers and 8 IOs belong to - this device. Please notice not all IOs support Low-Voltage detection. - In this case, it will be presented by lvol_none. - - For example the LVOL mapping on NPCX7 GPIOC would be - lvol-maps = <&lvol_none &lvol_ioc1 &lvol_ioc2 &lvol_none - &lvol_none &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>; - - "#gpio-cells": - const: 2 + reg: + required: true + + index: + type: int + required: true + description: index of gpio device + + wui-maps: + type: phandles + required: true + description: | + Mapping table between Wake-Up Input (WUI) and 8 IOs belong to this device. + Please notice not all IOs connect to WUIs. + In this case, it will be presented by wui_none. + + For example the WUI mapping on NPCX7 GPIO8 would be + wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83 + &wui_none &wui_none &wui_io86 &wui_io87>; + + lvol-maps: + type: phandles + description: | + Mapping table between Low-Voltage controllers and 8 IOs belong to + this device. Please notice not all IOs support Low-Voltage detection. + In this case, it will be presented by lvol_none. + + For example the LVOL mapping on NPCX7 GPIOC would be + lvol-maps = <&lvol_none &lvol_ioc1 &lvol_ioc2 &lvol_none + &lvol_none &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>; + + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/nuvoton,numicro-gpio.yaml b/dts/bindings/gpio/nuvoton,numicro-gpio.yaml index daf5de62c43a2e..173dcb3d7ebc45 100644 --- a/dts/bindings/gpio/nuvoton,numicro-gpio.yaml +++ b/dts/bindings/gpio/nuvoton,numicro-gpio.yaml @@ -8,14 +8,14 @@ compatible: "nuvoton,numicro-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/nxp,imx-gpio.yaml b/dts/bindings/gpio/nxp,imx-gpio.yaml index 791c617b861174..6662e639cbf85f 100644 --- a/dts/bindings/gpio/nxp,imx-gpio.yaml +++ b/dts/bindings/gpio/nxp,imx-gpio.yaml @@ -8,24 +8,24 @@ compatible: "nxp,imx-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true - - rdc: - type: int - description: Set the RDC permission for this peripheral - - pinmux: - type: phandles - description: | - IMX pin selection peripheral does not follow specific - pattern for which GPIO port uses which pinmux. Use this property to specify - pinctrl nodes to use for the gpio port when CONFIG_PINCTRL=y. Note that - the order of the nodes matters. The first node for gpio1 will be used - as the pinmux for gpio0, port 0. - - "#gpio-cells": - const: 2 + reg: + required: true + + rdc: + type: int + description: Set the RDC permission for this peripheral + + pinmux: + type: phandles + description: | + IMX pin selection peripheral does not follow specific + pattern for which GPIO port uses which pinmux. Use this property to specify + pinctrl nodes to use for the gpio port when CONFIG_PINCTRL=y. Note that + the order of the nodes matters. The first node for gpio1 will be used + as the pinmux for gpio0, port 0. + + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/nxp,kinetis-gpio.yaml b/dts/bindings/gpio/nxp,kinetis-gpio.yaml index f2aa597730e298..845a13714e0d85 100644 --- a/dts/bindings/gpio/nxp,kinetis-gpio.yaml +++ b/dts/bindings/gpio/nxp,kinetis-gpio.yaml @@ -5,18 +5,18 @@ compatible: "nxp,kinetis-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - nxp,kinetis-port: - required: true - type: phandle - description: | - A phandle reference to the device tree node that contains the pinmux - port associated with this GPIO controller. + nxp,kinetis-port: + required: true + type: phandle + description: | + A phandle reference to the device tree node that contains the pinmux + port associated with this GPIO controller. gpio-cells: - pin diff --git a/dts/bindings/gpio/nxp,lpc-gpio.yaml b/dts/bindings/gpio/nxp,lpc-gpio.yaml index 2a3ee2be72751a..0f38e0267a056f 100644 --- a/dts/bindings/gpio/nxp,lpc-gpio.yaml +++ b/dts/bindings/gpio/nxp,lpc-gpio.yaml @@ -8,25 +8,25 @@ compatible: "nxp,lpc-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - port: - type: int - required: true - description: The GPIO port this node describes - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 + port: + type: int + required: true + description: The GPIO port this node describes + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 gpio-cells: - pin diff --git a/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml b/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml index c3ab04a0f5d56e..612d6f83d19de6 100644 --- a/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml +++ b/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml @@ -8,29 +8,29 @@ compatible: "nxp,lpc11u6x-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - base: - type: int - default: 0 - description: index of the first GPIO for this port. + base: + type: int + default: 0 + description: index of the first GPIO for this port. - clocks: - required: true + clocks: + required: true - iocon: - required: true - type: phandle - description: | - a phandle reference to the devicetree node that contains the pinmux - controller associated with the GPIO controller. + iocon: + required: true + type: phandle + description: | + a phandle reference to the devicetree node that contains the pinmux + controller associated with the GPIO controller. gpio-cells: - pin diff --git a/dts/bindings/gpio/nxp,pca95xx.yaml b/dts/bindings/gpio/nxp,pca95xx.yaml index c2102f0cf5b198..449d52ac47b07c 100644 --- a/dts/bindings/gpio/nxp,pca95xx.yaml +++ b/dts/bindings/gpio/nxp,pca95xx.yaml @@ -8,20 +8,20 @@ compatible: "nxp,pca95xx" include: [gpio-controller.yaml, i2c-device.yaml] properties: - has-pud: - type: boolean - description: Supports pull-up/pull-down + has-pud: + type: boolean + description: Supports pull-up/pull-down - has-interrupt-mask-reg: - type: boolean - description: Has Interrupt mask register (PCAL95xx) + has-interrupt-mask-reg: + type: boolean + description: Has Interrupt mask register (PCAL95xx) - interrupt-gpios: - type: phandle-array - description: Interrupt GPIO pin (active-low open-drain) + interrupt-gpios: + type: phandle-array + description: Interrupt GPIO pin (active-low open-drain) - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/nxp,pcal6408a.yaml b/dts/bindings/gpio/nxp,pcal6408a.yaml index 3667bb4b405827..9f101c2826b10c 100644 --- a/dts/bindings/gpio/nxp,pcal6408a.yaml +++ b/dts/bindings/gpio/nxp,pcal6408a.yaml @@ -8,22 +8,22 @@ compatible: "nxp,pcal6408a" include: [i2c-device.yaml, gpio-controller.yaml] properties: - ngpios: - required: true - const: 8 - - int-gpios: - type: phandle-array - description: | - GPIO connected to the controller INT pin. This pin is active-low. - - reset-gpios: - type: phandle-array - description: | - GPIO connected to the controller RESET pin. This pin is active-low. - - "#gpio-cells": - const: 2 + ngpios: + required: true + const: 8 + + int-gpios: + type: phandle-array + description: | + GPIO connected to the controller INT pin. This pin is active-low. + + reset-gpios: + type: phandle-array + description: | + GPIO connected to the controller RESET pin. This pin is active-low. + + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/nxp,pcf8574.yaml b/dts/bindings/gpio/nxp,pcf8574.yaml index e48f31006b9cdf..96cb2409c16b4f 100644 --- a/dts/bindings/gpio/nxp,pcf8574.yaml +++ b/dts/bindings/gpio/nxp,pcf8574.yaml @@ -8,17 +8,17 @@ compatible: "nxp,pcf8574" include: [i2c-device.yaml, gpio-controller.yaml] properties: - ngpios: - required: true - const: 8 + ngpios: + required: true + const: 8 - int-gpios: - type: phandle-array - description: | - GPIO connected to the controller INT pin. This pin is active-low. + int-gpios: + type: phandle-array + description: | + GPIO connected to the controller INT pin. This pin is active-low. - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/nxp,s32-gpio.yaml b/dts/bindings/gpio/nxp,s32-gpio.yaml index 21208cf30cb5b0..3d19b61c9b3fe4 100644 --- a/dts/bindings/gpio/nxp,s32-gpio.yaml +++ b/dts/bindings/gpio/nxp,s32-gpio.yaml @@ -8,20 +8,20 @@ compatible: "nxp,s32-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - reg-names: - required: true + reg-names: + required: true - interrupts: - description: | - For GPIO ports that have pins can be used for processing - external interrupt signal, this is a list of GPIO pins and - respective external interrupt lines (). + interrupts: + description: | + For GPIO ports that have pins can be used for processing + external interrupt signal, this is a list of GPIO pins and + respective external interrupt lines (). - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/openisa,rv32m1-gpio.yaml b/dts/bindings/gpio/openisa,rv32m1-gpio.yaml index 9734c50019db55..369e25508d318c 100644 --- a/dts/bindings/gpio/openisa,rv32m1-gpio.yaml +++ b/dts/bindings/gpio/openisa,rv32m1-gpio.yaml @@ -5,21 +5,21 @@ compatible: "openisa,rv32m1-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - openisa,rv32m1-port: - required: true - type: phandle - description: | - A phandle reference to the device tree node that contains the pinmux - port associated with this GPIO controller. + openisa,rv32m1-port: + required: true + type: phandle + description: | + A phandle reference to the device tree node that contains the pinmux + port associated with this GPIO controller. gpio-cells: - pin diff --git a/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml b/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml index 2ce3b3245a9326..182a820db3991f 100644 --- a/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml +++ b/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml @@ -5,31 +5,31 @@ compatible: "quicklogic,eos-s3-gpio" include: [gpio-controller.yaml, base.yaml] properties: - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - pin-secondary-config: - type: int - required: true - description: | - This property is used to preconfigure the GPIOs and connect them to - a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs - which can be configured as follows - "GPIO_NUM : primary_pin_num / secondary_pin_num" - "0 : 6 / 24" - "1 : 9 / 26" - "2 : 11 / 28" - "3 : 14 / 30" - "4 : 18 / 31" - "5 : 21 / 36" - "6 : 22 / 38" - "7 : 23 / 45" - E.g. configuring GPIO 2 as secondary results in controlling pin 28, - to do so set the bit on the 2nd index of this property - "pin-secondary-config = <0x04>;" + pin-secondary-config: + type: int + required: true + description: | + This property is used to preconfigure the GPIOs and connect them to + a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs + which can be configured as follows + "GPIO_NUM : primary_pin_num / secondary_pin_num" + "0 : 6 / 24" + "1 : 9 / 26" + "2 : 11 / 28" + "3 : 14 / 30" + "4 : 18 / 31" + "5 : 21 / 36" + "6 : 22 / 38" + "7 : 23 / 45" + E.g. configuring GPIO 2 as secondary results in controlling pin 28, + to do so set the bit on the 2nd index of this property + "pin-secondary-config = <0x04>;" gpio-cells: - pin diff --git a/dts/bindings/gpio/renesas,rcar-gpio.yaml b/dts/bindings/gpio/renesas,rcar-gpio.yaml index 5fdfafc45d7f70..17df77b3583708 100644 --- a/dts/bindings/gpio/renesas,rcar-gpio.yaml +++ b/dts/bindings/gpio/renesas,rcar-gpio.yaml @@ -11,14 +11,14 @@ compatible: "renesas,rcar-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/renesas,smartbond-gpio.yaml b/dts/bindings/gpio/renesas,smartbond-gpio.yaml index 5df4b73f3012e5..36cb1537cde278 100644 --- a/dts/bindings/gpio/renesas,smartbond-gpio.yaml +++ b/dts/bindings/gpio/renesas,smartbond-gpio.yaml @@ -8,11 +8,11 @@ compatible: "renesas,smartbond-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/richtek,rt1718s.yaml b/dts/bindings/gpio/richtek,rt1718s.yaml index a1062a8e330b1c..446cde37a5511b 100644 --- a/dts/bindings/gpio/richtek,rt1718s.yaml +++ b/dts/bindings/gpio/richtek,rt1718s.yaml @@ -31,6 +31,6 @@ compatible: "richtek,rt1718s" include: [i2c-device.yaml] properties: - irq-gpios: - type: phandle-array - description: Interrupt GPIO pin connected from the chip(IRQB) + irq-gpios: + type: phandle-array + description: Interrupt GPIO pin connected from the chip(IRQB) diff --git a/dts/bindings/gpio/semtech,sx1509b.yaml b/dts/bindings/gpio/semtech,sx1509b.yaml index 03b74b4b6bbf59..b7e04843ef0db1 100644 --- a/dts/bindings/gpio/semtech,sx1509b.yaml +++ b/dts/bindings/gpio/semtech,sx1509b.yaml @@ -8,32 +8,32 @@ compatible: "semtech,sx1509b" include: [i2c-device.yaml, gpio-controller.yaml] properties: - "#gpio-cells": - const: 2 - - ngpios: - required: true - const: 16 - - nint-gpios: - type: phandle-array - description: | - Connection for the NINT signal. This signal is active-low when - produced by sx1509b GPIO node. - - init-out-low: - type: int - default: 0 - description: | - Bit mask identifying pins that should be initialized as outputs - driven low. - - init-out-high: - type: int - default: 0 - description: | - Bit mask identifying pins that should be initialized as outputs - driven high. + "#gpio-cells": + const: 2 + + ngpios: + required: true + const: 16 + + nint-gpios: + type: phandle-array + description: | + Connection for the NINT signal. This signal is active-low when + produced by sx1509b GPIO node. + + init-out-low: + type: int + default: 0 + description: | + Bit mask identifying pins that should be initialized as outputs + driven low. + + init-out-high: + type: int + default: 0 + description: | + Bit mask identifying pins that should be initialized as outputs + driven high. gpio-cells: - pin diff --git a/dts/bindings/gpio/sifive,gpio0.yaml b/dts/bindings/gpio/sifive,gpio0.yaml index 2b7e3fcc61b42e..41e7d2ae8a91e2 100644 --- a/dts/bindings/gpio/sifive,gpio0.yaml +++ b/dts/bindings/gpio/sifive,gpio0.yaml @@ -8,14 +8,14 @@ compatible: "sifive,gpio0" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/silabs,gecko-gpio-port.yaml b/dts/bindings/gpio/silabs,gecko-gpio-port.yaml index 21e4ad49d0fed8..e53ef5c8a4264d 100644 --- a/dts/bindings/gpio/silabs,gecko-gpio-port.yaml +++ b/dts/bindings/gpio/silabs,gecko-gpio-port.yaml @@ -5,16 +5,16 @@ compatible: "silabs,gecko-gpio-port" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - peripheral-id: - type: int - required: false - description: peripheral ID + peripheral-id: + type: int + required: false + description: peripheral ID - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/silabs,gecko-gpio.yaml b/dts/bindings/gpio/silabs,gecko-gpio.yaml index ab19e624646e8b..0e923fd72f8bd3 100644 --- a/dts/bindings/gpio/silabs,gecko-gpio.yaml +++ b/dts/bindings/gpio/silabs,gecko-gpio.yaml @@ -5,12 +5,12 @@ compatible: "silabs,gecko-gpio" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - location-swo: - type: int - description: Serial Wire Output (SWO) PIN location + location-swo: + type: int + description: Serial Wire Output (SWO) PIN location diff --git a/dts/bindings/gpio/snps,creg-gpio.yaml b/dts/bindings/gpio/snps,creg-gpio.yaml index 056873d7018c6e..954a9ae10d7ca1 100644 --- a/dts/bindings/gpio/snps,creg-gpio.yaml +++ b/dts/bindings/gpio/snps,creg-gpio.yaml @@ -8,23 +8,23 @@ compatible: "snps,creg-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - bit_per_gpio: - type: int - required: true + bit_per_gpio: + type: int + required: true - off_val: - type: int - required: true + off_val: + type: int + required: true - on_val: - type: int - required: true + on_val: + type: int + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/snps,designware-gpio.yaml b/dts/bindings/gpio/snps,designware-gpio.yaml index 9e33caf991cbdc..12b81c0455a614 100644 --- a/dts/bindings/gpio/snps,designware-gpio.yaml +++ b/dts/bindings/gpio/snps,designware-gpio.yaml @@ -8,11 +8,11 @@ compatible: "snps,designware-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/st,stm32-gpio.yaml b/dts/bindings/gpio/st,stm32-gpio.yaml index b1f77839a982fb..09a3a80514a9cf 100644 --- a/dts/bindings/gpio/st,stm32-gpio.yaml +++ b/dts/bindings/gpio/st,stm32-gpio.yaml @@ -8,14 +8,14 @@ compatible: "st,stm32-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/st,stmpe1600.yaml b/dts/bindings/gpio/st,stmpe1600.yaml index 8efa2b7d9b9f2a..ddd465aad94561 100644 --- a/dts/bindings/gpio/st,stmpe1600.yaml +++ b/dts/bindings/gpio/st,stmpe1600.yaml @@ -8,8 +8,8 @@ compatible: "st,stmpe1600" include: [gpio-controller.yaml, i2c-device.yaml] properties: - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/telink,b91-gpio.yaml b/dts/bindings/gpio/telink,b91-gpio.yaml index 5c01c09e62ecbf..511b61208c441c 100644 --- a/dts/bindings/gpio/telink,b91-gpio.yaml +++ b/dts/bindings/gpio/telink,b91-gpio.yaml @@ -8,11 +8,11 @@ compatible: "telink,b91-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml b/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml index acf94c55650c03..284c90d376a2d5 100644 --- a/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml +++ b/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml @@ -8,14 +8,14 @@ compatible: "ti,cc13xx-cc26xx-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/ti,cc32xx-gpio.yaml b/dts/bindings/gpio/ti,cc32xx-gpio.yaml index 1093909f0215d5..1673df891537d0 100644 --- a/dts/bindings/gpio/ti,cc32xx-gpio.yaml +++ b/dts/bindings/gpio/ti,cc32xx-gpio.yaml @@ -6,14 +6,14 @@ compatible: "ti,cc32xx-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml b/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml index 019dd1a6af984f..536b24be5c5f34 100644 --- a/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml +++ b/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml @@ -7,8 +7,8 @@ include: [gpio-controller.yaml, base.yaml] on-bus: lmp90xxx properties: - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/ti,sn74hc595.yaml b/dts/bindings/gpio/ti,sn74hc595.yaml index 77c9c0b5f7ee18..f9c0d958d1c730 100644 --- a/dts/bindings/gpio/ti,sn74hc595.yaml +++ b/dts/bindings/gpio/ti,sn74hc595.yaml @@ -8,19 +8,19 @@ compatible: "ti,sn74hc595" include: [gpio-controller.yaml, spi-device.yaml] properties: - reset-gpios: - type: phandle-array - required: true - description: Reset pin + reset-gpios: + type: phandle-array + required: true + description: Reset pin - ngpios: - type: int - required: true - const: 8 - description: Number of supported gpios + ngpios: + type: int + required: true + const: 8 + description: Number of supported gpios - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/ti,stellaris-gpio.yaml b/dts/bindings/gpio/ti,stellaris-gpio.yaml index 3bd8eca840940c..ecdfddd4a8dee9 100644 --- a/dts/bindings/gpio/ti,stellaris-gpio.yaml +++ b/dts/bindings/gpio/ti,stellaris-gpio.yaml @@ -7,14 +7,14 @@ compatible: "ti,stellaris-gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/ti,tca6424a.yaml b/dts/bindings/gpio/ti,tca6424a.yaml index 05cee578392010..1991a3ad7010ea 100644 --- a/dts/bindings/gpio/ti,tca6424a.yaml +++ b/dts/bindings/gpio/ti,tca6424a.yaml @@ -8,19 +8,19 @@ compatible: "ti,tca6424a" include: [gpio-controller.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - GPIO connected to the controller INT pin. This pin is active-low - and open-drain. + int-gpios: + type: phandle-array + description: | + GPIO connected to the controller INT pin. This pin is active-low + and open-drain. - reset-gpios: - type: phandle-array - description: | - GPIO connected to the controller RESET pin. This pin is active-low. + reset-gpios: + type: phandle-array + description: | + GPIO connected to the controller RESET pin. This pin is active-low. - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/ti,tca9538.yaml b/dts/bindings/gpio/ti,tca9538.yaml index 20e8675425930c..6cb235995abd6c 100644 --- a/dts/bindings/gpio/ti,tca9538.yaml +++ b/dts/bindings/gpio/ti,tca9538.yaml @@ -9,20 +9,20 @@ compatible: "ti,tca9538" include: [i2c-device.yaml, gpio-controller.yaml] properties: - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - ngpios: - required: true - const: 8 - description: | - Number of GPIOs available on port expander. + ngpios: + required: true + const: 8 + description: | + Number of GPIOs available on port expander. - nint-gpios: - type: phandle-array - description: | - Connection for the NINT signal. This signal is active-low when - produced by tca9538 GPIO node. + nint-gpios: + type: phandle-array + description: | + Connection for the NINT signal. This signal is active-low when + produced by tca9538 GPIO node. gpio-cells: - pin diff --git a/dts/bindings/gpio/xlnx,ps-gpio-bank.yaml b/dts/bindings/gpio/xlnx,ps-gpio-bank.yaml index 5c1bb41f782c99..43e8f457421a20 100644 --- a/dts/bindings/gpio/xlnx,ps-gpio-bank.yaml +++ b/dts/bindings/gpio/xlnx,ps-gpio-bank.yaml @@ -15,14 +15,14 @@ compatible: "xlnx,ps-gpio-bank" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 - ngpios: - required: true + ngpios: + required: true gpio-cells: - pin diff --git a/dts/bindings/gpio/xlnx,ps-gpio.yaml b/dts/bindings/gpio/xlnx,ps-gpio.yaml index bce24c6ae08fac..9271adda4e4e40 100644 --- a/dts/bindings/gpio/xlnx,ps-gpio.yaml +++ b/dts/bindings/gpio/xlnx,ps-gpio.yaml @@ -38,8 +38,8 @@ compatible: "xlnx,ps-gpio" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml index b0d8688ee55390..b2c44c436594f3 100644 --- a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml +++ b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml @@ -7,8 +7,8 @@ include: [gpio-controller.yaml, base.yaml] on-bus: xlnx,xps-gpio-1.00.a properties: - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml index dc6043adcb3d41..673f47291ca4bb 100644 --- a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml +++ b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml @@ -10,66 +10,66 @@ bus: xlnx,xps-gpio-1.00.a # https://github.com/Xilinx/device-tree-xlnx properties: - reg: - required: true - - xlnx,all-inputs: - type: int - description: | - 1 if all GPIOs are inputs, 0 otherwise - - xlnx,all-outputs: - type: int - description: | - 1 if all GPIOs are outputs, 0 otherwise - - xlnx,dout-default: - type: int - description: | - Default output value. If n-th bit is 1, GPIO-n default value is 1. - - xlnx,gpio-width: - type: int - description: | - Number of GPIOs supported - - xlnx,tri-default: - type: int - description: | - Default tristate register value. If n-th bit is 1, GPIO-n is an input. - - xlnx,is-dual: - type: int - description: | - 1 if controller has GPIO2 enabled, 0 otherwise - - xlnx,all-inputs-2: - type: int - description: | - 1 if all GPIO2s are inputs, 0 otherwise - - xlnx,all-outputs-2: - type: int - description: | - 1 if all GPIO2s are outputs, 0 otherwise - - xlnx,dout-default-2: - type: int - description: | - Default output value. If n-th bit is 1, GPIO2-n default value is 1. - - xlnx,gpio2-width: - type: int - description: | - Number of GPIO2s supported - - xlnx,tri-default-2: - type: int - description: | - Default tristate register value. If n-th bit is 1, GPIO2-n is an input. - - "#gpio-cells": - const: 2 + reg: + required: true + + xlnx,all-inputs: + type: int + description: | + 1 if all GPIOs are inputs, 0 otherwise + + xlnx,all-outputs: + type: int + description: | + 1 if all GPIOs are outputs, 0 otherwise + + xlnx,dout-default: + type: int + description: | + Default output value. If n-th bit is 1, GPIO-n default value is 1. + + xlnx,gpio-width: + type: int + description: | + Number of GPIOs supported + + xlnx,tri-default: + type: int + description: | + Default tristate register value. If n-th bit is 1, GPIO-n is an input. + + xlnx,is-dual: + type: int + description: | + 1 if controller has GPIO2 enabled, 0 otherwise + + xlnx,all-inputs-2: + type: int + description: | + 1 if all GPIO2s are inputs, 0 otherwise + + xlnx,all-outputs-2: + type: int + description: | + 1 if all GPIO2s are outputs, 0 otherwise + + xlnx,dout-default-2: + type: int + description: | + Default output value. If n-th bit is 1, GPIO2-n default value is 1. + + xlnx,gpio2-width: + type: int + description: | + Number of GPIO2s supported + + xlnx,tri-default-2: + type: int + description: | + Default tristate register value. If n-th bit is 1, GPIO2-n is an input. + + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml b/dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml index 2893740319751b..892b208e0260d1 100644 --- a/dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml +++ b/dts/bindings/gpio/zephyr,gpio-emul-sdl.yaml @@ -46,8 +46,8 @@ compatible: "zephyr,gpio-emul-sdl" include: base.yaml properties: - scancodes: - type: array - required: true - description: | - An array of SDL scancodes mapped to its GPIO index + scancodes: + type: array + required: true + description: | + An array of SDL scancodes mapped to its GPIO index diff --git a/dts/bindings/gpio/zephyr,gpio-emul.yaml b/dts/bindings/gpio/zephyr,gpio-emul.yaml index 65c6385c8989f1..b1810ef26991cc 100644 --- a/dts/bindings/gpio/zephyr,gpio-emul.yaml +++ b/dts/bindings/gpio/zephyr,gpio-emul.yaml @@ -8,27 +8,27 @@ compatible: "zephyr,gpio-emul" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - rising-edge: - description: Enables support for rising edge interrupt detection - type: boolean + rising-edge: + description: Enables support for rising edge interrupt detection + type: boolean - falling-edge: - description: Enables support for falling edge interrupt detection - type: boolean + falling-edge: + description: Enables support for falling edge interrupt detection + type: boolean - high-level: - description: Enables support for high level interrupt detection - type: boolean + high-level: + description: Enables support for high level interrupt detection + type: boolean - low-level: - description: Enables support for low level interrupt detection - type: boolean + low-level: + description: Enables support for low level interrupt detection + type: boolean - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/hda/intel,hda-dai.yaml b/dts/bindings/hda/intel,hda-dai.yaml index 110f463a054076..765673d7a65413 100644 --- a/dts/bindings/hda/intel,hda-dai.yaml +++ b/dts/bindings/hda/intel,hda-dai.yaml @@ -9,5 +9,5 @@ compatible: "intel,hda-dai" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/hwinfo/atmel,sam4l-uid.yaml b/dts/bindings/hwinfo/atmel,sam4l-uid.yaml index a8a76aa1342bdc..b9d612fd282410 100644 --- a/dts/bindings/hwinfo/atmel,sam4l-uid.yaml +++ b/dts/bindings/hwinfo/atmel,sam4l-uid.yaml @@ -8,5 +8,5 @@ compatible: "atmel,sam4l-uid" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/hwinfo/cypress,psoc6-uid.yaml b/dts/bindings/hwinfo/cypress,psoc6-uid.yaml index d713960dd29dc7..8602842c074b41 100644 --- a/dts/bindings/hwinfo/cypress,psoc6-uid.yaml +++ b/dts/bindings/hwinfo/cypress,psoc6-uid.yaml @@ -8,5 +8,5 @@ compatible: "cypress,psoc6-uid" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/hwinfo/litex,dna0.yaml b/dts/bindings/hwinfo/litex,dna0.yaml index 64e4f4e2062f5e..23ac0e6eece295 100644 --- a/dts/bindings/hwinfo/litex,dna0.yaml +++ b/dts/bindings/hwinfo/litex,dna0.yaml @@ -8,5 +8,5 @@ compatible: "litex,dna0" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/hwinfo/microchip,xec-ecs.yaml b/dts/bindings/hwinfo/microchip,xec-ecs.yaml index 90f78fee449bef..55d848902331f1 100644 --- a/dts/bindings/hwinfo/microchip,xec-ecs.yaml +++ b/dts/bindings/hwinfo/microchip,xec-ecs.yaml @@ -8,5 +8,5 @@ compatible: "microchip,xec-ecs" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/hwinfo/nxp,lpc-uid.yaml b/dts/bindings/hwinfo/nxp,lpc-uid.yaml index 9d47c3b7157181..435427983348c0 100644 --- a/dts/bindings/hwinfo/nxp,lpc-uid.yaml +++ b/dts/bindings/hwinfo/nxp,lpc-uid.yaml @@ -8,5 +8,5 @@ compatible: "nxp,lpc-uid" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/i2c/altr,nios2-i2c.yaml b/dts/bindings/i2c/altr,nios2-i2c.yaml index 87a87504e2134c..0ab4f53fc4fb96 100644 --- a/dts/bindings/i2c/altr,nios2-i2c.yaml +++ b/dts/bindings/i2c/altr,nios2-i2c.yaml @@ -8,8 +8,8 @@ compatible: "altr,nios2-i2c" include: i2c-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/i2c/andestech,atciic100.yaml b/dts/bindings/i2c/andestech,atciic100.yaml index c922d16441db94..1af3b04c181655 100644 --- a/dts/bindings/i2c/andestech,atciic100.yaml +++ b/dts/bindings/i2c/andestech,atciic100.yaml @@ -5,15 +5,15 @@ # description: - This is a representation of AndesTech atciic100 I2C node + This is a representation of AndesTech atciic100 I2C node compatible: "andestech,atciic100" include: i2c-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/i2c/arm,versatile-i2c.yaml b/dts/bindings/i2c/arm,versatile-i2c.yaml index 2f7c145cb100d0..c88d87002e5dd9 100644 --- a/dts/bindings/i2c/arm,versatile-i2c.yaml +++ b/dts/bindings/i2c/arm,versatile-i2c.yaml @@ -8,5 +8,5 @@ compatible: "arm,versatile-i2c" include: i2c-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/i2c/atmel,sam-i2c-twi.yaml b/dts/bindings/i2c/atmel,sam-i2c-twi.yaml index 4c64435dddd51c..491ac2f475af53 100644 --- a/dts/bindings/i2c/atmel,sam-i2c-twi.yaml +++ b/dts/bindings/i2c/atmel,sam-i2c-twi.yaml @@ -6,17 +6,17 @@ description: Atmel SAM Family I2C (TWI) node compatible: "atmel,sam-i2c-twi" include: - - name: i2c-controller.yaml - - name: pinctrl-device.yaml + - name: i2c-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml b/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml index da8d58536dbfc1..22cd734c9177c6 100644 --- a/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml +++ b/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml @@ -6,17 +6,17 @@ description: Atmel SAM Family I2C (TWIHS) node compatible: "atmel,sam-i2c-twihs" include: - - name: i2c-controller.yaml - - name: pinctrl-device.yaml + - name: i2c-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/i2c/atmel,sam-i2c-twim.yaml b/dts/bindings/i2c/atmel,sam-i2c-twim.yaml index 0ce59ced15d858..1eb5aece558319 100644 --- a/dts/bindings/i2c/atmel,sam-i2c-twim.yaml +++ b/dts/bindings/i2c/atmel,sam-i2c-twim.yaml @@ -38,168 +38,168 @@ description: | compatible: "atmel,sam-i2c-twim" include: - - name: i2c-controller.yaml - - name: pinctrl-device.yaml + - name: i2c-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true - - interrupts: - required: true - - peripheral-id: - type: int - required: true - description: peripheral ID - - std-clk-slew-lim: - type: int - required: true - description: | - Slew limit of the TWCK output buffer. This should be adjusted with - std-clk-strength-low to fine tune the TWCK slope. - enum: - - 0 - - 1 - - 2 - - 3 - - std-clk-strength-low: - type: string - required: true - description: | - Pull-down drive strength of the TWCK output buffer in fast/fast plus - mode. This should be adjusted to provide proper TWCK line fall time. - The value represents the port output current in mA when signal on - low level. - enum: - - "0.5" - - "1.0" - - "1.6" - - "3.1" - - "6.2" - - "9.3" - - "15.5" - - "21.8" - - std-data-slew-lim: - type: int - required: true - description: | - Slew limit of the TWD output buffer. This should be adjusted with - std-data-strength-low to fine tune the TWD slope. - enum: - - 0 - - 1 - - 2 - - 3 - - std-data-strength-low: - type: string - required: true - description: | - Pull-down drive strength of the TWD output buffer in fast/fast plus - mode. This should be adjusted to provide proper TWD line fall time. - The value represents the port output current in mA when signal on - low level. - enum: - - "0.5" - - "1.0" - - "1.6" - - "3.1" - - "6.2" - - "9.3" - - "15.5" - - "21.8" - - hs-clk-slew-lim: - type: int - required: true - description: | - Slew limit of the TWCK output buffer in high speed mode. This - should be adjusted with both hs-clk-strength-high and - hs-clk-strength-low to fine tune the TWCK slope. - enum: - - 0 - - 1 - - 2 - - 3 - - hs-clk-strength-high: - type: string - required: true - description: | - Pull-up drive strength of the TWCK output buffer in high speed - mode. This should be adjusted to provide proper TWCK line rise time. - The value represents the port output current in mA when signal on - high level. - enum: - - "0.5" - - "1.0" - - "1.5" - - "3.0" - - hs-clk-strength-low: - type: string - required: true - description: | - Pull-down drive strength of the TWCK output buffer in high speed - mode. This should be adjusted to provide proper TWCK line fall time. - The value represents the port output current in mA when signal on - low level. - enum: - - "0.5" - - "1.0" - - "1.6" - - "3.1" - - "6.2" - - "9.3" - - "15.5" - - "21.8" - - hs-data-slew-lim: - type: int - required: true - description: | - Slew limit of the TWD output buffer in high speed mode. This - should be adjusted with hs-data-strength-low to fine tune the TWD - slope. - enum: - - 0 - - 1 - - 2 - - 3 - - hs-data-strength-low: - type: string - description: | - Pull-down drive strength of the TWD output buffer in high speed - mode. This should be adjusted to provide proper TWD line fall time. - The value represents the port output current in mA when signal on - low level. - enum: - - "0.5" - - "1.0" - - "1.6" - - "3.1" - - "6.2" - - "9.3" - - "15.5" - - "21.8" - - hs-master-code: - type: int - required: true - description: | - 3-bit code to be prefixed with 0b00001 to form a unique - 8-bit HS-mode master code (0000 1XXX) - enum: - - 0 # 000 - - 1 # 001 - - 2 # 010 - - 3 # 011 - - 4 # 100 - - 5 # 101 - - 6 # 110 - - 7 # 111 + reg: + required: true + + interrupts: + required: true + + peripheral-id: + type: int + required: true + description: peripheral ID + + std-clk-slew-lim: + type: int + required: true + description: | + Slew limit of the TWCK output buffer. This should be adjusted with + std-clk-strength-low to fine tune the TWCK slope. + enum: + - 0 + - 1 + - 2 + - 3 + + std-clk-strength-low: + type: string + required: true + description: | + Pull-down drive strength of the TWCK output buffer in fast/fast plus + mode. This should be adjusted to provide proper TWCK line fall time. + The value represents the port output current in mA when signal on + low level. + enum: + - "0.5" + - "1.0" + - "1.6" + - "3.1" + - "6.2" + - "9.3" + - "15.5" + - "21.8" + + std-data-slew-lim: + type: int + required: true + description: | + Slew limit of the TWD output buffer. This should be adjusted with + std-data-strength-low to fine tune the TWD slope. + enum: + - 0 + - 1 + - 2 + - 3 + + std-data-strength-low: + type: string + required: true + description: | + Pull-down drive strength of the TWD output buffer in fast/fast plus + mode. This should be adjusted to provide proper TWD line fall time. + The value represents the port output current in mA when signal on + low level. + enum: + - "0.5" + - "1.0" + - "1.6" + - "3.1" + - "6.2" + - "9.3" + - "15.5" + - "21.8" + + hs-clk-slew-lim: + type: int + required: true + description: | + Slew limit of the TWCK output buffer in high speed mode. This + should be adjusted with both hs-clk-strength-high and + hs-clk-strength-low to fine tune the TWCK slope. + enum: + - 0 + - 1 + - 2 + - 3 + + hs-clk-strength-high: + type: string + required: true + description: | + Pull-up drive strength of the TWCK output buffer in high speed + mode. This should be adjusted to provide proper TWCK line rise time. + The value represents the port output current in mA when signal on + high level. + enum: + - "0.5" + - "1.0" + - "1.5" + - "3.0" + + hs-clk-strength-low: + type: string + required: true + description: | + Pull-down drive strength of the TWCK output buffer in high speed + mode. This should be adjusted to provide proper TWCK line fall time. + The value represents the port output current in mA when signal on + low level. + enum: + - "0.5" + - "1.0" + - "1.6" + - "3.1" + - "6.2" + - "9.3" + - "15.5" + - "21.8" + + hs-data-slew-lim: + type: int + required: true + description: | + Slew limit of the TWD output buffer in high speed mode. This + should be adjusted with hs-data-strength-low to fine tune the TWD + slope. + enum: + - 0 + - 1 + - 2 + - 3 + + hs-data-strength-low: + type: string + description: | + Pull-down drive strength of the TWD output buffer in high speed + mode. This should be adjusted to provide proper TWD line fall time. + The value represents the port output current in mA when signal on + low level. + enum: + - "0.5" + - "1.0" + - "1.6" + - "3.1" + - "6.2" + - "9.3" + - "15.5" + - "21.8" + + hs-master-code: + type: int + required: true + description: | + 3-bit code to be prefixed with 0b00001 to form a unique + 8-bit HS-mode master code (0000 1XXX) + enum: + - 0 # 000 + - 1 # 001 + - 2 # 010 + - 3 # 011 + - 4 # 100 + - 5 # 101 + - 6 # 110 + - 7 # 111 diff --git a/dts/bindings/i2c/atmel,sam0-i2c.yaml b/dts/bindings/i2c/atmel,sam0-i2c.yaml index aaa46d6173752c..9f8d34e95f95a0 100644 --- a/dts/bindings/i2c/atmel,sam0-i2c.yaml +++ b/dts/bindings/i2c/atmel,sam0-i2c.yaml @@ -6,35 +6,35 @@ description: Atmel SAM0 series SERCOM I2C node compatible: "atmel,sam0-i2c" include: - - name: i2c-controller.yaml - - name: pinctrl-device.yaml + - name: i2c-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - clock-names: - required: true + clock-names: + required: true - dmas: - description: | - Optional TX & RX dma specifiers. Each specifier will have a phandle - reference to the dmac controller, the channel number, and peripheral - trigger source. + dmas: + description: | + Optional TX & RX dma specifiers. Each specifier will have a phandle + reference to the dmac controller, the channel number, and peripheral + trigger source. - For example dmas for TX, RX on SERCOM3 - dmas = <&dmac 0 0xb>, <&dmac 0 0xa>; + For example dmas for TX, RX on SERCOM3 + dmas = <&dmac 0 0xb>, <&dmac 0 0xa>; - dma-names: - description: | - Required if the dmas property exists. This should be "tx" and "rx" - to match the dmas property. + dma-names: + description: | + Required if the dmas property exists. This should be "tx" and "rx" + to match the dmas property. - For example - dma-names = "tx", "rx"; + For example + dma-names = "tx", "rx"; diff --git a/dts/bindings/i2c/espressif,esp32-i2c.yaml b/dts/bindings/i2c/espressif,esp32-i2c.yaml index 25389894c79467..13e38c01002a50 100644 --- a/dts/bindings/i2c/espressif,esp32-i2c.yaml +++ b/dts/bindings/i2c/espressif,esp32-i2c.yaml @@ -9,42 +9,42 @@ compatible: "espressif,esp32-i2c" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - scl-gpios: - type: phandle-array - description: | - GPIO to which the I2C SCL signal is routed. This is only required - if the target SoC does not have support in hardware for clearing - the I2C bus in case of a communication failure - - sda-gpios: - type: phandle-array - description: | - GPIO to which the I2C SDA signal is routed. This is only required - if the target SoC does not have support in hardware for clearing - the I2C bus in case of a communication failure - - tx-lsb: - type: boolean - description: Set I2C TX data as LSB - - rx-lsb: - type: boolean - description: Set I2C RX data as LSB - - scl-timeout-us: - type: int - description: | - Timeout for unchanged SCL during clock stretching of the I2C target in - microseconds. - - If not set or 0, the timeout is disabled or set to the maximum possible - value if the MCU does not support disabling the timeout. + reg: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + scl-gpios: + type: phandle-array + description: | + GPIO to which the I2C SCL signal is routed. This is only required + if the target SoC does not have support in hardware for clearing + the I2C bus in case of a communication failure + + sda-gpios: + type: phandle-array + description: | + GPIO to which the I2C SDA signal is routed. This is only required + if the target SoC does not have support in hardware for clearing + the I2C bus in case of a communication failure + + tx-lsb: + type: boolean + description: Set I2C TX data as LSB + + rx-lsb: + type: boolean + description: Set I2C RX data as LSB + + scl-timeout-us: + type: int + description: | + Timeout for unchanged SCL during clock stretching of the I2C target in + microseconds. + + If not set or 0, the timeout is disabled or set to the maximum possible + value if the MCU does not support disabling the timeout. diff --git a/dts/bindings/i2c/fsl,imx21-i2c.yaml b/dts/bindings/i2c/fsl,imx21-i2c.yaml index 09f92b5270c4f7..8c9238dc396bf8 100644 --- a/dts/bindings/i2c/fsl,imx21-i2c.yaml +++ b/dts/bindings/i2c/fsl,imx21-i2c.yaml @@ -8,13 +8,13 @@ compatible: "fsl,imx21-i2c" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - rdc: - type: int - required: true - description: Set the RDC permission for this peripheral + rdc: + type: int + required: true + description: Set the RDC permission for this peripheral diff --git a/dts/bindings/i2c/gpio-i2c.yaml b/dts/bindings/i2c/gpio-i2c.yaml index 45319d693b3e55..e9913d014a96ca 100644 --- a/dts/bindings/i2c/gpio-i2c.yaml +++ b/dts/bindings/i2c/gpio-i2c.yaml @@ -8,11 +8,11 @@ compatible: "gpio-i2c" include: i2c-controller.yaml properties: - scl-gpios: - type: phandle-array - required: true - description: GPIO to which the SCL pin of the I2C bus is connected. - sda-gpios: - type: phandle-array - required: true - description: GPIO to which the SDA pin of the I2C bus is connected. + scl-gpios: + type: phandle-array + required: true + description: GPIO to which the SCL pin of the I2C bus is connected. + sda-gpios: + type: phandle-array + required: true + description: GPIO to which the SDA pin of the I2C bus is connected. diff --git a/dts/bindings/i2c/i2c-controller.yaml b/dts/bindings/i2c/i2c-controller.yaml index ddef102e4733eb..f8b3a30dcf6668 100644 --- a/dts/bindings/i2c/i2c-controller.yaml +++ b/dts/bindings/i2c/i2c-controller.yaml @@ -8,12 +8,12 @@ include: base.yaml bus: i2c properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - required: true - const: 0 - clock-frequency: - type: int - description: Initial clock frequency in Hz + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 0 + clock-frequency: + type: int + description: Initial clock frequency in Hz diff --git a/dts/bindings/i2c/i2c-device.yaml b/dts/bindings/i2c/i2c-device.yaml index 1df4a7fffad9c7..de3824fc35a62f 100644 --- a/dts/bindings/i2c/i2c-device.yaml +++ b/dts/bindings/i2c/i2c-device.yaml @@ -8,6 +8,6 @@ include: [base.yaml, power.yaml] on-bus: i2c properties: - reg: - required: true - description: device address on i2c bus + reg: + required: true + description: device address on i2c bus diff --git a/dts/bindings/i2c/ite,common-i2c.yaml b/dts/bindings/i2c/ite,common-i2c.yaml index 8ac9a60fc35945..251903efafcc4b 100644 --- a/dts/bindings/i2c/ite,common-i2c.yaml +++ b/dts/bindings/i2c/ite,common-i2c.yaml @@ -6,51 +6,51 @@ description: Common fields for ITE it8xxx2 I2C include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - port-num: - type: int - required: true - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - description: Ordinal identifying the port - 0 = SMB_CHANNEL_A, - 1 = SMB_CHANNEL_B, - 2 = SMB_CHANNEL_C, - 3 = I2C_CHANNEL_D, - 4 = I2C_CHANNEL_E, - 5 = I2C_CHANNEL_F, - - scl-gpios: - type: phandle-array - required: true - description: | - The SCL pin for the selected port. - - sda-gpios: - type: phandle-array - required: true - description: | - The SDA pin for the selected port. - - clock-gate-offset: - type: int - required: true - description: | - The clock gate offsets combine the register offset from - ECPM_BASE and the mask within that register into one value. - - pinctrl-0: - required: true - - pinctrl-names: - required: true + reg: + required: true + + interrupts: + required: true + + port-num: + type: int + required: true + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + description: Ordinal identifying the port + 0 = SMB_CHANNEL_A, + 1 = SMB_CHANNEL_B, + 2 = SMB_CHANNEL_C, + 3 = I2C_CHANNEL_D, + 4 = I2C_CHANNEL_E, + 5 = I2C_CHANNEL_F, + + scl-gpios: + type: phandle-array + required: true + description: | + The SCL pin for the selected port. + + sda-gpios: + type: phandle-array + required: true + description: | + The SDA pin for the selected port. + + clock-gate-offset: + type: int + required: true + description: | + The clock gate offsets combine the register offset from + ECPM_BASE and the mask within that register into one value. + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/i2c/ite,enhance-i2c.yaml b/dts/bindings/i2c/ite,enhance-i2c.yaml index b1813c5e24841f..c9f0adf198610e 100644 --- a/dts/bindings/i2c/ite,enhance-i2c.yaml +++ b/dts/bindings/i2c/ite,enhance-i2c.yaml @@ -8,12 +8,12 @@ compatible: "ite,enhance-i2c" include: ite,common-i2c.yaml properties: - prescale-scl-low: - type: int - description: | - This option is used to configure the I2C speed prescaler for - the SCL low period. When set to >= 1, it will increase the - low period of the SCL clock and so reduce the signal frequency. - The resulting SCL cycle time is given by the following formula: - SCL cycle = 2 * (psr + prescale_tweak + 2) * - SMBus clock cycle + prescale-scl-low: + type: int + description: | + This option is used to configure the I2C speed prescaler for + the SCL low period. When set to >= 1, it will increase the + low period of the SCL clock and so reduce the signal frequency. + The resulting SCL cycle time is given by the following formula: + SCL cycle = 2 * (psr + prescale_tweak + 2) * + SMBus clock cycle diff --git a/dts/bindings/i2c/ite,it8xxx2-i2c.yaml b/dts/bindings/i2c/ite,it8xxx2-i2c.yaml index 9891eb17733c76..3b045cb1781323 100644 --- a/dts/bindings/i2c/ite,it8xxx2-i2c.yaml +++ b/dts/bindings/i2c/ite,it8xxx2-i2c.yaml @@ -8,8 +8,8 @@ compatible: "ite,it8xxx2-i2c" include: ite,common-i2c.yaml properties: - fifo-enable: - type: boolean - description: | - FIFO1 supports channel A. - FIFO2 only supports one channel of B or C. + fifo-enable: + type: boolean + description: | + FIFO1 supports channel A. + FIFO2 only supports one channel of B or C. diff --git a/dts/bindings/i2c/litex,i2c.yaml b/dts/bindings/i2c/litex,i2c.yaml index d243b26949be69..acb9032bd4eb71 100644 --- a/dts/bindings/i2c/litex,i2c.yaml +++ b/dts/bindings/i2c/litex,i2c.yaml @@ -11,5 +11,5 @@ compatible: "litex,i2c" include: i2c-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/i2c/microchip,xec-i2c-v2.yaml b/dts/bindings/i2c/microchip,xec-i2c-v2.yaml index 7374cdb73268ca..619e8e86231d35 100644 --- a/dts/bindings/i2c/microchip,xec-i2c-v2.yaml +++ b/dts/bindings/i2c/microchip,xec-i2c-v2.yaml @@ -8,26 +8,26 @@ compatible: "microchip,xec-i2c-v2" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - port_sel: - type: int - description: soc block mapping to pin - required: true + port_sel: + type: int + description: soc block mapping to pin + required: true - girqs: - type: array - required: true - description: array of GIRQ numbers [8:26] and bit positions [0:31] + girqs: + type: array + required: true + description: array of GIRQ numbers [8:26] and bit positions [0:31] - pcrs: - type: array - required: true - description: PCR sleep register index and bit position + pcrs: + type: array + required: true + description: PCR sleep register index and bit position - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/i2c/microchip,xec-i2c.yaml b/dts/bindings/i2c/microchip,xec-i2c.yaml index 50cdc531402cdd..d5bd35bae49b8d 100644 --- a/dts/bindings/i2c/microchip,xec-i2c.yaml +++ b/dts/bindings/i2c/microchip,xec-i2c.yaml @@ -8,40 +8,40 @@ compatible: "microchip,xec-i2c" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - port_sel: - type: int - description: soc block mapping to pin - required: true - - girq: - type: int - required: true - description: GIRQ for this device - - girq-bit: - type: int - required: true - description: Bit position in GIRQ for this device - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - sda-gpios: - type: phandle-array - required: true - description: | - The SDA pin for the selected port. Pin choice for port is - determined by chip and package. - - scl-gpios: - type: phandle-array - required: true - description: | - The SCL pin for the selected port. Pin choice for port is - determined by chip and package. + reg: + required: true + + port_sel: + type: int + description: soc block mapping to pin + required: true + + girq: + type: int + required: true + description: GIRQ for this device + + girq-bit: + type: int + required: true + description: Bit position in GIRQ for this device + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + sda-gpios: + type: phandle-array + required: true + description: | + The SDA pin for the selected port. Pin choice for port is + determined by chip and package. + + scl-gpios: + type: phandle-array + required: true + description: | + The SCL pin for the selected port. Pin choice for port is + determined by chip and package. diff --git a/dts/bindings/i2c/nordic,nrf-twi-common.yaml b/dts/bindings/i2c/nordic,nrf-twi-common.yaml index 213a6025b5f414..f2f35d51a43eb3 100644 --- a/dts/bindings/i2c/nordic,nrf-twi-common.yaml +++ b/dts/bindings/i2c/nordic,nrf-twi-common.yaml @@ -7,37 +7,37 @@ include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - sda-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. + sda-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. - The SDA pin to use. + The SDA pin to use. - For pins P0.0 through P0.31, use the pin number. For example, - to use P0.16 for SDA, set: + For pins P0.0 through P0.31, use the pin number. For example, + to use P0.16 for SDA, set: - sda-pin = <16>; + sda-pin = <16>; - For pins P1.0 through P1.31, add 32 to the pin number. For - example, to use P1.2 for SDA, set: + For pins P1.0 through P1.31, add 32 to the pin number. For + example, to use P1.2 for SDA, set: - sda-pin = <34>; /* 32 + 2 */ + sda-pin = <34>; /* 32 + 2 */ - scl-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. + scl-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. - The SCL pin to use. The pin numbering scheme is the same as - the sda-pin property's. + The SCL pin to use. The pin numbering scheme is the same as + the sda-pin property's. diff --git a/dts/bindings/i2c/nordic,nrf-twim.yaml b/dts/bindings/i2c/nordic,nrf-twim.yaml index 4980a95e7b2c5a..feab0e61bae72a 100644 --- a/dts/bindings/i2c/nordic,nrf-twim.yaml +++ b/dts/bindings/i2c/nordic,nrf-twim.yaml @@ -26,36 +26,36 @@ compatible: "nordic,nrf-twim" include: nordic,nrf-twi-common.yaml properties: - zephyr,concat-buf-size: - type: int - default: 16 - description: | - Size of a concatenation buffer that the driver is to use for merging - multiple same direction I2C messages that have no RESTART or STOP - flag between them (see e.g. the i2c_burst_write() function) into one - transfer on the bus. - - This property must be provided when interacting with devices like - the SSD1306 display that cannot tolerate a repeated start and - address appearing on the bus between message fragments. For many - devices a concatenation buffer is not necessary. - - zephyr,flash-buf-max-size: - type: int - default: 16 - description: | - TWIM peripherals cannot perform write transactions from buffers - located in flash. If such buffers are expected to be used with - a given instance of the TWIM peripheral, this property must be - set to the maximum possible size of those buffers, so that the - driver can reserve enough space in RAM to copy there the contents - of particular buffers before requesting the actual transfers. - - If this property is not set to a value adequate for a given - application, write transactions may fail for buffers that are - located in flash, what in turn may cause certain components, - like the DPS310 sensor driver, to not work. - - It is recommended to use the same value for this property and for - the zephyr,concat-buf-size one, as both these buffering mechanisms - can utilize the same space in RAM. + zephyr,concat-buf-size: + type: int + default: 16 + description: | + Size of a concatenation buffer that the driver is to use for merging + multiple same direction I2C messages that have no RESTART or STOP + flag between them (see e.g. the i2c_burst_write() function) into one + transfer on the bus. + + This property must be provided when interacting with devices like + the SSD1306 display that cannot tolerate a repeated start and + address appearing on the bus between message fragments. For many + devices a concatenation buffer is not necessary. + + zephyr,flash-buf-max-size: + type: int + default: 16 + description: | + TWIM peripherals cannot perform write transactions from buffers + located in flash. If such buffers are expected to be used with + a given instance of the TWIM peripheral, this property must be + set to the maximum possible size of those buffers, so that the + driver can reserve enough space in RAM to copy there the contents + of particular buffers before requesting the actual transfers. + + If this property is not set to a value adequate for a given + application, write transactions may fail for buffers that are + located in flash, what in turn may cause certain components, + like the DPS310 sensor driver, to not work. + + It is recommended to use the same value for this property and for + the zephyr,concat-buf-size one, as both these buffering mechanisms + can utilize the same space in RAM. diff --git a/dts/bindings/i2c/nordic,nrf-twis.yaml b/dts/bindings/i2c/nordic,nrf-twis.yaml index f44ccfd9cb5cb3..01d39a13627cad 100644 --- a/dts/bindings/i2c/nordic,nrf-twis.yaml +++ b/dts/bindings/i2c/nordic,nrf-twis.yaml @@ -30,10 +30,10 @@ compatible: "nordic,nrf-twis" include: nordic,nrf-twi-common.yaml properties: - address-0: - type: int - description: TWI slave address 0 + address-0: + type: int + description: TWI slave address 0 - address-1: - type: int - description: TWI slave address 1 + address-1: + type: int + description: TWI slave address 1 diff --git a/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml b/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml index 43b92156c2f182..e14ce0ae236b7c 100644 --- a/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml +++ b/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml @@ -8,7 +8,7 @@ compatible: "nuvoton,npcx-i2c-ctrl" include: base.yaml properties: - reg: - required: true - clocks: - required: true + reg: + required: true + clocks: + required: true diff --git a/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml b/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml index d94266000e6a01..8f5f288705e87a 100644 --- a/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml +++ b/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml @@ -8,21 +8,21 @@ compatible: "nuvoton,npcx-i2c-port" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - port: - type: int - required: true - description: index of i2c port + port: + type: int + required: true + description: index of i2c port - controller: - type: phandle - required: true - description: i2c controller to handle signals from port pads + controller: + type: phandle + required: true + description: i2c controller to handle signals from port pads - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - clock-frequency: - required: true + clock-frequency: + required: true diff --git a/dts/bindings/i2c/nxp,imx-lpi2c.yaml b/dts/bindings/i2c/nxp,imx-lpi2c.yaml index 79c617f0ae9b69..50437430918e0a 100644 --- a/dts/bindings/i2c/nxp,imx-lpi2c.yaml +++ b/dts/bindings/i2c/nxp,imx-lpi2c.yaml @@ -8,24 +8,24 @@ compatible: "nxp,imx-lpi2c" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - bus-idle-timeout: - type: int - description: Bus idle timeout in nanoseconds - - scl-gpios: - type: phandle-array - description: | - GPIO to which the I2C SCL signal is routed. This is only needed for I2C bus recovery - support. - - sda-gpios: - type: phandle-array - description: | - GPIO to which the I2C SDA signal is routed. This is only needed for I2C bus recovery - support. + reg: + required: true + + interrupts: + required: true + + bus-idle-timeout: + type: int + description: Bus idle timeout in nanoseconds + + scl-gpios: + type: phandle-array + description: | + GPIO to which the I2C SCL signal is routed. This is only needed for I2C bus recovery + support. + + sda-gpios: + type: phandle-array + description: | + GPIO to which the I2C SDA signal is routed. This is only needed for I2C bus recovery + support. diff --git a/dts/bindings/i2c/nxp,kinetis-i2c.yaml b/dts/bindings/i2c/nxp,kinetis-i2c.yaml index 8e64083e1cd2cb..86bf2897a93a00 100644 --- a/dts/bindings/i2c/nxp,kinetis-i2c.yaml +++ b/dts/bindings/i2c/nxp,kinetis-i2c.yaml @@ -8,12 +8,12 @@ compatible: "nxp,kinetis-i2c" include: ["i2c-controller.yaml", "pinctrl-device.yaml"] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - type: phandles - required: true + pinctrl-0: + type: phandles + required: true diff --git a/dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml b/dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml index 5aeb57900b3f4a..757e0b18c19029 100644 --- a/dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml +++ b/dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml @@ -8,17 +8,17 @@ compatible: "nxp,lpc11u6x-i2c" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml b/dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml index cf575024601fc7..82f77c08a7ea14 100644 --- a/dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml +++ b/dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml @@ -8,8 +8,8 @@ compatible: "openisa,rv32m1-lpi2c" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/i2c/renesas,rcar-i2c.yaml b/dts/bindings/i2c/renesas,rcar-i2c.yaml index 620b33cce7712b..8c4bcdbfa4d9fe 100644 --- a/dts/bindings/i2c/renesas,rcar-i2c.yaml +++ b/dts/bindings/i2c/renesas,rcar-i2c.yaml @@ -8,9 +8,9 @@ compatible: "renesas,rcar-i2c" include: i2c-controller.yaml properties: - reg: - required: true - interrupts: - required: true - clocks: - required: true + reg: + required: true + interrupts: + required: true + clocks: + required: true diff --git a/dts/bindings/i2c/sifive,i2c0.yaml b/dts/bindings/i2c/sifive,i2c0.yaml index ab0b1102149741..81c94e29e6c0d6 100644 --- a/dts/bindings/i2c/sifive,i2c0.yaml +++ b/dts/bindings/i2c/sifive,i2c0.yaml @@ -8,5 +8,5 @@ compatible: "sifive,i2c0" include: i2c-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/i2c/silabs,gecko-i2c.yaml b/dts/bindings/i2c/silabs,gecko-i2c.yaml index 84d1b76008d3a5..8d1e4d94ee75ec 100644 --- a/dts/bindings/i2c/silabs,gecko-i2c.yaml +++ b/dts/bindings/i2c/silabs,gecko-i2c.yaml @@ -8,21 +8,21 @@ compatible: "silabs,gecko-i2c" include: i2c-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - # Note: Not all SoC series support setting individual pin location. If this - # is a case all location-* properties need to have identical value. + # Note: Not all SoC series support setting individual pin location. If this + # is a case all location-* properties need to have identical value. - location-sda: - type: array - required: true - description: SDA pin configuration defined as + location-sda: + type: array + required: true + description: SDA pin configuration defined as - location-scl: - type: array - required: true - description: SCL pin configuration defined as + location-scl: + type: array + required: true + description: SCL pin configuration defined as diff --git a/dts/bindings/i2c/snps,designware-i2c.yaml b/dts/bindings/i2c/snps,designware-i2c.yaml index 3c8014cf8c1763..596558cec0b5f3 100644 --- a/dts/bindings/i2c/snps,designware-i2c.yaml +++ b/dts/bindings/i2c/snps,designware-i2c.yaml @@ -8,5 +8,5 @@ compatible: "snps,designware-i2c" include: [i2c-controller.yaml, pinctrl-device.yaml, pcie-device.yaml] properties: - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/i2c/st,stm32-i2c-v1.yaml b/dts/bindings/i2c/st,stm32-i2c-v1.yaml index d86cdb8aedd87b..e2b73dc4fdee0a 100644 --- a/dts/bindings/i2c/st,stm32-i2c-v1.yaml +++ b/dts/bindings/i2c/st,stm32-i2c-v1.yaml @@ -8,14 +8,14 @@ compatible: "st,stm32-i2c-v1" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/i2c/st,stm32-i2c-v2.yaml b/dts/bindings/i2c/st,stm32-i2c-v2.yaml index c2e617c6e3d1cf..46772c859fa920 100644 --- a/dts/bindings/i2c/st,stm32-i2c-v2.yaml +++ b/dts/bindings/i2c/st,stm32-i2c-v2.yaml @@ -8,38 +8,38 @@ compatible: "st,stm32-i2c-v2" include: [i2c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - timings: - type: array - description: | - An optional table of pre-computed i2c timing values with the - matching clock configuration. + timings: + type: array + description: | + An optional table of pre-computed i2c timing values with the + matching clock configuration. - Precise timings values for a given Hardware can be pre-computed - with a tool like STM32CubeMX or directly from I2C_TIMINGR register - description. + Precise timings values for a given Hardware can be pre-computed + with a tool like STM32CubeMX or directly from I2C_TIMINGR register + description. - Because timing value is valid for a given I2C peripheral clock - frequency and target I2C bus clock, each timing value must be - provided with the matching configuration. + Because timing value is valid for a given I2C peripheral clock + frequency and target I2C bus clock, each timing value must be + provided with the matching configuration. - The resulting table entries should look like + The resulting table entries should look like - For example timings could be defined as + For example timings could be defined as - timings = <64000000 I2C_BITRATE_STANDARD 0x10707DBC>, - <64000000 I2C_BITRATE_FAST 0x00603D56>, - <56000000 I2C_BITRATE_STANDARD 0x10606DA4>, - <56000000 I2C_BITRATE_FAST 0x00501D63>; + timings = <64000000 I2C_BITRATE_STANDARD 0x10707DBC>, + <64000000 I2C_BITRATE_FAST 0x00603D56>, + <56000000 I2C_BITRATE_STANDARD 0x10606DA4>, + <56000000 I2C_BITRATE_FAST 0x00501D63>; diff --git a/dts/bindings/i2c/telink,b91-i2c.yaml b/dts/bindings/i2c/telink,b91-i2c.yaml index a0efe7f8ffc495..d0de9f93891e74 100644 --- a/dts/bindings/i2c/telink,b91-i2c.yaml +++ b/dts/bindings/i2c/telink,b91-i2c.yaml @@ -8,9 +8,9 @@ include: i2c-controller.yaml compatible: "telink,b91-i2c" properties: - reg: - required: true + reg: + required: true - pinctrl-0: - type: phandles - required: true + pinctrl-0: + type: phandles + required: true diff --git a/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml b/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml index df92ebe7318177..f9e55a09a779f2 100644 --- a/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml +++ b/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml @@ -8,8 +8,8 @@ compatible: "ti,cc13xx-cc26xx-i2c" include: [i2c-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/i2c/ti,cc32xx-i2c.yaml b/dts/bindings/i2c/ti,cc32xx-i2c.yaml index 00d6a8f489ee84..f76fb35a805c6e 100644 --- a/dts/bindings/i2c/ti,cc32xx-i2c.yaml +++ b/dts/bindings/i2c/ti,cc32xx-i2c.yaml @@ -5,8 +5,8 @@ compatible: "ti,cc32xx-i2c" include: i2c-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml b/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml index 7bd4f58acbc785..3352e29750b7b5 100644 --- a/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml +++ b/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml @@ -8,5 +8,5 @@ compatible: "zephyr,i2c-emul-controller" include: i2c-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/i2s/i2s-controller.yaml b/dts/bindings/i2s/i2s-controller.yaml index 280d12cf2fd2c4..b38465f2a97701 100644 --- a/dts/bindings/i2s/i2s-controller.yaml +++ b/dts/bindings/i2s/i2s-controller.yaml @@ -8,9 +8,9 @@ include: base.yaml bus: i2s properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - required: true - const: 0 + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 0 diff --git a/dts/bindings/i2s/i2s-device.yaml b/dts/bindings/i2s/i2s-device.yaml index cc554950c3bef4..d4cb0abb47ffd6 100644 --- a/dts/bindings/i2s/i2s-device.yaml +++ b/dts/bindings/i2s/i2s-device.yaml @@ -8,5 +8,5 @@ include: base.yaml on-bus: i2s properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/i2s/intel,cavs-i2s.yaml b/dts/bindings/i2s/intel,cavs-i2s.yaml index 3350704605c227..b38168770d6c02 100644 --- a/dts/bindings/i2s/intel,cavs-i2s.yaml +++ b/dts/bindings/i2s/intel,cavs-i2s.yaml @@ -9,17 +9,17 @@ compatible: "intel,cavs-i2s" include: [i2s-controller.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - interrupt-parent: - required: true + interrupt-parent: + required: true - dmas: - required: true + dmas: + required: true - dma-names: - required: true + dma-names: + required: true diff --git a/dts/bindings/i2s/intel,ssp-dai.yaml b/dts/bindings/i2s/intel,ssp-dai.yaml index c9f5424e93ecb6..83beeec081b806 100644 --- a/dts/bindings/i2s/intel,ssp-dai.yaml +++ b/dts/bindings/i2s/intel,ssp-dai.yaml @@ -9,17 +9,17 @@ compatible: "intel,ssp-dai" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - interrupt-parent: - required: true + interrupt-parent: + required: true - dmas: - required: true + dmas: + required: true - dma-names: - required: true + dma-names: + required: true diff --git a/dts/bindings/i2s/intel,ssp-sspbase.yaml b/dts/bindings/i2s/intel,ssp-sspbase.yaml index d829f3e7aba7c3..0a016441e3e07e 100644 --- a/dts/bindings/i2s/intel,ssp-sspbase.yaml +++ b/dts/bindings/i2s/intel,ssp-sspbase.yaml @@ -9,5 +9,5 @@ compatible: "intel,ssp-sspbase" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/i2s/litex,i2s.yaml b/dts/bindings/i2s/litex,i2s.yaml index 3d1bcbc6b3fb9a..9259e02250af42 100644 --- a/dts/bindings/i2s/litex,i2s.yaml +++ b/dts/bindings/i2s/litex,i2s.yaml @@ -10,9 +10,9 @@ compatible: "litex,i2s" include: i2s-controller.yaml properties: - reg: - required: true + reg: + required: true - fifo_depth: - type: int - required: true + fifo_depth: + type: int + required: true diff --git a/dts/bindings/i2s/nordic,nrf-i2s.yaml b/dts/bindings/i2s/nordic,nrf-i2s.yaml index d7ce52c4024cf6..836b35167ea97b 100644 --- a/dts/bindings/i2s/nordic,nrf-i2s.yaml +++ b/dts/bindings/i2s/nordic,nrf-i2s.yaml @@ -8,86 +8,86 @@ compatible: "nordic,nrf-i2s" include: [i2s-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - sck-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The SCK pin to use. - - For pins P0.0 through P0.31, use the pin number. For example, - to use P0.16 for SCK, set: - - sck-pin = <16>; - - For pins P1.0 through P1.31, add 32 to the pin number. For - example, to use P1.2 for SCK, set: - - sck-pin = <34>; /* 32 + 2 */ - - lrck-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The LRCK pin to use. The pin numbering scheme is the same as - the sck-pin property's. - - sdout-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The SDOUT pin to use. The pin numbering scheme is the same as - the sck-pin property's. - - sdin-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The SDIN pin to use. The pin numbering scheme is the same as - the sck-pin property's. - - mck-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The MCK pin to use. The pin numbering scheme is the same as - the sck-pin property's. - - clock-source: - type: string - default: "PCLK32M_HFXO" - description: | - Clock source to be used by the I2S peripheral for the master clock - (MCK) generator. The generator is only needed when the I2S peripheral - is operating in Master mode. The following options are available: - - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK - - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator - (HFXO) for better clock accuracy and jitter performance - - "ACLK": Audio PLL clock with configurable frequency (frequency for - this clock must be set via the "hfclkaudio-frequency" property - in the "nordic,nrf-clock" node); this clock source is only available - in the nRF53 Series SoCs and it requires the use of HFXO - enum: - - "PCLK32M" - - "PCLK32M_HFXO" - - "ACLK" + reg: + required: true + + interrupts: + required: true + + sck-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The SCK pin to use. + + For pins P0.0 through P0.31, use the pin number. For example, + to use P0.16 for SCK, set: + + sck-pin = <16>; + + For pins P1.0 through P1.31, add 32 to the pin number. For + example, to use P1.2 for SCK, set: + + sck-pin = <34>; /* 32 + 2 */ + + lrck-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The LRCK pin to use. The pin numbering scheme is the same as + the sck-pin property's. + + sdout-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The SDOUT pin to use. The pin numbering scheme is the same as + the sck-pin property's. + + sdin-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The SDIN pin to use. The pin numbering scheme is the same as + the sck-pin property's. + + mck-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The MCK pin to use. The pin numbering scheme is the same as + the sck-pin property's. + + clock-source: + type: string + default: "PCLK32M_HFXO" + description: | + Clock source to be used by the I2S peripheral for the master clock + (MCK) generator. The generator is only needed when the I2S peripheral + is operating in Master mode. The following options are available: + - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK + - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator + (HFXO) for better clock accuracy and jitter performance + - "ACLK": Audio PLL clock with configurable frequency (frequency for + this clock must be set via the "hfclkaudio-frequency" property + in the "nordic,nrf-clock" node); this clock source is only available + in the nRF53 Series SoCs and it requires the use of HFXO + enum: + - "PCLK32M" + - "PCLK32M_HFXO" + - "ACLK" diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml index c6307dc04faad1..a4eae452396a2d 100644 --- a/dts/bindings/i2s/nxp,mcux-i2s.yaml +++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml @@ -8,55 +8,55 @@ compatible: "nxp,mcux-i2s" include: [i2s-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - dma-names: - required: true - - nxp,tx-dma-channel: - type: int - required: true - description: tx dma channel number - - nxp,rx-dma-channel: - type: int - required: true - description: rx dma channel number - - nxp,tx-sync-mode: - type: boolean - description: tx sync mode - - nxp,rx-sync-mode: - type: boolean - description: rx sync mode - - pre-div: - type: int - description: pre divider - - podf: - type: int - description: post-divider fraction - - pll-clocks: - type: phandle-array - description: pll settings - specifier-space: pll-clock - - pll-clock-names: - type: string-array - description: Provided names of pll-clock specifiers - - pinmuxes: - type: phandle-array - specifier-space: pinmux - description: iomux settings - - nxp,tx-channel: - type: int - description: tx channel the maximum number is SOC dependent + reg: + required: true + + interrupts: + required: true + + dma-names: + required: true + + nxp,tx-dma-channel: + type: int + required: true + description: tx dma channel number + + nxp,rx-dma-channel: + type: int + required: true + description: rx dma channel number + + nxp,tx-sync-mode: + type: boolean + description: tx sync mode + + nxp,rx-sync-mode: + type: boolean + description: rx sync mode + + pre-div: + type: int + description: pre divider + + podf: + type: int + description: post-divider fraction + + pll-clocks: + type: phandle-array + description: pll settings + specifier-space: pll-clock + + pll-clock-names: + type: string-array + description: Provided names of pll-clock specifiers + + pinmuxes: + type: phandle-array + specifier-space: pinmux + description: iomux settings + + nxp,tx-channel: + type: int + description: tx channel the maximum number is SOC dependent diff --git a/dts/bindings/i2s/st,stm32-i2s.yaml b/dts/bindings/i2s/st,stm32-i2s.yaml index d66a6c8d438abc..4deb6bfd54321d 100644 --- a/dts/bindings/i2s/st,stm32-i2s.yaml +++ b/dts/bindings/i2s/st,stm32-i2s.yaml @@ -8,20 +8,20 @@ compatible: "st,stm32-i2s" include: [i2s-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - dmas: - required: true + dmas: + required: true - dma-names: - required: true + dma-names: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/i3c/cdns,i3c.yaml b/dts/bindings/i3c/cdns,i3c.yaml index 3d51b258f095f7..954af09d63df64 100644 --- a/dts/bindings/i3c/cdns,i3c.yaml +++ b/dts/bindings/i3c/cdns,i3c.yaml @@ -9,13 +9,13 @@ compatible: "cdns,i3c" include: [i3c-controller.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - input-clock-frequency: - type: int - required: true - description: The controller input clock frequency + input-clock-frequency: + type: int + required: true + description: The controller input clock frequency diff --git a/dts/bindings/i3c/i3c-controller.yaml b/dts/bindings/i3c/i3c-controller.yaml index 53f294dc812ab1..50472604b5ea47 100644 --- a/dts/bindings/i3c/i3c-controller.yaml +++ b/dts/bindings/i3c/i3c-controller.yaml @@ -9,24 +9,24 @@ include: base.yaml bus: [i3c, i2c] properties: - "#address-cells": - required: true - const: 3 + "#address-cells": + required: true + const: 3 - "#size-cells": - required: true - const: 0 + "#size-cells": + required: true + const: 0 - i3c-scl-hz: - type: int - description: | - Frequency of the SCL signal used for I3C transfers. When undefined, - use the controller default or as specified by the I3C specification. + i3c-scl-hz: + type: int + description: | + Frequency of the SCL signal used for I3C transfers. When undefined, + use the controller default or as specified by the I3C specification. - i2c-scl-hz: - type: int - description: | - Frequency of the SCL signal used for I2C transfers. When undefined - and there are I2C devices attached to the bus, look at the Legacy - Virtual Register (LVR) of all connected I2C devices to determine - the maximum allowed frequency. + i2c-scl-hz: + type: int + description: | + Frequency of the SCL signal used for I2C transfers. When undefined + and there are I2C devices attached to the bus, look at the Legacy + Virtual Register (LVR) of all connected I2C devices to determine + the maximum allowed frequency. diff --git a/dts/bindings/i3c/i3c-device.yaml b/dts/bindings/i3c/i3c-device.yaml index a4ce423841e6f5..48a0bd01e71f25 100644 --- a/dts/bindings/i3c/i3c-device.yaml +++ b/dts/bindings/i3c/i3c-device.yaml @@ -8,56 +8,56 @@ include: [base.yaml, power.yaml] on-bus: i3c properties: - reg: - required: true - description: | - Contains 3 fields. - - For I3C devices, the 3 fields are static address, first half - of Provisioned ID, and the second half of the Provisioned ID. - 1. The static address can be assigned to be the target device's - dynamic address before Dynamic Address Assignment (DAA) - starts. Can be zero if static address is not used, and - target address is determined via DAA. - 2. First half of the Provisioned ID contains the manufacturer - ID left-shifted by 1, where the manufacturer ID is - the bits 33-47 (zero-based) of the 48-bit Provisioned ID. - 3. Second half of the Provisioned ID contains the combination of - the part ID (bits 16-31 of the Provisioned ID) left-shifted - by 16, and the instance ID (bits 12-15 of the Provisioned ID) - left-shifted by 12. Basically, this is the lower 32 bits - of the Provisioned ID. - - Note that the DT node of a I3C target device should be in format - "@
", e.g. "sensor@4200001234012345678", - where the PID part is expanded to be a 64-bit integer. - - For I2C devices, the 3 fields are static address, 0x00, and - value of the Legacy Virtual Register (LVR). - 1. 7-bit address of the I2C device. (Note that 10-bit - addressing is not supported.) - 2. Always 0x00. - 3. LVR describes the I2C device where, - * bit[31:8]: unused. - * bit[7:5]: I2C device index: - * Index 0: I2C device has a 50 ns spike filter where - it is not affected by high frequency on SCL. - * Index 1: I2C device does not have a 50 ns spike filter - but can work with high frequency on SCL. - * Index 2: I2C device does not have a 50 ns spike filter - and cannot work with high frequency on SCL. - * Other values are reserved. - * bit[4]: I2C mode indicator: - * 0: FM+ mode - * 1: FM mode - * bit[3:0]: reserved. - - The DT node of a I2C device should be in format - "@
", - e.g. "sensor@5000000000000000FF", where the middle 0x00 and LVR - are both expanded to 32-bit integers. - - assigned-address: - type: int - description: | - Dynamic address to be assigned to the device. + reg: + required: true + description: | + Contains 3 fields. + + For I3C devices, the 3 fields are static address, first half + of Provisioned ID, and the second half of the Provisioned ID. + 1. The static address can be assigned to be the target device's + dynamic address before Dynamic Address Assignment (DAA) + starts. Can be zero if static address is not used, and + target address is determined via DAA. + 2. First half of the Provisioned ID contains the manufacturer + ID left-shifted by 1, where the manufacturer ID is + the bits 33-47 (zero-based) of the 48-bit Provisioned ID. + 3. Second half of the Provisioned ID contains the combination of + the part ID (bits 16-31 of the Provisioned ID) left-shifted + by 16, and the instance ID (bits 12-15 of the Provisioned ID) + left-shifted by 12. Basically, this is the lower 32 bits + of the Provisioned ID. + + Note that the DT node of a I3C target device should be in format + "@
", e.g. "sensor@4200001234012345678", + where the PID part is expanded to be a 64-bit integer. + + For I2C devices, the 3 fields are static address, 0x00, and + value of the Legacy Virtual Register (LVR). + 1. 7-bit address of the I2C device. (Note that 10-bit + addressing is not supported.) + 2. Always 0x00. + 3. LVR describes the I2C device where, + * bit[31:8]: unused. + * bit[7:5]: I2C device index: + * Index 0: I2C device has a 50 ns spike filter where + it is not affected by high frequency on SCL. + * Index 1: I2C device does not have a 50 ns spike filter + but can work with high frequency on SCL. + * Index 2: I2C device does not have a 50 ns spike filter + and cannot work with high frequency on SCL. + * Other values are reserved. + * bit[4]: I2C mode indicator: + * 0: FM+ mode + * 1: FM mode + * bit[3:0]: reserved. + + The DT node of a I2C device should be in format + "@
", + e.g. "sensor@5000000000000000FF", where the middle 0x00 and LVR + are both expanded to 32-bit integers. + + assigned-address: + type: int + description: | + Dynamic address to be assigned to the device. diff --git a/dts/bindings/i3c/nxp,mcux-i3c.yaml b/dts/bindings/i3c/nxp,mcux-i3c.yaml index be8f4e8ad61e8b..a31d61d6a85c5e 100644 --- a/dts/bindings/i3c/nxp,mcux-i3c.yaml +++ b/dts/bindings/i3c/nxp,mcux-i3c.yaml @@ -10,29 +10,29 @@ compatible: "nxp,mcux-i3c" include: [i3c-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - i3c-od-scl-hz: - type: int - description: | - Open Drain Frequency for the I3C controller. When undefined, use - the controller default or as specified by the I3C specification. - - clk-divider: - type: int - description: Main clock divider for I3C - required: true - - clk-divider-tc: - type: int - description: TC clock divider for I3C - required: true - - clk-divider-slow: - type: int - description: Slow clock divider for I3C - required: true + reg: + required: true + + interrupts: + required: true + + i3c-od-scl-hz: + type: int + description: | + Open Drain Frequency for the I3C controller. When undefined, use + the controller default or as specified by the I3C specification. + + clk-divider: + type: int + description: Main clock divider for I3C + required: true + + clk-divider-tc: + type: int + description: TC clock divider for I3C + required: true + + clk-divider-slow: + type: int + description: Slow clock divider for I3C + required: true diff --git a/dts/bindings/ieee802154/atmel,rf2xx.yaml b/dts/bindings/ieee802154/atmel,rf2xx.yaml index 5283402e7af658..7d87ac4e723125 100644 --- a/dts/bindings/ieee802154/atmel,rf2xx.yaml +++ b/dts/bindings/ieee802154/atmel,rf2xx.yaml @@ -8,120 +8,120 @@ compatible: "atmel,rf2xx" include: spi-device.yaml properties: - irq-gpios: - type: phandle-array - required: true - - reset-gpios: - type: phandle-array - required: true - - slptr-gpios: - type: phandle-array - required: true - description: | - Multi-functional pin that controls sleep, deep sleep, transmit - start and receive states - - dig2-gpios: - type: phandle-array - description: RX and TX Frame Time Stamping(TX_ARET) - - clkm-gpios: - type: phandle-array - description: Master clock signal output - - local-mac-address: - type: uint8-array - description: | - Specifies the MAC address that was assigned to the network - device - - channel-page: - type: int - enum: - - 0 - - 2 - - 5 - description: | - Selects Channel Page accordingly with IEEE 802.15.4 standard. The Page 0 - is used in both Sub-Giga and 2.4GHz. It allows select channels 0-10 in - Sub-Giga band (0: BPSK-20, 1-10: BPSK-40) and 11-26 in 2.4GHz band - (11-26: O-QPSK-250). Channel 2 is for Sub-Giga and selects - (0: OQPSK-SIN-RC-100, 1-10: OQPSK-SIN-250). Channel 5 is for Sub-Giga - (JAPAN) and selects (0-3: OQPSK-RC-250) . - 0: Page 0 - BPSK-20 [0], BPSK-40 [1-10], O-QPSK-250 [11-26]. - 2: Page 2 - OQPSK-SIN-RC-100 [0], OQPSK-SIN-250 [1-10]. - 5: Page 5 - OQPSK-RC-250 [0-3]. - - tx-pwr-table: - type: uint8-array - default: [0x00] - description: | - This is the Transmission Power Mapping Table array used to comply with - local regulations. By default this value set an output power above 0dBm - for all transceivers. This property must be used with tx-pwr-min and - tx-pwr-max for normal operations. The number of elements is defined by - the size of the tx-pwr-table array property. The max entry value for - 2.4GHz is 0x0f and 0xff for Sub-Giga. See PHY_TX_PWR at datasheet for - more details. - - The output power is determined by following formula: - - linear_step = (tx-pwr-max - tx-pwr-min) - / (sizeof(tx-pwr-table) - 1.0); - table_index = abs((value_in_dbm - tx-pwr-max) / linear_step); - output_power = tx-pwr-table[table_index]; - - Using AT86RF233 as example without external PA. By the datasheet the - tx-pwr-min = -17 dBm and tx-pwr-max = +4 dBm. Using 48 elements in the - tx-pwr-table array. The table array is filled from higher to lower power. - - tx-pwr-min = [01 11]; /* -17.0 dBm */ - tx-pwr-max = [00 04]; /* 4.0 dBm */ - tx-pwr-table = [00 01 03 04 05 05 06 06 - 07 07 07 08 08 09 09 0a - 0a 0a 0b 0b 0b 0b 0c 0c - 0c 0c 0d 0d 0d 0d 0d 0d - 0d 0d 0e 0e 0e 0e 0e 0e - 0e 0e 0e 0e 0e 0e 0f 0f]; - - The values in the table are filled based on table 9-9 [TX Output Power] - using the linear step in dBm as: - - linear_step = (4 - (-17)) / (48 - 1) => ~0.45 dBm - - Assuming that user wants set 0 dBm as output power: - - table_index = abs((0 - 4) / 0.45) => 8.95 ( round to 9 ) - output_power = tx-pwr-table[9] => 0x07 ( 0 dBm as table 9-9 ) - - Note when tx-pwr-min is [0x00, 0x00] and tx-pwr-max is [0x00, 0x00] - the linear step is zero. This means that table_index will be always the - first element of the tx-pwr-table array, which is 0x00 by default. This - is defined as general case when user not define any tx-pwr-* entries. It - sets the transceiver to use always a value above 0 dBm as output power. - - tx-pwr-min: - type: uint8-array - default: [0x00, 0x00] - description: | - This value represent minimum normalized value in dBm for the transceiver - output power. This property must be used when tx-pwr-table is defined. - The value is represented by two entries where first element represents - the signal indication [0x00-positive, 0x01-negative] and second element - is the minimal value in dBm for the transceiver output power. By default, - the combination of tx-pwr-min as [0x00, 0x00] and tx-pwr-max as [0x00, - 0x00] will create a fixed transmission power. - - tx-pwr-max: - type: uint8-array - default: [0x00, 0x00] - description: | - This value represent maximum normalized value in dBm for the transceiver - output power. This property must be used when tx-pwr-table is defined. - The value is represented by two entries where first element represents - the signal indication [ 0x00-positive] and second element is the maximum - value in dBm for the transceiver output power. By default, the - combination of tx-pwr-max as [0x00, 0x00] and tx-pwr-min as [0x00, - 0x00] will create a fixed transmission power. + irq-gpios: + type: phandle-array + required: true + + reset-gpios: + type: phandle-array + required: true + + slptr-gpios: + type: phandle-array + required: true + description: | + Multi-functional pin that controls sleep, deep sleep, transmit + start and receive states + + dig2-gpios: + type: phandle-array + description: RX and TX Frame Time Stamping(TX_ARET) + + clkm-gpios: + type: phandle-array + description: Master clock signal output + + local-mac-address: + type: uint8-array + description: | + Specifies the MAC address that was assigned to the network + device + + channel-page: + type: int + enum: + - 0 + - 2 + - 5 + description: | + Selects Channel Page accordingly with IEEE 802.15.4 standard. The Page 0 + is used in both Sub-Giga and 2.4GHz. It allows select channels 0-10 in + Sub-Giga band (0: BPSK-20, 1-10: BPSK-40) and 11-26 in 2.4GHz band + (11-26: O-QPSK-250). Channel 2 is for Sub-Giga and selects + (0: OQPSK-SIN-RC-100, 1-10: OQPSK-SIN-250). Channel 5 is for Sub-Giga + (JAPAN) and selects (0-3: OQPSK-RC-250) . + 0: Page 0 - BPSK-20 [0], BPSK-40 [1-10], O-QPSK-250 [11-26]. + 2: Page 2 - OQPSK-SIN-RC-100 [0], OQPSK-SIN-250 [1-10]. + 5: Page 5 - OQPSK-RC-250 [0-3]. + + tx-pwr-table: + type: uint8-array + default: [0x00] + description: | + This is the Transmission Power Mapping Table array used to comply with + local regulations. By default this value set an output power above 0dBm + for all transceivers. This property must be used with tx-pwr-min and + tx-pwr-max for normal operations. The number of elements is defined by + the size of the tx-pwr-table array property. The max entry value for + 2.4GHz is 0x0f and 0xff for Sub-Giga. See PHY_TX_PWR at datasheet for + more details. + + The output power is determined by following formula: + + linear_step = (tx-pwr-max - tx-pwr-min) + / (sizeof(tx-pwr-table) - 1.0); + table_index = abs((value_in_dbm - tx-pwr-max) / linear_step); + output_power = tx-pwr-table[table_index]; + + Using AT86RF233 as example without external PA. By the datasheet the + tx-pwr-min = -17 dBm and tx-pwr-max = +4 dBm. Using 48 elements in the + tx-pwr-table array. The table array is filled from higher to lower power. + + tx-pwr-min = [01 11]; /* -17.0 dBm */ + tx-pwr-max = [00 04]; /* 4.0 dBm */ + tx-pwr-table = [00 01 03 04 05 05 06 06 + 07 07 07 08 08 09 09 0a + 0a 0a 0b 0b 0b 0b 0c 0c + 0c 0c 0d 0d 0d 0d 0d 0d + 0d 0d 0e 0e 0e 0e 0e 0e + 0e 0e 0e 0e 0e 0e 0f 0f]; + + The values in the table are filled based on table 9-9 [TX Output Power] + using the linear step in dBm as: + + linear_step = (4 - (-17)) / (48 - 1) => ~0.45 dBm + + Assuming that user wants set 0 dBm as output power: + + table_index = abs((0 - 4) / 0.45) => 8.95 ( round to 9 ) + output_power = tx-pwr-table[9] => 0x07 ( 0 dBm as table 9-9 ) + + Note when tx-pwr-min is [0x00, 0x00] and tx-pwr-max is [0x00, 0x00] + the linear step is zero. This means that table_index will be always the + first element of the tx-pwr-table array, which is 0x00 by default. This + is defined as general case when user not define any tx-pwr-* entries. It + sets the transceiver to use always a value above 0 dBm as output power. + + tx-pwr-min: + type: uint8-array + default: [0x00, 0x00] + description: | + This value represent minimum normalized value in dBm for the transceiver + output power. This property must be used when tx-pwr-table is defined. + The value is represented by two entries where first element represents + the signal indication [0x00-positive, 0x01-negative] and second element + is the minimal value in dBm for the transceiver output power. By default, + the combination of tx-pwr-min as [0x00, 0x00] and tx-pwr-max as [0x00, + 0x00] will create a fixed transmission power. + + tx-pwr-max: + type: uint8-array + default: [0x00, 0x00] + description: | + This value represent maximum normalized value in dBm for the transceiver + output power. This property must be used when tx-pwr-table is defined. + The value is represented by two entries where first element represents + the signal indication [ 0x00-positive] and second element is the maximum + value in dBm for the transceiver output power. By default, the + combination of tx-pwr-max as [0x00, 0x00] and tx-pwr-min as [0x00, + 0x00] will create a fixed transmission power. diff --git a/dts/bindings/ieee802154/decawave,dw1000.yaml b/dts/bindings/ieee802154/decawave,dw1000.yaml index 847f61b75d88df..d43f5dbef71557 100644 --- a/dts/bindings/ieee802154/decawave,dw1000.yaml +++ b/dts/bindings/ieee802154/decawave,dw1000.yaml @@ -8,28 +8,28 @@ compatible: "decawave,dw1000" include: spi-device.yaml properties: - int-gpios: - type: phandle-array - required: true - description: Interrupt pin. - - The interrupt pin IRQ of DW1000 is active high output. - If connected directly the MCU pin should be configured - as active high. - - reset-gpios: - type: phandle-array - required: true - description: RESET pin. - - The RESET pin of DW1000 is active low. - If connected directly the MCU pin should be configured - as active low. - - tx-ant-delay: - type: int - description: Transmitter antenna delay. - - rx-ant-delay: - type: int - description: Receiver antenna delay. + int-gpios: + type: phandle-array + required: true + description: Interrupt pin. + + The interrupt pin IRQ of DW1000 is active high output. + If connected directly the MCU pin should be configured + as active high. + + reset-gpios: + type: phandle-array + required: true + description: RESET pin. + + The RESET pin of DW1000 is active low. + If connected directly the MCU pin should be configured + as active low. + + tx-ant-delay: + type: int + description: Transmitter antenna delay. + + rx-ant-delay: + type: int + description: Receiver antenna delay. diff --git a/dts/bindings/ieee802154/nxp,mcr20a.yaml b/dts/bindings/ieee802154/nxp,mcr20a.yaml index b7f9f63776f3b1..ae0467d7cb7fec 100644 --- a/dts/bindings/ieee802154/nxp,mcr20a.yaml +++ b/dts/bindings/ieee802154/nxp,mcr20a.yaml @@ -8,20 +8,20 @@ compatible: "nxp,mcr20a" include: spi-device.yaml properties: - irqb-gpios: - type: phandle-array - required: true - description: Interrupt pin. + irqb-gpios: + type: phandle-array + required: true + description: Interrupt pin. - The interrupt pin of MCR20A is open-drain, active low. - If connected directly the MCU pin should be configured - as pull-up, active low. + The interrupt pin of MCR20A is open-drain, active low. + If connected directly the MCU pin should be configured + as pull-up, active low. - reset-gpios: - type: phandle-array - required: true - description: RESET pin. + reset-gpios: + type: phandle-array + required: true + description: RESET pin. - The RESET pin of MCR20A is active low. - If connected directly the MCU pin should be configured - as active low. + The RESET pin of MCR20A is active low. + If connected directly the MCU pin should be configured + as active low. diff --git a/dts/bindings/ieee802154/telink,b91-zb.yaml b/dts/bindings/ieee802154/telink,b91-zb.yaml index f7cb7f10e39402..879f019b14a5fb 100644 --- a/dts/bindings/ieee802154/telink,b91-zb.yaml +++ b/dts/bindings/ieee802154/telink,b91-zb.yaml @@ -8,8 +8,8 @@ compatible: "telink,b91-zb" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/ieee802154/ti,cc1200.yaml b/dts/bindings/ieee802154/ti,cc1200.yaml index 492d82dda398cb..68682196f66cdc 100644 --- a/dts/bindings/ieee802154/ti,cc1200.yaml +++ b/dts/bindings/ieee802154/ti,cc1200.yaml @@ -8,6 +8,6 @@ compatible: "ti,cc1200" include: spi-device.yaml properties: - int-gpios: - type: phandle-array - required: true + int-gpios: + type: phandle-array + required: true diff --git a/dts/bindings/ieee802154/ti,cc2520.yaml b/dts/bindings/ieee802154/ti,cc2520.yaml index c310add544df6e..614e9c71551ee2 100644 --- a/dts/bindings/ieee802154/ti,cc2520.yaml +++ b/dts/bindings/ieee802154/ti,cc2520.yaml @@ -8,26 +8,26 @@ compatible: "ti,cc2520" include: spi-device.yaml properties: - vreg-en-gpios: - type: phandle-array - required: true + vreg-en-gpios: + type: phandle-array + required: true - reset-gpios: - type: phandle-array - required: true + reset-gpios: + type: phandle-array + required: true - fifo-gpios: - type: phandle-array - required: true + fifo-gpios: + type: phandle-array + required: true - cca-gpios: - type: phandle-array - required: true + cca-gpios: + type: phandle-array + required: true - sfd-gpios: - type: phandle-array - required: true + sfd-gpios: + type: phandle-array + required: true - fifop-gpios: - type: phandle-array - required: true + fifop-gpios: + type: phandle-array + required: true diff --git a/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml b/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml index 17414926b2e36b..78701bdc81a949 100644 --- a/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml +++ b/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml @@ -8,26 +8,26 @@ compatible: "nuvoton,npcx-adc" include: [adc-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - clocks: - required: true - pinctrl-0: - required: true - pinctrl-names: - required: true - channel-count: - type: int - required: true - description: the number of ADC channels - threshold-reg-offset: - type: int - required: true - description: the offset of threshold detector register address - threshold-count: - type: int - required: true - description: the number of threshold detectors adc supports + reg: + required: true + clocks: + required: true + pinctrl-0: + required: true + pinctrl-names: + required: true + channel-count: + type: int + required: true + description: the number of ADC channels + threshold-reg-offset: + type: int + required: true + description: the offset of threshold detector register address + threshold-count: + type: int + required: true + description: the number of threshold detectors adc supports io-channel-cells: - - input + - input diff --git a/dts/bindings/iio/adc/nxp,lpc-lpadc.yaml b/dts/bindings/iio/adc/nxp,lpc-lpadc.yaml index adf4b27d69af4b..e682afb455c633 100644 --- a/dts/bindings/iio/adc/nxp,lpc-lpadc.yaml +++ b/dts/bindings/iio/adc/nxp,lpc-lpadc.yaml @@ -8,49 +8,49 @@ compatible: "nxp,lpc-lpadc" include: [adc-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - clk-divider: - type: int - required: true - description: clock divider for the converter - - clk-source: - type: int - required: true - description: source to attach the ADC clock to - - voltage-ref: - type: int - required: true - description: reference voltage source - - calibration-average: - type: int - required: true - description: conversion average number for auto-calibration - - power-level: - type: int - required: true - description: power level for the ADC - - offset-value-a: - type: int - required: true - description: Offset value A to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false - - offset-value-b: - type: int - required: true - description: Offset value B to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false - - "#io-channel-cells": - const: 1 + reg: + required: true + + interrupts: + required: true + + clk-divider: + type: int + required: true + description: clock divider for the converter + + clk-source: + type: int + required: true + description: source to attach the ADC clock to + + voltage-ref: + type: int + required: true + description: reference voltage source + + calibration-average: + type: int + required: true + description: conversion average number for auto-calibration + + power-level: + type: int + required: true + description: power level for the ADC + + offset-value-a: + type: int + required: true + description: Offset value A to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false + + offset-value-b: + type: int + required: true + description: Offset value B to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false + + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/input/gpio-keys.yaml b/dts/bindings/input/gpio-keys.yaml index dbd76d4741258e..bbf08d95212e0d 100644 --- a/dts/bindings/input/gpio-keys.yaml +++ b/dts/bindings/input/gpio-keys.yaml @@ -8,23 +8,23 @@ compatible: "gpio-keys" include: base.yaml properties: - debounce-interval-ms: - type: int - default: 30 - description: | - Debouncing interval time in milliseconds. - If not specified defaults to 30. + debounce-interval-ms: + type: int + default: 30 + description: | + Debouncing interval time in milliseconds. + If not specified defaults to 30. child-binding: - description: GPIO KEYS child node - properties: - gpios: - type: phandle-array - required: true - label: - type: string - description: Descriptive name of the key - zephyr,code: - type: int - default: 0 - description: Key / Axis code to emit. + description: GPIO KEYS child node + properties: + gpios: + type: phandle-array + required: true + label: + type: string + description: Descriptive name of the key + zephyr,code: + type: int + default: 0 + description: Key / Axis code to emit. diff --git a/dts/bindings/interrupt-controller/arm,gic-v3-its.yaml b/dts/bindings/interrupt-controller/arm,gic-v3-its.yaml index 45f34c7c23ea1a..ba72d32b9a040d 100644 --- a/dts/bindings/interrupt-controller/arm,gic-v3-its.yaml +++ b/dts/bindings/interrupt-controller/arm,gic-v3-its.yaml @@ -8,5 +8,5 @@ compatible: "arm,gic-v3-its" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/interrupt-controller/arm,gic.yaml b/dts/bindings/interrupt-controller/arm,gic.yaml index a7f70b40d2b720..5dae97f34219ca 100644 --- a/dts/bindings/interrupt-controller/arm,gic.yaml +++ b/dts/bindings/interrupt-controller/arm,gic.yaml @@ -8,8 +8,8 @@ compatible: "arm,gic" include: base.yaml properties: - reg: - required: true + reg: + required: true interrupt-cells: - type diff --git a/dts/bindings/interrupt-controller/arm,v6m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v6m-nvic.yaml index 1fc581fa1af302..73f1fcdccee9b4 100644 --- a/dts/bindings/interrupt-controller/arm,v6m-nvic.yaml +++ b/dts/bindings/interrupt-controller/arm,v6m-nvic.yaml @@ -5,16 +5,16 @@ compatible: "arm,v6m-nvic" include: [interrupt-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - arm,num-irq-priority-bits: - required: true - type: int - description: number of bits of IRQ priorities + arm,num-irq-priority-bits: + required: true + type: int + description: number of bits of IRQ priorities - "#interrupt-cells": - const: 2 + "#interrupt-cells": + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml index 43847c442054a7..8fa04f48d1a1f3 100644 --- a/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml +++ b/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml @@ -5,16 +5,16 @@ compatible: "arm,v7m-nvic" include: [interrupt-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - arm,num-irq-priority-bits: - required: true - type: int - description: number of bits of IRQ priorities + arm,num-irq-priority-bits: + required: true + type: int + description: number of bits of IRQ priorities - "#interrupt-cells": - const: 2 + "#interrupt-cells": + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml index cb1e26e742992c..8ebb8af9d9f376 100644 --- a/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml +++ b/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml @@ -5,16 +5,16 @@ compatible: "arm,v8.1m-nvic" include: [interrupt-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - arm,num-irq-priority-bits: - required: true - type: int - description: number of bits of IRQ priorities + arm,num-irq-priority-bits: + required: true + type: int + description: number of bits of IRQ priorities - "#interrupt-cells": - const: 2 + "#interrupt-cells": + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml index 6aadc1b687008e..9c69bfb20439e2 100644 --- a/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml +++ b/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml @@ -5,16 +5,16 @@ compatible: "arm,v8m-nvic" include: [interrupt-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - arm,num-irq-priority-bits: - required: true - type: int - description: number of bits of IRQ priorities + arm,num-irq-priority-bits: + required: true + type: int + description: number of bits of IRQ priorities - "#interrupt-cells": - const: 2 + "#interrupt-cells": + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/cdns,xtensa-core-intc.yaml b/dts/bindings/interrupt-controller/cdns,xtensa-core-intc.yaml index 5c52526218dc28..cc755dbef93683 100644 --- a/dts/bindings/interrupt-controller/cdns,xtensa-core-intc.yaml +++ b/dts/bindings/interrupt-controller/cdns,xtensa-core-intc.yaml @@ -6,10 +6,10 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true "#interrupt-cells": - const: 3 + const: 3 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/cypress,psoc6-intmux-ch.yaml b/dts/bindings/interrupt-controller/cypress,psoc6-intmux-ch.yaml index 5e02a63091ea5e..96030436ef2618 100644 --- a/dts/bindings/interrupt-controller/cypress,psoc6-intmux-ch.yaml +++ b/dts/bindings/interrupt-controller/cypress,psoc6-intmux-ch.yaml @@ -13,10 +13,10 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true interrupts: - required: true + required: true interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml b/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml index 3cee72721a527b..982d7b4aa089e6 100644 --- a/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml +++ b/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml @@ -73,4 +73,4 @@ include: base.yaml properties: reg: - required: true + required: true diff --git a/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml b/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml index 60561db1bcba8a..f8c651e707cbf1 100644 --- a/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml +++ b/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml @@ -8,7 +8,7 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/gaisler,irqmp.yaml b/dts/bindings/interrupt-controller/gaisler,irqmp.yaml index b5734c9a046d1e..a5ff4014b057a3 100644 --- a/dts/bindings/interrupt-controller/gaisler,irqmp.yaml +++ b/dts/bindings/interrupt-controller/gaisler,irqmp.yaml @@ -8,15 +8,15 @@ compatible: "gaisler,irqmp" include: [interrupt-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - eirq: - type: int - description: Extended interrupt number (or 0 for none) + eirq: + type: int + description: Extended interrupt number (or 0 for none) - "#interrupt-cells": - const: 1 + "#interrupt-cells": + const: 1 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/intel,ace-intc.yaml b/dts/bindings/interrupt-controller/intel,ace-intc.yaml index 276526ce40741e..8de6b206b76529 100644 --- a/dts/bindings/interrupt-controller/intel,ace-intc.yaml +++ b/dts/bindings/interrupt-controller/intel,ace-intc.yaml @@ -6,18 +6,18 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true interrupts: - required: true + required: true "#interrupt-cells": - const: 3 + const: 3 num-irqs: - type: int - required: true - description: Number of irq the controller manages + type: int + required: true + description: Number of irq the controller manages interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/intel,cavs-intc.yaml b/dts/bindings/interrupt-controller/intel,cavs-intc.yaml index 5424a0b8ea6eb0..e51976bef2b7d1 100644 --- a/dts/bindings/interrupt-controller/intel,cavs-intc.yaml +++ b/dts/bindings/interrupt-controller/intel,cavs-intc.yaml @@ -6,13 +6,13 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true interrupts: - required: true + required: true "#interrupt-cells": - const: 3 + const: 3 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/intel,ioapic.yaml b/dts/bindings/interrupt-controller/intel,ioapic.yaml index 3d8f9fb67930ea..d7d3226c741fe9 100644 --- a/dts/bindings/interrupt-controller/intel,ioapic.yaml +++ b/dts/bindings/interrupt-controller/intel,ioapic.yaml @@ -6,10 +6,10 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true "#interrupt-cells": - const: 3 + const: 3 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/intel,vt-d.yaml b/dts/bindings/interrupt-controller/intel,vt-d.yaml index 97fae0ef756975..cfd36283dbc568 100644 --- a/dts/bindings/interrupt-controller/intel,vt-d.yaml +++ b/dts/bindings/interrupt-controller/intel,vt-d.yaml @@ -8,5 +8,5 @@ compatible: "intel,vt-d" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/interrupt-controller/interrupt-controller.yaml b/dts/bindings/interrupt-controller/interrupt-controller.yaml index 93e1a433beb576..37a2869aec38ad 100644 --- a/dts/bindings/interrupt-controller/interrupt-controller.yaml +++ b/dts/bindings/interrupt-controller/interrupt-controller.yaml @@ -4,11 +4,11 @@ # Common fields for interrupt controllers properties: - "interrupt-controller": - type: boolean - required: true - description: Convey's this node is an interrupt controller - "#interrupt-cells": - type: int - required: true - description: Number of items to expect in an interrupt specifier + "interrupt-controller": + type: boolean + required: true + description: Convey's this node is an interrupt controller + "#interrupt-cells": + type: int + required: true + description: Number of items to expect in an interrupt specifier diff --git a/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml b/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml index 54c932d8931ac9..dc61d5dc20769c 100644 --- a/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml +++ b/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml @@ -8,7 +8,7 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/ite,it8xxx2-wuc-map.yaml b/dts/bindings/interrupt-controller/ite,it8xxx2-wuc-map.yaml index 6f0e8ae4357496..e657b56bd7cbd0 100644 --- a/dts/bindings/interrupt-controller/ite,it8xxx2-wuc-map.yaml +++ b/dts/bindings/interrupt-controller/ite,it8xxx2-wuc-map.yaml @@ -6,8 +6,8 @@ description: ITE Wake-Up Controller (WUC) mapping child node compatible: "ite,it8xxx2-wuc-map" child-binding: - description: Child node to present the mapping between input of WUC and its source device - properties: - wucs: - type: phandle-array - required: true + description: Child node to present the mapping between input of WUC and its source device + properties: + wucs: + type: phandle-array + required: true diff --git a/dts/bindings/interrupt-controller/microchip,xec-ecia-girq.yaml b/dts/bindings/interrupt-controller/microchip,xec-ecia-girq.yaml index fcd28162f6115c..dd2c844e5b518f 100644 --- a/dts/bindings/interrupt-controller/microchip,xec-ecia-girq.yaml +++ b/dts/bindings/interrupt-controller/microchip,xec-ecia-girq.yaml @@ -5,19 +5,19 @@ compatible: "microchip,xec-ecia-girq" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - girq-id: - type: int - required: true - description: GIRQ ID number [0, 18] + girq-id: + type: int + required: true + description: GIRQ ID number [0, 18] - sources: - type: array - required: true - description: | - Bit positions of each source implemented by this GIRQ. + sources: + type: array + required: true + description: | + Bit positions of each source implemented by this GIRQ. diff --git a/dts/bindings/interrupt-controller/microchip,xec-ecia.yaml b/dts/bindings/interrupt-controller/microchip,xec-ecia.yaml index 11a688b2b7544b..97c9c4a3dc1f36 100644 --- a/dts/bindings/interrupt-controller/microchip,xec-ecia.yaml +++ b/dts/bindings/interrupt-controller/microchip,xec-ecia.yaml @@ -5,15 +5,15 @@ compatible: "microchip,xec-ecia" include: base.yaml properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - direct-capable-girqs: - type: array - required: true - description: | - Array of GIRQ numbers in [8, 26] whose result bits can be connected - directly to the ARM NVIC. + direct-capable-girqs: + type: array + required: true + description: | + Array of GIRQ numbers in [8, 26] whose result bits can be connected + directly to the ARM NVIC. diff --git a/dts/bindings/interrupt-controller/mti,cpu-intc.yaml b/dts/bindings/interrupt-controller/mti,cpu-intc.yaml index f7192ebed0d20d..2972c4c80228c9 100644 --- a/dts/bindings/interrupt-controller/mti,cpu-intc.yaml +++ b/dts/bindings/interrupt-controller/mti,cpu-intc.yaml @@ -10,7 +10,7 @@ include: [interrupt-controller.yaml, base.yaml] properties: "#interrupt-cells": - const: 1 + const: 1 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/nuclei,eclic.yaml b/dts/bindings/interrupt-controller/nuclei,eclic.yaml index 47aee3157dfc1b..4353f7e38d1748 100644 --- a/dts/bindings/interrupt-controller/nuclei,eclic.yaml +++ b/dts/bindings/interrupt-controller/nuclei,eclic.yaml @@ -9,10 +9,10 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true "#interrupt-cells": - const: 2 + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-int-map.yaml b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-int-map.yaml index 4c070c36162012..c2d5a096af286c 100644 --- a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-int-map.yaml +++ b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-int-map.yaml @@ -6,26 +6,26 @@ description: NPCX-MIWU group-interrupt mapping child node compatible: "nuvoton,npcx-miwu-int-map" properties: - parent: - type: phandle - required: true - description: parent device node of miwu groups + parent: + type: phandle + required: true + description: parent device node of miwu groups child-binding: - description: Child node to present the mapping between MIWU group and interrupt - properties: - irq: - type: int - required: true - description: irq for miwu group - irq-prio: - type: int - required: true - description: irq's priority for miwu group. The valid number is from 0 to 7. - group-mask: - type: int - required: true - description: group bit-mask for miwu interrupts - groups: - type: array - description: groups shared the same interrupt + description: Child node to present the mapping between MIWU group and interrupt + properties: + irq: + type: int + required: true + description: irq for miwu group + irq-prio: + type: int + required: true + description: irq's priority for miwu group. The valid number is from 0 to 7. + group-mask: + type: int + required: true + description: group bit-mask for miwu interrupts + groups: + type: array + description: groups shared the same interrupt diff --git a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-wui-map.yaml b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-wui-map.yaml index 6711820ee00fc6..4c6d15326d8a51 100644 --- a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-wui-map.yaml +++ b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-wui-map.yaml @@ -6,8 +6,8 @@ description: NPCX-MIWU Wake-Up Unit Input (WUI) mapping child node compatible: "nuvoton,npcx-miwu-wui-map" child-binding: - description: Child node to present the mapping between input of MIWU and its source device - properties: - miwus: - type: phandle-array - required: true + description: Child node to present the mapping between input of MIWU and its source device + properties: + miwus: + type: phandle-array + required: true diff --git a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu.yaml b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu.yaml index 99c88c5ce8709c..10d9ebc311b184 100644 --- a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu.yaml +++ b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu.yaml @@ -8,15 +8,15 @@ compatible: "nuvoton,npcx-miwu" include: [base.yaml] properties: - index: - type: int - required: true - description: index of miwu device + index: + type: int + required: true + description: index of miwu device - "#miwu-cells": - type: int - required: true - description: Number of items to present a MIWU input souce specifier + "#miwu-cells": + type: int + required: true + description: Number of items to present a MIWU input souce specifier miwu-cells: - group diff --git a/dts/bindings/interrupt-controller/openisa,rv32m1-event-unit.yaml b/dts/bindings/interrupt-controller/openisa,rv32m1-event-unit.yaml index e08fe1d0bbf0e2..dc8b3b457ba767 100644 --- a/dts/bindings/interrupt-controller/openisa,rv32m1-event-unit.yaml +++ b/dts/bindings/interrupt-controller/openisa,rv32m1-event-unit.yaml @@ -10,10 +10,10 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true "#interrupt-cells": - const: 1 + const: 1 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/openisa,rv32m1-intmux-ch.yaml b/dts/bindings/interrupt-controller/openisa,rv32m1-intmux-ch.yaml index be4e68c9cbbe02..ed5892be6ba52c 100644 --- a/dts/bindings/interrupt-controller/openisa,rv32m1-intmux-ch.yaml +++ b/dts/bindings/interrupt-controller/openisa,rv32m1-intmux-ch.yaml @@ -9,10 +9,10 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true interrupts: - required: true + required: true interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/openisa,rv32m1-intmux.yaml b/dts/bindings/interrupt-controller/openisa,rv32m1-intmux.yaml index caaa9aede375a6..e5579e191707b3 100644 --- a/dts/bindings/interrupt-controller/openisa,rv32m1-intmux.yaml +++ b/dts/bindings/interrupt-controller/openisa,rv32m1-intmux.yaml @@ -9,4 +9,4 @@ include: base.yaml properties: reg: - required: true + required: true diff --git a/dts/bindings/interrupt-controller/riscv,cpu-intc.yaml b/dts/bindings/interrupt-controller/riscv,cpu-intc.yaml index b5592e0c530066..9646dadae7e528 100644 --- a/dts/bindings/interrupt-controller/riscv,cpu-intc.yaml +++ b/dts/bindings/interrupt-controller/riscv,cpu-intc.yaml @@ -9,7 +9,7 @@ include: [interrupt-controller.yaml, base.yaml] properties: "#interrupt-cells": - const: 1 + const: 1 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/riscv,plic0.yaml b/dts/bindings/interrupt-controller/riscv,plic0.yaml index f662b6258f0b3d..5e5a179601bbec 100644 --- a/dts/bindings/interrupt-controller/riscv,plic0.yaml +++ b/dts/bindings/interrupt-controller/riscv,plic0.yaml @@ -7,15 +7,15 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true riscv,max-priority: - type: int - description: maximum interrupt priority - required: true + type: int + description: maximum interrupt priority + required: true "#interrupt-cells": - const: 2 + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/shared-irq.yaml b/dts/bindings/interrupt-controller/shared-irq.yaml index b5e806f520c072..2fed0fae68124d 100644 --- a/dts/bindings/interrupt-controller/shared-irq.yaml +++ b/dts/bindings/interrupt-controller/shared-irq.yaml @@ -6,4 +6,4 @@ include: [interrupt-controller.yaml, base.yaml] properties: interrupts: - required: true + required: true diff --git a/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 45d004ed8ca69b..4698d7f85150f5 100644 --- a/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -8,7 +8,7 @@ compatible: "sifive,plic-1.0.0" include: riscv,plic0.yaml properties: - riscv,ndev: - type: int - description: Number of external interrupts supported - required: true + riscv,ndev: + type: int + description: Number of external interrupts supported + required: true diff --git a/dts/bindings/interrupt-controller/snps,arcv2-intc.yaml b/dts/bindings/interrupt-controller/snps,arcv2-intc.yaml index 09f1a029d538f9..5b594f4a4ab07d 100644 --- a/dts/bindings/interrupt-controller/snps,arcv2-intc.yaml +++ b/dts/bindings/interrupt-controller/snps,arcv2-intc.yaml @@ -8,8 +8,8 @@ compatible: "snps,arcv2-intc" include: [interrupt-controller.yaml, base.yaml] properties: - "#interrupt-cells": - const: 2 + "#interrupt-cells": + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/snps,designware-intc.yaml b/dts/bindings/interrupt-controller/snps,designware-intc.yaml index 957aa90d48383b..02266d0b53bdda 100644 --- a/dts/bindings/interrupt-controller/snps,designware-intc.yaml +++ b/dts/bindings/interrupt-controller/snps,designware-intc.yaml @@ -6,18 +6,18 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true interrupts: - required: true + required: true "#interrupt-cells": - const: 3 + const: 3 num-irqs: - type: int - required: true - description: Number of irq the controller manages + type: int + required: true + description: Number of irq the controller manages interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/swerv,pic.yaml b/dts/bindings/interrupt-controller/swerv,pic.yaml index f71f2676e45822..630f7e6e8cc70e 100644 --- a/dts/bindings/interrupt-controller/swerv,pic.yaml +++ b/dts/bindings/interrupt-controller/swerv,pic.yaml @@ -8,12 +8,12 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true riscv,max-priority: - type: int - description: maximum interrupt priority - required: true + type: int + description: maximum interrupt priority + required: true interrupt-cells: - irq diff --git a/dts/bindings/interrupt-controller/vexriscv-intc0.yaml b/dts/bindings/interrupt-controller/vexriscv-intc0.yaml index a99c8a297ea98f..e370a774c5a638 100644 --- a/dts/bindings/interrupt-controller/vexriscv-intc0.yaml +++ b/dts/bindings/interrupt-controller/vexriscv-intc0.yaml @@ -9,15 +9,15 @@ include: [interrupt-controller.yaml, base.yaml] properties: reg: - required: true + required: true riscv,max-priority: - type: int - description: maximum interrupt priority - required: true + type: int + description: maximum interrupt priority + required: true "#interrupt-cells": - const: 2 + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/ipm/nordic,nrf-ipc.yaml b/dts/bindings/ipm/nordic,nrf-ipc.yaml index 11b0cc4f5b2713..f3e392def63d38 100644 --- a/dts/bindings/ipm/nordic,nrf-ipc.yaml +++ b/dts/bindings/ipm/nordic,nrf-ipc.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-ipc" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/ipm/nxp,lpc-mailbox.yaml b/dts/bindings/ipm/nxp,lpc-mailbox.yaml index 9c1243b1918c25..12f99a83386677 100644 --- a/dts/bindings/ipm/nxp,lpc-mailbox.yaml +++ b/dts/bindings/ipm/nxp,lpc-mailbox.yaml @@ -9,7 +9,7 @@ include: base.yaml properties: reg: - required: true + required: true interrupts: - required: true + required: true diff --git a/dts/bindings/kscan/focaltech,ft5336.yaml b/dts/bindings/kscan/focaltech,ft5336.yaml index da1261a2e8821b..a5741ddb93001b 100644 --- a/dts/bindings/kscan/focaltech,ft5336.yaml +++ b/dts/bindings/kscan/focaltech,ft5336.yaml @@ -8,5 +8,5 @@ compatible: "focaltech,ft5336" include: [kscan.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array + int-gpios: + type: phandle-array diff --git a/dts/bindings/kscan/goodix,gt911.yaml b/dts/bindings/kscan/goodix,gt911.yaml index 84a2e527f51107..b363cb76e2b78e 100644 --- a/dts/bindings/kscan/goodix,gt911.yaml +++ b/dts/bindings/kscan/goodix,gt911.yaml @@ -8,7 +8,7 @@ compatible: "goodix,gt911" include: [kscan.yaml, i2c-device.yaml] properties: - irq-gpios: - type: phandle-array - reset-gpios: - type: phandle-array + irq-gpios: + type: phandle-array + reset-gpios: + type: phandle-array diff --git a/dts/bindings/kscan/hynitron,cst816s.yaml b/dts/bindings/kscan/hynitron,cst816s.yaml index 338abd83a66fae..02dc01f0390d60 100644 --- a/dts/bindings/kscan/hynitron,cst816s.yaml +++ b/dts/bindings/kscan/hynitron,cst816s.yaml @@ -8,16 +8,16 @@ compatible: "hynitron,cst816s" include: i2c-device.yaml properties: - irq-gpios: - type: phandle-array - description: | - The irq signal defaults to active low as produced by the - sensor. The property value should ensure the flags properly - describe the signal that is presented to the driver. + irq-gpios: + type: phandle-array + description: | + The irq signal defaults to active low as produced by the + sensor. The property value should ensure the flags properly + describe the signal that is presented to the driver. - rst-gpios: - type: phandle-array - description: | - The reset signal defaults to active low to the - sensor. The property value should ensure the flags properly - describe the signal that is presented to the driver. + rst-gpios: + type: phandle-array + description: | + The reset signal defaults to active low to the + sensor. The property value should ensure the flags properly + describe the signal that is presented to the driver. diff --git a/dts/bindings/kscan/ite,it8xxx2-kscan.yaml b/dts/bindings/kscan/ite,it8xxx2-kscan.yaml index a905e046c9840d..47a06b44ee37bd 100644 --- a/dts/bindings/kscan/ite,it8xxx2-kscan.yaml +++ b/dts/bindings/kscan/ite,it8xxx2-kscan.yaml @@ -8,35 +8,35 @@ compatible: "ite,it8xxx2-kscan" include: [kscan.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - wucctrl: - type: phandles - description: | - Configure wakeup controller, this controller is used to set that - when the interrupt is triggered in EC low power mode, it can wakeup - EC or not. Via this controller, we set the wakeup trigger edge, - enable, disable, and clear wakeup status for the specific pin which - may be gpio pins or alternate pins. - - kso16-gpios: - type: phandle-array - required: true - description: | - The KSO16 pin for the selected port. - - kso17-gpios: - type: phandle-array - required: true - description: | - The KSO17 pin for the selected port. - - pinctrl-0: - required: true - - pinctrl-names: - required: true + reg: + required: true + + interrupts: + required: true + + wucctrl: + type: phandles + description: | + Configure wakeup controller, this controller is used to set that + when the interrupt is triggered in EC low power mode, it can wakeup + EC or not. Via this controller, we set the wakeup trigger edge, + enable, disable, and clear wakeup status for the specific pin which + may be gpio pins or alternate pins. + + kso16-gpios: + type: phandle-array + required: true + description: | + The KSO16 pin for the selected port. + + kso17-gpios: + type: phandle-array + required: true + description: | + The KSO17 pin for the selected port. + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/kscan/microchip,cap1203.yaml b/dts/bindings/kscan/microchip,cap1203.yaml index 9b4ce9873de2e4..cfa8b0158aad49 100644 --- a/dts/bindings/kscan/microchip,cap1203.yaml +++ b/dts/bindings/kscan/microchip,cap1203.yaml @@ -8,5 +8,5 @@ compatible: "microchip,cap1203" include: [kscan.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array + int-gpios: + type: phandle-array diff --git a/dts/bindings/kscan/microchip,xec-kscan.yaml b/dts/bindings/kscan/microchip,xec-kscan.yaml index 2a6fa41dd82004..3639103e2007f4 100644 --- a/dts/bindings/kscan/microchip,xec-kscan.yaml +++ b/dts/bindings/kscan/microchip,xec-kscan.yaml @@ -9,24 +9,24 @@ compatible: "microchip,xec-kscan" include: [kscan.yaml, pinctrl-device.yaml] properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - type: int - const: 0 - reg: - required: true + "#address-cells": + required: true + const: 1 + "#size-cells": + type: int + const: 0 + reg: + required: true - interrupts: - required: true + interrupts: + required: true - girqs: - type: array - required: true - description: Array of pairs of GIRQ number and bit position + girqs: + type: array + required: true + description: Array of pairs of GIRQ number and bit position - pcrs: - type: array - required: true - description: ADC PCR register index and bit position + pcrs: + type: array + required: true + description: ADC PCR register index and bit position diff --git a/dts/bindings/kscan/nuvoton,npcx-kscan.yaml b/dts/bindings/kscan/nuvoton,npcx-kscan.yaml index 0c1a2b78719658..aad51793e7cc68 100644 --- a/dts/bindings/kscan/nuvoton,npcx-kscan.yaml +++ b/dts/bindings/kscan/nuvoton,npcx-kscan.yaml @@ -8,56 +8,56 @@ compatible: "nuvoton,npcx-kscan" include: [kscan.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - clocks: - required: true - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - wui-maps: - type: phandles - required: true - description: | - Mapping table between Wake-Up Input (WUI) and KSIs. - - For example the WUI mapping on 8 KSI pads would be - wui-maps = <&wui_io30 &wui_io31 &wui_io27 &wui_io26 - &wui_io25 &wui_io24 &wui_io23 &wui_io22>; - - row-size: - type: int - default: 8 - required: true - description: | - The row size is used in the keyboard matrix. - valid range: 1 - 8 - - col-size: - type: int - default: 18 - required: true - description: | - The column size is used in the keyboard matrix. - valid range: 1 - 18 - - debounce-down-ms: - type: int - default: 10 - description: Determines the time in msecs for debouncing a key press. - - debounce-up-ms: - type: int - default: 20 - description: Determines the time in msecs for debouncing a key release. - - no-ghostkey-check: - type: boolean - description: | - Ignore the ghost key checking in the driver if the diodes are used - in the matrix hardware. + reg: + required: true + + clocks: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + wui-maps: + type: phandles + required: true + description: | + Mapping table between Wake-Up Input (WUI) and KSIs. + + For example the WUI mapping on 8 KSI pads would be + wui-maps = <&wui_io30 &wui_io31 &wui_io27 &wui_io26 + &wui_io25 &wui_io24 &wui_io23 &wui_io22>; + + row-size: + type: int + default: 8 + required: true + description: | + The row size is used in the keyboard matrix. + valid range: 1 - 8 + + col-size: + type: int + default: 18 + required: true + description: | + The column size is used in the keyboard matrix. + valid range: 1 - 18 + + debounce-down-ms: + type: int + default: 10 + description: Determines the time in msecs for debouncing a key press. + + debounce-up-ms: + type: int + default: 20 + description: Determines the time in msecs for debouncing a key release. + + no-ghostkey-check: + type: boolean + description: | + Ignore the ghost key checking in the driver if the diodes are used + in the matrix hardware. diff --git a/dts/bindings/led/gpio-leds.yaml b/dts/bindings/led/gpio-leds.yaml index b9f18c05169fc7..6a5d37b929a5a9 100644 --- a/dts/bindings/led/gpio-leds.yaml +++ b/dts/bindings/led/gpio-leds.yaml @@ -35,14 +35,14 @@ description: | compatible: "gpio-leds" child-binding: - description: GPIO LED child node - properties: - gpios: - type: phandle-array - required: true - label: - type: string - description: | - Human readable string describing the LED. It can be used by an - application to identify this LED or to retrieve its number/index - (i.e. child node number) on the parent device. + description: GPIO LED child node + properties: + gpios: + type: phandle-array + required: true + label: + type: string + description: | + Human readable string describing the LED. It can be used by an + application to identify this LED or to retrieve its number/index + (i.e. child node number) on the parent device. diff --git a/dts/bindings/led/holtek,ht16k33.yaml b/dts/bindings/led/holtek,ht16k33.yaml index 1780a84f768366..58fc84809cb564 100644 --- a/dts/bindings/led/holtek,ht16k33.yaml +++ b/dts/bindings/led/holtek,ht16k33.yaml @@ -7,6 +7,6 @@ include: i2c-device.yaml bus: ht16k33 properties: - irq-gpios: - type: phandle-array - description: IRQ pin + irq-gpios: + type: phandle-array + description: IRQ pin diff --git a/dts/bindings/led/led-controller.yaml b/dts/bindings/led/led-controller.yaml index dcf8d525d64707..86aac36baf514d 100644 --- a/dts/bindings/led/led-controller.yaml +++ b/dts/bindings/led/led-controller.yaml @@ -4,29 +4,29 @@ # Common fields for LED controllers and child LEDs child-binding: - description: LED child node - properties: - label: - type: string - description: Human readable string describing the LED - index: - type: int - description: | - Index of the LED on a controller. It can be used by drivers or - applications to map a logical LED to its real position on the - controller. For example, this allows to handle boards where the - LEDs in an array/strip are not wired following the LED order of - the controller. - color-mapping: - type: array - description: | - Channel to color mapping of a multicolor LED. If a LED supports - several colors, then the color-mapping property can be used to - describe how the hardware channels and the colors are mapped. + description: LED child node + properties: + label: + type: string + description: Human readable string describing the LED + index: + type: int + description: | + Index of the LED on a controller. It can be used by drivers or + applications to map a logical LED to its real position on the + controller. For example, this allows to handle boards where the + LEDs in an array/strip are not wired following the LED order of + the controller. + color-mapping: + type: array + description: | + Channel to color mapping of a multicolor LED. If a LED supports + several colors, then the color-mapping property can be used to + describe how the hardware channels and the colors are mapped. - For example the channel to color mapping of RGB LEDs would be + For example the channel to color mapping of RGB LEDs would be - color-mapping = - , - , - ; + color-mapping = + , + , + ; diff --git a/dts/bindings/led/microchip,xec-bbled.yaml b/dts/bindings/led/microchip,xec-bbled.yaml index 085c31559e591e..fc883e0552f847 100644 --- a/dts/bindings/led/microchip,xec-bbled.yaml +++ b/dts/bindings/led/microchip,xec-bbled.yaml @@ -8,24 +8,24 @@ include: [base.yaml, pinctrl-device.yaml] compatible: "microchip,xec-bbled" properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: false + pinctrl-0: + required: false - pinctrl-names: - required: false + pinctrl-names: + required: false - girqs: - type: array - required: true - description: Array of pairs of GIRQ number and bit position + girqs: + type: array + required: true + description: Array of pairs of GIRQ number and bit position - pcrs: - type: array - required: true - description: BBLED PCR register index and bit position + pcrs: + type: array + required: true + description: BBLED PCR register index and bit position diff --git a/dts/bindings/led/pwm-leds.yaml b/dts/bindings/led/pwm-leds.yaml index 72bf10e174b8de..f8942d204573c4 100644 --- a/dts/bindings/led/pwm-leds.yaml +++ b/dts/bindings/led/pwm-leds.yaml @@ -6,15 +6,15 @@ description: PWM LEDs parent node compatible: "pwm-leds" child-binding: - description: PWM LED child node - properties: - pwms: - required: true - type: phandle-array + description: PWM LED child node + properties: + pwms: + required: true + type: phandle-array - label: - type: string - description: | - Human readable string describing the LED. It can be used by an - application to identify this LED or to retrieve its number/index - (i.e. child node number) on the parent device. + label: + type: string + description: | + Human readable string describing the LED. It can be used by an + application to identify this LED or to retrieve its number/index + (i.e. child node number) on the parent device. diff --git a/dts/bindings/led/ti,lp503x.yaml b/dts/bindings/led/ti,lp503x.yaml index a5d49e070be6a8..feac4f2077c573 100644 --- a/dts/bindings/led/ti,lp503x.yaml +++ b/dts/bindings/led/ti,lp503x.yaml @@ -8,21 +8,21 @@ compatible: "ti,lp503x" include: ["i2c-device.yaml", "led-controller.yaml"] properties: - max_curr_opt: - type: boolean - description: | - If enabled the maximum current output is set to 35 mA (25.5 mA else). - log_scale_en: - type: boolean - description: | - If enabled a logarithmic dimming scale curve is used for LED brightness - control. A linear dimming scale curve is used else. + max_curr_opt: + type: boolean + description: | + If enabled the maximum current output is set to 35 mA (25.5 mA else). + log_scale_en: + type: boolean + description: | + If enabled a logarithmic dimming scale curve is used for LED brightness + control. A linear dimming scale curve is used else. child-binding: - properties: - label: - required: true - index: - required: true - color-mapping: - required: true + properties: + label: + required: true + index: + required: true + color-mapping: + required: true diff --git a/dts/bindings/lora/semtech,sx1261.yaml b/dts/bindings/lora/semtech,sx1261.yaml index 8e637a16f8d2c9..d5fa4c69fbe9f0 100644 --- a/dts/bindings/lora/semtech,sx1261.yaml +++ b/dts/bindings/lora/semtech,sx1261.yaml @@ -8,9 +8,9 @@ compatible: "semtech,sx1261" include: semtech,sx126x-base.yaml properties: - reset-gpios: - required: true - busy-gpios: - required: true - dio1-gpios: - required: true + reset-gpios: + required: true + busy-gpios: + required: true + dio1-gpios: + required: true diff --git a/dts/bindings/lora/semtech,sx1262.yaml b/dts/bindings/lora/semtech,sx1262.yaml index c6d04a23be7ae0..cbc586945a4b56 100644 --- a/dts/bindings/lora/semtech,sx1262.yaml +++ b/dts/bindings/lora/semtech,sx1262.yaml @@ -8,9 +8,9 @@ compatible: "semtech,sx1262" include: semtech,sx126x-base.yaml properties: - reset-gpios: - required: true - busy-gpios: - required: true - dio1-gpios: - required: true + reset-gpios: + required: true + busy-gpios: + required: true + dio1-gpios: + required: true diff --git a/dts/bindings/lora/semtech,sx126x-base.yaml b/dts/bindings/lora/semtech,sx126x-base.yaml index 91d7e0e5fe66bb..dd9f96381a4720 100644 --- a/dts/bindings/lora/semtech,sx126x-base.yaml +++ b/dts/bindings/lora/semtech,sx126x-base.yaml @@ -5,57 +5,57 @@ include: spi-device.yaml properties: - reset-gpios: - type: phandle-array - description: | - GPIO connected to the modem's NRESET signal. - - This signal is open-drain, active-low as interpreted by the - modem. - - busy-gpios: - type: phandle-array - description: | - GPIO connected to the modem's BUSY signal. - - antenna-enable-gpios: - type: phandle-array - description: | - Antenna power enable pin. - - tx-enable-gpios: - type: phandle-array - description: | - Antenna switch TX enable GPIO. If set, the driver tracks the - state of the radio and controls the RF switch. - - rx-enable-gpios: - type: phandle-array - description: | - Antenna switch RX enable GPIO. If set, the driver tracks the - state of the radio and controls the RF switch. - - dio1-gpios: - type: phandle-array - description: | - GPIO connected to DIO1. This GPIO will be used as a generic - IRQ line from the chip. - - dio2-tx-enable: - type: boolean - description: | - Use DIO2 to drive an RF switch selecting between the TX and RX - paths. When enabled, DIO2 goes high when the chip is - transmitting. - - dio3-tcxo-voltage: - type: int - description: | - TCXO supply voltage controlled by DIO3 if present. - - See constants in dt-bindings/lora/sx126x.h. - - tcxo-power-startup-delay-ms: - type: int - description: | - Startup delay to let the TCXO stabilize after TCXO power on. + reset-gpios: + type: phandle-array + description: | + GPIO connected to the modem's NRESET signal. + + This signal is open-drain, active-low as interpreted by the + modem. + + busy-gpios: + type: phandle-array + description: | + GPIO connected to the modem's BUSY signal. + + antenna-enable-gpios: + type: phandle-array + description: | + Antenna power enable pin. + + tx-enable-gpios: + type: phandle-array + description: | + Antenna switch TX enable GPIO. If set, the driver tracks the + state of the radio and controls the RF switch. + + rx-enable-gpios: + type: phandle-array + description: | + Antenna switch RX enable GPIO. If set, the driver tracks the + state of the radio and controls the RF switch. + + dio1-gpios: + type: phandle-array + description: | + GPIO connected to DIO1. This GPIO will be used as a generic + IRQ line from the chip. + + dio2-tx-enable: + type: boolean + description: | + Use DIO2 to drive an RF switch selecting between the TX and RX + paths. When enabled, DIO2 goes high when the chip is + transmitting. + + dio3-tcxo-voltage: + type: int + description: | + TCXO supply voltage controlled by DIO3 if present. + + See constants in dt-bindings/lora/sx126x.h. + + tcxo-power-startup-delay-ms: + type: int + description: | + Startup delay to let the TCXO stabilize after TCXO power on. diff --git a/dts/bindings/lora/semtech,sx127x-base.yaml b/dts/bindings/lora/semtech,sx127x-base.yaml index 91ce8b19a2784a..6a7b92f4b27d00 100644 --- a/dts/bindings/lora/semtech,sx127x-base.yaml +++ b/dts/bindings/lora/semtech,sx127x-base.yaml @@ -5,59 +5,59 @@ include: spi-device.yaml properties: - reset-gpios: - type: phandle-array - required: true - description: | - GPIO connected to the modem's RESET/NRESET signal. - - This signal is open-drain, active-high (SX1272/3) or - active-low (SX1276/7/8/9) as interpreted by the modem. - - dio-gpios: - type: phandle-array - required: true - description: | - Up to six pins that produce service interrupts from the modem. - - These signals are normally active-high. - - power-amplifier-output: - type: string - description: | - Selects power amplifier output pin. This is required when neither - 'rfo-enable-gpios' nor 'pa-boost-enable-gpios' is specified. In other - case this property is simply ignored. - enum: - - "rfo" - - "pa-boost" - - antenna-enable-gpios: - type: phandle-array - description: | - Antenna power enable pin. - - rfi-enable-gpios: - type: phandle-array - description: | - RFI antenna input enable pin. - - rfo-enable-gpios: - type: phandle-array - description: | - RFO antenna output enable pin. - - pa-boost-enable-gpios: - type: phandle-array - description: | - PA_BOOST antenna output enable pin. - - tcxo-power-gpios: - type: phandle-array - description: | - TCXO power enable pin. - - tcxo-power-startup-delay-ms: - type: int - description: | - Delay which has to be applied after enabling TCXO power. + reset-gpios: + type: phandle-array + required: true + description: | + GPIO connected to the modem's RESET/NRESET signal. + + This signal is open-drain, active-high (SX1272/3) or + active-low (SX1276/7/8/9) as interpreted by the modem. + + dio-gpios: + type: phandle-array + required: true + description: | + Up to six pins that produce service interrupts from the modem. + + These signals are normally active-high. + + power-amplifier-output: + type: string + description: | + Selects power amplifier output pin. This is required when neither + 'rfo-enable-gpios' nor 'pa-boost-enable-gpios' is specified. In other + case this property is simply ignored. + enum: + - "rfo" + - "pa-boost" + + antenna-enable-gpios: + type: phandle-array + description: | + Antenna power enable pin. + + rfi-enable-gpios: + type: phandle-array + description: | + RFI antenna input enable pin. + + rfo-enable-gpios: + type: phandle-array + description: | + RFO antenna output enable pin. + + pa-boost-enable-gpios: + type: phandle-array + description: | + PA_BOOST antenna output enable pin. + + tcxo-power-gpios: + type: phandle-array + description: | + TCXO power enable pin. + + tcxo-power-startup-delay-ms: + type: int + description: | + Delay which has to be applied after enabling TCXO power. diff --git a/dts/bindings/lora/st,stm32wl-subghz-radio.yaml b/dts/bindings/lora/st,stm32wl-subghz-radio.yaml index 3060703e5af910..fb2a54486b3bc1 100644 --- a/dts/bindings/lora/st,stm32wl-subghz-radio.yaml +++ b/dts/bindings/lora/st,stm32wl-subghz-radio.yaml @@ -8,7 +8,7 @@ compatible: "st,stm32wl-subghz-radio" include: semtech,sx126x-base.yaml properties: - interrupts: - required: true - description: | - Position of the "Radio IRQ, Busy" interrupt line. + interrupts: + required: true + description: | + Position of the "Radio IRQ, Busy" interrupt line. diff --git a/dts/bindings/mbox/mailbox-controller.yaml b/dts/bindings/mbox/mailbox-controller.yaml index ff9f80e55e2baf..f4ab6a14df7c15 100644 --- a/dts/bindings/mbox/mailbox-controller.yaml +++ b/dts/bindings/mbox/mailbox-controller.yaml @@ -4,7 +4,7 @@ # Common fields for mailbox / IPM controllers properties: - "#mbox-cells": - type: int - required: true - description: Number of items to expect in a Mailbox specifier + "#mbox-cells": + type: int + required: true + description: Number of items to expect in a Mailbox specifier diff --git a/dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml b/dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml index 07f79aeed94f1c..2558877fe7fd4f 100644 --- a/dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml +++ b/dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml @@ -8,18 +8,18 @@ compatible: "nordic,mbox-nrf-ipc" include: [base.yaml, mailbox-controller.yaml] properties: - tx-mask: - type: int - required: true - description: TX supported channels mask + tx-mask: + type: int + required: true + description: TX supported channels mask - rx-mask: - type: int - required: true - description: RX supported channels mask + rx-mask: + type: int + required: true + description: RX supported channels mask - interrupts: - required: true + interrupts: + required: true mbox-cells: - channel diff --git a/dts/bindings/mdio/atmel,sam-mdio.yaml b/dts/bindings/mdio/atmel,sam-mdio.yaml index 4b7a45615dba99..4eb649b5b24fa2 100644 --- a/dts/bindings/mdio/atmel,sam-mdio.yaml +++ b/dts/bindings/mdio/atmel,sam-mdio.yaml @@ -6,5 +6,5 @@ description: Atmel SAM Family MDIO Driver node compatible: "atmel,sam-mdio" include: - - name: mdio-controller.yaml - - name: pinctrl-device.yaml + - name: mdio-controller.yaml + - name: pinctrl-device.yaml diff --git a/dts/bindings/mdio/espressif,esp32-mdio.yaml b/dts/bindings/mdio/espressif,esp32-mdio.yaml index a6405e4f370a09..d869d656da5015 100644 --- a/dts/bindings/mdio/espressif,esp32-mdio.yaml +++ b/dts/bindings/mdio/espressif,esp32-mdio.yaml @@ -6,5 +6,5 @@ description: ESP32 MDIO Driver node compatible: "espressif,esp32-mdio" include: - - name: mdio-controller.yaml - - name: pinctrl-device.yaml + - name: mdio-controller.yaml + - name: pinctrl-device.yaml diff --git a/dts/bindings/mdio/mdio-controller.yaml b/dts/bindings/mdio/mdio-controller.yaml index 88bc641a40e65c..aed844bf8f8754 100644 --- a/dts/bindings/mdio/mdio-controller.yaml +++ b/dts/bindings/mdio/mdio-controller.yaml @@ -8,17 +8,17 @@ include: base.yaml bus: mdio properties: - protocol: - type: string - description: | - MDIO bus framing protocol to use for communication. Most devices - support clause 22. + protocol: + type: string + description: | + MDIO bus framing protocol to use for communication. Most devices + support clause 22. - - clause 22: IEEE802.3 clause 22 frame format - - clause 45: IEEE802.3 clause 45 frame format - - micrel SMI: Micrel Serial Management Interface frame format - enum: - - "clause 22" - - "clause 45" - - "micrel SMI" - default: "clause 22" + - clause 22: IEEE802.3 clause 22 frame format + - clause 45: IEEE802.3 clause 45 frame format + - micrel SMI: Micrel Serial Management Interface frame format + enum: + - "clause 22" + - "clause 45" + - "micrel SMI" + default: "clause 22" diff --git a/dts/bindings/memory-controllers/ite,it8xxx2-bbram.yaml b/dts/bindings/memory-controllers/ite,it8xxx2-bbram.yaml index 5297a679a84f7b..9cd0d62baec16d 100644 --- a/dts/bindings/memory-controllers/ite,it8xxx2-bbram.yaml +++ b/dts/bindings/memory-controllers/ite,it8xxx2-bbram.yaml @@ -8,5 +8,5 @@ compatible: "ite,it8xxx2-bbram" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/memory-controllers/microchip,xec-bbram.yaml b/dts/bindings/memory-controllers/microchip,xec-bbram.yaml index aeca313be18dbd..a87081db826420 100644 --- a/dts/bindings/memory-controllers/microchip,xec-bbram.yaml +++ b/dts/bindings/memory-controllers/microchip,xec-bbram.yaml @@ -8,5 +8,5 @@ compatible: "microchip,xec-bbram" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/memory-controllers/nuvoton,npcx-bbram.yaml b/dts/bindings/memory-controllers/nuvoton,npcx-bbram.yaml index 24642795ff6c21..4886cf62ce6b37 100644 --- a/dts/bindings/memory-controllers/nuvoton,npcx-bbram.yaml +++ b/dts/bindings/memory-controllers/nuvoton,npcx-bbram.yaml @@ -8,5 +8,5 @@ compatible: "nuvoton,npcx-bbram" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/memory-controllers/nxp,imx-semc.yaml b/dts/bindings/memory-controllers/nxp,imx-semc.yaml index 245a83fc9f0c21..b82e3c8b4ccb1f 100644 --- a/dts/bindings/memory-controllers/nxp,imx-semc.yaml +++ b/dts/bindings/memory-controllers/nxp,imx-semc.yaml @@ -8,8 +8,8 @@ compatible: "nxp,imx-semc" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/memory-controllers/st,stm32-bbram.yaml b/dts/bindings/memory-controllers/st,stm32-bbram.yaml index 951ece0efbacd5..3f8ddba15211b9 100644 --- a/dts/bindings/memory-controllers/st,stm32-bbram.yaml +++ b/dts/bindings/memory-controllers/st,stm32-bbram.yaml @@ -15,7 +15,7 @@ compatible: "st,stm32-bbram" include: base.yaml properties: - st,backup-regs: - type: int - required: true - description: Number of available backup registers. + st,backup-regs: + type: int + required: true + description: Number of available backup registers. diff --git a/dts/bindings/memory-controllers/st,stm32-fmc.yaml b/dts/bindings/memory-controllers/st,stm32-fmc.yaml index 0de4b72653c276..7f2172297555db 100644 --- a/dts/bindings/memory-controllers/st,stm32-fmc.yaml +++ b/dts/bindings/memory-controllers/st,stm32-fmc.yaml @@ -32,14 +32,14 @@ compatible: "st,stm32-fmc" include: [base.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml b/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml index 3ddbe5ae71e9f8..89fa3bf2a4700b 100644 --- a/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml +++ b/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml @@ -32,18 +32,18 @@ compatible: "st,stm32h7-fmc" include: ["st,stm32-fmc.yaml"] properties: - st,mem-swap: - type: string - default: "disable" # reset state - enum: - - "disable" - - "sdram-sram" - - "sdramb2" - description: | - The FMC bank mapping configuration (BMAP bits of FMC_BCR1). - - * disable - Default mapping. - * sdram-sram - Swap the NOR/PSRAM bank with SDRAM. - * sdramb2 - Remaps the SDRAM bank2. - - If absent, then default mapping (disable) is used (reset state). + st,mem-swap: + type: string + default: "disable" # reset state + enum: + - "disable" + - "sdram-sram" + - "sdramb2" + description: | + The FMC bank mapping configuration (BMAP bits of FMC_BCR1). + + * disable - Default mapping. + * sdram-sram - Swap the NOR/PSRAM bank with SDRAM. + * sdramb2 - Remaps the SDRAM bank2. + + If absent, then default mapping (disable) is used (reset state). diff --git a/dts/bindings/memory-controllers/zephyr,bbram-emul.yaml b/dts/bindings/memory-controllers/zephyr,bbram-emul.yaml index a68e79d196c23b..576df8a1f31dff 100644 --- a/dts/bindings/memory-controllers/zephyr,bbram-emul.yaml +++ b/dts/bindings/memory-controllers/zephyr,bbram-emul.yaml @@ -8,7 +8,7 @@ compatible: "zephyr,bbram-emul" include: base.yaml properties: - size: - type: int - required: true - description: Size of the BBRAM region in bytes. + size: + type: int + required: true + description: Size of the BBRAM region in bytes. diff --git a/dts/bindings/mfd/gd,gd32-rcu.yaml b/dts/bindings/mfd/gd,gd32-rcu.yaml index 2753d018fe0b9a..a0a7c5a7191e6e 100644 --- a/dts/bindings/mfd/gd,gd32-rcu.yaml +++ b/dts/bindings/mfd/gd,gd32-rcu.yaml @@ -11,5 +11,5 @@ compatible: "gd,gd32-rcu" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/mfd/nordic,npm6001.yaml b/dts/bindings/mfd/nordic,npm6001.yaml index 4f50fb4628f1e8..ce2e019a277f96 100644 --- a/dts/bindings/mfd/nordic,npm6001.yaml +++ b/dts/bindings/mfd/nordic,npm6001.yaml @@ -8,5 +8,5 @@ compatible: "nordic,npm6001" include: i2c-device.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/mhu/arm,mhu.yaml b/dts/bindings/mhu/arm,mhu.yaml index 0589c4da38c0f1..8a259380d733c5 100644 --- a/dts/bindings/mhu/arm,mhu.yaml +++ b/dts/bindings/mhu/arm,mhu.yaml @@ -8,8 +8,8 @@ compatible: "arm,mhu" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/mipi-dsi/mipi-dsi-device.yaml b/dts/bindings/mipi-dsi/mipi-dsi-device.yaml index ce520ae401cc31..fde81db220f515 100644 --- a/dts/bindings/mipi-dsi/mipi-dsi-device.yaml +++ b/dts/bindings/mipi-dsi/mipi-dsi-device.yaml @@ -8,17 +8,17 @@ include: base.yaml on-bus: mipi-dsi properties: - reg: - required: true + reg: + required: true - data-lanes: - type: array - required: true - description: - Number of data lanes. + data-lanes: + type: array + required: true + description: + Number of data lanes. - pixel-format: - type: int - required: true - description: - Pixel format. Available formats in dt-bindings/mipi_dsi/mipi_dsi.h. + pixel-format: + type: int + required: true + description: + Pixel format. Available formats in dt-bindings/mipi_dsi/mipi_dsi.h. diff --git a/dts/bindings/mipi-dsi/mipi-dsi-host.yaml b/dts/bindings/mipi-dsi/mipi-dsi-host.yaml index 1302ee92f9201f..24a048765ef7e1 100644 --- a/dts/bindings/mipi-dsi/mipi-dsi-host.yaml +++ b/dts/bindings/mipi-dsi/mipi-dsi-host.yaml @@ -8,10 +8,10 @@ include: base.yaml bus: mipi-dsi properties: - "#address-cells": - required: true - const: 1 + "#address-cells": + required: true + const: 1 - "#size-cells": - required: true - const: 0 + "#size-cells": + required: true + const: 0 diff --git a/dts/bindings/mipi-dsi/nxp,imx-mipi-dsi.yaml b/dts/bindings/mipi-dsi/nxp,imx-mipi-dsi.yaml index 5f46b337f2bef6..216c8bdc1dd9a5 100644 --- a/dts/bindings/mipi-dsi/nxp,imx-mipi-dsi.yaml +++ b/dts/bindings/mipi-dsi/nxp,imx-mipi-dsi.yaml @@ -10,63 +10,63 @@ compatible: "nxp,imx-mipi-dsi" include: mipi-dsi-host.yaml properties: - interrupts: - required: true + interrupts: + required: true - nxp,lcdif: - type: phandle - required: true - description: - Instance of the LCDIF peripheral. + nxp,lcdif: + type: phandle + required: true + description: + Instance of the LCDIF peripheral. - dpi-color-coding: - type: string - enum: - - "16-bit-config-1" - - "16-bit-config-2" - - "16-bit-config-3" - - "18-bit-config-1" - - "18-bit-config-2" - - "24-bit" - description: - MIPI DPI interface color coding. Sets the distribution of RGB bits within - the 24-bit d bus, as specified by the DPI specification. + dpi-color-coding: + type: string + enum: + - "16-bit-config-1" + - "16-bit-config-2" + - "16-bit-config-3" + - "18-bit-config-1" + - "18-bit-config-2" + - "24-bit" + description: + MIPI DPI interface color coding. Sets the distribution of RGB bits within + the 24-bit d bus, as specified by the DPI specification. - dpi-pixel-packet: - type: string - enum: - - "16-bit" - - "18-bit" - - "18-bit-loose" - - "24-bit" - description: - MIPI DSI pixel packet type send through DPI interface. + dpi-pixel-packet: + type: string + enum: + - "16-bit" + - "18-bit" + - "18-bit-loose" + - "24-bit" + description: + MIPI DSI pixel packet type send through DPI interface. - dpi-video-mode: - type: string - enum: - - "non-burst-sync-pulse" - - "non-burst-sync-event" - - "burst" - description: - DPI video mode. + dpi-video-mode: + type: string + enum: + - "non-burst-sync-pulse" + - "non-burst-sync-event" + - "burst" + description: + DPI video mode. - dpi-bllp-mode: - type: string - enum: - - "low-power" - - "blank" - - "null" - description: - Behavior in BLLP (Blanking or Low-Power Interval). + dpi-bllp-mode: + type: string + enum: + - "low-power" + - "blank" + - "null" + description: + Behavior in BLLP (Blanking or Low-Power Interval). - autoinsert-eotp: - type: boolean - description: - Automatically insert an EoTp short packet when switching from HS to LP mode. + autoinsert-eotp: + type: boolean + description: + Automatically insert an EoTp short packet when switching from HS to LP mode. - dphy-ref-frequency: - type: int - required: true - description: - Maximum clock speed supported by the device, in Hz. + dphy-ref-frequency: + type: int + required: true + description: + Maximum clock speed supported by the device, in Hz. diff --git a/dts/bindings/misc/nuvoton,npcx-booter-variant.yaml b/dts/bindings/misc/nuvoton,npcx-booter-variant.yaml index 393cdfa293fb07..08a8702c8ca63c 100644 --- a/dts/bindings/misc/nuvoton,npcx-booter-variant.yaml +++ b/dts/bindings/misc/nuvoton,npcx-booter-variant.yaml @@ -6,8 +6,8 @@ description: Nuvoton, NPCX booter variant options compatible: "nuvoton,npcx-booter-variant" properties: - hif-type-auto: - type: boolean - description: | - The host interface type (LPC/eSPI/SHI) is configured by booter - if true; otherwise, it should be configured by the firmware. + hif-type-auto: + type: boolean + description: | + The host interface type (LPC/eSPI/SHI) is configured by booter + if true; otherwise, it should be configured by the firmware. diff --git a/dts/bindings/misc/nuvoton,npcx-soc-id.yaml b/dts/bindings/misc/nuvoton,npcx-soc-id.yaml index e65a5473fa2a73..2f44d469902306 100644 --- a/dts/bindings/misc/nuvoton,npcx-soc-id.yaml +++ b/dts/bindings/misc/nuvoton,npcx-soc-id.yaml @@ -6,22 +6,22 @@ description: Nuvoton, NPCX soc ID node compatible: "nuvoton,npcx-soc-id" properties: - family-id: - type: int - required: true - description: NPCX family ID + family-id: + type: int + required: true + description: NPCX family ID - chip-id: - type: int - required: true - description: NPCX chip ID + chip-id: + type: int + required: true + description: NPCX chip ID - device-id: - type: int - required: true - description: NPCX device ID + device-id: + type: int + required: true + description: NPCX device ID - revision-reg: - type: array - required: true - description: NPCX revision register address & length in byte + revision-reg: + type: array + required: true + description: NPCX revision register address & length in byte diff --git a/dts/bindings/misc/skyworks,sky13351.yaml b/dts/bindings/misc/skyworks,sky13351.yaml index f4e3152881e208..7bcf912482fa6e 100644 --- a/dts/bindings/misc/skyworks,sky13351.yaml +++ b/dts/bindings/misc/skyworks,sky13351.yaml @@ -8,11 +8,11 @@ compatible: "skyworks,sky13351" include: base.yaml properties: - vctl1-gpios: - type: phandle-array - required: true - description: VCTL1 pin - vctl2-gpios: - type: phandle-array - required: true - description: VCTL2 pin + vctl1-gpios: + type: phandle-array + required: true + description: VCTL1 pin + vctl2-gpios: + type: phandle-array + required: true + description: VCTL2 pin diff --git a/dts/bindings/misc/snps,arc-iot-sysconf.yaml b/dts/bindings/misc/snps,arc-iot-sysconf.yaml index 710ca731f36e7d..b4141f55384e5e 100644 --- a/dts/bindings/misc/snps,arc-iot-sysconf.yaml +++ b/dts/bindings/misc/snps,arc-iot-sysconf.yaml @@ -8,5 +8,5 @@ compatible: "snps,arc-iot-sysconf" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/misc/zephyr,flash-disk.yaml b/dts/bindings/misc/zephyr,flash-disk.yaml index dfc4b699e5cf32..caefe7c7d0aaa2 100644 --- a/dts/bindings/misc/zephyr,flash-disk.yaml +++ b/dts/bindings/misc/zephyr,flash-disk.yaml @@ -8,31 +8,31 @@ compatible: "zephyr,flash-disk" include: base.yaml properties: - partition: - type: phandle - required: true - description: | - Backing storage flash map partition. + partition: + type: phandle + required: true + description: | + Backing storage flash map partition. - disk-name: - type: string - required: true - description: | - Disk name. + disk-name: + type: string + required: true + description: | + Disk name. - sector-size: - type: int - default: 512 - description: | - Emulated block device sector size in bytes. + sector-size: + type: int + default: 512 + description: | + Emulated block device sector size in bytes. - cache-size: - type: int - required: true - description: | - Size of statically allocated buffer size in bytes. The size should be - adequately chosen. On storage backends with uniform erase-blocks it - should be at least the erase-block-size, on storage backends with - non-uniform erase-blocks it should be at least the largest - erase-block-size. The cache-size property is ignored if the partition - is read-only. + cache-size: + type: int + required: true + description: | + Size of statically allocated buffer size in bytes. The size should be + adequately chosen. On storage backends with uniform erase-blocks it + should be at least the erase-block-size, on storage backends with + non-uniform erase-blocks it should be at least the largest + erase-block-size. The cache-size property is ignored if the partition + is read-only. diff --git a/dts/bindings/misc/zephyr,modbus-serial.yaml b/dts/bindings/misc/zephyr,modbus-serial.yaml index b07134f4da43d8..688511943a3b2e 100644 --- a/dts/bindings/misc/zephyr,modbus-serial.yaml +++ b/dts/bindings/misc/zephyr,modbus-serial.yaml @@ -8,18 +8,18 @@ compatible: "zephyr,modbus-serial" include: uart-device.yaml properties: - de-gpios: - type: phandle-array - description: Driver enable pin. + de-gpios: + type: phandle-array + description: Driver enable pin. - Driver enable pin (DE) of the RS-485 transceiver. - If connected directly the MCU pin should be configured - as active high. + Driver enable pin (DE) of the RS-485 transceiver. + If connected directly the MCU pin should be configured + as active high. - re-gpios: - type: phandle-array - description: Receiver enable pin. + re-gpios: + type: phandle-array + description: Receiver enable pin. - Receiver enable pin (nRE) of the RS-485 transceiver. - If connected directly the MCU pin should be configured - as active low. + Receiver enable pin (nRE) of the RS-485 transceiver. + If connected directly the MCU pin should be configured + as active low. diff --git a/dts/bindings/mm/intel,adsp-imr.yaml b/dts/bindings/mm/intel,adsp-imr.yaml index 05464e9938810c..5ebcfbc4fb4034 100644 --- a/dts/bindings/mm/intel,adsp-imr.yaml +++ b/dts/bindings/mm/intel,adsp-imr.yaml @@ -9,9 +9,9 @@ compatible: "intel,adsp-imr" include: [mm_drv.yaml, "zephyr,memory-region.yaml"] properties: - reg: - required: true + reg: + required: true - block-size: - required: true - type: int + block-size: + required: true + type: int diff --git a/dts/bindings/mm/intel,adsp-mtl-tlb.yaml b/dts/bindings/mm/intel,adsp-mtl-tlb.yaml index 2b3dacbc5893af..d7b7e1dcda74ba 100644 --- a/dts/bindings/mm/intel,adsp-mtl-tlb.yaml +++ b/dts/bindings/mm/intel,adsp-mtl-tlb.yaml @@ -9,18 +9,18 @@ compatible: "intel,adsp-mtl-tlb" include: mm_drv.yaml properties: - reg: - required: true + reg: + required: true - paddr-size: - type: int - description: Number of significant bits in the page index. - required: true + paddr-size: + type: int + description: Number of significant bits in the page index. + required: true - exec-bit-idx: - type: int - description: Index of the execute permission bit. + exec-bit-idx: + type: int + description: Index of the execute permission bit. - write-bit-idx: - type: int - description: Index of the write permission bit. + write-bit-idx: + type: int + description: Index of the write permission bit. diff --git a/dts/bindings/mm/intel,adsp-tlb.yaml b/dts/bindings/mm/intel,adsp-tlb.yaml index 56e473c6c82d3d..045ffed0806b95 100644 --- a/dts/bindings/mm/intel,adsp-tlb.yaml +++ b/dts/bindings/mm/intel,adsp-tlb.yaml @@ -9,18 +9,18 @@ compatible: "intel,adsp-tlb" include: mm_drv.yaml properties: - reg: - required: true + reg: + required: true - paddr-size: - type: int - description: Number of significant bits in the page index. - required: true + paddr-size: + type: int + description: Number of significant bits in the page index. + required: true - exec-bit-idx: - type: int - description: Index of the execute permission bit. + exec-bit-idx: + type: int + description: Index of the execute permission bit. - write-bit-idx: - type: int - description: Index of the write permission bit. + write-bit-idx: + type: int + description: Index of the write permission bit. diff --git a/dts/bindings/mmc/st,stm32-sdmmc.yaml b/dts/bindings/mmc/st,stm32-sdmmc.yaml index 194e4766aab85a..aeb5f85bafd197 100644 --- a/dts/bindings/mmc/st,stm32-sdmmc.yaml +++ b/dts/bindings/mmc/st,stm32-sdmmc.yaml @@ -5,52 +5,52 @@ compatible: "st,stm32-sdmmc" include: [mmc.yaml, pinctrl-device.yaml] properties: - clocks: - required: true - - reg: - required: true - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - cd-gpios: - type: phandle-array - description: Card Detect pin - - pwr-gpios: - type: phandle-array - description: Power pin - - bus-width: - type: int - default: 1 - description: | - bus width for SDMMC access, defaults to the minimum necessary - number of bus lines - enum: - - 1 - - 4 - - 8 - - dmas: - description: | - Optional DMA channel specifier. If DMA should be used, specifier should - hold a phandle reference to the dma controller, the channel number, - the slot number, channel configuration and finally features. - - Only priority bits are used in the configuration. There are no feature - flags. - - For example dmas for TX/RX on SDMMC - dmas = <&dma2 4 6 0x30000 0x00>, <&dma2 4 3 0x30000 0x00>; - - dma-names: - description: | - DMA channel name. If DMA should be used, expected value is "tx", "rx". - - For example - dma-names = "tx", "rx"; + clocks: + required: true + + reg: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + cd-gpios: + type: phandle-array + description: Card Detect pin + + pwr-gpios: + type: phandle-array + description: Power pin + + bus-width: + type: int + default: 1 + description: | + bus width for SDMMC access, defaults to the minimum necessary + number of bus lines + enum: + - 1 + - 4 + - 8 + + dmas: + description: | + Optional DMA channel specifier. If DMA should be used, specifier should + hold a phandle reference to the dma controller, the channel number, + the slot number, channel configuration and finally features. + + Only priority bits are used in the configuration. There are no feature + flags. + + For example dmas for TX/RX on SDMMC + dmas = <&dma2 4 6 0x30000 0x00>, <&dma2 4 3 0x30000 0x00>; + + dma-names: + description: | + DMA channel name. If DMA should be used, expected value is "tx", "rx". + + For example + dma-names = "tx", "rx"; diff --git a/dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml index e44a04a50beb42..6534ec078744a8 100644 --- a/dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml +++ b/dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml @@ -8,11 +8,11 @@ compatible: "arm,armv6m-mpu" include: base.yaml properties: - reg: - required: true + reg: + required: true - arm,num-mpu-regions: - required: true - type: int - const: 8 - description: number of MPU regions supported by hardware + arm,num-mpu-regions: + required: true + type: int + const: 8 + description: number of MPU regions supported by hardware diff --git a/dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml index 4225b6aaf6e93d..36de0b9f711a71 100644 --- a/dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml +++ b/dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml @@ -5,10 +5,10 @@ compatible: "arm,armv7m-mpu" include: base.yaml properties: - reg: - required: true + reg: + required: true - arm,num-mpu-regions: - required: true - type: int - description: number of MPU regions supported by hardware + arm,num-mpu-regions: + required: true + type: int + description: number of MPU regions supported by hardware diff --git a/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml index 610ec29daa6de9..fd924284de8775 100644 --- a/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml +++ b/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml @@ -5,10 +5,10 @@ compatible: "arm,armv8.1m-mpu" include: base.yaml properties: - reg: - required: true + reg: + required: true - arm,num-mpu-regions: - required: true - type: int - description: number of MPU regions supported by hardware + arm,num-mpu-regions: + required: true + type: int + description: number of MPU regions supported by hardware diff --git a/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml index 662b5043715412..103216228919db 100644 --- a/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml +++ b/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml @@ -5,10 +5,10 @@ compatible: "arm,armv8m-mpu" include: base.yaml properties: - reg: - required: true + reg: + required: true - arm,num-mpu-regions: - required: true - type: int - description: number of MPU regions supported by hardware + arm,num-mpu-regions: + required: true + type: int + description: number of MPU regions supported by hardware diff --git a/dts/bindings/modem/openisa,rv32m1-genfsk.yaml b/dts/bindings/modem/openisa,rv32m1-genfsk.yaml index 37416f084ffe31..81d2fd34318bca 100644 --- a/dts/bindings/modem/openisa,rv32m1-genfsk.yaml +++ b/dts/bindings/modem/openisa,rv32m1-genfsk.yaml @@ -8,8 +8,8 @@ compatible: "openisa,rv32m1-genfsk" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/modem/quectel,bg9x.yaml b/dts/bindings/modem/quectel,bg9x.yaml index 8539d8bdfdf03b..1526769821714a 100644 --- a/dts/bindings/modem/quectel,bg9x.yaml +++ b/dts/bindings/modem/quectel,bg9x.yaml @@ -8,16 +8,16 @@ compatible: "quectel,bg9x" include: uart-device.yaml properties: - mdm-power-gpios: - type: phandle-array - required: true + mdm-power-gpios: + type: phandle-array + required: true - mdm-reset-gpios: - type: phandle-array - required: true + mdm-reset-gpios: + type: phandle-array + required: true - mdm-dtr-gpios: - type: phandle-array + mdm-dtr-gpios: + type: phandle-array - mdm-wdisable-gpios: - type: phandle-array + mdm-wdisable-gpios: + type: phandle-array diff --git a/dts/bindings/modem/swir,hl7800.yaml b/dts/bindings/modem/swir,hl7800.yaml index 689d3819cea494..b937031455fff2 100644 --- a/dts/bindings/modem/swir,hl7800.yaml +++ b/dts/bindings/modem/swir,hl7800.yaml @@ -11,37 +11,37 @@ compatible: "swir,hl7800" include: uart-device.yaml properties: - mdm-wake-gpios: - type: phandle-array - required: true + mdm-wake-gpios: + type: phandle-array + required: true - mdm-reset-gpios: - type: phandle-array - required: true + mdm-reset-gpios: + type: phandle-array + required: true - mdm-pwr-on-gpios: - type: phandle-array - required: true + mdm-pwr-on-gpios: + type: phandle-array + required: true - mdm-fast-shutd-gpios: - type: phandle-array - required: true + mdm-fast-shutd-gpios: + type: phandle-array + required: true - mdm-vgpio-gpios: - type: phandle-array - required: true + mdm-vgpio-gpios: + type: phandle-array + required: true - mdm-uart-dsr-gpios: - type: phandle-array - required: true + mdm-uart-dsr-gpios: + type: phandle-array + required: true - mdm-uart-cts-gpios: - type: phandle-array - required: true + mdm-uart-cts-gpios: + type: phandle-array + required: true - mdm-gpio2-gpios: - type: phandle-array + mdm-gpio2-gpios: + type: phandle-array - mdm-gpio6-gpios: - type: phandle-array - required: true + mdm-gpio6-gpios: + type: phandle-array + required: true diff --git a/dts/bindings/modem/u-blox,sara-r4.yaml b/dts/bindings/modem/u-blox,sara-r4.yaml index 9f3fc5efb82210..f24bc57e0a7408 100644 --- a/dts/bindings/modem/u-blox,sara-r4.yaml +++ b/dts/bindings/modem/u-blox,sara-r4.yaml @@ -8,12 +8,12 @@ compatible: "u-blox,sara-r4" include: uart-device.yaml properties: - mdm-power-gpios: - type: phandle-array - required: true + mdm-power-gpios: + type: phandle-array + required: true - mdm-reset-gpios: - type: phandle-array + mdm-reset-gpios: + type: phandle-array - mdm-vint-gpios: - type: phandle-array + mdm-vint-gpios: + type: phandle-array diff --git a/dts/bindings/modem/wnc,m14a2a.yaml b/dts/bindings/modem/wnc,m14a2a.yaml index a08fbd97e6811d..db00b6fbeb64a2 100644 --- a/dts/bindings/modem/wnc,m14a2a.yaml +++ b/dts/bindings/modem/wnc,m14a2a.yaml @@ -8,26 +8,26 @@ compatible: "wnc,m14a2a" include: uart-device.yaml properties: - mdm-boot-mode-sel-gpios: - type: phandle-array - required: true + mdm-boot-mode-sel-gpios: + type: phandle-array + required: true - mdm-power-gpios: - type: phandle-array - required: true + mdm-power-gpios: + type: phandle-array + required: true - mdm-keep-awake-gpios: - type: phandle-array - required: true + mdm-keep-awake-gpios: + type: phandle-array + required: true - mdm-reset-gpios: - type: phandle-array - required: true + mdm-reset-gpios: + type: phandle-array + required: true - mdm-shld-trans-ena-gpios: - type: phandle-array - required: true + mdm-shld-trans-ena-gpios: + type: phandle-array + required: true - mdm-send-ok-gpios: - type: phandle-array - description: UART RTS pin if no HW flow control (set to always enabled) + mdm-send-ok-gpios: + type: phandle-array + description: UART RTS pin if no HW flow control (set to always enabled) diff --git a/dts/bindings/mtd/atmel,at2x-base.yaml b/dts/bindings/mtd/atmel,at2x-base.yaml index a3515262d96e76..1120dee014aec4 100644 --- a/dts/bindings/mtd/atmel,at2x-base.yaml +++ b/dts/bindings/mtd/atmel,at2x-base.yaml @@ -6,23 +6,23 @@ include: eeprom-base.yaml properties: - size: - required: true - pagesize: - type: int - required: true - description: EEPROM page size in bytes - address-width: - type: int - required: true - description: EEPROM address width in bits - timeout: - type: int - required: true - description: EEPROM write cycle timeout in milliseconds - wp-gpios: - type: phandle-array - description: | - GPIO to which the write-protect pin of the chip is connected. + size: + required: true + pagesize: + type: int + required: true + description: EEPROM page size in bytes + address-width: + type: int + required: true + description: EEPROM address width in bits + timeout: + type: int + required: true + description: EEPROM write cycle timeout in milliseconds + wp-gpios: + type: phandle-array + description: | + GPIO to which the write-protect pin of the chip is connected. - The device will interpret this signal as active-low. + The device will interpret this signal as active-low. diff --git a/dts/bindings/mtd/eeprom-base.yaml b/dts/bindings/mtd/eeprom-base.yaml index 6e7ad61ab0dc18..8141bc3cd90ca6 100644 --- a/dts/bindings/mtd/eeprom-base.yaml +++ b/dts/bindings/mtd/eeprom-base.yaml @@ -6,9 +6,9 @@ include: base.yaml properties: - size: - type: int - description: Total EEPROM size in bytes - read-only: - type: boolean - description: Disable writes to the EEPROM + size: + type: int + description: Total EEPROM size in bytes + read-only: + type: boolean + description: Disable writes to the EEPROM diff --git a/dts/bindings/mtd/fixed-partitions.yaml b/dts/bindings/mtd/fixed-partitions.yaml index 0f4ec0ce21e953..18bf4ee24c6001 100644 --- a/dts/bindings/mtd/fixed-partitions.yaml +++ b/dts/bindings/mtd/fixed-partitions.yaml @@ -3,25 +3,25 @@ description: Flash partitions parent node compatible: "fixed-partitions" properties: - "#address-cells": - type: int - description: number of address cells in reg property + "#address-cells": + type: int + description: number of address cells in reg property - "#size-cells": - type: int - description: number of size cells in reg property + "#size-cells": + type: int + description: number of size cells in reg property child-binding: - description: Flash partition child node - properties: - label: - type: string - description: | - Human readable string describing the device (used as device_get_binding() argument) - read-only: - type: boolean - description: if the partition is read-only or not - reg: - type: array - description: register space - required: true + description: Flash partition child node + properties: + label: + type: string + description: | + Human readable string describing the device (used as device_get_binding() argument) + read-only: + type: boolean + description: if the partition is read-only or not + reg: + type: array + description: register space + required: true diff --git a/dts/bindings/mtd/infineon,xmc4xxx-nv-flash.yaml b/dts/bindings/mtd/infineon,xmc4xxx-nv-flash.yaml index 43f0f9d87ab5ef..547915ef70fd67 100644 --- a/dts/bindings/mtd/infineon,xmc4xxx-nv-flash.yaml +++ b/dts/bindings/mtd/infineon,xmc4xxx-nv-flash.yaml @@ -8,15 +8,15 @@ compatible: "infineon,xmc4xxx-nv-flash" include: soc-nv-flash.yaml child-binding: - description: Flash page layout description - child-binding: - description: Individual flash page layout entry - properties: - pages-count: - description: Number of consecutive pages with size pages-size bytes - type: int - required: true + description: Flash page layout description + child-binding: + description: Individual flash page layout entry + properties: + pages-count: + description: Number of consecutive pages with size pages-size bytes + type: int + required: true - pages-size: - type: int - required: true + pages-size: + type: int + required: true diff --git a/dts/bindings/mtd/microchip,xec-eeprom.yaml b/dts/bindings/mtd/microchip,xec-eeprom.yaml index e84ec4b7b364e0..ca6b5cb259f28e 100644 --- a/dts/bindings/mtd/microchip,xec-eeprom.yaml +++ b/dts/bindings/mtd/microchip,xec-eeprom.yaml @@ -8,17 +8,17 @@ compatible: "microchip,xec-eeprom" include: [eeprom-base.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - girqs: - type: array - required: true - description: | - Array of GIRQ and bit position pairs for each interrupt - signal the block generates. + girqs: + type: array + required: true + description: | + Array of GIRQ and bit position pairs for each interrupt + signal the block generates. - pcrs: - type: array - required: true - description: PS2 PCR register index and bit position + pcrs: + type: array + required: true + description: PS2 PCR register index and bit position diff --git a/dts/bindings/mtd/nxp,imx-flexspi-device.yaml b/dts/bindings/mtd/nxp,imx-flexspi-device.yaml index 2c2fc4fb96d467..add3a7c0aef256 100644 --- a/dts/bindings/mtd/nxp,imx-flexspi-device.yaml +++ b/dts/bindings/mtd/nxp,imx-flexspi-device.yaml @@ -6,85 +6,85 @@ description: NXP FlexSPI device include: [spi-device.yaml, "jedec,jesd216.yaml"] properties: - cs-interval-unit: - type: int - default: 1 - enum: - - 1 - - 256 - description: | - Chip select interval units, in serial clock cycles. See the - CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The - default corresponds to the reset value of the register field. + cs-interval-unit: + type: int + default: 1 + enum: + - 1 + - 256 + description: | + Chip select interval units, in serial clock cycles. See the + CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The + default corresponds to the reset value of the register field. - cs-interval: - type: int - default: 0 - description: | - Minimum interval between chip select deassertion and assertion. See the - CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The - default corresponds to the reset value of the register field. + cs-interval: + type: int + default: 0 + description: | + Minimum interval between chip select deassertion and assertion. See the + CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The + default corresponds to the reset value of the register field. - cs-setup-time: - type: int - default: 3 - description: | - Chip select setup time, in serial clock cycles. See the TCSS field in - registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the - reset value of the register field. + cs-setup-time: + type: int + default: 3 + description: | + Chip select setup time, in serial clock cycles. See the TCSS field in + registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the + reset value of the register field. - cs-hold-time: - type: int - default: 3 - description: | - Chip select hold time, in serial clock cycles. See the TCSH field in - registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the - reset value of the register field. + cs-hold-time: + type: int + default: 3 + description: | + Chip select hold time, in serial clock cycles. See the TCSH field in + registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the + reset value of the register field. - data-valid-time: - type: int - default: 0 - description: | - Data valid time, in nanoseconds. See the registers DLLACR through - DLLBCR. + data-valid-time: + type: int + default: 0 + description: | + Data valid time, in nanoseconds. See the registers DLLACR through + DLLBCR. - column-space: - type: int - default: 0 - description: | - Column address bit width. Set to zero if the flash does not support - column address. See the CAS field in registers FLASHA1CR0 through - FLASHB2CR0. The default corresponds to the reset value of the register - field. + column-space: + type: int + default: 0 + description: | + Column address bit width. Set to zero if the flash does not support + column address. See the CAS field in registers FLASHA1CR0 through + FLASHB2CR0. The default corresponds to the reset value of the register + field. - word-addressable: - type: boolean - description: | - Don't transmit the least significant address bit when the flash is word - addressable. See the WA field in registers FLASHA1CR0 through - FLASHB2CR0. + word-addressable: + type: boolean + description: | + Don't transmit the least significant address bit when the flash is word + addressable. See the WA field in registers FLASHA1CR0 through + FLASHB2CR0. - ahb-write-wait-unit: - type: int - default: 2 - enum: - - 2 - - 8 - - 32 - - 128 - - 512 - - 2048 - - 8192 - - 32768 - description: | - AHB write wait interval units, in AHB clock cycles. See the AWRWAITUNIT - field in registers FLASHA1CR2 through FLASHB2CR2. The default - corresponds to the reset value of the register field. + ahb-write-wait-unit: + type: int + default: 2 + enum: + - 2 + - 8 + - 32 + - 128 + - 512 + - 2048 + - 8192 + - 32768 + description: | + AHB write wait interval units, in AHB clock cycles. See the AWRWAITUNIT + field in registers FLASHA1CR2 through FLASHB2CR2. The default + corresponds to the reset value of the register field. - ahb-write-wait-interval: - type: int - default: 0 - description: | - Time to wait between AHB triggered command sequences. See the AWRWAIT - field in registers FLASHA1CR2 through FLASHB2CR2. The default - corresponds to the reset value of the register field. + ahb-write-wait-interval: + type: int + default: 0 + description: | + Time to wait between AHB triggered command sequences. See the AWRWAIT + field in registers FLASHA1CR2 through FLASHB2CR2. The default + corresponds to the reset value of the register field. diff --git a/dts/bindings/mtd/soc-nv-flash.yaml b/dts/bindings/mtd/soc-nv-flash.yaml index 0c043aa1574d9e..85d31bdcafce47 100644 --- a/dts/bindings/mtd/soc-nv-flash.yaml +++ b/dts/bindings/mtd/soc-nv-flash.yaml @@ -5,10 +5,10 @@ compatible: "soc-nv-flash" include: base.yaml properties: - erase-block-size: - type: int - description: address alignment required by flash erase operations + erase-block-size: + type: int + description: address alignment required by flash erase operations - write-block-size: - type: int - description: address alignment required by flash write operations + write-block-size: + type: int + description: address alignment required by flash write operations diff --git a/dts/bindings/mtd/st,stm32-eeprom.yaml b/dts/bindings/mtd/st,stm32-eeprom.yaml index 6f2c0040a32113..eacc45ae42415f 100644 --- a/dts/bindings/mtd/st,stm32-eeprom.yaml +++ b/dts/bindings/mtd/st,stm32-eeprom.yaml @@ -8,5 +8,5 @@ compatible: "st,stm32-eeprom" include: eeprom-base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/mtd/st,stm32-nv-flash.yaml b/dts/bindings/mtd/st,stm32-nv-flash.yaml index 08e89ef7240317..23e1e29bebb464 100644 --- a/dts/bindings/mtd/st,stm32-nv-flash.yaml +++ b/dts/bindings/mtd/st,stm32-nv-flash.yaml @@ -8,7 +8,7 @@ include: soc-nv-flash.yaml compatible: st,stm32-nv-flash properties: - max-erase-time: - type: int - description: max erase time(millisecond) of a flash sector or page or half-page - required: true + max-erase-time: + type: int + description: max erase time(millisecond) of a flash sector or page or half-page + required: true diff --git a/dts/bindings/mtd/zephyr,emu-eeprom.yaml b/dts/bindings/mtd/zephyr,emu-eeprom.yaml index 8ece816a8284b9..9c3d2eda399bdf 100644 --- a/dts/bindings/mtd/zephyr,emu-eeprom.yaml +++ b/dts/bindings/mtd/zephyr,emu-eeprom.yaml @@ -8,22 +8,22 @@ compatible: "zephyr,emu-eeprom" include: eeprom-base.yaml properties: - size: - required: true - pagesize: - type: int - required: true - description: Size of a page used to emulate EEPROM in flash - partition: - type: phandle - required: true - description: Flash partition used to store the emulated EEPROM data - rambuf: - type: boolean - description: Enable a ram buffer of EEPROM size for improved read speed - partition-erase: - type: boolean - description: | - Delay erase until complete partition is used. This enables a - ram buffer to allow data to be copied during the partition erase. If - power is lost during the partition erase the data will be lost. + size: + required: true + pagesize: + type: int + required: true + description: Size of a page used to emulate EEPROM in flash + partition: + type: phandle + required: true + description: Flash partition used to store the emulated EEPROM data + rambuf: + type: boolean + description: Enable a ram buffer of EEPROM size for improved read speed + partition-erase: + type: boolean + description: | + Delay erase until complete partition is used. This enables a + ram buffer to allow data to be copied during the partition erase. If + power is lost during the partition erase the data will be lost. diff --git a/dts/bindings/mtd/zephyr,fake-eeprom.yaml b/dts/bindings/mtd/zephyr,fake-eeprom.yaml index 8103b2b808c0e7..ba07679c69b0a5 100644 --- a/dts/bindings/mtd/zephyr,fake-eeprom.yaml +++ b/dts/bindings/mtd/zephyr,fake-eeprom.yaml @@ -9,5 +9,5 @@ compatible: "zephyr,fake-eeprom" include: eeprom-base.yaml properties: - size: - required: true + size: + required: true diff --git a/dts/bindings/mtd/zephyr,sim-eeprom.yaml b/dts/bindings/mtd/zephyr,sim-eeprom.yaml index c7c7cb7b4ff642..5b0a09041d51e8 100644 --- a/dts/bindings/mtd/zephyr,sim-eeprom.yaml +++ b/dts/bindings/mtd/zephyr,sim-eeprom.yaml @@ -8,5 +8,5 @@ compatible: "zephyr,sim-eeprom" include: eeprom-base.yaml properties: - size: - required: true + size: + required: true diff --git a/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml b/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml index c243272705f8a4..a7202f1294d983 100644 --- a/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml +++ b/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml @@ -22,34 +22,34 @@ compatible: "generic-fem-two-ctrl-pins" include: base.yaml properties: - ctx-gpios: - type: phandle-array - description: | - SoC GPIO connected to the CTX input pin on the FEM device. - - crx-gpios: - type: phandle-array - description: | - SoC GPIO connected to the CRX input pin on the FEM device. - - ctx-settle-time-us: - type: int - description: | - Desired minimum settling time, in microseconds, from - assertion of the CTX pin to beginning of transmission. - - crx-settle-time-us: - type: int - description: | - Desired minimum settling time, in microseconds, from - assertion of the CRX pin to beginning of reception. - - tx-gain-db: - type: int - description: | - TX gain of the PA of the FEM device, in dB. - - rx-gain-db: - type: int - description: | - RX gain of the LNA of the FEM device, in dB. + ctx-gpios: + type: phandle-array + description: | + SoC GPIO connected to the CTX input pin on the FEM device. + + crx-gpios: + type: phandle-array + description: | + SoC GPIO connected to the CRX input pin on the FEM device. + + ctx-settle-time-us: + type: int + description: | + Desired minimum settling time, in microseconds, from + assertion of the CTX pin to beginning of transmission. + + crx-settle-time-us: + type: int + description: | + Desired minimum settling time, in microseconds, from + assertion of the CRX pin to beginning of reception. + + tx-gain-db: + type: int + description: | + TX gain of the PA of the FEM device, in dB. + + rx-gain-db: + type: int + description: | + RX gain of the LNA of the FEM device, in dB. diff --git a/dts/bindings/net/wireless/nordic,nrf-nfct.yaml b/dts/bindings/net/wireless/nordic,nrf-nfct.yaml index 97e56e289d44ee..5f0691300d3dcc 100644 --- a/dts/bindings/net/wireless/nordic,nrf-nfct.yaml +++ b/dts/bindings/net/wireless/nordic,nrf-nfct.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-nfct" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/net/wireless/nordic,nrf-radio.yaml b/dts/bindings/net/wireless/nordic,nrf-radio.yaml index 0498f2ea47ddc6..9814e5f5fb7cd1 100644 --- a/dts/bindings/net/wireless/nordic,nrf-radio.yaml +++ b/dts/bindings/net/wireless/nordic,nrf-radio.yaml @@ -111,119 +111,119 @@ compatible: "nordic,nrf-radio" include: [base.yaml] properties: - reg: - required: true - - interrupts: - required: true - - fem: - type: phandle - description: | - Phandle linking the RADIO node to its external front-end module. - - coex: - type: phandle - description: | - Phandle linking the RADIO node to the external radio coexistence arbitrator. - - dfe-supported: - type: boolean - description: | - If set, the radio hardware supports the Direction Finding Extension. - This property should be treated as read-only and should not be overridden; - the correct value is provided for your target's SoC already. - - dfe-antenna-num: - type: int - description: | - Number of available antennas for the Direction Finding Extension. - - This should only be set if dfe-supported is true. If you set this - property, the value must be at least two. - - dfe-pdu-antenna: - type: int - description: | - Antenna switch pattern to be used for transmission of PDU before start - of transmission of Constant Tone Extension. - - This should only be set if dfe-supported is true. - - This pattern is stored in SWITCHPATTERN[0] before actual antenna - switching patterns. This pattern will also be used to drive GPIOs - when the radio releases control of GPIOs used to switch antennas. - - dfegpio0-gpios: - type: phandle-array - description: | - Pin select for DFE pin 0. This should only be set if dfe-supported - is true. - - For example, to use P0.2 on an nRF5x SoC: - - dfegpio1-gpios = <&gpio0 2 0>; - - To use P1.4: - - dfegpio1-gpios = <&gpio1 4 0>; - - Note the last 'flags' cell in the property is not used, - and should be set to 0 as shown. - - dfegpio1-gpios: - type: phandle-array - description: | - Pin select for DFE pin 1. See description for dfegpio0-gpios. - - dfegpio2-gpios: - type: phandle-array - description: | - Pin select for DFE pin 2. See description for dfegpio0-gpios. - - dfegpio3-gpios: - type: phandle-array - description: | - Pin select for DFE pin 3. See description for dfegpio0-gpios. - - dfegpio4-gpios: - type: phandle-array - description: | - Pin select for DFE pin 4. See description for dfegpio0-gpios. - - dfegpio5-gpios: - type: phandle-array - description: | - Pin select for DFE pin 5. See description for dfegpio0-gpios. - - dfegpio6-gpios: - type: phandle-array - description: | - Pin select for DFE pin 6. See description for dfegpio0-gpios. - - dfegpio7-gpios: - type: phandle-array - description: | - Pin select for DFE pin 7. See description for dfegpio0-gpios. - - ieee802154-supported: - type: boolean - description: | - If set, indicates that the radio hardware supports the IEEE 802.15.4 - mode. - - ble-2mbps-supported: - type: boolean - description: | - If set, indicates that the radio hardware supports the 2 Mbps BLE mode. - - ble-coded-phy-supported: - type: boolean - description: | - If set, indicates that the radio hardware supports coded BLE PHY. - - tx-high-power-supported: - type: boolean - description: | - If set, indicates that the radio hardware supports high TX power - settings. + reg: + required: true + + interrupts: + required: true + + fem: + type: phandle + description: | + Phandle linking the RADIO node to its external front-end module. + + coex: + type: phandle + description: | + Phandle linking the RADIO node to the external radio coexistence arbitrator. + + dfe-supported: + type: boolean + description: | + If set, the radio hardware supports the Direction Finding Extension. + This property should be treated as read-only and should not be overridden; + the correct value is provided for your target's SoC already. + + dfe-antenna-num: + type: int + description: | + Number of available antennas for the Direction Finding Extension. + + This should only be set if dfe-supported is true. If you set this + property, the value must be at least two. + + dfe-pdu-antenna: + type: int + description: | + Antenna switch pattern to be used for transmission of PDU before start + of transmission of Constant Tone Extension. + + This should only be set if dfe-supported is true. + + This pattern is stored in SWITCHPATTERN[0] before actual antenna + switching patterns. This pattern will also be used to drive GPIOs + when the radio releases control of GPIOs used to switch antennas. + + dfegpio0-gpios: + type: phandle-array + description: | + Pin select for DFE pin 0. This should only be set if dfe-supported + is true. + + For example, to use P0.2 on an nRF5x SoC: + + dfegpio1-gpios = <&gpio0 2 0>; + + To use P1.4: + + dfegpio1-gpios = <&gpio1 4 0>; + + Note the last 'flags' cell in the property is not used, + and should be set to 0 as shown. + + dfegpio1-gpios: + type: phandle-array + description: | + Pin select for DFE pin 1. See description for dfegpio0-gpios. + + dfegpio2-gpios: + type: phandle-array + description: | + Pin select for DFE pin 2. See description for dfegpio0-gpios. + + dfegpio3-gpios: + type: phandle-array + description: | + Pin select for DFE pin 3. See description for dfegpio0-gpios. + + dfegpio4-gpios: + type: phandle-array + description: | + Pin select for DFE pin 4. See description for dfegpio0-gpios. + + dfegpio5-gpios: + type: phandle-array + description: | + Pin select for DFE pin 5. See description for dfegpio0-gpios. + + dfegpio6-gpios: + type: phandle-array + description: | + Pin select for DFE pin 6. See description for dfegpio0-gpios. + + dfegpio7-gpios: + type: phandle-array + description: | + Pin select for DFE pin 7. See description for dfegpio0-gpios. + + ieee802154-supported: + type: boolean + description: | + If set, indicates that the radio hardware supports the IEEE 802.15.4 + mode. + + ble-2mbps-supported: + type: boolean + description: | + If set, indicates that the radio hardware supports the 2 Mbps BLE mode. + + ble-coded-phy-supported: + type: boolean + description: | + If set, indicates that the radio hardware supports coded BLE PHY. + + tx-high-power-supported: + type: boolean + description: | + If set, indicates that the radio hardware supports high TX power + settings. diff --git a/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml b/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml index 152f8ee5b7f9a3..706fe8dd9e66fb 100644 --- a/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml +++ b/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml @@ -67,72 +67,72 @@ compatible: "nordic,nrf21540-fem" include: base.yaml properties: - tx-en-gpios: - type: phandle-array - description: | - GPIO of the SOC controlling TX_EN pin of the nRF21540 - rx-en-gpios: - type: phandle-array - description: | - GPIO of the SOC controlling RX_EN pin of the nRF21540 - pdn-gpios: - type: phandle-array - description: | - GPIO of the SOC controlling PDN pin of the nRF21540 - ant-sel-gpios: - type: phandle-array - description: | - GPIO of the SOC controlling ANT-SEL pin of the nRF21540 - mode-gpios: - type: phandle-array - description: | - GPIO of the SOC controlling MODE pin of the nRF21540 - spi-if: - type: phandle - description: | - Reference to the nordic,nrf21540-fem-spi SPI bus interface. - - This must be present to support SPI control of the FEM. - tx-en-settle-time-us: - type: int - default: 11 - description: | - Settling time in microseconds from state PG to TX. - - Default value is based on Table 6 of the nRF21540 Product - Specification (v1.0), and can be overridden for tuned - configurations. - rx-en-settle-time-us: - type: int - default: 11 - description: | - Settling time in microseconds from state PG to RX. - - Default value is based on Table 6 of the nRF21540 Product - Specification (v1.0), and can be overridden for tuned - configurations. - pdn-settle-time-us: - type: int - default: 18 - description: | - Settling time in microseconds from state PD to PG. - - Default value is based on Table 6 of the nRF21540 Product - Specification (v1.0), and can be overridden for tuned - configurations. - trx-hold-time-us: - type: int - default: 3 - description: | - Power-off time in microseconds when changing from RX or TX to PG. - - Default value is based on Table 6 of the nRF21540 Product - Specification (v1.0), and can be overridden for tuned - configurations. - supply-voltage-mv: - type: int - description: | - nRF21540 supply voltage in mV. - - This is used if compensation for nRF21540 supply voltage is supported - by software. + tx-en-gpios: + type: phandle-array + description: | + GPIO of the SOC controlling TX_EN pin of the nRF21540 + rx-en-gpios: + type: phandle-array + description: | + GPIO of the SOC controlling RX_EN pin of the nRF21540 + pdn-gpios: + type: phandle-array + description: | + GPIO of the SOC controlling PDN pin of the nRF21540 + ant-sel-gpios: + type: phandle-array + description: | + GPIO of the SOC controlling ANT-SEL pin of the nRF21540 + mode-gpios: + type: phandle-array + description: | + GPIO of the SOC controlling MODE pin of the nRF21540 + spi-if: + type: phandle + description: | + Reference to the nordic,nrf21540-fem-spi SPI bus interface. + + This must be present to support SPI control of the FEM. + tx-en-settle-time-us: + type: int + default: 11 + description: | + Settling time in microseconds from state PG to TX. + + Default value is based on Table 6 of the nRF21540 Product + Specification (v1.0), and can be overridden for tuned + configurations. + rx-en-settle-time-us: + type: int + default: 11 + description: | + Settling time in microseconds from state PG to RX. + + Default value is based on Table 6 of the nRF21540 Product + Specification (v1.0), and can be overridden for tuned + configurations. + pdn-settle-time-us: + type: int + default: 18 + description: | + Settling time in microseconds from state PD to PG. + + Default value is based on Table 6 of the nRF21540 Product + Specification (v1.0), and can be overridden for tuned + configurations. + trx-hold-time-us: + type: int + default: 3 + description: | + Power-off time in microseconds when changing from RX or TX to PG. + + Default value is based on Table 6 of the nRF21540 Product + Specification (v1.0), and can be overridden for tuned + configurations. + supply-voltage-mv: + type: int + description: | + nRF21540 supply voltage in mV. + + This is used if compensation for nRF21540 supply voltage is supported + by software. diff --git a/dts/bindings/neural_net/intel,gna.yaml b/dts/bindings/neural_net/intel,gna.yaml index f62f6f9a9a380a..9d363fededb03c 100644 --- a/dts/bindings/neural_net/intel,gna.yaml +++ b/dts/bindings/neural_net/intel,gna.yaml @@ -9,11 +9,11 @@ compatible: "intel,gna" include: [base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - interrupt-parent: - required: true + interrupt-parent: + required: true diff --git a/dts/bindings/ospi/st,stm32-ospi.yaml b/dts/bindings/ospi/st,stm32-ospi.yaml index 65201a1802ea67..0e6554502d6813 100644 --- a/dts/bindings/ospi/st,stm32-ospi.yaml +++ b/dts/bindings/ospi/st,stm32-ospi.yaml @@ -25,47 +25,47 @@ include: [base.yaml, pinctrl-device.yaml] bus: ospi properties: - reg: - required: true - - interrupts: - required: true - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - clock-names: - required: true - - dmas: - description: | - Optional DMA channel specifier, required for DMA transactions. - For example dmas for TX/RX on OSPI - dmas = <&dma1 5 41 0x10000>; - - With, in each cell of the dmas specifier: - - &dma1: dma controller phandle - - 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x. - - 41: slot number (request which could be given by the DMAMUX) - - 0x10000: channel configuration (only for srce/dest data size, priority) - - Notes: - - On series supporting DMAMUX, the DMA phandle should be provided - but DMAMUX node should also be enabled in the DTS. - - For channel configuration, only the config bits priority and - periph/mem datasize are used. The periph/mem datasize must be equal, - 0 is a correct value. - - There is no Fifo used by this DMA peripheral. - - For example dmas for TX/RX on OSPI - dmas = <&dma1 5 41 0x10000>; - - dma-names: - description: | - DMA channel name. If DMA should be used, expected value is "tx_rx". - - For example - dma-names = "tx_rx"; + reg: + required: true + + interrupts: + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + clock-names: + required: true + + dmas: + description: | + Optional DMA channel specifier, required for DMA transactions. + For example dmas for TX/RX on OSPI + dmas = <&dma1 5 41 0x10000>; + + With, in each cell of the dmas specifier: + - &dma1: dma controller phandle + - 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x. + - 41: slot number (request which could be given by the DMAMUX) + - 0x10000: channel configuration (only for srce/dest data size, priority) + + Notes: + - On series supporting DMAMUX, the DMA phandle should be provided + but DMAMUX node should also be enabled in the DTS. + - For channel configuration, only the config bits priority and + periph/mem datasize are used. The periph/mem datasize must be equal, + 0 is a correct value. + - There is no Fifo used by this DMA peripheral. + + For example dmas for TX/RX on OSPI + dmas = <&dma1 5 41 0x10000>; + + dma-names: + description: | + DMA channel name. If DMA should be used, expected value is "tx_rx". + + For example + dma-names = "tx_rx"; diff --git a/dts/bindings/pcie/endpoint/brcm,iproc-pcie-ep.yaml b/dts/bindings/pcie/endpoint/brcm,iproc-pcie-ep.yaml index 9353bf410bf842..227ad20ecf0347 100644 --- a/dts/bindings/pcie/endpoint/brcm,iproc-pcie-ep.yaml +++ b/dts/bindings/pcie/endpoint/brcm,iproc-pcie-ep.yaml @@ -8,9 +8,9 @@ compatible: "brcm,iproc-pcie-ep" include: base.yaml properties: - reg: - required: true - description: | - Register space for the memory mapped PAX(PCIe to AXI bridge) registers, - It includes registers to access EP configuration space - and to map Host PCIe address to PCIe Outbound memory. + reg: + required: true + description: | + Register space for the memory mapped PAX(PCIe to AXI bridge) registers, + It includes registers to access EP configuration space + and to map Host PCIe address to PCIe Outbound memory. diff --git a/dts/bindings/pcie/host/pci-host-ecam-generic.yaml b/dts/bindings/pcie/host/pci-host-ecam-generic.yaml index edd2f1a7cbc297..fea7d35ef17a59 100644 --- a/dts/bindings/pcie/host/pci-host-ecam-generic.yaml +++ b/dts/bindings/pcie/host/pci-host-ecam-generic.yaml @@ -8,25 +8,25 @@ compatible: "pci-host-ecam-generic" include: pcie-controller.yaml properties: - reg: - required: true + reg: + required: true - msi-parent: - type: phandle + msi-parent: + type: phandle - ranges: - type: array - required: true - description: | - As described in IEEE Std 1275-1994, but must provide at least a - definition of non-prefetchable memory. One or both of prefetchable Memory - and IO Space may also be provided. + ranges: + type: array + required: true + description: | + As described in IEEE Std 1275-1994, but must provide at least a + definition of non-prefetchable memory. One or both of prefetchable Memory + and IO Space may also be provided. - interrupt-map-mask: - type: array + interrupt-map-mask: + type: array - interrupt-map: - type: compound + interrupt-map: + type: compound - bus-range: - type: array + bus-range: + type: array diff --git a/dts/bindings/pcie/host/pcie-controller.yaml b/dts/bindings/pcie/host/pcie-controller.yaml index fb8ab644c9f4cd..c5e1bcd83d647c 100644 --- a/dts/bindings/pcie/host/pcie-controller.yaml +++ b/dts/bindings/pcie/host/pcie-controller.yaml @@ -8,7 +8,7 @@ include: base.yaml bus: pcie properties: - "#address-cells": - required: true - "#size-cells": - required: true + "#address-cells": + required: true + "#size-cells": + required: true diff --git a/dts/bindings/pcie/host/pcie-device.yaml b/dts/bindings/pcie/host/pcie-device.yaml index 490a0aa63ecab7..773b8aefbad0dc 100644 --- a/dts/bindings/pcie/host/pcie-device.yaml +++ b/dts/bindings/pcie/host/pcie-device.yaml @@ -4,9 +4,9 @@ # Common fields for PCIe devices properties: - vendor-id: - type: int - description: Vendor ID of the device - device-id: - type: int - description: Device ID of the device + vendor-id: + type: int + description: Vendor ID of the device + device-id: + type: int + description: Device ID of the device diff --git a/dts/bindings/peci/ite,it8xxx2-peci.yaml b/dts/bindings/peci/ite,it8xxx2-peci.yaml index b2c5b87dc0ba8b..97e61684ae77ff 100644 --- a/dts/bindings/peci/ite,it8xxx2-peci.yaml +++ b/dts/bindings/peci/ite,it8xxx2-peci.yaml @@ -8,8 +8,8 @@ compatible: "ite,it8xxx2-peci" include: [peci.yaml, pinctrl-device.yaml] properties: - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/peci/microchip,xec-peci.yaml b/dts/bindings/peci/microchip,xec-peci.yaml index fa4502cc3acc1f..00ad08cb57a4e9 100644 --- a/dts/bindings/peci/microchip,xec-peci.yaml +++ b/dts/bindings/peci/microchip,xec-peci.yaml @@ -8,18 +8,18 @@ compatible: "microchip,xec-peci" include: [peci.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - girqs: - type: array - required: true - description: Array of pairs of GIRQ number and bit position + girqs: + type: array + required: true + description: Array of pairs of GIRQ number and bit position - pcrs: - type: array - required: true - description: ADC PCR register index and bit position + pcrs: + type: array + required: true + description: ADC PCR register index and bit position diff --git a/dts/bindings/peci/nuvoton,npcx-peci.yaml b/dts/bindings/peci/nuvoton,npcx-peci.yaml index 07dfb35391cde3..e4dbc8ba46869f 100644 --- a/dts/bindings/peci/nuvoton,npcx-peci.yaml +++ b/dts/bindings/peci/nuvoton,npcx-peci.yaml @@ -8,8 +8,8 @@ compatible: "nuvoton,npcx-peci" include: [peci.yaml, pinctrl-device.yaml] properties: - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/peci/peci.yaml b/dts/bindings/peci/peci.yaml index ff69ae2c093e05..c9233f42a65a6a 100644 --- a/dts/bindings/peci/peci.yaml +++ b/dts/bindings/peci/peci.yaml @@ -8,11 +8,11 @@ include: base.yaml bus: peci properties: - "#address-cells": - type: int - required: true - const: 1 - "#size-cells": - type: int - required: true - const: 0 + "#address-cells": + type: int + required: true + const: 1 + "#size-cells": + type: int + required: true + const: 0 diff --git a/dts/bindings/phy/can-transceiver-gpio.yaml b/dts/bindings/phy/can-transceiver-gpio.yaml index 2ee5a98843a0a4..bb535547ab4d03 100644 --- a/dts/bindings/phy/can-transceiver-gpio.yaml +++ b/dts/bindings/phy/can-transceiver-gpio.yaml @@ -8,16 +8,16 @@ compatible: "can-transceiver-gpio" include: can-transceiver.yaml properties: - enable-gpios: - type: phandle-array - description: | - GPIO to use to enable/disable the CAN transceiver. This GPIO is driven - active when the CAN transceiver is enabled and inactive when the CAN - transceiver is disabled. + enable-gpios: + type: phandle-array + description: | + GPIO to use to enable/disable the CAN transceiver. This GPIO is driven + active when the CAN transceiver is enabled and inactive when the CAN + transceiver is disabled. - standby-gpios: - type: phandle-array - description: | - GPIO to use to put the CAN transceiver into standby. This GPIO is driven - inactive when the CAN transceiver is enabled and active when the CAN - transceiver is disabled. + standby-gpios: + type: phandle-array + description: | + GPIO to use to put the CAN transceiver into standby. This GPIO is driven + inactive when the CAN transceiver is enabled and active when the CAN + transceiver is disabled. diff --git a/dts/bindings/phy/can-transceiver.yaml b/dts/bindings/phy/can-transceiver.yaml index 35e9c9b4f4f0dd..428c386be8f019 100644 --- a/dts/bindings/phy/can-transceiver.yaml +++ b/dts/bindings/phy/can-transceiver.yaml @@ -6,11 +6,11 @@ include: phy-controller.yaml properties: - max-bitrate: - type: int - required: true - description: | - The maximum bitrate supported by the CAN transceiver in bits/s. + max-bitrate: + type: int + required: true + description: | + The maximum bitrate supported by the CAN transceiver in bits/s. - "#phy-cells": - const: 0 + "#phy-cells": + const: 0 diff --git a/dts/bindings/phy/phy-controller.yaml b/dts/bindings/phy/phy-controller.yaml index cd0b8307347458..0b1ed1712cadec 100644 --- a/dts/bindings/phy/phy-controller.yaml +++ b/dts/bindings/phy/phy-controller.yaml @@ -6,9 +6,9 @@ include: base.yaml properties: - "#phy-cells": - type: int - required: true - description: | - Number of cells in a PHY provider. The meaning those - cells is defined by the binding for the phy node. + "#phy-cells": + type: int + required: true + description: | + Number of cells in a PHY provider. The meaning those + cells is defined by the binding for the phy node. diff --git a/dts/bindings/phy/st,stm32-usbphyc.yaml b/dts/bindings/phy/st,stm32-usbphyc.yaml index 019a997e5b9b34..e304a1545de912 100644 --- a/dts/bindings/phy/st,stm32-usbphyc.yaml +++ b/dts/bindings/phy/st,stm32-usbphyc.yaml @@ -8,8 +8,8 @@ compatible: "st,stm32-usbphyc" include: phy-controller.yaml properties: - reg: - required: true + reg: + required: true - "#phy-cells": - const: 0 + "#phy-cells": + const: 0 diff --git a/dts/bindings/phy/usb-nop-xceiv.yaml b/dts/bindings/phy/usb-nop-xceiv.yaml index 3e1a631a64f610..0faf3e7fe8747a 100644 --- a/dts/bindings/phy/usb-nop-xceiv.yaml +++ b/dts/bindings/phy/usb-nop-xceiv.yaml @@ -10,5 +10,5 @@ compatible: "usb-nop-xceiv" include: phy-controller.yaml properties: - "#phy-cells": - const: 0 + "#phy-cells": + const: 0 diff --git a/dts/bindings/phy/usb-ulpi-phy.yaml b/dts/bindings/phy/usb-ulpi-phy.yaml index 8d64437e6481ec..e9c55ad41e15a6 100644 --- a/dts/bindings/phy/usb-ulpi-phy.yaml +++ b/dts/bindings/phy/usb-ulpi-phy.yaml @@ -10,11 +10,11 @@ compatible: "usb-ulpi-phy" include: phy-controller.yaml properties: - "#phy-cells": - const: 0 + "#phy-cells": + const: 0 - reset-gpios: - type: phandle-array - required: false - description: | - GPIO connected to the ulpi RESET pin. + reset-gpios: + type: phandle-array + required: false + description: | + GPIO connected to the ulpi RESET pin. diff --git a/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml b/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml index f7ae71cf056cae..63ac10827550e7 100644 --- a/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml +++ b/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml @@ -76,12 +76,12 @@ compatible: "atmel,sam-pinctrl" include: base.yaml properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - required: true - const: 1 + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 1 child-binding: description: | diff --git a/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml b/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml index acf23b353a62df..7557c5e52e91cb 100644 --- a/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml +++ b/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml @@ -78,12 +78,12 @@ compatible: "atmel,sam0-pinctrl" include: base.yaml properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - required: true - const: 1 + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 1 child-binding: description: | diff --git a/dts/bindings/pinctrl/atmel,sam0-pinmux.yaml b/dts/bindings/pinctrl/atmel,sam0-pinmux.yaml index 3caf6c2eea1d71..16d9352708d32c 100644 --- a/dts/bindings/pinctrl/atmel,sam0-pinmux.yaml +++ b/dts/bindings/pinctrl/atmel,sam0-pinmux.yaml @@ -5,8 +5,8 @@ compatible: "atmel,sam0-pinmux" include: base.yaml properties: - reg: - required: true + reg: + required: true pinmux-cells: - pin diff --git a/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml b/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml index ed28ce2e76e64c..8914f873f81f24 100644 --- a/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml +++ b/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml @@ -22,18 +22,18 @@ compatible: "cypress,psoc6-pinctrl" include: base.yaml properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - required: true - const: 1 + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 1 child-binding: - description: cypress pins + description: cypress pins - include: pincfg-node.yaml + include: pincfg-node.yaml - properties: - "cypress,pins": - type: phandle-array + properties: + "cypress,pins": + type: phandle-array diff --git a/dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml b/dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml index 891d7762aafb91..5821a28defd4cb 100644 --- a/dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml +++ b/dts/bindings/pinctrl/infineon,xmc4xxx-pinctrl.yaml @@ -50,62 +50,62 @@ compatible: "infineon,xmc4xxx-pinctrl" include: base.yaml properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - required: true - const: 1 + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 1 child-binding: - description: Each child node defines the configuration for a particular state. - - include: - - name: pincfg-node.yaml - property-allowlist: - - bias-pull-down - - bias-pull-up - - drive-push-pull - - drive-open-drain - - output-high - - output-low - - properties: - pinmux: - description: | - Encodes port/pin and alternate function. See helper macro XMC4XX_PINMUX_SET(). - Alternate function is only set for output pins; It selects ALT1-ALT4 - output line in the GPIO element. The alternate function for input pins is - handled separately by the peripheral. It is upto the peripheral to configure which - input pin to use (For example see parameter input-src in infineon,xmc4xxx-uart.yaml). - required: true - type: int - - drive-strength: - description: | - Drive strength of the output pin. Following options as in XMC_GPIO_OUTPUT_STRENGTH - See xmc4_gpio.h. This only has an effect if the pin is in drive-push-pull mode. - required: true - type: string - enum: - - "strong-sharp-edge" - - "strong-medium-edge" - - "strong-soft-edge" - - "strong-slow-edge" - - "medium" - - "medium-unknown1-edge" - - "medium-unknown2-edge" - - "weak" - - invert-input: - description: Inverts the input. - type: boolean - - hwctrl: - description: Pre-assigns hardware control of the pin to a certain peripheral. - required: true - type: string - enum: - - "disabled" - - "periph1" - - "periph2" + description: Each child node defines the configuration for a particular state. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-pull-down + - bias-pull-up + - drive-push-pull + - drive-open-drain + - output-high + - output-low + + properties: + pinmux: + description: | + Encodes port/pin and alternate function. See helper macro XMC4XX_PINMUX_SET(). + Alternate function is only set for output pins; It selects ALT1-ALT4 + output line in the GPIO element. The alternate function for input pins is + handled separately by the peripheral. It is upto the peripheral to configure which + input pin to use (For example see parameter input-src in infineon,xmc4xxx-uart.yaml). + required: true + type: int + + drive-strength: + description: | + Drive strength of the output pin. Following options as in XMC_GPIO_OUTPUT_STRENGTH + See xmc4_gpio.h. This only has an effect if the pin is in drive-push-pull mode. + required: true + type: string + enum: + - "strong-sharp-edge" + - "strong-medium-edge" + - "strong-soft-edge" + - "strong-slow-edge" + - "medium" + - "medium-unknown1-edge" + - "medium-unknown2-edge" + - "weak" + + invert-input: + description: Inverts the input. + type: boolean + + hwctrl: + description: Pre-assigns hardware control of the pin to a certain peripheral. + required: true + type: string + enum: + - "disabled" + - "periph1" + - "periph2" diff --git a/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml b/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml index c00c4c6f63d9b1..3df41db957c0ee 100644 --- a/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml +++ b/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml @@ -8,29 +8,29 @@ compatible: "ite,it8xxx2-pinctrl-func" include: base.yaml properties: - func3-gcr: - type: array - required: true + func3-gcr: + type: array + required: true - func3-en-mask: - type: array - required: true + func3-en-mask: + type: array + required: true - func4-gcr: - type: array - required: true + func4-gcr: + type: array + required: true - func4-en-mask: - type: array - required: true + func4-en-mask: + type: array + required: true - volt-sel: - type: array - required: true + volt-sel: + type: array + required: true - volt-sel-mask: - type: array - required: true + volt-sel-mask: + type: array + required: true pinmux-cells: - pin diff --git a/dts/bindings/pinctrl/ite,it8xxx2-pinctrl.yaml b/dts/bindings/pinctrl/ite,it8xxx2-pinctrl.yaml index a68c1ab7fb7797..f052db2d67791d 100644 --- a/dts/bindings/pinctrl/ite,it8xxx2-pinctrl.yaml +++ b/dts/bindings/pinctrl/ite,it8xxx2-pinctrl.yaml @@ -64,32 +64,32 @@ compatible: "ite,it8xxx2-pinctrl" include: base.yaml child-binding: - description: | - This binding gives a base representation of the ITE IT8XXX2 pins configration. - - include: - - name: pincfg-node.yaml - property-allowlist: - - bias-high-impedance - - bias-pull-pin-default - - bias-pull-up - - bias-pull-down - - input-enable - - properties: - pinmuxs: - required: true - type: phandle-array - description: | - ITE IT8XXX2 pin's configuration (pinctrl node, pin and function). - - gpio-voltage: - type: string - description: | - Pin input voltage selection 3.3V or 1.8V. All gpio pins support 3.3V. - This property only needs to be configured if the board specifies a - pin as 1.8V. So the default is 3.3V - default: "3v3" - enum: - - "3v3" - - "1v8" + description: | + This binding gives a base representation of the ITE IT8XXX2 pins configration. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-high-impedance + - bias-pull-pin-default + - bias-pull-up + - bias-pull-down + - input-enable + + properties: + pinmuxs: + required: true + type: phandle-array + description: | + ITE IT8XXX2 pin's configuration (pinctrl node, pin and function). + + gpio-voltage: + type: string + description: | + Pin input voltage selection 3.3V or 1.8V. All gpio pins support 3.3V. + This property only needs to be configured if the board specifies a + pin as 1.8V. So the default is 3.3V + default: "3v3" + enum: + - "3v3" + - "1v8" diff --git a/dts/bindings/pinctrl/microchip,xec-pinctrl.yaml b/dts/bindings/pinctrl/microchip,xec-pinctrl.yaml index c6181383ba337e..1b35c5f186a031 100644 --- a/dts/bindings/pinctrl/microchip,xec-pinctrl.yaml +++ b/dts/bindings/pinctrl/microchip,xec-pinctrl.yaml @@ -66,61 +66,61 @@ compatible: "microchip,xec-pinctrl" include: base.yaml properties: - reg: - required: true + reg: + required: true child-binding: - description: | - This binding gives a base representation of the Microchip XEC pins - configuration - - include: - - name: pincfg-node.yaml - property-allowlist: - - bias-disable - - bias-pull-down - - bias-pull-up - - drive-push-pull - - drive-open-drain - - low-power-enable - - output-high - - output-low - - properties: - pinmux: - type: int - required: true - description: Pinmux selection - - slew-rate: - type: string - default: "low-speed" - enum: - - "low-speed" - - "high-speed" - description: | - Pin speed. The default value of slew-rate is the SoC power-on-reset - value. Please refer to the data sheet as a small number of pins - may have a different default and some pins do not implement - slew rate adjustment. - - drive-strength: - type: string - default: "1x" - enum: - - "1x" - - "2x" - - "4x" - - "6x" - description: | - Pin output drive strength for PIO and PIO-24 pin types. Default - is "1x" for most pins. PIO pins are 2, 4, 8, or 12 mA. PIO-24 pins - are 4, 8, 16, or 24 mA. Please refer to the data sheet for each - pin's PIO type and default drive strength. - - microchip,output-func-invert: - required: false - type: boolean - description: - Invert polarity of an output alternate function. Input functions - are not affected. + description: | + This binding gives a base representation of the Microchip XEC pins + configuration + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-down + - bias-pull-up + - drive-push-pull + - drive-open-drain + - low-power-enable + - output-high + - output-low + + properties: + pinmux: + type: int + required: true + description: Pinmux selection + + slew-rate: + type: string + default: "low-speed" + enum: + - "low-speed" + - "high-speed" + description: | + Pin speed. The default value of slew-rate is the SoC power-on-reset + value. Please refer to the data sheet as a small number of pins + may have a different default and some pins do not implement + slew rate adjustment. + + drive-strength: + type: string + default: "1x" + enum: + - "1x" + - "2x" + - "4x" + - "6x" + description: | + Pin output drive strength for PIO and PIO-24 pin types. Default + is "1x" for most pins. PIO pins are 2, 4, 8, or 12 mA. PIO-24 pins + are 4, 8, 16, or 24 mA. Please refer to the data sheet for each + pin's PIO type and default drive strength. + + microchip,output-func-invert: + required: false + type: boolean + description: + Invert polarity of an output alternate function. Input functions + are not affected. diff --git a/dts/bindings/pinctrl/microchip,xec-pinmux.yaml b/dts/bindings/pinctrl/microchip,xec-pinmux.yaml index b1c72e48b74d4f..ed5b6e0002cded 100644 --- a/dts/bindings/pinctrl/microchip,xec-pinmux.yaml +++ b/dts/bindings/pinctrl/microchip,xec-pinmux.yaml @@ -7,15 +7,15 @@ compatible: "microchip,xec-pinmux" include: base.yaml child-binding: - description: pinmux child node - properties: - ph-reg: - type: phandle - required: true + description: pinmux child node + properties: + ph-reg: + type: phandle + required: true - port-num: - type: int - required: true - description: | - Zero based GPIO port number. Pin group 000 - 036 is port 0, - 040 - 076 is port 1, etc. + port-num: + type: int + required: true + description: | + Zero based GPIO port number. Pin group 000 - 036 is port 0, + 040 - 076 is port 1, etc. diff --git a/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-conf.yaml b/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-conf.yaml index ed1cd709dd2c80..5451c4a633dba4 100644 --- a/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-conf.yaml +++ b/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-conf.yaml @@ -9,9 +9,9 @@ description: | compatible: "nuvoton,npcx-lvolctrl-conf" child-binding: - description: Child node to present the mapping between GPIO pad and its low-voltage support - properties: - lvols: - type: phandle-array - required: true - description: list of configurations map between io and low-voltage controllers + description: Child node to present the mapping between GPIO pad and its low-voltage support + properties: + lvols: + type: phandle-array + required: true + description: list of configurations map between io and low-voltage controllers diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml index ff319f509e9c7c..a7d0fd2d647f4c 100644 --- a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml +++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml @@ -8,9 +8,9 @@ description: | compatible: "nuvoton,npcx-pinctrl-conf" child-binding: - description: NPCX Pinmux configuration child node - properties: - alts: - type: phandle-array - required: true - description: A SCFG ALT (Alternative controllers) specifier for pinmuxing of npcx ec + description: NPCX Pinmux configuration child node + properties: + alts: + type: phandle-array + required: true + description: A SCFG ALT (Alternative controllers) specifier for pinmuxing of npcx ec diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml index 09e62fa7e66ba5..0087bb49f4ba07 100644 --- a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml +++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml @@ -8,7 +8,7 @@ compatible: "nuvoton,npcx-pinctrl-def" include: [base.yaml] properties: - pinmux: - type: phandles - required: true - description: list of configurations of pinmux controllers need to set + pinmux: + type: phandles + required: true + description: list of configurations of pinmux controllers need to set diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml index 5f2276886e2d84..962ecad5fa877d 100644 --- a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml +++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml @@ -43,56 +43,56 @@ compatible: "nuvoton,npcx-pinctrl" include: base.yaml child-binding: - description: | - NPCX pin controller pin configuration nodes + description: | + NPCX pin controller pin configuration nodes - include: - - name: pincfg-node.yaml - property-allowlist: - - bias-pull-down - - bias-pull-up - - drive-open-drain + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-pull-down + - bias-pull-up + - drive-open-drain - properties: - pinmux: - type: phandle - description: Configurations of pinmux selection - periph-pupd: - type: array - description: | - A map to PUPD_ENn register/bit that enable pull-up/down of NPCX peripheral devices. - Please don't overwrite this property in the board-level DT driver. - psl-offset: - type: int - description: | - Offset to PSL_CTS register that is used for PSL input's status and detection mode. - Please don't overwrite this property in the board-level DT driver. - psl-polarity: - type: phandle - description: | - A map to DEVALTn that configures detection polarity of PSL input pads. - Please don't overwrite this property in the board-level DT driver. - pinmux-locked: - type: boolean - description: Lock pinmux selection - pinmux-gpio: - type: boolean - description: Inverse pinmux selection to GPIO - psl-in-mode: - type: string - description: | - The assertion detection mode of PSL input selection - - "level": Select the detection mode to level detection - - "edge": Select the detection mode to edge detection - enum: - - "level" - - "edge" - psl-in-pol: - type: string - description: | - The assertion detection polarity of PSL input selection - - "low-falling": Select the detection polarity to low/falling - - "high-rising": Select the detection polarity to high/rising - enum: - - "low-falling" - - "high-rising" + properties: + pinmux: + type: phandle + description: Configurations of pinmux selection + periph-pupd: + type: array + description: | + A map to PUPD_ENn register/bit that enable pull-up/down of NPCX peripheral devices. + Please don't overwrite this property in the board-level DT driver. + psl-offset: + type: int + description: | + Offset to PSL_CTS register that is used for PSL input's status and detection mode. + Please don't overwrite this property in the board-level DT driver. + psl-polarity: + type: phandle + description: | + A map to DEVALTn that configures detection polarity of PSL input pads. + Please don't overwrite this property in the board-level DT driver. + pinmux-locked: + type: boolean + description: Lock pinmux selection + pinmux-gpio: + type: boolean + description: Inverse pinmux selection to GPIO + psl-in-mode: + type: string + description: | + The assertion detection mode of PSL input selection + - "level": Select the detection mode to level detection + - "edge": Select the detection mode to edge detection + enum: + - "level" + - "edge" + psl-in-pol: + type: string + description: | + The assertion detection polarity of PSL input selection + - "low-falling": Select the detection polarity to low/falling + - "high-rising": Select the detection polarity to high/rising + enum: + - "low-falling" + - "high-rising" diff --git a/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml b/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml index edbc952354cb7f..b8c881fbffa9be 100644 --- a/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml +++ b/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml @@ -8,25 +8,25 @@ compatible: "nuvoton,npcx-scfg" include: [base.yaml] properties: - reg: - required: true + reg: + required: true - "#alt-cells": - type: int - required: true - description: Number of items to expect in a SCFG ALT (Alternative controllers) specifier + "#alt-cells": + type: int + required: true + description: Number of items to expect in a SCFG ALT (Alternative controllers) specifier - "#lvol-cells": - type: int - required: true - description: | - Number of items to expect in a SCFG LV_GPIO_CTL (Low level IO controllers) specifier + "#lvol-cells": + type: int + required: true + description: | + Number of items to expect in a SCFG LV_GPIO_CTL (Low level IO controllers) specifier alt-cells: - - group - - bit - - inv + - group + - bit + - inv lvol-cells: - - ctrl - - bit + - ctrl + - bit diff --git a/dts/bindings/pinctrl/nuvoton,numicro-pinctrl.yaml b/dts/bindings/pinctrl/nuvoton,numicro-pinctrl.yaml index 0c4f6c7d5ee739..379aa67469295e 100644 --- a/dts/bindings/pinctrl/nuvoton,numicro-pinctrl.yaml +++ b/dts/bindings/pinctrl/nuvoton,numicro-pinctrl.yaml @@ -25,36 +25,36 @@ properties: required: true child-binding: - description: NuMicro pin controller pin group - child-binding: - description: | - NuMicro pin controller pin configuration node - include: - - name: pincfg-node.yaml - property-allowlist: - - bias-pull-down - - bias-pull-up - - drive-open-drain - - input-schmitt-enable - - input-disable - properties: - pinmux: - required: true - type: array - description: | - Pin mux selections for this group. See the SoC level pinctrl dtsi file - for a defined list of these options. - slew-rate: - default: "normal" - type: string - enum: - - "normal" - - "high" - - "fast" - description: | - Pin output slew rate. Sets the HSRENx register. If not set, defaults to the - reset value (normal). - input-debounce: - type: boolean - description: | - enable the input debounce function + description: NuMicro pin controller pin group + child-binding: + description: | + NuMicro pin controller pin configuration node + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-pull-down + - bias-pull-up + - drive-open-drain + - input-schmitt-enable + - input-disable + properties: + pinmux: + required: true + type: array + description: | + Pin mux selections for this group. See the SoC level pinctrl dtsi file + for a defined list of these options. + slew-rate: + default: "normal" + type: string + enum: + - "normal" + - "high" + - "fast" + description: | + Pin output slew rate. Sets the HSRENx register. If not set, defaults to the + reset value (normal). + input-debounce: + type: boolean + description: | + enable the input debounce function diff --git a/dts/bindings/pinctrl/nxp,imx-gpr.yaml b/dts/bindings/pinctrl/nxp,imx-gpr.yaml index 0549ceeee1f81b..f6944de8860b3a 100644 --- a/dts/bindings/pinctrl/nxp,imx-gpr.yaml +++ b/dts/bindings/pinctrl/nxp,imx-gpr.yaml @@ -8,8 +8,8 @@ compatible: "nxp,imx-gpr" include: base.yaml properties: - reg: - required: true + reg: + required: true pinmux-cells: - pin diff --git a/dts/bindings/pinctrl/nxp,imx-iomuxc.yaml b/dts/bindings/pinctrl/nxp,imx-iomuxc.yaml index 76af3245a70c1d..fa3e3927066860 100644 --- a/dts/bindings/pinctrl/nxp,imx-iomuxc.yaml +++ b/dts/bindings/pinctrl/nxp,imx-iomuxc.yaml @@ -13,11 +13,11 @@ description: | compatible: "nxp,imx-iomuxc" include: - - name: base.yaml + - name: base.yaml properties: - reg: - required: true + reg: + required: true child-binding: description: MCUX RT pin mux option diff --git a/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml b/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml index 361971bcd02683..d81e5a4ad8791f 100644 --- a/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml +++ b/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml @@ -5,11 +5,11 @@ compatible: "nxp,kinetis-pinmux" include: base.yaml properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true child-binding: include: pincfg-node.yaml diff --git a/dts/bindings/pinctrl/nxp,lpc-iocon-pinctrl.yaml b/dts/bindings/pinctrl/nxp,lpc-iocon-pinctrl.yaml index 80ed7f8e856b55..f36b941c17b150 100644 --- a/dts/bindings/pinctrl/nxp,lpc-iocon-pinctrl.yaml +++ b/dts/bindings/pinctrl/nxp,lpc-iocon-pinctrl.yaml @@ -102,8 +102,8 @@ child-binding: power-source: type: string enum: - - "3v3" - - "1v8" + - "3v3" + - "1v8" description: | Pin output power source. Only valid for I2C mode pins running in I2C mode. @@ -114,16 +114,16 @@ child-binding: nxp,i2c-filter: type: string enum: - - "slow" - - "fast" + - "slow" + - "fast" description: | I2C glitch filter speed. Only valid for I2C mode pins. Fast mode typically only required for High speed I2C. nxp,i2c-speed: type: string enum: - - "slow" - - "fast" + - "slow" + - "fast" description: | I2C speed. Only valid for I2C mode pins. Fast mode should be used for fast mode plus I2C. diff --git a/dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml b/dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml index 85704153258e92..cc9701db526ed6 100644 --- a/dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml +++ b/dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml @@ -8,5 +8,5 @@ compatible: "nxp,lpc-iocon-pio" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/pinctrl/nxp,lpc-iocon.yaml b/dts/bindings/pinctrl/nxp,lpc-iocon.yaml index 62d5a2bd561da8..e41ae319dd4ab2 100644 --- a/dts/bindings/pinctrl/nxp,lpc-iocon.yaml +++ b/dts/bindings/pinctrl/nxp,lpc-iocon.yaml @@ -8,5 +8,5 @@ compatible: "nxp,lpc-iocon" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml b/dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml index 312310b105328e..b6a3d7f12bc02f 100644 --- a/dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml +++ b/dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml @@ -8,14 +8,14 @@ compatible: "nxp,lpc11u6x-pinmux" include: base.yaml properties: - reg: - required: true + reg: + required: true - "#pinmux-cells": - type: int - required: true - const: 2 - description: number of items in a pinmux specifier + "#pinmux-cells": + type: int + required: true + const: 2 + description: number of items in a pinmux specifier pinmux-cells: - pin diff --git a/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml b/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml index 87f49b6d5f3483..436531c8db099e 100644 --- a/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml +++ b/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml @@ -5,11 +5,11 @@ compatible: "openisa,rv32m1-pinmux" include: base.yaml properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true pinmux-cells: - pin diff --git a/dts/bindings/pinctrl/renesas,rcar-pfc.yaml b/dts/bindings/pinctrl/renesas,rcar-pfc.yaml index 5d14b574d96b6d..fa94cd11c05eb1 100644 --- a/dts/bindings/pinctrl/renesas,rcar-pfc.yaml +++ b/dts/bindings/pinctrl/renesas,rcar-pfc.yaml @@ -68,8 +68,8 @@ compatible: "renesas,rcar-pfc" include: base.yaml properties: - reg: - required: true + reg: + required: true child-binding: description: | diff --git a/dts/bindings/pinctrl/sifive,pinctrl.yaml b/dts/bindings/pinctrl/sifive,pinctrl.yaml index 41acb79e175919..67863e16aa4955 100644 --- a/dts/bindings/pinctrl/sifive,pinctrl.yaml +++ b/dts/bindings/pinctrl/sifive,pinctrl.yaml @@ -30,8 +30,8 @@ compatible: "sifive,pinctrl" include: base.yaml properties: - reg: - required: true + reg: + required: true child-binding: description: | diff --git a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml index 3e76bd9791e51d..cfc1c2a6fa75c1 100644 --- a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -14,91 +14,91 @@ compatible: "st,stm32-pinctrl" include: base.yaml properties: - reg: - required: true + reg: + required: true - remap-pa11: - type: boolean - description: Remaps the PA11 pin to operate as PA9 pin. - Use of this property is restricted to STM32G0 SoCs. + remap-pa11: + type: boolean + description: Remaps the PA11 pin to operate as PA9 pin. + Use of this property is restricted to STM32G0 SoCs. - remap-pa12: - type: boolean - description: Remaps the PA12 pin to operate as PA10 pin. - Use of this property is restricted to STM32G0 SoCs. + remap-pa12: + type: boolean + description: Remaps the PA12 pin to operate as PA10 pin. + Use of this property is restricted to STM32G0 SoCs. - remap-pa11-pa12: - type: boolean - description: Remaps the PA11/PA12 pin to operate as PA9/PA10 pin. - Use of this property is restricted to STM32F070x SoCs. + remap-pa11-pa12: + type: boolean + description: Remaps the PA11/PA12 pin to operate as PA9/PA10 pin. + Use of this property is restricted to STM32F070x SoCs. child-binding: - description: | - This binding gives a base representation of the STM32 pins configration + description: | + This binding gives a base representation of the STM32 pins configration - include: - - name: pincfg-node.yaml - property-allowlist: - - bias-disable - - bias-pull-down - - bias-pull-up - - drive-push-pull - - drive-open-drain - - output-low - - output-high + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-down + - bias-pull-up + - drive-push-pull + - drive-open-drain + - output-low + - output-high - properties: - pinmux: - required: true - type: int - description: | - Reused from - https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml - Integer array, represents gpio pin number and mux setting. - These defines are calculated as: ((port * 16 + line) << 8) | function - With: - - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) - - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) - - function: The function number, can be: - * 0 : Alternate Function 0 - * 1 : Alternate Function 1 - * 2 : Alternate Function 2 - * ... - * 15 : Alternate Function 15 - * 16 : Analog - * 17 : GPIO - In case selected pin function is GPIO, pin is statically configured as - a plain input/output GPIO. Default configuration is input. Output value - can be configured by adding 'ouptut-low' or 'output-high' properties - to the pin configuration. + properties: + pinmux: + required: true + type: int + description: | + Reused from + https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml + Integer array, represents gpio pin number and mux setting. + These defines are calculated as: ((port * 16 + line) << 8) | function + With: + - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) + - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) + - function: The function number, can be: + * 0 : Alternate Function 0 + * 1 : Alternate Function 1 + * 2 : Alternate Function 2 + * ... + * 15 : Alternate Function 15 + * 16 : Analog + * 17 : GPIO + In case selected pin function is GPIO, pin is statically configured as + a plain input/output GPIO. Default configuration is input. Output value + can be configured by adding 'ouptut-low' or 'output-high' properties + to the pin configuration. - To simplify the usage, macro is available to generate "pinmux" field. - This macro is available here: - -include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h - Some examples of macro usage: - GPIO A9 set as alernate function 2 - ... { - pinmux = ; - }; - GPIO A9 set as analog - ... { - pinmux = ; - }; - GPIO A9 set as GPIO output high - ... { - pinmux = ; - output-high; - }; + To simplify the usage, macro is available to generate "pinmux" field. + This macro is available here: + -include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h + Some examples of macro usage: + GPIO A9 set as alernate function 2 + ... { + pinmux = ; + }; + GPIO A9 set as analog + ... { + pinmux = ; + }; + GPIO A9 set as GPIO output high + ... { + pinmux = ; + output-high; + }; - slew-rate: - type: string - default: "low-speed" - enum: - - "low-speed" # Default value. - - "medium-speed" - - "high-speed" - - "very-high-speed" - description: | - Pin speed. Default to low-speed. For few pins (PA11 and - PB3 depending on SoCs)hardware reset value could differ - (very-high-speed). Carefully check reference manual for these pins. + slew-rate: + type: string + default: "low-speed" + enum: + - "low-speed" # Default value. + - "medium-speed" + - "high-speed" + - "very-high-speed" + description: | + Pin speed. Default to low-speed. For few pins (PA11 and + PB3 depending on SoCs)hardware reset value could differ + (very-high-speed). Carefully check reference manual for these pins. diff --git a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml index 2ebe2d529a4e84..f96b3c123ea0b7 100644 --- a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml +++ b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml @@ -14,102 +14,102 @@ compatible: "st,stm32f1-pinctrl" include: base.yaml properties: - reg: - required: true + reg: + required: true - swj-cfg: - type: string - default: "full" # reset state - enum: - - "full" - - "no-njtrst" - - "jtag-disable" - - "disable" - description: | - Configures number of pins assigned to the SWJ debug port. + swj-cfg: + type: string + default: "full" # reset state + enum: + - "full" + - "no-njtrst" + - "jtag-disable" + - "disable" + description: | + Configures number of pins assigned to the SWJ debug port. - * full - Full SWJ (JTAG-DP + SW-DP). - * no-njtrst - Full SWJ (JTAG-DP + SW-DP) but without NJTRST. - Releases: PB4. - * jtag-disable - JTAG-DP Disabled and SW-DP Enabled. - Releases: PA15 PB3 PB4. - * disable - JTAG-DP Disabled and SW-DP Disabled. - Releases: PA13 PA14 PA15 PB3 PB4. + * full - Full SWJ (JTAG-DP + SW-DP). + * no-njtrst - Full SWJ (JTAG-DP + SW-DP) but without NJTRST. + Releases: PB4. + * jtag-disable - JTAG-DP Disabled and SW-DP Enabled. + Releases: PA15 PB3 PB4. + * disable - JTAG-DP Disabled and SW-DP Disabled. + Releases: PA13 PA14 PA15 PB3 PB4. - If absent, then Full SWJ (JTAG-DP + SW-DP) is used (reset state). + If absent, then Full SWJ (JTAG-DP + SW-DP) is used (reset state). child-binding: - description: | - This binding gives a base representation of the STM32F1 pins - configration + description: | + This binding gives a base representation of the STM32F1 pins + configration - include: - - name: pincfg-node.yaml - property-allowlist: - - bias-disable - - bias-pull-down - - bias-pull-up - - drive-push-pull - - drive-open-drain - - output-low - - output-high + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-down + - bias-pull-up + - drive-push-pull + - drive-open-drain + - output-low + - output-high - properties: - pinmux: - required: true - type: int - description: | - Adapted from - https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml - Integer array, represents gpio pin number and mux setting. - These defines are calculated as: ((port * 16 + line) << 8) | (function << 6) | remap) - With: - - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) - - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) - - function: The configuration mode, can be: - * 0 : Alternate function output - * 1 : Input - * 2 : Analog - * 3 : GPIO output - In case selected pin function is GPIO output, pin is statically configured as - a plain output GPIO, which configuration can be set by adding 'ouptut-low' or - 'output-high' properties to the pinctrl configuration. Default is output-low. - - remap: The pin remapping configuration. It allows to assign the pin - function to a different peripheral. Remain configuration can be: - * 0 : No remap - * 1 : Partial remap 1 - * 2 : Partial remap 2 - * 3 : Partial remap 3 - * 4 : Full remap - To simplify the usage, macro is available to generate "pinmux" field. - This macro is available here: - -include/zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h - Some examples of macro usage: - GPIO A9 set as alernate with no remap - ... { - pinmux = ; - }; - GPIO A9 set as alernate with full remap - ... { - pinmux = ; - }; - GPIO A9 set as input - ... { - pinmux = ; - }; - GPIO A9 set as output-high - ... { - pinmux = ; - output-high; - }; + properties: + pinmux: + required: true + type: int + description: | + Adapted from + https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml + Integer array, represents gpio pin number and mux setting. + These defines are calculated as: ((port * 16 + line) << 8) | (function << 6) | remap) + With: + - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) + - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) + - function: The configuration mode, can be: + * 0 : Alternate function output + * 1 : Input + * 2 : Analog + * 3 : GPIO output + In case selected pin function is GPIO output, pin is statically configured as + a plain output GPIO, which configuration can be set by adding 'ouptut-low' or + 'output-high' properties to the pinctrl configuration. Default is output-low. + - remap: The pin remapping configuration. It allows to assign the pin + function to a different peripheral. Remain configuration can be: + * 0 : No remap + * 1 : Partial remap 1 + * 2 : Partial remap 2 + * 3 : Partial remap 3 + * 4 : Full remap + To simplify the usage, macro is available to generate "pinmux" field. + This macro is available here: + -include/zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h + Some examples of macro usage: + GPIO A9 set as alernate with no remap + ... { + pinmux = ; + }; + GPIO A9 set as alernate with full remap + ... { + pinmux = ; + }; + GPIO A9 set as input + ... { + pinmux = ; + }; + GPIO A9 set as output-high + ... { + pinmux = ; + output-high; + }; - slew-rate: - type: string - default: "max-speed-10mhz" - enum: - - "max-speed-10mhz" # Default - - "max-speed-2mhz" - - "max-speed-50mhz" - description: | - Pin output mode, maximum achievable speed. Only applies to - output mode (alternate). + slew-rate: + type: string + default: "max-speed-10mhz" + enum: + - "max-speed-10mhz" # Default + - "max-speed-2mhz" + - "max-speed-50mhz" + description: | + Pin output mode, maximum achievable speed. Only applies to + output mode (alternate). diff --git a/dts/bindings/pinctrl/telink,b91-pinctrl.yaml b/dts/bindings/pinctrl/telink,b91-pinctrl.yaml index dc0af310dc5586..2c19c46a0804e7 100644 --- a/dts/bindings/pinctrl/telink,b91-pinctrl.yaml +++ b/dts/bindings/pinctrl/telink,b91-pinctrl.yaml @@ -66,35 +66,35 @@ compatible: "telink,b91-pinctrl" include: base.yaml properties: - reg: - required: true + reg: + required: true - pad-mul-sel: - type: int - required: true - description: | - PinMux pad_mul_sel register value. Pin functions depend on it. + pad-mul-sel: + type: int + required: true + description: | + PinMux pad_mul_sel register value. Pin functions depend on it. - For instance: - Function C of PB2 configs the pin to UART0_TX if pad_mul_sel is set to <1>. - But, the same function configs the same pin to DAC_I_DAT2_I if pad_mul_sel is set to <0>. + For instance: + Function C of PB2 configs the pin to UART0_TX if pad_mul_sel is set to <1>. + But, the same function configs the same pin to DAC_I_DAT2_I if pad_mul_sel is set to <0>. - Refer to the Telink TLSR9 specs to get more information about pins configuration. + Refer to the Telink TLSR9 specs to get more information about pins configuration. child-binding: - description: | - This binding gives a base representation of the Telink B91 pins configration. + description: | + This binding gives a base representation of the Telink B91 pins configration. - include: - - name: pincfg-node.yaml - property-allowlist: - - bias-disable - - bias-pull-down - - bias-pull-up + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-down + - bias-pull-up - properties: - pinmux: - required: true - type: int - description: | - Telink B91 pin's configuration (port, pin and function). + properties: + pinmux: + required: true + type: int + description: | + Telink B91 pin's configuration (port, pin and function). diff --git a/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml b/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml index 813979057fe58a..5c78d9c561eeb2 100644 --- a/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml +++ b/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml @@ -62,8 +62,8 @@ compatible: "ti,cc13xx-cc26xx-pinctrl" include: base.yaml properties: - reg: - required: true + reg: + required: true child-binding: description: | diff --git a/dts/bindings/power-domain/intel,adsp-power-domain.yaml b/dts/bindings/power-domain/intel,adsp-power-domain.yaml index 7bbb45b37f4909..70bf2a2c1ba81e 100644 --- a/dts/bindings/power-domain/intel,adsp-power-domain.yaml +++ b/dts/bindings/power-domain/intel,adsp-power-domain.yaml @@ -9,11 +9,11 @@ compatible: "intel,adsp-power-domain" include: power-domain.yaml properties: - bit-position: - type: int - required: true - description: | - Position of the bit to set in write_address (PWRCTL) or read in - read_address (PWRSTS) to set power active or confirm power active - for a desired domain. - Same for write and read addresses + bit-position: + type: int + required: true + description: | + Position of the bit to set in write_address (PWRCTL) or read in + read_address (PWRSTS) to set power active or confirm power active + for a desired domain. + Same for write and read addresses diff --git a/dts/bindings/power/nordic,nrf-power.yaml b/dts/bindings/power/nordic,nrf-power.yaml index fbc38c33aecfd8..9a138e7ff74796 100644 --- a/dts/bindings/power/nordic,nrf-power.yaml +++ b/dts/bindings/power/nordic,nrf-power.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-power" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/power/nordic,nrf-regulators.yaml b/dts/bindings/power/nordic,nrf-regulators.yaml index ecfa6b1befbd70..bb25b41e3b28da 100644 --- a/dts/bindings/power/nordic,nrf-regulators.yaml +++ b/dts/bindings/power/nordic,nrf-regulators.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-regulators" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/power/nordic,nrf-usbreg.yaml b/dts/bindings/power/nordic,nrf-usbreg.yaml index cf4ddbc1e016ce..7e2eb47edf3257 100644 --- a/dts/bindings/power/nordic,nrf-usbreg.yaml +++ b/dts/bindings/power/nordic,nrf-usbreg.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-usbreg" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/power/nordic,nrf-vmc.yaml b/dts/bindings/power/nordic,nrf-vmc.yaml index 9ed6fa584c2404..9f37384a73161f 100644 --- a/dts/bindings/power/nordic,nrf-vmc.yaml +++ b/dts/bindings/power/nordic,nrf-vmc.yaml @@ -8,5 +8,5 @@ compatible: "nordic,nrf-vmc" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/power/telink,b91-power.yaml b/dts/bindings/power/telink,b91-power.yaml index 7132f9d0272760..076ee5981af268 100644 --- a/dts/bindings/power/telink,b91-power.yaml +++ b/dts/bindings/power/telink,b91-power.yaml @@ -8,20 +8,20 @@ compatible: "telink,b91-power" include: base.yaml properties: - reg: - required: true + reg: + required: true - power-mode: - type: string - required: true - enum: - - "LDO_1P4_LDO_1P8" - - "DCDC_1P4_LDO_1P8" - - "DCDC_1P4_DCDC_1P8" + power-mode: + type: string + required: true + enum: + - "LDO_1P4_LDO_1P8" + - "DCDC_1P4_LDO_1P8" + - "DCDC_1P4_DCDC_1P8" - vbat-type: - type: string - required: true - enum: - - "VBAT_MAX_VALUE_LESS_THAN_3V6" - - "VBAT_MAX_VALUE_GREATER_THAN_3V6" + vbat-type: + type: string + required: true + enum: + - "VBAT_MAX_VALUE_LESS_THAN_3V6" + - "VBAT_MAX_VALUE_GREATER_THAN_3V6" diff --git a/dts/bindings/power/zephyr,power-state.yaml b/dts/bindings/power/zephyr,power-state.yaml index f5028f0f8954bb..5c645306b58a12 100644 --- a/dts/bindings/power/zephyr,power-state.yaml +++ b/dts/bindings/power/zephyr,power-state.yaml @@ -6,28 +6,28 @@ description: Properties for power management state compatible: "zephyr,power-state" properties: - power-state-name: - type: string - required: true - description: indicates a power state - enum: - - "active" - - "runtime-idle" - - "suspend-to-idle" - - "standby" - - "suspend-to-ram" - - "suspend-to-disk" - - "soft-off" - substate-id: - type: int - description: Platform specific identification. - min-residency-us: - type: int - description: | - Minimum residency duration in microseconds. It is the minimum time for a - given idle state to be worthwhile energywise. It includes the time to enter - in this state. - exit-latency-us: - type: int - description: | - Worst case latency in microseconds required to exit the idle state. + power-state-name: + type: string + required: true + description: indicates a power state + enum: + - "active" + - "runtime-idle" + - "suspend-to-idle" + - "standby" + - "suspend-to-ram" + - "suspend-to-disk" + - "soft-off" + substate-id: + type: int + description: Platform specific identification. + min-residency-us: + type: int + description: | + Minimum residency duration in microseconds. It is the minimum time for a + given idle state to be worthwhile energywise. It includes the time to enter + in this state. + exit-latency-us: + type: int + description: | + Worst case latency in microseconds required to exit the idle state. diff --git a/dts/bindings/ps2/microchip,xec-ps2.yaml b/dts/bindings/ps2/microchip,xec-ps2.yaml index 717e5d4707dc1b..0480b5ed05969b 100644 --- a/dts/bindings/ps2/microchip,xec-ps2.yaml +++ b/dts/bindings/ps2/microchip,xec-ps2.yaml @@ -8,20 +8,20 @@ compatible: "microchip,xec-ps2" include: [ps2.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - girqs: - type: array - required: true - description: | - Array of GIRQ and bit position pairs for each interrupt - signal the block generates. + girqs: + type: array + required: true + description: | + Array of GIRQ and bit position pairs for each interrupt + signal the block generates. - pcrs: - type: array - required: true - description: PS2 PCR register index and bit position + pcrs: + type: array + required: true + description: PS2 PCR register index and bit position diff --git a/dts/bindings/ps2/nuvoton,npcx-ps2-channel.yaml b/dts/bindings/ps2/nuvoton,npcx-ps2-channel.yaml index c66785e3afe15c..8bd6140e72f4a8 100644 --- a/dts/bindings/ps2/nuvoton,npcx-ps2-channel.yaml +++ b/dts/bindings/ps2/nuvoton,npcx-ps2-channel.yaml @@ -8,13 +8,13 @@ compatible: "nuvoton,npcx-ps2-channel" include: [base.yaml, pinctrl-device.yaml] properties: - channel: - type: int - required: true - description: index of i2c channel + channel: + type: int + required: true + description: index of i2c channel - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml b/dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml index f1571235f75e85..40cae9790d37ae 100644 --- a/dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml +++ b/dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml @@ -10,11 +10,11 @@ include: base.yaml bus: ps2 properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/ps2/ps2.yaml b/dts/bindings/ps2/ps2.yaml index f91352974e4bc7..f234073255a403 100644 --- a/dts/bindings/ps2/ps2.yaml +++ b/dts/bindings/ps2/ps2.yaml @@ -8,11 +8,11 @@ include: base.yaml bus: ps2 properties: - "#address-cells": - type: int - required: true - const: 1 - "#size-cells": - type: int - required: true - const: 0 + "#address-cells": + type: int + required: true + const: 1 + "#size-cells": + type: int + required: true + const: 0 diff --git a/dts/bindings/pwm/atmel,sam-pwm.yaml b/dts/bindings/pwm/atmel,sam-pwm.yaml index 034811802023d5..11b175887c139b 100644 --- a/dts/bindings/pwm/atmel,sam-pwm.yaml +++ b/dts/bindings/pwm/atmel,sam-pwm.yaml @@ -6,34 +6,34 @@ description: Atmel SAM PWM compatible: "atmel,sam-pwm" include: - - name: base.yaml - - name: pwm-controller.yaml - - name: pinctrl-device.yaml + - name: base.yaml + - name: pwm-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true - prescaler: - type: int - required: true - description: Clock prescaler at the input of the PWM (0 to 10) + prescaler: + type: int + required: true + description: Clock prescaler at the input of the PWM (0 to 10) - divider: - type: int - required: true - description: Clock divider at the input of the PWM (1 to 255) + divider: + type: int + required: true + description: Clock divider at the input of the PWM (1 to 255) - "#pwm-cells": - const: 3 + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml b/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml index 6a21468ae8456a..358528f47ef22e 100644 --- a/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml +++ b/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml @@ -6,9 +6,9 @@ description: Atmel SAM0 TCC in PWM mode compatible: "atmel,sam0-tcc-pwm" include: - - name: base.yaml - - name: pwm-controller.yaml - - name: pinctrl-device.yaml + - name: base.yaml + - name: pwm-controller.yaml + - name: pinctrl-device.yaml properties: reg: diff --git a/dts/bindings/pwm/espressif,esp32-ledc.yaml b/dts/bindings/pwm/espressif,esp32-ledc.yaml index 53c5822555bc66..9678146eb5e772 100644 --- a/dts/bindings/pwm/espressif,esp32-ledc.yaml +++ b/dts/bindings/pwm/espressif,esp32-ledc.yaml @@ -131,6 +131,6 @@ child-binding: one of four high-speed/low-speed timers. pwm-cells: - - channel - - period - - flags +- channel +- period +- flags diff --git a/dts/bindings/pwm/fsl,imx27-pwm.yaml b/dts/bindings/pwm/fsl,imx27-pwm.yaml index a4c6c774cfe968..10bf3e99393ee6 100644 --- a/dts/bindings/pwm/fsl,imx27-pwm.yaml +++ b/dts/bindings/pwm/fsl,imx27-pwm.yaml @@ -13,24 +13,24 @@ compatible: "fsl,imx27-pwm" include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - prescaler: - type: int - required: true - description: Set the PWM prescale between 0 and 4096 + prescaler: + type: int + required: true + description: Set the PWM prescale between 0 and 4096 - rdc: - type: int - required: true - description: Set the RDC permission for this peripheral + rdc: + type: int + required: true + description: Set the RDC permission for this peripheral - "#pwm-cells": - const: 2 + "#pwm-cells": + const: 2 pwm-cells: - channel diff --git a/dts/bindings/pwm/ite,it8xxx2-pwm.yaml b/dts/bindings/pwm/ite,it8xxx2-pwm.yaml index 93787ccc047288..cec7b6c0d0134b 100644 --- a/dts/bindings/pwm/ite,it8xxx2-pwm.yaml +++ b/dts/bindings/pwm/ite,it8xxx2-pwm.yaml @@ -8,49 +8,49 @@ compatible: "ite,it8xxx2-pwm" include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - channel: - type: int - required: true - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - description: | - 0 = PWM_CHANNEL_0, 1 = PWM_CHANNEL_1, 2 = PWM_CHANNEL_2, - 3 = PWM_CHANNEL_3, 4 = PWM_CHANNEL_4, 5 = PWM_CHANNEL_5, - 6 = PWM_CHANNEL_6, 7 = PWM_CHANNEL_7 - - pwmctrl: - type: phandle - required: true - description: PWM prescaler controller - - prescaler-cx: - type: int - required: true - enum: - - 1 - - 2 - - 3 - description: 1 = PWM_PRESCALER_C4, 2 = PWM_PRESCALER_C6, 3 = PWM_PRESCALER_C7 - - pwm-output-frequency: - type: int - description: PWM output frequency for operation - - pinctrl-0: - required: true - - pinctrl-names: - required: true + reg: + required: true + + channel: + type: int + required: true + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + description: | + 0 = PWM_CHANNEL_0, 1 = PWM_CHANNEL_1, 2 = PWM_CHANNEL_2, + 3 = PWM_CHANNEL_3, 4 = PWM_CHANNEL_4, 5 = PWM_CHANNEL_5, + 6 = PWM_CHANNEL_6, 7 = PWM_CHANNEL_7 + + pwmctrl: + type: phandle + required: true + description: PWM prescaler controller + + prescaler-cx: + type: int + required: true + enum: + - 1 + - 2 + - 3 + description: 1 = PWM_PRESCALER_C4, 2 = PWM_PRESCALER_C6, 3 = PWM_PRESCALER_C7 + + pwm-output-frequency: + type: int + description: PWM output frequency for operation + + pinctrl-0: + required: true + + pinctrl-names: + required: true pwm-cells: - channel diff --git a/dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml b/dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml index 4d102a8409f675..28a87358af9732 100644 --- a/dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml +++ b/dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml @@ -8,5 +8,5 @@ compatible: "ite,it8xxx2-pwmprs" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/pwm/litex,pwm.yaml b/dts/bindings/pwm/litex,pwm.yaml index 168ba477340384..713483516b7603 100644 --- a/dts/bindings/pwm/litex,pwm.yaml +++ b/dts/bindings/pwm/litex,pwm.yaml @@ -11,11 +11,11 @@ include: [pwm-controller.yaml, base.yaml] compatible: "litex,pwm" properties: - reg: - required: true + reg: + required: true - "#pwm-cells": - const: 2 + "#pwm-cells": + const: 2 pwm-cells: - channel diff --git a/dts/bindings/pwm/microchip,xec-pwm.yaml b/dts/bindings/pwm/microchip,xec-pwm.yaml index 5ec88c8b0bb951..c05f83c21ee273 100644 --- a/dts/bindings/pwm/microchip,xec-pwm.yaml +++ b/dts/bindings/pwm/microchip,xec-pwm.yaml @@ -8,17 +8,17 @@ include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] compatible: "microchip,xec-pwm" properties: - reg: - required: true + reg: + required: true - pcrs: - type: array - required: true - description: PWM PCR register index and bit position + pcrs: + type: array + required: true + description: PWM PCR register index and bit position - "#pwm-cells": - const: 2 + "#pwm-cells": + const: 2 pwm-cells: - - channel - - period + - channel + - period diff --git a/dts/bindings/pwm/nordic,nrf-pwm.yaml b/dts/bindings/pwm/nordic,nrf-pwm.yaml index ee84ba904e3475..c0bd362caa1977 100644 --- a/dts/bindings/pwm/nordic,nrf-pwm.yaml +++ b/dts/bindings/pwm/nordic,nrf-pwm.yaml @@ -5,108 +5,108 @@ compatible: "nordic,nrf-pwm" include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - center-aligned: - type: boolean - description: Set this to use center-aligned (up and down) counter mode. - - ch0-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The channel 0 pin to use. - - For pins P0.0 through P0.31, use the pin number. For example, - to use P0.16 for channel 0, set: - - ch0-pin = <16>; - - For pins P1.0 through P1.31, add 32 to the pin number. For - example, to use P1.2 for channel 0, set: - - ch0-pin = <34>; /* 32 + 2 */ - - ch0-inverted: - type: boolean - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - When the pin control driver is enabled, use the "nordic,invert" property - in the corresponding pin configuration group instead. - - Set this to invert channel 0. - - ch1-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The channel 1 pin to use. The pin numbering scheme is the same - as the ch0-pin property's. - - ch1-inverted: - type: boolean - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - When the pin control driver is enabled, use the "nordic,invert" property - in the corresponding pin configuration group instead. - - Set this to invert channel 1. - - ch2-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The channel 2 pin to use. The pin numbering scheme is the same - as the ch0-pin property's. - - ch2-inverted: - type: boolean - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - When the pin control driver is enabled, use the "nordic,invert" property - in the corresponding pin configuration group instead. - - Set this to invert channel 2. - - ch3-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The channel 3 pin to use. The pin numbering scheme is the same - as the ch0-pin property's. - - ch3-inverted: - type: boolean - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - When the pin control driver is enabled, use the "nordic,invert" property - in the corresponding pin configuration group instead. - - Set this to invert channel 3. - - "#pwm-cells": - const: 3 + reg: + required: true + + center-aligned: + type: boolean + description: Set this to use center-aligned (up and down) counter mode. + + ch0-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The channel 0 pin to use. + + For pins P0.0 through P0.31, use the pin number. For example, + to use P0.16 for channel 0, set: + + ch0-pin = <16>; + + For pins P1.0 through P1.31, add 32 to the pin number. For + example, to use P1.2 for channel 0, set: + + ch0-pin = <34>; /* 32 + 2 */ + + ch0-inverted: + type: boolean + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + When the pin control driver is enabled, use the "nordic,invert" property + in the corresponding pin configuration group instead. + + Set this to invert channel 0. + + ch1-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The channel 1 pin to use. The pin numbering scheme is the same + as the ch0-pin property's. + + ch1-inverted: + type: boolean + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + When the pin control driver is enabled, use the "nordic,invert" property + in the corresponding pin configuration group instead. + + Set this to invert channel 1. + + ch2-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The channel 2 pin to use. The pin numbering scheme is the same + as the ch0-pin property's. + + ch2-inverted: + type: boolean + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + When the pin control driver is enabled, use the "nordic,invert" property + in the corresponding pin configuration group instead. + + Set this to invert channel 2. + + ch3-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The channel 3 pin to use. The pin numbering scheme is the same + as the ch0-pin property's. + + ch3-inverted: + type: boolean + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + When the pin control driver is enabled, use the "nordic,invert" property + in the corresponding pin configuration group instead. + + Set this to invert channel 3. + + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml b/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml index 56bddda1dd2102..6eda67ecaa232a 100644 --- a/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml +++ b/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml @@ -5,56 +5,56 @@ compatible: "nordic,nrf-sw-pwm" include: [pwm-controller.yaml, base.yaml] properties: - generator: - type: phandle - required: true - description: | - Reference to TIMER or RTC instance for generating PWM output signals - - clock-prescaler: - type: int - required: true - description: | - Clock prescaler for RTC or TIMER used for generating PWM output signals. - - RTC: needs to be set to 0, which gives 32768 Hz base clock for PWM - generation. - - TIMER: 16 MHz / 2^prescaler base clock is used for PWM generation. - - channel-gpios: - type: phandle-array - required: true - description: | - An array of GPIOs assigned as outputs for the PWM channels. The number - of items in this array determines the number of channels that this PWM - will provide. This value is limited by the number of compare registers - in the used RTC/TIMER instance minus 1. - - Example: - - sw_pwm: sw-pwm { - compatible = "nordic,nrf-sw-pwm"; - ... - channel-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>, - <&gpio1 12 GPIO_ACTIVE_HIGH>; - ... - }; - - The above will assign P0.20 as the output for channel 0 and P1.12 as - the output for channel 1. Both outputs will be initially configured as - active high. - - Please note that in the flags cell (the last component of each item - of the array) only the GPIO flags that specify the active level are - taken into account (any others are ignored), and they are used only - when the initial (inactive) state of the outputs is set. - After any PWM signal generation is requested for a given channel, - the polarity of its output is determined by the flag specified - in the request, i.e. PWM_POLARITY_INVERTED or PWM_POLARITY_NORMAL. - - "#pwm-cells": - const: 3 + generator: + type: phandle + required: true + description: | + Reference to TIMER or RTC instance for generating PWM output signals + + clock-prescaler: + type: int + required: true + description: | + Clock prescaler for RTC or TIMER used for generating PWM output signals. + + RTC: needs to be set to 0, which gives 32768 Hz base clock for PWM + generation. + + TIMER: 16 MHz / 2^prescaler base clock is used for PWM generation. + + channel-gpios: + type: phandle-array + required: true + description: | + An array of GPIOs assigned as outputs for the PWM channels. The number + of items in this array determines the number of channels that this PWM + will provide. This value is limited by the number of compare registers + in the used RTC/TIMER instance minus 1. + + Example: + + sw_pwm: sw-pwm { + compatible = "nordic,nrf-sw-pwm"; + ... + channel-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>, + <&gpio1 12 GPIO_ACTIVE_HIGH>; + ... + }; + + The above will assign P0.20 as the output for channel 0 and P1.12 as + the output for channel 1. Both outputs will be initially configured as + active high. + + Please note that in the flags cell (the last component of each item + of the array) only the GPIO flags that specify the active level are + taken into account (any others are ignored), and they are used only + when the initial (inactive) state of the outputs is set. + After any PWM signal generation is requested for a given channel, + the polarity of its output is determined by the flag specified + in the request, i.e. PWM_POLARITY_INVERTED or PWM_POLARITY_NORMAL. + + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/nuvoton,npcx-pwm.yaml b/dts/bindings/pwm/nuvoton,npcx-pwm.yaml index a72edcb840e4ad..678dd110978651 100644 --- a/dts/bindings/pwm/nuvoton,npcx-pwm.yaml +++ b/dts/bindings/pwm/nuvoton,npcx-pwm.yaml @@ -8,29 +8,29 @@ compatible: "nuvoton,npcx-pwm" include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] properties: - reg: - required: true - clocks: - required: true - pinctrl-0: - required: true - pinctrl-names: - required: true - pwm-channel: - type: int - description: | - A index to indicate PWM module that generates a single PWM signal. - Please don't overwrite it in the board-level DT driver. - clock-bus: - type: string - description: | - Select a specific input clock source for the PWM module. If this - property doesn't exist, fallback to default value in clocks property. - enum: - - NPCX_CLOCK_BUS_APB2 - - NPCX_CLOCK_BUS_LFCLK + reg: + required: true + clocks: + required: true + pinctrl-0: + required: true + pinctrl-names: + required: true + pwm-channel: + type: int + description: | + A index to indicate PWM module that generates a single PWM signal. + Please don't overwrite it in the board-level DT driver. + clock-bus: + type: string + description: | + Select a specific input clock source for the PWM module. If this + property doesn't exist, fallback to default value in clocks property. + enum: + - NPCX_CLOCK_BUS_APB2 + - NPCX_CLOCK_BUS_LFCLK pwm-cells: - - channel - - period - - flags + - channel + - period + - flags diff --git a/dts/bindings/pwm/nxp,flexpwm.yaml b/dts/bindings/pwm/nxp,flexpwm.yaml index ba6284926c6f0e..dc0f5ae38a0441 100644 --- a/dts/bindings/pwm/nxp,flexpwm.yaml +++ b/dts/bindings/pwm/nxp,flexpwm.yaml @@ -8,8 +8,8 @@ compatible: "nxp,flexpwm" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/pwm/nxp,imx-pwm.yaml b/dts/bindings/pwm/nxp,imx-pwm.yaml index 83ffcd86146c08..1863054ac8a0d7 100644 --- a/dts/bindings/pwm/nxp,imx-pwm.yaml +++ b/dts/bindings/pwm/nxp,imx-pwm.yaml @@ -8,33 +8,33 @@ compatible: "nxp,imx-pwm" include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - index: - type: int - description: flexpwm submodule index - required: true - - interrupts: - required: true - - run-in-wait: - type: boolean - description: | - Enable for PWM to keep running in WAIT mode. - - run-in-debug: - type: boolean - description: | - Enable for PWM to keep running in debug mode. - - nxp,prescaler: - type: int - enum: [1, 2, 4, 8, 16, 32, 64, 128] - required: true - description: | - Clock prescaler at the input of the PWM. - - "#pwm-cells": - const: 2 + index: + type: int + description: flexpwm submodule index + required: true + + interrupts: + required: true + + run-in-wait: + type: boolean + description: | + Enable for PWM to keep running in WAIT mode. + + run-in-debug: + type: boolean + description: | + Enable for PWM to keep running in debug mode. + + nxp,prescaler: + type: int + enum: [1, 2, 4, 8, 16, 32, 64, 128] + required: true + description: | + Clock prescaler at the input of the PWM. + + "#pwm-cells": + const: 2 pwm-cells: - channel diff --git a/dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml b/dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml index 40a86d6d14c9d5..5dd363efb056bc 100644 --- a/dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml +++ b/dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml @@ -8,12 +8,12 @@ compatible: "nxp,kinetis-ftm-pwm" include: [pwm-controller.yaml, "nxp,kinetis-ftm.yaml", "pinctrl-device.yaml"] properties: - "#pwm-cells": - const: 3 + "#pwm-cells": + const: 3 - pinctrl-0: - type: phandles - required: true + pinctrl-0: + type: phandles + required: true pwm-cells: - channel diff --git a/dts/bindings/pwm/nxp,kinetis-pwt.yaml b/dts/bindings/pwm/nxp,kinetis-pwt.yaml index ee387ace92d671..768751a09d0c74 100644 --- a/dts/bindings/pwm/nxp,kinetis-pwt.yaml +++ b/dts/bindings/pwm/nxp,kinetis-pwt.yaml @@ -8,28 +8,28 @@ compatible: "nxp,kinetis-pwt" include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - prescaler: - type: int - required: true - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 - description: Input clock prescaler - - "#pwm-cells": - const: 3 + reg: + required: true + + interrupts: + required: true + + prescaler: + type: int + required: true + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + description: Input clock prescaler + + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/nxp,kinetis-tpm.yaml b/dts/bindings/pwm/nxp,kinetis-tpm.yaml index 2014e42aad191b..1035b5242b60d3 100644 --- a/dts/bindings/pwm/nxp,kinetis-tpm.yaml +++ b/dts/bindings/pwm/nxp,kinetis-tpm.yaml @@ -8,18 +8,18 @@ compatible: "nxp,kinetis-tpm" include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - type: phandles - required: true + pinctrl-0: + type: phandles + required: true - "#pwm-cells": - const: 3 + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/nxp,sctimer-pwm.yaml b/dts/bindings/pwm/nxp,sctimer-pwm.yaml index 6c9769097646b5..50222e6413bdb7 100644 --- a/dts/bindings/pwm/nxp,sctimer-pwm.yaml +++ b/dts/bindings/pwm/nxp,sctimer-pwm.yaml @@ -8,22 +8,22 @@ compatible: "nxp,sctimer-pwm" include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - prescaler: - type: int - default: 1 - description: prescaling factor from the SCT clock. Default to 1 which is the reset value - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 + prescaler: + type: int + default: 1 + description: prescaling factor from the SCT clock. Default to 1 which is the reset value + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 - "#pwm-cells": - const: 3 + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/openisa,rv32m1-tpm.yaml b/dts/bindings/pwm/openisa,rv32m1-tpm.yaml index 853559e8dadeb2..26caa3949f4012 100644 --- a/dts/bindings/pwm/openisa,rv32m1-tpm.yaml +++ b/dts/bindings/pwm/openisa,rv32m1-tpm.yaml @@ -8,14 +8,14 @@ compatible: "openisa,rv32m1-tpm" include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#pwm-cells": - const: 3 + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/pwm-controller.yaml b/dts/bindings/pwm/pwm-controller.yaml index ee82f3a70b9a09..d31fa0b3a29cff 100644 --- a/dts/bindings/pwm/pwm-controller.yaml +++ b/dts/bindings/pwm/pwm-controller.yaml @@ -4,7 +4,7 @@ # Common fields for PWM controllers properties: - "#pwm-cells": - type: int - required: true - description: Number of items to expect in a pwm specifier + "#pwm-cells": + type: int + required: true + description: Number of items to expect in a pwm specifier diff --git a/dts/bindings/pwm/raspberrypi,pico-pwm.yaml b/dts/bindings/pwm/raspberrypi,pico-pwm.yaml index df61be19a5025d..b8ac90eacc5530 100644 --- a/dts/bindings/pwm/raspberrypi,pico-pwm.yaml +++ b/dts/bindings/pwm/raspberrypi,pico-pwm.yaml @@ -8,100 +8,100 @@ compatible: "raspberrypi,pico-pwm" include: [pwm-controller.yaml, pinctrl-device.yaml, reset-device.yaml, base.yaml] properties: - reg: - required: true - - interrupts: - required: true - - divider-int-0: - type: int - default: 1 - description: | - The integral part of the divider for pwm slice 0. - This number should be in the range 1 - 255. Defaults - to 1, the same as the RESET value. - - divider-frac-0: - type: int - default: 0 - description: | - The fractional part of the divider for pwm slice 0. - This number should be in the range 0 - 15. Defaults - to 0, the same as the RESET value. - - divider-int-1: - type: int - default: 1 - description: See divider-int-0 for help - - divider-frac-1: - type: int - default: 0 - description: See divider-frac-0 for help - - divider-int-2: - type: int - default: 1 - description: See divider-int-0 for help - - divider-frac-2: - type: int - default: 0 - description: See divider-frac-0 for help - - divider-int-3: - type: int - default: 1 - description: See divider-int-0 for help - - divider-frac-3: - type: int - default: 0 - description: See divider-frac-0 for help - - divider-int-4: - type: int - default: 1 - description: See divider-int-0 for help - - divider-frac-4: - type: int - default: 0 - description: See divider-frac-0 for help - - divider-int-5: - type: int - default: 1 - description: See divider-int-0 for help - - divider-frac-5: - type: int - default: 0 - description: See divider-frac-0 for help - - divider-int-6: - type: int - default: 1 - description: See divider-int-0 for help - - divider-frac-6: - type: int - default: 0 - description: See divider-frac-0 for help - - divider-int-7: - type: int - default: 1 - description: See divider-int-0 for help - - divider-frac-7: - type: int - default: 0 - description: See divider-frac-0 for help - - "#pwm-cells": - const: 3 + reg: + required: true + + interrupts: + required: true + + divider-int-0: + type: int + default: 1 + description: | + The integral part of the divider for pwm slice 0. + This number should be in the range 1 - 255. Defaults + to 1, the same as the RESET value. + + divider-frac-0: + type: int + default: 0 + description: | + The fractional part of the divider for pwm slice 0. + This number should be in the range 0 - 15. Defaults + to 0, the same as the RESET value. + + divider-int-1: + type: int + default: 1 + description: See divider-int-0 for help + + divider-frac-1: + type: int + default: 0 + description: See divider-frac-0 for help + + divider-int-2: + type: int + default: 1 + description: See divider-int-0 for help + + divider-frac-2: + type: int + default: 0 + description: See divider-frac-0 for help + + divider-int-3: + type: int + default: 1 + description: See divider-int-0 for help + + divider-frac-3: + type: int + default: 0 + description: See divider-frac-0 for help + + divider-int-4: + type: int + default: 1 + description: See divider-int-0 for help + + divider-frac-4: + type: int + default: 0 + description: See divider-frac-0 for help + + divider-int-5: + type: int + default: 1 + description: See divider-int-0 for help + + divider-frac-5: + type: int + default: 0 + description: See divider-frac-0 for help + + divider-int-6: + type: int + default: 1 + description: See divider-int-0 for help + + divider-frac-6: + type: int + default: 0 + description: See divider-frac-0 for help + + divider-int-7: + type: int + default: 1 + description: See divider-int-0 for help + + divider-frac-7: + type: int + default: 0 + description: See divider-frac-0 for help + + "#pwm-cells": + const: 3 pwm-cells: # The rpi pico pwm peripheral is divided in 8 slices with an individual diff --git a/dts/bindings/pwm/renesas,pwm-rcar.yaml b/dts/bindings/pwm/renesas,pwm-rcar.yaml index ffdb62f59a9d8f..f2432c27492555 100644 --- a/dts/bindings/pwm/renesas,pwm-rcar.yaml +++ b/dts/bindings/pwm/renesas,pwm-rcar.yaml @@ -8,8 +8,8 @@ compatible: "renesas,pwm-rcar" include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - "#pwm-cells": - const: 3 + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/sifive,pwm0.yaml b/dts/bindings/pwm/sifive,pwm0.yaml index 83647c35d76760..1bfe20aecba1ca 100644 --- a/dts/bindings/pwm/sifive,pwm0.yaml +++ b/dts/bindings/pwm/sifive,pwm0.yaml @@ -8,19 +8,19 @@ compatible: "sifive,pwm0" include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - sifive,compare-width: - type: int - required: true - description: Width of the PWM comparator in bits + sifive,compare-width: + type: int + required: true + description: Width of the PWM comparator in bits - "#pwm-cells": - const: 2 + "#pwm-cells": + const: 2 pwm-cells: - channel diff --git a/dts/bindings/pwm/silabs,gecko-pwm.yaml b/dts/bindings/pwm/silabs,gecko-pwm.yaml index 28442306e50b55..3b610988e8a318 100644 --- a/dts/bindings/pwm/silabs,gecko-pwm.yaml +++ b/dts/bindings/pwm/silabs,gecko-pwm.yaml @@ -5,30 +5,30 @@ compatible: "silabs,gecko-pwm" include: [pwm-controller.yaml, base.yaml] properties: - pin-location: - type: array - required: true - description: pwm pin configuration defined as + pin-location: + type: array + required: true + description: pwm pin configuration defined as - prescaler: - type: int - default: 1 - description: prescaling factor from the HFPERCLK clock - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 - - 256 - - 512 - - 1024 + prescaler: + type: int + default: 1 + description: prescaling factor from the HFPERCLK clock + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + - 256 + - 512 + - 1024 - "#pwm-cells": - const: 3 + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/st,stm32-pwm.yaml b/dts/bindings/pwm/st,stm32-pwm.yaml index 1bef55b7a9a369..bf7b9cf60884bf 100644 --- a/dts/bindings/pwm/st,stm32-pwm.yaml +++ b/dts/bindings/pwm/st,stm32-pwm.yaml @@ -5,21 +5,21 @@ compatible: "st,stm32-pwm" include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml] properties: - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - "#pwm-cells": - const: 3 - description: | - Number of items to expect in a PWM - - channel of the timer used for PWM - - period to set in ns - - flags : combination of standard flags like PWM_POLARITY_NORMAL - or specific flags like PWM_STM32_COMPLEMENTARY. As an example for channel2: - <&pwm1 2 100 (PWM_POLARITY_NORMAL | PWM_STM32_COMPLEMENTARY)>; + "#pwm-cells": + const: 3 + description: | + Number of items to expect in a PWM + - channel of the timer used for PWM + - period to set in ns + - flags : combination of standard flags like PWM_POLARITY_NORMAL + or specific flags like PWM_STM32_COMPLEMENTARY. As an example for channel2: + <&pwm1 2 100 (PWM_POLARITY_NORMAL | PWM_STM32_COMPLEMENTARY)>; pwm-cells: - channel diff --git a/dts/bindings/pwm/telink,b91-pwm.yaml b/dts/bindings/pwm/telink,b91-pwm.yaml index 9c296cc6a936ce..7c96698f0f61a6 100644 --- a/dts/bindings/pwm/telink,b91-pwm.yaml +++ b/dts/bindings/pwm/telink,b91-pwm.yaml @@ -10,50 +10,50 @@ compatible: "telink,b91-pwm" properties: - pinctrl-0: - type: phandles - required: true - - clock-frequency: - type: int - required: true - description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled) - - clk32k-ch0-enable: - type: boolean - description: Enable 32K Source Clock for PWM Channel 0 - - clk32k-ch1-enable: - type: boolean - description: Enable 32K Source Clock for PWM Channel 1 - - clk32k-ch2-enable: - type: boolean - description: Enable 32K Source Clock for PWM Channel 2 - - clk32k-ch3-enable: - type: boolean - description: Enable 32K Source Clock for PWM Channel 3 - - clk32k-ch4-enable: - type: boolean - description: Enable 32K Source Clock for PWM Channel 4 - - clk32k-ch5-enable: - type: boolean - description: Enable 32K Source Clock for PWM Channel 5 - - channels: - type: int - const: 6 - required: true - description: Number of channels this PWM has - - reg: - required: true - - "#pwm-cells": - const: 3 + pinctrl-0: + type: phandles + required: true + + clock-frequency: + type: int + required: true + description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled) + + clk32k-ch0-enable: + type: boolean + description: Enable 32K Source Clock for PWM Channel 0 + + clk32k-ch1-enable: + type: boolean + description: Enable 32K Source Clock for PWM Channel 1 + + clk32k-ch2-enable: + type: boolean + description: Enable 32K Source Clock for PWM Channel 2 + + clk32k-ch3-enable: + type: boolean + description: Enable 32K Source Clock for PWM Channel 3 + + clk32k-ch4-enable: + type: boolean + description: Enable 32K Source Clock for PWM Channel 4 + + clk32k-ch5-enable: + type: boolean + description: Enable 32K Source Clock for PWM Channel 5 + + channels: + type: int + const: 6 + required: true + description: Number of channels this PWM has + + reg: + required: true + + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/pwm/xlnx,xps-timer-1.00.a-pwm.yaml b/dts/bindings/pwm/xlnx,xps-timer-1.00.a-pwm.yaml index e32422819d737a..7ef17de1407365 100644 --- a/dts/bindings/pwm/xlnx,xps-timer-1.00.a-pwm.yaml +++ b/dts/bindings/pwm/xlnx,xps-timer-1.00.a-pwm.yaml @@ -5,17 +5,17 @@ compatible: "xlnx,xps-timer-1.00.a-pwm" include: ["xlnx,xps-timer-1.00.a.yaml", pwm-controller.yaml] properties: - xlnx,gen0-assert: - required: true + xlnx,gen0-assert: + required: true - xlnx,gen1-assert: - required: true + xlnx,gen1-assert: + required: true - xlnx,trig0-assert: - required: true + xlnx,trig0-assert: + required: true - xlnx,trig1-assert: - required: true + xlnx,trig1-assert: + required: true pwm-cells: - channel diff --git a/dts/bindings/qspi/altr,nios2-qspi.yaml b/dts/bindings/qspi/altr,nios2-qspi.yaml index 48cfe6deef2cc6..af48ac324f9c38 100644 --- a/dts/bindings/qspi/altr,nios2-qspi.yaml +++ b/dts/bindings/qspi/altr,nios2-qspi.yaml @@ -10,5 +10,5 @@ include: [base.yaml] bus: qspi properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/qspi/st,stm32-qspi.yaml b/dts/bindings/qspi/st,stm32-qspi.yaml index 424e202112c3e8..b6897c95657a97 100644 --- a/dts/bindings/qspi/st,stm32-qspi.yaml +++ b/dts/bindings/qspi/st,stm32-qspi.yaml @@ -23,40 +23,40 @@ include: [base.yaml, pinctrl-device.yaml] bus: qspi properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - dmas: - description: | - Optional DMA channel specifier. If DMA should be used, specifier should - hold a phandle reference to the dma controller, the channel number, - the slot number, channel configuration and finally features. + dmas: + description: | + Optional DMA channel specifier. If DMA should be used, specifier should + hold a phandle reference to the dma controller, the channel number, + the slot number, channel configuration and finally features. - For example dmas for TX/RX on QSPI - dmas = <&dma1 5 5 0x0000 0x03>; + For example dmas for TX/RX on QSPI + dmas = <&dma1 5 5 0x0000 0x03>; - dma-names: - description: | - DMA channel name. If DMA should be used, expected value is "tx_rx". + dma-names: + description: | + DMA channel name. If DMA should be used, expected value is "tx_rx". - For example - dma-names = "tx_rx"; + For example + dma-names = "tx_rx"; - flash-id: - type: int - description: | - FLash ID number. This number, if defined, helps to select the right - QSPI GPIO banks (defined as 'quadspi_bk[12]' in pinctrl property) - to communicate with flash memory. + flash-id: + type: int + description: | + FLash ID number. This number, if defined, helps to select the right + QSPI GPIO banks (defined as 'quadspi_bk[12]' in pinctrl property) + to communicate with flash memory. - For example - flash-id = <2>; + For example + flash-id = <2>; diff --git a/dts/bindings/regulator/nxp,pca9420.yaml b/dts/bindings/regulator/nxp,pca9420.yaml index eba682eb2590df..1f88113760118e 100644 --- a/dts/bindings/regulator/nxp,pca9420.yaml +++ b/dts/bindings/regulator/nxp,pca9420.yaml @@ -74,32 +74,32 @@ child-binding: description: Voltage output of PMIC controller regulator properties: - enable-inverted: - type: boolean - description: | - If the enable bit should be zero to turn the regulator on, add this - property. - - nxp,mode0-microvolt: - type: int - description: | - The voltage level to be configured for mode 0, in microvolts. Setting - this value to zero will disable the source in mode 0. - - nxp,mode1-microvolt: - type: int - description: | - The voltage level to be configured for mode 1, in microvolts. Setting - this value to zero will disable the source in mode 1. - - nxp,mode2-microvolt: - type: int - description: | - The voltage level to be configured for mode 2, in microvolts. Setting - this value to zero will disable the source in mode 2. - - nxp,mode3-microvolt: - type: int - description: | - The voltage level to be configured for mode 3, in microvolts. Setting - this value to zero will disable the source in mode 3. + enable-inverted: + type: boolean + description: | + If the enable bit should be zero to turn the regulator on, add this + property. + + nxp,mode0-microvolt: + type: int + description: | + The voltage level to be configured for mode 0, in microvolts. Setting + this value to zero will disable the source in mode 0. + + nxp,mode1-microvolt: + type: int + description: | + The voltage level to be configured for mode 1, in microvolts. Setting + this value to zero will disable the source in mode 1. + + nxp,mode2-microvolt: + type: int + description: | + The voltage level to be configured for mode 2, in microvolts. Setting + this value to zero will disable the source in mode 2. + + nxp,mode3-microvolt: + type: int + description: | + The voltage level to be configured for mode 3, in microvolts. Setting + this value to zero will disable the source in mode 3. diff --git a/dts/bindings/reserved-memory/memory-region.yaml b/dts/bindings/reserved-memory/memory-region.yaml index e933705cbe2075..b599d5f36ddd1a 100644 --- a/dts/bindings/reserved-memory/memory-region.yaml +++ b/dts/bindings/reserved-memory/memory-region.yaml @@ -5,10 +5,10 @@ # by adding a memory-region property to the device node. properties: - memory-regions: - type: phandle-array - description: List of memory region phandles + memory-regions: + type: phandle-array + description: List of memory region phandles - memory-region-names: - type: string-array - description: A list of names, one for each corresponding phandle in memory-region + memory-region-names: + type: string-array + description: A list of names, one for each corresponding phandle in memory-region diff --git a/dts/bindings/reset/aspeed,ast10x0-reset.yaml b/dts/bindings/reset/aspeed,ast10x0-reset.yaml index 4f5cab8b27049b..a6d7a14ecce2a2 100644 --- a/dts/bindings/reset/aspeed,ast10x0-reset.yaml +++ b/dts/bindings/reset/aspeed,ast10x0-reset.yaml @@ -8,8 +8,8 @@ compatible: "aspeed,ast10x0-reset" include: [base.yaml, reset-controller.yaml] properties: - "#reset-cells": - const: 1 + "#reset-cells": + const: 1 clock-cells: - reset_id diff --git a/dts/bindings/reset/gd,gd32-rctl.yaml b/dts/bindings/reset/gd,gd32-rctl.yaml index c9317e67056bcd..6fcebc5622fb28 100644 --- a/dts/bindings/reset/gd,gd32-rctl.yaml +++ b/dts/bindings/reset/gd,gd32-rctl.yaml @@ -25,8 +25,8 @@ compatible: "gd,gd32-rctl" include: [reset-controller.yaml, base.yaml] properties: - "#reset-cells": - const: 1 + "#reset-cells": + const: 1 reset-cells: - id diff --git a/dts/bindings/reset/raspberrypi,pico-reset.yaml b/dts/bindings/reset/raspberrypi,pico-reset.yaml index e2616778cb5a10..f6393d3e056c5e 100644 --- a/dts/bindings/reset/raspberrypi,pico-reset.yaml +++ b/dts/bindings/reset/raspberrypi,pico-reset.yaml @@ -8,16 +8,16 @@ compatible: "raspberrypi,pico-reset" include: [base.yaml, reset-controller.yaml] properties: - reg: - required: true - reg-width: - type: int - description: The width of the reset registers in bytes. Default is 4 bytes. - active-low: - type: int - description: Set if reset is active low. Default is 0, which means active-high. - "#reset-cells": - const: 1 + reg: + required: true + reg-width: + type: int + description: The width of the reset registers in bytes. Default is 4 bytes. + active-low: + type: int + description: Set if reset is active low. Default is 0, which means active-high. + "#reset-cells": + const: 1 reset-cells: - id diff --git a/dts/bindings/reset/reset-controller.yaml b/dts/bindings/reset/reset-controller.yaml index 2ca40d6f1b74b4..eddf52c376ada3 100644 --- a/dts/bindings/reset/reset-controller.yaml +++ b/dts/bindings/reset/reset-controller.yaml @@ -4,7 +4,7 @@ description: Reset Controller properties: - "#reset-cells": - type: int - required: true - description: Number of cells in reset property + "#reset-cells": + type: int + required: true + description: Number of cells in reset property diff --git a/dts/bindings/reset/st,stm32-rcc-rctl.yaml b/dts/bindings/reset/st,stm32-rcc-rctl.yaml index 26f1491e14fd91..3629db3813a947 100644 --- a/dts/bindings/reset/st,stm32-rcc-rctl.yaml +++ b/dts/bindings/reset/st,stm32-rcc-rctl.yaml @@ -24,14 +24,14 @@ compatible: "st,stm32-rcc-rctl" include: [reset-controller.yaml, base.yaml] properties: - "#reset-cells": - const: 1 - - set-bit-to-deassert: - type: boolean - description: | - Indicates if the driver should set bit in clear register to - deassert reset. + "#reset-cells": + const: 1 + + set-bit-to-deassert: + type: boolean + description: | + Indicates if the driver should set bit in clear register to + deassert reset. reset-cells: - id diff --git a/dts/bindings/riscv/openisa,rv32m1-pcc.yaml b/dts/bindings/riscv/openisa,rv32m1-pcc.yaml index 62ddff55453a6c..15e9f6fcea0da3 100644 --- a/dts/bindings/riscv/openisa,rv32m1-pcc.yaml +++ b/dts/bindings/riscv/openisa,rv32m1-pcc.yaml @@ -8,11 +8,11 @@ compatible: "openisa,rv32m1-pcc" include: [clock-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#clock-cells": - const: 1 + "#clock-cells": + const: 1 clock-cells: - name diff --git a/dts/bindings/riscv/sifive-common.yaml b/dts/bindings/riscv/sifive-common.yaml index 5977e94eca13fd..e5b3851c615de4 100644 --- a/dts/bindings/riscv/sifive-common.yaml +++ b/dts/bindings/riscv/sifive-common.yaml @@ -6,6 +6,6 @@ include: riscv,cpus.yaml properties: - hardware-exec-breakpoint-count: - type: int - description: Number of hardware break points + hardware-exec-breakpoint-count: + type: int + description: Number of hardware break points diff --git a/dts/bindings/rng/atmel,sam-trng.yaml b/dts/bindings/rng/atmel,sam-trng.yaml index 26c7d288d7c2d9..23adaca31fb74d 100644 --- a/dts/bindings/rng/atmel,sam-trng.yaml +++ b/dts/bindings/rng/atmel,sam-trng.yaml @@ -8,13 +8,13 @@ compatible: "atmel,sam-trng" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/rng/espressif,esp32-trng.yaml b/dts/bindings/rng/espressif,esp32-trng.yaml index e66de6a2697e68..78c3fd1e1ec78b 100644 --- a/dts/bindings/rng/espressif,esp32-trng.yaml +++ b/dts/bindings/rng/espressif,esp32-trng.yaml @@ -12,5 +12,5 @@ compatible: "espressif,esp32-trng" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rng/litex,prbs.yaml b/dts/bindings/rng/litex,prbs.yaml index 051fc75a6494c0..d74df530b62818 100644 --- a/dts/bindings/rng/litex,prbs.yaml +++ b/dts/bindings/rng/litex,prbs.yaml @@ -8,5 +8,5 @@ compatible: "litex,prbs" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rng/neorv32-trng.yaml b/dts/bindings/rng/neorv32-trng.yaml index 89d894fc37d56a..2514944481bd97 100644 --- a/dts/bindings/rng/neorv32-trng.yaml +++ b/dts/bindings/rng/neorv32-trng.yaml @@ -5,11 +5,11 @@ compatible: "neorv32-trng" include: base.yaml properties: - reg: - required: true - - syscon: - type: phandle - required: true - description: | - phandle to syscon (NEORV32 SYSINFO) node. + reg: + required: true + + syscon: + type: phandle + required: true + description: | + phandle to syscon (NEORV32 SYSINFO) node. diff --git a/dts/bindings/rng/nordic,nrf-rng.yaml b/dts/bindings/rng/nordic,nrf-rng.yaml index fabc6b60c10b27..c6873b85e433e2 100644 --- a/dts/bindings/rng/nordic,nrf-rng.yaml +++ b/dts/bindings/rng/nordic,nrf-rng.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-rng" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/rng/nxp,css-v2.yaml b/dts/bindings/rng/nxp,css-v2.yaml index e9dc28448464c2..18ac4ee3d85e72 100644 --- a/dts/bindings/rng/nxp,css-v2.yaml +++ b/dts/bindings/rng/nxp,css-v2.yaml @@ -8,5 +8,5 @@ compatible: "nxp,css-v2" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rng/nxp,imx-caam.yaml b/dts/bindings/rng/nxp,imx-caam.yaml index 51c67fa637f80f..2a15833007facc 100644 --- a/dts/bindings/rng/nxp,imx-caam.yaml +++ b/dts/bindings/rng/nxp,imx-caam.yaml @@ -8,8 +8,8 @@ compatible: "nxp,imx-caam" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/rng/nxp,kinetis-rnga.yaml b/dts/bindings/rng/nxp,kinetis-rnga.yaml index 7773566159800e..fd1881dd7b8f81 100644 --- a/dts/bindings/rng/nxp,kinetis-rnga.yaml +++ b/dts/bindings/rng/nxp,kinetis-rnga.yaml @@ -8,8 +8,8 @@ compatible: "nxp,kinetis-rnga" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/rng/nxp,kinetis-trng.yaml b/dts/bindings/rng/nxp,kinetis-trng.yaml index 5049ebd6cb136a..a856d41ea8598b 100644 --- a/dts/bindings/rng/nxp,kinetis-trng.yaml +++ b/dts/bindings/rng/nxp,kinetis-trng.yaml @@ -8,8 +8,8 @@ compatible: "nxp,kinetis-trng" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/rng/nxp,lpc-rng.yaml b/dts/bindings/rng/nxp,lpc-rng.yaml index 0588366de5bb7e..ddf85b58e7e303 100644 --- a/dts/bindings/rng/nxp,lpc-rng.yaml +++ b/dts/bindings/rng/nxp,lpc-rng.yaml @@ -8,5 +8,5 @@ compatible: "nxp,lpc-rng" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rng/openisa,rv32m1-trng.yaml b/dts/bindings/rng/openisa,rv32m1-trng.yaml index 904ce94a65967a..eebfd099d40dd3 100644 --- a/dts/bindings/rng/openisa,rv32m1-trng.yaml +++ b/dts/bindings/rng/openisa,rv32m1-trng.yaml @@ -8,8 +8,8 @@ compatible: "openisa,rv32m1-trng" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/rng/silabs,gecko-trng.yaml b/dts/bindings/rng/silabs,gecko-trng.yaml index 4ae1f0d22f7148..de88e5d4bfa515 100644 --- a/dts/bindings/rng/silabs,gecko-trng.yaml +++ b/dts/bindings/rng/silabs,gecko-trng.yaml @@ -11,8 +11,8 @@ compatible: "silabs,gecko-trng" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/rng/st,stm32-rng.yaml b/dts/bindings/rng/st,stm32-rng.yaml index a10d0f653a4860..a2693bc154d208 100644 --- a/dts/bindings/rng/st,stm32-rng.yaml +++ b/dts/bindings/rng/st,stm32-rng.yaml @@ -8,33 +8,33 @@ compatible: "st,stm32-rng" include: base.yaml properties: - reg: - required: true - - clocks: - required: true - - nist-config: - type: int - description: | - This property is used to configure the RNG_CR for the NIST certification - The validation conditions are following the refMan - to certify NIST SP800-90B. RNG clock source must be 48MHz. - This config is valid with some STM32 families - and when Conditioning Soft Reset (RNG_CR_CONDRST bit) exists. - The value is directly mapped from the RNG configuration (A) table. - The Health Register (health-test-config property) must correspond - to this table configuration. - On the stm32U5, the ARDIS bit7 is also written. - - health-test-magic: - type: int - description: | - Magic Number to be written to Health Test Configuration Register (HTCR) - prior to real configuration, if any. - - health-test-config: - type: int - description: | - Heath Test Configuration, necessary to have proper RNG behavior, - when available. + reg: + required: true + + clocks: + required: true + + nist-config: + type: int + description: | + This property is used to configure the RNG_CR for the NIST certification + The validation conditions are following the refMan + to certify NIST SP800-90B. RNG clock source must be 48MHz. + This config is valid with some STM32 families + and when Conditioning Soft Reset (RNG_CR_CONDRST bit) exists. + The value is directly mapped from the RNG configuration (A) table. + The Health Register (health-test-config property) must correspond + to this table configuration. + On the stm32U5, the ARDIS bit7 is also written. + + health-test-magic: + type: int + description: | + Magic Number to be written to Health Test Configuration Register (HTCR) + prior to real configuration, if any. + + health-test-config: + type: int + description: | + Heath Test Configuration, necessary to have proper RNG behavior, + when available. diff --git a/dts/bindings/rng/telink,b91-trng.yaml b/dts/bindings/rng/telink,b91-trng.yaml index a1bf1bfdf11f69..b8ebee37b88c20 100644 --- a/dts/bindings/rng/telink,b91-trng.yaml +++ b/dts/bindings/rng/telink,b91-trng.yaml @@ -8,5 +8,5 @@ compatible: "telink,b91-trng" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml b/dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml index b3b15065aa03ef..4737072fc0c936 100644 --- a/dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml +++ b/dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml @@ -8,8 +8,8 @@ compatible: "ti,cc13xx-cc26xx-trng" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/rtc/atmel,sam0-rtc.yaml b/dts/bindings/rtc/atmel,sam0-rtc.yaml index edea478dd3fbdf..f2210e8bfb4e06 100644 --- a/dts/bindings/rtc/atmel,sam0-rtc.yaml +++ b/dts/bindings/rtc/atmel,sam0-rtc.yaml @@ -6,14 +6,14 @@ description: Atmel SAM0 RTC compatible: "atmel,sam0-rtc" include: - - name: rtc.yaml - - name: pinctrl-device.yaml + - name: rtc.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - clock-generator: - type: int - description: clock generator index - required: true + clock-generator: + type: int + description: clock generator index + required: true diff --git a/dts/bindings/rtc/microchip,xec-timer.yaml b/dts/bindings/rtc/microchip,xec-timer.yaml index dd13fba9f4ba88..8608833dc3b28e 100644 --- a/dts/bindings/rtc/microchip,xec-timer.yaml +++ b/dts/bindings/rtc/microchip,xec-timer.yaml @@ -8,31 +8,31 @@ compatible: "microchip,xec-timer" include: rtc.yaml properties: - reg: - required: true - - interrupts: - required: true - - clock-frequency: - required: true - - prescaler: - type: int - required: true - description: Timer frequency equals clock-frequency divided by the prescaler value - - max-value: - type: int - required: true - description: Maximum counter value the instance can handle - - girqs: - type: array - required: true - description: Array of GIRQ numbers [8:26] and bit positions [0:31]. - - pcrs: - type: array - required: true - description: PCR sleep enable register index and bit position. + reg: + required: true + + interrupts: + required: true + + clock-frequency: + required: true + + prescaler: + type: int + required: true + description: Timer frequency equals clock-frequency divided by the prescaler value + + max-value: + type: int + required: true + description: Maximum counter value the instance can handle + + girqs: + type: array + required: true + description: Array of GIRQ numbers [8:26] and bit positions [0:31]. + + pcrs: + type: array + required: true + description: PCR sleep enable register index and bit position. diff --git a/dts/bindings/rtc/nordic,nrf-rtc.yaml b/dts/bindings/rtc/nordic,nrf-rtc.yaml index f01117fd7d1495..b04a2bd9d36cb4 100644 --- a/dts/bindings/rtc/nordic,nrf-rtc.yaml +++ b/dts/bindings/rtc/nordic,nrf-rtc.yaml @@ -8,28 +8,28 @@ compatible: "nordic,nrf-rtc" include: rtc.yaml properties: - reg: - required: true - - cc-num: - type: int - required: true - description: | - Number of compare (CC) registers available. - - On nRF53 these registers can also be used for capture. - - # If enabled, overflow different than full range (24 bits) is handled - # through PPI channel which ensures precise timing. If disabled then - # counter is cleared in the interrupt which results in accumulative error - # of counter period if top value is different than maximal. - ppi-wrap: - type: boolean - description: Enable wrapping with PPI - - # If enabled then counter based on nRF RTC peripheral supports only maximal - # top value. That results in code optimizations and availability of one more - # channel - fixed-top: - type: boolean - description: Enable fixed top value + reg: + required: true + + cc-num: + type: int + required: true + description: | + Number of compare (CC) registers available. + + On nRF53 these registers can also be used for capture. + + # If enabled, overflow different than full range (24 bits) is handled + # through PPI channel which ensures precise timing. If disabled then + # counter is cleared in the interrupt which results in accumulative error + # of counter period if top value is different than maximal. + ppi-wrap: + type: boolean + description: Enable wrapping with PPI + + # If enabled then counter based on nRF RTC peripheral supports only maximal + # top value. That results in code optimizations and availability of one more + # channel + fixed-top: + type: boolean + description: Enable fixed top value diff --git a/dts/bindings/rtc/nxp,kinetis-lptmr.yaml b/dts/bindings/rtc/nxp,kinetis-lptmr.yaml index ee31f855fcc4d3..f16451fc0a35a9 100644 --- a/dts/bindings/rtc/nxp,kinetis-lptmr.yaml +++ b/dts/bindings/rtc/nxp,kinetis-lptmr.yaml @@ -8,24 +8,24 @@ compatible: "nxp,kinetis-lptmr" include: rtc.yaml properties: - reg: - required: true + reg: + required: true - clock-frequency: - required: true + clock-frequency: + required: true - prescaler: - required: true + prescaler: + required: true - clk-source: - type: int - required: true - description: Prescaler clock source (0 to 3) + clk-source: + type: int + required: true + description: Prescaler clock source (0 to 3) - input-pin: - type: int - description: Pulse counter input pin (0 to 3). + input-pin: + type: int + description: Pulse counter input pin (0 to 3). - active-low: - type: boolean - description: Pulse counter input pin is active-low + active-low: + type: boolean + description: Pulse counter input pin is active-low diff --git a/dts/bindings/rtc/nxp,kinetis-pit.yaml b/dts/bindings/rtc/nxp,kinetis-pit.yaml index 0b8943c545dc5e..6d2f478ecb0838 100644 --- a/dts/bindings/rtc/nxp,kinetis-pit.yaml +++ b/dts/bindings/rtc/nxp,kinetis-pit.yaml @@ -8,15 +8,15 @@ compatible: "nxp,kinetis-pit" include: [rtc.yaml] properties: - reg: - required: true + reg: + required: true - pit-channel: - type: int - required: true - description: pit channel to active + pit-channel: + type: int + required: true + description: pit channel to active - pit-period: - type: int - required: true - description: pit default period in us + pit-period: + type: int + required: true + description: pit default period in us diff --git a/dts/bindings/rtc/nxp,kinetis-rtc.yaml b/dts/bindings/rtc/nxp,kinetis-rtc.yaml index e9203f44f87fb0..226d7d6e59a936 100644 --- a/dts/bindings/rtc/nxp,kinetis-rtc.yaml +++ b/dts/bindings/rtc/nxp,kinetis-rtc.yaml @@ -8,5 +8,5 @@ compatible: "nxp,kinetis-rtc" include: rtc.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rtc/nxp,lpc-rtc.yaml b/dts/bindings/rtc/nxp,lpc-rtc.yaml index fd9455335d7566..1c8b5fe569ec9e 100644 --- a/dts/bindings/rtc/nxp,lpc-rtc.yaml +++ b/dts/bindings/rtc/nxp,lpc-rtc.yaml @@ -8,5 +8,5 @@ compatible: "nxp,lpc-rtc" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rtc/rtc.yaml b/dts/bindings/rtc/rtc.yaml index 5aa4459e461554..15b5e1a9c758a6 100644 --- a/dts/bindings/rtc/rtc.yaml +++ b/dts/bindings/rtc/rtc.yaml @@ -6,12 +6,12 @@ include: base.yaml properties: - clock-frequency: - type: int - description: Clock frequency information for RTC operation - interrupts: - required: true + clock-frequency: + type: int + description: Clock frequency information for RTC operation + interrupts: + required: true - prescaler: - type: int - description: RTC frequency equals clock-frequency divided by the prescaler value + prescaler: + type: int + description: RTC frequency equals clock-frequency divided by the prescaler value diff --git a/dts/bindings/rtc/silabs,gecko-rtcc.yaml b/dts/bindings/rtc/silabs,gecko-rtcc.yaml index 014c92d60eed7d..b66fc8a4a31238 100644 --- a/dts/bindings/rtc/silabs,gecko-rtcc.yaml +++ b/dts/bindings/rtc/silabs,gecko-rtcc.yaml @@ -8,5 +8,5 @@ compatible: "silabs,gecko-rtcc" include: rtc.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rtc/silabs,gecko-stimer.yaml b/dts/bindings/rtc/silabs,gecko-stimer.yaml index 272c27b97211cb..f624a76559d46e 100644 --- a/dts/bindings/rtc/silabs,gecko-stimer.yaml +++ b/dts/bindings/rtc/silabs,gecko-stimer.yaml @@ -8,5 +8,5 @@ compatible: "silabs,gecko-stimer" include: rtc.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rtc/st,stm32-rtc.yaml b/dts/bindings/rtc/st,stm32-rtc.yaml index 8498474f48507f..4358340f911dff 100644 --- a/dts/bindings/rtc/st,stm32-rtc.yaml +++ b/dts/bindings/rtc/st,stm32-rtc.yaml @@ -8,5 +8,5 @@ compatible: "st,stm32-rtc" include: rtc.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml b/dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml index f98544b4e488f2..93f7912d3cd6f3 100644 --- a/dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml +++ b/dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml @@ -11,5 +11,5 @@ compatible: "ti,cc13xx-cc26xx-rtc" include: rtc.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml b/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml index 1ee2bfdd0a45fe..b0b5fb3cc07e2b 100644 --- a/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml +++ b/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml @@ -8,60 +8,60 @@ include: rtc.yaml # https://github.com/Xilinx/meta-xilinx properties: - clock-frequency: - required: true + clock-frequency: + required: true - xlnx,count-width: - type: int - required: true - enum: - - 8 - - 16 - - 32 - description: | - Individual timer/counter width in bits. + xlnx,count-width: + type: int + required: true + enum: + - 8 + - 16 + - 32 + description: | + Individual timer/counter width in bits. - xlnx,gen0-assert: - type: int - enum: - - 0 - - 1 - description: | - Active state of the generateout0 signal (0 for active-low, 1 for - active-high). + xlnx,gen0-assert: + type: int + enum: + - 0 + - 1 + description: | + Active state of the generateout0 signal (0 for active-low, 1 for + active-high). - xlnx,gen1-assert: - type: int - enum: - - 0 - - 1 - description: | - Active state of the generateout1 signal (0 for active-low, 1 for - active-high). + xlnx,gen1-assert: + type: int + enum: + - 0 + - 1 + description: | + Active state of the generateout1 signal (0 for active-low, 1 for + active-high). - xlnx,one-timer-only: - type: int - required: true - enum: - - 0 - - 1 - description: | - 0 if both Timer 1 and Timer 2 are enabled, 1 if only Timer 1 is enabled. + xlnx,one-timer-only: + type: int + required: true + enum: + - 0 + - 1 + description: | + 0 if both Timer 1 and Timer 2 are enabled, 1 if only Timer 1 is enabled. - xlnx,trig0-assert: - type: int - enum: - - 0 - - 1 - description: | - Active state of the capturetrig0 signal (0 for active-low, 1 for - active-high). + xlnx,trig0-assert: + type: int + enum: + - 0 + - 1 + description: | + Active state of the capturetrig0 signal (0 for active-low, 1 for + active-high). - xlnx,trig1-assert: - type: int - enum: - - 0 - - 1 - description: | - Active state of the capturetrig1 signal (0 for active-low, 1 for - active-high). + xlnx,trig1-assert: + type: int + enum: + - 0 + - 1 + description: | + Active state of the capturetrig1 signal (0 for active-low, 1 for + active-high). diff --git a/dts/bindings/sdhc/nxp,imx-usdhc.yaml b/dts/bindings/sdhc/nxp,imx-usdhc.yaml index 5ef513847b9b9b..3b8df7db39f185 100644 --- a/dts/bindings/sdhc/nxp,imx-usdhc.yaml +++ b/dts/bindings/sdhc/nxp,imx-usdhc.yaml @@ -36,7 +36,7 @@ properties: Max drive current in mA at 3.3V. A value of zero indicates no maximum is specified by the driver. clocks: - required: true + required: true pwr-gpios: type: phandle-array diff --git a/dts/bindings/sensor/adi,adt7420.yaml b/dts/bindings/sensor/adi,adt7420.yaml index 19523db96d1b41..3a4a75eaf218b1 100644 --- a/dts/bindings/sensor/adi,adt7420.yaml +++ b/dts/bindings/sensor/adi,adt7420.yaml @@ -8,8 +8,8 @@ compatible: "adi,adt7420" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - The INT signal defaults to active low open drain, so requires a - pull-up on the board or in the flags cell of this entry. + int-gpios: + type: phandle-array + description: | + The INT signal defaults to active low open drain, so requires a + pull-up on the board or in the flags cell of this entry. diff --git a/dts/bindings/sensor/adi,adxl362.yaml b/dts/bindings/sensor/adi,adxl362.yaml index f0f4a7e0327789..a173375adb7bb4 100644 --- a/dts/bindings/sensor/adi,adxl362.yaml +++ b/dts/bindings/sensor/adi,adxl362.yaml @@ -8,22 +8,22 @@ compatible: "adi,adxl362" include: [sensor-device.yaml, spi-device.yaml] properties: - int1-gpios: - type: phandle-array - description: | - The INT1 signal defaults to active high as produced by the - sensor. The property value should ensure the flags properly - describe the signal that is presented to the driver. + int1-gpios: + type: phandle-array + description: | + The INT1 signal defaults to active high as produced by the + sensor. The property value should ensure the flags properly + describe the signal that is presented to the driver. - wakeup-mode: - type: boolean - description: | - This mode is intended for extremely low power consumption, - checking for motion only about six times a second. + wakeup-mode: + type: boolean + description: | + This mode is intended for extremely low power consumption, + checking for motion only about six times a second. - autosleep: - type: boolean - description: | - Enter Wake-Up mode when inactivity is detected, - reenter Measurement mode when activity is detected. - Only applies for Linked and Loop mode, ignored otherwise. + autosleep: + type: boolean + description: | + Enter Wake-Up mode when inactivity is detected, + reenter Measurement mode when activity is detected. + Only applies for Linked and Loop mode, ignored otherwise. diff --git a/dts/bindings/sensor/adi,adxl372-common.yaml b/dts/bindings/sensor/adi,adxl372-common.yaml index a56b9247a19e58..6c666dce8a9355 100644 --- a/dts/bindings/sensor/adi,adxl372-common.yaml +++ b/dts/bindings/sensor/adi,adxl372-common.yaml @@ -4,55 +4,55 @@ include: sensor-device.yaml properties: - odr: - type: int - default: 0 - description: | - Accelerometer sampling frequency (ODR). Default is power on reset value. - 0 # 400Hz - 1 # 800Hz - 2 # 1600Hz - 3 # 3200Hz - 4 # 6400Hz - enum: - - 0 - - 1 - - 2 - - 3 - - 4 + odr: + type: int + default: 0 + description: | + Accelerometer sampling frequency (ODR). Default is power on reset value. + 0 # 400Hz + 1 # 800Hz + 2 # 1600Hz + 3 # 3200Hz + 4 # 6400Hz + enum: + - 0 + - 1 + - 2 + - 3 + - 4 - bw: - type: int - default: 12 - description: | - Low-Pass (Antialiasing) Filter corner frequency. Default is power on reset value. - 0 # 200Hz - 1 # 400Hz - 2 # 800Hz - 3 # 1600Hz - 4 # 3200Hz - 12 # Disabled - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 12 + bw: + type: int + default: 12 + description: | + Low-Pass (Antialiasing) Filter corner frequency. Default is power on reset value. + 0 # 200Hz + 1 # 400Hz + 2 # 800Hz + 3 # 1600Hz + 4 # 3200Hz + 12 # Disabled + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 12 - hpf: - type: int - default: 4 - description: | - High-Pass Filter corner frequency. Default is power on reset value. - 0 # ODR/210 - 1 # ODR/411 - 2 # ODR/812 - 3 # ODR/1616 - 4 # Disabled - enum: - - 0 - - 1 - - 2 - - 3 - - 4 + hpf: + type: int + default: 4 + description: | + High-Pass Filter corner frequency. Default is power on reset value. + 0 # ODR/210 + 1 # ODR/411 + 2 # ODR/812 + 3 # ODR/1616 + 4 # Disabled + enum: + - 0 + - 1 + - 2 + - 3 + - 4 diff --git a/dts/bindings/sensor/adi,adxl372-i2c.yaml b/dts/bindings/sensor/adi,adxl372-i2c.yaml index cf53e6ea2affd4..2da0abcac77b55 100644 --- a/dts/bindings/sensor/adi,adxl372-i2c.yaml +++ b/dts/bindings/sensor/adi,adxl372-i2c.yaml @@ -8,9 +8,9 @@ compatible: "adi,adxl372" include: ["i2c-device.yaml", "adi,adxl372-common.yaml"] properties: - int1-gpios: - type: phandle-array - description: | - The INT1 signal defaults to active high as produced by the - sensor. The property value should ensure the flags properly - describe the signal that is presented to the driver. + int1-gpios: + type: phandle-array + description: | + The INT1 signal defaults to active high as produced by the + sensor. The property value should ensure the flags properly + describe the signal that is presented to the driver. diff --git a/dts/bindings/sensor/adi,adxl372-spi.yaml b/dts/bindings/sensor/adi,adxl372-spi.yaml index 06c16da7aaef3e..7d6863c3118117 100644 --- a/dts/bindings/sensor/adi,adxl372-spi.yaml +++ b/dts/bindings/sensor/adi,adxl372-spi.yaml @@ -9,9 +9,9 @@ compatible: "adi,adxl372" include: ["spi-device.yaml", "adi,adxl372-common.yaml"] properties: - int1-gpios: - type: phandle-array - description: | - The INT1 signal defaults to active high as produced by the - sensor. The property value should ensure the flags properly - describe the signal that is presented to the driver. + int1-gpios: + type: phandle-array + description: | + The INT1 signal defaults to active high as produced by the + sensor. The property value should ensure the flags properly + describe the signal that is presented to the driver. diff --git a/dts/bindings/sensor/ams,as6212.yaml b/dts/bindings/sensor/ams,as6212.yaml index e1ecf05a16cb49..4604e9b50cb1af 100644 --- a/dts/bindings/sensor/ams,as6212.yaml +++ b/dts/bindings/sensor/ams,as6212.yaml @@ -10,8 +10,8 @@ compatible: "ams,as6212" include: i2c-device.yaml properties: - alert-gpios: - type: phandle-array - description: | - Identifies the ALERT signal, which is active-low open drain when - produced by the sensor. + alert-gpios: + type: phandle-array + description: | + Identifies the ALERT signal, which is active-low open drain when + produced by the sensor. diff --git a/dts/bindings/sensor/ams,ccs811.yaml b/dts/bindings/sensor/ams,ccs811.yaml index c6c3c957617760..66601c2e1c361f 100644 --- a/dts/bindings/sensor/ams,ccs811.yaml +++ b/dts/bindings/sensor/ams,ccs811.yaml @@ -8,21 +8,21 @@ compatible: "ams,ccs811" include: [sensor-device.yaml, i2c-device.yaml] properties: - wake-gpios: - type: phandle-array - description: | - The WAKEn pin is asserted to communicate with the sensor. The - sensor receives this as an active-low signal. + wake-gpios: + type: phandle-array + description: | + The WAKEn pin is asserted to communicate with the sensor. The + sensor receives this as an active-low signal. - reset-gpios: - type: phandle-array - description: | - The RESETn pin is asserted to disable the sensor causing a hard - reset. The sensor receives this as an active-low signal. + reset-gpios: + type: phandle-array + description: | + The RESETn pin is asserted to disable the sensor causing a hard + reset. The sensor receives this as an active-low signal. - irq-gpios: - type: phandle-array - description: | - The INTn pin signals that a new reading is available. The - sensor generates an active-low level signal which remains - asserted until the data is read. + irq-gpios: + type: phandle-array + description: | + The INTn pin signals that a new reading is available. The + sensor generates an active-low level signal which remains + asserted until the data is read. diff --git a/dts/bindings/sensor/atmel,sam-tc-qdec.yaml b/dts/bindings/sensor/atmel,sam-tc-qdec.yaml index f55c0d6f97e3c0..2effbfda4848e7 100644 --- a/dts/bindings/sensor/atmel,sam-tc-qdec.yaml +++ b/dts/bindings/sensor/atmel,sam-tc-qdec.yaml @@ -5,17 +5,17 @@ description: Atmel SAM Timer Counter (TC) QDEC node compatible: "atmel,sam-tc-qdec" include: - - name: sensor-device.yaml - - name: pinctrl-device.yaml + - name: sensor-device.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: array - description: peripheral ID - required: true + peripheral-id: + type: array + description: peripheral ID + required: true diff --git a/dts/bindings/sensor/avago,apds9960.yaml b/dts/bindings/sensor/avago,apds9960.yaml index dd79c9071d8b5d..904f98a8fc1606 100644 --- a/dts/bindings/sensor/avago,apds9960.yaml +++ b/dts/bindings/sensor/avago,apds9960.yaml @@ -8,11 +8,11 @@ compatible: "avago,apds9960" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - required: true - description: Interrupt pin. + int-gpios: + type: phandle-array + required: true + description: Interrupt pin. - The interrupt pin of APDS9960 is open-drain, active low. - If connected directly the MCU pin should be configured - as pull-up, active low. + The interrupt pin of APDS9960 is open-drain, active low. + If connected directly the MCU pin should be configured + as pull-up, active low. diff --git a/dts/bindings/sensor/bosch,bmc150_magn.yaml b/dts/bindings/sensor/bosch,bmc150_magn.yaml index 9ef7f1e240207c..04b493e95fd270 100644 --- a/dts/bindings/sensor/bosch,bmc150_magn.yaml +++ b/dts/bindings/sensor/bosch,bmc150_magn.yaml @@ -10,5 +10,5 @@ compatible: "bosch,bmc150_magn" include: [sensor-device.yaml, i2c-device.yaml] properties: - drdy-gpios: - type: phandle-array + drdy-gpios: + type: phandle-array diff --git a/dts/bindings/sensor/bosch,bmg160.yaml b/dts/bindings/sensor/bosch,bmg160.yaml index 25659a0638b586..9c592291a047b7 100644 --- a/dts/bindings/sensor/bosch,bmg160.yaml +++ b/dts/bindings/sensor/bosch,bmg160.yaml @@ -10,5 +10,5 @@ compatible: "bosch,bmg160" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array + int-gpios: + type: phandle-array diff --git a/dts/bindings/sensor/bosch,bmi160.yaml b/dts/bindings/sensor/bosch,bmi160.yaml index 698bc82037b38f..aade60041bf767 100644 --- a/dts/bindings/sensor/bosch,bmi160.yaml +++ b/dts/bindings/sensor/bosch,bmi160.yaml @@ -6,9 +6,9 @@ description: BMI160 inertial measurement unit include: sensor-device.yaml properties: - int-gpios: - type: phandle-array - description: | - This property specifies the connection for INT1, because the - Zephyr driver maps all interrupts to INT1. The signal defaults - to output low when produced by the sensor. + int-gpios: + type: phandle-array + description: | + This property specifies the connection for INT1, because the + Zephyr driver maps all interrupts to INT1. The signal defaults + to output low when produced by the sensor. diff --git a/dts/bindings/sensor/bosch,bmp388.yaml b/dts/bindings/sensor/bosch,bmp388.yaml index e4829878ca1756..e44e834caccdcf 100644 --- a/dts/bindings/sensor/bosch,bmp388.yaml +++ b/dts/bindings/sensor/bosch,bmp388.yaml @@ -6,101 +6,101 @@ include: sensor-device.yaml properties: - int-gpios: - type: phandle-array + int-gpios: + type: phandle-array - odr: - type: string - description: | - Default output data rate in Hz. Only the following values are allowed: - 200 - 200 - 5ms (default; chip reset value) - 100 - 100 - 10ms - 50 - 50 - 20ms - 25 - 25 - 40ms - 12.5 - 25/2 - 80ms - 6.25 - 25/4 - 160ms - 3.125 - 25/8 - 320ms - 1.563 - 25/16 - 640ms - .781 - 25/32 - 1.28s - .391 - 25/64 - 2.56s - .195 - 25/128 - 5.12s - .098 - 25/256 - 10.24s - .049 - 25/512 - 20.48s - .024 - 25/1024 - 40.96s - .012 - 25/2048 - 81.92s - .006 - 25/4096 - 163.84s - .003 - 25/8192 - 327.68s - default: "200" - enum: - - "200" - - "100" - - "50" - - "25" - - "12.5" - - "6.25" - - "3.125" - - "1.563" - - ".781" - - ".391" - - ".195" - - ".098" - - ".049" - - ".024" - - ".012" - - ".006" - - ".003" + odr: + type: string + description: | + Default output data rate in Hz. Only the following values are allowed: + 200 - 200 - 5ms (default; chip reset value) + 100 - 100 - 10ms + 50 - 50 - 20ms + 25 - 25 - 40ms + 12.5 - 25/2 - 80ms + 6.25 - 25/4 - 160ms + 3.125 - 25/8 - 320ms + 1.563 - 25/16 - 640ms + .781 - 25/32 - 1.28s + .391 - 25/64 - 2.56s + .195 - 25/128 - 5.12s + .098 - 25/256 - 10.24s + .049 - 25/512 - 20.48s + .024 - 25/1024 - 40.96s + .012 - 25/2048 - 81.92s + .006 - 25/4096 - 163.84s + .003 - 25/8192 - 327.68s + default: "200" + enum: + - "200" + - "100" + - "50" + - "25" + - "12.5" + - "6.25" + - "3.125" + - "1.563" + - ".781" + - ".391" + - ".195" + - ".098" + - ".049" + - ".024" + - ".012" + - ".006" + - ".003" - osr-press: - type: int - description: | - Default pressure oversampling rate. Only the following values are - allowed: - 1 sample, 16-bit, 2.64 Pa - 2 samples, 17-bit, 1.32 Pa - 4 samples, 18-bit, 0.66 Pa (default; chip reset value) - 8 samples, 19-bit, 0.33 Pa - 16 samples, 20-bit, 0.17 Pa - 32 Samples, 21-bit, 0.085 Pa - default: 4 - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 + osr-press: + type: int + description: | + Default pressure oversampling rate. Only the following values are + allowed: + 1 sample, 16-bit, 2.64 Pa + 2 samples, 17-bit, 1.32 Pa + 4 samples, 18-bit, 0.66 Pa (default; chip reset value) + 8 samples, 19-bit, 0.33 Pa + 16 samples, 20-bit, 0.17 Pa + 32 Samples, 21-bit, 0.085 Pa + default: 4 + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 - osr-temp: - type: int - description: | - Default temperature oversampling rate. Only the following values are - allowed: - 1 sample, 16-bit, .0050 C (default; chip reset value) - 2 samples, 17-bit, .0025 C - 4 samples, 18-bit, .0012 C - 8 samples, 19-bit, .0006 C - 16 samples, 20-bit, .0003 C - 32 Samples, 21-bit, .00015 C - default: 1 - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 + osr-temp: + type: int + description: | + Default temperature oversampling rate. Only the following values are + allowed: + 1 sample, 16-bit, .0050 C (default; chip reset value) + 2 samples, 17-bit, .0025 C + 4 samples, 18-bit, .0012 C + 8 samples, 19-bit, .0006 C + 16 samples, 20-bit, .0003 C + 32 Samples, 21-bit, .00015 C + default: 1 + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 - iir-filter: - type: int - description: | - Default IIR filter coefficient. The default 0 is the chip reset value. - default: 0 - enum: - - 0 - - 1 - - 3 - - 7 - - 15 - - 31 - - 63 - - 127 + iir-filter: + type: int + description: | + Default IIR filter coefficient. The default 0 is the chip reset value. + default: 0 + enum: + - 0 + - 1 + - 3 + - 7 + - 15 + - 31 + - 63 + - 127 diff --git a/dts/bindings/sensor/espressif,esp32-temp.yaml b/dts/bindings/sensor/espressif,esp32-temp.yaml index 0acaf9e928f19e..32bf13a3013701 100644 --- a/dts/bindings/sensor/espressif,esp32-temp.yaml +++ b/dts/bindings/sensor/espressif,esp32-temp.yaml @@ -8,17 +8,17 @@ compatible: "espressif,esp32-temp" include: sensor-device.yaml properties: - range: - type: int - description: | - The temperature sensor is available on the ESP32-S2, ESP32-C3. Note - that it is unavailable on the ESP32 due to missing offset calibration. - Temperature range is defined by the temperature offset which is used - during calculation of the output temperature from the measured value. - default: 2 - enum: - - 0 # measure range: 50°C ~ 125°C, error < 3°C - - 1 # measure range: 20°C ~ 100°C, error < 2°C - - 2 # measure range:-10°C ~ 80°C, error < 1°C - - 3 # measure range:-30°C ~ 50°C, error < 2°C - - 4 # measure range:-40°C ~ 20°C, error < 3°C + range: + type: int + description: | + The temperature sensor is available on the ESP32-S2, ESP32-C3. Note + that it is unavailable on the ESP32 due to missing offset calibration. + Temperature range is defined by the temperature offset which is used + during calculation of the output temperature from the measured value. + default: 2 + enum: + - 0 # measure range: 50°C ~ 125°C, error < 3°C + - 1 # measure range: 20°C ~ 100°C, error < 2°C + - 2 # measure range:-10°C ~ 80°C, error < 1°C + - 3 # measure range:-30°C ~ 50°C, error < 2°C + - 4 # measure range:-40°C ~ 20°C, error < 3°C diff --git a/dts/bindings/sensor/honeywell,hmc5883l.yaml b/dts/bindings/sensor/honeywell,hmc5883l.yaml index 8c222d1bf107e7..e2ec24f358276a 100644 --- a/dts/bindings/sensor/honeywell,hmc5883l.yaml +++ b/dts/bindings/sensor/honeywell,hmc5883l.yaml @@ -8,10 +8,10 @@ compatible: "honeywell,hmc5883l" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: DRDY pin + int-gpios: + type: phandle-array + description: DRDY pin - This pin is active low, with an internal pullup in the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin is active low, with an internal pullup in the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/honeywell,sm351lt.yaml b/dts/bindings/sensor/honeywell,sm351lt.yaml index f12045fc10a2a9..b199ad87690656 100644 --- a/dts/bindings/sensor/honeywell,sm351lt.yaml +++ b/dts/bindings/sensor/honeywell,sm351lt.yaml @@ -8,7 +8,7 @@ compatible: "honeywell,sm351lt" include: sensor-device.yaml properties: - gpios: - type: phandle-array - required: true - description: GPIO connected to the sensor + gpios: + type: phandle-array + required: true + description: GPIO connected to the sensor diff --git a/dts/bindings/sensor/hzgrow,r502a.yaml b/dts/bindings/sensor/hzgrow,r502a.yaml index 8e5492bb849513..f519b70ef39bb1 100644 --- a/dts/bindings/sensor/hzgrow,r502a.yaml +++ b/dts/bindings/sensor/hzgrow,r502a.yaml @@ -8,21 +8,21 @@ compatible: "hzgrow,r502a" include: [sensor-device.yaml, uart-device.yaml] properties: - reg: - required: true - int-gpios: - type: phandle-array - required: true - description: | - Interrupt pin. When the sensor is touched, the GPIO is set to high. - It is used to trigger a fingerprint enroll or match operations. - vin-gpios: - type: phandle-array - required: false - description: | - Voltage input pin to the fingerprint sensor. - act-gpios: - type: phandle-array - required: false - description: | - Finger detection power pin to detect the presence of finger. + reg: + required: true + int-gpios: + type: phandle-array + required: true + description: | + Interrupt pin. When the sensor is touched, the GPIO is set to high. + It is used to trigger a fingerprint enroll or match operations. + vin-gpios: + type: phandle-array + required: false + description: | + Voltage input pin to the fingerprint sensor. + act-gpios: + type: phandle-array + required: false + description: | + Finger detection power pin to detect the presence of finger. diff --git a/dts/bindings/sensor/invensense,icm42605.yaml b/dts/bindings/sensor/invensense,icm42605.yaml index a6305ca38fabb3..1781c5e903b2d0 100644 --- a/dts/bindings/sensor/invensense,icm42605.yaml +++ b/dts/bindings/sensor/invensense,icm42605.yaml @@ -9,77 +9,77 @@ compatible: "invensense,icm42605" include: [sensor-device.yaml, spi-device.yaml] properties: - int-gpios: - type: phandle-array - required: true - description: | - The INT signal default configuration is active-high. The - property value should ensure the flags properly describe the - signal that is presented to the driver. + int-gpios: + type: phandle-array + required: true + description: | + The INT signal default configuration is active-high. The + property value should ensure the flags properly describe the + signal that is presented to the driver. - accel-hz: - type: int - default: 12 - description: | - Default frequency of accelerometer. (Unit - Hz) - Maps to ACCEL_ODR field in ACCEL_CONFIG0 setting - enum: - - 1 - - 3 - - 6 - - 12 - - 25 - - 50 - - 100 - - 200 - - 500 - - 1000 - - 2000 - - 4000 - - 8000 + accel-hz: + type: int + default: 12 + description: | + Default frequency of accelerometer. (Unit - Hz) + Maps to ACCEL_ODR field in ACCEL_CONFIG0 setting + enum: + - 1 + - 3 + - 6 + - 12 + - 25 + - 50 + - 100 + - 200 + - 500 + - 1000 + - 2000 + - 4000 + - 8000 - gyro-hz: - type: int - default: 12 - description: | - Default frequency of gyroscope. (Unit - Hz) - Maps to GYRO_ODR field in GYRO_CONFIG0 setting - enum: - - 12 - - 25 - - 50 - - 100 - - 200 - - 500 - - 1000 - - 2000 - - 4000 - - 8000 + gyro-hz: + type: int + default: 12 + description: | + Default frequency of gyroscope. (Unit - Hz) + Maps to GYRO_ODR field in GYRO_CONFIG0 setting + enum: + - 12 + - 25 + - 50 + - 100 + - 200 + - 500 + - 1000 + - 2000 + - 4000 + - 8000 - accel-fs: - type: int - default: 16 - description: | - Default full scale of accelerometer. (Unit - g) - Maps to ACCEL_FS_SEL field in ACCEL_CONFIG0 setting - enum: - - 16 - - 8 - - 4 - - 2 + accel-fs: + type: int + default: 16 + description: | + Default full scale of accelerometer. (Unit - g) + Maps to ACCEL_FS_SEL field in ACCEL_CONFIG0 setting + enum: + - 16 + - 8 + - 4 + - 2 - gyro-fs: - type: int - default: 2000 - description: | - Default full scale of gyroscope. (Unit - DPS) - Maps to GYRO_FS_SEL field in GYRO_CONFIG0 setting - enum: - - 2000 - - 1000 - - 500 - - 250 - - 125 - - 62.5 - - 31.25 - - 15.625 + gyro-fs: + type: int + default: 2000 + description: | + Default full scale of gyroscope. (Unit - DPS) + Maps to GYRO_FS_SEL field in GYRO_CONFIG0 setting + enum: + - 2000 + - 1000 + - 500 + - 250 + - 125 + - 62.5 + - 31.25 + - 15.625 diff --git a/dts/bindings/sensor/invensense,icm42670.yaml b/dts/bindings/sensor/invensense,icm42670.yaml index 2a6bec637e4e36..1f2ddebfc984a4 100644 --- a/dts/bindings/sensor/invensense,icm42670.yaml +++ b/dts/bindings/sensor/invensense,icm42670.yaml @@ -9,72 +9,72 @@ compatible: "invensense,icm42670" include: [sensor-device.yaml, spi-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - The INT signal default configuration is active-high. The - property value should ensure the flags properly describe the - signal that is presented to the driver. + int-gpios: + type: phandle-array + description: | + The INT signal default configuration is active-high. The + property value should ensure the flags properly describe the + signal that is presented to the driver. - accel-hz: - type: int - required: true - description: | - Default frequency of accelerometer. (Unit - Hz) - Maps to ACCEL_ODR field in ACCEL_CONFIG0 setting - Power-on reset value is 800. - enum: - - 1 - - 3 - - 6 - - 12 - - 25 - - 50 - - 100 - - 200 - - 400 - - 800 - - 1600 + accel-hz: + type: int + required: true + description: | + Default frequency of accelerometer. (Unit - Hz) + Maps to ACCEL_ODR field in ACCEL_CONFIG0 setting + Power-on reset value is 800. + enum: + - 1 + - 3 + - 6 + - 12 + - 25 + - 50 + - 100 + - 200 + - 400 + - 800 + - 1600 - gyro-hz: - type: int - required: true - description: | - Default frequency of gyroscope. (Unit - Hz) - Maps to GYRO_ODR field in GYRO_CONFIG0 setting - Power-on reset value is 800. - enum: - - 12 - - 25 - - 50 - - 100 - - 200 - - 400 - - 800 - - 1600 + gyro-hz: + type: int + required: true + description: | + Default frequency of gyroscope. (Unit - Hz) + Maps to GYRO_ODR field in GYRO_CONFIG0 setting + Power-on reset value is 800. + enum: + - 12 + - 25 + - 50 + - 100 + - 200 + - 400 + - 800 + - 1600 - accel-fs: - type: int - required: true - description: | - Default full scale of accelerometer. (Unit - g) - Maps to ACCEL_FS_SEL field in ACCEL_CONFIG0 setting - Power-on reset value is 16 - enum: - - 16 - - 8 - - 4 - - 2 + accel-fs: + type: int + required: true + description: | + Default full scale of accelerometer. (Unit - g) + Maps to ACCEL_FS_SEL field in ACCEL_CONFIG0 setting + Power-on reset value is 16 + enum: + - 16 + - 8 + - 4 + - 2 - gyro-fs: - type: int - required: true - description: | - Default full scale of gyroscope. (Unit - DPS) - Maps to GYRO_FS_SEL field in GYRO_CONFIG0 setting - Power-on reset value is 2000 - enum: - - 2000 - - 1000 - - 500 - - 250 + gyro-fs: + type: int + required: true + description: | + Default full scale of gyroscope. (Unit - DPS) + Maps to GYRO_FS_SEL field in GYRO_CONFIG0 setting + Power-on reset value is 2000 + enum: + - 2000 + - 1000 + - 500 + - 250 diff --git a/dts/bindings/sensor/invensense,icp10125.yaml b/dts/bindings/sensor/invensense,icp10125.yaml index 4936c843eb70fc..78fa69d7851754 100644 --- a/dts/bindings/sensor/invensense,icp10125.yaml +++ b/dts/bindings/sensor/invensense,icp10125.yaml @@ -8,22 +8,22 @@ compatible: "invensense,icp10125" include: [sensor-device.yaml, i2c-device.yaml] properties: - temperature-measurement-mode: - type: string - required: true - description: Mode of ambient temperature measurement - enum: - - "low-power" - - "normal" - - "low-noise" - - "ultra-low-noise" + temperature-measurement-mode: + type: string + required: true + description: Mode of ambient temperature measurement + enum: + - "low-power" + - "normal" + - "low-noise" + - "ultra-low-noise" - pressure-measurement-mode: - type: string - required: true - description: Mode of barometric pressure measurement - enum: - - "low-power" - - "normal" - - "low-noise" - - "ultra-low-noise" + pressure-measurement-mode: + type: string + required: true + description: Mode of barometric pressure measurement + enum: + - "low-power" + - "normal" + - "low-noise" + - "ultra-low-noise" diff --git a/dts/bindings/sensor/invensense,mpu6050.yaml b/dts/bindings/sensor/invensense,mpu6050.yaml index dd1b8997b856e7..6e56444008ebfa 100644 --- a/dts/bindings/sensor/invensense,mpu6050.yaml +++ b/dts/bindings/sensor/invensense,mpu6050.yaml @@ -10,9 +10,9 @@ compatible: "invensense,mpu6050" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - The INT signal default configuration is active-high. The - property value should ensure the flags properly describe the - signal that is presented to the driver. + int-gpios: + type: phandle-array + description: | + The INT signal default configuration is active-high. The + property value should ensure the flags properly describe the + signal that is presented to the driver. diff --git a/dts/bindings/sensor/invensense,mpu9250.yaml b/dts/bindings/sensor/invensense,mpu9250.yaml index 8a4280bc1b7faf..6764582424b5d7 100644 --- a/dts/bindings/sensor/invensense,mpu9250.yaml +++ b/dts/bindings/sensor/invensense,mpu9250.yaml @@ -10,75 +10,75 @@ compatible: "invensense,mpu9250" include: [sensor-device.yaml, i2c-device.yaml] properties: - irq-gpios: - type: phandle-array - description: | - The INT signal default configuration is active-high. The - property value should ensure the flags properly describe the - signal that is presented to the driver. - This property is required when the trigger mode is used. + irq-gpios: + type: phandle-array + description: | + The INT signal default configuration is active-high. The + property value should ensure the flags properly describe the + signal that is presented to the driver. + This property is required when the trigger mode is used. - gyro-sr-div: - type: int - required: true - description: | - Default gyrscope sample rate divider. This divider is only effective - when gyro-dlpf is in range 5-184. - rate = sample_rate / (1 + gyro-sr-div) - Valid range: 0 - 255 + gyro-sr-div: + type: int + required: true + description: | + Default gyrscope sample rate divider. This divider is only effective + when gyro-dlpf is in range 5-184. + rate = sample_rate / (1 + gyro-sr-div) + Valid range: 0 - 255 - gyro-dlpf: - type: int - required: true - description: | - Default digital low pass filter frequency of gyroscope. - Maps to DLPF_CFG field in Configuration setting. - enum: - - 250 - - 184 - - 92 - - 41 - - 20 - - 10 - - 5 - - 3600 + gyro-dlpf: + type: int + required: true + description: | + Default digital low pass filter frequency of gyroscope. + Maps to DLPF_CFG field in Configuration setting. + enum: + - 250 + - 184 + - 92 + - 41 + - 20 + - 10 + - 5 + - 3600 - gyro-fs: - type: int - required: true - description: | - Default full scale of gyroscope. (Unit - DPS). - Maps to GYRO_FS_SEL field in Gyroscope Configuration setting. - enum: - - 250 - - 500 - - 1000 - - 2000 + gyro-fs: + type: int + required: true + description: | + Default full scale of gyroscope. (Unit - DPS). + Maps to GYRO_FS_SEL field in Gyroscope Configuration setting. + enum: + - 250 + - 500 + - 1000 + - 2000 - accel-fs: - type: int - required: true - description: | - Default full scale of accelerometer. (Unit - g) - Maps to ACCEL_FS_SEL field in Accelerometer Configuration setting - enum: - - 2 - - 4 - - 8 - - 16 + accel-fs: + type: int + required: true + description: | + Default full scale of accelerometer. (Unit - g) + Maps to ACCEL_FS_SEL field in Accelerometer Configuration setting + enum: + - 2 + - 4 + - 8 + - 16 - accel-dlpf: - type: string - required: true - description: | - Default digital low pass filter frequency of accelerometer. - Maps to DLPF_CFG field in Accelerometer Configuration 2 setting. - enum: - - "218.1" - - "218.1a" - - "99" - - "44.8" - - "21.2" - - "10.2" - - "5.05" - - "420" + accel-dlpf: + type: string + required: true + description: | + Default digital low pass filter frequency of accelerometer. + Maps to DLPF_CFG field in Accelerometer Configuration 2 setting. + enum: + - "218.1" + - "218.1a" + - "99" + - "44.8" + - "21.2" + - "10.2" + - "5.05" + - "420" diff --git a/dts/bindings/sensor/isil,isl29035.yaml b/dts/bindings/sensor/isil,isl29035.yaml index 1284185b3ef8b8..6d8becd7999208 100644 --- a/dts/bindings/sensor/isil,isl29035.yaml +++ b/dts/bindings/sensor/isil,isl29035.yaml @@ -10,9 +10,9 @@ compatible: "isil,isl29035" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - The INT pin defaults to active low when produced by the sensor. - The property value should ensure the flags properly describe the - signal that is presented to the driver. + int-gpios: + type: phandle-array + description: | + The INT pin defaults to active low when produced by the sensor. + The property value should ensure the flags properly describe the + signal that is presented to the driver. diff --git a/dts/bindings/sensor/lm77.yaml b/dts/bindings/sensor/lm77.yaml index 367c60fe511004..01531cd103af8a 100644 --- a/dts/bindings/sensor/lm77.yaml +++ b/dts/bindings/sensor/lm77.yaml @@ -9,26 +9,26 @@ compatible: "lm77" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - Identifies the INT signal, which is active-low open drain by default - when produced by the sensor. + int-gpios: + type: phandle-array + description: | + Identifies the INT signal, which is active-low open drain by default + when produced by the sensor. - int-inverted: - type: boolean - description: | - When present, the polarity on the INT signal is inverted (active-high). + int-inverted: + type: boolean + description: | + When present, the polarity on the INT signal is inverted (active-high). - tcrita-inverted: - type: boolean - description: | - When present, the polarity on the T_CRIT_A signal is inverted - (active-high). + tcrita-inverted: + type: boolean + description: | + When present, the polarity on the T_CRIT_A signal is inverted + (active-high). - enable-fault-queue: - type: boolean - description: | - When present, the fault queue is enabled. The fault queue allows up to 4 - faults to prevent false INT/T_CRIT_A tripping when the LM77 is used in - noisy environments. + enable-fault-queue: + type: boolean + description: | + When present, the fault queue is enabled. The fault queue allows up to 4 + faults to prevent false INT/T_CRIT_A tripping when the LM77 is used in + noisy environments. diff --git a/dts/bindings/sensor/maxim,ds18b20.yaml b/dts/bindings/sensor/maxim,ds18b20.yaml index 0da3bc659b8b1b..a48c852374fec6 100644 --- a/dts/bindings/sensor/maxim,ds18b20.yaml +++ b/dts/bindings/sensor/maxim,ds18b20.yaml @@ -8,9 +8,9 @@ compatible: "maxim,ds18b20" include: [sensor-device.yaml, w1-slave.yaml] properties: - resolution: - type: int - required: true - description: | - Resolution of the temperature reading in bit. - Valid configurations are from 9 to 12 bits. + resolution: + type: int + required: true + description: | + Resolution of the temperature reading in bit. + Valid configurations are from 9 to 12 bits. diff --git a/dts/bindings/sensor/maxim,max17055.yaml b/dts/bindings/sensor/maxim,max17055.yaml index c6089ab896c04f..34ea4c762d87e9 100644 --- a/dts/bindings/sensor/maxim,max17055.yaml +++ b/dts/bindings/sensor/maxim,max17055.yaml @@ -11,38 +11,38 @@ compatible: "maxim,max17055" include: [sensor-device.yaml, i2c-device.yaml] properties: - design-capacity: - type: int - required: true - description: The design capacity (aka label capacity) of the cell in mAh - - design-voltage: - type: int - required: true - description: Battery Design Voltage in mV (3300 to 4400) - - desired-voltage: - type: int - required: true - description: Battery Desired Voltage in mV (3300 to 4400) - - desired-charging-current: - type: int - required: true - description: Battery Design Charging Current in mA (e.g. 2000) - - i-chg-term: - type: int - required: true - description: The charge termination current in mA - - rsense-mohms: - type: int - required: true - description: | - Value of Rsense resistor in milliohms (e.g. 5). It cannot be 0. - - v-empty: - type: int - required: true - description: The empty voltage of the cell in mV + design-capacity: + type: int + required: true + description: The design capacity (aka label capacity) of the cell in mAh + + design-voltage: + type: int + required: true + description: Battery Design Voltage in mV (3300 to 4400) + + desired-voltage: + type: int + required: true + description: Battery Desired Voltage in mV (3300 to 4400) + + desired-charging-current: + type: int + required: true + description: Battery Design Charging Current in mA (e.g. 2000) + + i-chg-term: + type: int + required: true + description: The charge termination current in mA + + rsense-mohms: + type: int + required: true + description: | + Value of Rsense resistor in milliohms (e.g. 5). It cannot be 0. + + v-empty: + type: int + required: true + description: The empty voltage of the cell in mV diff --git a/dts/bindings/sensor/maxim,max17262.yaml b/dts/bindings/sensor/maxim,max17262.yaml index 01651fb125a6db..4d01864c28bfea 100644 --- a/dts/bindings/sensor/maxim,max17262.yaml +++ b/dts/bindings/sensor/maxim,max17262.yaml @@ -11,37 +11,37 @@ compatible: "maxim,max17262" include: [sensor-device.yaml, i2c-device.yaml] properties: - design-voltage: - type: int - required: true - description: Battery Design Voltage in mV (3300 to 4400) - - desired-voltage: - type: int - required: true - description: Battery Desired Voltage in mV (3300 to 4400) - - desired-charging-current: - type: int - required: true - description: Battery Design Charging Current in mA (e.g. 2000) - - design-cap: - type: int - required: true - description: Battery Capacity in mAh (default 3000) - - empty-voltage: - type: int - required: true - description: Empty voltage target during load in mV (default 3300) - - recovery-voltage: - type: int - required: true - description: The voltage level for clearing empty detection in mV (default 3880) - - charge-voltage: - type: int - required: true - description: Charge voltage in mV + design-voltage: + type: int + required: true + description: Battery Design Voltage in mV (3300 to 4400) + + desired-voltage: + type: int + required: true + description: Battery Desired Voltage in mV (3300 to 4400) + + desired-charging-current: + type: int + required: true + description: Battery Design Charging Current in mA (e.g. 2000) + + design-cap: + type: int + required: true + description: Battery Capacity in mAh (default 3000) + + empty-voltage: + type: int + required: true + description: Empty voltage target during load in mV (default 3300) + + recovery-voltage: + type: int + required: true + description: The voltage level for clearing empty detection in mV (default 3880) + + charge-voltage: + type: int + required: true + description: Charge voltage in mV diff --git a/dts/bindings/sensor/maxim,max44009.yaml b/dts/bindings/sensor/maxim,max44009.yaml index a410a6980faf25..47657cd3348e39 100644 --- a/dts/bindings/sensor/maxim,max44009.yaml +++ b/dts/bindings/sensor/maxim,max44009.yaml @@ -10,5 +10,5 @@ compatible: "maxim,max44009" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array + int-gpios: + type: phandle-array diff --git a/dts/bindings/sensor/microchip,mcp9808.yaml b/dts/bindings/sensor/microchip,mcp9808.yaml index cc823957b4297d..7467d75e0f8bc4 100644 --- a/dts/bindings/sensor/microchip,mcp9808.yaml +++ b/dts/bindings/sensor/microchip,mcp9808.yaml @@ -10,22 +10,22 @@ compatible: "microchip,mcp9808" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - The alert pin defaults to active low when produced by the - sensor, and is open-drain. A pull-up may be appropriate. The - property value should ensure the flags properly describe the - signal that is presented to the driver. + int-gpios: + type: phandle-array + description: | + The alert pin defaults to active low when produced by the + sensor, and is open-drain. A pull-up may be appropriate. The + property value should ensure the flags properly describe the + signal that is presented to the driver. - resolution: - type: int - default: 3 - description: | - Sensor resolution. Default is 0.0625C (0b11), - which is the power-up default. - enum: - - 0 # 0.5C - - 1 # 0.25C - - 2 # 0.125C - - 3 # 0.0625C + resolution: + type: int + default: 3 + description: | + Sensor resolution. Default is 0.0625C (0b11), + which is the power-up default. + enum: + - 0 # 0.5C + - 1 # 0.25C + - 2 # 0.125C + - 3 # 0.0625C diff --git a/dts/bindings/sensor/nordic,nrf-qdec.yaml b/dts/bindings/sensor/nordic,nrf-qdec.yaml index c8a209f68a4923..372db4a30d8ced 100644 --- a/dts/bindings/sensor/nordic,nrf-qdec.yaml +++ b/dts/bindings/sensor/nordic,nrf-qdec.yaml @@ -8,63 +8,63 @@ compatible: "nordic,nrf-qdec" include: [sensor-device.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - a-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The A pin to use. - - For pins P0.0 through P0.31, use the pin number. For example, - to use P0.16 for the A pin, set: - - a-pin = <16>; - - For pins P1.0 through P1.31, add 32 to the pin number. For - example, to use P1.2 for the A pin, set: - - a-pin = <34>; /* 32 + 2 */ - - b-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The B pin to use. The pin numbering scheme is the same as - the a-pin property's. - - led-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The LED pin to use for a light based QDEC device. The pin - numbering scheme is the same as the a-pin property's. - - enable-pin: - type: int - description: | - The enable pin to use, to enable a connected QDEC device. The - pin numbering scheme is the same as the a-pin property's. - - led-pre: - type: int - description: Time LED is enabled prior to sampling event (in us) - required: true - - steps: - type: int - description: Number of steps on the rotating wheel - required: true + reg: + required: true + + interrupts: + required: true + + a-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The A pin to use. + + For pins P0.0 through P0.31, use the pin number. For example, + to use P0.16 for the A pin, set: + + a-pin = <16>; + + For pins P1.0 through P1.31, add 32 to the pin number. For + example, to use P1.2 for the A pin, set: + + a-pin = <34>; /* 32 + 2 */ + + b-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The B pin to use. The pin numbering scheme is the same as + the a-pin property's. + + led-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The LED pin to use for a light based QDEC device. The pin + numbering scheme is the same as the a-pin property's. + + enable-pin: + type: int + description: | + The enable pin to use, to enable a connected QDEC device. The + pin numbering scheme is the same as the a-pin property's. + + led-pre: + type: int + description: Time LED is enabled prior to sampling event (in us) + required: true + + steps: + type: int + description: Number of steps on the rotating wheel + required: true diff --git a/dts/bindings/sensor/nordic,nrf-temp.yaml b/dts/bindings/sensor/nordic,nrf-temp.yaml index b45e9ee58e74bf..ceb35811222a11 100644 --- a/dts/bindings/sensor/nordic,nrf-temp.yaml +++ b/dts/bindings/sensor/nordic,nrf-temp.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-temp" include: sensor-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/sensor/nuvoton,adc-cmp.yaml b/dts/bindings/sensor/nuvoton,adc-cmp.yaml index 9acbc3191e7b12..769304b25b2320 100644 --- a/dts/bindings/sensor/nuvoton,adc-cmp.yaml +++ b/dts/bindings/sensor/nuvoton,adc-cmp.yaml @@ -9,22 +9,22 @@ compatible: "nuvoton,adc-cmp" include: sensor-device.yaml properties: - io-channels: - type: phandle-array - required: true - description: | - ADC channel that will perform measurement. + io-channels: + type: phandle-array + required: true + description: | + ADC channel that will perform measurement. - threshold-mv: - type: int - description: | - Value in millivolts present on ADC data as threshold assert. + threshold-mv: + type: int + description: | + Value in millivolts present on ADC data as threshold assert. - comparison: - type: string - description: | - Determines the condition to be met between ADC data and - threshold assert value that will trigger comparator event. - enum: - - ADC_CMP_NPCX_GREATER - - ADC_CMP_NPCX_LESS_OR_EQUAL + comparison: + type: string + description: | + Determines the condition to be met between ADC data and + threshold assert value that will trigger comparator event. + enum: + - ADC_CMP_NPCX_GREATER + - ADC_CMP_NPCX_LESS_OR_EQUAL diff --git a/dts/bindings/sensor/nxp,fxas21002-common.yaml b/dts/bindings/sensor/nxp,fxas21002-common.yaml index 2260f77064cb28..d88d7be26a2352 100644 --- a/dts/bindings/sensor/nxp,fxas21002-common.yaml +++ b/dts/bindings/sensor/nxp,fxas21002-common.yaml @@ -6,26 +6,26 @@ description: FXAS21002 3-axis gyroscope sensor include: sensor-device.yaml properties: - reset-gpios: - type: phandle-array - description: | - RST pin - This pin defaults to active low when consumed by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + reset-gpios: + type: phandle-array + description: | + RST pin + This pin defaults to active low when consumed by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. - int1-gpios: - type: phandle-array - description: | - INT1 pin - This pin defaults to active low when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + int1-gpios: + type: phandle-array + description: | + INT1 pin + This pin defaults to active low when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. - int2-gpios: - type: phandle-array - description: | - INT2 pin - This pin defaults to active low when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + int2-gpios: + type: phandle-array + description: | + INT2 pin + This pin defaults to active low when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/nxp,fxos8700-common.yaml b/dts/bindings/sensor/nxp,fxos8700-common.yaml index 605baa8b44eee6..79cd77521cbccf 100644 --- a/dts/bindings/sensor/nxp,fxos8700-common.yaml +++ b/dts/bindings/sensor/nxp,fxos8700-common.yaml @@ -6,137 +6,137 @@ description: FXOS8700 6-axis accelerometer/magnetometer sensor include: sensor-device.yaml properties: - reset-gpios: - type: phandle-array - description: | - RST pin - This pin defaults to active high when consumed by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. - - int1-gpios: - type: phandle-array - description: | - INT1 pin - This pin defaults to active low when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. - - int2-gpios: - type: phandle-array - description: | - INT2 pin - This pin defaults to active low when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. - - range: - type: int - default: 8 - description: Range in g - enum: - - 8 # 8g (0.976 mg/LSB) - - 4 # 4g (0.488 mg/LSB) - - 2 # 2g (0.244 mg/LSB) - - power-mode: - type: int - default: 0 - description: Power mode - enum: - - 0 # Normal - - 1 # Low noise, low power - - 2 # High resolution - - 3 # Low power - - pulse-cfg: - type: int - default: 0x3f - description: Pulse configuration register - - pulse-thsx: - type: int - default: 0x20 - description: | - Pulse X-axis threshold - Threshold to start the pulse-event detection procedure on the X-axis. - Threshold values for each axis are unsigned 7-bit numbers with a fixed - resolution of 0.063 g/LSB, corresponding to an 8g acceleration - full-scale range. - - pulse-thsy: - type: int - default: 0x20 - description: | - Pulse Y-axis threshold - Threshold to start the pulse-event detection procedure on the Y-axis. - Threshold values for each axis are unsigned 7-bit numbers with a fixed - resolution of 0.063 g/LSB, corresponding to an 8g acceleration - full-scale range. - - pulse-thsz: - type: int - default: 0x40 - description: | - Pulse Z-axis threshold - Threshold to start the pulse-event detection procedure on the Z-axis. - Threshold values for each axis are unsigned 7-bit numbers with a fixed - resolution of 0.063 g/LSB, corresponding to an 8g acceleration - full-scale range. - - pulse-tmlt: - type: int - default: 0x18 - description: | - Pulse time limit - The maximum time interval that can elapse between the start of the - acceleration on the selected channel exceeding the specified threshold - and the end when the channel acceleration goes back below the specified - threshold. The resolution depends upon the sample rate (ODR) and the - high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For - ODR=800 Hz and pls_hpf_en=0, the resolution is 0.625 ms/LSB. - - pulse-ltcy: - type: int - default: 0x28 - description: | - Pulse latency - The time interval that starts after the first pulse detection where the - pulse-detection function ignores the start of a new pulse. The - resolution depends upon the sample rate (ODR) and the high-pass filter - configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and - pls_hpf_en=0, the resolution is 1.25 ms/LSB. - - pulse-wind: - type: int - default: 0x3c - description: | - Pulse window - The maximum interval of time that can elapse after the end of the - latency interval in which the start of the second pulse event must be - detected provided the device has been configured for double pulse - detection. The detected second pulse width must be shorter than the - time limit constraint specified by the PULSE_TMLT register, but the end - of the double pulse need not finish within the time specified by the - PULSE_WIND register. The resolution depends upon the sample rate (ODR) - and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). - For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB. - - mag-vecm-cfg: - type: int - default: 0x4e - description: Magnetic vector-magnitude configuration register - - mag-vecm-ths-msb: - type: int - default: 0x00 - description: | - Magnetic vector-magnitude threshold most significant byte. - Resolution is 0.1 uT/LSB. - - mag-vecm-ths-lsb: - type: int - default: 0x5a - description: | - Magnetic vector-magnitude threshold least significant byte. - Resolution is 0.1 uT/LSB. + reset-gpios: + type: phandle-array + description: | + RST pin + This pin defaults to active high when consumed by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + int1-gpios: + type: phandle-array + description: | + INT1 pin + This pin defaults to active low when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + int2-gpios: + type: phandle-array + description: | + INT2 pin + This pin defaults to active low when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + range: + type: int + default: 8 + description: Range in g + enum: + - 8 # 8g (0.976 mg/LSB) + - 4 # 4g (0.488 mg/LSB) + - 2 # 2g (0.244 mg/LSB) + + power-mode: + type: int + default: 0 + description: Power mode + enum: + - 0 # Normal + - 1 # Low noise, low power + - 2 # High resolution + - 3 # Low power + + pulse-cfg: + type: int + default: 0x3f + description: Pulse configuration register + + pulse-thsx: + type: int + default: 0x20 + description: | + Pulse X-axis threshold + Threshold to start the pulse-event detection procedure on the X-axis. + Threshold values for each axis are unsigned 7-bit numbers with a fixed + resolution of 0.063 g/LSB, corresponding to an 8g acceleration + full-scale range. + + pulse-thsy: + type: int + default: 0x20 + description: | + Pulse Y-axis threshold + Threshold to start the pulse-event detection procedure on the Y-axis. + Threshold values for each axis are unsigned 7-bit numbers with a fixed + resolution of 0.063 g/LSB, corresponding to an 8g acceleration + full-scale range. + + pulse-thsz: + type: int + default: 0x40 + description: | + Pulse Z-axis threshold + Threshold to start the pulse-event detection procedure on the Z-axis. + Threshold values for each axis are unsigned 7-bit numbers with a fixed + resolution of 0.063 g/LSB, corresponding to an 8g acceleration + full-scale range. + + pulse-tmlt: + type: int + default: 0x18 + description: | + Pulse time limit + The maximum time interval that can elapse between the start of the + acceleration on the selected channel exceeding the specified threshold + and the end when the channel acceleration goes back below the specified + threshold. The resolution depends upon the sample rate (ODR) and the + high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For + ODR=800 Hz and pls_hpf_en=0, the resolution is 0.625 ms/LSB. + + pulse-ltcy: + type: int + default: 0x28 + description: | + Pulse latency + The time interval that starts after the first pulse detection where the + pulse-detection function ignores the start of a new pulse. The + resolution depends upon the sample rate (ODR) and the high-pass filter + configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and + pls_hpf_en=0, the resolution is 1.25 ms/LSB. + + pulse-wind: + type: int + default: 0x3c + description: | + Pulse window + The maximum interval of time that can elapse after the end of the + latency interval in which the start of the second pulse event must be + detected provided the device has been configured for double pulse + detection. The detected second pulse width must be shorter than the + time limit constraint specified by the PULSE_TMLT register, but the end + of the double pulse need not finish within the time specified by the + PULSE_WIND register. The resolution depends upon the sample rate (ODR) + and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). + For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB. + + mag-vecm-cfg: + type: int + default: 0x4e + description: Magnetic vector-magnitude configuration register + + mag-vecm-ths-msb: + type: int + default: 0x00 + description: | + Magnetic vector-magnitude threshold most significant byte. + Resolution is 0.1 uT/LSB. + + mag-vecm-ths-lsb: + type: int + default: 0x5a + description: | + Magnetic vector-magnitude threshold least significant byte. + Resolution is 0.1 uT/LSB. diff --git a/dts/bindings/sensor/nxp,kinetis-acmp.yaml b/dts/bindings/sensor/nxp,kinetis-acmp.yaml index 7e2430c08b5ae5..9608f9305c9c07 100644 --- a/dts/bindings/sensor/nxp,kinetis-acmp.yaml +++ b/dts/bindings/sensor/nxp,kinetis-acmp.yaml @@ -8,51 +8,51 @@ compatible: "nxp,kinetis-acmp" include: [sensor-device.yaml, pinctrl-device.yaml] properties: - interrupts: - required: true - - reg: - required: true - - nxp,enable-output-pin: - type: boolean - description: | - Make the comparator output (CMP0) available on a packaged pin. - - nxp,use-unfiltered-output: - type: boolean - description: | - Use the unfiltered comparator output for CMP0. - - nxp,high-speed-mode: - type: boolean - description: | - Enable high speed comparison mode. - - nxp,enable-sample: - type: boolean - description: | - Enable external sample signal as clock input. - - nxp,filter-count: - type: int - description: | - Filter sample count (0 to 7). - - nxp,filter-period: - type: int - description: | - Filter sample period in bus clock cycles (0 to 255). - - nxp,window-mode: - type: boolean - description: | - Enable windowing mode. - - "#io-channel-cells": - type: int - const: 2 + interrupts: + required: true + + reg: + required: true + + nxp,enable-output-pin: + type: boolean + description: | + Make the comparator output (CMP0) available on a packaged pin. + + nxp,use-unfiltered-output: + type: boolean + description: | + Use the unfiltered comparator output for CMP0. + + nxp,high-speed-mode: + type: boolean + description: | + Enable high speed comparison mode. + + nxp,enable-sample: + type: boolean + description: | + Enable external sample signal as clock input. + + nxp,filter-count: + type: int + description: | + Filter sample count (0 to 7). + + nxp,filter-period: + type: int + description: | + Filter sample period in bus clock cycles (0 to 255). + + nxp,window-mode: + type: boolean + description: | + Enable windowing mode. + + "#io-channel-cells": + type: int + const: 2 io-channel-cells: - - positive - - negative + - positive + - negative diff --git a/dts/bindings/sensor/nxp,kinetis-temperature.yaml b/dts/bindings/sensor/nxp,kinetis-temperature.yaml index 732b6ac20dd39c..0b2b4d9df9df4f 100644 --- a/dts/bindings/sensor/nxp,kinetis-temperature.yaml +++ b/dts/bindings/sensor/nxp,kinetis-temperature.yaml @@ -8,35 +8,35 @@ compatible: "nxp,kinetis-temperature" include: sensor-device.yaml properties: - io-channels: - required: true - description: ADC channels for temperature sensor and bandgap voltage - - io-channel-names: - required: true - description: name of each ADC channel (SENSOR or BANDGAP) - - bandgap-voltage: - type: int - required: true - description: Bandgap voltage in microvolts - - vtemp25: - type: int - required: true - description: | - Temperature sensor voltage at 25 degrees Celcius in microvolts - - sensor-slope-cold: - type: int - required: true - description: | - Temperature sensor slope in microvolts per degree Celsius for - temperatures below 25 degrees Celsius - - sensor-slope-hot: - type: int - required: true - description: | - Temperature sensor slope in microvolts per degree Celsius for - temperatures above or equal to 25 degrees Celsius + io-channels: + required: true + description: ADC channels for temperature sensor and bandgap voltage + + io-channel-names: + required: true + description: name of each ADC channel (SENSOR or BANDGAP) + + bandgap-voltage: + type: int + required: true + description: Bandgap voltage in microvolts + + vtemp25: + type: int + required: true + description: | + Temperature sensor voltage at 25 degrees Celcius in microvolts + + sensor-slope-cold: + type: int + required: true + description: | + Temperature sensor slope in microvolts per degree Celsius for + temperatures below 25 degrees Celsius + + sensor-slope-hot: + type: int + required: true + description: | + Temperature sensor slope in microvolts per degree Celsius for + temperatures above or equal to 25 degrees Celsius diff --git a/dts/bindings/sensor/panasonic,amg88xx.yaml b/dts/bindings/sensor/panasonic,amg88xx.yaml index 3f50d2912090da..4ab1ca5093c097 100644 --- a/dts/bindings/sensor/panasonic,amg88xx.yaml +++ b/dts/bindings/sensor/panasonic,amg88xx.yaml @@ -8,11 +8,11 @@ compatible: "panasonic,amg88xx" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - required: true - description: Interrupt pin. + int-gpios: + type: phandle-array + required: true + description: Interrupt pin. - The interrupt pin of AMG88XX is open-drain, active low. - If connected directly the MCU pin should be configured - as pull-up, active low. + The interrupt pin of AMG88XX is open-drain, active low. + If connected directly the MCU pin should be configured + as pull-up, active low. diff --git a/dts/bindings/sensor/semtech,sx9500.yaml b/dts/bindings/sensor/semtech,sx9500.yaml index 37c91743f71e0d..d0ca8929ed36a1 100644 --- a/dts/bindings/sensor/semtech,sx9500.yaml +++ b/dts/bindings/sensor/semtech,sx9500.yaml @@ -10,8 +10,8 @@ compatible: "semtech,sx9500" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - Connection for the NIRQ signal. This signal is active-low when - produced by the sensor. + int-gpios: + type: phandle-array + description: | + Connection for the NIRQ signal. This signal is active-low when + produced by the sensor. diff --git a/dts/bindings/sensor/sensirion,sgp40.yaml b/dts/bindings/sensor/sensirion,sgp40.yaml index 9affb9fa5e18cd..e391fbbd1f74ad 100644 --- a/dts/bindings/sensor/sensirion,sgp40.yaml +++ b/dts/bindings/sensor/sensirion,sgp40.yaml @@ -10,8 +10,8 @@ compatible: "sensirion,sgp40" include: [sensor-device.yaml, i2c-device.yaml] properties: - enable-selftest: - type: boolean - description: | - Enabling this will run a selftest when the driver initializes. - The selftest takes ~250ms. + enable-selftest: + type: boolean + description: | + Enabling this will run a selftest when the driver initializes. + The selftest takes ~250ms. diff --git a/dts/bindings/sensor/sensirion,sht3xd.yaml b/dts/bindings/sensor/sensirion,sht3xd.yaml index cfd5b74e65dbad..a7755eeb237a8f 100644 --- a/dts/bindings/sensor/sensirion,sht3xd.yaml +++ b/dts/bindings/sensor/sensirion,sht3xd.yaml @@ -8,11 +8,11 @@ compatible: "sensirion,sht3xd" include: [sensor-device.yaml, i2c-device.yaml] properties: - alert-gpios: - type: phandle-array - description: | - ALERT pin. + alert-gpios: + type: phandle-array + description: | + ALERT pin. - This pin signals active high when produced by the sensor. The - property value should ensure the flags properly describe the - signal that is presented to the driver. + This pin signals active high when produced by the sensor. The + property value should ensure the flags properly describe the + signal that is presented to the driver. diff --git a/dts/bindings/sensor/sensirion,sht4x.yaml b/dts/bindings/sensor/sensirion,sht4x.yaml index b1086e43bee457..e0538ac34adc65 100644 --- a/dts/bindings/sensor/sensirion,sht4x.yaml +++ b/dts/bindings/sensor/sensirion,sht4x.yaml @@ -10,15 +10,15 @@ compatible: "sensirion,sht4x" include: [sensor-device.yaml, i2c-device.yaml] properties: - repeatability: - type: int - required: true - description: | - Repeatability of the T/RH Measurement - 0 = low -> 1.7 ms - 1 = med -> 4.5 ms - 2 = high -> 8.2 ms - enum: - - 0 - - 1 - - 2 + repeatability: + type: int + required: true + description: | + Repeatability of the T/RH Measurement + 0 = low -> 1.7 ms + 1 = med -> 4.5 ms + 2 = high -> 8.2 ms + enum: + - 0 + - 1 + - 2 diff --git a/dts/bindings/sensor/sensirion,shtcx.yaml b/dts/bindings/sensor/sensirion,shtcx.yaml index 19b30af9b48442..e0d90c6a929a78 100644 --- a/dts/bindings/sensor/sensirion,shtcx.yaml +++ b/dts/bindings/sensor/sensirion,shtcx.yaml @@ -16,8 +16,8 @@ properties: timing information and supported command set. SHTC3 has an additional sleep mode that is entered between measurements. enum: - - "shtc1" - - "shtc3" + - "shtc1" + - "shtc3" measure-mode: type: string @@ -26,8 +26,8 @@ properties: Specifies which measurement mode is used. SHTC1 sensor only supports the normal measuremnt mode. enum: - - "normal" - - "low-power" + - "normal" + - "low-power" clock-stretching: type: boolean diff --git a/dts/bindings/sensor/st,hts221-common.yaml b/dts/bindings/sensor/st,hts221-common.yaml index 412893e8458d2d..efa9987d9dc53a 100644 --- a/dts/bindings/sensor/st,hts221-common.yaml +++ b/dts/bindings/sensor/st,hts221-common.yaml @@ -4,10 +4,10 @@ include: sensor-device.yaml properties: - drdy-gpios: - type: phandle-array - description: DRDY pin + drdy-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/st,iis2dh-i2c.yaml b/dts/bindings/sensor/st,iis2dh-i2c.yaml index 3021944a45dd06..710f942c7cc9f5 100644 --- a/dts/bindings/sensor/st,iis2dh-i2c.yaml +++ b/dts/bindings/sensor/st,iis2dh-i2c.yaml @@ -9,10 +9,10 @@ compatible: "st,iis2dh" include: [sensor-device.yaml, i2c-device.yaml] properties: - drdy-gpios: - type: phandle-array - description: DRDY pin + drdy-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/st,iis2dh-spi.yaml b/dts/bindings/sensor/st,iis2dh-spi.yaml index 06ea6943f5ac25..e128cabb54fb88 100644 --- a/dts/bindings/sensor/st,iis2dh-spi.yaml +++ b/dts/bindings/sensor/st,iis2dh-spi.yaml @@ -9,10 +9,10 @@ compatible: "st,iis2dh" include: [sensor-device.yaml, spi-device.yaml] properties: - drdy-gpios: - type: phandle-array - description: DRDY pin + drdy-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/st,iis2dlpc-common.yaml b/dts/bindings/sensor/st,iis2dlpc-common.yaml index fff971c41b4649..36c258df4b12a5 100644 --- a/dts/bindings/sensor/st,iis2dlpc-common.yaml +++ b/dts/bindings/sensor/st,iis2dlpc-common.yaml @@ -4,106 +4,106 @@ include: sensor-device.yaml properties: - drdy-gpios: - type: phandle-array - description: | - DRDY pin - - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. - - drdy-int: - type: int - default: 1 - enum: - - 1 # drdy is generated from INT1 - - 2 # drdy is generated from INT2 - description: Select DRDY pin number (1 or 2). - - This number represents which of the two interrupt pins - (INT1 or INT2) the drdy line is attached to. This property is not - mandatory and if not present it defaults to 1 which is the - configuration at power-up. - - range: - type: int - default: 2 - description: Range in g. Default is power-up configuration. - enum: - - 16 # 16g (1.952 mg/LSB) - - 8 # 8g (0.976 mg/LSB) - - 4 # 4g (0.488 mg/LSB) - - 2 # 2g (0.244 mg/LSB) - - power-mode: - type: int - default: 0 - description: Specify the sensor power mode. Default is power-up configuration. - enum: - - 0 # Low Power M1 - - 1 # Low Power M2 - - 2 # Low Power M3 - - 3 # Low Power M4 - - 4 # High Performance - - # tap and tap-tap configuration section - # All default values are selected to match the power-up values. - # tap and tap-tap events can be generated on INT1 only. - - tap-mode: - type: int - default: 0 - description: Tap mode. Default is power-up configuration. - enum: - - 0 # Only Single Tap - - 1 # Single and Double Tap - - tap-threshold: - type: array - default: [0, 0, 0] - description: | - Tap X/Y/Z axes threshold. Default is power-up configuration. - (X/Y/Z values range from 0x00 to 0x1F) - - Thresholds to start the tap-event detection procedure on the X/Y/Z axes. - Threshold values for each axis are unsigned 5-bit corresponding - to a 2g acceleration full-scale range. A threshold value equal to zero - corresponds to disable the tap detection on that axis. - - For example, if you want to set the threshold for X to 12, for Z to 14 - and want to disable tap detection on Y, you should specify in Device Tree - - tap-threshold = <12>, <0>, <14> - - which is equivalent to X = 12 * 2g/32 = 750mg and Z = 14 * 2g/32 = 875mg. - - tap-shock: - type: int - default: 0x0 - description: | - Tap shock value. Default is power-up configuration. - (values range from 0x0 to 0x3) - This register represents the maximum time of an over-threshold signal - detection to be recognized as a tap event. Where 0 equals 4*1/ODR and - 1LSB = 8*1/ODR. - - tap-latency: - type: int - default: 0x0 - description: | - Tap latency. Default is power-up configuration. - (values range from 0x0 to 0xF) - When double-tap recognition is enabled, this register expresses the - maximum time between two successive detected taps to determine a - double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR. - - tap-quiet: - type: int - default: 0x0 - description: | - Expected quiet time after a tap detection. Default is power-up configuration. - (values range from 0x0 to 0x3) - This register represents the time after the first detected tap in which - there must not be any overthreshold event. Where 0 equals 2*1/ODR - and 1LSB = 4*1/ODR. + drdy-gpios: + type: phandle-array + description: | + DRDY pin + + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + drdy-int: + type: int + default: 1 + enum: + - 1 # drdy is generated from INT1 + - 2 # drdy is generated from INT2 + description: Select DRDY pin number (1 or 2). + + This number represents which of the two interrupt pins + (INT1 or INT2) the drdy line is attached to. This property is not + mandatory and if not present it defaults to 1 which is the + configuration at power-up. + + range: + type: int + default: 2 + description: Range in g. Default is power-up configuration. + enum: + - 16 # 16g (1.952 mg/LSB) + - 8 # 8g (0.976 mg/LSB) + - 4 # 4g (0.488 mg/LSB) + - 2 # 2g (0.244 mg/LSB) + + power-mode: + type: int + default: 0 + description: Specify the sensor power mode. Default is power-up configuration. + enum: + - 0 # Low Power M1 + - 1 # Low Power M2 + - 2 # Low Power M3 + - 3 # Low Power M4 + - 4 # High Performance + + # tap and tap-tap configuration section + # All default values are selected to match the power-up values. + # tap and tap-tap events can be generated on INT1 only. + + tap-mode: + type: int + default: 0 + description: Tap mode. Default is power-up configuration. + enum: + - 0 # Only Single Tap + - 1 # Single and Double Tap + + tap-threshold: + type: array + default: [0, 0, 0] + description: | + Tap X/Y/Z axes threshold. Default is power-up configuration. + (X/Y/Z values range from 0x00 to 0x1F) + + Thresholds to start the tap-event detection procedure on the X/Y/Z axes. + Threshold values for each axis are unsigned 5-bit corresponding + to a 2g acceleration full-scale range. A threshold value equal to zero + corresponds to disable the tap detection on that axis. + + For example, if you want to set the threshold for X to 12, for Z to 14 + and want to disable tap detection on Y, you should specify in Device Tree + + tap-threshold = <12>, <0>, <14> + + which is equivalent to X = 12 * 2g/32 = 750mg and Z = 14 * 2g/32 = 875mg. + + tap-shock: + type: int + default: 0x0 + description: | + Tap shock value. Default is power-up configuration. + (values range from 0x0 to 0x3) + This register represents the maximum time of an over-threshold signal + detection to be recognized as a tap event. Where 0 equals 4*1/ODR and + 1LSB = 8*1/ODR. + + tap-latency: + type: int + default: 0x0 + description: | + Tap latency. Default is power-up configuration. + (values range from 0x0 to 0xF) + When double-tap recognition is enabled, this register expresses the + maximum time between two successive detected taps to determine a + double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR. + + tap-quiet: + type: int + default: 0x0 + description: | + Expected quiet time after a tap detection. Default is power-up configuration. + (values range from 0x0 to 0x3) + This register represents the time after the first detected tap in which + there must not be any overthreshold event. Where 0 equals 2*1/ODR + and 1LSB = 4*1/ODR. diff --git a/dts/bindings/sensor/st,iis2iclx-common.yaml b/dts/bindings/sensor/st,iis2iclx-common.yaml index 319acfcda09d38..9551c274ae10e5 100644 --- a/dts/bindings/sensor/st,iis2iclx-common.yaml +++ b/dts/bindings/sensor/st,iis2iclx-common.yaml @@ -4,52 +4,52 @@ include: sensor-device.yaml properties: - drdy-gpios: - type: phandle-array - description: DRDY pin + drdy-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. - int-pin: - type: int - default: 1 - enum: - - 1 # drdy is generated from INT1 - - 2 # drdy is generated from INT2 - description: Select DRDY pin number (1 or 2). + int-pin: + type: int + default: 1 + enum: + - 1 # drdy is generated from INT1 + - 2 # drdy is generated from INT2 + description: Select DRDY pin number (1 or 2). - This number represents which of the two interrupt pins - (INT1 or INT2) the drdy line is attached to. This property is not - mandatory and if not present it defaults to 1 which is the - configuration at power-up. + This number represents which of the two interrupt pins + (INT1 or INT2) the drdy line is attached to. This property is not + mandatory and if not present it defaults to 1 which is the + configuration at power-up. - range: - type: int - default: 3 - description: Range in g. Default is power-up configuration. - enum: - - 0 # 500mg (0.015 mg/LSB) - - 1 # 3g (0.122 mg/LSB) - - 2 # 1g (0.031 mg/LSB) - - 3 # 2g (0.061 mg/LSB) + range: + type: int + default: 3 + description: Range in g. Default is power-up configuration. + enum: + - 0 # 500mg (0.015 mg/LSB) + - 1 # 3g (0.122 mg/LSB) + - 2 # 1g (0.031 mg/LSB) + - 3 # 2g (0.061 mg/LSB) - odr: - type: int - default: 0 - description: - Specify the default accelerometer output data rate expressed in samples per second (Hz). - Default is power-up configuration. - enum: - - 0 # Power-Down - - 1 # 12.5Hz - - 2 # 26Hz - - 3 # 52Hz - - 4 # 104Hz - - 5 # 208Hz - - 6 # 416Hz - - 7 # 833Hz - - 8 # 1660Hz - - 9 # 3330Hz - - 10 # 6660Hz + odr: + type: int + default: 0 + description: + Specify the default accelerometer output data rate expressed in samples per second (Hz). + Default is power-up configuration. + enum: + - 0 # Power-Down + - 1 # 12.5Hz + - 2 # 26Hz + - 3 # 52Hz + - 4 # 104Hz + - 5 # 208Hz + - 6 # 416Hz + - 7 # 833Hz + - 8 # 1660Hz + - 9 # 3330Hz + - 10 # 6660Hz diff --git a/dts/bindings/sensor/st,iis2mdc-i2c.yaml b/dts/bindings/sensor/st,iis2mdc-i2c.yaml index 6ea85c265d5953..d9386c4cc5750d 100644 --- a/dts/bindings/sensor/st,iis2mdc-i2c.yaml +++ b/dts/bindings/sensor/st,iis2mdc-i2c.yaml @@ -9,10 +9,10 @@ compatible: "st,iis2mdc" include: [sensor-device.yaml, i2c-device.yaml] properties: - drdy-gpios: - type: phandle-array - description: DRDY pin + drdy-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/st,iis2mdc-spi.yaml b/dts/bindings/sensor/st,iis2mdc-spi.yaml index 4c1069793cde4e..d60e8459de2727 100644 --- a/dts/bindings/sensor/st,iis2mdc-spi.yaml +++ b/dts/bindings/sensor/st,iis2mdc-spi.yaml @@ -9,10 +9,10 @@ compatible: "st,iis2mdc" include: [sensor-device.yaml, spi-device.yaml] properties: - drdy-gpios: - type: phandle-array - description: DRDY pin + drdy-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/st,iis3dhhc-spi.yaml b/dts/bindings/sensor/st,iis3dhhc-spi.yaml index 4da94882613a7d..ef3b912ee124ac 100644 --- a/dts/bindings/sensor/st,iis3dhhc-spi.yaml +++ b/dts/bindings/sensor/st,iis3dhhc-spi.yaml @@ -9,10 +9,10 @@ compatible: "st,iis3dhhc" include: [sensor-device.yaml, spi-device.yaml] properties: - irq-gpios: - type: phandle-array - description: DRDY pin + irq-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/st,ism330dhcx-common.yaml b/dts/bindings/sensor/st,ism330dhcx-common.yaml index b3f7fdbc06317c..93d9be0890ef87 100644 --- a/dts/bindings/sensor/st,ism330dhcx-common.yaml +++ b/dts/bindings/sensor/st,ism330dhcx-common.yaml @@ -4,129 +4,129 @@ include: sensor-device.yaml properties: - drdy-gpios: - type: phandle-array - description: | - DRDY gpio pin + drdy-gpios: + type: phandle-array + description: | + DRDY gpio pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. - int-pin: - type: int - default: 1 - description: | - Select DRDY pin number (1 or 2). + int-pin: + type: int + default: 1 + description: | + Select DRDY pin number (1 or 2). - Selection - 1 drdy is generated from INT1 - 2 drdy is generated from INT2 + Selection + 1 drdy is generated from INT1 + 2 drdy is generated from INT2 - This number represents which of the two interrupt pins - (INT1 or INT2) the drdy line is attached to. This property is not - mandatory and if not present it defaults to 1 which is the - configuration at power-up. - enum: - - 1 - - 2 + This number represents which of the two interrupt pins + (INT1 or INT2) the drdy line is attached to. This property is not + mandatory and if not present it defaults to 1 which is the + configuration at power-up. + enum: + - 1 + - 2 - accel-odr: - type: int - default: 0 - description: | - Specify the default accelerometer output data rate expressed in samples per second (Hz). - Default is power-up configuration. + accel-odr: + type: int + default: 0 + description: | + Specify the default accelerometer output data rate expressed in samples per second (Hz). + Default is power-up configuration. - Selection - 0 Power-Down - 1 12.5Hz - 2 26Hz - 3 52Hz - 4 104Hz - 5 208Hz - 6 416Hz - 7 833Hz - 8 1660Hz - 9 3330Hz - 10 6660Hz - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 + Selection + 0 Power-Down + 1 12.5Hz + 2 26Hz + 3 52Hz + 4 104Hz + 5 208Hz + 6 416Hz + 7 833Hz + 8 1660Hz + 9 3330Hz + 10 6660Hz + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 - accel-range: - type: int - default: 2 - description: | - Range in g. Default is power-up configuration. + accel-range: + type: int + default: 2 + description: | + Range in g. Default is power-up configuration. - Selection - 16 16g (0.488 mg/LSB) - 8 8g (0.244 mg/LSB) - 4 4g (0.122 mg/LSB) - 2 2g (0.061 mg/LSB) - enum: - - 16 - - 8 - - 4 - - 2 + Selection + 16 16g (0.488 mg/LSB) + 8 8g (0.244 mg/LSB) + 4 4g (0.122 mg/LSB) + 2 2g (0.061 mg/LSB) + enum: + - 16 + - 8 + - 4 + - 2 - gyro-odr: - type: int - default: 0 - description: | - Specify the default gyro output data rate expressed in samples per second (Hz). - Default is power-up configuration. + gyro-odr: + type: int + default: 0 + description: | + Specify the default gyro output data rate expressed in samples per second (Hz). + Default is power-up configuration. - Selection - 0 Power-Down - 1 12.5Hz - 2 26Hz - 3 52Hz - 4 104Hz - 5 208Hz - 6 416Hz - 7 833Hz - 8 1660Hz - 9 3330Hz - 10 6660Hz - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 - - 10 + Selection + 0 Power-Down + 1 12.5Hz + 2 26Hz + 3 52Hz + 4 104Hz + 5 208Hz + 6 416Hz + 7 833Hz + 8 1660Hz + 9 3330Hz + 10 6660Hz + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 + - 10 - gyro-range: - type: int - default: 125 - description: | - Range in dps. Default is power-up configuration. + gyro-range: + type: int + default: 125 + description: | + Range in dps. Default is power-up configuration. - Selection - 125 +/- 125dps - 250 +/- 250dps - 500 +/- 500dps - 1000 +/- 1000dps - 2000 +/- 2000dps - enum: - - 125 - - 250 - - 500 - - 1000 - - 2000 + Selection + 125 +/- 125dps + 250 +/- 250dps + 500 +/- 500dps + 1000 +/- 1000dps + 2000 +/- 2000dps + enum: + - 125 + - 250 + - 500 + - 1000 + - 2000 diff --git a/dts/bindings/sensor/st,lis2dh-common.yaml b/dts/bindings/sensor/st,lis2dh-common.yaml index 96f61aa9dcaec4..d86960e26d3e20 100644 --- a/dts/bindings/sensor/st,lis2dh-common.yaml +++ b/dts/bindings/sensor/st,lis2dh-common.yaml @@ -4,46 +4,46 @@ include: sensor-device.yaml properties: - irq-gpios: - type: phandle-array - description: | - The INT1 and (optional) INT2 signal connections. These signals - are active-high as produced by the sensor. - - disconnect-sdo-sa0-pull-up: - type: boolean - description: | - Indicates the device driver should disconnect SDO/SA0 pull-up - during device initialization (e.g. to save current - leakage). Note that only subset of devices supported by this - binding have SDO/SA0 pull-up (e.g. LIS2DH12, LIS3DH). - - anym-on-int1: - type: boolean - description: | - Indicates that the device driver should use interrupt 1 - for any movement. This is for boards that only have one - interrupt line connected from the sensor to the processor. - - anym-no-latch: - type: boolean - description: | - Disable the latching of interrupts for any movement. - - anym-mode: - type: int - default: 0 - description: | - Select the interrupt mode for any movement. - - 0 = OR combination of interrupt events - 1 = 6D movement recognition - 2 = AND combination of interrupt events - 3 = 6D position recognition - - The default of 0 is the power-on-reset value. - enum: - - 0 - - 1 - - 2 - - 3 + irq-gpios: + type: phandle-array + description: | + The INT1 and (optional) INT2 signal connections. These signals + are active-high as produced by the sensor. + + disconnect-sdo-sa0-pull-up: + type: boolean + description: | + Indicates the device driver should disconnect SDO/SA0 pull-up + during device initialization (e.g. to save current + leakage). Note that only subset of devices supported by this + binding have SDO/SA0 pull-up (e.g. LIS2DH12, LIS3DH). + + anym-on-int1: + type: boolean + description: | + Indicates that the device driver should use interrupt 1 + for any movement. This is for boards that only have one + interrupt line connected from the sensor to the processor. + + anym-no-latch: + type: boolean + description: | + Disable the latching of interrupts for any movement. + + anym-mode: + type: int + default: 0 + description: | + Select the interrupt mode for any movement. + + 0 = OR combination of interrupt events + 1 = 6D movement recognition + 2 = AND combination of interrupt events + 3 = 6D position recognition + + The default of 0 is the power-on-reset value. + enum: + - 0 + - 1 + - 2 + - 3 diff --git a/dts/bindings/sensor/st,lis2ds12-common.yaml b/dts/bindings/sensor/st,lis2ds12-common.yaml index 57c3c5847b6aa5..4a5926c42ad21a 100644 --- a/dts/bindings/sensor/st,lis2ds12-common.yaml +++ b/dts/bindings/sensor/st,lis2ds12-common.yaml @@ -4,55 +4,55 @@ include: sensor-device.yaml properties: - irq-gpios: - type: phandle-array - description: | - DRDY pin - - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. - - range: - type: int - default: 2 - description: | - Range in g. Default is power-up configuration. - - enum: - - 16 # 16g (0.488 mg/LSB) - - 8 # 8g (0.244 mg/LSB) - - 4 # 4g (0.122 mg/LSB) - - 2 # 2g (0.061 mg/LSB) - - power-mode: - type: int - default: 0 - description: | - Specify the sensor power mode. Default is power-down mode - - enum: - - 0 # Power Down (PD) - - 1 # Low Power (LP) - - 2 # High Resolution (HR) - - 3 # High Frequency (HF) - - odr: - type: int - default: 0 - description: | - Specify the default output data rate expressed in samples per second (Hz). - Default is power-down mode - enum: - - 0 # Power-Down - - 1 # 1Hz (available in LP mode only) - - 2 # 12.5Hz (available in LP and HR mode) - - 3 # 25Hz (available in LP and HR mode) - - 4 # 50Hz (available in LP and HR mode) - - 5 # 100Hz (available in LP and HR mode) - - 6 # 200Hz (available in LP and HR mode) - - 7 # 400Hz (available in LP and HR mode) - - 8 # 800Hz (available in LP and HR mode) - - 9 # 1600Hz (available in HF mode only) - - 10 # 3200Hz (available in HF mode only) - - 11 # 6400Hz (available in HF mode only) + irq-gpios: + type: phandle-array + description: | + DRDY pin + + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + range: + type: int + default: 2 + description: | + Range in g. Default is power-up configuration. + + enum: + - 16 # 16g (0.488 mg/LSB) + - 8 # 8g (0.244 mg/LSB) + - 4 # 4g (0.122 mg/LSB) + - 2 # 2g (0.061 mg/LSB) + + power-mode: + type: int + default: 0 + description: | + Specify the sensor power mode. Default is power-down mode + + enum: + - 0 # Power Down (PD) + - 1 # Low Power (LP) + - 2 # High Resolution (HR) + - 3 # High Frequency (HF) + + odr: + type: int + default: 0 + description: | + Specify the default output data rate expressed in samples per second (Hz). + Default is power-down mode + enum: + - 0 # Power-Down + - 1 # 1Hz (available in LP mode only) + - 2 # 12.5Hz (available in LP and HR mode) + - 3 # 25Hz (available in LP and HR mode) + - 4 # 50Hz (available in LP and HR mode) + - 5 # 100Hz (available in LP and HR mode) + - 6 # 200Hz (available in LP and HR mode) + - 7 # 400Hz (available in LP and HR mode) + - 8 # 800Hz (available in LP and HR mode) + - 9 # 1600Hz (available in HF mode only) + - 10 # 3200Hz (available in HF mode only) + - 11 # 6400Hz (available in HF mode only) diff --git a/dts/bindings/sensor/st,lis2dw12-common.yaml b/dts/bindings/sensor/st,lis2dw12-common.yaml index f18f42dfe4e84e..635e9d9e9d5afd 100644 --- a/dts/bindings/sensor/st,lis2dw12-common.yaml +++ b/dts/bindings/sensor/st,lis2dw12-common.yaml @@ -4,245 +4,245 @@ include: sensor-device.yaml properties: - irq-gpios: - type: phandle-array - description: | - DRDY pin - - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. - - int-pin: - type: int - default: 1 - enum: - - 1 - - 2 - description: | - Select DRDY pin number (1 or 2). - - 1 # drdy is generated from INT1 - 2 # drdy is generated from INT2 - - This number represents which of the two interrupt pins - (INT1 or INT2) the drdy line is attached to. This property is not - mandatory and if not present it defaults to 1 which is the - configuration at power-up. - - range: - type: int - default: 2 - description: | - Range in g. Default is power-up configuration. - - 16 # 16g (1.952 mg/LSB) - 8 # 8g (0.976 mg/LSB) - 4 # 4g (0.488 mg/LSB) - 2 # 2g (0.244 mg/LSB) - - enum: - - 16 - - 8 - - 4 - - 2 - - odr: - type: int - description: | - Output data rate in Hz. Default value is 12.5Hz if this is not set. - The output data rates which are represented with fractional - numbers are converted into their integer parts (1.65Hz -> 1, 12.5Hz -> 12). - If 0 selected as the odr, the accelerometer initializes into - power off state. - - enum: - - 0 - - 1 - - 12 - - 25 - - 50 - - 100 - - 200 - - 400 - - 800 - - 1600 - - bw-filt: - type: int - default: 0 - description: | - Digital filtering cutoff bandwidth. Default is power-up configuration. - - 3 # ODR/20 (HP/LP) - 2 # ODR/10 (HP/LP) - 1 # ODR/ 4 (HP/LP) - 0 # ODR/ 2 (up to ODR = 800 Hz, 400 Hz when ODR = 1600 Hz) - - enum: - - 3 - - 2 - - 1 - - 0 - - power-mode: - type: int - default: 0 - description: | - Specify the sensor power mode. Default is power-up configuration. - - 0 # Low Power M1 - 1 # Low Power M2 - 2 # Low Power M3 - 3 # Low Power M4 - 4 # High Performance - - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - # tap and tap-tap configuration section - # All default values are selected to match the power-up values. - # tap and tap-tap events can be generated on INT1 only. - - tap-mode: - type: int - default: 0 - description: | - Tap mode. Default is power-up configuration. - - 0 # Only Single Tap - 1 # Single and Double Tap - - enum: - - 0 - - 1 - - tap-threshold: - type: array - default: [0, 0, 0] - description: | - Tap X/Y/Z axes threshold. Default is power-up configuration. - (X/Y/Z values range from 0x00 to 0x1F) - - Thresholds to start the tap-event detection procedure on the X/Y/Z axes. - Threshold values for each axis are unsigned 5-bit corresponding - to a 2g acceleration full-scale range. A threshold value equal to zero - corresponds to disable the tap detection on that axis. - - For example, if you want to set the threshold for X to 12, for Z to 14 - and want to disable tap detection on Y, you should specify in Device Tree - - tap-threshold = <12>, <0>, <14> - - which is equivalent to X = 12 * 2g/32 = 750mg and Z = 14 * 2g/32 = 875mg. - - tap-shock: - type: int - default: 0x0 - description: | - Tap shock value. Default is power-up configuration. - (values range from 0x0 to 0x3) - This register represents the maximum time of an over-threshold signal - detection to be recognized as a tap event. Where 0 equals 4*1/ODR and - 1LSB = 8*1/ODR. - - tap-latency: - type: int - default: 0x0 - description: | - Tap latency. Default is power-up configuration. - (values range from 0x0 to 0xF) - When double-tap recognition is enabled, this register expresses the - maximum time between two successive detected taps to determine a - double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR. - - tap-quiet: - type: int - default: 0x0 - description: | - Expected quiet time after a tap detection. Default is power-up configuration. - (values range from 0x0 to 0x3) - This register represents the time after the first detected tap in which - there must not be any overthreshold event. Where 0 equals 2*1/ODR - and 1LSB = 4*1/ODR. - - low-noise: - type: boolean - description: | - Enables the LOW_NOISE flag in the CTRL6 register. - This influences the noise density and the current consumption. - See the datasheet for more information. - - hp-filter-path: - type: boolean - description: | - Sets the Filtered Data Selection bit in the CTRL6 register. - When enabled, the high-pass filter path is selected. - When disabled, the low-pass filter path is selected. - Note that this influences the OUT_REG / FIFO values, - but not the Wakeup function. - - hp-ref-mode: - type: boolean - description: | - Enables the high-pass filter reference mode in the CTRL7 register. - When the high-pass filter is configured in reference mode, - the output data is calculated as the difference between the input - acceleration and the values captured when reference mode was enabled. - In this way only the difference is applied without any filtering - of the LIS2DW12. - Note that this influences both the OUT_REG / FIFO values, - as well as the Wakeup function. - - drdy-pulsed: - type: boolean - description: | - Selects the pulsed mode for data-ready interrupt when enabled, - and the latched mode when disabled. - Sets the corresponding DRDY_PULSED bit in the CTRL7 register. - - ff-duration: - type: int - default: 30 - description: | - The freefall duration value represented in milliseconds. - If the accelerometer readings of the all axes are lower - than the freefall threshold value for the freefall duration long, - then a freefall trigger occurs. This value is 5 bits long in the - register and 1 LSB = 1 * 1/ODR. This value depends on the ODR. - if the data rate change in code with SENSOR ATTR SAMPLING FREQUENCY, - It must be set again with SENSOR_ATT_FF_DUR attribute. ST propose - 100Hz ODR and 30ms ff-duration for recognize freefall detection - refer to ST DT0100 design tip document. - - ff-threshold: - type: int - default: 3 - description: | - The freefall threshold value represented in mg. - If the accelerometer readings of the all axes are lower - than the freefall threshold value for the freefall duration long, - then a freefall trigger occurs. This value is 3 bits long. - Default value chosen 3 (312 mg) refer to ST DT0100 design tip document. - 0 # ~156mg - 1 # ~219mg - 2 # ~250mg - 3 # ~312mg - 4 # ~344mg - 5 # ~406mg - 6 # ~469mg - 7 # ~500mg - - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 + irq-gpios: + type: phandle-array + description: | + DRDY pin + + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + int-pin: + type: int + default: 1 + enum: + - 1 + - 2 + description: | + Select DRDY pin number (1 or 2). + + 1 # drdy is generated from INT1 + 2 # drdy is generated from INT2 + + This number represents which of the two interrupt pins + (INT1 or INT2) the drdy line is attached to. This property is not + mandatory and if not present it defaults to 1 which is the + configuration at power-up. + + range: + type: int + default: 2 + description: | + Range in g. Default is power-up configuration. + + 16 # 16g (1.952 mg/LSB) + 8 # 8g (0.976 mg/LSB) + 4 # 4g (0.488 mg/LSB) + 2 # 2g (0.244 mg/LSB) + + enum: + - 16 + - 8 + - 4 + - 2 + + odr: + type: int + description: | + Output data rate in Hz. Default value is 12.5Hz if this is not set. + The output data rates which are represented with fractional + numbers are converted into their integer parts (1.65Hz -> 1, 12.5Hz -> 12). + If 0 selected as the odr, the accelerometer initializes into + power off state. + + enum: + - 0 + - 1 + - 12 + - 25 + - 50 + - 100 + - 200 + - 400 + - 800 + - 1600 + + bw-filt: + type: int + default: 0 + description: | + Digital filtering cutoff bandwidth. Default is power-up configuration. + + 3 # ODR/20 (HP/LP) + 2 # ODR/10 (HP/LP) + 1 # ODR/ 4 (HP/LP) + 0 # ODR/ 2 (up to ODR = 800 Hz, 400 Hz when ODR = 1600 Hz) + + enum: + - 3 + - 2 + - 1 + - 0 + + power-mode: + type: int + default: 0 + description: | + Specify the sensor power mode. Default is power-up configuration. + + 0 # Low Power M1 + 1 # Low Power M2 + 2 # Low Power M3 + 3 # Low Power M4 + 4 # High Performance + + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + + # tap and tap-tap configuration section + # All default values are selected to match the power-up values. + # tap and tap-tap events can be generated on INT1 only. + + tap-mode: + type: int + default: 0 + description: | + Tap mode. Default is power-up configuration. + + 0 # Only Single Tap + 1 # Single and Double Tap + + enum: + - 0 + - 1 + + tap-threshold: + type: array + default: [0, 0, 0] + description: | + Tap X/Y/Z axes threshold. Default is power-up configuration. + (X/Y/Z values range from 0x00 to 0x1F) + + Thresholds to start the tap-event detection procedure on the X/Y/Z axes. + Threshold values for each axis are unsigned 5-bit corresponding + to a 2g acceleration full-scale range. A threshold value equal to zero + corresponds to disable the tap detection on that axis. + + For example, if you want to set the threshold for X to 12, for Z to 14 + and want to disable tap detection on Y, you should specify in Device Tree + + tap-threshold = <12>, <0>, <14> + + which is equivalent to X = 12 * 2g/32 = 750mg and Z = 14 * 2g/32 = 875mg. + + tap-shock: + type: int + default: 0x0 + description: | + Tap shock value. Default is power-up configuration. + (values range from 0x0 to 0x3) + This register represents the maximum time of an over-threshold signal + detection to be recognized as a tap event. Where 0 equals 4*1/ODR and + 1LSB = 8*1/ODR. + + tap-latency: + type: int + default: 0x0 + description: | + Tap latency. Default is power-up configuration. + (values range from 0x0 to 0xF) + When double-tap recognition is enabled, this register expresses the + maximum time between two successive detected taps to determine a + double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR. + + tap-quiet: + type: int + default: 0x0 + description: | + Expected quiet time after a tap detection. Default is power-up configuration. + (values range from 0x0 to 0x3) + This register represents the time after the first detected tap in which + there must not be any overthreshold event. Where 0 equals 2*1/ODR + and 1LSB = 4*1/ODR. + + low-noise: + type: boolean + description: | + Enables the LOW_NOISE flag in the CTRL6 register. + This influences the noise density and the current consumption. + See the datasheet for more information. + + hp-filter-path: + type: boolean + description: | + Sets the Filtered Data Selection bit in the CTRL6 register. + When enabled, the high-pass filter path is selected. + When disabled, the low-pass filter path is selected. + Note that this influences the OUT_REG / FIFO values, + but not the Wakeup function. + + hp-ref-mode: + type: boolean + description: | + Enables the high-pass filter reference mode in the CTRL7 register. + When the high-pass filter is configured in reference mode, + the output data is calculated as the difference between the input + acceleration and the values captured when reference mode was enabled. + In this way only the difference is applied without any filtering + of the LIS2DW12. + Note that this influences both the OUT_REG / FIFO values, + as well as the Wakeup function. + + drdy-pulsed: + type: boolean + description: | + Selects the pulsed mode for data-ready interrupt when enabled, + and the latched mode when disabled. + Sets the corresponding DRDY_PULSED bit in the CTRL7 register. + + ff-duration: + type: int + default: 30 + description: | + The freefall duration value represented in milliseconds. + If the accelerometer readings of the all axes are lower + than the freefall threshold value for the freefall duration long, + then a freefall trigger occurs. This value is 5 bits long in the + register and 1 LSB = 1 * 1/ODR. This value depends on the ODR. + if the data rate change in code with SENSOR ATTR SAMPLING FREQUENCY, + It must be set again with SENSOR_ATT_FF_DUR attribute. ST propose + 100Hz ODR and 30ms ff-duration for recognize freefall detection + refer to ST DT0100 design tip document. + + ff-threshold: + type: int + default: 3 + description: | + The freefall threshold value represented in mg. + If the accelerometer readings of the all axes are lower + than the freefall threshold value for the freefall duration long, + then a freefall trigger occurs. This value is 3 bits long. + Default value chosen 3 (312 mg) refer to ST DT0100 design tip document. + 0 # ~156mg + 1 # ~219mg + 2 # ~250mg + 3 # ~312mg + 4 # ~344mg + 5 # ~406mg + 6 # ~469mg + 7 # ~500mg + + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 diff --git a/dts/bindings/sensor/st,lis2mdl-common.yaml b/dts/bindings/sensor/st,lis2mdl-common.yaml index dcb88eba94b38e..4fe9e877bbca6b 100644 --- a/dts/bindings/sensor/st,lis2mdl-common.yaml +++ b/dts/bindings/sensor/st,lis2mdl-common.yaml @@ -4,27 +4,27 @@ include: sensor-device.yaml properties: - irq-gpios: - type: phandle-array - description: IRQ pin + irq-gpios: + type: phandle-array + description: IRQ pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. - single-mode: - type: boolean - description: | - Set to config the sensor in single measurement mode. Leave - unset to configure the sensor in continious measurement mode. + single-mode: + type: boolean + description: | + Set to config the sensor in single measurement mode. Leave + unset to configure the sensor in continious measurement mode. - cancel-offset: - type: boolean - description: | - Set to enable the offset cancellation. Otherwise it would be - disabled as default. + cancel-offset: + type: boolean + description: | + Set to enable the offset cancellation. Otherwise it would be + disabled as default. - spi-full-duplex: - type: boolean - description: | - Enable SPI 4wires mode with separated MISO and MOSI lines + spi-full-duplex: + type: boolean + description: | + Enable SPI 4wires mode with separated MISO and MOSI lines diff --git a/dts/bindings/sensor/st,lis3mdl-magn.yaml b/dts/bindings/sensor/st,lis3mdl-magn.yaml index ba6cd8c79e5682..4e9b79387dc95c 100644 --- a/dts/bindings/sensor/st,lis3mdl-magn.yaml +++ b/dts/bindings/sensor/st,lis3mdl-magn.yaml @@ -8,10 +8,10 @@ compatible: "st,lis3mdl-magn" include: [sensor-device.yaml, i2c-device.yaml] properties: - irq-gpios: - type: phandle-array - description: DRDY pin + irq-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/st,lps22hh-common.yaml b/dts/bindings/sensor/st,lps22hh-common.yaml index 655e68486c0de0..a704eac46aea2d 100644 --- a/dts/bindings/sensor/st,lps22hh-common.yaml +++ b/dts/bindings/sensor/st,lps22hh-common.yaml @@ -4,27 +4,27 @@ include: sensor-device.yaml properties: - drdy-gpios: - type: phandle-array - description: | - DRDY pin + drdy-gpios: + type: phandle-array + description: | + DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. - odr: - type: int - default: 0 - description: | - Specify the default output data rate expressed in samples per second (Hz). - The default is the power-on reset value. - enum: - - 0 # Power-Down - - 1 # 1Hz - - 2 # 10Hz - - 3 # 25Hz - - 4 # 50Hz - - 5 # 75Hz - - 6 # 100Hz - - 7 # 200Hz + odr: + type: int + default: 0 + description: | + Specify the default output data rate expressed in samples per second (Hz). + The default is the power-on reset value. + enum: + - 0 # Power-Down + - 1 # 1Hz + - 2 # 10Hz + - 3 # 25Hz + - 4 # 50Hz + - 5 # 75Hz + - 6 # 100Hz + - 7 # 200Hz diff --git a/dts/bindings/sensor/st,lsm6dsl-i2c.yaml b/dts/bindings/sensor/st,lsm6dsl-i2c.yaml index de9a697fdeae1d..cd99c27c8d9e09 100644 --- a/dts/bindings/sensor/st,lsm6dsl-i2c.yaml +++ b/dts/bindings/sensor/st,lsm6dsl-i2c.yaml @@ -8,6 +8,6 @@ compatible: "st,lsm6dsl" include: [sensor-device.yaml, i2c-device.yaml] properties: - irq-gpios: - # This signal is active high when produced by the sensor - type: phandle-array + irq-gpios: + # This signal is active high when produced by the sensor + type: phandle-array diff --git a/dts/bindings/sensor/st,lsm6dsl-spi.yaml b/dts/bindings/sensor/st,lsm6dsl-spi.yaml index b949afd64768b7..08695559fe9733 100644 --- a/dts/bindings/sensor/st,lsm6dsl-spi.yaml +++ b/dts/bindings/sensor/st,lsm6dsl-spi.yaml @@ -10,6 +10,6 @@ compatible: "st,lsm6dsl" include: [sensor-device.yaml, spi-device.yaml] properties: - irq-gpios: - # This signal is active high when produced by the sensor - type: phandle-array + irq-gpios: + # This signal is active high when produced by the sensor + type: phandle-array diff --git a/dts/bindings/sensor/st,lsm6dso-common.yaml b/dts/bindings/sensor/st,lsm6dso-common.yaml index a26c3162845c8c..e8de1e9a75df11 100644 --- a/dts/bindings/sensor/st,lsm6dso-common.yaml +++ b/dts/bindings/sensor/st,lsm6dso-common.yaml @@ -4,113 +4,113 @@ include: sensor-device.yaml properties: - irq-gpios: - type: phandle-array - description: | - DRDY pin + irq-gpios: + type: phandle-array + description: | + DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. - int-pin: - type: int - default: 1 - enum: - - 1 # drdy is generated from INT1 - - 2 # drdy is generated from INT2 - description: | - Select DRDY pin number (1 or 2). + int-pin: + type: int + default: 1 + enum: + - 1 # drdy is generated from INT1 + - 2 # drdy is generated from INT2 + description: | + Select DRDY pin number (1 or 2). - This number represents which of the two interrupt pins - (INT1 or INT2) the drdy line is attached to. This property is not - mandatory and if not present it defaults to 1 which is the - configuration at power-up. + This number represents which of the two interrupt pins + (INT1 or INT2) the drdy line is attached to. This property is not + mandatory and if not present it defaults to 1 which is the + configuration at power-up. - accel-pm: - type: int - default: 0 - description: | - Specify the accelerometer power mode. - Default is power-up configuration. - enum: - - 0 # High Performance mode (default) - - 1 # Low/Normal Power mode - - 2 # Ultra Low Power mode + accel-pm: + type: int + default: 0 + description: | + Specify the accelerometer power mode. + Default is power-up configuration. + enum: + - 0 # High Performance mode (default) + - 1 # Low/Normal Power mode + - 2 # Ultra Low Power mode - accel-range: - type: int - default: 0 - description: | - Range in g. Default is power-up configuration. - enum: - - 0 # 2g (0.061 mg/LSB) (LSM6DSO32 will be double these values) - - 1 # 16g (0.488 mg/LSB) - - 2 # 4g (0.122 mg/LSB) - - 3 # 8g (0.244 mg/LSB) + accel-range: + type: int + default: 0 + description: | + Range in g. Default is power-up configuration. + enum: + - 0 # 2g (0.061 mg/LSB) (LSM6DSO32 will be double these values) + - 1 # 16g (0.488 mg/LSB) + - 2 # 4g (0.122 mg/LSB) + - 3 # 8g (0.244 mg/LSB) - accel-odr: - type: int - default: 0 - description: | - Specify the default accelerometer output data rate expressed in samples per second (Hz). - Default is power-up configuration. - enum: - - 0 # Power-Down - - 1 # 12.5Hz - - 2 # 26Hz - - 3 # 52Hz - - 4 # 104Hz - - 5 # 208Hz - - 6 # 417Hz - - 7 # 833Hz - - 8 # 1667Hz - - 9 # 3333Hz - - 10 # 6667Hz + accel-odr: + type: int + default: 0 + description: | + Specify the default accelerometer output data rate expressed in samples per second (Hz). + Default is power-up configuration. + enum: + - 0 # Power-Down + - 1 # 12.5Hz + - 2 # 26Hz + - 3 # 52Hz + - 4 # 104Hz + - 5 # 208Hz + - 6 # 417Hz + - 7 # 833Hz + - 8 # 1667Hz + - 9 # 3333Hz + - 10 # 6667Hz - gyro-pm: - type: int - default: 0 - description: | - Specify the gyrometer power mode. - Default is power-up configuration. - enum: - - 0 # High Performance mode (default) - - 1 # Low/Normal Power mode + gyro-pm: + type: int + default: 0 + description: | + Specify the gyrometer power mode. + Default is power-up configuration. + enum: + - 0 # High Performance mode (default) + - 1 # Low/Normal Power mode - gyro-range: - type: int - default: 0 - description: | - Range in dps. Default is power-up configuration. - enum: - - 0 # 250 dps (8.75 mdps/LSB) - - 1 # 125 dps (4.375 mdps/LSB) - - 2 # 500 dps (17.50 mdps/LSB) - - 4 # 1000 dps (35 mdps/LSB) - - 6 # 2000 dps (70 mdps/LSB) + gyro-range: + type: int + default: 0 + description: | + Range in dps. Default is power-up configuration. + enum: + - 0 # 250 dps (8.75 mdps/LSB) + - 1 # 125 dps (4.375 mdps/LSB) + - 2 # 500 dps (17.50 mdps/LSB) + - 4 # 1000 dps (35 mdps/LSB) + - 6 # 2000 dps (70 mdps/LSB) - gyro-odr: - type: int - default: 0 - description: | - Specify the default gyro output data rate expressed in samples per second (Hz). - Default is power-up configuration. - enum: - - 0 # Power-Down - - 1 # 12.5Hz - - 2 # 26Hz - - 3 # 52Hz - - 4 # 104Hz - - 5 # 208Hz - - 6 # 417Hz - - 7 # 833Hz - - 8 # 1667Hz - - 9 # 3333Hz - - 10 # 6667Hz + gyro-odr: + type: int + default: 0 + description: | + Specify the default gyro output data rate expressed in samples per second (Hz). + Default is power-up configuration. + enum: + - 0 # Power-Down + - 1 # 12.5Hz + - 2 # 26Hz + - 3 # 52Hz + - 4 # 104Hz + - 5 # 208Hz + - 6 # 417Hz + - 7 # 833Hz + - 8 # 1667Hz + - 9 # 3333Hz + - 10 # 6667Hz - drdy-pulsed: - type: boolean - description: | - Selects the pulsed mode for data-ready interrupt when enabled, - and the latched mode when disabled. + drdy-pulsed: + type: boolean + description: | + Selects the pulsed mode for data-ready interrupt when enabled, + and the latched mode when disabled. diff --git a/dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml b/dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml index ce4d2c78338936..418e8895491b94 100644 --- a/dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml +++ b/dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml @@ -8,5 +8,5 @@ compatible: "st,lsm9ds0-gyro" include: [sensor-device.yaml, i2c-device.yaml] properties: - irq-gpios: - type: phandle-array + irq-gpios: + type: phandle-array diff --git a/dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml b/dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml index 7d9edc6dc83676..be7a08d7a4f958 100644 --- a/dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml +++ b/dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml @@ -8,5 +8,5 @@ compatible: "st,lsm9ds0-mfd" include: [sensor-device.yaml, i2c-device.yaml] properties: - irq-gpios: - type: phandle-array + irq-gpios: + type: phandle-array diff --git a/dts/bindings/sensor/st,stm32-qdec.yaml b/dts/bindings/sensor/st,stm32-qdec.yaml index de7e2b9ce3c45d..9efae737e7f6be 100644 --- a/dts/bindings/sensor/st,stm32-qdec.yaml +++ b/dts/bindings/sensor/st,stm32-qdec.yaml @@ -6,67 +6,67 @@ description: STM32 quadrature decoder compatible: "st,stm32-qdec" include: - - name: base.yaml - - name: pinctrl-device.yaml + - name: base.yaml + - name: pinctrl-device.yaml properties: - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - st,input-polarity-inverted: - type: boolean - description: Encoder is triggered by a falling edge on the input pin + st,input-polarity-inverted: + type: boolean + description: Encoder is triggered by a falling edge on the input pin - st,input-filter-level: - type: int - description: | - Intensity of the filter applied to the input signal. This is - implemented by scaling the sampling frequency and adding a counter - in which N consecutive samples with same value are needed to validate - a transition. - Mapping is as follows (F_clk is the timer's clock): - 0: No filter, sampling is done at F_dts (default value) - 1: Fs = F_clk, N=2 - 2: Fs = F_clk, N=4 - 3: Fs = F_clk, N=8 - 4: Fs = F_clk/2, N=6 - 5: Fs = F_clk/2, N=8 - 6: Fs = F_clk/4, N=6 - 7: Fs = F_clk/4, N=8 - 8: Fs = F_clk/8, N=6 - 9: Fs = F_clk/8, N=8 - 10: Fs = F_clk/16, N=5 - 11: Fs = F_clk/16, N=6 - 12: Fs = F_clk/16, N=8 - 13: Fs = F_clk/32, N=5 - 14: Fs = F_clk/32, N=6 - 15: Fs = F_clk/32, N=8 - Default value is set by hardware at reset - default: 0 - enum: - - 0 # No filter - - 1 # FDIV1_N2 - - 2 # FDIV1_N4 - - 3 # FDIV1_N8 - - 4 # FDIV2_N6 - - 5 # FDIV2_N8 - - 6 # FDIV4_N6 - - 7 # FDIV4_N8 - - 8 # FDIV8_N6 - - 9 # FDIV8_N8 - - 10 # FDIV16_N5 - - 11 # FDIV16_N6 - - 12 # FDIV16_N8 - - 13 # FDIV32_N5 - - 14 # FDIV32_N6 - - 15 # FDIV32_N8 + st,input-filter-level: + type: int + description: | + Intensity of the filter applied to the input signal. This is + implemented by scaling the sampling frequency and adding a counter + in which N consecutive samples with same value are needed to validate + a transition. + Mapping is as follows (F_clk is the timer's clock): + 0: No filter, sampling is done at F_dts (default value) + 1: Fs = F_clk, N=2 + 2: Fs = F_clk, N=4 + 3: Fs = F_clk, N=8 + 4: Fs = F_clk/2, N=6 + 5: Fs = F_clk/2, N=8 + 6: Fs = F_clk/4, N=6 + 7: Fs = F_clk/4, N=8 + 8: Fs = F_clk/8, N=6 + 9: Fs = F_clk/8, N=8 + 10: Fs = F_clk/16, N=5 + 11: Fs = F_clk/16, N=6 + 12: Fs = F_clk/16, N=8 + 13: Fs = F_clk/32, N=5 + 14: Fs = F_clk/32, N=6 + 15: Fs = F_clk/32, N=8 + Default value is set by hardware at reset + default: 0 + enum: + - 0 # No filter + - 1 # FDIV1_N2 + - 2 # FDIV1_N4 + - 3 # FDIV1_N8 + - 4 # FDIV2_N6 + - 5 # FDIV2_N8 + - 6 # FDIV4_N6 + - 7 # FDIV4_N8 + - 8 # FDIV8_N6 + - 9 # FDIV8_N8 + - 10 # FDIV16_N5 + - 11 # FDIV16_N6 + - 12 # FDIV16_N8 + - 13 # FDIV32_N5 + - 14 # FDIV32_N6 + - 15 # FDIV32_N8 - st,counts-per-revolution: - type: int - required: true - description: | - This is a number >= 1 that is used to determine how many revolutions - were done based on the current counter's value. + st,counts-per-revolution: + type: int + required: true + description: | + This is a number >= 1 that is used to determine how many revolutions + were done based on the current counter's value. diff --git a/dts/bindings/sensor/st,stm32-temp-cal.yaml b/dts/bindings/sensor/st,stm32-temp-cal.yaml index e20256f6408946..b061e699ff130c 100644 --- a/dts/bindings/sensor/st,stm32-temp-cal.yaml +++ b/dts/bindings/sensor/st,stm32-temp-cal.yaml @@ -8,46 +8,46 @@ compatible: "st,stm32-temp-cal" include: [base.yaml, "st,stm32-temp-common.yaml"] properties: - ts-cal1-addr: - type: int - required: true - description: address of parameter TS_CAL1 - - ts-cal2-addr: - type: int - required: true - description: address of parameter TS_CAL2 - - ts-cal1-temp: - type: int - required: true - description: | - temperature at which temperature sensor has been - calibrated in production for data into ts-cal1-addr - - ts-cal2-temp: - type: int - required: true - description: | - temperature at which temperature sensor has been - calibrated in production for data into ts-cal2-addr - - ts-cal-vrefanalog: - type: int - required: true - description: | - Analog voltage reference (Vref+) voltage with which - temperature sensor has been calibrated in production - - ts-cal-resolution: - type: int - description: | - Temperature calibration resolution with which the ts-cal1-temp and - ts-cal2-temp are measured. - For most stm32 series a native 12-bit ADC is embedded in the device, - except for H7 on 16-bit and U5 on 14-bit - default: 12 - enum: - - 12 - - 14 - - 16 + ts-cal1-addr: + type: int + required: true + description: address of parameter TS_CAL1 + + ts-cal2-addr: + type: int + required: true + description: address of parameter TS_CAL2 + + ts-cal1-temp: + type: int + required: true + description: | + temperature at which temperature sensor has been + calibrated in production for data into ts-cal1-addr + + ts-cal2-temp: + type: int + required: true + description: | + temperature at which temperature sensor has been + calibrated in production for data into ts-cal2-addr + + ts-cal-vrefanalog: + type: int + required: true + description: | + Analog voltage reference (Vref+) voltage with which + temperature sensor has been calibrated in production + + ts-cal-resolution: + type: int + description: | + Temperature calibration resolution with which the ts-cal1-temp and + ts-cal2-temp are measured. + For most stm32 series a native 12-bit ADC is embedded in the device, + except for H7 on 16-bit and U5 on 14-bit + default: 12 + enum: + - 12 + - 14 + - 16 diff --git a/dts/bindings/sensor/st,stm32-temp-common.yaml b/dts/bindings/sensor/st,stm32-temp-common.yaml index b78e3396e665a3..cf45e234d4a74c 100644 --- a/dts/bindings/sensor/st,stm32-temp-common.yaml +++ b/dts/bindings/sensor/st,stm32-temp-common.yaml @@ -4,6 +4,6 @@ include: sensor-device.yaml properties: - io-channels: - required: true - description: ADC channel for temperature sensor + io-channels: + required: true + description: ADC channel for temperature sensor diff --git a/dts/bindings/sensor/st,stm32-temp.yaml b/dts/bindings/sensor/st,stm32-temp.yaml index 557c36f991ae3d..31ce5b84f64bee 100644 --- a/dts/bindings/sensor/st,stm32-temp.yaml +++ b/dts/bindings/sensor/st,stm32-temp.yaml @@ -8,24 +8,24 @@ compatible: "st,stm32-temp" include: [base.yaml, "st,stm32-temp-common.yaml"] properties: - avgslope: - type: int - default: 25 - description: | - Average slope of T-V chart (in mV/C x10) according to - datasheet "Electrical characteristics/Operating conditions" - STM32F1 Table 5.3.19 (min 4 mV/C, max 4.6, default 4.3) - STM32F4 Table 6.3.21 default 2.5 + avgslope: + type: int + default: 25 + description: | + Average slope of T-V chart (in mV/C x10) according to + datasheet "Electrical characteristics/Operating conditions" + STM32F1 Table 5.3.19 (min 4 mV/C, max 4.6, default 4.3) + STM32F4 Table 6.3.21 default 2.5 - v25: - type: int - default: 760 - description: | - Voltage of temperature sensor at 25C in mV according to - datasheet "Electrical characteristics/Operating conditions" - STM32F1 Table 5.3.19 (min 1340, max 1520, default 1430) - STM32F4 Table 6.3.21 default 760 + v25: + type: int + default: 760 + description: | + Voltage of temperature sensor at 25C in mV according to + datasheet "Electrical characteristics/Operating conditions" + STM32F1 Table 5.3.19 (min 1340, max 1520, default 1430) + STM32F4 Table 6.3.21 default 760 - ntc: - type: boolean - description: Negative Temperature Coefficient. True if STM32F1 + ntc: + type: boolean + description: Negative Temperature Coefficient. True if STM32F1 diff --git a/dts/bindings/sensor/st,stm32-vbat.yaml b/dts/bindings/sensor/st,stm32-vbat.yaml index bc85ba88910354..c23b8f84a35471 100644 --- a/dts/bindings/sensor/st,stm32-vbat.yaml +++ b/dts/bindings/sensor/st,stm32-vbat.yaml @@ -8,11 +8,11 @@ include: sensor-device.yaml compatible: "st,stm32-vbat" properties: - io-channels: - required: true - description: ADC channel for Vbat sensor + io-channels: + required: true + description: ADC channel for Vbat sensor - ratio: - type: int - required: true - description: fraction of VBat to be connected to the ADC input + ratio: + type: int + required: true + description: fraction of VBat to be connected to the ADC input diff --git a/dts/bindings/sensor/st,stts751-i2c.yaml b/dts/bindings/sensor/st,stts751-i2c.yaml index 3d5025ba9ec18a..83e7e629f2fe08 100644 --- a/dts/bindings/sensor/st,stts751-i2c.yaml +++ b/dts/bindings/sensor/st,stts751-i2c.yaml @@ -9,10 +9,10 @@ compatible: "st,stts751" include: [sensor-device.yaml, i2c-device.yaml] properties: - drdy-gpios: - type: phandle-array - description: DRDY pin + drdy-gpios: + type: phandle-array + description: DRDY pin - This pin defaults to active high when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. + This pin defaults to active high when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. diff --git a/dts/bindings/sensor/st,vl53l0x.yaml b/dts/bindings/sensor/st,vl53l0x.yaml index caec562912bb82..68184e8b458464 100644 --- a/dts/bindings/sensor/st,vl53l0x.yaml +++ b/dts/bindings/sensor/st,vl53l0x.yaml @@ -8,5 +8,5 @@ compatible: "st,vl53l0x" include: [sensor-device.yaml, i2c-device.yaml] properties: - xshut-gpios: - type: phandle-array + xshut-gpios: + type: phandle-array diff --git a/dts/bindings/sensor/ti,bq274xx.yaml b/dts/bindings/sensor/ti,bq274xx.yaml index 9e43683d05800f..b641e401a9ffc7 100644 --- a/dts/bindings/sensor/ti,bq274xx.yaml +++ b/dts/bindings/sensor/ti,bq274xx.yaml @@ -11,37 +11,37 @@ compatible: "ti,bq274xx" include: [sensor-device.yaml, i2c-device.yaml] properties: - design-voltage: - type: int - required: true - description: Battery Design Voltage in mV (3300 - 4400) - - design-capacity: - type: int - required: true - description: Battery Design Capacity in mAh - - taper-current: - type: int - required: true - description: Battery Taper current in mAh - - terminate-voltage: - type: int - required: true - description: Battery Terminate Voltage in mV - - int-gpios: - type: phandle-array - description: | - The INT signal defaults to active low open drain, so requires a - pull-up on the board. By default it acts as an output and signals - specific events happening (e.g. change in State of Charge). While in - shutdown mode it acts as an input and toggling it will make the sensor - exit the mode. - - zephyr,lazy-load: - type: boolean - description: | - Configuring the sensor can take a long time, using lazy loading we can delay - until the first sample request and keep the boot time as short as possible. + design-voltage: + type: int + required: true + description: Battery Design Voltage in mV (3300 - 4400) + + design-capacity: + type: int + required: true + description: Battery Design Capacity in mAh + + taper-current: + type: int + required: true + description: Battery Taper current in mAh + + terminate-voltage: + type: int + required: true + description: Battery Terminate Voltage in mV + + int-gpios: + type: phandle-array + description: | + The INT signal defaults to active low open drain, so requires a + pull-up on the board. By default it acts as an output and signals + specific events happening (e.g. change in State of Charge). While in + shutdown mode it acts as an input and toggling it will make the sensor + exit the mode. + + zephyr,lazy-load: + type: boolean + description: | + Configuring the sensor can take a long time, using lazy loading we can delay + until the first sample request and keep the boot time as short as possible. diff --git a/dts/bindings/sensor/ti,fdc2x1x.yaml b/dts/bindings/sensor/ti,fdc2x1x.yaml index ab9ce9a3d54d72..4d8d9c6f245d41 100644 --- a/dts/bindings/sensor/ti,fdc2x1x.yaml +++ b/dts/bindings/sensor/ti,fdc2x1x.yaml @@ -8,243 +8,243 @@ compatible: "ti,fdc2x1x" include: [sensor-device.yaml, i2c-device.yaml] properties: - sd-gpios: - type: phandle-array - description: | - The SD pin defaults to active high when consumed by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. - - intb-gpios: - type: phandle-array - description: | - The INTB pin defaults to active low when produced by the sensor. - The property value should ensure the flags properly describe - the signal that is presented to the driver. - - fdc2x14: - type: boolean - description: | - Set to identify the sensor as FDC2114 or FDC2214 (4-channel version) - - autoscan: - type: boolean - description: | - Set the Auto-Scan Mode. - - false = Continuous conversion on the single channel selected by - "active-channel" (single channel mode). + sd-gpios: + type: phandle-array + description: | + The SD pin defaults to active high when consumed by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + intb-gpios: + type: phandle-array + description: | + The INTB pin defaults to active low when produced by the sensor. + The property value should ensure the flags properly describe + the signal that is presented to the driver. + + fdc2x14: + type: boolean + description: | + Set to identify the sensor as FDC2114 or FDC2214 (4-channel version) + + autoscan: + type: boolean + description: | + Set the Auto-Scan Mode. + + false = Continuous conversion on the single channel selected by + "active-channel" (single channel mode). + + true = Auto-Scan conversions as selected by "rr-sequence" + (multichannel mode). + + fref: + type: int + required: true + description: | + Reference frequency of the used clock source in KHz. + The internal clock oscillates at around 43360 KHz (43.36 MHz) + at 20 degrees Celcius. + Recommended external clock source frequency is 40000 KHz (40 MHz). + + rr-sequence: + type: int + default: 0 + description: | + Auto-Scan Sequence Configuration. + The FDC will perform a single conversion on each channel + in the sequence selected, and then restart the sequence continuously. + + The sensor performs conversion on Channel 0 to 1 by default after + power-on-reset. This setting only applies if autoscan=true + (multichannel mode). + + 0 = Ch0, Ch1 + 1 = Ch0, Ch1, Ch2 (FDC2114, FDC2214 only) + 2 = Ch0, Ch1, Ch2, Ch3 (FDC2114, FDC2214 only) + enum: + - 0 + - 1 + - 2 + + active-channel: + type: int + default: 0 + description: | + Selects channel for continuous conversions. + + The sensor performs continuous conversion on Channel 0 by default after + power-on-reset. This setting only applies if autoscan=false + (single channel mode). + + 0 = Perform continuous conversions on Channel 0 + 1 = Perform continuous conversions on Channel 1 + 2 = Perform continuous conversions on Channel 2 (FDC2114, FDC2214 only) + 3 = Perform continuous conversions on Channel 3 (FDC2114, FDC2214 only) + enum: + - 0 + - 1 + - 2 + - 3 + + deglitch: + type: int + required: true + description: | + Input deglitch filter bandwidth. Select the lowest setting that exceeds + the oscillation tank oscillation frequency. + + 1 = 1MHz + 4 = 3.3MHz + 5 = 10MHz + 7 = 33MHz + enum: + - 1 + - 4 + - 5 + - 7 + + sensor-activate-sel: + type: string + default: "low-power" + description: | + Sensor Activation Mode Selection. + + The sensor uses low-power activation mode by default after + power-on-reset. + + full-current = the FDC will drive maximum + sensor current for a shorter sensor activation time. + + low-power = the FDC uses the value programmed by "idrive" during + sensor activation to minimize power consumption. + enum: + - "full-current" + - "low-power" + + ref-clk-src: + type: string + default: "internal" + description: | + Select Reference Frequency Source. + + The sensor uses the internal clock by default after power-on-reset. + + internal = Use Internal oscillator as reference frequency + external = Reference frequency is provided from CLKIN pin. + enum: + - "internal" + - "external" + + current-drive: + type: string + default: "normal" + description: | + Select Current Sensor Drive. + + The sensor uses normal current drive by default after power-on-reset. + High current drive is not supported if autoscan=false and will default + to normal. + + normal = The FDC will drive all channels with normal sensor current + (1.5mA max). + + high = The FDC will drive channel 0 with current >1.5mA. + enum: + - "normal" + - "high" + + output-gain: + type: int + default: 0 + description: | + Output gain control (FDC2112, FDC2114 only) + + The default output gain is 0 after power-on-reset. + + 0 = Gain = 1 | Effective Resolution 12 bits | 100% full scale + 1 = Gain = 4 | Effective Resolution 14 bits | 25% full scale + 2 = Gain = 8 | Effective Resolution 15 bits | 12.5% full scale + 3 = Gain = 16 | Effective Resolution 16 bits | 6.25% full scale + enum: + - 0 + - 1 + - 2 + - 3 - true = Auto-Scan conversions as selected by "rr-sequence" - (multichannel mode). +child-binding: + description: | + Settings for each channel 0-1 (FDC2112 and FDC2212) or + 0-3 (FDC2114 and FDC2214) - fref: + properties: + rcount: type: int required: true description: | - Reference frequency of the used clock source in KHz. - The internal clock oscillates at around 43360 KHz (43.36 MHz) - at 20 degrees Celcius. - Recommended external clock source frequency is 40000 KHz (40 MHz). + Channel X Reference Count Conversion Interval Time. + Valid range: 256 - 65535 - rr-sequence: + offset: type: int default: 0 description: | - Auto-Scan Sequence Configuration. - The FDC will perform a single conversion on each channel - in the sequence selected, and then restart the sequence continuously. - - The sensor performs conversion on Channel 0 to 1 by default after - power-on-reset. This setting only applies if autoscan=true - (multichannel mode). - - 0 = Ch0, Ch1 - 1 = Ch0, Ch1, Ch2 (FDC2114, FDC2214 only) - 2 = Ch0, Ch1, Ch2, Ch3 (FDC2114, FDC2214 only) - enum: - - 0 - - 1 - - 2 + Channel X Conversion Offset (FDC2112 and FDC2212 only). + The default offset value after power-on-reset is 0. + Valid range: 0 - 65535 - active-channel: + settlecount: type: int - default: 0 + required: true description: | - Selects channel for continuous conversions. + Channel X Conversion Settling. - The sensor performs continuous conversion on Channel 0 by default after - power-on-reset. This setting only applies if autoscan=false - (single channel mode). + The FDC will use this settling time to allow the LC sensor to + stabilize before initiation of a conversion on Channel X. + Valid range: 0 - 65535 - 0 = Perform continuous conversions on Channel 0 - 1 = Perform continuous conversions on Channel 1 - 2 = Perform continuous conversions on Channel 2 (FDC2114, FDC2214 only) - 3 = Perform continuous conversions on Channel 3 (FDC2114, FDC2214 only) - enum: - - 0 - - 1 - - 2 - - 3 - - deglitch: + fref-divider: type: int required: true description: | - Input deglitch filter bandwidth. Select the lowest setting that exceeds - the oscillation tank oscillation frequency. - - 1 = 1MHz - 4 = 3.3MHz - 5 = 10MHz - 7 = 33MHz - enum: - - 1 - - 4 - - 5 - - 7 - - sensor-activate-sel: - type: string - default: "low-power" - description: | - Sensor Activation Mode Selection. + Channel X Reference Divider. - The sensor uses low-power activation mode by default after - power-on-reset. + Sets the divider for Channel X reference. + Use this to scale the maximum conversion frequency. + Valid range: 1 - 1023 - full-current = the FDC will drive maximum - sensor current for a shorter sensor activation time. - - low-power = the FDC uses the value programmed by "idrive" during - sensor activation to minimize power consumption. - enum: - - "full-current" - - "low-power" - - ref-clk-src: - type: string - default: "internal" + idrive: + type: int + required: true description: | - Select Reference Frequency Source. + Channel X Sensor drive current. - The sensor uses the internal clock by default after power-on-reset. + This field defines the Drive Current used during the settling + + conversion time of Channel X sensor clock. + Valid range: 0 - 31 - internal = Use Internal oscillator as reference frequency - external = Reference frequency is provided from CLKIN pin. - enum: - - "internal" - - "external" - - current-drive: - type: string - default: "normal" + fin-sel: + type: int + required: true description: | - Select Current Sensor Drive. + Channel X Sensor frequency select. - The sensor uses normal current drive by default after power-on-reset. - High current drive is not supported if autoscan=false and will default - to normal. + For differential sensor configuration: + 1 = divide by 1. Choose for sensor frequencies between + 0.01MHz and 8.75MHz + 2 = divide by 2. Choose for sensor frequencies between 5MHz + and 10MHz - normal = The FDC will drive all channels with normal sensor current - (1.5mA max). - - high = The FDC will drive channel 0 with current >1.5mA. + For single-ended sensor configuration: + 2 = divide by 2. Choose for sensor frequencies between + 0.01MHz and 10MHz enum: - - "normal" - - "high" + - 1 # Divide by 1 + - 2 # Divide by 2 - output-gain: + inductance: type: int - default: 0 + required: true description: | - Output gain control (FDC2112, FDC2114 only) - - The default output gain is 0 after power-on-reset. - - 0 = Gain = 1 | Effective Resolution 12 bits | 100% full scale - 1 = Gain = 4 | Effective Resolution 14 bits | 25% full scale - 2 = Gain = 8 | Effective Resolution 15 bits | 12.5% full scale - 3 = Gain = 16 | Effective Resolution 16 bits | 6.25% full scale - enum: - - 0 - - 1 - - 2 - - 3 - -child-binding: - description: | - Settings for each channel 0-1 (FDC2112 and FDC2212) or - 0-3 (FDC2114 and FDC2214) - - properties: - rcount: - type: int - required: true - description: | - Channel X Reference Count Conversion Interval Time. - Valid range: 256 - 65535 - - offset: - type: int - default: 0 - description: | - Channel X Conversion Offset (FDC2112 and FDC2212 only). - The default offset value after power-on-reset is 0. - Valid range: 0 - 65535 - - settlecount: - type: int - required: true - description: | - Channel X Conversion Settling. - - The FDC will use this settling time to allow the LC sensor to - stabilize before initiation of a conversion on Channel X. - Valid range: 0 - 65535 - - fref-divider: - type: int - required: true - description: | - Channel X Reference Divider. - - Sets the divider for Channel X reference. - Use this to scale the maximum conversion frequency. - Valid range: 1 - 1023 - - idrive: - type: int - required: true - description: | - Channel X Sensor drive current. - - This field defines the Drive Current used during the settling + - conversion time of Channel X sensor clock. - Valid range: 0 - 31 - - fin-sel: - type: int - required: true - description: | - Channel X Sensor frequency select. - - For differential sensor configuration: - 1 = divide by 1. Choose for sensor frequencies between - 0.01MHz and 8.75MHz - 2 = divide by 2. Choose for sensor frequencies between 5MHz - and 10MHz - - For single-ended sensor configuration: - 2 = divide by 2. Choose for sensor frequencies between - 0.01MHz and 10MHz - enum: - - 1 # Divide by 1 - - 2 # Divide by 2 - - inductance: - type: int - required: true - description: | - Inductor value used on the PCB for the sensing network of the - specific channel, which is usually 18uH. + Inductor value used on the PCB for the sensing network of the + specific channel, which is usually 18uH. diff --git a/dts/bindings/sensor/ti,hdc.yaml b/dts/bindings/sensor/ti,hdc.yaml index f5187464efe9fc..c939c282f9c8dd 100644 --- a/dts/bindings/sensor/ti,hdc.yaml +++ b/dts/bindings/sensor/ti,hdc.yaml @@ -8,10 +8,10 @@ compatible: "ti,hdc" include: [sensor-device.yaml, i2c-device.yaml] properties: - drdy-gpios: - type: phandle-array - description: Data ready pin. + drdy-gpios: + type: phandle-array + description: Data ready pin. - The DRDYn pin of HDC sensor is open-drain, active low. - If connected directly the MCU pin should be configured - as pull-up, active low. + The DRDYn pin of HDC sensor is open-drain, active low. + If connected directly the MCU pin should be configured + as pull-up, active low. diff --git a/dts/bindings/sensor/ti,hdc20xx.yaml b/dts/bindings/sensor/ti,hdc20xx.yaml index 91186f7a60d429..c9ffe9c9e085e0 100644 --- a/dts/bindings/sensor/ti,hdc20xx.yaml +++ b/dts/bindings/sensor/ti,hdc20xx.yaml @@ -8,10 +8,10 @@ compatible: "ti,hdc20xx" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: DRDY/INT pin. + int-gpios: + type: phandle-array + description: DRDY/INT pin. - The DRDY/INT pin of HDC20xx sensor is open-drain, active low. If - connected directly the MCU pin should be configured as pull-up - as pull-up, active low. + The DRDY/INT pin of HDC20xx sensor is open-drain, active low. If + connected directly the MCU pin should be configured as pull-up + as pull-up, active low. diff --git a/dts/bindings/sensor/ti,ina219.yaml b/dts/bindings/sensor/ti,ina219.yaml index 000c70becd39eb..2fcc40a2314ba7 100644 --- a/dts/bindings/sensor/ti,ina219.yaml +++ b/dts/bindings/sensor/ti,ina219.yaml @@ -8,120 +8,120 @@ compatible: "ti,ina219" include: [sensor-device.yaml, i2c-device.yaml] properties: - lsb-microamp: - type: int - required: true - description: | - Current LSB in microAmpere - Current LSB = max expected current [A] / 2^15 - example: 100 -> ~3A - shunt-milliohm: - type: int - required: true - description: | - Value of the shunt resistor in milliOhm - brng: - type: int - default: 1 - description: | - Bus Voltage Range - 0 = 16 V FSR - 1 = 32 V FSR + lsb-microamp: + type: int + required: true + description: | + Current LSB in microAmpere + Current LSB = max expected current [A] / 2^15 + example: 100 -> ~3A + shunt-milliohm: + type: int + required: true + description: | + Value of the shunt resistor in milliOhm + brng: + type: int + default: 1 + description: | + Bus Voltage Range + 0 = 16 V FSR + 1 = 32 V FSR - The default of 32V is the power-on reset value of the device. + The default of 32V is the power-on reset value of the device. - Should the expected bus voltage be below 16V set this to 0. - enum: - - 0 - - 1 - pg: - type: int - default: 3 - description: | - Programmable Gain - 0 = 1 -> ±40 mV - 1 = /2 -> ±80 mV - 2 = /4 -> ±160 mV - 3 = /8 -> ±320 mV + Should the expected bus voltage be below 16V set this to 0. + enum: + - 0 + - 1 + pg: + type: int + default: 3 + description: | + Programmable Gain + 0 = 1 -> ±40 mV + 1 = /2 -> ±80 mV + 2 = /4 -> ±160 mV + 3 = /8 -> ±320 mV - The default of ±320 mV is the power-on reset value of the device. + The default of ±320 mV is the power-on reset value of the device. - In case the expected voltage drop across the shunt resistor is lower - one can adjust this to get more accurate readings. - enum: - - 0 - - 1 - - 2 - - 3 - badc: - type: int - default: 3 - description: | - Bus ADC configuration - 0 = 9 bit -> 84 µs - 1 = 10 bit -> 148 µs - 2 = 11 bit -> 276 µs - 3 = 12 bit -> 532 µs - 9 = 12 bit - 2 sample averaging -> 1.06 ms - 10 = 12 bit - 4 sample averaging -> 2.13 ms - 11 = 12 bit - 8 sample averaging -> 4.26 ms - 12 = 12 bit - 16 sample averaging -> 8.51 ms - 13 = 12 bit - 32 sample averaging -> 17.02 ms - 14 = 12 bit - 64 sample averaging -> 34.05 ms - 15 = 12 bit - 128 sample averaging -> 68.10 ms + In case the expected voltage drop across the shunt resistor is lower + one can adjust this to get more accurate readings. + enum: + - 0 + - 1 + - 2 + - 3 + badc: + type: int + default: 3 + description: | + Bus ADC configuration + 0 = 9 bit -> 84 µs + 1 = 10 bit -> 148 µs + 2 = 11 bit -> 276 µs + 3 = 12 bit -> 532 µs + 9 = 12 bit - 2 sample averaging -> 1.06 ms + 10 = 12 bit - 4 sample averaging -> 2.13 ms + 11 = 12 bit - 8 sample averaging -> 4.26 ms + 12 = 12 bit - 16 sample averaging -> 8.51 ms + 13 = 12 bit - 32 sample averaging -> 17.02 ms + 14 = 12 bit - 64 sample averaging -> 34.05 ms + 15 = 12 bit - 128 sample averaging -> 68.10 ms - The default of 12 bit is the power-on reset value of the device. + The default of 12 bit is the power-on reset value of the device. - Lowering the resolution of the ADC gives less accurate readings but - cuts down on conversion times. + Lowering the resolution of the ADC gives less accurate readings but + cuts down on conversion times. - Averaging over multiple samples gives more stable readings but adds - to overall conversion time. - enum: - - 0 - - 1 - - 2 - - 3 - - 9 - - 10 - - 11 - - 12 - - 13 - - 14 - - 15 - sadc: - type: int - default: 3 - description: | - Shunt ADC configuration - 0 = 9 bit -> 84 µs - 1 = 10 bit -> 148 µs - 2 = 11 bit -> 276 µs - 3 = 12 bit -> 532 µs - 9 = 12 bit - 2 sample averaging -> 1.06 ms - 10 = 12 bit - 4 sample averaging -> 2.13 ms - 11 = 12 bit - 8 sample averaging -> 4.26 ms - 12 = 12 bit - 16 sample averaging -> 8.51 ms - 13 = 12 bit - 32 sample averaging -> 17.02 ms - 14 = 12 bit - 64 sample averaging -> 34.05 ms - 15 = 12 bit - 128 sample averaging -> 68.10 ms + Averaging over multiple samples gives more stable readings but adds + to overall conversion time. + enum: + - 0 + - 1 + - 2 + - 3 + - 9 + - 10 + - 11 + - 12 + - 13 + - 14 + - 15 + sadc: + type: int + default: 3 + description: | + Shunt ADC configuration + 0 = 9 bit -> 84 µs + 1 = 10 bit -> 148 µs + 2 = 11 bit -> 276 µs + 3 = 12 bit -> 532 µs + 9 = 12 bit - 2 sample averaging -> 1.06 ms + 10 = 12 bit - 4 sample averaging -> 2.13 ms + 11 = 12 bit - 8 sample averaging -> 4.26 ms + 12 = 12 bit - 16 sample averaging -> 8.51 ms + 13 = 12 bit - 32 sample averaging -> 17.02 ms + 14 = 12 bit - 64 sample averaging -> 34.05 ms + 15 = 12 bit - 128 sample averaging -> 68.10 ms - The default of 12 bit is the power-on reset value of the device. + The default of 12 bit is the power-on reset value of the device. - Lowering the resolution of the ADC gives less accurate readings but - cuts down on conversion times. + Lowering the resolution of the ADC gives less accurate readings but + cuts down on conversion times. - Averaging over multiple samples gives more stable readings but adds - to overall conversion time. - enum: - - 0 - - 1 - - 2 - - 3 - - 9 - - 10 - - 11 - - 12 - - 13 - - 14 - - 15 + Averaging over multiple samples gives more stable readings but adds + to overall conversion time. + enum: + - 0 + - 1 + - 2 + - 3 + - 9 + - 10 + - 11 + - 12 + - 13 + - 14 + - 15 diff --git a/dts/bindings/sensor/ti,ina230.yaml b/dts/bindings/sensor/ti,ina230.yaml index 62af3f991083cd..bc59a090b5f6ad 100644 --- a/dts/bindings/sensor/ti,ina230.yaml +++ b/dts/bindings/sensor/ti,ina230.yaml @@ -16,14 +16,14 @@ compatible: "ti,ina230" include: ti,ina23x-common.yaml properties: - mask: - type: int - default: 0 - # default all alert sources to disabled - description: Mask register, default matches the power-on reset value + mask: + type: int + default: 0 + # default all alert sources to disabled + description: Mask register, default matches the power-on reset value - alert-limit: - type: int - default: 0 - # default alert limit is 0V - description: Alert register, default matches the power-on reset value + alert-limit: + type: int + default: 0 + # default alert limit is 0V + description: Alert register, default matches the power-on reset value diff --git a/dts/bindings/sensor/ti,ina237.yaml b/dts/bindings/sensor/ti,ina237.yaml index a41dee2d3b28ae..cb223a1e672e5e 100644 --- a/dts/bindings/sensor/ti,ina237.yaml +++ b/dts/bindings/sensor/ti,ina237.yaml @@ -15,13 +15,13 @@ compatible: "ti,ina237" include: ti,ina23x-common.yaml properties: - adc-config: - type: int - required: true - description: | - Value of the ADC configuration register (ADC conversion times, - averaging, operating mode and etc). + adc-config: + type: int + required: true + description: | + Value of the ADC configuration register (ADC conversion times, + averaging, operating mode and etc). - alert-config: - type: int - description: Diag alert register, default matches the power-on reset value + alert-config: + type: int + description: Diag alert register, default matches the power-on reset value diff --git a/dts/bindings/sensor/ti,ina23x-common.yaml b/dts/bindings/sensor/ti,ina23x-common.yaml index e010ba3d5fdea9..7e196a30a43f1b 100644 --- a/dts/bindings/sensor/ti,ina23x-common.yaml +++ b/dts/bindings/sensor/ti,ina23x-common.yaml @@ -7,38 +7,38 @@ include: [sensor-device.yaml, i2c-device.yaml] properties: - config: - type: int - required: true - description: | - Value of the configuration register - e.g shunt voltage and bus voltage ADC conversion - times and averaging, operating mode for INA230 or - delay for initial ADC conversion, shunt full scale range - for INA237. - - current-lsb-microamps: - type: int - required: true - description: | - This value should be selected so that measurement resolution is - maximized, that is: - - current-lsb(A) = maximum expected current(A) / 2^15 - - (sensor has 15 bits). For example, if maximum expected current is 15A: - - current-lsb(A) = 15A / 2^15 ~= 457uA - - Rounded values may be used for convenience, e.g. 500uA/LSB or 1mA/LSB - while keeping a good measurement resolution. The units are in uA/LSB - so that low maximum currents can be measured with enough resolution. - - rshunt-milliohms: - type: int - required: true - description: Shunt resistor value in milliohms - - alert-gpios: - type: phandle-array - description: Alert pin + config: + type: int + required: true + description: | + Value of the configuration register + e.g shunt voltage and bus voltage ADC conversion + times and averaging, operating mode for INA230 or + delay for initial ADC conversion, shunt full scale range + for INA237. + + current-lsb-microamps: + type: int + required: true + description: | + This value should be selected so that measurement resolution is + maximized, that is: + + current-lsb(A) = maximum expected current(A) / 2^15 + + (sensor has 15 bits). For example, if maximum expected current is 15A: + + current-lsb(A) = 15A / 2^15 ~= 457uA + + Rounded values may be used for convenience, e.g. 500uA/LSB or 1mA/LSB + while keeping a good measurement resolution. The units are in uA/LSB + so that low maximum currents can be measured with enough resolution. + + rshunt-milliohms: + type: int + required: true + description: Shunt resistor value in milliohms + + alert-gpios: + type: phandle-array + description: Alert pin diff --git a/dts/bindings/sensor/ti,tmp007.yaml b/dts/bindings/sensor/ti,tmp007.yaml index 3037f2121cc403..4d8629c357a147 100644 --- a/dts/bindings/sensor/ti,tmp007.yaml +++ b/dts/bindings/sensor/ti,tmp007.yaml @@ -10,8 +10,8 @@ compatible: "ti,tmp007" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - Identifies the ALERT signal, which is active-low open drain when - produced by the sensor. + int-gpios: + type: phandle-array + description: | + Identifies the ALERT signal, which is active-low open drain when + produced by the sensor. diff --git a/dts/bindings/sensor/ti,tmp108.yaml b/dts/bindings/sensor/ti,tmp108.yaml index 19175b42ad78da..4a6822cabee48e 100644 --- a/dts/bindings/sensor/ti,tmp108.yaml +++ b/dts/bindings/sensor/ti,tmp108.yaml @@ -11,8 +11,8 @@ compatible: "ti,tmp108" include: [sensor-device.yaml, i2c-device.yaml] properties: - alert-gpios: - type: phandle-array - description: | - Identifies the ALERT signal, which is active-low open drain when - produced by the sensor. + alert-gpios: + type: phandle-array + description: | + Identifies the ALERT signal, which is active-low open drain when + produced by the sensor. diff --git a/dts/bindings/sensor/vishay,vcnl4040.yaml b/dts/bindings/sensor/vishay,vcnl4040.yaml index 687a1b306f6110..96d4b2c5e54ddb 100644 --- a/dts/bindings/sensor/vishay,vcnl4040.yaml +++ b/dts/bindings/sensor/vishay,vcnl4040.yaml @@ -10,73 +10,73 @@ compatible: "vishay,vcnl4040" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - The INT pin signals that a programmable interrupt function - for ALS and PS with upper and lower thresholds has been - triggered. The sensor generates an active-low level signal - which remains asserted until the data is read. + int-gpios: + type: phandle-array + description: | + The INT pin signals that a programmable interrupt function + for ALS and PS with upper and lower thresholds has been + triggered. The sensor generates an active-low level signal + which remains asserted until the data is read. - led-current: - type: int - default: 50 - # default of 50 mA is POR (0b000) for PS_MS[LED_I] register - description: LED current in mA - enum: - - 50 - - 75 - - 100 - - 120 - - 140 - - 160 - - 180 - - 200 + led-current: + type: int + default: 50 + # default of 50 mA is POR (0b000) for PS_MS[LED_I] register + description: LED current in mA + enum: + - 50 + - 75 + - 100 + - 120 + - 140 + - 160 + - 180 + - 200 - led-duty-cycle: - type: int - default: 40 - # default of 40 Hz is POR (0b00) for PS_CONF1[PS_Duty] register - description: LED duty cycle in Hz - enum: - - 40 - - 80 - - 160 - - 320 + led-duty-cycle: + type: int + default: 40 + # default of 40 Hz is POR (0b00) for PS_CONF1[PS_Duty] register + description: LED duty cycle in Hz + enum: + - 40 + - 80 + - 160 + - 320 - proximity-it: - type: string - default: "1" - # default of 1 is POR (0b000) for PS_CONF2[PS_IT] register - description: Proximity integration time in T - enum: - - "1" - - "1.5" - - "2" - - "2.5" - - "3" - - "3.5" - - "4" - - "8" + proximity-it: + type: string + default: "1" + # default of 1 is POR (0b000) for PS_CONF2[PS_IT] register + description: Proximity integration time in T + enum: + - "1" + - "1.5" + - "2" + - "2.5" + - "3" + - "3.5" + - "4" + - "8" - proximity-trigger: - type: string - default: "disabled" - # default of "disabled" is POR (0b00) for PS_CONF2[PS_INT] register - description: Proximity trigger type - enum: - - "disabled" - - "close" - - "away" - - "close-away" + proximity-trigger: + type: string + default: "disabled" + # default of "disabled" is POR (0b00) for PS_CONF2[PS_INT] register + description: Proximity trigger type + enum: + - "disabled" + - "close" + - "away" + - "close-away" - als-it: - type: int - default: 80 - # default of 80 is POR (0b00) for ALS_CONF[ALS_IT] register - description: ALS integration time in ms - enum: - - 80 - - 160 - - 320 - - 640 + als-it: + type: int + default: 80 + # default of 80 is POR (0b00) for ALS_CONF[ALS_IT] register + description: ALS integration time in ms + enum: + - 80 + - 160 + - 320 + - 640 diff --git a/dts/bindings/sensor/we,wsen-hids-common.yaml b/dts/bindings/sensor/we,wsen-hids-common.yaml index b1863f1f807ad4..be3c5906e4c09e 100644 --- a/dts/bindings/sensor/we,wsen-hids-common.yaml +++ b/dts/bindings/sensor/we,wsen-hids-common.yaml @@ -4,19 +4,19 @@ include: sensor-device.yaml properties: - drdy-gpios: - type: phandle-array - description: | - Data-ready interrupt pin. - Interrupt is active high by default. + drdy-gpios: + type: phandle-array + description: | + Data-ready interrupt pin. + Interrupt is active high by default. - odr: - type: string - required: true - enum: - - "1" - - "7" - - "12.5" - description: | - Sensor output data rate expressed in samples per second. - Data rates supported by the chip are "1", "7" and "12.5". + odr: + type: string + required: true + enum: + - "1" + - "7" + - "12.5" + description: | + Sensor output data rate expressed in samples per second. + Data rates supported by the chip are "1", "7" and "12.5". diff --git a/dts/bindings/sensor/we,wsen-itds.yaml b/dts/bindings/sensor/we,wsen-itds.yaml index 236c792bbafc54..5f73ed01867861 100644 --- a/dts/bindings/sensor/we,wsen-itds.yaml +++ b/dts/bindings/sensor/we,wsen-itds.yaml @@ -8,33 +8,33 @@ compatible: "we,wsen-itds" include: [sensor-device.yaml, i2c-device.yaml] properties: - int-gpios: - type: phandle-array - description: | - This property specifies the connection for INT0, the driver maps - all interrupts to INT0 as default. The signal to output high when - data produced by the sensor. + int-gpios: + type: phandle-array + description: | + This property specifies the connection for INT0, the driver maps + all interrupts to INT0 as default. The signal to output high when + data produced by the sensor. - odr: - type: string - required: true - description: Output data rate in Hz - enum: - - "1.6" - - "12.5" - - "25" - - "50" - - "100" - - "200" - - "400" - - "800" - - "1600" + odr: + type: string + required: true + description: Output data rate in Hz + enum: + - "1.6" + - "12.5" + - "25" + - "50" + - "100" + - "200" + - "400" + - "800" + - "1600" - op-mode: - type: string - required: true - description: Operating mode of sensor - enum: - - "low-power" - - "normal" - - "high-perf" + op-mode: + type: string + required: true + description: Operating mode of sensor + enum: + - "low-power" + - "normal" + - "high-perf" diff --git a/dts/bindings/serial/altr,jtag-uart.yaml b/dts/bindings/serial/altr,jtag-uart.yaml index fd10756aa35e9f..8f539519ead374 100644 --- a/dts/bindings/serial/altr,jtag-uart.yaml +++ b/dts/bindings/serial/altr,jtag-uart.yaml @@ -5,5 +5,5 @@ compatible: "altr,jtag-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/serial/arm,cmsdk-uart.yaml b/dts/bindings/serial/arm,cmsdk-uart.yaml index 667670c443e3fd..88288c15169aaa 100644 --- a/dts/bindings/serial/arm,cmsdk-uart.yaml +++ b/dts/bindings/serial/arm,cmsdk-uart.yaml @@ -5,8 +5,8 @@ compatible: "arm,cmsdk-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/arm,pl011.yaml b/dts/bindings/serial/arm,pl011.yaml index 2711f29d27615b..e823638ede0492 100644 --- a/dts/bindings/serial/arm,pl011.yaml +++ b/dts/bindings/serial/arm,pl011.yaml @@ -5,8 +5,8 @@ compatible: "arm,pl011" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/arm,sbsa-uart.yaml b/dts/bindings/serial/arm,sbsa-uart.yaml index 97c6d4c9b063d9..287e21d38574ef 100644 --- a/dts/bindings/serial/arm,sbsa-uart.yaml +++ b/dts/bindings/serial/arm,sbsa-uart.yaml @@ -5,7 +5,7 @@ compatible: "arm,sbsa-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: + interrupts: diff --git a/dts/bindings/serial/atmel,sam-uart.yaml b/dts/bindings/serial/atmel,sam-uart.yaml index 9d3a242675369b..8534d0b2324c78 100644 --- a/dts/bindings/serial/atmel,sam-uart.yaml +++ b/dts/bindings/serial/atmel,sam-uart.yaml @@ -3,17 +3,17 @@ description: SAM family UART compatible: "atmel,sam-uart" include: - - name: uart-controller.yaml - - name: pinctrl-device.yaml + - name: uart-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/serial/atmel,sam-usart.yaml b/dts/bindings/serial/atmel,sam-usart.yaml index 91c6f0b8f566ee..cb81deca1afbd3 100644 --- a/dts/bindings/serial/atmel,sam-usart.yaml +++ b/dts/bindings/serial/atmel,sam-usart.yaml @@ -3,17 +3,17 @@ description: Atmel SAM family USART compatible: "atmel,sam-usart" include: - - name: uart-controller.yaml - - name: pinctrl-device.yaml + - name: uart-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/serial/atmel,sam0-uart.yaml b/dts/bindings/serial/atmel,sam0-uart.yaml index 140c7a9bc9758d..30588f35dfd795 100644 --- a/dts/bindings/serial/atmel,sam0-uart.yaml +++ b/dts/bindings/serial/atmel,sam0-uart.yaml @@ -3,49 +3,49 @@ description: Atmel SAM0 SERCOM UART driver compatible: "atmel,sam0-uart" include: - - name: uart-controller.yaml - - name: pinctrl-device.yaml + - name: uart-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - clock-names: - required: true + clock-names: + required: true - rxpo: - type: int - required: true - description: Receive Data Pinout + rxpo: + type: int + required: true + description: Receive Data Pinout - txpo: - type: int - required: true - description: Transmit Data Pinout + txpo: + type: int + required: true + description: Transmit Data Pinout - collision-detection: - type: boolean - description: Enable collision detection for half-duplex mode. + collision-detection: + type: boolean + description: Enable collision detection for half-duplex mode. - dmas: - description: | - Optional TX & RX dma specifiers. Each specifier will have a phandle - reference to the dmac controller, the channel number, and peripheral - trigger source. + dmas: + description: | + Optional TX & RX dma specifiers. Each specifier will have a phandle + reference to the dmac controller, the channel number, and peripheral + trigger source. - For example dmas for TX, RX on SERCOM3 - dmas = <&dmac 0 0xb>, <&dmac 0 0xa>; + For example dmas for TX, RX on SERCOM3 + dmas = <&dmac 0 0xb>, <&dmac 0 0xa>; - dma-names: - description: | - Required if the dmas property exists. This should be "tx" and "rx" - to match the dmas property. + dma-names: + description: | + Required if the dmas property exists. This should be "tx" and "rx" + to match the dmas property. - For example - dma-names = "tx", "rx"; + For example + dma-names = "tx", "rx"; diff --git a/dts/bindings/serial/cdns,uart.yaml b/dts/bindings/serial/cdns,uart.yaml index 2f7b154efa2657..1962ed17d52518 100644 --- a/dts/bindings/serial/cdns,uart.yaml +++ b/dts/bindings/serial/cdns,uart.yaml @@ -10,17 +10,17 @@ compatible: "cdns,uart" include: uart-controller.yaml properties: - current-speed: - type: int - required: true - description: Baud Rate in bps. - clock-frequency: - type: int - required: true - description: Frequency(Hz) of Clock to the UART IP. - bdiv: - type: int - required: true - description: Baud Rate Divide register value. - reg: - required: true + current-speed: + type: int + required: true + description: Baud Rate in bps. + clock-frequency: + type: int + required: true + description: Frequency(Hz) of Clock to the UART IP. + bdiv: + type: int + required: true + description: Baud Rate Divide register value. + reg: + required: true diff --git a/dts/bindings/serial/cypress,psoc6-uart.yaml b/dts/bindings/serial/cypress,psoc6-uart.yaml index 37fcac07a2fb61..543975ab7c8c2d 100644 --- a/dts/bindings/serial/cypress,psoc6-uart.yaml +++ b/dts/bindings/serial/cypress,psoc6-uart.yaml @@ -9,26 +9,26 @@ compatible: "cypress,psoc6-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true - pinctrl-0: - type: phandles - description: | - Port pin configuration for RX & TX signals. We expect that the - phandles will reference pinctrl nodes. These nodes will have a - nodelabel that matches the Cypress SoC HAL defines and be of the - form p___. + pinctrl-0: + type: phandles + description: | + Port pin configuration for RX & TX signals. We expect that the + phandles will reference pinctrl nodes. These nodes will have a + nodelabel that matches the Cypress SoC HAL defines and be of the + form p___. - For example the UART on PSoC-63 Pioneer Kit would be - pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>; + For example the UART on PSoC-63 Pioneer Kit would be + pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>; - required: true + required: true diff --git a/dts/bindings/serial/espressif,esp32-uart.yaml b/dts/bindings/serial/espressif,esp32-uart.yaml index 4c4e73412f5a1e..82f1144766190f 100644 --- a/dts/bindings/serial/espressif,esp32-uart.yaml +++ b/dts/bindings/serial/espressif,esp32-uart.yaml @@ -5,11 +5,11 @@ compatible: "espressif,esp32-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/serial/gaisler,apbuart.yaml b/dts/bindings/serial/gaisler,apbuart.yaml index 338d737efda4d7..48d0e35bb75cc2 100644 --- a/dts/bindings/serial/gaisler,apbuart.yaml +++ b/dts/bindings/serial/gaisler,apbuart.yaml @@ -5,5 +5,5 @@ compatible: "gaisler,apbuart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/serial/gd,gd32-usart.yaml b/dts/bindings/serial/gd,gd32-usart.yaml index 5cd27a016f0db5..6b6b3f6914b1e2 100644 --- a/dts/bindings/serial/gd,gd32-usart.yaml +++ b/dts/bindings/serial/gd,gd32-usart.yaml @@ -8,14 +8,14 @@ compatible: "gd,gd32-usart" include: [uart-controller.yaml, reset-device.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - resets: - required: true + resets: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/serial/infineon,xmc4xxx-uart.yaml b/dts/bindings/serial/infineon,xmc4xxx-uart.yaml index c0609561b0b00c..dec73ae7446506 100644 --- a/dts/bindings/serial/infineon,xmc4xxx-uart.yaml +++ b/dts/bindings/serial/infineon,xmc4xxx-uart.yaml @@ -5,78 +5,78 @@ compatible: "infineon,xmc4xxx-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - input-src: - description: | - Connects the UART receive line (USIC DX0 input) to a specific GPIO pin. - The USIC DX0 input is a multiplexer which connects to different GPIO pins. - Refer to the XMC4XXX reference manual for the GPIO pin/mux mappings. DX0G - is the loopback input line. - type: string - required: true - enum: - - "DX0A" - - "DX0B" - - "DX0C" - - "DX0D" - - "DX0E" - - "DX0F" - - "DX0G" + input-src: + description: | + Connects the UART receive line (USIC DX0 input) to a specific GPIO pin. + The USIC DX0 input is a multiplexer which connects to different GPIO pins. + Refer to the XMC4XXX reference manual for the GPIO pin/mux mappings. DX0G + is the loopback input line. + type: string + required: true + enum: + - "DX0A" + - "DX0B" + - "DX0C" + - "DX0D" + - "DX0E" + - "DX0F" + - "DX0G" - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - fifo-start-offset: - description: | - Each USIC0..2 has a fifo that is shared between two channels. For example, - usic0ch0 and usic0ch1 will share the same fifo. This parameter defines an offset - where the tx and rx fifos will start. When sharing the fifo, the user must properly - define the offset based on the configuration of the other channel. The fifo has a - capacity of 64 entries. The tx/rx fifos are created on fifo-xx-size aligned - boundaries. + fifo-start-offset: + description: | + Each USIC0..2 has a fifo that is shared between two channels. For example, + usic0ch0 and usic0ch1 will share the same fifo. This parameter defines an offset + where the tx and rx fifos will start. When sharing the fifo, the user must properly + define the offset based on the configuration of the other channel. The fifo has a + capacity of 64 entries. The tx/rx fifos are created on fifo-xx-size aligned + boundaries. - required: true - type: int + required: true + type: int - fifo-tx-size: - description: | - Fifo size used for buffering transmit bytes. A value of 0 implies that - the fifo is not used while transmitting. - required: true - type: int - enum: - - 0 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 + fifo-tx-size: + description: | + Fifo size used for buffering transmit bytes. A value of 0 implies that + the fifo is not used while transmitting. + required: true + type: int + enum: + - 0 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 - fifo-rx-size: - description: | - Fifo size used for buffering received bytes. A value of 0 implies that - the fifo is not used while receiving. - required: true - type: int - enum: - - 0 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 + fifo-rx-size: + description: | + Fifo size used for buffering received bytes. A value of 0 implies that + the fifo is not used while receiving. + required: true + type: int + enum: + - 0 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 - interrupts: - description: | - IRQ number and priority to use for interrupt driven UART. - USIC0..2 have their own interrupt range as follows: - USIC0 = [84, 89] - USIC1 = [90, 95] - USIC2 = [96, 101] + interrupts: + description: | + IRQ number and priority to use for interrupt driven UART. + USIC0..2 have their own interrupt range as follows: + USIC0 = [84, 89] + USIC1 = [90, 95] + USIC2 = [96, 101] diff --git a/dts/bindings/serial/ite,it8xxx2-uart.yaml b/dts/bindings/serial/ite,it8xxx2-uart.yaml index 73689ac02133ff..d04d835c1d64ba 100644 --- a/dts/bindings/serial/ite,it8xxx2-uart.yaml +++ b/dts/bindings/serial/ite,it8xxx2-uart.yaml @@ -8,25 +8,25 @@ compatible: "ite,it8xxx2-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - port-num: - type: int - required: true - description: Ordinal identifying the port + port-num: + type: int + required: true + description: Ordinal identifying the port - gpios: - type: phandle-array - required: true + gpios: + type: phandle-array + required: true - uart-dev: - type: phandle - required: true - description: Get the handle of the UART device + uart-dev: + type: phandle + required: true + description: Get the handle of the UART device - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/serial/litex,uart0.yaml b/dts/bindings/serial/litex,uart0.yaml index c798d8808067be..1c60e75c89fb87 100644 --- a/dts/bindings/serial/litex,uart0.yaml +++ b/dts/bindings/serial/litex,uart0.yaml @@ -8,8 +8,8 @@ compatible: "litex,uart0" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/microchip,xec-uart.yaml b/dts/bindings/serial/microchip,xec-uart.yaml index 6ac77e7ebf1804..7d670f1de4c1e2 100644 --- a/dts/bindings/serial/microchip,xec-uart.yaml +++ b/dts/bindings/serial/microchip,xec-uart.yaml @@ -5,29 +5,29 @@ compatible: "microchip,xec-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - ldn: - type: int - required: true - description: logical device number + ldn: + type: int + required: true + description: logical device number - girqs: - type: array - required: true - description: UART GIRQ and bit position in EC interrupt aggregator + girqs: + type: array + required: true + description: UART GIRQ and bit position in EC interrupt aggregator - pcrs: - type: array - required: true - description: UART Power Clock Reset(PCR) register index and bit position + pcrs: + type: array + required: true + description: UART Power Clock Reset(PCR) register index and bit position - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/serial/microsemi,coreuart.yaml b/dts/bindings/serial/microsemi,coreuart.yaml index 4a56369ff37dad..e5764a21a19297 100644 --- a/dts/bindings/serial/microsemi,coreuart.yaml +++ b/dts/bindings/serial/microsemi,coreuart.yaml @@ -8,5 +8,5 @@ compatible: "microsemi,coreuart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/serial/neorv32-uart.yaml b/dts/bindings/serial/neorv32-uart.yaml index c60e6066b96425..8c9b8334c0b243 100644 --- a/dts/bindings/serial/neorv32-uart.yaml +++ b/dts/bindings/serial/neorv32-uart.yaml @@ -5,20 +5,20 @@ compatible: "neorv32-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - interrupt-names: - required: true + interrupt-names: + required: true - current-speed: - required: true + current-speed: + required: true - syscon: - type: phandle - required: true - description: | - phandle to syscon (NEORV32 SYSINFO) node. + syscon: + type: phandle + required: true + description: | + phandle to syscon (NEORV32 SYSINFO) node. diff --git a/dts/bindings/serial/nordic,nrf-uart-common.yaml b/dts/bindings/serial/nordic,nrf-uart-common.yaml index b02f33c9b409b3..a5d645975c7153 100644 --- a/dts/bindings/serial/nordic,nrf-uart-common.yaml +++ b/dts/bindings/serial/nordic,nrf-uart-common.yaml @@ -1,105 +1,105 @@ include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - disable-rx: - type: boolean - description: | - Disable UART reception capabilities (only required to disable reception - if CONFIG_PINCTRL is enabled). - - current-speed: - description: | - Initial baud rate setting for UART. Only a fixed set of baud - rates are selectable on these devices. - enum: - - 1200 - - 2400 - - 4800 - - 9600 - - 14400 - - 19200 - - 28800 - - 31250 - - 38400 - - 56000 - - 57600 - - 76800 - - 115200 - - 230400 - - 250000 - - 460800 - - 921600 - - 1000000 - - tx-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The TX pin to use. - - For pins P0.0 through P0.31, use the pin number. For example, - to use P0.16 for TX, set: - - tx-pin = <16>; - - For pins P1.0 through P1.31, add 32 to the pin number. For - example, to use P1.2 for TX, set: - - tx-pin = <34>; /* 32 + 2 */ - - rx-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The RX pin to use. The pin numbering scheme is the same as the - tx-pin property's. - - rts-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The RTS pin to use. The pin numbering scheme is the same as the - tx-pin property's. - - cts-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The CTS pin to use. The pin numbering scheme is the same as the - tx-pin property's. - - rx-pull-up: - type: boolean - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - Enable pull-up resistor on the RX pin. - - cts-pull-up: - type: boolean - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - Enable pull-up resistor on the CTS pin. + reg: + required: true + + interrupts: + required: true + + disable-rx: + type: boolean + description: | + Disable UART reception capabilities (only required to disable reception + if CONFIG_PINCTRL is enabled). + + current-speed: + description: | + Initial baud rate setting for UART. Only a fixed set of baud + rates are selectable on these devices. + enum: + - 1200 + - 2400 + - 4800 + - 9600 + - 14400 + - 19200 + - 28800 + - 31250 + - 38400 + - 56000 + - 57600 + - 76800 + - 115200 + - 230400 + - 250000 + - 460800 + - 921600 + - 1000000 + + tx-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The TX pin to use. + + For pins P0.0 through P0.31, use the pin number. For example, + to use P0.16 for TX, set: + + tx-pin = <16>; + + For pins P1.0 through P1.31, add 32 to the pin number. For + example, to use P1.2 for TX, set: + + tx-pin = <34>; /* 32 + 2 */ + + rx-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The RX pin to use. The pin numbering scheme is the same as the + tx-pin property's. + + rts-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The RTS pin to use. The pin numbering scheme is the same as the + tx-pin property's. + + cts-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The CTS pin to use. The pin numbering scheme is the same as the + tx-pin property's. + + rx-pull-up: + type: boolean + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + Enable pull-up resistor on the RX pin. + + cts-pull-up: + type: boolean + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + Enable pull-up resistor on the CTS pin. diff --git a/dts/bindings/serial/ns16550.yaml b/dts/bindings/serial/ns16550.yaml index 814987d8494093..8823d236256fa9 100644 --- a/dts/bindings/serial/ns16550.yaml +++ b/dts/bindings/serial/ns16550.yaml @@ -5,15 +5,15 @@ compatible: "ns16550" include: [uart-controller.yaml, pcie-device.yaml] properties: - reg-shift: - type: int - required: true - description: quantity to shift the register offsets by + reg-shift: + type: int + required: true + description: quantity to shift the register offsets by - pcp: - type: int - description: custom clock (PRV_CLOCK_PARAMS, if supported) + pcp: + type: int + description: custom clock (PRV_CLOCK_PARAMS, if supported) - dlf: - type: int - description: divisor latch fraction (DLF, if supported) + dlf: + type: int + description: divisor latch fraction (DLF, if supported) diff --git a/dts/bindings/serial/nuvoton,npcx-uart.yaml b/dts/bindings/serial/nuvoton,npcx-uart.yaml index 8b309a90d77312..3e6ed207ba389b 100644 --- a/dts/bindings/serial/nuvoton,npcx-uart.yaml +++ b/dts/bindings/serial/nuvoton,npcx-uart.yaml @@ -8,19 +8,19 @@ compatible: "nuvoton,npcx-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - clocks: - required: true - pinctrl-0: - required: true - pinctrl-names: - required: true - uart-rx: - type: phandle - required: true - description: | - Mapping table between Wake-Up Input (WUI) and uart rx START signal. + reg: + required: true + clocks: + required: true + pinctrl-0: + required: true + pinctrl-names: + required: true + uart-rx: + type: phandle + required: true + description: | + Mapping table between Wake-Up Input (WUI) and uart rx START signal. - For example the WUI mapping on NPCX7 UART1 would be - uart-rx = <&wui_cr_sin1>; + For example the WUI mapping on NPCX7 UART1 would be + uart-rx = <&wui_cr_sin1>; diff --git a/dts/bindings/serial/nuvoton,numicro-uart.yaml b/dts/bindings/serial/nuvoton,numicro-uart.yaml index 3627fe9ccc3c5d..50a809606695db 100644 --- a/dts/bindings/serial/nuvoton,numicro-uart.yaml +++ b/dts/bindings/serial/nuvoton,numicro-uart.yaml @@ -5,8 +5,8 @@ compatible: "nuvoton,numicro-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true diff --git a/dts/bindings/serial/nxp,imx-iuart.yaml b/dts/bindings/serial/nxp,imx-iuart.yaml index d1898e2e4659d3..6abfb13b6684d0 100644 --- a/dts/bindings/serial/nxp,imx-iuart.yaml +++ b/dts/bindings/serial/nxp,imx-iuart.yaml @@ -6,14 +6,14 @@ compatible: "nxp,imx-iuart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/serial/nxp,imx-uart.yaml b/dts/bindings/serial/nxp,imx-uart.yaml index 1f8c7defb8d8ce..7e19df0820aa5d 100644 --- a/dts/bindings/serial/nxp,imx-uart.yaml +++ b/dts/bindings/serial/nxp,imx-uart.yaml @@ -8,24 +8,24 @@ compatible: "nxp,imx-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - modem-mode: - type: int - required: true - description: Set the UART Port to modem mode 0 (dce) 64 (dte) + modem-mode: + type: int + required: true + description: Set the UART Port to modem mode 0 (dce) 64 (dte) - rdc: - type: int - required: true - description: Set the RDC permission for this peripheral + rdc: + type: int + required: true + description: Set the RDC permission for this peripheral - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/serial/nxp,kinetis-lpsci.yaml b/dts/bindings/serial/nxp,kinetis-lpsci.yaml index 0105da9efc5792..362038669cd64d 100644 --- a/dts/bindings/serial/nxp,kinetis-lpsci.yaml +++ b/dts/bindings/serial/nxp,kinetis-lpsci.yaml @@ -5,12 +5,12 @@ compatible: "nxp,kinetis-lpsci" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - type: phandles - required: true + pinctrl-0: + type: phandles + required: true diff --git a/dts/bindings/serial/nxp,kinetis-lpuart.yaml b/dts/bindings/serial/nxp,kinetis-lpuart.yaml index 2fd878d2350303..1ecc17663c54ee 100644 --- a/dts/bindings/serial/nxp,kinetis-lpuart.yaml +++ b/dts/bindings/serial/nxp,kinetis-lpuart.yaml @@ -5,28 +5,28 @@ compatible: "nxp,kinetis-lpuart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - nxp,loopback: - type: boolean - description: | - Enable loopback mode on LPUART peripheral. When present, RX pin is - disconnected, and transmitter output is internally connected to - the receiver input. + nxp,loopback: + type: boolean + description: | + Enable loopback mode on LPUART peripheral. When present, RX pin is + disconnected, and transmitter output is internally connected to + the receiver input. - nxp,rs485-mode: - type: boolean - required: false - description: | - Set to enable RTS signal, which can be used to enable the driver - of an external RS-485 transceiver. Note hw-flow-control should be - set to false. + nxp,rs485-mode: + type: boolean + required: false + description: | + Set to enable RTS signal, which can be used to enable the driver + of an external RS-485 transceiver. Note hw-flow-control should be + set to false. - nxp,rs485-de-active-low: - type: boolean - required: false - description: RTS polarity at RS485 mode. + nxp,rs485-de-active-low: + type: boolean + required: false + description: RTS polarity at RS485 mode. diff --git a/dts/bindings/serial/nxp,kinetis-uart.yaml b/dts/bindings/serial/nxp,kinetis-uart.yaml index 56483ecc4ff905..6a109b201433f4 100644 --- a/dts/bindings/serial/nxp,kinetis-uart.yaml +++ b/dts/bindings/serial/nxp,kinetis-uart.yaml @@ -5,15 +5,15 @@ compatible: "nxp,kinetis-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - pinctrl-0: - type: phandles - required: true + pinctrl-0: + type: phandles + required: true diff --git a/dts/bindings/serial/nxp,lpc11u6x-uart.yaml b/dts/bindings/serial/nxp,lpc11u6x-uart.yaml index ef48ca5092b007..989dc9ec687c76 100644 --- a/dts/bindings/serial/nxp,lpc11u6x-uart.yaml +++ b/dts/bindings/serial/nxp,lpc11u6x-uart.yaml @@ -5,17 +5,17 @@ compatible: "nxp,lpc11u6x-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/serial/nxp,s32-linflexd.yaml b/dts/bindings/serial/nxp,s32-linflexd.yaml index 570ce800f8db6e..0c4e014da8f8a3 100644 --- a/dts/bindings/serial/nxp,s32-linflexd.yaml +++ b/dts/bindings/serial/nxp,s32-linflexd.yaml @@ -8,14 +8,14 @@ compatible: "nxp,s32-linflexd" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/serial/openisa,rv32m1-lpuart.yaml b/dts/bindings/serial/openisa,rv32m1-lpuart.yaml index 4903e22c697249..47ed818004fed6 100644 --- a/dts/bindings/serial/openisa,rv32m1-lpuart.yaml +++ b/dts/bindings/serial/openisa,rv32m1-lpuart.yaml @@ -5,8 +5,8 @@ compatible: "openisa,rv32m1-lpuart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/quicklogic,usbserialport_s3b.yaml b/dts/bindings/serial/quicklogic,usbserialport_s3b.yaml index 2b2b375a5bbec8..55661083585178 100644 --- a/dts/bindings/serial/quicklogic,usbserialport_s3b.yaml +++ b/dts/bindings/serial/quicklogic,usbserialport_s3b.yaml @@ -8,5 +8,5 @@ compatible: "quicklogic,usbserialport-s3b" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/serial/raspberrypi,pico-uart.yaml b/dts/bindings/serial/raspberrypi,pico-uart.yaml index 6fbfcf2a75b2bc..e9c3ef68b5581c 100644 --- a/dts/bindings/serial/raspberrypi,pico-uart.yaml +++ b/dts/bindings/serial/raspberrypi,pico-uart.yaml @@ -5,8 +5,8 @@ compatible: "raspberrypi,pico-uart" include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/renesas,rcar-scif.yaml b/dts/bindings/serial/renesas,rcar-scif.yaml index b819052e109139..eca7323b25662a 100644 --- a/dts/bindings/serial/renesas,rcar-scif.yaml +++ b/dts/bindings/serial/renesas,rcar-scif.yaml @@ -8,8 +8,8 @@ compatible: "renesas,rcar-scif" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/serial/renesas,smartbond-uart.yaml b/dts/bindings/serial/renesas,smartbond-uart.yaml index 6b12398f4bff67..4b2a2b973c2d95 100644 --- a/dts/bindings/serial/renesas,smartbond-uart.yaml +++ b/dts/bindings/serial/renesas,smartbond-uart.yaml @@ -5,36 +5,36 @@ compatible: "renesas,smartbond-uart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - periph-clock-config: - type: int - description: Peripheral clock register configuration (COM domain) - required: true + periph-clock-config: + type: int + description: Peripheral clock register configuration (COM domain) + required: true - current-speed: - description: | - Initial baud rate setting for UART. Only a fixed set of baud - rates are selectable on these devices. - enum: - - 4800 - - 9600 - - 14400 - - 19200 - - 28800 - - 38400 - - 57600 - - 115200 - - 230400 - - 500000 - - 921600 - - 1000000 - - 2000000 + current-speed: + description: | + Initial baud rate setting for UART. Only a fixed set of baud + rates are selectable on these devices. + enum: + - 4800 + - 9600 + - 14400 + - 19200 + - 28800 + - 38400 + - 57600 + - 115200 + - 230400 + - 500000 + - 921600 + - 1000000 + - 2000000 - hw-flow-control-supported: - type: boolean - description: Set to indicate RTS/CTS flow control is supported. + hw-flow-control-supported: + type: boolean + description: Set to indicate RTS/CTS flow control is supported. diff --git a/dts/bindings/serial/segger,rtt-uart.yaml b/dts/bindings/serial/segger,rtt-uart.yaml index deb16301f71942..4d23776b0c0137 100644 --- a/dts/bindings/serial/segger,rtt-uart.yaml +++ b/dts/bindings/serial/segger,rtt-uart.yaml @@ -8,18 +8,18 @@ compatible: "segger,rtt-uart" include: uart-controller.yaml properties: - tx-buffer-size: - type: int - default: 1024 - description: | - Size of the RTT up buffer for transmission - Not used for RTT channel 0 as channel 0 is initialized at compile time, - see SEGGER_RTT_BUFFER_SIZE_UP. + tx-buffer-size: + type: int + default: 1024 + description: | + Size of the RTT up buffer for transmission + Not used for RTT channel 0 as channel 0 is initialized at compile time, + see SEGGER_RTT_BUFFER_SIZE_UP. - rx-buffer-size: - type: int - default: 16 - description: | - Size of the RTT down buffer for reception - Not used for RTT channel 0 as channel 0 is initialized at compile time, - see SEGGER_RTT_BUFFER_SIZE_DOWN. + rx-buffer-size: + type: int + default: 16 + description: | + Size of the RTT down buffer for reception + Not used for RTT channel 0 as channel 0 is initialized at compile time, + see SEGGER_RTT_BUFFER_SIZE_DOWN. diff --git a/dts/bindings/serial/sifive,uart0.yaml b/dts/bindings/serial/sifive,uart0.yaml index 6e235e6c004dd8..6fb3beb3ec73a9 100644 --- a/dts/bindings/serial/sifive,uart0.yaml +++ b/dts/bindings/serial/sifive,uart0.yaml @@ -8,8 +8,8 @@ compatible: "sifive,uart0" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/silabs,gecko-leuart.yaml b/dts/bindings/serial/silabs,gecko-leuart.yaml index bfdb6b9bd4098b..76e6d5970b7450 100644 --- a/dts/bindings/serial/silabs,gecko-leuart.yaml +++ b/dts/bindings/serial/silabs,gecko-leuart.yaml @@ -5,26 +5,26 @@ compatible: "silabs,gecko-leuart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - required: true - description: peripheral ID + peripheral-id: + type: int + required: true + description: peripheral ID - # Note: Not all SoC series support setting individual pin location. If this - # is a case all location-* properties need to have identical value. + # Note: Not all SoC series support setting individual pin location. If this + # is a case all location-* properties need to have identical value. - location-rx: - type: array - required: true - description: RX pin configuration defined as + location-rx: + type: array + required: true + description: RX pin configuration defined as - location-tx: - type: array - required: true - description: TX pin configuration defined as + location-tx: + type: array + required: true + description: TX pin configuration defined as diff --git a/dts/bindings/serial/silabs,gecko-uart.yaml b/dts/bindings/serial/silabs,gecko-uart.yaml index a03fd6b6665a6b..ae22286e72bd42 100644 --- a/dts/bindings/serial/silabs,gecko-uart.yaml +++ b/dts/bindings/serial/silabs,gecko-uart.yaml @@ -5,26 +5,26 @@ compatible: "silabs,gecko-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - required: true - description: peripheral ID + peripheral-id: + type: int + required: true + description: peripheral ID - # Note: Not all SoC series support setting individual pin location. If this - # is a case all location-* properties need to have identical value. + # Note: Not all SoC series support setting individual pin location. If this + # is a case all location-* properties need to have identical value. - location-rx: - type: array - required: true - description: RX pin configuration defined as + location-rx: + type: array + required: true + description: RX pin configuration defined as - location-tx: - type: array - required: true - description: TX pin configuration defined as + location-tx: + type: array + required: true + description: TX pin configuration defined as diff --git a/dts/bindings/serial/silabs,gecko-usart.yaml b/dts/bindings/serial/silabs,gecko-usart.yaml index 4f08ab88c19bce..2d2709f4d85e9c 100644 --- a/dts/bindings/serial/silabs,gecko-usart.yaml +++ b/dts/bindings/serial/silabs,gecko-usart.yaml @@ -5,32 +5,32 @@ compatible: "silabs,gecko-usart" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - required: false - description: peripheral ID + peripheral-id: + type: int + required: false + description: peripheral ID - # Note: Not all SoC series support setting individual pin location. If this - # is a case all location-* properties need to have identical value. + # Note: Not all SoC series support setting individual pin location. If this + # is a case all location-* properties need to have identical value. - location-rx: - type: array - description: RX pin configuration defined as + location-rx: + type: array + description: RX pin configuration defined as - location-tx: - type: array - description: TX pin configuration defined as + location-tx: + type: array + description: TX pin configuration defined as - location-rts: - type: array - description: RTS pin configuration defined as + location-rts: + type: array + description: RTS pin configuration defined as - location-cts: - type: array - description: CTS pin configuration defined as + location-cts: + type: array + description: CTS pin configuration defined as diff --git a/dts/bindings/serial/snps,nsim-uart.yaml b/dts/bindings/serial/snps,nsim-uart.yaml index f68d27cdcb71fe..d9e37eb534940b 100644 --- a/dts/bindings/serial/snps,nsim-uart.yaml +++ b/dts/bindings/serial/snps,nsim-uart.yaml @@ -8,5 +8,5 @@ compatible: "snps,nsim-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/serial/st,stm32-uart-base.yaml b/dts/bindings/serial/st,stm32-uart-base.yaml index f9db8c68e38281..fbe5973797a53b 100644 --- a/dts/bindings/serial/st,stm32-uart-base.yaml +++ b/dts/bindings/serial/st,stm32-uart-base.yaml @@ -7,54 +7,54 @@ description: STM32 UART-BASE include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml] properties: - reg: - required: true - - clocks: - required: true - - resets: - required: true - - interrupts: - required: true - - single-wire: - type: boolean - description: | - Enable the single wire half-duplex communication. - Using this mode, TX and RX lines are internally connected and - only TX pin is used afterwards and should be configured. - RX/TX conflicts must be handled on user side. - - tx-rx-swap: - type: boolean - description: - Swap the TX and RX pins. Used in case of a cross wired connection. - - tx-invert: - type: boolean - description: | - Invert the binary logic of tx pin. When enabled, physical logic levels are inverted and - we use 1=Low, 0=High instead of 1=High, 0=Low. - - rx-invert: - type: boolean - description: | - Invert the binary logic of rx pin. When enabled, physical logic levels are inverted and - we use 1=Low, 0=High instead of 1=High, 0=Low. - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - wakeup-line: - type: int - description: | - EXTI line number matching the device wakeup interrupt mask register. - This property is required on stm32 devices where the wakeup interrupt signal could be - configured masked at boot (sm32wl55 for instance), preventing the device to wakeup - the core from stop mode(s). - Valid range: 0 - 31 + reg: + required: true + + clocks: + required: true + + resets: + required: true + + interrupts: + required: true + + single-wire: + type: boolean + description: | + Enable the single wire half-duplex communication. + Using this mode, TX and RX lines are internally connected and + only TX pin is used afterwards and should be configured. + RX/TX conflicts must be handled on user side. + + tx-rx-swap: + type: boolean + description: + Swap the TX and RX pins. Used in case of a cross wired connection. + + tx-invert: + type: boolean + description: | + Invert the binary logic of tx pin. When enabled, physical logic levels are inverted and + we use 1=Low, 0=High instead of 1=High, 0=Low. + + rx-invert: + type: boolean + description: | + Invert the binary logic of rx pin. When enabled, physical logic levels are inverted and + we use 1=Low, 0=High instead of 1=High, 0=Low. + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + wakeup-line: + type: int + description: | + EXTI line number matching the device wakeup interrupt mask register. + This property is required on stm32 devices where the wakeup interrupt signal could be + configured masked at boot (sm32wl55 for instance), preventing the device to wakeup + the core from stop mode(s). + Valid range: 0 - 31 diff --git a/dts/bindings/serial/telink,b91-uart.yaml b/dts/bindings/serial/telink,b91-uart.yaml index fffb4f0e76f40f..b3affa70c68ee2 100644 --- a/dts/bindings/serial/telink,b91-uart.yaml +++ b/dts/bindings/serial/telink,b91-uart.yaml @@ -8,12 +8,12 @@ compatible: "telink,b91-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - type: phandles - required: true + pinctrl-0: + type: phandles + required: true diff --git a/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml b/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml index 855bfb5e3d2816..5b13c83934ccb9 100644 --- a/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml +++ b/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml @@ -8,8 +8,8 @@ compatible: "ti,cc13xx-cc26xx-uart" include: [uart-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/ti,cc32xx-uart.yaml b/dts/bindings/serial/ti,cc32xx-uart.yaml index e8b480b365bc9b..2ff828d81c8bf1 100644 --- a/dts/bindings/serial/ti,cc32xx-uart.yaml +++ b/dts/bindings/serial/ti,cc32xx-uart.yaml @@ -5,8 +5,8 @@ compatible: "ti,cc32xx-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/ti,msp432p4xx-uart.yaml b/dts/bindings/serial/ti,msp432p4xx-uart.yaml index 9d6213c85dbca1..436934522f9f54 100644 --- a/dts/bindings/serial/ti,msp432p4xx-uart.yaml +++ b/dts/bindings/serial/ti,msp432p4xx-uart.yaml @@ -5,8 +5,8 @@ compatible: "ti,msp432p4xx-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/ti,stellaris-uart.yaml b/dts/bindings/serial/ti,stellaris-uart.yaml index c5b12769082957..00ef0b4356075d 100644 --- a/dts/bindings/serial/ti,stellaris-uart.yaml +++ b/dts/bindings/serial/ti,stellaris-uart.yaml @@ -5,8 +5,8 @@ compatible: "ti,stellaris-uart" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/serial/uart-controller.yaml b/dts/bindings/serial/uart-controller.yaml index 48a0f98c242a23..f1fb68eba0dd08 100644 --- a/dts/bindings/serial/uart-controller.yaml +++ b/dts/bindings/serial/uart-controller.yaml @@ -5,21 +5,21 @@ include: base.yaml bus: uart properties: - clock-frequency: - type: int - description: Clock frequency information for UART operation - current-speed: - type: int - description: Initial baud rate setting for UART - hw-flow-control: - type: boolean - description: Set to enable RTS/CTS flow control at boot time - parity: - type: string - description: | - Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd - and 2 for even parity. Default to none if not specified. - enum: - - "none" - - "odd" - - "even" + clock-frequency: + type: int + description: Clock frequency information for UART operation + current-speed: + type: int + description: Initial baud rate setting for UART + hw-flow-control: + type: boolean + description: Set to enable RTS/CTS flow control at boot time + parity: + type: string + description: | + Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd + and 2 for even parity. Default to none if not specified. + enum: + - "none" + - "odd" + - "even" diff --git a/dts/bindings/serial/xlnx,xps-uartlite-1.00.a.yaml b/dts/bindings/serial/xlnx,xps-uartlite-1.00.a.yaml index 85516108fc182f..df1d9956791012 100644 --- a/dts/bindings/serial/xlnx,xps-uartlite-1.00.a.yaml +++ b/dts/bindings/serial/xlnx,xps-uartlite-1.00.a.yaml @@ -5,5 +5,5 @@ compatible: "xlnx,xps-uartlite-1.00.a" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/serial/xlnx,xuartps.yaml b/dts/bindings/serial/xlnx,xuartps.yaml index 19a7959330f632..f13efd386c46ec 100644 --- a/dts/bindings/serial/xlnx,xuartps.yaml +++ b/dts/bindings/serial/xlnx,xuartps.yaml @@ -5,5 +5,5 @@ compatible: "xlnx,xuartps" include: [uart-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/serial/zephyr,cdc-acm-uart.yaml b/dts/bindings/serial/zephyr,cdc-acm-uart.yaml index bbe999d2d2ddf1..73ee5adcd311a3 100644 --- a/dts/bindings/serial/zephyr,cdc-acm-uart.yaml +++ b/dts/bindings/serial/zephyr,cdc-acm-uart.yaml @@ -10,16 +10,16 @@ include: uart-controller.yaml on-bus: usb properties: - tx-fifo-size: - type: int - default: 1024 - description: | - Size of the virtual CDC ACM UART TX FIFO - required: false + tx-fifo-size: + type: int + default: 1024 + description: | + Size of the virtual CDC ACM UART TX FIFO + required: false - rx-fifo-size: - type: int - default: 1024 - description: | - Size of the virtual CDC ACM UART RX FIFO - required: false + rx-fifo-size: + type: int + default: 1024 + description: | + Size of the virtual CDC ACM UART RX FIFO + required: false diff --git a/dts/bindings/spi/andestech.atcspi200.yaml b/dts/bindings/spi/andestech.atcspi200.yaml index c0d5cd7dc6b4c3..edf0b2e8051348 100644 --- a/dts/bindings/spi/andestech.atcspi200.yaml +++ b/dts/bindings/spi/andestech.atcspi200.yaml @@ -12,5 +12,5 @@ compatible: "andestech,atcspi200" include: spi-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/spi/atmel,sam-spi.yaml b/dts/bindings/spi/atmel,sam-spi.yaml index 8b46d2d4925cde..fc5e3bc7e3a8f7 100644 --- a/dts/bindings/spi/atmel,sam-spi.yaml +++ b/dts/bindings/spi/atmel,sam-spi.yaml @@ -6,41 +6,41 @@ description: Atmel SAM SPI controller compatible: "atmel,sam-spi" include: - - name: spi-controller.yaml - - name: pinctrl-device.yaml + - name: spi-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true - - interrupts: - required: true - - peripheral-id: - type: int - description: peripheral ID - required: true - - loopback: - type: boolean - description: | - Connects TX to RX internally creating a loop back connection. Useful - for testing. - - dmas: - description: | - TX & RX dma specifiers. Each specifier will have a phandle - reference to the dma controller, the channel number, and peripheral - trigger source. The channel number is arbitrary but must not be - reused. The number of channels available is device dependent. - - For example dmas for TX and RX may look like - dmas = <&xdmac 1 DMA_PERID_SPI0_TX>, <&xdmac 2 DMA_PERID_SPI0_RX>; - - dma-names: - description: | - This should be "tx" and "rx" and should match the order given for - dmas. - - For example using the example dmas, an example dma-names would be - dma-names = "tx", "rx"; + reg: + required: true + + interrupts: + required: true + + peripheral-id: + type: int + description: peripheral ID + required: true + + loopback: + type: boolean + description: | + Connects TX to RX internally creating a loop back connection. Useful + for testing. + + dmas: + description: | + TX & RX dma specifiers. Each specifier will have a phandle + reference to the dma controller, the channel number, and peripheral + trigger source. The channel number is arbitrary but must not be + reused. The number of channels available is device dependent. + + For example dmas for TX and RX may look like + dmas = <&xdmac 1 DMA_PERID_SPI0_TX>, <&xdmac 2 DMA_PERID_SPI0_RX>; + + dma-names: + description: | + This should be "tx" and "rx" and should match the order given for + dmas. + + For example using the example dmas, an example dma-names would be + dma-names = "tx", "rx"; diff --git a/dts/bindings/spi/atmel,sam0-spi.yaml b/dts/bindings/spi/atmel,sam0-spi.yaml index 01be0f187272ad..8b1c79b8220864 100644 --- a/dts/bindings/spi/atmel,sam0-spi.yaml +++ b/dts/bindings/spi/atmel,sam0-spi.yaml @@ -6,42 +6,42 @@ description: Atmel SAM0 SERCOM SPI controller compatible: "atmel,sam0-spi" include: - - name: spi-controller.yaml - - name: pinctrl-device.yaml + - name: spi-controller.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - clock-names: - required: true + clock-names: + required: true - dipo: - type: int - required: true - description: Data In Pinout + dipo: + type: int + required: true + description: Data In Pinout - dopo: - type: int - required: true - description: Data Out Pinout + dopo: + type: int + required: true + description: Data Out Pinout - dmas: - description: | - Optional TX & RX dma specifiers. Each specifier will have a phandle - reference to the dmac controller, the channel number, and peripheral - trigger source. + dmas: + description: | + Optional TX & RX dma specifiers. Each specifier will have a phandle + reference to the dmac controller, the channel number, and peripheral + trigger source. - For example dmas for TX, RX on SERCOM3 - dmas = <&dmac 0 0xb>, <&dmac 1 0xa>; + For example dmas for TX, RX on SERCOM3 + dmas = <&dmac 0 0xb>, <&dmac 1 0xa>; - dma-names: - description: | - Required if the dmas property exists. This should be "tx" and "rx" - to match the dmas property. + dma-names: + description: | + Required if the dmas property exists. This should be "tx" and "rx" + to match the dmas property. - For example - dma-names = "tx", "rx"; + For example + dma-names = "tx", "rx"; diff --git a/dts/bindings/spi/cypress,psoc6-spi.yaml b/dts/bindings/spi/cypress,psoc6-spi.yaml index e496c20e2f7520..81a12f44ec5dbc 100644 --- a/dts/bindings/spi/cypress,psoc6-spi.yaml +++ b/dts/bindings/spi/cypress,psoc6-spi.yaml @@ -8,27 +8,27 @@ compatible: "cypress,psoc6-spi" include: spi-controller.yaml properties: - reg: - required: true - - interrupts: - required: true - - peripheral-id: - type: int - description: peripheral ID - required: true - - pinctrl-0: - type: phandles - description: | - Port pin configuration for the various SPI signals that includes - MISO, MOSI, SCK, and possibly various chip selects signals. We - expect that the phandles will reference pinctrl nodes. These - nodes will have a nodelabel that matches the Cypress SoC HAL defines - and be of the form p___. - - For example the SPI on PSoC-63 Pioneer Kit would be - pinctrl-0 = <&p12_0_spi6_mosi &p12_1_spi6_miso &p12_2_spi6_clk &p12_3_spi6_sel0>; - - required: true + reg: + required: true + + interrupts: + required: true + + peripheral-id: + type: int + description: peripheral ID + required: true + + pinctrl-0: + type: phandles + description: | + Port pin configuration for the various SPI signals that includes + MISO, MOSI, SCK, and possibly various chip selects signals. We + expect that the phandles will reference pinctrl nodes. These + nodes will have a nodelabel that matches the Cypress SoC HAL defines + and be of the form p___. + + For example the SPI on PSoC-63 Pioneer Kit would be + pinctrl-0 = <&p12_0_spi6_mosi &p12_1_spi6_miso &p12_2_spi6_clk &p12_3_spi6_sel0>; + + required: true diff --git a/dts/bindings/spi/espressif,esp32-spi.yaml b/dts/bindings/spi/espressif,esp32-spi.yaml index 09afe73c857839..85b0e43779e60f 100644 --- a/dts/bindings/spi/espressif,esp32-spi.yaml +++ b/dts/bindings/spi/espressif,esp32-spi.yaml @@ -5,62 +5,62 @@ compatible: "espressif,esp32-spi" include: [spi-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - half-duplex: - type: boolean - description: | - Enable half-duplex communication mode. + half-duplex: + type: boolean + description: | + Enable half-duplex communication mode. - Transmit data before receiving it, instead of simultaneously + Transmit data before receiving it, instead of simultaneously - dummy-comp: - type: boolean - description: Enable dummy SPI compensation cycles + dummy-comp: + type: boolean + description: Enable dummy SPI compensation cycles - sio: - type: boolean - description: | - Enable 3-wire mode + sio: + type: boolean + description: | + Enable 3-wire mode - Use MOSI for both sending and receiving data + Use MOSI for both sending and receiving data - dma-enabled: - type: boolean - description: Enable SPI DMA support + dma-enabled: + type: boolean + description: Enable SPI DMA support - dma-clk: - type: int - description: DMA clock source + dma-clk: + type: int + description: DMA clock source - dma-host: - type: int - description: DMA Host - 0 -> SPI2, 1 -> SPI3 + dma-host: + type: int + description: DMA Host - 0 -> SPI2, 1 -> SPI3 - clk-as-cs: - type: boolean - description: | - Support to toggle the CS while the clock toggles + clk-as-cs: + type: boolean + description: | + Support to toggle the CS while the clock toggles - Output clock on CS line if CS is active + Output clock on CS line if CS is active - positive-cs: - type: boolean - description: Make CS positive during a transaction instead of negative + positive-cs: + type: boolean + description: Make CS positive during a transaction instead of negative - use-iomux: - type: boolean - description: | - Some pins are allowed to bypass the GPIO Matrix and use the IO_MUX - routing mechanism instead, this avoids extra routing latency and makes - possible the use of operating frequencies higher than 20 MHz. + use-iomux: + type: boolean + description: | + Some pins are allowed to bypass the GPIO Matrix and use the IO_MUX + routing mechanism instead, this avoids extra routing latency and makes + possible the use of operating frequencies higher than 20 MHz. - Refer to SoC's Technical Reference Manual to check which pins are - allowed to use this routing path. + Refer to SoC's Technical Reference Manual to check which pins are + allowed to use this routing path. diff --git a/dts/bindings/spi/ite,it8xxx2-sspi.yaml b/dts/bindings/spi/ite,it8xxx2-sspi.yaml index 0653617b9f5e21..e214d8fdb798e3 100644 --- a/dts/bindings/spi/ite,it8xxx2-sspi.yaml +++ b/dts/bindings/spi/ite,it8xxx2-sspi.yaml @@ -8,8 +8,8 @@ compatible: "ite,it8xxx2-sspi" include: spi-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/spi/litex,spi.yaml b/dts/bindings/spi/litex,spi.yaml index 31c134b05e373c..522182034171d6 100644 --- a/dts/bindings/spi/litex,spi.yaml +++ b/dts/bindings/spi/litex,spi.yaml @@ -8,5 +8,5 @@ compatible: "litex,spi" include: spi-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/spi/microchip,mpfs-qspi.yaml b/dts/bindings/spi/microchip,mpfs-qspi.yaml index 167db019e96707..ab3c66809b3ed2 100644 --- a/dts/bindings/spi/microchip,mpfs-qspi.yaml +++ b/dts/bindings/spi/microchip,mpfs-qspi.yaml @@ -8,8 +8,8 @@ compatible: "microchip,mpfs-qspi" include: spi-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/spi/microchip,xec-qmspi.yaml b/dts/bindings/spi/microchip,xec-qmspi.yaml index 127969f3d2e5ad..11a5577a0c6d49 100644 --- a/dts/bindings/spi/microchip,xec-qmspi.yaml +++ b/dts/bindings/spi/microchip,xec-qmspi.yaml @@ -8,56 +8,56 @@ compatible: "microchip,xec-qmspi" include: [spi-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - port_sel: - type: int - required: true - description: SPI Port 0 or 1. - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - rxdma: - type: int - required: true - description: Receive DMA channel - - txdma: - type: int - required: true - description: Transmit DMA channel - - lines: - type: int - required: true - description: QMSPI lines 1, 2, or 4 - - chip_select: - type: int - required: true - description: Use QMSPI CS0# or CS1# - - dcsckon: - type: int - required: true - description: Delay in system clocks from CS# assertion to first clock edge - - dckcsoff: - type: int - required: true - description: Delay in system clocks from last clock edge to CS# de-assertion - - dldh: - type: int - required: true - description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP# - - dcsda: - type: int - required: true - description: Delay in system clocks from CS# de-assertion to CS# assertion + reg: + required: true + + port_sel: + type: int + required: true + description: SPI Port 0 or 1. + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + rxdma: + type: int + required: true + description: Receive DMA channel + + txdma: + type: int + required: true + description: Transmit DMA channel + + lines: + type: int + required: true + description: QMSPI lines 1, 2, or 4 + + chip_select: + type: int + required: true + description: Use QMSPI CS0# or CS1# + + dcsckon: + type: int + required: true + description: Delay in system clocks from CS# assertion to first clock edge + + dckcsoff: + type: int + required: true + description: Delay in system clocks from last clock edge to CS# de-assertion + + dldh: + type: int + required: true + description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP# + + dcsda: + type: int + required: true + description: Delay in system clocks from CS# de-assertion to CS# assertion diff --git a/dts/bindings/spi/microchip-xec-qmspi-v2.yaml b/dts/bindings/spi/microchip-xec-qmspi-v2.yaml index 2fddc1854598d7..940a6966e69acf 100644 --- a/dts/bindings/spi/microchip-xec-qmspi-v2.yaml +++ b/dts/bindings/spi/microchip-xec-qmspi-v2.yaml @@ -7,99 +7,99 @@ description: Microchip XEC QMSPI controller V2 include: [spi-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - girqs: - type: array - required: true - description: | - An array of integers encoding each interrupt signal connection. - This information includes the aggregated GIRQ number, GIRQ bit - position, aggregated GIRQ NVIC connection, and direct NVIC - connection of the GIRQ bit. - - pcrs: - type: array - required: true - description: | - A two entry integer array containing the QMSPI PCR sleep register - index and bit position. - - pinctrl-0: - required: true - - pinctrl-names: - required: true - - lines: - type: int - description: | - QMSPI data lines 1, 2, or 4. 1 data line is full-duplex - MOSI and MISO or half-duplex on MOSI only. Lines set to 2 - or 4 indicate dual or quad I/O modes. - Defaults to 1 for full duplex driver's support for full-duplex spi. - enum: - - 1 - - 2 - - 4 - - port-sel: - type: int - description: | - SPI Port 0, 1, or 2. Port 0 is the shared SPI, port 1 is - the private SPI, and port 2 is the internal SPI port for - chip configurations with an embedded SPI flash. Defaults - to port 0 (shared SPI port). - - chip-select: - type: int - description: | - Use QMSPI CS0# or CS1#. Port 0 supports both chip selects. - Ports 1 and 2 implement CS0# only. Defaults to CS0#. - - dcsckon: - type: int - description: | - Delay in QMSPI main clocks from CS# assertion to first clock edge. - If not present use hardware default value. Refer to chip documention - for QMSPI input clock frequency. - - dckcsoff: - type: int - description: | - Delay in QMSPI main clocks from last clock edge to CS# de-assertion. - If not presetn use hardware default value. Refer to chip documention - for QMSPI input clock frequency. - - dldh: - type: int - description: | - Delay in QMSPI main clocks from CS# de-assertion to driving HOLD# - and WP#. If not present use hardware default value. Refer to chip - documention for QMSPI input clock frequency. - - dcsda: - type: int - description: | - Delay in QMSPI main clocks from CS# de-assertion to CS# assertion. - If not present use hardware default value. Refer to chip documention - for QMSPI input clock frequency. - - cs1-freq: - type: int - description: | - Allows different frequencies for CS#0 and CS1# devices. This applies - to ports implementing CS1#. - - tctradj: - type: int - description: | - An optional signed 8-bit value for adjusting the QMSPI control signal - timing tap. - - tsckadj: - type: int - description: | - An optional signed 8-bit value for adjusting the QMSPI clock signal - timing tap. + reg: + required: true + + girqs: + type: array + required: true + description: | + An array of integers encoding each interrupt signal connection. + This information includes the aggregated GIRQ number, GIRQ bit + position, aggregated GIRQ NVIC connection, and direct NVIC + connection of the GIRQ bit. + + pcrs: + type: array + required: true + description: | + A two entry integer array containing the QMSPI PCR sleep register + index and bit position. + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + lines: + type: int + description: | + QMSPI data lines 1, 2, or 4. 1 data line is full-duplex + MOSI and MISO or half-duplex on MOSI only. Lines set to 2 + or 4 indicate dual or quad I/O modes. + Defaults to 1 for full duplex driver's support for full-duplex spi. + enum: + - 1 + - 2 + - 4 + + port-sel: + type: int + description: | + SPI Port 0, 1, or 2. Port 0 is the shared SPI, port 1 is + the private SPI, and port 2 is the internal SPI port for + chip configurations with an embedded SPI flash. Defaults + to port 0 (shared SPI port). + + chip-select: + type: int + description: | + Use QMSPI CS0# or CS1#. Port 0 supports both chip selects. + Ports 1 and 2 implement CS0# only. Defaults to CS0#. + + dcsckon: + type: int + description: | + Delay in QMSPI main clocks from CS# assertion to first clock edge. + If not present use hardware default value. Refer to chip documention + for QMSPI input clock frequency. + + dckcsoff: + type: int + description: | + Delay in QMSPI main clocks from last clock edge to CS# de-assertion. + If not presetn use hardware default value. Refer to chip documention + for QMSPI input clock frequency. + + dldh: + type: int + description: | + Delay in QMSPI main clocks from CS# de-assertion to driving HOLD# + and WP#. If not present use hardware default value. Refer to chip + documention for QMSPI input clock frequency. + + dcsda: + type: int + description: | + Delay in QMSPI main clocks from CS# de-assertion to CS# assertion. + If not present use hardware default value. Refer to chip documention + for QMSPI input clock frequency. + + cs1-freq: + type: int + description: | + Allows different frequencies for CS#0 and CS1# devices. This applies + to ports implementing CS1#. + + tctradj: + type: int + description: | + An optional signed 8-bit value for adjusting the QMSPI control signal + timing tap. + + tsckadj: + type: int + description: | + An optional signed 8-bit value for adjusting the QMSPI clock signal + timing tap. diff --git a/dts/bindings/spi/nordic,nrf-spi-common.yaml b/dts/bindings/spi/nordic,nrf-spi-common.yaml index 97adb41ffbf4d9..16a60292479fbf 100644 --- a/dts/bindings/spi/nordic,nrf-spi-common.yaml +++ b/dts/bindings/spi/nordic,nrf-spi-common.yaml @@ -6,62 +6,62 @@ include: [spi-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - max-frequency: - type: int - required: true - description: | - Maximum data rate the SPI peripheral can be driven at, in Hz. This - property must be set at SoC level DTS files. - - overrun-character: - type: int - default: 0xff - description: | - The overrun character (ORC) is used when all bytes from the TX buffer - are sent, but the transfer continues due to RX. Defaults to 0xff - (line high), the most common value used in SPI transfers. - - sck-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The SCK pin to use. - - For pins P0.0 through P0.31, use the pin number. For example, - to use P0.16 for SCK, set: - - sck-pin = <16>; - - For pins P1.0 through P1.31, add 32 to the pin number. For - example, to use P1.2 for SCK, set: - - sck-pin = <34>; /* 32 + 2 */ - - mosi-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The MOSI pin to use. The pin numbering scheme is the same as - the sck-pin property's. - - miso-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. - - The MISO pin to use. The pin numbering scheme is the same as - the sck-pin property's. + reg: + required: true + + interrupts: + required: true + + max-frequency: + type: int + required: true + description: | + Maximum data rate the SPI peripheral can be driven at, in Hz. This + property must be set at SoC level DTS files. + + overrun-character: + type: int + default: 0xff + description: | + The overrun character (ORC) is used when all bytes from the TX buffer + are sent, but the transfer continues due to RX. Defaults to 0xff + (line high), the most common value used in SPI transfers. + + sck-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The SCK pin to use. + + For pins P0.0 through P0.31, use the pin number. For example, + to use P0.16 for SCK, set: + + sck-pin = <16>; + + For pins P1.0 through P1.31, add 32 to the pin number. For + example, to use P1.2 for SCK, set: + + sck-pin = <34>; /* 32 + 2 */ + + mosi-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The MOSI pin to use. The pin numbering scheme is the same as + the sck-pin property's. + + miso-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. + + The MISO pin to use. The pin numbering scheme is the same as + the sck-pin property's. diff --git a/dts/bindings/spi/nordic,nrf-spi.yaml b/dts/bindings/spi/nordic,nrf-spi.yaml index efe9d0b94b177f..ae26e25ff4e9fd 100644 --- a/dts/bindings/spi/nordic,nrf-spi.yaml +++ b/dts/bindings/spi/nordic,nrf-spi.yaml @@ -8,10 +8,10 @@ compatible: "nordic,nrf-spi" include: nordic,nrf-spi-common.yaml properties: - miso-pull-up: - type: boolean - description: Enable pull-up on MISO line + miso-pull-up: + type: boolean + description: Enable pull-up on MISO line - miso-pull-down: - type: boolean - description: Enable pull-down on MISO line + miso-pull-down: + type: boolean + description: Enable pull-down on MISO line diff --git a/dts/bindings/spi/nordic,nrf-spim.yaml b/dts/bindings/spi/nordic,nrf-spim.yaml index 4514f9ab7ed54e..1a7087375d1483 100644 --- a/dts/bindings/spi/nordic,nrf-spim.yaml +++ b/dts/bindings/spi/nordic,nrf-spim.yaml @@ -8,40 +8,40 @@ compatible: "nordic,nrf-spim" include: ["nordic,nrf-spi-common.yaml", "memory-region.yaml"] properties: - miso-pull-up: - type: boolean - description: Enable pull-up on MISO line - - miso-pull-down: - type: boolean - description: Enable pull-down on MISO line - - anomaly-58-workaround: - type: boolean - description: | - Enables the workaround for the nRF52832 SoC SPIM PAN 58 anomaly. - Must be used in conjunction with - CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58=y - - rx-delay-supported: - type: boolean - description: | - Indicates if the SPIM instance has the capability of delaying MISO - sampling. This property needs to be defined at SoC level DTS files. - - rx-delay: - type: int - enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - description: | - Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge - of SCK (leading or trailing, depending on the CPHA setting used) until - the input serial data on MISO is actually sampled. This property does - not have any effect if the rx-delay-supported property is not set. + miso-pull-up: + type: boolean + description: Enable pull-up on MISO line + + miso-pull-down: + type: boolean + description: Enable pull-down on MISO line + + anomaly-58-workaround: + type: boolean + description: | + Enables the workaround for the nRF52832 SoC SPIM PAN 58 anomaly. + Must be used in conjunction with + CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58=y + + rx-delay-supported: + type: boolean + description: | + Indicates if the SPIM instance has the capability of delaying MISO + sampling. This property needs to be defined at SoC level DTS files. + + rx-delay: + type: int + enum: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + description: | + Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge + of SCK (leading or trailing, depending on the CPHA setting used) until + the input serial data on MISO is actually sampled. This property does + not have any effect if the rx-delay-supported property is not set. diff --git a/dts/bindings/spi/nordic,nrf-spis.yaml b/dts/bindings/spi/nordic,nrf-spis.yaml index 5ce3874ebc0539..3c68b522e3a782 100644 --- a/dts/bindings/spi/nordic,nrf-spis.yaml +++ b/dts/bindings/spi/nordic,nrf-spis.yaml @@ -8,19 +8,19 @@ compatible: "nordic,nrf-spis" include: nordic,nrf-spi-common.yaml properties: - csn-pin: - type: int - deprecated: true - description: | - IMPORTANT: This option will only be used if the new pin control driver - is not enabled. + csn-pin: + type: int + deprecated: true + description: | + IMPORTANT: This option will only be used if the new pin control driver + is not enabled. - The CSN pin to use. The pin numbering scheme is the same as - the sck-pin property's. + The CSN pin to use. The pin numbering scheme is the same as + the sck-pin property's. - def-char: - type: int - required: true - description: | - Default character. Character clocked out when the slave was not - provided with buffers and is ignoring the transaction. + def-char: + type: int + required: true + description: | + Default character. Character clocked out when the slave was not + provided with buffers and is ignoring the transaction. diff --git a/dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml b/dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml index 00d87dddad6472..6f3b900e435a20 100644 --- a/dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml +++ b/dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml @@ -8,7 +8,7 @@ compatible: "nuvoton,npcx-spi-fiu" include: [spi-controller.yaml] properties: - reg: - required: true - clocks: - required: true + reg: + required: true + clocks: + required: true diff --git a/dts/bindings/spi/nxp,imx-flexspi.yaml b/dts/bindings/spi/nxp,imx-flexspi.yaml index dd55b8b474016d..0cc29c680c5f7e 100644 --- a/dts/bindings/spi/nxp,imx-flexspi.yaml +++ b/dts/bindings/spi/nxp,imx-flexspi.yaml @@ -8,60 +8,60 @@ compatible: "nxp,imx-flexspi" include: [spi-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - ahb-bufferable: - type: boolean - description: | - Enable AHB bufferable write access by setting register field - AHBCR[BUFFERABLEEN]. + ahb-bufferable: + type: boolean + description: | + Enable AHB bufferable write access by setting register field + AHBCR[BUFFERABLEEN]. - ahb-cacheable: - type: boolean - description: | - Enable AHB cacheable read access by setting register field - AHBCR[CACHEABLEEN]. + ahb-cacheable: + type: boolean + description: | + Enable AHB cacheable read access by setting register field + AHBCR[CACHEABLEEN]. - ahb-prefetch: - type: boolean - description: | - Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN]. + ahb-prefetch: + type: boolean + description: | + Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN]. - ahb-read-addr-opt: - type: boolean - description: | - Remove burst start address alignment limitation by setting register - field AHBCR[READADDROPT]. + ahb-read-addr-opt: + type: boolean + description: | + Remove burst start address alignment limitation by setting register + field AHBCR[READADDROPT]. - combination-mode: - type: boolean - description: | - Combine port A and port B data pins to support octal mode access by - setting register field MCR0[COMBINATIONEN]. + combination-mode: + type: boolean + description: | + Combine port A and port B data pins to support octal mode access by + setting register field MCR0[COMBINATIONEN]. - sck-differential-clock: - type: boolean - description: | - Enable/disable SCKB pad use as SCKA differential clock output, - when enabled, Port B flash access is not available. + sck-differential-clock: + type: boolean + description: | + Enable/disable SCKB pad use as SCKA differential clock output, + when enabled, Port B flash access is not available. - rx-clock-source: - type: int - default: 0 - enum: - - 0 # Loopback internally - - 1 # Loopback from DQS pad - - 2 # Loopback from SCK pad - - 3 # External input from DQS pad - description: | - Source clock for flash read. See the RXCLKSRC field in register MCR0. - The default corresponds to the reset value of the register field. + rx-clock-source: + type: int + default: 0 + enum: + - 0 # Loopback internally + - 1 # Loopback from DQS pad + - 2 # Loopback from SCK pad + - 3 # External input from DQS pad + description: | + Source clock for flash read. See the RXCLKSRC field in register MCR0. + The default corresponds to the reset value of the register field. child-binding: - description: NXP FlexSPI port + description: NXP FlexSPI port - include: nxp,imx-flexspi-device.yaml + include: nxp,imx-flexspi-device.yaml diff --git a/dts/bindings/spi/nxp,imx-lpspi.yaml b/dts/bindings/spi/nxp,imx-lpspi.yaml index 567c27f84a2ffd..1a830d17bf1327 100644 --- a/dts/bindings/spi/nxp,imx-lpspi.yaml +++ b/dts/bindings/spi/nxp,imx-lpspi.yaml @@ -8,29 +8,29 @@ compatible: "nxp,imx-lpspi" include: ["spi-controller.yaml", "pinctrl-device.yaml"] properties: - reg: - required: true - - interrupts: - required: true - - clocks: - required: true - - pcs-sck-delay: - type: int - description: | - Delay in nanoseconds from the chip select assert to the first clock - edge. If not set, the minimum supported delay is used. - - sck-pcs-delay: - type: int - description: | - Delay in nanoseconds from the last clock edge to the chip select - deassert. If not set, the minimum supported delay is used. - - transfer-delay: - type: int - description: | - Delay in nanoseconds from the chip select deassert to the next chip - select assert. If not set, the minimum supported delay is used. + reg: + required: true + + interrupts: + required: true + + clocks: + required: true + + pcs-sck-delay: + type: int + description: | + Delay in nanoseconds from the chip select assert to the first clock + edge. If not set, the minimum supported delay is used. + + sck-pcs-delay: + type: int + description: | + Delay in nanoseconds from the last clock edge to the chip select + deassert. If not set, the minimum supported delay is used. + + transfer-delay: + type: int + description: | + Delay in nanoseconds from the chip select deassert to the next chip + select assert. If not set, the minimum supported delay is used. diff --git a/dts/bindings/spi/nxp,kinetis-dspi.yaml b/dts/bindings/spi/nxp,kinetis-dspi.yaml index 1dc137546051cc..8d01c74e04e511 100644 --- a/dts/bindings/spi/nxp,kinetis-dspi.yaml +++ b/dts/bindings/spi/nxp,kinetis-dspi.yaml @@ -8,77 +8,77 @@ compatible: "nxp,kinetis-dspi" include: ["spi-controller.yaml", "pinctrl-device.yaml"] properties: - reg: - required: true - - interrupts: - required: true - - clocks: - required: true - - pcs-sck-delay: - type: int - description: | - Delay in nanoseconds from the chip select assert to the first clock - edge. If not set, the minimum supported delay is used. - - sck-pcs-delay: - type: int - description: | - Delay in nanoseconds from the last clock edge to the chip select - deassert. If not set, the minimum supported delay is used. - - transfer-delay: - type: int - description: | - Delay in nanoseconds from the chip select deassert to the next chip - select assert. If not set, the minimum supported delay is used. - - pinctrl-0: - type: phandles - required: true - - nxp,rx-tx-chn-share: - type: boolean - description: If the edma channel shared with tx and rx - - ctar: - type: int - description: | - ctar register selection range form 0-1 for master mode, 0 for slave mode - - sample-point: - type: int - description: | - Controls when the DSPI master samples SIN in the Modified Transfer Format. - This field is valid only when the CPHA bit in the CTAR register is 0. - - continuous-sck: - type: boolean - description: | - continuous SCK enable. Note that the continuous SCK is only - supported for CPHA = 1. - - rx-fifo-overwrite: - type: boolean - description: | - receive FIFO overflow overwrite enable. If ROOE = 0, the incoming - data is ignored and the data from the transfer that generated the overflow - is also ignored. If ROOE = 1, the incoming data is shifted to the - shift register. - - modified-timing-format: - type: boolean - description: | - Enables a modified transfer format to be used if true. - - tx-fifo-size: - type: int - description: | - tx fifo size - - rx-fifo-size: - type: int - description: | - rx fifo size + reg: + required: true + + interrupts: + required: true + + clocks: + required: true + + pcs-sck-delay: + type: int + description: | + Delay in nanoseconds from the chip select assert to the first clock + edge. If not set, the minimum supported delay is used. + + sck-pcs-delay: + type: int + description: | + Delay in nanoseconds from the last clock edge to the chip select + deassert. If not set, the minimum supported delay is used. + + transfer-delay: + type: int + description: | + Delay in nanoseconds from the chip select deassert to the next chip + select assert. If not set, the minimum supported delay is used. + + pinctrl-0: + type: phandles + required: true + + nxp,rx-tx-chn-share: + type: boolean + description: If the edma channel shared with tx and rx + + ctar: + type: int + description: | + ctar register selection range form 0-1 for master mode, 0 for slave mode + + sample-point: + type: int + description: | + Controls when the DSPI master samples SIN in the Modified Transfer Format. + This field is valid only when the CPHA bit in the CTAR register is 0. + + continuous-sck: + type: boolean + description: | + continuous SCK enable. Note that the continuous SCK is only + supported for CPHA = 1. + + rx-fifo-overwrite: + type: boolean + description: | + receive FIFO overflow overwrite enable. If ROOE = 0, the incoming + data is ignored and the data from the transfer that generated the overflow + is also ignored. If ROOE = 1, the incoming data is shifted to the + shift register. + + modified-timing-format: + type: boolean + description: | + Enables a modified transfer format to be used if true. + + tx-fifo-size: + type: int + description: | + tx fifo size + + rx-fifo-size: + type: int + description: | + rx fifo size diff --git a/dts/bindings/spi/nxp,lpc-spi.yaml b/dts/bindings/spi/nxp,lpc-spi.yaml index 7307410fb2e0e1..a29aec892f8b4c 100644 --- a/dts/bindings/spi/nxp,lpc-spi.yaml +++ b/dts/bindings/spi/nxp,lpc-spi.yaml @@ -8,33 +8,33 @@ compatible: "nxp,lpc-spi" include: [spi-controller.yaml, "nxp,lpc-flexcomm.yaml"] properties: - pre-delay: - type: int - description: | - Delay in nanoseconds inserted between chip select assert to the first - clock edge. If not set, no additional delay is inserted. - - post-delay: - type: int - description: | - Delay in nanoseconds inserted between the last clock edge to the chip - select deassert. If not set, no additional delay is inserted. - - frame-delay: - type: int - description: | - Delay in nanoseconds inserted between data frames when chip select is - asserted and the EOF flag is set. If not set, no additional delay is - inserted. - - transfer-delay: - type: int - description: | - Delay in nanoseconds inserted between transfers when chip select is - deasserted. If not set, no additional delay is inserted. - - def-char: - type: int - description: | - Default character clocked out when the TX buffer pointer is NULL. - Applies to SPI master and slave configurations. + pre-delay: + type: int + description: | + Delay in nanoseconds inserted between chip select assert to the first + clock edge. If not set, no additional delay is inserted. + + post-delay: + type: int + description: | + Delay in nanoseconds inserted between the last clock edge to the chip + select deassert. If not set, no additional delay is inserted. + + frame-delay: + type: int + description: | + Delay in nanoseconds inserted between data frames when chip select is + asserted and the EOF flag is set. If not set, no additional delay is + inserted. + + transfer-delay: + type: int + description: | + Delay in nanoseconds inserted between transfers when chip select is + deasserted. If not set, no additional delay is inserted. + + def-char: + type: int + description: | + Default character clocked out when the TX buffer pointer is NULL. + Applies to SPI master and slave configurations. diff --git a/dts/bindings/spi/opencores,spi-simple.yaml b/dts/bindings/spi/opencores,spi-simple.yaml index 2e896b15efc2cc..f63cb863fa2355 100644 --- a/dts/bindings/spi/opencores,spi-simple.yaml +++ b/dts/bindings/spi/opencores,spi-simple.yaml @@ -8,5 +8,5 @@ compatible: "opencores,spi-simple" include: spi-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/spi/openisa,rv32m1-lpspi.yaml b/dts/bindings/spi/openisa,rv32m1-lpspi.yaml index 85d4a594bb7fca..3bf8381cb79703 100644 --- a/dts/bindings/spi/openisa,rv32m1-lpspi.yaml +++ b/dts/bindings/spi/openisa,rv32m1-lpspi.yaml @@ -8,8 +8,8 @@ compatible: "openisa,rv32m1-lpspi" include: [spi-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/spi/sifive,spi0.yaml b/dts/bindings/spi/sifive,spi0.yaml index c8d72de314b745..68a3fd14d237d8 100644 --- a/dts/bindings/spi/sifive,spi0.yaml +++ b/dts/bindings/spi/sifive,spi0.yaml @@ -13,5 +13,5 @@ compatible: "sifive,spi0" include: [spi-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/spi/silabs,gecko-spi-usart.yaml b/dts/bindings/spi/silabs,gecko-spi-usart.yaml index 820ce9677dcec0..6e6c624424af0d 100644 --- a/dts/bindings/spi/silabs,gecko-spi-usart.yaml +++ b/dts/bindings/spi/silabs,gecko-spi-usart.yaml @@ -5,31 +5,31 @@ compatible: "silabs,gecko-spi-usart" include: spi-controller.yaml properties: - reg: - required: true - - interrupts: - required: true - - peripheral-id: - type: int - required: true - description: peripheral ID - - # Note: Not all SoC series support setting individual pin location. If this - # is a case all location-* properties need to have identical value. - - location-rx: - type: array - required: true - description: RX pin configuration defined as - - location-tx: - type: array - required: true - description: TX pin configuration defined as - - location-clk: - type: array - required: true - description: CLK pin configuration defined as + reg: + required: true + + interrupts: + required: true + + peripheral-id: + type: int + required: true + description: peripheral ID + + # Note: Not all SoC series support setting individual pin location. If this + # is a case all location-* properties need to have identical value. + + location-rx: + type: array + required: true + description: RX pin configuration defined as + + location-tx: + type: array + required: true + description: TX pin configuration defined as + + location-clk: + type: array + required: true + description: CLK pin configuration defined as diff --git a/dts/bindings/spi/snps,designware-spi.yaml b/dts/bindings/spi/snps,designware-spi.yaml index 1b9e640a4e4b01..b75fe4ae905441 100644 --- a/dts/bindings/spi/snps,designware-spi.yaml +++ b/dts/bindings/spi/snps,designware-spi.yaml @@ -8,8 +8,8 @@ compatible: "snps,designware-spi" include: spi-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/spi/spi-controller.yaml b/dts/bindings/spi/spi-controller.yaml index f3e808295412a8..22e112fcd97061 100644 --- a/dts/bindings/spi/spi-controller.yaml +++ b/dts/bindings/spi/spi-controller.yaml @@ -8,52 +8,52 @@ include: base.yaml bus: spi properties: - clock-frequency: - type: int - description: | - Clock frequency the SPI peripheral is being driven at, in Hz. - "#address-cells": - required: true - const: 1 - "#size-cells": - required: true - const: 0 - cs-gpios: - type: phandle-array - description: | - An array of chip select GPIOs to use. Each element - in the array specifies a GPIO. The index in the array - corresponds to the child node that the CS gpio controls. - - Example: - - spi@... { - cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>, - ...; - - spi-device@0 { - reg = <0>; - ... - }; - spi-device@1 { - reg = <1>; - ... - }; - ... - }; - - The child node "spi-device@0" specifies a SPI device with - chip select controller gpio0, pin 23, and devicetree - GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO - controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional - devices can be configured in the same way. - - If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe - choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if - intervening hardware inverts the signal to the peripheral device or - the line itself is active high. - - If this property is not defined, no chip select GPIOs are set. - SPI controllers with dedicated CS pins do not need to define - the cs-gpios property. + clock-frequency: + type: int + description: | + Clock frequency the SPI peripheral is being driven at, in Hz. + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 0 + cs-gpios: + type: phandle-array + description: | + An array of chip select GPIOs to use. Each element + in the array specifies a GPIO. The index in the array + corresponds to the child node that the CS gpio controls. + + Example: + + spi@... { + cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>, + ...; + + spi-device@0 { + reg = <0>; + ... + }; + spi-device@1 { + reg = <1>; + ... + }; + ... + }; + + The child node "spi-device@0" specifies a SPI device with + chip select controller gpio0, pin 23, and devicetree + GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO + controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional + devices can be configured in the same way. + + If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe + choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if + intervening hardware inverts the signal to the peripheral device or + the line itself is active high. + + If this property is not defined, no chip select GPIOs are set. + SPI controllers with dedicated CS pins do not need to define + the cs-gpios property. diff --git a/dts/bindings/spi/spi-device.yaml b/dts/bindings/spi/spi-device.yaml index 827d5ad3bc02cd..f820863b30d4a5 100644 --- a/dts/bindings/spi/spi-device.yaml +++ b/dts/bindings/spi/spi-device.yaml @@ -8,35 +8,35 @@ include: [base.yaml, power.yaml] on-bus: spi properties: - reg: - required: true - spi-max-frequency: - type: int - required: true - description: Maximum clock frequency of device's SPI interface in Hz - duplex: - type: int - default: 0 - description: | - Duplex mode, full or half. By default it's always full duplex thus 0 - as this is, by far, the most common mode. - Use the macros not the actual enum value, here is the concordance - list (see dt-bindings/spi/spi.h) - 0 SPI_FULL_DUPLEX - 2048 SPI_HALF_DUPLEX - enum: - - 0 - - 2048 - frame-format: - type: int - default: 0 - description: | - Motorola or TI frame format. By default it's always Motorola's, - thus 0 as this is, by far, the most common format. - Use the macros not the actual enum value, here is the concordance - list (see dt-bindings/spi/spi.h) - 0 SPI_FRAME_FORMAT_MOTOROLA - 32768 SPI_FRAME_FORMAT_TI - enum: - - 0 - - 32768 + reg: + required: true + spi-max-frequency: + type: int + required: true + description: Maximum clock frequency of device's SPI interface in Hz + duplex: + type: int + default: 0 + description: | + Duplex mode, full or half. By default it's always full duplex thus 0 + as this is, by far, the most common mode. + Use the macros not the actual enum value, here is the concordance + list (see dt-bindings/spi/spi.h) + 0 SPI_FULL_DUPLEX + 2048 SPI_HALF_DUPLEX + enum: + - 0 + - 2048 + frame-format: + type: int + default: 0 + description: | + Motorola or TI frame format. By default it's always Motorola's, + thus 0 as this is, by far, the most common format. + Use the macros not the actual enum value, here is the concordance + list (see dt-bindings/spi/spi.h) + 0 SPI_FRAME_FORMAT_MOTOROLA + 32768 SPI_FRAME_FORMAT_TI + enum: + - 0 + - 32768 diff --git a/dts/bindings/spi/st,stm32-spi-common.yaml b/dts/bindings/spi/st,stm32-spi-common.yaml index 42b7462d6a5120..ce9ac0b2c6fc53 100644 --- a/dts/bindings/spi/st,stm32-spi-common.yaml +++ b/dts/bindings/spi/st,stm32-spi-common.yaml @@ -6,14 +6,14 @@ include: [spi-controller.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/spi/st,stm32-spi-subghz.yaml b/dts/bindings/spi/st,stm32-spi-subghz.yaml index 5e43f6f03de54d..b5b51e676a37ab 100644 --- a/dts/bindings/spi/st,stm32-spi-subghz.yaml +++ b/dts/bindings/spi/st,stm32-spi-subghz.yaml @@ -12,9 +12,9 @@ include: - pinctrl-names properties: - use-subghzspi-nss: - type: boolean - required: true - description: | - Control the SUBGHZPI NSS line using the PWR HAL functions. This is for - the special purpose SUBGHZSPI interface found in the STM32WL series. + use-subghzspi-nss: + type: boolean + required: true + description: | + Control the SUBGHZPI NSS line using the PWR HAL functions. This is for + the special purpose SUBGHZSPI interface found in the STM32WL series. diff --git a/dts/bindings/spi/telink,b91-spi.yaml b/dts/bindings/spi/telink,b91-spi.yaml index 4ce3dd4c299e6f..e49e660d41d1c9 100644 --- a/dts/bindings/spi/telink,b91-spi.yaml +++ b/dts/bindings/spi/telink,b91-spi.yaml @@ -8,47 +8,47 @@ include: spi-controller.yaml compatible: "telink,b91-spi" properties: - reg: - required: true - - peripheral-id: - type: string - required: true - enum: - - "PSPI_MODULE" - - "HSPI_MODULE" - - pinctrl-0: - type: phandles - required: true - - cs0-pin: - type: string - required: true - enum: - - "0" - - "PSPI_CSN_PC4" - - "PSPI_CSN_PC0" - - "PSPI_CSN_PD0" - - "HSPI_CSN_PA1" - - "HSPI_CSN_PB6" - - cs1-pin: - type: string - enum: - - "0" - - "PSPI_CSN_PC4" - - "PSPI_CSN_PC0" - - "PSPI_CSN_PD0" - - "HSPI_CSN_PA1" - - "HSPI_CSN_PB6" - - cs2-pin: - type: string - enum: - - "0" - - "PSPI_CSN_PC4" - - "PSPI_CSN_PC0" - - "PSPI_CSN_PD0" - - "HSPI_CSN_PA1" - - "HSPI_CSN_PB6" + reg: + required: true + + peripheral-id: + type: string + required: true + enum: + - "PSPI_MODULE" + - "HSPI_MODULE" + + pinctrl-0: + type: phandles + required: true + + cs0-pin: + type: string + required: true + enum: + - "0" + - "PSPI_CSN_PC4" + - "PSPI_CSN_PC0" + - "PSPI_CSN_PD0" + - "HSPI_CSN_PA1" + - "HSPI_CSN_PB6" + + cs1-pin: + type: string + enum: + - "0" + - "PSPI_CSN_PC4" + - "PSPI_CSN_PC0" + - "PSPI_CSN_PD0" + - "HSPI_CSN_PA1" + - "HSPI_CSN_PB6" + + cs2-pin: + type: string + enum: + - "0" + - "PSPI_CSN_PC4" + - "PSPI_CSN_PC0" + - "PSPI_CSN_PD0" + - "HSPI_CSN_PA1" + - "HSPI_CSN_PB6" diff --git a/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml b/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml index bea40c725e0d91..b614c7f4336d67 100644 --- a/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml +++ b/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml @@ -8,5 +8,5 @@ compatible: "ti,cc13xx-cc26xx-spi" include: [spi-controller.yaml, pinctrl-device.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml b/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml index d1b54083bb7de0..05127fe69822f4 100644 --- a/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml +++ b/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml @@ -11,29 +11,29 @@ include: spi-controller.yaml # https://github.com/Xilinx/device-tree-xlnx properties: - reg: - required: true - - interrupts: - required: true - - xlnx,num-ss-bits: - type: int - required: true - enum: - - 1 - - 2 - - 3 - - 4 - description: | - Number of slave select bits implemented - - xlnx,num-transfer-bits: - type: int - required: true - enum: - - 8 - - 16 - - 32 - description: | - Number of bits per transfer + reg: + required: true + + interrupts: + required: true + + xlnx,num-ss-bits: + type: int + required: true + enum: + - 1 + - 2 + - 3 + - 4 + description: | + Number of slave select bits implemented + + xlnx,num-transfer-bits: + type: int + required: true + enum: + - 8 + - 16 + - 32 + description: | + Number of bits per transfer diff --git a/dts/bindings/spi/zephyr,spi-bitbang.yaml b/dts/bindings/spi/zephyr,spi-bitbang.yaml index 972e02855cb421..27d5bac27cc055 100644 --- a/dts/bindings/spi/zephyr,spi-bitbang.yaml +++ b/dts/bindings/spi/zephyr,spi-bitbang.yaml @@ -8,20 +8,20 @@ compatible: "zephyr,spi-bitbang" include: spi-controller.yaml properties: - clk-gpios: - type: phandle-array - required: true - description: | - Clock gpio info + clk-gpios: + type: phandle-array + required: true + description: | + Clock gpio info - mosi-gpios: - type: phandle-array - description: | - MOSI gpio info. Output pin for Master Out Slave In. - If this is not provided then the driver will transmit 0s + mosi-gpios: + type: phandle-array + description: | + MOSI gpio info. Output pin for Master Out Slave In. + If this is not provided then the driver will transmit 0s - miso-gpios: - type: phandle-array - description: | - MISO gpio info. Input pin for Master In Slave Out. - If this is not provided the driver will read 0s + miso-gpios: + type: phandle-array + description: | + MISO gpio info. Input pin for Master In Slave Out. + If this is not provided the driver will read 0s diff --git a/dts/bindings/spi/zephyr,spi-emul-controller.yaml b/dts/bindings/spi/zephyr,spi-emul-controller.yaml index df4574245079a3..557531903f655d 100644 --- a/dts/bindings/spi/zephyr,spi-emul-controller.yaml +++ b/dts/bindings/spi/zephyr,spi-emul-controller.yaml @@ -8,5 +8,5 @@ compatible: "zephyr,spi-emul-controller" include: spi-controller.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/sram/mmio-sram.yaml b/dts/bindings/sram/mmio-sram.yaml index 1df524f3009028..e1255e185c4d6b 100644 --- a/dts/bindings/sram/mmio-sram.yaml +++ b/dts/bindings/sram/mmio-sram.yaml @@ -8,5 +8,5 @@ compatible: "mmio-sram" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/sram/sifive,dtim0.yaml b/dts/bindings/sram/sifive,dtim0.yaml index d67bef034a1a92..5b7f8260eefdab 100644 --- a/dts/bindings/sram/sifive,dtim0.yaml +++ b/dts/bindings/sram/sifive,dtim0.yaml @@ -8,5 +8,5 @@ compatible: "sifive,dtim0" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/syscon/syscon.yaml b/dts/bindings/syscon/syscon.yaml index 6c5cf1e9e65a81..92f255a61d4871 100644 --- a/dts/bindings/syscon/syscon.yaml +++ b/dts/bindings/syscon/syscon.yaml @@ -8,8 +8,8 @@ compatible: "syscon" include: base.yaml properties: - reg: - required: true - reg-io-width: - type: int - description: The width of the registers in the syscon region in bytes. Default is 4 bytes. + reg: + required: true + reg-io-width: + type: int + description: The width of the registers in the syscon region in bytes. Default is 4 bytes. diff --git a/dts/bindings/tach/ite,it8xxx2-tach.yaml b/dts/bindings/tach/ite,it8xxx2-tach.yaml index 94f77fb5cbe33b..d00d4eca3c4296 100644 --- a/dts/bindings/tach/ite,it8xxx2-tach.yaml +++ b/dts/bindings/tach/ite,it8xxx2-tach.yaml @@ -8,34 +8,34 @@ compatible: "ite,it8xxx2-tach" include: [tach.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - dvs-bit: - type: int - required: true - description: tachometer data valid bit of tswctlr register - - chsel-bit: - type: int - required: true - description: tachometer data valid status bit of tswctlr register - - channel: - type: int - required: true - enum: - - 0 - - 1 - description: 0 = TACH_CHANNEL_A, 1 = TACH_CHANNEL_B - - pulses-per-round: - type: int - required: true - description: number of pulses per round of tachometer's input - - pinctrl-0: - required: true - - pinctrl-names: - required: true + reg: + required: true + + dvs-bit: + type: int + required: true + description: tachometer data valid bit of tswctlr register + + chsel-bit: + type: int + required: true + description: tachometer data valid status bit of tswctlr register + + channel: + type: int + required: true + enum: + - 0 + - 1 + description: 0 = TACH_CHANNEL_A, 1 = TACH_CHANNEL_B + + pulses-per-round: + type: int + required: true + description: number of pulses per round of tachometer's input + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/tach/microchip,xec-tach.yaml b/dts/bindings/tach/microchip,xec-tach.yaml index f451f2d79762ce..bf9170d2049605 100644 --- a/dts/bindings/tach/microchip,xec-tach.yaml +++ b/dts/bindings/tach/microchip,xec-tach.yaml @@ -8,26 +8,26 @@ compatible: "microchip,xec-tach" include: [tach.yaml, pinctrl-device.yaml] properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - type: int - const: 0 - reg: - required: true + "#address-cells": + required: true + const: 1 + "#size-cells": + type: int + const: 0 + reg: + required: true - interrupts: - required: true + interrupts: + required: true - girqs: - type: array - required: true - description: | - Array of GIRQ and bit position pairs for each interrupt - signal the block generates. + girqs: + type: array + required: true + description: | + Array of GIRQ and bit position pairs for each interrupt + signal the block generates. - pcrs: - type: array - required: true - description: PCR sleep register index and bit position + pcrs: + type: array + required: true + description: PCR sleep register index and bit position diff --git a/dts/bindings/tach/nuvoton,npcx-tach.yaml b/dts/bindings/tach/nuvoton,npcx-tach.yaml index af67b657432f25..8a2c35ae004485 100644 --- a/dts/bindings/tach/nuvoton,npcx-tach.yaml +++ b/dts/bindings/tach/nuvoton,npcx-tach.yaml @@ -8,22 +8,22 @@ compatible: "nuvoton,npcx-tach" include: [tach.yaml, pinctrl-device.yaml] properties: - reg: - required: true - clocks: - required: true - pinctrl-0: - required: true - pinctrl-names: - required: true - sample-clk: - type: int - description: | - sampling clock frequency of tachometer. Please notice that it must be - fixed to 32768 if bus in clocks property is NPCX_CLOCK_BUS_LFCLK. - port: - type: int - description: selected port of tachometer (port-A is 0 and port-B is 1) - pulses-per-round: - type: int - description: number of pulses (holes) per round of tachometer's input (encoder) + reg: + required: true + clocks: + required: true + pinctrl-0: + required: true + pinctrl-names: + required: true + sample-clk: + type: int + description: | + sampling clock frequency of tachometer. Please notice that it must be + fixed to 32768 if bus in clocks property is NPCX_CLOCK_BUS_LFCLK. + port: + type: int + description: selected port of tachometer (port-A is 0 and port-B is 1) + pulses-per-round: + type: int + description: number of pulses (holes) per round of tachometer's input (encoder) diff --git a/dts/bindings/tcpc/st,stm32-ucpd.yaml b/dts/bindings/tcpc/st,stm32-ucpd.yaml index e1d0226ef8c266..0e0104a5e891ad 100644 --- a/dts/bindings/tcpc/st,stm32-ucpd.yaml +++ b/dts/bindings/tcpc/st,stm32-ucpd.yaml @@ -10,61 +10,61 @@ compatible: "st,stm32-ucpd" include: [base.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - interrupts: - required: true + interrupts: + required: true - psc-ucpdclk: - default: 2 - type: int - enum: - - 1 - - 2 - - 4 - - 8 - - 16 - - 32 - - 64 - - 128 - description: | - Determines the division ratio of a kernel clock pre-scaler - producing UCPD peripheral clock (ucpd_clk). It is recommended - to use the pre-scaler so as to set the ucpd_clk frequency in - the range from 6 to 9 MHz. + psc-ucpdclk: + default: 2 + type: int + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + - 32 + - 64 + - 128 + description: | + Determines the division ratio of a kernel clock pre-scaler + producing UCPD peripheral clock (ucpd_clk). It is recommended + to use the pre-scaler so as to set the ucpd_clk frequency in + the range from 6 to 9 MHz. - ifrgap: - type: int - default: 17 - description: | - Determines the division ratio of a ucpd_clk divider producing - inter-frame gap timer clock (tInterFrameGap). - The division ratio 15 is to apply for Tx clock at the USB PD 2.0 - specification nominal value. - Valid range: 2 - 32 + ifrgap: + type: int + default: 17 + description: | + Determines the division ratio of a ucpd_clk divider producing + inter-frame gap timer clock (tInterFrameGap). + The division ratio 15 is to apply for Tx clock at the USB PD 2.0 + specification nominal value. + Valid range: 2 - 32 - transwin: - type: int - default: 8 - description: | - Determines the division ratio of a hbit_clk divider producing - tTransitionWindow interval. - Valid range: 2 - 32 + transwin: + type: int + default: 8 + description: | + Determines the division ratio of a hbit_clk divider producing + tTransitionWindow interval. + Valid range: 2 - 32 - hbitclkdiv: - type: int - default: 14 - description: | - Determines the division ratio of a ucpd_clk divider producing - half-bit clock (hbit_clk) - Valid range: 1 - 64 + hbitclkdiv: + type: int + default: 14 + description: | + Determines the division ratio of a ucpd_clk divider producing + half-bit clock (hbit_clk) + Valid range: 1 - 64 - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true diff --git a/dts/bindings/test/vnd,adc-temp-sensor.yaml b/dts/bindings/test/vnd,adc-temp-sensor.yaml index 25741fde27ea22..8bc33a7373afb6 100644 --- a/dts/bindings/test/vnd,adc-temp-sensor.yaml +++ b/dts/bindings/test/vnd,adc-temp-sensor.yaml @@ -8,22 +8,22 @@ compatible: "vnd,adc-temp-sensor" include: [base.yaml, reset-device.yaml] properties: - io-channels: - required: true - description: ADC conversion channels + io-channels: + required: true + description: ADC conversion channels - io-channel-names: - required: true - description: conversion channel names + io-channel-names: + required: true + description: conversion channel names - clocks: - required: true + clocks: + required: true - pinctrl-0: - type: phandles + pinctrl-0: + type: phandles - pinctrl-1: - type: phandles + pinctrl-1: + type: phandles - pinctrl-2: - type: phandles + pinctrl-2: + type: phandles diff --git a/dts/bindings/test/vnd,adc.yaml b/dts/bindings/test/vnd,adc.yaml index f7b274ea3b95c1..c0de525dea3867 100644 --- a/dts/bindings/test/vnd,adc.yaml +++ b/dts/bindings/test/vnd,adc.yaml @@ -8,8 +8,8 @@ compatible: "vnd,adc" include: adc-controller.yaml properties: - "#io-channel-cells": - const: 1 + "#io-channel-cells": + const: 1 io-channel-cells: - - input + - input diff --git a/dts/bindings/test/vnd,busy-sim.yaml b/dts/bindings/test/vnd,busy-sim.yaml index 5c6f5a54eb4870..aa839af7264a59 100644 --- a/dts/bindings/test/vnd,busy-sim.yaml +++ b/dts/bindings/test/vnd,busy-sim.yaml @@ -7,13 +7,13 @@ description: | compatible: "vnd,busy-sim" properties: - counter: - type: phandle - required: true - description: | - Counter device used for generating intervals. + counter: + type: phandle + required: true + description: | + Counter device used for generating intervals. - active-gpios: - type: phandle-array - description: | - Debug pin is set to active state when cpu load is active. + active-gpios: + type: phandle-array + description: | + Debug pin is set to active state when cpu load is active. diff --git a/dts/bindings/test/vnd,clock.yaml b/dts/bindings/test/vnd,clock.yaml index 325c0a2b08c9cc..e4e2f7c8e2eda2 100644 --- a/dts/bindings/test/vnd,clock.yaml +++ b/dts/bindings/test/vnd,clock.yaml @@ -8,8 +8,8 @@ compatible: "vnd,clock" include: [clock-controller.yaml, base.yaml] properties: - "#clock-cells": - const: 2 + "#clock-cells": + const: 2 clock-cells: - bus diff --git a/dts/bindings/test/vnd,dma.yaml b/dts/bindings/test/vnd,dma.yaml index 3c1dfa4ebbce41..88fb066ef4e960 100644 --- a/dts/bindings/test/vnd,dma.yaml +++ b/dts/bindings/test/vnd,dma.yaml @@ -8,14 +8,14 @@ compatible: "vnd,dma" include: dma-controller.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - "#dma-cells": - const: 2 + "#dma-cells": + const: 2 dma-cells: - channel diff --git a/dts/bindings/test/vnd,gpio-device.yaml b/dts/bindings/test/vnd,gpio-device.yaml index c2fee5220ca52a..27c9f1997da069 100644 --- a/dts/bindings/test/vnd,gpio-device.yaml +++ b/dts/bindings/test/vnd,gpio-device.yaml @@ -12,14 +12,14 @@ include: - label properties: - reg: - required: true + reg: + required: true - label: - type: string + label: + type: string - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/test/vnd,gpio-expander-common.yaml b/dts/bindings/test/vnd,gpio-expander-common.yaml index 041cafb90d33c7..f664076e61d4e0 100644 --- a/dts/bindings/test/vnd,gpio-expander-common.yaml +++ b/dts/bindings/test/vnd,gpio-expander-common.yaml @@ -6,11 +6,11 @@ description: Test GPIO node include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/test/vnd,gpio-expander-i2c.yaml b/dts/bindings/test/vnd,gpio-expander-i2c.yaml index ef6bb1eb9a83f0..8eb291905c6e87 100644 --- a/dts/bindings/test/vnd,gpio-expander-i2c.yaml +++ b/dts/bindings/test/vnd,gpio-expander-i2c.yaml @@ -14,5 +14,5 @@ include: - label properties: - label: - type: string + label: + type: string diff --git a/dts/bindings/test/vnd,gpio-one-cell.yaml b/dts/bindings/test/vnd,gpio-one-cell.yaml index 6865a3b19c3b50..83f6987ec2706d 100644 --- a/dts/bindings/test/vnd,gpio-one-cell.yaml +++ b/dts/bindings/test/vnd,gpio-one-cell.yaml @@ -8,11 +8,11 @@ compatible: "vnd,gpio-one-cell" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 1 + "#gpio-cells": + const: 1 gpio-cells: - pin diff --git a/dts/bindings/test/vnd,gpio.yaml b/dts/bindings/test/vnd,gpio.yaml index 6c00cf37a1789c..c5702bcfa9dbb8 100644 --- a/dts/bindings/test/vnd,gpio.yaml +++ b/dts/bindings/test/vnd,gpio.yaml @@ -8,11 +8,11 @@ compatible: "vnd,gpio" include: [gpio-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#gpio-cells": - const: 2 + "#gpio-cells": + const: 2 gpio-cells: - pin diff --git a/dts/bindings/test/vnd,i2c-device.yaml b/dts/bindings/test/vnd,i2c-device.yaml index 1245fd304bdf1d..54ad45d54d197e 100644 --- a/dts/bindings/test/vnd,i2c-device.yaml +++ b/dts/bindings/test/vnd,i2c-device.yaml @@ -11,5 +11,5 @@ include: - label properties: - label: - type: string + label: + type: string diff --git a/dts/bindings/test/vnd,i2c.yaml b/dts/bindings/test/vnd,i2c.yaml index fe8a0a39946b38..3287e46211552a 100644 --- a/dts/bindings/test/vnd,i2c.yaml +++ b/dts/bindings/test/vnd,i2c.yaml @@ -11,5 +11,5 @@ include: - label properties: - label: - type: string + label: + type: string diff --git a/dts/bindings/test/vnd,i3c-device.yaml b/dts/bindings/test/vnd,i3c-device.yaml index c4f95ff682b135..b4a28a647204db 100644 --- a/dts/bindings/test/vnd,i3c-device.yaml +++ b/dts/bindings/test/vnd,i3c-device.yaml @@ -13,5 +13,5 @@ include: - label properties: - label: - type: string + label: + type: string diff --git a/dts/bindings/test/vnd,i3c-i2c-device.yaml b/dts/bindings/test/vnd,i3c-i2c-device.yaml index d1aada11994393..4b5be74740f18d 100644 --- a/dts/bindings/test/vnd,i3c-i2c-device.yaml +++ b/dts/bindings/test/vnd,i3c-i2c-device.yaml @@ -13,5 +13,5 @@ include: - label properties: - label: - type: string + label: + type: string diff --git a/dts/bindings/test/vnd,i3c.yaml b/dts/bindings/test/vnd,i3c.yaml index 936ef101319b6d..fde41c5e259819 100644 --- a/dts/bindings/test/vnd,i3c.yaml +++ b/dts/bindings/test/vnd,i3c.yaml @@ -13,5 +13,5 @@ include: - label properties: - label: - type: string + label: + type: string diff --git a/dts/bindings/test/vnd,intc.yaml b/dts/bindings/test/vnd,intc.yaml index ace8f796cbac69..4294d41c373e6b 100644 --- a/dts/bindings/test/vnd,intc.yaml +++ b/dts/bindings/test/vnd,intc.yaml @@ -8,11 +8,11 @@ compatible: "vnd,intc" include: [interrupt-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#interrupt-cells": - const: 2 + "#interrupt-cells": + const: 2 interrupt-cells: - irq diff --git a/dts/bindings/test/vnd,interrupt-holder.yaml b/dts/bindings/test/vnd,interrupt-holder.yaml index 38d611ad4d35d8..68f18970562639 100644 --- a/dts/bindings/test/vnd,interrupt-holder.yaml +++ b/dts/bindings/test/vnd,interrupt-holder.yaml @@ -8,8 +8,8 @@ compatible: "vnd,interrupt-holder" include: [base.yaml] properties: - interrupts: - required: true + interrupts: + required: true - interrupt-names: - required: true + interrupt-names: + required: true diff --git a/dts/bindings/test/vnd,pwm.yaml b/dts/bindings/test/vnd,pwm.yaml index 0a6b11f57208ca..92fb691b2db244 100644 --- a/dts/bindings/test/vnd,pwm.yaml +++ b/dts/bindings/test/vnd,pwm.yaml @@ -8,11 +8,11 @@ compatible: "vnd,pwm" include: [pwm-controller.yaml, base.yaml] properties: - reg: - required: true + reg: + required: true - "#pwm-cells": - const: 3 + "#pwm-cells": + const: 3 pwm-cells: - channel diff --git a/dts/bindings/test/vnd,reg-holder.yaml b/dts/bindings/test/vnd,reg-holder.yaml index c2685a49e3eb15..a73dcace74c3bd 100644 --- a/dts/bindings/test/vnd,reg-holder.yaml +++ b/dts/bindings/test/vnd,reg-holder.yaml @@ -8,11 +8,11 @@ compatible: "vnd,reg-holder" include: [base.yaml] properties: - reg: - required: true + reg: + required: true - reg-names: - required: true + reg-names: + required: true - misc-prop: - type: int + misc-prop: + type: int diff --git a/dts/bindings/test/vnd,reset.yaml b/dts/bindings/test/vnd,reset.yaml index dd0d27d9f90449..6951357cc60c5e 100644 --- a/dts/bindings/test/vnd,reset.yaml +++ b/dts/bindings/test/vnd,reset.yaml @@ -8,11 +8,11 @@ compatible: "vnd,reset" include: [base.yaml, reset-controller.yaml] properties: - reg-width: - type: int - description: Register width - "#reset-cells": - const: 1 + reg-width: + type: int + description: Register width + "#reset-cells": + const: 1 reset-cells: - id diff --git a/dts/bindings/test/vnd,serial.yaml b/dts/bindings/test/vnd,serial.yaml index 116529fb1a2a9f..dc2327b4827991 100644 --- a/dts/bindings/test/vnd,serial.yaml +++ b/dts/bindings/test/vnd,serial.yaml @@ -5,12 +5,12 @@ compatible: "vnd,serial" include: uart-controller.yaml properties: - reg: - required: true + reg: + required: true - baud-rate: - type: int + baud-rate: + type: int - buffer-size: - type: int - description: "Size of buffer to capture output data or to queue input data." + buffer-size: + type: int + description: "Size of buffer to capture output data or to queue input data." diff --git a/dts/bindings/test/vnd,spi-device.yaml b/dts/bindings/test/vnd,spi-device.yaml index 8b823c58f00113..91c6ef5cb6491f 100644 --- a/dts/bindings/test/vnd,spi-device.yaml +++ b/dts/bindings/test/vnd,spi-device.yaml @@ -11,5 +11,5 @@ include: - label properties: - label: - type: string + label: + type: string diff --git a/dts/bindings/test/vnd,spi.yaml b/dts/bindings/test/vnd,spi.yaml index 587326c885750d..afa76a57a98858 100644 --- a/dts/bindings/test/vnd,spi.yaml +++ b/dts/bindings/test/vnd,spi.yaml @@ -11,5 +11,5 @@ include: - label properties: - label: - type: string + label: + type: string diff --git a/dts/bindings/timer/andestech,atcpit100.yaml b/dts/bindings/timer/andestech,atcpit100.yaml index bcd7fc25f7ce42..46bc9da525b8c4 100644 --- a/dts/bindings/timer/andestech,atcpit100.yaml +++ b/dts/bindings/timer/andestech,atcpit100.yaml @@ -12,32 +12,32 @@ compatible: "andestech,atcpit100" include: base.yaml properties: - reg: - required: true - - interrupts: - required: true - - clock-frequency: - type: int - required: true - description: channel clock source - - prescaler: - type: int - default: 1 - description: | - The prescaler value defines the counter frequency - (clock-frequency/prescaler) in atcpit100 counter driver, the prescaler - value could be in range [1 .. clock-frequency] and 1 means no prescaler - for the PIT clock-frequency. - - Defaults to 1 to use the PIT clock-frequency as the counter frequency. - - Setting the prescaler value if the system overhead is close to or - larger than a counter tick period, reducing the counter frequency to - avoid imprecise counter value. - - For example, andes_v5_ae350 platform takes about 200 ~ 300 PIT - clock cycles for counter interface, setting prescaler value to 600 in - this case. + reg: + required: true + + interrupts: + required: true + + clock-frequency: + type: int + required: true + description: channel clock source + + prescaler: + type: int + default: 1 + description: | + The prescaler value defines the counter frequency + (clock-frequency/prescaler) in atcpit100 counter driver, the prescaler + value could be in range [1 .. clock-frequency] and 1 means no prescaler + for the PIT clock-frequency. + + Defaults to 1 to use the PIT clock-frequency as the counter frequency. + + Setting the prescaler value if the system overhead is close to or + larger than a counter tick period, reducing the counter frequency to + avoid imprecise counter value. + + For example, andes_v5_ae350 platform takes about 200 ~ 300 PIT + clock cycles for counter interface, setting prescaler value to 600 in + this case. diff --git a/dts/bindings/timer/andestech,machine-timer.yaml b/dts/bindings/timer/andestech,machine-timer.yaml index 88621d7f1e8f18..9a1c4e891d32da 100644 --- a/dts/bindings/timer/andestech,machine-timer.yaml +++ b/dts/bindings/timer/andestech,machine-timer.yaml @@ -12,8 +12,8 @@ compatible: "andestech,machine-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts-extended: - required: true + interrupts-extended: + required: true diff --git a/dts/bindings/timer/arm,armv6m-systick.yaml b/dts/bindings/timer/arm,armv6m-systick.yaml index 838bb210c37bb2..607d1d40c8a5b1 100644 --- a/dts/bindings/timer/arm,armv6m-systick.yaml +++ b/dts/bindings/timer/arm,armv6m-systick.yaml @@ -8,5 +8,5 @@ compatible: "arm,armv6m-systick" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/timer/arm,armv7m-systick.yaml b/dts/bindings/timer/arm,armv7m-systick.yaml index 215b3c40d55e65..ae9bc5a8d6c723 100644 --- a/dts/bindings/timer/arm,armv7m-systick.yaml +++ b/dts/bindings/timer/arm,armv7m-systick.yaml @@ -8,5 +8,5 @@ compatible: "arm,armv7m-systick" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/timer/arm,armv8-timer.yaml b/dts/bindings/timer/arm,armv8-timer.yaml index eef75b6c97aeae..6b8400c4616e49 100644 --- a/dts/bindings/timer/arm,armv8-timer.yaml +++ b/dts/bindings/timer/arm,armv8-timer.yaml @@ -5,5 +5,5 @@ compatible: "arm,armv8-timer" include: base.yaml properties: - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/arm,armv8.1m-systick.yaml b/dts/bindings/timer/arm,armv8.1m-systick.yaml index 847394e97c954d..a1616236057bb3 100644 --- a/dts/bindings/timer/arm,armv8.1m-systick.yaml +++ b/dts/bindings/timer/arm,armv8.1m-systick.yaml @@ -8,5 +8,5 @@ compatible: "arm,armv8.1m-systick" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/timer/arm,armv8m-systick.yaml b/dts/bindings/timer/arm,armv8m-systick.yaml index 7c7467cca9757a..50215a8a902489 100644 --- a/dts/bindings/timer/arm,armv8m-systick.yaml +++ b/dts/bindings/timer/arm,armv8m-systick.yaml @@ -8,5 +8,5 @@ compatible: "arm,armv8m-systick" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/timer/arm,cmsdk-dtimer.yaml b/dts/bindings/timer/arm,cmsdk-dtimer.yaml index 360964f5abe2fb..219f43bf0ebb1c 100644 --- a/dts/bindings/timer/arm,cmsdk-dtimer.yaml +++ b/dts/bindings/timer/arm,cmsdk-dtimer.yaml @@ -5,8 +5,8 @@ compatible: "arm,cmsdk-dtimer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/arm,cmsdk-timer.yaml b/dts/bindings/timer/arm,cmsdk-timer.yaml index f6f5bcab9bc74a..8b86d2a85a15a8 100644 --- a/dts/bindings/timer/arm,cmsdk-timer.yaml +++ b/dts/bindings/timer/arm,cmsdk-timer.yaml @@ -5,8 +5,8 @@ compatible: "arm,cmsdk-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/atmel,sam-tc.yaml b/dts/bindings/timer/atmel,sam-tc.yaml index 1e348439a7cf02..a0b87cffcaab24 100644 --- a/dts/bindings/timer/atmel,sam-tc.yaml +++ b/dts/bindings/timer/atmel,sam-tc.yaml @@ -5,57 +5,57 @@ description: Atmel SAM Timer Counter (TC) node compatible: "atmel,sam-tc" include: - - name: base.yaml - - name: pinctrl-device.yaml + - name: base.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true - - interrupts: - required: true - - peripheral-id: - type: array - description: peripheral ID - required: true - - channel: - type: int - description: | - Timer / Counter channel to use, channel 0 is the default. - Valid range: 0 - 2 - - clk: - type: int - description: | - Clock source selection as defined by TCCLKS bit-field of TC_CMR - register. Consult the datasheet for the details. - - nodivclk: - type: boolean - description: | - If set to true the `clk` property is ignored. Instead the TC module is - driven directly via MCLK. Only supported on sam4e, same70, same70b, - samv71, samv71b SoC series. - - reg-cmr: - type: int - description: | - Alternate value of the CMR (Channel Mode Register) register. - If specified this value will be written to the register during driver - instance initialization instead of the default. It can be used to - configure the timer / counter in the custom mode. Together with other - properties like channel-num, pinctrl-0 this allows e.g. to configure - the driver to count events generated on the TIOA, TIOB signal connected - to the external pin. - - reg-rc: - type: int - description: | - Register C compare/match value. RC can be used as compare/match unit - for an specific timer unit. Their use depends on how timer channel - is configured,see reg-cmr. It can be used as trigger for both input - capture or counter mode, or even as event source. The RC register - behavior is SoC dependent. For more information and use cases, - check SoC datasheet and application notes. + reg: + required: true + + interrupts: + required: true + + peripheral-id: + type: array + description: peripheral ID + required: true + + channel: + type: int + description: | + Timer / Counter channel to use, channel 0 is the default. + Valid range: 0 - 2 + + clk: + type: int + description: | + Clock source selection as defined by TCCLKS bit-field of TC_CMR + register. Consult the datasheet for the details. + + nodivclk: + type: boolean + description: | + If set to true the `clk` property is ignored. Instead the TC module is + driven directly via MCLK. Only supported on sam4e, same70, same70b, + samv71, samv71b SoC series. + + reg-cmr: + type: int + description: | + Alternate value of the CMR (Channel Mode Register) register. + If specified this value will be written to the register during driver + instance initialization instead of the default. It can be used to + configure the timer / counter in the custom mode. Together with other + properties like channel-num, pinctrl-0 this allows e.g. to configure + the driver to count events generated on the TIOA, TIOB signal connected + to the external pin. + + reg-rc: + type: int + description: | + Register C compare/match value. RC can be used as compare/match unit + for an specific timer unit. Their use depends on how timer channel + is configured,see reg-cmr. It can be used as trigger for both input + capture or counter mode, or even as event source. The RC register + behavior is SoC dependent. For more information and use cases, + check SoC datasheet and application notes. diff --git a/dts/bindings/timer/atmel,sam0-tc32.yaml b/dts/bindings/timer/atmel,sam0-tc32.yaml index 44137fa36f6f6f..c523e6e4104989 100644 --- a/dts/bindings/timer/atmel,sam0-tc32.yaml +++ b/dts/bindings/timer/atmel,sam0-tc32.yaml @@ -6,8 +6,8 @@ description: Atmel SAM0 basic timer counter (TC) operating in 32-bit wide mode compatible: "atmel,sam0-tc32" include: - - name: base.yaml - - name: pinctrl-device.yaml + - name: base.yaml + - name: pinctrl-device.yaml properties: reg: diff --git a/dts/bindings/timer/espressif,esp32-systimer.yaml b/dts/bindings/timer/espressif,esp32-systimer.yaml index 02302b5299fcbe..bc08df7e39c532 100644 --- a/dts/bindings/timer/espressif,esp32-systimer.yaml +++ b/dts/bindings/timer/espressif,esp32-systimer.yaml @@ -8,8 +8,8 @@ compatible: "espressif,esp32-systimer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/gaisler,gptimer.yaml b/dts/bindings/timer/gaisler,gptimer.yaml index 09a8c9deaf9b82..156e35a9da9a06 100644 --- a/dts/bindings/timer/gaisler,gptimer.yaml +++ b/dts/bindings/timer/gaisler,gptimer.yaml @@ -5,8 +5,8 @@ compatible: "gaisler,gptimer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/intel,adsp-timer.yaml b/dts/bindings/timer/intel,adsp-timer.yaml index 592cec7123eed3..c03ab2be448926 100644 --- a/dts/bindings/timer/intel,adsp-timer.yaml +++ b/dts/bindings/timer/intel,adsp-timer.yaml @@ -8,8 +8,8 @@ compatible: "intel,adsp-timer" include: base.yaml properties: - syscon: - type: phandle - required: true - description: | - phandle to syscon node. + syscon: + type: phandle + required: true + description: | + phandle to syscon node. diff --git a/dts/bindings/timer/intel,hpet.yaml b/dts/bindings/timer/intel,hpet.yaml index 614e1c29d7c10b..b293f2e7e482a9 100644 --- a/dts/bindings/timer/intel,hpet.yaml +++ b/dts/bindings/timer/intel,hpet.yaml @@ -8,12 +8,12 @@ compatible: "intel,hpet" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - no-legacy-irq: - type: boolean - description: Do not set legacy IRQ bit + no-legacy-irq: + type: boolean + description: Do not set legacy IRQ bit diff --git a/dts/bindings/timer/ite,it8xxx2-timer.yaml b/dts/bindings/timer/ite,it8xxx2-timer.yaml index 9244256654d12e..ee6665ace18cd9 100644 --- a/dts/bindings/timer/ite,it8xxx2-timer.yaml +++ b/dts/bindings/timer/ite,it8xxx2-timer.yaml @@ -8,8 +8,8 @@ compatible: "ite,it8xxx2-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/litex,timer0.yaml b/dts/bindings/timer/litex,timer0.yaml index e892d69d4da7a4..69f88d6369734c 100644 --- a/dts/bindings/timer/litex,timer0.yaml +++ b/dts/bindings/timer/litex,timer0.yaml @@ -8,8 +8,8 @@ compatible: "litex,timer0" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/microchip,xec-rtos-timer.yaml b/dts/bindings/timer/microchip,xec-rtos-timer.yaml index 8e0c813c92153d..7099bca798a9db 100644 --- a/dts/bindings/timer/microchip,xec-rtos-timer.yaml +++ b/dts/bindings/timer/microchip,xec-rtos-timer.yaml @@ -8,13 +8,13 @@ compatible: "microchip,xec-rtos-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - girqs: - type: array - required: true - description: Array of GIRQ numbers [8:26] and bit positions [0:31]. + girqs: + type: array + required: true + description: Array of GIRQ numbers [8:26] and bit positions [0:31]. diff --git a/dts/bindings/timer/neorv32-machine-timer.yaml b/dts/bindings/timer/neorv32-machine-timer.yaml index 9bd8331ad6bca1..4c72679f6a589d 100644 --- a/dts/bindings/timer/neorv32-machine-timer.yaml +++ b/dts/bindings/timer/neorv32-machine-timer.yaml @@ -12,8 +12,8 @@ compatible: "neorv32-machine-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/nordic,nrf-timer.yaml b/dts/bindings/timer/nordic,nrf-timer.yaml index b0ec306f65eb41..bc09e1bc8f2a87 100644 --- a/dts/bindings/timer/nordic,nrf-timer.yaml +++ b/dts/bindings/timer/nordic,nrf-timer.yaml @@ -8,18 +8,18 @@ compatible: "nordic,nrf-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - cc-num: - type: int - required: true - description: Number of capture/compare (CC) registers available + cc-num: + type: int + required: true + description: Number of capture/compare (CC) registers available - interrupts: - required: true + interrupts: + required: true - prescaler: - type: int - required: true - description: Prescaler value determines frequency (16MHz/2^prescaler) + prescaler: + type: int + required: true + description: Prescaler value determines frequency (16MHz/2^prescaler) diff --git a/dts/bindings/timer/nuclei,systimer.yaml b/dts/bindings/timer/nuclei,systimer.yaml index 12ee6da9d5b3d2..cee9e2bc9e7812 100644 --- a/dts/bindings/timer/nuclei,systimer.yaml +++ b/dts/bindings/timer/nuclei,systimer.yaml @@ -12,37 +12,37 @@ compatible: "nuclei,systimer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clk-divider: - type: int - description: | - clk-divider specifies the division ratio to the CPU frequency that - clock used by the system timer. - This property supports the case that the system timer and CPU use - different clock sources. - This configuration is used sometimes for such as low power consumption. + clk-divider: + type: int + description: | + clk-divider specifies the division ratio to the CPU frequency that + clock used by the system timer. + This property supports the case that the system timer and CPU use + different clock sources. + This configuration is used sometimes for such as low power consumption. - For example, the CPU clock frequency is 108MHz, and the system timer - uses 27MHz, which is the CPU clock divided by 4. - In this case, the CPU clock frequency is defined in the CPU node - as follows + For example, the CPU clock frequency is 108MHz, and the system timer + uses 27MHz, which is the CPU clock divided by 4. + In this case, the CPU clock frequency is defined in the CPU node + as follows - clock-frequency = <108000000>; + clock-frequency = <108000000>; - This property takes exponent of the power of 2. - The relationship with the frequency division ratio is as - following equation. + This property takes exponent of the power of 2. + The relationship with the frequency division ratio is as + following equation. - division_ratio = 2^n - n = log_2(division_ratio) + division_ratio = 2^n + n = log_2(division_ratio) - Setting clk-divider to 2 specifies the system timer uses the clock - that CPU clock frequency divided by (2^2=)4, or 27MHz. + Setting clk-divider to 2 specifies the system timer uses the clock + that CPU clock frequency divided by (2^2=)4, or 27MHz. - Devision ratio constants can be found in the - dt-bindings/timer/nuclei-systimer.h header file. + Devision ratio constants can be found in the + dt-bindings/timer/nuclei-systimer.h header file. diff --git a/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml b/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml index c34bfb1eccb2ef..4e538507727c63 100644 --- a/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml +++ b/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml @@ -8,8 +8,8 @@ compatible: "nuvoton,npcx-itim-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/nxp,gpt-hw-timer.yaml b/dts/bindings/timer/nxp,gpt-hw-timer.yaml index 5e9437e20b8fae..e54196cae92356 100644 --- a/dts/bindings/timer/nxp,gpt-hw-timer.yaml +++ b/dts/bindings/timer/nxp,gpt-hw-timer.yaml @@ -8,8 +8,8 @@ compatible: "nxp,gpt-hw-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/nxp,imx-gpt.yaml b/dts/bindings/timer/nxp,imx-gpt.yaml index 4ee5ae97d6860c..31396093097489 100644 --- a/dts/bindings/timer/nxp,imx-gpt.yaml +++ b/dts/bindings/timer/nxp,imx-gpt.yaml @@ -8,13 +8,13 @@ compatible: "nxp,imx-gpt" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - gptfreq: - type: int - required: true - description: gpt frequences + gptfreq: + type: int + required: true + description: gpt frequences diff --git a/dts/bindings/timer/nxp,lpc-ctimer.yaml b/dts/bindings/timer/nxp,lpc-ctimer.yaml index a1700d86ae17bb..936c1d1978ce13 100644 --- a/dts/bindings/timer/nxp,lpc-ctimer.yaml +++ b/dts/bindings/timer/nxp,lpc-ctimer.yaml @@ -8,28 +8,28 @@ compatible: "nxp,lpc-ctimer" include: base.yaml properties: - reg: - required: true - - interrupts: - required: true - - clk-source: - type: int - required: true - description: clock to use - - mode: - type: int - required: true - description: timer mode - - input: - type: int - required: true - description: input channel - - prescale: - type: int - required: true - description: prescale value + reg: + required: true + + interrupts: + required: true + + clk-source: + type: int + required: true + description: clock to use + + mode: + type: int + required: true + description: timer mode + + input: + type: int + required: true + description: input channel + + prescale: + type: int + required: true + description: prescale value diff --git a/dts/bindings/timer/nxp,os-timer.yaml b/dts/bindings/timer/nxp,os-timer.yaml index db1e9c9a12743b..649bce77c5efd3 100644 --- a/dts/bindings/timer/nxp,os-timer.yaml +++ b/dts/bindings/timer/nxp,os-timer.yaml @@ -8,8 +8,8 @@ compatible: "nxp,os-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/openisa,rv32m1-lptmr.yaml b/dts/bindings/timer/openisa,rv32m1-lptmr.yaml index 89855258455890..28b50bfa873d23 100644 --- a/dts/bindings/timer/openisa,rv32m1-lptmr.yaml +++ b/dts/bindings/timer/openisa,rv32m1-lptmr.yaml @@ -5,8 +5,8 @@ compatible: "openisa,rv32m1-lptmr" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/renesas,rcar-cmt.yaml b/dts/bindings/timer/renesas,rcar-cmt.yaml index 94b395004f4fb2..734d00d5e44c1f 100644 --- a/dts/bindings/timer/renesas,rcar-cmt.yaml +++ b/dts/bindings/timer/renesas,rcar-cmt.yaml @@ -5,16 +5,16 @@ compatible: "renesas,rcar-cmt" include: base.yaml properties: - reg: - required: true + reg: + required: true - clock-frequency: - type: int - required: true - description: Clock frequency information for Timer operation + clock-frequency: + type: int + required: true + description: Clock frequency information for Timer operation - clocks: - required: true + clocks: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/sifive,clint0.yaml b/dts/bindings/timer/sifive,clint0.yaml index 5c2b194ec8f2d3..608b17b1a4f7b9 100644 --- a/dts/bindings/timer/sifive,clint0.yaml +++ b/dts/bindings/timer/sifive,clint0.yaml @@ -9,4 +9,4 @@ include: base.yaml properties: reg: - required: true + required: true diff --git a/dts/bindings/timer/silabs,gecko-timer.yaml b/dts/bindings/timer/silabs,gecko-timer.yaml index 90abcbdde30c62..7953ae2bf1c4db 100644 --- a/dts/bindings/timer/silabs,gecko-timer.yaml +++ b/dts/bindings/timer/silabs,gecko-timer.yaml @@ -8,5 +8,5 @@ compatible: "silabs,gecko-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/timer/st,stm32-lptim.yaml b/dts/bindings/timer/st,stm32-lptim.yaml index ad3e55d4a4881c..8e0e8cd1f71f78 100644 --- a/dts/bindings/timer/st,stm32-lptim.yaml +++ b/dts/bindings/timer/st,stm32-lptim.yaml @@ -8,7 +8,7 @@ compatible: "st,stm32-lptim" include: - name: st,stm32-timers.yaml property-blocklist: - # 'resets' property is not supported yet - - resets - - st,prescaler - - st,countermode + # 'resets' property is not supported yet + - resets + - st,prescaler + - st,countermode diff --git a/dts/bindings/timer/st,stm32-timers.yaml b/dts/bindings/timer/st,stm32-timers.yaml index e5140531ce865d..135ed7eb63a0c6 100644 --- a/dts/bindings/timer/st,stm32-timers.yaml +++ b/dts/bindings/timer/st,stm32-timers.yaml @@ -8,41 +8,41 @@ compatible: "st,stm32-timers" include: [base.yaml, reset-device.yaml] properties: - reg: - required: true - - clocks: - required: true - - resets: - required: true - - st,prescaler: - type: int - required: true - description: | - Clock prescaler at the input of the timer - Could be in range [0 .. 0xFFFF] for STM32 General Purpose Timers (CLK/(prescaler+1) ) - - st,countermode: - type: int - default: 0 # STM32_TIM_COUNTERMODE_UP - reset state - description: | - Sets timer counter mode. - - Use constants defined in dt-bindings/timer/stm32-timer.h. - - * STM32_TIM_COUNTERMODE_UP - used as upcounter. - * STM32_TIM_COUNTERMODE_DOWN - used as downcounter. - * STM32_TIM_COUNTERMODE_CENTER_DOWN - counts up and down alternatively. - Output compare interrupt flags of output channels - are set only when the counter is counting down. - * STM32_TIM_COUNTERMODE_CENTER_UP - counts up and down alternatively. - Output compare interrupt flags of output channels - are set only when the counter is counting up. - * STM32_TIM_COUNTERMODE_CENTER_UP_DOWN - counts up and down alternatively. - Output compare interrupt flags of output channels - are set only when the counter is counting up or - down. - - If absent, then STM32_TIM_COUNTERMODE_UP is used (reset state). + reg: + required: true + + clocks: + required: true + + resets: + required: true + + st,prescaler: + type: int + required: true + description: | + Clock prescaler at the input of the timer + Could be in range [0 .. 0xFFFF] for STM32 General Purpose Timers (CLK/(prescaler+1) ) + + st,countermode: + type: int + default: 0 # STM32_TIM_COUNTERMODE_UP - reset state + description: | + Sets timer counter mode. + + Use constants defined in dt-bindings/timer/stm32-timer.h. + + * STM32_TIM_COUNTERMODE_UP - used as upcounter. + * STM32_TIM_COUNTERMODE_DOWN - used as downcounter. + * STM32_TIM_COUNTERMODE_CENTER_DOWN - counts up and down alternatively. + Output compare interrupt flags of output channels + are set only when the counter is counting down. + * STM32_TIM_COUNTERMODE_CENTER_UP - counts up and down alternatively. + Output compare interrupt flags of output channels + are set only when the counter is counting up. + * STM32_TIM_COUNTERMODE_CENTER_UP_DOWN - counts up and down alternatively. + Output compare interrupt flags of output channels + are set only when the counter is counting up or + down. + + If absent, then STM32_TIM_COUNTERMODE_UP is used (reset state). diff --git a/dts/bindings/timer/telink,machine-timer.yaml b/dts/bindings/timer/telink,machine-timer.yaml index db307649d3b01d..0ee37bd6de711a 100644 --- a/dts/bindings/timer/telink,machine-timer.yaml +++ b/dts/bindings/timer/telink,machine-timer.yaml @@ -12,8 +12,8 @@ compatible: "telink,machine-timer" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/timer/xlnx,ttcps.yaml b/dts/bindings/timer/xlnx,ttcps.yaml index 7ee6062cf2905d..44450fe1447808 100644 --- a/dts/bindings/timer/xlnx,ttcps.yaml +++ b/dts/bindings/timer/xlnx,ttcps.yaml @@ -5,10 +5,10 @@ compatible: "xlnx,ttcps" include: base.yaml properties: - reg: - required: true + reg: + required: true - clock-frequency: - type: int - required: true - description: Clock frequency information for Timer operation + clock-frequency: + type: int + required: true + description: Clock frequency information for Timer operation diff --git a/dts/bindings/timestamp/intel,ace-timestamp.yaml b/dts/bindings/timestamp/intel,ace-timestamp.yaml index 4908fbbe28ee03..b783f89812600b 100644 --- a/dts/bindings/timestamp/intel,ace-timestamp.yaml +++ b/dts/bindings/timestamp/intel,ace-timestamp.yaml @@ -6,4 +6,4 @@ include: base.yaml properties: reg: - required: true + required: true diff --git a/dts/bindings/usb-c/usb-c-connector.yaml b/dts/bindings/usb-c/usb-c-connector.yaml index 049287bf2c8fa6..d5a9499e9918df 100644 --- a/dts/bindings/usb-c/usb-c-connector.yaml +++ b/dts/bindings/usb-c/usb-c-connector.yaml @@ -14,128 +14,128 @@ compatible: "usb-c-connector" include: base.yaml properties: - tcpc: - type: phandle - required: true - description: | - Type-C Port Controller for this port. - - vbus: - type: phandle - required: true - description: | - VBUS measurement and control for this port. - - power-role: - type: string - required: true - enum: - - "sink" - - "source" - - "dual" - description: | - The Port power role. "dual" for Dual Role Port. - - try-power-role: - type: string - enum: - - "sink" - - "source" - - "dual" - description: | - Preferred power role. - - data-role: - type: string - enum: - - "host" - - "device" - - "dual" - description: | - The Port data role. - * "host" for Downstream Facing Port (DFP) - * "device" for Upstream Facing Port (UFP) - * "dual" for Dual Role Data - - typec-power-opmode: - type: string - enum: - - "default" - - "1.5A" - - "3.0A" - description: | - Initial Type C advertised power, determined by the Rp when - operating as a Source. - * "default" corresponds to default USB voltage and current - defined by the USB 2.0 and USB 3.2 specifications. - * 5V@500mA for USB 2.0 - * 5V@900mA for USB 3.2 single-lane - * 5V@1500mA for USB 3.2 dual-lane - * "1.5A" and "3.0A", 5V@1.5A and 5V@3.0A. - - pd-disable: - type: boolean - description: | - Disables power delivery when true - - source-pdos: - type: array - description: | - An array of source Power Data Objects (PDOs). - Use tht following macros to define the PDOs, defined in - dt-bindings/usb-c/pd.h. - * PDO_FIXED - * PDO_BATT - * PDO_VAR - * PDO_PPS_APDO - Valid range: 1 - 7 - - sink-pdos: - type: array - description: | - An array of sink Power Data Objects (PDOs). - Use tht following macros to define the PDOs, defined in - dt-bindings/usb-c/pd.h. - * PDO_FIXED - * PDO_BATT - * PDO_VAR - * PDO_PPS_APDO - Valid range: 1 - 7 - - sink-vdos: - type: array - description: | - An array of sink Vendor Defined Objects (VDOs). - Use tht following macros to define the VDOs, defined in - dt-bindings/usb-c/pd.h. - * VDO_IDH - * VDO_CERT - * VDO_PRODUCT - * VDO_UFP - * VDO_DFP - * VDO_PCABLE - * VDO_ACABLE - * VDO_VPD - Valid range: 3 - 6 - - sink-vdos-v1: - type: array - description: | - An array of sink Vendor Defined Objects (VDOs). - Use tht following macros to define the VDOs, defined in - dt-bindings/usb-c/pd.h. - * VDO_IDH - * VDO_CERT - * VDO_PRODUCT - * VDO_CABLE - * VDO_AMA - Valid range: 3 - 6 - - op-sink-microwatt: - type: int - description: | - Minimum power, in microwatts, needed by the sink. A Capability - Mismatch is sent to the Source if the power can't be met. + tcpc: + type: phandle + required: true + description: | + Type-C Port Controller for this port. + + vbus: + type: phandle + required: true + description: | + VBUS measurement and control for this port. + + power-role: + type: string + required: true + enum: + - "sink" + - "source" + - "dual" + description: | + The Port power role. "dual" for Dual Role Port. + + try-power-role: + type: string + enum: + - "sink" + - "source" + - "dual" + description: | + Preferred power role. + + data-role: + type: string + enum: + - "host" + - "device" + - "dual" + description: | + The Port data role. + * "host" for Downstream Facing Port (DFP) + * "device" for Upstream Facing Port (UFP) + * "dual" for Dual Role Data + + typec-power-opmode: + type: string + enum: + - "default" + - "1.5A" + - "3.0A" + description: | + Initial Type C advertised power, determined by the Rp when + operating as a Source. + * "default" corresponds to default USB voltage and current + defined by the USB 2.0 and USB 3.2 specifications. + * 5V@500mA for USB 2.0 + * 5V@900mA for USB 3.2 single-lane + * 5V@1500mA for USB 3.2 dual-lane + * "1.5A" and "3.0A", 5V@1.5A and 5V@3.0A. + + pd-disable: + type: boolean + description: | + Disables power delivery when true + + source-pdos: + type: array + description: | + An array of source Power Data Objects (PDOs). + Use tht following macros to define the PDOs, defined in + dt-bindings/usb-c/pd.h. + * PDO_FIXED + * PDO_BATT + * PDO_VAR + * PDO_PPS_APDO + Valid range: 1 - 7 + + sink-pdos: + type: array + description: | + An array of sink Power Data Objects (PDOs). + Use tht following macros to define the PDOs, defined in + dt-bindings/usb-c/pd.h. + * PDO_FIXED + * PDO_BATT + * PDO_VAR + * PDO_PPS_APDO + Valid range: 1 - 7 + + sink-vdos: + type: array + description: | + An array of sink Vendor Defined Objects (VDOs). + Use tht following macros to define the VDOs, defined in + dt-bindings/usb-c/pd.h. + * VDO_IDH + * VDO_CERT + * VDO_PRODUCT + * VDO_UFP + * VDO_DFP + * VDO_PCABLE + * VDO_ACABLE + * VDO_VPD + Valid range: 3 - 6 + + sink-vdos-v1: + type: array + description: | + An array of sink Vendor Defined Objects (VDOs). + Use tht following macros to define the VDOs, defined in + dt-bindings/usb-c/pd.h. + * VDO_IDH + * VDO_CERT + * VDO_PRODUCT + * VDO_CABLE + * VDO_AMA + Valid range: 3 - 6 + + op-sink-microwatt: + type: int + description: | + Minimum power, in microwatts, needed by the sink. A Capability + Mismatch is sent to the Source if the power can't be met. # EXAMPLE: # diff --git a/dts/bindings/usb-c/zephyr,usb-c-vbus-adc.yaml b/dts/bindings/usb-c/zephyr,usb-c-vbus-adc.yaml index 3ee154f03c118a..bac0166f4fdb18 100644 --- a/dts/bindings/usb-c/zephyr,usb-c-vbus-adc.yaml +++ b/dts/bindings/usb-c/zephyr,usb-c-vbus-adc.yaml @@ -10,5 +10,5 @@ compatible: "zephyr,usb-c-vbus-adc" include: [base.yaml, voltage-divider.yaml] properties: - discharge-gpios: - type: phandle-array + discharge-gpios: + type: phandle-array diff --git a/dts/bindings/usb/atmel,sam-usbc.yaml b/dts/bindings/usb/atmel,sam-usbc.yaml index 6f94f8e53f9edb..9d38082a886e4d 100644 --- a/dts/bindings/usb/atmel,sam-usbc.yaml +++ b/dts/bindings/usb/atmel,sam-usbc.yaml @@ -8,17 +8,17 @@ description: | compatible: "atmel,sam-usbc" include: - - name: usb-ep.yaml - - name: pinctrl-device.yaml + - name: usb-ep.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - required: true - description: peripheral ID + peripheral-id: + type: int + required: true + description: peripheral ID diff --git a/dts/bindings/usb/atmel,sam-usbhs.yaml b/dts/bindings/usb/atmel,sam-usbhs.yaml index bbaa8b0ab84345..ca9bdc62a3c6ef 100644 --- a/dts/bindings/usb/atmel,sam-usbhs.yaml +++ b/dts/bindings/usb/atmel,sam-usbhs.yaml @@ -7,17 +7,17 @@ description: | compatible: "atmel,sam-usbhs" include: - - name: usb-ep.yaml - - name: pinctrl-device.yaml + - name: usb-ep.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - required: true - description: peripheral ID + peripheral-id: + type: int + required: true + description: peripheral ID diff --git a/dts/bindings/usb/atmel,sam0-usb.yaml b/dts/bindings/usb/atmel,sam0-usb.yaml index 79748202ed85fe..55f3ae45f6c3f3 100644 --- a/dts/bindings/usb/atmel,sam0-usb.yaml +++ b/dts/bindings/usb/atmel,sam0-usb.yaml @@ -4,12 +4,12 @@ description: | compatible: "atmel,sam0-usb" include: - - name: usb-ep.yaml - - name: pinctrl-device.yaml + - name: usb-ep.yaml + - name: pinctrl-device.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/usb/maxim,max3421e_spi.yaml b/dts/bindings/usb/maxim,max3421e_spi.yaml index aba177e03e1d8c..6e72f3498dc020 100644 --- a/dts/bindings/usb/maxim,max3421e_spi.yaml +++ b/dts/bindings/usb/maxim,max3421e_spi.yaml @@ -9,18 +9,18 @@ compatible: "maxim,max3421e_spi" include: [spi-device.yaml] properties: - int-gpios: - type: phandle-array - required: true - description: | - Interrupt pin of MAX3421E, active low. - If connected directly the MCU pin should be configured - as active low. + int-gpios: + type: phandle-array + required: true + description: | + Interrupt pin of MAX3421E, active low. + If connected directly the MCU pin should be configured + as active low. - reset-gpios: - type: phandle-array - required: false - description: | - RESET pin of MAX3421E, active low. - If connected directly the MCU pin should be configured - as active low. + reset-gpios: + type: phandle-array + required: false + description: | + RESET pin of MAX3421E, active low. + If connected directly the MCU pin should be configured + as active low. diff --git a/dts/bindings/usb/nordic,nrf-usbd.yaml b/dts/bindings/usb/nordic,nrf-usbd.yaml index 4fd6c2acddb2fb..4de7fb0f9e4c06 100644 --- a/dts/bindings/usb/nordic,nrf-usbd.yaml +++ b/dts/bindings/usb/nordic,nrf-usbd.yaml @@ -9,18 +9,18 @@ compatible: "nordic,nrf-usbd" include: usb-ep.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - num-isoin-endpoints: - type: int - required: true - description: Number of ISOIN endpoints supported by hardware + num-isoin-endpoints: + type: int + required: true + description: Number of ISOIN endpoints supported by hardware - num-isoout-endpoints: - type: int - required: true - description: Number of ISOOUT endpoints supported by hardware + num-isoout-endpoints: + type: int + required: true + description: Number of ISOOUT endpoints supported by hardware diff --git a/dts/bindings/usb/nxp,kinetis-usbd.yaml b/dts/bindings/usb/nxp,kinetis-usbd.yaml index e7ee211b24d08d..2ef1b74c2e12b1 100644 --- a/dts/bindings/usb/nxp,kinetis-usbd.yaml +++ b/dts/bindings/usb/nxp,kinetis-usbd.yaml @@ -9,8 +9,8 @@ compatible: "nxp,kinetis-usbd" include: usb-ep.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/usb/nxp,mcux-usbd.yaml b/dts/bindings/usb/nxp,mcux-usbd.yaml index 85cbb51d4cc675..d39df8d5d3ddec 100644 --- a/dts/bindings/usb/nxp,mcux-usbd.yaml +++ b/dts/bindings/usb/nxp,mcux-usbd.yaml @@ -9,29 +9,29 @@ compatible: "nxp,mcux-usbd" include: usb-ep.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - usb-controller-index: - required: true - type: string - description: | - This is taken from the usb_controller_index_t enum that is included inside the NXP SDK - enum: - - "Khci0" - - "Khci1" - - "Ehci0" - - "Ehci1" - - "LpcIp3511Fs0" - - "LpcIp3511Fs1" - - "LpcIp3511Hs0" - - "LpcIp3511Hs1" - - "Ohci0" - - "Ohci1" - - "Ip3516Hs0" - - "Ip3516Hs1" - - "Dwc30" - - "Dwc31" + usb-controller-index: + required: true + type: string + description: | + This is taken from the usb_controller_index_t enum that is included inside the NXP SDK + enum: + - "Khci0" + - "Khci1" + - "Ehci0" + - "Ehci1" + - "LpcIp3511Fs0" + - "LpcIp3511Fs1" + - "LpcIp3511Hs0" + - "LpcIp3511Hs1" + - "Ohci0" + - "Ohci1" + - "Ip3516Hs0" + - "Ip3516Hs1" + - "Dwc30" + - "Dwc31" diff --git a/dts/bindings/usb/raspberrypi,pico-usbd.yaml b/dts/bindings/usb/raspberrypi,pico-usbd.yaml index a75695d96f3bb9..6d307bdf0e5c50 100644 --- a/dts/bindings/usb/raspberrypi,pico-usbd.yaml +++ b/dts/bindings/usb/raspberrypi,pico-usbd.yaml @@ -8,8 +8,8 @@ compatible: "raspberrypi,pico-usbd" include: [usb-ep.yaml, reset-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/usb/snps,designware-usb.yaml b/dts/bindings/usb/snps,designware-usb.yaml index 68264c51b7495a..993e1f738e3898 100644 --- a/dts/bindings/usb/snps,designware-usb.yaml +++ b/dts/bindings/usb/snps,designware-usb.yaml @@ -8,8 +8,8 @@ compatible: "snps,designware-usb" include: usb-ep.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/usb/st,stm32-otgfs.yaml b/dts/bindings/usb/st,stm32-otgfs.yaml index 1357a3a9c7ae7c..65ab6b616f9d62 100644 --- a/dts/bindings/usb/st,stm32-otgfs.yaml +++ b/dts/bindings/usb/st,stm32-otgfs.yaml @@ -8,28 +8,28 @@ compatible: "st,stm32-otgfs" include: [usb-ep.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - ram-size: - type: int - required: true - description: | - Size of USB dedicated RAM. STM32 SOC's reference - manual defines a shared FIFO size. + ram-size: + type: int + required: true + description: | + Size of USB dedicated RAM. STM32 SOC's reference + manual defines a shared FIFO size. - phys: - type: phandle - description: PHY provider specifier + phys: + type: phandle + description: PHY provider specifier - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/usb/st,stm32-otghs.yaml b/dts/bindings/usb/st,stm32-otghs.yaml index 82c6f88476309a..dfd40a9ed3d40b 100644 --- a/dts/bindings/usb/st,stm32-otghs.yaml +++ b/dts/bindings/usb/st,stm32-otghs.yaml @@ -8,28 +8,28 @@ compatible: "st,stm32-otghs" include: [usb-ep.yaml, pinctrl-device.yaml] properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - pinctrl-0: - required: true + pinctrl-0: + required: true - pinctrl-names: - required: true + pinctrl-names: + required: true - ram-size: - type: int - required: true - description: | - Size of USB dedicated RAM. STM32 SOC's reference - manual defines a shared FIFO size. + ram-size: + type: int + required: true + description: | + Size of USB dedicated RAM. STM32 SOC's reference + manual defines a shared FIFO size. - phys: - type: phandle - description: PHY provider specifier + phys: + type: phandle + description: PHY provider specifier - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/usb/st,stm32-usb.yaml b/dts/bindings/usb/st,stm32-usb.yaml index 5b0eaa758fa4f2..1328211bea905d 100644 --- a/dts/bindings/usb/st,stm32-usb.yaml +++ b/dts/bindings/usb/st,stm32-usb.yaml @@ -8,28 +8,28 @@ compatible: "st,stm32-usb" include: [usb-ep.yaml, pinctrl-device.yaml] properties: - reg: - required: true - - interrupts: - required: true - - ram-size: - type: int - required: true - description: | - Size of USB dedicated RAM. STM32 SOC's reference - manual defines USB packet SRAM size. - - disconnect-gpios: - type: phandle-array - description: | - Some boards use a USB DISCONNECT pin to enable - the pull-up resistor on USB Data Positive signal. - - phys: - type: phandle - description: PHY provider specifier - - clocks: - required: true + reg: + required: true + + interrupts: + required: true + + ram-size: + type: int + required: true + description: | + Size of USB dedicated RAM. STM32 SOC's reference + manual defines USB packet SRAM size. + + disconnect-gpios: + type: phandle-array + description: | + Some boards use a USB DISCONNECT pin to enable + the pull-up resistor on USB Data Positive signal. + + phys: + type: phandle + description: PHY provider specifier + + clocks: + required: true diff --git a/dts/bindings/usb/usb-audio-hp.yaml b/dts/bindings/usb/usb-audio-hp.yaml index af77f3e13ea382..051c57c07d38b4 100644 --- a/dts/bindings/usb/usb-audio-hp.yaml +++ b/dts/bindings/usb/usb-audio-hp.yaml @@ -14,10 +14,10 @@ properties: type: int default: 16 enum: - - 8 - - 16 - - 24 - - 32 + - 8 + - 16 + - 24 + - 32 # channel configuration options channel-l: type: boolean diff --git a/dts/bindings/usb/usb-audio-hs.yaml b/dts/bindings/usb/usb-audio-hs.yaml index 3f74b62c7d11d7..3c4a39842a562e 100644 --- a/dts/bindings/usb/usb-audio-hs.yaml +++ b/dts/bindings/usb/usb-audio-hs.yaml @@ -14,10 +14,10 @@ properties: type: int default: 16 enum: - - 8 - - 16 - - 24 - - 32 + - 8 + - 16 + - 24 + - 32 mic-sync-type: default: "Synchronous" type: string @@ -26,18 +26,18 @@ properties: Default value is Sychronous. Adaptive is not supported. enum: - - "No Synchronization" - - "Asynchronous" - - "Adaptive" - - "Synchronous" + - "No Synchronization" + - "Asynchronous" + - "Adaptive" + - "Synchronous" hp-resolution: type: int default: 16 enum: - - 8 - - 16 - - 24 - - 32 + - 8 + - 16 + - 24 + - 32 # microphone channel configuration options mic-channel-l: type: boolean diff --git a/dts/bindings/usb/usb-audio-mic.yaml b/dts/bindings/usb/usb-audio-mic.yaml index bbf407dc6df51a..032021fd363a0a 100644 --- a/dts/bindings/usb/usb-audio-mic.yaml +++ b/dts/bindings/usb/usb-audio-mic.yaml @@ -14,10 +14,10 @@ properties: type: int default: 16 enum: - - 8 - - 16 - - 24 - - 32 + - 8 + - 16 + - 24 + - 32 sync-type: default: "Synchronous" type: string @@ -26,10 +26,10 @@ properties: Default value is Sychronous. Adaptive is not supported. enum: - - "No Synchronization" - - "Asynchronous" - - "Adaptive" - - "Synchronous" + - "No Synchronization" + - "Asynchronous" + - "Adaptive" + - "Synchronous" # channel configuration options channel-l: type: boolean diff --git a/dts/bindings/usb/usb-controller.yaml b/dts/bindings/usb/usb-controller.yaml index 54ce93acc717a8..185562e9a3e43c 100644 --- a/dts/bindings/usb/usb-controller.yaml +++ b/dts/bindings/usb/usb-controller.yaml @@ -8,19 +8,19 @@ include: base.yaml bus: usb properties: - maximum-speed: - type: string - description: Configures USB controllers to work up to a specific - speed. Valid arguments are "super-speed", "high-speed", - "full-speed" and "low-speed". If this is not passed - via DT, USB controllers should use their maximum - hardware capability. - enum: - - "low-speed" - - "full-speed" - - "high-speed" - - "super-speed" + maximum-speed: + type: string + description: Configures USB controllers to work up to a specific + speed. Valid arguments are "super-speed", "high-speed", + "full-speed" and "low-speed". If this is not passed + via DT, USB controllers should use their maximum + hardware capability. + enum: + - "low-speed" + - "full-speed" + - "high-speed" + - "super-speed" - vbus-gpios: - type: phandle-array - description: Control VBUS via GPIO pin. + vbus-gpios: + type: phandle-array + description: Control VBUS via GPIO pin. diff --git a/dts/bindings/usb/usb-ep.yaml b/dts/bindings/usb/usb-ep.yaml index 112041f309026b..8d82cecb42dded 100644 --- a/dts/bindings/usb/usb-ep.yaml +++ b/dts/bindings/usb/usb-ep.yaml @@ -6,21 +6,21 @@ include: usb-controller.yaml properties: - num-bidir-endpoints: - type: int - required: true - description: | - Number of bi-directional endpoints supported by hardware - (including EP0) + num-bidir-endpoints: + type: int + required: true + description: | + Number of bi-directional endpoints supported by hardware + (including EP0) - num-in-endpoints: - type: int - description: | - Number of IN endpoints supported by hardware - (including EP0 IN) + num-in-endpoints: + type: int + description: | + Number of IN endpoints supported by hardware + (including EP0 IN) - num-out-endpoints: - type: int - description: | - Number of OUT endpoints supported by hardware - (including EP0 OUT) + num-out-endpoints: + type: int + description: | + Number of OUT endpoints supported by hardware + (including EP0 OUT) diff --git a/dts/bindings/video/nxp,imx-csi.yaml b/dts/bindings/video/nxp,imx-csi.yaml index 940c23cc1023c2..d2553d68911844 100644 --- a/dts/bindings/video/nxp,imx-csi.yaml +++ b/dts/bindings/video/nxp,imx-csi.yaml @@ -11,10 +11,10 @@ compatible: "nxp,imx-csi" include: [base.yaml, pinctrl-device.yaml] properties: - interrupts: - required: true + interrupts: + required: true - sensor: - required: true - type: phandle - description: phandle of connected sensor device + sensor: + required: true + type: phandle + description: phandle of connected sensor device diff --git a/dts/bindings/video/ovti,ov2640.yaml b/dts/bindings/video/ovti,ov2640.yaml index 8ab9ff10ce9c22..796020e06999e9 100644 --- a/dts/bindings/video/ovti,ov2640.yaml +++ b/dts/bindings/video/ovti,ov2640.yaml @@ -6,10 +6,10 @@ description: OV2640 CMOS video sensor compatible: "ovti,ov2640" properties: - reset-gpios: - type: phandle-array - description: | - The RESETn pin is asserted to disable the sensor causing a hard - reset. The sensor receives this as an active-low signal. + reset-gpios: + type: phandle-array + description: | + The RESETn pin is asserted to disable the sensor causing a hard + reset. The sensor receives this as an active-low signal. include: i2c-device.yaml diff --git a/dts/bindings/video/ovti,ov7725.yaml b/dts/bindings/video/ovti,ov7725.yaml index 76e9cba878223c..15b557d78e7409 100644 --- a/dts/bindings/video/ovti,ov7725.yaml +++ b/dts/bindings/video/ovti,ov7725.yaml @@ -6,10 +6,10 @@ description: OV7725 CMOS video sensor compatible: "ovti,ov7725" properties: - reset-gpios: - type: phandle-array - description: | - The RESETn pin is asserted to disable the sensor causing a hard - reset. The sensor receives this as an active-low signal. + reset-gpios: + type: phandle-array + description: | + The RESETn pin is asserted to disable the sensor causing a hard + reset. The sensor receives this as an active-low signal. include: i2c-device.yaml diff --git a/dts/bindings/w1/maxim,ds2477_85_common.yaml b/dts/bindings/w1/maxim,ds2477_85_common.yaml index 2e676469664901..584173d6f89de3 100644 --- a/dts/bindings/w1/maxim,ds2477_85_common.yaml +++ b/dts/bindings/w1/maxim,ds2477_85_common.yaml @@ -46,10 +46,10 @@ properties: type: string required: true enum: - - "extern" - - "500" - - "1000" - - "333" + - "extern" + - "500" + - "1000" + - "333" description: | Default 1-Wire Weak Pullup Resistance in ohms. For most configurations with a single slave "1000" ohms are recommended, diff --git a/dts/bindings/w1/w1-master.yaml b/dts/bindings/w1/w1-master.yaml index 4c593effd7ca13..39a15ebe2be4c4 100644 --- a/dts/bindings/w1/w1-master.yaml +++ b/dts/bindings/w1/w1-master.yaml @@ -8,7 +8,7 @@ include: base.yaml bus: w1 properties: - active-pullup: - type: boolean - description: | - Enable the active pullup for the 1-Wire bus. + active-pullup: + type: boolean + description: | + Enable the active pullup for the 1-Wire bus. diff --git a/dts/bindings/w1/w1-slave.yaml b/dts/bindings/w1/w1-slave.yaml index e78bc169f12316..b80a8e7908d9ce 100644 --- a/dts/bindings/w1/w1-slave.yaml +++ b/dts/bindings/w1/w1-slave.yaml @@ -8,14 +8,14 @@ include: base.yaml on-bus: w1 properties: - family-code: - type: int - description: | - 8-bit 1-Wire family code, which is also part of the 64 bit ROM ID. - overdrive-speed: - type: boolean - description: | - Instead of standard speed timing, use overdrive speed timing for - communication. - The driver will automatically use OVERDRIVE_SKIP and OVERDRIVE_MATCH - command instead of the standard commands. + family-code: + type: int + description: | + 8-bit 1-Wire family code, which is also part of the 64 bit ROM ID. + overdrive-speed: + type: boolean + description: | + Instead of standard speed timing, use overdrive speed timing for + communication. + The driver will automatically use OVERDRIVE_SKIP and OVERDRIVE_MATCH + command instead of the standard commands. diff --git a/dts/bindings/watchdog/arm,cmsdk-watchdog.yaml b/dts/bindings/watchdog/arm,cmsdk-watchdog.yaml index e5611fc07f24b4..805c14cc0c0eb7 100644 --- a/dts/bindings/watchdog/arm,cmsdk-watchdog.yaml +++ b/dts/bindings/watchdog/arm,cmsdk-watchdog.yaml @@ -5,8 +5,8 @@ compatible: "arm,cmsdk-watchdog" include: base.yaml properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/watchdog/atmel,sam-watchdog.yaml b/dts/bindings/watchdog/atmel,sam-watchdog.yaml index 331b4099b45bc2..adbfca4e6d9b31 100644 --- a/dts/bindings/watchdog/atmel,sam-watchdog.yaml +++ b/dts/bindings/watchdog/atmel,sam-watchdog.yaml @@ -8,13 +8,13 @@ compatible: "atmel,sam-watchdog" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/watchdog/atmel,sam0-watchdog.yaml b/dts/bindings/watchdog/atmel,sam0-watchdog.yaml index 92bd159dbc2740..dd16a7d69e5dae 100644 --- a/dts/bindings/watchdog/atmel,sam0-watchdog.yaml +++ b/dts/bindings/watchdog/atmel,sam0-watchdog.yaml @@ -5,8 +5,8 @@ compatible: "atmel,sam0-watchdog" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/watchdog/espressif,esp32-watchdog.yaml b/dts/bindings/watchdog/espressif,esp32-watchdog.yaml index 7ee7e6d39dc5ad..87997e291adfee 100644 --- a/dts/bindings/watchdog/espressif,esp32-watchdog.yaml +++ b/dts/bindings/watchdog/espressif,esp32-watchdog.yaml @@ -10,5 +10,5 @@ compatible: "espressif,esp32-watchdog" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/watchdog/gd,gd32-fwdgt.yaml b/dts/bindings/watchdog/gd,gd32-fwdgt.yaml index d9b7bcf1e4f408..66499614ca3ebc 100644 --- a/dts/bindings/watchdog/gd,gd32-fwdgt.yaml +++ b/dts/bindings/watchdog/gd,gd32-fwdgt.yaml @@ -8,26 +8,26 @@ compatible: "gd,gd32-fwdgt" include: base.yaml properties: - reg: - required: true + reg: + required: true - initial-timeout-ms: - type: int - default: 250 - description: | - Set timeout value in milliseconds. - The following equation gives the maximum timeout value + initial-timeout-ms: + type: int + default: 250 + description: | + Set timeout value in milliseconds. + The following equation gives the maximum timeout value - timeout = (reload + 1) / (peripheral_freqency / prescaler). + timeout = (reload + 1) / (peripheral_freqency / prescaler). - where the maximum prescaler = 256 and the maximum reload = 4096. - The peripheral_frequency uses GD32_LOW_SPEED_IRC_FREQUENCY - that defined in modules/hal_gigadevice/Kconfig. - Validate the value is within a capable range at the compile time. + where the maximum prescaler = 256 and the maximum reload = 4096. + The peripheral_frequency uses GD32_LOW_SPEED_IRC_FREQUENCY + that defined in modules/hal_gigadevice/Kconfig. + Validate the value is within a capable range at the compile time. - The default value defined is close to the register reset value - from values that don't cause calculation errors in both cases of - the low-speed internal RC oscillator frequency is 32kHz or 40kHz. + The default value defined is close to the register reset value + from values that don't cause calculation errors in both cases of + the low-speed internal RC oscillator frequency is 32kHz or 40kHz. - 0.25 [timeout in sec] = (1999 [reload] + 1) / (32000 [freq] / 4 [prescaler]) - 0.25 [timeout in sec] = (2499 [reload] + 1) / (40000 [freq] / 4 [prescaler]) + 0.25 [timeout in sec] = (1999 [reload] + 1) / (32000 [freq] / 4 [prescaler]) + 0.25 [timeout in sec] = (2499 [reload] + 1) / (40000 [freq] / 4 [prescaler]) diff --git a/dts/bindings/watchdog/gd,gd32-wwdgt.yaml b/dts/bindings/watchdog/gd,gd32-wwdgt.yaml index 5c1be1d89ea1f7..78406df82388d9 100644 --- a/dts/bindings/watchdog/gd,gd32-wwdgt.yaml +++ b/dts/bindings/watchdog/gd,gd32-wwdgt.yaml @@ -8,11 +8,11 @@ compatible: "gd,gd32-wwdgt" include: [base.yaml, reset-device.yaml] properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true - resets: - required: true + resets: + required: true diff --git a/dts/bindings/watchdog/ite,it8xxx2-watchdog.yaml b/dts/bindings/watchdog/ite,it8xxx2-watchdog.yaml index 314246b9b04958..f5aa18be876e8b 100644 --- a/dts/bindings/watchdog/ite,it8xxx2-watchdog.yaml +++ b/dts/bindings/watchdog/ite,it8xxx2-watchdog.yaml @@ -8,8 +8,8 @@ include: base.yaml compatible: "ite,it8xxx2-watchdog" properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/watchdog/microchip,xec-watchdog.yaml b/dts/bindings/watchdog/microchip,xec-watchdog.yaml index 01550594a506fa..c53f3c204af12b 100644 --- a/dts/bindings/watchdog/microchip,xec-watchdog.yaml +++ b/dts/bindings/watchdog/microchip,xec-watchdog.yaml @@ -8,18 +8,18 @@ include: base.yaml compatible: "microchip,xec-watchdog" properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - girqs: - type: array - required: true - description: Array of GIRQ numbers [8:26] and bit positions [0:31]. + girqs: + type: array + required: true + description: Array of GIRQ numbers [8:26] and bit positions [0:31]. - pcrs: - type: array - required: true - description: PCR sleep enable register index and bit position. + pcrs: + type: array + required: true + description: PCR sleep enable register index and bit position. diff --git a/dts/bindings/watchdog/nordic,nrf-wdt.yaml b/dts/bindings/watchdog/nordic,nrf-wdt.yaml index 0597b3f6ef585a..cd91ad960fd600 100644 --- a/dts/bindings/watchdog/nordic,nrf-wdt.yaml +++ b/dts/bindings/watchdog/nordic,nrf-wdt.yaml @@ -8,8 +8,8 @@ compatible: "nordic,nrf-wdt" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml b/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml index 9a508b2d6474bd..87a2abb2e62ec8 100644 --- a/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml +++ b/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml @@ -8,12 +8,12 @@ compatible: "nuvoton,npcx-watchdog" include: [base.yaml] properties: - reg: - required: true - t0-out: - type: phandle - required: true - description: | - Mapping table between Wake-Up Input (WUI) and t0-out timer expired signal. - For example, the WUI mapping on NPCX7 t0-out timer would be - t0-out = <&wui_t0out>; + reg: + required: true + t0-out: + type: phandle + required: true + description: | + Mapping table between Wake-Up Input (WUI) and t0-out timer expired signal. + For example, the WUI mapping on NPCX7 t0-out timer would be + t0-out = <&wui_t0out>; diff --git a/dts/bindings/watchdog/nxp,imx-wdog.yaml b/dts/bindings/watchdog/nxp,imx-wdog.yaml index ffef8db7959b08..1ed34e4c9a73a3 100644 --- a/dts/bindings/watchdog/nxp,imx-wdog.yaml +++ b/dts/bindings/watchdog/nxp,imx-wdog.yaml @@ -8,8 +8,8 @@ compatible: "nxp,imx-wdog" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/watchdog/nxp,kinetis-wdog.yaml b/dts/bindings/watchdog/nxp,kinetis-wdog.yaml index 44a3c7776d7df7..28c0adaf8768e4 100644 --- a/dts/bindings/watchdog/nxp,kinetis-wdog.yaml +++ b/dts/bindings/watchdog/nxp,kinetis-wdog.yaml @@ -8,11 +8,11 @@ compatible: "nxp,kinetis-wdog" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/watchdog/nxp,kinetis-wdog32.yaml b/dts/bindings/watchdog/nxp,kinetis-wdog32.yaml index b722f415080494..a28f54f8bad1aa 100644 --- a/dts/bindings/watchdog/nxp,kinetis-wdog32.yaml +++ b/dts/bindings/watchdog/nxp,kinetis-wdog32.yaml @@ -8,21 +8,21 @@ compatible: "nxp,kinetis-wdog32" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clocks: - required: true + clocks: + required: true - clk-source: - type: int - required: true - description: Watchdog counter clock source + clk-source: + type: int + required: true + description: Watchdog counter clock source - clk-divider: - type: int - description: Watchdog counter clock divider - required: true + clk-divider: + type: int + description: Watchdog counter clock divider + required: true diff --git a/dts/bindings/watchdog/nxp,lpc-wwdt.yaml b/dts/bindings/watchdog/nxp,lpc-wwdt.yaml index 01bc9c364f6cd6..0781ef4e8c198f 100644 --- a/dts/bindings/watchdog/nxp,lpc-wwdt.yaml +++ b/dts/bindings/watchdog/nxp,lpc-wwdt.yaml @@ -8,13 +8,13 @@ compatible: "nxp,lpc-wwdt" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - clk-divider: - type: int - description: Watchdog clock divider - required: true + clk-divider: + type: int + description: Watchdog clock divider + required: true diff --git a/dts/bindings/watchdog/raspberrypi,pico-watchdog.yaml b/dts/bindings/watchdog/raspberrypi,pico-watchdog.yaml index eef9fe1963c021..901c69f4996de3 100644 --- a/dts/bindings/watchdog/raspberrypi,pico-watchdog.yaml +++ b/dts/bindings/watchdog/raspberrypi,pico-watchdog.yaml @@ -8,9 +8,9 @@ compatible: "raspberrypi,pico-watchdog" include: base.yaml properties: - reg: - required: true + reg: + required: true - clocks: - required: true - description: Crystal oscillator source clock + clocks: + required: true + description: Crystal oscillator source clock diff --git a/dts/bindings/watchdog/sifive,wdt.yaml b/dts/bindings/watchdog/sifive,wdt.yaml index 1d7aa1096aaa51..8117497cf5e6fa 100644 --- a/dts/bindings/watchdog/sifive,wdt.yaml +++ b/dts/bindings/watchdog/sifive,wdt.yaml @@ -8,8 +8,8 @@ compatible: "sifive,wdt" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true diff --git a/dts/bindings/watchdog/silabs,gecko-wdog.yaml b/dts/bindings/watchdog/silabs,gecko-wdog.yaml index 8c06269e75e901..84f219c4feb6be 100644 --- a/dts/bindings/watchdog/silabs,gecko-wdog.yaml +++ b/dts/bindings/watchdog/silabs,gecko-wdog.yaml @@ -9,13 +9,13 @@ compatible: "silabs,gecko-wdog" include: base.yaml properties: - reg: - required: true + reg: + required: true - interrupts: - required: true + interrupts: + required: true - peripheral-id: - type: int - description: peripheral ID - required: true + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/watchdog/st,stm32-watchdog.yaml b/dts/bindings/watchdog/st,stm32-watchdog.yaml index ddb04e14862734..9bbca17bc30556 100644 --- a/dts/bindings/watchdog/st,stm32-watchdog.yaml +++ b/dts/bindings/watchdog/st,stm32-watchdog.yaml @@ -8,5 +8,5 @@ compatible: "st,stm32-watchdog" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/watchdog/st,stm32-window-watchdog.yaml b/dts/bindings/watchdog/st,stm32-window-watchdog.yaml index e3cdf0f4b23817..305d1f821ac69a 100644 --- a/dts/bindings/watchdog/st,stm32-window-watchdog.yaml +++ b/dts/bindings/watchdog/st,stm32-window-watchdog.yaml @@ -8,8 +8,8 @@ compatible: "st,stm32-window-watchdog" include: base.yaml properties: - reg: - required: true + reg: + required: true - clocks: - required: true + clocks: + required: true diff --git a/dts/bindings/watchdog/ti,cc32xx-watchdog.yaml b/dts/bindings/watchdog/ti,cc32xx-watchdog.yaml index 0b8636daee4b26..1819cae957639e 100644 --- a/dts/bindings/watchdog/ti,cc32xx-watchdog.yaml +++ b/dts/bindings/watchdog/ti,cc32xx-watchdog.yaml @@ -8,5 +8,5 @@ compatible: "ti,cc32xx-watchdog" include: base.yaml properties: - reg: - required: true + reg: + required: true diff --git a/dts/bindings/watchdog/zephyr,counter-watchdog.yaml b/dts/bindings/watchdog/zephyr,counter-watchdog.yaml index 1a847435b28a99..a7f03e979bb119 100644 --- a/dts/bindings/watchdog/zephyr,counter-watchdog.yaml +++ b/dts/bindings/watchdog/zephyr,counter-watchdog.yaml @@ -9,8 +9,8 @@ compatible: "zephyr,counter-watchdog" include: base.yaml properties: - counter: - type: phandle - required: true - description: | - Counter device used for watchdog. + counter: + type: phandle + required: true + description: | + Counter device used for watchdog. diff --git a/dts/bindings/wifi/atmel,winc1500.yaml b/dts/bindings/wifi/atmel,winc1500.yaml index 83de2fd6d4887c..e48763bb3e02b8 100644 --- a/dts/bindings/wifi/atmel,winc1500.yaml +++ b/dts/bindings/wifi/atmel,winc1500.yaml @@ -8,14 +8,14 @@ compatible: "atmel,winc1500" include: spi-device.yaml properties: - irq-gpios: - type: phandle-array - required: true + irq-gpios: + type: phandle-array + required: true - reset-gpios: - type: phandle-array - required: true + reset-gpios: + type: phandle-array + required: true - enable-gpios: - type: phandle-array - required: true + enable-gpios: + type: phandle-array + required: true diff --git a/dts/bindings/wifi/espressif,esp-at.yaml b/dts/bindings/wifi/espressif,esp-at.yaml index 40bc56baf1483f..312db8b5727a60 100644 --- a/dts/bindings/wifi/espressif,esp-at.yaml +++ b/dts/bindings/wifi/espressif,esp-at.yaml @@ -8,14 +8,14 @@ compatible: "espressif,esp-at" include: uart-device.yaml properties: - power-gpios: - type: phandle-array + power-gpios: + type: phandle-array - reset-gpios: - type: phandle-array + reset-gpios: + type: phandle-array - target-speed: - type: int - description: - UART baudrate which will be requested using AT commands and to which - UART interface will be reconfigured during initialization phase. + target-speed: + type: int + description: + UART baudrate which will be requested using AT commands and to which + UART interface will be reconfigured during initialization phase. diff --git a/dts/bindings/wifi/inventek,eswifi-uart.yaml b/dts/bindings/wifi/inventek,eswifi-uart.yaml index 9399a43beaa0fb..9f618f422eb689 100644 --- a/dts/bindings/wifi/inventek,eswifi-uart.yaml +++ b/dts/bindings/wifi/inventek,eswifi-uart.yaml @@ -9,9 +9,9 @@ compatible: "inventek,eswifi-uart" include: uart-device.yaml properties: - resetn-gpios: - type: phandle-array - required: true + resetn-gpios: + type: phandle-array + required: true - wakeup-gpios: - type: phandle-array + wakeup-gpios: + type: phandle-array diff --git a/dts/bindings/wifi/inventek,eswifi.yaml b/dts/bindings/wifi/inventek,eswifi.yaml index 350829bcb4b897..51a18eed410c30 100644 --- a/dts/bindings/wifi/inventek,eswifi.yaml +++ b/dts/bindings/wifi/inventek,eswifi.yaml @@ -8,16 +8,16 @@ compatible: "inventek,eswifi" include: spi-device.yaml properties: - resetn-gpios: - type: phandle-array - required: true + resetn-gpios: + type: phandle-array + required: true - data-gpios: - type: phandle-array - required: true + data-gpios: + type: phandle-array + required: true - wakeup-gpios: - type: phandle-array + wakeup-gpios: + type: phandle-array - boot0-gpios: - type: phandle-array + boot0-gpios: + type: phandle-array diff --git a/dts/bindings/xen/xen,xen-4.15.yaml b/dts/bindings/xen/xen,xen-4.15.yaml index e01717f00d36be..7456450d3ad785 100644 --- a/dts/bindings/xen/xen,xen-4.15.yaml +++ b/dts/bindings/xen/xen,xen-4.15.yaml @@ -5,7 +5,7 @@ compatible: "xen,xen-4.15" include: base.yaml properties: - reg: - required: true - interrupts: - required: true + reg: + required: true + interrupts: + required: true