Strategy for better large-scale simulation and synthesis

[tomcl]

Currently the fast simulation turns hierarchical designs into a flat sea of gates to simulate.

• This is necessary - and works very well with almost no simulation code errors found when debugging.
• However it would be better to keep the hierarchy info (when a sheet begins or ends) and generate Verilog output (optionally) in multiple files that follow (one module per sheet) the design sheets.
• One use case for this is module-level testing and debugging of Verilog output- sea of gates is incomprehensible.
• Another use case is for example when specific block RAM resources need to be used in a design. Ideally a library sheet should be written with the correct simulation behaviour and that sheet output (as Verilog) using the on-chip block RAM by writing a small Verilog adapter module which is held with the library sheet and used instead of the default sea of gates Verilog output.
• The fast simulation keeps nearly all of the sheet boundary info at the moment, so adding this in should not be too difficult.
• This feature is similar to black-box tagging in an HDL.