CAD in NYCU
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Updated
Dec 22, 2023 - Verilog
CAD in NYCU
This project is a part of the report for my 7th semester program elective (EC-4143 VLSI-CAD).
TCL Script automating the frontend of ASIC design
5-Day TCL begginer to advanced workshop by VSD
A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)
5 Day TCL begginer to advanced training workshop by VSD
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
A High-performance Timing Analysis Tool for VLSI Systems
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