static-timing-analysis
Here are 12 public repositories matching this topic...
5-Day TCL begginer to advanced workshop by VSD
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Jan 24, 2024 - Verilog
This project is a part of the report for my 7th semester program elective (EC-4143 VLSI-CAD).
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Jan 11, 2024 - Tcl
CAD in NYCU
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Dec 22, 2023 - Verilog
5 Day TCL begginer to advanced training workshop by VSD
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Oct 18, 2023 - Verilog
TCL Script automating the frontend of ASIC design
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Jun 21, 2023 - Verilog
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Jun 3, 2023 - HTML
A High-performance Timing Analysis Tool for VLSI Systems
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May 26, 2023 - Verilog
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
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Aug 7, 2022 - C++
A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)
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Mar 25, 2021 - HTML
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