Vitis In-Depth Tutorials
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Updated
Jul 15, 2024 - C
Vitis In-Depth Tutorials
A portable interface for energy monitoring utilities
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
ZCU102 two IMX274 camera design.
Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.
Collection of FPGA modules for video capture and processing.
Workflow for executing CNN Networks on Zynq Ultrascale+ with Vitis AI toolchain. Detailed analysis, configuration and execution of Convolutional Neural Networks on ZCU102 using Vitis AI, evaluating performance on the board compared to Cloud infrastructure (eg. Kaggle). Developed for educational exam purposes.
This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)
This directory contains the source code for implementing Random Linear Network Coding (RLNC) into Multi-Processor System-on-Chips (MPSoC). By exploiting data vectorization, we obtained latency and throughputs gains during the matrix multiplication operations.
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