Move on to the new toy, Celestial Peak. How can we RE it ?

[ImNotMyself]

Quick spec:
Stratix 1SGHF43, aka. 1SG110, with 10 SKhynix H5AN8G6NC
Boardcom BCM 58732 8-cores A72, with 5 Micron D9WFR

I extracted and uploaded the flash image here https://github.com/ImNotMyself/a2040
But now the question is what's next, how can we RE it ?

[Nic30]

Let me just add few keywords for better SEO.
Microsoft RR-MSK-A-2040, Microsoft A-2040, A2040, Overlake: Celestial Peak, Microsoft Stratix 10 FPGA, MICROSOFT A-2040 M1132139-001
Cloud and FPGAs in Physics and HPC from Data Acquisition to the Cloud, Andrew Putnam, July 22, 2022

[tow3rs]

@ImNotMyself
It seems that it will be very difficult, if not impossible, to obtain a complete reversal of the board pinout based only on the FPGA bitstream.
A first attempt may be to assume that the QSFP ports and PCIe lines are wired to the S10 Hard IPs. According to the Quartus Pin Planner, the following pin configuration should be used in this scenario.

[ImNotMyself]

@tow3rs make sense !
for the other parts, anything I can do ? I am very willing to trial and/or debug on board, if you are happy to guide me through
Thanks advance.

[tow3rs]

Another option, or maybe the first one, is to use the TopJTAG Probe tool, with the help of this tool and the BSDL file for the S10 it's relatively easy to monitor the FPGA pins that have activity, such as clock inputs.
The hardest part will be to identify the DDR4 pinout, you can try the method described in Jan Marjanovic's blog: https://j-marjanovic.io/stratix-v-accelerator-card-from-ebay-part-5.html
The last option would be to desolder the memory chips... with the risk of damaging the board...

[imkow]

I got a Glacier Peak A-2051, just start digging

[myfpga]

So A-2030 is the most cost-effective board, with less than $50 and sufficient information. Although I also want to study A-2040 and A-2051, I know my ability is limited, and the prices of these two are too high to easily get started.

[11tools]

have anyone try run intel npu project on arria10 catapult-v3?

https://github.com/intel/fpga-npu

I tryed. but this project have some dsp IP use stritx10 , can't synthesis on arria10

if A-2040 cracked. i will buy one. or try to synthesis on arria10 .... i think this project can make catapult-v3 useful

[myfpga]

您好！很荣幸收到您的来信，我会在看到后尽快回复您！