From e6037af75630d15debf91a93d2c2a7e0dac61547 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 14 Apr 2023 07:54:53 +0000 Subject: [PATCH 01/46] im2d_api: feature: add support for more Porter-Duff blend mode 1. Add support src-in/dst-in/src-out/dst-out/src-atop/dst-atop/xor. 2. Drivers must be greater than or equal to 1.3.0. Change-Id: I5b58b7c90f161a447cebe825d4b0021fb50b9680 Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 105 +++++++++++++++++++------------------ im2d_api/src/im2d_impl.cpp | 20 +++++-- 2 files changed, 70 insertions(+), 55 deletions(-) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index e3c5fa8..0d0d627 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -695,64 +695,67 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { if(is_out_log()) ALOGE("blend = %x , perpixelAlpha = %d",blend,perpixelAlpha); - /* blend bit[0:15] is to set which way to blend,such as whether need glabal alpha,and so on. */ - switch ((blend & 0xFFFF)) { - case 0x0001:/* src */ - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha , 1, 1, 0); - break; - - case 0x0002:/* dst */ - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha , 1, 2, 0); - break; - - case 0x0105:/* src over , no need to Premultiplied. */ - if (perpixelAlpha && planeAlpha < 255) { - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha, 1, 9, 0); - } else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0, 1, 3, 0); - else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, planeAlpha, 0, 0, 0); - break; + /* Compatible with legacy blend mode. */ + if (blend == 0x405 || blend == 0x504 || + blend == 0x105 || blend == 0x501 || + blend == 0x100) { + /* blend bit[0:15] is to set which way to blend, such as whether need glabal alpha, and so on. */ + switch ((blend & 0xFFFF)) { + case 0x0105:/* src over , no need to Premultiplied. */ + if (perpixelAlpha && planeAlpha < 255) { + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha, 1, 9, 0); + } else if (perpixelAlpha) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0, 1, 3, 0); + else + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, planeAlpha, 0, 0, 0); + break; - case 0x0405:/* src over , need to Premultiplied. */ - if (perpixelAlpha && planeAlpha < 255) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha, 1, 9, 0); - else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0, 1, 3, 0); - else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, planeAlpha, 0, 0, 0); + case 0x0405:/* src over , need to Premultiplied. */ + if (perpixelAlpha && planeAlpha < 255) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha, 1, 9, 0); + else if (perpixelAlpha) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0, 1, 3, 0); + else + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, planeAlpha, 0, 0, 0); - rgaReg.alpha_rop_flag |= (1 << 9); //real color mode + rgaReg.alpha_rop_flag |= (1 << 9); //real color mode - break; + break; - case 0x0501:/* dst over , no need premultiplied. */ - if (perpixelAlpha && planeAlpha < 255) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha , 1, 4, 0); - else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, planeAlpha , 1, 4, 0); - else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, planeAlpha , 1, 4, 0); - break; + case 0x0501:/* dst over , no need premultiplied. */ + if (perpixelAlpha && planeAlpha < 255) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha , 1, 4, 0); + else if (perpixelAlpha) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, planeAlpha , 1, 4, 0); + else + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, planeAlpha , 1, 4, 0); + break; - case 0x0504:/* dst over, need premultiplied. */ - if (perpixelAlpha && planeAlpha < 255) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha , 1, 4, 0); - else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, planeAlpha , 1, 4, 0); - else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, planeAlpha , 1, 4, 0); + case 0x0504:/* dst over, need premultiplied. */ + if (perpixelAlpha && planeAlpha < 255) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha , 1, 4, 0); + else if (perpixelAlpha) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, planeAlpha , 1, 4, 0); + else + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, planeAlpha , 1, 4, 0); - rgaReg.alpha_rop_flag |= (1 << 9); //real color mode - break; + rgaReg.alpha_rop_flag |= (1 << 9); //real color mode + break; + case 0x0100: + default: + /* Tips: BLENDING_NONE is non-zero value, handle zero value as + * BLENDING_NONE. */ + /* C = Cs + * A = As */ + break; + } + } else if (blend > 0) { + /* botn not use global alpha. */ + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, planeAlpha , 1, blend & 0xfff, 0); - case 0x0100: - default: - /* Tips: BLENDING_NONE is non-zero value, handle zero value as - * BLENDING_NONE. */ - /* C = Cs - * A = As */ - break; + /* need to pre-multiply. */ + if ((blend >> 12) & 1) + rgaReg.alpha_rop_flag |= (1 << 9); } /* discripe a picture need high stride.If high stride not to be set, need use height as high stride. */ diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index 6303619..54bf8bd 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -1638,25 +1638,37 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r srcinfo.blend = 0x2; break; case IM_ALPHA_BLEND_SRC_OVER: - srcinfo.blend = (usage & IM_ALPHA_BLEND_PRE_MUL) ? 0x405 : 0x105; + srcinfo.blend = 0x3; + break; + case IM_ALPHA_BLEND_DST_OVER: + srcinfo.blend = 0x4; break; case IM_ALPHA_BLEND_SRC_IN: + srcinfo.blend = 0x5; break; case IM_ALPHA_BLEND_DST_IN: + srcinfo.blend = 0x6; break; case IM_ALPHA_BLEND_SRC_OUT: + srcinfo.blend = 0x7; break; - case IM_ALPHA_BLEND_DST_OVER: - srcinfo.blend = (usage & IM_ALPHA_BLEND_PRE_MUL) ? 0x504 : 0x501; + case IM_ALPHA_BLEND_DST_OUT: + srcinfo.blend = 0x8; break; case IM_ALPHA_BLEND_SRC_ATOP: + srcinfo.blend = 0x9; break; - case IM_ALPHA_BLEND_DST_OUT: + case IM_ALPHA_BLEND_DST_ATOP: + srcinfo.blend = 0xa; break; case IM_ALPHA_BLEND_XOR: + srcinfo.blend = 0xb; break; } + if (usage & IM_ALPHA_BLEND_PRE_MUL) + srcinfo.blend |= (1 << 12); + if(srcinfo.blend == 0) IM_LOGE("rga_im2d: Could not find blend usage : 0x%x \n", usage); From acfc14ae14f350ed6b254cd65a5ca56a08a3688f Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 15 Aug 2023 01:57:32 +0000 Subject: [PATCH 02/46] docs: Update FAQ Added some Q&A about RGA2 32bit mmu (within 4G) and multi-core scheduling. Change-Id: I89ebd35a1025c7f469a705f7e4241b3f1dcf8b30 Signed-off-by: Yu Qiaowei --- docs/Rockchip_FAQ_RGA_CN.md | 68 ++++++++++++++++++++++++++----------- docs/Rockchip_FAQ_RGA_EN.md | 58 +++++++++++++++++++++++-------- 2 files changed, 91 insertions(+), 35 deletions(-) diff --git a/docs/Rockchip_FAQ_RGA_CN.md b/docs/Rockchip_FAQ_RGA_CN.md index 6f5c3a1..78a8a63 100644 --- a/docs/Rockchip_FAQ_RGA_CN.md +++ b/docs/Rockchip_FAQ_RGA_CN.md @@ -193,7 +193,7 @@ https://eyun.baidu.com/s/3i6sbsDR setprop vendor.rga.log_level 6 ``` - + - Linux平台 @@ -213,7 +213,7 @@ https://eyun.baidu.com/s/3i6sbsDR export ROCKCHIP_RGA_LOG_LEVEL=6 ``` - + #### 日志说明 @@ -453,7 +453,7 @@ help: - msg模式 - RGA Device Driver、RGA2 Device Driver - + ``` rga2: open rga2 test MSG! //msg日志开启打印。 rga2: cmd is RGA2_GET_VERSION //获取版本号功能，每个进程第一次调用librga时会查询硬件版本。 @@ -467,11 +467,11 @@ help: rga2: yuv2rgb mode is 0 //csc模式 rga2: *** rga2_blit_sync proc *** ``` - + - RGA multicore Device Driver - + - 内存管理器日志 - + ``` rga: import buffer info: rga_common: external: memory = 0xb400007458406000, type = virt_addr @@ -480,9 +480,9 @@ help: //w/h/f：以图像画布的形式描述内存大小，size：内存大小 rga_dma_buf: iova_align size = 3686400 //iova对齐后的大小 ``` - + - 任务请求日志 - + ``` rga: Blit mode: request id = 192732 //运行模式以及request id rga_debugger: render_mode = 0, bitblit_mode=0, rotate_mode = 0 @@ -500,9 +500,9 @@ help: rga_debugger: set core = 0, priority = 0, in_fence_fd = -1 //set_core：用户态指定的核心，priority：用户态指定的优先级，in_fence_fd：用户态传递的acquire_fence fd ``` - + - 硬件匹配日志 - + ``` rga_policy: start policy on core = 1 rga_policy: start policy on core = 2 @@ -511,9 +511,9 @@ help: rga_policy: optional_cores = 3 //当前请求可匹配的硬件核心合集 rga_policy: assign core: 1 //匹配后绑定的硬件核心标识 ``` - + - 对应硬件参数日志 - + ``` rga3_reg: render_mode:bitblt, bitblit_mode=0, rotate_mode:0 rga3_reg: win0: y = ffc70000 uv = ffd51000 v = ffd89400 src_w = 1280 src_h = 720 @@ -868,9 +868,21 @@ index 02938b0..10a1dc4 100644 -**Q1.8**：为什么当搭载8G DDR时，RGA效率较于4G时性能下降严重？ +**Q1.8**：调用RGA时为什么会有较高的CPU负载？ + +**A1.8**：调用RGA时除了基础必要的CPU负载外，有以下几种情况会导致增加较高的额外CPU负载： + +​ 1). 当使用虚拟地址调用RGA时，虚拟地址本身是CPU的访问地址，要通过当前进程的映射表转换为硬件可识别的离散的物理地址表是通过CPU查询、计算的，因此会引入额外的CPU负载。通常不建议在实际的产品场景中使用虚拟地址调用RGA，更建议使用dma-buf fd来调用RGA，除非业务逻辑上仅存在虚拟地址并不在意这部分CPU负载损耗。 -**A1.8**：由于部分RGA1/RGA2的IOMMU仅支持最大32位的物理地址，而RGA Device Driver、RGA2 Device Driver中对于不满足硬件内存要求的调用申请，默认是通过swiotlb机制进行访问访问受限制的内存（原理上相当于通过CPU将高位内存拷贝至复合硬件要求的低位内存中，再交由硬件进行处理，处理完毕后再通过CPU将低位内存搬运回目标的高位内存上。）因此效率十分低下，通常在正常耗时的3-4倍之间浮动，并且引入受CPU负载影响。 +​ 2). 当使用的虚拟地址是cacheable的，由于使能了cache，RGA驱动会在硬件访问内存前后强制同步cache数据，因此会增加CPU同步cache和内存的负载。由于常见的虚拟地址分配器并不是设计用于给其他硬件访问的，并存在同步cache的接口，因此驱动针对虚拟地址强制同步cache也是必要的。 + +​ 3). 当时用dma-buf fd调用RGA时，有些分配器默认分配的是cacheable的buffer，并且kernel中dma-buf的处理会强制同步cache的情况，这是也会存在每次调用RGA时会有较大的CPU负载，也是因为CPU同步cache和内存引入的负载。该种情况下建议分配禁用cache的dma-buf。 + + + +**Q1.9**：为什么当搭载8G DDR时，RGA效率较于4G时性能下降严重？ + +**A1.9**：由于部分RGA1/RGA2的IOMMU仅支持最大32位的物理地址，而RGA Device Driver、RGA2 Device Driver中对于不满足硬件内存要求的调用申请，默认是通过swiotlb机制进行访问访问受限制的内存（原理上相当于通过CPU将高位内存拷贝至复合硬件要求的低位内存中，再交由硬件进行处理，处理完毕后再通过CPU将低位内存搬运回目标的高位内存上。）因此效率十分低下，通常在正常耗时的3-4倍之间浮动，并且引入受CPU负载影响。 RGA Multicore Device Driver中针对访问受限制的内存会禁用swiotlb机制，直接通过调用失败的方式显示的通知调用者申请合理的内存再调用，来保证RGA的高效。通常伴随着以下日志： @@ -1189,11 +1201,23 @@ Date: Tue Nov 24 19:50:17 2020 +0800 -**A2.21**：调用RGA处理图像后出现黑色或绿色的小条纹，这是什么原因？ +**Q2.21**：调用RGA处理图像后出现黑色或绿色的小条纹，这是什么原因？ ​ ![image-cache-abnormal](RGA_FAQ.assets/image-cache-abnormal.png) -**Q2.21**：这是使用非虚拟地址调用时，buffer使能了cache，并且在CPU操作前后没有同步cache导致的。如果不了解如何同步cache可以参考samples/allocator_demo/src/rga_allocator_dma_cache_demo.cpp中的用法。 +**A2.21**：这是使用非虚拟地址调用时，buffer使能了cache，并且在CPU操作前后没有同步cache导致的。如果不了解如何同步cache可以参考samples/allocator_demo/src/rga_allocator_dma_cache_demo.cpp中的用法。 + + + +**Q2.22**：在RK3588上出现同一显示区域使用RGA缩放后画面抖动，这是什么原因导致的？ + +**A2.22**：由于RK3588比较特殊，搭载有两种RGA核心（一颗RGA2，两颗RGA3），它们在缩放算法上存在一些取数行为的差异导致结果会出现整体左上移/右下移的现象，因为在这种对显示效果有要求的场景上，建议指定核心的方式来避免出现算法差异引入的抖动问题。 + +​ 指定核心可以参考以下示例代码： + +​ **/samples/config_demo/src/rga_config_single_core_demo.cpp** + +​ **/samples/config_demo/src/rga_config_thread_core_demo.cpp** @@ -1238,15 +1262,15 @@ Fatal error: Failed to call RockChipRga interface, please use 'dmesg' command to **A3.2.2**：出现该标头报错说明当前RGA任务在驱动运行失败返回，具体原因需要通过dmesg查看驱动日志。 -​ **Q3.2.2.1**：“RgaBlit(1027) RGA_BLIT fail: Not a typewriter” +​ **Q3.2.2.1**：“RgaBlit(1027) RGA_BLIT fail: Not a typewriter” ​ **A3.2.2.1**：该报错通常为参数错误导致，建议检查一下缩放倍数、虚宽是否小于实宽与对应方向的偏移的和、对齐是否符合要求。建议新开发项目使用IM2D API，拥有更全面的检测报错机制，方便开发者节省大量的调试时间。 -​ **Q3.2.2.2**：“RgaBlit(1349) RGA_BLIT fail: Bad file descriptor” +​ **Q3.2.2.2**：“RgaBlit(1349) RGA_BLIT fail: Bad file descriptor” ​ **A3.2.2.2**：该报错为ioctl报错，标识当前传入的设备节点的fd无效，请尝试更新librga或确认RGA的初始化流程是否有被修改。 -​ **Q3.2.2.3**：“RgaBlit(1360) RGA_BLIT fail: Bad address” +​ **Q3.2.2.3**：“RgaBlit(1360) RGA_BLIT fail: Bad address” ​ **A3.2.2.4**：该报错通常为传入内核的src/src1/dst通道的内存地址存在问题导致（常见为越界），可以参照本文档 “日志获取与说明” —— “驱动调试节点” 小节，开启驱动日志，并定位出错的内存。 @@ -1278,7 +1302,7 @@ E rockchiprga: This output the user parameters when rga call blit fail //报错 ### kernel层报错 -**Q4.1**：“RGA2 failed to get vma, result = 32769, pageCount = 65537”报错是什么导致的？ +**Q4.1**：“RGA2 failed to get pte, result = -14, pageCount = 112”、“RGA2 failed to get vma, result = 32769, pageCount = 65537”报错是什么导致的？ **A4.1**：该报错通常为使用虚拟地址调用RGA时，虚拟地址的实际内存小于实际需要的内存大小（即根据图像参数计算出当前通道的图像需要多大的内存），只需检查buffer的大小即可，在一些申请和调用不是在同一处的场景下，可以在调用RGA前执行一遍memset对应图像的大小，确认是否为内存大小不足导致的问题。 @@ -1367,6 +1391,10 @@ Failed to call RockChipRga interface, please use 'dmesg' command to view driver 当芯片平台上仅搭载内存访问受限制的核心时，则调用RGA时必须申请符合搭载核心对内存要求的内存，解决方案同上场景2。 +4. 当使用DRM、malloc、new等不支持指定分配4G以内内存空间的内存的内存分配器时，也可以通过修改uboot的内存映射范围来解决。 + + uboot相关修改可以参考SDK文档中 **uboot开发文档->Chapter-8 调试手段->修改DDR容量** ，将内存映射范围全局限制在0~4G内存空间以内即可。 + **Q4.6**：“rga_policy: invalid function policy”、“rga_job: job assign failed”字样报错是什么导致的？ diff --git a/docs/Rockchip_FAQ_RGA_EN.md b/docs/Rockchip_FAQ_RGA_EN.md index 74825af..dcd0a28 100644 --- a/docs/Rockchip_FAQ_RGA_EN.md +++ b/docs/Rockchip_FAQ_RGA_EN.md @@ -184,12 +184,12 @@ https://eyun.baidu.com/s/3i6sbsDR - set log level： The log level is divided into full print (0), DEFAULT (1), DEBUG (3), INFO (4), WRANING (5), ERROR (6). - + ``` setprop vendor.rga.log_level 6 ``` - - + + - Linux @@ -200,16 +200,16 @@ https://eyun.baidu.com/s/3i6sbsDR ``` export ROCKCHIP_RGA_LOG=1 ``` - + - set log level： - + The log level is divided into full print (0), DEFAULT (1), DEBUG (3), INFO (4), WRANING (5), ERROR (6). - + ``` export ROCKCHIP_RGA_LOG_LEVEL=6 ``` - - + + #### Log Description @@ -454,9 +454,9 @@ For RGA problem debugging, logs are needed to confirm work of RGA hardware. When rga2: cmd is RGA2_GET_VERSION //Get version number, which queries hardware version the first time each process calls librga. rga2: cmd is RGA_BLIT_SYNC //Current working mode. rga2: render_mode:bitblt,bitblit_mode=0,rotate_mode:0 //Render_mode: display calling interface, bitblit_mode: current blending mode（0：two-channel mode A+B->B, 1: three-channel mode A+B->C, rotate_mode: rotation angle. - rga2: src : y=0 uv=b4000072cc8bc040 v=b4000072cc99d040 aw=1280 ah=720 vw=1280 vh=720 xoff=0 yoff=0 format=RGBA8888 + rga2: src : y=0 uv=b4000072cc8bc040 v=b4000072cc99d040 aw=1280 ah=720 vw=1280 vh=720 xoff=0 yoff=0 format=RGBA8888 //Parameters of src channel of image data y:fd, uv:virtual address, v：vw * vh + uv, aw and ah：actual width and height, the actual area of image. operation, vw、vh:virtual width and height, the size of image itself, xoff、yoff: offset in the x and y directions, format：image format. - rga2: dst : y=0 uv=b4000072cc535040 v=b4000072cc616040 aw=1280 ah=720 vw=1280 vh=720 xoff=0 yoff=0 format=RGBA8888 + rga2: dst : y=0 uv=b4000072cc535040 v=b4000072cc616040 aw=1280 ah=720 vw=1280 vh=720 xoff=0 yoff=0 format=RGBA8888 //Parameters of dst channel of image data. rga2: mmu : src=01 src1=00 dst=01 els=00 //MMU enabled flag，0 for close，1 for open. rga2: alpha : flag 0 mode0=0 mode1=0 //Configuration of blending. @@ -760,7 +760,7 @@ This section introduces common questions about RGA in the form of Q&A. If the pr ​ RGA3 ： 1920 × 1080 / （4 × 300000000） = 0.001728s -​ The actual consuming time depends on the type of memory used. The efficiency of different memory types from high to low is physical address > dma_fd > virtual address. +​ The actual consuming time depends on the type of memory used. The efficiency of different memory types from high to low is physical address > dma_fd > virtual address. ​ When the system is in no load, the actual time consuming of physical address is about 1.1-1.2 times of the theoretical time consuming, the actual time consuming of dma_fd is about 1.3-1.5 times of the theoretical time consuming, and the actual time consuming of virtual address is about 1.8-2.1 times of the theoretical time consuming, and is greatly affected by CPU. In general, we recommend developers to use dma_fd as the memory type passed in, which achieves great balance between accessibility and efficiency. Virtual addresses are only used as a simple and easy-to-use memory type when learning about RGA. The following table shows the actual test data of different RGA frequencies when the system is in no load on RK3566. @@ -862,9 +862,21 @@ index 02938b0..10a1dc4 100644 -**Q1.8**： When carrying 8G DDR, why is RGA efficiency worse than 4G? +**Q1.8:** Why is there a high CPU load when calling RGA? + +**A1.8:** In addition to the basic necessary CPU load when calling RGA, the following situations can cause additional high CPU load: + +​ 1). When calling RGA using virtual addresses, the virtual address itself is the CPU's access address, which needs to be converted into a hardware-recognizable discrete physical address table through the current process's mapping table by CPU querying and calculation. Therefore, additional CPU load will be introduced. It is generally not recommended to call RGA using virtual addresses in actual product scenarios, and it is recommended to use dma-buf fd to call RGA, unless the business logic only exists in virtual addresses and does not care about this part of CPU load. + +​ 2). When the virtual address used is cacheable, the RGA driver will force synchronization of cache data before and after hardware memory access due to the enabled cache, which will increase the CPU load of synchronizing cache and memory. Since common virtual address allocators are not designed for other hardware access and there is an interface for synchronizing cache, it is necessary for the driver to force synchronization of cache for virtual addresses. + +​ 3). When calling RGA using a dma-buf fd, some allocators by default allocate cacheable buffers, and the kernel's dma-buf handling enforces cache synchronization, which can result in significant CPU load every time RGA is called. This is due to the CPU load introduced by cache and memory synchronization. In this case, it is recommended to allocate a dma-buf with cache disabled. -**A1.8**：Since the current RGA1/RGA2 MMU only supports a maximum of 32 bits of physical address, therefore, with devices equipped with DDR of 4G or more, when a buffer with memory greater than 4G is passed to RGA, the RGA driver copies the data from the memory with the highest address to the memory reserved by swiotlb through the DMA interface and returns the corresponding address for RGA to read and write. After the work is finished, the result is copied to the previous high target address through dma, so the CPU involvement was increased, leading to a serious increase in the working time of the librga. If only RGA2/RGA1 is configured and the DDR of the device is greater than 4 GB, you are advised to use less than 4 GB memory when calling RGA to ensure RGA efficiency. + + +**Q1.9**： When carrying 8G DDR, why is RGA efficiency worse than 4G? + +**A1.9**：Since the current RGA1/RGA2 MMU only supports a maximum of 32 bits of physical address, therefore, with devices equipped with DDR of 4G or more, when a buffer with memory greater than 4G is passed to RGA, the RGA driver copies the data from the memory with the highest address to the memory reserved by swiotlb through the DMA interface and returns the corresponding address for RGA to read and write. After the work is finished, the result is copied to the previous high target address through dma, so the CPU involvement was increased, leading to a serious increase in the working time of the librga. If only RGA2/RGA1 is configured and the DDR of the device is greater than 4 GB, you are advised to use less than 4 GB memory when calling RGA to ensure RGA efficiency. In the RGA Multicore Device Driver, the swiotlb mechanism will be disabled for access-restricted memory, and the caller will be notified directly to apply for a reasonable memory re-call by displaying the failure of the call to ensure the efficiency of RGA. Usually accompanied by the following logs: @@ -1178,11 +1190,23 @@ Date: Tue Nov 24 19:50:17 2020 +0800 -**A2.21**：Small black or green stripes appear after calling RGA to process the image. What is the reason? +**Q2.21**：Small black or green stripes appear after calling RGA to process the image. What is the reason? ​ ![image-cache-abnormal](RGA_FAQ.assets/image-cache-abnormal.png) -**Q2.21**：This is caused by the buffer enabling the cache when using a call that is not a virtual address, and the cache is not synchronized before and after the CPU operation. If you don't know how to synchronize the cache, you can refer to the usage in samples/allocator_demo/src/rga_allocator_dma_cache_demo.cpp. +**A2.21**：This is caused by the buffer enabling the cache when using a call that is not a virtual address, and the cache is not synchronized before and after the CPU operation. If you don't know how to synchronize the cache, you can refer to the usage in samples/allocator_demo/src/rga_allocator_dma_cache_demo.cpp. + + + +**Q2.22**: What causes screen jitter when using RGA scaling on the same display area on RK3588? + +**A2.22**: Due to the special design of RK3588, which is equipped with two types of RGA cores (one RGA2 and two RGA3), there are differences in the sampling behavior of their scaling algorithms, resulting in an overall shift of the image to the upper left or lower right. In scenarios where display quality is important, it is recommended to specify the core to avoid jitter caused by algorithmic differences. + +​ You can refer to the following sample code for specifying the core: + +​ **/samples/config_demo/src/rga_config_single_core_demo.cpp** + +​ **/samples/config_demo/src/rga_config_thread_core_demo.cpp** @@ -1359,6 +1383,10 @@ When this error occurs, there are usually the following scenarios and correspond When the chip platform is only equipped with a core with limited memory access, you must apply for memory that meets the memory requirements of the core when calling RGA. The solution is the same as scenario 2 above. +4. When using DRM, malloc, new and other memory allocators that do not support the allocation of memory within 4G, it can also be solved by modifying the memory mapping range of uboot. + + For uboot-related modifications, please refer to **uboot开发文档->Chapter-8 调试手段->修改DDR容量** in the SDK documentation, and limit the memory mapping range globally to within 0~4G memory space. + **Q4.6**: What is the cause of the "rga_policy: invalid function policy" and "rga_job: job assign failed" errors? From a9ca05ab4379e62c97f2a4ef32fe5ea1d50db632 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 17 Aug 2023 01:47:49 +0000 Subject: [PATCH 03/46] samples: fix typos(fg => bg) Change-Id: Ia9dfba2b47a2a7ace85210d14b0075aedd31066a Signed-off-by: Yu Qiaowei --- samples/alpha_demo/src/rga_alpha_3channel_demo.cpp | 2 +- samples/alpha_demo/src/rga_alpha_colorkey_demo.cpp | 2 +- samples/alpha_demo/src/rga_alpha_demo.cpp | 2 +- samples/alpha_demo/src/rga_alpha_yuv_demo.cpp | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/samples/alpha_demo/src/rga_alpha_3channel_demo.cpp b/samples/alpha_demo/src/rga_alpha_3channel_demo.cpp index bcd80ed..407d8c5 100644 --- a/samples/alpha_demo/src/rga_alpha_3channel_demo.cpp +++ b/samples/alpha_demo/src/rga_alpha_3channel_demo.cpp @@ -77,7 +77,7 @@ int main() { printf("foreground image read err\n"); memset(fg_buf, 0xaa, fg_buf_size); } - if (0 != read_image_from_file(fg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 1)) { + if (0 != read_image_from_file(bg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 1)) { printf("background image read err\n"); memset(bg_buf, 0x66, bg_buf_size); } diff --git a/samples/alpha_demo/src/rga_alpha_colorkey_demo.cpp b/samples/alpha_demo/src/rga_alpha_colorkey_demo.cpp index 81ff3b5..8670f0a 100644 --- a/samples/alpha_demo/src/rga_alpha_colorkey_demo.cpp +++ b/samples/alpha_demo/src/rga_alpha_colorkey_demo.cpp @@ -71,7 +71,7 @@ int main() { printf("foreground image read err\n"); memset(fg_buf, 0xaa, fg_buf_size); } - if (0 != read_image_from_file(fg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 1)) { + if (0 != read_image_from_file(bg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 1)) { printf("background image read err\n"); memset(bg_buf, 0x66, bg_buf_size); } diff --git a/samples/alpha_demo/src/rga_alpha_demo.cpp b/samples/alpha_demo/src/rga_alpha_demo.cpp index f461bae..f1b775f 100644 --- a/samples/alpha_demo/src/rga_alpha_demo.cpp +++ b/samples/alpha_demo/src/rga_alpha_demo.cpp @@ -69,7 +69,7 @@ int main() { printf("foreground image read err\n"); memset(fg_buf, 0xaa, fg_buf_size); } - if (0 != read_image_from_file(fg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 1)) { + if (0 != read_image_from_file(bg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 1)) { printf("background image read err\n"); memset(bg_buf, 0x66, bg_buf_size); } diff --git a/samples/alpha_demo/src/rga_alpha_yuv_demo.cpp b/samples/alpha_demo/src/rga_alpha_yuv_demo.cpp index b69a4f1..c6f2e9b 100644 --- a/samples/alpha_demo/src/rga_alpha_yuv_demo.cpp +++ b/samples/alpha_demo/src/rga_alpha_yuv_demo.cpp @@ -82,7 +82,7 @@ int main() { printf("foreground image read err\n"); memset(fg_buf, 0xaa, fg_buf_size); } - if (0 != read_image_from_file(fg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 0)) { + if (0 != read_image_from_file(bg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 0)) { printf("background image read err\n"); memset(bg_buf, 0x66, bg_buf_size); } From eac159c4e9c6bda06eab8582d39c54d88a20d966 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 18 Aug 2023 02:50:57 +0000 Subject: [PATCH 04/46] im2d: optimize duplicate code Change-Id: I5217ba20b6fbd32669a9f9efc4cc155b7ccaebf0 Signed-off-by: Yu Qiaowei --- im2d_api/src/im2d.cpp | 136 ++++++++++-------------------------------- 1 file changed, 31 insertions(+), 105 deletions(-) diff --git a/im2d_api/src/im2d.cpp b/im2d_api/src/im2d.cpp index 8328048..9aff286 100644 --- a/im2d_api/src/im2d.cpp +++ b/im2d_api/src/im2d.cpp @@ -144,6 +144,18 @@ IM_API IM_STATUS releasebuffer_handle(rga_buffer_handle_t handle) { return rga_release_buffer(handle); } +static inline void set_default_rga_buffer(rga_buffer_t *buffer, + int width, int height, int format, + int wstride, int hstride) { + + buffer->width = width; + buffer->height = height; + buffer->wstride = wstride; + buffer->hstride = hstride; + buffer->format = format; + +} + #undef wrapbuffer_virtualaddr static rga_buffer_t wrapbuffer_virtualaddr(void* vir_addr, int width, int height, int format, @@ -153,11 +165,9 @@ static rga_buffer_t wrapbuffer_virtualaddr(void* vir_addr, memset(&buffer, 0, sizeof(rga_buffer_t)); buffer.vir_addr = vir_addr; - buffer.width = width; - buffer.height = height; - buffer.format = format; - buffer.wstride = wstride ? wstride : width; - buffer.hstride = hstride ? hstride : height; + set_default_rga_buffer(&buffer, width, height, format, + wstride ? wstride : width, + hstride ? hstride : height); return buffer; } @@ -171,11 +181,9 @@ static rga_buffer_t wrapbuffer_physicaladdr(void* phy_addr, memset(&buffer, 0, sizeof(rga_buffer_t)); buffer.phy_addr = phy_addr; - buffer.width = width; - buffer.height = height; - buffer.format = format; - buffer.wstride = wstride ? wstride : width; - buffer.hstride = hstride ? hstride : height; + set_default_rga_buffer(&buffer, width, height, format, + wstride ? wstride : width, + hstride ? hstride : height); return buffer; } @@ -188,12 +196,10 @@ static rga_buffer_t wrapbuffer_fd(int fd, memset(&buffer, 0, sizeof(rga_buffer_t)); - buffer.fd = fd; - buffer.width = width; - buffer.height = height; - buffer.format = format; - buffer.wstride = wstride ? wstride : width; - buffer.hstride = hstride ? hstride : height; + buffer.fd = fd; + set_default_rga_buffer(&buffer, width, height, format, + wstride ? wstride : width, + hstride ? hstride : height); return buffer; } @@ -206,12 +212,10 @@ IM_API rga_buffer_t wrapbuffer_handle(rga_buffer_handle_t handle, memset(&buffer, 0, sizeof(rga_buffer_t)); - buffer.handle = handle; - buffer.width = width; - buffer.height = height; - buffer.format = format; - buffer.wstride = wstride ? wstride : width; - buffer.hstride = hstride ? hstride : height; + buffer.handle = handle; + set_default_rga_buffer(&buffer, width, height, format, + wstride ? wstride : width, + hstride ? hstride : height); return buffer; } @@ -292,11 +296,9 @@ IM_API rga_buffer_t wrapbuffer_handle(buffer_handle_t hnd) { goto INVAILD; } - buffer.width = dstAttrs.at(AWIDTH); - buffer.height = dstAttrs.at(AHEIGHT); - buffer.wstride = dstAttrs.at(ASTRIDE); - buffer.hstride = dstAttrs.at(AHEIGHT); - buffer.format = dstAttrs.at(AFORMAT); + set_default_rga_buffer(&buffer, + dstAttrs.at(AWIDTH), dstAttrs.at(AHEIGHT), dstAttrs.at(AFORMAT), + dstAttrs.at(ASTRIDE), dstAttrs.at(AHEIGHT)); if (buffer.wstride % 16) { IM_LOGE("Graphicbuffer wstride needs align to 16, please align to 16 or use other buffer types, wstride = %d", buffer.wstride); @@ -308,45 +310,7 @@ IM_API rga_buffer_t wrapbuffer_handle(buffer_handle_t hnd) { } IM_API rga_buffer_t wrapbuffer_GraphicBuffer(sp buf) { - int ret = 0; - rga_buffer_t buffer; - std::vector dstAttrs; - - RockchipRga& rkRga(RockchipRga::get()); - - memset(&buffer, 0, sizeof(rga_buffer_t)); - - ret = rkRga.RkRgaGetBufferFd(buf->handle, &buffer.fd); - if (ret) - IM_LOGE("rga_im2d: get buffer fd fail: %s, hnd=%p", strerror(errno), (void*)(buf->handle)); - - if (buffer.fd <= 0) { - ret = rkRga.RkRgaGetHandleMapCpuAddress(buf->handle, &buffer.vir_addr); - if(!buffer.vir_addr) { - IM_LOGE("invaild GraphicBuffer, can not get fd and virtual address, hnd = %p", (void *)(buf->handle)); - goto INVAILD; - } - } - - ret = RkRgaGetHandleAttributes(buf->handle, &dstAttrs); - if (ret) { - IM_LOGE("handle get Attributes fail, ret = %d, hnd = %p", ret, (void *)(buf->handle)); - goto INVAILD; - } - - buffer.width = dstAttrs.at(AWIDTH); - buffer.height = dstAttrs.at(AHEIGHT); - buffer.wstride = dstAttrs.at(ASTRIDE); - buffer.hstride = dstAttrs.at(AHEIGHT); - buffer.format = dstAttrs.at(AFORMAT); - - if (buffer.wstride % 16) { - IM_LOGE("Graphicbuffer wstride needs align to 16, please align to 16 or use other buffer types, wstride = %d", buffer.wstride); - goto INVAILD; - } - -INVAILD: - return buffer; + return wrapbuffer_handle(buf->handle); } #if USE_AHARDWAREBUFFER @@ -358,47 +322,9 @@ IM_API rga_buffer_handle_t importbuffer_AHardwareBuffer(AHardwareBuffer *buf) { } IM_API rga_buffer_t wrapbuffer_AHardwareBuffer(AHardwareBuffer *buf) { - int ret = 0; - rga_buffer_t buffer; - std::vector dstAttrs; - - RockchipRga& rkRga(RockchipRga::get()); - - memset(&buffer, 0, sizeof(rga_buffer_t)); - GraphicBuffer *gbuffer = reinterpret_cast(buf); - ret = rkRga.RkRgaGetBufferFd(gbuffer->handle, &buffer.fd); - if (ret) - IM_LOGE("rga_im2d: get buffer fd fail: %s, hnd=%p", strerror(errno), (void*)(gbuffer->handle)); - - if (buffer.fd <= 0) { - ret = rkRga.RkRgaGetHandleMapCpuAddress(gbuffer->handle, &buffer.vir_addr); - if(!buffer.vir_addr) { - IM_LOGE("invaild GraphicBuffer, can not get fd and virtual address, hnd = %p", (void *)(gbuffer->handle)); - goto INVAILD; - } - } - - ret = RkRgaGetHandleAttributes(gbuffer->handle, &dstAttrs); - if (ret) { - IM_LOGE("handle get Attributes fail, ret = %d, hnd = %p", ret, (void *)(gbuffer->handle)); - goto INVAILD; - } - - buffer.width = dstAttrs.at(AWIDTH); - buffer.height = dstAttrs.at(AHEIGHT); - buffer.wstride = dstAttrs.at(ASTRIDE); - buffer.hstride = dstAttrs.at(AHEIGHT); - buffer.format = dstAttrs.at(AFORMAT); - - if (buffer.wstride % 16) { - IM_LOGE("Graphicbuffer wstride needs align to 16, please align to 16 or use other buffer types, wstride = %d", buffer.wstride); - goto INVAILD; - } - -INVAILD: - return buffer; + return wrapbuffer_handle(gbuffer->handle); } #endif #endif From 6a8c755c2936813d78a55f5571a3a8f23db3ffac Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 21 Aug 2023 06:27:01 +0000 Subject: [PATCH 05/46] docs: samples: add example file description Change-Id: I74d9841ba2b030227a242a52ac8b1f17828f7d77 Signed-off-by: Yu Qiaowei --- samples/README.md | 52 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/samples/README.md b/samples/README.md index 2b1cd6c..91e2912 100644 --- a/samples/README.md +++ b/samples/README.md @@ -121,3 +121,55 @@ $ chmod +x ./cmake_linux.sh $ ./cmake_linux.sh ``` + + +## 测试文件说明 + +### 示例文件 + +​ 用于测试的输入与输出二进制文件需提前准备好，在/sample/sample_file目录下，存放着默认的RGBA8888格式的源图像文件可以直接使用。 + +### 路径说明 + +​ 在示例代码中，可以通过配置以下宏定义来修改读取图像文件的路径： + +| 宏定义 | 描述 | +| --------------- | ------------------------------------------------------------ | +| LOCAL_FILE_PATH | read_image_from_file/write_image_to_file函数第二个传参，用于描述当前读/写示例文件的路径，默认路径为"/data" | + +### 示例文件名说明 + +​ 文件命名规则如下： + +``` +in%dw%d-h%d-%s.bin +out%dw%d-h%d-%s.bin + +示例： +1280×720 RGBA8888的输入图像： in0w1280-h720-rgba8888.bin +1280×720 RGBA8888的输出图像： out0w1280-h720-rgba8888.bin +``` + +​ 参数解释如下： + +> 输入文件为 in ， 输出文件为 out +> --->第一个%d 是文件的索引， 一般为 0， 用于区别格式及宽高完全相同的文件 +> --->第二个%d 是宽的意思， 这里的宽一般指虚宽 +> --->第三个%d 是高的意思， 这里的高一般指虚高 +> --->第四个%s 是格式的名字。 +> +> 预置测试的部分常用图像格式如下，其他格式对应字符串名可以查看rgaUtils.cpp中查看： + +| format（Android） | format（Linux） | name | +| :-------------------------------- | -------------------------- | ----------- | +| HAL_PIXEL_FORMAT_RGB_565 | RK_FORMAT_RGB_565 | "rgb565" | +| HAL_PIXEL_FORMAT_RGB_888 | RK_FORMAT_RGB_888 | "rgb888" | +| HAL_PIXEL_FORMAT_RGBA_8888 | RK_FORMAT_RGBA_8888 | "rgba8888" | +| HAL_PIXEL_FORMAT_RGBX_8888 | RK_FORMAT_RGBX_8888 | "rgbx8888" | +| HAL_PIXEL_FORMAT_BGRA_8888 | RK_FORMAT_BGRA_8888 | "bgra8888" | +| HAL_PIXEL_FORMAT_YCrCb_420_SP | RK_FORMAT_YCrCb_420_SP | "crcb420sp" | +| HAL_PIXEL_FORMAT_YCrCb_NV12 | RK_FORMAT_YCbCr_420_SP | "nv12" | +| HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO | / | "nv12" | +| HAL_PIXEL_FORMAT_YCrCb_NV12_10 | RK_FORMAT_YCbCr_420_SP_10B | "nv12_10" | + +> 通常demo中默认配置的输入图像分辨率为1280x720，格式为RGBA8888。因此需在对应配置的读文件路径下提前准备好in0w1280-h720-rgba8888.bin的源图像文件，图像合成模式还需额外准备好名为in1w1280-h720-rgba8888.bin的源图像文件。 From 88077daba4ea1f297d01799110dd3d2c8edc31ea Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 22 Aug 2023 10:03:28 +0000 Subject: [PATCH 06/46] im2d: add imsetOpacity() Perform the current alpha blending by configuring the opacity through global_alpha. Change-Id: I41d9ca6a857a8c7f3b60689fe88af25558a3bea5 Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 43 +++++++++++++++++++------------------- core/NormalRga.h | 9 ++++---- core/NormalRgaApi.cpp | 11 ++++++---- core/hardware/rga_ioctl.h | 6 +++++- im2d_api/im2d_buffer.h | 2 ++ im2d_api/src/im2d.cpp | 8 +++++++ im2d_api/src/im2d_impl.cpp | 10 ++++----- 7 files changed, 53 insertions(+), 36 deletions(-) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index 0d0d627..840468a 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -374,7 +374,7 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { int src1VirW,src1VirH,src1ActW,src1ActH,src1XPos,src1YPos; int scaleMode,rotateMode,orientation,ditherEn; int srcType,dstType,src1Type,srcMmuFlag,dstMmuFlag,src1MmuFlag; - int planeAlpha; + int fg_global_alpha, bg_global_alpha; int dstFd = -1; int srcFd = -1; int src1Fd = -1; @@ -687,7 +687,8 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { #endif /* blend bit[16:23] is to set global alpha. */ - planeAlpha = (blend & 0xFF0000) >> 16; + fg_global_alpha = (blend >> 16) & 0xff; + bg_global_alpha = (blend >> 24) & 0xff; /* determined by format, need pixel alpha or not. */ perpixelAlpha = NormalRgaFormatHasAlpha(RkRgaGetRgaFormat(relSrcRect.format)); @@ -702,42 +703,42 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { /* blend bit[0:15] is to set which way to blend, such as whether need glabal alpha, and so on. */ switch ((blend & 0xFFFF)) { case 0x0105:/* src over , no need to Premultiplied. */ - if (perpixelAlpha && planeAlpha < 255) { - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha, 1, 9, 0); + if (perpixelAlpha && fg_global_alpha < 0xff) { + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, fg_global_alpha, 0xff, 1, 9, 0); } else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0, 1, 3, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0xff, 0xff, 1, 3, 0); else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, planeAlpha, 0, 0, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, fg_global_alpha, 0xff, 0, 0, 0); break; case 0x0405:/* src over , need to Premultiplied. */ - if (perpixelAlpha && planeAlpha < 255) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha, 1, 9, 0); + if (perpixelAlpha && fg_global_alpha < 0xff) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, fg_global_alpha, 0xff, 1, 9, 0); else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0, 1, 3, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0xff, 0xff, 1, 3, 0); else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, planeAlpha, 0, 0, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, fg_global_alpha, 0xff, 0, 0, 0); rgaReg.alpha_rop_flag |= (1 << 9); //real color mode break; case 0x0501:/* dst over , no need premultiplied. */ - if (perpixelAlpha && planeAlpha < 255) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha , 1, 4, 0); + if (perpixelAlpha && bg_global_alpha < 0xff) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, 0xff, bg_global_alpha , 1, 4, 0); else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, planeAlpha , 1, 4, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0xff, 0xff , 1, 4, 0); else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, planeAlpha , 1, 4, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, 0xff, bg_global_alpha , 1, 4, 0); break; case 0x0504:/* dst over, need premultiplied. */ - if (perpixelAlpha && planeAlpha < 255) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, planeAlpha , 1, 4, 0); + if (perpixelAlpha && bg_global_alpha < 0xff) + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, 0xff, bg_global_alpha , 1, 4, 0); else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, planeAlpha , 1, 4, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0xff, 0xff , 1, 4, 0); else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, planeAlpha , 1, 4, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, 0xff, bg_global_alpha , 1, 4, 0); rgaReg.alpha_rop_flag |= (1 << 9); //real color mode break; @@ -749,12 +750,12 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { * A = As */ break; } - } else if (blend > 0) { + } else if ((blend & 0xfff) > 0) { /* botn not use global alpha. */ - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, planeAlpha , 1, blend & 0xfff, 0); + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, fg_global_alpha, bg_global_alpha , 1, blend & 0xfff, 0); /* need to pre-multiply. */ - if ((blend >> 12) & 1) + if ((blend >> 12) & 0x1) rgaReg.alpha_rop_flag |= (1 << 9); } diff --git a/core/NormalRga.h b/core/NormalRga.h index d8e5abb..a0ba4f6 100644 --- a/core/NormalRga.h +++ b/core/NormalRga.h @@ -172,10 +172,11 @@ int NormalRgaSetRopMaskInfo(struct rga_req *msg, /* use dst alpha */ -int NormalRgaSetAlphaEnInfo(struct rga_req *msg, - unsigned int alpha_cal_mode, unsigned int alpha_mode, - unsigned int global_a_value, unsigned int PD_en, - unsigned int PD_mode, unsigned int dst_alpha_en ); +int NormalRgaSetAlphaEnInfo(struct rga_req *msg, + unsigned int alpha_cal_mode, unsigned int alpha_mode, + unsigned int fg_global_alpha, unsigned int bg_global_alpha, + unsigned int PD_en, unsigned int PD_mode, + unsigned int dst_alpha_en); diff --git a/core/NormalRgaApi.cpp b/core/NormalRgaApi.cpp index 0679b8f..6c920ff 100644 --- a/core/NormalRgaApi.cpp +++ b/core/NormalRgaApi.cpp @@ -446,19 +446,22 @@ int NormalRgaSetRopMaskInfo(struct rga_req *msg, int NormalRgaSetAlphaEnInfo(struct rga_req *msg, unsigned int alpha_cal_mode, unsigned int alpha_mode, - unsigned int global_a_value, unsigned int PD_en, - unsigned int PD_mode, unsigned int dst_alpha_en ) { + unsigned int fg_global_alpha, unsigned int bg_global_alpha, + unsigned int PD_en, unsigned int PD_mode, + unsigned int dst_alpha_en) { msg->alpha_rop_flag |= 1; msg->alpha_rop_flag |= ((PD_en & 1) << 3); msg->alpha_rop_flag |= ((alpha_cal_mode & 1) << 4); - msg->alpha_global_value = global_a_value; + // msg->alpha_global_value = global_a_value; + msg->fg_global_alpha = fg_global_alpha; + msg->bg_global_alpha = bg_global_alpha; + msg->alpha_rop_mode |= (alpha_mode & 3); msg->alpha_rop_mode |= (dst_alpha_en << 5); msg->PD_mode = PD_mode; - return 1; } diff --git a/core/hardware/rga_ioctl.h b/core/hardware/rga_ioctl.h index de593de..8fef6fa 100644 --- a/core/hardware/rga_ioctl.h +++ b/core/hardware/rga_ioctl.h @@ -453,7 +453,11 @@ struct rga_req { rga_pre_intr_info_t pre_intr_info; - uint8_t reservr[59]; + /* global alpha */ + uint8_t fg_global_alpha; + uint8_t bg_global_alpha; + + uint8_t reservr[57]; }; struct rga_user_request { diff --git a/im2d_api/im2d_buffer.h b/im2d_api/im2d_buffer.h index 41dc60e..5722734 100644 --- a/im2d_api/im2d_buffer.h +++ b/im2d_api/im2d_buffer.h @@ -176,4 +176,6 @@ IM_API rga_buffer_t wrapbuffer_handle(rga_buffer_handle_t handle, int wstride, int hstride); #endif +void imsetOpacity(rga_buffer_t *buf, uint8_t alpha); + #endif /* #ifndef _im2d_buffer_h_ */ diff --git a/im2d_api/src/im2d.cpp b/im2d_api/src/im2d.cpp index 9aff286..01473ca 100644 --- a/im2d_api/src/im2d.cpp +++ b/im2d_api/src/im2d.cpp @@ -154,6 +154,9 @@ static inline void set_default_rga_buffer(rga_buffer_t *buffer, buffer->hstride = hstride; buffer->format = format; + buffer->global_alpha = 0xff; + buffer->color_space_mode = IM_COLOR_SPACE_DEFAULT; + buffer->rd_mode = IM_RASTER_MODE; } #undef wrapbuffer_virtualaddr @@ -329,6 +332,11 @@ IM_API rga_buffer_t wrapbuffer_AHardwareBuffer(AHardwareBuffer *buf) { #endif #endif +void imsetOpacity(rga_buffer_t *buf, uint8_t alpha) { + buf->global_alpha = alpha; +} + + IM_API const char* querystring(int name) { bool all_output = 0, all_output_prepared = 0; int rga_version = 0; diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index 54bf8bd..4d8c329 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -1673,16 +1673,14 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r IM_LOGE("rga_im2d: Could not find blend usage : 0x%x \n", usage); /* set global alpha */ - if (src.global_alpha > 0) - srcinfo.blend ^= src.global_alpha << 16; - else { - srcinfo.blend ^= 0xFF << 16; - } + srcinfo.blend |= (src.global_alpha & 0xff) << 16; + srcinfo.blend |= (dst.global_alpha & 0xff) << 24; } /* color key */ if (usage & IM_ALPHA_COLORKEY_MASK) { - srcinfo.blend = 0xff0105; + if (!(srcinfo.blend & 0xfff)) + srcinfo.blend |= 0xffff1001; srcinfo.colorkey_en = 1; srcinfo.colorkey_min = opt.colorkey_range.min; From 7cd840a4e44ac934947a1472c67ee3f381a06793 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Wed, 23 Aug 2023 02:08:48 +0000 Subject: [PATCH 07/46] replace magic numbers with enum Change-Id: Idd34cdf5416917f36706e0ace7d4782027f01c64 Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 73 ++++++++++---------------------------- core/hardware/rga_ioctl.h | 16 +++++++++ im2d_api/src/im2d_impl.cpp | 22 ++++++------ 3 files changed, 46 insertions(+), 65 deletions(-) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index 840468a..a9063c3 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -686,72 +686,37 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { } #endif - /* blend bit[16:23] is to set global alpha. */ - fg_global_alpha = (blend >> 16) & 0xff; - bg_global_alpha = (blend >> 24) & 0xff; - /* determined by format, need pixel alpha or not. */ perpixelAlpha = NormalRgaFormatHasAlpha(RkRgaGetRgaFormat(relSrcRect.format)); if(is_out_log()) ALOGE("blend = %x , perpixelAlpha = %d",blend,perpixelAlpha); - /* Compatible with legacy blend mode. */ - if (blend == 0x405 || blend == 0x504 || - blend == 0x105 || blend == 0x501 || - blend == 0x100) { - /* blend bit[0:15] is to set which way to blend, such as whether need glabal alpha, and so on. */ - switch ((blend & 0xFFFF)) { - case 0x0105:/* src over , no need to Premultiplied. */ - if (perpixelAlpha && fg_global_alpha < 0xff) { - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, fg_global_alpha, 0xff, 1, 9, 0); - } else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0xff, 0xff, 1, 3, 0); - else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, fg_global_alpha, 0xff, 0, 0, 0); - break; - - case 0x0405:/* src over , need to Premultiplied. */ - if (perpixelAlpha && fg_global_alpha < 0xff) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, fg_global_alpha, 0xff, 1, 9, 0); - else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0xff, 0xff, 1, 3, 0); - else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 0, fg_global_alpha, 0xff, 0, 0, 0); - - rgaReg.alpha_rop_flag |= (1 << 9); //real color mode + if (blend & 0xfff) { + /* blend bit[16:23] is to set global alpha. */ + fg_global_alpha = (blend >> 16) & 0xff; + bg_global_alpha = (blend >> 24) & 0xff; + switch (blend) { + case 0x405: + blend = RGA_ALPHA_BLEND_SRC_OVER; + blend |= 0x1 << 12; break; - - case 0x0501:/* dst over , no need premultiplied. */ - if (perpixelAlpha && bg_global_alpha < 0xff) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, 0xff, bg_global_alpha , 1, 4, 0); - else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0xff, 0xff , 1, 4, 0); - else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, 0xff, bg_global_alpha , 1, 4, 0); + case 0x504: + blend = RGA_ALPHA_BLEND_DST_OVER; + blend |= 0x1 << 12; break; - - case 0x0504:/* dst over, need premultiplied. */ - if (perpixelAlpha && bg_global_alpha < 0xff) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 2, 0xff, bg_global_alpha , 1, 4, 0); - else if (perpixelAlpha) - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, 0xff, 0xff , 1, 4, 0); - else - NormalRgaSetAlphaEnInfo(&rgaReg, 1, 3, 0xff, bg_global_alpha , 1, 4, 0); - - rgaReg.alpha_rop_flag |= (1 << 9); //real color mode + case 0x105: + blend = RGA_ALPHA_BLEND_SRC_OVER; break; - case 0x0100: - default: - /* Tips: BLENDING_NONE is non-zero value, handle zero value as - * BLENDING_NONE. */ - /* C = Cs - * A = As */ + case 0x501: + blend = RGA_ALPHA_BLEND_DST_OVER; + break; + case 0x100: + blend = RGA_ALPHA_BLEND_SRC; break; } - } else if ((blend & 0xfff) > 0) { - /* botn not use global alpha. */ + NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, fg_global_alpha, bg_global_alpha , 1, blend & 0xfff, 0); /* need to pre-multiply. */ diff --git a/core/hardware/rga_ioctl.h b/core/hardware/rga_ioctl.h index 8fef6fa..313f4c7 100644 --- a/core/hardware/rga_ioctl.h +++ b/core/hardware/rga_ioctl.h @@ -125,6 +125,22 @@ enum { rotate_mode3 = 0x3, /* y_mirror */ }; +enum rga_alpha_blend_mode { + RGA_ALPHA_NONE = 0, + RGA_ALPHA_BLEND_SRC, + RGA_ALPHA_BLEND_DST, + RGA_ALPHA_BLEND_SRC_OVER, + RGA_ALPHA_BLEND_DST_OVER, + RGA_ALPHA_BLEND_SRC_IN, + RGA_ALPHA_BLEND_DST_IN, + RGA_ALPHA_BLEND_SRC_OUT, + RGA_ALPHA_BLEND_DST_OUT, + RGA_ALPHA_BLEND_SRC_ATOP, + RGA_ALPHA_BLEND_DST_ATOP, + RGA_ALPHA_BLEND_XOR, + RGA_ALPHA_BLEND_CLEAR, +}; + typedef struct rga_img_info_t { uint64_t yrgb_addr; /* yrgb mem addr */ uint64_t uv_addr; /* cb/cr mem addr */ diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index 4d8c329..a36fa30 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -1632,37 +1632,37 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r if (usage & IM_ALPHA_BLEND_MASK) { switch(usage & IM_ALPHA_BLEND_MASK) { case IM_ALPHA_BLEND_SRC: - srcinfo.blend = 0x1; + srcinfo.blend = RGA_ALPHA_BLEND_SRC; break; case IM_ALPHA_BLEND_DST: - srcinfo.blend = 0x2; + srcinfo.blend = RGA_ALPHA_BLEND_DST; break; case IM_ALPHA_BLEND_SRC_OVER: - srcinfo.blend = 0x3; + srcinfo.blend = RGA_ALPHA_BLEND_SRC_OVER; break; case IM_ALPHA_BLEND_DST_OVER: - srcinfo.blend = 0x4; + srcinfo.blend = RGA_ALPHA_BLEND_DST_OVER; break; case IM_ALPHA_BLEND_SRC_IN: - srcinfo.blend = 0x5; + srcinfo.blend = RGA_ALPHA_BLEND_SRC_IN; break; case IM_ALPHA_BLEND_DST_IN: - srcinfo.blend = 0x6; + srcinfo.blend = RGA_ALPHA_BLEND_DST_IN; break; case IM_ALPHA_BLEND_SRC_OUT: - srcinfo.blend = 0x7; + srcinfo.blend = RGA_ALPHA_BLEND_SRC_OUT; break; case IM_ALPHA_BLEND_DST_OUT: - srcinfo.blend = 0x8; + srcinfo.blend = RGA_ALPHA_BLEND_DST_OUT; break; case IM_ALPHA_BLEND_SRC_ATOP: - srcinfo.blend = 0x9; + srcinfo.blend = RGA_ALPHA_BLEND_SRC_ATOP; break; case IM_ALPHA_BLEND_DST_ATOP: - srcinfo.blend = 0xa; + srcinfo.blend = RGA_ALPHA_BLEND_DST_ATOP; break; case IM_ALPHA_BLEND_XOR: - srcinfo.blend = 0xb; + srcinfo.blend = RGA_ALPHA_BLEND_XOR; break; } From 825ec0edc079e919e7c88bd68dd391bb1597de2e Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 24 Aug 2023 17:38:30 +0800 Subject: [PATCH 08/46] full_csc support RGB2YUV 709 limit range Change-Id: I2d21a6c3c4562482b827feb306c199edbfa021cd Signed-off-by: Yu Qiaowei --- core/NormalRgaApi.cpp | 16 ++++++++++------ im2d_api/src/im2d_impl.cpp | 3 +++ include/rga.h | 1 + 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/core/NormalRgaApi.cpp b/core/NormalRgaApi.cpp index 6c920ff..4f6be28 100644 --- a/core/NormalRgaApi.cpp +++ b/core/NormalRgaApi.cpp @@ -882,6 +882,7 @@ int NormalRgaFullColorSpaceConvert(struct rga_req *msg, int color_space_mode) { static full_csc_float_t default_csc_float_table[] = { /* coe_00 * R + coe_01 * G + coe_02 * B + coe_off */ { { 0.299, 0.587, 0.114, 0 }, { -0.169, -0.331, 0.5, 128 }, { 0.5, -0.419, -0.081, 128 } }, //R2Y 601 full + { { 0.183, 0.614, 0.062, 16 }, { -0.101, -0.339, 0.439, 128 }, { 0.439, -0.399, -0.040, 128 } }, //R2Y 709 limit { { 0.213, 0.715, 0.072, 0 }, { -0.115, -0.385, 0.5, 128 }, { 0.5, -0.454, -0.046, 128 } }, //R2Y 709 full /* coe_00 * V + coe_01 * Y + coe_02 * U + coe_off */ { { -0.1826, 0.8588, -0.1014, 52.3554 }, { 0.1007, -0.0004, 0.8948, 0.5781 }, { 0.9005, 0, 0.0653, 4.3855 } }, //601 full range => 709 limit range @@ -897,24 +898,28 @@ int NormalRgaFullColorSpaceConvert(struct rga_req *msg, int color_space_mode) { fptr = &(default_csc_float_table[0]); break; - case rgb2yuv_709_full : + case rgb2yuv_709_limit: fptr = &(default_csc_float_table[1]); break; + case rgb2yuv_709_full : + fptr = &(default_csc_float_table[2]); + break; + case yuv2yuv_709_limit_2_601_limit : - fptr = &(default_csc_float_table[3]); + fptr = &(default_csc_float_table[4]); break; case yuv2yuv_601_full_2_709_limit : - fptr = &(default_csc_float_table[2]); + fptr = &(default_csc_float_table[3]); break; case yuv2yuv_709_full_2_601_limit : - fptr = &(default_csc_float_table[4]); + fptr = &(default_csc_float_table[5]); break; case yuv2yuv_709_full_2_601_full : - fptr = &(default_csc_float_table[5]); + fptr = &(default_csc_float_table[6]); break; case yuv2yuv_601_limit_2_709_limit : @@ -946,7 +951,6 @@ int NormalRgaFullColorSpaceConvert(struct rga_req *msg, int color_space_mode) { default_csc_table.coe_v.off = (int)(fptr->coe_v.off * factor +0.5); if (color_space_mode >> 8) { - msg->full_csc.flag = 1; memcpy(&msg->full_csc, &default_csc_table, sizeof(full_csc_t)); } diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index a36fa30..0ab72a3 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -1869,6 +1869,9 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r if (src.color_space_mode == IM_RGB_FULL && dst.color_space_mode == IM_YUV_BT709_FULL_RANGE) { dstinfo.color_space_mode = rgb2yuv_709_full; + } else if (src.color_space_mode == IM_RGB_FULL && + dst.color_space_mode == IM_YUV_BT709_LIMIT_RANGE) { + dstinfo.color_space_mode = rgb2yuv_709_limit; } else if (src.color_space_mode == IM_YUV_BT601_FULL_RANGE && dst.color_space_mode == IM_YUV_BT709_LIMIT_RANGE) { dstinfo.color_space_mode = yuv2yuv_601_full_2_709_limit; diff --git a/include/rga.h b/include/rga.h index 9b82b1b..988fc6e 100644 --- a/include/rga.h +++ b/include/rga.h @@ -155,6 +155,7 @@ enum { yuv2yuv_601_full_2_709_full = 0x8 << 8, //not support yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support yuv2yuv_709_full_2_601_full = 0xa << 8, //not support + rgb2yuv_709_limit = 0xb << 8, full_csc_mask = 0xf00, }; From 525680347143e5a9ee711bc629e29759ce48d402 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 28 Aug 2023 17:17:43 +0800 Subject: [PATCH 09/46] im2d: add imsetColorSpace() Change-Id: I9d22fdfd8d75030f071d40b91859e547c4a85712 Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 6 +- core/NormalRgaApi.cpp | 1 - im2d_api/im2d_buffer.h | 1 + im2d_api/src/im2d.cpp | 3 + im2d_api/src/im2d_impl.cpp | 148 +++++++++++++++++++++++++++++++------ include/rga.h | 5 ++ 6 files changed, 140 insertions(+), 24 deletions(-) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index a9063c3..4f4fc6e 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -1265,7 +1265,11 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { NormalRgaSetPatActiveInfo(&rgaReg, src1ActW, src1ActH, src1XPos, src1YPos); if (dst->color_space_mode & full_csc_mask) { - NormalRgaFullColorSpaceConvert(&rgaReg, dst->color_space_mode); + ret = NormalRgaFullColorSpaceConvert(&rgaReg, dst->color_space_mode); + if (ret < 0) { + ALOGE("Not support full csc mode [%x]\n", dst->color_space_mode); + return -EINVAL; + } } else { if (src1) { /* special config for yuv + rgb => rgb */ diff --git a/core/NormalRgaApi.cpp b/core/NormalRgaApi.cpp index 4f6be28..f6c17eb 100644 --- a/core/NormalRgaApi.cpp +++ b/core/NormalRgaApi.cpp @@ -927,7 +927,6 @@ int NormalRgaFullColorSpaceConvert(struct rga_req *msg, int color_space_mode) { case yuv2yuv_601_full_2_709_full : case yuv2yuv_709_limit_2_601_full : default : - printf("Not support full csc mode [%x]\n", color_space_mode); return -1; } diff --git a/im2d_api/im2d_buffer.h b/im2d_api/im2d_buffer.h index 5722734..20d419e 100644 --- a/im2d_api/im2d_buffer.h +++ b/im2d_api/im2d_buffer.h @@ -177,5 +177,6 @@ IM_API rga_buffer_t wrapbuffer_handle(rga_buffer_handle_t handle, #endif void imsetOpacity(rga_buffer_t *buf, uint8_t alpha); +void imsetColorSpace(rga_buffer_t *buf, IM_COLOR_SPACE_MODE mode); #endif /* #ifndef _im2d_buffer_h_ */ diff --git a/im2d_api/src/im2d.cpp b/im2d_api/src/im2d.cpp index 01473ca..c112b82 100644 --- a/im2d_api/src/im2d.cpp +++ b/im2d_api/src/im2d.cpp @@ -336,6 +336,9 @@ void imsetOpacity(rga_buffer_t *buf, uint8_t alpha) { buf->global_alpha = alpha; } +void imsetColorSpace(rga_buffer_t *buf, IM_COLOR_SPACE_MODE mode) { + buf->color_space_mode = mode; +} IM_API const char* querystring(int name) { bool all_output = 0, all_output_prepared = 0; diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index 0ab72a3..41f9d9e 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -1866,28 +1866,132 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r } } - if (src.color_space_mode == IM_RGB_FULL && - dst.color_space_mode == IM_YUV_BT709_FULL_RANGE) { - dstinfo.color_space_mode = rgb2yuv_709_full; - } else if (src.color_space_mode == IM_RGB_FULL && - dst.color_space_mode == IM_YUV_BT709_LIMIT_RANGE) { - dstinfo.color_space_mode = rgb2yuv_709_limit; - } else if (src.color_space_mode == IM_YUV_BT601_FULL_RANGE && - dst.color_space_mode == IM_YUV_BT709_LIMIT_RANGE) { - dstinfo.color_space_mode = yuv2yuv_601_full_2_709_limit; - } else if (src.color_space_mode == IM_YUV_BT709_LIMIT_RANGE && - dst.color_space_mode == IM_YUV_BT601_LIMIT_RANGE) { - dstinfo.color_space_mode = yuv2yuv_709_limit_2_601_limit; - } else if (src.color_space_mode == IM_YUV_BT709_FULL_RANGE && - dst.color_space_mode == IM_YUV_BT601_LIMIT_RANGE) { - dstinfo.color_space_mode = yuv2yuv_709_full_2_601_limit; - } else if (src.color_space_mode == IM_YUV_BT709_FULL_RANGE && - dst.color_space_mode == IM_YUV_BT601_FULL_RANGE) { - dstinfo.color_space_mode = yuv2yuv_709_full_2_601_full; - } else { - IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", - src.color_space_mode, dst.color_space_mode); - return IM_STATUS_NOT_SUPPORTED; + switch (src.color_space_mode) { + case IM_RGB_FULL: + switch (dst.color_space_mode) { + case IM_YUV_BT601_LIMIT_RANGE: + dstinfo.color_space_mode = IM_RGB_TO_YUV_BT601_LIMIT; + break; + case IM_YUV_BT601_FULL_RANGE: + dstinfo.color_space_mode = IM_RGB_TO_YUV_BT601_FULL; + break; + case IM_YUV_BT709_LIMIT_RANGE: + dstinfo.color_space_mode = rgb2yuv_709_limit; + break; + case IM_YUV_BT709_FULL_RANGE: + dstinfo.color_space_mode = rgb2yuv_709_full; + break; + case IM_RGB_FULL: + break; + case IM_RGB_CLIP: + default: + IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", + src.color_space_mode, dst.color_space_mode); + return IM_STATUS_NOT_SUPPORTED; + } + break; + + case IM_YUV_BT601_LIMIT_RANGE: + switch (dst.color_space_mode) { + case IM_RGB_FULL: + dstinfo.color_space_mode = IM_YUV_TO_RGB_BT601_LIMIT; + break; + case IM_YUV_BT601_FULL_RANGE: + dstinfo.color_space_mode = yuv2yuv_601_limit_2_601_full; + break; + case IM_YUV_BT709_LIMIT_RANGE: + dstinfo.color_space_mode = yuv2yuv_601_limit_2_709_limit; + break; + case IM_YUV_BT709_FULL_RANGE: + dstinfo.color_space_mode = yuv2yuv_601_limit_2_709_full; + break; + case IM_YUV_BT601_LIMIT_RANGE: + break; + case IM_RGB_CLIP: + default: + IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", + src.color_space_mode, dst.color_space_mode); + return IM_STATUS_NOT_SUPPORTED; + } + break; + + case IM_YUV_BT601_FULL_RANGE: + switch (dst.color_space_mode) { + case IM_RGB_FULL: + dstinfo.color_space_mode = IM_YUV_TO_RGB_BT601_FULL; + break; + case IM_YUV_BT601_LIMIT_RANGE: + dstinfo.color_space_mode = yuv2yuv_601_full_2_601_limit; + break; + case IM_YUV_BT709_LIMIT_RANGE: + dstinfo.color_space_mode = yuv2yuv_601_full_2_709_limit; + break; + case IM_YUV_BT709_FULL_RANGE: + dstinfo.color_space_mode = yuv2yuv_601_full_2_709_full; + break; + case IM_YUV_BT601_FULL_RANGE: + break; + case IM_RGB_CLIP: + default: + IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", + src.color_space_mode, dst.color_space_mode); + return IM_STATUS_NOT_SUPPORTED; + } + break; + + case IM_YUV_BT709_LIMIT_RANGE: + switch (dst.color_space_mode) { + case IM_RGB_FULL: + dstinfo.color_space_mode = IM_YUV_TO_RGB_BT709_LIMIT; + break; + case IM_YUV_BT601_LIMIT_RANGE: + dstinfo.color_space_mode = yuv2yuv_709_limit_2_601_limit; + break; + case IM_YUV_BT601_FULL_RANGE: + dstinfo.color_space_mode = yuv2yuv_709_limit_2_601_full; + break; + case IM_YUV_BT709_FULL_RANGE: + dstinfo.color_space_mode = yuv2yuv_709_limit_2_709_full; + break; + case IM_YUV_BT709_LIMIT_RANGE: + break; + case IM_RGB_CLIP: + default: + IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", + src.color_space_mode, dst.color_space_mode); + return IM_STATUS_NOT_SUPPORTED; + } + break; + + case IM_YUV_BT709_FULL_RANGE: + switch (dst.color_space_mode) { + case IM_RGB_FULL: + dstinfo.color_space_mode = yuv2rgb_709_full; + break; + case IM_YUV_BT601_LIMIT_RANGE: + dstinfo.color_space_mode = yuv2yuv_709_full_2_601_limit; + break; + case IM_YUV_BT601_FULL_RANGE: + dstinfo.color_space_mode = yuv2yuv_709_full_2_601_full; + break; + case IM_YUV_BT709_LIMIT_RANGE: + dstinfo.color_space_mode = yuv2yuv_709_full_2_709_limit; + break; + case IM_YUV_BT709_FULL_RANGE: + break; + case IM_RGB_CLIP: + default: + IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", + src.color_space_mode, dst.color_space_mode); + return IM_STATUS_NOT_SUPPORTED; + } + break; + + case IM_RGB_CLIP: + default: + IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", + src.color_space_mode, dst.color_space_mode); + return IM_STATUS_NOT_SUPPORTED; } } diff --git a/include/rga.h b/include/rga.h index 988fc6e..590424d 100644 --- a/include/rga.h +++ b/include/rga.h @@ -156,6 +156,11 @@ enum { yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support yuv2yuv_709_full_2_601_full = 0xa << 8, //not support rgb2yuv_709_limit = 0xb << 8, + yuv2rgb_709_full = 0xc << 8, //not support + yuv2yuv_601_limit_2_601_full = 0xd << 8, //not support + yuv2yuv_601_full_2_601_limit = 0xe << 8, //not support + yuv2yuv_709_limit_2_709_full = 0xf << 8, //not support + yuv2yuv_709_full_2_709_limit = 0x10 << 8, //not support full_csc_mask = 0xf00, }; From c821585769401ea732f0e43940b24190a7aced07 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 28 Aug 2023 17:34:16 +0800 Subject: [PATCH 10/46] toolchains: update toolchain_linux.cmake Change-Id: I32808c0b8d88e67cd19a7b8b67d3ef1c8a841f9c Signed-off-by: Yu Qiaowei --- toolchains/toolchain_linux.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/toolchain_linux.cmake b/toolchains/toolchain_linux.cmake index 058a820..f446557 100644 --- a/toolchains/toolchain_linux.cmake +++ b/toolchains/toolchain_linux.cmake @@ -1,4 +1,4 @@ -SET(TOOLCHAIN_HOME "/home1/yqw/linux/rk3588/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu") +SET(TOOLCHAIN_HOME "/home/yqw/workspace/linux/common/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu") SET(TOOLCHAIN_NAME "aarch64-rockchip1031-linux-gnu") # this is required From 3b2bab59c9c390ca34ca224596b70bcd353bdfb9 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Wed, 30 Aug 2023 18:33:45 +0800 Subject: [PATCH 11/46] normal: global_alpha: compatible with legacy configuration methods Change-Id: I57aa57acf990802105bccf81892437b1a2fc5b0d Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 1 + core/hardware/rga_ioctl.h | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index 4f4fc6e..e1140c6 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -717,6 +717,7 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { break; } + rgaReg.feature.global_alpha_en = true; NormalRgaSetAlphaEnInfo(&rgaReg, 1, 1, fg_global_alpha, bg_global_alpha , 1, blend & 0xfff, 0); /* need to pre-multiply. */ diff --git a/core/hardware/rga_ioctl.h b/core/hardware/rga_ioctl.h index 313f4c7..05cea77 100644 --- a/core/hardware/rga_ioctl.h +++ b/core/hardware/rga_ioctl.h @@ -473,7 +473,11 @@ struct rga_req { uint8_t fg_global_alpha; uint8_t bg_global_alpha; - uint8_t reservr[57]; + struct { + uint32_t global_alpha_en:1; + } feature; + + uint8_t reservr[53]; }; struct rga_user_request { From b0e4869d1f7efd1095595f622148e02149d4398d Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 31 Aug 2023 18:27:26 +0800 Subject: [PATCH 12/46] normal: full_csc: add full_csc clip config Change-Id: Ia59b26c9d0b1d2d5c03260cc40ef47f6e11f6ac3 Signed-off-by: Yu Qiaowei --- core/NormalRgaApi.cpp | 16 ++++++++++++++++ core/hardware/rga_ioctl.h | 15 ++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/core/NormalRgaApi.cpp b/core/NormalRgaApi.cpp index f6c17eb..53ccea6 100644 --- a/core/NormalRgaApi.cpp +++ b/core/NormalRgaApi.cpp @@ -877,6 +877,7 @@ int NormalRgaFullColorSpaceConvert(struct rga_req *msg, int color_space_mode) { int factor = 0; full_csc_float_t *fptr = NULL; full_csc_t default_csc_table; + struct rga_csc_clip *clip_ptr = NULL; /* ABGR => AUYV */ static full_csc_float_t default_csc_float_table[] = { @@ -891,35 +892,48 @@ int NormalRgaFullColorSpaceConvert(struct rga_req *msg, int color_space_mode) { { { 0.1955, 1, 0.1019, -38.0729 }, { -0.1104, 0, 0.9899, 15.4218 }, { 0.9836, 0, -0.0716, 11.2587 } }, //709 full range => 601 full range }; + static struct rga_csc_clip default_csc_clip_table[] = { + { { 0xff, 0x0}, { 0xff, 0x0} }, //yuv full range Y[255,0] UV[255,0], rgb full range RGB[255,0] + { { 0xeb, 0x10}, { 0xf0, 0x10} }, //yuv limit range Y[235,16] UV[240,16] + { { 0xeb, 0x10}, { 0xeb, 0x10} }, //rga limit range RGB[235,0] + }; + factor = 0x3ff; switch (color_space_mode) { case rgb2yuv_601_full : fptr = &(default_csc_float_table[0]); + clip_ptr = &(default_csc_clip_table[0]); break; case rgb2yuv_709_limit: fptr = &(default_csc_float_table[1]); + clip_ptr = &(default_csc_clip_table[1]); break; case rgb2yuv_709_full : fptr = &(default_csc_float_table[2]); + clip_ptr = &(default_csc_clip_table[0]); break; case yuv2yuv_709_limit_2_601_limit : fptr = &(default_csc_float_table[4]); + clip_ptr = &(default_csc_clip_table[1]); break; case yuv2yuv_601_full_2_709_limit : fptr = &(default_csc_float_table[3]); + clip_ptr = &(default_csc_clip_table[1]); break; case yuv2yuv_709_full_2_601_limit : fptr = &(default_csc_float_table[5]); + clip_ptr = &(default_csc_clip_table[1]); break; case yuv2yuv_709_full_2_601_full : fptr = &(default_csc_float_table[6]); + clip_ptr = &(default_csc_clip_table[0]); break; case yuv2yuv_601_limit_2_709_limit : @@ -951,6 +965,8 @@ int NormalRgaFullColorSpaceConvert(struct rga_req *msg, int color_space_mode) { if (color_space_mode >> 8) { memcpy(&msg->full_csc, &default_csc_table, sizeof(full_csc_t)); + memcpy(&msg->full_csc_clip, clip_ptr, sizeof(full_csc_t)); + msg->feature.full_csc_clip_en = true; } return 0; diff --git a/core/hardware/rga_ioctl.h b/core/hardware/rga_ioctl.h index 05cea77..d69f9c5 100644 --- a/core/hardware/rga_ioctl.h +++ b/core/hardware/rga_ioctl.h @@ -228,6 +228,16 @@ typedef struct full_csc_t { csc_coe_t coe_v; } full_csc_t; +struct rga_csc_range { + uint8_t max; + uint8_t min; +}; + +struct rga_csc_clip { + struct rga_csc_range y; + struct rga_csc_range uv; +}; + typedef struct rga_mosaic_info_ioctl { uint8_t enable; uint8_t mode; @@ -475,9 +485,12 @@ struct rga_req { struct { uint32_t global_alpha_en:1; + uint32_t full_csc_clip_en:1; } feature; - uint8_t reservr[53]; + struct rga_csc_clip full_csc_clip; + + uint8_t reservr[49]; }; struct rga_user_request { From 78859352fe4e73eee22424b897b8294bcf8100aa Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 7 Sep 2023 17:13:36 +0800 Subject: [PATCH 13/46] docs: guide: add RK3562 Change-Id: I46757c876cab1e01280d7f13f85bbb10666069b3 Signed-off-by: Yu Qiaowei --- docs/Rockchip_Developer_Guide_RGA_CN.md | 13 +++++++++---- docs/Rockchip_Developer_Guide_RGA_EN.md | 13 ++++++++++--- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/docs/Rockchip_Developer_Guide_RGA_CN.md b/docs/Rockchip_Developer_Guide_RGA_CN.md index d14287c..d524882 100644 --- a/docs/Rockchip_Developer_Guide_RGA_CN.md +++ b/docs/Rockchip_Developer_Guide_RGA_CN.md @@ -191,7 +191,7 @@ RGA (Raster Graphic Acceleration Unit)是一个独立的2D硬件加速器，可 8192x8192 2x2 4096x4096 - 90/180/270 Rotate
X/Y Mirror
Crop
1/16~16 scale
Alpha blend
Color key
Color fill
Color palette
ROP(NA for RV1108/RV1109/RK3566)
NN quantize(NA for RK3399/RV1108)
osd (only RV1106/RV1103)
IOMMU(32bit, RK3528为40bit，NA for RV1106/1103) + 90/180/270 Rotate
X/Y Mirror
Crop
1/16~16 scale
Alpha blend
Color key
Color fill
Color palette
ROP(NA for RV1108/RV1109/RK3566)
NN quantize(NA for RK3399/RV1108)
osd (only RV1106/RV1103)
IOMMU(32bit, RK3528/RK3562为40bit，NA for RV1106/1103) 2 @@ -234,6 +234,7 @@ RGA (Raster Graphic Acceleration Unit)是一个独立的2D硬件加速器，可 + > 注： > > 1). 单位时钟周期处理像素的能力为理论数据，实际运行性能表现与带宽、硬件频率等相关，列表数据仅供参考。 @@ -341,7 +342,7 @@ RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMA RK1808 - RGA2-Enhance + RGA2-Enhance Mclaren RK3399 RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMAT_ABGR_8888
RK_FORMAT_RGBX_8888
RK_FORMAT_BGRX_8888
RK_FORMAT_XRGB_8888
RK_FORMAT_XBGR_8888
RK_FORMAT_RGBA_4444
RK_FORMAT_BGRA_4444
RK_FORMAT_ARGB_4444
RK_FORMAT_ABGR_4444
RK_FORMAT_RGBA_5551
RK_FORMAT_BGRA_5551
RK_FORMAT_ARGB_5551
RK_FORMAT_ABGR_5551
RK_FORMAT_RGB_888
RK_FORMAT_BGR_888
RK_FORMAT_RGB_565
RK_FORMAT_BGR_565
RK_FORMAT_YCbCr_420_SP
RK_FORMAT_YCrCbr_420_SP
RK_FORMAT_YCbCr_422_SP
RK_FORMAT_YCrCbr_422_SP
RK_FORMAT_YCbCr_420_P
RK_FORMAT_YCrCbr_420_P
RK_FORMAT_YCbCr_422_P
RK_FORMAT_YCrCbr_422_P
RK_FORMAT_YCbCr_420_SP_10B
RK_FORMAT_YCrCb_420_SP_10B
RK_FORMAT_YCbCr_422_SP_10B
RK_FORMAT_YCrCb_422_SP_10B
RK_FORMAT_BPP1 (only for color palette)
RK_FORMAT_BPP2 (only for color palette)
RK_FORMAT_BPP4 (only for color palette)
RK_FORMAT_BPP8 (only for color palette) @@ -356,9 +357,9 @@ RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMA Puma RV1126/ RV1109 - RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMAT_ABGR_8888
RK_FORMAT_RGBX_8888
RK_FORMAT_BGRX_8888
RK_FORMAT_XRGB_8888
RK_FORMAT_XBGR_8888
RK_FORMAT_RGBA_4444
RK_FORMAT_BGRA_4444
RK_FORMAT_ARGB_4444
RK_FORMAT_ABGR_4444
RK_FORMAT_RGBA_5551
RK_FORMAT_BGRA_5551
RK_FORMAT_ARGB_5551
RK_FORMAT_ABGR_5551
RK_FORMAT_RGB_888
RK_FORMAT_BGR_888
RK_FORMAT_RGB_565
RK_FORMAT_BGR_565
RK_FORMAT_YCbCr_420_SP
RK_FORMAT_YCrCbr_420_SP
RK_FORMAT_YCbCr_422_SP
RK_FORMAT_YCrCbr_422_SP
RK_FORMAT_YCbCr_420_P
RK_FORMAT_YCrCbr_420_P
RK_FORMAT_YCbCr_422_P
RK_FORMAT_YCrCbr_422_P
RK_FORMAT_YUYV_422
RK_FORMAT_YVYU_422
RK_FORMAT_UYVY_422
RK_FORMAT_VYUY_422
RK_FORMAT_YCbCr_400
RK_FORMAT_YCbCr_420_SP_10B
RK_FORMAT_YCrCb_420_SP_10B
RK_FORMAT_YCbCr_422_SP_10B
RK_FORMAT_YCrCb_422_SP_10B
RK_FORMAT_BPP1 (only for color palette)
RK_FORMAT_BPP2 (only for color palette)
RK_FORMAT_BPP4 (only for color palette)
RK_FORMAT_BPP8 (only for color palette) + RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMAT_ABGR_8888
RK_FORMAT_RGBX_8888
RK_FORMAT_BGRX_8888
RK_FORMAT_XRGB_8888
RK_FORMAT_XBGR_8888
RK_FORMAT_RGBA_4444
RK_FORMAT_BGRA_4444
RK_FORMAT_ARGB_4444
RK_FORMAT_ABGR_4444
RK_FORMAT_RGBA_5551
RK_FORMAT_BGRA_5551
RK_FORMAT_ARGB_5551
RK_FORMAT_ABGR_5551
RK_FORMAT_RGB_888
RK_FORMAT_BGR_888
RK_FORMAT_RGB_565
RK_FORMAT_BGR_565
RK_FORMAT_YCbCr_420_SP
RK_FORMAT_YCrCbr_420_SP
RK_FORMAT_YCbCr_422_SP
RK_FORMAT_YCrCbr_422_SP
RK_FORMAT_YCbCr_420_P
RK_FORMAT_YCrCbr_420_P
RK_FORMAT_YCbCr_422_P
RK_FORMAT_YCrCbr_422_P
RK_FORMAT_YUYV_422
RK_FORMAT_YVYU_422
RK_FORMAT_UYVY_422
RK_FORMAT_VYUY_422
RK_FORMAT_YCbCr_400
RK_FORMAT_YCbCr_420_SP_10B
RK_FORMAT_YCrCb_420_SP_10B
RK_FORMAT_YCbCr_422_SP_10B
RK_FORMAT_YCrCb_422_SP_10B
RK_FORMAT_BPP1 (only for color palette)
RK_FORMAT_BPP2 (only for color palette)
RK_FORMAT_BPP4 (only for color palette)
RK_FORMAT_BPP8 (only for color palette) - + RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMAT_ABGR_8888
RK_FORMAT_RGBX_8888
RK_FORMAT_BGRX_8888
RK_FORMAT_XRGB_8888
RK_FORMAT_XBGR_8888
RK_FORMAT_RGBA_4444
RK_FORMAT_BGRA_4444
RK_FORMAT_ARGB_4444
RK_FORMAT_ABGR_4444
RK_FORMAT_RGBA_5551
RK_FORMAT_BGRA_5551
RK_FORMAT_ARGB_5551
RK_FORMAT_ABGR_5551
RK_FORMAT_RGB_888
RK_FORMAT_BGR_888
RK_FORMAT_RGB_565
RK_FORMAT_BGR_565
RK_FORMAT_YCbCr_420_SP
RK_FORMAT_YCrCbr_420_SP
RK_FORMAT_YCbCr_422_SP
RK_FORMAT_YCrCbr_422_SP
RK_FORMAT_YCbCr_420_P
RK_FORMAT_YCrCbr_420_P
RK_FORMAT_YCbCr_422_P
RK_FORMAT_YCrCbr_422_P
RK_FORMAT_YUYV_422
RK_FORMAT_YVYU_422
RK_FORMAT_UYVY_422
RK_FORMAT_VYUY_422
RK_FORMAT_YCbCr_400
RK_FORMAT_Y4 @@ -377,6 +378,9 @@ RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMA Bull RK3528 + Snipe + RK3562 + RGA3 Orion @@ -390,6 +394,7 @@ RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_RGBX_8888
RK_FORMA + > 注： > > 1). ”RK_FORMAT_YCbCr_400“格式即YUV格式仅取Y通道，常用于256（2的8次方）阶灰度图，这里需要注意由于是YUV格式存在RGB/YUV色域转换时需要留意色域配置，例如需要完整的256阶灰度图需要在转换时配置为full range。 diff --git a/docs/Rockchip_Developer_Guide_RGA_EN.md b/docs/Rockchip_Developer_Guide_RGA_EN.md index ab0511c..8b79bdb 100644 --- a/docs/Rockchip_Developer_Guide_RGA_EN.md +++ b/docs/Rockchip_Developer_Guide_RGA_EN.md @@ -339,7 +339,7 @@ RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMA RK1808 - RGA2-Enhance + RGA2-Enhance Mclaren RK3399 RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMAT_ABGR_8888
RK_FORMAT_RGBX_8888
RK_FORMAT_BGRX_8888
RK_FORMAT_XRGB_8888
RK_FORMAT_XBGR_8888
RK_FORMAT_RGBA_4444
RK_FORMAT_BGRA_4444
RK_FORMAT_ARGB_4444
RK_FORMAT_ABGR_4444
RK_FORMAT_RGBA_5551
RK_FORMAT_BGRA_5551
RK_FORMAT_ARGB_5551
RK_FORMAT_ABGR_5551
RK_FORMAT_RGB_888
RK_FORMAT_BGR_888
RK_FORMAT_RGB_565
RK_FORMAT_BGR_565
RK_FORMAT_YCbCr_420_SP
RK_FORMAT_YCrCbr_420_SP
RK_FORMAT_YCbCr_422_SP
RK_FORMAT_YCrCbr_422_SP
RK_FORMAT_YCbCr_420_P
RK_FORMAT_YCrCbr_420_P
RK_FORMAT_YCbCr_422_P
RK_FORMAT_YCrCbr_422_P
RK_FORMAT_YCbCr_420_SP_10B
RK_FORMAT_YCrCb_420_SP_10B
RK_FORMAT_YCbCr_422_SP_10B
RK_FORMAT_YCrCb_422_SP_10B
RK_FORMAT_BPP1 (only for color palette)
RK_FORMAT_BPP2 (only for color palette)
RK_FORMAT_BPP4 (only for color palette)
RK_FORMAT_BPP8 (only for color palette) @@ -354,9 +354,9 @@ RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMA Puma RV1126/ RV1109 - RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMAT_ABGR_8888
RK_FORMAT_RGBX_8888
RK_FORMAT_BGRX_8888
RK_FORMAT_XRGB_8888
RK_FORMAT_XBGR_8888
RK_FORMAT_RGBA_4444
RK_FORMAT_BGRA_4444
RK_FORMAT_ARGB_4444
RK_FORMAT_ABGR_4444
RK_FORMAT_RGBA_5551
RK_FORMAT_BGRA_5551
RK_FORMAT_ARGB_5551
RK_FORMAT_ABGR_5551
RK_FORMAT_RGB_888
RK_FORMAT_BGR_888
RK_FORMAT_RGB_565
RK_FORMAT_BGR_565
RK_FORMAT_YCbCr_420_SP
RK_FORMAT_YCrCbr_420_SP
RK_FORMAT_YCbCr_422_SP
RK_FORMAT_YCrCbr_422_SP
RK_FORMAT_YCbCr_420_P
RK_FORMAT_YCrCbr_420_P
RK_FORMAT_YCbCr_422_P
RK_FORMAT_YCrCbr_422_P
RK_FORMAT_YUYV_422
RK_FORMAT_YVYU_422
RK_FORMAT_UYVY_422
RK_FORMAT_VYUY_422
RK_FORMAT_YCbCr_400
RK_FORMAT_YCbCr_420_SP_10B
RK_FORMAT_YCrCb_420_SP_10B
RK_FORMAT_YCbCr_422_SP_10B
RK_FORMAT_YCrCb_422_SP_10B
RK_FORMAT_BPP1 (only for color palette)
RK_FORMAT_BPP2 (only for color palette)
RK_FORMAT_BPP4 (only for color palette)
RK_FORMAT_BPP8 (only for color palette) + RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMAT_ABGR_8888
RK_FORMAT_RGBX_8888
RK_FORMAT_BGRX_8888
RK_FORMAT_XRGB_8888
RK_FORMAT_XBGR_8888
RK_FORMAT_RGBA_4444
RK_FORMAT_BGRA_4444
RK_FORMAT_ARGB_4444
RK_FORMAT_ABGR_4444
RK_FORMAT_RGBA_5551
RK_FORMAT_BGRA_5551
RK_FORMAT_ARGB_5551
RK_FORMAT_ABGR_5551
RK_FORMAT_RGB_888
RK_FORMAT_BGR_888
RK_FORMAT_RGB_565
RK_FORMAT_BGR_565
RK_FORMAT_YCbCr_420_SP
RK_FORMAT_YCrCbr_420_SP
RK_FORMAT_YCbCr_422_SP
RK_FORMAT_YCrCbr_422_SP
RK_FORMAT_YCbCr_420_P
RK_FORMAT_YCrCbr_420_P
RK_FORMAT_YCbCr_422_P
RK_FORMAT_YCrCbr_422_P
RK_FORMAT_YUYV_422
RK_FORMAT_YVYU_422
RK_FORMAT_UYVY_422
RK_FORMAT_VYUY_422
RK_FORMAT_YCbCr_400
RK_FORMAT_YCbCr_420_SP_10B
RK_FORMAT_YCrCb_420_SP_10B
RK_FORMAT_YCbCr_422_SP_10B
RK_FORMAT_YCrCb_422_SP_10B
RK_FORMAT_BPP1 (only for color palette)
RK_FORMAT_BPP2 (only for color palette)
RK_FORMAT_BPP4 (only for color palette)
RK_FORMAT_BPP8 (only for color palette) - + RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMAT_ABGR_8888
RK_FORMAT_RGBX_8888
RK_FORMAT_BGRX_8888
RK_FORMAT_XRGB_8888
RK_FORMAT_XBGR_8888
RK_FORMAT_RGBA_4444
RK_FORMAT_BGRA_4444
RK_FORMAT_ARGB_4444
RK_FORMAT_ABGR_4444
RK_FORMAT_RGBA_5551
RK_FORMAT_BGRA_5551
RK_FORMAT_ARGB_5551
RK_FORMAT_ABGR_5551
RK_FORMAT_RGB_888
RK_FORMAT_BGR_888
RK_FORMAT_RGB_565
RK_FORMAT_BGR_565
RK_FORMAT_YCbCr_420_SP
RK_FORMAT_YCrCbr_420_SP
RK_FORMAT_YCbCr_422_SP
RK_FORMAT_YCrCbr_422_SP
RK_FORMAT_YCbCr_420_P
RK_FORMAT_YCrCbr_420_P
RK_FORMAT_YCbCr_422_P
RK_FORMAT_YCrCbr_422_P
RK_FORMAT_YUYV_422
RK_FORMAT_YVYU_422
RK_FORMAT_UYVY_422
RK_FORMAT_VYUY_422
RK_FORMAT_YUYV_420
RK_FORMAT_YVYU_420
RK_FORMAT_UYVY_420
RK_FORMAT_VYUY_420
RK_FORMAT_YCbCr_400
RK_FORMAT_Y4 @@ -372,6 +372,12 @@ RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_ARGB_8888
RK_FORMA Otter RV1106/1103 + Bull + RK3528 + + Snipe + RK3562 + RGA3 Orion @@ -386,6 +392,7 @@ RK_FORMAT_RGBA_8888
RK_FORMAT_BGRA_8888
RK_FORMAT_RGBX_8888
RK_FORMA + > Note: > > 1). The "RK_FORMAT_YCbCr_400" format means that the YUV format only takes the Y channel, and is often used in 256 (2 to the 8th power) grayscale images. Here, it should be noted that since the YUV format exists in the RGB/YUV color space conversion, you need to pay attention to the color space configuration , for example, a full 256-level grayscale image needs to be configured as full range during conversion. From 3ba89da6345a5566ac68611dc1e23aac26fc32a6 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 8 Sep 2023 09:53:37 +0800 Subject: [PATCH 14/46] samples: alpha: add global alpha demo Change-Id: Ibb546a30c11bb2ab53314d4ad6f26211f5ef07ab Signed-off-by: Yu Qiaowei --- samples/alpha_demo/src/CMakeLists.txt | 10 ++ .../src/rga_alpha_global_alpha_demo.cpp | 133 ++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 samples/alpha_demo/src/rga_alpha_global_alpha_demo.cpp diff --git a/samples/alpha_demo/src/CMakeLists.txt b/samples/alpha_demo/src/CMakeLists.txt index 232249d..69e646c 100644 --- a/samples/alpha_demo/src/CMakeLists.txt +++ b/samples/alpha_demo/src/CMakeLists.txt @@ -8,6 +8,16 @@ target_link_libraries(rga_alpha_demo ) install(TARGETS rga_alpha_demo DESTINATION ${CMAKE_INSTALL_BINDIR}) +# rga_alpha_global_alpha_demo +add_executable(rga_alpha_global_alpha_demo + rga_alpha_global_alpha_demo.cpp +) +target_link_libraries(rga_alpha_global_alpha_demo + utils_obj + ${RGA_LIB} +) +install(TARGETS rga_alpha_global_alpha_demo DESTINATION ${CMAKE_INSTALL_BINDIR}) + # rga_alpha_3channel_demo add_executable(rga_alpha_3channel_demo rga_alpha_3channel_demo.cpp diff --git a/samples/alpha_demo/src/rga_alpha_global_alpha_demo.cpp b/samples/alpha_demo/src/rga_alpha_global_alpha_demo.cpp new file mode 100644 index 0000000..8a48321 --- /dev/null +++ b/samples/alpha_demo/src/rga_alpha_global_alpha_demo.cpp @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2023 Rockchip Electronics Co., Ltd. + * Authors: + * YuQiaowei + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define LOG_NDEBUG 0 +#undef LOG_TAG +#define LOG_TAG "rga_alpha_global_alpha_demo" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "RgaUtils.h" +#include "im2d.hpp" + +#include "utils.h" + +#define LOCAL_FILE_PATH "/data" + +int main() { + int ret = 0; + int fg_width, fg_height, fg_format; + int bg_width, bg_height, bg_format; + char *fg_buf, *bg_buf; + int fg_buf_size, bg_buf_size; + + rga_buffer_t fg_img, bg_img; + rga_buffer_handle_t fg_handle, bg_handle; + + memset(&fg_img, 0, sizeof(fg_img)); + memset(&bg_img, 0, sizeof(bg_img)); + + fg_width = 1280; + fg_height = 720; + fg_format = RK_FORMAT_RGBA_8888; + + bg_width = 1280; + bg_height = 720; + bg_format = RK_FORMAT_YCbCr_420_SP; + + fg_buf_size = fg_width * fg_height * get_bpp_from_format(fg_format); + bg_buf_size = bg_width * bg_height * get_bpp_from_format(bg_format); + + fg_buf = (char *)malloc(fg_buf_size); + bg_buf = (char *)malloc(bg_buf_size); + + /* fill image data */ + if (0 != read_image_from_file(fg_buf, LOCAL_FILE_PATH, fg_width, fg_height, fg_format, 0)) { + printf("foreground image read err\n"); + memset(fg_buf, 0xaa, fg_buf_size); + } + if (0 != read_image_from_file(bg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 1)) { + printf("background image read err\n"); + memset(bg_buf, 0x66, bg_buf_size); + } + + fg_handle = importbuffer_virtualaddr(fg_buf, fg_buf_size); + bg_handle = importbuffer_virtualaddr(bg_buf, bg_buf_size); + if (fg_handle == 0 || bg_handle == 0) { + printf("importbuffer failed!\n"); + goto release_buffer; + } + + fg_img = wrapbuffer_handle(fg_handle, fg_width, fg_height, fg_format); + bg_img = wrapbuffer_handle(bg_handle, bg_width, bg_height, bg_format); + + /* + * Set the opacity from 0 to 0xFF (255), and use it as the global alpha for + * the current layer to guide the blending. + * If the current layer has per-pixel alpha, then the alpha value is calculated as + * alpha = (per-pixel alpha * global alpha) >> 8. + */ + imsetOpacity(&fg_img, 0x80); + imsetOpacity(&bg_img, 0xe0); + + /* + * Here are two RGBA8888 images of the same size for src_over overlay. + -------------- -------------- -------------- + | | | | | | + | fg_img | + | bg_img | => | fg over bg | + | | | | | | + -------------- -------------- -------------- + */ + + ret = imcheck(fg_img, bg_img, {}, {}); + if (IM_STATUS_NOERROR != ret) { + printf("%d, check error! %s", __LINE__, imStrError((IM_STATUS)ret)); + return -1; + } + + ret = imblend(fg_img, bg_img, IM_ALPHA_BLEND_SRC_OVER | IM_ALPHA_BLEND_PRE_MUL); + if (ret == IM_STATUS_SUCCESS) { + printf("%s running success!\n", LOG_TAG); + } else { + printf("%s running failed, %s\n", LOG_TAG, imStrError((IM_STATUS)ret)); + goto release_buffer; + } + + write_image_to_file(bg_buf, LOCAL_FILE_PATH, bg_width, bg_height, bg_format, 0); + +release_buffer: + if (fg_handle) + releasebuffer_handle(fg_handle); + if (bg_handle) + releasebuffer_handle(bg_handle); + + if (fg_buf) + free(fg_buf); + if (bg_buf) + free(bg_buf); + + return ret; +} From 98b174fa91182daae628760a8892987e3c91133d Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 8 Sep 2023 11:34:17 +0800 Subject: [PATCH 15/46] im2d_api: fix imcvtcolor() cannot set color space Change-Id: Ia89884a5ed63720727f19e553253ef944621896d Signed-off-by: Yu Qiaowei --- im2d_api/src/im2d.cpp | 3 ++- im2d_api/src/im2d_impl.cpp | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/im2d_api/src/im2d.cpp b/im2d_api/src/im2d.cpp index c112b82..591df85 100644 --- a/im2d_api/src/im2d.cpp +++ b/im2d_api/src/im2d.cpp @@ -840,7 +840,8 @@ IM_API IM_STATUS imcvtcolor(rga_buffer_t src, rga_buffer_t dst, int sfmt, int df src.format = sfmt; dst.format = dfmt; - dst.color_space_mode = mode; + if (dst.color_space_mode == 0) + dst.color_space_mode = mode; if (sync == 0) usage |= IM_ASYNC; diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index 41f9d9e..525b45a 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -1860,9 +1860,9 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r if (dst.color_space_mode == IM_COLOR_SPACE_DEFAULT) { if (NormalRgaIsRgbFormat(dst.format)) { - src.color_space_mode = IM_RGB_FULL; + dst.color_space_mode = IM_RGB_FULL; } else if (NormalRgaIsYuvFormat(dst.format)) { - src.color_space_mode = IM_YUV_BT601_LIMIT_RANGE; + dst.color_space_mode = IM_YUV_BT601_LIMIT_RANGE; } } From 456704a0a973ab34e8f46a8c592f6ef88260faec Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 8 Sep 2023 11:39:32 +0800 Subject: [PATCH 16/46] im2d_api: add color space string Change-Id: I9ee96bc679136c8902119f132d17a6352fe6c3fb Signed-off-by: Yu Qiaowei --- im2d_api/src/im2d_impl.cpp | 49 ++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 12 deletions(-) diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index 525b45a..b773bb7 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -73,6 +73,25 @@ IM_API static IM_STATUS rga_get_context(void) { return IM_STATUS_SUCCESS; } +static const char *srting_color_space(int mode) { + switch (mode) { + case IM_RGB_FULL: + return "RGB_FULL"; + case IM_RGB_CLIP: + return "RGB_CLIP"; + case IM_YUV_BT601_LIMIT_RANGE: + return "YUV_BT601_LIMIT"; + case IM_YUV_BT601_FULL_RANGE: + return "YUV_BT601_FULL"; + case IM_YUV_BT709_LIMIT_RANGE: + return "YUV_BT709_LIMIT"; + case IM_YUV_BT709_FULL_RANGE: + return "YUV_BT709_FULL"; + default: + return "UNKNOWN"; + } +} + static IM_STATUS rga_support_info_merge_table(rga_info_table_entry *dst_table, rga_info_table_entry *merge_table) { if (dst_table == NULL || merge_table == NULL) { IM_LOGE("%s[%d] dst or merge table is NULL!\n", __FUNCTION__, __LINE__); @@ -1885,8 +1904,9 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r break; case IM_RGB_CLIP: default: - IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", - src.color_space_mode, dst.color_space_mode); + IM_LOGW("Unsupported full CSC mode! src %s(0x%x), dst %s(0x%x)", + srting_color_space(src.color_space_mode), src.color_space_mode, + srting_color_space(dst.color_space_mode), dst.color_space_mode); return IM_STATUS_NOT_SUPPORTED; } break; @@ -1909,8 +1929,9 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r break; case IM_RGB_CLIP: default: - IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", - src.color_space_mode, dst.color_space_mode); + IM_LOGW("Unsupported full CSC mode! src %s(0x%x), dst %s(0x%x)", + srting_color_space(src.color_space_mode), src.color_space_mode, + srting_color_space(dst.color_space_mode), dst.color_space_mode); return IM_STATUS_NOT_SUPPORTED; } break; @@ -1933,8 +1954,9 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r break; case IM_RGB_CLIP: default: - IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", - src.color_space_mode, dst.color_space_mode); + IM_LOGW("Unsupported full CSC mode! src %s(0x%x), dst %s(0x%x)", + srting_color_space(src.color_space_mode), src.color_space_mode, + srting_color_space(dst.color_space_mode), dst.color_space_mode); return IM_STATUS_NOT_SUPPORTED; } break; @@ -1957,8 +1979,9 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r break; case IM_RGB_CLIP: default: - IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", - src.color_space_mode, dst.color_space_mode); + IM_LOGW("Unsupported full CSC mode! src %s(0x%x), dst %s(0x%x)", + srting_color_space(src.color_space_mode), src.color_space_mode, + srting_color_space(dst.color_space_mode), dst.color_space_mode); return IM_STATUS_NOT_SUPPORTED; } break; @@ -1981,16 +2004,18 @@ static IM_STATUS rga_task_submit(im_job_handle_t job_handle, rga_buffer_t src, r break; case IM_RGB_CLIP: default: - IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", - src.color_space_mode, dst.color_space_mode); + IM_LOGW("Unsupported full CSC mode! src %s(0x%x), dst %s(0x%x)", + srting_color_space(src.color_space_mode), src.color_space_mode, + srting_color_space(dst.color_space_mode), dst.color_space_mode); return IM_STATUS_NOT_SUPPORTED; } break; case IM_RGB_CLIP: default: - IM_LOGW("Unsupported full csc mode! src_csm = 0x%x, dst_csm = 0x%x", - src.color_space_mode, dst.color_space_mode); + IM_LOGW("Unsupported full CSC mode! src %s(0x%x), dst %s(0x%x)", + srting_color_space(src.color_space_mode), src.color_space_mode, + srting_color_space(dst.color_space_mode), dst.color_space_mode); return IM_STATUS_NOT_SUPPORTED; } } From 01b6a827d5a900d6152e8afbfca630e5abdfd62c Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 8 Sep 2023 15:54:52 +0800 Subject: [PATCH 17/46] normal: fix RGA3 cannot config BT709_limit Change-Id: I8269480343e8a155c8dc95c998728d16dcbf6345 Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index e1140c6..4efa66a 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -1271,6 +1271,9 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { ALOGE("Not support full csc mode [%x]\n", dst->color_space_mode); return -EINVAL; } + + if (dst->color_space_mode == rgb2yuv_709_limit) + yuvToRgbMode |= 0x3 << 2; } else { if (src1) { /* special config for yuv + rgb => rgb */ From 5c128718713d9c0308fb7f5b644b7ceb325f674a Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 8 Sep 2023 15:57:00 +0800 Subject: [PATCH 18/46] samples: cvtcolor: update rga_cvtcolor_csc_demo Using the new color space configuration method to configure color space conversion. Change-Id: I2c513221f3ee9b304ad465f6c79660ef76d0987a Signed-off-by: Yu Qiaowei --- .../src/rga_cvtcolor_csc_demo.cpp | 33 +++++++++++++------ 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp b/samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp index 51c0163..50977c1 100644 --- a/samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp +++ b/samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp @@ -39,6 +39,7 @@ #include "im2d.hpp" #include "utils.h" +#include "dma_alloc.h" #define LOCAL_FILE_PATH "/data" @@ -46,6 +47,7 @@ int main() { int ret = 0; int src_width, src_height, src_format; int dst_width, dst_height, dst_format; + int src_dma_fd, dst_dma_fd; char *src_buf, *dst_buf; int src_buf_size, dst_buf_size; @@ -66,8 +68,18 @@ int main() { src_buf_size = src_width * src_height * get_bpp_from_format(src_format); dst_buf_size = dst_width * dst_height * get_bpp_from_format(dst_format); - src_buf = (char *)malloc(src_buf_size); - dst_buf = (char *)malloc(dst_buf_size); + ret = dma_buf_alloc(DMA_HEAP_DMA32_UNCACHE_PATCH, src_buf_size, &src_dma_fd, (void **)&src_buf); + if (ret < 0) { + printf("alloc src dma_heap buffer failed!\n"); + return -1; + } + + ret = dma_buf_alloc(DMA_HEAP_DMA32_UNCACHE_PATCH, dst_buf_size, &dst_dma_fd, (void **)&dst_buf); + if (ret < 0) { + printf("alloc dst dma_heap buffer failed!\n"); + dma_buf_free(src_buf_size, &src_dma_fd, src_buf); + return -1; + } /* fill image data */ if (0 != read_image_from_file(src_buf, LOCAL_FILE_PATH, src_width, src_height, src_format, 0)) { @@ -76,8 +88,8 @@ int main() { } memset(dst_buf, 0x80, dst_buf_size); - src_handle = importbuffer_virtualaddr(src_buf, src_buf_size); - dst_handle = importbuffer_virtualaddr(dst_buf, dst_buf_size); + src_handle = importbuffer_fd(src_dma_fd, src_buf_size); + dst_handle = importbuffer_fd(dst_dma_fd, dst_buf_size); if (src_handle == 0 || dst_handle == 0) { printf("importbuffer failed!\n"); goto release_buffer; @@ -86,13 +98,16 @@ int main() { src_img = wrapbuffer_handle(src_handle, src_width, src_height, src_format); dst_img = wrapbuffer_handle(dst_handle, dst_width, dst_height, dst_format); + imsetColorSpace(&src_img, IM_RGB_FULL); + imsetColorSpace(&dst_img, IM_YUV_BT709_LIMIT_RANGE); + ret = imcheck(src_img, dst_img, {}, {}); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } - ret = imcvtcolor(src_img, dst_img, src_format, dst_format, IM_RGB_TO_YUV_BT709_LIMIT); + ret = imcvtcolor(src_img, dst_img, src_format, dst_format); if (ret == IM_STATUS_SUCCESS) { printf("%s running success!\n", LOG_TAG); } else { @@ -108,10 +123,8 @@ int main() { if (dst_handle) releasebuffer_handle(dst_handle); - if (src_buf) - free(src_buf); - if (dst_buf) - free(dst_buf); + dma_buf_free(dst_buf_size, &dst_dma_fd, dst_buf); + dma_buf_free(src_buf_size, &src_dma_fd, src_buf); return ret; } From ebe6d6d610393ab30a4514519c28d6cefbab55cb Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 11 Sep 2023 17:20:50 +0800 Subject: [PATCH 19/46] normal: user-space closes acquire_fence Since GKI disables closing fd in the kernel, the acquire fence fd should be closed in user-space. The acquire_fence_fd can only be closed from user space after updating the driver to version 1.3.0. Change-Id: I05196b5c78c24cee68ca0d82e78e4deb83cd50e9 Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 23 +++++++++++++++++++++++ core/NormalRgaContext.h | 5 +++++ core/hardware/rga_ioctl.h | 1 + 3 files changed, 29 insertions(+) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index 4efa66a..f9dcc88 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -60,6 +60,11 @@ int get_int_property(void) { return atoi(level); } +static void rga_set_driver_feature(struct rgaContext *ctx) { + if (rga_version_compare(ctx->mDriverVersion, (struct rga_version_t){ 1, 3, 0, {0} }) > 0) + ctx->driver_feature |= RGA_DRIVER_FEATURE_USER_CLOSE_FENCE; +} + int NormalRgaOpen(void **context) { struct rgaContext *ctx = NULL; int fd = -1; @@ -126,6 +131,8 @@ int NormalRgaOpen(void **context) { ALOGE("librga fail to get driver version! Compatibility mode will be enabled.\n"); } + rga_set_driver_feature(ctx); + NormalRgaInitTables(); rgaCtx = ctx; @@ -403,6 +410,8 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { //init memset(&rgaReg, 0, sizeof(struct rga_req)); + if (rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE) + rgaReg.feature.user_close_fence = true; srcType = dstType = srcMmuFlag = dstMmuFlag = 0; src1Type = src1MmuFlag = 0; @@ -1447,6 +1456,10 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { dst->out_fence_fd = rgaReg.out_fence_fd; + if ((rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE) && + (dst->in_fence_fd >= 0)) + close(dst->in_fence_fd); + return 0; } @@ -1498,6 +1511,7 @@ int RgaCollorFill(rga_info *dst) { } memset(&rgaReg, 0, sizeof(struct rga_req)); + rgaReg.feature.user_close_fence = true; dstType = dstMmuFlag = 0; @@ -1747,6 +1761,10 @@ int RgaCollorFill(rga_info *dst) { dst->out_fence_fd = rgaReg.out_fence_fd; + if ((rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE) && + (dst->in_fence_fd >= 0)) + close(dst->in_fence_fd); + return 0; } @@ -1778,6 +1796,7 @@ int RgaCollorPalette(rga_info *src, rga_info *dst, rga_info *lut) { //init memset(&rgaReg, 0, sizeof(struct rga_req)); + rgaReg.feature.user_close_fence = true; srcType = dstType = lutType = srcMmuFlag = dstMmuFlag = lutMmuFlag = 0; @@ -2364,6 +2383,10 @@ int RgaCollorPalette(rga_info *src, rga_info *dst, rga_info *lut) { dst->out_fence_fd = rgaReg.out_fence_fd; + if ((rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE) && + (dst->in_fence_fd >= 0)) + close(dst->in_fence_fd); + return 0; } diff --git a/core/NormalRgaContext.h b/core/NormalRgaContext.h index 5036677..d187208 100644 --- a/core/NormalRgaContext.h +++ b/core/NormalRgaContext.h @@ -34,6 +34,10 @@ typedef enum { RGA_DRIVER_IOC_DEFAULT = RGA_DRIVER_IOC_MULTI_RGA, } RGA_DRIVER_IOC_TYPE; +typedef enum { + RGA_DRIVER_FEATURE_USER_CLOSE_FENCE = 1, +} RGA_DRIVER_FEATURE; + struct rgaContext { int rgaFd; int mLogAlways; @@ -43,5 +47,6 @@ struct rgaContext { struct rga_hw_versions_t mHwVersions; struct rga_version_t mDriverVersion; RGA_DRIVER_IOC_TYPE driver = RGA_DRIVER_IOC_DEFAULT; + uint32_t driver_feature; }; #endif diff --git a/core/hardware/rga_ioctl.h b/core/hardware/rga_ioctl.h index d69f9c5..157196e 100644 --- a/core/hardware/rga_ioctl.h +++ b/core/hardware/rga_ioctl.h @@ -486,6 +486,7 @@ struct rga_req { struct { uint32_t global_alpha_en:1; uint32_t full_csc_clip_en:1; + uint32_t user_close_fence:1; } feature; struct rga_csc_clip full_csc_clip; From f186640f9867b46d219baacd7738236dcf42cf55 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 11 Sep 2023 17:40:31 +0800 Subject: [PATCH 20/46] samples: fixed async_demo incorrectly using SYNC mode Change-Id: Ic3d815de7bc1e68f28e606d3de1896f43bc0a777 Signed-off-by: Yu Qiaowei --- samples/async_demo/src/rga_async_demo.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/samples/async_demo/src/rga_async_demo.cpp b/samples/async_demo/src/rga_async_demo.cpp index 0ad0c7c..af81c1d 100644 --- a/samples/async_demo/src/rga_async_demo.cpp +++ b/samples/async_demo/src/rga_async_demo.cpp @@ -117,7 +117,8 @@ int main() { goto release_buffer; } - ret = imcopy(src_img, tmp_img, 1, &release_fence_fd); + release_fence_fd = -1; + ret = imcopy(src_img, tmp_img, 0, &release_fence_fd); if (ret == IM_STATUS_SUCCESS) { printf("%s src->tmp running success!\n", LOG_TAG); } else { From 2ae5fc42a00ae2b8590bf8f8e6657d8e701a9b16 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 12 Sep 2023 16:57:26 +0800 Subject: [PATCH 21/46] docs: Updated hardware support features add mosaic Change-Id: I660e039dab30c7e12a4c6caae94f822e41532f27 Signed-off-by: Yu Qiaowei --- docs/Rockchip_Developer_Guide_RGA_CN.md | 2 +- docs/Rockchip_Developer_Guide_RGA_EN.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Rockchip_Developer_Guide_RGA_CN.md b/docs/Rockchip_Developer_Guide_RGA_CN.md index d524882..0802500 100644 --- a/docs/Rockchip_Developer_Guide_RGA_CN.md +++ b/docs/Rockchip_Developer_Guide_RGA_CN.md @@ -191,7 +191,7 @@ RGA (Raster Graphic Acceleration Unit)是一个独立的2D硬件加速器，可 8192x8192 2x2 4096x4096 - 90/180/270 Rotate
X/Y Mirror
Crop
1/16~16 scale
Alpha blend
Color key
Color fill
Color palette
ROP(NA for RV1108/RV1109/RK3566)
NN quantize(NA for RK3399/RV1108)
osd (only RV1106/RV1103)
IOMMU(32bit, RK3528/RK3562为40bit，NA for RV1106/1103) + 90/180/270 Rotate
X/Y Mirror
Crop
1/16~16 scale
Alpha blend
Color key
Color fill
Color palette
ROP(NA for RV1108/RV1109/RK3566)
NN quantize(NA for RK3399/RV1108)
osd (only RV1106/RV1103/RK3562/RK3528)
mosaic(only RV1106/RV1103/RK3562/RK3528)
IOMMU(32bit, RK3528/RK3562为40bit，NA for RV1106/1103) 2 diff --git a/docs/Rockchip_Developer_Guide_RGA_EN.md b/docs/Rockchip_Developer_Guide_RGA_EN.md index 8b79bdb..5ca7337 100644 --- a/docs/Rockchip_Developer_Guide_RGA_EN.md +++ b/docs/Rockchip_Developer_Guide_RGA_EN.md @@ -185,7 +185,7 @@ RGA (Raster Graphic Acceleration Unit) is an independent 2D hardware accelerator 8192x8192 2x2 4096x4096 - 90/180/270 Rotate
X/Y Mirror
Crop
1/16~16 scale
Alpha blend
Color key
Color fill
Color palette
ROP(NA for 1108/1109)
NN quantize(NA for 3399/1108)
osd(only 1106/1103)
IOMMU(32bit, RK3528/RK3562 is 40bit，NA for RV1106/1103) + 90/180/270 Rotate
X/Y Mirror
Crop
1/16~16 scale
Alpha blend
Color key
Color fill
Color palette
ROP(NA for RV1108/RV1109/RK3566)
NN quantize(NA for RK3399/RV1108)
osd (only RV1106/RV1103/RK3562/RK3528)
mosaic(only RV1106/RV1103/RK3562/RK3528)
IOMMU(32bit, RK3528/RK3562为40bit，NA for RV1106/1103) 2 From f2889ca5e6f353086de1660d5ef7ead0aae9471d Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 11 Sep 2023 17:29:24 +0800 Subject: [PATCH 22/46] update rga_ioctl.h to dirver verison v1.3.0 Change-Id: Id568bee24e28a31a484ea1572dedb7c9bffb5d24 Signed-off-by: Yu Qiaowei --- core/hardware/rga_ioctl.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/core/hardware/rga_ioctl.h b/core/hardware/rga_ioctl.h index 157196e..623c149 100644 --- a/core/hardware/rga_ioctl.h +++ b/core/hardware/rga_ioctl.h @@ -385,6 +385,12 @@ struct rga_buffer_pool { uint32_t size; }; +struct rga_feature { + uint32_t global_alpha_en:1; + uint32_t full_csc_clip_en:1; + uint32_t user_close_fence:1; +}; + struct rga_req { uint8_t render_mode; /* (enum) process mode sel */ @@ -479,19 +485,15 @@ struct rga_req { rga_pre_intr_info_t pre_intr_info; - /* global alpha */ - uint8_t fg_global_alpha; - uint8_t bg_global_alpha; + /* global alpha */ + uint8_t fg_global_alpha; + uint8_t bg_global_alpha; - struct { - uint32_t global_alpha_en:1; - uint32_t full_csc_clip_en:1; - uint32_t user_close_fence:1; - } feature; + struct rga_feature feature; - struct rga_csc_clip full_csc_clip; + struct rga_csc_clip full_csc_clip; - uint8_t reservr[49]; + uint8_t reservr[49]; }; struct rga_user_request { From 7be06aca232f45f3e6cb5824c3c6c4534fb6ab28 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 12 Sep 2023 17:42:11 +0800 Subject: [PATCH 23/46] docs: update CHANGELOG update to 1.10.0_[0] Change-Id: Idf826fcaf9ea998d4b08a37871c7a316c156b87a Signed-off-by: Yu Qiaowei --- CHANGELOG.md | 31 +++++++++++++++++++++++++++++++ README.md | 2 +- im2d_api/im2d_version.h | 6 +++--- 3 files changed, 35 insertions(+), 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ac87c75..fcc24cf 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,36 @@ # 更新日志 +## 1.10.0 （2023-09-12） + +该版本RGA驱动建议更新至1.3.0及以上版本，最低支持1.2.4。 + +### 新增 + +- 支持更多Porter-Duff混合模型，src-in/dst-in/src-out/dst-out/src-atop/dst-atop/xor。（驱动须更新至1.3.0） +- 新增配置单独通道透明度API imsetOpacity()。 +- 新增配置单独通道色域空间API imsetColorSpace()。 +- 新增配置全局alpha示例代码。 +- 支持GKI。（驱动须更新至1.3.0） + +### 优化 + +- 补充FAQ中对于常见RGA2 不支持大于4G内存空间问题的Q&A。 + +### 变更 + +- samples/padding_demo使用dma32分配内存。 +- 配置色域转换方式更改为通过imsetColorSpace()配置对应通道的色域空间。 + +### 修复 + +- RGA2可以支持 RGB2YUV模式下BT 709 limit range。（驱动须更新至1.3.0） +- 修复一些条件下调用task API参数会丢失的异常。 +- 修复部分示例代码的笔误。 + +### 移除 + +- 移除对SDK环境变量ANDROID_12的依赖。 + ## 1.9.3 （2023-06-28） 该版本RGA驱动建议更新至1.2.27及以上版本，最低支持1.2.4。 diff --git a/README.md b/README.md index ebe47bb..7f4e55e 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ RGA (Raster Graphic Acceleration Unit)是一个独立的2D硬件加速器，可 ## 版本说明 -**RGA API** 版本: 1.9.3 +**RGA API** 版本: 1.10.0 ## 适用芯片平台 diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index 354c672..56448bc 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -24,9 +24,9 @@ /* RGA im2d api verison */ #define RGA_API_MAJOR_VERSION 1 -#define RGA_API_MINOR_VERSION 9 -#define RGA_API_REVISION_VERSION 3 -#define RGA_API_BUILD_VERSION 2 +#define RGA_API_MINOR_VERSION 10 +#define RGA_API_REVISION_VERSION 0 +#define RGA_API_BUILD_VERSION 0 #define RGA_API_SUFFIX From 73300181798b48301f44ef44f232f85ec4c67948 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Wed, 20 Sep 2023 11:08:32 +0800 Subject: [PATCH 24/46] im2d_api: add hardware version support for RK1808 update to 1.10.0_[1] Change-Id: Ice1fbb54e496b4ede53b4c98fa251d27b199c7f9 Signed-off-by: Yu Qiaowei --- im2d_api/im2d_version.h | 2 +- im2d_api/src/im2d_impl.cpp | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index 56448bc..cc936e3 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -26,7 +26,7 @@ #define RGA_API_MAJOR_VERSION 1 #define RGA_API_MINOR_VERSION 10 #define RGA_API_REVISION_VERSION 0 -#define RGA_API_BUILD_VERSION 0 +#define RGA_API_BUILD_VERSION 1 #define RGA_API_SUFFIX diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index b773bb7..7dccd35 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -527,14 +527,17 @@ IM_STATUS rga_get_info(rga_info_table_entry *return_table) { rgaCtx->mHwVersions.version[i].minor == 0) { switch (rgaCtx->mHwVersions.version[i].revision) { case 0x16445 : + // RK3288 rga_version = IM_RGA_HW_VERSION_RGA_2_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); break; case 0x22245 : + // RK1108 rga_version = IM_RGA_HW_VERSION_RGA_2_ENHANCE_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); break; case 0x76831 : + // RK3588 rga_version = IM_RGA_HW_VERSION_RGA_3_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); break; @@ -545,13 +548,16 @@ IM_STATUS rga_get_info(rga_info_table_entry *return_table) { rgaCtx->mHwVersions.version[i].minor == 2) { switch (rgaCtx->mHwVersions.version[i].revision) { case 0x18218 : + // RK3399 rga_version = IM_RGA_HW_VERSION_RGA_2_ENHANCE_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); merge_table.feature |= IM_RGA_SUPPORT_FEATURE_ROP; break; case 0x56726 : + // RV1109 case 0x63318 : + // RK3566/RK3568/RK3588 rga_version = IM_RGA_HW_VERSION_RGA_2_ENHANCE_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); @@ -570,6 +576,7 @@ IM_STATUS rga_get_info(rga_info_table_entry *return_table) { rgaCtx->mHwVersions.version[i].minor == 3) { switch (rgaCtx->mHwVersions.version[i].revision) { case 0x87975: + // RV1106 rga_version = IM_RGA_HW_VERSION_RGA_2_ENHANCE_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); @@ -592,6 +599,7 @@ IM_STATUS rga_get_info(rga_info_table_entry *return_table) { rgaCtx->mHwVersions.version[i].minor == 6) { switch (rgaCtx->mHwVersions.version[i].revision) { case 0x92812: + // RK3562 rga_version = IM_RGA_HW_VERSION_RGA_2_ENHANCE_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); @@ -614,6 +622,7 @@ IM_STATUS rga_get_info(rga_info_table_entry *return_table) { rgaCtx->mHwVersions.version[i].minor == 7) { switch (rgaCtx->mHwVersions.version[i].revision) { case 0x93215: + // RK3528 rga_version = IM_RGA_HW_VERSION_RGA_2_ENHANCE_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); @@ -636,11 +645,16 @@ IM_STATUS rga_get_info(rga_info_table_entry *return_table) { rgaCtx->mHwVersions.version[i].minor == 0) { switch (rgaCtx->mHwVersions.version[i].revision) { case 0x18632 : + // RK3366/RK3368 rga_version = IM_RGA_HW_VERSION_RGA_2_LITE0_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); break; case 0x23998 : + // RK3228H + case 0x27615 : + // RK1808 case 0x28610 : + // RK3326 rga_version = IM_RGA_HW_VERSION_RGA_2_LITE1_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); @@ -652,6 +666,7 @@ IM_STATUS rga_get_info(rga_info_table_entry *return_table) { } else if (rgaCtx->mHwVersions.version[i].major == 42 && rgaCtx->mHwVersions.version[i].minor == 0) { if (rgaCtx->mHwVersions.version[i].revision == 0x17760) { + // RK3228 rga_version = IM_RGA_HW_VERSION_RGA_2_LITE1_INDEX; memcpy(&merge_table, &hw_info_table[rga_version], sizeof(merge_table)); } else { From 3273b647e6b6a9261b8b52597ec22821fba04a59 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 22 Sep 2023 10:26:11 +0800 Subject: [PATCH 25/46] include: rga_ioctl.h: fix the incorrect reserved size of rga_req update to 1.10.0_[2] Change-Id: I826572ce25c70a57208b67b604aabe21715c0772 Signed-off-by: Yu Qiaowei --- core/hardware/rga_ioctl.h | 2 +- im2d_api/im2d_version.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/core/hardware/rga_ioctl.h b/core/hardware/rga_ioctl.h index 623c149..e082269 100644 --- a/core/hardware/rga_ioctl.h +++ b/core/hardware/rga_ioctl.h @@ -493,7 +493,7 @@ struct rga_req { struct rga_csc_clip full_csc_clip; - uint8_t reservr[49]; + uint8_t reservr[43]; }; struct rga_user_request { diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index cc936e3..f81295c 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -26,7 +26,7 @@ #define RGA_API_MAJOR_VERSION 1 #define RGA_API_MINOR_VERSION 10 #define RGA_API_REVISION_VERSION 0 -#define RGA_API_BUILD_VERSION 1 +#define RGA_API_BUILD_VERSION 2 #define RGA_API_SUFFIX From 3221023aea428158fb7d6f2b799cb967c5e98f56 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 26 Sep 2023 11:50:26 +0800 Subject: [PATCH 26/46] normal: rgaBlit api disable globalAlpha To avoid compatibility issues, the rgaBlit API will disable the configuration of globalAlpha. update to 1.10.0_[3] Change-Id: I8855efaa85a93ab7fcfa698657b8b78de87efd39 Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 20 ++++++++++++++++++++ im2d_api/im2d_type.h | 2 +- im2d_api/im2d_version.h | 2 +- 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index f9dcc88..bbc74b3 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -706,22 +706,42 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { fg_global_alpha = (blend >> 16) & 0xff; bg_global_alpha = (blend >> 24) & 0xff; + /* + * In the legacy interface, the src-over mode supports globalAlpha + * configuration for the src channel, while the other modes do not + * support globalAlpha configuration. + */ switch (blend) { case 0x405: + fg_global_alpha = (blend >> 16) & 0xff; + bg_global_alpha = 0xff; + blend = RGA_ALPHA_BLEND_SRC_OVER; blend |= 0x1 << 12; break; case 0x504: + fg_global_alpha = 0xff; + bg_global_alpha = 0xff; + blend = RGA_ALPHA_BLEND_DST_OVER; blend |= 0x1 << 12; break; case 0x105: + fg_global_alpha = (blend >> 16) & 0xff; + bg_global_alpha = 0xff; + blend = RGA_ALPHA_BLEND_SRC_OVER; break; case 0x501: + fg_global_alpha = 0xff; + bg_global_alpha = 0xff; + blend = RGA_ALPHA_BLEND_DST_OVER; break; case 0x100: + fg_global_alpha = 0xff; + bg_global_alpha = 0xff; + blend = RGA_ALPHA_BLEND_SRC; break; } diff --git a/im2d_api/im2d_type.h b/im2d_api/im2d_type.h index 24365b4..754a971 100644 --- a/im2d_api/im2d_type.h +++ b/im2d_api/im2d_type.h @@ -294,7 +294,7 @@ typedef struct { int format; /* format */ int color_space_mode; /* color_space_mode */ - int global_alpha; /* global_alpha */ + int global_alpha; /* global_alpha, the default should be 0xff */ int rd_mode; /* legarcy */ diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index f81295c..2b3f779 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -26,7 +26,7 @@ #define RGA_API_MAJOR_VERSION 1 #define RGA_API_MINOR_VERSION 10 #define RGA_API_REVISION_VERSION 0 -#define RGA_API_BUILD_VERSION 2 +#define RGA_API_BUILD_VERSION 3 #define RGA_API_SUFFIX From 2a2a9a850d16fdfb960a9f839c17354215c84f48 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Sat, 7 Oct 2023 17:55:45 +0800 Subject: [PATCH 27/46] remove dependency on libm Change-Id: Id77d5b01bb0fd8bea07639ef904081ad24fc4cf8 Signed-off-by: Yu Qiaowei --- core/RgaUtils.cpp | 1 - core/RockchipRga.cpp | 1 - im2d_api/src/im2d.cpp | 1 - im2d_api/src/im2d_impl.cpp | 18 +++++++----------- 4 files changed, 7 insertions(+), 14 deletions(-) diff --git a/core/RgaUtils.cpp b/core/RgaUtils.cpp index 219a497..186c941 100644 --- a/core/RgaUtils.cpp +++ b/core/RgaUtils.cpp @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/core/RockchipRga.cpp b/core/RockchipRga.cpp index 8a30b0e..53865d9 100644 --- a/core/RockchipRga.cpp +++ b/core/RockchipRga.cpp @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include diff --git a/im2d_api/src/im2d.cpp b/im2d_api/src/im2d.cpp index 591df85..77aca5a 100644 --- a/im2d_api/src/im2d.cpp +++ b/im2d_api/src/im2d.cpp @@ -24,7 +24,6 @@ #define LOG_TAG "im2d_rga" #endif -#include #include #include "RgaUtils.h" diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index 7dccd35..d89dfe4 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -26,7 +26,6 @@ #include #include #include -#include #include #include "im2d.h" @@ -810,8 +809,8 @@ IM_STATUS rga_check_info(const char *name, const rga_buffer_t info, const im_rec } IM_STATUS rga_check_limit(rga_buffer_t src, rga_buffer_t dst, int scale_usage, int mode_usage) { - int src_width = 0, src_height = 0; - int dst_width = 0, dst_height = 0; + float src_width = 0, src_height = 0; + float dst_width = 0, dst_height = 0; src_width = src.width; src_height = src.height; @@ -823,14 +822,11 @@ IM_STATUS rga_check_limit(rga_buffer_t src, rga_buffer_t dst, int scale_usage, i dst_width = dst.width; dst_height = dst.height; } - if (((src_width >> (int)(log(scale_usage)/log(2))) > dst_width) || - ((src_height >> (int)(log(scale_usage)/log(2))) > dst_height)) { - IM_LOGW("Unsupported to scaling less than 1/%d ~ %d times, src[w,h] = [%d, %d], dst[w,h] = [%d, %d]", - scale_usage, scale_usage, src.width, src.height, dst.width, dst.height); - return IM_STATUS_NOT_SUPPORTED; - } - if (((dst_width >> (int)(log(scale_usage)/log(2))) > src_width) || - ((dst_height >> (int)(log(scale_usage)/log(2))) > src_height)) { + + if (src_width / dst_width > (float)scale_usage || + src_height / dst_height > (float)scale_usage || + dst_width / src_width > (float)scale_usage || + dst_height / src_height > (float)scale_usage) { IM_LOGW("Unsupported to scaling more than 1/%d ~ %d times, src[w,h] = [%d, %d], dst[w,h] = [%d, %d]", scale_usage, scale_usage, src.width, src.height, dst.width, dst.height); return IM_STATUS_NOT_SUPPORTED; From d18f60f607e84976b7f898509f2cbe48d3a5c531 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Sat, 7 Oct 2023 18:02:49 +0800 Subject: [PATCH 28/46] samples: remove dependency on libm Change-Id: Ia6088ff32c35f4ae4840078723a7d41f1c4495e8 Signed-off-by: Yu Qiaowei --- samples/async_demo/src/rga_async_demo.cpp | 1 - samples/config_demo/src/rga_config_single_core_demo.cpp | 1 - samples/config_demo/src/rga_config_thread_core_demo.cpp | 1 - samples/copy_demo/src/rga_copy_demo.cpp | 1 - samples/copy_demo/src/rga_copy_fbc_demo.cpp | 1 - samples/copy_demo/src/rga_copy_splice_demo.cpp | 1 - samples/copy_demo/src/rga_copy_splice_task_demo.cpp | 1 - samples/copy_demo/src/rga_copy_tile8x8_demo.cpp | 1 - samples/crop_demo/src/rga_crop_demo.cpp | 1 - samples/crop_demo/src/rga_crop_rect_demo.cpp | 1 - samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp | 1 - samples/cvtcolor_demo/src/rga_cvtcolor_demo.cpp | 1 - samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp | 2 +- samples/im2d_api_demo/rgaImDemo.cpp | 1 - samples/im2d_slt/sources/dma_alloc.cpp | 1 - samples/im2d_slt/sources/rga_im2d_slt.cpp | 1 - samples/padding_demo/src/rga_padding_demo.cpp | 1 - samples/resize_demo/src/rga_resize_demo.cpp | 1 - samples/resize_demo/src/rga_resize_rect_demo.cpp | 1 - samples/resize_demo/src/rga_resize_uv_downsampling_demo.cpp | 1 - samples/rop_demo/src/rga_rop_demo.cpp | 1 - samples/transform_demo/src/rga_transform_flip_demo.cpp | 1 - samples/transform_demo/src/rga_transform_rotate_demo.cpp | 1 - samples/transform_demo/src/rga_transform_rotate_flip_demo.cpp | 1 - samples/utils/allocator/dma_alloc.cpp | 1 - 25 files changed, 1 insertion(+), 25 deletions(-) diff --git a/samples/async_demo/src/rga_async_demo.cpp b/samples/async_demo/src/rga_async_demo.cpp index af81c1d..8a5e990 100644 --- a/samples/async_demo/src/rga_async_demo.cpp +++ b/samples/async_demo/src/rga_async_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/config_demo/src/rga_config_single_core_demo.cpp b/samples/config_demo/src/rga_config_single_core_demo.cpp index 61f5de5..48f20cf 100644 --- a/samples/config_demo/src/rga_config_single_core_demo.cpp +++ b/samples/config_demo/src/rga_config_single_core_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/config_demo/src/rga_config_thread_core_demo.cpp b/samples/config_demo/src/rga_config_thread_core_demo.cpp index c6da42b..3ad72ba 100644 --- a/samples/config_demo/src/rga_config_thread_core_demo.cpp +++ b/samples/config_demo/src/rga_config_thread_core_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/copy_demo/src/rga_copy_demo.cpp b/samples/copy_demo/src/rga_copy_demo.cpp index 3bfcca6..b84d751 100644 --- a/samples/copy_demo/src/rga_copy_demo.cpp +++ b/samples/copy_demo/src/rga_copy_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/copy_demo/src/rga_copy_fbc_demo.cpp b/samples/copy_demo/src/rga_copy_fbc_demo.cpp index 0838cba..3219769 100644 --- a/samples/copy_demo/src/rga_copy_fbc_demo.cpp +++ b/samples/copy_demo/src/rga_copy_fbc_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/copy_demo/src/rga_copy_splice_demo.cpp b/samples/copy_demo/src/rga_copy_splice_demo.cpp index 337bf72..7d223eb 100644 --- a/samples/copy_demo/src/rga_copy_splice_demo.cpp +++ b/samples/copy_demo/src/rga_copy_splice_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/copy_demo/src/rga_copy_splice_task_demo.cpp b/samples/copy_demo/src/rga_copy_splice_task_demo.cpp index b8cf746..d1442ac 100644 --- a/samples/copy_demo/src/rga_copy_splice_task_demo.cpp +++ b/samples/copy_demo/src/rga_copy_splice_task_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/copy_demo/src/rga_copy_tile8x8_demo.cpp b/samples/copy_demo/src/rga_copy_tile8x8_demo.cpp index 16f8e46..3102b8c 100644 --- a/samples/copy_demo/src/rga_copy_tile8x8_demo.cpp +++ b/samples/copy_demo/src/rga_copy_tile8x8_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/crop_demo/src/rga_crop_demo.cpp b/samples/crop_demo/src/rga_crop_demo.cpp index 658a409..7411854 100644 --- a/samples/crop_demo/src/rga_crop_demo.cpp +++ b/samples/crop_demo/src/rga_crop_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/crop_demo/src/rga_crop_rect_demo.cpp b/samples/crop_demo/src/rga_crop_rect_demo.cpp index 72e0ded..16264af 100644 --- a/samples/crop_demo/src/rga_crop_rect_demo.cpp +++ b/samples/crop_demo/src/rga_crop_rect_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp b/samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp index 50977c1..382f2d1 100644 --- a/samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp +++ b/samples/cvtcolor_demo/src/rga_cvtcolor_csc_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/cvtcolor_demo/src/rga_cvtcolor_demo.cpp b/samples/cvtcolor_demo/src/rga_cvtcolor_demo.cpp index ba8c67a..0270661 100644 --- a/samples/cvtcolor_demo/src/rga_cvtcolor_demo.cpp +++ b/samples/cvtcolor_demo/src/rga_cvtcolor_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp b/samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp index e8f8feb..299af98 100644 --- a/samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp +++ b/samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp @@ -29,7 +29,7 @@ #include #include #include -#include +#include <> #include #include #include diff --git a/samples/im2d_api_demo/rgaImDemo.cpp b/samples/im2d_api_demo/rgaImDemo.cpp index 37cc40b..e67eb4d 100644 --- a/samples/im2d_api_demo/rgaImDemo.cpp +++ b/samples/im2d_api_demo/rgaImDemo.cpp @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/im2d_slt/sources/dma_alloc.cpp b/samples/im2d_slt/sources/dma_alloc.cpp index 9d8d90d..b1507e7 100644 --- a/samples/im2d_slt/sources/dma_alloc.cpp +++ b/samples/im2d_slt/sources/dma_alloc.cpp @@ -42,7 +42,6 @@ #include #include -#include #include #include diff --git a/samples/im2d_slt/sources/rga_im2d_slt.cpp b/samples/im2d_slt/sources/rga_im2d_slt.cpp index 3721ed3..a3f5b1f 100644 --- a/samples/im2d_slt/sources/rga_im2d_slt.cpp +++ b/samples/im2d_slt/sources/rga_im2d_slt.cpp @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/padding_demo/src/rga_padding_demo.cpp b/samples/padding_demo/src/rga_padding_demo.cpp index 0e53d7c..832b485 100644 --- a/samples/padding_demo/src/rga_padding_demo.cpp +++ b/samples/padding_demo/src/rga_padding_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/resize_demo/src/rga_resize_demo.cpp b/samples/resize_demo/src/rga_resize_demo.cpp index eb6d9ff..8d43e99 100644 --- a/samples/resize_demo/src/rga_resize_demo.cpp +++ b/samples/resize_demo/src/rga_resize_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/resize_demo/src/rga_resize_rect_demo.cpp b/samples/resize_demo/src/rga_resize_rect_demo.cpp index 9c5b1b1..160b1cb 100644 --- a/samples/resize_demo/src/rga_resize_rect_demo.cpp +++ b/samples/resize_demo/src/rga_resize_rect_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/resize_demo/src/rga_resize_uv_downsampling_demo.cpp b/samples/resize_demo/src/rga_resize_uv_downsampling_demo.cpp index 123c4ac..e07f192 100644 --- a/samples/resize_demo/src/rga_resize_uv_downsampling_demo.cpp +++ b/samples/resize_demo/src/rga_resize_uv_downsampling_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/rop_demo/src/rga_rop_demo.cpp b/samples/rop_demo/src/rga_rop_demo.cpp index 979a067..b18766d 100644 --- a/samples/rop_demo/src/rga_rop_demo.cpp +++ b/samples/rop_demo/src/rga_rop_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/transform_demo/src/rga_transform_flip_demo.cpp b/samples/transform_demo/src/rga_transform_flip_demo.cpp index 3cc7632..8d95d69 100644 --- a/samples/transform_demo/src/rga_transform_flip_demo.cpp +++ b/samples/transform_demo/src/rga_transform_flip_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/transform_demo/src/rga_transform_rotate_demo.cpp b/samples/transform_demo/src/rga_transform_rotate_demo.cpp index ea621d6..47c413a 100644 --- a/samples/transform_demo/src/rga_transform_rotate_demo.cpp +++ b/samples/transform_demo/src/rga_transform_rotate_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/transform_demo/src/rga_transform_rotate_flip_demo.cpp b/samples/transform_demo/src/rga_transform_rotate_flip_demo.cpp index cdceac3..57663c4 100644 --- a/samples/transform_demo/src/rga_transform_rotate_flip_demo.cpp +++ b/samples/transform_demo/src/rga_transform_rotate_flip_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/samples/utils/allocator/dma_alloc.cpp b/samples/utils/allocator/dma_alloc.cpp index a395e2f..3bbe379 100644 --- a/samples/utils/allocator/dma_alloc.cpp +++ b/samples/utils/allocator/dma_alloc.cpp @@ -42,7 +42,6 @@ #include #include -#include #include #include From 7f8eb9e97d94107a01a5337e2ddf1ad7b015df6e Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 9 Oct 2023 17:31:52 +0800 Subject: [PATCH 29/46] fix typo Change-Id: Id327a887b59ba20de1bc9cc442063f31cc251c5e Signed-off-by: Yu Qiaowei --- im2d_api/im2d_type.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/im2d_api/im2d_type.h b/im2d_api/im2d_type.h index 754a971..db72dd2 100644 --- a/im2d_api/im2d_type.h +++ b/im2d_api/im2d_type.h @@ -297,7 +297,7 @@ typedef struct { int global_alpha; /* global_alpha, the default should be 0xff */ int rd_mode; - /* legarcy */ + /* legacy */ int color; /* color, used by color fill */ im_colorkey_range colorkey_range; /* range value of color key */ im_nn_t nn; From e944743948760477ff611c5dbf6146cef81c15d2 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Wed, 18 Oct 2023 17:01:57 +0800 Subject: [PATCH 30/46] normal: hardware: fix the incorrect structure in the rga_req update to 1.10.0_[4] Change-Id: Ib6b612fd56211d1c032ddddb0a0278dd2a896392 Signed-off-by: Yu Qiaowei --- core/hardware/rga_ioctl.h | 4 ++-- im2d_api/im2d_version.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/core/hardware/rga_ioctl.h b/core/hardware/rga_ioctl.h index e082269..66dd64e 100644 --- a/core/hardware/rga_ioctl.h +++ b/core/hardware/rga_ioctl.h @@ -229,8 +229,8 @@ typedef struct full_csc_t { } full_csc_t; struct rga_csc_range { - uint8_t max; - uint8_t min; + uint16_t max; + uint16_t min; }; struct rga_csc_clip { diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index 2b3f779..d0b4aee 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -26,7 +26,7 @@ #define RGA_API_MAJOR_VERSION 1 #define RGA_API_MINOR_VERSION 10 #define RGA_API_REVISION_VERSION 0 -#define RGA_API_BUILD_VERSION 3 +#define RGA_API_BUILD_VERSION 4 #define RGA_API_SUFFIX From 44ed92834d0e90a3c767eae1f900ddc6a667841b Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 23 Oct 2023 17:43:55 +0800 Subject: [PATCH 31/46] samples: fix the incorrect usage of imcancel() Change-Id: I5f5fc2cd417e004d454a560d50060fa2200605da Signed-off-by: Yu Qiaowei --- .../copy_demo/src/rga_copy_splice_demo.cpp | 4 ++++ .../src/rga_copy_splice_task_demo.cpp | 19 ++++++++++++------- .../rga_fill_rectangle_task_array_demo.cpp | 15 ++++++++------- .../src/rga_fill_rectangle_task_demo.cpp | 15 ++++++++------- 4 files changed, 32 insertions(+), 21 deletions(-) diff --git a/samples/copy_demo/src/rga_copy_splice_demo.cpp b/samples/copy_demo/src/rga_copy_splice_demo.cpp index 7d223eb..e8042cc 100644 --- a/samples/copy_demo/src/rga_copy_splice_demo.cpp +++ b/samples/copy_demo/src/rga_copy_splice_demo.cpp @@ -172,11 +172,15 @@ int main() { release_buffer: if (left_handle) releasebuffer_handle(left_handle); + if (right_handle) + releasebuffer_handle(right_handle); if (dst_handle) releasebuffer_handle(dst_handle); if (left_buf) free(left_buf); + if (right_buf) + free(right_buf); if (dst_buf) free(dst_buf); diff --git a/samples/copy_demo/src/rga_copy_splice_task_demo.cpp b/samples/copy_demo/src/rga_copy_splice_task_demo.cpp index d1442ac..70ee1a4 100644 --- a/samples/copy_demo/src/rga_copy_splice_task_demo.cpp +++ b/samples/copy_demo/src/rga_copy_splice_task_demo.cpp @@ -138,7 +138,8 @@ int main() { ret = imcheck(left_img, dst_img, {}, left_rect); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s", __LINE__, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } ret = improcessTask(job_handle, left_img, dst_img, {}, {}, left_rect, {}, NULL, IM_SYNC); @@ -146,7 +147,8 @@ int main() { printf("%s job[%d] add left task success!\n", LOG_TAG, job_handle); } else { printf("%s job[%d] add left task failed, %s\n", LOG_TAG, job_handle, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } /* @@ -166,7 +168,8 @@ int main() { ret = imcheck(right_img, dst_img, {}, right_rect); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s", __LINE__, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } ret = improcessTask(job_handle, right_img, dst_img, {}, {}, right_rect, {}, NULL, IM_SYNC); @@ -174,7 +177,8 @@ int main() { printf("%s job[%d] add right task success!\n", LOG_TAG, job_handle); } else { printf("%s job[%d] add right task failed, %s\n", LOG_TAG, job_handle, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } /* @@ -191,17 +195,18 @@ int main() { printf("output [0x%x, 0x%x, 0x%x, 0x%x]\n", dst_buf[0], dst_buf[1], dst_buf[2], dst_buf[3]); write_image_to_file(dst_buf, LOCAL_FILE_PATH, dst_width, dst_height, dst_format, 0); -cancel_job: - imcancelJob(job_handle); - release_buffer: if (left_handle) releasebuffer_handle(left_handle); + if (right_handle) + releasebuffer_handle(right_handle); if (dst_handle) releasebuffer_handle(dst_handle); if (left_buf) free(left_buf); + if (right_buf) + free(right_buf); if (dst_buf) free(dst_buf); diff --git a/samples/fill_demo/src/rga_fill_rectangle_task_array_demo.cpp b/samples/fill_demo/src/rga_fill_rectangle_task_array_demo.cpp index 2c3d968..29ee16f 100644 --- a/samples/fill_demo/src/rga_fill_rectangle_task_array_demo.cpp +++ b/samples/fill_demo/src/rga_fill_rectangle_task_array_demo.cpp @@ -112,7 +112,8 @@ int main(void) { ret = imcheck({}, dst, {}, green_rect[i], IM_COLOR_FILL); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s", __LINE__, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } } @@ -121,7 +122,8 @@ int main(void) { printf("%s job[%d] add fill task array success!\n", LOG_TAG, job_handle); } else { printf("%s job[%d] add fill task array failed, %s\n", LOG_TAG, job_handle, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } /* Add a task that fills an array of green rectangle borders */ @@ -134,7 +136,8 @@ int main(void) { ret = imcheck({}, dst, {}, red_rect[i], IM_COLOR_FILL); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s", __LINE__, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } } @@ -143,7 +146,8 @@ int main(void) { printf("%s job[%d] add fill task array success!\n", LOG_TAG, job_handle); } else { printf("%s job[%d] add fill task array failed, %s\n", LOG_TAG, job_handle, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } /* Submit and wait for the job to complete. */ @@ -158,9 +162,6 @@ int main(void) { printf("output [0x%x, 0x%x, 0x%x, 0x%x]\n", dst_buf[0], dst_buf[1], dst_buf[2], dst_buf[3]); write_image_to_file(dst_buf, LOCAL_FILE_PATH, dst_width, dst_height, dst_format, 0); -cancel_job: - imcancelJob(job_handle); - release_buffer: if (dst_handle > 0) releasebuffer_handle(dst_handle); diff --git a/samples/fill_demo/src/rga_fill_rectangle_task_demo.cpp b/samples/fill_demo/src/rga_fill_rectangle_task_demo.cpp index bd9dbce..0f6db8a 100644 --- a/samples/fill_demo/src/rga_fill_rectangle_task_demo.cpp +++ b/samples/fill_demo/src/rga_fill_rectangle_task_demo.cpp @@ -106,7 +106,8 @@ int main(void) { ret = imcheck({}, dst, {}, dst_rect[0], IM_COLOR_FILL); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s", __LINE__, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } ret = imrectangleTask(job_handle, dst, dst_rect[0], 0xff00ff00, -1); @@ -114,7 +115,8 @@ int main(void) { printf("%s job[%d] add fill task success!\n", LOG_TAG, job_handle); } else { printf("%s job[%d] add fill task failed, %s\n", LOG_TAG, job_handle, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } /* Add a task to fill the rectangle border. */ @@ -123,7 +125,8 @@ int main(void) { ret = imcheck({}, dst, {}, dst_rect[0], IM_COLOR_FILL); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s", __LINE__, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } ret = imrectangleTask(job_handle, dst, dst_rect[0], 0xffff0000, 4); @@ -131,7 +134,8 @@ int main(void) { printf("%s job[%d] add fill task success!\n", LOG_TAG, job_handle); } else { printf("%s job[%d] add fill task failed, %s\n", LOG_TAG, job_handle, imStrError((IM_STATUS)ret)); - goto cancel_job; + imcancelJob(job_handle); + goto release_buffer; } /* Submit and wait for the job to complete. */ @@ -146,9 +150,6 @@ int main(void) { printf("output [0x%x, 0x%x, 0x%x, 0x%x]\n", dst_buf[0], dst_buf[1], dst_buf[2], dst_buf[3]); write_image_to_file(dst_buf, LOCAL_FILE_PATH, dst_width, dst_height, dst_format, 0); -cancel_job: - imcancelJob(job_handle); - release_buffer: if (dst_handle > 0) releasebuffer_handle(dst_handle); From a210e4b7d1508a41e9574c3fba038bf34215aa30 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 30 Oct 2023 15:41:55 +0800 Subject: [PATCH 32/46] samples: allocator: use the correct usage to call lock/unlock Change-Id: I6f4b7ff36b9b1b3457b71edd8cd295c51d7741a0 Signed-off-by: Yu Qiaowei --- .../src/rga_allocator_graphicbuffer_demo.cpp | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/samples/allocator_demo/src/rga_allocator_graphicbuffer_demo.cpp b/samples/allocator_demo/src/rga_allocator_graphicbuffer_demo.cpp index 0e0e505..e3ced67 100644 --- a/samples/allocator_demo/src/rga_allocator_graphicbuffer_demo.cpp +++ b/samples/allocator_demo/src/rga_allocator_graphicbuffer_demo.cpp @@ -76,6 +76,10 @@ int main(void) { dst_buf_size = dst_width * dst_height * get_bpp_from_format(dst_format); /* allocate GraphicBuffer */ + src_gb_flags |= GRALLOC_USAGE_SW_WRITE_OFTEN | GRALLOC_USAGE_SW_READ_OFTEN; + dst_gb_flags |= GRALLOC_USAGE_SW_WRITE_OFTEN | GRALLOC_USAGE_SW_READ_OFTEN; + + /* for CORE_RGA2 */ src_gb_flags |= RK_GRALLOC_USAGE_WITHIN_4G; dst_gb_flags |= RK_GRALLOC_USAGE_WITHIN_4G; @@ -90,7 +94,7 @@ int main(void) { return -1; } - ret = src_gb->lock(0, (void **)&src_buf); + ret = src_gb->lock(GRALLOC_USAGE_SW_WRITE_OFTEN, (void **)&src_buf); if (ret) { printf("lock buffer error : %s\n",strerror(errno)); return -1; @@ -108,7 +112,7 @@ int main(void) { return -1; } - ret = dst_gb->lock(0, (void **)&dst_buf); + ret = dst_gb->lock(GRALLOC_USAGE_SW_WRITE_OFTEN, (void **)&dst_buf); if (ret) { printf("lock buffer error : %s\n",strerror(errno)); return -1; @@ -154,7 +158,7 @@ int main(void) { goto release_buffer; } - ret = dst_gb->lock(0, (void **)&dst_buf); + ret = dst_gb->lock(GRALLOC_USAGE_SW_READ_OFTEN, (void **)&dst_buf); if (ret) { printf("lock buffer error : %s\n",strerror(errno)); return -1; From d4710dddc753397cde3c0b286ff9625eb994ce34 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 7 Nov 2023 16:55:11 +0800 Subject: [PATCH 33/46] docs: FAQ: add Q&A about performance Change-Id: Idea5a47daecabf96da85b244f66ff4c7c1567664 Signed-off-by: Yu Qiaowei --- docs/Rockchip_FAQ_RGA_CN.md | 80 +++++++++++++++++++++++++++++++++---- docs/Rockchip_FAQ_RGA_EN.md | 70 ++++++++++++++++++++++++++++++-- 2 files changed, 138 insertions(+), 12 deletions(-) diff --git a/docs/Rockchip_FAQ_RGA_CN.md b/docs/Rockchip_FAQ_RGA_CN.md index 78a8a63..c9232d5 100644 --- a/docs/Rockchip_FAQ_RGA_CN.md +++ b/docs/Rockchip_FAQ_RGA_CN.md @@ -568,13 +568,27 @@ rga2: 00000000 00000000 00000000 00000000 rga2: sync one cmd end time 2414 //打印本次工作RGA硬件的耗时，单位为us ``` - - multi + - multi-rga + > 1.3.0以下版本 + ``` - rga3_reg: set cmd use time = 196 //开始处理请求到配置寄存器的耗时 - rga_job: hw use time = 554 //硬件启动到硬件中断返回耗时 - rga_job: (pid:3197) job done use time = 751 //开始处理请求到请求完成的耗时 - rga_job: (pid:3197) job clean use time = 933 //开始处理请求到请求资源处理完毕的耗时 + rga3_reg: set cmd use time = 196 //开始处理请求到配置寄存器的耗时，单位为us + rga_job: hw use time = 554 //硬件启动到硬件中断返回耗时，单位为us + rga_job: (pid:3197) job done use time = 751 //开始处理请求到请求完成的耗时，单位为us + rga_job: (pid:3197) job clean use time = 933 //开始处理请求到请求资源处理完毕的耗时，单位为us + ``` + + > 1.3.0及以上版本 + + ``` + rga_mm: request[3300], get buffer_handle info cost 188 us //获取当前buffer_handle信息耗时（虚拟地址则包含cache同步的耗时） + rga3_reg: request[3300], generate register cost time 2 us //生成寄存器配置耗时 + rga3_reg: request[3300], set register cost time 301 us //配置寄存器耗时 + rga_job: request[3300], hardware[RGA3_core0] cost time 539 us //对应的硬件核心完成任务耗时 + rga_mm: request[3300], put buffer_handle info cost 153 us //释放当前buffer_handle信息耗时（虚拟地址则包含cache同步的耗时） + rga_job: request[3300], job done total cost time 1023 us //当前job从提交到完成返回用户态的全部耗时 + rga_job: request[3300], job cleanup total cost time 1030 us //当前job从提交到资源释放完毕的全部耗时 ``` @@ -813,7 +827,7 @@ rga_debugger: dump image to: /data/rga_image/1_core1_dst_plane0_virt_addr_w1280_ **Q1.4**：RGA的效率不能满足我们产品的需求，有什么办法可以提升么？ -**A1.4**：部分芯片的出厂固件的RGA频率并不是最高频率，例如3399、1126等芯片RGA的频率最高可以到400M，可以通过以下两种方式实现RGA提频： +**A1.4**：部分芯片早期（2021年之前）的出厂固件的RGA频率并不是最高频率，例如3399、1126等芯片RGA的频率最高可以到400M，可以通过以下两种方式实现RGA提频： - 通过命令设置（临时修改，设备重启则恢复频率） @@ -876,7 +890,7 @@ index 02938b0..10a1dc4 100644 ​ 2). 当使用的虚拟地址是cacheable的，由于使能了cache，RGA驱动会在硬件访问内存前后强制同步cache数据，因此会增加CPU同步cache和内存的负载。由于常见的虚拟地址分配器并不是设计用于给其他硬件访问的，并存在同步cache的接口，因此驱动针对虚拟地址强制同步cache也是必要的。 -​ 3). 当时用dma-buf fd调用RGA时，有些分配器默认分配的是cacheable的buffer，并且kernel中dma-buf的处理会强制同步cache的情况，这是也会存在每次调用RGA时会有较大的CPU负载，也是因为CPU同步cache和内存引入的负载。该种情况下建议分配禁用cache的dma-buf。 +​ 3). 当使用dma-buf fd调用RGA时，有些分配器默认分配的是cacheable的buffer，并且kernel中dma-buf的处理会强制同步cache的情况，这是也会存在每次调用RGA时会有较大的CPU负载，也是因为CPU同步cache和内存引入的负载。该种情况下建议分配禁用cache的dma-buf。 @@ -884,7 +898,7 @@ index 02938b0..10a1dc4 100644 **A1.9**：由于部分RGA1/RGA2的IOMMU仅支持最大32位的物理地址，而RGA Device Driver、RGA2 Device Driver中对于不满足硬件内存要求的调用申请，默认是通过swiotlb机制进行访问访问受限制的内存（原理上相当于通过CPU将高位内存拷贝至复合硬件要求的低位内存中，再交由硬件进行处理，处理完毕后再通过CPU将低位内存搬运回目标的高位内存上。）因此效率十分低下，通常在正常耗时的3-4倍之间浮动，并且引入受CPU负载影响。 -RGA Multicore Device Driver中针对访问受限制的内存会禁用swiotlb机制，直接通过调用失败的方式显示的通知调用者申请合理的内存再调用，来保证RGA的高效。通常伴随着以下日志： +RGA Multicore Device Driver中针对访问受限制的内存会禁用swiotlb机制，直接通过调用失败的方式显示的通知调用者申请符合要求的内存再调用，来保证RGA的高效。通常伴随着以下日志： > HAL层日志： @@ -925,6 +939,56 @@ rga_policy: start policy on core = 4 +**Q1.10**：为什么调用RGA API时发现API返回耗时远高于驱动打印硬件耗时？ + +​ **Q1.10.1**：通过“TIME”运行日志发现map/unmap buffer耗时过大。 +​ **Q1.10.2**：对比kernel日志时间戳发现打印参数日志到寄存器打印之间存在较大的空白时间。 +​ **Q1.10.3**：相同的参数配置，仅使用不同的内存分配器得到的运行耗时差异较大。 + +**A1.10**：这里的耗时异常的原因均为外部buffer的内存映射行为（map/unmap）导致。所有的外部buffer都需要映射、绑定到RGA驱动中才能保证硬件最终能够访问指定的buffer。而不同的分配器对应的底层实现差异会导致驱动映射、绑定内存时耗时不一，从而导致看起来好像API耗时会比硬件实际耗时高很多的情况。常见的会存在较高额外耗时的dma-buf分配器有ION、V4L2等，通常这些差异与cache的同步有关，针对这类型问题可以通过横向对比不同分配器进行确认。 + +这类问题通常可以通过以下几种方式进行优化： + +​ 1). 使用map/unmap耗时合理的内存分配器，常见的有dma_heap、DRM以及对应的封装内存分配器，以下是对应内存分配器分配内存调用RGA的示例代码： + +**/samples/allocator_demo/src/rga_allocator_dma_demo.cpp** + +**/samples/allocator_demo/src/rga_allocator_drm_demo.cpp** + +​ 2). 该问题对应的调用场景为通过wrapbuffer_fd()封装rga_buffer_t或者使用importbuffer_fd后仅运行一帧就立即releasebuffer_handle，这对于临时的测试或者每一帧buffer都是变化的场景是正常的，但本身在实际产品中buffer反复的重新分配这个行为就是性能较差且不合理的，建议整体性的进行优化buffer流程。 + +通常我们建议整体流程按照以下方式进行设计： + +> 1. 构造buffer_pool，分配n个buffer用于作为轮转buffer，n的大小视实际场景进行配置。 +> +> 2. 将这部分buffer 通过importbuffer_fd()导入RGA，获取到RGA的buffer_handle。 +> +> 3. 使用轮转到的buffer_handle调用RGA执行图像操作，反复轮转、循环。 +> 4. 当不再需要这个buffer_pool内的buffer时，调用releasebuffer_handle()释放这部分buffer在RGA内部的引用，以保证后续该buffer能够被释放、销毁。 +> 5. 释放buffer_pool内不需要的buffer。 + +按照上述流程设计，那么即使分配器的map/unmap行为会导致异常耗时也被收敛到importbuffer_fd()/releasebuffer_handle()的调用上，对于实际运行时每一帧调用将不再会有影响，这是一种很好的规避由于内存分配器实现差异引入性能差异的方案。 + +​ 3). 对于无法更改内存分配器以及业务流程的场景，将只能通过修改使用的内存分配器map/unmap流程进行优化耗时，这是十分危险的行为，需要确保自己知晓全部使用该内存分配器的模块的应用行为后，提交redmine咨询对应内存分配器维护者来获取技术支持。 + + + +**Q1.11**：为什么importbuffer_fd()/importbuffer_virtualaddr()调用耗时很高，为什么要调用该API？ + +**A1.11**：该接口相关用法以及说明可以查看源码目录下docs文件夹内的[《Rockchip_Developer_Guide_RGA_CN》](./Rockchip_Developer_Guide_RGA_CN.md)中 “概述” 章节——“[图像缓冲区预处理](./Rockchip_Developer_Guide_RGA_CN.md#图像缓冲区预处理)” 了解用法说明。importbuffer_xx()的作用是将外部的buffer导入到RGA驱动内，使后续每一帧RGA调用都可以通过buffer_handle快速的访问该buffer，而导入外部buffer是比较耗时的操作，需要将外部的buffer映射到RGA驱动内，并保存对应的物理地址以及buffer信息，这对于调用RGA来说是不可缺少的行为。 + + + +**Q1.12**：RGA支持并行的操作么？为什么多线程调用RGA时会出现个别帧耗时增多、翻倍的情况？ + +**A1.12**：RGA API是可以支持多线程/进程并行调用的，但实际硬件上是否并行执行图像操作取决于当前使用芯片搭载的RGA核心数量，即搭载的核心数量则为最大支持的并行任务数量，超过核心数量的任务则会进入等待状态，直到有核心进入空闲状态。因此当并行调用的数量超过了硬件最大支持的并行数量后，那么个别帧的调用将会增加等待硬件空闲的耗时。具体可以通过以下调试节点（具体说明可以查看“驱动调试节点”小节中“硬件信息查询”部分）获取当前芯片搭载的核心数量以及支持的功能： + +```shell +/# cat hardware +``` + + + ### 功能咨询 **Q2.1**：如何知道我当前的芯片平台搭载的RGA版本以及可以实现的功能？ diff --git a/docs/Rockchip_FAQ_RGA_EN.md b/docs/Rockchip_FAQ_RGA_EN.md index dcd0a28..ef1a7b5 100644 --- a/docs/Rockchip_FAQ_RGA_EN.md +++ b/docs/Rockchip_FAQ_RGA_EN.md @@ -565,16 +565,30 @@ rga2: 00000000 00000000 00000000 00000000 rga2: sync one cmd end time 2414 //Print the RGA. hardware time of the work,in us. ``` - - multi + - multi-rga + > Versions below 1.3.0 + ``` rga3_reg: set cmd use time = 196 //Time elapsed from start processing request to configuration register. rga_job: hw use time = 554 //Time-consuming from hardware startup to hardware interrupt return. rga_job: (pid:3197) job done use time = 751 //Time-consuming from the start of processing the request to the completion of the request. rga_job: (pid:3197) job clean use time = 933 //Time-consuming from the start of processing the request to the completion of the request resource processing. ``` - - + + > Version 1.3.0 and above + + ``` + rga_mm: request[3300], get buffer_handle info cost 188 us + rga3_reg: request[3300], generate register cost time 2 us + rga3_reg: request[3300], set register cost time 301 us + rga_job: request[3300], hardware[RGA3_core0] cost time 539 us + rga_mm: request[3300], put buffer_handle info cost 153 us + rga_job: request[3300], job done total cost time 1023 us + rga_job: request[3300], job cleanup total cost time 1030 us + ``` + + ##### Version Information Query @@ -807,7 +821,7 @@ This section introduces common questions about RGA in the form of Q&A. If the pr **Q1.4**：The efficiency of RGA cannot meet the needs of our products. Is there any way to improve it? -**A1.4**：The RGA frequency of the factory firmware of some chips is not the highest frequency. For example, the RGA frequency of chips such as 3399 and 1126 can be up to 400M. The RGA frequency can be improved in the following two ways: +**A1.4**：The RGA frequency of the factory firmware of some chips(Before 2021) is not the highest frequency. For example, the RGA frequency of chips such as 3399 and 1126 can be up to 400M. The RGA frequency can be improved in the following two ways: - Set by command (temporarily modified, frequency restored upon device restart) @@ -919,6 +933,54 @@ Therefore, for this scenario, it is recommended to apply for memory within 4G to +**Q1.10**: Why is the API time-consuming higher than the hardware time printed in the log? + + **Q1.10.1**: Through the "TIME" running log, it is found that the map/unmap buffer takes too much time. + **Q1.10.2**: A comparison of the kernel log timestamps reveals a large gap between the timestamps of the "MSG" log and the "REG" log. + **Q1.10.3**: The same parameter configuration, but using different memory allocators only results in a large difference in running time. + +**A1.10**: The reasons for the time-consuming exception here are all caused by the memory mapping behavior (map/unmap) of the external buffer. All external buffers need to be mapped and bound to the RGA driver to ensure that the hardware can eventually access the specified buffer. The differences in the underlying implementations corresponding to the different allocators can lead to different time consumptions when the driver maps and binds the memory, resulting in a situation where it looks as if the API time consumptions will be much larger than the hardware time consumptions. Common dma-buf allocators with high extra time consumption are ION, V4L2, etc. Usually these differences are related to the synchronization of the cache, and this type of problem can be confirmed by comparing the time consumption of using different allocators. + +This type of issue can usually be optimized in the following ways: + + 1). You can choose a memory allocator that is relatively more reasonable in terms of time consumption for the map/unmap process. Common ones are dma_heap, DRM, and the corresponding wrapper memory allocator. The following is sample code for calling RGA using memory allocated by these memory allocators: + +**/samples/allocator_demo/src/rga_allocator_dma_demo.cpp** + +**/samples/allocator_demo/src/rga_allocator_drm_demo.cpp** + +2). The calling scenario corresponding to this problem is to encapsulate rga_buffer_t through wrapbuffer_fd() or use importbuffer_fd to run only one frame and then immediately releasebuffer_handle. This is normal for temporary tests or scenarios where the buffer changes every frame, but it itself In actual products, repeated buffer reallocation has poor performance and is unreasonable. It is recommended to optimize the buffer process as a whole. + +Generally we recommend that the overall process be designed in the following way: + +> 1. Construct buffer_pool and allocate buffers to be used as rotation buffers. The size of is configured according to the actual scenario. +> 2. Import this buffer into RGA through importbuffer_fd() and obtain the buffer_handle of RGA. +> 3. Use the rotated buffer_handle to call RGA to perform image operations, and repeatedly rotate and loop. +> 4. When the buffer in this buffer_pool is no longer needed, call releasebuffer_handle() to release the reference of this part of the buffer in RGA to ensure that the buffer can be released and destroyed subsequently. +> 5. Release unnecessary buffers in buffer_pool. + +According to the above process design, even if the allocator's map/unmap behavior will cause abnormal time-consuming, it will be converged to the call of importbuffer_fd()/releasebuffer_handle(), and the call will no longer have an impact on each frame of the actual runtime. This is A good way to avoid performance differences due to differences in memory allocator implementation. + + 3). For scenarios where the memory allocator and business process cannot be changed, the time-consuming optimization can only be done by modifying the map/unmap process of the memory allocator used. This is a very dangerous behavior, and you need to ensure that you are aware of all use of the memory. After applying the behavior of the allocator module, submit it to redmine to consult the corresponding memory allocator maintainer for technical support. + + + +**Q1.11**: Why is the importbuffer_fd()/importbuffer_virtualaddr() call time-consuming? Why do we need to call this API? + +**A1.11**: The related usage and instructions of this interface can be viewed in the "Overview" chapter of ["Rockchip_Developer_Guide_RGA_EN"](./Rockchip_Developer_Guide_RGA_EN.md) in the docs folder in the source code directory - "[Image Buffer Preprocessing ](./Rockchip_Developer_Guide_RGA_EN.md#Image Buffer Preprocessing)" for usage instructions. The function of importbuffer_xx() is to import the external buffer into the RGA driver, so that every subsequent frame RGA call can quickly access the buffer through buffer_handle. Importing an external buffer is a time-consuming operation. It is necessary to map the external buffer to the RGA driver and save the corresponding physical address and buffer information. This is indispensable behavior for calling RGA. + + + +**Q1.12**: Does RGA support parallel operations? Why does the time consumption of individual frames increase or double when calling RGA from multiple threads? + +**A1.12**: The RGA API can support parallel calls by multiple threads/processes, but whether image operations can be executed in parallel on the actual hardware depends on the number of RGA cores currently used on the chip. That is, the number of cores installed is the maximum supported number of parallel tasks. Tasks that exceed the number of cores will enter the waiting state until a core enters the idle state. Therefore, when the number of parallel calls exceeds the maximum number of parallel calls supported by the hardware, some frame calls will increase the time spent waiting for the hardware to become idle. Specifically, you can obtain the number of cores and supported functions of the current chip through the following debugging nodes (for specific instructions, please see the "Hardware Information Query" section in the "Drive Debugging Node" section): + +```shell +/# cat hardware +``` + + + ### Functions Consulting **Q2.1**：How do I know what version of RGA is available on my current chip platform and what functions are available? From d1a255496b64a3c4b52546231646e1053f646671 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Wed, 8 Nov 2023 17:50:15 +0800 Subject: [PATCH 34/46] samples: utils: 3rdparty: libdrm: remove useless headers update to 1.10.0_[5] Change-Id: Ica498e33f57c6863994b7fb6779e691d2687a647 Signed-off-by: Yu Qiaowei --- im2d_api/im2d_version.h | 2 +- samples/utils/3rdparty/libdrm/include/demo.h | 136 -- .../3rdparty/libdrm/include/demo_define.h | 44 - .../libdrm/include/libdrm/amdgpu_drm.h | 1067 --------- .../libdrm/include/libdrm/drm_sarea.h | 92 - .../3rdparty/libdrm/include/libdrm/i915_drm.h | 1915 ----------------- .../libdrm/include/libdrm/mach64_drm.h | 256 --- .../3rdparty/libdrm/include/libdrm/mga_drm.h | 427 ---- .../libdrm/include/libdrm/nouveau_drm.h | 221 -- .../3rdparty/libdrm/include/libdrm/qxl_drm.h | 158 -- .../3rdparty/libdrm/include/libdrm/r128_drm.h | 336 --- .../libdrm/include/libdrm/radeon_drm.h | 1079 ---------- .../libdrm/include/libdrm/savage_drm.h | 220 -- .../3rdparty/libdrm/include/libdrm/sis_drm.h | 77 - .../libdrm/include/libdrm/tegra_drm.h | 681 ------ .../3rdparty/libdrm/include/libdrm/vc4_drm.h | 442 ---- .../3rdparty/libdrm/include/libdrm/via_drm.h | 283 --- .../libdrm/include/libdrm/virtgpu_drm.h | 182 -- samples/utils/3rdparty/libdrm/include/tool.h | 145 -- .../3rdparty/libdrm/include/xf86drmMode.h | 551 ----- 20 files changed, 1 insertion(+), 8313 deletions(-) delete mode 100755 samples/utils/3rdparty/libdrm/include/demo.h delete mode 100755 samples/utils/3rdparty/libdrm/include/demo_define.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/amdgpu_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/drm_sarea.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/i915_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/mach64_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/mga_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/nouveau_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/qxl_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/r128_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/radeon_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/savage_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/sis_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/tegra_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/vc4_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/via_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/libdrm/virtgpu_drm.h delete mode 100755 samples/utils/3rdparty/libdrm/include/tool.h delete mode 100755 samples/utils/3rdparty/libdrm/include/xf86drmMode.h diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index d0b4aee..2ea735a 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -26,7 +26,7 @@ #define RGA_API_MAJOR_VERSION 1 #define RGA_API_MINOR_VERSION 10 #define RGA_API_REVISION_VERSION 0 -#define RGA_API_BUILD_VERSION 4 +#define RGA_API_BUILD_VERSION 5 #define RGA_API_SUFFIX diff --git a/samples/utils/3rdparty/libdrm/include/demo.h b/samples/utils/3rdparty/libdrm/include/demo.h deleted file mode 100755 index 0aafc91..0000000 --- a/samples/utils/3rdparty/libdrm/include/demo.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - - */ - -#ifndef DEMO_H_ -#define DEMO_H_ -//ڴ˴ͷļ -#include "stdio.h" -#include "string.h" -#include "stdlib.h" -#include "math.h" - -#include "demo_define.h" -#include "tool.h" -#include "inital_alg_params_ynr.h" -#include "inital_alg_params_gic.h" -#include "inital_alg_params_lsc.h" -#include "inital_alg_params_lsc2.h" -#include "inital_alg_params_rk_shapren_HW.h" -#include "inital_alg_params_rk_edgefilter.h" - -#include "initial_alg_params_bayernr.h" - -#include "inital_alg_params_rkuvnr.h" -#include "inital_alg_params_rk_cnr.h" - -#include "inital_alg_params_mfnr.h" -#include "rk_aiq_awb_algo_v200.h" -#define FILE_RAW_EXT ".raw" -#define FILE_YUV_EXT ".yuv" -#define FILE_DAT_EXT ".dat" - -typedef enum YUV_FILE_FMT -{ - F_YUV_420SP = 0x00, - F_YUV_420P = 0x01, - F_YUV_422I = 0x02, - F_YUV_422SP = 0x03, - F_YUV_422P = 0x04, - F_YUV_444I = 0x05, - - F_YUV_MAX = 0x10, -}YUV_FILE_FMT_t; - -typedef enum INPUT_FILE_FMT -{ - F_IN_FMT_RAW = 0x00, - F_IN_FMT_YUV, - - - F_IN_FMT_MAX = 0x10, -}INPUT_FILE_FMT_t; - - - -//˴ -typedef struct tag_config_com -{ - int exp_info_en ; - int framenum ; - int rawwid ; - int rawhgt ; - int rawbit ; - int bayerfmt ; - int yuvbit ; - int yuvfmt ; -}tag_config_com; - -typedef struct tag_config_txt -{ - tag_config_com config_com; - - int framecnt ; - int iso ; - int exptime[3] ; - int expgain[3] ; - int rgain ; - int bgain ; - int grgain ; - int gbgain ; - int dGain ; - int lux ; -}tag_config_txt; - -typedef struct tag_ST_DEMO_INPUT_PARAMS -{ - int width; //rawͼ - int height; //rawͼ - int bayerPattern; //bayer patternʽ:0--BGGR,1--GBRG,2--GRBG,3--RGGB - int yuvFmt; //yuv file ʽ: YUV_FILE_FMT_t - int bitValue; //rawλ - int hdr_framenum; - float expGain[MAX_HDR_FRM_NUM]; // - float expTime[MAX_HDR_FRM_NUM]; //عʱ - int rGain; //wb rgain - int bGain; //wb bgain - int grGain; //wb grgain - int gbGain; //wb gbgain - int dGain; //wb gbgain - int fileFmt; //input file format:INPUT_FILE_FMT_t - int width_full; //rawͼ - int height_full; //rawͼ - int crop_width; - int crop_height; - int crop_xoffset; - int crop_yoffset; - - char pathFileCfg[256];//configļ· - char pathRawData[256];//rawͼ· - char nameRawData[256];//rawͼ - char pathExpInfo[256];//exp_infoļ· - char pathReslut[256];//ļ· - char suffix[256]; // ļ׺ַ - char pathRtlin[256]; //rtl in path - int skip_num; - int frame_end; - - int hdr_proc_mode; - int out_mode; - - - char dbgFlg[1024]; // must > ISP_CAP_MAX - int config_full; - - int exp_info_en; - int file_info_en; - FILE *fp_exp_info; -}ST_DEMO_INPUT_PARAMS; - - - -//˴ - - - -#endif // DEMO_H_ diff --git a/samples/utils/3rdparty/libdrm/include/demo_define.h b/samples/utils/3rdparty/libdrm/include/demo_define.h deleted file mode 100755 index da7d26e..0000000 --- a/samples/utils/3rdparty/libdrm/include/demo_define.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - - */ - -#ifndef DEFINE_H_ -#define DEFINE_H_ -//ڴ˴ͷļ - - - -#define S7_EDGE 1 -#define GZ 2 -#define DVR 3 -/* -#define ISP_BAYER_NR 1 -#define ISP_DPC 2 -#define ISP_BLC 3 -#define ISP_STAT_3A 4 -#define ISP_LSC 5 -#define ISP_AWBG 6 -#define ISP_VHDM 7 -#define ISP_GAMMA 8 -#define ISP_CSM 9 -#define ISP_DRC 10 -#define ISP_RGB2YUV 11 -#define ISP_LCE 12 -#define ISP_Y_NR 13 -#define ISP_SHARPEN 14 -#define ISP_SCALING 15 -#define ISP_GIC 16 -#define ISP_UV_NR 17 -#define ISP_HDR_MERGE 18 -#define ISP_HDR_TMO 19 -#define ISP_DPN 20 -#define ISP_CTK 21 -#define ISP_WDR 22 -*/ -#define SAVE_RESULT 1 - - -//#define GET_LSC_CALIBRATION_DATA //ȡlens shadingУ궨 - - -#endif // DEFINE_H_ diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/amdgpu_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/amdgpu_drm.h deleted file mode 100755 index 4fe35d6..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/amdgpu_drm.h +++ /dev/null @@ -1,1067 +0,0 @@ -/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - * Keith Whitwell - */ - -#ifndef __AMDGPU_DRM_H__ -#define __AMDGPU_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_AMDGPU_GEM_CREATE 0x00 -#define DRM_AMDGPU_GEM_MMAP 0x01 -#define DRM_AMDGPU_CTX 0x02 -#define DRM_AMDGPU_BO_LIST 0x03 -#define DRM_AMDGPU_CS 0x04 -#define DRM_AMDGPU_INFO 0x05 -#define DRM_AMDGPU_GEM_METADATA 0x06 -#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 -#define DRM_AMDGPU_GEM_VA 0x08 -#define DRM_AMDGPU_WAIT_CS 0x09 -#define DRM_AMDGPU_GEM_OP 0x10 -#define DRM_AMDGPU_GEM_USERPTR 0x11 -#define DRM_AMDGPU_WAIT_FENCES 0x12 -#define DRM_AMDGPU_VM 0x13 -#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 -#define DRM_AMDGPU_SCHED 0x15 - -#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) -#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) -#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) -#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) -#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) -#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) -#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) -#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) -#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) -#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) -#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) -#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) -#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) -#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) -#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) - -/** - * DOC: memory domains - * - * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. - * Memory in this pool could be swapped out to disk if there is pressure. - * - * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the - * GPU's virtual address space via gart. Gart memory linearizes non-contiguous - * pages of system memory, allows GPU access system memory in a linezrized - * fashion. - * - * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory - * carved out by the BIOS. - * - * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data - * across shader threads. - * - * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the - * execution of all the waves on a device. - * - * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines - * for appending data. - */ -#define AMDGPU_GEM_DOMAIN_CPU 0x1 -#define AMDGPU_GEM_DOMAIN_GTT 0x2 -#define AMDGPU_GEM_DOMAIN_VRAM 0x4 -#define AMDGPU_GEM_DOMAIN_GDS 0x8 -#define AMDGPU_GEM_DOMAIN_GWS 0x10 -#define AMDGPU_GEM_DOMAIN_OA 0x20 -#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ - AMDGPU_GEM_DOMAIN_GTT | \ - AMDGPU_GEM_DOMAIN_VRAM | \ - AMDGPU_GEM_DOMAIN_GDS | \ - AMDGPU_GEM_DOMAIN_GWS | \ - AMDGPU_GEM_DOMAIN_OA) - -/* Flag that CPU access will be required for the case of VRAM domain */ -#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) -/* Flag that CPU access will not work, this VRAM domain is invisible */ -#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) -/* Flag that USWC attributes should be used for GTT */ -#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) -/* Flag that the memory should be in VRAM and cleared */ -#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) -/* Flag that create shadow bo(GTT) while allocating vram bo */ -#define AMDGPU_GEM_CREATE_SHADOW (1 << 4) -/* Flag that allocating the BO should use linear VRAM */ -#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) -/* Flag that BO is always valid in this VM */ -#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) -/* Flag that BO sharing will be explicitly synchronized */ -#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) -/* Flag that indicates allocating MQD gart on GFX9, where the mtype - * for the second page onward should be set to NC. - */ -#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) -/* Flag that BO may contain sensitive data that must be wiped before - * releasing the memory - */ -#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) - -struct drm_amdgpu_gem_create_in { - /** the requested memory size */ - __u64 bo_size; - /** physical start_addr alignment in bytes for some HW requirements */ - __u64 alignment; - /** the requested memory domains */ - __u64 domains; - /** allocation flags */ - __u64 domain_flags; -}; - -struct drm_amdgpu_gem_create_out { - /** returned GEM object handle */ - __u32 handle; - __u32 _pad; -}; - -union drm_amdgpu_gem_create { - struct drm_amdgpu_gem_create_in in; - struct drm_amdgpu_gem_create_out out; -}; - -/** Opcode to create new residency list. */ -#define AMDGPU_BO_LIST_OP_CREATE 0 -/** Opcode to destroy previously created residency list */ -#define AMDGPU_BO_LIST_OP_DESTROY 1 -/** Opcode to update resource information in the list */ -#define AMDGPU_BO_LIST_OP_UPDATE 2 - -struct drm_amdgpu_bo_list_in { - /** Type of operation */ - __u32 operation; - /** Handle of list or 0 if we want to create one */ - __u32 list_handle; - /** Number of BOs in list */ - __u32 bo_number; - /** Size of each element describing BO */ - __u32 bo_info_size; - /** Pointer to array describing BOs */ - __u64 bo_info_ptr; -}; - -struct drm_amdgpu_bo_list_entry { - /** Handle of BO */ - __u32 bo_handle; - /** New (if specified) BO priority to be used during migration */ - __u32 bo_priority; -}; - -struct drm_amdgpu_bo_list_out { - /** Handle of resource list */ - __u32 list_handle; - __u32 _pad; -}; - -union drm_amdgpu_bo_list { - struct drm_amdgpu_bo_list_in in; - struct drm_amdgpu_bo_list_out out; -}; - -/* context related */ -#define AMDGPU_CTX_OP_ALLOC_CTX 1 -#define AMDGPU_CTX_OP_FREE_CTX 2 -#define AMDGPU_CTX_OP_QUERY_STATE 3 -#define AMDGPU_CTX_OP_QUERY_STATE2 4 - -/* GPU reset status */ -#define AMDGPU_CTX_NO_RESET 0 -/* this the context caused it */ -#define AMDGPU_CTX_GUILTY_RESET 1 -/* some other context caused it */ -#define AMDGPU_CTX_INNOCENT_RESET 2 -/* unknown cause */ -#define AMDGPU_CTX_UNKNOWN_RESET 3 - -/* indicate gpu reset occured after ctx created */ -#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) -/* indicate vram lost occured after ctx created */ -#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) -/* indicate some job from this context once cause gpu hang */ -#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) -/* indicate some errors are detected by RAS */ -#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) -#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) - -/* Context priority level */ -#define AMDGPU_CTX_PRIORITY_UNSET -2048 -#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 -#define AMDGPU_CTX_PRIORITY_LOW -512 -#define AMDGPU_CTX_PRIORITY_NORMAL 0 -/* - * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires - * CAP_SYS_NICE or DRM_MASTER -*/ -#define AMDGPU_CTX_PRIORITY_HIGH 512 -#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 - -struct drm_amdgpu_ctx_in { - /** AMDGPU_CTX_OP_* */ - __u32 op; - /** For future use, no flags defined so far */ - __u32 flags; - __u32 ctx_id; - /** AMDGPU_CTX_PRIORITY_* */ - __s32 priority; -}; - -union drm_amdgpu_ctx_out { - struct { - __u32 ctx_id; - __u32 _pad; - } alloc; - - struct { - /** For future use, no flags defined so far */ - __u64 flags; - /** Number of resets caused by this context so far. */ - __u32 hangs; - /** Reset status since the last call of the ioctl. */ - __u32 reset_status; - } state; -}; - -union drm_amdgpu_ctx { - struct drm_amdgpu_ctx_in in; - union drm_amdgpu_ctx_out out; -}; - -/* vm ioctl */ -#define AMDGPU_VM_OP_RESERVE_VMID 1 -#define AMDGPU_VM_OP_UNRESERVE_VMID 2 - -struct drm_amdgpu_vm_in { - /** AMDGPU_VM_OP_* */ - __u32 op; - __u32 flags; -}; - -struct drm_amdgpu_vm_out { - /** For future use, no flags defined so far */ - __u64 flags; -}; - -union drm_amdgpu_vm { - struct drm_amdgpu_vm_in in; - struct drm_amdgpu_vm_out out; -}; - -/* sched ioctl */ -#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 -#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 - -struct drm_amdgpu_sched_in { - /* AMDGPU_SCHED_OP_* */ - __u32 op; - __u32 fd; - /** AMDGPU_CTX_PRIORITY_* */ - __s32 priority; - __u32 ctx_id; -}; - -union drm_amdgpu_sched { - struct drm_amdgpu_sched_in in; -}; - -/* - * This is not a reliable API and you should expect it to fail for any - * number of reasons and have fallback path that do not use userptr to - * perform any operation. - */ -#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) -#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) -#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) -#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) - -struct drm_amdgpu_gem_userptr { - __u64 addr; - __u64 size; - /* AMDGPU_GEM_USERPTR_* */ - __u32 flags; - /* Resulting GEM handle */ - __u32 handle; -}; - -/* SI-CI-VI: */ -/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ -#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 -#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf -#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 -#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f -#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 -#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 -#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 -#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 -#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 -#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 -#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 -#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 -#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 -#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 -#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 -#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 - -/* GFX9 and later: */ -#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 -#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f -#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 -#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF -#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 -#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF -#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 -#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 - -/* Set/Get helpers for tiling flags. */ -#define AMDGPU_TILING_SET(field, value) \ - (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) -#define AMDGPU_TILING_GET(value, field) \ - (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) - -#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 -#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 - -/** The same structure is shared for input/output */ -struct drm_amdgpu_gem_metadata { - /** GEM Object handle */ - __u32 handle; - /** Do we want get or set metadata */ - __u32 op; - struct { - /** For future use, no flags defined so far */ - __u64 flags; - /** family specific tiling info */ - __u64 tiling_info; - __u32 data_size_bytes; - __u32 data[64]; - } data; -}; - -struct drm_amdgpu_gem_mmap_in { - /** the GEM object handle */ - __u32 handle; - __u32 _pad; -}; - -struct drm_amdgpu_gem_mmap_out { - /** mmap offset from the vma offset manager */ - __u64 addr_ptr; -}; - -union drm_amdgpu_gem_mmap { - struct drm_amdgpu_gem_mmap_in in; - struct drm_amdgpu_gem_mmap_out out; -}; - -struct drm_amdgpu_gem_wait_idle_in { - /** GEM object handle */ - __u32 handle; - /** For future use, no flags defined so far */ - __u32 flags; - /** Absolute timeout to wait */ - __u64 timeout; -}; - -struct drm_amdgpu_gem_wait_idle_out { - /** BO status: 0 - BO is idle, 1 - BO is busy */ - __u32 status; - /** Returned current memory domain */ - __u32 domain; -}; - -union drm_amdgpu_gem_wait_idle { - struct drm_amdgpu_gem_wait_idle_in in; - struct drm_amdgpu_gem_wait_idle_out out; -}; - -struct drm_amdgpu_wait_cs_in { - /* Command submission handle - * handle equals 0 means none to wait for - * handle equals ~0ull means wait for the latest sequence number - */ - __u64 handle; - /** Absolute timeout to wait */ - __u64 timeout; - __u32 ip_type; - __u32 ip_instance; - __u32 ring; - __u32 ctx_id; -}; - -struct drm_amdgpu_wait_cs_out { - /** CS status: 0 - CS completed, 1 - CS still busy */ - __u64 status; -}; - -union drm_amdgpu_wait_cs { - struct drm_amdgpu_wait_cs_in in; - struct drm_amdgpu_wait_cs_out out; -}; - -struct drm_amdgpu_fence { - __u32 ctx_id; - __u32 ip_type; - __u32 ip_instance; - __u32 ring; - __u64 seq_no; -}; - -struct drm_amdgpu_wait_fences_in { - /** This points to uint64_t * which points to fences */ - __u64 fences; - __u32 fence_count; - __u32 wait_all; - __u64 timeout_ns; -}; - -struct drm_amdgpu_wait_fences_out { - __u32 status; - __u32 first_signaled; -}; - -union drm_amdgpu_wait_fences { - struct drm_amdgpu_wait_fences_in in; - struct drm_amdgpu_wait_fences_out out; -}; - -#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 -#define AMDGPU_GEM_OP_SET_PLACEMENT 1 - -/* Sets or returns a value associated with a buffer. */ -struct drm_amdgpu_gem_op { - /** GEM object handle */ - __u32 handle; - /** AMDGPU_GEM_OP_* */ - __u32 op; - /** Input or return value */ - __u64 value; -}; - -#define AMDGPU_VA_OP_MAP 1 -#define AMDGPU_VA_OP_UNMAP 2 -#define AMDGPU_VA_OP_CLEAR 3 -#define AMDGPU_VA_OP_REPLACE 4 - -/* Delay the page table update till the next CS */ -#define AMDGPU_VM_DELAY_UPDATE (1 << 0) - -/* Mapping flags */ -/* readable mapping */ -#define AMDGPU_VM_PAGE_READABLE (1 << 1) -/* writable mapping */ -#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) -/* executable mapping, new for VI */ -#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) -/* partially resident texture */ -#define AMDGPU_VM_PAGE_PRT (1 << 4) -/* MTYPE flags use bit 5 to 8 */ -#define AMDGPU_VM_MTYPE_MASK (0xf << 5) -/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ -#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) -/* Use NC MTYPE instead of default MTYPE */ -#define AMDGPU_VM_MTYPE_NC (1 << 5) -/* Use WC MTYPE instead of default MTYPE */ -#define AMDGPU_VM_MTYPE_WC (2 << 5) -/* Use CC MTYPE instead of default MTYPE */ -#define AMDGPU_VM_MTYPE_CC (3 << 5) -/* Use UC MTYPE instead of default MTYPE */ -#define AMDGPU_VM_MTYPE_UC (4 << 5) - -struct drm_amdgpu_gem_va { - /** GEM object handle */ - __u32 handle; - __u32 _pad; - /** AMDGPU_VA_OP_* */ - __u32 operation; - /** AMDGPU_VM_PAGE_* */ - __u32 flags; - /** va address to assign . Must be correctly aligned.*/ - __u64 va_address; - /** Specify offset inside of BO to assign. Must be correctly aligned.*/ - __u64 offset_in_bo; - /** Specify mapping size. Must be correctly aligned. */ - __u64 map_size; -}; - -#define AMDGPU_HW_IP_GFX 0 -#define AMDGPU_HW_IP_COMPUTE 1 -#define AMDGPU_HW_IP_DMA 2 -#define AMDGPU_HW_IP_UVD 3 -#define AMDGPU_HW_IP_VCE 4 -#define AMDGPU_HW_IP_UVD_ENC 5 -#define AMDGPU_HW_IP_VCN_DEC 6 -#define AMDGPU_HW_IP_VCN_ENC 7 -#define AMDGPU_HW_IP_VCN_JPEG 8 -#define AMDGPU_HW_IP_NUM 9 - -#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 - -#define AMDGPU_CHUNK_ID_IB 0x01 -#define AMDGPU_CHUNK_ID_FENCE 0x02 -#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 -#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 -#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 -#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 -#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 -#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 -#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 - -struct drm_amdgpu_cs_chunk { - __u32 chunk_id; - __u32 length_dw; - __u64 chunk_data; -}; - -struct drm_amdgpu_cs_in { - /** Rendering context id */ - __u32 ctx_id; - /** Handle of resource list associated with CS */ - __u32 bo_list_handle; - __u32 num_chunks; - __u32 _pad; - /** this points to __u64 * which point to cs chunks */ - __u64 chunks; -}; - -struct drm_amdgpu_cs_out { - __u64 handle; -}; - -union drm_amdgpu_cs { - struct drm_amdgpu_cs_in in; - struct drm_amdgpu_cs_out out; -}; - -/* Specify flags to be used for IB */ - -/* This IB should be submitted to CE */ -#define AMDGPU_IB_FLAG_CE (1<<0) - -/* Preamble flag, which means the IB could be dropped if no context switch */ -#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) - -/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ -#define AMDGPU_IB_FLAG_PREEMPT (1<<2) - -/* The IB fence should do the L2 writeback but not invalidate any shader - * caches (L2/vL1/sL1/I$). */ -#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) - -/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. - * This will reset wave ID counters for the IB. - */ -#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) - -struct drm_amdgpu_cs_chunk_ib { - __u32 _pad; - /** AMDGPU_IB_FLAG_* */ - __u32 flags; - /** Virtual address to begin IB execution */ - __u64 va_start; - /** Size of submission */ - __u32 ib_bytes; - /** HW IP to submit to */ - __u32 ip_type; - /** HW IP index of the same type to submit to */ - __u32 ip_instance; - /** Ring index to submit to */ - __u32 ring; -}; - -struct drm_amdgpu_cs_chunk_dep { - __u32 ip_type; - __u32 ip_instance; - __u32 ring; - __u32 ctx_id; - __u64 handle; -}; - -struct drm_amdgpu_cs_chunk_fence { - __u32 handle; - __u32 offset; -}; - -struct drm_amdgpu_cs_chunk_sem { - __u32 handle; -}; - -struct drm_amdgpu_cs_chunk_syncobj { - __u32 handle; - __u32 flags; - __u64 point; -}; - -#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 -#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 -#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 - -union drm_amdgpu_fence_to_handle { - struct { - struct drm_amdgpu_fence fence; - __u32 what; - __u32 pad; - } in; - struct { - __u32 handle; - } out; -}; - -struct drm_amdgpu_cs_chunk_data { - union { - struct drm_amdgpu_cs_chunk_ib ib_data; - struct drm_amdgpu_cs_chunk_fence fence_data; - }; -}; - -/** - * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU - * - */ -#define AMDGPU_IDS_FLAGS_FUSION 0x1 -#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 - -/* indicate if acceleration can be working */ -#define AMDGPU_INFO_ACCEL_WORKING 0x00 -/* get the crtc_id from the mode object id? */ -#define AMDGPU_INFO_CRTC_FROM_ID 0x01 -/* query hw IP info */ -#define AMDGPU_INFO_HW_IP_INFO 0x02 -/* query hw IP instance count for the specified type */ -#define AMDGPU_INFO_HW_IP_COUNT 0x03 -/* timestamp for GL_ARB_timer_query */ -#define AMDGPU_INFO_TIMESTAMP 0x05 -/* Query the firmware version */ -#define AMDGPU_INFO_FW_VERSION 0x0e - /* Subquery id: Query VCE firmware version */ - #define AMDGPU_INFO_FW_VCE 0x1 - /* Subquery id: Query UVD firmware version */ - #define AMDGPU_INFO_FW_UVD 0x2 - /* Subquery id: Query GMC firmware version */ - #define AMDGPU_INFO_FW_GMC 0x03 - /* Subquery id: Query GFX ME firmware version */ - #define AMDGPU_INFO_FW_GFX_ME 0x04 - /* Subquery id: Query GFX PFP firmware version */ - #define AMDGPU_INFO_FW_GFX_PFP 0x05 - /* Subquery id: Query GFX CE firmware version */ - #define AMDGPU_INFO_FW_GFX_CE 0x06 - /* Subquery id: Query GFX RLC firmware version */ - #define AMDGPU_INFO_FW_GFX_RLC 0x07 - /* Subquery id: Query GFX MEC firmware version */ - #define AMDGPU_INFO_FW_GFX_MEC 0x08 - /* Subquery id: Query SMC firmware version */ - #define AMDGPU_INFO_FW_SMC 0x0a - /* Subquery id: Query SDMA firmware version */ - #define AMDGPU_INFO_FW_SDMA 0x0b - /* Subquery id: Query PSP SOS firmware version */ - #define AMDGPU_INFO_FW_SOS 0x0c - /* Subquery id: Query PSP ASD firmware version */ - #define AMDGPU_INFO_FW_ASD 0x0d - /* Subquery id: Query VCN firmware version */ - #define AMDGPU_INFO_FW_VCN 0x0e - /* Subquery id: Query GFX RLC SRLC firmware version */ - #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f - /* Subquery id: Query GFX RLC SRLG firmware version */ - #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 - /* Subquery id: Query GFX RLC SRLS firmware version */ - #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 - /* Subquery id: Query DMCU firmware version */ - #define AMDGPU_INFO_FW_DMCU 0x12 - #define AMDGPU_INFO_FW_TA 0x13 -/* number of bytes moved for TTM migration */ -#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f -/* the used VRAM size */ -#define AMDGPU_INFO_VRAM_USAGE 0x10 -/* the used GTT size */ -#define AMDGPU_INFO_GTT_USAGE 0x11 -/* Information about GDS, etc. resource configuration */ -#define AMDGPU_INFO_GDS_CONFIG 0x13 -/* Query information about VRAM and GTT domains */ -#define AMDGPU_INFO_VRAM_GTT 0x14 -/* Query information about register in MMR address space*/ -#define AMDGPU_INFO_READ_MMR_REG 0x15 -/* Query information about device: rev id, family, etc. */ -#define AMDGPU_INFO_DEV_INFO 0x16 -/* visible vram usage */ -#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 -/* number of TTM buffer evictions */ -#define AMDGPU_INFO_NUM_EVICTIONS 0x18 -/* Query memory about VRAM and GTT domains */ -#define AMDGPU_INFO_MEMORY 0x19 -/* Query vce clock table */ -#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A -/* Query vbios related information */ -#define AMDGPU_INFO_VBIOS 0x1B - /* Subquery id: Query vbios size */ - #define AMDGPU_INFO_VBIOS_SIZE 0x1 - /* Subquery id: Query vbios image */ - #define AMDGPU_INFO_VBIOS_IMAGE 0x2 -/* Query UVD handles */ -#define AMDGPU_INFO_NUM_HANDLES 0x1C -/* Query sensor related information */ -#define AMDGPU_INFO_SENSOR 0x1D - /* Subquery id: Query GPU shader clock */ - #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 - /* Subquery id: Query GPU memory clock */ - #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 - /* Subquery id: Query GPU temperature */ - #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 - /* Subquery id: Query GPU load */ - #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 - /* Subquery id: Query average GPU power */ - #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 - /* Subquery id: Query northbridge voltage */ - #define AMDGPU_INFO_SENSOR_VDDNB 0x6 - /* Subquery id: Query graphics voltage */ - #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 - /* Subquery id: Query GPU stable pstate shader clock */ - #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 - /* Subquery id: Query GPU stable pstate memory clock */ - #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 -/* Number of VRAM page faults on CPU access. */ -#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E -#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F -/* query ras mask of enabled features*/ -#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 - -/* RAS MASK: UMC (VRAM) */ -#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) -/* RAS MASK: SDMA */ -#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) -/* RAS MASK: GFX */ -#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) -/* RAS MASK: MMHUB */ -#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) -/* RAS MASK: ATHUB */ -#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) -/* RAS MASK: PCIE */ -#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) -/* RAS MASK: HDP */ -#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) -/* RAS MASK: XGMI */ -#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) -/* RAS MASK: DF */ -#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) -/* RAS MASK: SMN */ -#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) -/* RAS MASK: SEM */ -#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) -/* RAS MASK: MP0 */ -#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) -/* RAS MASK: MP1 */ -#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) -/* RAS MASK: FUSE */ -#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) - -#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 -#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 -#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff - -struct drm_amdgpu_query_fw { - /** AMDGPU_INFO_FW_* */ - __u32 fw_type; - /** - * Index of the IP if there are more IPs of - * the same type. - */ - __u32 ip_instance; - /** - * Index of the engine. Whether this is used depends - * on the firmware type. (e.g. MEC, SDMA) - */ - __u32 index; - __u32 _pad; -}; - -/* Input structure for the INFO ioctl */ -struct drm_amdgpu_info { - /* Where the return value will be stored */ - __u64 return_pointer; - /* The size of the return value. Just like "size" in "snprintf", - * it limits how many bytes the kernel can write. */ - __u32 return_size; - /* The query request id. */ - __u32 query; - - union { - struct { - __u32 id; - __u32 _pad; - } mode_crtc; - - struct { - /** AMDGPU_HW_IP_* */ - __u32 type; - /** - * Index of the IP if there are more IPs of the same - * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. - */ - __u32 ip_instance; - } query_hw_ip; - - struct { - __u32 dword_offset; - /** number of registers to read */ - __u32 count; - __u32 instance; - /** For future use, no flags defined so far */ - __u32 flags; - } read_mmr_reg; - - struct drm_amdgpu_query_fw query_fw; - - struct { - __u32 type; - __u32 offset; - } vbios_info; - - struct { - __u32 type; - } sensor_info; - }; -}; - -struct drm_amdgpu_info_gds { - /** GDS GFX partition size */ - __u32 gds_gfx_partition_size; - /** GDS compute partition size */ - __u32 compute_partition_size; - /** total GDS memory size */ - __u32 gds_total_size; - /** GWS size per GFX partition */ - __u32 gws_per_gfx_partition; - /** GSW size per compute partition */ - __u32 gws_per_compute_partition; - /** OA size per GFX partition */ - __u32 oa_per_gfx_partition; - /** OA size per compute partition */ - __u32 oa_per_compute_partition; - __u32 _pad; -}; - -struct drm_amdgpu_info_vram_gtt { - __u64 vram_size; - __u64 vram_cpu_accessible_size; - __u64 gtt_size; -}; - -struct drm_amdgpu_heap_info { - /** max. physical memory */ - __u64 total_heap_size; - - /** Theoretical max. available memory in the given heap */ - __u64 usable_heap_size; - - /** - * Number of bytes allocated in the heap. This includes all processes - * and private allocations in the kernel. It changes when new buffers - * are allocated, freed, and moved. It cannot be larger than - * heap_size. - */ - __u64 heap_usage; - - /** - * Theoretical possible max. size of buffer which - * could be allocated in the given heap - */ - __u64 max_allocation; -}; - -struct drm_amdgpu_memory_info { - struct drm_amdgpu_heap_info vram; - struct drm_amdgpu_heap_info cpu_accessible_vram; - struct drm_amdgpu_heap_info gtt; -}; - -struct drm_amdgpu_info_firmware { - __u32 ver; - __u32 feature; -}; - -#define AMDGPU_VRAM_TYPE_UNKNOWN 0 -#define AMDGPU_VRAM_TYPE_GDDR1 1 -#define AMDGPU_VRAM_TYPE_DDR2 2 -#define AMDGPU_VRAM_TYPE_GDDR3 3 -#define AMDGPU_VRAM_TYPE_GDDR4 4 -#define AMDGPU_VRAM_TYPE_GDDR5 5 -#define AMDGPU_VRAM_TYPE_HBM 6 -#define AMDGPU_VRAM_TYPE_DDR3 7 -#define AMDGPU_VRAM_TYPE_DDR4 8 -#define AMDGPU_VRAM_TYPE_GDDR6 9 - -struct drm_amdgpu_info_device { - /** PCI Device ID */ - __u32 device_id; - /** Internal chip revision: A0, A1, etc.) */ - __u32 chip_rev; - __u32 external_rev; - /** Revision id in PCI Config space */ - __u32 pci_rev; - __u32 family; - __u32 num_shader_engines; - __u32 num_shader_arrays_per_engine; - /* in KHz */ - __u32 gpu_counter_freq; - __u64 max_engine_clock; - __u64 max_memory_clock; - /* cu information */ - __u32 cu_active_number; - /* NOTE: cu_ao_mask is INVALID, DON'T use it */ - __u32 cu_ao_mask; - __u32 cu_bitmap[4][4]; - /** Render backend pipe mask. One render backend is CB+DB. */ - __u32 enabled_rb_pipes_mask; - __u32 num_rb_pipes; - __u32 num_hw_gfx_contexts; - __u32 _pad; - __u64 ids_flags; - /** Starting virtual address for UMDs. */ - __u64 virtual_address_offset; - /** The maximum virtual address */ - __u64 virtual_address_max; - /** Required alignment of virtual addresses. */ - __u32 virtual_address_alignment; - /** Page table entry - fragment size */ - __u32 pte_fragment_size; - __u32 gart_page_size; - /** constant engine ram size*/ - __u32 ce_ram_size; - /** video memory type info*/ - __u32 vram_type; - /** video memory bit width*/ - __u32 vram_bit_width; - /* vce harvesting instance */ - __u32 vce_harvest_config; - /* gfx double offchip LDS buffers */ - __u32 gc_double_offchip_lds_buf; - /* NGG Primitive Buffer */ - __u64 prim_buf_gpu_addr; - /* NGG Position Buffer */ - __u64 pos_buf_gpu_addr; - /* NGG Control Sideband */ - __u64 cntl_sb_buf_gpu_addr; - /* NGG Parameter Cache */ - __u64 param_buf_gpu_addr; - __u32 prim_buf_size; - __u32 pos_buf_size; - __u32 cntl_sb_buf_size; - __u32 param_buf_size; - /* wavefront size*/ - __u32 wave_front_size; - /* shader visible vgprs*/ - __u32 num_shader_visible_vgprs; - /* CU per shader array*/ - __u32 num_cu_per_sh; - /* number of tcc blocks*/ - __u32 num_tcc_blocks; - /* gs vgt table depth*/ - __u32 gs_vgt_table_depth; - /* gs primitive buffer depth*/ - __u32 gs_prim_buffer_depth; - /* max gs wavefront per vgt*/ - __u32 max_gs_waves_per_vgt; - __u32 _pad1; - /* always on cu bitmap */ - __u32 cu_ao_bitmap[4][4]; - /** Starting high virtual address for UMDs. */ - __u64 high_va_offset; - /** The maximum high virtual address */ - __u64 high_va_max; - /* gfx10 pa_sc_tile_steering_override */ - __u32 pa_sc_tile_steering_override; - /* disabled TCCs */ - __u64 tcc_disabled_mask; -}; - -struct drm_amdgpu_info_hw_ip { - /** Version of h/w IP */ - __u32 hw_ip_version_major; - __u32 hw_ip_version_minor; - /** Capabilities */ - __u64 capabilities_flags; - /** command buffer address start alignment*/ - __u32 ib_start_alignment; - /** command buffer size alignment*/ - __u32 ib_size_alignment; - /** Bitmask of available rings. Bit 0 means ring 0, etc. */ - __u32 available_rings; - __u32 _pad; -}; - -struct drm_amdgpu_info_num_handles { - /** Max handles as supported by firmware for UVD */ - __u32 uvd_max_handles; - /** Handles currently in use for UVD */ - __u32 uvd_used_handles; -}; - -#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 - -struct drm_amdgpu_info_vce_clock_table_entry { - /** System clock */ - __u32 sclk; - /** Memory clock */ - __u32 mclk; - /** VCE clock */ - __u32 eclk; - __u32 pad; -}; - -struct drm_amdgpu_info_vce_clock_table { - struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; - __u32 num_valid_entries; - __u32 pad; -}; - -/* - * Supported GPU families - */ -#define AMDGPU_FAMILY_UNKNOWN 0 -#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ -#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ -#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ -#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ -#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ -#define AMDGPU_FAMILY_AI 141 /* Vega10 */ -#define AMDGPU_FAMILY_RV 142 /* Raven */ -#define AMDGPU_FAMILY_NV 143 /* Navi10 */ - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/drm_sarea.h b/samples/utils/3rdparty/libdrm/include/libdrm/drm_sarea.h deleted file mode 100755 index 93025be..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/drm_sarea.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * \file drm_sarea.h - * \brief SAREA definitions - * - * \author Michel Dänzer - */ - -/* - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DRM_SAREA_H_ -#define _DRM_SAREA_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* SAREA area needs to be at least a page */ -#if defined(__alpha__) -#define SAREA_MAX 0x2000U -#elif defined(__mips__) -#define SAREA_MAX 0x4000U -#elif defined(__ia64__) -#define SAREA_MAX 0x10000U /* 64kB */ -#else -/* Intel 830M driver needs at least 8k SAREA */ -#define SAREA_MAX 0x2000U -#endif - -/** Maximum number of drawables in the SAREA */ -#define SAREA_MAX_DRAWABLES 256 - -#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 - -/** SAREA drawable */ -struct drm_sarea_drawable { - unsigned int stamp; - unsigned int flags; -}; - -/** SAREA frame */ -struct drm_sarea_frame { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int fullscreen; -}; - -/** SAREA */ -struct drm_sarea { - /** first thing is always the DRM locking structure */ - struct drm_hw_lock lock; - /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ - struct drm_hw_lock drawable_lock; - struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ - struct drm_sarea_frame frame; /**< frame */ - drm_context_t dummy_context; -}; - -typedef struct drm_sarea_drawable drm_sarea_drawable_t; -typedef struct drm_sarea_frame drm_sarea_frame_t; -typedef struct drm_sarea drm_sarea_t; - -#if defined(__cplusplus) -} -#endif - -#endif /* _DRM_SAREA_H_ */ diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/i915_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/i915_drm.h deleted file mode 100755 index 72afd94..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/i915_drm.h +++ /dev/null @@ -1,1915 +0,0 @@ -/* - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _I915_DRM_H_ -#define _I915_DRM_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - */ - -/** - * DOC: uevents generated by i915 on it's device node - * - * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch - * event from the gpu l3 cache. Additional information supplied is ROW, - * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep - * track of these events and if a specific cache-line seems to have a - * persistent error remap it with the l3 remapping tool supplied in - * intel-gpu-tools. The value supplied with the event is always 1. - * - * I915_ERROR_UEVENT - Generated upon error detection, currently only via - * hangcheck. The error detection event is a good indicator of when things - * began to go badly. The value supplied with the event is a 1 upon error - * detection, and a 0 upon reset completion, signifying no more error - * exists. NOTE: Disabling hangcheck or reset via module parameter will - * cause the related events to not be seen. - * - * I915_RESET_UEVENT - Event is generated just before an attempt to reset the - * the GPU. The value supplied with the event is always 1. NOTE: Disable - * reset via module parameter will cause this event to not be seen. - */ -#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" -#define I915_ERROR_UEVENT "ERROR" -#define I915_RESET_UEVENT "RESET" - -/* - * i915_user_extension: Base class for defining a chain of extensions - * - * Many interfaces need to grow over time. In most cases we can simply - * extend the struct and have userspace pass in more data. Another option, - * as demonstrated by Vulkan's approach to providing extensions for forward - * and backward compatibility, is to use a list of optional structs to - * provide those extra details. - * - * The key advantage to using an extension chain is that it allows us to - * redefine the interface more easily than an ever growing struct of - * increasing complexity, and for large parts of that interface to be - * entirely optional. The downside is more pointer chasing; chasing across - * the boundary with pointers encapsulated inside u64. - */ -struct i915_user_extension { - __u64 next_extension; - __u32 name; - __u32 flags; /* All undefined bits must be zero. */ - __u32 rsvd[4]; /* Reserved for future use; must be zero. */ -}; - -/* - * MOCS indexes used for GPU surfaces, defining the cacheability of the - * surface data and the coherency for this data wrt. CPU vs. GPU accesses. - */ -enum i915_mocs_table_index { - /* - * Not cached anywhere, coherency between CPU and GPU accesses is - * guaranteed. - */ - I915_MOCS_UNCACHED, - /* - * Cacheability and coherency controlled by the kernel automatically - * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current - * usage of the surface (used for display scanout or not). - */ - I915_MOCS_PTE, - /* - * Cached in all GPU caches available on the platform. - * Coherency between CPU and GPU accesses to the surface is not - * guaranteed without extra synchronization. - */ - I915_MOCS_CACHED, -}; - -/* - * Different engines serve different roles, and there may be more than one - * engine serving each role. enum drm_i915_gem_engine_class provides a - * classification of the role of the engine, which may be used when requesting - * operations to be performed on a certain subset of engines, or for providing - * information about that group. - */ -enum drm_i915_gem_engine_class { - I915_ENGINE_CLASS_RENDER = 0, - I915_ENGINE_CLASS_COPY = 1, - I915_ENGINE_CLASS_VIDEO = 2, - I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, - - /* should be kept compact */ - - I915_ENGINE_CLASS_INVALID = -1 -}; - -/** - * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 - * - */ - -enum drm_i915_pmu_engine_sample { - I915_SAMPLE_BUSY = 0, - I915_SAMPLE_WAIT = 1, - I915_SAMPLE_SEMA = 2 -}; - -#define I915_PMU_SAMPLE_BITS (4) -#define I915_PMU_SAMPLE_MASK (0xf) -#define I915_PMU_SAMPLE_INSTANCE_BITS (8) -#define I915_PMU_CLASS_SHIFT \ - (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) - -#define __I915_PMU_ENGINE(class, instance, sample) \ - ((class) << I915_PMU_CLASS_SHIFT | \ - (instance) << I915_PMU_SAMPLE_BITS | \ - (sample)) - -#define I915_PMU_ENGINE_BUSY(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) - -#define I915_PMU_ENGINE_WAIT(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) - -#define I915_PMU_ENGINE_SEMA(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) - -#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) - -#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) -#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) -#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) -#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) - -#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY - -/* Each region is a minimum of 16k, and there are at most 255 of them. - */ -#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use - * of chars for next/prev indices */ -#define I915_LOG_MIN_TEX_REGION_SIZE 14 - -typedef struct _drm_i915_init { - enum { - I915_INIT_DMA = 0x01, - I915_CLEANUP_DMA = 0x02, - I915_RESUME_DMA = 0x03 - } func; - unsigned int mmio_offset; - int sarea_priv_offset; - unsigned int ring_start; - unsigned int ring_end; - unsigned int ring_size; - unsigned int front_offset; - unsigned int back_offset; - unsigned int depth_offset; - unsigned int w; - unsigned int h; - unsigned int pitch; - unsigned int pitch_bits; - unsigned int back_pitch; - unsigned int depth_pitch; - unsigned int cpp; - unsigned int chipset; -} drm_i915_init_t; - -typedef struct _drm_i915_sarea { - struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; - int last_upload; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ - int last_dispatch; /* age of the most recently dispatched buffer */ - int ctxOwner; /* last context to upload state */ - int texAge; - int pf_enabled; /* is pageflipping allowed? */ - int pf_active; - int pf_current_page; /* which buffer is being displayed? */ - int perf_boxes; /* performance boxes to be displayed */ - int width, height; /* screen size in pixels */ - - drm_handle_t front_handle; - int front_offset; - int front_size; - - drm_handle_t back_handle; - int back_offset; - int back_size; - - drm_handle_t depth_handle; - int depth_offset; - int depth_size; - - drm_handle_t tex_handle; - int tex_offset; - int tex_size; - int log_tex_granularity; - int pitch; - int rotation; /* 0, 90, 180 or 270 */ - int rotated_offset; - int rotated_size; - int rotated_pitch; - int virtualX, virtualY; - - unsigned int front_tiled; - unsigned int back_tiled; - unsigned int depth_tiled; - unsigned int rotated_tiled; - unsigned int rotated2_tiled; - - int pipeA_x; - int pipeA_y; - int pipeA_w; - int pipeA_h; - int pipeB_x; - int pipeB_y; - int pipeB_w; - int pipeB_h; - - /* fill out some space for old userspace triple buffer */ - drm_handle_t unused_handle; - __u32 unused1, unused2, unused3; - - /* buffer object handles for static buffers. May change - * over the lifetime of the client. - */ - __u32 front_bo_handle; - __u32 back_bo_handle; - __u32 unused_bo_handle; - __u32 depth_bo_handle; - -} drm_i915_sarea_t; - -/* due to userspace building against these headers we need some compat here */ -#define planeA_x pipeA_x -#define planeA_y pipeA_y -#define planeA_w pipeA_w -#define planeA_h pipeA_h -#define planeB_x pipeB_x -#define planeB_y pipeB_y -#define planeB_w pipeB_w -#define planeB_h pipeB_h - -/* Flags for perf_boxes - */ -#define I915_BOX_RING_EMPTY 0x1 -#define I915_BOX_FLIP 0x2 -#define I915_BOX_WAIT 0x4 -#define I915_BOX_TEXTURE_LOAD 0x8 -#define I915_BOX_LOST_CONTEXT 0x10 - -/* - * i915 specific ioctls. - * - * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie - * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset - * against DRM_COMMAND_BASE and should be between [0x0, 0x60). - */ -#define DRM_I915_INIT 0x00 -#define DRM_I915_FLUSH 0x01 -#define DRM_I915_FLIP 0x02 -#define DRM_I915_BATCHBUFFER 0x03 -#define DRM_I915_IRQ_EMIT 0x04 -#define DRM_I915_IRQ_WAIT 0x05 -#define DRM_I915_GETPARAM 0x06 -#define DRM_I915_SETPARAM 0x07 -#define DRM_I915_ALLOC 0x08 -#define DRM_I915_FREE 0x09 -#define DRM_I915_INIT_HEAP 0x0a -#define DRM_I915_CMDBUFFER 0x0b -#define DRM_I915_DESTROY_HEAP 0x0c -#define DRM_I915_SET_VBLANK_PIPE 0x0d -#define DRM_I915_GET_VBLANK_PIPE 0x0e -#define DRM_I915_VBLANK_SWAP 0x0f -#define DRM_I915_HWS_ADDR 0x11 -#define DRM_I915_GEM_INIT 0x13 -#define DRM_I915_GEM_EXECBUFFER 0x14 -#define DRM_I915_GEM_PIN 0x15 -#define DRM_I915_GEM_UNPIN 0x16 -#define DRM_I915_GEM_BUSY 0x17 -#define DRM_I915_GEM_THROTTLE 0x18 -#define DRM_I915_GEM_ENTERVT 0x19 -#define DRM_I915_GEM_LEAVEVT 0x1a -#define DRM_I915_GEM_CREATE 0x1b -#define DRM_I915_GEM_PREAD 0x1c -#define DRM_I915_GEM_PWRITE 0x1d -#define DRM_I915_GEM_MMAP 0x1e -#define DRM_I915_GEM_SET_DOMAIN 0x1f -#define DRM_I915_GEM_SW_FINISH 0x20 -#define DRM_I915_GEM_SET_TILING 0x21 -#define DRM_I915_GEM_GET_TILING 0x22 -#define DRM_I915_GEM_GET_APERTURE 0x23 -#define DRM_I915_GEM_MMAP_GTT 0x24 -#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 -#define DRM_I915_GEM_MADVISE 0x26 -#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 -#define DRM_I915_OVERLAY_ATTRS 0x28 -#define DRM_I915_GEM_EXECBUFFER2 0x29 -#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 -#define DRM_I915_GET_SPRITE_COLORKEY 0x2a -#define DRM_I915_SET_SPRITE_COLORKEY 0x2b -#define DRM_I915_GEM_WAIT 0x2c -#define DRM_I915_GEM_CONTEXT_CREATE 0x2d -#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e -#define DRM_I915_GEM_SET_CACHING 0x2f -#define DRM_I915_GEM_GET_CACHING 0x30 -#define DRM_I915_REG_READ 0x31 -#define DRM_I915_GET_RESET_STATS 0x32 -#define DRM_I915_GEM_USERPTR 0x33 -#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 -#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 -#define DRM_I915_PERF_OPEN 0x36 -#define DRM_I915_PERF_ADD_CONFIG 0x37 -#define DRM_I915_PERF_REMOVE_CONFIG 0x38 -#define DRM_I915_QUERY 0x39 -/* Must be kept compact -- no holes */ - -#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) -#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) -#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) -#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) -#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) -#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) -#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) -#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) -#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) -#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) -#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) -#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) -#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) -#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) -#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) -#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) -#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) -#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) -#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) -#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) -#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) -#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) -#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) -#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) -#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) -#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) -#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) -#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) -#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) -#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) -#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) -#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) -#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) -#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) -#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) -#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) -#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) -#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) -#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) -#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) -#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) -#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) -#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) -#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) -#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) -#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) -#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) - -/* Allow drivers to submit batchbuffers directly to hardware, relying - * on the security mechanisms provided by hardware. - */ -typedef struct drm_i915_batchbuffer { - int start; /* agp offset */ - int used; /* nr bytes in use */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ -} drm_i915_batchbuffer_t; - -/* As above, but pass a pointer to userspace buffer which can be - * validated by the kernel prior to sending to hardware. - */ -typedef struct _drm_i915_cmdbuffer { - char *buf; /* pointer to userspace command buffer */ - int sz; /* nr bytes in buf */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ -} drm_i915_cmdbuffer_t; - -/* Userspace can request & wait on irq's: - */ -typedef struct drm_i915_irq_emit { - int *irq_seq; -} drm_i915_irq_emit_t; - -typedef struct drm_i915_irq_wait { - int irq_seq; -} drm_i915_irq_wait_t; - -/* - * Different modes of per-process Graphics Translation Table, - * see I915_PARAM_HAS_ALIASING_PPGTT - */ -#define I915_GEM_PPGTT_NONE 0 -#define I915_GEM_PPGTT_ALIASING 1 -#define I915_GEM_PPGTT_FULL 2 - -/* Ioctl to query kernel params: - */ -#define I915_PARAM_IRQ_ACTIVE 1 -#define I915_PARAM_ALLOW_BATCHBUFFER 2 -#define I915_PARAM_LAST_DISPATCH 3 -#define I915_PARAM_CHIPSET_ID 4 -#define I915_PARAM_HAS_GEM 5 -#define I915_PARAM_NUM_FENCES_AVAIL 6 -#define I915_PARAM_HAS_OVERLAY 7 -#define I915_PARAM_HAS_PAGEFLIPPING 8 -#define I915_PARAM_HAS_EXECBUF2 9 -#define I915_PARAM_HAS_BSD 10 -#define I915_PARAM_HAS_BLT 11 -#define I915_PARAM_HAS_RELAXED_FENCING 12 -#define I915_PARAM_HAS_COHERENT_RINGS 13 -#define I915_PARAM_HAS_EXEC_CONSTANTS 14 -#define I915_PARAM_HAS_RELAXED_DELTA 15 -#define I915_PARAM_HAS_GEN7_SOL_RESET 16 -#define I915_PARAM_HAS_LLC 17 -#define I915_PARAM_HAS_ALIASING_PPGTT 18 -#define I915_PARAM_HAS_WAIT_TIMEOUT 19 -#define I915_PARAM_HAS_SEMAPHORES 20 -#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 -#define I915_PARAM_HAS_VEBOX 22 -#define I915_PARAM_HAS_SECURE_BATCHES 23 -#define I915_PARAM_HAS_PINNED_BATCHES 24 -#define I915_PARAM_HAS_EXEC_NO_RELOC 25 -#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 -#define I915_PARAM_HAS_WT 27 -#define I915_PARAM_CMD_PARSER_VERSION 28 -#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 -#define I915_PARAM_MMAP_VERSION 30 -#define I915_PARAM_HAS_BSD2 31 -#define I915_PARAM_REVISION 32 -#define I915_PARAM_SUBSLICE_TOTAL 33 -#define I915_PARAM_EU_TOTAL 34 -#define I915_PARAM_HAS_GPU_RESET 35 -#define I915_PARAM_HAS_RESOURCE_STREAMER 36 -#define I915_PARAM_HAS_EXEC_SOFTPIN 37 -#define I915_PARAM_HAS_POOLED_EU 38 -#define I915_PARAM_MIN_EU_IN_POOL 39 -#define I915_PARAM_MMAP_GTT_VERSION 40 - -/* - * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution - * priorities and the driver will attempt to execute batches in priority order. - * The param returns a capability bitmask, nonzero implies that the scheduler - * is enabled, with different features present according to the mask. - * - * The initial priority for each batch is supplied by the context and is - * controlled via I915_CONTEXT_PARAM_PRIORITY. - */ -#define I915_PARAM_HAS_SCHEDULER 41 -#define I915_SCHEDULER_CAP_ENABLED (1ul << 0) -#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) -#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) -#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) - -#define I915_PARAM_HUC_STATUS 42 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of - * synchronisation with implicit fencing on individual objects. - * See EXEC_OBJECT_ASYNC. - */ -#define I915_PARAM_HAS_EXEC_ASYNC 43 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - - * both being able to pass in a sync_file fd to wait upon before executing, - * and being able to return a new sync_file fd that is signaled when the - * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. - */ -#define I915_PARAM_HAS_EXEC_FENCE 44 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture - * user specified buffers for post-mortem debugging of GPU hangs. See - * EXEC_OBJECT_CAPTURE. - */ -#define I915_PARAM_HAS_EXEC_CAPTURE 45 - -#define I915_PARAM_SLICE_MASK 46 - -/* Assuming it's uniform for each slice, this queries the mask of subslices - * per-slice for this system. - */ -#define I915_PARAM_SUBSLICE_MASK 47 - -/* - * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer - * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. - */ -#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 - -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of - * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. - */ -#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 - -/* - * Query whether every context (both per-file default and user created) is - * isolated (insofar as HW supports). If this parameter is not true, then - * freshly created contexts may inherit values from an existing context, - * rather than default HW values. If true, it also ensures (insofar as HW - * supports) that all state set by this context will not leak to any other - * context. - * - * As not every engine across every gen support contexts, the returned - * value reports the support of context isolation for individual engines by - * returning a bitmask of each engine class set to true if that class supports - * isolation. - */ -#define I915_PARAM_HAS_CONTEXT_ISOLATION 50 - -/* Frequency of the command streamer timestamps given by the *_TIMESTAMP - * registers. This used to be fixed per platform but from CNL onwards, this - * might vary depending on the parts. - */ -#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 - -/* - * Once upon a time we supposed that writes through the GGTT would be - * immediately in physical memory (once flushed out of the CPU path). However, - * on a few different processors and chipsets, this is not necessarily the case - * as the writes appear to be buffered internally. Thus a read of the backing - * storage (physical memory) via a different path (with different physical tags - * to the indirect write via the GGTT) will see stale values from before - * the GGTT write. Inside the kernel, we can for the most part keep track of - * the different read/write domains in use (e.g. set-domain), but the assumption - * of coherency is baked into the ABI, hence reporting its true state in this - * parameter. - * - * Reports true when writes via mmap_gtt are immediately visible following an - * lfence to flush the WCB. - * - * Reports false when writes via mmap_gtt are indeterminately delayed in an in - * internal buffer and are _not_ immediately visible to third parties accessing - * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC - * communications channel when reporting false is strongly disadvised. - */ -#define I915_PARAM_MMAP_GTT_COHERENT 52 - -/* Must be kept compact -- no holes and well documented */ - -typedef struct drm_i915_getparam { - __s32 param; - /* - * WARNING: Using pointers instead of fixed-size u64 means we need to write - * compat32 code. Don't repeat this mistake. - */ - int *value; -} drm_i915_getparam_t; - -/* Ioctl to set kernel params: - */ -#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 -#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 -#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 -#define I915_SETPARAM_NUM_USED_FENCES 4 -/* Must be kept compact -- no holes */ - -typedef struct drm_i915_setparam { - int param; - int value; -} drm_i915_setparam_t; - -/* A memory manager for regions of shared memory: - */ -#define I915_MEM_REGION_AGP 1 - -typedef struct drm_i915_mem_alloc { - int region; - int alignment; - int size; - int *region_offset; /* offset from start of fb or agp */ -} drm_i915_mem_alloc_t; - -typedef struct drm_i915_mem_free { - int region; - int region_offset; -} drm_i915_mem_free_t; - -typedef struct drm_i915_mem_init_heap { - int region; - int size; - int start; -} drm_i915_mem_init_heap_t; - -/* Allow memory manager to be torn down and re-initialized (eg on - * rotate): - */ -typedef struct drm_i915_mem_destroy_heap { - int region; -} drm_i915_mem_destroy_heap_t; - -/* Allow X server to configure which pipes to monitor for vblank signals - */ -#define DRM_I915_VBLANK_PIPE_A 1 -#define DRM_I915_VBLANK_PIPE_B 2 - -typedef struct drm_i915_vblank_pipe { - int pipe; -} drm_i915_vblank_pipe_t; - -/* Schedule buffer swap at given vertical blank: - */ -typedef struct drm_i915_vblank_swap { - drm_drawable_t drawable; - enum drm_vblank_seq_type seqtype; - unsigned int sequence; -} drm_i915_vblank_swap_t; - -typedef struct drm_i915_hws_addr { - __u64 addr; -} drm_i915_hws_addr_t; - -struct drm_i915_gem_init { - /** - * Beginning offset in the GTT to be managed by the DRM memory - * manager. - */ - __u64 gtt_start; - /** - * Ending offset in the GTT to be managed by the DRM memory - * manager. - */ - __u64 gtt_end; -}; - -struct drm_i915_gem_create { - /** - * Requested size for the object. - * - * The (page-aligned) allocated size for the object will be returned. - */ - __u64 size; - /** - * Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; - __u32 pad; -}; - -struct drm_i915_gem_pread { - /** Handle for the object being read. */ - __u32 handle; - __u32 pad; - /** Offset into the object to read from */ - __u64 offset; - /** Length of data to read */ - __u64 size; - /** - * Pointer to write the data into. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 data_ptr; -}; - -struct drm_i915_gem_pwrite { - /** Handle for the object being written to. */ - __u32 handle; - __u32 pad; - /** Offset into the object to write to */ - __u64 offset; - /** Length of data to write */ - __u64 size; - /** - * Pointer to read the data from. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 data_ptr; -}; - -struct drm_i915_gem_mmap { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** Offset in the object to map. */ - __u64 offset; - /** - * Length of data to map. - * - * The value will be page-aligned. - */ - __u64 size; - /** - * Returned pointer the data was mapped at. - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 addr_ptr; - - /** - * Flags for extended behaviour. - * - * Added in version 2. - */ - __u64 flags; -#define I915_MMAP_WC 0x1 -}; - -struct drm_i915_gem_mmap_gtt { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 pad; - /** - * Fake offset to use for subsequent mmap call - * - * This is a fixed-size type for 32/64 compatibility. - */ - __u64 offset; -}; - -struct drm_i915_gem_set_domain { - /** Handle for the object */ - __u32 handle; - - /** New read domains */ - __u32 read_domains; - - /** New write domain */ - __u32 write_domain; -}; - -struct drm_i915_gem_sw_finish { - /** Handle for the object */ - __u32 handle; -}; - -struct drm_i915_gem_relocation_entry { - /** - * Handle of the buffer being pointed to by this relocation entry. - * - * It's appealing to make this be an index into the mm_validate_entry - * list to refer to the buffer, but this allows the driver to create - * a relocation list for state buffers and not re-write it per - * exec using the buffer. - */ - __u32 target_handle; - - /** - * Value to be added to the offset of the target buffer to make up - * the relocation entry. - */ - __u32 delta; - - /** Offset in the buffer the relocation entry will be written into */ - __u64 offset; - - /** - * Offset value of the target buffer that the relocation entry was last - * written as. - * - * If the buffer has the same offset as last time, we can skip syncing - * and writing the relocation. This value is written back out by - * the execbuffer ioctl when the relocation is written. - */ - __u64 presumed_offset; - - /** - * Target memory domains read by this operation. - */ - __u32 read_domains; - - /** - * Target memory domains written by this operation. - * - * Note that only one domain may be written by the whole - * execbuffer operation, so that where there are conflicts, - * the application will get -EINVAL back. - */ - __u32 write_domain; -}; - -/** @{ - * Intel memory domains - * - * Most of these just align with the various caches in - * the system and are used to flush and invalidate as - * objects end up cached in different domains. - */ -/** CPU cache */ -#define I915_GEM_DOMAIN_CPU 0x00000001 -/** Render cache, used by 2D and 3D drawing */ -#define I915_GEM_DOMAIN_RENDER 0x00000002 -/** Sampler cache, used by texture engine */ -#define I915_GEM_DOMAIN_SAMPLER 0x00000004 -/** Command queue, used to load batch buffers */ -#define I915_GEM_DOMAIN_COMMAND 0x00000008 -/** Instruction cache, used by shader programs */ -#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 -/** Vertex address cache */ -#define I915_GEM_DOMAIN_VERTEX 0x00000020 -/** GTT domain - aperture and scanout */ -#define I915_GEM_DOMAIN_GTT 0x00000040 -/** WC domain - uncached access */ -#define I915_GEM_DOMAIN_WC 0x00000080 -/** @} */ - -struct drm_i915_gem_exec_object { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - __u32 handle; - - /** Number of relocations to be performed on this buffer */ - __u32 relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - __u64 relocs_ptr; - - /** Required alignment in graphics aperture */ - __u64 alignment; - - /** - * Returned value of the updated offset of the object, for future - * presumed_offset writes. - */ - __u64 offset; -}; - -struct drm_i915_gem_execbuffer { - /** - * List of buffers to be validated with their relocations to be - * performend on them. - * - * This is a pointer to an array of struct drm_i915_gem_validate_entry. - * - * These buffers must be listed in an order such that all relocations - * a buffer is performing refer to buffers that have already appeared - * in the validate list. - */ - __u64 buffers_ptr; - __u32 buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - __u32 batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - __u32 batch_len; - __u32 DR1; - __u32 DR4; - __u32 num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ - __u64 cliprects_ptr; -}; - -struct drm_i915_gem_exec_object2 { - /** - * User's handle for a buffer to be bound into the GTT for this - * operation. - */ - __u32 handle; - - /** Number of relocations to be performed on this buffer */ - __u32 relocation_count; - /** - * Pointer to array of struct drm_i915_gem_relocation_entry containing - * the relocations to be performed in this buffer. - */ - __u64 relocs_ptr; - - /** Required alignment in graphics aperture */ - __u64 alignment; - - /** - * When the EXEC_OBJECT_PINNED flag is specified this is populated by - * the user with the GTT offset at which this object will be pinned. - * When the I915_EXEC_NO_RELOC flag is specified this must contain the - * presumed_offset of the object. - * During execbuffer2 the kernel populates it with the value of the - * current GTT offset of the object, for future presumed_offset writes. - */ - __u64 offset; - -#define EXEC_OBJECT_NEEDS_FENCE (1<<0) -#define EXEC_OBJECT_NEEDS_GTT (1<<1) -#define EXEC_OBJECT_WRITE (1<<2) -#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) -#define EXEC_OBJECT_PINNED (1<<4) -#define EXEC_OBJECT_PAD_TO_SIZE (1<<5) -/* The kernel implicitly tracks GPU activity on all GEM objects, and - * synchronises operations with outstanding rendering. This includes - * rendering on other devices if exported via dma-buf. However, sometimes - * this tracking is too coarse and the user knows better. For example, - * if the object is split into non-overlapping ranges shared between different - * clients or engines (i.e. suballocating objects), the implicit tracking - * by kernel assumes that each operation affects the whole object rather - * than an individual range, causing needless synchronisation between clients. - * The kernel will also forgo any CPU cache flushes prior to rendering from - * the object as the client is expected to be also handling such domain - * tracking. - * - * The kernel maintains the implicit tracking in order to manage resources - * used by the GPU - this flag only disables the synchronisation prior to - * rendering with this object in this execbuf. - * - * Opting out of implicit synhronisation requires the user to do its own - * explicit tracking to avoid rendering corruption. See, for example, - * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. - */ -#define EXEC_OBJECT_ASYNC (1<<6) -/* Request that the contents of this execobject be copied into the error - * state upon a GPU hang involving this batch for post-mortem debugging. - * These buffers are recorded in no particular order as "user" in - * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see - * if the kernel supports this flag. - */ -#define EXEC_OBJECT_CAPTURE (1<<7) -/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ -#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) - __u64 flags; - - union { - __u64 rsvd1; - __u64 pad_to_size; - }; - __u64 rsvd2; -}; - -struct drm_i915_gem_exec_fence { - /** - * User's handle for a drm_syncobj to wait on or signal. - */ - __u32 handle; - -#define I915_EXEC_FENCE_WAIT (1<<0) -#define I915_EXEC_FENCE_SIGNAL (1<<1) -#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) - __u32 flags; -}; - -struct drm_i915_gem_execbuffer2 { - /** - * List of gem_exec_object2 structs - */ - __u64 buffers_ptr; - __u32 buffer_count; - - /** Offset in the batchbuffer to start execution from. */ - __u32 batch_start_offset; - /** Bytes used in batchbuffer from batch_start_offset */ - __u32 batch_len; - __u32 DR1; - __u32 DR4; - __u32 num_cliprects; - /** - * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY - * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a - * struct drm_i915_gem_exec_fence *fences. - */ - __u64 cliprects_ptr; -#define I915_EXEC_RING_MASK (0x3f) -#define I915_EXEC_DEFAULT (0<<0) -#define I915_EXEC_RENDER (1<<0) -#define I915_EXEC_BSD (2<<0) -#define I915_EXEC_BLT (3<<0) -#define I915_EXEC_VEBOX (4<<0) - -/* Used for switching the constants addressing mode on gen4+ RENDER ring. - * Gen6+ only supports relative addressing to dynamic state (default) and - * absolute addressing. - * - * These flags are ignored for the BSD and BLT rings. - */ -#define I915_EXEC_CONSTANTS_MASK (3<<6) -#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ -#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) -#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ - __u64 flags; - __u64 rsvd1; /* now used for context info */ - __u64 rsvd2; -}; - -/** Resets the SO write offset registers for transform feedback on gen7. */ -#define I915_EXEC_GEN7_SOL_RESET (1<<8) - -/** Request a privileged ("secure") batch buffer. Note only available for - * DRM_ROOT_ONLY | DRM_MASTER processes. - */ -#define I915_EXEC_SECURE (1<<9) - -/** Inform the kernel that the batch is and will always be pinned. This - * negates the requirement for a workaround to be performed to avoid - * an incoherent CS (such as can be found on 830/845). If this flag is - * not passed, the kernel will endeavour to make sure the batch is - * coherent with the CS before execution. If this flag is passed, - * userspace assumes the responsibility for ensuring the same. - */ -#define I915_EXEC_IS_PINNED (1<<10) - -/** Provide a hint to the kernel that the command stream and auxiliary - * state buffers already holds the correct presumed addresses and so the - * relocation process may be skipped if no buffers need to be moved in - * preparation for the execbuffer. - */ -#define I915_EXEC_NO_RELOC (1<<11) - -/** Use the reloc.handle as an index into the exec object array rather - * than as the per-file handle. - */ -#define I915_EXEC_HANDLE_LUT (1<<12) - -/** Used for switching BSD rings on the platforms with two BSD rings */ -#define I915_EXEC_BSD_SHIFT (13) -#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) -/* default ping-pong mode */ -#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) -#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) -#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) - -/** Tell the kernel that the batchbuffer is processed by - * the resource streamer. - */ -#define I915_EXEC_RESOURCE_STREAMER (1<<15) - -/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent - * a sync_file fd to wait upon (in a nonblocking manner) prior to executing - * the batch. - * - * Returns -EINVAL if the sync_file fd cannot be found. - */ -#define I915_EXEC_FENCE_IN (1<<16) - -/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd - * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given - * to the caller, and it should be close() after use. (The fd is a regular - * file descriptor and will be cleaned up on process termination. It holds - * a reference to the request, but nothing else.) - * - * The sync_file fd can be combined with other sync_file and passed either - * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip - * will only occur after this request completes), or to other devices. - * - * Using I915_EXEC_FENCE_OUT requires use of - * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written - * back to userspace. Failure to do so will cause the out-fence to always - * be reported as zero, and the real fence fd to be leaked. - */ -#define I915_EXEC_FENCE_OUT (1<<17) - -/* - * Traditionally the execbuf ioctl has only considered the final element in - * the execobject[] to be the executable batch. Often though, the client - * will known the batch object prior to construction and being able to place - * it into the execobject[] array first can simplify the relocation tracking. - * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the - * execobject[] as the * batch instead (the default is to use the last - * element). - */ -#define I915_EXEC_BATCH_FIRST (1<<18) - -/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr - * define an array of i915_gem_exec_fence structures which specify a set of - * dma fences to wait upon or signal. - */ -#define I915_EXEC_FENCE_ARRAY (1<<19) - -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) - -#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) -#define i915_execbuffer2_set_context_id(eb2, context) \ - (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK -#define i915_execbuffer2_get_context_id(eb2) \ - ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) - -struct drm_i915_gem_pin { - /** Handle of the buffer to be pinned. */ - __u32 handle; - __u32 pad; - - /** alignment required within the aperture */ - __u64 alignment; - - /** Returned GTT offset of the buffer. */ - __u64 offset; -}; - -struct drm_i915_gem_unpin { - /** Handle of the buffer to be unpinned. */ - __u32 handle; - __u32 pad; -}; - -struct drm_i915_gem_busy { - /** Handle of the buffer to check for busy */ - __u32 handle; - - /** Return busy status - * - * A return of 0 implies that the object is idle (after - * having flushed any pending activity), and a non-zero return that - * the object is still in-flight on the GPU. (The GPU has not yet - * signaled completion for all pending requests that reference the - * object.) An object is guaranteed to become idle eventually (so - * long as no new GPU commands are executed upon it). Due to the - * asynchronous nature of the hardware, an object reported - * as busy may become idle before the ioctl is completed. - * - * Furthermore, if the object is busy, which engine is busy is only - * provided as a guide and only indirectly by reporting its class - * (there may be more than one engine in each class). There are race - * conditions which prevent the report of which engines are busy from - * being always accurate. However, the converse is not true. If the - * object is idle, the result of the ioctl, that all engines are idle, - * is accurate. - * - * The returned dword is split into two fields to indicate both - * the engine classess on which the object is being read, and the - * engine class on which it is currently being written (if any). - * - * The low word (bits 0:15) indicate if the object is being written - * to by any engine (there can only be one, as the GEM implicit - * synchronisation rules force writes to be serialised). Only the - * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as - * 1 not 0 etc) for the last write is reported. - * - * The high word (bits 16:31) are a bitmask of which engines classes - * are currently reading from the object. Multiple engines may be - * reading from the object simultaneously. - * - * The value of each engine class is the same as specified in the - * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e. - * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. - * reported as active itself. Some hardware may have parallel - * execution engines, e.g. multiple media engines, which are - * mapped to the same class identifier and so are not separately - * reported for busyness. - * - * Caveat emptor: - * Only the boolean result of this query is reliable; that is whether - * the object is idle or busy. The report of which engines are busy - * should be only used as a heuristic. - */ - __u32 busy; -}; - -/** - * I915_CACHING_NONE - * - * GPU access is not coherent with cpu caches. Default for machines without an - * LLC. - */ -#define I915_CACHING_NONE 0 -/** - * I915_CACHING_CACHED - * - * GPU access is coherent with cpu caches and furthermore the data is cached in - * last-level caches shared between cpu cores and the gpu GT. Default on - * machines with HAS_LLC. - */ -#define I915_CACHING_CACHED 1 -/** - * I915_CACHING_DISPLAY - * - * Special GPU caching mode which is coherent with the scanout engines. - * Transparently falls back to I915_CACHING_NONE on platforms where no special - * cache mode (like write-through or gfdt flushing) is available. The kernel - * automatically sets this mode when using a buffer as a scanout target. - * Userspace can manually set this mode to avoid a costly stall and clflush in - * the hotpath of drawing the first frame. - */ -#define I915_CACHING_DISPLAY 2 - -struct drm_i915_gem_caching { - /** - * Handle of the buffer to set/get the caching level of. */ - __u32 handle; - - /** - * Caching level to apply or return value - * - * bits0-15 are for generic caching control (i.e. the above defined - * values). bits16-31 are reserved for platform-specific variations - * (e.g. l3$ caching on gen7). */ - __u32 caching; -}; - -#define I915_TILING_NONE 0 -#define I915_TILING_X 1 -#define I915_TILING_Y 2 -#define I915_TILING_LAST I915_TILING_Y - -#define I915_BIT_6_SWIZZLE_NONE 0 -#define I915_BIT_6_SWIZZLE_9 1 -#define I915_BIT_6_SWIZZLE_9_10 2 -#define I915_BIT_6_SWIZZLE_9_11 3 -#define I915_BIT_6_SWIZZLE_9_10_11 4 -/* Not seen by userland */ -#define I915_BIT_6_SWIZZLE_UNKNOWN 5 -/* Seen by userland. */ -#define I915_BIT_6_SWIZZLE_9_17 6 -#define I915_BIT_6_SWIZZLE_9_10_17 7 - -struct drm_i915_gem_set_tiling { - /** Handle of the buffer to have its tiling state updated */ - __u32 handle; - - /** - * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - * - * This value is to be set on request, and will be updated by the - * kernel on successful return with the actual chosen tiling layout. - * - * The tiling mode may be demoted to I915_TILING_NONE when the system - * has bit 6 swizzling that can't be managed correctly by GEM. - * - * Buffer contents become undefined when changing tiling_mode. - */ - __u32 tiling_mode; - - /** - * Stride in bytes for the object when in I915_TILING_X or - * I915_TILING_Y. - */ - __u32 stride; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - __u32 swizzle_mode; -}; - -struct drm_i915_gem_get_tiling { - /** Handle of the buffer to get tiling state for. */ - __u32 handle; - - /** - * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, - * I915_TILING_Y). - */ - __u32 tiling_mode; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping. - */ - __u32 swizzle_mode; - - /** - * Returned address bit 6 swizzling required for CPU access through - * mmap mapping whilst bound. - */ - __u32 phys_swizzle_mode; -}; - -struct drm_i915_gem_get_aperture { - /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ - __u64 aper_size; - - /** - * Available space in the aperture used by i915_gem_execbuffer, in - * bytes - */ - __u64 aper_available_size; -}; - -struct drm_i915_get_pipe_from_crtc_id { - /** ID of CRTC being requested **/ - __u32 crtc_id; - - /** pipe of requested CRTC **/ - __u32 pipe; -}; - -#define I915_MADV_WILLNEED 0 -#define I915_MADV_DONTNEED 1 -#define __I915_MADV_PURGED 2 /* internal state */ - -struct drm_i915_gem_madvise { - /** Handle of the buffer to change the backing store advice */ - __u32 handle; - - /* Advice: either the buffer will be needed again in the near future, - * or wont be and could be discarded under memory pressure. - */ - __u32 madv; - - /** Whether the backing store still exists. */ - __u32 retained; -}; - -/* flags */ -#define I915_OVERLAY_TYPE_MASK 0xff -#define I915_OVERLAY_YUV_PLANAR 0x01 -#define I915_OVERLAY_YUV_PACKED 0x02 -#define I915_OVERLAY_RGB 0x03 - -#define I915_OVERLAY_DEPTH_MASK 0xff00 -#define I915_OVERLAY_RGB24 0x1000 -#define I915_OVERLAY_RGB16 0x2000 -#define I915_OVERLAY_RGB15 0x3000 -#define I915_OVERLAY_YUV422 0x0100 -#define I915_OVERLAY_YUV411 0x0200 -#define I915_OVERLAY_YUV420 0x0300 -#define I915_OVERLAY_YUV410 0x0400 - -#define I915_OVERLAY_SWAP_MASK 0xff0000 -#define I915_OVERLAY_NO_SWAP 0x000000 -#define I915_OVERLAY_UV_SWAP 0x010000 -#define I915_OVERLAY_Y_SWAP 0x020000 -#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 - -#define I915_OVERLAY_FLAGS_MASK 0xff000000 -#define I915_OVERLAY_ENABLE 0x01000000 - -struct drm_intel_overlay_put_image { - /* various flags and src format description */ - __u32 flags; - /* source picture description */ - __u32 bo_handle; - /* stride values and offsets are in bytes, buffer relative */ - __u16 stride_Y; /* stride for packed formats */ - __u16 stride_UV; - __u32 offset_Y; /* offset for packet formats */ - __u32 offset_U; - __u32 offset_V; - /* in pixels */ - __u16 src_width; - __u16 src_height; - /* to compensate the scaling factors for partially covered surfaces */ - __u16 src_scan_width; - __u16 src_scan_height; - /* output crtc description */ - __u32 crtc_id; - __u16 dst_x; - __u16 dst_y; - __u16 dst_width; - __u16 dst_height; -}; - -/* flags */ -#define I915_OVERLAY_UPDATE_ATTRS (1<<0) -#define I915_OVERLAY_UPDATE_GAMMA (1<<1) -#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) -struct drm_intel_overlay_attrs { - __u32 flags; - __u32 color_key; - __s32 brightness; - __u32 contrast; - __u32 saturation; - __u32 gamma0; - __u32 gamma1; - __u32 gamma2; - __u32 gamma3; - __u32 gamma4; - __u32 gamma5; -}; - -/* - * Intel sprite handling - * - * Color keying works with a min/mask/max tuple. Both source and destination - * color keying is allowed. - * - * Source keying: - * Sprite pixels within the min & max values, masked against the color channels - * specified in the mask field, will be transparent. All other pixels will - * be displayed on top of the primary plane. For RGB surfaces, only the min - * and mask fields will be used; ranged compares are not allowed. - * - * Destination keying: - * Primary plane pixels that match the min value, masked against the color - * channels specified in the mask field, will be replaced by corresponding - * pixels from the sprite plane. - * - * Note that source & destination keying are exclusive; only one can be - * active on a given plane. - */ - -#define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set - * flags==0 to disable colorkeying. - */ -#define I915_SET_COLORKEY_DESTINATION (1<<1) -#define I915_SET_COLORKEY_SOURCE (1<<2) -struct drm_intel_sprite_colorkey { - __u32 plane_id; - __u32 min_value; - __u32 channel_mask; - __u32 max_value; - __u32 flags; -}; - -struct drm_i915_gem_wait { - /** Handle of BO we shall wait on */ - __u32 bo_handle; - __u32 flags; - /** Number of nanoseconds to wait, Returns time remaining. */ - __s64 timeout_ns; -}; - -struct drm_i915_gem_context_create { - __u32 ctx_id; /* output: id of new context*/ - __u32 pad; -}; - -struct drm_i915_gem_context_create_ext { - __u32 ctx_id; /* output: id of new context*/ - __u32 flags; -#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) -#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ - (-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1)) - __u64 extensions; -}; - -struct drm_i915_gem_context_param { - __u32 ctx_id; - __u32 size; - __u64 param; -#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 -#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 -#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 -#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 -#define I915_CONTEXT_PARAM_BANNABLE 0x5 -#define I915_CONTEXT_PARAM_PRIORITY 0x6 -#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ -#define I915_CONTEXT_DEFAULT_PRIORITY 0 -#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ - /* - * When using the following param, value should be a pointer to - * drm_i915_gem_context_param_sseu. - */ -#define I915_CONTEXT_PARAM_SSEU 0x7 - -/* - * Not all clients may want to attempt automatic recover of a context after - * a hang (for example, some clients may only submit very small incremental - * batches relying on known logical state of previous batches which will never - * recover correctly and each attempt will hang), and so would prefer that - * the context is forever banned instead. - * - * If set to false (0), after a reset, subsequent (and in flight) rendering - * from this context is discarded, and the client will need to create a new - * context to use instead. - * - * If set to true (1), the kernel will automatically attempt to recover the - * context by skipping the hanging batch and executing the next batch starting - * from the default context state (discarding the incomplete logical context - * state lost due to the reset). - * - * On creation, all new contexts are marked as recoverable. - */ -#define I915_CONTEXT_PARAM_RECOVERABLE 0x8 -/* Must be kept compact -- no holes and well documented */ - - __u64 value; -}; - -/** - * Context SSEU programming - * - * It may be necessary for either functional or performance reason to configure - * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ - * Sub-slice/EU). - * - * This is done by configuring SSEU configuration using the below - * @struct drm_i915_gem_context_param_sseu for every supported engine which - * userspace intends to use. - * - * Not all GPUs or engines support this functionality in which case an error - * code -ENODEV will be returned. - * - * Also, flexibility of possible SSEU configuration permutations varies between - * GPU generations and software imposed limitations. Requesting such a - * combination will return an error code of -EINVAL. - * - * NOTE: When perf/OA is active the context's SSEU configuration is ignored in - * favour of a single global setting. - */ -struct drm_i915_gem_context_param_sseu { - /* - * Engine class & instance to be configured or queried. - */ - __u16 engine_class; - __u16 engine_instance; - - /* - * Unused for now. Must be cleared to zero. - */ - __u32 flags; - - /* - * Mask of slices to enable for the context. Valid values are a subset - * of the bitmask value returned for I915_PARAM_SLICE_MASK. - */ - __u64 slice_mask; - - /* - * Mask of subslices to enable for the context. Valid values are a - * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. - */ - __u64 subslice_mask; - - /* - * Minimum/Maximum number of EUs to enable per subslice for the - * context. min_eus_per_subslice must be inferior or equal to - * max_eus_per_subslice. - */ - __u16 min_eus_per_subslice; - __u16 max_eus_per_subslice; - - /* - * Unused for now. Must be cleared to zero. - */ - __u32 rsvd; -}; - -struct drm_i915_gem_context_create_ext_setparam { -#define I915_CONTEXT_CREATE_EXT_SETPARAM 0 - struct i915_user_extension base; - struct drm_i915_gem_context_param param; -}; - -struct drm_i915_gem_context_destroy { - __u32 ctx_id; - __u32 pad; -}; - -/* - * DRM_I915_GEM_VM_CREATE - - * - * Create a new virtual memory address space (ppGTT) for use within a context - * on the same file. Extensions can be provided to configure exactly how the - * address space is setup upon creation. - * - * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is - * returned in the outparam @id. - * - * No flags are defined, with all bits reserved and must be zero. - * - * An extension chain maybe provided, starting with @extensions, and terminated - * by the @next_extension being 0. Currently, no extensions are defined. - * - * DRM_I915_GEM_VM_DESTROY - - * - * Destroys a previously created VM id, specified in @id. - * - * No extensions or flags are allowed currently, and so must be zero. - */ -struct drm_i915_gem_vm_control { - __u64 extensions; - __u32 flags; - __u32 vm_id; -}; - -struct drm_i915_reg_read { - /* - * Register offset. - * For 64bit wide registers where the upper 32bits don't immediately - * follow the lower 32bits, the offset of the lower 32bits must - * be specified - */ - __u64 offset; -#define I915_REG_READ_8B_WA (1ul << 0) - - __u64 val; /* Return value */ -}; - -/* Known registers: - * - * Render engine timestamp - 0x2358 + 64bit - gen7+ - * - Note this register returns an invalid value if using the default - * single instruction 8byte read, in order to workaround that pass - * flag I915_REG_READ_8B_WA in offset field. - * - */ - -struct drm_i915_reset_stats { - __u32 ctx_id; - __u32 flags; - - /* All resets since boot/module reload, for all contexts */ - __u32 reset_count; - - /* Number of batches lost when active in GPU, for this context */ - __u32 batch_active; - - /* Number of batches lost pending for execution, for this context */ - __u32 batch_pending; - - __u32 pad; -}; - -struct drm_i915_gem_userptr { - __u64 user_ptr; - __u64 user_size; - __u32 flags; -#define I915_USERPTR_READ_ONLY 0x1 -#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 - /** - * Returned handle for the object. - * - * Object handles are nonzero. - */ - __u32 handle; -}; - -enum drm_i915_oa_format { - I915_OA_FORMAT_A13 = 1, /* HSW only */ - I915_OA_FORMAT_A29, /* HSW only */ - I915_OA_FORMAT_A13_B8_C8, /* HSW only */ - I915_OA_FORMAT_B4_C8, /* HSW only */ - I915_OA_FORMAT_A45_B8_C8, /* HSW only */ - I915_OA_FORMAT_B4_C8_A16, /* HSW only */ - I915_OA_FORMAT_C4_B8, /* HSW+ */ - - /* Gen8+ */ - I915_OA_FORMAT_A12, - I915_OA_FORMAT_A12_B8_C8, - I915_OA_FORMAT_A32u40_A4u32_B8_C8, - - I915_OA_FORMAT_MAX /* non-ABI */ -}; - -enum drm_i915_perf_property_id { - /** - * Open the stream for a specific context handle (as used with - * execbuffer2). A stream opened for a specific context this way - * won't typically require root privileges. - */ - DRM_I915_PERF_PROP_CTX_HANDLE = 1, - - /** - * A value of 1 requests the inclusion of raw OA unit reports as - * part of stream samples. - */ - DRM_I915_PERF_PROP_SAMPLE_OA, - - /** - * The value specifies which set of OA unit metrics should be - * be configured, defining the contents of any OA unit reports. - */ - DRM_I915_PERF_PROP_OA_METRICS_SET, - - /** - * The value specifies the size and layout of OA unit reports. - */ - DRM_I915_PERF_PROP_OA_FORMAT, - - /** - * Specifying this property implicitly requests periodic OA unit - * sampling and (at least on Haswell) the sampling frequency is derived - * from this exponent as follows: - * - * 80ns * 2^(period_exponent + 1) - */ - DRM_I915_PERF_PROP_OA_EXPONENT, - - DRM_I915_PERF_PROP_MAX /* non-ABI */ -}; - -struct drm_i915_perf_open_param { - __u32 flags; -#define I915_PERF_FLAG_FD_CLOEXEC (1<<0) -#define I915_PERF_FLAG_FD_NONBLOCK (1<<1) -#define I915_PERF_FLAG_DISABLED (1<<2) - - /** The number of u64 (id, value) pairs */ - __u32 num_properties; - - /** - * Pointer to array of u64 (id, value) pairs configuring the stream - * to open. - */ - __u64 properties_ptr; -}; - -/** - * Enable data capture for a stream that was either opened in a disabled state - * via I915_PERF_FLAG_DISABLED or was later disabled via - * I915_PERF_IOCTL_DISABLE. - * - * It is intended to be cheaper to disable and enable a stream than it may be - * to close and re-open a stream with the same configuration. - * - * It's undefined whether any pending data for the stream will be lost. - */ -#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) - -/** - * Disable data capture for a stream. - * - * It is an error to try and read a stream that is disabled. - */ -#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) - -/** - * Common to all i915 perf records - */ -struct drm_i915_perf_record_header { - __u32 type; - __u16 pad; - __u16 size; -}; - -enum drm_i915_perf_record_type { - - /** - * Samples are the work horse record type whose contents are extensible - * and defined when opening an i915 perf stream based on the given - * properties. - * - * Boolean properties following the naming convention - * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in - * every sample. - * - * The order of these sample properties given by userspace has no - * affect on the ordering of data within a sample. The order is - * documented here. - * - * struct { - * struct drm_i915_perf_record_header header; - * - * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA - * }; - */ - DRM_I915_PERF_RECORD_SAMPLE = 1, - - /* - * Indicates that one or more OA reports were not written by the - * hardware. This can happen for example if an MI_REPORT_PERF_COUNT - * command collides with periodic sampling - which would be more likely - * at higher sampling frequencies. - */ - DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, - - /** - * An error occurred that resulted in all pending OA reports being lost. - */ - DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, - - DRM_I915_PERF_RECORD_MAX /* non-ABI */ -}; - -/** - * Structure to upload perf dynamic configuration into the kernel. - */ -struct drm_i915_perf_oa_config { - /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ - char uuid[36]; - - __u32 n_mux_regs; - __u32 n_boolean_regs; - __u32 n_flex_regs; - - /* - * These fields are pointers to tuples of u32 values (register address, - * value). For example the expected length of the buffer pointed by - * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). - */ - __u64 mux_regs_ptr; - __u64 boolean_regs_ptr; - __u64 flex_regs_ptr; -}; - -struct drm_i915_query_item { - __u64 query_id; -#define DRM_I915_QUERY_TOPOLOGY_INFO 1 -/* Must be kept compact -- no holes and well documented */ - - /* - * When set to zero by userspace, this is filled with the size of the - * data to be written at the data_ptr pointer. The kernel sets this - * value to a negative value to signal an error on a particular query - * item. - */ - __s32 length; - - /* - * Unused for now. Must be cleared to zero. - */ - __u32 flags; - - /* - * Data will be written at the location pointed by data_ptr when the - * value of length matches the length of the data to be written by the - * kernel. - */ - __u64 data_ptr; -}; - -struct drm_i915_query { - __u32 num_items; - - /* - * Unused for now. Must be cleared to zero. - */ - __u32 flags; - - /* - * This points to an array of num_items drm_i915_query_item structures. - */ - __u64 items_ptr; -}; - -/* - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : - * - * data: contains the 3 pieces of information : - * - * - the slice mask with one bit per slice telling whether a slice is - * available. The availability of slice X can be queried with the following - * formula : - * - * (data[X / 8] >> (X % 8)) & 1 - * - * - the subslice mask for each slice with one bit per subslice telling - * whether a subslice is available. The availability of subslice Y in slice - * X can be queried with the following formula : - * - * (data[subslice_offset + - * X * subslice_stride + - * Y / 8] >> (Y % 8)) & 1 - * - * - the EU mask for each subslice in each slice with one bit per EU telling - * whether an EU is available. The availability of EU Z in subslice Y in - * slice X can be queried with the following formula : - * - * (data[eu_offset + - * (X * max_subslices + Y) * eu_stride + - * Z / 8] >> (Z % 8)) & 1 - */ -struct drm_i915_query_topology_info { - /* - * Unused for now. Must be cleared to zero. - */ - __u16 flags; - - __u16 max_slices; - __u16 max_subslices; - __u16 max_eus_per_subslice; - - /* - * Offset in data[] at which the subslice masks are stored. - */ - __u16 subslice_offset; - - /* - * Stride at which each of the subslice masks for each slice are - * stored. - */ - __u16 subslice_stride; - - /* - * Offset in data[] at which the EU masks are stored. - */ - __u16 eu_offset; - - /* - * Stride at which each of the EU masks for each subslice are stored. - */ - __u16 eu_stride; - - __u8 data[]; -}; - -#if defined(__cplusplus) -} -#endif - -#endif /* _I915_DRM_H_ */ diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/mach64_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/mach64_drm.h deleted file mode 100755 index 1f5fd84..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/mach64_drm.h +++ /dev/null @@ -1,256 +0,0 @@ -/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*- - * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com - */ -/* - * Copyright 2000 Gareth Hughes - * Copyright 2002 Frank C. Earl - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Frank C. Earl - * Leif Delgass - */ - -#ifndef __MACH64_DRM_H__ -#define __MACH64_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mach64_sarea.h) - */ -#ifndef __MACH64_SAREA_DEFINES__ -#define __MACH64_SAREA_DEFINES__ - -/* What needs to be changed for the current vertex buffer? - * GH: We're going to be pedantic about this. We want the card to do as - * little as possible, so let's avoid having it fetch a whole bunch of - * register values that don't change all that often, if at all. - */ -#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001 -#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002 -#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004 -#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008 -#define MACH64_UPLOAD_DP_FOG_CLR 0x0010 -#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020 -#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040 -#define MACH64_UPLOAD_SETUP_CNTL 0x0080 -#define MACH64_UPLOAD_MISC 0x0100 -#define MACH64_UPLOAD_TEXTURE 0x0200 -#define MACH64_UPLOAD_TEX0IMAGE 0x0400 -#define MACH64_UPLOAD_TEX1IMAGE 0x0800 -#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */ -#define MACH64_UPLOAD_CONTEXT 0x00ff -#define MACH64_UPLOAD_ALL 0x1fff - -/* DMA buffer size - */ -#define MACH64_BUFFER_SIZE 16384 - -/* Max number of swaps allowed on the ring - * before the client must wait - */ -#define MACH64_MAX_QUEUED_FRAMES 3U - -/* Byte offsets for host blit buffer data - */ -#define MACH64_HOSTDATA_BLIT_OFFSET 104 - -/* Keep these small for testing. - */ -#define MACH64_NR_SAREA_CLIPRECTS 8 - -#define MACH64_CARD_HEAP 0 -#define MACH64_AGP_HEAP 1 -#define MACH64_NR_TEX_HEAPS 2 -#define MACH64_NR_TEX_REGIONS 64 -#define MACH64_LOG_TEX_GRANULARITY 16 - -#define MACH64_TEX_MAXLEVELS 1 - -#define MACH64_NR_CONTEXT_REGS 15 -#define MACH64_NR_TEXTURE_REGS 4 - -#endif /* __MACH64_SAREA_DEFINES__ */ - -typedef struct { - unsigned int dst_off_pitch; - - unsigned int z_off_pitch; - unsigned int z_cntl; - unsigned int alpha_tst_cntl; - - unsigned int scale_3d_cntl; - - unsigned int sc_left_right; - unsigned int sc_top_bottom; - - unsigned int dp_fog_clr; - unsigned int dp_write_mask; - unsigned int dp_pix_width; - unsigned int dp_mix; - unsigned int dp_src; - - unsigned int clr_cmp_cntl; - unsigned int gui_traj_cntl; - - unsigned int setup_cntl; - - unsigned int tex_size_pitch; - unsigned int tex_cntl; - unsigned int secondary_tex_off; - unsigned int tex_offset; -} drm_mach64_context_regs_t; - -typedef struct drm_mach64_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex dma buffer. - */ - drm_mach64_context_regs_t context_state; - unsigned int dirty; - unsigned int vertsize; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int frames_queued; - - /* Texture memory LRU. - */ - struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + - 1]; - unsigned int tex_age[MACH64_NR_TEX_HEAPS]; - int ctx_owner; -} drm_mach64_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mach64_common.h) - */ - -/* Mach64 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ - -#define DRM_MACH64_INIT 0x00 -#define DRM_MACH64_IDLE 0x01 -#define DRM_MACH64_RESET 0x02 -#define DRM_MACH64_SWAP 0x03 -#define DRM_MACH64_CLEAR 0x04 -#define DRM_MACH64_VERTEX 0x05 -#define DRM_MACH64_BLIT 0x06 -#define DRM_MACH64_FLUSH 0x07 -#define DRM_MACH64_GETPARAM 0x08 - -#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t) -#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE ) -#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET ) -#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP ) -#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t) -#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t) -#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t) -#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH ) -#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t) - -/* Buffer flags for clears - */ -#define MACH64_FRONT 0x1 -#define MACH64_BACK 0x2 -#define MACH64_DEPTH 0x4 - -/* Primitive types for vertex buffers - */ -#define MACH64_PRIM_POINTS 0x00000000 -#define MACH64_PRIM_LINES 0x00000001 -#define MACH64_PRIM_LINE_LOOP 0x00000002 -#define MACH64_PRIM_LINE_STRIP 0x00000003 -#define MACH64_PRIM_TRIANGLES 0x00000004 -#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005 -#define MACH64_PRIM_TRIANGLE_FAN 0x00000006 -#define MACH64_PRIM_QUADS 0x00000007 -#define MACH64_PRIM_QUAD_STRIP 0x00000008 -#define MACH64_PRIM_POLYGON 0x00000009 - -typedef enum _drm_mach64_dma_mode_t { - MACH64_MODE_DMA_ASYNC, - MACH64_MODE_DMA_SYNC, - MACH64_MODE_MMIO -} drm_mach64_dma_mode_t; - -typedef struct drm_mach64_init { - enum { - DRM_MACH64_INIT_DMA = 0x01, - DRM_MACH64_CLEANUP_DMA = 0x02 - } func; - - unsigned long sarea_priv_offset; - int is_pci; - drm_mach64_dma_mode_t dma_mode; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; -} drm_mach64_init_t; - -typedef struct drm_mach64_clear { - unsigned int flags; - int x, y, w, h; - unsigned int clear_color; - unsigned int clear_depth; -} drm_mach64_clear_t; - -typedef struct drm_mach64_vertex { - int prim; - void *buf; /* Address of vertex buffer */ - unsigned long used; /* Number of bytes in buffer */ - int discard; /* Client finished with buffer? */ -} drm_mach64_vertex_t; - -typedef struct drm_mach64_blit { - void *buf; - int pitch; - int offset; - int format; - unsigned short x, y; - unsigned short width, height; -} drm_mach64_blit_t; - -typedef struct drm_mach64_getparam { - enum { - MACH64_PARAM_FRAMES_QUEUED = 0x01, - MACH64_PARAM_IRQ_NR = 0x02 - } param; - void *value; -} drm_mach64_getparam_t; - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/mga_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/mga_drm.h deleted file mode 100755 index 7930011..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/mga_drm.h +++ /dev/null @@ -1,427 +0,0 @@ -/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- - * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jeff Hartmann - * Keith Whitwell - * - * Rewritten by: - * Gareth Hughes - */ - -#ifndef __MGA_DRM_H__ -#define __MGA_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mga_sarea.h) - */ - -#ifndef __MGA_SAREA_DEFINES__ -#define __MGA_SAREA_DEFINES__ - -/* WARP pipe flags - */ -#define MGA_F 0x1 /* fog */ -#define MGA_A 0x2 /* alpha */ -#define MGA_S 0x4 /* specular */ -#define MGA_T2 0x8 /* multitexture */ - -#define MGA_WARP_TGZ 0 -#define MGA_WARP_TGZF (MGA_F) -#define MGA_WARP_TGZA (MGA_A) -#define MGA_WARP_TGZAF (MGA_F|MGA_A) -#define MGA_WARP_TGZS (MGA_S) -#define MGA_WARP_TGZSF (MGA_S|MGA_F) -#define MGA_WARP_TGZSA (MGA_S|MGA_A) -#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) -#define MGA_WARP_T2GZ (MGA_T2) -#define MGA_WARP_T2GZF (MGA_T2|MGA_F) -#define MGA_WARP_T2GZA (MGA_T2|MGA_A) -#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) -#define MGA_WARP_T2GZS (MGA_T2|MGA_S) -#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) -#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) -#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) - -#define MGA_MAX_G200_PIPES 8 /* no multitex */ -#define MGA_MAX_G400_PIPES 16 -#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES -#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ - -#define MGA_CARD_TYPE_G200 1 -#define MGA_CARD_TYPE_G400 2 -#define MGA_CARD_TYPE_G450 3 /* not currently used */ -#define MGA_CARD_TYPE_G550 4 - -#define MGA_FRONT 0x1 -#define MGA_BACK 0x2 -#define MGA_DEPTH 0x4 - -/* What needs to be changed for the current vertex dma buffer? - */ -#define MGA_UPLOAD_CONTEXT 0x1 -#define MGA_UPLOAD_TEX0 0x2 -#define MGA_UPLOAD_TEX1 0x4 -#define MGA_UPLOAD_PIPE 0x8 -#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ -#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ -#define MGA_UPLOAD_2D 0x40 -#define MGA_WAIT_AGE 0x80 /* handled client-side */ -#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ -#if 0 -#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock - quiescent */ -#endif - -/* 32 buffers of 64k each, total 2 meg. - */ -#define MGA_BUFFER_SIZE (1 << 16) -#define MGA_NUM_BUFFERS 128 - -/* Keep these small for testing. - */ -#define MGA_NR_SAREA_CLIPRECTS 8 - -/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 - * regions, subject to a minimum region size of (1<<16) == 64k. - * - * Clients may subdivide regions internally, but when sharing between - * clients, the region size is the minimum granularity. - */ - -#define MGA_CARD_HEAP 0 -#define MGA_AGP_HEAP 1 -#define MGA_NR_TEX_HEAPS 2 -#define MGA_NR_TEX_REGIONS 16 -#define MGA_LOG_MIN_TEX_REGION_SIZE 16 - -#define DRM_MGA_IDLE_RETRY 2048 - -#endif /* __MGA_SAREA_DEFINES__ */ - -/* Setup registers for 3D context - */ -typedef struct { - unsigned int dstorg; - unsigned int maccess; - unsigned int plnwt; - unsigned int dwgctl; - unsigned int alphactrl; - unsigned int fogcolor; - unsigned int wflag; - unsigned int tdualstage0; - unsigned int tdualstage1; - unsigned int fcol; - unsigned int stencil; - unsigned int stencilctl; -} drm_mga_context_regs_t; - -/* Setup registers for 2D, X server - */ -typedef struct { - unsigned int pitch; -} drm_mga_server_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int texctl; - unsigned int texctl2; - unsigned int texfilter; - unsigned int texbordercol; - unsigned int texorg; - unsigned int texwidth; - unsigned int texheight; - unsigned int texorg1; - unsigned int texorg2; - unsigned int texorg3; - unsigned int texorg4; -} drm_mga_texture_regs_t; - -/* General aging mechanism - */ -typedef struct { - unsigned int head; /* Position of head pointer */ - unsigned int wrap; /* Primary DMA wrap count */ -} drm_mga_age_t; - -typedef struct _drm_mga_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex dma buffer. - */ - drm_mga_context_regs_t context_state; - drm_mga_server_regs_t server_state; - drm_mga_texture_regs_t tex_state[2]; - unsigned int warp_pipe; - unsigned int dirty; - unsigned int vertsize; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Information about the most recently used 3d drawable. The - * client fills in the req_* fields, the server fills in the - * exported_ fields and puts the cliprects into boxes, above. - * - * The client clears the exported_drawable field before - * clobbering the boxes data. - */ - unsigned int req_drawable; /* the X drawable id */ - unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ - - unsigned int exported_drawable; - unsigned int exported_index; - unsigned int exported_stamp; - unsigned int exported_buffers; - unsigned int exported_nfront; - unsigned int exported_nback; - int exported_back_x, exported_front_x, exported_w; - int exported_back_y, exported_front_y, exported_h; - struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; - - /* Counters for aging textures and for client-side throttling. - */ - unsigned int status[4]; - unsigned int last_wrap; - - drm_mga_age_t last_frame; - unsigned int last_enqueue; /* last time a buffer was enqueued */ - unsigned int last_dispatch; /* age of the most recently dispatched buffer */ - unsigned int last_quiescent; /* */ - - /* LRU lists for texture memory in agp space and on the card. - */ - struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; - unsigned int texAge[MGA_NR_TEX_HEAPS]; - - /* Mechanism to validate card state. - */ - int ctxOwner; -} drm_mga_sarea_t; - -/* MGA specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_MGA_INIT 0x00 -#define DRM_MGA_FLUSH 0x01 -#define DRM_MGA_RESET 0x02 -#define DRM_MGA_SWAP 0x03 -#define DRM_MGA_CLEAR 0x04 -#define DRM_MGA_VERTEX 0x05 -#define DRM_MGA_INDICES 0x06 -#define DRM_MGA_ILOAD 0x07 -#define DRM_MGA_BLIT 0x08 -#define DRM_MGA_GETPARAM 0x09 - -/* 3.2: - * ioctls for operating on fences. - */ -#define DRM_MGA_SET_FENCE 0x0a -#define DRM_MGA_WAIT_FENCE 0x0b -#define DRM_MGA_DMA_BOOTSTRAP 0x0c - -#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock) -#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) -#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) -#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) -#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) -#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) -#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) -#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) -#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) -#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32) -#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32) -#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) - -typedef struct _drm_mga_warp_index { - int installed; - unsigned long phys_addr; - int size; -} drm_mga_warp_index_t; - -typedef struct drm_mga_init { - enum { - MGA_INIT_DMA = 0x01, - MGA_CLEANUP_DMA = 0x02 - } func; - - unsigned long sarea_priv_offset; - - int chipset; - int sgram; - - unsigned int maccess; - - unsigned int fb_cpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_cpp; - unsigned int depth_offset, depth_pitch; - - unsigned int texture_offset[MGA_NR_TEX_HEAPS]; - unsigned int texture_size[MGA_NR_TEX_HEAPS]; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long status_offset; - unsigned long warp_offset; - unsigned long primary_offset; - unsigned long buffers_offset; -} drm_mga_init_t; - -typedef struct drm_mga_dma_bootstrap { - /** - * \name AGP texture region - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will - * be filled in with the actual AGP texture settings. - * - * \warning - * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode - * is zero, it means that PCI memory (most likely through the use of - * an IOMMU) is being used for "AGP" textures. - */ - /*@{ */ - unsigned long texture_handle; /**< Handle used to map AGP textures. */ - __u32 texture_size; /**< Size of the AGP texture region. */ - /*@} */ - - /** - * Requested size of the primary DMA region. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual AGP mode. If AGP was not available - */ - __u32 primary_size; - - /** - * Requested number of secondary DMA buffers. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual number of secondary DMA buffers - * allocated. Particularly when PCI DMA is used, this may be - * (subtantially) less than the number requested. - */ - __u32 secondary_bin_count; - - /** - * Requested size of each secondary DMA buffer. - * - * While the kernel \b is free to reduce - * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed - * to reduce dma_mga_dma_bootstrap::secondary_bin_size. - */ - __u32 secondary_bin_size; - - /** - * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, - * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is - * zero, it means that PCI DMA should be used, even if AGP is - * possible. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual AGP mode. If AGP was not available - * (i.e., PCI DMA was used), this value will be zero. - */ - __u32 agp_mode; - - /** - * Desired AGP GART size, measured in megabytes. - */ - __u8 agp_size; -} drm_mga_dma_bootstrap_t; - -typedef struct drm_mga_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; -} drm_mga_clear_t; - -typedef struct drm_mga_vertex { - int idx; /* buffer to queue */ - int used; /* bytes in use */ - int discard; /* client finished with buffer? */ -} drm_mga_vertex_t; - -typedef struct drm_mga_indices { - int idx; /* buffer to queue */ - unsigned int start; - unsigned int end; - int discard; /* client finished with buffer? */ -} drm_mga_indices_t; - -typedef struct drm_mga_iload { - int idx; - unsigned int dstorg; - unsigned int length; -} drm_mga_iload_t; - -typedef struct _drm_mga_blit { - unsigned int planemask; - unsigned int srcorg; - unsigned int dstorg; - int src_pitch, dst_pitch; - int delta_sx, delta_sy; - int delta_dx, delta_dy; - int height, ydir; /* flip image vertically */ - int source_pitch, dest_pitch; -} drm_mga_blit_t; - -/* 3.1: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define MGA_PARAM_IRQ_NR 1 - -/* 3.2: Query the actual card type. The DDX only distinguishes between - * G200 chips and non-G200 chips, which it calls G400. It turns out that - * there are some very sublte differences between the G4x0 chips and the G550 - * chips. Using this parameter query, a client-side driver can detect the - * difference between a G4x0 and a G550. - */ -#define MGA_PARAM_CARD_TYPE 2 - -typedef struct drm_mga_getparam { - int param; - void *value; -} drm_mga_getparam_t; - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/nouveau_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/nouveau_drm.h deleted file mode 100755 index d42105c..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/nouveau_drm.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright 2005 Stephane Marchesin. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __NOUVEAU_DRM_H__ -#define __NOUVEAU_DRM_H__ - -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16 - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -struct drm_nouveau_channel_alloc { - uint32_t fb_ctxdma_handle; - uint32_t tt_ctxdma_handle; - - int channel; - uint32_t pushbuf_domains; - - /* Notifier memory */ - uint32_t notifier_handle; - - /* DRM-enforced subchannel assignments */ - struct { - uint32_t handle; - uint32_t grclass; - } subchan[8]; - uint32_t nr_subchan; -}; - -struct drm_nouveau_channel_free { - int channel; -}; - -struct drm_nouveau_grobj_alloc { - int channel; - uint32_t handle; - int class; -}; - -struct drm_nouveau_notifierobj_alloc { - uint32_t channel; - uint32_t handle; - uint32_t size; - uint32_t offset; -}; - -struct drm_nouveau_gpuobj_free { - int channel; - uint32_t handle; -}; - -/* FIXME : maybe unify {GET,SET}PARAMs */ -#define NOUVEAU_GETPARAM_PCI_VENDOR 3 -#define NOUVEAU_GETPARAM_PCI_DEVICE 4 -#define NOUVEAU_GETPARAM_BUS_TYPE 5 -#define NOUVEAU_GETPARAM_FB_PHYSICAL 6 -#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7 -#define NOUVEAU_GETPARAM_FB_SIZE 8 -#define NOUVEAU_GETPARAM_AGP_SIZE 9 -#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 -#define NOUVEAU_GETPARAM_CHIPSET_ID 11 -#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 -#define NOUVEAU_GETPARAM_GRAPH_UNITS 13 -#define NOUVEAU_GETPARAM_PTIMER_TIME 14 -#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 -#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 -struct drm_nouveau_getparam { - uint64_t param; - uint64_t value; -}; - -struct drm_nouveau_setparam { - uint64_t param; - uint64_t value; -}; - -#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) -#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) -#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) -#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) -#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) - -#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ -#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 -#define NOUVEAU_GEM_TILE_16BPP 0x00000001 -#define NOUVEAU_GEM_TILE_32BPP 0x00000002 -#define NOUVEAU_GEM_TILE_ZETA 0x00000004 -#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 - -struct drm_nouveau_gem_info { - __u32 handle; - __u32 domain; - __u64 size; - __u64 offset; - __u64 map_handle; - __u32 tile_mode; - __u32 tile_flags; -}; - -struct drm_nouveau_gem_new { - struct drm_nouveau_gem_info info; - __u32 channel_hint; - __u32 align; -}; - -#define NOUVEAU_GEM_MAX_BUFFERS 1024 -struct drm_nouveau_gem_pushbuf_bo_presumed { - __u32 valid; - __u32 domain; - __u64 offset; -}; - -struct drm_nouveau_gem_pushbuf_bo { - __u64 user_priv; - __u32 handle; - __u32 read_domains; - __u32 write_domains; - __u32 valid_domains; - struct drm_nouveau_gem_pushbuf_bo_presumed presumed; -}; - -#define NOUVEAU_GEM_RELOC_LOW (1 << 0) -#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) -#define NOUVEAU_GEM_RELOC_OR (1 << 2) -#define NOUVEAU_GEM_MAX_RELOCS 1024 -struct drm_nouveau_gem_pushbuf_reloc { - __u32 reloc_bo_index; - __u32 reloc_bo_offset; - __u32 bo_index; - __u32 flags; - __u32 data; - __u32 vor; - __u32 tor; -}; - -#define NOUVEAU_GEM_MAX_PUSH 512 -struct drm_nouveau_gem_pushbuf_push { - __u32 bo_index; - __u32 pad; - __u64 offset; - __u64 length; -}; - -struct drm_nouveau_gem_pushbuf { - __u32 channel; - __u32 nr_buffers; - __u64 buffers; - __u32 nr_relocs; - __u32 nr_push; - __u64 relocs; - __u64 push; - __u32 suffix0; - __u32 suffix1; - __u64 vram_available; - __u64 gart_available; -}; - -#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 -#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 -#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 -struct drm_nouveau_gem_cpu_prep { - __u32 handle; - __u32 flags; -}; - -struct drm_nouveau_gem_cpu_fini { - __u32 handle; -}; - -enum nouveau_bus_type { - NV_AGP = 0, - NV_PCI = 1, - NV_PCIE = 2, -}; - -struct drm_nouveau_sarea { -}; - -#define DRM_NOUVEAU_GETPARAM 0x00 -#define DRM_NOUVEAU_SETPARAM 0x01 -#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 -#define DRM_NOUVEAU_CHANNEL_FREE 0x03 -#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 -#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 -#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 -#define DRM_NOUVEAU_NVIF 0x07 -#define DRM_NOUVEAU_GEM_NEW 0x40 -#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 -#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 -#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 -#define DRM_NOUVEAU_GEM_INFO 0x44 - -#if defined(__cplusplus) -} -#endif - -#endif /* __NOUVEAU_DRM_H__ */ diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/qxl_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/qxl_drm.h deleted file mode 100755 index 880999d..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/qxl_drm.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright 2013 Red Hat - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef QXL_DRM_H -#define QXL_DRM_H - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - * - * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel - * compatibility Keep fields aligned to their size - */ - -#define QXL_GEM_DOMAIN_CPU 0 -#define QXL_GEM_DOMAIN_VRAM 1 -#define QXL_GEM_DOMAIN_SURFACE 2 - -#define DRM_QXL_ALLOC 0x00 -#define DRM_QXL_MAP 0x01 -#define DRM_QXL_EXECBUFFER 0x02 -#define DRM_QXL_UPDATE_AREA 0x03 -#define DRM_QXL_GETPARAM 0x04 -#define DRM_QXL_CLIENTCAP 0x05 - -#define DRM_QXL_ALLOC_SURF 0x06 - -struct drm_qxl_alloc { - __u32 size; - __u32 handle; /* 0 is an invalid handle */ -}; - -struct drm_qxl_map { - __u64 offset; /* use for mmap system call */ - __u32 handle; - __u32 pad; -}; - -/* - * dest is the bo we are writing the relocation into - * src is bo we are relocating. - * *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr + - * src_offset) - */ -#define QXL_RELOC_TYPE_BO 1 -#define QXL_RELOC_TYPE_SURF 2 - -struct drm_qxl_reloc { - __u64 src_offset; /* offset into src_handle or src buffer */ - __u64 dst_offset; /* offset in dest handle */ - __u32 src_handle; /* dest handle to compute address from */ - __u32 dst_handle; /* 0 if to command buffer */ - __u32 reloc_type; - __u32 pad; -}; - -struct drm_qxl_command { - __u64 command; /* void* */ - __u64 relocs; /* struct drm_qxl_reloc* */ - __u32 type; - __u32 command_size; - __u32 relocs_num; - __u32 pad; -}; - -struct drm_qxl_execbuffer { - __u32 flags; /* for future use */ - __u32 commands_num; - __u64 commands; /* struct drm_qxl_command* */ -}; - -struct drm_qxl_update_area { - __u32 handle; - __u32 top; - __u32 left; - __u32 bottom; - __u32 right; - __u32 pad; -}; - -#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */ -#define QXL_PARAM_MAX_RELOCS 2 -struct drm_qxl_getparam { - __u64 param; - __u64 value; -}; - -/* these are one bit values */ -struct drm_qxl_clientcap { - __u32 index; - __u32 pad; -}; - -struct drm_qxl_alloc_surf { - __u32 format; - __u32 width; - __u32 height; - __s32 stride; - __u32 handle; - __u32 pad; -}; - -#define DRM_IOCTL_QXL_ALLOC \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc) - -#define DRM_IOCTL_QXL_MAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map) - -#define DRM_IOCTL_QXL_EXECBUFFER \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\ - struct drm_qxl_execbuffer) - -#define DRM_IOCTL_QXL_UPDATE_AREA \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\ - struct drm_qxl_update_area) - -#define DRM_IOCTL_QXL_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\ - struct drm_qxl_getparam) - -#define DRM_IOCTL_QXL_CLIENTCAP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\ - struct drm_qxl_clientcap) - -#define DRM_IOCTL_QXL_ALLOC_SURF \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\ - struct drm_qxl_alloc_surf) - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/r128_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/r128_drm.h deleted file mode 100755 index bf431a0..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/r128_drm.h +++ /dev/null @@ -1,336 +0,0 @@ -/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- - * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com - */ -/* - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Kevin E. Martin - */ - -#ifndef __R128_DRM_H__ -#define __R128_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the X server file (r128_sarea.h) - */ -#ifndef __R128_SAREA_DEFINES__ -#define __R128_SAREA_DEFINES__ - -/* What needs to be changed for the current vertex buffer? - */ -#define R128_UPLOAD_CONTEXT 0x001 -#define R128_UPLOAD_SETUP 0x002 -#define R128_UPLOAD_TEX0 0x004 -#define R128_UPLOAD_TEX1 0x008 -#define R128_UPLOAD_TEX0IMAGES 0x010 -#define R128_UPLOAD_TEX1IMAGES 0x020 -#define R128_UPLOAD_CORE 0x040 -#define R128_UPLOAD_MASKS 0x080 -#define R128_UPLOAD_WINDOW 0x100 -#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ -#define R128_REQUIRE_QUIESCENCE 0x400 -#define R128_UPLOAD_ALL 0x7ff - -#define R128_FRONT 0x1 -#define R128_BACK 0x2 -#define R128_DEPTH 0x4 - -/* Primitive types - */ -#define R128_POINTS 0x1 -#define R128_LINES 0x2 -#define R128_LINE_STRIP 0x3 -#define R128_TRIANGLES 0x4 -#define R128_TRIANGLE_FAN 0x5 -#define R128_TRIANGLE_STRIP 0x6 - -/* Vertex/indirect buffer size - */ -#define R128_BUFFER_SIZE 16384 - -/* Byte offsets for indirect buffer data - */ -#define R128_INDEX_PRIM_OFFSET 20 -#define R128_HOSTDATA_BLIT_OFFSET 32 - -/* Keep these small for testing. - */ -#define R128_NR_SAREA_CLIPRECTS 12 - -/* There are 2 heaps (local/AGP). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. - */ -#define R128_LOCAL_TEX_HEAP 0 -#define R128_AGP_TEX_HEAP 1 -#define R128_NR_TEX_HEAPS 2 -#define R128_NR_TEX_REGIONS 64 -#define R128_LOG_TEX_GRANULARITY 16 - -#define R128_NR_CONTEXT_REGS 12 - -#define R128_MAX_TEXTURE_LEVELS 11 -#define R128_MAX_TEXTURE_UNITS 2 - -#endif /* __R128_SAREA_DEFINES__ */ - -typedef struct { - /* Context state - can be written in one large chunk */ - unsigned int dst_pitch_offset_c; - unsigned int dp_gui_master_cntl_c; - unsigned int sc_top_left_c; - unsigned int sc_bottom_right_c; - unsigned int z_offset_c; - unsigned int z_pitch_c; - unsigned int z_sten_cntl_c; - unsigned int tex_cntl_c; - unsigned int misc_3d_state_cntl_reg; - unsigned int texture_clr_cmp_clr_c; - unsigned int texture_clr_cmp_msk_c; - unsigned int fog_color_c; - - /* Texture state */ - unsigned int tex_size_pitch_c; - unsigned int constant_color_c; - - /* Setup state */ - unsigned int pm4_vc_fpu_setup; - unsigned int setup_cntl; - - /* Mask state */ - unsigned int dp_write_mask; - unsigned int sten_ref_mask_c; - unsigned int plane_3d_mask_c; - - /* Window state */ - unsigned int window_xy_offset; - - /* Core state */ - unsigned int scale_3d_cntl; -} drm_r128_context_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int tex_cntl; - unsigned int tex_combine_cntl; - unsigned int tex_size_pitch; - unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; - unsigned int tex_border_color; -} drm_r128_texture_regs_t; - -typedef struct drm_r128_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex buffer. - */ - drm_r128_context_regs_t context_state; - drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; - unsigned int dirty; - unsigned int vertsize; - unsigned int vc_format; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int last_frame; - unsigned int last_dispatch; - - struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; - unsigned int tex_age[R128_NR_TEX_HEAPS]; - int ctx_owner; - int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ - int pfCurrentPage; /* which buffer is being displayed? */ -} drm_r128_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmR128.h) - */ - -/* Rage 128 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_R128_INIT 0x00 -#define DRM_R128_CCE_START 0x01 -#define DRM_R128_CCE_STOP 0x02 -#define DRM_R128_CCE_RESET 0x03 -#define DRM_R128_CCE_IDLE 0x04 -/* 0x05 not used */ -#define DRM_R128_RESET 0x06 -#define DRM_R128_SWAP 0x07 -#define DRM_R128_CLEAR 0x08 -#define DRM_R128_VERTEX 0x09 -#define DRM_R128_INDICES 0x0a -#define DRM_R128_BLIT 0x0b -#define DRM_R128_DEPTH 0x0c -#define DRM_R128_STIPPLE 0x0d -/* 0x0e not used */ -#define DRM_R128_INDIRECT 0x0f -#define DRM_R128_FULLSCREEN 0x10 -#define DRM_R128_CLEAR2 0x11 -#define DRM_R128_GETPARAM 0x12 -#define DRM_R128_FLIP 0x13 - -#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) -#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) -#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) -#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) -#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) -/* 0x05 not used */ -#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) -#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) -#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) -#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) -#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) -#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) -#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) -#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) -/* 0x0e not used */ -#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) -#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) -#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) -#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) -#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) - -typedef struct drm_r128_init { - enum { - R128_INIT_CCE = 0x01, - R128_CLEANUP_CCE = 0x02 - } func; - unsigned long sarea_priv_offset; - int is_pci; - int cce_mode; - int cce_secure; - int ring_size; - int usec_timeout; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - unsigned int span_offset; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; -} drm_r128_init_t; - -typedef struct drm_r128_cce_stop { - int flush; - int idle; -} drm_r128_cce_stop_t; - -typedef struct drm_r128_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; -} drm_r128_clear_t; - -typedef struct drm_r128_vertex { - int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ -} drm_r128_vertex_t; - -typedef struct drm_r128_indices { - int prim; - int idx; - int start; - int end; - int discard; /* Client finished with buffer? */ -} drm_r128_indices_t; - -typedef struct drm_r128_blit { - int idx; - int pitch; - int offset; - int format; - unsigned short x, y; - unsigned short width, height; -} drm_r128_blit_t; - -typedef struct drm_r128_depth { - enum { - R128_WRITE_SPAN = 0x01, - R128_WRITE_PIXELS = 0x02, - R128_READ_SPAN = 0x03, - R128_READ_PIXELS = 0x04 - } func; - int n; - int *x; - int *y; - unsigned int *buffer; - unsigned char *mask; -} drm_r128_depth_t; - -typedef struct drm_r128_stipple { - unsigned int *mask; -} drm_r128_stipple_t; - -typedef struct drm_r128_indirect { - int idx; - int start; - int end; - int discard; -} drm_r128_indirect_t; - -typedef struct drm_r128_fullscreen { - enum { - R128_INIT_FULLSCREEN = 0x01, - R128_CLEANUP_FULLSCREEN = 0x02 - } func; -} drm_r128_fullscreen_t; - -/* 2.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define R128_PARAM_IRQ_NR 1 - -typedef struct drm_r128_getparam { - int param; - void *value; -} drm_r128_getparam_t; - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/radeon_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/radeon_drm.h deleted file mode 100755 index a1e385d..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/radeon_drm.h +++ /dev/null @@ -1,1079 +0,0 @@ -/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - * Keith Whitwell - */ - -#ifndef __RADEON_DRM_H__ -#define __RADEON_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the X server file (radeon_sarea.h) - */ -#ifndef __RADEON_SAREA_DEFINES__ -#define __RADEON_SAREA_DEFINES__ - -/* Old style state flags, required for sarea interface (1.1 and 1.2 - * clears) and 1.2 drm_vertex2 ioctl. - */ -#define RADEON_UPLOAD_CONTEXT 0x00000001 -#define RADEON_UPLOAD_VERTFMT 0x00000002 -#define RADEON_UPLOAD_LINE 0x00000004 -#define RADEON_UPLOAD_BUMPMAP 0x00000008 -#define RADEON_UPLOAD_MASKS 0x00000010 -#define RADEON_UPLOAD_VIEWPORT 0x00000020 -#define RADEON_UPLOAD_SETUP 0x00000040 -#define RADEON_UPLOAD_TCL 0x00000080 -#define RADEON_UPLOAD_MISC 0x00000100 -#define RADEON_UPLOAD_TEX0 0x00000200 -#define RADEON_UPLOAD_TEX1 0x00000400 -#define RADEON_UPLOAD_TEX2 0x00000800 -#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 -#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 -#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 -#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ -#define RADEON_REQUIRE_QUIESCENCE 0x00010000 -#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ -#define RADEON_UPLOAD_ALL 0x003effff -#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff - -/* New style per-packet identifiers for use in cmd_buffer ioctl with - * the RADEON_EMIT_PACKET command. Comments relate new packets to old - * state bits and the packet size: - */ -#define RADEON_EMIT_PP_MISC 0 /* context/7 */ -#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ -#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ -#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ -#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ -#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ -#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ -#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ -#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ -#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ -#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ -#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ -#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ -#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ -#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ -#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ -#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ -#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ -#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ -#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ -#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ -#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ -#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ -#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ -#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ -#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ -#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ -#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ -#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ -#define R200_EMIT_VAP_CTL 32 /* vap/1 */ -#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ -#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ -#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ -#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ -#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ -#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ -#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ -#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ -#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ -#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ -#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ -#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ -#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ -#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ -#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ -#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ -#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ -#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ -#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ -#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ -#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ -#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ -#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ -#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ -#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ -#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ -#define R200_EMIT_PP_CUBIC_FACES_0 61 -#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 -#define R200_EMIT_PP_CUBIC_FACES_1 63 -#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 -#define R200_EMIT_PP_CUBIC_FACES_2 65 -#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 -#define R200_EMIT_PP_CUBIC_FACES_3 67 -#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 -#define R200_EMIT_PP_CUBIC_FACES_4 69 -#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 -#define R200_EMIT_PP_CUBIC_FACES_5 71 -#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 -#define RADEON_EMIT_PP_TEX_SIZE_0 73 -#define RADEON_EMIT_PP_TEX_SIZE_1 74 -#define RADEON_EMIT_PP_TEX_SIZE_2 75 -#define R200_EMIT_RB3D_BLENDCOLOR 76 -#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 -#define RADEON_EMIT_PP_CUBIC_FACES_0 78 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 -#define RADEON_EMIT_PP_CUBIC_FACES_1 80 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 -#define RADEON_EMIT_PP_CUBIC_FACES_2 82 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 -#define R200_EMIT_PP_TRI_PERF_CNTL 84 -#define R200_EMIT_PP_AFS_0 85 -#define R200_EMIT_PP_AFS_1 86 -#define R200_EMIT_ATF_TFACTOR 87 -#define R200_EMIT_PP_TXCTLALL_0 88 -#define R200_EMIT_PP_TXCTLALL_1 89 -#define R200_EMIT_PP_TXCTLALL_2 90 -#define R200_EMIT_PP_TXCTLALL_3 91 -#define R200_EMIT_PP_TXCTLALL_4 92 -#define R200_EMIT_PP_TXCTLALL_5 93 -#define R200_EMIT_VAP_PVS_CNTL 94 -#define RADEON_MAX_STATE_PACKETS 95 - -/* Commands understood by cmd_buffer ioctl. More can be added but - * obviously these can't be removed or changed: - */ -#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ -#define RADEON_CMD_SCALARS 2 /* emit scalar data */ -#define RADEON_CMD_VECTORS 3 /* emit vector data */ -#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ -#define RADEON_CMD_PACKET3 5 /* emit hw packet */ -#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ -#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ -#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: - * doesn't make the cpu wait, just - * the graphics hardware */ -#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ - -typedef union { - int i; - struct { - unsigned char cmd_type, pad0, pad1, pad2; - } header; - struct { - unsigned char cmd_type, packet_id, pad0, pad1; - } packet; - struct { - unsigned char cmd_type, offset, stride, count; - } scalars; - struct { - unsigned char cmd_type, offset, stride, count; - } vectors; - struct { - unsigned char cmd_type, addr_lo, addr_hi, count; - } veclinear; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; - } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; - } wait; -} drm_radeon_cmd_header_t; - -#define RADEON_WAIT_2D 0x1 -#define RADEON_WAIT_3D 0x2 - -/* Allowed parameters for R300_CMD_PACKET3 - */ -#define R300_CMD_PACKET3_CLEAR 0 -#define R300_CMD_PACKET3_RAW 1 - -/* Commands understood by cmd_buffer ioctl for R300. - * The interface has not been stabilized, so some of these may be removed - * and eventually reordered before stabilization. - */ -#define R300_CMD_PACKET0 1 -#define R300_CMD_VPU 2 /* emit vertex program upload */ -#define R300_CMD_PACKET3 3 /* emit a packet3 */ -#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ -#define R300_CMD_CP_DELAY 5 -#define R300_CMD_DMA_DISCARD 6 -#define R300_CMD_WAIT 7 -# define R300_WAIT_2D 0x1 -# define R300_WAIT_3D 0x2 -/* these two defines are DOING IT WRONG - however - * we have userspace which relies on using these. - * The wait interface is backwards compat new - * code should use the NEW_WAIT defines below - * THESE ARE NOT BIT FIELDS - */ -# define R300_WAIT_2D_CLEAN 0x3 -# define R300_WAIT_3D_CLEAN 0x4 - -# define R300_NEW_WAIT_2D_3D 0x3 -# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 -# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 -# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 - -#define R300_CMD_SCRATCH 8 -#define R300_CMD_R500FP 9 - -typedef union { - unsigned int u; - struct { - unsigned char cmd_type, pad0, pad1, pad2; - } header; - struct { - unsigned char cmd_type, count, reglo, reghi; - } packet0; - struct { - unsigned char cmd_type, count, adrlo, adrhi; - } vpu; - struct { - unsigned char cmd_type, packet, pad0, pad1; - } packet3; - struct { - unsigned char cmd_type, packet; - unsigned short count; /* amount of packet2 to emit */ - } delay; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; - } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; - } wait; - struct { - unsigned char cmd_type, reg, n_bufs, flags; - } scratch; - struct { - unsigned char cmd_type, count, adrlo, adrhi_flags; - } r500fp; -} drm_r300_cmd_header_t; - -#define RADEON_FRONT 0x1 -#define RADEON_BACK 0x2 -#define RADEON_DEPTH 0x4 -#define RADEON_STENCIL 0x8 -#define RADEON_CLEAR_FASTZ 0x80000000 -#define RADEON_USE_HIERZ 0x40000000 -#define RADEON_USE_COMP_ZBUF 0x20000000 - -#define R500FP_CONSTANT_TYPE (1 << 1) -#define R500FP_CONSTANT_CLAMP (1 << 2) - -/* Primitive types - */ -#define RADEON_POINTS 0x1 -#define RADEON_LINES 0x2 -#define RADEON_LINE_STRIP 0x3 -#define RADEON_TRIANGLES 0x4 -#define RADEON_TRIANGLE_FAN 0x5 -#define RADEON_TRIANGLE_STRIP 0x6 - -/* Vertex/indirect buffer size - */ -#define RADEON_BUFFER_SIZE 65536 - -/* Byte offsets for indirect buffer data - */ -#define RADEON_INDEX_PRIM_OFFSET 20 - -#define RADEON_SCRATCH_REG_OFFSET 32 - -#define R600_SCRATCH_REG_OFFSET 256 - -#define RADEON_NR_SAREA_CLIPRECTS 12 - -/* There are 2 heaps (local/GART). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. - */ -#define RADEON_LOCAL_TEX_HEAP 0 -#define RADEON_GART_TEX_HEAP 1 -#define RADEON_NR_TEX_HEAPS 2 -#define RADEON_NR_TEX_REGIONS 64 -#define RADEON_LOG_TEX_GRANULARITY 16 - -#define RADEON_MAX_TEXTURE_LEVELS 12 -#define RADEON_MAX_TEXTURE_UNITS 3 - -#define RADEON_MAX_SURFACES 8 - -/* Blits have strict offset rules. All blit offset must be aligned on - * a 1K-byte boundary. - */ -#define RADEON_OFFSET_SHIFT 10 -#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) -#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) - -#endif /* __RADEON_SAREA_DEFINES__ */ - -typedef struct { - unsigned int red; - unsigned int green; - unsigned int blue; - unsigned int alpha; -} radeon_color_regs_t; - -typedef struct { - /* Context state */ - unsigned int pp_misc; /* 0x1c14 */ - unsigned int pp_fog_color; - unsigned int re_solid_color; - unsigned int rb3d_blendcntl; - unsigned int rb3d_depthoffset; - unsigned int rb3d_depthpitch; - unsigned int rb3d_zstencilcntl; - - unsigned int pp_cntl; /* 0x1c38 */ - unsigned int rb3d_cntl; - unsigned int rb3d_coloroffset; - unsigned int re_width_height; - unsigned int rb3d_colorpitch; - unsigned int se_cntl; - - /* Vertex format state */ - unsigned int se_coord_fmt; /* 0x1c50 */ - - /* Line state */ - unsigned int re_line_pattern; /* 0x1cd0 */ - unsigned int re_line_state; - - unsigned int se_line_width; /* 0x1db8 */ - - /* Bumpmap state */ - unsigned int pp_lum_matrix; /* 0x1d00 */ - - unsigned int pp_rot_matrix_0; /* 0x1d58 */ - unsigned int pp_rot_matrix_1; - - /* Mask state */ - unsigned int rb3d_stencilrefmask; /* 0x1d7c */ - unsigned int rb3d_ropcntl; - unsigned int rb3d_planemask; - - /* Viewport state */ - unsigned int se_vport_xscale; /* 0x1d98 */ - unsigned int se_vport_xoffset; - unsigned int se_vport_yscale; - unsigned int se_vport_yoffset; - unsigned int se_vport_zscale; - unsigned int se_vport_zoffset; - - /* Setup state */ - unsigned int se_cntl_status; /* 0x2140 */ - - /* Misc state */ - unsigned int re_top_left; /* 0x26c0 */ - unsigned int re_misc; -} drm_radeon_context_regs_t; - -typedef struct { - /* Zbias state */ - unsigned int se_zbias_factor; /* 0x1dac */ - unsigned int se_zbias_constant; -} drm_radeon_context2_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int pp_txfilter; - unsigned int pp_txformat; - unsigned int pp_txoffset; - unsigned int pp_txcblend; - unsigned int pp_txablend; - unsigned int pp_tfactor; - unsigned int pp_border_color; -} drm_radeon_texture_regs_t; - -typedef struct { - unsigned int start; - unsigned int finish; - unsigned int prim:8; - unsigned int stateidx:8; - unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ - unsigned int vc_format; /* vertex format */ -} drm_radeon_prim_t; - -typedef struct { - drm_radeon_context_regs_t context; - drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; - drm_radeon_context2_regs_t context2; - unsigned int dirty; -} drm_radeon_state_t; - -typedef struct { - /* The channel for communication of state information to the - * kernel on firing a vertex buffer with either of the - * obsoleted vertex/index ioctls. - */ - drm_radeon_context_regs_t context_state; - drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; - unsigned int dirty; - unsigned int vertsize; - unsigned int vc_format; - - /* The current cliprects, or a subset thereof. - */ - struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int last_frame; - unsigned int last_dispatch; - unsigned int last_clear; - - struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + - 1]; - unsigned int tex_age[RADEON_NR_TEX_HEAPS]; - int ctx_owner; - int pfState; /* number of 3d windows (0,1,2ormore) */ - int pfCurrentPage; /* which buffer is being displayed? */ - int crtc2_base; /* CRTC2 frame offset */ - int tiling_enabled; /* set by drm, read by 2d + 3d clients */ -} drm_radeon_sarea_t; - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmRadeon.h) - * - * KW: actually it's illegal to change any of this (backwards compatibility). - */ - -/* Radeon specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_RADEON_CP_INIT 0x00 -#define DRM_RADEON_CP_START 0x01 -#define DRM_RADEON_CP_STOP 0x02 -#define DRM_RADEON_CP_RESET 0x03 -#define DRM_RADEON_CP_IDLE 0x04 -#define DRM_RADEON_RESET 0x05 -#define DRM_RADEON_FULLSCREEN 0x06 -#define DRM_RADEON_SWAP 0x07 -#define DRM_RADEON_CLEAR 0x08 -#define DRM_RADEON_VERTEX 0x09 -#define DRM_RADEON_INDICES 0x0A -#define DRM_RADEON_NOT_USED -#define DRM_RADEON_STIPPLE 0x0C -#define DRM_RADEON_INDIRECT 0x0D -#define DRM_RADEON_TEXTURE 0x0E -#define DRM_RADEON_VERTEX2 0x0F -#define DRM_RADEON_CMDBUF 0x10 -#define DRM_RADEON_GETPARAM 0x11 -#define DRM_RADEON_FLIP 0x12 -#define DRM_RADEON_ALLOC 0x13 -#define DRM_RADEON_FREE 0x14 -#define DRM_RADEON_INIT_HEAP 0x15 -#define DRM_RADEON_IRQ_EMIT 0x16 -#define DRM_RADEON_IRQ_WAIT 0x17 -#define DRM_RADEON_CP_RESUME 0x18 -#define DRM_RADEON_SETPARAM 0x19 -#define DRM_RADEON_SURF_ALLOC 0x1a -#define DRM_RADEON_SURF_FREE 0x1b -/* KMS ioctl */ -#define DRM_RADEON_GEM_INFO 0x1c -#define DRM_RADEON_GEM_CREATE 0x1d -#define DRM_RADEON_GEM_MMAP 0x1e -#define DRM_RADEON_GEM_PREAD 0x21 -#define DRM_RADEON_GEM_PWRITE 0x22 -#define DRM_RADEON_GEM_SET_DOMAIN 0x23 -#define DRM_RADEON_GEM_WAIT_IDLE 0x24 -#define DRM_RADEON_CS 0x26 -#define DRM_RADEON_INFO 0x27 -#define DRM_RADEON_GEM_SET_TILING 0x28 -#define DRM_RADEON_GEM_GET_TILING 0x29 -#define DRM_RADEON_GEM_BUSY 0x2a -#define DRM_RADEON_GEM_VA 0x2b -#define DRM_RADEON_GEM_OP 0x2c -#define DRM_RADEON_GEM_USERPTR 0x2d - -#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) -#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) -#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) -#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) -#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) -#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) -#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) -#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) -#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) -#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) -#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) -#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) -#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) -#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) -#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) -#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) -#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) -/* KMS */ -#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) -#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) -#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) -#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) -#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) -#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) -#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) -#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) -#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) -#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) -#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) -#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) -#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) -#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) -#define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) - -typedef struct drm_radeon_init { - enum { - RADEON_INIT_CP = 0x01, - RADEON_CLEANUP_CP = 0x02, - RADEON_INIT_R200_CP = 0x03, - RADEON_INIT_R300_CP = 0x04, - RADEON_INIT_R600_CP = 0x05 - } func; - unsigned long sarea_priv_offset; - int is_pci; - int cp_mode; - int gart_size; - int ring_size; - int usec_timeout; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long gart_textures_offset; -} drm_radeon_init_t; - -typedef struct drm_radeon_cp_stop { - int flush; - int idle; -} drm_radeon_cp_stop_t; - -typedef struct drm_radeon_fullscreen { - enum { - RADEON_INIT_FULLSCREEN = 0x01, - RADEON_CLEANUP_FULLSCREEN = 0x02 - } func; -} drm_radeon_fullscreen_t; - -#define CLEAR_X1 0 -#define CLEAR_Y1 1 -#define CLEAR_X2 2 -#define CLEAR_Y2 3 -#define CLEAR_DEPTH 4 - -typedef union drm_radeon_clear_rect { - float f[5]; - unsigned int ui[5]; -} drm_radeon_clear_rect_t; - -typedef struct drm_radeon_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; /* misnamed field: should be stencil */ - drm_radeon_clear_rect_t *depth_boxes; -} drm_radeon_clear_t; - -typedef struct drm_radeon_vertex { - int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ -} drm_radeon_vertex_t; - -typedef struct drm_radeon_indices { - int prim; - int idx; - int start; - int end; - int discard; /* Client finished with buffer? */ -} drm_radeon_indices_t; - -/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices - * - allows multiple primitives and state changes in a single ioctl - * - supports driver change to emit native primitives - */ -typedef struct drm_radeon_vertex2 { - int idx; /* Index of vertex buffer */ - int discard; /* Client finished with buffer? */ - int nr_states; - drm_radeon_state_t *state; - int nr_prims; - drm_radeon_prim_t *prim; -} drm_radeon_vertex2_t; - -/* v1.3 - obsoletes drm_radeon_vertex2 - * - allows arbitrarily large cliprect list - * - allows updating of tcl packet, vector and scalar state - * - allows memory-efficient description of state updates - * - allows state to be emitted without a primitive - * (for clears, ctx switches) - * - allows more than one dma buffer to be referenced per ioctl - * - supports tcl driver - * - may be extended in future versions with new cmd types, packets - */ -typedef struct drm_radeon_cmd_buffer { - int bufsz; - char *buf; - int nbox; - struct drm_clip_rect *boxes; -} drm_radeon_cmd_buffer_t; - -typedef struct drm_radeon_tex_image { - unsigned int x, y; /* Blit coordinates */ - unsigned int width, height; - const void *data; -} drm_radeon_tex_image_t; - -typedef struct drm_radeon_texture { - unsigned int offset; - int pitch; - int format; - int width; /* Texture image coordinates */ - int height; - drm_radeon_tex_image_t *image; -} drm_radeon_texture_t; - -typedef struct drm_radeon_stipple { - unsigned int *mask; -} drm_radeon_stipple_t; - -typedef struct drm_radeon_indirect { - int idx; - int start; - int end; - int discard; -} drm_radeon_indirect_t; - -/* enum for card type parameters */ -#define RADEON_CARD_PCI 0 -#define RADEON_CARD_AGP 1 -#define RADEON_CARD_PCIE 2 - -/* 1.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ -#define RADEON_PARAM_LAST_FRAME 2 -#define RADEON_PARAM_LAST_DISPATCH 3 -#define RADEON_PARAM_LAST_CLEAR 4 -/* Added with DRM version 1.6. */ -#define RADEON_PARAM_IRQ_NR 5 -#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ -/* Added with DRM version 1.8. */ -#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ -#define RADEON_PARAM_STATUS_HANDLE 8 -#define RADEON_PARAM_SAREA_HANDLE 9 -#define RADEON_PARAM_GART_TEX_HANDLE 10 -#define RADEON_PARAM_SCRATCH_OFFSET 11 -#define RADEON_PARAM_CARD_TYPE 12 -#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ -#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ -#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ -#define RADEON_PARAM_DEVICE_ID 16 -#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ - -typedef struct drm_radeon_getparam { - int param; - void *value; -} drm_radeon_getparam_t; - -/* 1.6: Set up a memory manager for regions of shared memory: - */ -#define RADEON_MEM_REGION_GART 1 -#define RADEON_MEM_REGION_FB 2 - -typedef struct drm_radeon_mem_alloc { - int region; - int alignment; - int size; - int *region_offset; /* offset from start of fb or GART */ -} drm_radeon_mem_alloc_t; - -typedef struct drm_radeon_mem_free { - int region; - int region_offset; -} drm_radeon_mem_free_t; - -typedef struct drm_radeon_mem_init_heap { - int region; - int size; - int start; -} drm_radeon_mem_init_heap_t; - -/* 1.6: Userspace can request & wait on irq's: - */ -typedef struct drm_radeon_irq_emit { - int *irq_seq; -} drm_radeon_irq_emit_t; - -typedef struct drm_radeon_irq_wait { - int irq_seq; -} drm_radeon_irq_wait_t; - -/* 1.10: Clients tell the DRM where they think the framebuffer is located in - * the card's address space, via a new generic ioctl to set parameters - */ - -typedef struct drm_radeon_setparam { - unsigned int param; - __s64 value; -} drm_radeon_setparam_t; - -#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ -#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ -#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ -#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ -#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ -#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ -/* 1.14: Clients can allocate/free a surface - */ -typedef struct drm_radeon_surface_alloc { - unsigned int address; - unsigned int size; - unsigned int flags; -} drm_radeon_surface_alloc_t; - -typedef struct drm_radeon_surface_free { - unsigned int address; -} drm_radeon_surface_free_t; - -#define DRM_RADEON_VBLANK_CRTC1 1 -#define DRM_RADEON_VBLANK_CRTC2 2 - -/* - * Kernel modesetting world below. - */ -#define RADEON_GEM_DOMAIN_CPU 0x1 -#define RADEON_GEM_DOMAIN_GTT 0x2 -#define RADEON_GEM_DOMAIN_VRAM 0x4 - -struct drm_radeon_gem_info { - __u64 gart_size; - __u64 vram_size; - __u64 vram_visible; -}; - -#define RADEON_GEM_NO_BACKING_STORE (1 << 0) -#define RADEON_GEM_GTT_UC (1 << 1) -#define RADEON_GEM_GTT_WC (1 << 2) -/* BO is expected to be accessed by the CPU */ -#define RADEON_GEM_CPU_ACCESS (1 << 3) -/* CPU access is not expected to work for this BO */ -#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) - -struct drm_radeon_gem_create { - __u64 size; - __u64 alignment; - __u32 handle; - __u32 initial_domain; - __u32 flags; -}; - -/* - * This is not a reliable API and you should expect it to fail for any - * number of reasons and have fallback path that do not use userptr to - * perform any operation. - */ -#define RADEON_GEM_USERPTR_READONLY (1 << 0) -#define RADEON_GEM_USERPTR_ANONONLY (1 << 1) -#define RADEON_GEM_USERPTR_VALIDATE (1 << 2) -#define RADEON_GEM_USERPTR_REGISTER (1 << 3) - -struct drm_radeon_gem_userptr { - __u64 addr; - __u64 size; - __u32 flags; - __u32 handle; -}; - -#define RADEON_TILING_MACRO 0x1 -#define RADEON_TILING_MICRO 0x2 -#define RADEON_TILING_SWAP_16BIT 0x4 -#define RADEON_TILING_R600_NO_SCANOUT RADEON_TILING_SWAP_16BIT -#define RADEON_TILING_SWAP_32BIT 0x8 -/* this object requires a surface when mapped - i.e. front buffer */ -#define RADEON_TILING_SURFACE 0x10 -#define RADEON_TILING_MICRO_SQUARE 0x20 -#define RADEON_TILING_EG_BANKW_SHIFT 8 -#define RADEON_TILING_EG_BANKW_MASK 0xf -#define RADEON_TILING_EG_BANKH_SHIFT 12 -#define RADEON_TILING_EG_BANKH_MASK 0xf -#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 -#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf -#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 -#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf -#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 -#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf - -struct drm_radeon_gem_set_tiling { - __u32 handle; - __u32 tiling_flags; - __u32 pitch; -}; - -struct drm_radeon_gem_get_tiling { - __u32 handle; - __u32 tiling_flags; - __u32 pitch; -}; - -struct drm_radeon_gem_mmap { - __u32 handle; - __u32 pad; - __u64 offset; - __u64 size; - __u64 addr_ptr; -}; - -struct drm_radeon_gem_set_domain { - __u32 handle; - __u32 read_domains; - __u32 write_domain; -}; - -struct drm_radeon_gem_wait_idle { - __u32 handle; - __u32 pad; -}; - -struct drm_radeon_gem_busy { - __u32 handle; - __u32 domain; -}; - -struct drm_radeon_gem_pread { - /** Handle for the object being read. */ - __u32 handle; - __u32 pad; - /** Offset into the object to read from */ - __u64 offset; - /** Length of data to read */ - __u64 size; - /** Pointer to write the data into. */ - /* void *, but pointers are not 32/64 compatible */ - __u64 data_ptr; -}; - -struct drm_radeon_gem_pwrite { - /** Handle for the object being written to. */ - __u32 handle; - __u32 pad; - /** Offset into the object to write to */ - __u64 offset; - /** Length of data to write */ - __u64 size; - /** Pointer to read the data from. */ - /* void *, but pointers are not 32/64 compatible */ - __u64 data_ptr; -}; - -/* Sets or returns a value associated with a buffer. */ -struct drm_radeon_gem_op { - __u32 handle; /* buffer */ - __u32 op; /* RADEON_GEM_OP_* */ - __u64 value; /* input or return value */ -}; - -#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 -#define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 - -#define RADEON_VA_MAP 1 -#define RADEON_VA_UNMAP 2 - -#define RADEON_VA_RESULT_OK 0 -#define RADEON_VA_RESULT_ERROR 1 -#define RADEON_VA_RESULT_VA_EXIST 2 - -#define RADEON_VM_PAGE_VALID (1 << 0) -#define RADEON_VM_PAGE_READABLE (1 << 1) -#define RADEON_VM_PAGE_WRITEABLE (1 << 2) -#define RADEON_VM_PAGE_SYSTEM (1 << 3) -#define RADEON_VM_PAGE_SNOOPED (1 << 4) - -struct drm_radeon_gem_va { - __u32 handle; - __u32 operation; - __u32 vm_id; - __u32 flags; - __u64 offset; -}; - -#define RADEON_CHUNK_ID_RELOCS 0x01 -#define RADEON_CHUNK_ID_IB 0x02 -#define RADEON_CHUNK_ID_FLAGS 0x03 -#define RADEON_CHUNK_ID_CONST_IB 0x04 - -/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ -#define RADEON_CS_KEEP_TILING_FLAGS 0x01 -#define RADEON_CS_USE_VM 0x02 -#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */ -/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ -#define RADEON_CS_RING_GFX 0 -#define RADEON_CS_RING_COMPUTE 1 -#define RADEON_CS_RING_DMA 2 -#define RADEON_CS_RING_UVD 3 -#define RADEON_CS_RING_VCE 4 -/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ -/* 0 = normal, + = higher priority, - = lower priority */ - -struct drm_radeon_cs_chunk { - __u32 chunk_id; - __u32 length_dw; - __u64 chunk_data; -}; - -/* drm_radeon_cs_reloc.flags */ -#define RADEON_RELOC_PRIO_MASK (0xf << 0) - -struct drm_radeon_cs_reloc { - __u32 handle; - __u32 read_domains; - __u32 write_domain; - __u32 flags; -}; - -struct drm_radeon_cs { - __u32 num_chunks; - __u32 cs_id; - /* this points to __u64 * which point to cs chunks */ - __u64 chunks; - /* updates to the limits after this CS ioctl */ - __u64 gart_limit; - __u64 vram_limit; -}; - -#define RADEON_INFO_DEVICE_ID 0x00 -#define RADEON_INFO_NUM_GB_PIPES 0x01 -#define RADEON_INFO_NUM_Z_PIPES 0x02 -#define RADEON_INFO_ACCEL_WORKING 0x03 -#define RADEON_INFO_CRTC_FROM_ID 0x04 -#define RADEON_INFO_ACCEL_WORKING2 0x05 -#define RADEON_INFO_TILING_CONFIG 0x06 -#define RADEON_INFO_WANT_HYPERZ 0x07 -#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ -#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ -#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ -#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ -#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ -#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ -/* virtual address start, va < start are reserved by the kernel */ -#define RADEON_INFO_VA_START 0x0e -/* maximum size of ib using the virtual memory cs */ -#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f -/* max pipes - needed for compute shaders */ -#define RADEON_INFO_MAX_PIPES 0x10 -/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ -#define RADEON_INFO_TIMESTAMP 0x11 -/* max shader engines (SE) - needed for geometry shaders, etc. */ -#define RADEON_INFO_MAX_SE 0x12 -/* max SH per SE */ -#define RADEON_INFO_MAX_SH_PER_SE 0x13 -/* fast fb access is enabled */ -#define RADEON_INFO_FASTFB_WORKING 0x14 -/* query if a RADEON_CS_RING_* submission is supported */ -#define RADEON_INFO_RING_WORKING 0x15 -/* SI tile mode array */ -#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 -/* query if CP DMA is supported on the compute ring */ -#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 -/* CIK macrotile mode array */ -#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 -/* query the number of render backends */ -#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 -/* max engine clock - needed for OpenCL */ -#define RADEON_INFO_MAX_SCLK 0x1a -/* version of VCE firmware */ -#define RADEON_INFO_VCE_FW_VERSION 0x1b -/* version of VCE feedback */ -#define RADEON_INFO_VCE_FB_VERSION 0x1c -#define RADEON_INFO_NUM_BYTES_MOVED 0x1d -#define RADEON_INFO_VRAM_USAGE 0x1e -#define RADEON_INFO_GTT_USAGE 0x1f -#define RADEON_INFO_ACTIVE_CU_COUNT 0x20 -#define RADEON_INFO_CURRENT_GPU_TEMP 0x21 -#define RADEON_INFO_CURRENT_GPU_SCLK 0x22 -#define RADEON_INFO_CURRENT_GPU_MCLK 0x23 -#define RADEON_INFO_READ_REG 0x24 -#define RADEON_INFO_VA_UNMAP_WORKING 0x25 -#define RADEON_INFO_GPU_RESET_COUNTER 0x26 - -struct drm_radeon_info { - __u32 request; - __u32 pad; - __u64 value; -}; - -/* Those correspond to the tile index to use, this is to explicitly state - * the API that is implicitly defined by the tile mode array. - */ -#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 -#define SI_TILE_MODE_COLOR_1D 13 -#define SI_TILE_MODE_COLOR_1D_SCANOUT 9 -#define SI_TILE_MODE_COLOR_2D_8BPP 14 -#define SI_TILE_MODE_COLOR_2D_16BPP 15 -#define SI_TILE_MODE_COLOR_2D_32BPP 16 -#define SI_TILE_MODE_COLOR_2D_64BPP 17 -#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 -#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 -#define SI_TILE_MODE_DEPTH_STENCIL_1D 4 -#define SI_TILE_MODE_DEPTH_STENCIL_2D 0 -#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 -#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 -#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 - -#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/savage_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/savage_drm.h deleted file mode 100755 index 1a91234..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/savage_drm.h +++ /dev/null @@ -1,220 +0,0 @@ -/* savage_drm.h -- Public header for the savage driver - * - * Copyright 2004 Felix Kuehling - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF - * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __SAVAGE_DRM_H__ -#define __SAVAGE_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#ifndef __SAVAGE_SAREA_DEFINES__ -#define __SAVAGE_SAREA_DEFINES__ - -/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 - * regions, subject to a minimum region size of (1<<16) == 64k. - * - * Clients may subdivide regions internally, but when sharing between - * clients, the region size is the minimum granularity. - */ - -#define SAVAGE_CARD_HEAP 0 -#define SAVAGE_AGP_HEAP 1 -#define SAVAGE_NR_TEX_HEAPS 2 -#define SAVAGE_NR_TEX_REGIONS 16 -#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 - -#endif /* __SAVAGE_SAREA_DEFINES__ */ - -typedef struct _drm_savage_sarea { - /* LRU lists for texture memory in agp space and on the card. - */ - struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + - 1]; - unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; - - /* Mechanism to validate card state. - */ - int ctxOwner; -} drm_savage_sarea_t, *drm_savage_sarea_ptr; - -/* Savage-specific ioctls - */ -#define DRM_SAVAGE_BCI_INIT 0x00 -#define DRM_SAVAGE_BCI_CMDBUF 0x01 -#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 -#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 - -#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) -#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) -#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) -#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) - -#define SAVAGE_DMA_PCI 1 -#define SAVAGE_DMA_AGP 3 -typedef struct drm_savage_init { - enum { - SAVAGE_INIT_BCI = 1, - SAVAGE_CLEANUP_BCI = 2 - } func; - unsigned int sarea_priv_offset; - - /* some parameters */ - unsigned int cob_size; - unsigned int bci_threshold_lo, bci_threshold_hi; - unsigned int dma_type; - - /* frame buffer layout */ - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - /* local textures */ - unsigned int texture_offset; - unsigned int texture_size; - - /* physical locations of non-permanent maps */ - unsigned long status_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; - unsigned long cmd_dma_offset; -} drm_savage_init_t; - -typedef union drm_savage_cmd_header drm_savage_cmd_header_t; -typedef struct drm_savage_cmdbuf { - /* command buffer in client's address space */ - drm_savage_cmd_header_t *cmd_addr; - unsigned int size; /* size of the command buffer in 64bit units */ - - unsigned int dma_idx; /* DMA buffer index to use */ - int discard; /* discard DMA buffer when done */ - /* vertex buffer in client's address space */ - unsigned int *vb_addr; - unsigned int vb_size; /* size of client vertex buffer in bytes */ - unsigned int vb_stride; /* stride of vertices in 32bit words */ - /* boxes in client's address space */ - struct drm_clip_rect *box_addr; - unsigned int nbox; /* number of clipping boxes */ -} drm_savage_cmdbuf_t; - -#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ -#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ -#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ -typedef struct drm_savage_event { - unsigned int count; - unsigned int flags; -} drm_savage_event_emit_t, drm_savage_event_wait_t; - -/* Commands for the cmdbuf ioctl - */ -#define SAVAGE_CMD_STATE 0 /* a range of state registers */ -#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ -#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ -#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ -#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ -#define SAVAGE_CMD_CLEAR 5 /* clear buffers */ -#define SAVAGE_CMD_SWAP 6 /* swap buffers */ - -/* Primitive types -*/ -#define SAVAGE_PRIM_TRILIST 0 /* triangle list */ -#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ -#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ -#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat - * shading on s3d */ - -/* Skip flags (vertex format) - */ -#define SAVAGE_SKIP_Z 0x01 -#define SAVAGE_SKIP_W 0x02 -#define SAVAGE_SKIP_C0 0x04 -#define SAVAGE_SKIP_C1 0x08 -#define SAVAGE_SKIP_S0 0x10 -#define SAVAGE_SKIP_T0 0x20 -#define SAVAGE_SKIP_ST0 0x30 -#define SAVAGE_SKIP_S1 0x40 -#define SAVAGE_SKIP_T1 0x80 -#define SAVAGE_SKIP_ST1 0xc0 -#define SAVAGE_SKIP_ALL_S3D 0x3f -#define SAVAGE_SKIP_ALL_S4 0xff - -/* Buffer names for clear command - */ -#define SAVAGE_FRONT 0x1 -#define SAVAGE_BACK 0x2 -#define SAVAGE_DEPTH 0x4 - -/* 64-bit command header - */ -union drm_savage_cmd_header { - struct { - unsigned char cmd; /* command */ - unsigned char pad0; - unsigned short pad1; - unsigned short pad2; - unsigned short pad3; - } cmd; /* generic */ - struct { - unsigned char cmd; - unsigned char global; /* need idle engine? */ - unsigned short count; /* number of consecutive registers */ - unsigned short start; /* first register */ - unsigned short pad3; - } state; /* SAVAGE_CMD_STATE */ - struct { - unsigned char cmd; - unsigned char prim; /* primitive type */ - unsigned short skip; /* vertex format (skip flags) */ - unsigned short count; /* number of vertices */ - unsigned short start; /* first vertex in DMA/vertex buffer */ - } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ - struct { - unsigned char cmd; - unsigned char prim; - unsigned short skip; - unsigned short count; /* number of indices that follow */ - unsigned short pad3; - } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ - struct { - unsigned char cmd; - unsigned char pad0; - unsigned short pad1; - unsigned int flags; - } clear0; /* SAVAGE_CMD_CLEAR */ - struct { - unsigned int mask; - unsigned int value; - } clear1; /* SAVAGE_CMD_CLEAR data */ -}; - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/sis_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/sis_drm.h deleted file mode 100755 index 8e51bb9..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/sis_drm.h +++ /dev/null @@ -1,77 +0,0 @@ -/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */ -/* - * Copyright 2005 Eric Anholt - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - */ - -#ifndef __SIS_DRM_H__ -#define __SIS_DRM_H__ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* SiS specific ioctls */ -#define NOT_USED_0_3 -#define DRM_SIS_FB_ALLOC 0x04 -#define DRM_SIS_FB_FREE 0x05 -#define NOT_USED_6_12 -#define DRM_SIS_AGP_INIT 0x13 -#define DRM_SIS_AGP_ALLOC 0x14 -#define DRM_SIS_AGP_FREE 0x15 -#define DRM_SIS_FB_INIT 0x16 - -#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t) -#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t) -#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t) -#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t) -#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t) -#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t) -/* -#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) -#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) -#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) -*/ - -typedef struct { - int context; - unsigned int offset; - unsigned int size; - unsigned long free; -} drm_sis_mem_t; - -typedef struct { - unsigned int offset, size; -} drm_sis_agp_t; - -typedef struct { - unsigned int offset, size; -} drm_sis_fb_t; - -#if defined(__cplusplus) -} -#endif - -#endif /* __SIS_DRM_H__ */ diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/tegra_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/tegra_drm.h deleted file mode 100755 index 6c07919..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/tegra_drm.h +++ /dev/null @@ -1,681 +0,0 @@ -/* - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _TEGRA_DRM_H_ -#define _TEGRA_DRM_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) -#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) - -/** - * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL - */ -struct drm_tegra_gem_create { - /** - * @size: - * - * The size, in bytes, of the buffer object to be created. - */ - __u64 size; - - /** - * @flags: - * - * A bitmask of flags that influence the creation of GEM objects: - * - * DRM_TEGRA_GEM_CREATE_TILED - * Use the 16x16 tiling format for this buffer. - * - * DRM_TEGRA_GEM_CREATE_BOTTOM_UP - * The buffer has a bottom-up layout. - */ - __u32 flags; - - /** - * @handle: - * - * The handle of the created GEM object. Set by the kernel upon - * successful completion of the IOCTL. - */ - __u32 handle; -}; - -/** - * struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL - */ -struct drm_tegra_gem_mmap { - /** - * @handle: - * - * Handle of the GEM object to obtain an mmap offset for. - */ - __u32 handle; - - /** - * @pad: - * - * Structure padding that may be used in the future. Must be 0. - */ - __u32 pad; - - /** - * @offset: - * - * The mmap offset for the given GEM object. Set by the kernel upon - * successful completion of the IOCTL. - */ - __u64 offset; -}; - -/** - * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL - */ -struct drm_tegra_syncpt_read { - /** - * @id: - * - * ID of the syncpoint to read the current value from. - */ - __u32 id; - - /** - * @value: - * - * The current syncpoint value. Set by the kernel upon successful - * completion of the IOCTL. - */ - __u32 value; -}; - -/** - * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL - */ -struct drm_tegra_syncpt_incr { - /** - * @id: - * - * ID of the syncpoint to increment. - */ - __u32 id; - - /** - * @pad: - * - * Structure padding that may be used in the future. Must be 0. - */ - __u32 pad; -}; - -/** - * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL - */ -struct drm_tegra_syncpt_wait { - /** - * @id: - * - * ID of the syncpoint to wait on. - */ - __u32 id; - - /** - * @thresh: - * - * Threshold value for which to wait. - */ - __u32 thresh; - - /** - * @timeout: - * - * Timeout, in milliseconds, to wait. - */ - __u32 timeout; - - /** - * @value: - * - * The new syncpoint value after the wait. Set by the kernel upon - * successful completion of the IOCTL. - */ - __u32 value; -}; - -#define DRM_TEGRA_NO_TIMEOUT (0xffffffff) - -/** - * struct drm_tegra_open_channel - parameters for the open channel IOCTL - */ -struct drm_tegra_open_channel { - /** - * @client: - * - * The client ID for this channel. - */ - __u32 client; - - /** - * @pad: - * - * Structure padding that may be used in the future. Must be 0. - */ - __u32 pad; - - /** - * @context: - * - * The application context of this channel. Set by the kernel upon - * successful completion of the IOCTL. This context needs to be passed - * to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs. - */ - __u64 context; -}; - -/** - * struct drm_tegra_close_channel - parameters for the close channel IOCTL - */ -struct drm_tegra_close_channel { - /** - * @context: - * - * The application context of this channel. This is obtained from the - * DRM_TEGRA_OPEN_CHANNEL IOCTL. - */ - __u64 context; -}; - -/** - * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL - */ -struct drm_tegra_get_syncpt { - /** - * @context: - * - * The application context identifying the channel for which to obtain - * the syncpoint ID. - */ - __u64 context; - - /** - * @index: - * - * Index of the client syncpoint for which to obtain the ID. - */ - __u32 index; - - /** - * @id: - * - * The ID of the given syncpoint. Set by the kernel upon successful - * completion of the IOCTL. - */ - __u32 id; -}; - -/** - * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL - */ -struct drm_tegra_get_syncpt_base { - /** - * @context: - * - * The application context identifying for which channel to obtain the - * wait base. - */ - __u64 context; - - /** - * @syncpt: - * - * ID of the syncpoint for which to obtain the wait base. - */ - __u32 syncpt; - - /** - * @id: - * - * The ID of the wait base corresponding to the client syncpoint. Set - * by the kernel upon successful completion of the IOCTL. - */ - __u32 id; -}; - -/** - * struct drm_tegra_syncpt - syncpoint increment operation - */ -struct drm_tegra_syncpt { - /** - * @id: - * - * ID of the syncpoint to operate on. - */ - __u32 id; - - /** - * @incrs: - * - * Number of increments to perform for the syncpoint. - */ - __u32 incrs; -}; - -/** - * struct drm_tegra_cmdbuf - structure describing a command buffer - */ -struct drm_tegra_cmdbuf { - /** - * @handle: - * - * Handle to a GEM object containing the command buffer. - */ - __u32 handle; - - /** - * @offset: - * - * Offset, in bytes, into the GEM object identified by @handle at - * which the command buffer starts. - */ - __u32 offset; - - /** - * @words: - * - * Number of 32-bit words in this command buffer. - */ - __u32 words; - - /** - * @pad: - * - * Structure padding that may be used in the future. Must be 0. - */ - __u32 pad; -}; - -/** - * struct drm_tegra_reloc - GEM object relocation structure - */ -struct drm_tegra_reloc { - struct { - /** - * @cmdbuf.handle: - * - * Handle to the GEM object containing the command buffer for - * which to perform this GEM object relocation. - */ - __u32 handle; - - /** - * @cmdbuf.offset: - * - * Offset, in bytes, into the command buffer at which to - * insert the relocated address. - */ - __u32 offset; - } cmdbuf; - struct { - /** - * @target.handle: - * - * Handle to the GEM object to be relocated. - */ - __u32 handle; - - /** - * @target.offset: - * - * Offset, in bytes, into the target GEM object at which the - * relocated data starts. - */ - __u32 offset; - } target; - - /** - * @shift: - * - * The number of bits by which to shift relocated addresses. - */ - __u32 shift; - - /** - * @pad: - * - * Structure padding that may be used in the future. Must be 0. - */ - __u32 pad; -}; - -/** - * struct drm_tegra_waitchk - wait check structure - */ -struct drm_tegra_waitchk { - /** - * @handle: - * - * Handle to the GEM object containing a command stream on which to - * perform the wait check. - */ - __u32 handle; - - /** - * @offset: - * - * Offset, in bytes, of the location in the command stream to perform - * the wait check on. - */ - __u32 offset; - - /** - * @syncpt: - * - * ID of the syncpoint to wait check. - */ - __u32 syncpt; - - /** - * @thresh: - * - * Threshold value for which to check. - */ - __u32 thresh; -}; - -/** - * struct drm_tegra_submit - job submission structure - */ -struct drm_tegra_submit { - /** - * @context: - * - * The application context identifying the channel to use for the - * execution of this job. - */ - __u64 context; - - /** - * @num_syncpts: - * - * The number of syncpoints operated on by this job. This defines the - * length of the array pointed to by @syncpts. - */ - __u32 num_syncpts; - - /** - * @num_cmdbufs: - * - * The number of command buffers to execute as part of this job. This - * defines the length of the array pointed to by @cmdbufs. - */ - __u32 num_cmdbufs; - - /** - * @num_relocs: - * - * The number of relocations to perform before executing this job. - * This defines the length of the array pointed to by @relocs. - */ - __u32 num_relocs; - - /** - * @num_waitchks: - * - * The number of wait checks to perform as part of this job. This - * defines the length of the array pointed to by @waitchks. - */ - __u32 num_waitchks; - - /** - * @waitchk_mask: - * - * Bitmask of valid wait checks. - */ - __u32 waitchk_mask; - - /** - * @timeout: - * - * Timeout, in milliseconds, before this job is cancelled. - */ - __u32 timeout; - - /** - * @syncpts: - * - * A pointer to an array of &struct drm_tegra_syncpt structures that - * specify the syncpoint operations performed as part of this job. - * The number of elements in the array must be equal to the value - * given by @num_syncpts. - */ - __u64 syncpts; - - /** - * @cmdbufs: - * - * A pointer to an array of &struct drm_tegra_cmdbuf structures that - * define the command buffers to execute as part of this job. The - * number of elements in the array must be equal to the value given - * by @num_syncpts. - */ - __u64 cmdbufs; - - /** - * @relocs: - * - * A pointer to an array of &struct drm_tegra_reloc structures that - * specify the relocations that need to be performed before executing - * this job. The number of elements in the array must be equal to the - * value given by @num_relocs. - */ - __u64 relocs; - - /** - * @waitchks: - * - * A pointer to an array of &struct drm_tegra_waitchk structures that - * specify the wait checks to be performed while executing this job. - * The number of elements in the array must be equal to the value - * given by @num_waitchks. - */ - __u64 waitchks; - - /** - * @fence: - * - * The threshold of the syncpoint associated with this job after it - * has been completed. Set by the kernel upon successful completion of - * the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to - * wait for this job to be finished. - */ - __u32 fence; - - /** - * @reserved: - * - * This field is reserved for future use. Must be 0. - */ - __u32 reserved[5]; -}; - -#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 -#define DRM_TEGRA_GEM_TILING_MODE_TILED 1 -#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 - -/** - * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL - */ -struct drm_tegra_gem_set_tiling { - /** - * @handle: - * - * Handle to the GEM object for which to set the tiling parameters. - */ - __u32 handle; - - /** - * @mode: - * - * The tiling mode to set. Must be one of: - * - * DRM_TEGRA_GEM_TILING_MODE_PITCH - * pitch linear format - * - * DRM_TEGRA_GEM_TILING_MODE_TILED - * 16x16 tiling format - * - * DRM_TEGRA_GEM_TILING_MODE_BLOCK - * 16Bx2 tiling format - */ - __u32 mode; - - /** - * @value: - * - * The value to set for the tiling mode parameter. - */ - __u32 value; - - /** - * @pad: - * - * Structure padding that may be used in the future. Must be 0. - */ - __u32 pad; -}; - -/** - * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL - */ -struct drm_tegra_gem_get_tiling { - /** - * @handle: - * - * Handle to the GEM object for which to query the tiling parameters. - */ - __u32 handle; - - /** - * @mode: - * - * The tiling mode currently associated with the GEM object. Set by - * the kernel upon successful completion of the IOCTL. - */ - __u32 mode; - - /** - * @value: - * - * The tiling mode parameter currently associated with the GEM object. - * Set by the kernel upon successful completion of the IOCTL. - */ - __u32 value; - - /** - * @pad: - * - * Structure padding that may be used in the future. Must be 0. - */ - __u32 pad; -}; - -#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) -#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) - -/** - * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL - */ -struct drm_tegra_gem_set_flags { - /** - * @handle: - * - * Handle to the GEM object for which to set the flags. - */ - __u32 handle; - - /** - * @flags: - * - * The flags to set for the GEM object. - */ - __u32 flags; -}; - -/** - * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL - */ -struct drm_tegra_gem_get_flags { - /** - * @handle: - * - * Handle to the GEM object for which to query the flags. - */ - __u32 handle; - - /** - * @flags: - * - * The flags currently associated with the GEM object. Set by the - * kernel upon successful completion of the IOCTL. - */ - __u32 flags; -}; - -#define DRM_TEGRA_GEM_CREATE 0x00 -#define DRM_TEGRA_GEM_MMAP 0x01 -#define DRM_TEGRA_SYNCPT_READ 0x02 -#define DRM_TEGRA_SYNCPT_INCR 0x03 -#define DRM_TEGRA_SYNCPT_WAIT 0x04 -#define DRM_TEGRA_OPEN_CHANNEL 0x05 -#define DRM_TEGRA_CLOSE_CHANNEL 0x06 -#define DRM_TEGRA_GET_SYNCPT 0x07 -#define DRM_TEGRA_SUBMIT 0x08 -#define DRM_TEGRA_GET_SYNCPT_BASE 0x09 -#define DRM_TEGRA_GEM_SET_TILING 0x0a -#define DRM_TEGRA_GEM_GET_TILING 0x0b -#define DRM_TEGRA_GEM_SET_FLAGS 0x0c -#define DRM_TEGRA_GEM_GET_FLAGS 0x0d - -#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) -#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) -#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) -#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) -#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) -#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) -#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel) -#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) -#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) -#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) -#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) -#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) -#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) -#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/vc4_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/vc4_drm.h deleted file mode 100755 index 31f50de..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/vc4_drm.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * Copyright © 2014-2015 Broadcom - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef _VC4_DRM_H_ -#define _VC4_DRM_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define DRM_VC4_SUBMIT_CL 0x00 -#define DRM_VC4_WAIT_SEQNO 0x01 -#define DRM_VC4_WAIT_BO 0x02 -#define DRM_VC4_CREATE_BO 0x03 -#define DRM_VC4_MMAP_BO 0x04 -#define DRM_VC4_CREATE_SHADER_BO 0x05 -#define DRM_VC4_GET_HANG_STATE 0x06 -#define DRM_VC4_GET_PARAM 0x07 -#define DRM_VC4_SET_TILING 0x08 -#define DRM_VC4_GET_TILING 0x09 -#define DRM_VC4_LABEL_BO 0x0a -#define DRM_VC4_GEM_MADVISE 0x0b -#define DRM_VC4_PERFMON_CREATE 0x0c -#define DRM_VC4_PERFMON_DESTROY 0x0d -#define DRM_VC4_PERFMON_GET_VALUES 0x0e - -#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) -#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) -#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) -#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) -#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) -#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) -#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) -#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) -#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) -#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) -#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) -#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) -#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) -#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) -#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) - -struct drm_vc4_submit_rcl_surface { - __u32 hindex; /* Handle index, or ~0 if not present. */ - __u32 offset; /* Offset to start of buffer. */ - /* - * Bits for either render config (color_write) or load/store packet. - * Bits should all be 0 for MSAA load/stores. - */ - __u16 bits; - -#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) - __u16 flags; -}; - -/** - * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D - * engine. - * - * Drivers typically use GPU BOs to store batchbuffers / command lists and - * their associated state. However, because the VC4 lacks an MMU, we have to - * do validation of memory accesses by the GPU commands. If we were to store - * our commands in BOs, we'd need to do uncached readback from them to do the - * validation process, which is too expensive. Instead, userspace accumulates - * commands and associated state in plain memory, then the kernel copies the - * data to its own address space, and then validates and stores it in a GPU - * BO. - */ -struct drm_vc4_submit_cl { - /* Pointer to the binner command list. - * - * This is the first set of commands executed, which runs the - * coordinate shader to determine where primitives land on the screen, - * then writes out the state updates and draw calls necessary per tile - * to the tile allocation BO. - */ - __u64 bin_cl; - - /* Pointer to the shader records. - * - * Shader records are the structures read by the hardware that contain - * pointers to uniforms, shaders, and vertex attributes. The - * reference to the shader record has enough information to determine - * how many pointers are necessary (fixed number for shaders/uniforms, - * and an attribute count), so those BO indices into bo_handles are - * just stored as __u32s before each shader record passed in. - */ - __u64 shader_rec; - - /* Pointer to uniform data and texture handles for the textures - * referenced by the shader. - * - * For each shader state record, there is a set of uniform data in the - * order referenced by the record (FS, VS, then CS). Each set of - * uniform data has a __u32 index into bo_handles per texture - * sample operation, in the order the QPU_W_TMUn_S writes appear in - * the program. Following the texture BO handle indices is the actual - * uniform data. - * - * The individual uniform state blocks don't have sizes passed in, - * because the kernel has to determine the sizes anyway during shader - * code validation. - */ - __u64 uniforms; - __u64 bo_handles; - - /* Size in bytes of the binner command list. */ - __u32 bin_cl_size; - /* Size in bytes of the set of shader records. */ - __u32 shader_rec_size; - /* Number of shader records. - * - * This could just be computed from the contents of shader_records and - * the address bits of references to them from the bin CL, but it - * keeps the kernel from having to resize some allocations it makes. - */ - __u32 shader_rec_count; - /* Size in bytes of the uniform state. */ - __u32 uniforms_size; - - /* Number of BO handles passed in (size is that times 4). */ - __u32 bo_handle_count; - - /* RCL setup: */ - __u16 width; - __u16 height; - __u8 min_x_tile; - __u8 min_y_tile; - __u8 max_x_tile; - __u8 max_y_tile; - struct drm_vc4_submit_rcl_surface color_read; - struct drm_vc4_submit_rcl_surface color_write; - struct drm_vc4_submit_rcl_surface zs_read; - struct drm_vc4_submit_rcl_surface zs_write; - struct drm_vc4_submit_rcl_surface msaa_color_write; - struct drm_vc4_submit_rcl_surface msaa_zs_write; - __u32 clear_color[2]; - __u32 clear_z; - __u8 clear_s; - - __u32 pad:24; - -#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) -/* By default, the kernel gets to choose the order that the tiles are - * rendered in. If this is set, then the tiles will be rendered in a - * raster order, with the right-to-left vs left-to-right and - * top-to-bottom vs bottom-to-top dictated by - * VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping - * blits to be implemented using the 3D engine. - */ -#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) -#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) -#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) - __u32 flags; - - /* Returned value of the seqno of this render job (for the - * wait ioctl). - */ - __u64 seqno; - - /* ID of the perfmon to attach to this job. 0 means no perfmon. */ - __u32 perfmonid; - - /* Syncobj handle to wait on. If set, processing of this render job - * will not start until the syncobj is signaled. 0 means ignore. - */ - __u32 in_sync; - - /* Syncobj handle to export fence to. If set, the fence in the syncobj - * will be replaced with a fence that signals upon completion of this - * render job. 0 means ignore. - */ - __u32 out_sync; - - __u32 pad2; -}; - -/** - * struct drm_vc4_wait_seqno - ioctl argument for waiting for - * DRM_VC4_SUBMIT_CL completion using its returned seqno. - * - * timeout_ns is the timeout in nanoseconds, where "0" means "don't - * block, just return the status." - */ -struct drm_vc4_wait_seqno { - __u64 seqno; - __u64 timeout_ns; -}; - -/** - * struct drm_vc4_wait_bo - ioctl argument for waiting for - * completion of the last DRM_VC4_SUBMIT_CL on a BO. - * - * This is useful for cases where multiple processes might be - * rendering to a BO and you want to wait for all rendering to be - * completed. - */ -struct drm_vc4_wait_bo { - __u32 handle; - __u32 pad; - __u64 timeout_ns; -}; - -/** - * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. - * - * There are currently no values for the flags argument, but it may be - * used in a future extension. - */ -struct drm_vc4_create_bo { - __u32 size; - __u32 flags; - /** Returned GEM handle for the BO. */ - __u32 handle; - __u32 pad; -}; - -/** - * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. - * - * This doesn't actually perform an mmap. Instead, it returns the - * offset you need to use in an mmap on the DRM device node. This - * means that tools like valgrind end up knowing about the mapped - * memory. - * - * There are currently no values for the flags argument, but it may be - * used in a future extension. - */ -struct drm_vc4_mmap_bo { - /** Handle for the object being mapped. */ - __u32 handle; - __u32 flags; - /** offset into the drm node to use for subsequent mmap call. */ - __u64 offset; -}; - -/** - * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 - * shader BOs. - * - * Since allowing a shader to be overwritten while it's also being - * executed from would allow privlege escalation, shaders must be - * created using this ioctl, and they can't be mmapped later. - */ -struct drm_vc4_create_shader_bo { - /* Size of the data argument. */ - __u32 size; - /* Flags, currently must be 0. */ - __u32 flags; - - /* Pointer to the data. */ - __u64 data; - - /** Returned GEM handle for the BO. */ - __u32 handle; - /* Pad, must be 0. */ - __u32 pad; -}; - -struct drm_vc4_get_hang_state_bo { - __u32 handle; - __u32 paddr; - __u32 size; - __u32 pad; -}; - -/** - * struct drm_vc4_hang_state - ioctl argument for collecting state - * from a GPU hang for analysis. -*/ -struct drm_vc4_get_hang_state { - /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ - __u64 bo; - /** - * On input, the size of the bo array. Output is the number - * of bos to be returned. - */ - __u32 bo_count; - - __u32 start_bin, start_render; - - __u32 ct0ca, ct0ea; - __u32 ct1ca, ct1ea; - __u32 ct0cs, ct1cs; - __u32 ct0ra0, ct1ra0; - - __u32 bpca, bpcs; - __u32 bpoa, bpos; - - __u32 vpmbase; - - __u32 dbge; - __u32 fdbgo; - __u32 fdbgb; - __u32 fdbgr; - __u32 fdbgs; - __u32 errstat; - - /* Pad that we may save more registers into in the future. */ - __u32 pad[16]; -}; - -#define DRM_VC4_PARAM_V3D_IDENT0 0 -#define DRM_VC4_PARAM_V3D_IDENT1 1 -#define DRM_VC4_PARAM_V3D_IDENT2 2 -#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 -#define DRM_VC4_PARAM_SUPPORTS_ETC1 4 -#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 -#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 -#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 -#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8 - -struct drm_vc4_get_param { - __u32 param; - __u32 pad; - __u64 value; -}; - -struct drm_vc4_get_tiling { - __u32 handle; - __u32 flags; - __u64 modifier; -}; - -struct drm_vc4_set_tiling { - __u32 handle; - __u32 flags; - __u64 modifier; -}; - -/** - * struct drm_vc4_label_bo - Attach a name to a BO for debug purposes. - */ -struct drm_vc4_label_bo { - __u32 handle; - __u32 len; - __u64 name; -}; - -/* - * States prefixed with '__' are internal states and cannot be passed to the - * DRM_IOCTL_VC4_GEM_MADVISE ioctl. - */ -#define VC4_MADV_WILLNEED 0 -#define VC4_MADV_DONTNEED 1 -#define __VC4_MADV_PURGED 2 -#define __VC4_MADV_NOTSUPP 3 - -struct drm_vc4_gem_madvise { - __u32 handle; - __u32 madv; - __u32 retained; - __u32 pad; -}; - -enum { - VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER, - VC4_PERFCNT_FEP_VALID_PRIMS_RENDER, - VC4_PERFCNT_FEP_CLIPPED_QUADS, - VC4_PERFCNT_FEP_VALID_QUADS, - VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL, - VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL, - VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL, - VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE, - VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE, - VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF, - VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT, - VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING, - VC4_PERFCNT_PSE_PRIMS_REVERSED, - VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES, - VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING, - VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING, - VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST, - VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS, - VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD, - VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS, - VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT, - VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS, - VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT, - VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS, - VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED, - VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS, - VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED, - VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED, - VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT, - VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS, - VC4_PERFCNT_NUM_EVENTS, -}; - -#define DRM_VC4_MAX_PERF_COUNTERS 16 - -struct drm_vc4_perfmon_create { - __u32 id; - __u32 ncounters; - __u8 events[DRM_VC4_MAX_PERF_COUNTERS]; -}; - -struct drm_vc4_perfmon_destroy { - __u32 id; -}; - -/* - * Returns the values of the performance counters tracked by this - * perfmon (as an array of ncounters u64 values). - * - * No implicit synchronization is performed, so the user has to - * guarantee that any jobs using this perfmon have already been - * completed (probably by blocking on the seqno returned by the - * last exec that used the perfmon). - */ -struct drm_vc4_perfmon_get_values { - __u32 id; - __u64 values_ptr; -}; - -#if defined(__cplusplus) -} -#endif - -#endif /* _VC4_DRM_H_ */ diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/via_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/via_drm.h deleted file mode 100755 index 8b69e81..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/via_drm.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef _VIA_DRM_H_ -#define _VIA_DRM_H_ - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* WARNING: These defines must be the same as what the Xserver uses. - * if you change them, you must change the defines in the Xserver. - */ - -#ifndef _VIA_DEFINES_ -#define _VIA_DEFINES_ - -#include "via_drmclient.h" - -#define VIA_NR_SAREA_CLIPRECTS 8 -#define VIA_NR_XVMC_PORTS 10 -#define VIA_NR_XVMC_LOCKS 5 -#define VIA_MAX_CACHELINE_SIZE 64 -#define XVMCLOCKPTR(saPriv,lockNo) \ - ((__volatile__ struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ - (VIA_MAX_CACHELINE_SIZE - 1)) & \ - ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ - VIA_MAX_CACHELINE_SIZE*(lockNo))) - -/* Each region is a minimum of 64k, and there are at most 64 of them. - */ -#define VIA_NR_TEX_REGIONS 64 -#define VIA_LOG_MIN_TEX_REGION_SIZE 16 -#endif - -#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ -#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ -#define VIA_UPLOAD_CTX 0x4 -#define VIA_UPLOAD_BUFFERS 0x8 -#define VIA_UPLOAD_TEX0 0x10 -#define VIA_UPLOAD_TEX1 0x20 -#define VIA_UPLOAD_CLIPRECTS 0x40 -#define VIA_UPLOAD_ALL 0xff - -/* VIA specific ioctls */ -#define DRM_VIA_ALLOCMEM 0x00 -#define DRM_VIA_FREEMEM 0x01 -#define DRM_VIA_AGP_INIT 0x02 -#define DRM_VIA_FB_INIT 0x03 -#define DRM_VIA_MAP_INIT 0x04 -#define DRM_VIA_DEC_FUTEX 0x05 -#define NOT_USED -#define DRM_VIA_DMA_INIT 0x07 -#define DRM_VIA_CMDBUFFER 0x08 -#define DRM_VIA_FLUSH 0x09 -#define DRM_VIA_PCICMD 0x0a -#define DRM_VIA_CMDBUF_SIZE 0x0b -#define NOT_USED -#define DRM_VIA_WAIT_IRQ 0x0d -#define DRM_VIA_DMA_BLIT 0x0e -#define DRM_VIA_BLIT_SYNC 0x0f - -#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) -#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) -#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) -#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) -#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) -#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) -#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) -#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) -#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH) -#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) -#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \ - drm_via_cmdbuf_size_t) -#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) -#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) -#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) - -/* Indices into buf.Setup where various bits of state are mirrored per - * context and per buffer. These can be fired at the card as a unit, - * or in a piecewise fashion as required. - */ - -#define VIA_TEX_SETUP_SIZE 8 - -/* Flags for clear ioctl - */ -#define VIA_FRONT 0x1 -#define VIA_BACK 0x2 -#define VIA_DEPTH 0x4 -#define VIA_STENCIL 0x8 -#define VIA_MEM_VIDEO 0 /* matches drm constant */ -#define VIA_MEM_AGP 1 /* matches drm constant */ -#define VIA_MEM_SYSTEM 2 -#define VIA_MEM_MIXED 3 -#define VIA_MEM_UNKNOWN 4 - -typedef struct { - __u32 offset; - __u32 size; -} drm_via_agp_t; - -typedef struct { - __u32 offset; - __u32 size; -} drm_via_fb_t; - -typedef struct { - __u32 context; - __u32 type; - __u32 size; - unsigned long index; - unsigned long offset; -} drm_via_mem_t; - -typedef struct _drm_via_init { - enum { - VIA_INIT_MAP = 0x01, - VIA_CLEANUP_MAP = 0x02 - } func; - - unsigned long sarea_priv_offset; - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long agpAddr; -} drm_via_init_t; - -typedef struct _drm_via_futex { - enum { - VIA_FUTEX_WAIT = 0x00, - VIA_FUTEX_WAKE = 0X01 - } func; - __u32 ms; - __u32 lock; - __u32 val; -} drm_via_futex_t; - -typedef struct _drm_via_dma_init { - enum { - VIA_INIT_DMA = 0x01, - VIA_CLEANUP_DMA = 0x02, - VIA_DMA_INITIALIZED = 0x03 - } func; - - unsigned long offset; - unsigned long size; - unsigned long reg_pause_addr; -} drm_via_dma_init_t; - -typedef struct _drm_via_cmdbuffer { - char *buf; - unsigned long size; -} drm_via_cmdbuffer_t; - -/* Warning: If you change the SAREA structure you must change the Xserver - * structure as well */ - -typedef struct _drm_via_tex_region { - unsigned char next, prev; /* indices to form a circular LRU */ - unsigned char inUse; /* owned by a client, or free? */ - int age; /* tracked by clients to update local LRU's */ -} drm_via_tex_region_t; - -typedef struct _drm_via_sarea { - unsigned int dirty; - unsigned int nbox; - struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; - drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; - int texAge; /* last time texture was uploaded */ - int ctxOwner; /* last context to upload state */ - int vertexPrim; - - /* - * Below is for XvMC. - * We want the lock integers alone on, and aligned to, a cache line. - * Therefore this somewhat strange construct. - */ - - char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; - - unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; - unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; - unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */ - - /* Used by the 3d driver only at this point, for pageflipping: - */ - unsigned int pfCurrentOffset; -} drm_via_sarea_t; - -typedef struct _drm_via_cmdbuf_size { - enum { - VIA_CMDBUF_SPACE = 0x01, - VIA_CMDBUF_LAG = 0x02 - } func; - int wait; - __u32 size; -} drm_via_cmdbuf_size_t; - -typedef enum { - VIA_IRQ_ABSOLUTE = 0x0, - VIA_IRQ_RELATIVE = 0x1, - VIA_IRQ_SIGNAL = 0x10000000, - VIA_IRQ_FORCE_SEQUENCE = 0x20000000 -} via_irq_seq_type_t; - -#define VIA_IRQ_FLAGS_MASK 0xF0000000 - -enum drm_via_irqs { - drm_via_irq_hqv0 = 0, - drm_via_irq_hqv1, - drm_via_irq_dma0_dd, - drm_via_irq_dma0_td, - drm_via_irq_dma1_dd, - drm_via_irq_dma1_td, - drm_via_irq_num -}; - -struct drm_via_wait_irq_request { - unsigned irq; - via_irq_seq_type_t type; - __u32 sequence; - __u32 signal; -}; - -typedef union drm_via_irqwait { - struct drm_via_wait_irq_request request; - struct drm_wait_vblank_reply reply; -} drm_via_irqwait_t; - -typedef struct drm_via_blitsync { - __u32 sync_handle; - unsigned engine; -} drm_via_blitsync_t; - -/* - * Below,"flags" is currently unused but will be used for possible future - * extensions like kernel space bounce buffers for bad alignments and - * blit engine busy-wait polling for better latency in the absence of - * interrupts. - */ - -typedef struct drm_via_dmablit { - __u32 num_lines; - __u32 line_length; - - __u32 fb_addr; - __u32 fb_stride; - - unsigned char *mem_addr; - __u32 mem_stride; - - __u32 flags; - int to_fb; - - drm_via_blitsync_t sync; -} drm_via_dmablit_t; - -#if defined(__cplusplus) -} -#endif - -#endif /* _VIA_DRM_H_ */ diff --git a/samples/utils/3rdparty/libdrm/include/libdrm/virtgpu_drm.h b/samples/utils/3rdparty/libdrm/include/libdrm/virtgpu_drm.h deleted file mode 100755 index f06a789..0000000 --- a/samples/utils/3rdparty/libdrm/include/libdrm/virtgpu_drm.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2013 Red Hat - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef VIRTGPU_DRM_H -#define VIRTGPU_DRM_H - -#include "drm.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - * - * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel - * compatibility Keep fields aligned to their size - */ - -#define DRM_VIRTGPU_MAP 0x01 -#define DRM_VIRTGPU_EXECBUFFER 0x02 -#define DRM_VIRTGPU_GETPARAM 0x03 -#define DRM_VIRTGPU_RESOURCE_CREATE 0x04 -#define DRM_VIRTGPU_RESOURCE_INFO 0x05 -#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 -#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 -#define DRM_VIRTGPU_WAIT 0x08 -#define DRM_VIRTGPU_GET_CAPS 0x09 - -#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 -#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 -#define VIRTGPU_EXECBUF_FLAGS (\ - VIRTGPU_EXECBUF_FENCE_FD_IN |\ - VIRTGPU_EXECBUF_FENCE_FD_OUT |\ - 0) - -struct drm_virtgpu_map { - __u64 offset; /* use for mmap system call */ - __u32 handle; - __u32 pad; -}; - -struct drm_virtgpu_execbuffer { - __u32 flags; - __u32 size; - __u64 command; /* void* */ - __u64 bo_handles; - __u32 num_bo_handles; - __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ -}; - -#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ -#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ - -struct drm_virtgpu_getparam { - __u64 param; - __u64 value; -}; - -/* NO_BO flags? NO resource flag? */ -/* resource flag for y_0_top */ -struct drm_virtgpu_resource_create { - __u32 target; - __u32 format; - __u32 bind; - __u32 width; - __u32 height; - __u32 depth; - __u32 array_size; - __u32 last_level; - __u32 nr_samples; - __u32 flags; - __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ - __u32 res_handle; /* returned by kernel */ - __u32 size; /* validate transfer in the host */ - __u32 stride; /* validate transfer in the host */ -}; - -struct drm_virtgpu_resource_info { - __u32 bo_handle; - __u32 res_handle; - __u32 size; - __u32 stride; -}; - -struct drm_virtgpu_3d_box { - __u32 x; - __u32 y; - __u32 z; - __u32 w; - __u32 h; - __u32 d; -}; - -struct drm_virtgpu_3d_transfer_to_host { - __u32 bo_handle; - struct drm_virtgpu_3d_box box; - __u32 level; - __u32 offset; -}; - -struct drm_virtgpu_3d_transfer_from_host { - __u32 bo_handle; - struct drm_virtgpu_3d_box box; - __u32 level; - __u32 offset; -}; - -#define VIRTGPU_WAIT_NOWAIT 1 /* like it */ -struct drm_virtgpu_3d_wait { - __u32 handle; /* 0 is an invalid handle */ - __u32 flags; -}; - -struct drm_virtgpu_get_caps { - __u32 cap_set_id; - __u32 cap_set_ver; - __u64 addr; - __u32 size; - __u32 pad; -}; - -#define DRM_IOCTL_VIRTGPU_MAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) - -#define DRM_IOCTL_VIRTGPU_EXECBUFFER \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ - struct drm_virtgpu_execbuffer) - -#define DRM_IOCTL_VIRTGPU_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ - struct drm_virtgpu_getparam) - -#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ - struct drm_virtgpu_resource_create) - -#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ - struct drm_virtgpu_resource_info) - -#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ - struct drm_virtgpu_3d_transfer_from_host) - -#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ - struct drm_virtgpu_3d_transfer_to_host) - -#define DRM_IOCTL_VIRTGPU_WAIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ - struct drm_virtgpu_3d_wait) - -#define DRM_IOCTL_VIRTGPU_GET_CAPS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ - struct drm_virtgpu_get_caps) - -#if defined(__cplusplus) -} -#endif - -#endif diff --git a/samples/utils/3rdparty/libdrm/include/tool.h b/samples/utils/3rdparty/libdrm/include/tool.h deleted file mode 100755 index 5e577c8..0000000 --- a/samples/utils/3rdparty/libdrm/include/tool.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - - */ - -#ifndef TOOL_H_ -#define TOOL_H_ -//ڴ˴ͷļ -#include "stdio.h" -#include "string.h" -#include "stdlib.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define YUV420 0 -#define YUV422 YUV420 + 1 -#define YUV444 YUV422 + 1 -/************************************************************* -Function: ReadBmpFile -Description: ȡbmpͼڴ -Input: pFilePathbmp· - pDatargbͼڴָ룬rgbͼ˳Ϊbgrbgr...bgrrgbֵΪ8bit - widthͼ - heightͼ -Output: -*************************************************************/ -extern void ReadBmpFile(char *pFilePath, unsigned char *pData, int & width, int & height); -/************************************************************* -Function: SaveBmpFile -Description: rgbͼݱΪbmp -Input: pFilePathbmp· - pDatargbͼڴָ룬rgbͼ˳Ϊbgrbgr...bgrrgbֵΪ8bit - widthͼ - heightͼ -Output: -*************************************************************/ -extern void SaveBmpFile(char *pFilePath, unsigned char *pData, int width, int height); -/************************************************************* -Function: SaveRaw -Description: rawͼ -Input: pSavePathraw· - pDataraw - widthrawͼ - heightrawͼ -Output: -*************************************************************/ -extern void SaveRaw(char *pSavePath, short *pRawData, int width, int height); - -extern void SaveRaw32bit(char *pSavePath, long *pRawData, int width, int height); - -/************************************************************* -Function: SaveBmpFile2 -Description: λ8bitbmpͼ -Input: pFilePathbmp· - widthͼ - heightͼ - bitValueͼλ - pRGBDatargbͼڴָ룬rgbͼ˳Ϊbgrbgr...bgr -Output: -*************************************************************/ -extern void SaveBmpFile2(char *pFilePath, int width, int height, int bitValue, short *pRGBData); - -/************************************************************* -Function: SaveYUVData -Description: 8bit YUVͼ -Input: pSavePath· - pDatayuvݣ8bit˳yyy...yyyuuu...uuuvvv...vvv - widthͼ - heightͼ -Output: -*************************************************************/ -extern void SaveYUVData(char *pSavePath, unsigned char *pData, int width, int height); - - - -/************************************************************* -Function: SaveYUVData2 -Description: λ8bitYUVͼ -Input: pSavePath· - pDatayuvݣλ8bit˳yyy...yyyuuu...uuuvvv...vvv - widthͼ - heightͼ -Output: -*************************************************************/ -extern void SaveYUVData2(char *pSavePath, short *pData, int width, int height, int bitValue); -/************************************************************* -Function: SaveYUVData1 -Description: 8bit YUV420ͼ -Input: pSavePath· - pDatayuvݣ8bit˳yyy...yyyuuu...uuuvvv...vvv - widthͼ - heightͼ -Output: -*************************************************************/ -extern void SaveYUVData1(char *pSavePath, unsigned char *pData, int width, int height, int fmt); -/************************************************************* -Function: ReadYUVData1 -Description: ȡ8bit YUV420ͼ -Input: pReadPath· - pDatayuvݣ8bit˳yyy...yyyuuu...uuuvvv...vvv - widthͼ - heightͼ -Output: -*************************************************************/ -extern void ReadYUVData1(char *pReadPath, unsigned char *pData, int width, int height, int fmt); -/************************************************************* -Function: Yuvfmtconv -Description: yuv fmt conversion.444 420 422 to 444 420 422 -Input: pDatain 뻺 - pDataout - width - height - fmt_in ʽ - fmt_out ʽ -Output: -*************************************************************/ -extern void Yuvfmtconv(void *pDatain, void *pDataout, int width, int height, int fmt_in, int fmt_out, int size); -/************************************************************* -Function: Yuvbitstochar -Description: save yuv to 8 bitdepth -Input: pDatain 뻺 - pDataout - size yuv - height λ -Output: -*************************************************************/ -extern void Yuvbitstochar(short *pDatain, unsigned char *pDataout, int size, int bitdepth); - -/************************************************************* -Function: SaveCfaBmp -Description: rawcfaͼ -Input: pRawDatarawͼ - widthrawͼ - heightrawͼߣ - bayerPatternbayer patternʽȡֵΧ[03] - bitValuerawλ -Output: -*************************************************************/ -extern void SaveCfaBmp(char *pFilePath, short *pRawData, int width, int height, int bayerPattern, int bitValue); - -#ifdef __cplusplus -} -#endif - -#endif // TOOL_H_ diff --git a/samples/utils/3rdparty/libdrm/include/xf86drmMode.h b/samples/utils/3rdparty/libdrm/include/xf86drmMode.h deleted file mode 100755 index a32902f..0000000 --- a/samples/utils/3rdparty/libdrm/include/xf86drmMode.h +++ /dev/null @@ -1,551 +0,0 @@ -/* - * \file xf86drmMode.h - * Header for DRM modesetting interface. - * - * \author Jakob Bornecrantz - * - * \par Acknowledgements: - * Feb 2007, Dave Airlie - */ - -/* - * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas. - * Copyright (c) 2007-2008 Dave Airlie - * Copyright (c) 2007-2008 Jakob Bornecrantz - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - */ - -#ifndef _XF86DRMMODE_H_ -#define _XF86DRMMODE_H_ - -#if defined(__cplusplus) -extern "C" { -#endif - -#include - -/* - * This is the interface for modesetting for drm. - * - * In order to use this interface you must include either or another - * header defining uint32_t, int32_t and uint16_t. - * - * It aims to provide a randr1.2 compatible interface for modesettings in the - * kernel, the interface is also meant to be used by libraries like EGL. - * - * More information can be found in randrproto.txt which can be found here: - * http://gitweb.freedesktop.org/?p=xorg/proto/randrproto.git - * - * There are some major differences to be noted. Unlike the randr1.2 proto you - * need to create the memory object of the framebuffer yourself with the ttm - * buffer object interface. This object needs to be pinned. - */ - -/* - * If we pickup an old version of drm.h which doesn't include drm_mode.h - * we should redefine defines. This is so that builds doesn't breaks with - * new libdrm on old kernels. - */ -#ifndef _DRM_MODE_H - -#define DRM_DISPLAY_INFO_LEN 32 -#define DRM_CONNECTOR_NAME_LEN 32 -#define DRM_DISPLAY_MODE_LEN 32 -#define DRM_PROP_NAME_LEN 32 - -#define DRM_MODE_TYPE_BUILTIN (1<<0) -#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) -#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) -#define DRM_MODE_TYPE_PREFERRED (1<<3) -#define DRM_MODE_TYPE_DEFAULT (1<<4) -#define DRM_MODE_TYPE_USERDEF (1<<5) -#define DRM_MODE_TYPE_DRIVER (1<<6) - -/* Video mode flags */ -/* bit compatible with the xorg definitions. */ -#define DRM_MODE_FLAG_PHSYNC (1<<0) -#define DRM_MODE_FLAG_NHSYNC (1<<1) -#define DRM_MODE_FLAG_PVSYNC (1<<2) -#define DRM_MODE_FLAG_NVSYNC (1<<3) -#define DRM_MODE_FLAG_INTERLACE (1<<4) -#define DRM_MODE_FLAG_DBLSCAN (1<<5) -#define DRM_MODE_FLAG_CSYNC (1<<6) -#define DRM_MODE_FLAG_PCSYNC (1<<7) -#define DRM_MODE_FLAG_NCSYNC (1<<8) -#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ -#define DRM_MODE_FLAG_BCAST (1<<10) -#define DRM_MODE_FLAG_PIXMUX (1<<11) -#define DRM_MODE_FLAG_DBLCLK (1<<12) -#define DRM_MODE_FLAG_CLKDIV2 (1<<13) -#define DRM_MODE_FLAG_3D_MASK (0x1f<<14) -#define DRM_MODE_FLAG_3D_NONE (0<<14) -#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) -#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) -#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) -#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14) -#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14) -#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) -#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) -#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) - -/* DPMS flags */ -/* bit compatible with the xorg definitions. */ -#define DRM_MODE_DPMS_ON 0 -#define DRM_MODE_DPMS_STANDBY 1 -#define DRM_MODE_DPMS_SUSPEND 2 -#define DRM_MODE_DPMS_OFF 3 - -/* Scaling mode options */ -#define DRM_MODE_SCALE_NON_GPU 0 -#define DRM_MODE_SCALE_FULLSCREEN 1 -#define DRM_MODE_SCALE_NO_SCALE 2 -#define DRM_MODE_SCALE_ASPECT 3 - -/* Dithering mode options */ -#define DRM_MODE_DITHERING_OFF 0 -#define DRM_MODE_DITHERING_ON 1 - -#define DRM_MODE_ENCODER_NONE 0 -#define DRM_MODE_ENCODER_DAC 1 -#define DRM_MODE_ENCODER_TMDS 2 -#define DRM_MODE_ENCODER_LVDS 3 -#define DRM_MODE_ENCODER_TVDAC 4 -#define DRM_MODE_ENCODER_VIRTUAL 5 -#define DRM_MODE_ENCODER_DSI 6 -#define DRM_MODE_ENCODER_DPMST 7 -#define DRM_MODE_ENCODER_DPI 8 - -#define DRM_MODE_SUBCONNECTOR_Automatic 0 -#define DRM_MODE_SUBCONNECTOR_Unknown 0 -#define DRM_MODE_SUBCONNECTOR_DVID 3 -#define DRM_MODE_SUBCONNECTOR_DVIA 4 -#define DRM_MODE_SUBCONNECTOR_Composite 5 -#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 -#define DRM_MODE_SUBCONNECTOR_Component 8 -#define DRM_MODE_SUBCONNECTOR_SCART 9 - -#define DRM_MODE_CONNECTOR_Unknown 0 -#define DRM_MODE_CONNECTOR_VGA 1 -#define DRM_MODE_CONNECTOR_DVII 2 -#define DRM_MODE_CONNECTOR_DVID 3 -#define DRM_MODE_CONNECTOR_DVIA 4 -#define DRM_MODE_CONNECTOR_Composite 5 -#define DRM_MODE_CONNECTOR_SVIDEO 6 -#define DRM_MODE_CONNECTOR_LVDS 7 -#define DRM_MODE_CONNECTOR_Component 8 -#define DRM_MODE_CONNECTOR_9PinDIN 9 -#define DRM_MODE_CONNECTOR_DisplayPort 10 -#define DRM_MODE_CONNECTOR_HDMIA 11 -#define DRM_MODE_CONNECTOR_HDMIB 12 -#define DRM_MODE_CONNECTOR_TV 13 -#define DRM_MODE_CONNECTOR_eDP 14 -#define DRM_MODE_CONNECTOR_VIRTUAL 15 -#define DRM_MODE_CONNECTOR_DSI 16 -#define DRM_MODE_CONNECTOR_DPI 17 - -#define DRM_MODE_PROP_PENDING (1<<0) -#define DRM_MODE_PROP_RANGE (1<<1) -#define DRM_MODE_PROP_IMMUTABLE (1<<2) -#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ -#define DRM_MODE_PROP_BLOB (1<<4) - -#define DRM_MODE_CURSOR_BO (1<<0) -#define DRM_MODE_CURSOR_MOVE (1<<1) - -#endif /* _DRM_MODE_H */ - - -/* - * Feature defines - * - * Just because these are defined doesn't mean that the kernel - * can do that feature, its just for new code vs old libdrm. - */ -#define DRM_MODE_FEATURE_KMS 1 -#define DRM_MODE_FEATURE_DIRTYFB 1 - - -typedef struct _drmModeRes { - - int count_fbs; - uint32_t *fbs; - - int count_crtcs; - uint32_t *crtcs; - - int count_connectors; - uint32_t *connectors; - - int count_encoders; - uint32_t *encoders; - - uint32_t min_width, max_width; - uint32_t min_height, max_height; -} drmModeRes, *drmModeResPtr; - -typedef struct _drmModeModeInfo { - uint32_t clock; - uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew; - uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan; - - uint32_t vrefresh; - - uint32_t flags; - uint32_t type; - char name[DRM_DISPLAY_MODE_LEN]; -} drmModeModeInfo, *drmModeModeInfoPtr; - -typedef struct _drmModeFB { - uint32_t fb_id; - uint32_t width, height; - uint32_t pitch; - uint32_t bpp; - uint32_t depth; - /* driver specific handle */ - uint32_t handle; -} drmModeFB, *drmModeFBPtr; - -typedef struct drm_clip_rect drmModeClip, *drmModeClipPtr; - -typedef struct _drmModePropertyBlob { - uint32_t id; - uint32_t length; - void *data; -} drmModePropertyBlobRes, *drmModePropertyBlobPtr; - -typedef struct _drmModeProperty { - uint32_t prop_id; - uint32_t flags; - char name[DRM_PROP_NAME_LEN]; - int count_values; - uint64_t *values; /* store the blob lengths */ - int count_enums; - struct drm_mode_property_enum *enums; - int count_blobs; - uint32_t *blob_ids; /* store the blob IDs */ -} drmModePropertyRes, *drmModePropertyPtr; - -static __inline int drm_property_type_is(drmModePropertyPtr property, - uint32_t type) -{ - /* instanceof for props.. handles extended type vs original types: */ - if (property->flags & DRM_MODE_PROP_EXTENDED_TYPE) - return (property->flags & DRM_MODE_PROP_EXTENDED_TYPE) == type; - return property->flags & type; -} - -typedef struct _drmModeCrtc { - uint32_t crtc_id; - uint32_t buffer_id; /**< FB id to connect to 0 = disconnect */ - - uint32_t x, y; /**< Position on the framebuffer */ - uint32_t width, height; - int mode_valid; - drmModeModeInfo mode; - - int gamma_size; /**< Number of gamma stops */ - -} drmModeCrtc, *drmModeCrtcPtr; - -typedef struct _drmModeEncoder { - uint32_t encoder_id; - uint32_t encoder_type; - uint32_t crtc_id; - uint32_t possible_crtcs; - uint32_t possible_clones; -} drmModeEncoder, *drmModeEncoderPtr; - -typedef enum { - DRM_MODE_CONNECTED = 1, - DRM_MODE_DISCONNECTED = 2, - DRM_MODE_UNKNOWNCONNECTION = 3 -} drmModeConnection; - -typedef enum { - DRM_MODE_SUBPIXEL_UNKNOWN = 1, - DRM_MODE_SUBPIXEL_HORIZONTAL_RGB = 2, - DRM_MODE_SUBPIXEL_HORIZONTAL_BGR = 3, - DRM_MODE_SUBPIXEL_VERTICAL_RGB = 4, - DRM_MODE_SUBPIXEL_VERTICAL_BGR = 5, - DRM_MODE_SUBPIXEL_NONE = 6 -} drmModeSubPixel; - -typedef struct _drmModeConnector { - uint32_t connector_id; - uint32_t encoder_id; /**< Encoder currently connected to */ - uint32_t connector_type; - uint32_t connector_type_id; - drmModeConnection connection; - uint32_t mmWidth, mmHeight; /**< HxW in millimeters */ - drmModeSubPixel subpixel; - - int count_modes; - drmModeModeInfoPtr modes; - - int count_props; - uint32_t *props; /**< List of property ids */ - uint64_t *prop_values; /**< List of property values */ - - int count_encoders; - uint32_t *encoders; /**< List of encoder ids */ -} drmModeConnector, *drmModeConnectorPtr; - -#define DRM_PLANE_TYPE_OVERLAY 0 -#define DRM_PLANE_TYPE_PRIMARY 1 -#define DRM_PLANE_TYPE_CURSOR 2 - -typedef struct _drmModeObjectProperties { - uint32_t count_props; - uint32_t *props; - uint64_t *prop_values; -} drmModeObjectProperties, *drmModeObjectPropertiesPtr; - -typedef struct _drmModePlane { - uint32_t count_formats; - uint32_t *formats; - uint32_t plane_id; - - uint32_t crtc_id; - uint32_t fb_id; - - uint32_t crtc_x, crtc_y; - uint32_t x, y; - - uint32_t possible_crtcs; - uint32_t gamma_size; -} drmModePlane, *drmModePlanePtr; - -typedef struct _drmModePlaneRes { - uint32_t count_planes; - uint32_t *planes; -} drmModePlaneRes, *drmModePlaneResPtr; - -extern void drmModeFreeModeInfo( drmModeModeInfoPtr ptr ); -extern void drmModeFreeResources( drmModeResPtr ptr ); -extern void drmModeFreeFB( drmModeFBPtr ptr ); -extern void drmModeFreeCrtc( drmModeCrtcPtr ptr ); -extern void drmModeFreeConnector( drmModeConnectorPtr ptr ); -extern void drmModeFreeEncoder( drmModeEncoderPtr ptr ); -extern void drmModeFreePlane( drmModePlanePtr ptr ); -extern void drmModeFreePlaneResources(drmModePlaneResPtr ptr); - -/** - * Retrieves all of the resources associated with a card. - */ -extern drmModeResPtr drmModeGetResources(int fd); - -/* - * FrameBuffer manipulation. - */ - -/** - * Retrieve information about framebuffer bufferId - */ -extern drmModeFBPtr drmModeGetFB(int fd, uint32_t bufferId); - -/** - * Creates a new framebuffer with an buffer object as its scanout buffer. - */ -extern int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth, - uint8_t bpp, uint32_t pitch, uint32_t bo_handle, - uint32_t *buf_id); -/* ...with a specific pixel format */ -extern int drmModeAddFB2(int fd, uint32_t width, uint32_t height, - uint32_t pixel_format, const uint32_t bo_handles[4], - const uint32_t pitches[4], const uint32_t offsets[4], - uint32_t *buf_id, uint32_t flags); - -/* ...with format modifiers */ -int drmModeAddFB2WithModifiers(int fd, uint32_t width, uint32_t height, - uint32_t pixel_format, const uint32_t bo_handles[4], - const uint32_t pitches[4], const uint32_t offsets[4], - const uint64_t modifier[4], uint32_t *buf_id, - uint32_t flags); - -/** - * Destroies the given framebuffer. - */ -extern int drmModeRmFB(int fd, uint32_t bufferId); - -/** - * Mark a region of a framebuffer as dirty. - */ -extern int drmModeDirtyFB(int fd, uint32_t bufferId, - drmModeClipPtr clips, uint32_t num_clips); - - -/* - * Crtc functions - */ - -/** - * Retrieve information about the ctrt crtcId - */ -extern drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId); - -/** - * Set the mode on a crtc crtcId with the given mode modeId. - */ -int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId, - uint32_t x, uint32_t y, uint32_t *connectors, int count, - drmModeModeInfoPtr mode); - -/* - * Cursor functions - */ - -/** - * Set the cursor on crtc - */ -int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height); - -int drmModeSetCursor2(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height, int32_t hot_x, int32_t hot_y); -/** - * Move the cursor on crtc - */ -int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y); - -/** - * Encoder functions - */ -drmModeEncoderPtr drmModeGetEncoder(int fd, uint32_t encoder_id); - -/* - * Connector manipulation - */ - -/** - * Retrieve all information about the connector connectorId. This will do a - * forced probe on the connector to retrieve remote information such as EDIDs - * from the display device. - */ -extern drmModeConnectorPtr drmModeGetConnector(int fd, - uint32_t connectorId); - -/** - * Retrieve current information, i.e the currently active mode and encoder, - * about the connector connectorId. This will not do any probing on the - * connector or remote device, and only reports what is currently known. - * For the complete set of modes and encoders associated with the connector - * use drmModeGetConnector() which will do a probe to determine any display - * link changes first. - */ -extern drmModeConnectorPtr drmModeGetConnectorCurrent(int fd, - uint32_t connector_id); - -/** - * Attaches the given mode to an connector. - */ -extern int drmModeAttachMode(int fd, uint32_t connectorId, drmModeModeInfoPtr mode_info); - -/** - * Detaches a mode from the connector - * must be unused, by the given mode. - */ -extern int drmModeDetachMode(int fd, uint32_t connectorId, drmModeModeInfoPtr mode_info); - -extern drmModePropertyPtr drmModeGetProperty(int fd, uint32_t propertyId); -extern void drmModeFreeProperty(drmModePropertyPtr ptr); - -extern drmModePropertyBlobPtr drmModeGetPropertyBlob(int fd, uint32_t blob_id); -extern void drmModeFreePropertyBlob(drmModePropertyBlobPtr ptr); -extern int drmModeConnectorSetProperty(int fd, uint32_t connector_id, uint32_t property_id, - uint64_t value); -extern int drmCheckModesettingSupported(const char *busid); - -extern int drmModeCrtcSetGamma(int fd, uint32_t crtc_id, uint32_t size, - uint16_t *red, uint16_t *green, uint16_t *blue); -extern int drmModeCrtcGetGamma(int fd, uint32_t crtc_id, uint32_t size, - uint16_t *red, uint16_t *green, uint16_t *blue); -extern int drmModePageFlip(int fd, uint32_t crtc_id, uint32_t fb_id, - uint32_t flags, void *user_data); -extern int drmModePageFlipTarget(int fd, uint32_t crtc_id, uint32_t fb_id, - uint32_t flags, void *user_data, - uint32_t target_vblank); - -extern drmModePlaneResPtr drmModeGetPlaneResources(int fd); -extern drmModePlanePtr drmModeGetPlane(int fd, uint32_t plane_id); -extern int drmModeSetPlane(int fd, uint32_t plane_id, uint32_t crtc_id, - uint32_t fb_id, uint32_t flags, - int32_t crtc_x, int32_t crtc_y, - uint32_t crtc_w, uint32_t crtc_h, - uint32_t src_x, uint32_t src_y, - uint32_t src_w, uint32_t src_h); - -extern drmModeObjectPropertiesPtr drmModeObjectGetProperties(int fd, - uint32_t object_id, - uint32_t object_type); -extern void drmModeFreeObjectProperties(drmModeObjectPropertiesPtr ptr); -extern int drmModeObjectSetProperty(int fd, uint32_t object_id, - uint32_t object_type, uint32_t property_id, - uint64_t value); - - -typedef struct _drmModeAtomicReq drmModeAtomicReq, *drmModeAtomicReqPtr; - -extern drmModeAtomicReqPtr drmModeAtomicAlloc(void); -extern drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr req); -extern int drmModeAtomicMerge(drmModeAtomicReqPtr base, - drmModeAtomicReqPtr augment); -extern void drmModeAtomicFree(drmModeAtomicReqPtr req); -extern int drmModeAtomicGetCursor(drmModeAtomicReqPtr req); -extern void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor); -extern int drmModeAtomicAddProperty(drmModeAtomicReqPtr req, - uint32_t object_id, - uint32_t property_id, - uint64_t value); -extern int drmModeAtomicCommit(int fd, - drmModeAtomicReqPtr req, - uint32_t flags, - void *user_data); - -extern int drmModeCreatePropertyBlob(int fd, const void *data, size_t size, - uint32_t *id); -extern int drmModeDestroyPropertyBlob(int fd, uint32_t id); - -/* - * DRM mode lease APIs. These create and manage new drm_masters with - * access to a subset of the available DRM resources - */ - -extern int drmModeCreateLease(int fd, const uint32_t *objects, int num_objects, int flags, uint32_t *lessee_id); - -typedef struct drmModeLesseeList { - uint32_t count; - uint32_t lessees[0]; -} drmModeLesseeListRes, *drmModeLesseeListPtr; - -extern drmModeLesseeListPtr drmModeListLessees(int fd); - -typedef struct drmModeObjectList { - uint32_t count; - uint32_t objects[0]; -} drmModeObjectListRes, *drmModeObjectListPtr; - -extern drmModeObjectListPtr drmModeGetLease(int fd); - -extern int drmModeRevokeLease(int fd, uint32_t lessee_id); - -#if defined(__cplusplus) -} -#endif - -#endif From 57ff9c68ee2125588657826efd8140657c6476d2 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 27 Nov 2023 16:07:34 +0800 Subject: [PATCH 35/46] samples: utils: cmake: supplemental utils dependencies on librga header Change-Id: Ib43bafee78c45402e77bdee109a0407fb2222d90 Signed-off-by: Yu Qiaowei --- samples/utils/CMakeLists.txt | 5 ++++- samples/utils/allocator/dma_alloc.cpp | 1 - 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/samples/utils/CMakeLists.txt b/samples/utils/CMakeLists.txt index aca18b5..02f8669 100644 --- a/samples/utils/CMakeLists.txt +++ b/samples/utils/CMakeLists.txt @@ -1,17 +1,20 @@ add_library(utils_obj OBJECT "") SET(THIRD_PARTY_PATH ${CMAKE_CURRENT_LIST_DIR}/3rdparty) +SET(UTILS_LIBRGA_SOURCE_PATH ${CMAKE_CURRENT_LIST_DIR}/../..) include(${CMAKE_CURRENT_LIST_DIR}/allocator/CMakeLists.txt) target_sources(utils_obj PRIVATE - ${CMAKE_CURRENT_LIST_DIR}/utils.cpp + ${CMAKE_CURRENT_LIST_DIR}/utils.cpp PUBLIC ${CMAKE_CURRENT_LIST_DIR}/utils.h ) target_include_directories(utils_obj + PRIVATE + ${UTILS_LIBRGA_SOURCE_PATH}/include PUBLIC ${CMAKE_CURRENT_LIST_DIR} ) diff --git a/samples/utils/allocator/dma_alloc.cpp b/samples/utils/allocator/dma_alloc.cpp index 3bbe379..3c207e8 100644 --- a/samples/utils/allocator/dma_alloc.cpp +++ b/samples/utils/allocator/dma_alloc.cpp @@ -46,7 +46,6 @@ #include #include "dma_alloc.h" -#include "RgaUtils.h" typedef unsigned long long __u64; typedef unsigned int __u32; From 6f18212f26be63732a9cf844292ace9ca2eac5d3 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 28 Nov 2023 16:40:56 +0800 Subject: [PATCH 36/46] samples: im2d_api_demo: add support for RV1106(cma-buf) Change-Id: Ib7f06303037acb9eb7a4217f9cb968859fc101a9 Signed-off-by: Yu Qiaowei --- samples/im2d_api_demo/CMakeLists.txt | 6 +- samples/im2d_api_demo/rgaImDemo.cpp | 565 ++++++++++++--------------- 2 files changed, 257 insertions(+), 314 deletions(-) diff --git a/samples/im2d_api_demo/CMakeLists.txt b/samples/im2d_api_demo/CMakeLists.txt index 5d0ad2b..b83580a 100644 --- a/samples/im2d_api_demo/CMakeLists.txt +++ b/samples/im2d_api_demo/CMakeLists.txt @@ -65,8 +65,12 @@ set(IM2D_DEMO_INCLUDE ../../include ../../im2d_api) +if (NOT DEFINED RGA_SAMPLES_UTILS_COMPILED) + include(${CMAKE_CURRENT_SOURCE_DIR}/../utils/CMakeLists.txt) +endif() + add_executable(${IM2D_DEMO_NAME} ${IM2D_DEMO_SRCS}) target_include_directories(${IM2D_DEMO_NAME} PUBLIC ${IM2D_DEMO_INCLUDE}) -target_link_libraries(${IM2D_DEMO_NAME} ${RGA_LIB}) +target_link_libraries(${IM2D_DEMO_NAME} ${RGA_LIB} utils_obj) install(TARGETS ${IM2D_DEMO_NAME} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) diff --git a/samples/im2d_api_demo/rgaImDemo.cpp b/samples/im2d_api_demo/rgaImDemo.cpp index e67eb4d..64581d5 100644 --- a/samples/im2d_api_demo/rgaImDemo.cpp +++ b/samples/im2d_api_demo/rgaImDemo.cpp @@ -26,6 +26,11 @@ #include #include +#include "im2d.hpp" +#include "RockchipRga.h" +#include "RgaUtils.h" +#include "args.h" + #ifdef ANDROID #include #if defined(ANDROID_12) || defined(USE_HARDWARE_ROCKCHIP) @@ -33,36 +38,26 @@ #endif #endif -#include "im2d.hpp" -#include "RockchipRga.h" -#include "RgaUtils.h" -#include "args.h" +#ifdef USE_PHYSICAL_CONTIGUOUS +#include "dma_alloc.h" +#endif #define ERROR -1 -/********** SrcInfo set **********/ -#define SRC_WIDTH 1280 -#define SRC_HEIGHT 720 +#define DEFAULT_WIDTH 1280 +#define DEFAULT_HEIGHT 720 +#define DEFAULT_SCALE_UP_WIDTH 1920 +#define DEFAULT_SCALE_UP_HEIGHT 1080 +#define DEFAULT_SCALE_DOWN_WIDTH 720 +#define DEFAULT_SCALE_DOWN_HEIGHT 480 #ifdef ANDROID -#define SRC_FORMAT HAL_PIXEL_FORMAT_RGBA_8888 -#endif -#ifdef LINUX -#define SRC_FORMAT RK_FORMAT_RGBA_8888 -#endif -/********** DstInfo set **********/ -#define DST_WIDTH 1280 -#define DST_HEIGHT 720 - -#ifdef ANDROID -#define DST_FORMAT HAL_PIXEL_FORMAT_RGBA_8888 -#endif -#ifdef LINUX -#define DST_FORMAT RK_FORMAT_RGBA_8888 -#endif - -struct timeval start, end; -long usec1; +#define DEFAULT_RGBA_FORMAT HAL_PIXEL_FORMAT_RGBA_8888 +#define DEFAULT_YUV_FORMAT HAL_PIXEL_FORMAT_YCrCb_420_SP +#else +#define DEFAULT_RGBA_FORMAT RK_FORMAT_RGBA_8888 +#define DEFAULT_YUV_FORMAT RK_FORMAT_YCbCr_420_SP +#endif /* #ifdef ANDROID */ #ifdef ANDROID enum { @@ -169,21 +164,22 @@ int AHardwareBuffer_Fill(AHardwareBuffer** buffer, int flag, int index) { void AHardwareBuffer_Deinit(AHardwareBuffer* buffer) { AHardwareBuffer_release(buffer); } - #endif #endif int main(int argc, char* argv[]) { - int ret = 0, while_time = 0; - int parm_data[MODE_MAX] = {0}; + struct timeval start, end; + long usec1; - int COLOR; - IM_USAGE ROTATE; - IM_USAGE FLIP; + int ret = 0; + int while_time = 0; + int mode; + int parm_data[MODE_MAX] = {0}; - int MODE; - IM_INFORMATION IM_INFO; - IM_STATUS STATUS; + IM_STATUS status; + IM_USAGE rotate; + IM_USAGE flip; + im_color_t color; im_rect src_rect; im_rect dst_rect; @@ -192,6 +188,10 @@ int main(int argc, char* argv[]) { rga_buffer_handle_t src_handle; rga_buffer_handle_t dst_handle; + int src_width, src_height, src_format; + int dst_width, dst_height, dst_format; + int src_buf_size, dst_buf_size; + #ifdef ANDROID #if USE_AHARDWAREBUFFER AHardwareBuffer* src_buf = nullptr; @@ -200,143 +200,219 @@ int main(int argc, char* argv[]) { sp src_buf; sp dst_buf; #endif -#endif - -#ifdef LINUX +#else /* #if USE_AHARDWAREBUFFER */ +#if USE_PHYSICAL_CONTIGUOUS char* src_buf = NULL; char* dst_buf = NULL; -#endif + int src_dma_fd, dst_dma_fd; +#else + char* src_buf = NULL; + char* dst_buf = NULL; +#endif /* #if USE_PHYSICAL_CONTIGUOUS */ +#endif /* #ifdef ANDROID */ memset(&src_rect, 0, sizeof(src_rect)); memset(&dst_rect, 0, sizeof(dst_rect)); memset(&src, 0, sizeof(src)); memset(&dst, 0, sizeof(dst)); - MODE = readArguments(argc, argv, parm_data); - if (MODE & WHILE_FLAG) { + mode = readArguments(argc, argv, parm_data); + if(MODE_NONE == mode) { + printf("%s, Unknow RGA mode\n", __FUNCTION__); + return ERROR; + } + + printf("RGA demo mode = %x\n", mode); + if (mode == MODE_QUERYSTRING) { + printf("\n%s\n", querystring((IM_INFORMATION)parm_data[MODE_QUERYSTRING])); + + return 0; + } + if (mode & WHILE_FLAG) { /* Remove flag of MODE_WHILE. */ - MODE &= ~WHILE_FLAG; + mode &= ~WHILE_FLAG; while_time = parm_data[MODE_WHILE]; } - printf("MODE = %x\n", MODE); - if(MODE_NONE == MODE) { - printf("%s, Unknow RGA mode\n", __FUNCTION__); - return ERROR; + + src_width = DEFAULT_WIDTH; + src_height = DEFAULT_HEIGHT; + src_format = DEFAULT_RGBA_FORMAT; + + switch (mode) { + case MODE_RESIZE: + switch(parm_data[MODE_RESIZE]) { + case IM_UP_SCALE: + dst_width = DEFAULT_SCALE_UP_WIDTH; + dst_height = DEFAULT_SCALE_UP_HEIGHT; + break; + case IM_DOWN_SCALE: + dst_width = DEFAULT_SCALE_DOWN_WIDTH; + dst_height = DEFAULT_SCALE_DOWN_HEIGHT; + break; + default: + printf("Please configure the correct scaling mode.\n"); + return ERROR; + } + + dst_format = DEFAULT_RGBA_FORMAT; + + break; + + case MODE_CVTCOLOR: + dst_width = DEFAULT_WIDTH; + dst_height = DEFAULT_HEIGHT; + dst_format = DEFAULT_YUV_FORMAT; + + break; + + default: + dst_width = DEFAULT_WIDTH; + dst_height = DEFAULT_HEIGHT; + dst_format = DEFAULT_RGBA_FORMAT; + + break; } + src_buf_size = src_width * src_height * get_bpp_from_format(src_format); + dst_buf_size = dst_width * dst_height * get_bpp_from_format(dst_format); + /********** Get parameters **********/ - if(MODE != MODE_QUERYSTRING) { #ifdef ANDROID #if USE_AHARDWAREBUFFER - if(ERROR == AHardwareBuffer_Init(SRC_WIDTH, SRC_HEIGHT, SRC_FORMAT, &src_buf)) { - printf("AHardwareBuffer init error!\n"); - return ERROR; - } - if(ERROR == AHardwareBuffer_Init(DST_WIDTH, DST_HEIGHT, DST_FORMAT, &dst_buf)) { - printf("AHardwareBuffer init error!\n"); - return ERROR; - } + if(ERROR == AHardwareBuffer_Init(src_width, src_height, src_format, &src_buf)) { + printf("AHardwareBuffer init error!\n"); + return ERROR; + } + if(ERROR == AHardwareBuffer_Init(dst_width, dst_height, dst_format, &dst_buf)) { + printf("AHardwareBuffer init error!\n"); + return ERROR; + } - if(ERROR == AHardwareBuffer_Fill(&src_buf, FILL_BUFF, 0)) { + if(ERROR == AHardwareBuffer_Fill(&src_buf, FILL_BUFF, 0)) { + printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); + return -1; + } + if(mode == MODE_BLEND || mode == MODE_FILL) { + if(ERROR == AHardwareBuffer_Fill(&dst_buf, FILL_BUFF, 1)) { printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); - return -1; - } - if(MODE == MODE_BLEND || MODE == MODE_FILL) { - if(ERROR == AHardwareBuffer_Fill(&dst_buf, FILL_BUFF, 1)) { - printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); - return ERROR; - } - } else { - if(ERROR == AHardwareBuffer_Fill(&dst_buf, EMPTY_BUFF, 1)) { - printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); - return ERROR; - } - } - - src_handle = importbuffer_AHardwareBuffer(src_buf); - if (src_handle <= 0) { - printf("Failed to import AHardwareBuffer for src channel!\n"); return ERROR; } - dst_handle = importbuffer_AHardwareBuffer(dst_buf); - if (dst_handle <= 0) { - printf("Failed to import AHardwareBuffer for dst channel!\n"); + } else { + if(ERROR == AHardwareBuffer_Fill(&dst_buf, EMPTY_BUFF, 1)) { + printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); return ERROR; } + } + + src_handle = importbuffer_AHardwareBuffer(src_buf); + if (src_handle <= 0) { + printf("Failed to import AHardwareBuffer for src channel!\n", imStrError()); + return ERROR; + } + dst_handle = importbuffer_AHardwareBuffer(dst_buf); + if (dst_handle <= 0) { + printf("Failed to import AHardwareBuffer for dst channel!\n", imStrError()); + return ERROR; + } #else - src_buf = GraphicBuffer_Init(SRC_WIDTH, SRC_HEIGHT, SRC_FORMAT); - dst_buf = GraphicBuffer_Init(DST_WIDTH, DST_HEIGHT, DST_FORMAT); - if (src_buf == NULL || dst_buf == NULL) { - printf("GraphicBuff init error!\n"); - return ERROR; - } + src_buf = GraphicBuffer_Init(src_width, src_height, src_format); + dst_buf = GraphicBuffer_Init(dst_width, dst_height, dst_format); + if (src_buf == NULL || dst_buf == NULL) { + printf("GraphicBuff init error!\n"); + return ERROR; + } - if(ERROR == GraphicBuffer_Fill(src_buf, FILL_BUFF, 0)) { + if(ERROR == GraphicBuffer_Fill(src_buf, FILL_BUFF, 0)) { + printf("%s, write Graphicbuffer error!\n", __FUNCTION__); + return -1; + } + if(mode == MODE_BLEND || mode == MODE_FILL) { + if(ERROR == GraphicBuffer_Fill(dst_buf, FILL_BUFF, 1)) { printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return -1; - } - if(MODE == MODE_BLEND || MODE == MODE_FILL) { - if(ERROR == GraphicBuffer_Fill(dst_buf, FILL_BUFF, 1)) { - printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return ERROR; - } - } else { - if(ERROR == GraphicBuffer_Fill(dst_buf, EMPTY_BUFF, 1)) { - printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return ERROR; - } - } - - src_handle = importbuffer_GraphicBuffer(src_buf); - if (src_handle <= 0) { - printf("Failed to import GraphicBuffer for src channel!\n"); return ERROR; } - dst_handle = importbuffer_GraphicBuffer(dst_buf); - if (dst_handle <= 0) { - printf("Failed to import GraphicBuffer for dst channel!\n"); + } else { + if(ERROR == GraphicBuffer_Fill(dst_buf, EMPTY_BUFF, 1)) { + printf("%s, write Graphicbuffer error!\n", __FUNCTION__); return ERROR; } -#endif -#elif LINUX - src_buf = (char*)malloc(SRC_WIDTH*SRC_HEIGHT*get_bpp_from_format(SRC_FORMAT)); - dst_buf = (char*)malloc(DST_WIDTH*DST_HEIGHT*get_bpp_from_format(DST_FORMAT)); + } - ret = get_buf_from_file(src_buf, SRC_FORMAT, SRC_WIDTH, SRC_HEIGHT, 0); - if (!ret) - printf("open file\n"); - else - printf ("can not open file\n"); - - if(MODE == MODE_BLEND || MODE == MODE_FILL) { - ret = get_buf_from_file(dst_buf, DST_FORMAT, DST_WIDTH, DST_HEIGHT, 1); - if (!ret) - printf("open file\n"); - else - printf ("can not open file\n"); - } else { - memset(dst_buf,0x00,DST_WIDTH*DST_HEIGHT*get_bpp_from_format(DST_FORMAT)); - } + src_handle = importbuffer_GraphicBuffer(src_buf); + if (src_handle <= 0) { + printf("Failed to import GraphicBuffer for src channel!\n", imStrError()); + return ERROR; + } + dst_handle = importbuffer_GraphicBuffer(dst_buf); + if (dst_handle <= 0) { + printf("Failed to import GraphicBuffer for dst channel!\n", imStrError()); + return ERROR; + } +#endif /* #if USE_AHARDWAREBUFFER */ +#else +#if USE_PHYSICAL_CONTIGUOUS + ret = dma_buf_alloc(RV1106_CMA_HEAP_PATH, src_buf_size, &src_dma_fd, (void **)&src_buf); + if (ret < 0) { + printf("alloc src CMA buffer failed!\n"); + return -1; + } - src_handle = importbuffer_virtualaddr(src_buf, SRC_WIDTH, SRC_HEIGHT, SRC_FORMAT); - if (src_handle <= 0) { - printf("Failed to import virtualaddr for src channel!\n"); - return ERROR; - } - dst_handle = importbuffer_virtualaddr(dst_buf, DST_WIDTH, DST_HEIGHT, DST_FORMAT); - if (dst_handle <= 0) { - printf("Failed to import virtualaddr for dst channel!\n"); - return ERROR; - } -#endif + ret = dma_buf_alloc(RV1106_CMA_HEAP_PATH, dst_buf_size, &dst_dma_fd, (void **)&dst_buf); + if (ret < 0) { + printf("alloc dst CMA buffer failed!\n"); + dma_buf_free(src_buf_size, &src_dma_fd, src_buf); + return -1; + } - src = wrapbuffer_handle(src_handle, SRC_WIDTH, SRC_HEIGHT, SRC_FORMAT); - dst = wrapbuffer_handle(dst_handle, DST_WIDTH, DST_HEIGHT, DST_FORMAT); - if(src.width == 0 || dst.width == 0) { - printf("%s, %s", __FUNCTION__, imStrError()); - return ERROR; + src_handle = importbuffer_fd(src_dma_fd, src_buf_size); + if (src_handle <= 0) { + printf("Failed to import CMA buffer fd for src channel!\n", imStrError()); + return ERROR; + } + dst_handle = importbuffer_fd(dst_dma_fd, dst_buf_size); + if (dst_handle <= 0) { + printf("Failed to import CMA buffer fd for dst channel!\n", imStrError()); + return ERROR; + } +#else + src_buf = (char*)malloc(src_buf_size); + dst_buf = (char*)malloc(dst_buf_size); + + src_handle = importbuffer_virtualaddr(src_buf, src_buf_size); + if (src_handle <= 0) { + printf("Failed to import virtualaddr for src channel! %s\n", imStrError()); + return ERROR; + } + dst_handle = importbuffer_virtualaddr(dst_buf, dst_buf_size); + if (dst_handle <= 0) { + printf("Failed to import virtualaddr for dst channel! %s\n", imStrError()); + return ERROR; + } +#endif /* #if USE_PHYSICAL_CONTIGUOUS */ + + ret = get_buf_from_file(src_buf, src_format, src_width, src_height, 0); + if (ret != 0) { + printf ("can not open file for src channel, memset to %d.\n", 0x11); + memset(dst_buf, 0x11, dst_buf_size); + } + + if(mode == MODE_BLEND || mode == MODE_FILL) { + ret = get_buf_from_file(dst_buf, dst_format, dst_width, dst_height, 1); + if (ret != 0) { + printf ("can not open file for dst channel, memset to %d.\n", 0x22); + memset(dst_buf, 0x22, dst_buf_size); } + } else { + memset(dst_buf, 0x00, dst_buf_size); + } +#endif /* #ifdef ANDROID */ + + src = wrapbuffer_handle(src_handle, src_width, src_height, src_format); + dst = wrapbuffer_handle(dst_handle, dst_width, dst_height, dst_format); + if(src.width == 0 || dst.width == 0) { + printf("%s, %s", __FUNCTION__, imStrError()); + return ERROR; } do { @@ -348,16 +424,8 @@ int main(int argc, char* argv[]) { while_time--; } /********** Execution function according to mode **********/ - switch(MODE) { - case MODE_QUERYSTRING : - - IM_INFO = (IM_INFORMATION)parm_data[MODE_QUERYSTRING]; - printf("\n%s\n", querystring(IM_INFO)); - - break; - + switch(mode) { case MODE_COPY : //rgaImDemo --copy - ret = imcheck(src, dst, src_rect, dst_rect); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); @@ -365,135 +433,15 @@ int main(int argc, char* argv[]) { } gettimeofday(&start, NULL); - STATUS = imcopy(src, dst); + status = imcopy(src, dst); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("copying .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("copying .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_RESIZE : //rgaImDemo --resize=up/down - releasebuffer_handle(dst_handle); - dst_handle = -1; - - switch(parm_data[MODE_RESIZE]) { - case IM_UP_SCALE : -#ifdef ANDROID -#if USE_AHARDWAREBUFFER - if(ERROR == AHardwareBuffer_Init(1920, 1080, DST_FORMAT, &dst_buf)) { - printf("AHardwareBuffer init error!\n"); - return ERROR; - } - - if(ERROR == AHardwareBuffer_Fill(&dst_buf, EMPTY_BUFF, 0)) { - printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); - return ERROR; - } - - dst_handle = importbuffer_AHardwareBuffer(dst_buf); - if (dst_handle <= 0) { - printf("Failed to import AHardwareBuffer for dst channel!\n"); - return ERROR; - } -#else - dst_buf = GraphicBuffer_Init(1920, 1080, DST_FORMAT); - if (dst_buf == NULL) { - printf("dst GraphicBuff init error!\n"); - return ERROR; - } - if(ERROR == GraphicBuffer_Fill(dst_buf, EMPTY_BUFF, 1)) { - printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return ERROR; - } - - dst_handle = importbuffer_GraphicBuffer(dst_buf); - if (dst_handle <= 0) { - printf("Failed to import GraphicBuffer for dst channel!\n"); - return ERROR; - } -#endif -#elif LINUX - if (dst_buf != NULL) { - free(dst_buf); - dst_buf = NULL; - } - dst_buf = (char*)malloc(1920*1080*get_bpp_from_format(DST_FORMAT)); - - memset(dst_buf,0x00,1920*1080*get_bpp_from_format(DST_FORMAT)); - - dst_handle = importbuffer_virtualaddr(dst_buf, 1920, 1080, DST_FORMAT); - if (dst_handle <= 0) { - printf("Failed to import virtualaddr for dst channel!\n"); - return ERROR; - } -#endif - dst = wrapbuffer_handle(dst_handle, 1920, 1080, DST_FORMAT); - if(dst.width == 0) { - printf("%s, %s\n", __FUNCTION__, imStrError()); - return ERROR; - } - - break; - case IM_DOWN_SCALE : - -#ifdef ANDROID -#if USE_AHARDWAREBUFFER - if(ERROR == AHardwareBuffer_Init(720, 480, DST_FORMAT, &dst_buf)) { - printf("AHardwareBuffer init error!\n"); - return ERROR; - } - - if(ERROR == AHardwareBuffer_Fill(&dst_buf, EMPTY_BUFF, 0)) { - printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); - return ERROR; - } - - dst_handle = importbuffer_AHardwareBuffer(dst_buf); - if (dst_handle <= 0) { - printf("Failed to import AHardwareBuffer for dst channel!\n"); - return ERROR; - } -#else - dst_buf = GraphicBuffer_Init(720, 480, DST_FORMAT); - if (dst_buf == NULL) { - printf("dst GraphicBuff init error!\n"); - return ERROR; - } - if(ERROR == GraphicBuffer_Fill(dst_buf, EMPTY_BUFF, 1)) { - printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return ERROR; - } - - dst_handle = importbuffer_GraphicBuffer(dst_buf); - if (dst_handle <= 0) { - printf("Failed to import GraphicBuffer for dst channel!\n"); - return ERROR; - } -#endif -#elif LINUX - if (dst_buf != NULL) { - free(dst_buf); - dst_buf = NULL; - } - dst_buf = (char*)malloc(720*480*get_bpp_from_format(DST_FORMAT)); - - memset(dst_buf,0x00,720*480*get_bpp_from_format(DST_FORMAT)); - - dst_handle = importbuffer_virtualaddr(dst_buf, 720, 480, DST_FORMAT); - if (dst_handle <= 0) { - printf("Failed to import virtualaddr for dst channel!\n"); - return ERROR; - } -#endif - dst = wrapbuffer_handle(dst_handle, 720, 480, DST_FORMAT); - if(dst.width == 0) { - printf("%s, %s\n", __FUNCTION__, imStrError()); - return ERROR; - } - break; - } - ret = imcheck(src, dst, src_rect, dst_rect); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); @@ -502,16 +450,15 @@ int main(int argc, char* argv[]) { gettimeofday(&start, NULL); - STATUS = imresize(src, dst); + status = imresize(src, dst); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("resizing .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("resizing .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_CROP : //rgaImDemo --crop - src_rect.x = 100; src_rect.y = 100; src_rect.width = 300; @@ -525,26 +472,25 @@ int main(int argc, char* argv[]) { gettimeofday(&start, NULL); - STATUS = imcrop(src, dst, src_rect); + status = imcrop(src, dst, src_rect); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("cropping .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("cropping .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_ROTATE : //rgaImDemo --rotate=90/180/270 + rotate = (IM_USAGE)parm_data[MODE_ROTATE]; - ROTATE = (IM_USAGE)parm_data[MODE_ROTATE]; - - if (IM_HAL_TRANSFORM_ROT_90 == ROTATE || IM_HAL_TRANSFORM_ROT_270 == ROTATE) { + if (IM_HAL_TRANSFORM_ROT_90 == rotate || IM_HAL_TRANSFORM_ROT_270 == rotate) { dst.width = src.height; dst.height = src.width; dst.wstride = src.hstride; dst.hstride = src.wstride; } - ret = imcheck(src, dst, src_rect, dst_rect, ROTATE); + ret = imcheck(src, dst, src_rect, dst_rect, rotate); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); return -1; @@ -552,17 +498,16 @@ int main(int argc, char* argv[]) { gettimeofday(&start, NULL); - STATUS = imrotate(src, dst, ROTATE); + status = imrotate(src, dst, rotate); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("rotating .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("rotating .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_FLIP : //rgaImDemo --flip=H/V - - FLIP = (IM_USAGE)parm_data[MODE_FLIP]; + flip = (IM_USAGE)parm_data[MODE_FLIP]; ret = imcheck(src, dst, src_rect, dst_rect); if (IM_STATUS_NOERROR != ret) { @@ -572,16 +517,15 @@ int main(int argc, char* argv[]) { gettimeofday(&start, NULL); - STATUS = imflip(src, dst, FLIP); + status = imflip(src, dst, flip); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("flipping .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("flipping .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_TRANSLATE : //rgaImDemo --translate - src_rect.x = 300; src_rect.y = 300; @@ -593,16 +537,15 @@ int main(int argc, char* argv[]) { gettimeofday(&start, NULL); - STATUS = imtranslate(src, dst, src_rect.x, src_rect.y); + status = imtranslate(src, dst, src_rect.x, src_rect.y); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("translating .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("translating .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_BLEND : //rgaImDemo --blend - ret = imcheck(src, dst, src_rect, dst_rect); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); @@ -611,25 +554,15 @@ int main(int argc, char* argv[]) { gettimeofday(&start, NULL); - STATUS = imblend(src, dst); + status = imblend(src, dst); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("blending .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("blending .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_CVTCOLOR : //rgaImDemo --cvtcolor - -#ifdef ANDROID - src.format = HAL_PIXEL_FORMAT_RGBA_8888; - dst.format = HAL_PIXEL_FORMAT_YCrCb_NV12; -#endif -#ifdef LINUX - src.format = RK_FORMAT_RGBA_8888; - dst.format = RK_FORMAT_YCbCr_420_SP; -#endif - ret = imcheck(src, dst, src_rect, dst_rect); if (IM_STATUS_NOERROR != ret) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); @@ -638,17 +571,16 @@ int main(int argc, char* argv[]) { gettimeofday(&start, NULL); - STATUS = imcvtcolor(src, dst, src.format, dst.format); + status = imcvtcolor(src, dst, src.format, dst.format); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("cvtcolor .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("cvtcolor .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_FILL : //rgaImDemo --fill=blue/green/red - - COLOR = parm_data[MODE_FILL]; + color.value = parm_data[MODE_FILL]; dst_rect.x = 100; dst_rect.y = 100; @@ -663,22 +595,20 @@ int main(int argc, char* argv[]) { gettimeofday(&start, NULL); - STATUS = imfill(dst, dst_rect, COLOR); + status = imfill(dst, dst_rect, color.value); gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("filling .... cost time %ld us, %s\n", usec1, imStrError(STATUS)); + printf("filling .... cost time %ld us, %s\n", usec1, imStrError(status)); break; case MODE_NONE : - printf("%s, Unknown mode\n", __FUNCTION__); break; default : - printf("%s, Invalid mode\n", __FUNCTION__); break; @@ -688,7 +618,7 @@ int main(int argc, char* argv[]) { /* 200ms */ usleep(200000); } - }while(while_time); + } while(while_time); /********** release rga buffer handle **********/ releasebuffer_handle(src_handle); @@ -697,6 +627,7 @@ int main(int argc, char* argv[]) { /********** output buf data to file **********/ #ifdef ANDROID char* outbuf = NULL; + #if USE_AHARDWAREBUFFER sp gbuffer = reinterpret_cast(dst_buf); if (gbuffer != NULL) { @@ -705,7 +636,9 @@ int main(int argc, char* argv[]) { printf("%s, %d, lock buffer failed!\n", __FUNCTION__, __LINE__); return -1; } + output_buf_data_to_file(outbuf, dst.format, dst.wstride, dst.hstride, 0); + ret = gbuffer->unlock(); if (ret != 0) { printf("%s, %d, unlock buffer failed!\n", __FUNCTION__, __LINE__); @@ -722,28 +655,34 @@ int main(int argc, char* argv[]) { printf("%s, %d, lock buffer failed!\n", __FUNCTION__, __LINE__); return -1; } + output_buf_data_to_file(outbuf, dst.format, dst.wstride, dst.hstride, 0); + ret = dst_buf->unlock(); if (ret != 0) { printf("%s, %d, unlock buffer failed!\n", __FUNCTION__, __LINE__); return -1; } } -#endif -#endif +#endif /* #if USE_AHARDWAREBUFFER */ +#else + output_buf_data_to_file(dst_buf, dst.format, dst.wstride, dst.hstride, 0); -#ifdef LINUX +#if USE_PHYSICAL_CONTIGUOUS + dma_buf_free(src_buf_size, &src_dma_fd, src_buf); + dma_buf_free(dst_buf_size, &dst_dma_fd, dst_buf); +#else if (src_buf != NULL) { free(src_buf); src_buf = NULL; } if (dst_buf != NULL) { - output_buf_data_to_file(dst_buf, dst.format, dst.wstride, dst.hstride, 0); free(dst_buf); dst_buf = NULL; } -#endif +#endif /* #if USE_PHYSICAL_CONTIGUOUS */ +#endif /* #ifdef ANDROID */ return 0; } From 4c6b31f75de4791057f7bbcc71f8587354c55b69 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 28 Nov 2023 16:49:56 +0800 Subject: [PATCH 37/46] samples: im2d_api_demo: remove dependency on GraphicBuffer/AHardwareBuffer Change-Id: I763a56b89f8f20afb3284d3559231a9c92171555 Signed-off-by: Yu Qiaowei --- samples/im2d_api_demo/CMakeLists.txt | 5 + samples/im2d_api_demo/args.cpp | 10 +- samples/im2d_api_demo/args.h | 3 + samples/im2d_api_demo/rgaImDemo.cpp | 528 ++++++++++----------------- 4 files changed, 202 insertions(+), 344 deletions(-) diff --git a/samples/im2d_api_demo/CMakeLists.txt b/samples/im2d_api_demo/CMakeLists.txt index b83580a..f591eb9 100644 --- a/samples/im2d_api_demo/CMakeLists.txt +++ b/samples/im2d_api_demo/CMakeLists.txt @@ -42,6 +42,11 @@ if(CMAKE_BUILD_TARGET STREQUAL cmake_linux) message(FATAL_ERROR "RGA: CMAKE_CXX_COMPILER not define") endif() + set(RKRGA_TARGET_SOC rv1106) + + if(RKRGA_TARGET_SOC STREQUAL rv1106) + add_definitions(-DUSE_RV1106_CMA=1) + endif() endif() if (EXISTS ${LIBRGA_FILE_LIB}/librga.so) diff --git a/samples/im2d_api_demo/args.cpp b/samples/im2d_api_demo/args.cpp index 143478b..337af5a 100644 --- a/samples/im2d_api_demo/args.cpp +++ b/samples/im2d_api_demo/args.cpp @@ -72,8 +72,8 @@ int readArguments(int argc, char *argv[], int* parm) { { "blend", no_argument, NULL, MODE_BLEND_CHAR }, { "cvtcolor", no_argument, NULL, MODE_CVTCOLOR_CHAR }, { "fill", required_argument, NULL, MODE_FILL_CHAR }, - { "help", no_argument, NULL, 'h' }, - { "while", required_argument, NULL, 'w' }, + { "while", required_argument, NULL, MODE_WHILE_CHAR }, + { "help", no_argument, NULL, MODE_HELP_CHAR }, { NULL , 0, NULL, 0 }, }; @@ -164,12 +164,12 @@ int readArguments(int argc, char *argv[], int* parm) { mode_code |= MODE_FILL; return mode_code; - case 'h' : + case MODE_HELP_CHAR : help_function(); - mode_code |= MODE_NONE; + mode_code |= MODE_HELP; return mode_code; - case 'w' : + case MODE_WHILE_CHAR : printf("im2d while .. "); if (optarg != NULL) diff --git a/samples/im2d_api_demo/args.h b/samples/im2d_api_demo/args.h index d7a29fa..2357830 100644 --- a/samples/im2d_api_demo/args.h +++ b/samples/im2d_api_demo/args.h @@ -34,6 +34,7 @@ typedef enum _mode_code { MODE_CVTCOLOR, MODE_FILL, MODE_WHILE, + MODE_HELP, MODE_NONE, MODE_MAX } MODE_CODE; @@ -48,6 +49,8 @@ typedef enum _mode_code { #define MODE_BLEND_CHAR (char) (MODE_BLEND +'0') #define MODE_CVTCOLOR_CHAR (char) (MODE_CVTCOLOR +'0') #define MODE_FILL_CHAR (char) (MODE_FILL +'0') +#define MODE_WHILE_CHAR 'w' +#define MODE_HELP_CHAR 'h' #define MODE_NONE_CHAR (char) (MODE_NONE +'0') #define BLUE_COLOR 0xffff0000 diff --git a/samples/im2d_api_demo/rgaImDemo.cpp b/samples/im2d_api_demo/rgaImDemo.cpp index 64581d5..1c097f4 100644 --- a/samples/im2d_api_demo/rgaImDemo.cpp +++ b/samples/im2d_api_demo/rgaImDemo.cpp @@ -31,18 +31,10 @@ #include "RgaUtils.h" #include "args.h" -#ifdef ANDROID -#include -#if defined(ANDROID_12) || defined(USE_HARDWARE_ROCKCHIP) -#include -#endif -#endif - -#ifdef USE_PHYSICAL_CONTIGUOUS +#include "utils.h" #include "dma_alloc.h" -#endif -#define ERROR -1 +#define LOCAL_FILE_PATH "/data" #define DEFAULT_WIDTH 1280 #define DEFAULT_HEIGHT 720 @@ -51,122 +43,19 @@ #define DEFAULT_SCALE_DOWN_WIDTH 720 #define DEFAULT_SCALE_DOWN_HEIGHT 480 -#ifdef ANDROID -#define DEFAULT_RGBA_FORMAT HAL_PIXEL_FORMAT_RGBA_8888 -#define DEFAULT_YUV_FORMAT HAL_PIXEL_FORMAT_YCrCb_420_SP -#else #define DEFAULT_RGBA_FORMAT RK_FORMAT_RGBA_8888 #define DEFAULT_YUV_FORMAT RK_FORMAT_YCbCr_420_SP -#endif /* #ifdef ANDROID */ - -#ifdef ANDROID -enum { - FILL_BUFF = 0, - EMPTY_BUFF = 1 -}; - -/* - * In order to be compatible with different android versions, - * some gralloc usage is defined here. - * The correct usage should be to refer to the corresponding header file: - * Android 12 and above: #include "hardware/gralloc_rockchip.h" - * Android 11 and below: #include "hardware/gralloc.h" - */ -#define GRALLOC_USAGE_PRIVATE_11 (1ULL << 56) -#define RK_GRALLOC_USAGE_WITHIN_4G GRALLOC_USAGE_PRIVATE_11 -#define RK_GRALLOC_USAGE_RGA_ACCESS RK_GRALLOC_USAGE_WITHIN_4G -sp GraphicBuffer_Init(int width, int height,int format) { - uint64_t usage = 0; - - /* cacheable */ - // usage |= GRALLOC_USAGE_SW_READ_OFTEN; - usage |= RK_GRALLOC_USAGE_WITHIN_4G; - - sp gb(new GraphicBuffer(width, height, format, 0, usage)); - - if (gb->initCheck()) { - printf("GraphicBuffer check error : %s\n",strerror(errno)); - return NULL; - } else - printf("GraphicBuffer check %s \n","ok"); - - return gb; -} - -/********** write data to buffer or init buffer**********/ -int GraphicBuffer_Fill(sp gb, int flag, int index) { - int ret; - char* buf = NULL; - ret = gb->lock(GRALLOC_USAGE_SW_WRITE_OFTEN, (void**)&buf); - - if (ret) { - printf("lock buffer error : %s\n",strerror(errno)); - return ERROR; - } else - printf("lock buffer %s \n","ok"); - - if(flag) - memset(buf,0x00,gb->getPixelFormat()*gb->getWidth()*gb->getHeight()); - else { - ret = get_buf_from_file(buf, gb->getPixelFormat(), gb->getWidth(), gb->getHeight(), index); - if (!ret) - printf("open file %s \n", "ok"); - else { - printf ("open file %s \n", "fault"); - return ERROR; - } +static int file_exists(const char* file_name) { + FILE* file = fopen(file_name, "r"); + if (file != NULL) { + fclose(file); + return true; } - ret = gb->unlock(); - if (ret) { - printf("unlock buffer error : %s\n",strerror(errno)); - return ERROR; - } else - printf("unlock buffer %s \n","ok"); - - return 0; + return false; } -#if USE_AHARDWAREBUFFER -int AHardwareBuffer_Init(int width, int height, int format, AHardwareBuffer** outBuffer) { - sp gbuffer; - gbuffer = GraphicBuffer_Init(width, height, format); - if(gbuffer == NULL) { - return ERROR; - } - - *outBuffer = reinterpret_cast(gbuffer.get()); - // Ensure the buffer doesn't get destroyed when the sp<> goes away. - AHardwareBuffer_acquire(*outBuffer); - printf("AHardwareBuffer init ok!\n"); - return 0; -} - -int AHardwareBuffer_Fill(AHardwareBuffer** buffer, int flag, int index) { - sp gbuffer; - - gbuffer = reinterpret_cast(*buffer); - - if(ERROR == GraphicBuffer_Fill(gbuffer, flag, index)) { - printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return ERROR; - } - - *buffer = reinterpret_cast(gbuffer.get()); - // Ensure the buffer doesn't get destroyed when the sp<> goes away. - - AHardwareBuffer_acquire(*buffer); - printf("AHardwareBuffer %s ok!\n", flag==0?"fill":"empty"); - return 0; -} - -void AHardwareBuffer_Deinit(AHardwareBuffer* buffer) { - AHardwareBuffer_release(buffer); -} -#endif -#endif - int main(int argc, char* argv[]) { struct timeval start, end; long usec1; @@ -192,24 +81,13 @@ int main(int argc, char* argv[]) { int dst_width, dst_height, dst_format; int src_buf_size, dst_buf_size; -#ifdef ANDROID -#if USE_AHARDWAREBUFFER - AHardwareBuffer* src_buf = nullptr; - AHardwareBuffer* dst_buf = nullptr; -#else - sp src_buf; - sp dst_buf; -#endif -#else /* #if USE_AHARDWAREBUFFER */ -#if USE_PHYSICAL_CONTIGUOUS char* src_buf = NULL; char* dst_buf = NULL; int src_dma_fd, dst_dma_fd; -#else - char* src_buf = NULL; - char* dst_buf = NULL; -#endif /* #if USE_PHYSICAL_CONTIGUOUS */ -#endif /* #ifdef ANDROID */ + + const char *heap_name = NULL; + int use_dma_heap = false; + int flush_cache = false; memset(&src_rect, 0, sizeof(src_rect)); memset(&dst_rect, 0, sizeof(dst_rect)); @@ -219,15 +97,20 @@ int main(int argc, char* argv[]) { mode = readArguments(argc, argv, parm_data); if(MODE_NONE == mode) { printf("%s, Unknow RGA mode\n", __FUNCTION__); - return ERROR; + return -1; } - printf("RGA demo mode = %x\n", mode); + printf("RGA demo mode = 0x%x\n", mode); if (mode == MODE_QUERYSTRING) { printf("\n%s\n", querystring((IM_INFORMATION)parm_data[MODE_QUERYSTRING])); return 0; } + + if (mode == MODE_HELP) { + return 0; + } + if (mode & WHILE_FLAG) { /* Remove flag of MODE_WHILE. */ mode &= ~WHILE_FLAG; @@ -252,7 +135,7 @@ int main(int argc, char* argv[]) { break; default: printf("Please configure the correct scaling mode.\n"); - return ERROR; + return -1; } dst_format = DEFAULT_RGBA_FORMAT; @@ -277,142 +160,104 @@ int main(int argc, char* argv[]) { src_buf_size = src_width * src_height * get_bpp_from_format(src_format); dst_buf_size = dst_width * dst_height * get_bpp_from_format(dst_format); - /********** Get parameters **********/ -#ifdef ANDROID -#if USE_AHARDWAREBUFFER - if(ERROR == AHardwareBuffer_Init(src_width, src_height, src_format, &src_buf)) { - printf("AHardwareBuffer init error!\n"); - return ERROR; - } - if(ERROR == AHardwareBuffer_Init(dst_width, dst_height, dst_format, &dst_buf)) { - printf("AHardwareBuffer init error!\n"); - return ERROR; - } +#if USE_RV1106_CMA + heap_name = RV1106_CMA_HEAP_PATH; + flush_cache = true; +#else + heap_name = DMA_HEAP_DMA32_UNCACHE_PATCH; +#endif - if(ERROR == AHardwareBuffer_Fill(&src_buf, FILL_BUFF, 0)) { - printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); - return -1; - } - if(mode == MODE_BLEND || mode == MODE_FILL) { - if(ERROR == AHardwareBuffer_Fill(&dst_buf, FILL_BUFF, 1)) { - printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); - return ERROR; - } - } else { - if(ERROR == AHardwareBuffer_Fill(&dst_buf, EMPTY_BUFF, 1)) { - printf("%s, write AHardwareBuffer error!\n", __FUNCTION__); - return ERROR; + /********** Get parameters **********/ + use_dma_heap = file_exists(heap_name); + if (use_dma_heap) { + printf("alloc buffer from \"%s\".\n", heap_name); + ret = dma_buf_alloc(heap_name, src_buf_size, &src_dma_fd, (void **)&src_buf); + if (ret < 0) { + printf("alloc src %s failed!\n", heap_name); + return -1; } - } - src_handle = importbuffer_AHardwareBuffer(src_buf); - if (src_handle <= 0) { - printf("Failed to import AHardwareBuffer for src channel!\n", imStrError()); - return ERROR; - } - dst_handle = importbuffer_AHardwareBuffer(dst_buf); - if (dst_handle <= 0) { - printf("Failed to import AHardwareBuffer for dst channel!\n", imStrError()); - return ERROR; - } -#else - src_buf = GraphicBuffer_Init(src_width, src_height, src_format); - dst_buf = GraphicBuffer_Init(dst_width, dst_height, dst_format); - if (src_buf == NULL || dst_buf == NULL) { - printf("GraphicBuff init error!\n"); - return ERROR; - } + ret = dma_buf_alloc(heap_name, dst_buf_size, &dst_dma_fd, (void **)&dst_buf); + if (ret < 0) { + printf("alloc dst %s failed!\n", heap_name); + dma_buf_free(src_buf_size, &src_dma_fd, src_buf); + goto free_buffer; + } - if(ERROR == GraphicBuffer_Fill(src_buf, FILL_BUFF, 0)) { - printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return -1; - } - if(mode == MODE_BLEND || mode == MODE_FILL) { - if(ERROR == GraphicBuffer_Fill(dst_buf, FILL_BUFF, 1)) { - printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return ERROR; + src_handle = importbuffer_fd(src_dma_fd, src_buf_size); + if (src_handle == 0) { + printf("Failed to import CMA buffer fd for src channel! %s\n", imStrError()); + goto free_buffer; } - } else { - if(ERROR == GraphicBuffer_Fill(dst_buf, EMPTY_BUFF, 1)) { - printf("%s, write Graphicbuffer error!\n", __FUNCTION__); - return ERROR; + dst_handle = importbuffer_fd(dst_dma_fd, dst_buf_size); + if (dst_handle == 0) { + printf("Failed to import CMA buffer fd for dst channel! %s\n", imStrError()); + goto free_buffer; } - } - - src_handle = importbuffer_GraphicBuffer(src_buf); - if (src_handle <= 0) { - printf("Failed to import GraphicBuffer for src channel!\n", imStrError()); - return ERROR; - } - dst_handle = importbuffer_GraphicBuffer(dst_buf); - if (dst_handle <= 0) { - printf("Failed to import GraphicBuffer for dst channel!\n", imStrError()); - return ERROR; - } -#endif /* #if USE_AHARDWAREBUFFER */ -#else -#if USE_PHYSICAL_CONTIGUOUS - ret = dma_buf_alloc(RV1106_CMA_HEAP_PATH, src_buf_size, &src_dma_fd, (void **)&src_buf); - if (ret < 0) { - printf("alloc src CMA buffer failed!\n"); - return -1; - } + } else { + printf("\"%s\" does not exist, so use malloc.\n", heap_name); - ret = dma_buf_alloc(RV1106_CMA_HEAP_PATH, dst_buf_size, &dst_dma_fd, (void **)&dst_buf); - if (ret < 0) { - printf("alloc dst CMA buffer failed!\n"); - dma_buf_free(src_buf_size, &src_dma_fd, src_buf); - return -1; - } + src_buf = (char*)malloc(src_buf_size); + dst_buf = (char*)malloc(dst_buf_size); + if (src_buf == NULL || dst_buf == NULL) { + printf("malloc buffer failed!\n"); + goto free_buffer; + } - src_handle = importbuffer_fd(src_dma_fd, src_buf_size); - if (src_handle <= 0) { - printf("Failed to import CMA buffer fd for src channel!\n", imStrError()); - return ERROR; - } - dst_handle = importbuffer_fd(dst_dma_fd, dst_buf_size); - if (dst_handle <= 0) { - printf("Failed to import CMA buffer fd for dst channel!\n", imStrError()); - return ERROR; + src_handle = importbuffer_virtualaddr(src_buf, src_buf_size); + if (src_handle == 0) { + printf("Failed to import virtualaddr for src channel! %s\n", imStrError()); + ret = -1; + goto free_buffer; + } + dst_handle = importbuffer_virtualaddr(dst_buf, dst_buf_size); + if (dst_handle == 0) { + printf("Failed to import virtualaddr for dst channel! %s\n", imStrError()); + ret = -1; + goto free_buffer; + } } -#else - src_buf = (char*)malloc(src_buf_size); - dst_buf = (char*)malloc(dst_buf_size); - src_handle = importbuffer_virtualaddr(src_buf, src_buf_size); - if (src_handle <= 0) { - printf("Failed to import virtualaddr for src channel! %s\n", imStrError()); - return ERROR; + /* invalid CPU cache */ + if (flush_cache && src_dma_fd && dst_dma_fd) { + dma_sync_device_to_cpu(src_dma_fd); + dma_sync_device_to_cpu(dst_dma_fd); } - dst_handle = importbuffer_virtualaddr(dst_buf, dst_buf_size); - if (dst_handle <= 0) { - printf("Failed to import virtualaddr for dst channel! %s\n", imStrError()); - return ERROR; - } -#endif /* #if USE_PHYSICAL_CONTIGUOUS */ - ret = get_buf_from_file(src_buf, src_format, src_width, src_height, 0); + ret = read_image_from_file(src_buf, LOCAL_FILE_PATH, src_width, src_height, src_format, 0); if (ret != 0) { - printf ("can not open file for src channel, memset to %d.\n", 0x11); - memset(dst_buf, 0x11, dst_buf_size); + printf ("can not open file for src channel, memset to 0x%x.\n", 0x11); + memset(src_buf, 0x11, src_buf_size); } - if(mode == MODE_BLEND || mode == MODE_FILL) { - ret = get_buf_from_file(dst_buf, dst_format, dst_width, dst_height, 1); + if(mode == MODE_FILL) { + ret = read_image_from_file(dst_buf, LOCAL_FILE_PATH, dst_width, dst_height, dst_format, 0); if (ret != 0) { - printf ("can not open file for dst channel, memset to %d.\n", 0x22); + printf ("can not open file for dst channel, memset to 0x%x.\n", 0x22); memset(dst_buf, 0x22, dst_buf_size); } + } else if (mode == MODE_BLEND) { + ret = read_image_from_file(dst_buf, LOCAL_FILE_PATH, dst_width, dst_height, dst_format, 1); + if (ret != 0) { + printf ("can not open file for dst channel, memset to 0x%x.\n", 0x33); + memset(dst_buf, 0x33, dst_buf_size); + } } else { memset(dst_buf, 0x00, dst_buf_size); } -#endif /* #ifdef ANDROID */ + + /* clear CPU cache */ + if (flush_cache && src_dma_fd && dst_dma_fd) { + dma_sync_cpu_to_device(src_dma_fd); + dma_sync_cpu_to_device(dst_dma_fd); + } src = wrapbuffer_handle(src_handle, src_width, src_height, src_format); dst = wrapbuffer_handle(dst_handle, dst_width, dst_height, dst_format); if(src.width == 0 || dst.width == 0) { printf("%s, %s", __FUNCTION__, imStrError()); - return ERROR; + ret = -1; + goto release_buffer; } do { @@ -427,34 +272,43 @@ int main(int argc, char* argv[]) { switch(mode) { case MODE_COPY : //rgaImDemo --copy ret = imcheck(src, dst, src_rect, dst_rect); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } + gettimeofday(&start, NULL); - status = imcopy(src, dst); + ret = imcopy(src, dst); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imcopy failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("copying .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("copying .... cost time %ld us\n", usec1); break; case MODE_RESIZE : //rgaImDemo --resize=up/down ret = imcheck(src, dst, src_rect, dst_rect); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } gettimeofday(&start, NULL); - status = imresize(src, dst); + ret = imresize(src, dst); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imresize failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("resizing .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("resizing .... cost time %ld us\n", usec1); break; @@ -465,18 +319,22 @@ int main(int argc, char* argv[]) { src_rect.height = 300; ret = imcheck(src, dst, src_rect, dst_rect, IM_CROP); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } gettimeofday(&start, NULL); - status = imcrop(src, dst, src_rect); + ret = imcrop(src, dst, src_rect); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imcrop failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("cropping .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("cropping .... cost time %ld us\n", usec1); break; @@ -491,18 +349,22 @@ int main(int argc, char* argv[]) { } ret = imcheck(src, dst, src_rect, dst_rect, rotate); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } gettimeofday(&start, NULL); - status = imrotate(src, dst, rotate); + ret = imrotate(src, dst, rotate); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imrotate failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("rotating .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("rotating .... cost time %ld us\n", usec1); break; @@ -510,18 +372,22 @@ int main(int argc, char* argv[]) { flip = (IM_USAGE)parm_data[MODE_FLIP]; ret = imcheck(src, dst, src_rect, dst_rect); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } gettimeofday(&start, NULL); - status = imflip(src, dst, flip); + ret = imflip(src, dst, flip); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imflip failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("flipping .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("flipping .... cost time %ld us\n", usec1); break; @@ -530,52 +396,64 @@ int main(int argc, char* argv[]) { src_rect.y = 300; ret = imcheck(src, dst, src_rect, dst_rect); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } gettimeofday(&start, NULL); - status = imtranslate(src, dst, src_rect.x, src_rect.y); + ret = imtranslate(src, dst, src_rect.x, src_rect.y); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imtranslate failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("translating .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("translating .... cost time %ld us\n", usec1); break; case MODE_BLEND : //rgaImDemo --blend ret = imcheck(src, dst, src_rect, dst_rect); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } gettimeofday(&start, NULL); - status = imblend(src, dst); + ret = imblend(src, dst, parm_data[MODE_FLIP] | IM_ALPHA_BLEND_PRE_MUL); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imblend failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("blending .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("blending .... cost time %ld us\n", usec1); break; case MODE_CVTCOLOR : //rgaImDemo --cvtcolor ret = imcheck(src, dst, src_rect, dst_rect); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } gettimeofday(&start, NULL); - status = imcvtcolor(src, dst, src.format, dst.format); + ret = imcvtcolor(src, dst, src.format, dst.format); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imcvtcolor failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("cvtcolor .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("cvtcolor .... cost time %ld us\n", usec1); break; @@ -588,18 +466,22 @@ int main(int argc, char* argv[]) { dst_rect.height = 300; ret = imcheck(src, dst, src_rect, dst_rect, IM_COLOR_FILL); - if (IM_STATUS_NOERROR != ret) { + if (ret != IM_STATUS_NOERROR) { printf("%d, check error! %s\n", __LINE__, imStrError((IM_STATUS)ret)); - return -1; + goto release_buffer; } gettimeofday(&start, NULL); - status = imfill(dst, dst_rect, color.value); + ret = imfill(dst, dst_rect, color.value); + if (ret != IM_STATUS_SUCCESS) { + printf("%d, imfill failed! %s\n", __LINE__, imStrError((IM_STATUS)ret)); + goto release_buffer; + } gettimeofday(&end, NULL); usec1 = 1000000 * (end.tv_sec - start.tv_sec) + (end.tv_usec - start.tv_usec); - printf("filling .... cost time %ld us, %s\n", usec1, imStrError(status)); + printf("filling .... cost time %ld us\n", usec1); break; @@ -620,70 +502,38 @@ int main(int argc, char* argv[]) { } } while(while_time); - /********** release rga buffer handle **********/ - releasebuffer_handle(src_handle); - releasebuffer_handle(dst_handle); + /* invalid CPU cache */ + if (flush_cache && src_dma_fd && dst_dma_fd) { + dma_sync_device_to_cpu(src_dma_fd); + dma_sync_device_to_cpu(dst_dma_fd); + } /********** output buf data to file **********/ -#ifdef ANDROID - char* outbuf = NULL; + write_image_to_file(dst_buf, LOCAL_FILE_PATH, dst_width, dst_height, dst_format, 0); -#if USE_AHARDWAREBUFFER - sp gbuffer = reinterpret_cast(dst_buf); - if (gbuffer != NULL) { - ret = gbuffer->lock(GRALLOC_USAGE_SW_WRITE_OFTEN | GRALLOC_USAGE_SW_READ_OFTEN, (void**)&outbuf); - if (ret != 0) { - printf("%s, %d, lock buffer failed!\n", __FUNCTION__, __LINE__); - return -1; - } - - output_buf_data_to_file(outbuf, dst.format, dst.wstride, dst.hstride, 0); - - ret = gbuffer->unlock(); - if (ret != 0) { - printf("%s, %d, unlock buffer failed!\n", __FUNCTION__, __LINE__); - return -1; - } - } +release_buffer: + /********** release rga buffer handle **********/ + releasebuffer_handle(src_handle); + releasebuffer_handle(dst_handle); - AHardwareBuffer_Deinit(src_buf); - AHardwareBuffer_Deinit(dst_buf); -#else - if (dst_buf != NULL) { - ret = dst_buf->lock(GRALLOC_USAGE_SW_WRITE_OFTEN | GRALLOC_USAGE_SW_READ_OFTEN, (void**)&outbuf); - if (ret != 0) { - printf("%s, %d, lock buffer failed!\n", __FUNCTION__, __LINE__); - return -1; +free_buffer: + if (use_dma_heap) { + if (src_buf != NULL) + dma_buf_free(src_buf_size, &src_dma_fd, src_buf); + if (dst_buf != NULL) + dma_buf_free(dst_buf_size, &dst_dma_fd, dst_buf); + } else { + if (src_buf != NULL) { + free(src_buf); + src_buf = NULL; } - output_buf_data_to_file(outbuf, dst.format, dst.wstride, dst.hstride, 0); - - ret = dst_buf->unlock(); - if (ret != 0) { - printf("%s, %d, unlock buffer failed!\n", __FUNCTION__, __LINE__); - return -1; + if (dst_buf != NULL) { + free(dst_buf); + dst_buf = NULL; } } -#endif /* #if USE_AHARDWAREBUFFER */ -#else - output_buf_data_to_file(dst_buf, dst.format, dst.wstride, dst.hstride, 0); - -#if USE_PHYSICAL_CONTIGUOUS - dma_buf_free(src_buf_size, &src_dma_fd, src_buf); - dma_buf_free(dst_buf_size, &dst_dma_fd, dst_buf); -#else - if (src_buf != NULL) { - free(src_buf); - src_buf = NULL; - } - - if (dst_buf != NULL) { - free(dst_buf); - dst_buf = NULL; - } -#endif /* #if USE_PHYSICAL_CONTIGUOUS */ -#endif /* #ifdef ANDROID */ - return 0; + return ret; } From bcaa4d4eeab568556b7747028e2190a3db39534b Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 28 Nov 2023 16:50:59 +0800 Subject: [PATCH 38/46] amples: im2d_api_demo: optimize somme commands 1. '--blend' supports more Porter-Duff modes. 2. '--fill' supports configuration of custom color values. 3. '--help' adds more option descriptions. Change-Id: I7a4b4051744a94592186ac813633580f86f4981e Signed-off-by: Yu Qiaowei --- samples/im2d_api_demo/args.cpp | 114 +++++++++++++++++++++++++++++---- 1 file changed, 101 insertions(+), 13 deletions(-) diff --git a/samples/im2d_api_demo/args.cpp b/samples/im2d_api_demo/args.cpp index 337af5a..ea905f5 100644 --- a/samples/im2d_api_demo/args.cpp +++ b/samples/im2d_api_demo/args.cpp @@ -37,24 +37,52 @@ void help_function() { "\t --querystring You can print the version or support information corresponding to the current version of RGA according to the options.\n" "\t If there is no input options, all versions and support information of the current version of RGA will be printed.\n" "\t :\n" - "\t vendor \tPrint vendor information.\n" - "\t version \tPrint RGA version, and librga/im2d_api version.\n" - "\t maxinput \tPrint max input resolution.\n" - "\t maxoutput \tPrint max output resolution.\n" - "\t scalelimit \tPrint scale limit.\n" - "\t inputformat \tPrint supported input formats.\n" - "\t outputformat \tPrint supported output formats.\n" - "\t expected \tPrint expected performance.\n" - "\t all \tPrint all information.\n" + "\t vendor \tPrint vendor information.\n" + "\t version \tPrint RGA version, and librga/im2d_api version.\n" + "\t maxinput \tPrint max input resolution.\n" + "\t maxoutput \tPrint max output resolution.\n" + "\t scalelimit \tPrint scale limit.\n" + "\t inputformat \tPrint supported input formats.\n" + "\t outputformat \tPrint supported output formats.\n" + "\t expected \tPrint expected performance.\n" + "\t all \tPrint all information.(Default)\n" "\t --copy Copy the image by RGA.The default is 720p to 720p.\n" "\t --resize resize the image by RGA.You can choose to up(720p->1080p) or down(720p->480p).\n" + "\t :\n" + "\t up \tScaling up 720p(1280x720) -> 1080p(1920x1080).\n" + "\t down \tScaling down 720p(1280x720) -> 480p(720x480).\n" "\t --crop Crop the image by RGA.By default, a picture of 300*300 size is cropped from (100,100).\n" "\t --rotate Rotate the image by RGA.You can choose to rotate 90/180/270 degrees.\n" + "\t :\n" + "\t 90 \tRotate 90 degrees.\n" + "\t 180 \tRotate 180 degrees.\n" + "\t 270 \tRotate 270 degrees.\n" "\t --flip Flip the image by RGA.You can choice of horizontal flip or vertical flip.\n" + "\t :\n" + "\t H \tHorizontal mirror.\n" + "\t V \tVertical mirror.\n" "\t --translate Translate the image by RGA.Default translation (300,300).\n" "\t --blend Blend the image by RGA.Default, Porter-Duff 'SRC over DST'.\n" + "\t :\n" + "\t src \tPorter-Duff SRC mode.\n" + "\t dst \tPorter-Duff DST mode.\n" + "\t src-over \tPorter-Duff SRC-OVER mode.(Default)\n" + "\t dst-over \tPorter-Duff DST-OVER mode.\n" + "\t src-in \tPorter-Duff SRC-IN mode.\n" + "\t dst-in \tPorter-Duff DST-IN mode.\n" + "\t src-out \tPorter-Duff SRC-OUT mode.\n" + "\t dst-out \tPorter-Duff DST-OUT mode.\n" + "\t src-atop \tPorter-Duff SRC-ATOP mode.\n" + "\t dst-atop \tPorter-Duff DST-ATOP mode.\n" + "\t xor \tPorter-Duff XOR mode.\n" "\t --cvtcolor Modify the image format and color space by RGA.The default is RGBA8888 to NV12.\n" - "\t --fill Fill the image by RGA to blue, green, red, when you set the option to the corresponding color.\n"); + "\t --fill Fill the image by RGA to blue, green, red, when you set the option to the corresponding color.\n" + "\t :\n" + "\t red \tFill in red.\n" + "\t blue \tFill in blue.\n" + "\t green \tFill in green.\n" + "\t \tFill in color value, red[0:7] green[8:15] blue[16:23] alpha[24:31].\n" + ); printf("=============================================================================================\n\n"); } @@ -69,7 +97,7 @@ int readArguments(int argc, char *argv[], int* parm) { { "rotate", required_argument, NULL, MODE_ROTATE_CHAR }, { "flip", required_argument, NULL, MODE_FLIP_CHAR }, { "translate", no_argument, NULL, MODE_TRANSLATE_CHAR }, - { "blend", no_argument, NULL, MODE_BLEND_CHAR }, + { "blend", optional_argument, NULL, MODE_BLEND_CHAR }, { "cvtcolor", no_argument, NULL, MODE_CVTCOLOR_CHAR }, { "fill", required_argument, NULL, MODE_FILL_CHAR }, { "while", required_argument, NULL, MODE_WHILE_CHAR }, @@ -144,6 +172,49 @@ int readArguments(int argc, char *argv[], int* parm) { case MODE_BLEND_CHAR : printf("im2d blend ..\n"); + if (optarg != NULL) { + if (strcmp(optarg, "src") == 0 ) { + printf("src mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_SRC; + } else if (strcmp(optarg, "dst") == 0) { + printf("dst mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_DST; + } else if (strcmp(optarg, "src-over") == 0) { + printf("src-over mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_SRC_OVER; + } else if (strcmp(optarg, "dst-over") == 0) { + printf("dst-over mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_DST_OVER; + } else if (strcmp(optarg, "src-in") == 0) { + printf("src-in mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_SRC_IN; + } else if (strcmp(optarg, "dst-in") == 0) { + printf("dst-in mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_DST_IN; + } else if (strcmp(optarg, "src-out") == 0) { + printf("src-out mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_SRC_OUT; + } else if (strcmp(optarg, "dst-out") == 0) { + printf("dst-out mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_DST_OUT; + } else if (strcmp(optarg, "src-atop") == 0) { + printf("src-atop mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_SRC_ATOP; + } else if (strcmp(optarg, "dst-atop") == 0) { + printf("dst-atop mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_DST_ATOP; + } else if (strcmp(optarg, "src-in") == 0) { + printf("xor mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_XOR; + } else { + printf("default to src-over mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_SRC_OVER; + } + } else { + printf("default to src-over mode ...\n"); + parm[MODE_FLIP] = IM_ALPHA_BLEND_SRC_OVER; + } + mode_code |= MODE_BLEND; return mode_code; @@ -156,8 +227,25 @@ int readArguments(int argc, char *argv[], int* parm) { case MODE_FILL_CHAR : printf("im2d fill ..\n"); - if (optarg != NULL) - parm[MODE_FILL] = readParm(optarg); + if (optarg != NULL) { + if (strcmp(optarg,"blue") == 0) { + printf("fill blue ...\n"); + parm[MODE_FILL] = BLUE_COLOR; + } else if (strcmp(optarg,"green") == 0) { + printf("fill green ...\n"); + parm[MODE_FILL] = GREEN_COLOR; + } else if (strcmp(optarg,"red") == 0) { + printf("fill red ...\n"); + parm[MODE_FILL] = RED_COLOR; + } else { + if (sscanf(optarg, "%x", &parm[MODE_FILL]) != 1) { + printf("0x%x is invaild color value\n", parm[MODE_FILL]); + parm[MODE_FILL] = -1; + goto out; + } + printf("fill 0x%x\n", parm[MODE_FILL]); + } + } if (parm[MODE_FILL] == -1) goto out; From 0c9b5f27ba0ff38153483f5e376e6d2e14e76864 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 28 Nov 2023 17:02:27 +0800 Subject: [PATCH 39/46] toolchains: add RV1106 toolchain.cmake Change-Id: I24f61e2192e29ccb314fc2d931b6e1ce9079735c Signed-off-by: Yu Qiaowei --- .../allocator_demo/cmake-linux-rv1106-1103.sh | 6 +++--- toolchains/toolchain_linux_1106.cmake | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+), 3 deletions(-) create mode 100644 toolchains/toolchain_linux_1106.cmake diff --git a/samples/allocator_demo/cmake-linux-rv1106-1103.sh b/samples/allocator_demo/cmake-linux-rv1106-1103.sh index 93a3c6d..fdfd30a 100755 --- a/samples/allocator_demo/cmake-linux-rv1106-1103.sh +++ b/samples/allocator_demo/cmake-linux-rv1106-1103.sh @@ -4,9 +4,9 @@ SCRIPT_DIR=$(cd $(dirname ${BASH_SOURCE[0]}); pwd) SAMPLES_DIR=${SCRIPT_DIR}/.. # Modify to the local toolchain path. -TOOLCHAIN_PATH=${SAMPLES_DIR}/../toolchains/toolchain_linux.cmake -LIBRGA_PATH=${SAMPLES_DIR}/../build/build_linux/install/lib -BUILD_DIR=build/build_linux +TOOLCHAIN_PATH=${SAMPLES_DIR}/../toolchains/toolchain_linux_1106.cmake +LIBRGA_PATH=${SAMPLES_DIR}/../build/build_linux_1106/install/lib +BUILD_DIR=build/build_linux_1106 BUILD_TYPE=Release rm -rf $BUILD_DIR diff --git a/toolchains/toolchain_linux_1106.cmake b/toolchains/toolchain_linux_1106.cmake new file mode 100644 index 0000000..60b5613 --- /dev/null +++ b/toolchains/toolchain_linux_1106.cmake @@ -0,0 +1,19 @@ +SET(TOOLCHAIN_HOME "/home/yqw/workspace/linux/ipc/1106/tools/linux/toolchain/arm-rockchip830-linux-uclibcgnueabihf") +SET(TOOLCHAIN_NAME "arm-rockchip830-linux-uclibcgnueabihf") + +# this is required +#SET(CMAKE_SYSTEM_NAME Linux) + +# specify the cross compiler +SET(CMAKE_C_COMPILER ${TOOLCHAIN_HOME}/bin/${TOOLCHAIN_NAME}-gcc) +SET(CMAKE_CXX_COMPILER ${TOOLCHAIN_HOME}/bin/${TOOLCHAIN_NAME}-g++) + +# where is the target environment +SET(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_HOME}) + +# search for programs in the build host directories (not necessary) +SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +# for libraries and headers in the target directories +SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + From 29d763eafe720389c739ef5ff004044294ac797f Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 28 Nov 2023 16:57:12 +0800 Subject: [PATCH 40/46] im2d_api: fix importbuffer_xx returning incorrect return values update to 1.10.0_[6] Change-Id: I675b777e9ccef181ba76b5cd073f2f8cf6de272a Signed-off-by: Yu Qiaowei --- im2d_api/im2d_version.h | 2 +- im2d_api/src/im2d_impl.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index 2ea735a..dad4b9c 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -26,7 +26,7 @@ #define RGA_API_MAJOR_VERSION 1 #define RGA_API_MINOR_VERSION 10 #define RGA_API_REVISION_VERSION 0 -#define RGA_API_BUILD_VERSION 5 +#define RGA_API_BUILD_VERSION 6 #define RGA_API_SUFFIX diff --git a/im2d_api/src/im2d_impl.cpp b/im2d_api/src/im2d_impl.cpp index d89dfe4..4503228 100644 --- a/im2d_api/src/im2d_impl.cpp +++ b/im2d_api/src/im2d_impl.cpp @@ -1374,7 +1374,7 @@ IM_API rga_buffer_handle_t rga_import_buffer(uint64_t memory, int type, uint32_t buffer_pool.size = 1; if (rga_import_buffers(&buffer_pool) != IM_STATUS_SUCCESS) - return -1; + return 0; return buffers[0].handle; } From ab8b0c377cc7ecf4cacc982a4ae44c4773d62926 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Wed, 29 Nov 2023 17:36:50 +0800 Subject: [PATCH 41/46] normal: fix normal API causing fd 0 to be close Acquire_fence_fd is valid only if acquire_fence_fd > 0 and in async mode. update to 1.10.0_[7] Change-Id: I7d215bf6a5535c56322b3b1c075f3fb9aef00a88 Signed-off-by: Yu Qiaowei --- core/NormalRga.cpp | 18 +++++++----------- im2d_api/im2d_version.h | 2 +- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/core/NormalRga.cpp b/core/NormalRga.cpp index bbc74b3..3a38240 100644 --- a/core/NormalRga.cpp +++ b/core/NormalRga.cpp @@ -61,7 +61,7 @@ int get_int_property(void) { } static void rga_set_driver_feature(struct rgaContext *ctx) { - if (rga_version_compare(ctx->mDriverVersion, (struct rga_version_t){ 1, 3, 0, {0} }) > 0) + if (rga_version_compare(ctx->mDriverVersion, (struct rga_version_t){ 1, 3, 0, {0} }) >= 0) ctx->driver_feature |= RGA_DRIVER_FEATURE_USER_CLOSE_FENCE; } @@ -1476,8 +1476,9 @@ int RgaBlit(rga_info *src, rga_info *dst, rga_info *src1) { dst->out_fence_fd = rgaReg.out_fence_fd; - if ((rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE) && - (dst->in_fence_fd >= 0)) + if (rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE && + dst->in_fence_fd > 0 && + sync_mode == RGA_BLIT_ASYNC) close(dst->in_fence_fd); return 0; @@ -1781,8 +1782,9 @@ int RgaCollorFill(rga_info *dst) { dst->out_fence_fd = rgaReg.out_fence_fd; - if ((rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE) && - (dst->in_fence_fd >= 0)) + if (rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE && + dst->in_fence_fd > 0 && + sync_mode == RGA_BLIT_ASYNC) close(dst->in_fence_fd); return 0; @@ -2401,12 +2403,6 @@ int RgaCollorPalette(rga_info *src, rga_info *dst, rga_info *lut) { return -errno; } - dst->out_fence_fd = rgaReg.out_fence_fd; - - if ((rgaCtx->driver_feature & RGA_DRIVER_FEATURE_USER_CLOSE_FENCE) && - (dst->in_fence_fd >= 0)) - close(dst->in_fence_fd); - return 0; } diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index dad4b9c..02b828a 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -26,7 +26,7 @@ #define RGA_API_MAJOR_VERSION 1 #define RGA_API_MINOR_VERSION 10 #define RGA_API_REVISION_VERSION 0 -#define RGA_API_BUILD_VERSION 6 +#define RGA_API_BUILD_VERSION 7 #define RGA_API_SUFFIX From 9392876f17258b70d1d5f9150e569d69adf6fa4f Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 30 Nov 2023 16:29:38 +0800 Subject: [PATCH 42/46] build: cmake: set internally referenced header files to the 'PRIVATE' Change-Id: I92df3ab281368819a317b71e9acb688ce2a90d54 Signed-off-by: Yu Qiaowei --- CMakeLists.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 019b7c4..d513c65 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -106,7 +106,7 @@ set(OBJECT_NAME ${PROJECT_NAME}-object) add_library(${OBJECT_NAME} OBJECT ${IM2D_SRCS}) -target_include_directories(${OBJECT_NAME} PUBLIC ${IM2D_INCLUDE}) +target_include_directories(${OBJECT_NAME} PRIVATE ${IM2D_INCLUDE}) # Some older compilers need to explicitly set this property # After setting this property, it can be used to generate a shared library set_target_properties(${OBJECT_NAME} PROPERTIES POSITION_INDEPENDENT_CODE 1) @@ -116,7 +116,7 @@ set(SHARED_LIB_NAME ${PROJECT_NAME}) add_library(${SHARED_LIB_NAME} SHARED $) -target_include_directories(${SHARED_LIB_NAME} PUBLIC ${IM2D_INCLUDE}) +target_include_directories(${SHARED_LIB_NAME} PRIVATE ${IM2D_INCLUDE}) if(NOT DEFINED IM2D_API_VERSION) set_target_properties(${SHARED_LIB_NAME} PROPERTIES @@ -133,7 +133,7 @@ set(STATIC_LIB_NAME ${PROJECT_NAME}-static) add_library(${STATIC_LIB_NAME} STATIC $) -target_include_directories(${STATIC_LIB_NAME} PUBLIC ${IM2D_INCLUDE}) +target_include_directories(${STATIC_LIB_NAME} PRIVATE ${IM2D_INCLUDE}) set_target_properties(${STATIC_LIB_NAME} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) # If cmake version is 3.5.1, FIXIT From 87765e5b2b444385fd2b006c36953d4d8000fa11 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 30 Nov 2023 16:30:57 +0800 Subject: [PATCH 43/46] samples: cvtcolor_demo: fix typo for '#include <>' Change-Id: I81aa553f3cebdf6a9f71a33e0bade58b0f6d43c8 Signed-off-by: Yu Qiaowei --- samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp b/samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp index 299af98..e9199df 100644 --- a/samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp +++ b/samples/cvtcolor_demo/src/rga_cvtcolor_gray256_demo.cpp @@ -29,7 +29,6 @@ #include #include #include -#include <> #include #include #include From 14f16d927664ce55888b72081eb1d87a02d99505 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 30 Nov 2023 18:02:33 +0800 Subject: [PATCH 44/46] samples: im2d_api_demo: build: Android.mk: fix compilation errors Change-Id: Icaf947826357f8d4669c1f6c153fa05898f51097 Signed-off-by: Yu Qiaowei --- samples/im2d_api_demo/Android.mk | 18 ++++++++++++++++++ samples/im2d_api_demo/rgaImDemo.cpp | 17 ++++++++--------- 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/samples/im2d_api_demo/Android.mk b/samples/im2d_api_demo/Android.mk index 66d18e2..ca1aff2 100644 --- a/samples/im2d_api_demo/Android.mk +++ b/samples/im2d_api_demo/Android.mk @@ -75,6 +75,24 @@ LOCAL_SRC_FILES:= \ rgaImDemo.cpp \ args.cpp +# utils +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/../utils/ \ + $(LOCAL_PATH)/../../include + +LOCAL_SRC_FILES += \ + ../utils/utils.cpp + +# allocator +LOCAL_C_INCLUDES += \ + $(LOCAL_PATH)/../utils/allocator/include \ + $(LOCAL_PATH)/../utils/3rdparty/libdrm/include \ + $(LOCAL_PATH)/../utils/3rdparty/libdrm/include/libdrm \ + +LOCAL_SRC_FILES += \ + ../utils/allocator/dma_alloc.cpp \ + ../utils/allocator/drm_alloc.cpp \ + LOCAL_MODULE:= rgaImDemo ifdef TARGET_32_BIT_SURFACEFLINGER diff --git a/samples/im2d_api_demo/rgaImDemo.cpp b/samples/im2d_api_demo/rgaImDemo.cpp index 1c097f4..7e8800f 100644 --- a/samples/im2d_api_demo/rgaImDemo.cpp +++ b/samples/im2d_api_demo/rgaImDemo.cpp @@ -65,15 +65,14 @@ int main(int argc, char* argv[]) { int mode; int parm_data[MODE_MAX] = {0}; - IM_STATUS status; - IM_USAGE rotate; - IM_USAGE flip; - im_color_t color; - - im_rect src_rect; - im_rect dst_rect; - rga_buffer_t src; - rga_buffer_t dst; + IM_USAGE rotate; + IM_USAGE flip; + im_color_t color; + + im_rect src_rect; + im_rect dst_rect; + rga_buffer_t src; + rga_buffer_t dst; rga_buffer_handle_t src_handle; rga_buffer_handle_t dst_handle; From 128ba807a3183c88108bd725bdc26b4625239f84 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 30 Nov 2023 18:08:58 +0800 Subject: [PATCH 45/46] build: meson: rgaImDemo support utils Change-Id: I2f4cd74ed7cbc5c98a7ac26a62b75275cc623e20 Signed-off-by: Yu Qiaowei --- meson.build | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/meson.build b/meson.build index 90bb8a4..be2c2e9 100644 --- a/meson.build +++ b/meson.build @@ -73,10 +73,20 @@ pkgconfig.generate( librga_demo_option = get_option('librga_demo') if librga_demo_option != 'false' demo_src = [ + 'samples/utils/utils.cpp', + 'samples/utils/allocator/dma_alloc.cpp', + 'samples/utils/allocator/drm_alloc.cpp', 'samples/im2d_api_demo/rgaImDemo.cpp', - 'samples/im2d_api_demo/args.cpp' + 'samples/im2d_api_demo/args.cpp', ] - demo_incdir = include_directories('include', 'im2d_api') + demo_incdir = include_directories( + 'include', + 'im2d_api', + 'samples/utils', + 'samples/utils/allocator/include', + 'utils/3rdparty/libdrm/include', + 'utils/3rdparty/libdrm/include/libdrm' + ) librga_dep = dependency('librga') executable( 'rgaImDemo', From d7a0a485ed6c201f882c20b3a8881e801f131385 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 1 Dec 2023 09:43:46 +0800 Subject: [PATCH 46/46] samples: utils: build: cmake: fix compile errors fix "undefined reference to dlopen'" update to 1.10.0_[8] Change-Id: I683c03c657af5b0bc93bee97f9d57a15acb5947f Signed-off-by: Yu Qiaowei --- im2d_api/im2d_version.h | 2 +- samples/utils/allocator/CMakeLists.txt | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/im2d_api/im2d_version.h b/im2d_api/im2d_version.h index 02b828a..fd9fe6e 100644 --- a/im2d_api/im2d_version.h +++ b/im2d_api/im2d_version.h @@ -26,7 +26,7 @@ #define RGA_API_MAJOR_VERSION 1 #define RGA_API_MINOR_VERSION 10 #define RGA_API_REVISION_VERSION 0 -#define RGA_API_BUILD_VERSION 7 +#define RGA_API_BUILD_VERSION 8 #define RGA_API_SUFFIX diff --git a/samples/utils/allocator/CMakeLists.txt b/samples/utils/allocator/CMakeLists.txt index e00b3fc..ba1be1b 100644 --- a/samples/utils/allocator/CMakeLists.txt +++ b/samples/utils/allocator/CMakeLists.txt @@ -13,3 +13,5 @@ target_include_directories(utils_obj ${THIRD_PARTY_PATH}/libdrm/include/libdrm ${CMAKE_CURRENT_LIST_DIR}/include ) + +target_link_libraries(utils_obj dl)