All notable changes to the "verilog-highlight" extension will be documented in this file.
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- Fixed case statements with don't cares
module temp; always @(*) begin casez(c) 5'b11111: d = 0; 5'b0000?: d = 1; 5'b1????: d = 2; 5'b010Z?: d = 3; default: d = 0; endcase end // Note: It does not work well with font ligature on // Also, some ternary expressions is broken (but the use of don't cares in ternary expression is rare) // Same code, three colorings assign e1 = c==5'h123Z??Z:4'b110?; assign e2 = c==5'h123Z?? Z:4'b110?; assign e3 = c==5'h123Z? ?Z:4'b110?; endmodule
- Allow constant expression in declaration
module temp; reg a = 'd123; // A.2.2.1 real_type and variable_type can include a constant_expression real b = 3770; // A.2.8 block_real_type and block_variable_type does not include constant_expressions, // but current implementation allows it for simplicity. endmodule
- Fix port declaration start with
input,output,inout
- Match incomplete declarations.
module test; // incomplete register declaration reg // some comments endmodule
- Fix function call in rvalue of continuous assignment
- Highlights verilog code blocks inside markdown
- Stop some keywords from being tokenized as module type
- Fix typo in keyword (medium)
- Initial release