ASAP7 + OpenRoad. ERROR: Can't open ABC output file.

[exhaust-create]

Background Work

• Yes, I searched the mailing list
• Yes, I searched prior issues
• Yes, I searched the documentation

Chipyard Version and Hash

Chipyard Release: 1.11.0

OS Setup

Ubuntu: 22.04

Other Setup

yosys Release: 0.27_4_gb58664d44

Current Behavior

I'm trying to use ASAP7 + OpenRoad to run VLSI Flow. I added the below code to the file tutorial.mk to run the VLSI Flow:

ifeq ($(tutorial),asap7-openroad)
    tech_name         ?= asap7
    CONFIG            ?= SmallBoomConfig
    TOOLS_CONF        ?= example-openroad.yml
    TECH_CONF         ?= example-asap7.yml
    DESIGN_CONFS      ?= 
    VLSI_OBJ_DIR      ?= build-asap7-openroad
    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
    # Yosys compatibility for CIRCT-generated Verilog
    ENABLE_YOSYS_FLOW  = 1
endif

I can produce the file hammer.d after running make buildfile tutorial=asap7-openroad, but when I run make syn tutorial=asap7-openroad, an error always occurs when the below step is running:

689.2. Extracting gate netlist of module `\ALU' to `/tmp/yosys-abc-fmM0q5/input.blif'..
Extracted 1751 gates and 1884 wires to a netlist network with 133 inputs and 64 outputs.

and the ERROR is:

689.2.1. Executing ABC.
ERROR: Can't open ABC output file `/tmp/yosys-abc-fmM0q5/output.blif'.
[synthesis] Did not run write_regs
Traceback (most recent call last):
  File "/home/cmj/chipyard/vlsi/./example-vlsi", line 71, in <module>
    ExampleDriver().main()
  File "/home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/vlsi/cli_driver.py", line 1725, in main
    sys.exit(self.run_main_parsed(vars(parser.parse_args(args))))
  File "/home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/vlsi/cli_driver.py", line 1630, in run_main_parsed
    output_config = action_func(driver, errors.append)  # type: Optional[dict]
  File "/home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/vlsi/cli_driver.py", line 592, in action
    success, output = driver.run_synthesis(
  File "/home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/vlsi/driver.py", line 930, in run_synthesis
    run_succeeded = self.syn_tool.run(hooks_to_use)
  File "/home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/vlsi/hammer_tool.py", line 118, in run
    return self.fill_outputs()
  File "/home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/synthesis/yosys/__init__.py", line 91, in fill_outputs
    raise ValueError("Output mapped verilog %s not found" % (mapped_v)) # better error?
ValueError: Output mapped verilog /home/cmj/chipyard/vlsi/build-asap7-openroad/chipyard.harness.TestHarness.SmallBoomConfig-ChipTop/syn-rundir/ChipTop.mapped.v not found
make: *** [/home/cmj/chipyard/vlsi/build-asap7-openroad/chipyard.harness.TestHarness.SmallBoomConfig-ChipTop/hammer.d:73: /home/cmj/chipyard/vlsi/build-asap7-openroad/chipyard.harness.TestHarness.SmallBoomConfig-ChipTop/syn-rundir/syn-output-full.json] Error 1

I have tried the method like The-OpenROAD-Project/OpenLane#123 or The-OpenROAD-Project/OpenLane#1523 to add a command like set ::env(SYNTH_STRATEGY) {DELAY 2} before the synthesis step syn_generic in the syn.tcl file, but it doesn't work.

Additionally, the director /tmp is mounted on /, and there is still 62G available.

Expected Behavior

How to resolve this problem?
What is the matter with this problem?

Other Information

No response

[exhaust-create]

I entered into the folder /tmp/yosys-abc-fmM0q5 and use yosys-abc -c 'source abc.script' to check the error details. The full error is shown below:

+ read_blif /tmp/yosys-abc-bUMBbk/input.blif 
+ read_lib -w /home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/technology/asap7/sram_compiler/memories/lib/SRAM1RW4096x8_lib/SRAM1RW4096x8_PVT_0P63V_100C.lib 
Parsing finished successfully.  Parsing time =     0.00 sec
Scl_LibertyReadGenlib() skipped cell "SRAM1RW4096x8" due to dont_use attribute.
Library "SRAM1RW4096x8_PVT_0P63V_100C" from "/home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/technology/asap7/sram_compiler/memories/lib/SRAM1RW4096x8_lib/SRAM1RW4096x8_PVT_0P63V_100C.lib" has 0 cells (0 skipped: 0 seq; 0 tri-state; 0 no func; 1 dont_use).  Time =     0.00 sec
Memory =    0.03 MB. Time =     0.00 sec
Library with only 0 cell classes cannot be used.
+ read_constr -v /home/cmj/chipyard/vlsi/build-asap7-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/syn-rundir/ChipTop.mapped.sdc 
+ strash 
+ &get -n 
+ &fraig -x 
+ &put 
+ scorr 
Warning: The network is combinational (run "fraig" or "fraig_sweep").
+ dc2 
+ dretime 
+ retime -o -D 1000 
+ strash 
+ &get -n 
+ &dch -f 
+ &nf -D 1000 
Error: Current library is not available.
** cmd error: aborting 'source abc.script'

I applied this setup on TinyRocket and the same error occured. Then I compared the temporary files generated by example "sky130-openroad", and the temp file showed that instead of reading a SRAM .lib file as a whitebox:

read_lib -w /home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/technology/asap7/sram_compiler/memories/lib/SRAM1RW4096x8_lib/SRAM1RW4096x8_PVT_0P63V_100C.lib

it read pdk's .lib file as a whitebox:

read_lib -w "/home/cmj/sky130/conda-sky130/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"

I don't know if this error matters with Hammer or just Yosys & ABC ?

[exhaust-create]

Maybe I know where the problem is. It is not about the Yosys & ABC. It is about how to choose the .lib file by the Hammer. When using ASAP7 + Yosys to produce syn.tcl, the liberty file for abc is set as below:

abc -D 50000 \
    -constr "/home/cmj/chipyard/vlsi/build-asap7-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/syn-rundir/ChipTop.mapped.sdc" \
    -liberty "/home/cmj/chipyard/.conda-env/lib/python3.10/site-packages/hammer/technology/asap7/sram_compiler/memories/lib/SRAM1RW4096x8_lib/SRAM1RW4096x8_PVT_0P63V_100C.lib" \
    -showtmp \
    -nocleanup

but for the sky130 + Yosys, the counterpart in syn.tcl will be produced as:

abc -D 50000 \
    -constr "/home/cmj/chipyard/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/syn-rundir/ChipTop.mapped.sdc" \
    -liberty "/home/cmj/sky130/conda-sky130/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" \
    -showtmp \
    -nocleanup

So could somebody tell me how to change the liberty file in the syn.tcl?

[exhaust-create]

I have solved this problem. It's too damn hard!

Because ASAP7 has multiple files for multiple gates, I had to merge SIMPLE, OA, AO, and INVBUF into a .lib file with ABC. The command I used is read_lib -dwm <file_1> <file_2> for sequential emergence (the generated file's name is ended by "_temp.lib"). Then I used gzip to compress the merged liberty file which was named "asap7sc7p5t_ALL_LOGIC_RVT_TT_NLDM_201020.lib" by myself and moved this .gz file to asap7sc7p5t_27/LIB/NLDM/. To let the Hammer recognize this file, I added the below codes in the python file hammer/technology/asap7/asap7.tech.json:

# Add the codes under the "libraries" item.
{
    "nldm_liberty_file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_ALL_LOGIC_RVT_TT_nldm_201020.lib.gz",
    "lef_file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
    "spice_file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
    "gds_file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
    "qrc_techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
    "spice model file": {
    "path": "$PDK/models/hspice/7nm_TT.pm"
    },
    "corner": {
    "nmos": "typical",
    "pmos": "typical",
    "temperature": "25 C"
    },
    "supplies": {
    "VDD": "0.70 V",
    "GND": "0 V"
    },
    "provides": [
    {
        "lib_type": "stdcell",
        "vt": "RVT"
    }
    ]
},

Also in the file hammer/synthesis/yosys/__init__.py, I changed the function syn_map(self) to pick the ALL_LOGIC liberty file for ABC:

def syn_map(self) -> bool:

  ######## New Codes Begin ##########
  # Changed by Mingjun CHENG
  tech = hammer_tech.HammerTechnology.get_setting(self,"vlsi.core.technology") # type: str
  # If the tech is ASAP7, then keep all RVT_TT lib except for SEQ.
  if tech.split(".")[-1] == "asap7":
      # logic_RVT_TT = [stdcell for stdcell in self.liberty_files_tt.split() if 'RVT_TT' in stdcell] # type: List[]
      # logic_RVT_TT = [stdcell for stdcell in logic_RVT_TT if "SEQ" not in stdcell]
      # Because I have merge SIMPLE, AO, OA, and INVBUF into a file, so I use the below method to flter .lib.
      logic_RVT_TT = [stdcell for stdcell in self.liberty_files_tt.split() if 'ALL_LOGIC_RVT_TT' in stdcell]
      # Flatten
      liberty_for_abc = " ".join(logic_RVT_TT)
  else:
      # Only consider SKY130 if not ASAP7 
      liberty_for_abc = self.liberty_files_tt.split()[0]
  ######## New Codes End ###########
  
  self.block_append(f"""
  abc ... \\
  ... \\
  -liberty "{liberty_for_abc}" \\
  ...
  """)
  ...

After doing these, I can use Yosys with ASAP7 to synthesize the designs.