From bde95ebe664a694b23516199f99b65fc24436e65 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 17:16:01 -0700 Subject: [PATCH 01/13] Fix par timing flow for innovus/tempus --- hammer/generate_properties.py | 5 ++++- hammer/par/innovus/__init__.py | 26 +++++++++++++++++++++++++- hammer/timing/tempus/__init__.py | 5 +++-- hammer/timing/tempus/defaults.yml | 2 +- hammer/vlsi/driver.py | 4 ++-- hammer/vlsi/hammer_vlsi_impl.py | 1 + 6 files changed, 36 insertions(+), 7 deletions(-) diff --git a/hammer/generate_properties.py b/hammer/generate_properties.py index 532a48ef3..5c7007390 100755 --- a/hammer/generate_properties.py +++ b/hammer/generate_properties.py @@ -145,6 +145,7 @@ def main(args) -> int: "(optional) output ILM information for hierarchical mode"), InterfaceVar("output_gds", "str", "path to the output GDS file"), InterfaceVar("output_netlist", "str", "path to the output netlist file"), + InterfaceVar("output_physical_netlist", "str", "path to the output physical netlist file"), InterfaceVar("output_sim_netlist", "str", "path to the output simulation netlist file"), InterfaceVar("hcells_list", "List[str]", "list of cells to explicitly map hierarchically in LVS"), @@ -249,7 +250,9 @@ def main(args) -> int: InterfaceVar("spefs", "Optional[List]", "(optional) list of SPEF files"), InterfaceVar("sdf_file", "Optional[str]", - "(optional) input SDF file") + "(optional) input SDF file"), + InterfaceVar("def_file", "Optional[str]", + "(optional) input DEF file") ], outputs=[] ) diff --git a/hammer/par/innovus/__init__.py b/hammer/par/innovus/__init__.py index 0c1b95593..99988342b 100644 --- a/hammer/par/innovus/__init__.py +++ b/hammer/par/innovus/__init__.py @@ -32,6 +32,7 @@ def export_config_outputs(self) -> Dict[str, Any]: outputs["par.outputs.seq_cells"] = self.output_seq_cells outputs["par.outputs.all_regs"] = self.output_all_regs outputs["par.outputs.sdf_file"] = self.output_sdf_path + outputs["par.outputs.def_file"] = self.output_def_path outputs["par.outputs.spefs"] = self.output_spef_paths return outputs @@ -114,6 +115,10 @@ def output_gds_filename(self) -> str: def output_netlist_filename(self) -> str: return os.path.join(self.run_dir, "{top}.lvs.v".format(top=self.top_module)) + @property + def output_physical_netlist_filename(self) -> str: + return os.path.join(self.run_dir, "{top}.physical.v".format(top=self.top_module)) + @property def output_sim_netlist_filename(self) -> str: return os.path.join(self.run_dir, "{top}.sim.v".format(top=self.top_module)) @@ -130,6 +135,10 @@ def all_cells_path(self) -> str: def output_sdf_path(self) -> str: return os.path.join(self.run_dir, "{top}.par.sdf".format(top=self.top_module)) + @property + def output_def_path(self) -> str: + return os.path.join(self.run_dir, "{top}.def".format(top=self.top_module)) + @property def output_spef_paths(self) -> List[str]: corners = self.get_mmmc_corners() @@ -771,13 +780,20 @@ def write_netlist(self) -> bool: if pwr_gnd_net.tie is not None: self.verbose_append("connect_global_net {tie} -type net -net_base_name {net}".format(tie=pwr_gnd_net.tie, net=pwr_gnd_net.name)) - # Output the Verilog netlist for the design and include physical cells (-phys) like decaps and fill + # Output a flattened Verilog netlist for the design and include physical cells (-phys) like decaps and fill self.verbose_append("write_netlist {netlist} -top_module_first -top_module {top} -exclude_leaf_cells -phys -flat -exclude_insts_of_cells {{ {pcells} }} ".format( netlist=self.output_netlist_filename, top=self.top_module, pcells=" ".join(self.get_physical_only_cells()) )) + # Output a non-flattened Verilog netlist with physical instances + self.verbose_append("write_netlist {netlist} -top_module_first -top_module {top} -exclude_leaf_cells -phys -exclude_insts_of_cells {{ {pcells} }} ".format( + netlist=self.output_physical_netlist_filename, + top=self.top_module, + pcells=" ".join(self.get_physical_only_cells()) + )) + self.verbose_append("write_netlist {netlist} -top_module_first -top_module {top} -exclude_leaf_cells -exclude_insts_of_cells {{ {pcells} }} ".format( netlist=self.output_sim_netlist_filename, top=self.top_module, @@ -848,6 +864,11 @@ def write_gds(self) -> bool: )) return True + def write_def(self) -> bool: + self.verbose_append("write_def {def_file} -floorplan -netlist -routing".format(def_file=self.output_def_path)) + + return True + def write_sdf(self) -> bool: if self.hierarchical_mode.is_nonleaf_hierarchical(): self.verbose_append("flatten_ilm") @@ -936,6 +957,9 @@ def write_design(self) -> bool: # Write netlist self.write_netlist() + # Write DEF + self.write_def() + # GDS streamout. self.write_gds() diff --git a/hammer/timing/tempus/__init__.py b/hammer/timing/tempus/__init__.py index 2d32b4f67..6f6343819 100644 --- a/hammer/timing/tempus/__init__.py +++ b/hammer/timing/tempus/__init__.py @@ -130,7 +130,7 @@ def init_design(self) -> bool: for ilm in self.get_input_ilms(): # Assumes that the ILM was created by Innovus (or at least the file/folder structure). # TODO: support non-Innovus hierarchical (read netlists, etc.) - verbose_append("read_ilm -cell {module} -directory {dir}".format(dir=ilm.dir, module=ilm.module)) + verbose_append("set_ilm -cell {module} -in_dir {dir}".format(dir=ilm.dir, module=ilm.module)) # Read power intent if self.get_setting("vlsi.inputs.power_spec_mode") != "empty": @@ -168,7 +168,8 @@ def init_design(self) -> bool: verbose_append("init_design") - # TODO: Optionally read additional DEF or OA physical data + if self.def_file is not None: + verbose_append("read_def " + os.path.join(os.getcwd(), self.def_file)) # Set some default analysis settings for max accuracy diff --git a/hammer/timing/tempus/defaults.yml b/hammer/timing/tempus/defaults.yml index 2425bf282..03e784b1c 100644 --- a/hammer/timing/tempus/defaults.yml +++ b/hammer/timing/tempus/defaults.yml @@ -8,7 +8,7 @@ timing.tempus: # Tempus version to use # Used to locate the binary - e.g. the '211_ISR3' in ${cadence.cadence_home}/SSV/SSV211_ISR3/bin/tempus - version: "211_ISR3" + version: "231" # Enable signal integrity delay and glitch analysis # Note: your tech libs should have noise models! diff --git a/hammer/vlsi/driver.py b/hammer/vlsi/driver.py index 8b2862bdd..116ddee7e 100644 --- a/hammer/vlsi/driver.py +++ b/hammer/vlsi/driver.py @@ -1165,13 +1165,13 @@ def par_output_to_timing_input(output_dict: dict) -> Optional[dict]: or None if output_dict was invalid """ try: - input_files = deeplist([output_dict["par.outputs.output_netlist"]]) + input_files = deeplist([output_dict["par.outputs.output_physical_netlist"]]) result = { "timing.inputs.input_files": input_files, "timing.inputs.input_files_meta": "append", "timing.inputs.top_module": output_dict["par.inputs.top_module"], "timing.inputs.spefs": output_dict["par.outputs.spefs"], - "timing.inputs.sdf_file": output_dict["par.outputs.sdf_file"], + "timing.inputs.def": output_dict.get("par.outputs.def_file", None), "vlsi.builtins.is_complete": False } # type: Dict[str, Any] return result diff --git a/hammer/vlsi/hammer_vlsi_impl.py b/hammer/vlsi/hammer_vlsi_impl.py index 7d92e1e74..d3fa11671 100644 --- a/hammer/vlsi/hammer_vlsi_impl.py +++ b/hammer/vlsi/hammer_vlsi_impl.py @@ -397,6 +397,7 @@ def export_config_outputs(self) -> Dict[str, Any]: outputs["vlsi.inputs.ilms_meta"] = "append" # to coalesce ILMs for entire hierarchical tree outputs["par.outputs.output_gds"] = str(self.output_gds) outputs["par.outputs.output_netlist"] = str(self.output_netlist) + outputs["par.outputs.output_physical_netlist"] = str(self.output_physical_netlist) outputs["par.outputs.output_sim_netlist"] = str(self.output_sim_netlist) outputs["par.outputs.hcells_list"] = list(self.hcells_list) outputs["par.outputs.seq_cells"] = self.output_seq_cells From 27994d36a4638264173b4776ba87f479c11aa664 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 17:34:51 -0700 Subject: [PATCH 02/13] default to output netlist if needed --- hammer/vlsi/driver.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hammer/vlsi/driver.py b/hammer/vlsi/driver.py index 116ddee7e..3886377a0 100644 --- a/hammer/vlsi/driver.py +++ b/hammer/vlsi/driver.py @@ -1165,7 +1165,7 @@ def par_output_to_timing_input(output_dict: dict) -> Optional[dict]: or None if output_dict was invalid """ try: - input_files = deeplist([output_dict["par.outputs.output_physical_netlist"]]) + input_files = deeplist([output_dict.get("par.outputs.output_physical_netlist", output_dict.get("par.outputs.output_netlist"))]) result = { "timing.inputs.input_files": input_files, "timing.inputs.input_files_meta": "append", From 1042fe1871851523cc6470784d3ade2c48f170bc Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 17:38:19 -0700 Subject: [PATCH 03/13] add default value --- hammer/common/cadence/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hammer/common/cadence/__init__.py b/hammer/common/cadence/__init__.py index d77fa46bf..6e358f10e 100644 --- a/hammer/common/cadence/__init__.py +++ b/hammer/common/cadence/__init__.py @@ -150,7 +150,7 @@ def append_mmmc(cmd: str) -> None: self.run_executable(["touch", blank_sdc]) sdc_files_arg = "-sdc_files {{ {} }}".format(blank_sdc) if self.hierarchical_mode.is_nonleaf_hierarchical(): - ilm_sdcs = reduce_list_str(add_lists, list(map(lambda ilm: ilm.sdcs, self.get_input_ilms()))) # type: List[str] + ilm_sdcs = reduce_list_str(add_lists, list(map(lambda ilm: ilm.sdcs, self.get_input_ilms())), []) # type: List[str] ilm_sdc_files_arg = "-ilm_sdc_files [list {sdc_files}]".format( sdc_files=" ".join(ilm_sdcs)) else: From b17ffef9670910afd5d4aee6fc7375426ff085bf Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 17:40:34 -0700 Subject: [PATCH 04/13] run generate properties --- hammer/vlsi/hammer_vlsi_impl.py | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hammer/vlsi/hammer_vlsi_impl.py b/hammer/vlsi/hammer_vlsi_impl.py index d3fa11671..4b3711eea 100644 --- a/hammer/vlsi/hammer_vlsi_impl.py +++ b/hammer/vlsi/hammer_vlsi_impl.py @@ -512,6 +512,26 @@ def output_netlist(self, value: str) -> None: self.attr_setter("_output_netlist", value) + @property + def output_physical_netlist(self) -> str: + """ + Get the path to the output physical netlist file. + + :return: The path to the output physical netlist file. + """ + try: + return self.attr_getter("_output_physical_netlist", None) + except AttributeError: + raise ValueError("Nothing set for the path to the output physical netlist file yet") + + @output_physical_netlist.setter + def output_physical_netlist(self, value: str) -> None: + """Set the path to the output physical netlist file.""" + if not (isinstance(value, str)): + raise TypeError("output_physical_netlist must be a str") + self.attr_setter("_output_physical_netlist", value) + + @property def output_sim_netlist(self) -> str: """ @@ -2086,6 +2106,26 @@ def sdf_file(self, value: Optional[str]) -> None: self.attr_setter("_sdf_file", value) + @property + def def_file(self) -> Optional[str]: + """ + Get the (optional) input DEF file. + + :return: The (optional) input DEF file. + """ + try: + return self.attr_getter("_def_file", None) + except AttributeError: + return None + + @def_file.setter + def def_file(self, value: Optional[str]) -> None: + """Set the (optional) input DEF file.""" + if not (isinstance(value, str) or (value is None)): + raise TypeError("def_file must be a Optional[str]") + self.attr_setter("_def_file", value) + + ### Outputs ### ### END Generated interface HammerTimingTool ### From 1a128ac7213a252c4d2d9d268711ad2b96209ebd Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 18:06:58 -0700 Subject: [PATCH 05/13] add update constraint mode to tempus flow --- hammer/common/cadence/__init__.py | 10 ++++------ hammer/timing/tempus/__init__.py | 1 + hammer/vlsi/driver.py | 1 + 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hammer/common/cadence/__init__.py b/hammer/common/cadence/__init__.py index 6e358f10e..e64bd6afc 100644 --- a/hammer/common/cadence/__init__.py +++ b/hammer/common/cadence/__init__.py @@ -13,6 +13,7 @@ class CadenceTool(HasSDCSupport, HasCPFSupport, HasUPFSupport, TCLTool, HammerTool): """Mix-in trait with functions useful for Cadence-based tools.""" + constraint_mode = "my_constraint_mode" @property def env_vars(self) -> Dict[str, str]: @@ -127,9 +128,6 @@ def generate_mmmc_script(self) -> str: def append_mmmc(cmd: str) -> None: self.verbose_tcl_append(cmd, mmmc_output) - # Create an Innovus constraint mode. - constraint_mode = "my_constraint_mode" - sdc_files = self.generate_sdc_files() # Append any custom SDC files. @@ -156,7 +154,7 @@ def append_mmmc(cmd: str) -> None: else: ilm_sdc_files_arg = "" append_mmmc("create_constraint_mode -name {name} {sdc_files_arg} {ilm_sdc_files_arg}".format( - name=constraint_mode, + name=self.constraint_mode, sdc_files_arg=sdc_files_arg, ilm_sdc_files_arg=ilm_sdc_files_arg )) @@ -205,7 +203,7 @@ def append_mmmc(cmd: str) -> None: # Next, create the analysis views append_mmmc("create_analysis_view -name {name}_view -delay_corner {name}_delay -constraint_mode {constraint}".format( name=corner_name, - constraint=constraint_mode + constraint=self.constraint_mode )) # Finally, apply the analysis view. @@ -251,7 +249,7 @@ def append_mmmc(cmd: str) -> None: # Next, create an Innovus analysis view. analysis_view_name = "my_view" append_mmmc("create_analysis_view -name {name} -delay_corner {corner} -constraint_mode {constraint}".format( - name=analysis_view_name, corner=delay_corner_name, constraint=constraint_mode)) + name=analysis_view_name, corner=delay_corner_name, constraint=self.constraint_mode)) # Finally, apply the analysis view. # TODO: introduce different views of setup/hold and true multi-corner append_mmmc("set_analysis_view -setup {{ {setup_view} }} -hold {{ {hold_view} }}".format( diff --git a/hammer/timing/tempus/__init__.py b/hammer/timing/tempus/__init__.py index 6f6343819..87e06a5b2 100644 --- a/hammer/timing/tempus/__init__.py +++ b/hammer/timing/tempus/__init__.py @@ -101,6 +101,7 @@ def init_design(self) -> bool: mmmc_path = os.path.join(self.run_dir, "mmmc.tcl") self.write_contents_to_path(self.generate_mmmc_script(), mmmc_path) verbose_append("read_mmmc {mmmc_path}".format(mmmc_path=mmmc_path)) + verbose_append("update_constraint_mode -name {name} -ilm_sdc_files {post_synth_sdc}".format(name=self.constraint_mode, post_synth_sdc=self.post_synth_sdc)) # Read physical LEFs (optional in Tempus) lef_files = self.technology.read_libs([ diff --git a/hammer/vlsi/driver.py b/hammer/vlsi/driver.py index 3886377a0..431818033 100644 --- a/hammer/vlsi/driver.py +++ b/hammer/vlsi/driver.py @@ -1170,6 +1170,7 @@ def par_output_to_timing_input(output_dict: dict) -> Optional[dict]: "timing.inputs.input_files": input_files, "timing.inputs.input_files_meta": "append", "timing.inputs.top_module": output_dict["par.inputs.top_module"], + "timing.inputs.post_synth_sdc": output_dict["par.inputs.post_synth_sdc"], "timing.inputs.spefs": output_dict["par.outputs.spefs"], "timing.inputs.def": output_dict.get("par.outputs.def_file", None), "vlsi.builtins.is_complete": False From d00800bd277aff7a4d78d037d33b34d3b7a7675d Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 18:27:22 -0700 Subject: [PATCH 06/13] pass timing inputs to timing tool --- hammer/vlsi/driver.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hammer/vlsi/driver.py b/hammer/vlsi/driver.py index 431818033..5c5986dcc 100644 --- a/hammer/vlsi/driver.py +++ b/hammer/vlsi/driver.py @@ -757,6 +757,9 @@ def set_up_timing_tool(self, timing_tool: HammerTimingTool, missing_inputs = True if missing_inputs: return False + timing_tool.post_synth_sdc = self.database.get_setting("timing.inputs.post_synth_sdc") + timing_tool.spefs = self.database.get_setting("timing.inputs.spefs") + timing_tool.def_file = self.database.get_setting("timing.inputs.def_file") self.timing_tool = timing_tool @@ -1172,7 +1175,7 @@ def par_output_to_timing_input(output_dict: dict) -> Optional[dict]: "timing.inputs.top_module": output_dict["par.inputs.top_module"], "timing.inputs.post_synth_sdc": output_dict["par.inputs.post_synth_sdc"], "timing.inputs.spefs": output_dict["par.outputs.spefs"], - "timing.inputs.def": output_dict.get("par.outputs.def_file", None), + "timing.inputs.def_file": output_dict.get("par.outputs.def_file", None), "vlsi.builtins.is_complete": False } # type: Dict[str, Any] return result From 6b01b83da43d3a53342073bd7c85bc942b255189 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 18:35:38 -0700 Subject: [PATCH 07/13] use full tree ilms --- hammer/timing/tempus/__init__.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hammer/timing/tempus/__init__.py b/hammer/timing/tempus/__init__.py index 87e06a5b2..a47335941 100644 --- a/hammer/timing/tempus/__init__.py +++ b/hammer/timing/tempus/__init__.py @@ -128,7 +128,7 @@ def init_design(self) -> bool: if self.hierarchical_mode.is_nonleaf_hierarchical(): # Read ILMs. - for ilm in self.get_input_ilms(): + for ilm in self.get_input_ilms(full_tree=True): # Assumes that the ILM was created by Innovus (or at least the file/folder structure). # TODO: support non-Innovus hierarchical (read netlists, etc.) verbose_append("set_ilm -cell {module} -in_dir {dir}".format(dir=ilm.dir, module=ilm.module)) @@ -139,6 +139,11 @@ def init_design(self) -> bool: for l in self.generate_power_spec_commands(): verbose_append(l) + verbose_append("init_design") + + if self.def_file is not None: + verbose_append("read_def " + os.path.join(os.getcwd(), self.def_file)) + # Read parasitics if self.spefs is not None: # post-P&R corners = self.get_mmmc_corners() @@ -167,11 +172,9 @@ def init_design(self) -> bool: if self.sdf_file is not None: verbose_append("read_sdf " + os.path.join(os.getcwd(), self.sdf_file)) - verbose_append("init_design") - - if self.def_file is not None: - verbose_append("read_def " + os.path.join(os.getcwd(), self.def_file)) - + if self.hierarchical_mode.is_nonleaf_hierarchical() and len(self.get_input_ilms(full_tree=True)): + verbose_append("read_ilm") + verbose_append("flatten_ilm") # Set some default analysis settings for max accuracy # Clock path pessimism removal From c9b7e9a2bc58ddb25d222ea4c83bf5e7486788e6 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 19:02:28 -0700 Subject: [PATCH 08/13] use full tree ilms --- hammer/timing/tempus/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hammer/timing/tempus/__init__.py b/hammer/timing/tempus/__init__.py index a47335941..f88ea67f5 100644 --- a/hammer/timing/tempus/__init__.py +++ b/hammer/timing/tempus/__init__.py @@ -108,7 +108,7 @@ def init_design(self) -> bool: hammer_tech.filters.lef_filter ], hammer_tech.HammerTechnologyUtils.to_plain_item) if self.hierarchical_mode.is_nonleaf_hierarchical(): - ilm_lefs = list(map(lambda ilm: ilm.lef, self.get_input_ilms())) + ilm_lefs = list(map(lambda ilm: ilm.lef, self.get_input_ilms(full_tree=True))) lef_files.extend(ilm_lefs) verbose_append("read_physical -lef {{ {files} }}".format( files=" ".join(lef_files) From aac99ece449a26ccceb951767321c4052a014dc1 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 20:09:50 -0700 Subject: [PATCH 09/13] make physical netlist optional --- hammer/generate_properties.py | 2 +- hammer/vlsi/hammer_vlsi_impl.py | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hammer/generate_properties.py b/hammer/generate_properties.py index 5c7007390..89414ae82 100755 --- a/hammer/generate_properties.py +++ b/hammer/generate_properties.py @@ -145,7 +145,7 @@ def main(args) -> int: "(optional) output ILM information for hierarchical mode"), InterfaceVar("output_gds", "str", "path to the output GDS file"), InterfaceVar("output_netlist", "str", "path to the output netlist file"), - InterfaceVar("output_physical_netlist", "str", "path to the output physical netlist file"), + InterfaceVar("output_physical_netlist", "Optional[str]", "(optional) path to the output physical netlist file"), InterfaceVar("output_sim_netlist", "str", "path to the output simulation netlist file"), InterfaceVar("hcells_list", "List[str]", "list of cells to explicitly map hierarchically in LVS"), diff --git a/hammer/vlsi/hammer_vlsi_impl.py b/hammer/vlsi/hammer_vlsi_impl.py index 4b3711eea..695a6490a 100644 --- a/hammer/vlsi/hammer_vlsi_impl.py +++ b/hammer/vlsi/hammer_vlsi_impl.py @@ -513,22 +513,22 @@ def output_netlist(self, value: str) -> None: @property - def output_physical_netlist(self) -> str: + def output_physical_netlist(self) -> Optional[str]: """ - Get the path to the output physical netlist file. + Get the (optional) path to the output physical netlist file. - :return: The path to the output physical netlist file. + :return: The (optional) path to the output physical netlist file. """ try: return self.attr_getter("_output_physical_netlist", None) except AttributeError: - raise ValueError("Nothing set for the path to the output physical netlist file yet") + return None @output_physical_netlist.setter - def output_physical_netlist(self, value: str) -> None: - """Set the path to the output physical netlist file.""" - if not (isinstance(value, str)): - raise TypeError("output_physical_netlist must be a str") + def output_physical_netlist(self, value: Optional[str]) -> None: + """Set the (optional) path to the output physical netlist file.""" + if not (isinstance(value, str) or (value is None)): + raise TypeError("output_physical_netlist must be a Optional[str]") self.attr_setter("_output_physical_netlist", value) From 909da594ee0e56765aec680ac95b1ee0b78678c7 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 20:16:24 -0700 Subject: [PATCH 10/13] remove extraneous call to get --- hammer/vlsi/driver.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hammer/vlsi/driver.py b/hammer/vlsi/driver.py index 5c5986dcc..a37805455 100644 --- a/hammer/vlsi/driver.py +++ b/hammer/vlsi/driver.py @@ -1168,7 +1168,7 @@ def par_output_to_timing_input(output_dict: dict) -> Optional[dict]: or None if output_dict was invalid """ try: - input_files = deeplist([output_dict.get("par.outputs.output_physical_netlist", output_dict.get("par.outputs.output_netlist"))]) + input_files = deeplist([output_dict.get("par.outputs.output_physical_netlist", output_dict["par.outputs.output_netlist")]]) result = { "timing.inputs.input_files": input_files, "timing.inputs.input_files_meta": "append", From 658edab1a1a7ebb39f786c1fb64cbe5426fd1443 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 20:24:47 -0700 Subject: [PATCH 11/13] remove use of my constraint mode --- hammer/common/cadence/__init__.py | 1 + hammer/par/innovus/__init__.py | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hammer/common/cadence/__init__.py b/hammer/common/cadence/__init__.py index e64bd6afc..e805e516a 100644 --- a/hammer/common/cadence/__init__.py +++ b/hammer/common/cadence/__init__.py @@ -13,6 +13,7 @@ class CadenceTool(HasSDCSupport, HasCPFSupport, HasUPFSupport, TCLTool, HammerTool): """Mix-in trait with functions useful for Cadence-based tools.""" + constraint_mode = "my_constraint_mode" @property diff --git a/hammer/par/innovus/__init__.py b/hammer/par/innovus/__init__.py index 99988342b..4d61623e5 100644 --- a/hammer/par/innovus/__init__.py +++ b/hammer/par/innovus/__init__.py @@ -563,8 +563,8 @@ def place_opt_design(self) -> bool: if self.hierarchical_mode.is_nonleaf_hierarchical(): self.verbose_append(''' flatten_ilm - update_constraint_mode -name my_constraint_mode -ilm_sdc_files {sdc} - '''.format(sdc=self.post_synth_sdc), clean=True) + update_constraint_mode -name {name} -ilm_sdc_files {sdc} + '''.format(name=self.constraint_mode, sdc=self.post_synth_sdc), clean=True) # Use place_opt_design V2 (POD-Turbo). Option must be explicitly set only in 22.1. if self.version() >= self.version_number("221") and self.version() < self.version_number("231"): From d5a2660e910e4874f8bfc406f406f8a07a8b91c3 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 25 Apr 2024 20:28:19 -0700 Subject: [PATCH 12/13] typo --- hammer/vlsi/driver.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hammer/vlsi/driver.py b/hammer/vlsi/driver.py index a37805455..e021d1483 100644 --- a/hammer/vlsi/driver.py +++ b/hammer/vlsi/driver.py @@ -1168,7 +1168,7 @@ def par_output_to_timing_input(output_dict: dict) -> Optional[dict]: or None if output_dict was invalid """ try: - input_files = deeplist([output_dict.get("par.outputs.output_physical_netlist", output_dict["par.outputs.output_netlist")]]) + input_files = deeplist([output_dict.get("par.outputs.output_physical_netlist", output_dict["par.outputs.output_netlist"])]) result = { "timing.inputs.input_files": input_files, "timing.inputs.input_files_meta": "append", From bfc11bed7c8a3f2bc6af6d785e80de1b6666d482 Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Sun, 2 Feb 2025 22:23:37 -0800 Subject: [PATCH 13/13] sdcs read in by read_mmmc in mmmc flow --- hammer/timing/tempus/__init__.py | 1 - 1 file changed, 1 deletion(-) diff --git a/hammer/timing/tempus/__init__.py b/hammer/timing/tempus/__init__.py index f88ea67f5..a5b24ee6e 100644 --- a/hammer/timing/tempus/__init__.py +++ b/hammer/timing/tempus/__init__.py @@ -101,7 +101,6 @@ def init_design(self) -> bool: mmmc_path = os.path.join(self.run_dir, "mmmc.tcl") self.write_contents_to_path(self.generate_mmmc_script(), mmmc_path) verbose_append("read_mmmc {mmmc_path}".format(mmmc_path=mmmc_path)) - verbose_append("update_constraint_mode -name {name} -ilm_sdc_files {post_synth_sdc}".format(name=self.constraint_mode, post_synth_sdc=self.post_synth_sdc)) # Read physical LEFs (optional in Tempus) lef_files = self.technology.read_libs([