From 2ece93b0a10187550d82d139bda1032e63e4507c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 12 Aug 2024 14:15:11 -0700 Subject: [PATCH] Mention B-ext support in README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 127d99f..2846811 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ Shuttle: A Rocket-based Superscalar In-order RISC-V Core ======================================================== -Shuttle is a Rocket-based superscalar in-order RISC-V core, supporting the base RV64IMAFDC instruction set with supervisor and user-mode. +Shuttle is a Rocket-based superscalar in-order RISC-V core, supporting the base RV64IMAFDCB instruction set with supervisor and user-mode. Shuttle is a 6-stage core that can be configured to be dual, three, or quad-issue, although dual-issue is the most sensible design point. Shuttle is *not* designed to meet any power, performance, or area targets. It exists purely as a demonstrative example of another RISC-V CPU design point.