Known-good Commit and FPGA Image

[bastibl]

I used the print example program that is part of the Rust reconstructor project to compare my signal captures with the sample captures (reconstructor/test-data/iqzip/ble-advertising.iqz). Reconstructing the sample works but my recordings are garbage. I noticed a difference between the recordings that suggests that something close to the hardware is different: For both FFT Data and Averages, the indexes of the FFT bins are ascending in the sample and seemingly random in my captures.
My capture (cargo run --example=print < compressed.iqz):

1            Average                         0      196608               0
2            Average                      1024      196608               0
3            Average                       512      196608               0

BLE sample (cargo run --example=print < test-data/iqzip/ble-advertising.iqz):

18467        Average                         0      270336               7
18468        Average                         1      270336               9
18469        Average                         2      270336               8

Closer inspection shows that this is a flipped bit order compared to the sample file. I could imaging that a different byte order might stem from a bug on the host. But IMHO a different bit order suggests that there is something different on the FPGA. So I wondered:

• Was the sample actually recorded with the FPGA image that is in the repo?
• Was the FPGA image in the repo tested and is known to work?
• Just to be sure: this project does not require any changes to the firmware of the ZPU?