regenerate symbols & add loongarch backend (#1903) (#2148)

* regenerate symbols

* Squash loongarch

---------

Co-authored-by: WangLiangpu <[email protected]>

Author: amaanq

CMakeLists.txt

@@ -279,6 +279,11 @@ else()
                 set(UNICORN_TARGET_ARCH "avr")
                 break()
             endif()
+            string(FIND ${UC_COMPILER_MACRO} "loongarch64" UC_RET)
+            if (${UC_RET} GREATER_EQUAL "0")
+                set(UNICORN_TARGET_ARCH "loongarch64")
+                break()
+            endif()
             message(FATAL_ERROR "Unknown host compiler: ${CMAKE_C_COMPILER}.")
         endwhile(TRUE)
     endif()

qemu/avr.h

@@ -4,6 +4,10 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _avr
 #endif
+#define unicorn_fill_tlb unicorn_fill_tlb_avr
+#define reg_read reg_read_avr
+#define reg_write reg_write_avr
+#define uc_init uc_init_avr
 #define uc_add_inline_hook uc_add_inline_hook_avr
 #define uc_del_inline_hook uc_del_inline_hook_avr
 #define tb_invalidate_phys_range tb_invalidate_phys_range_avr
@@ -38,7 +42,10 @@
 #define tcg_gen_shl_i64 tcg_gen_shl_i64_avr
 #define tcg_gen_shr_i64 tcg_gen_shr_i64_avr
 #define tcg_gen_st_i64 tcg_gen_st_i64_avr
+#define tcg_gen_add_i64 tcg_gen_add_i64_avr
+#define tcg_gen_sub_i64 tcg_gen_sub_i64_avr
 #define tcg_gen_xor_i64 tcg_gen_xor_i64_avr
+#define tcg_gen_neg_i64 tcg_gen_neg_i64_avr
 #define cpu_icount_to_ns cpu_icount_to_ns_avr
 #define cpu_is_stopped cpu_is_stopped_avr
 #define cpu_get_ticks cpu_get_ticks_avr
@@ -121,7 +128,10 @@
 #define memory_map memory_map_avr
 #define memory_map_io memory_map_io_avr
 #define memory_map_ptr memory_map_ptr_avr
+#define memory_cow memory_cow_avr
 #define memory_unmap memory_unmap_avr
+#define memory_moveout memory_moveout_avr
+#define memory_movein memory_movein_avr
 #define memory_free memory_free_avr
 #define flatview_unref flatview_unref_avr
 #define address_space_get_flatview address_space_get_flatview_avr
@@ -140,14 +150,17 @@
 #define memory_region_get_ram_addr memory_region_get_ram_addr_avr
 #define memory_region_add_subregion memory_region_add_subregion_avr
 #define memory_region_del_subregion memory_region_del_subregion_avr
+#define memory_region_add_subregion_overlap memory_region_add_subregion_overlap_avr
 #define memory_region_find memory_region_find_avr
+#define memory_region_filter_subregions memory_region_filter_subregions_avr
 #define memory_listener_register memory_listener_register_avr
 #define memory_listener_unregister memory_listener_unregister_avr
 #define address_space_remove_listeners address_space_remove_listeners_avr
 #define address_space_init address_space_init_avr
 #define address_space_destroy address_space_destroy_avr
 #define memory_region_init_ram memory_region_init_ram_avr
 #define memory_mapping_list_add_merge_sorted memory_mapping_list_add_merge_sorted_avr
+#define find_memory_mapping find_memory_mapping_avr
 #define exec_inline_op exec_inline_op_avr
 #define floatx80_default_nan floatx80_default_nan_avr
 #define float_raise float_raise_avr
@@ -364,6 +377,8 @@
 #define floatx80_sub floatx80_sub_avr
 #define floatx80_mul floatx80_mul_avr
 #define floatx80_div floatx80_div_avr
+#define floatx80_modrem floatx80_modrem_avr
+#define floatx80_mod floatx80_mod_avr
 #define floatx80_rem floatx80_rem_avr
 #define floatx80_sqrt floatx80_sqrt_avr
 #define floatx80_eq floatx80_eq_avr
@@ -638,6 +653,7 @@
 #define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_avr
 #define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_avr
 #define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_avr
+#define tcg_gen_gvec_dup_imm tcg_gen_gvec_dup_imm_avr
 #define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_avr
 #define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_avr
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_avr
@@ -692,13 +708,20 @@
 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_avr
 #define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_avr
 #define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_avr
+#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_avr
+#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_avr
 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_avr
+#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_avr
+#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_avr
 #define tcg_gen_gvec_shls tcg_gen_gvec_shls_avr
 #define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_avr
 #define tcg_gen_gvec_sars tcg_gen_gvec_sars_avr
+#define tcg_gen_gvec_rotls tcg_gen_gvec_rotls_avr
 #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_avr
 #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_avr
 #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_avr
+#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_avr
+#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_avr
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_avr
 #define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_avr
 #define tcg_can_emit_vecop_list tcg_can_emit_vecop_list_avr
@@ -735,6 +758,8 @@
 #define tcg_gen_shli_vec tcg_gen_shli_vec_avr
 #define tcg_gen_shri_vec tcg_gen_shri_vec_avr
 #define tcg_gen_sari_vec tcg_gen_sari_vec_avr
+#define tcg_gen_rotli_vec tcg_gen_rotli_vec_avr
+#define tcg_gen_rotri_vec tcg_gen_rotri_vec_avr
 #define tcg_gen_cmp_vec tcg_gen_cmp_vec_avr
 #define tcg_gen_add_vec tcg_gen_add_vec_avr
 #define tcg_gen_sub_vec tcg_gen_sub_vec_avr
@@ -750,9 +775,12 @@
 #define tcg_gen_shlv_vec tcg_gen_shlv_vec_avr
 #define tcg_gen_shrv_vec tcg_gen_shrv_vec_avr
 #define tcg_gen_sarv_vec tcg_gen_sarv_vec_avr
+#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_avr
+#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_avr
 #define tcg_gen_shls_vec tcg_gen_shls_vec_avr
 #define tcg_gen_shrs_vec tcg_gen_shrs_vec_avr
 #define tcg_gen_sars_vec tcg_gen_sars_vec_avr
+#define tcg_gen_rotls_vec tcg_gen_rotls_vec_avr
 #define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_avr
 #define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_avr
 #define tb_htable_lookup tb_htable_lookup_avr
@@ -764,6 +792,7 @@
 #define cpu_loop_exit_restore cpu_loop_exit_restore_avr
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_avr
 #define tlb_init tlb_init_avr
+#define tlb_destroy tlb_destroy_avr
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_avr
 #define tlb_flush tlb_flush_avr
 #define tlb_flush_by_mmuidx_all_cpus tlb_flush_by_mmuidx_all_cpus_avr
@@ -784,6 +813,7 @@
 #define tlb_set_page tlb_set_page_avr
 #define get_page_addr_code_hostp get_page_addr_code_hostp_avr
 #define get_page_addr_code get_page_addr_code_avr
+#define probe_access_flags probe_access_flags_avr
 #define probe_access probe_access_avr
 #define tlb_vaddr_to_host tlb_vaddr_to_host_avr
 #define helper_ret_ldub_mmu helper_ret_ldub_mmu_avr
@@ -800,22 +830,34 @@
 #define helper_be_ldsl_mmu helper_be_ldsl_mmu_avr
 #define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_avr
 #define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_avr
-#define cpu_lduw_mmuidx_ra cpu_lduw_mmuidx_ra_avr
-#define cpu_ldsw_mmuidx_ra cpu_ldsw_mmuidx_ra_avr
-#define cpu_ldl_mmuidx_ra cpu_ldl_mmuidx_ra_avr
-#define cpu_ldq_mmuidx_ra cpu_ldq_mmuidx_ra_avr
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_avr
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_avr
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_avr
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_avr
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_avr
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_avr
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_avr
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_avr
 #define cpu_ldub_data_ra cpu_ldub_data_ra_avr
 #define cpu_ldsb_data_ra cpu_ldsb_data_ra_avr
-#define cpu_lduw_data_ra cpu_lduw_data_ra_avr
-#define cpu_ldsw_data_ra cpu_ldsw_data_ra_avr
-#define cpu_ldl_data_ra cpu_ldl_data_ra_avr
-#define cpu_ldq_data_ra cpu_ldq_data_ra_avr
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_avr
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_avr
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_avr
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_avr
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_avr
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_avr
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_avr
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_avr
 #define cpu_ldub_data cpu_ldub_data_avr
 #define cpu_ldsb_data cpu_ldsb_data_avr
-#define cpu_lduw_data cpu_lduw_data_avr
-#define cpu_ldsw_data cpu_ldsw_data_avr
-#define cpu_ldl_data cpu_ldl_data_avr
-#define cpu_ldq_data cpu_ldq_data_avr
+#define cpu_lduw_be_data cpu_lduw_be_data_avr
+#define cpu_lduw_le_data cpu_lduw_le_data_avr
+#define cpu_ldsw_be_data cpu_ldsw_be_data_avr
+#define cpu_ldsw_le_data cpu_ldsw_le_data_avr
+#define cpu_ldl_be_data cpu_ldl_be_data_avr
+#define cpu_ldl_le_data cpu_ldl_le_data_avr
+#define cpu_ldq_le_data cpu_ldq_le_data_avr
+#define cpu_ldq_be_data cpu_ldq_be_data_avr
 #define helper_ret_stb_mmu helper_ret_stb_mmu_avr
 #define helper_le_stw_mmu helper_le_stw_mmu_avr
 #define helper_be_stw_mmu helper_be_stw_mmu_avr
@@ -824,17 +866,26 @@
 #define helper_le_stq_mmu helper_le_stq_mmu_avr
 #define helper_be_stq_mmu helper_be_stq_mmu_avr
 #define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_avr
-#define cpu_stw_mmuidx_ra cpu_stw_mmuidx_ra_avr
-#define cpu_stl_mmuidx_ra cpu_stl_mmuidx_ra_avr
-#define cpu_stq_mmuidx_ra cpu_stq_mmuidx_ra_avr
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_avr
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_avr
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_avr
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_avr
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_avr
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_avr
 #define cpu_stb_data_ra cpu_stb_data_ra_avr
-#define cpu_stw_data_ra cpu_stw_data_ra_avr
-#define cpu_stl_data_ra cpu_stl_data_ra_avr
-#define cpu_stq_data_ra cpu_stq_data_ra_avr
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_avr
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_avr
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_avr
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_avr
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_avr
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_avr
 #define cpu_stb_data cpu_stb_data_avr
-#define cpu_stw_data cpu_stw_data_avr
-#define cpu_stl_data cpu_stl_data_avr
-#define cpu_stq_data cpu_stq_data_avr
+#define cpu_stw_be_data cpu_stw_be_data_avr
+#define cpu_stw_le_data cpu_stw_le_data_avr
+#define cpu_stl_be_data cpu_stl_be_data_avr
+#define cpu_stl_le_data cpu_stl_le_data_avr
+#define cpu_stq_be_data cpu_stq_be_data_avr
+#define cpu_stq_le_data cpu_stq_le_data_avr
 #define helper_atomic_cmpxchgb_mmu helper_atomic_cmpxchgb_mmu_avr
 #define helper_atomic_xchgb_mmu helper_atomic_xchgb_mmu_avr
 #define helper_atomic_fetch_addb_mmu helper_atomic_fetch_addb_mmu_avr
@@ -1091,6 +1142,7 @@
 #define cpu_lduw_code cpu_lduw_code_avr
 #define cpu_ldl_code cpu_ldl_code_avr
 #define cpu_ldq_code cpu_ldq_code_avr
+#define cpu_interrupt_handler cpu_interrupt_handler_avr
 #define helper_div_i32 helper_div_i32_avr
 #define helper_rem_i32 helper_rem_i32_avr
 #define helper_divu_i32 helper_divu_i32_avr
@@ -1175,6 +1227,10 @@
 #define helper_gvec_sar16i helper_gvec_sar16i_avr
 #define helper_gvec_sar32i helper_gvec_sar32i_avr
 #define helper_gvec_sar64i helper_gvec_sar64i_avr
+#define helper_gvec_rotl8i helper_gvec_rotl8i_avr
+#define helper_gvec_rotl16i helper_gvec_rotl16i_avr
+#define helper_gvec_rotl32i helper_gvec_rotl32i_avr
+#define helper_gvec_rotl64i helper_gvec_rotl64i_avr
 #define helper_gvec_shl8v helper_gvec_shl8v_avr
 #define helper_gvec_shl16v helper_gvec_shl16v_avr
 #define helper_gvec_shl32v helper_gvec_shl32v_avr
@@ -1187,6 +1243,14 @@
 #define helper_gvec_sar16v helper_gvec_sar16v_avr
 #define helper_gvec_sar32v helper_gvec_sar32v_avr
 #define helper_gvec_sar64v helper_gvec_sar64v_avr
+#define helper_gvec_rotl8v helper_gvec_rotl8v_avr
+#define helper_gvec_rotl16v helper_gvec_rotl16v_avr
+#define helper_gvec_rotl32v helper_gvec_rotl32v_avr
+#define helper_gvec_rotl64v helper_gvec_rotl64v_avr
+#define helper_gvec_rotr8v helper_gvec_rotr8v_avr
+#define helper_gvec_rotr16v helper_gvec_rotr16v_avr
+#define helper_gvec_rotr32v helper_gvec_rotr32v_avr
+#define helper_gvec_rotr64v helper_gvec_rotr64v_avr
 #define helper_gvec_eq8 helper_gvec_eq8_avr
 #define helper_gvec_ne8 helper_gvec_ne8_avr
 #define helper_gvec_lt8 helper_gvec_lt8_avr
@@ -1279,6 +1343,9 @@
 #define gen_helper_vfp_set_fpscr gen_helper_vfp_set_fpscr_avr
 #define gen_helper_cpsr_read gen_helper_cpsr_read_avr
 #define gen_helper_cpsr_write gen_helper_cpsr_write_avr
+#define tlb_reset_dirty_by_vaddr tlb_reset_dirty_by_vaddr_avr
+#define helper_stqcx_le_parallel helper_stqcx_le_parallel_avr
+#define helper_stqcx_be_parallel helper_stqcx_be_parallel_avr
 #define helper_sleep helper_sleep_avr
 #define helper_unsupported helper_unsupported_avr
 #define helper_debug helper_debug_avr
@@ -1290,8 +1357,4 @@
 #define helper_wdr helper_wdr_avr
 #define gen_intermediate_code gen_intermediate_code_avr
 #define restore_state_to_opc restore_state_to_opc_avr
-
-#define reg_read reg_read_avr
-#define reg_write reg_write_avr
-#define uc_init uc_init_avr
 #endif

qemu/configure

@@ -498,6 +498,8 @@ elif check_define __tricore__ ; then
   cpu="tricore"
 elif check_define __AVR__ ; then
   cpu="avr"
+elif check_define __loongarch64 ; then
+  cpu="loongarch64"
 else
   cpu=$(uname -m)
 fi
@@ -545,6 +547,10 @@ case "$cpu" in
     cpu="avr"
     supported_cpu="yes"
   ;;
+  loongarch64)
+    cpu="loongarch64"
+    supported_cpu="yes"
+  ;;
   *)
     # This will result in either an error or falling back to TCI later
     ARCH=unknown
@@ -859,6 +865,11 @@ case "$cpu" in
            CPU_CFLAGS="-m64 -mcx16"
            QEMU_LDFLAGS="-m64 $QEMU_LDFLAGS"
            ;;
+    loongarch*)
+	   CPU_CFLAGS=""
+           QEMU_LDFLAGS=" $QEMU_LDFLAGS"
+           ;;
+
     x32)
            CPU_CFLAGS="-mx32"
            QEMU_LDFLAGS="-mx32 $QEMU_LDFLAGS"
@@ -2680,6 +2691,11 @@ case "$target_name" in
     mttcg="yes"
     TARGET_SYSTBL_ABI=i386
   ;;
+  loongarch64)
+    mttcg="yes"
+    TARGET_ARCH=loongarch64
+    TARGET_SYSTBL_ABI=common,64
+  ;;
   x86_64)
     TARGET_BASE_ARCH=i386
     TARGET_SYSTBL_ABI=common,64

qemu/include/elf.h

@@ -176,6 +176,7 @@ typedef struct mips_elf_abiflags_v0 {
 
 #define EM_NANOMIPS     249     /* Wave Computing nanoMIPS */
 
+#define EM_LOONGARCH        258 /* LoongArch */
 /*
  * This is an interim value that we will use until the committee comes
  * up with a final number.