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pdn.config
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pdn.config
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# PDN physical parameters
# C4 pad pitch (m)
-PDN_padpitch 285e-6
# C4 pad diameter (m)
-PDN_padD 100e-6
# C4 pad resistance (Ohm)
-PDN_padR 10e-3
# C4 pad current density threshold (A/m^2)
-PDN_cur_dense 8.5e7
# How are the pads distributed
# 0: load pad location from padloc_file_in;
# 1: all seats for pads are filled with P/G;
-PDN_padconfig 1
# pad location input file
-padloc_file_in example.padloc
# pad location file format
# 0: parse as on-chip virtual grid, dump as on-chip virtual grid
# 1: parse as on-chip virtual grid, dump as pad grid
# 2: parse as pad grid, dump as on-chip virtual grid
# 3: parse as pad grid, dump as pad grid
-padloc_format 0
# Metal layer specification file
# If not specified, use default values. For more details,
# see function populate_defalt_mlayers in PDN_sim.c
-mlayer_spec_file (null)
# On-chip decap
-PDN_decap_dense 100 # decap density (nF/mm2)
-PDN_decap_ratio 0.10 # % of chip area dedicated for decap
# Package RLC values
-PDN_padL 7.2e-12 # pad L
-PDN_pkg_sL 3e-12 # serial part of package L
-PDN_pkg_sR 0.015e-3 # serial part of package R
-PDN_pkg_C 26.4e-6 # package C
-PDN_pkg_pR 0.5415e-3 # parallel part of package R
-PDN_pkg_pL 4.61e-12 # parallel part of package L
# Supply voltage
-vdd 1 # global power supply (V)
-gnd 0 # global ground (V)
# 3D PDN
# 3D layer spec file
-layer_file_3D (null)
# switch for voltage stacking
-v_stacking 0
# how are the TSVs distributed
# 0: through tsvloc files specified by lcf file
# 1: all grid nodes are connected to TSVs;
-TSV_config 1
# TSV parameters
-TSV_R 46.85e-3
-TSV_L 34.262e-12
# location file for IVRs (all layer same loc)
-IVR_loc_file (null)
# Parameters for SC converters
-SC_freq 50e6
-SC_totcap 8e-9
-SC_Rontop 1.052
-SC_Ronbtm 1.17
# PDN simulation parameters
# modeling granularity, larger numer => finer on-chip grid
# on-chip grid row/col ~= PDN_grid_intv * pad grid row/col
-PDN_grid_intv 2
# switch for steady state PDN simulation
# 0 - no steady state;
# 1 - run steady state, use ptrace average
-run_PDN 0
# Processor clock frequency (Hz)
-proc_clock_freq 3.7e9
# Power trace sampling interval (number of clock cycles)
-ptrace_sampling_intvl 1
# Transient Time step (per clock cycle)
-PDN_step_percycle 5
# number of power trace lines for warm up, no stats analyse during warm up
-PDN_ptrace_warmup 0
# transient package switch, if 0, package only have resistance
-PDN_pkgLC 1
# transient onchip L switch, if 0, on-chip gird only have resistance
-PDN_gridL 1
# PDN stats dump files
# pad current output file
-padcur_file (null)
# grid voltage output file
# Can be used for both steady state drop and transient droop
-gridvol_file (null)
# grid voltage output file
-vio_file (null)
# grid node per cycle violatoin trace file
-node_viotrace_file (null)
# Voltage noise threshold in analysis (%Vdd)
-PDN_noise_th 5
# Debug/Development parameters
# sensor location input file, automatically use if specified
-senloc_file (null)
# Create voltage map animation, one frame per intv time steps
#-animation 0 # 1-2D Voltage plot, 2-3D Voltage plot, 3-Current plot
#-frame_intv 5
# Color map range for Voltage graph, ratio of Vdd
#-legend_lwr 0.05
#-legend_upr 0.03
# Color map range for Current graph, in A
#-legend_curupr 0.02
# generate sin wave as power trace internally
# switch
#-PDN_sin_pattern 0
# how many time steps to simulate
#-PDN_sin_totstep 5000
# frequency of sin wave
#-PDN_sin_freq 100e6
# multi-domain PDN; cores per domain, 0 for uni-domain
# negative values for special
#-PDN_multi_dom 0
# use this parameter scale package parameters
#-PDN_pkg_scale 1 # Area_chip/Area_domain