From 17b99fc87a1abe459115ca7b1c8f903e30e7f30f Mon Sep 17 00:00:00 2001
From: Stephen More <stephen.w.more@gmail.com>
Date: Wed, 12 Oct 2022 20:16:47 -0400
Subject: [PATCH 1/7] added mode in hardblock flow to stop after COFFE after
 running asic flow, added recursive searching for design files in hardblock
 flow, added support to put intermediary stages of asic flow (synth,pnr,power
 reporting) into unique directories based on configuration

---
 analyze_results/condense_reports.py           | 169 +++++++++++++++
 analyze_results/plot_coffe_results.py         | 101 +++++++++
 coffe/fpga.py                                 |   4 +-
 coffe/hardblock_functions.py                  |  95 +++++---
 coffe/utils.py                                |  13 +-
 .../dsp_block_hdl/accumulate.v                |  50 +++++
 .../strtx_III_dsp_sadegh/dsp_block_hdl/dsp.v  |  98 +++++++++
 .../dsp_block_hdl/half_dsp.v                  |  79 +++++++
 .../dsp_block_hdl/twomadder.v                 |  64 ++++++
 .../strtx_III_dsp_sadegh/dsp_coffe_params.txt | 204 ++++++++++++++++++
 .../strtx_III_dsp_sadegh/dsp_hb_settings.txt  | 164 ++++++++++++++
 11 files changed, 1007 insertions(+), 34 deletions(-)
 create mode 100644 analyze_results/condense_reports.py
 create mode 100755 analyze_results/plot_coffe_results.py
 create mode 100755 input_files/strtx_III_dsp_sadegh/dsp_block_hdl/accumulate.v
 create mode 100755 input_files/strtx_III_dsp_sadegh/dsp_block_hdl/dsp.v
 create mode 100755 input_files/strtx_III_dsp_sadegh/dsp_block_hdl/half_dsp.v
 create mode 100755 input_files/strtx_III_dsp_sadegh/dsp_block_hdl/twomadder.v
 create mode 100755 input_files/strtx_III_dsp_sadegh/dsp_coffe_params.txt
 create mode 100755 input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt

diff --git a/analyze_results/condense_reports.py b/analyze_results/condense_reports.py
new file mode 100644
index 0000000..be70918
--- /dev/null
+++ b/analyze_results/condense_reports.py
@@ -0,0 +1,169 @@
+
+import sys
+import os
+import argparse
+import subprocess as sp
+import shlex 
+import csv
+import re
+
+############### PYTHON3 ###############
+#This allows for the command to output to console while running but with certain commands it causes issues (awk)
+def run_shell_cmd(cmd_str,out_flag):
+    cmd_lst = shlex.split(cmd_str)
+    cmd_out = sp.Popen(cmd_lst, stdin=sp.PIPE, stdout=sp.PIPE, stderr=sp.PIPE,env=cur_env)
+    cmd_stdout = ""
+    for line in iter(cmd_out.stdout.readline, ""):
+        if(cmd_out.poll() is None):
+            cmd_stdout += line.decode("utf-8")
+            if(out_flag == 1):
+                sys.stdout.buffer.write(line)
+            elif(out_flag == 2):
+                sys.stderr.buffer.write(line)
+        else:
+            break
+    _, cmd_stderr = cmd_out.communicate()
+    cmd_stderr = cmd_stderr.decode("utf-8")
+    print("cmd: %s returned with: %d" % (cmd_str,cmd_out.returncode))
+    return cmd_stdout, cmd_stderr
+
+#safe mode for running shell commands
+def safe_run_shell_cmd(cmd_str):
+    cmd_lst = shlex.split(cmd_str)
+    cmd_out = sp.run(cmd_lst, stdin=sp.PIPE, stdout=sp.PIPE, stderr=sp.PIPE,env=cur_env)
+    cmd_stdout = cmd_out.stdout.decode("utf-8")
+    cmd_stderr = cmd_out.stderr.decode("utf-8")
+    # print("cmd: %s returned with: %d" % (cmd_str,cmd_out.returncode))
+    if(cmd_out.returncode != 0):
+        print(cmd_stderr)
+    return cmd_stdout, cmd_stderr
+############### PYTHON3 ###############
+
+#return the relative path of top level repo (COFFE in this case)
+def find_top_repo(repo_str):
+  cwd_pwd_list = os.getcwd().split("/")
+  cwd_pwd_list.reverse()
+  repo_idx = cwd_pwd_list.index(repo_str)
+  return "../"*(repo_idx)
+
+def make_dir(dir_rel_path):
+  if(not os.path.isdir(dir_rel_path)):
+      os.mkdir(dir_rel_path)
+      # print("made directory in the path\n%s" % ( os.getcwd()))
+
+#creates output directories and move to arch out folder to prepare for scripts to run
+def create_out_dirs(hard_params,arch_params):
+    gen_out_dir_name = "output_files"
+    os.chdir(arch_params["coffe_repo_path"])
+    make_dir(gen_out_dir_name)
+    os.chdir(gen_out_dir_name)
+    #make directory for this specific coffe run
+    make_dir(arch_params["coffe_design_name"])
+    os.chdir(arch_params["coffe_design_name"])
+    make_dir(hard_params["arch_dir"])
+    os.chdir(hard_params["arch_dir"])
+    arch_dir = os.getcwd()
+    os.chdir(arch_params["coffe_repo_path"])
+    #return abs path to run ASIC flow from
+    return arch_dir
+
+def modify_hb_params(hard_params,arch_params):
+    # GET DIR NAMES FROM PATHS
+    for hb_key,hb_val in hard_params.items():
+        if "folder" in hb_key:
+          #takes the abs path and gets dir name
+          out_dir_name = hb_val.split("/")[-1]
+          if("synth_" in hb_key):
+              hard_params["synth_dir"] = out_dir_name
+          elif("pr_" in hb_key):
+              hard_params["pnr_dir"] = out_dir_name
+          elif("primetime_"in hb_key):
+              hard_params["pt_dir"] = out_dir_name
+    arch_out_path = arch_params["arch_out_folder"].split("/")[-1]
+    out_dir_name = arch_out_path.split("/")[-1]
+    hard_params["arch_dir"] = out_dir_name
+
+#outputs csv to the report_csv_out dir
+def reports_to_csv(report_path):
+  os.chdir(report_path)
+  decimal_re = re.compile(r'\d+\.{0,1}\d*')
+  report_dict = {
+      'mode': [],
+      'top_level_mod' : [],
+      'period': [],
+      'wire_model': [],
+      'metal_layers' : [],
+      'utilization' : [],
+      'area': [],
+      'delay': [],
+      'power': []
+  }
+  for rep in os.listdir(report_path):
+    report_csv_out_dir = "report_csv_out"
+    if("report_" in rep):
+        #parse asic params from rep name
+        rep_params = rep.split("_")
+        if(len(rep_params) < 7):
+          continue
+        #check to see if its the mode or average of modes reports
+        #be careful the mode param is only gonna work for dsp block (or other verilog that has mode_0,mode_1 ports to muxes), will have to be generalized in future TODO
+        if("mode" in rep_params[1]):
+            report_dict["mode"].append(rep_params[1])
+            param_idx = 1
+        else:
+            report_dict["mode"].append("none")
+            param_idx = 0
+
+        report_dict["top_level_mod"].append(rep_params[1+param_idx])
+        report_dict["period"].append(rep_params[2+param_idx])
+        #skip one index for "wire" keyword
+        report_dict["wire_model"].append(rep_params[3+param_idx])
+        report_dict["metal_layers"].append(rep_params[5+param_idx])
+        #remove the .txt from the last param in filename
+        report_dict["utilization"].append(os.path.splitext(rep_params[6+param_idx])[0])
+        fd = open(rep,"r")
+        delay = ""
+        power = ""
+        area = ""
+        for line in fd:
+            if("area" in line):
+                area = decimal_re.search(line).group(0)
+            elif("delay" in line):
+                delay = decimal_re.search(line).group(0)
+            elif("power" in line):
+                power = decimal_re.search(line).group(0)
+        report_dict['area'].append(area)
+        report_dict['delay'].append(delay)
+        report_dict['power'].append(power)
+        fd.close()
+  os.chdir(script_path)
+  make_dir(report_csv_out_dir)
+  for row_idx in range(len(report_dict["delay"])):
+    dict_row = [report_dict[key][row_idx] for key in report_dict.keys()]
+  fd = open(report_csv_out_dir + "/condensed_report.csv","w")
+  writer = csv.writer(fd)
+  writer.writerow(report_dict.keys())
+  for row_idx in range(len(report_dict["delay"])):
+    dict_row = [report_dict[key][row_idx] for key in report_dict.keys()]
+    writer.writerow(dict_row)
+  fd.close()
+  return report_dict
+
+def main():
+    global cur_env
+    cur_env = os.environ.copy()
+    global script_path
+    script_path = os.getcwd()
+    parser = argparse.ArgumentParser()
+    parser.add_argument('-r','--report_path',type=str,help="path to directory containing coffe report outputs")
+    args = parser.parse_args()
+    arg_dict = vars(args)
+    #create condensed reports
+    report_pwd = os.path.join(os.getcwd(),arg_dict["report_path"])
+    report_dict = reports_to_csv(report_pwd)
+
+
+
+if __name__ == "__main__":
+    main()
+
diff --git a/analyze_results/plot_coffe_results.py b/analyze_results/plot_coffe_results.py
new file mode 100755
index 0000000..de3d5ce
--- /dev/null
+++ b/analyze_results/plot_coffe_results.py
@@ -0,0 +1,101 @@
+import matplotlib.pyplot as plt
+import csv
+import sys
+import argparse
+
+
+def plot_key_vs_freq(data_dict,key=None,cost=False):
+    #use delay to get
+    target_freqs = [(1/float(i))*1000 if float(i) != 0 else None for i in data_dict["period"]]
+    achieved_freqs = [(1/float(i))*1000 if float(i) != 0 else None for i in data_dict["delay"]]
+    unique_tfreqs = list(set(target_freqs))
+    freq_idxs = [None]*len(target_freqs)
+    #The freq_idxs array stores indexes for each report according to the target frequency
+    for i,u_tfreq in enumerate(unique_tfreqs):
+        for j,t_freq in enumerate(target_freqs):
+            if(t_freq == u_tfreq):
+                freq_idxs[j] = i
+    #now we have map from target freq to achived freq, use this to get to lists for each target_freq
+    tfreq_unique_data = []
+    afreq_unique_data = []
+    tfreq_unique_data_2 = []
+    for i in range(len(unique_tfreqs)):
+        tfreq_unique_data.append([])
+        afreq_unique_data.append([])
+        tfreq_unique_data_2.append([])
+    for idx,i in enumerate(freq_idxs):
+        if(cost == False):
+            tfreq_unique_data[i].append(float(data_dict[key][idx]))
+        else:
+            tfreq_unique_data[i].append(float(data_dict["area"][idx]))
+            tfreq_unique_data_2[i].append(float(data_dict["delay"][idx]))
+        afreq_unique_data[i].append(achieved_freqs[idx])
+    avg_key_val = [None]*len(unique_tfreqs)
+    avg_achieved_freq = [None]*len(unique_tfreqs)
+    for i in range(len(unique_tfreqs)):
+        if(cost == False):
+            avg_key_val[i] = float(sum(tfreq_unique_data[i]))/float(len(tfreq_unique_data[i]))
+        else:
+            avg_key_val[i] = float(sum([area*delay for area,delay in zip(tfreq_unique_data[i],tfreq_unique_data_2[i])])/float(len(tfreq_unique_data[i])))            
+        avg_achieved_freq[i] = float(sum(afreq_unique_data[i]))/float(len(afreq_unique_data[i]))
+    fig, ax = plt.subplots(1,2,figsize=(12,5))
+    fig.tight_layout(pad=5.0)
+    ax0_ylabel_str = ""
+    if(cost == False):
+        ys = [float(i) for i in data_dict[key]] 
+        fig_name = f"{key}_fig.png"
+        if(key == "area"):
+            ax0_ylabel_str = "Area (um2)"
+        elif(key == "power"):
+            ax0_ylabel_str = "Power (mW)"
+            ys = [i*1000 for i in ys]
+            avg_key_val = [i*1000 for i in avg_key_val]
+        elif(key == "delay"):
+            ax0_ylabel_str = "Delay (ns)"
+    else:
+        fig_name = "cost_fig.png"
+        ax0_ylabel_str = "Area (um2) x Delay (ns)"
+        ys = [float(i)*float(j) for i,j in zip(data_dict["area"],data_dict["delay"])]
+
+    xmin,xmax = (min(achieved_freqs),max(achieved_freqs))
+    ymin,ymax = (min(ys), max(ys))
+    yrange = ymax - ymin
+    xrange = xmax - xmin
+    #data plot for key selected
+    ax[0].set_xlim(xmin-(xrange/10),xmax+(xrange/10))
+    ax[0].set_ylim(ymin-(yrange/10),ymax+(yrange/10))
+    ax[0].set_xlabel("Achieved Freq (MHz)")
+    ax[0].set_ylabel(ax0_ylabel_str)
+    ax[0].scatter(achieved_freqs,ys,marker='x',c='b')
+    # average plot
+    ax[1].set_xlim(xmin-(xrange/10),xmax+(xrange/10))
+    ax[1].set_ylim(ymin-(yrange/10),ymax+(yrange/10))
+    ax[1].scatter(avg_achieved_freq,avg_key_val,marker='x',c='r')
+    ax[1].set_xlabel("Achieved Freq (MHz)")
+    ax[1].set_ylabel("Avg " + ax0_ylabel_str)
+    plt.savefig(fig_name)
+
+def read_csv(csv_path):
+    data_dict = {}
+    with open(csv_path,'r') as infile:
+        reader = csv.reader(infile)
+        header = next(reader)
+        next(reader)
+        out_list = [list(i) for i in zip(*reader)]
+    for idx,key in enumerate(header):
+        data_dict[key] = out_list[idx]
+    return data_dict
+
+def main():
+    parser = argparse.ArgumentParser()
+    parser.add_argument('-c','--csv_path',type=str,help="path to condensed csv file")
+    args = parser.parse_args()
+    arg_dict = vars(args)
+    data_dict = read_csv(arg_dict['csv_path'])
+    plot_key_vs_freq(data_dict,"area")
+    plot_key_vs_freq(data_dict,"delay")
+    plot_key_vs_freq(data_dict,"power")
+    plot_key_vs_freq(data_dict,cost=True)
+
+if __name__ == "__main__":
+    main()
\ No newline at end of file
diff --git a/coffe/fpga.py b/coffe/fpga.py
index 9fe222f..f105593 100644
--- a/coffe/fpga.py
+++ b/coffe/fpga.py
@@ -5175,8 +5175,10 @@ def generate_top(self):
         if self.parameters['num_dedicated_outputs'] > 0:
             self.dedicated.generate_top()
 
-        # hard flow
+        # hard block flow
         self.flow_results = hardblock_functions.hardblock_flow(self.parameters)
+        if(self.parameters["asic_flow_only"] == True):
+            sys.exit()
         #the area returned by the hardblock flow is in um^2. In area_dict, all areas are in nm^2 
         self.area = self.flow_results[0] * self.parameters['area_scale_factor'] * (1e+6) 
 
diff --git a/coffe/hardblock_functions.py b/coffe/hardblock_functions.py
index 74690a1..28a1c1e 100644
--- a/coffe/hardblock_functions.py
+++ b/coffe/hardblock_functions.py
@@ -25,17 +25,11 @@ def hardblock_flow(flow_settings):
   ###########################################
   design_files = []
   if flow_settings['design_language'] == 'verilog':
-    for file in os.listdir(os.path.expanduser(flow_settings['design_folder'])):
-      if file.endswith(".v"):
-        design_files.append(file)
+    design_files = [fn for _, _, fs in os.walk(flow_settings['design_folder']) for fn in fs if fn.endswith(".v")]
   elif flow_settings['design_language'] == 'vhdl':
-    for file in os.listdir(os.path.expanduser(flow_settings['design_folder'])):
-      if file.endswith(".vhdl"):
-        design_files.append(file)
+    design_files = [fn for _, _, fs in os.walk(flow_settings['design_folder']) for fn in fs if fn.endswith(".vhdl")]
   elif flow_settings['design_language'] == 'sverilog':
-    for file in os.listdir(os.path.expanduser(flow_settings['design_folder'])):
-      if file.endswith(".sv"):
-        design_files.append(file)    
+    design_files = [fn for _, _, fs in os.walk(flow_settings['design_folder']) for fn in fs if fn.endswith(".sv") or fn.endswith(".v")]
   subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['synth_folder']) + "\n", shell=True)
   # Make sure we managed to read the design files
   assert len(design_files) >= 1
@@ -105,12 +99,11 @@ def hardblock_flow(flow_settings):
       file.close()
 
       # Run the scrip in design compiler shell
-      subprocess.call('dc_shell-t -f dc_script.tcl', shell=True, executable='/bin/tcsh') 
+      subprocess.call('dc_shell-t -f dc_script.tcl | tee dc.log', shell=True) 
       # clean after DC!
       subprocess.call('rm -rf command.log', shell=True)
       subprocess.call('rm -rf default.svf', shell=True)
       subprocess.call('rm -rf filenames.log', shell=True)
-      subprocess.call('rm -rf dc_script.tcl', shell=True) 
 
       # Make sure it worked properly
       # Open the timing report and make sure the critical path is non-zero:
@@ -124,8 +117,18 @@ def hardblock_flow(flow_settings):
           print "In spite of the warning, the rest of the flow will continue to execute."
       check_file.close()
 
-      #if the user doesn't want to perform place and route, extract the results from DC reports and end
+      #Copy synthesis results to a unique dir in synth dir
+      synth_report_str = "period_" + clock_period + "_" + "wire_mdl_" + wire_selection
+      report_dest_str = os.path.expanduser(flow_settings['synth_folder']) + "/" + synth_report_str + "_reports"
+      mkdir_cmd_str = "mkdir -p " + report_dest_str
+      copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['synth_folder']) + "/*.rpt " + report_dest_str
+      copy_logs_cmd_str = "cp " + "dc.log "+ "dc_script.tcl " + report_dest_str
+      subprocess.call(mkdir_cmd_str,shell=True)
+      subprocess.call(copy_rep_cmd_str,shell=True)
+      subprocess.call(copy_logs_cmd_str,shell=True)
+      subprocess.call('rm -f dc.log dc_script.tcl',shell=True)
 
+      #if the user doesn't want to perform place and route, extract the results from DC reports and end
       if flow_settings['synthesis_only']:
 
         # read total area from the report file:
@@ -161,7 +164,7 @@ def hardblock_flow(flow_settings):
               total_dynamic_power[0] *= 0.000001
             else:
               total_dynamic_power[0] = 0
-        file.close()    
+        file.close()
 
         # write the final report file:
         file = open("report.txt" ,"w")
@@ -325,13 +328,11 @@ def hardblock_flow(flow_settings):
           file.close()
 
           # Run the scrip in EDI
-          subprocess.call('encounter -nowin -init edi.tcl', shell=True) 
+          subprocess.call('encounter -nowin -init edi.tcl | tee edi.log', shell=True) 
           # clean after EDI!
-          subprocess.call('rm -rf edi.tcl', shell=True)
-          subprocess.call('rm -rf edi.conf', shell=True)
           subprocess.call('mv encounter.log ' + os.path.expanduser(flow_settings['pr_folder']) + '/encounter_log.log', shell=True)
           subprocess.call('mv encounter.cmd ' + os.path.expanduser(flow_settings['pr_folder']) + '/encounter.cmd', shell=True)
-
+          
           # read total area from the report file:
           file = open(os.path.expanduser(flow_settings['pr_folder']) + "/pr_report.txt" ,"r")
           for line in file:
@@ -339,6 +340,17 @@ def hardblock_flow(flow_settings):
               total_area = re.findall(r'\d+\.{0,1}\d*', line)
           file.close()
           
+          #Copy pnr results to a unique dir in pnr dir
+          pnr_report_str = synth_report_str + "_" + "metal_layers_" + metal_layer + "_" + "util_" + core_utilization
+          report_dest_str = os.path.expanduser(flow_settings['pr_folder']) + "/" + pnr_report_str + "_reports"
+          mkdir_cmd_str = "mkdir -p " + report_dest_str
+          copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['pr_folder']) + "/*.rpt " + os.path.expanduser(flow_settings['pr_folder']) + "/pr_report.txt " + report_dest_str
+          copy_logs_cmd_str = "cp " + "edi.log " + "edi.tcl " + "edi.conf " + report_dest_str
+          subprocess.call(mkdir_cmd_str,shell=True)
+          subprocess.call(copy_rep_cmd_str,shell=True)
+          subprocess.call(copy_logs_cmd_str,shell=True)
+          subprocess.call('rm -f edi.log edi.conf edi.tcl', shell=True)
+
           if len(flow_settings['mode_signal']) > 0:
             mode_enabled = True
           else:
@@ -387,25 +399,30 @@ def hardblock_flow(flow_settings):
             file.write("set sh_enable_page_mode true \n")
 
             file.write("set search_path " + flow_settings['primetime_lib_path'] + " \n")
-            file.write("set link_path "  + r'"* ' + flow_settings['primetime_lib_name'] + '"' + " \n") 
+            file.write("set my_top_level " + flow_settings['top_level'] + "\n")
+            file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
+            file.write("set target_library " + flow_settings['target_libraries'] + "\n")
+            file.write("set link_library " + flow_settings['link_libraries'] + "\n")
 
             file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
             if mode_enabled and x <2**len(flow_settings['mode_signal']):
               for y in range (0, len(flow_settings['mode_signal'])):
                 file.write("set_case_analysis " + str((x >> y) & 1) + " " +  flow_settings['mode_signal'][y] + " \n")
             file.write("link \n")
+            
+            file.write("set my_period " + str(clock_period) + " \n")
+            file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
+            file.write("if { $find_clock != [list] } { \n")
+            file.write("set clk_name $my_clock_pin \n")
+            file.write("create_clock -period $my_period $clk_name} \n\n")
 
-            file.write("create_clock -period " + clock_period + " " + flow_settings['clock_pin_name'] + " \n")
             file.write("read_parasitics -increment " + os.path.expanduser(flow_settings['pr_folder']) + "/spef.spef \n")
             file.write("report_timing > " + os.path.expanduser(flow_settings['primetime_folder']) + "/timing.rpt \n")
             file.write("quit \n")
             file.close()
 
             # run prime time
-            subprocess.call('dc_shell-t -f primetime.tcl', shell=True) 
-
-            # clean after prime time
-            subprocess.call('rm -rf primetime.tcl', shell=True)
+            subprocess.call('dc_shell-t -f primetime.tcl | tee pt.log', shell=True) 
 
             # Read timing parameters
             file = open(os.path.expanduser(flow_settings['primetime_folder']) + "/timing.rpt" ,"r")
@@ -424,12 +441,19 @@ def hardblock_flow(flow_settings):
             file.write("set sh_enable_page_mode true \n")
 
             file.write("set search_path " + flow_settings['primetime_lib_path'] + " \n")
-            file.write("set link_path "  + r'"* ' + flow_settings['primetime_lib_name'] + '"' + " \n") 
+            file.write("set my_top_level " + flow_settings['top_level'] + "\n")
+            file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
+            file.write("set target_library " + flow_settings['target_libraries'] + "\n")
+            file.write("set link_library " + flow_settings['link_libraries'] + "\n")
 
             file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
             file.write("link \n")
 
-            file.write("create_clock -period " + str(total_delay) + " " + flow_settings['clock_pin_name'] + " \n")
+            file.write("set my_period " + str(clock_period) + " \n")
+            file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
+            file.write("if { $find_clock != [list] } { \n")
+            file.write("set clk_name $my_clock_pin \n")
+            file.write("create_clock -period $my_period $clk_name} \n\n")
             if mode_enabled and x <2**len(flow_settings['mode_signal']):
               for y in range (0, len(flow_settings['mode_signal'])):
                 file.write("set_case_analysis " + str((x >> y) & 1) + " " +  flow_settings['mode_signal'][y] +  " \n")
@@ -438,7 +462,7 @@ def hardblock_flow(flow_settings):
             if flow_settings['generate_activity_file']:
 							file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
             else:
-              file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " [all_nets] \n")
+              file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " -base_clock $my_clock_pin -type inputs \n")
             #file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
             #file.write("read_vcd -input ./modelsim_dir/vcd.vcd \n")
             file.write(r'read_parasitics -increment ' + os.path.expanduser(flow_settings['pr_folder']) + r'/spef.spef' + "\n")
@@ -448,12 +472,19 @@ def hardblock_flow(flow_settings):
             file.close()
 
             # run prime time
-            subprocess.call('dc_shell-t -f primetime_power.tcl', shell=True) 
-
-            # clean after prime time
-            subprocess.call('rm -rf primetime_power.tcl', shell=True)
-
-
+            subprocess.call('dc_shell-t -f primetime_power.tcl | tee pt_pwr.log', shell=True) 
+
+            #copy reports and logs to a unique dir in pt dir
+            pt_report_str = pnr_report_str + "_" + "mode_" + str(x)
+            report_dest_str = os.path.expanduser(flow_settings['primetime_folder']) + "/" + pt_report_str + "_reports"
+            mkdir_cmd_str = "mkdir -p " + report_dest_str
+            copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['primetime_folder']) + "/*.rpt " + report_dest_str
+            copy_logs_cmd_str = "cp " + "pt.log pt_pwr.log primetime.tcl primetime_power.tcl " + report_dest_str
+            subprocess.call(mkdir_cmd_str,shell=True)
+            subprocess.call(copy_rep_cmd_str,shell=True)
+            subprocess.call(copy_logs_cmd_str,shell=True)
+            subprocess.call('rm -f pt.log pt_pwr.log primetime.tcl primetime_power.tcl', shell=True)
+            
             # Read dynamic power
             file = open(os.path.expanduser(flow_settings['primetime_folder']) + "/power.rpt" ,"r")
             for line in file:
diff --git a/coffe/utils.py b/coffe/utils.py
index 5d7dd03..3664eed 100644
--- a/coffe/utils.py
+++ b/coffe/utils.py
@@ -509,6 +509,8 @@ def load_arch_params(filename):
         'FAs_per_flut':2,
         'hb_files' : [],
         'arch_out_folder': "None",
+        # 'coffe_design_name' : "coffe_test",
+        # 'coffe_repo_path' : "None"
     }
 
     params_file = open(filename, 'r')
@@ -658,6 +660,10 @@ def load_arch_params(filename):
             arch_params['hb_files'].append(value)
         elif param == 'arch_out_folder':
             arch_params['arch_out_folder'] = value
+        # elif param == 'coffe_design_name':
+        #     arch_params['coffe_design_name'] = str(value)
+        # elif param == 'coffe_repo_path':
+        #     arch_params['coffe_repo_path'] = str(value)
 
     params_file.close()
     
@@ -704,6 +710,7 @@ def load_hard_params(filename):
         'synth_folder': "",
         'show_warnings': False,
         'synthesis_only': False,
+        'asic_flow_only': False,
         'read_saif_file': False,
         'static_probability': -1.0,
         'toggle_rate': -1,
@@ -850,6 +857,8 @@ def load_hard_params(filename):
             hard_params['show_warnings'] = (value == "True")
         elif param == 'synthesis_only':
             hard_params['synthesis_only'] = (value == "True")
+        elif param == 'asic_flow_only':
+            hard_params['asic_flow_only'] = (value == "True")
         elif param == 'read_saif_file':
             hard_params['read_saif_file'] = (value == "True")
         elif param == 'static_probability':
@@ -978,7 +987,9 @@ def check_arch_params (arch_params, filename):
     if arch_params['enable_bram_module'] == 1 and arch_params['use_finfet'] == True:
         print_error_not_compatable("finfet", "BRAM")           
     if arch_params['use_finfet'] == True and arch_params['use_fluts'] == True:
-        print_error_not_compatable("finfet", "flut")           
+        print_error_not_compatable("finfet", "flut")      
+    # if arch_params['coffe_repo_path'].split("/")[-1] != "COFFE":
+    #     print_error (arch_params['coffe_repo_path'],"coffe_repo_path",filename)
 
 
 
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/accumulate.v b/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/accumulate.v
new file mode 100755
index 0000000..2b401e7
--- /dev/null
+++ b/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/accumulate.v
@@ -0,0 +1,50 @@
+//Two multipliers and adder
+
+module accumulate(
+A0,
+B0,
+C0,
+clk,
+add_previous,
+reset,
+mode_0,
+S
+);
+
+input [71:0] A0;
+input [71:0] B0;
+input [43:0] C0;
+input clk;
+input reset;
+input add_previous;
+input mode_0;
+output [143:0] S;
+
+
+wire [37:0] A0pB0;
+wire [43:0] accumulated;
+reg [37:0] A0pB0_reg;
+reg [143:0] S_temp;
+
+always @(posedge clk)
+if (reset) begin
+    A0pB0_reg <= 38'b0;
+	S_temp <= 144'b0;
+    end else begin
+    A0pB0_reg <= A0pB0;
+	if (mode_0) begin
+	S_temp <= {A0[71:0],B0[71:0]};
+	end else if (add_previous) begin
+    S_temp <= { accumulated , 100'd0};
+    end else begin
+    S_temp <= {A0pB0_reg, 100'd0};
+    end
+    
+end
+
+
+assign A0pB0 = A0[35:0] + B0[35:0];
+assign accumulated = A0pB0_reg + C0;
+assign S = S_temp;
+
+endmodule
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/dsp.v b/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/dsp.v
new file mode 100755
index 0000000..0e2f684
--- /dev/null
+++ b/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/dsp.v
@@ -0,0 +1,98 @@
+module dsp (
+A0,
+A1,
+B0,
+B1,
+C0,
+C1,
+D0,
+D1,
+E0,
+E1,
+F0,
+F1,
+G0,
+G1,
+H0,
+H1,
+from_previous,
+add_previous,
+clk,
+mode_0,
+mode_1,
+reset,
+result0,
+result1
+);
+
+input [17:0] A0;
+input [17:0] A1;
+input [17:0] B0;
+input [17:0] B1;
+input [17:0] C0;
+input [17:0] C1;
+input [17:0] D0;
+input [17:0] D1;
+input [17:0] E0;
+input [17:0] E1;
+input [17:0] F0;
+input [17:0] F1;
+input [17:0] G0;
+input [17:0] G1;
+input [17:0] H0;
+input [17:0] H1;
+input [43:0] from_previous;
+input clk;
+input reset;
+input mode_0;
+input mode_1;
+input add_previous;
+
+output [143:0] result0;
+output [143:0] result1;
+
+wire [143:0] the_output0;
+wire [143:0] the_output1;
+
+half_dsp m0(
+.A0 (A0),
+.A1 (A1),
+.B0 (B0),
+.B1 (B1),
+.C0 (C0),
+.C1 (C1),
+.D0 (D0),
+.D1 (D1),
+.mode_0 (mode_0),
+.mode_1 (mode_1),
+.from_previous (from_previous),
+.add_previous (add_previous),
+.clk (clk),
+.reset (reset),
+.result (the_output0)
+);
+
+
+half_dsp m1(
+.A0 (E0),
+.A1 (E1),
+.B0 (F0),
+.B1 (F1),
+.C0 (G0),
+.C1 (G1),
+.D0 (H0),
+.D1 (H1),
+.mode_0 (mode_0),
+.mode_1 (mode_1),
+.from_previous (the_output0[71:28]),
+.add_previous (add_previous),
+.clk (clk),
+.reset (reset),
+.result (the_output1)
+);
+
+
+assign result0 = the_output0;
+assign result1 = the_output1;
+
+endmodule
\ No newline at end of file
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/half_dsp.v b/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/half_dsp.v
new file mode 100755
index 0000000..9f92b91
--- /dev/null
+++ b/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/half_dsp.v
@@ -0,0 +1,79 @@
+module half_dsp (
+A0,
+A1,
+B0,
+B1,
+C0,
+C1,
+D0,
+D1,
+mode_0,
+mode_1,
+from_previous,
+add_previous,
+clk,
+reset,
+result
+);
+
+input [17:0] A0;
+input [17:0] A1;
+input [17:0] B0;
+input [17:0] B1;
+input [17:0] C0;
+input [17:0] C1;
+input [17:0] D0;
+input [17:0] D1;
+input [43:0] from_previous;
+input clk;
+input reset;
+input mode_0;
+input mode_1;
+input add_previous;
+
+output [143:0] result;
+
+wire [71:0] partial_0;
+wire [71:0] partial_1;
+wire [143:0] the_output;
+
+two_multipliers_one_adder m0(
+.A0 (A0),
+.A1 (A1),
+.B0 (B0),
+.B1 (B1),
+.clk (clk),
+.mode_0 (mode_0),
+.mode_1 (mode_1),
+.reset (reset),
+.P (partial_0)
+);
+
+
+two_multipliers_one_adder m1(
+.A0 (C0),
+.A1 (C1),
+.B0 (D0),
+.B1 (D1),
+.clk (clk),
+.mode_0 (mode_0),
+.mode_1 (mode_1),
+.reset (reset),
+.P (partial_1)
+);
+
+
+accumulate m2(
+.A0 (partial_0),
+.B0 (partial_1),
+.C0 (from_previous),
+.add_previous (add_previous),
+.S (the_output),
+.clk (clk),
+.mode_0 (mode_0),
+.reset (reset)
+);
+
+assign result = the_output;
+
+endmodule
\ No newline at end of file
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/twomadder.v b/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/twomadder.v
new file mode 100755
index 0000000..7f13aa8
--- /dev/null
+++ b/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/twomadder.v
@@ -0,0 +1,64 @@
+//Two multipliers and adder
+
+module two_multipliers_one_adder(
+A0,
+A1,
+B0,
+B1,
+clk,
+reset,
+mode_0,
+mode_1,
+P
+);
+
+input [17:0] A0;
+input [17:0] A1;
+input [17:0] B0;
+input [17:0] B1;
+input clk;
+input reset;
+input mode_0;
+input mode_1;
+output [71:0] P;
+
+
+reg [17:0] A0_registered;
+reg [17:0] B0_registered;
+reg [17:0] A1_registered;
+reg [17:0] B1_registered;
+
+wire [35:0] A0xB0;
+wire [35:0] A1xB1;
+wire [36:0] tempsum;
+
+reg [71:0] moutput;
+
+always @(posedge clk)
+if (reset) begin
+    A0_registered <= 18'b0;
+    A1_registered <= 18'b0;
+    B0_registered <= 18'b0;
+    B1_registered <= 18'b0;
+	moutput <= 72'b0;
+	
+    end else begin
+    A0_registered <= A0;
+    A1_registered <= A1;
+    B0_registered <= B0;
+    B1_registered <= B1;
+	if (mode_0 == 1'b0 && mode_1 ==1'b0) begin
+	moutput <= {35'd0, tempsum};
+	end else if (mode_0 == 1'b1 && mode_1 ==1'b0) begin
+	moutput <= {A0xB0, A1xB1};
+	end else begin
+	moutput <= {36'd0, A0xB0};
+	end
+end
+
+assign A0xB0 = A0_registered * B0_registered;
+assign A1xB1 = A1_registered * B1_registered;
+assign P = moutput;
+assign tempsum = A0xB0 + A1xB1;
+
+endmodule
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_coffe_params.txt b/input_files/strtx_III_dsp_sadegh/dsp_coffe_params.txt
new file mode 100755
index 0000000..13f3c86
--- /dev/null
+++ b/input_files/strtx_III_dsp_sadegh/dsp_coffe_params.txt
@@ -0,0 +1,204 @@
+# EXAMPLE COFFE INPUT FILE (BULK TRANSISTORS)
+#
+# Note: COFFE interprets any line beginning with a '#' as a comment in it's input files.
+#
+# COFFE input parameters can be divided into 2 groups:
+# 1- Parameters describing the FPGA architecture
+# 2- Process technology-related parameters
+# 
+# [1] C. Chiasson and V.Betz. "COFFE: Fully-Automated Transistor Sizing for FPGAs",
+#      IEEE Int. Conf. on Field-Programmable Technology (FPT), 2013
+
+#######################################
+##### General parameters
+#######################################
+
+#Abs path to COFFE repo
+coffe_repo_path=/fs1/eecg/vaughn/morestep/COFFE
+
+#The directory in which all outputs are generated, makes it easier to make sense of data
+coffe_design_name=strtx_III_dsp_sadegh
+
+#The directory in which output files will be stored. 
+#If not specified, the directory containing this file is used as output dir.
+arch_out_folder=/fs1/eecg/vaughn/morestep/COFFE/output_files/strtx_III_dsp_sadegh/arch_out_dir
+
+#######################################
+##### Architecture Parameters
+#######################################
+
+# The following parameters are the classic VPR architecture parameters
+N=10
+K=6
+W=320
+L=4
+I=40
+Fs=3
+Fcin=0.2
+Fcout=0.025
+
+# The following architecture parameters are new and help COFFE describe
+# a more flexible BLE. See [1] for more details.
+
+# Number of BLE outputs to general routing 
+Or=2
+
+# Number of BLE outputs to local routing
+Ofb=1
+
+# Population of local routing MUXes 
+Fclocal=0.5
+
+# Register select:
+# Defines whether the FF can accept it's input directly from a BLE input or not.
+# To turn register-select off, Rsel=z
+# To turn register select on, Rsel=<ble_input_name>
+# where <ble_input_name> = the name of the BLE input from which the FF can
+# accept its input (e.g. a, b, c, etc...).
+Rsel=c
+
+# Register feedback muxes:
+# Defines which LUT inputs support register feedback.
+# Set Rfb to a string of LUT input names.
+# For example: 
+# Rfb=c tells COFFE to place a register feedback mux on LUT input C.
+# Rfb=cd tells COFFE to place a register feedback mux on both LUT inputs C and D.
+# Rfb=z tells COFFE that no LUT input should have register feedback muxes.
+Rfb=c
+
+# Do we want to use fracturable Luts?
+use_fluts=False
+# can be as large as K-1
+#independent_inputs = 0
+
+#enable_carry_chain = 1
+#carry_chain_type = skip
+#FAs_per_flut = 2
+
+
+#######################################
+##### Memory Block Parameters
+#######################################
+
+# Do we want Block RAM simulation at all?
+enable_bram_module = 0
+
+#Memory block voltage (low power transistors)
+vdd_low_power = 0.95
+
+
+# Memory technology type can be 'SRAM' or 'MTJ'.
+memory_technology = SRAM
+
+# The following determine the number of address bits used in each of the decoders
+# These bits are used to determine the aspect ratio of the memory module
+# Please note: if you use a two-bank BRAM, one of the bits below will be decoded by the bank selection address
+# To make it controllable, I decided that this bit will always be taken from the row decoder.
+
+# Row decoder
+row_decoder_bits = 8
+# Column decoder
+col_decoder_bits = 2
+# Width configurable decoder
+conf_decoder_bits = 5
+# Number of RAM banks
+number_of_banks = 2
+
+
+# voltage difference for the sense amp in volts
+sense_dv = 0.03
+
+# Weakest SRAM cell current in Amps
+worst_read_current = 0.0000015
+
+#MTJ resisitance values for 4 combinations of nominal/worst case for low/high states
+MTJ_Rlow_nominal = 2500
+MTJ_Rhigh_nominal = 6250
+MTJ_Rlow_worstcase = 3060
+MTJ_Rhigh_worstcase = 4840
+
+
+# BRAM read to write ratio for power measurements:
+read_to_write_ratio = 1.0
+
+#######################################
+##### Process Technology Parameters
+#######################################
+
+# Transistor type can be 'bulk' or 'finfet'. 
+# Make sure your spice model file matches the transistor type you choose.
+transistor_type=bulk
+
+# The switch type can be 'pass_transistor' or 'transmission_gate'.
+switch_type=pass_transistor
+#switch_type=transmission_gate
+
+# Supply voltage
+vdd=0.8
+
+# SRAM Vdd
+vsram=1.0
+
+# SRAM Vss
+vsram_n=0.0
+
+# Gate length (nm)
+gate_length=22
+
+# This parameter controls the gate length of PMOS level-restorers. For example, setting this paramater 
+# to 4 sets the gate length to 4x the value of 'gate_legnth'. Increasing the gate length weakens the 
+# PMOS level-restorer, which is sometimes necessary to ensure proper switching.
+rest_length_factor = 1
+
+# Minimum transistor diffusion width (nm).
+min_tran_width=45
+
+# Length of diffusion for a single-finger transistor (nm).
+# COFFE uses this when it calculates source/drain parasitic capacitances.
+trans_diffusion_length = 52
+
+# Minimum-width transistor area (nm^2)
+min_width_tran_area = 33864
+
+# SRAM area (in number of minimum width transistor areas)
+sram_cell_area = 4
+
+# Path to SPICE device models file and library to use
+model_path=spice_models/ptm_22nm_bulk_hp.l
+model_library=22NM_BULK_HP
+
+#######################################
+##### Metal data
+##### R in ohms/nm
+##### C in fF/nm
+##### format: metal=R,C
+##### ex: metal=0.054825,0.000175
+#######################################
+
+# Each 'metal' statement defines a new metal layer. 
+# COFFE uses two metal layers by default. The first metal layer is where COFFE 
+# implements all wires except for the general routing wires. They are implemented
+# in the second metal layer. 
+
+
+# All wires except the general routing wires are implemented in this layer.
+metal=0.054825,0.000175
+
+# General routing wires will be implemented in this layer 
+metal=0.007862,0.000215
+
+# Memory array wires will be implemented in this layer
+metal=0.029240,0.000139
+
+# This layer is used in MTJ wordline (if BRAM technology is MTJ)
+metal=0.227273,0.000000
+
+# If you wanted to, you could define more metal layers by adding more 'metal'
+# statements but, by default, COFFE would not use them because it only uses 2 layers.
+# The functionality of being able to add any number of metal layers is here to allow
+# you to investigate the use of more than 2 metal layers if you wanted to. However,
+# making use of more metal layers would require changes to the COFFE source code.
+
+
+# if hybrid blocks are enabled, list configurations here
+hb_files = input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt b/input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt
new file mode 100755
index 0000000..99c5b55
--- /dev/null
+++ b/input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt
@@ -0,0 +1,164 @@
+#This is a sample settings file for the hard block flow
+
+#############################################
+########## General Design Settings ##########
+#############################################
+
+# The folder in which all the design files are located:
+design_folder=/fs1/eecg/vaughn/morestep/COFFE/input_files/strtx_III_dsp_sadegh/dsp_block_hdl
+
+# The design language. Should be either 'verilog', 'vhdl' or 'sverilog'
+design_language=verilog
+# The exponents of delay and area in the cost function.
+# cost = (delay ^ delay_cost_exp) * (area ^ area_cost_exp)
+delay_cost_exp=1.0
+area_cost_exp=1.0
+
+
+########################################
+########## Synthesis Settings ##########
+########################################
+
+# Name of the clock pin in the design
+clock_pin_name=clk
+## -> this means that this was changed to run hspice on bastet
+# Desired clock period in ns
+##clock_period=1.53
+#clock_period=1.66
+#clock_period=1.81
+clock_period=2.0
+#clock_period=2.22
+#clock_period=2.5
+
+# Name of the top-level entity in the design
+#top_level=ASU_conv
+top_level=dsp
+
+# The name of the folder in which post-synthesis files and synthesis reports are to be stored
+synth_folder=~/COFFE/output_files/strtx_III_dsp_sadegh/synth
+
+# Do you want to be informed of warnings during synthesis?
+
+show_warnings=True
+
+# Should the flow terminate after synthesis?
+# A value of "False" will continue into placement and routing
+synthesis_only=False
+
+# Do you want to provide a saif file for power analysis?
+# In case of setting this to "True" a saif.saif file should be provided
+read_saif_file=False
+
+# If you don't want to provide a saif file, specify the switching activity parameters below:
+static_probability=0.5
+toggle_rate=25
+
+# Should COFFE generate an activity file for the design (using modelsim)
+generate_activity_file=False
+# Location of the library files.
+# if you have more than one library, please provide them similiar to the example below.
+
+link_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.db"
+
+target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.db"
+
+##############################################
+########## Place and Route Settings ##########
+##############################################
+
+# Libraries required in EDI:
+
+#metal_layers=8
+metal_layers=7
+#metal_layers=6
+#metal_layers=5
+
+#names of metal layers starting from the bottom-most layer on the left. use a python list format. 
+metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "AP"]
+
+#names of metal layers to use for each side of the power ring
+#order: top, bottom, left, right
+power_ring_metal_layer_names=["M1", "M1", "M2", "M2"]
+
+#name of the file to use for layer mapping. used for stream out.
+#set it to None if you want the tool to create a generic map file
+map_file=streamOut.map
+wire_selection=WireAreaLowkCon
+wire_selection=WireAreaLowkAgr
+#wire_selection=WireAreaForZero
+#specify names of ground and power pins and nets in the library
+gnd_net=VSS
+gnd_pin=VSS
+pwr_net=VDD
+pwr_pin=VDD
+tilehi_tielo_cells_between_power_gnd=True
+
+
+#specify footprint names for inverters, buffers, delays.
+#this is optional. you can get these values from the lib file.
+#you can also specify None, if you can't find them in the lib file.
+#SM: not sure if these are the correct standard cells to be using, as there are many options (need to figure out what DX refers to)
+inv_footprint=INVD0
+buf_footprint=BUFFD1
+delay_footprint=DEL0
+
+#list of filler cell names. use a python list format.
+#the names can be obtained from .lib files.
+filler_cell_names=["FILL1", "FILL16", "FILL1_LL", "FILL2", "FILL32", "FILL64", "FILL8", "FILL_NW_FA_LL", "FILL_NW_HH", "FILL_NW_LL"]
+
+#name of the core site in the floorplan. can be obtained from lef files.
+core_site_name=core
+
+#specify the utilization of the core site. you can specify multiple ones on different lines.
+##core_utilization=0.85
+core_utilization=0.90
+##core_utilization=0.95
+
+lef_files="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Back_End/lef/tcbn65gplus_200a/lef/tcbn65gplus_9lmT2.lef /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Back_End/lef/tpzn65gpgv2_140c/mt_2/9lm/lef/antenna_9lm.lef /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Back_End/lef/tpzn65gpgv2_140c/mt_2/9lm/lef/tpzn65gpgv2_9lm.lef"
+
+
+best_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplusbc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2bc.lib"
+
+standard_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2tc.lib"
+
+worst_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.lib"
+
+
+
+# EDI settings:
+power_ring_width=3
+power_ring_spacing=3
+height_to_width_ratio=4.0
+
+space_around_core=5
+
+
+# The folder in which place and route reports and post-routing netlists and spef files will be stored
+pr_folder=~/COFFE/output_files/strtx_III_dsp_sadegh/pr
+
+
+##############################################
+########## Prime Time Settings ###############
+##############################################
+
+mode_signal=mode_0
+mode_signal=mode_1
+
+primetime_lib_path=". /CMC/tools/synopsys/syn_vN-2017.09/libraries/syn /CMC/tools/synopsys/syn_vN-2017.09/dw/syn_ver /CMC/tools/synopsys/syn_vN-2017.09/dw/sim_ver /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
+
+primetime_folder=~/COFFE/output_files/strtx_III_dsp_sadegh/pt
+
+# COFFE parameters:
+name=hard_block
+num_gen_inputs=288
+crossbar_population=0.5
+height=1
+num_gen_outputs=288
+num_dedicated_outputs=0
+soft_logic_per_block=0.1
+area_scale_factor=0.12
+freq_scale_factor=1.35
+power_scale_factor=0.3
+input_usage=0.8
+num_crossbars=1
+crossbar_modelling=optimistic
\ No newline at end of file

From 638d1c70711d4962c0074bedd47541e73e566136 Mon Sep 17 00:00:00 2001
From: Stephen More <stephen.w.more@gmail.com>
Date: Thu, 13 Oct 2022 02:28:47 -0400
Subject: [PATCH 2/7] cleaned up hardblock flow to make it more understandable,
 updated readme

---
 User Manual.md                                |  56 ++
 coffe/hardblock_functions.py                  | 897 +++++++++---------
 coffe/utils.py                                |   2 +-
 .../coffe_inp_params.txt                      |   2 +-
 .../simple_dsp_slice_65nm/dsp_slice.txt       |  58 +-
 .../dsp_block_hdl/accumulate.v                |   0
 .../dsp_block_hdl/dsp.v                       |   0
 .../dsp_block_hdl/half_dsp.v                  |   0
 .../dsp_block_hdl/twomadder.v                 |   0
 .../dsp_coffe_params.txt                      |   8 +-
 .../dsp_hb_settings.txt                       |  11 +-
 11 files changed, 532 insertions(+), 502 deletions(-)
 rename input_files/{strtx_III_dsp_sadegh => strtx_III_dsp}/dsp_block_hdl/accumulate.v (100%)
 rename input_files/{strtx_III_dsp_sadegh => strtx_III_dsp}/dsp_block_hdl/dsp.v (100%)
 rename input_files/{strtx_III_dsp_sadegh => strtx_III_dsp}/dsp_block_hdl/half_dsp.v (100%)
 rename input_files/{strtx_III_dsp_sadegh => strtx_III_dsp}/dsp_block_hdl/twomadder.v (100%)
 rename input_files/{strtx_III_dsp_sadegh => strtx_III_dsp}/dsp_coffe_params.txt (92%)
 rename input_files/{strtx_III_dsp_sadegh => strtx_III_dsp}/dsp_hb_settings.txt (91%)

diff --git a/User Manual.md b/User Manual.md
index 3e5f183..9b8022b 100644
--- a/User Manual.md	
+++ b/User Manual.md	
@@ -29,6 +29,62 @@ To run COFFE, simply run coffe.py and follow the instructions.
 There are several sample input files in the test directory accompanying COFFE which stimulate all existing features. These files describe what each of the parameters are; simply read them and change them to form your desired architecture.
 We have also included several tests with COFFE which should smoothly run when using the latest version. To test your setup, you can run those.
 
+# How to run a test for ASIC flow (using stratix III like DSP)
+The following test was tested with the following tools:
+-Synopsys Design Compiler 2017
+-Cadence Encounter 2009
+
+Prerequisites:
+Make sure the ASIC tools are on your environments path, this can be done with the following commands:
+$(which dc_shell-t)
+$(which encounter)
+
+1. Now the configuration files for the asic tools must be edited to match the environment and ASIC PDK being used
+(If you're using UofT servers you can skip this portion as they're already setup)
+
+  open up the following file in editor:
+  - ~/COFFE/input_files/strtx_III_dsp/dsp_hb_settings.txt
+
+  If you only want to run the asic flow, set the "asic_flow_only" param to True
+
+  - set the "target_libraries" and "link_libraries" parameters to the absolute paths to the standard cell front end .db files provided by semiconductor PDK (surrounded by quotes).
+  - set the "inv_footprint", "buf_footprint", and "delay_footprint" params to footprints, found in front end .lib files from pdk (found under similar names to "INVD0" "BUFFD1" "DEL0")
+
+  The following params can be found in the PDK back end .lef files
+  - set "metal_layer_names", "filler_cell_names", "core_site_name" params
+  - set the "lef_files" param to the absolute path of the .lef files 
+
+  Note: 
+    make sure the number of metal layers being used is less than or equal to the number of metal_layer_names defined.
+    make sure the .lef file has the correct number of metal layers as well
+
+  - set the "best_case_libs", "standard_libs", and "worst_case_libs" to the corresponding absolute paths to PDK ".lib" files
+  - set the primetime_lib_path to the absolute paths of the following design compiler directories and the front end PDK dirs used
+  Optional Parameter Changes:
+  - if desired one can sweep target frequency, number of metal layers, wire load model, core utilization, and mode of operation (this currently only works for dsp block)
+    - to add additional sweep parameters one would define the variable to be swept again with the new value:
+      - Ex. 
+        clock_period=2.0
+        clock_period=2.5
+        etc...
+2. run the following command (run this with python2):
+  - $(python2 coffe.py -i 1 input_files/strtx_III_dsp/dsp_coffe_params.txt)
+
+3. Once the program has finished go to the following directory:
+  - ~/COFFE/analyze_results
+
+  run the following command the argument points to where the .txt reports from post ASIC flow exist, which should be the same as the arch_out_folder param in dsp_coffe_params.txt):
+    - $(python2 condense_results.py -r ../output_files/strtx_III_dsp/arch_out_dir)
+
+  The above command creates a csv file with all reports from the specified directory.
+  To plot the power, area, and delay results against target frequency run the following command (this requires python3 and matplotlib to be installed):
+  - $(python3 plot_coffe_results.py -c report_csv_out/condensed_report.csv)
+
+
+
+
+
+
 ## How to report an issue.
 
 If you encounter an issue running COFFE, or if you have any questions about the features we support, please file an issue in github.
diff --git a/coffe/hardblock_functions.py b/coffe/hardblock_functions.py
index 28a1c1e..56da169 100644
--- a/coffe/hardblock_functions.py
+++ b/coffe/hardblock_functions.py
@@ -10,7 +10,422 @@
 import shutil
 import math
 
-
+def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_selection):
+  ###########################################
+  # Synthesis
+  ###########################################
+  file = open("dc_script.tcl","w")
+  file.write("cd " + os.path.expanduser(flow_settings['synth_folder']) + "\n")
+  file.write("set search_path " + "\"" + " ".join(search_path_dirs) + "\"" + " \n")
+  if len(design_files) == 1:
+    file.write("set my_files " + design_files[0] + "\n")
+  else:
+    file.write("set my_files [list ")
+    for entity in design_files:
+      if not (entity == "parameters.v" or entity == "c_functions.v"):
+        file.write(entity + " ")
+    file.write("] \n")
+  file.write("set my_top_level " + flow_settings['top_level'] + "\n")
+  file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
+  file.write("set link_library " + flow_settings['link_libraries'] + "\n")
+  file.write("set target_library " + flow_settings['target_libraries'] + "\n")
+  file.write(r'set power_analysis_mode "averaged"' + "\n")
+  file.write("define_design_lib WORK -path ./WORK \n")
+  if flow_settings['design_language'] == 'verilog':
+    file.write("analyze -f verilog $my_files \n")
+  elif flow_settings['design_language'] == 'vhdl':
+    file.write("analyze -f vhdl $my_files \n")
+  else:
+    file.write("analyze -f sverilog $my_files \n")
+  file.write("elaborate $my_top_level \n")
+  file.write("current_design $my_top_level \n")
+  file.write("check_design >  " + os.path.expanduser(flow_settings['synth_folder']) + "/checkprecompile.rpt\n")
+  file.write("link \n")
+  file.write("uniquify \n")
+  #If wire_selection is None, then no wireload model is used during synthesis. This does imply results 
+  #are not as accurate (wires don't have any delay and area), but is useful to let the flow work/proceed 
+  #if the std cell library is missing wireload models.
+  if wire_selection != "None":
+    file.write(r'set_wire_load_selection ' + wire_selection + " \n")
+  file.write("set my_period " + str(clock_period) + " \n")
+  file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
+  file.write("if { $find_clock != [list] } { \n")
+  file.write("set clk_name $my_clock_pin \n")
+  file.write("create_clock -period $my_period $clk_name} \n\n")
+  file.write("compile_ultra\n")
+  file.write("check_design >  " + os.path.expanduser(flow_settings['synth_folder']) + "/check.rpt\n")
+  file.write("link \n")
+  file.write("write_file -format ddc -hierarchy -output " + os.path.expanduser(flow_settings['synth_folder']) + "/" +  flow_settings['top_level']  + ".ddc \n")
+  if flow_settings['read_saif_file']:
+    file.write("read_saif saif.saif \n")
+  else:
+    file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " -base_clock $my_clock_pin -type inputs \n")
+  file.write("ungroup -all -flatten \n")
+  file.write("report_power > " + os.path.expanduser(flow_settings['synth_folder']) + "/power.rpt\n")
+  file.write("report_area -nosplit -hierarchy > " + os.path.expanduser(flow_settings['synth_folder']) + "/area.rpt\n")
+  file.write("report_resources -nosplit -hierarchy > " + os.path.expanduser(flow_settings['synth_folder']) + "/resources.rpt\n")      
+  file.write("report_timing > " + os.path.expanduser(flow_settings['synth_folder']) + "/timing.rpt\n")
+  file.write("change_names -hier -rule verilog \n") 
+  file.write("write -f verilog -output " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.v\n")
+  file.write("write_sdf " + os.path.expanduser(flow_settings['synth_folder']) + "/synthsized.sdf \n")
+  file.write("write_parasitics -output " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.spef \n")
+  file.write("write_sdc " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.sdc \n")
+  file.write("quit \n")
+  file.close()
+
+  # Run the scrip in design compiler shell
+  subprocess.call('dc_shell-t -f dc_script.tcl | tee dc.log', shell=True,executable="/bin/bash") 
+  # clean after DC!
+  subprocess.call('rm -rf command.log', shell=True)
+  subprocess.call('rm -rf default.svf', shell=True)
+  subprocess.call('rm -rf filenames.log', shell=True)
+
+  # Make sure it worked properly
+  # Open the timing report and make sure the critical path is non-zero:
+  check_file = open(os.path.expanduser(flow_settings['synth_folder']) + "/check.rpt", "r")
+  for line in check_file:
+    if "Error" in line:
+      print "Your design has errors. Refer to check.rpt in synthesis directory"
+      exit(-1)
+    elif "Warning" in line and flow_settings['show_warnings']:
+      print "Your design has warnings. Refer to check.rpt in synthesis directory"
+      print "In spite of the warning, the rest of the flow will continue to execute."
+  check_file.close()
+
+  #Copy synthesis results to a unique dir in synth dir
+  synth_report_str = "period_" + clock_period + "_" + "wire_mdl_" + wire_selection
+  report_dest_str = os.path.expanduser(flow_settings['synth_folder']) + "/" + synth_report_str + "_reports"
+  mkdir_cmd_str = "mkdir -p " + report_dest_str
+  copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['synth_folder']) + "/*.rpt " + report_dest_str
+  copy_logs_cmd_str = "cp " + "dc.log "+ "dc_script.tcl " + report_dest_str
+  subprocess.call(mkdir_cmd_str,shell=True)
+  subprocess.call(copy_rep_cmd_str,shell=True)
+  subprocess.call(copy_logs_cmd_str,shell=True)
+  subprocess.call('rm -f dc.log dc_script.tcl',shell=True)
+
+  #if the user doesn't want to perform place and route, extract the results from DC reports and end
+  if flow_settings['synthesis_only']:
+    # read total area from the report file:
+    file = open(os.path.expanduser(flow_settings['synth_folder']) + "/area.rpt" ,"r")
+    for line in file:
+      if line.startswith('Total cell area:'):
+        total_area = re.findall(r'\d+\.{0,1}\d*', line)
+    file.close()
+    # Read timing parameters
+    file = open(os.path.expanduser(flow_settings['synth_folder']) + "/timing.rpt" ,"r")
+    for line in file:
+      if 'library setup time' in line:
+        library_setup_time = re.findall(r'\d+\.{0,1}\d*', line)
+      if 'data arrival time' in line:
+        data_arrival_time = re.findall(r'\d+\.{0,1}\d*', line)
+    try:
+      total_delay =  float(library_setup_time[0]) + float(data_arrival_time[0])
+    except NameError:
+      total_delay =  float(data_arrival_time[0])
+    file.close()    
+    # Read dynamic power
+    file = open(os.path.expanduser(flow_settings['synth_folder']) + "/power.rpt" ,"r")
+    for line in file:
+      if 'Total Dynamic Power' in line:
+        total_dynamic_power = re.findall(r'\d+\.\d*', line)
+        total_dynamic_power[0] = float(total_dynamic_power[0])
+        if 'mW' in line:
+          total_dynamic_power[0] *= 0.001
+        elif 'uw' in line:
+          total_dynamic_power[0] *= 0.000001
+        else:
+          total_dynamic_power[0] = 0
+    file.close()
+    # write the final report file:
+    file = open("report.txt" ,"w")
+    file.write("total area = "  + str(total_area[0]) +  "\n")
+    file.write("total delay = " + str(total_delay) + " ns\n")
+    file.write("total power = " + str(total_dynamic_power[0]) + " W\n")
+    file.close()
+    #return
+    exit()
+  return synth_report_str
+
+
+def run_pnr(flow_settings,metal_layer,core_utilization,synth_report_str):
+  ###########################################
+  # Place and Route
+  ###########################################
+  # generate the EDI (encounter) configuration
+  file = open("edi.conf", "w")
+  file.write("global rda_Input \n")
+  file.write("set cwd .\n\n")
+  file.write("set rda_Input(ui_leffile) " + flow_settings['lef_files'] + "\n")
+  file.write("set rda_Input(ui_timelib,min) " + flow_settings['best_case_libs'] + "\n")
+  file.write("set rda_Input(ui_timelib) " + flow_settings['standard_libs'] + "\n")
+  file.write("set rda_Input(ui_timelib,max) " + flow_settings['worst_case_libs'] + "\n")
+  file.write("set rda_Input(ui_netlist) " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.v" + "\n")
+  file.write("set rda_Input(ui_netlisttype) {Verilog} \n")
+  file.write("set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1}\n")
+  file.write("set rda_Input(ui_timingcon_file) " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.sdc" + "\n")
+  file.write("set rda_Input(ui_topcell) " + flow_settings['top_level'] + "\n\n")
+  gnd_pin = flow_settings['gnd_pin']
+  gnd_net = flow_settings['gnd_net']
+  pwr_pin = flow_settings['pwr_pin']
+  pwr_net = flow_settings['pwr_net']
+  file.write("set rda_Input(ui_gndnet) {" + gnd_net + "} \n")
+  file.write("set rda_Input(ui_pwrnet) {" + pwr_net + "} \n")
+  if flow_settings['tilehi_tielo_cells_between_power_gnd'] is True:
+    file.write("set rda_Input(ui_pg_connections) [list {PIN:" + gnd_pin + ":}" + " {TIEL::} " + "{NET:" + gnd_net + ":} {NET:" + pwr_net + ":}" + " {TIEH::} " + "{PIN:" + pwr_pin + ":} ] \n")
+  else:
+    file.write("set rda_Input(ui_pg_connections) [list {PIN:" + gnd_pin + ":} {NET:" + gnd_net + ":} {NET:" + pwr_net + ":} {PIN:" + pwr_pin + ":} ] \n")
+  file.write("set rda_Input(PIN:" + gnd_pin + ":) {" + gnd_pin + "} \n")
+  file.write("set rda_Input(TIEL::) {" + gnd_pin + "} \n")
+  file.write("set rda_Input(NET:" + gnd_net + ":) {" + gnd_net + "} \n")
+  file.write("set rda_Input(PIN:" + pwr_pin + ":) {" + pwr_pin + "} \n")
+  file.write("set rda_Input(TIEH::) {" + pwr_pin + "} \n")
+  file.write("set rda_Input(NET:" + pwr_net + ":) {" + pwr_net + "} \n\n")
+  if (flow_settings['inv_footprint'] != "None"):
+    file.write("set rda_Input(ui_inv_footprint) {" + flow_settings['inv_footprint'] + "}\n")
+  if (flow_settings['buf_footprint'] != "None"):
+    file.write("set rda_Input(ui_buf_footprint) {" + flow_settings['buf_footprint'] + "}\n")
+  if (flow_settings['delay_footprint'] != "None"):
+    file.write("set rda_Input(ui_delay_footprint) {" + flow_settings['delay_footprint'] + "}\n")
+  file.close()
+  metal_layer_bottom = flow_settings["metal_layer_names"][0]
+  metal_layer_second = flow_settings["metal_layer_names"][1]
+  metal_layer_top = flow_settings["metal_layer_names"][int(metal_layer)-1]
+  power_ring_metal_top = flow_settings["power_ring_metal_layer_names"][0] 
+  power_ring_metal_bottom = flow_settings["power_ring_metal_layer_names"][1] 
+  power_ring_metal_left = flow_settings["power_ring_metal_layer_names"][2] 
+  power_ring_metal_right = flow_settings["power_ring_metal_layer_names"][3] 
+  # generate the EDI (encounter) script
+  file = open("edi.tcl", "w")
+  file.write("loadConfig edi.conf \n")
+  file.write("floorPlan -site " + flow_settings['core_site_name'] \
+              + " -r " + str(flow_settings['height_to_width_ratio']) \
+              + " " + str(core_utilization) \
+              + " " + str(flow_settings['space_around_core']) \
+              + " " + str(flow_settings['space_around_core']) + " ")
+  file.write(str(flow_settings['space_around_core']) + " " + str(flow_settings['space_around_core']) + "\n")
+  file.write("setMaxRouteLayer " + str(metal_layer) + " \n")
+  file.write("fit \n")
+  file.write("addRing -spacing_bottom " + str(flow_settings['power_ring_spacing']) \
+              + " -spacing_right " + str(flow_settings['power_ring_spacing']) \
+              + " -spacing_top " + str(flow_settings['power_ring_spacing']) \
+              + " -spacing_left " + str(flow_settings['power_ring_spacing']) \
+              + " -width_right " + str(flow_settings['power_ring_width']) \
+              + " -width_left " + str(flow_settings['power_ring_width']) \
+              + " -width_bottom " + str(flow_settings['power_ring_width']) \
+              + " -width_top " + str(flow_settings['power_ring_width']) \
+              + " -center 1" \
+              + " -around core" \
+              + " -layer_top " + power_ring_metal_top \
+              + " -layer_bottom " + power_ring_metal_bottom \
+              + " -layer_left " + power_ring_metal_left \
+              + " -layer_right " + power_ring_metal_right \
+              + " -nets { " + gnd_net + " " + pwr_net + " }" \
+              + " -stacked_via_top_layer "+ metal_layer_top \
+              + " -stacked_via_bottom_layer " + metal_layer_bottom + " \n")
+  file.write("setPlaceMode -fp false -maxRouteLayer " + str(metal_layer) + "\n")
+  file.write("placeDesign -inPlaceOpt -noPrePlaceOpt \n")
+  file.write("checkPlace " + flow_settings['top_level'] +" \n")
+  file.write("trialroute \n")
+  file.write("buildTimingGraph \n")
+  file.write("timeDesign -preCTS -idealClock -numPaths 10 -prefix preCTS -outDir " + os.path.expanduser(flow_settings['pr_folder']) + "/timeDesignpreCTSReports" + "\n")
+  file.write("optDesign -preCTS -outDir " + os.path.expanduser(flow_settings['pr_folder']) + "/optDesignpreCTSReports" + "\n")
+  # I won't do a CTS anyway as the blocks are small.
+  file.write("addFiller -cell {" + " ".join([str(item) for item in flow_settings['filler_cell_names']]) + "} -prefix FILL -merge true \n")  
+  file.write("clearGlobalNets \n")
+  file.write("globalNetConnect " + gnd_net + " -type pgpin -pin " + gnd_pin + " -inst {} \n")
+  file.write("globalNetConnect " + pwr_net + " -type pgpin -pin " + pwr_pin + " -inst {} \n")
+  file.write("globalNetConnect " + gnd_net + " -type net -net " + gnd_net + " \n")
+  file.write("globalNetConnect " + pwr_net + " -type net -net " + pwr_net + " \n")
+  file.write("globalNetConnect " + pwr_net + " -type pgpin -pin " + pwr_pin + " -inst * \n")
+  file.write("globalNetConnect " + gnd_net + " -type pgpin -pin " + gnd_pin + " -inst * \n")
+  file.write("globalNetConnect " + pwr_net + " -type tiehi -inst * \n")
+  file.write("globalNetConnect " + gnd_net + " -type tielo -inst * \n")
+  file.write("sroute -connect { blockPin padPin padRing corePin floatingStripe }" \
+              + " -layerChangeRange { " + metal_layer_bottom + " " + metal_layer_top + " }" \
+              + " -blockPinTarget { nearestRingStripe nearestTarget }" \
+              + " -padPinPortConnect { allPort oneGeom }" \
+              + " -checkAlignedSecondaryPin 1" \
+              + " -blockPin useLef" \
+              + " -allowJogging 1" \
+              + " -crossoverViaBottomLayer " + metal_layer_bottom \
+              + " -allowLayerChange 1" \
+              + " -targetViaTopLayer " + metal_layer_top \
+              + " -crossoverViaTopLayer " + metal_layer_top \
+              + " -targetViaBottomLayer " + metal_layer_bottom \
+              + " -nets { " + gnd_net + " " + pwr_net + " } \n")
+  file.write("routeDesign -globalDetail\n")
+  file.write("setExtractRCMode -engine postRoute \n")
+  file.write("extractRC \n")
+  file.write("buildTimingGraph \n")
+  file.write("timeDesign -postRoute -outDir " + os.path.expanduser(flow_settings['pr_folder']) + "/timeDesignReports" + "\n")
+  file.write("optDesign -postRoute -outDir " + os.path.expanduser(flow_settings['pr_folder']) + "/optDesignReports" + "\n")
+  #by default, violations are reported in designname.geom.rpt
+  file.write("verifyGeometry -report " + (os.path.expanduser(flow_settings['pr_folder']) + "/" + flow_settings['top_level'] + ".geom.rpt") + "\n")
+  #by default, violations are reported in designname.conn.rpt
+  file.write("verifyConnectivity -type all -report " + (os.path.expanduser(flow_settings['pr_folder']) + "/" + flow_settings['top_level'] + ".conn.rpt") + "\n")
+  # report area
+  file.write("summaryReport -outFile " + os.path.expanduser(flow_settings['pr_folder']) + "/pr_report.txt \n")
+  # save design
+  file.write(r'saveNetlist ' + os.path.expanduser(flow_settings['pr_folder']) + r'/netlist.v' + "\n")
+  file.write(r'saveDesign ' + os.path.expanduser(flow_settings['pr_folder']) + r'/design.enc' + " \n")
+  file.write(r'rcOut -spef ' + os.path.expanduser(flow_settings['pr_folder']) + r'/spef.spef' + " \n")
+  file.write(r'write_sdf -ideal_clock_network ' + os.path.expanduser(flow_settings['pr_folder']) + r'/sdf.sdf' + " \n")
+  #If the user specified a layer mapping file, then use that. Otherwise, just let the tool create a default one.
+  if flow_settings['map_file'] != "None":
+    file.write(r'streamOut ' + os.path.expanduser(flow_settings['pr_folder']) + r'/final.gds2' + ' -mapFile ' + flow_settings['map_file'] + ' -stripes 1 -units 1000 -mode ALL' + "\n")
+  else:
+    file.write(r'streamOut ' + os.path.expanduser(flow_settings['pr_folder']) + r'/final.gds2' + ' -stripes 1 -units 1000 -mode ALL' + "\n")
+  file.write("exit \n")
+  file.close()
+  # Run the scrip in EDI
+  subprocess.call('encounter -nowin -init edi.tcl | tee edi.log', shell=True,executable="/bin/bash") 
+  # clean after EDI!
+  subprocess.call('mv encounter.log ' + os.path.expanduser(flow_settings['pr_folder']) + '/encounter_log.log', shell=True)
+  subprocess.call('mv encounter.cmd ' + os.path.expanduser(flow_settings['pr_folder']) + '/encounter.cmd', shell=True)
+  # read total area from the report file:
+  file = open(os.path.expanduser(flow_settings['pr_folder']) + "/pr_report.txt" ,"r")
+  for line in file:
+    if line.startswith('Total area of Core:'):
+      total_area = re.findall(r'\d+\.{0,1}\d*', line)
+  file.close()
+  #Copy pnr results to a unique dir in pnr dir
+  pnr_report_str = synth_report_str + "_" + "metal_layers_" + metal_layer + "_" + "util_" + core_utilization
+  report_dest_str = os.path.expanduser(flow_settings['pr_folder']) + "/" + pnr_report_str + "_reports"
+  mkdir_cmd_str = "mkdir -p " + report_dest_str
+  copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['pr_folder']) + "/*.rpt " + os.path.expanduser(flow_settings['pr_folder']) + "/pr_report.txt " + report_dest_str
+  copy_logs_cmd_str = "cp " + "edi.log " + "edi.tcl " + "edi.conf " + report_dest_str
+  subprocess.call(mkdir_cmd_str,shell=True)
+  subprocess.call(copy_rep_cmd_str,shell=True)
+  subprocess.call(copy_logs_cmd_str,shell=True)
+  subprocess.call('rm -f edi.log edi.conf edi.tcl', shell=True)
+  return pnr_report_str, total_area
+
+def run_sim():
+  # Create a modelsim folder
+  #subprocess.call("mkdir -p"+os.path.expanduser("./modelsim_dir")+"\n", shell=True)
+  # Create a modelsim .do file:
+  #subprocess.call("vlib modelsim_dir/libraries"+"\n",shell=True)
+  # todo: change the address and take it from the user as input
+  #subprocess.call("vlog -work modelsim_dir/libraries /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/verilog/tcbn65gplus_140b/tcbn65gplus.v /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/verilog/tpzn65gpgv2_140c/tpzn65gpgv2.v"+"\n",shell=True)
+  file = open("modelsim.do", "w")
+  file.write("cd " + os.path.expanduser("./modelsim_dir") + "\n")
+  file.write("vlib work \n")
+  file.write("vlog -work work ../../test/testbench.v \n")
+  file.write("vlog -work work ../../pr/netlist.v \n")
+  file.write("vsim -L work -L libraries testbench\n")
+  file.write("vcd file vcd.vcd \n")
+  file.write("vcd add -r testbench/uut/* \n")
+  file.write("run 1000 ns \n")
+  file.write("quit \n")
+  file.close()      
+  subprocess.call('vsim -c -do modelsim.do', shell=True)           
+  subprocess.call('rm -rf modelsim.do', shell=True)
+  subprocess.call('vcd2wlf ./modelsim_dir/vcd.vcd out.wlf', shell=True)
+  subprocess.call('wlf2vcd -o test.vcd out.wlf', shell=True)
+  subprocess.call('vcd2saif -input test.vcd -o saif.saif', shell=True)
+
+def run_power_timing(flow_settings,mode_enabled,clock_period,pnr_report_str):
+  ###########################################
+  # Primetime
+  ###########################################
+  if not mode_enabled:
+    x = 2**len(flow_settings['mode_signal'])
+  # backannotate into primetime
+  # This part should be reported for all the modes in the design.
+  file = open("primetime.tcl", "w")
+  file.write("set sh_enable_page_mode true \n")
+  file.write("set search_path " + flow_settings['primetime_lib_path'] + " \n")
+  file.write("set my_top_level " + flow_settings['top_level'] + "\n")
+  file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
+  file.write("set target_library " + flow_settings['target_libraries'] + "\n")
+  file.write("set link_library " + flow_settings['link_libraries'] + "\n")
+  file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
+  if mode_enabled and x <2**len(flow_settings['mode_signal']):
+    for y in range (0, len(flow_settings['mode_signal'])):
+      file.write("set_case_analysis " + str((x >> y) & 1) + " " +  flow_settings['mode_signal'][y] + " \n")
+  file.write("link \n")
+  file.write("set my_period " + str(clock_period) + " \n")
+  file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
+  file.write("if { $find_clock != [list] } { \n")
+  file.write("set clk_name $my_clock_pin \n")
+  file.write("create_clock -period $my_period $clk_name} \n\n")
+  file.write("read_parasitics -increment " + os.path.expanduser(flow_settings['pr_folder']) + "/spef.spef \n")
+  file.write("report_timing > " + os.path.expanduser(flow_settings['primetime_folder']) + "/timing.rpt \n")
+  file.write("quit \n")
+  file.close()
+  # run prime time
+  subprocess.call('dc_shell-t -f primetime.tcl | tee pt.log', shell=True,executable="/bin/bash") 
+  # Read timing parameters
+  file = open(os.path.expanduser(flow_settings['primetime_folder']) + "/timing.rpt" ,"r")
+  for line in file:
+    if 'library setup time' in line:
+      library_setup_time = re.findall(r'\d+\.{0,1}\d*', line)
+    if 'data arrival time' in line:
+      data_arrival_time = re.findall(r'\d+\.{0,1}\d*', line)
+  try:
+    total_delay =  float(library_setup_time[0]) + float(data_arrival_time[0])
+  except NameError:
+    total_delay =  float(data_arrival_time[0])
+  file.close()
+  # Create a script to measure power:
+  file = open("primetime_power.tcl", "w")
+  file.write("set sh_enable_page_mode true \n")
+  file.write("set search_path " + flow_settings['primetime_lib_path'] + " \n")
+  file.write("set my_top_level " + flow_settings['top_level'] + "\n")
+  file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
+  file.write("set target_library " + flow_settings['target_libraries'] + "\n")
+  file.write("set link_library " + flow_settings['link_libraries'] + "\n")
+  file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
+  file.write("link \n")
+  file.write("set my_period " + str(clock_period) + " \n")
+  file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
+  file.write("if { $find_clock != [list] } { \n")
+  file.write("set clk_name $my_clock_pin \n")
+  file.write("create_clock -period $my_period $clk_name} \n\n")
+  if mode_enabled and x <2**len(flow_settings['mode_signal']):
+    for y in range (0, len(flow_settings['mode_signal'])):
+      file.write("set_case_analysis " + str((x >> y) & 1) + " " +  flow_settings['mode_signal'][y] +  " \n")
+  file.write("set power_enable_analysis TRUE \n")
+  file.write(r'set power_analysis_mode "averaged"' + "\n")
+  if flow_settings['generate_activity_file']:
+    file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
+  else:
+    file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " -base_clock $my_clock_pin -type inputs \n")
+  #file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
+  #file.write("read_vcd -input ./modelsim_dir/vcd.vcd \n")
+  file.write(r'read_parasitics -increment ' + os.path.expanduser(flow_settings['pr_folder']) + r'/spef.spef' + "\n")
+  #file.write("update_power \n")
+  file.write(r'report_power > ' + os.path.expanduser(flow_settings['primetime_folder']) + r'/power.rpt' + " \n")
+  file.write("quit\n")
+  file.close()
+
+  # run prime time
+  subprocess.call('dc_shell-t -f primetime_power.tcl | tee pt_pwr.log', shell=True,executable="/bin/bash") 
+  #copy reports and logs to a unique dir in pt dir
+  pt_report_str = pnr_report_str + "_" + "mode_" + str(x)
+  report_dest_str = os.path.expanduser(flow_settings['primetime_folder']) + "/" + pt_report_str + "_reports"
+  mkdir_cmd_str = "mkdir -p " + report_dest_str
+  copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['primetime_folder']) + "/*.rpt " + report_dest_str
+  copy_logs_cmd_str = "cp " + "pt.log pt_pwr.log primetime.tcl primetime_power.tcl " + report_dest_str
+  subprocess.call(mkdir_cmd_str,shell=True)
+  subprocess.call(copy_rep_cmd_str,shell=True)
+  subprocess.call(copy_logs_cmd_str,shell=True)
+  subprocess.call('rm -f pt.log pt_pwr.log primetime.tcl primetime_power.tcl', shell=True)
+  # Read dynamic power
+  file = open(os.path.expanduser(flow_settings['primetime_folder']) + "/power.rpt" ,"r")
+  for line in file:
+    if 'Total Dynamic Power' in line:
+      total_dynamic_power = re.findall(r'\d+\.{0,1}\d*', line)
+      total_dynamic_power[0] = float(total_dynamic_power[0])
+      if 'mW' in line:
+        total_dynamic_power[0] *= 0.001
+      elif 'uw' in line:
+        total_dynamic_power[0] *= 0.000001
+      else:
+        total_dynamic_power[0] = 0
+  file.close() 
+  return library_setup_time, data_arrival_time, total_delay, total_dynamic_power   
+    
 # wire loads in the library are WireAreaLowkCon WireAreaLowkAgr WireAreaForZero
 def hardblock_flow(flow_settings):
 
@@ -20,485 +435,43 @@ def hardblock_flow(flow_settings):
   lowest_cost_delay = 1.0
   lowest_cost_power = 1.0
 
-  ###########################################
-  # Synthesis
-  ###########################################
   design_files = []
   if flow_settings['design_language'] == 'verilog':
-    design_files = [fn for _, _, fs in os.walk(flow_settings['design_folder']) for fn in fs if fn.endswith(".v")]
+    ext_re = re.compile(".*.v")
   elif flow_settings['design_language'] == 'vhdl':
-    design_files = [fn for _, _, fs in os.walk(flow_settings['design_folder']) for fn in fs if fn.endswith(".vhdl")]
+    ext_re = re.compile(".*.vhdl")
   elif flow_settings['design_language'] == 'sverilog':
-    design_files = [fn for _, _, fs in os.walk(flow_settings['design_folder']) for fn in fs if fn.endswith(".sv") or fn.endswith(".v")]
+    ext_re = re.compile(".*(.sv)|(.v)")
+
+  design_folder = os.path.expanduser(flow_settings['design_folder'])
+  design_files = [fn for _, _, fs in os.walk(design_folder) for fn in fs if ext_re.search(fn)]
+  search_path_dirs = []
+  search_path_dirs.append(design_folder)
+  for root,dirnames,fnames in os.walk(design_folder):
+    for dirname,fname in zip(dirnames,fnames):
+      if(ext_re.search(fname)):
+        search_path_dirs.append(os.path.join(root,dirname))
   subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['synth_folder']) + "\n", shell=True)
+  subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['pr_folder']) + "\n", shell=True)
+  subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['primetime_folder']) + "\n", shell=True)
   # Make sure we managed to read the design files
   assert len(design_files) >= 1
   for clock_period in flow_settings['clock_period']:
     for wire_selection in flow_settings['wire_selection']:
-      file = open("dc_script.tcl","w")
-      file.write("cd " + os.path.expanduser(flow_settings['synth_folder']) + "\n")
-      file.write("set search_path " + flow_settings['design_folder'] + " \n")
-      if len(design_files) == 1:
-        file.write("set my_files " + design_files[0] + "\n")
-      else:
-        file.write("set my_files [list ")
-        for entity in design_files:
-          if not (entity == "parameters.v" or entity == "c_functions.v"):
-            file.write(entity + " ")
-        file.write("] \n")
-      file.write("set my_top_level " + flow_settings['top_level'] + "\n")
-      file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-      file.write("set link_library " + flow_settings['link_libraries'] + "\n")
-      file.write("set target_library " + flow_settings['target_libraries'] + "\n")
-      file.write(r'set power_analysis_mode "averaged"' + "\n")
-      file.write("define_design_lib WORK -path ./WORK \n")
-      if flow_settings['design_language'] == 'verilog':
-        file.write("analyze -f verilog $my_files \n")
-      elif flow_settings['design_language'] == 'vhdl':
-        file.write("analyze -f vhdl $my_files \n")
-      else:
-        file.write("analyze -f sverilog $my_files \n")
-      file.write("elaborate $my_top_level \n")
-      file.write("current_design $my_top_level \n")
-      file.write("check_design >  " + os.path.expanduser(flow_settings['synth_folder']) + "/checkprecompile.rpt\n")
-      file.write("link \n")
-      file.write("uniquify \n")
-      #If wire_selection is None, then no wireload model is used during synthesis. This does imply results 
-      #are not as accurate (wires don't have any delay and area), but is useful to let the flow work/proceed 
-      #if the std cell library is missing wireload models.
-      if wire_selection != "None":
-        file.write(r'set_wire_load_selection ' + wire_selection + " \n")
-      file.write("set my_period " + str(clock_period) + " \n")
-      file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
-      file.write("if { $find_clock != [list] } { \n")
-      file.write("set clk_name $my_clock_pin \n")
-      file.write("create_clock -period $my_period $clk_name} \n\n")
-      file.write("compile_ultra\n")
-      file.write("check_design >  " + os.path.expanduser(flow_settings['synth_folder']) + "/check.rpt\n")
-      file.write("link \n")
-      file.write("write_file -format ddc -hierarchy -output " + os.path.expanduser(flow_settings['synth_folder']) + "/" +  flow_settings['top_level']  + ".ddc \n")
-
-      if flow_settings['read_saif_file']:
-        file.write("read_saif saif.saif \n")
-      else:
-        file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " [all_nets] \n")
-
-      file.write("ungroup -all -flatten \n")
-      file.write("report_power > " + os.path.expanduser(flow_settings['synth_folder']) + "/power.rpt\n")
-      file.write("report_area -nosplit -hierarchy > " + os.path.expanduser(flow_settings['synth_folder']) + "/area.rpt\n")
-      file.write("report_resources -nosplit -hierarchy > " + os.path.expanduser(flow_settings['synth_folder']) + "/resources.rpt\n")      
-      file.write("report_timing > " + os.path.expanduser(flow_settings['synth_folder']) + "/timing.rpt\n")
-      file.write("change_names -hier -rule verilog \n") 
-      
-      file.write("write -f verilog -output " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.v\n")
-      file.write("write_sdf " + os.path.expanduser(flow_settings['synth_folder']) + "/synthsized.sdf \n")
-      file.write("write_parasitics -output " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.spef \n")
-      file.write("write_sdc " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.sdc \n")
-
-      file.write("quit \n")
-      file.close()
-
-      # Run the scrip in design compiler shell
-      subprocess.call('dc_shell-t -f dc_script.tcl | tee dc.log', shell=True) 
-      # clean after DC!
-      subprocess.call('rm -rf command.log', shell=True)
-      subprocess.call('rm -rf default.svf', shell=True)
-      subprocess.call('rm -rf filenames.log', shell=True)
-
-      # Make sure it worked properly
-      # Open the timing report and make sure the critical path is non-zero:
-      check_file = open(os.path.expanduser(flow_settings['synth_folder']) + "/check.rpt", "r")
-      for line in check_file:
-        if "Error" in line:
-          print "Your design has errors. Refer to check.rpt in synthesis directory"
-          exit(-1)
-        elif "Warning" in line and flow_settings['show_warnings']:
-          print "Your design has warnings. Refer to check.rpt in synthesis directory"
-          print "In spite of the warning, the rest of the flow will continue to execute."
-      check_file.close()
-
-      #Copy synthesis results to a unique dir in synth dir
-      synth_report_str = "period_" + clock_period + "_" + "wire_mdl_" + wire_selection
-      report_dest_str = os.path.expanduser(flow_settings['synth_folder']) + "/" + synth_report_str + "_reports"
-      mkdir_cmd_str = "mkdir -p " + report_dest_str
-      copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['synth_folder']) + "/*.rpt " + report_dest_str
-      copy_logs_cmd_str = "cp " + "dc.log "+ "dc_script.tcl " + report_dest_str
-      subprocess.call(mkdir_cmd_str,shell=True)
-      subprocess.call(copy_rep_cmd_str,shell=True)
-      subprocess.call(copy_logs_cmd_str,shell=True)
-      subprocess.call('rm -f dc.log dc_script.tcl',shell=True)
-
-      #if the user doesn't want to perform place and route, extract the results from DC reports and end
-      if flow_settings['synthesis_only']:
-
-        # read total area from the report file:
-        file = open(os.path.expanduser(flow_settings['synth_folder']) + "/area.rpt" ,"r")
-        for line in file:
-          if line.startswith('Total cell area:'):
-            total_area = re.findall(r'\d+\.{0,1}\d*', line)
-        file.close()
-
-        # Read timing parameters
-        file = open(os.path.expanduser(flow_settings['synth_folder']) + "/timing.rpt" ,"r")
-        for line in file:
-          if 'library setup time' in line:
-            library_setup_time = re.findall(r'\d+\.{0,1}\d*', line)
-          if 'data arrival time' in line:
-            data_arrival_time = re.findall(r'\d+\.{0,1}\d*', line)
-        try:
-          total_delay =  float(library_setup_time[0]) + float(data_arrival_time[0])
-        except NameError:
-          total_delay =  float(data_arrival_time[0])
-        
-        file.close()    
-
-        # Read dynamic power
-        file = open(os.path.expanduser(flow_settings['synth_folder']) + "/power.rpt" ,"r")
-        for line in file:
-          if 'Total Dynamic Power' in line:
-            total_dynamic_power = re.findall(r'\d+\.\d*', line)
-            total_dynamic_power[0] = float(total_dynamic_power[0])
-            if 'mW' in line:
-              total_dynamic_power[0] *= 0.001
-            elif 'uw' in line:
-              total_dynamic_power[0] *= 0.000001
-            else:
-              total_dynamic_power[0] = 0
-        file.close()
-
-        # write the final report file:
-        file = open("report.txt" ,"w")
-        file.write("total area = "  + str(total_area[0]) +  "\n")
-        file.write("total delay = " + str(total_delay) + " ns\n")
-        file.write("total power = " + str(total_dynamic_power[0]) + " W\n")
-        file.close()
-
-        #return
-        exit()
-
-      ###########################################
-      # Place and Route
-      ###########################################
-      subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['pr_folder']) + "\n", shell=True)
+      synth_report_str = run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_selection)
       for metal_layer in flow_settings['metal_layers']:
         for core_utilization in flow_settings['core_utilization']:
-          # generate the EDI (encounter) configuration
-          file = open("edi.conf", "w")
-          file.write("global rda_Input \n")
-          file.write("set cwd .\n\n")
-          file.write("set rda_Input(ui_leffile) " + flow_settings['lef_files'] + "\n")
-          file.write("set rda_Input(ui_timelib,min) " + flow_settings['best_case_libs'] + "\n")
-          file.write("set rda_Input(ui_timelib) " + flow_settings['standard_libs'] + "\n")
-          file.write("set rda_Input(ui_timelib,max) " + flow_settings['worst_case_libs'] + "\n")
-          file.write("set rda_Input(ui_netlist) " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.v" + "\n")
-          file.write("set rda_Input(ui_netlisttype) {Verilog} \n")
-          file.write("set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1}\n")
-          file.write("set rda_Input(ui_timingcon_file) " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.sdc" + "\n")
-          file.write("set rda_Input(ui_topcell) " + flow_settings['top_level'] + "\n\n")
-
-          gnd_pin = flow_settings['gnd_pin']
-          gnd_net = flow_settings['gnd_net']
-          pwr_pin = flow_settings['pwr_pin']
-          pwr_net = flow_settings['pwr_net']
-          file.write("set rda_Input(ui_gndnet) {" + gnd_net + "} \n")
-          file.write("set rda_Input(ui_pwrnet) {" + pwr_net + "} \n")
-          
-          if flow_settings['tilehi_tielo_cells_between_power_gnd'] is True:
-            file.write("set rda_Input(ui_pg_connections) [list {PIN:" + gnd_pin + ":}" + " {TIEL::} " + "{NET:" + gnd_net + ":} {NET:" + pwr_net + ":}" + " {TIEH::} " + "{PIN:" + pwr_pin + ":} ] \n")
-          else:
-            file.write("set rda_Input(ui_pg_connections) [list {PIN:" + gnd_pin + ":} {NET:" + gnd_net + ":} {NET:" + pwr_net + ":} {PIN:" + pwr_pin + ":} ] \n")
-
-          file.write("set rda_Input(PIN:" + gnd_pin + ":) {" + gnd_pin + "} \n")
-          file.write("set rda_Input(TIEL::) {" + gnd_pin + "} \n")
-          file.write("set rda_Input(NET:" + gnd_net + ":) {" + gnd_net + "} \n")
-          file.write("set rda_Input(PIN:" + pwr_pin + ":) {" + pwr_pin + "} \n")
-          file.write("set rda_Input(TIEH::) {" + pwr_pin + "} \n")
-          file.write("set rda_Input(NET:" + pwr_net + ":) {" + pwr_net + "} \n\n")
-
-          if (flow_settings['inv_footprint'] != "None"):
-            file.write("set rda_Input(ui_inv_footprint) {" + flow_settings['inv_footprint'] + "}\n")
-          
-          if (flow_settings['buf_footprint'] != "None"):
-            file.write("set rda_Input(ui_buf_footprint) {" + flow_settings['buf_footprint'] + "}\n")
-
-          if (flow_settings['delay_footprint'] != "None"):
-            file.write("set rda_Input(ui_delay_footprint) {" + flow_settings['delay_footprint'] + "}\n")
-
-          file.close()
-
-          metal_layer_bottom = flow_settings["metal_layer_names"][0]
-          metal_layer_second = flow_settings["metal_layer_names"][1]
-          metal_layer_top = flow_settings["metal_layer_names"][int(metal_layer)-1]
-          power_ring_metal_top = flow_settings["power_ring_metal_layer_names"][0] 
-          power_ring_metal_bottom = flow_settings["power_ring_metal_layer_names"][1] 
-          power_ring_metal_left = flow_settings["power_ring_metal_layer_names"][2] 
-          power_ring_metal_right = flow_settings["power_ring_metal_layer_names"][3] 
-
-          # generate the EDI (encounter) script
-          file = open("edi.tcl", "w")
-          file.write("loadConfig edi.conf \n")
-          file.write("floorPlan -site " + flow_settings['core_site_name'] \
-                     + " -r " + str(flow_settings['height_to_width_ratio']) \
-                     + " " + str(core_utilization) \
-                     + " " + str(flow_settings['space_around_core']) \
-                     + " " + str(flow_settings['space_around_core']) + " ")
-          file.write(str(flow_settings['space_around_core']) + " " + str(flow_settings['space_around_core']) + "\n")
-          file.write("setMaxRouteLayer " + str(metal_layer) + " \n")
-          file.write("fit \n")
-          file.write("addRing -spacing_bottom " + str(flow_settings['power_ring_spacing']) \
-                     + " -spacing_right " + str(flow_settings['power_ring_spacing']) \
-                     + " -spacing_top " + str(flow_settings['power_ring_spacing']) \
-                     + " -spacing_left " + str(flow_settings['power_ring_spacing']) \
-                     + " -width_right " + str(flow_settings['power_ring_width']) \
-                     + " -width_left " + str(flow_settings['power_ring_width']) \
-                     + " -width_bottom " + str(flow_settings['power_ring_width']) \
-                     + " -width_top " + str(flow_settings['power_ring_width']) \
-                     + " -center 1" \
-                     + " -around core" \
-                     + " -layer_top " + power_ring_metal_top \
-                     + " -layer_bottom " + power_ring_metal_bottom \
-                     + " -layer_left " + power_ring_metal_left \
-                     + " -layer_right " + power_ring_metal_right \
-                     + " -nets { " + gnd_net + " " + pwr_net + " }" \
-                     + " -stacked_via_top_layer "+ metal_layer_top \
-                     + " -stacked_via_bottom_layer " + metal_layer_bottom + " \n")
-
-          file.write("setPlaceMode -fp false -maxRouteLayer " + str(metal_layer) + "\n")
-          file.write("placeDesign -inPlaceOpt -noPrePlaceOpt \n")
-          file.write("checkPlace " + flow_settings['top_level'] +" \n")
-
-          file.write("trialroute \n")
-          file.write("buildTimingGraph \n")
-          file.write("timeDesign -preCTS -idealClock -numPaths 10 -prefix preCTS -outDir " + os.path.expanduser(flow_settings['pr_folder']) + "/timeDesignpreCTSReports" + "\n")
-          file.write("optDesign -preCTS -outDir " + os.path.expanduser(flow_settings['pr_folder']) + "/optDesignpreCTSReports" + "\n")
-          # I won't do a CTS anyway as the blocks are small.
-
-          file.write("addFiller -cell {" + " ".join([str(item) for item in flow_settings['filler_cell_names']]) + "} -prefix FILL -merge true \n")  
-          
-          file.write("clearGlobalNets \n")
-          file.write("globalNetConnect " + gnd_net + " -type pgpin -pin " + gnd_pin + " -inst {} \n")
-          file.write("globalNetConnect " + pwr_net + " -type pgpin -pin " + pwr_pin + " -inst {} \n")
-          file.write("globalNetConnect " + gnd_net + " -type net -net " + gnd_net + " \n")
-          file.write("globalNetConnect " + pwr_net + " -type net -net " + pwr_net + " \n")
-          file.write("globalNetConnect " + pwr_net + " -type pgpin -pin " + pwr_pin + " -inst * \n")
-          file.write("globalNetConnect " + gnd_net + " -type pgpin -pin " + gnd_pin + " -inst * \n")
-          file.write("globalNetConnect " + pwr_net + " -type tiehi -inst * \n")
-          file.write("globalNetConnect " + gnd_net + " -type tielo -inst * \n")
-
-          file.write("sroute -connect { blockPin padPin padRing corePin floatingStripe }" \
-                     + " -layerChangeRange { " + metal_layer_bottom + " " + metal_layer_top + " }" \
-                     + " -blockPinTarget { nearestRingStripe nearestTarget }" \
-                     + " -padPinPortConnect { allPort oneGeom }" \
-                     + " -checkAlignedSecondaryPin 1" \
-                     + " -blockPin useLef" \
-                     + " -allowJogging 1" \
-                     + " -crossoverViaBottomLayer " + metal_layer_bottom \
-                     + " -allowLayerChange 1" \
-                     + " -targetViaTopLayer " + metal_layer_top \
-                     + " -crossoverViaTopLayer " + metal_layer_top \
-                     + " -targetViaBottomLayer " + metal_layer_bottom \
-                     + " -nets { " + gnd_net + " " + pwr_net + " } \n")
-
-          file.write("routeDesign -globalDetail\n")
-          file.write("setExtractRCMode -engine postRoute \n")
-          file.write("extractRC \n")
-          file.write("buildTimingGraph \n")
-          file.write("timeDesign -postRoute -outDir " + os.path.expanduser(flow_settings['pr_folder']) + "/timeDesignReports" + "\n")
-          file.write("optDesign -postRoute -outDir " + os.path.expanduser(flow_settings['pr_folder']) + "/optDesignReports" + "\n")
-
-          #by default, violations are reported in designname.geom.rpt
-          file.write("verifyGeometry -report " + (os.path.expanduser(flow_settings['pr_folder']) + "/" + flow_settings['top_level'] + ".geom.rpt") + "\n")
-          #by default, violations are reported in designname.conn.rpt
-          file.write("verifyConnectivity -type all -report " + (os.path.expanduser(flow_settings['pr_folder']) + "/" + flow_settings['top_level'] + ".conn.rpt") + "\n")
-
-          # report area
-          file.write("summaryReport -outFile " + os.path.expanduser(flow_settings['pr_folder']) + "/pr_report.txt \n")
-
-          # save design
-          file.write(r'saveNetlist ' + os.path.expanduser(flow_settings['pr_folder']) + r'/netlist.v' + "\n")
-          file.write(r'saveDesign ' + os.path.expanduser(flow_settings['pr_folder']) + r'/design.enc' + " \n")
-          file.write(r'rcOut -spef ' + os.path.expanduser(flow_settings['pr_folder']) + r'/spef.spef' + " \n")
-          file.write(r'write_sdf -ideal_clock_network ' + os.path.expanduser(flow_settings['pr_folder']) + r'/sdf.sdf' + " \n")
-          #If the user specified a layer mapping file, then use that. Otherwise, just let the tool create a default one.
-          if flow_settings['map_file'] != "None":
-            file.write(r'streamOut ' + os.path.expanduser(flow_settings['pr_folder']) + r'/final.gds2' + ' -mapFile ' + flow_settings['map_file'] + ' -stripes 1 -units 1000 -mode ALL' + "\n")
-          else:
-            file.write(r'streamOut ' + os.path.expanduser(flow_settings['pr_folder']) + r'/final.gds2' + ' -stripes 1 -units 1000 -mode ALL' + "\n")
-          file.write("exit \n")
-          file.close()
-
-          # Run the scrip in EDI
-          subprocess.call('encounter -nowin -init edi.tcl | tee edi.log', shell=True) 
-          # clean after EDI!
-          subprocess.call('mv encounter.log ' + os.path.expanduser(flow_settings['pr_folder']) + '/encounter_log.log', shell=True)
-          subprocess.call('mv encounter.cmd ' + os.path.expanduser(flow_settings['pr_folder']) + '/encounter.cmd', shell=True)
-          
-          # read total area from the report file:
-          file = open(os.path.expanduser(flow_settings['pr_folder']) + "/pr_report.txt" ,"r")
-          for line in file:
-            if line.startswith('Total area of Core:'):
-              total_area = re.findall(r'\d+\.{0,1}\d*', line)
-          file.close()
-          
-          #Copy pnr results to a unique dir in pnr dir
-          pnr_report_str = synth_report_str + "_" + "metal_layers_" + metal_layer + "_" + "util_" + core_utilization
-          report_dest_str = os.path.expanduser(flow_settings['pr_folder']) + "/" + pnr_report_str + "_reports"
-          mkdir_cmd_str = "mkdir -p " + report_dest_str
-          copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['pr_folder']) + "/*.rpt " + os.path.expanduser(flow_settings['pr_folder']) + "/pr_report.txt " + report_dest_str
-          copy_logs_cmd_str = "cp " + "edi.log " + "edi.tcl " + "edi.conf " + report_dest_str
-          subprocess.call(mkdir_cmd_str,shell=True)
-          subprocess.call(copy_rep_cmd_str,shell=True)
-          subprocess.call(copy_logs_cmd_str,shell=True)
-          subprocess.call('rm -f edi.log edi.conf edi.tcl', shell=True)
-
+          pnr_report_str, total_area = run_pnr(flow_settings,metal_layer,core_utilization,synth_report_str)
           if len(flow_settings['mode_signal']) > 0:
             mode_enabled = True
           else:
             mode_enabled = False
           the_power = 0.0
-
           # Optional: use modelsim to generate an activity file for the design:
           if flow_settings['generate_activity_file'] is True:
-            # Create a modelsim folder
-            #subprocess.call("mkdir -p"+os.path.expanduser("./modelsim_dir")+"\n", shell=True)
-            # Create a modelsim .do file:
-            #subprocess.call("vlib modelsim_dir/libraries"+"\n",shell=True)
-            # todo: change the address and take it from the user as input
-            #subprocess.call("vlog -work modelsim_dir/libraries /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/verilog/tcbn65gplus_140b/tcbn65gplus.v /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/verilog/tpzn65gpgv2_140c/tpzn65gpgv2.v"+"\n",shell=True)
-            
-            
-            file = open("modelsim.do", "w")
-            file.write("cd " + os.path.expanduser("./modelsim_dir") + "\n")
-            file.write("vlib work \n")
-            file.write("vlog -work work ../../test/testbench.v \n")
-            file.write("vlog -work work ../../pr/netlist.v \n")
-            file.write("vsim -L work -L libraries testbench\n")
-            file.write("vcd file vcd.vcd \n")
-            file.write("vcd add -r testbench/uut/* \n")
-            file.write("run 1000 ns \n")
-            file.write("quit \n")
-            file.close()      
-
-            subprocess.call('vsim -c -do modelsim.do', shell=True)           
-            subprocess.call('rm -rf modelsim.do', shell=True)
-            subprocess.call('vcd2wlf ./modelsim_dir/vcd.vcd out.wlf', shell=True)
-            subprocess.call('wlf2vcd -o test.vcd out.wlf', shell=True)
-            subprocess.call('vcd2saif -input test.vcd -o saif.saif', shell=True)
-          
-
-          ###########################################
-          # Primetime
-          ###########################################
+            run_sim()
           for x in range(0, 2**len(flow_settings['mode_signal']) + 1):
-            if not mode_enabled:
-              x = 2**len(flow_settings['mode_signal'])
-            # backannotate into primetime
-            # This part should be reported for all the modes in the design.
-            subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['primetime_folder']) + "\n", shell=True)
-            file = open("primetime.tcl", "w")
-            file.write("set sh_enable_page_mode true \n")
-
-            file.write("set search_path " + flow_settings['primetime_lib_path'] + " \n")
-            file.write("set my_top_level " + flow_settings['top_level'] + "\n")
-            file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-            file.write("set target_library " + flow_settings['target_libraries'] + "\n")
-            file.write("set link_library " + flow_settings['link_libraries'] + "\n")
-
-            file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
-            if mode_enabled and x <2**len(flow_settings['mode_signal']):
-              for y in range (0, len(flow_settings['mode_signal'])):
-                file.write("set_case_analysis " + str((x >> y) & 1) + " " +  flow_settings['mode_signal'][y] + " \n")
-            file.write("link \n")
-            
-            file.write("set my_period " + str(clock_period) + " \n")
-            file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
-            file.write("if { $find_clock != [list] } { \n")
-            file.write("set clk_name $my_clock_pin \n")
-            file.write("create_clock -period $my_period $clk_name} \n\n")
-
-            file.write("read_parasitics -increment " + os.path.expanduser(flow_settings['pr_folder']) + "/spef.spef \n")
-            file.write("report_timing > " + os.path.expanduser(flow_settings['primetime_folder']) + "/timing.rpt \n")
-            file.write("quit \n")
-            file.close()
-
-            # run prime time
-            subprocess.call('dc_shell-t -f primetime.tcl | tee pt.log', shell=True) 
-
-            # Read timing parameters
-            file = open(os.path.expanduser(flow_settings['primetime_folder']) + "/timing.rpt" ,"r")
-            for line in file:
-              if 'library setup time' in line:
-                library_setup_time = re.findall(r'\d+\.{0,1}\d*', line)
-              if 'data arrival time' in line:
-                data_arrival_time = re.findall(r'\d+\.{0,1}\d*', line)
-            try:
-              total_delay =  float(library_setup_time[0]) + float(data_arrival_time[0])
-            except NameError:
-              total_delay =  float(data_arrival_time[0])
-            file.close()
-            # Create a script to measure power:
-            file = open("primetime_power.tcl", "w")
-            file.write("set sh_enable_page_mode true \n")
-
-            file.write("set search_path " + flow_settings['primetime_lib_path'] + " \n")
-            file.write("set my_top_level " + flow_settings['top_level'] + "\n")
-            file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-            file.write("set target_library " + flow_settings['target_libraries'] + "\n")
-            file.write("set link_library " + flow_settings['link_libraries'] + "\n")
-
-            file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
-            file.write("link \n")
-
-            file.write("set my_period " + str(clock_period) + " \n")
-            file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
-            file.write("if { $find_clock != [list] } { \n")
-            file.write("set clk_name $my_clock_pin \n")
-            file.write("create_clock -period $my_period $clk_name} \n\n")
-            if mode_enabled and x <2**len(flow_settings['mode_signal']):
-              for y in range (0, len(flow_settings['mode_signal'])):
-                file.write("set_case_analysis " + str((x >> y) & 1) + " " +  flow_settings['mode_signal'][y] +  " \n")
-            file.write("set power_enable_analysis TRUE \n")
-            file.write(r'set power_analysis_mode "averaged"' + "\n")
-            if flow_settings['generate_activity_file']:
-							file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
-            else:
-              file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " -base_clock $my_clock_pin -type inputs \n")
-            #file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
-            #file.write("read_vcd -input ./modelsim_dir/vcd.vcd \n")
-            file.write(r'read_parasitics -increment ' + os.path.expanduser(flow_settings['pr_folder']) + r'/spef.spef' + "\n")
-            #file.write("update_power \n")
-            file.write(r'report_power > ' + os.path.expanduser(flow_settings['primetime_folder']) + r'/power.rpt' + " \n")
-            file.write("quit\n")
-            file.close()
-
-            # run prime time
-            subprocess.call('dc_shell-t -f primetime_power.tcl | tee pt_pwr.log', shell=True) 
-
-            #copy reports and logs to a unique dir in pt dir
-            pt_report_str = pnr_report_str + "_" + "mode_" + str(x)
-            report_dest_str = os.path.expanduser(flow_settings['primetime_folder']) + "/" + pt_report_str + "_reports"
-            mkdir_cmd_str = "mkdir -p " + report_dest_str
-            copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['primetime_folder']) + "/*.rpt " + report_dest_str
-            copy_logs_cmd_str = "cp " + "pt.log pt_pwr.log primetime.tcl primetime_power.tcl " + report_dest_str
-            subprocess.call(mkdir_cmd_str,shell=True)
-            subprocess.call(copy_rep_cmd_str,shell=True)
-            subprocess.call(copy_logs_cmd_str,shell=True)
-            subprocess.call('rm -f pt.log pt_pwr.log primetime.tcl primetime_power.tcl', shell=True)
-            
-            # Read dynamic power
-            file = open(os.path.expanduser(flow_settings['primetime_folder']) + "/power.rpt" ,"r")
-            for line in file:
-              if 'Total Dynamic Power' in line:
-                total_dynamic_power = re.findall(r'\d+\.{0,1}\d*', line)
-                total_dynamic_power[0] = float(total_dynamic_power[0])
-                if 'mW' in line:
-                  total_dynamic_power[0] *= 0.001
-                elif 'uw' in line:
-                  total_dynamic_power[0] *= 0.000001
-                else:
-                  total_dynamic_power[0] = 0
-            file.close()    
-
+            library_setup_time, data_arrival_time, total_delay, total_dynamic_power = run_power_timing(flow_settings,mode_enabled,clock_period,pnr_report_str)
             # write the final report file:
             if mode_enabled and x <2**len(flow_settings['mode_signal']):
               file = open("report_mode" + str(x) + "_" + str(flow_settings['top_level']) + "_" + str(clock_period) + "_" + str(wire_selection) + "_wire_" + str(metal_layer) + "_" + str(core_utilization) + ".txt" ,"w")
@@ -510,13 +483,11 @@ def hardblock_flow(flow_settings):
             file.close()
             if total_dynamic_power[0] > the_power:
               the_power = total_dynamic_power[0]
-              
             if lowest_cost > math.pow(float(total_area[0]), float(flow_settings['area_cost_exp'])) * math.pow(float(total_delay), float(flow_settings['delay_cost_exp'])):
               lowest_cost = math.pow(float(total_area[0]), float(flow_settings['area_cost_exp'])) * math.pow(float(total_delay), float(flow_settings['delay_cost_exp']))
               lowest_cost_area = float(total_area[0])
               lowest_cost_delay = float(total_delay)
               lowest_cost_power = float(the_power)
-              
             del total_dynamic_power[:]
             del library_setup_time[:]
             del data_arrival_time[:]
diff --git a/coffe/utils.py b/coffe/utils.py
index 3664eed..664d72e 100644
--- a/coffe/utils.py
+++ b/coffe/utils.py
@@ -1197,7 +1197,7 @@ def create_output_dir(arch_file_name, arch_out_folder):
         arch_desc_words = arch_file_name.split('.')
         arch_folder = arch_desc_words[0]
     else:
-        arch_folder = arch_out_folder
+        arch_folder = os.path.expanduser(arch_out_folder)
 
     if not os.path.exists(arch_folder):
         os.makedirs(arch_folder)
diff --git a/input_files/simple_dsp_slice_65nm/coffe_inp_params.txt b/input_files/simple_dsp_slice_65nm/coffe_inp_params.txt
index 7d2ea31..097eb12 100644
--- a/input_files/simple_dsp_slice_65nm/coffe_inp_params.txt
+++ b/input_files/simple_dsp_slice_65nm/coffe_inp_params.txt
@@ -15,7 +15,7 @@
 
 #The directory in which output files will be stored. 
 #If not specified, the directory containing this file is used as output dir.
-arch_out_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/arch_out_dir
+arch_out_folder=~/COFFE/output_files/simple_dsp_slice_65nm/arch_out_dir
 
 #######################################
 ##### Architecture Parameters
diff --git a/input_files/simple_dsp_slice_65nm/dsp_slice.txt b/input_files/simple_dsp_slice_65nm/dsp_slice.txt
index b142549..cb67c87 100644
--- a/input_files/simple_dsp_slice_65nm/dsp_slice.txt
+++ b/input_files/simple_dsp_slice_65nm/dsp_slice.txt
@@ -8,7 +8,7 @@
 ########## General Design Settings ##########
 #############################################
 # The folder in which all the design files are located:
-design_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/input_files/simple_dsp_slice_65nm/dsp_slice_hdl
+design_folder=~/COFFE/input_files/simple_dsp_slice_65nm/dsp_slice_hdl
 
 # The design language. Should be either 'verilog', 'vhdl' or 'sverilog'
 design_language=verilog
@@ -26,13 +26,13 @@ area_cost_exp=1.0
 clock_pin_name=clk
 
 # Desired clock period in ns
-clock_period=3.0
+clock_period=1.82
 
 # Name of the top-level entity in the design
 top_level=dsp_slice
 
 # The name of the folder in which post-synthesis files and synthesis reports are to be stored
-synth_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_synth
+synth_folder=~/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_synth
 
 # Do you want to be informed of warnings during synthesis?
 show_warnings=True
@@ -57,10 +57,11 @@ generate_activity_file=False
 
 #link_libraries=/usr/local/packages/cadence_2007/FreePDK45/osu_soc/lib/files/gscl45nm.db dw_foundation.sldb
 #link_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db dw_foundation.sldb
-link_libraries="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db dw_foundation.sldb"
+# Using the libraries from 65nm pdk
+link_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.db dw_foundation.sldb"
 
 #target_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db
-target_libraries=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db
+target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2tc.db"
 
 ##############################################
 ########## Place and Route Settings ##########
@@ -69,60 +70,63 @@ target_libraries=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vl
 # Libraries required in EDI:
 
 #this can be a list of numbers
-metal_layers=4
+metal_layers=6
 
 #names of metal layers starting from the bottom-most layer on the left. use a python list format. 
-metal_layer_names=["ME1", "ME2", "ME3", "ME4"]
+metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6"]
 
 #names of metal layers to use for each side of the power ring
 #order: top, bottom, left, right
-power_ring_metal_layer_names=["ME1", "ME1", "ME2", "ME2"]
+power_ring_metal_layer_names=["M1", "M1", "M2", "M2"]
 
 #name of the file to use for layer mapping. used for stream out.
 #set it to None if you want the tool to create a generic map file
 map_file=None
 
+#SM: The .lib files in question are in the Front_End tsmc dir
 #mention the wireload model to be used. this is present in .lib files.
 #if the library doesn't have wireload models, specify None.
 #multiple values can be specified. just add more rows like:
 #wire_selection=WireAreaLowkCon
 #wire_selection=WireAreaLowkAgr
 #wire_selection=WireAreaForZero
-wire_selection=DEFAULT
+wire_selection=WireAreaLowkAgr
 
 #specify names of ground and power pins and nets in the library
-gnd_net=gnd!
-gnd_pin=gnd!
-pwr_net=vdd!
-pwr_pin=vdd!
+gnd_net=VSS!
+gnd_pin=VSS!
+pwr_net=VDD!
+pwr_pin=VDD!
 tilehi_tielo_cells_between_power_gnd=False
 
+
 #specify footprint names for inverters, buffers, delays.
 #this is optional. you can get these values from the lib file.
 #you can also specify None, if you can't find them in the lib file.
-inv_footprint=INVX
-buf_footprint=BUFX
-delay_footprint=INVX
+#SM: not sure if these are the correct standard cells to be using, as there are many options (need to figure out what DX refers to)
+inv_footprint=INVD0
+buf_footprint=BUFFD0
+delay_footprint=INVD0
 
 #list of filler cell names. use a python list format.
 #the names can be obtained from .lib files.
-filler_cell_names=["FILL1", "FILL2", "FILL3", "FILL4"]
+filler_cell_names=["GFILL", "GFILL10", "GFILL2", "GFILL3", "GFILL4"]
 
 #name of the core site in the floorplan. can be obtained from lef files.
-core_site_name=Core
+core_site_name=core
 
 #specify the utilization of the core site. you can specify multiple ones on different lines.
-core_utilization=0.70
+core_utilization=0.90
 
 #specify LEF files in the library. remember to specify the tech/header file first and then the file that has macros/cells.
-lef_files="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/lef/ceid_vlsiLab_umc65ll_header.lef /home/projects/ljohn/aarora1/ceid/ceid_umc65ll/lef/ceid_vlsiLab_umc65ll_allStdCells.lef"
+lef_files="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Back_End/lef/tcbn65gplus_200a/lef/tcbn65gplus_6lmT1.lef"
 
 #list names (full paths) of the .lib files for various corners
-best_case_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+best_case_libs=/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplusbc.lib
 
-standard_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+standard_libs=/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.lib
 
-worst_case_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+worst_case_libs=/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.lib
 
 # EDI (Cadence Encounter) settings:
 power_ring_width=3
@@ -131,7 +135,7 @@ height_to_width_ratio=4.0
 space_around_core=10
 
 # The folder in which place and route reports and post-routing netlists and spef files will be stored
-pr_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pnr
+pr_folder=~/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pnr
 
 
 ##############################################
@@ -142,11 +146,11 @@ pr_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp
 #mode_signal=mode_1
 
 #the directory containing the primetime library and the name of the library file
-primetime_lib_path=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys
-primetime_lib_name=ceid_vlsiLab_umc65ll_stdCells.db
+primetime_lib_path="/CMC/tools/synopsys/syn_vN-2017.09/libraries/syn /CMC/tools/synopsys/syn_vN-2017.09/dw/syn_ver /CMC/tools/synopsys/syn_vN-2017.09/dw/sim_ver /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
+primetime_lib_name=tcbn65gplustc.db
 
 # The name of the folder in which primetime results/reports are to be stored
-primetime_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pt
+primetime_folder=~/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pt
 
 # COFFE parameters:
 name=hard_block
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/accumulate.v b/input_files/strtx_III_dsp/dsp_block_hdl/accumulate.v
similarity index 100%
rename from input_files/strtx_III_dsp_sadegh/dsp_block_hdl/accumulate.v
rename to input_files/strtx_III_dsp/dsp_block_hdl/accumulate.v
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/dsp.v b/input_files/strtx_III_dsp/dsp_block_hdl/dsp.v
similarity index 100%
rename from input_files/strtx_III_dsp_sadegh/dsp_block_hdl/dsp.v
rename to input_files/strtx_III_dsp/dsp_block_hdl/dsp.v
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/half_dsp.v b/input_files/strtx_III_dsp/dsp_block_hdl/half_dsp.v
similarity index 100%
rename from input_files/strtx_III_dsp_sadegh/dsp_block_hdl/half_dsp.v
rename to input_files/strtx_III_dsp/dsp_block_hdl/half_dsp.v
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_block_hdl/twomadder.v b/input_files/strtx_III_dsp/dsp_block_hdl/twomadder.v
similarity index 100%
rename from input_files/strtx_III_dsp_sadegh/dsp_block_hdl/twomadder.v
rename to input_files/strtx_III_dsp/dsp_block_hdl/twomadder.v
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_coffe_params.txt b/input_files/strtx_III_dsp/dsp_coffe_params.txt
similarity index 92%
rename from input_files/strtx_III_dsp_sadegh/dsp_coffe_params.txt
rename to input_files/strtx_III_dsp/dsp_coffe_params.txt
index 13f3c86..f88246b 100755
--- a/input_files/strtx_III_dsp_sadegh/dsp_coffe_params.txt
+++ b/input_files/strtx_III_dsp/dsp_coffe_params.txt
@@ -14,14 +14,14 @@
 #######################################
 
 #Abs path to COFFE repo
-coffe_repo_path=/fs1/eecg/vaughn/morestep/COFFE
+#coffe_repo_path=/fs1/eecg/vaughn/morestep/COFFE
 
 #The directory in which all outputs are generated, makes it easier to make sense of data
-coffe_design_name=strtx_III_dsp_sadegh
+#coffe_design_name=strtx_III_dsp
 
 #The directory in which output files will be stored. 
 #If not specified, the directory containing this file is used as output dir.
-arch_out_folder=/fs1/eecg/vaughn/morestep/COFFE/output_files/strtx_III_dsp_sadegh/arch_out_dir
+arch_out_folder=~/COFFE/output_files/strtx_III_dsp/arch_out_dir
 
 #######################################
 ##### Architecture Parameters
@@ -201,4 +201,4 @@ metal=0.227273,0.000000
 
 
 # if hybrid blocks are enabled, list configurations here
-hb_files = input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt
+hb_files = input_files/strtx_III_dsp/dsp_hb_settings.txt
diff --git a/input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt b/input_files/strtx_III_dsp/dsp_hb_settings.txt
similarity index 91%
rename from input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt
rename to input_files/strtx_III_dsp/dsp_hb_settings.txt
index 99c5b55..6a313c5 100755
--- a/input_files/strtx_III_dsp_sadegh/dsp_hb_settings.txt
+++ b/input_files/strtx_III_dsp/dsp_hb_settings.txt
@@ -5,7 +5,7 @@
 #############################################
 
 # The folder in which all the design files are located:
-design_folder=/fs1/eecg/vaughn/morestep/COFFE/input_files/strtx_III_dsp_sadegh/dsp_block_hdl
+design_folder=~/COFFE/input_files/strtx_III_dsp/dsp_block_hdl
 
 # The design language. Should be either 'verilog', 'vhdl' or 'sverilog'
 design_language=verilog
@@ -35,7 +35,7 @@ clock_period=2.0
 top_level=dsp
 
 # The name of the folder in which post-synthesis files and synthesis reports are to be stored
-synth_folder=~/COFFE/output_files/strtx_III_dsp_sadegh/synth
+synth_folder=~/COFFE/output_files/strtx_III_dsp/synth
 
 # Do you want to be informed of warnings during synthesis?
 
@@ -83,7 +83,7 @@ power_ring_metal_layer_names=["M1", "M1", "M2", "M2"]
 #name of the file to use for layer mapping. used for stream out.
 #set it to None if you want the tool to create a generic map file
 map_file=streamOut.map
-wire_selection=WireAreaLowkCon
+#wire_selection=WireAreaLowkCon
 wire_selection=WireAreaLowkAgr
 #wire_selection=WireAreaForZero
 #specify names of ground and power pins and nets in the library
@@ -97,7 +97,6 @@ tilehi_tielo_cells_between_power_gnd=True
 #specify footprint names for inverters, buffers, delays.
 #this is optional. you can get these values from the lib file.
 #you can also specify None, if you can't find them in the lib file.
-#SM: not sure if these are the correct standard cells to be using, as there are many options (need to figure out what DX refers to)
 inv_footprint=INVD0
 buf_footprint=BUFFD1
 delay_footprint=DEL0
@@ -134,7 +133,7 @@ space_around_core=5
 
 
 # The folder in which place and route reports and post-routing netlists and spef files will be stored
-pr_folder=~/COFFE/output_files/strtx_III_dsp_sadegh/pr
+pr_folder=~/COFFE/output_files/strtx_III_dsp/pr
 
 
 ##############################################
@@ -146,7 +145,7 @@ mode_signal=mode_1
 
 primetime_lib_path=". /CMC/tools/synopsys/syn_vN-2017.09/libraries/syn /CMC/tools/synopsys/syn_vN-2017.09/dw/syn_ver /CMC/tools/synopsys/syn_vN-2017.09/dw/sim_ver /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
 
-primetime_folder=~/COFFE/output_files/strtx_III_dsp_sadegh/pt
+primetime_folder=~/COFFE/output_files/strtx_III_dsp/pt
 
 # COFFE parameters:
 name=hard_block

From 7eba07f103599c5df0fcd2327f9b04824fda1aea Mon Sep 17 00:00:00 2001
From: Stephen More <stephen.w.more@gmail.com>
Date: Mon, 17 Oct 2022 10:44:04 -0400
Subject: [PATCH 3/7] added commented parameters using ceid 65nm libs to
 dsp_slice

---
 .../simple_dsp_slice_65nm/dsp_slice.txt       | 80 ++++++++++++++++---
 1 file changed, 69 insertions(+), 11 deletions(-)

diff --git a/input_files/simple_dsp_slice_65nm/dsp_slice.txt b/input_files/simple_dsp_slice_65nm/dsp_slice.txt
index cb67c87..d61b971 100644
--- a/input_files/simple_dsp_slice_65nm/dsp_slice.txt
+++ b/input_files/simple_dsp_slice_65nm/dsp_slice.txt
@@ -26,7 +26,7 @@ area_cost_exp=1.0
 clock_pin_name=clk
 
 # Desired clock period in ns
-clock_period=1.82
+clock_period=3.0
 
 # Name of the top-level entity in the design
 top_level=dsp_slice
@@ -54,13 +54,21 @@ generate_activity_file=False
 
 # Location of the library files.
 # if you have more than one library, please provide them similiar to the example below.
-
 #link_libraries=/usr/local/packages/cadence_2007/FreePDK45/osu_soc/lib/files/gscl45nm.db dw_foundation.sldb
 #link_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db dw_foundation.sldb
-# Using the libraries from 65nm pdk
+
+# uncomment below for UT austin
+# link_libraries="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db dw_foundation.sldb"
+
+# uncomment below for University of Toronto
 link_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.db dw_foundation.sldb"
 
 #target_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db
+
+# uncomment below for UT austin
+#target_libraries=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db
+
+# uncomment below for University of Toronto
 target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2tc.db"
 
 ##############################################
@@ -70,13 +78,23 @@ target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_En
 # Libraries required in EDI:
 
 #this can be a list of numbers
-metal_layers=6
+metal_layers=4
 
 #names of metal layers starting from the bottom-most layer on the left. use a python list format. 
+
+# uncomment below for UT austin
+#metal_layer_names=["ME1", "ME2", "ME3", "ME4"]
+
+# uncomment below for University of Toronto
 metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6"]
 
 #names of metal layers to use for each side of the power ring
 #order: top, bottom, left, right
+
+# uncomment below for UT austin
+# power_ring_metal_layer_names=["ME1", "ME1", "ME2", "ME2"]
+
+# uncomment below for University of Toronto
 power_ring_metal_layer_names=["M1", "M1", "M2", "M2"]
 
 #name of the file to use for layer mapping. used for stream out.
@@ -93,35 +111,69 @@ map_file=None
 wire_selection=WireAreaLowkAgr
 
 #specify names of ground and power pins and nets in the library
-gnd_net=VSS!
-gnd_pin=VSS!
-pwr_net=VDD!
-pwr_pin=VDD!
+
+# uncomment below for University of Toronto
+gnd_net=VSS
+gnd_pin=VSS
+pwr_net=VDD
+pwr_pin=VDD
+
+# uncomment below for UT austin
+#gnd_net=gnd!
+#gnd_pin=gnd!
+#pwr_net=vdd!
+#pwr_pin=vdd!
+
 tilehi_tielo_cells_between_power_gnd=False
 
 
 #specify footprint names for inverters, buffers, delays.
 #this is optional. you can get these values from the lib file.
 #you can also specify None, if you can't find them in the lib file.
-#SM: not sure if these are the correct standard cells to be using, as there are many options (need to figure out what DX refers to)
+# uncomment below for University of Toronto
 inv_footprint=INVD0
 buf_footprint=BUFFD0
 delay_footprint=INVD0
 
+# uncomment below for UT austin
+#inv_footprint=INVX
+#buf_footprint=BUFX
+#delay_footprint=INVX
+
 #list of filler cell names. use a python list format.
 #the names can be obtained from .lib files.
+
+# uncomment below for University of Toronto
 filler_cell_names=["GFILL", "GFILL10", "GFILL2", "GFILL3", "GFILL4"]
 
+# uncomment below for UT austin
+#filler_cell_names=["FILL1", "FILL2", "FILL3", "FILL4"]
+
 #name of the core site in the floorplan. can be obtained from lef files.
+
+# uncomment below for University of Toronto
 core_site_name=core
 
+# uncomment below for UT austin
+#core_site_name=Core
+
 #specify the utilization of the core site. you can specify multiple ones on different lines.
 core_utilization=0.90
-
 #specify LEF files in the library. remember to specify the tech/header file first and then the file that has macros/cells.
+# uncomment below for UT austin
+#lef_files="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/lef/ceid_vlsiLab_umc65ll_header.lef /home/projects/ljohn/aarora1/ceid/ceid_umc65ll/lef/ceid_vlsiLab_umc65ll_allStdCells.lef"
+
+# uncomment below for University of Toronto
 lef_files="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Back_End/lef/tcbn65gplus_200a/lef/tcbn65gplus_6lmT1.lef"
 
 #list names (full paths) of the .lib files for various corners
+
+# uncomment below for UT austin
+#best_case_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+#standard_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+#worst_case_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+
+# uncomment below for University of Toronto
 best_case_libs=/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplusbc.lib
 
 standard_libs=/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.lib
@@ -144,11 +196,17 @@ pr_folder=~/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pnr
 
 #mode_signal=mode_0
 #mode_signal=mode_1
-
 #the directory containing the primetime library and the name of the library file
+# uncomment below for UT austin
+#primetime_lib_path=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys
+#primetime_lib_name=ceid_vlsiLab_umc65ll_stdCells.db
+
+# uncomment below for University of Toronto
 primetime_lib_path="/CMC/tools/synopsys/syn_vN-2017.09/libraries/syn /CMC/tools/synopsys/syn_vN-2017.09/dw/syn_ver /CMC/tools/synopsys/syn_vN-2017.09/dw/sim_ver /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
 primetime_lib_name=tcbn65gplustc.db
 
+
+#the directory containing the primetime library and the name of the library file
 # The name of the folder in which primetime results/reports are to be stored
 primetime_folder=~/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pt
 

From 29623d3997c8e368782a4008b72ff6d5ff944151 Mon Sep 17 00:00:00 2001
From: Stephen More <stephen.w.more@gmail.com>
Date: Mon, 17 Oct 2022 10:49:28 -0400
Subject: [PATCH 4/7] added old version of dsp_slice under dsp_slice_ceid.txt

---
 .../simple_dsp_slice_65nm/dsp_slice_ceid.txt  | 327 ++++++++++++++++++
 1 file changed, 327 insertions(+)
 create mode 100644 input_files/simple_dsp_slice_65nm/dsp_slice_ceid.txt

diff --git a/input_files/simple_dsp_slice_65nm/dsp_slice_ceid.txt b/input_files/simple_dsp_slice_65nm/dsp_slice_ceid.txt
new file mode 100644
index 0000000..88dc564
--- /dev/null
+++ b/input_files/simple_dsp_slice_65nm/dsp_slice_ceid.txt
@@ -0,0 +1,327 @@
+#This is a sample settings file for the hard block flow.
+#The hard block flow is detailed in the paper: 
+#"COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures"
+#https://dl.acm.org/doi/10.1145/3301298
+#Most of the variables below have comments with them. The paper provides more context and details too.
+
+#############################################
+########## General Design Settings ##########
+#############################################
+# The folder in which all the design files are located:
+design_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/input_files/simple_dsp_slice_65nm/dsp_slice_hdl
+
+# The design language. Should be either 'verilog', 'vhdl' or 'sverilog'
+design_language=verilog
+
+# The exponents of delay and area in the cost function.
+# cost = (delay ^ delay_cost_exp) * (area ^ area_cost_exp)
+delay_cost_exp=1.0
+area_cost_exp=1.0
+
+########################################
+########## Synthesis Settings ##########
+########################################
+
+# Name of the clock pin in the design
+clock_pin_name=clk
+
+# Desired clock period in ns
+clock_period=3.0
+
+# Name of the top-level entity in the design
+top_level=dsp_slice
+
+# The name of the folder in which post-synthesis files and synthesis reports are to be stored
+synth_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_synth
+
+# Do you want to be informed of warnings during synthesis?
+show_warnings=True
+
+# Should the flow terminate after synthesis?
+# A value of "False" will continue into placement and routing
+synthesis_only=False
+
+# Do you want to provide a saif file for power analysis?
+# In case of setting this to "True" a saif.saif file should be provided
+read_saif_file=False
+
+# If you don't want to provide a saif file, specify the switching activity parameters below:
+static_probability=0.5
+toggle_rate=25
+
+# Should COFFE generate an activity file for the design (using modelsim)
+generate_activity_file=False
+
+# Location of the library files.
+# if you have more than one library, please provide them similiar to the example below.
+
+#link_libraries=/usr/local/packages/cadence_2007/FreePDK45/osu_soc/lib/files/gscl45nm.db dw_foundation.sldb
+#link_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db dw_foundation.sldb
+link_libraries="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db dw_foundation.sldb"
+
+#target_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db
+target_libraries=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db
+
+##############################################
+########## Place and Route Settings ##########
+##############################################
+
+# Libraries required in EDI:
+
+#this can be a list of numbers
+metal_layers=4
+
+#names of metal layers starting from the bottom-most layer on the left. use a python list format. 
+metal_layer_names=["ME1", "ME2", "ME3", "ME4"]
+
+#names of metal layers to use for each side of the power ring
+#order: top, bottom, left, right
+power_ring_metal_layer_names=["ME1", "ME1", "ME2", "ME2"]
+
+#name of the file to use for layer mapping. used for stream out.
+#set it to None if you want the tool to create a generic map file
+map_file=None
+
+#mention the wireload model to be used. this is present in .lib files.
+#if the library doesn't have wireload models, specify None.
+#multiple values can be specified. just add more rows like:
+#wire_selection=WireAreaLowkCon
+#wire_selection=WireAreaLowkAgr
+#wire_selection=WireAreaForZero
+wire_selection=DEFAULT
+
+#specify names of ground and power pins and nets in the library
+gnd_net=gnd!
+gnd_pin=gnd!
+pwr_net=vdd!
+pwr_pin=vdd!
+tilehi_tielo_cells_between_power_gnd=False
+
+#specify footprint names for inverters, buffers, delays.
+#this is optional. you can get these values from the lib file.
+#you can also specify None, if you can't find them in the lib file.
+inv_footprint=INVX
+buf_footprint=BUFX
+delay_footprint=INVX
+
+#list of filler cell names. use a python list format.
+#the names can be obtained from .lib files.
+filler_cell_names=["FILL1", "FILL2", "FILL3", "FILL4"]
+
+#name of the core site in the floorplan. can be obtained from lef files.
+core_site_name=Core
+
+#specify the utilization of the core site. you can specify multiple ones on different lines.
+core_utilization=0.70
+
+#specify LEF files in the library. remember to specify the tech/header file first and then the file that has macros/cells.
+lef_files="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/lef/ceid_vlsiLab_umc65ll_header.lef /home/projects/ljohn/aarora1/ceid/ceid_umc65ll/lef/ceid_vlsiLab_umc65ll_allStdCells.lef"
+
+#list names (full paths) of the .lib files for various corners
+best_case_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+
+standard_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+
+worst_case_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+
+# EDI (Cadence Encounter) settings:
+power_ring_width=3
+power_ring_spacing=1
+height_to_width_ratio=4.0
+space_around_core=10
+
+# The folder in which place and route reports and post-routing netlists and spef files will be stored
+pr_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pnr
+
+
+##############################################
+########## Prime Time Settings ###############
+##############################################
+
+#mode_signal=mode_0
+#mode_signal=mode_1
+
+#the directory containing the primetime library and the name of the library file
+primetime_lib_path=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys
+primetime_lib_name=ceid_vlsiLab_umc65ll_stdCells.db
+
+# The name of the folder in which primetime results/reports are to be stored
+primetime_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pt
+
+# COFFE parameters:
+name=hard_block
+num_gen_inputs=22
+crossbar_population=0.5
+height=4
+num_gen_outputs=9
+num_dedicated_outputs=0
+soft_logic_per_block=0.1
+area_scale_factor=0.14
+freq_scale_factor=2.32
+power_scale_factor=0.29
+input_usage=0.8
+num_crossbars=1
+crossbar_modelling=optimistic#This is a sample settings file for the hard block flow.
+#The hard block flow is detailed in the paper: 
+#"COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures"
+#https://dl.acm.org/doi/10.1145/3301298
+#Most of the variables below have comments with them. The paper provides more context and details too.
+
+#############################################
+########## General Design Settings ##########
+#############################################
+# The folder in which all the design files are located:
+design_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/input_files/simple_dsp_slice_65nm/dsp_slice_hdl
+
+# The design language. Should be either 'verilog', 'vhdl' or 'sverilog'
+design_language=verilog
+
+# The exponents of delay and area in the cost function.
+# cost = (delay ^ delay_cost_exp) * (area ^ area_cost_exp)
+delay_cost_exp=1.0
+area_cost_exp=1.0
+
+########################################
+########## Synthesis Settings ##########
+########################################
+
+# Name of the clock pin in the design
+clock_pin_name=clk
+
+# Desired clock period in ns
+clock_period=3.0
+
+# Name of the top-level entity in the design
+top_level=dsp_slice
+
+# The name of the folder in which post-synthesis files and synthesis reports are to be stored
+synth_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_synth
+
+# Do you want to be informed of warnings during synthesis?
+show_warnings=True
+
+# Should the flow terminate after synthesis?
+# A value of "False" will continue into placement and routing
+synthesis_only=False
+
+# Do you want to provide a saif file for power analysis?
+# In case of setting this to "True" a saif.saif file should be provided
+read_saif_file=False
+
+# If you don't want to provide a saif file, specify the switching activity parameters below:
+static_probability=0.5
+toggle_rate=25
+
+# Should COFFE generate an activity file for the design (using modelsim)
+generate_activity_file=False
+
+# Location of the library files.
+# if you have more than one library, please provide them similiar to the example below.
+
+#link_libraries=/usr/local/packages/cadence_2007/FreePDK45/osu_soc/lib/files/gscl45nm.db dw_foundation.sldb
+#link_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db dw_foundation.sldb
+link_libraries="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db dw_foundation.sldb"
+
+#target_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db
+target_libraries=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db
+
+##############################################
+########## Place and Route Settings ##########
+##############################################
+
+# Libraries required in EDI:
+
+#this can be a list of numbers
+metal_layers=4
+
+#names of metal layers starting from the bottom-most layer on the left. use a python list format. 
+metal_layer_names=["ME1", "ME2", "ME3", "ME4"]
+
+#names of metal layers to use for each side of the power ring
+#order: top, bottom, left, right
+power_ring_metal_layer_names=["ME1", "ME1", "ME2", "ME2"]
+
+#name of the file to use for layer mapping. used for stream out.
+#set it to None if you want the tool to create a generic map file
+map_file=None
+
+#mention the wireload model to be used. this is present in .lib files.
+#if the library doesn't have wireload models, specify None.
+#multiple values can be specified. just add more rows like:
+#wire_selection=WireAreaLowkCon
+#wire_selection=WireAreaLowkAgr
+#wire_selection=WireAreaForZero
+wire_selection=DEFAULT
+
+#specify names of ground and power pins and nets in the library
+gnd_net=gnd!
+gnd_pin=gnd!
+pwr_net=vdd!
+pwr_pin=vdd!
+tilehi_tielo_cells_between_power_gnd=False
+
+#specify footprint names for inverters, buffers, delays.
+#this is optional. you can get these values from the lib file.
+#you can also specify None, if you can't find them in the lib file.
+inv_footprint=INVX
+buf_footprint=BUFX
+delay_footprint=INVX
+
+#list of filler cell names. use a python list format.
+#the names can be obtained from .lib files.
+filler_cell_names=["FILL1", "FILL2", "FILL3", "FILL4"]
+
+#name of the core site in the floorplan. can be obtained from lef files.
+core_site_name=Core
+
+#specify the utilization of the core site. you can specify multiple ones on different lines.
+core_utilization=0.70
+
+#specify LEF files in the library. remember to specify the tech/header file first and then the file that has macros/cells.
+lef_files="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/lef/ceid_vlsiLab_umc65ll_header.lef /home/projects/ljohn/aarora1/ceid/ceid_umc65ll/lef/ceid_vlsiLab_umc65ll_allStdCells.lef"
+
+#list names (full paths) of the .lib files for various corners
+best_case_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+
+standard_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+
+worst_case_libs=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.lib
+
+# EDI (Cadence Encounter) settings:
+power_ring_width=3
+power_ring_spacing=1
+height_to_width_ratio=4.0
+space_around_core=10
+
+# The folder in which place and route reports and post-routing netlists and spef files will be stored
+pr_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pnr
+
+
+##############################################
+########## Prime Time Settings ###############
+##############################################
+
+#mode_signal=mode_0
+#mode_signal=mode_1
+
+#the directory containing the primetime library and the name of the library file
+primetime_lib_path=/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys
+primetime_lib_name=ceid_vlsiLab_umc65ll_stdCells.db
+
+# The name of the folder in which primetime results/reports are to be stored
+primetime_folder=/home/projects/ljohn/aarora1/coffe2_aman/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pt
+
+# COFFE parameters:
+name=hard_block
+num_gen_inputs=22
+crossbar_population=0.5
+height=4
+num_gen_outputs=9
+num_dedicated_outputs=0
+soft_logic_per_block=0.1
+area_scale_factor=0.14
+freq_scale_factor=2.32
+power_scale_factor=0.29
+input_usage=0.8
+num_crossbars=1
+crossbar_modelling=optimistic
\ No newline at end of file

From 0b8b6da5467f2068bf1cdc3cfe4c6e46a73cdd7f Mon Sep 17 00:00:00 2001
From: Stephen More <stephen.w.more@gmail.com>
Date: Mon, 17 Oct 2022 16:24:54 -0400
Subject: [PATCH 5/7] more refactoring, added preprocessing for parameters
 taken in from config files but which need to be changed to different formats
 when written out to tcl scripts, removed the primetime_lib_path parameter as
 its going to be the same as the libs used in synthesis, added the command
 line arg to only run hard block synthesis, added option to specify a
 process_specific_params file which makes it easier for users to distinguish
 which params need to be changed when changing process libs

---
 User Manual.md                                |   4 +
 coffe.py                                      | 195 +++++++-------
 coffe/fpga.py                                 |   2 -
 coffe/hardblock_functions.py                  | 252 +++++++++++-------
 coffe/utils.py                                | 194 ++++++++++----
 .../simple_dsp_slice_65nm/dsp_slice.txt       |  14 +-
 input_files/strtx_III_dsp/dsp_hb_settings.txt |  51 ++--
 .../strtx_III_dsp/process_specific_params.txt |  62 +++++
 unit_test.sh                                  |  15 ++
 9 files changed, 513 insertions(+), 276 deletions(-)
 create mode 100644 input_files/strtx_III_dsp/process_specific_params.txt
 create mode 100644 unit_test.sh

diff --git a/User Manual.md b/User Manual.md
index 9b8022b..de1b76e 100644
--- a/User Manual.md	
+++ b/User Manual.md	
@@ -80,6 +80,10 @@ $(which encounter)
   To plot the power, area, and delay results against target frequency run the following command (this requires python3 and matplotlib to be installed):
   - $(python3 plot_coffe_results.py -c report_csv_out/condensed_report.csv)
 
+4. A script that runs all of the above commands can be run from COFFE repo:
+  - $(chmod +x ./unit_test.sh)
+  - $(./unit_test.sh)
+
 
 
 
diff --git a/coffe.py b/coffe.py
index ebbcd95..db0d19b 100644
--- a/coffe.py
+++ b/coffe.py
@@ -46,6 +46,8 @@
 import datetime
 import math
 
+
+
 print "\nCOFFE 2.0\n"
 print "Man is a tool-using animal."
 print "Without tools he is nothing, with tools he is all."
@@ -65,106 +67,113 @@
 parser.add_argument('-a', '--area_opt_weight', type=int, default=1, help="area optimization weight")
 parser.add_argument('-d', '--delay_opt_weight', type=int, default=1, help="delay optimization weight")
 parser.add_argument('-i', '--max_iterations', type=int, default=6, help="max FPGA sizing iterations")
+parser.add_argument('-ho',"--hardblock_only",help="run only a single hardblock through the asic flow", action='store_true',default=False)
 
 # quick mode is disabled by default. Try passing -q 0.03 for 3% minimum improvement
 parser.add_argument('-q', '--quick_mode', type=float, default=-1.0, help="minimum cost function improvement for resizing")
 
 args = parser.parse_args()
 
-is_size_transistors = not args.no_sizing
-
 # Load the input architecture description file
 arch_params_dict = utils.load_arch_params(args.arch_description)
-
-# Make the top-level spice folder if it doesn't already exist
-# if it's already there delete its content
 arch_folder = utils.create_output_dir(args.arch_description, arch_params_dict['arch_out_folder'])
-
-# Print the options to both terminal and report file
-report_file_path = os.path.join(arch_folder, "report.txt") 
-utils.print_run_options(args, report_file_path)
-
-# Print architecture and process details to terminal and report file
-utils.print_architecture_params(arch_params_dict, report_file_path)
-
-# Default_dir is the dir you ran COFFE from. COFFE will be switching directories 
-# while running HSPICE, this variable is so that we can get back to our starting point
-default_dir = os.getcwd()
-
-# Create an HSPICE interface
-spice_interface = spice.SpiceInterface()
-
-# Record start time
-total_start_time = time.time()
-
-# Create an FPGA instance
-fpga_inst = fpga.FPGA(arch_params_dict, args, spice_interface)
-                     
-###############################################################
-## GENERATE FILES
-###############################################################
-
-# Change to the architecture directory
-os.chdir(arch_folder)  
-
-# Generate FPGA and associated SPICE files
-fpga_inst.generate(is_size_transistors) 
-
-# Go back to the base directory
-os.chdir(default_dir)
-
-# Extract initial transistor sizes from file and overwrite the 
-# default initial sizes if this option was used.
-if args.initial_sizes != "default" :
-  utils.use_initial_tran_size(args.initial_sizes, fpga_inst, tran_sizing, arch_params_dict['use_tgate'])
-
-# Print FPGA implementation details
-report_file = open(report_file_path, 'a')
-fpga_inst.print_details(report_file)  
-report_file.close()
-
-# Go to architecture directory
-os.chdir(arch_folder)
-
-###############################################################
-## TRANSISTOR SIZING
-###############################################################
-
-sys.stdout.flush()
-
-# Size FPGA transistors
-if is_size_transistors:
-    tran_sizing.size_fpga_transistors(fpga_inst, args, spice_interface)                                    
+if(args.hardblock_only):
+  # Change to the architecture directory
+  for hardblock_fname in arch_params_dict["hb_files"]:
+    hard_block = fpga._hard_block(hardblock_fname,False)
+    os.chdir(arch_folder)
+    hard_block.generate_top()
 else:
-  # in case of disabling floorplanning there is no need to 
-  # update delays before updating area. Tried both ways and 
-  # they give exactly the same results
-  #fpga_inst.update_delays(spice_interface)
-
-  # same thing here no need to update area before calculating 
-  # the lb_height value. Also tested and gave same results
-  #fpga_inst.update_area()
-  fpga_inst.lb_height = math.sqrt(fpga_inst.area_dict["tile"])
-  fpga_inst.update_area()
-  fpga_inst.compute_distance()
-  fpga_inst.update_wires()
-  fpga_inst.update_wire_rc()
-
-  # commented this part to avoid doing floorplannig for
-  # a non-sizing run
-  #fpga_inst.determine_height()
-
-  fpga_inst.update_delays(spice_interface)
-
-# Obtain Memory core power
-if arch_params_dict['enable_bram_module'] == 1:
-  fpga_inst.update_power(spice_interface)
-
-# Go back to the base directory
-os.chdir(default_dir)
-
-# Print out final COFFE report to file
-utils.print_summary(arch_folder, fpga_inst, total_start_time)
-
-# Print vpr architecure file
-coffe.vpr.print_vpr_file(fpga_inst, arch_folder, arch_params_dict['enable_bram_module'])
+  is_size_transistors = not args.no_sizing
+  # Make the top-level spice folder if it doesn't already exist
+  # if it's already there delete its content
+  # arch_folder = utils.create_output_dir(args.arch_description, arch_params_dict['arch_out_folder'])
+
+  # Print the options to both terminal and report file
+  report_file_path = os.path.join(arch_folder, "report.txt") 
+  utils.print_run_options(args, report_file_path)
+
+  # Print architecture and process details to terminal and report file
+  utils.print_architecture_params(arch_params_dict, report_file_path)
+
+  # Default_dir is the dir you ran COFFE from. COFFE will be switching directories 
+  # while running HSPICE, this variable is so that we can get back to our starting point
+  default_dir = os.getcwd()
+
+  # Create an HSPICE interface
+  spice_interface = spice.SpiceInterface()
+
+  # Record start time
+  total_start_time = time.time()
+
+  # Create an FPGA instance
+  fpga_inst = fpga.FPGA(arch_params_dict, args, spice_interface)
+                      
+  ###############################################################
+  ## GENERATE FILES
+  ###############################################################
+
+  # Change to the architecture directory
+  os.chdir(arch_folder)  
+
+  # Generate FPGA and associated SPICE files
+  fpga_inst.generate(is_size_transistors) 
+
+  # Go back to the base directory
+  os.chdir(default_dir)
+
+  # Extract initial transistor sizes from file and overwrite the 
+  # default initial sizes if this option was used.
+  if args.initial_sizes != "default" :
+    utils.use_initial_tran_size(args.initial_sizes, fpga_inst, tran_sizing, arch_params_dict['use_tgate'])
+
+  # Print FPGA implementation details
+  report_file = open(report_file_path, 'a')
+  fpga_inst.print_details(report_file)  
+  report_file.close()
+
+  # Go to architecture directory
+  os.chdir(arch_folder)
+
+  ###############################################################
+  ## TRANSISTOR SIZING
+  ###############################################################
+
+  sys.stdout.flush()
+
+  # Size FPGA transistors
+  if is_size_transistors:
+      tran_sizing.size_fpga_transistors(fpga_inst, args, spice_interface)                                    
+  else:
+    # in case of disabling floorplanning there is no need to 
+    # update delays before updating area. Tried both ways and 
+    # they give exactly the same results
+    #fpga_inst.update_delays(spice_interface)
+
+    # same thing here no need to update area before calculating 
+    # the lb_height value. Also tested and gave same results
+    #fpga_inst.update_area()
+    fpga_inst.lb_height = math.sqrt(fpga_inst.area_dict["tile"])
+    fpga_inst.update_area()
+    fpga_inst.compute_distance()
+    fpga_inst.update_wires()
+    fpga_inst.update_wire_rc()
+
+    # commented this part to avoid doing floorplannig for
+    # a non-sizing run
+    #fpga_inst.determine_height()
+
+    fpga_inst.update_delays(spice_interface)
+
+  # Obtain Memory core power
+  if arch_params_dict['enable_bram_module'] == 1:
+    fpga_inst.update_power(spice_interface)
+
+  # Go back to the base directory
+  os.chdir(default_dir)
+
+  # Print out final COFFE report to file
+  utils.print_summary(arch_folder, fpga_inst, total_start_time)
+
+  # Print vpr architecure file
+  coffe.vpr.print_vpr_file(fpga_inst, arch_folder, arch_params_dict['enable_bram_module'])
diff --git a/coffe/fpga.py b/coffe/fpga.py
index f105593..5d50259 100644
--- a/coffe/fpga.py
+++ b/coffe/fpga.py
@@ -5177,8 +5177,6 @@ def generate_top(self):
 
         # hard block flow
         self.flow_results = hardblock_functions.hardblock_flow(self.parameters)
-        if(self.parameters["asic_flow_only"] == True):
-            sys.exit()
         #the area returned by the hardblock flow is in um^2. In area_dict, all areas are in nm^2 
         self.area = self.flow_results[0] * self.parameters['area_scale_factor'] * (1e+6) 
 
diff --git a/coffe/hardblock_functions.py b/coffe/hardblock_functions.py
index 56da169..48c76ee 100644
--- a/coffe/hardblock_functions.py
+++ b/coffe/hardblock_functions.py
@@ -10,25 +10,28 @@
 import shutil
 import math
 
-def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_selection):
-  ###########################################
-  # Synthesis
-  ###########################################
+
+def write_synth_tcl(flow_settings,clock_period,wire_selection):
+  """
+  Writes the dc_script.tcl file which will be executed to run synthesis using Synopsys Design Compiler, tested under 2017 version
+  """
   file = open("dc_script.tcl","w")
-  file.write("cd " + os.path.expanduser(flow_settings['synth_folder']) + "\n")
-  file.write("set search_path " + "\"" + " ".join(search_path_dirs) + "\"" + " \n")
-  if len(design_files) == 1:
-    file.write("set my_files " + design_files[0] + "\n")
+  file.write("cd " + flow_settings['synth_folder'] + "\n")
+  file.write("set search_path " + flow_settings["search_path"] + " \n")
+  if len(flow_settings["design_files"]) == 1:
+    file.write("set my_files " + flow_settings["design_files"][0] + "\n")
   else:
     file.write("set my_files [list ")
-    for entity in design_files:
+    for entity in flow_settings["design_files"]:
+      #currently set to ignore filenames of parameters.v/c_functions.v this should be updated in the future as its design specific TODO
       if not (entity == "parameters.v" or entity == "c_functions.v"):
         file.write(entity + " ")
     file.write("] \n")
   file.write("set my_top_level " + flow_settings['top_level'] + "\n")
   file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-  file.write("set link_library " + flow_settings['link_libraries'] + "\n")
-  file.write("set target_library " + flow_settings['target_libraries'] + "\n")
+  #after pre_processing function, the target_library and link_library vars should be set (link_library is all files in cwd and target_library)
+  file.write("set target_library " + flow_settings["target_library"] + "\n")
+  file.write("set link_library " + flow_settings["link_library"] + "\n")
   file.write(r'set power_analysis_mode "averaged"' + "\n")
   file.write("define_design_lib WORK -path ./WORK \n")
   if flow_settings['design_language'] == 'verilog':
@@ -39,7 +42,7 @@ def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_sele
     file.write("analyze -f sverilog $my_files \n")
   file.write("elaborate $my_top_level \n")
   file.write("current_design $my_top_level \n")
-  file.write("check_design >  " + os.path.expanduser(flow_settings['synth_folder']) + "/checkprecompile.rpt\n")
+  file.write("check_design >  " + flow_settings['synth_folder'] + "/checkprecompile.rpt\n")
   file.write("link \n")
   file.write("uniquify \n")
   #If wire_selection is None, then no wireload model is used during synthesis. This does imply results 
@@ -53,26 +56,33 @@ def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_sele
   file.write("set clk_name $my_clock_pin \n")
   file.write("create_clock -period $my_period $clk_name} \n\n")
   file.write("compile_ultra\n")
-  file.write("check_design >  " + os.path.expanduser(flow_settings['synth_folder']) + "/check.rpt\n")
+  file.write("check_design >  " + flow_settings['synth_folder'] + "/check.rpt\n")
   file.write("link \n")
-  file.write("write_file -format ddc -hierarchy -output " + os.path.expanduser(flow_settings['synth_folder']) + "/" +  flow_settings['top_level']  + ".ddc \n")
+  file.write("write_file -format ddc -hierarchy -output " + flow_settings['synth_folder'] + "/" +  flow_settings['top_level']  + ".ddc \n")
   if flow_settings['read_saif_file']:
     file.write("read_saif saif.saif \n")
   else:
     file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " -base_clock $my_clock_pin -type inputs \n")
   file.write("ungroup -all -flatten \n")
-  file.write("report_power > " + os.path.expanduser(flow_settings['synth_folder']) + "/power.rpt\n")
-  file.write("report_area -nosplit -hierarchy > " + os.path.expanduser(flow_settings['synth_folder']) + "/area.rpt\n")
-  file.write("report_resources -nosplit -hierarchy > " + os.path.expanduser(flow_settings['synth_folder']) + "/resources.rpt\n")      
-  file.write("report_timing > " + os.path.expanduser(flow_settings['synth_folder']) + "/timing.rpt\n")
+  file.write("report_power > " + flow_settings['synth_folder'] + "/power.rpt\n")
+  file.write("report_area -nosplit -hierarchy > " + flow_settings['synth_folder'] + "/area.rpt\n")
+  file.write("report_resources -nosplit -hierarchy > " + flow_settings['synth_folder'] + "/resources.rpt\n")      
+  file.write("report_timing > " + flow_settings['synth_folder'] + "/timing.rpt\n")
   file.write("change_names -hier -rule verilog \n") 
-  file.write("write -f verilog -output " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.v\n")
-  file.write("write_sdf " + os.path.expanduser(flow_settings['synth_folder']) + "/synthsized.sdf \n")
-  file.write("write_parasitics -output " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.spef \n")
-  file.write("write_sdc " + os.path.expanduser(flow_settings['synth_folder']) + "/synthesized.sdc \n")
+  file.write("write -f verilog -output " + flow_settings['synth_folder'] + "/synthesized.v\n")
+  file.write("write_sdf " + flow_settings['synth_folder'] + "/synthsized.sdf \n")
+  file.write("write_parasitics -output " + flow_settings['synth_folder'] + "/synthesized.spef \n")
+  file.write("write_sdc " + flow_settings['synth_folder'] + "/synthesized.sdc \n")
   file.write("quit \n")
   file.close()
 
+#search_path_dirs,design_files,
+def run_synth(flow_settings,clock_period,wire_selection):
+  """"
+  runs the synthesis flow for specific clock period and wireload model
+  Prereqs: flow_settings_pre_process() function to properly format params for scripts
+  """
+  write_synth_tcl(flow_settings,clock_period,wire_selection)
   # Run the scrip in design compiler shell
   subprocess.call('dc_shell-t -f dc_script.tcl | tee dc.log', shell=True,executable="/bin/bash") 
   # clean after DC!
@@ -82,7 +92,7 @@ def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_sele
 
   # Make sure it worked properly
   # Open the timing report and make sure the critical path is non-zero:
-  check_file = open(os.path.expanduser(flow_settings['synth_folder']) + "/check.rpt", "r")
+  check_file = open(flow_settings['synth_folder'] + "/check.rpt", "r")
   for line in check_file:
     if "Error" in line:
       print "Your design has errors. Refer to check.rpt in synthesis directory"
@@ -94,9 +104,9 @@ def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_sele
 
   #Copy synthesis results to a unique dir in synth dir
   synth_report_str = "period_" + clock_period + "_" + "wire_mdl_" + wire_selection
-  report_dest_str = os.path.expanduser(flow_settings['synth_folder']) + "/" + synth_report_str + "_reports"
+  report_dest_str = flow_settings['synth_folder'] + "/" + synth_report_str + "_reports"
   mkdir_cmd_str = "mkdir -p " + report_dest_str
-  copy_rep_cmd_str = "cp " + os.path.expanduser(flow_settings['synth_folder']) + "/*.rpt " + report_dest_str
+  copy_rep_cmd_str = "cp " + flow_settings['synth_folder'] + "/*.rpt " + report_dest_str
   copy_logs_cmd_str = "cp " + "dc.log "+ "dc_script.tcl " + report_dest_str
   subprocess.call(mkdir_cmd_str,shell=True)
   subprocess.call(copy_rep_cmd_str,shell=True)
@@ -106,13 +116,13 @@ def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_sele
   #if the user doesn't want to perform place and route, extract the results from DC reports and end
   if flow_settings['synthesis_only']:
     # read total area from the report file:
-    file = open(os.path.expanduser(flow_settings['synth_folder']) + "/area.rpt" ,"r")
+    file = open(flow_settings['synth_folder'] + "/area.rpt" ,"r")
     for line in file:
       if line.startswith('Total cell area:'):
         total_area = re.findall(r'\d+\.{0,1}\d*', line)
     file.close()
     # Read timing parameters
-    file = open(os.path.expanduser(flow_settings['synth_folder']) + "/timing.rpt" ,"r")
+    file = open(flow_settings['synth_folder'] + "/timing.rpt" ,"r")
     for line in file:
       if 'library setup time' in line:
         library_setup_time = re.findall(r'\d+\.{0,1}\d*', line)
@@ -124,7 +134,7 @@ def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_sele
       total_delay =  float(data_arrival_time[0])
     file.close()    
     # Read dynamic power
-    file = open(os.path.expanduser(flow_settings['synth_folder']) + "/power.rpt" ,"r")
+    file = open(flow_settings['synth_folder'] + "/power.rpt" ,"r")
     for line in file:
       if 'Total Dynamic Power' in line:
         total_dynamic_power = re.findall(r'\d+\.\d*', line)
@@ -146,11 +156,10 @@ def run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_sele
     exit()
   return synth_report_str
 
-
-def run_pnr(flow_settings,metal_layer,core_utilization,synth_report_str):
-  ###########################################
-  # Place and Route
-  ###########################################
+def write_pnr_script(flow_settings,metal_layer,core_utilization):
+  """"
+  writes the tcl script for place and route using Cadence Encounter, tested under 2009 version
+  """
   # generate the EDI (encounter) configuration
   file = open("edi.conf", "w")
   file.write("global rda_Input \n")
@@ -277,6 +286,12 @@ def run_pnr(flow_settings,metal_layer,core_utilization,synth_report_str):
     file.write(r'streamOut ' + os.path.expanduser(flow_settings['pr_folder']) + r'/final.gds2' + ' -stripes 1 -units 1000 -mode ALL' + "\n")
   file.write("exit \n")
   file.close()
+def run_pnr(flow_settings,metal_layer,core_utilization,synth_report_str):
+  """
+  runs place and route using cadence encounter
+  Prereqs: flow_settings_pre_process() function to properly format params for scripts
+  """
+  write_pnr_script(flow_settings,metal_layer,core_utilization)
   # Run the scrip in EDI
   subprocess.call('encounter -nowin -init edi.tcl | tee edi.log', shell=True,executable="/bin/bash") 
   # clean after EDI!
@@ -301,6 +316,9 @@ def run_pnr(flow_settings,metal_layer,core_utilization,synth_report_str):
   return pnr_report_str, total_area
 
 def run_sim():
+  """
+  Runs simulation using a user inputted testbench, not tested and unsure of which hard block its modeling USE AT OWN RISK (ie use saif file option in hardblock settings file)
+  """
   # Create a modelsim folder
   #subprocess.call("mkdir -p"+os.path.expanduser("./modelsim_dir")+"\n", shell=True)
   # Create a modelsim .do file:
@@ -324,21 +342,53 @@ def run_sim():
   subprocess.call('wlf2vcd -o test.vcd out.wlf', shell=True)
   subprocess.call('vcd2saif -input test.vcd -o saif.saif', shell=True)
 
-def run_power_timing(flow_settings,mode_enabled,clock_period,pnr_report_str):
-  ###########################################
-  # Primetime
-  ###########################################
-  if not mode_enabled:
-    x = 2**len(flow_settings['mode_signal'])
+def write_pt_power_script(flow_settings,mode_enabled,clock_period,x):
+  """"
+  writes the tcl script for timing analysis using Synopsys Design Compiler, tested under 2017 version
+  """
+  # Create a script to measure power:
+  file = open("primetime_power.tcl", "w")
+  file.write("set sh_enable_page_mode true \n")
+  file.write("set search_path " + flow_settings['search_path'] + " \n")
+  file.write("set my_top_level " + flow_settings['top_level'] + "\n")
+  file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
+  file.write("set target_library " + flow_settings['target_library'] + "\n")
+  file.write("set link_library " + flow_settings['link_library'] + "\n")
+  file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
+  file.write("link \n")
+  file.write("set my_period " + str(clock_period) + " \n")
+  file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
+  file.write("if { $find_clock != [list] } { \n")
+  file.write("set clk_name $my_clock_pin \n")
+  file.write("create_clock -period $my_period $clk_name} \n\n")
+  if mode_enabled and x <2**len(flow_settings['mode_signal']):
+    for y in range (0, len(flow_settings['mode_signal'])):
+      file.write("set_case_analysis " + str((x >> y) & 1) + " " +  flow_settings['mode_signal'][y] +  " \n")
+  file.write("set power_enable_analysis TRUE \n")
+  file.write(r'set power_analysis_mode "averaged"' + "\n")
+  if flow_settings['generate_activity_file']:
+    file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
+  else:
+    file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " -base_clock $my_clock_pin -type inputs \n")
+  #file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
+  #file.write("read_vcd -input ./modelsim_dir/vcd.vcd \n")
+  file.write(r'read_parasitics -increment ' + os.path.expanduser(flow_settings['pr_folder']) + r'/spef.spef' + "\n")
+  #file.write("update_power \n")
+  file.write(r'report_power > ' + os.path.expanduser(flow_settings['primetime_folder']) + r'/power.rpt' + " \n")
+  file.write("quit\n")
+  file.close()
+
+def write_pt_timing_script(flow_settings,mode_enabled,clock_period,x):
+  """"""
   # backannotate into primetime
   # This part should be reported for all the modes in the design.
   file = open("primetime.tcl", "w")
   file.write("set sh_enable_page_mode true \n")
-  file.write("set search_path " + flow_settings['primetime_lib_path'] + " \n")
+  file.write("set search_path " + flow_settings['search_path'] + " \n")
   file.write("set my_top_level " + flow_settings['top_level'] + "\n")
   file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-  file.write("set target_library " + flow_settings['target_libraries'] + "\n")
-  file.write("set link_library " + flow_settings['link_libraries'] + "\n")
+  file.write("set target_library " + flow_settings['target_library'] + "\n")
+  file.write("set link_library " + flow_settings['link_library'] + "\n")
   file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
   if mode_enabled and x <2**len(flow_settings['mode_signal']):
     for y in range (0, len(flow_settings['mode_signal'])):
@@ -353,6 +403,11 @@ def run_power_timing(flow_settings,mode_enabled,clock_period,pnr_report_str):
   file.write("report_timing > " + os.path.expanduser(flow_settings['primetime_folder']) + "/timing.rpt \n")
   file.write("quit \n")
   file.close()
+
+def run_power_timing(flow_settings,mode_enabled,clock_period,x,pnr_report_str):
+  if not mode_enabled:
+    x = 2**len(flow_settings['mode_signal'])
+  write_pt_timing_script(flow_settings,mode_enabled,clock_period,x)
   # run prime time
   subprocess.call('dc_shell-t -f primetime.tcl | tee pt.log', shell=True,executable="/bin/bash") 
   # Read timing parameters
@@ -367,38 +422,7 @@ def run_power_timing(flow_settings,mode_enabled,clock_period,pnr_report_str):
   except NameError:
     total_delay =  float(data_arrival_time[0])
   file.close()
-  # Create a script to measure power:
-  file = open("primetime_power.tcl", "w")
-  file.write("set sh_enable_page_mode true \n")
-  file.write("set search_path " + flow_settings['primetime_lib_path'] + " \n")
-  file.write("set my_top_level " + flow_settings['top_level'] + "\n")
-  file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-  file.write("set target_library " + flow_settings['target_libraries'] + "\n")
-  file.write("set link_library " + flow_settings['link_libraries'] + "\n")
-  file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
-  file.write("link \n")
-  file.write("set my_period " + str(clock_period) + " \n")
-  file.write("set find_clock [ find port [list $my_clock_pin] ] \n")
-  file.write("if { $find_clock != [list] } { \n")
-  file.write("set clk_name $my_clock_pin \n")
-  file.write("create_clock -period $my_period $clk_name} \n\n")
-  if mode_enabled and x <2**len(flow_settings['mode_signal']):
-    for y in range (0, len(flow_settings['mode_signal'])):
-      file.write("set_case_analysis " + str((x >> y) & 1) + " " +  flow_settings['mode_signal'][y] +  " \n")
-  file.write("set power_enable_analysis TRUE \n")
-  file.write(r'set power_analysis_mode "averaged"' + "\n")
-  if flow_settings['generate_activity_file']:
-    file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
-  else:
-    file.write("set_switching_activity -static_probability " + str(flow_settings['static_probability']) + " -toggle_rate " + str(flow_settings['toggle_rate']) + " -base_clock $my_clock_pin -type inputs \n")
-  #file.write("read_saif -input saif.saif -instance_name testbench/uut \n")
-  #file.write("read_vcd -input ./modelsim_dir/vcd.vcd \n")
-  file.write(r'read_parasitics -increment ' + os.path.expanduser(flow_settings['pr_folder']) + r'/spef.spef' + "\n")
-  #file.write("update_power \n")
-  file.write(r'report_power > ' + os.path.expanduser(flow_settings['primetime_folder']) + r'/power.rpt' + " \n")
-  file.write("quit\n")
-  file.close()
-
+  write_pt_power_script(flow_settings,mode_enabled,clock_period,x)
   # run prime time
   subprocess.call('dc_shell-t -f primetime_power.tcl | tee pt_pwr.log', shell=True,executable="/bin/bash") 
   #copy reports and logs to a unique dir in pt dir
@@ -425,43 +449,85 @@ def run_power_timing(flow_settings,mode_enabled,clock_period,pnr_report_str):
         total_dynamic_power[0] = 0
   file.close() 
   return library_setup_time, data_arrival_time, total_delay, total_dynamic_power   
-    
-# wire loads in the library are WireAreaLowkCon WireAreaLowkAgr WireAreaForZero
-def hardblock_flow(flow_settings):
 
-  # Enter all the signals that change modes
-  lowest_cost = sys.float_info.max
-  lowest_cost_area = 1.0
-  lowest_cost_delay = 1.0
-  lowest_cost_power = 1.0
 
+# #this function adds additional hardblock flow parameters which don't require user input  
+# def add_hb_params(flow_settings,cur_env):
+
+
+def flow_settings_pre_process(processed_flow_settings,cur_env):
+  """Takes values from the flow_settings dict and converts them into data structures which can be used to write synthesis script"""
+  # formatting design_files
   design_files = []
-  if flow_settings['design_language'] == 'verilog':
+  if processed_flow_settings['design_language'] == 'verilog':
     ext_re = re.compile(".*.v")
-  elif flow_settings['design_language'] == 'vhdl':
+  elif processed_flow_settings['design_language'] == 'vhdl':
     ext_re = re.compile(".*.vhdl")
-  elif flow_settings['design_language'] == 'sverilog':
+  elif processed_flow_settings['design_language'] == 'sverilog':
     ext_re = re.compile(".*(.sv)|(.v)")
 
-  design_folder = os.path.expanduser(flow_settings['design_folder'])
+  design_folder = os.path.expanduser(processed_flow_settings['design_folder'])
   design_files = [fn for _, _, fs in os.walk(design_folder) for fn in fs if ext_re.search(fn)]
+  #The syn_write_tcl_script function expects this to be a list of all design files
+  processed_flow_settings["design_files"] = design_files
+  # formatting search_path
   search_path_dirs = []
+  search_path_dirs.append(".")
+  try:
+    syn_root = cur_env.get("SYNOPSYS")
+    search_path_dirs = [os.path.join(syn_root,"libraries",dirname) for dirname in ["syn","syn_ver","sim_ver"] ]
+  except:
+    print("could not find 'SYNOPSYS' environment variable set, please run the following command to your sysopsys home directory")
+    print("export SYNOPSYS=/abs/path/to/synopsys/home")
+    print("Ex. export SYNOPSYS=/CMC/tools/synopsys/syn_vN-2017.09/")
+    sys.exit(1)
+  
+  for p_lib_path in processed_flow_settings["process_lib_paths"]:
+    search_path_dirs.append(p_lib_path)
   search_path_dirs.append(design_folder)
   for root,dirnames,fnames in os.walk(design_folder):
     for dirname,fname in zip(dirnames,fnames):
       if(ext_re.search(fname)):
         search_path_dirs.append(os.path.join(root,dirname))
-  subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['synth_folder']) + "\n", shell=True)
-  subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['pr_folder']) + "\n", shell=True)
-  subprocess.call("mkdir -p " + os.path.expanduser(flow_settings['primetime_folder']) + "\n", shell=True)
+  search_path_str = "\"" + " ".join(search_path_dirs) + "\""
+  processed_flow_settings["search_path"] = search_path_str
+  #formatting target libs
+  processed_flow_settings["target_library"] = "\"" + " ".join(processed_flow_settings['target_libraries']) + "\""
+  processed_flow_settings["link_library"] = "\"" + "* $target_library" + "\""
+  #formatting all paths to files to expand them to user space
+  for flow_key, flow_val in processed_flow_settings.items():
+    if("folder" in flow_key):
+      processed_flow_settings[flow_key] = os.path.expanduser(flow_val)
+
+  #formatting process specific params
+  processed_flow_settings["lef_files"] = "\"" + " ".join(processed_flow_settings['lef_files']) + "\""
+  processed_flow_settings["best_case_libs"] = "\"" + " ".join(processed_flow_settings['best_case_libs']) + "\""
+  processed_flow_settings["standard_libs"] = "\"" + " ".join(processed_flow_settings['standard_libs']) + "\""
+  processed_flow_settings["worst_case_libs"] = "\"" + " ".join(processed_flow_settings['worst_case_libs']) + "\""
+    
+# wire loads in the library are WireAreaLowkCon WireAreaLowkAgr WireAreaForZero
+def hardblock_flow(flow_settings): 
+  cur_env = os.environ.copy()
+  #add_hb_params(flow_settings,cur_env)
+  # processed_flow_settings = {}
+  processed_flow_settings = flow_settings
+  flow_settings_pre_process(processed_flow_settings,cur_env)
+  # Enter all the signals that change modes
+  lowest_cost = sys.float_info.max
+  lowest_cost_area = 1.0
+  lowest_cost_delay = 1.0
+  lowest_cost_power = 1.0
+  subprocess.call("mkdir -p " + flow_settings['synth_folder'] + "\n", shell=True)
+  subprocess.call("mkdir -p " + flow_settings['pr_folder'] + "\n", shell=True)
+  subprocess.call("mkdir -p " + flow_settings['primetime_folder'] + "\n", shell=True)
   # Make sure we managed to read the design files
-  assert len(design_files) >= 1
+  assert len(processed_flow_settings["design_files"]) >= 1
   for clock_period in flow_settings['clock_period']:
     for wire_selection in flow_settings['wire_selection']:
-      synth_report_str = run_synth(flow_settings,search_path_dirs,design_files,clock_period,wire_selection)
+      synth_report_str = run_synth(processed_flow_settings,clock_period,wire_selection)
       for metal_layer in flow_settings['metal_layers']:
         for core_utilization in flow_settings['core_utilization']:
-          pnr_report_str, total_area = run_pnr(flow_settings,metal_layer,core_utilization,synth_report_str)
+          pnr_report_str, total_area = run_pnr(processed_flow_settings,metal_layer,core_utilization,synth_report_str)
           if len(flow_settings['mode_signal']) > 0:
             mode_enabled = True
           else:
@@ -471,7 +537,7 @@ def hardblock_flow(flow_settings):
           if flow_settings['generate_activity_file'] is True:
             run_sim()
           for x in range(0, 2**len(flow_settings['mode_signal']) + 1):
-            library_setup_time, data_arrival_time, total_delay, total_dynamic_power = run_power_timing(flow_settings,mode_enabled,clock_period,pnr_report_str)
+            library_setup_time, data_arrival_time, total_delay, total_dynamic_power = run_power_timing(flow_settings,mode_enabled,clock_period,x,pnr_report_str)
             # write the final report file:
             if mode_enabled and x <2**len(flow_settings['mode_signal']):
               file = open("report_mode" + str(x) + "_" + str(flow_settings['top_level']) + "_" + str(clock_period) + "_" + str(wire_selection) + "_wire_" + str(metal_layer) + "_" + str(core_utilization) + ".txt" ,"w")
diff --git a/coffe/utils.py b/coffe/utils.py
index 664d72e..b2640cc 100644
--- a/coffe/utils.py
+++ b/coffe/utils.py
@@ -679,7 +679,24 @@ def load_arch_params(filename):
     return arch_params 
 
 
+def sanatize_str_input_to_list(value):
+    """Makes sure unneeded quotes arent included when a string of values is seperated by a space and saved into
+    string seperated by spaces and surrouneded with quotes"""
+    vals = (value.strip("\"")).split(" ")
+    return vals
 
+def check_hard_params(hard_params,optional_params):
+    """
+    This function checks the hardblock/process parameters to make sure that all the parameters have been read in.
+    Right now, this functions just checks really basic stuff like 
+    checking for unset values
+    """
+
+    #TODO make this sort of a documentation for each parameter
+    for key,val in hard_params.items():
+        if ((val == "" or val == -1 or val == -1.0 or val == []) and key not in optional_params):
+            print("param \"%s\" is unset, please go to your hardblock/process params file and set it" % (key))
+            sys.exit(1)
 
 def load_hard_params(filename):
     """ Parse the hard block description file and load values into dictionary. 
@@ -710,24 +727,23 @@ def load_hard_params(filename):
         'synth_folder': "",
         'show_warnings': False,
         'synthesis_only': False,
-        'asic_flow_only': False,
         'read_saif_file': False,
         'static_probability': -1.0,
         'toggle_rate': -1,
-        'link_libraries': '',
-        'target_libraries': '',
-        'lef_files': '',
-        'best_case_libs': '',
-        'standard_libs': '',
-        'worst_case_libs': '',
+        #'link_libraries': '',
+        'target_libraries': [],
+        'lef_files': [],
+        'best_case_libs': [],
+        'standard_libs': [],
+        'worst_case_libs': [],
         'power_ring_width': -1,
         'power_ring_spacing': -1,
         'height_to_width_ratio': -1.0,
         'core_utilization': [],
         'space_around_core': -1,
         'pr_folder': "",
-        'primetime_lib_path': '',
-        'primetime_lib_name': '',
+        #'primetime_lib_path': '',
+        #'primetime_lib_name': '',
         'primetime_folder': "" ,
         'delay_cost_exp': 1.0,
         'area_cost_exp': 1.0,
@@ -748,10 +764,10 @@ def load_hard_params(filename):
         'generate_activity_file': False,
         'core_site_name':'',
         'mode_signal': [],
+        'process_lib_paths': [],
+        'process_params_file': "",
     }
 
-
-
     hard_file = open(filename, 'r')
     for line in hard_file:
     
@@ -813,36 +829,12 @@ def load_hard_params(filename):
             hard_params['clock_pin_name'] = value
         elif param == 'clock_period':
             hard_params['clock_period'].append(value)
-        elif param == 'wire_selection':
-            hard_params['wire_selection'].append(value)
         elif param == 'core_utilization':
             hard_params['core_utilization'].append(value)
-        elif param == 'metal_layers':
-            hard_params['metal_layers'].append(value)
-        elif param == 'metal_layer_names':
-            hard_params['metal_layer_names'] += eval(value)
-        elif param == 'power_ring_metal_layer_names':
-            hard_params['power_ring_metal_layer_names'] += eval(value)
         elif param == 'map_file':
             hard_params['map_file'] = value.strip()
-        elif param == 'gnd_net':
-            hard_params['gnd_net'] = value.strip()
-        elif param == 'gnd_pin':
-            hard_params['gnd_pin'] = value.strip()
-        elif param == 'pwr_net':
-            hard_params['pwr_net'] = value.strip()
-        elif param == 'pwr_pin':
-            hard_params['pwr_pin'] = value.strip()
         elif param == 'tilehi_tielo_cells_between_power_gnd':
             hard_params['tilehi_tielo_cells_between_power_gnd'] = (value == "True")
-        elif param == 'inv_footprint':
-            hard_params['inv_footprint'] = value.strip()
-        elif param == 'buf_footprint':
-            hard_params['buf_footprint'] = value.strip()
-        elif param == 'delay_footprint':
-            hard_params['delay_footprint'] = value.strip()
-        elif param == 'filler_cell_names':
-            hard_params['filler_cell_names'] += eval(value)
         elif param == 'generate_activity_file':
             hard_params['generate_activity_file'] = (value == "True")
         elif param == 'crossbar_modelling':
@@ -857,26 +849,12 @@ def load_hard_params(filename):
             hard_params['show_warnings'] = (value == "True")
         elif param == 'synthesis_only':
             hard_params['synthesis_only'] = (value == "True")
-        elif param == 'asic_flow_only':
-            hard_params['asic_flow_only'] = (value == "True")
         elif param == 'read_saif_file':
             hard_params['read_saif_file'] = (value == "True")
         elif param == 'static_probability':
             hard_params['static_probability'] = value
         elif param == 'toggle_rate':
             hard_params['toggle_rate'] = value
-        elif param == 'link_libraries':
-            hard_params['link_libraries'] = value
-        elif param == 'target_libraries':
-            hard_params['target_libraries'] = value
-        elif param == 'lef_files':
-            hard_params['lef_files'] = value
-        elif param == 'best_case_libs':
-            hard_params['best_case_libs'] = value
-        elif param == 'standard_libs':
-            hard_params['standard_libs'] = value
-        elif param == 'worst_case_libs':
-            hard_params['worst_case_libs'] = value
         elif param == 'power_ring_width':
             hard_params['power_ring_width'] = value
         elif param == 'power_ring_spacing':
@@ -887,18 +865,122 @@ def load_hard_params(filename):
             hard_params['space_around_core'] = value
         elif param == 'pr_folder':
             hard_params['pr_folder'] = value
-        elif param == 'primetime_lib_path':
-            hard_params['primetime_lib_path'] = value
-        elif param == 'primetime_lib_name':
-            hard_params['primetime_lib_name'] = value
         elif param == 'primetime_folder':
             hard_params['primetime_folder'] = value
-        elif param == 'core_site_name':
-            hard_params['core_site_name'] = value
         elif param == 'mode_signal':
             hard_params['mode_signal'].append(value)
-
+        elif param == "process_params_file":
+            hard_params["process_params_file"] = value
+        #To allow for the legacy way of inputting process specific params I'll keep these in (the only reason for having a seperate file is for understandability)
+        if param == "process_lib_paths":
+            hard_params["process_lib_paths"] = sanatize_str_input_to_list(value)
+        elif param == 'target_libraries':
+            hard_params['target_libraries'] = sanatize_str_input_to_list(value)
+        elif param == 'lef_files':
+            hard_params['lef_files'] = sanatize_str_input_to_list(value)
+        elif param == 'best_case_libs':
+            hard_params['best_case_libs'] = sanatize_str_input_to_list(value)
+        elif param == 'standard_libs':
+            hard_params['standard_libs'] = sanatize_str_input_to_list(value)
+        elif param == 'worst_case_libs':
+            hard_params['worst_case_libs'] = sanatize_str_input_to_list(value)
+        elif param == 'core_site_name':
+            hard_params['core_site_name'] = value
+        elif param == 'inv_footprint':
+            hard_params['inv_footprint'] = value.strip()
+        elif param == 'buf_footprint':
+            hard_params['buf_footprint'] = value.strip()
+        elif param == 'delay_footprint':
+            hard_params['delay_footprint'] = value.strip()
+        elif param == 'filler_cell_names':
+            hard_params['filler_cell_names'] += eval(value)
+        elif param == 'metal_layer_names':
+            hard_params['metal_layer_names'] += eval(value)
+        elif param == 'power_ring_metal_layer_names':
+            hard_params['power_ring_metal_layer_names'] += eval(value)
+        elif param == 'metal_layers':
+            hard_params['metal_layers'].append(value)
+        elif param == 'gnd_net':
+            hard_params['gnd_net'] = value.strip()
+        elif param == 'gnd_pin':
+            hard_params['gnd_pin'] = value.strip()
+        elif param == 'pwr_net':
+            hard_params['pwr_net'] = value.strip()
+        elif param == 'pwr_pin':
+            hard_params['pwr_pin'] = value.strip()
+        elif param == 'wire_selection':
+            hard_params['wire_selection'].append(value)
+    
     hard_file.close()
+
+    if hard_params["process_params_file"] != "":
+        process_param_file = open(hard_params["process_params_file"],"r")
+        for line in process_param_file:
+            # Ignore comment lines
+            if line.startswith('#'):
+                continue
+            
+            # Remove line feeds and spaces
+            line = line.replace('\n', '')
+            line = line.replace('\r', '')
+            line = line.replace('\t', '')
+            
+            # Ignore empty lines
+            if line == "":
+                continue
+            
+            # Split lines at '='
+            words = line.split('=')
+            if words[0] not in hard_params.keys():
+                print("ERROR: Found invalid hard block parameter (" + words[0] + ") in " + filename)
+                sys.exit()
+            
+            param = words[0]
+            value = words[1]
+            if param == "process_lib_paths":
+                hard_params["process_lib_paths"] = sanatize_str_input_to_list(value)
+            elif param == 'target_libraries':
+                hard_params['target_libraries'] = sanatize_str_input_to_list(value)
+            elif param == 'lef_files':
+                hard_params['lef_files'] = sanatize_str_input_to_list(value)
+            elif param == 'best_case_libs':
+                hard_params['best_case_libs'] = sanatize_str_input_to_list(value)
+            elif param == 'standard_libs':
+                hard_params['standard_libs'] = sanatize_str_input_to_list(value)
+            elif param == 'worst_case_libs':
+                hard_params['worst_case_libs'] = sanatize_str_input_to_list(value)
+            elif param == 'core_site_name':
+                hard_params['core_site_name'] = value
+            elif param == 'inv_footprint':
+                hard_params['inv_footprint'] = value.strip()
+            elif param == 'buf_footprint':
+                hard_params['buf_footprint'] = value.strip()
+            elif param == 'delay_footprint':
+                hard_params['delay_footprint'] = value.strip()
+            elif param == 'filler_cell_names':
+                hard_params['filler_cell_names'] += eval(value)
+            elif param == 'metal_layer_names':
+                hard_params['metal_layer_names'] += eval(value)
+            elif param == 'power_ring_metal_layer_names':
+                hard_params['power_ring_metal_layer_names'] += eval(value)
+            elif param == 'metal_layers':
+                hard_params['metal_layers'].append(value)
+            elif param == 'gnd_net':
+                hard_params['gnd_net'] = value.strip()
+            elif param == 'gnd_pin':
+                hard_params['gnd_pin'] = value.strip()
+            elif param == 'pwr_net':
+                hard_params['pwr_net'] = value.strip()
+            elif param == 'pwr_pin':
+                hard_params['pwr_pin'] = value.strip()
+            elif param == 'wire_selection':
+                hard_params['wire_selection'].append(value)
+            
+        process_param_file.close()
+    #TODO make this more accessable outside of the code, but for now this is how I declare optional parameters
+    optional_params = ["process_params_file","mode_signal"]
+    check_hard_params(hard_params,optional_params)
+
     return hard_params
 
 
diff --git a/input_files/simple_dsp_slice_65nm/dsp_slice.txt b/input_files/simple_dsp_slice_65nm/dsp_slice.txt
index d61b971..5d39244 100644
--- a/input_files/simple_dsp_slice_65nm/dsp_slice.txt
+++ b/input_files/simple_dsp_slice_65nm/dsp_slice.txt
@@ -18,6 +18,8 @@ design_language=verilog
 delay_cost_exp=1.0
 area_cost_exp=1.0
 
+process_lib_paths="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
+
 ########################################
 ########## Synthesis Settings ##########
 ########################################
@@ -26,7 +28,7 @@ area_cost_exp=1.0
 clock_pin_name=clk
 
 # Desired clock period in ns
-clock_period=3.0
+clock_period=1.82
 
 # Name of the top-level entity in the design
 top_level=dsp_slice
@@ -61,7 +63,7 @@ generate_activity_file=False
 # link_libraries="/home/projects/ljohn/aarora1/ceid/ceid_umc65ll/synopsys/ceid_vlsiLab_umc65ll_stdCells.db dw_foundation.sldb"
 
 # uncomment below for University of Toronto
-link_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.db dw_foundation.sldb"
+#link_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.db dw_foundation.sldb"
 
 #target_libraries=/home/projects/ljohn/aarora1/FreePDK45/FreePDK45/osu_soc/lib/files/gscl45nm.db
 
@@ -78,7 +80,7 @@ target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_En
 # Libraries required in EDI:
 
 #this can be a list of numbers
-metal_layers=4
+metal_layers=6
 
 #names of metal layers starting from the bottom-most layer on the left. use a python list format. 
 
@@ -86,7 +88,7 @@ metal_layers=4
 #metal_layer_names=["ME1", "ME2", "ME3", "ME4"]
 
 # uncomment below for University of Toronto
-metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6"]
+metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "AP"]
 
 #names of metal layers to use for each side of the power ring
 #order: top, bottom, left, right
@@ -202,8 +204,8 @@ pr_folder=~/COFFE/output_files/simple_dsp_slice_65nm/dsp_slice_pnr
 #primetime_lib_name=ceid_vlsiLab_umc65ll_stdCells.db
 
 # uncomment below for University of Toronto
-primetime_lib_path="/CMC/tools/synopsys/syn_vN-2017.09/libraries/syn /CMC/tools/synopsys/syn_vN-2017.09/dw/syn_ver /CMC/tools/synopsys/syn_vN-2017.09/dw/sim_ver /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
-primetime_lib_name=tcbn65gplustc.db
+#primetime_lib_path="/CMC/tools/synopsys/syn_vN-2017.09/libraries/syn /CMC/tools/synopsys/syn_vN-2017.09/dw/syn_ver /CMC/tools/synopsys/syn_vN-2017.09/dw/sim_ver /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
+#primetime_lib_name=tcbn65gplustc.db
 
 
 #the directory containing the primetime library and the name of the library file
diff --git a/input_files/strtx_III_dsp/dsp_hb_settings.txt b/input_files/strtx_III_dsp/dsp_hb_settings.txt
index 6a313c5..4684aab 100755
--- a/input_files/strtx_III_dsp/dsp_hb_settings.txt
+++ b/input_files/strtx_III_dsp/dsp_hb_settings.txt
@@ -14,6 +14,9 @@ design_language=verilog
 delay_cost_exp=1.0
 area_cost_exp=1.0
 
+#ASIC flow settings
+#path to absolute paths needed for process parameters (relative to coffe home repo)
+process_params_file=input_files/strtx_III_dsp/process_specific_params.txt
 
 ########################################
 ########## Synthesis Settings ##########
@@ -21,7 +24,6 @@ area_cost_exp=1.0
 
 # Name of the clock pin in the design
 clock_pin_name=clk
-## -> this means that this was changed to run hspice on bastet
 # Desired clock period in ns
 ##clock_period=1.53
 #clock_period=1.66
@@ -58,7 +60,7 @@ generate_activity_file=False
 # Location of the library files.
 # if you have more than one library, please provide them similiar to the example below.
 
-link_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.db"
+#link_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.db"
 
 target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.db"
 
@@ -69,58 +71,59 @@ target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_En
 # Libraries required in EDI:
 
 #metal_layers=8
-metal_layers=7
+#metal_layers=7
 #metal_layers=6
 #metal_layers=5
 
 #names of metal layers starting from the bottom-most layer on the left. use a python list format. 
-metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "AP"]
+#metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "AP"]
 
 #names of metal layers to use for each side of the power ring
 #order: top, bottom, left, right
-power_ring_metal_layer_names=["M1", "M1", "M2", "M2"]
+#power_ring_metal_layer_names=["M1", "M1", "M2", "M2"]
 
 #name of the file to use for layer mapping. used for stream out.
 #set it to None if you want the tool to create a generic map file
 map_file=streamOut.map
+
 #wire_selection=WireAreaLowkCon
-wire_selection=WireAreaLowkAgr
+#wire_selection=WireAreaLowkAgr
 #wire_selection=WireAreaForZero
 #specify names of ground and power pins and nets in the library
-gnd_net=VSS
-gnd_pin=VSS
-pwr_net=VDD
-pwr_pin=VDD
+#gnd_net=VSS
+#gnd_pin=VSS
+#pwr_net=VDD
+#pwr_pin=VDD
+
 tilehi_tielo_cells_between_power_gnd=True
 
 
 #specify footprint names for inverters, buffers, delays.
 #this is optional. you can get these values from the lib file.
 #you can also specify None, if you can't find them in the lib file.
-inv_footprint=INVD0
-buf_footprint=BUFFD1
-delay_footprint=DEL0
+#inv_footprint=INVD0
+#buf_footprint=BUFFD1
+#delay_footprint=DEL0
 
 #list of filler cell names. use a python list format.
 #the names can be obtained from .lib files.
-filler_cell_names=["FILL1", "FILL16", "FILL1_LL", "FILL2", "FILL32", "FILL64", "FILL8", "FILL_NW_FA_LL", "FILL_NW_HH", "FILL_NW_LL"]
+#filler_cell_names=["FILL1", "FILL16", "FILL1_LL", "FILL2", "FILL32", "FILL64", "FILL8", "FILL_NW_FA_LL", "FILL_NW_HH", "FILL_NW_LL"]
 
 #name of the core site in the floorplan. can be obtained from lef files.
-core_site_name=core
+#core_site_name=core
 
 #specify the utilization of the core site. you can specify multiple ones on different lines.
-##core_utilization=0.85
+#core_utilization=0.85
 core_utilization=0.90
-##core_utilization=0.95
-
-lef_files="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Back_End/lef/tcbn65gplus_200a/lef/tcbn65gplus_9lmT2.lef /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Back_End/lef/tpzn65gpgv2_140c/mt_2/9lm/lef/antenna_9lm.lef /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Back_End/lef/tpzn65gpgv2_140c/mt_2/9lm/lef/tpzn65gpgv2_9lm.lef"
+#core_utilization=0.95
 
+#lef_files="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Back_End/lef/tcbn65gplus_200a/lef/tcbn65gplus_9lmT2.lef /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Back_End/lef/tpzn65gpgv2_140c/mt_2/9lm/lef/antenna_9lm.lef /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Back_End/lef/tpzn65gpgv2_140c/mt_2/9lm/lef/tpzn65gpgv2_9lm.lef"
 
-best_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplusbc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2bc.lib"
+#best_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplusbc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2bc.lib"
 
-standard_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2tc.lib"
+#standard_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2tc.lib"
 
-worst_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.lib"
+#worst_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.lib"
 
 
 
@@ -131,11 +134,9 @@ height_to_width_ratio=4.0
 
 space_around_core=5
 
-
 # The folder in which place and route reports and post-routing netlists and spef files will be stored
 pr_folder=~/COFFE/output_files/strtx_III_dsp/pr
 
-
 ##############################################
 ########## Prime Time Settings ###############
 ##############################################
@@ -143,8 +144,6 @@ pr_folder=~/COFFE/output_files/strtx_III_dsp/pr
 mode_signal=mode_0
 mode_signal=mode_1
 
-primetime_lib_path=". /CMC/tools/synopsys/syn_vN-2017.09/libraries/syn /CMC/tools/synopsys/syn_vN-2017.09/dw/syn_ver /CMC/tools/synopsys/syn_vN-2017.09/dw/sim_ver /CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
-
 primetime_folder=~/COFFE/output_files/strtx_III_dsp/pt
 
 # COFFE parameters:
diff --git a/input_files/strtx_III_dsp/process_specific_params.txt b/input_files/strtx_III_dsp/process_specific_params.txt
new file mode 100644
index 0000000..09018a6
--- /dev/null
+++ b/input_files/strtx_III_dsp/process_specific_params.txt
@@ -0,0 +1,62 @@
+#This file contains all parameters relevant to process technology, seperated due to inclusion of absolute paths and clarity
+
+#############################################
+############# ASIC Flow Settings ############
+#############################################
+process_lib_paths="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
+
+# Standard cell libs which we are targeting for synthesis
+
+target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.db"
+
+##############################################
+########## Place and Route Settings ##########
+##############################################
+
+# Libraries required in EDI:
+
+#specify LEF files in the library. remember to specify the tech/header file first and then the file that has macros/cells.
+lef_files="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Back_End/lef/tcbn65gplus_200a/lef/tcbn65gplus_9lmT2.lef /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Back_End/lef/tpzn65gpgv2_140c/mt_2/9lm/lef/antenna_9lm.lef /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Back_End/lef/tpzn65gpgv2_140c/mt_2/9lm/lef/tpzn65gpgv2_9lm.lef"
+
+#list names (full paths) of the .lib files for various corners
+best_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplusbc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2bc.lib"
+standard_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2tc.lib"
+worst_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.lib"
+
+#metal_layers=8
+metal_layers=7
+#metal_layers=6
+#metal_layers=5
+
+#names of metal layers starting from the bottom-most layer on the left. use a python list format. 
+metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "AP"]
+
+#names of metal layers to use for each side of the power ring
+#order: top, bottom, left, right
+power_ring_metal_layer_names=["M1", "M1", "M2", "M2"]
+
+#specify wire load model (options found in library)
+
+#wire_selection=WireAreaLowkCon
+wire_selection=WireAreaLowkAgr
+#wire_selection=WireAreaForZero
+
+#specify names of ground and power pins and nets in the library
+gnd_net=VSS
+gnd_pin=VSS
+pwr_net=VDD
+pwr_pin=VDD
+
+#specify footprint names for inverters, buffers, delays.
+#this is optional. you can get these values from the lib file.
+#you can also specify None, if you can't find them in the lib file.
+inv_footprint=INVD0
+buf_footprint=BUFFD1
+delay_footprint=DEL0
+
+#list of filler cell names. use a python list format.
+#the names can be obtained from .lib files.
+filler_cell_names=["FILL1", "FILL16", "FILL1_LL", "FILL2", "FILL32", "FILL64", "FILL8", "FILL_NW_FA_LL", "FILL_NW_HH", "FILL_NW_LL"]
+
+#name of the core site in the floorplan. can be obtained from lef files.
+core_site_name=core
diff --git a/unit_test.sh b/unit_test.sh
new file mode 100644
index 0000000..24cdc1f
--- /dev/null
+++ b/unit_test.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+#This is a unit test, which just makes sure that all stages of the COFFE flow runs, then tests the reporting/plotting utilities
+py2=$(which python2)
+py3=$(which python3)
+if [ $py2 != "" ] || [ $py3 != "" ] 
+then
+    #run the coffe flow
+    python2 coffe.py -ho -i 1 input_files/strtx_III_dsp/dsp_coffe_params.txt
+    cd ./analyze_results
+    python3 condense_reports.py -r ../output_files/strtx_III_dsp/arch_out_dir
+    python3 plot_coffe_results.py -c report_csv_out/condensed_report.csv
+else
+    echo "couldn't find python2 executable"
+fi
\ No newline at end of file

From ebffb6249edfe24a00d1d7a6a22d8ee0e1c3a44a Mon Sep 17 00:00:00 2001
From: Stephen More <stephen.w.more@gmail.com>
Date: Tue, 18 Oct 2022 19:55:51 -0400
Subject: [PATCH 6/7] committed changes detailed in most recent edit of PR
 conversion

---
 coffe/hardblock_functions.py                    |  5 +++--
 coffe/utils.py                                  | 15 ++++++++++++++-
 input_files/strtx_III_dsp/dsp_hb_settings.txt   | 11 ++++++-----
 .../strtx_III_dsp/process_specific_params.txt   | 17 +++++++++++++++--
 unit_test.sh                                    |  4 ++--
 5 files changed, 40 insertions(+), 12 deletions(-)
 mode change 100644 => 100755 unit_test.sh

diff --git a/coffe/hardblock_functions.py b/coffe/hardblock_functions.py
index 48c76ee..1a0ef4b 100644
--- a/coffe/hardblock_functions.py
+++ b/coffe/hardblock_functions.py
@@ -352,7 +352,7 @@ def write_pt_power_script(flow_settings,mode_enabled,clock_period,x):
   file.write("set search_path " + flow_settings['search_path'] + " \n")
   file.write("set my_top_level " + flow_settings['top_level'] + "\n")
   file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-  file.write("set target_library " + flow_settings['target_library'] + "\n")
+  file.write("set target_library " + flow_settings['primetime_libs'] + "\n")
   file.write("set link_library " + flow_settings['link_library'] + "\n")
   file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
   file.write("link \n")
@@ -387,7 +387,7 @@ def write_pt_timing_script(flow_settings,mode_enabled,clock_period,x):
   file.write("set search_path " + flow_settings['search_path'] + " \n")
   file.write("set my_top_level " + flow_settings['top_level'] + "\n")
   file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-  file.write("set target_library " + flow_settings['target_library'] + "\n")
+  file.write("set target_library " + flow_settings['primetime_libs'] + "\n")
   file.write("set link_library " + flow_settings['link_library'] + "\n")
   file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
   if mode_enabled and x <2**len(flow_settings['mode_signal']):
@@ -504,6 +504,7 @@ def flow_settings_pre_process(processed_flow_settings,cur_env):
   processed_flow_settings["best_case_libs"] = "\"" + " ".join(processed_flow_settings['best_case_libs']) + "\""
   processed_flow_settings["standard_libs"] = "\"" + " ".join(processed_flow_settings['standard_libs']) + "\""
   processed_flow_settings["worst_case_libs"] = "\"" + " ".join(processed_flow_settings['worst_case_libs']) + "\""
+  processed_flow_settings["primetime_libs"] = "\"" + " ".join(processed_flow_settings['primetime_libs']) + "\""
     
 # wire loads in the library are WireAreaLowkCon WireAreaLowkAgr WireAreaForZero
 def hardblock_flow(flow_settings): 
diff --git a/coffe/utils.py b/coffe/utils.py
index b2640cc..50114c1 100644
--- a/coffe/utils.py
+++ b/coffe/utils.py
@@ -697,6 +697,9 @@ def check_hard_params(hard_params,optional_params):
         if ((val == "" or val == -1 or val == -1.0 or val == []) and key not in optional_params):
             print("param \"%s\" is unset, please go to your hardblock/process params file and set it" % (key))
             sys.exit(1)
+        elif(key == "pnr_tool" and val != "encounter" and val != "innovus" ):
+            print("ERROR: pnr_tool must be set as either \"encounter\" or \"innovus\" ")
+            sys.exit(1)
 
 def load_hard_params(filename):
     """ Parse the hard block description file and load values into dictionary. 
@@ -743,7 +746,7 @@ def load_hard_params(filename):
         'space_around_core': -1,
         'pr_folder': "",
         #'primetime_lib_path': '',
-        #'primetime_lib_name': '',
+        'primetime_libs': [],
         'primetime_folder': "" ,
         'delay_cost_exp': 1.0,
         'area_cost_exp': 1.0,
@@ -766,6 +769,8 @@ def load_hard_params(filename):
         'mode_signal': [],
         'process_lib_paths': [],
         'process_params_file': "",
+        #'pnr_tool': "",
+        #'process_size': "",
     }
 
     hard_file = open(filename, 'r')
@@ -871,9 +876,15 @@ def load_hard_params(filename):
             hard_params['mode_signal'].append(value)
         elif param == "process_params_file":
             hard_params["process_params_file"] = value
+        # elif param == "pnr_tool":
+        #     hard_params["pnr_tool"] = value
+        # elif param == "process_size":
+        #     hard_params["process_size"] = value
         #To allow for the legacy way of inputting process specific params I'll keep these in (the only reason for having a seperate file is for understandability)
         if param == "process_lib_paths":
             hard_params["process_lib_paths"] = sanatize_str_input_to_list(value)
+        elif param == "primetime_libs":
+            hard_params["primetime_libs"] = sanatize_str_input_to_list(value)
         elif param == 'target_libraries':
             hard_params['target_libraries'] = sanatize_str_input_to_list(value)
         elif param == 'lef_files':
@@ -975,6 +986,8 @@ def load_hard_params(filename):
                 hard_params['pwr_pin'] = value.strip()
             elif param == 'wire_selection':
                 hard_params['wire_selection'].append(value)
+            elif param == "primetime_libs":
+                hard_params["primetime_libs"] = sanatize_str_input_to_list(value)
             
         process_param_file.close()
     #TODO make this more accessable outside of the code, but for now this is how I declare optional parameters
diff --git a/input_files/strtx_III_dsp/dsp_hb_settings.txt b/input_files/strtx_III_dsp/dsp_hb_settings.txt
index 4684aab..aed3bde 100755
--- a/input_files/strtx_III_dsp/dsp_hb_settings.txt
+++ b/input_files/strtx_III_dsp/dsp_hb_settings.txt
@@ -25,7 +25,7 @@ process_params_file=input_files/strtx_III_dsp/process_specific_params.txt
 # Name of the clock pin in the design
 clock_pin_name=clk
 # Desired clock period in ns
-##clock_period=1.53
+#clock_period=1.53
 #clock_period=1.66
 #clock_period=1.81
 clock_period=2.0
@@ -70,13 +70,14 @@ target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_En
 
 # Libraries required in EDI:
 
+#metal_layers=9
 #metal_layers=8
 #metal_layers=7
 #metal_layers=6
 #metal_layers=5
 
 #names of metal layers starting from the bottom-most layer on the left. use a python list format. 
-#metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "AP"]
+#metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "M8", "M9","AP"]
 
 #names of metal layers to use for each side of the power ring
 #order: top, bottom, left, right
@@ -132,7 +133,7 @@ power_ring_width=3
 power_ring_spacing=3
 height_to_width_ratio=4.0
 
-space_around_core=5
+space_around_core=10
 
 # The folder in which place and route reports and post-routing netlists and spef files will be stored
 pr_folder=~/COFFE/output_files/strtx_III_dsp/pr
@@ -141,8 +142,8 @@ pr_folder=~/COFFE/output_files/strtx_III_dsp/pr
 ########## Prime Time Settings ###############
 ##############################################
 
-mode_signal=mode_0
-mode_signal=mode_1
+#mode_signal=mode_0
+#mode_signal=mode_1
 
 primetime_folder=~/COFFE/output_files/strtx_III_dsp/pt
 
diff --git a/input_files/strtx_III_dsp/process_specific_params.txt b/input_files/strtx_III_dsp/process_specific_params.txt
index 09018a6..d624ad2 100644
--- a/input_files/strtx_III_dsp/process_specific_params.txt
+++ b/input_files/strtx_III_dsp/process_specific_params.txt
@@ -3,10 +3,15 @@
 #############################################
 ############# ASIC Flow Settings ############
 #############################################
+#node size of process in nm
+#process_size=65
+
 process_lib_paths="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
 
+########################################
+########## Synthesis Settings ##########
+########################################
 # Standard cell libs which we are targeting for synthesis
-
 target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.db"
 
 ##############################################
@@ -23,13 +28,14 @@ best_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/
 standard_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2tc.lib"
 worst_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.lib"
 
+
 #metal_layers=8
 metal_layers=7
 #metal_layers=6
 #metal_layers=5
 
 #names of metal layers starting from the bottom-most layer on the left. use a python list format. 
-metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "AP"]
+metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "M8", "M9", "AP"]
 
 #names of metal layers to use for each side of the power ring
 #order: top, bottom, left, right
@@ -60,3 +66,10 @@ filler_cell_names=["FILL1", "FILL16", "FILL1_LL", "FILL2", "FILL32", "FILL64", "
 
 #name of the core site in the floorplan. can be obtained from lef files.
 core_site_name=core
+
+
+##############################################
+############## Power & Timing ################
+##############################################
+
+primetime_libs="tcbn65gpluswc.db tpzn65gpgv2wc.db"
\ No newline at end of file
diff --git a/unit_test.sh b/unit_test.sh
old mode 100644
new mode 100755
index 24cdc1f..a6900c4
--- a/unit_test.sh
+++ b/unit_test.sh
@@ -5,8 +5,8 @@ py2=$(which python2)
 py3=$(which python3)
 if [ $py2 != "" ] || [ $py3 != "" ] 
 then
-    #run the coffe flow
-    python2 coffe.py -ho -i 1 input_files/strtx_III_dsp/dsp_coffe_params.txt
+    #run the coffe flow, hardblock and full custom
+    python2 coffe.py -i 1 input_files/strtx_III_dsp/dsp_coffe_params.txt
     cd ./analyze_results
     python3 condense_reports.py -r ../output_files/strtx_III_dsp/arch_out_dir
     python3 plot_coffe_results.py -c report_csv_out/condensed_report.csv

From 522361206938eff56b31d02b966d81afdd345a7c Mon Sep 17 00:00:00 2001
From: Stephen More <stephen.w.more@gmail.com>
Date: Tue, 18 Oct 2022 20:11:25 -0400
Subject: [PATCH 7/7] added mentioned results to PR

---
 .../results_archive/condensed_report.csv      | 211 +++++++++++++++++
 .../results_archive/fig_archives/area_fig.png | Bin 0 -> 26891 bytes
 .../results_archive/fig_archives/cost_fig.png | Bin 0 -> 36614 bytes
 .../fig_archives/delay_fig.png                | Bin 0 -> 24684 bytes
 .../fig_archives/power_fig.png                | Bin 0 -> 26602 bytes
 .../final_full_custom_flow_report.txt         | 220 ++++++++++++++++++
 6 files changed, 431 insertions(+)
 create mode 100644 analyze_results/results_archive/condensed_report.csv
 create mode 100644 analyze_results/results_archive/fig_archives/area_fig.png
 create mode 100644 analyze_results/results_archive/fig_archives/cost_fig.png
 create mode 100644 analyze_results/results_archive/fig_archives/delay_fig.png
 create mode 100644 analyze_results/results_archive/fig_archives/power_fig.png
 create mode 100644 analyze_results/results_archive/final_full_custom_flow_report.txt

diff --git a/analyze_results/results_archive/condensed_report.csv b/analyze_results/results_archive/condensed_report.csv
new file mode 100644
index 0000000..71b21e4
--- /dev/null
+++ b/analyze_results/results_archive/condensed_report.csv
@@ -0,0 +1,211 @@
+delay,wire_model,power,mode,metal_layers,utilization,top_level_mod,area,period
+1.96,WireAreaLowkAgr,0.0365025,mode0,8,0.85,dsp,45358.020,2.0
+2.43,WireAreaLowkAgr,0.0299125,mode1,7,0.85,dsp,43101.540,2.5
+1.54,WireAreaLowkAgr,0.0517575,mode1,7,0.90,dsp,54244.242,1.53
+2.48,WireAreaLowkAgr,0.0291045,mode2,5,0.85,dsp,43101.540,2.5
+1.97,WireAreaLowkAgr,0.0365191,mode0,7,0.85,dsp,45358.020,2.0
+1.96,WireAreaLowkAgr,0.0371464,mode3,5,0.85,dsp,45358.020,2.0
+1.54,WireAreaLowkAgr,0.0518646,mode1,8,0.90,dsp,54244.242,1.53
+2.43,WireAreaLowkAgr,0.0298639,mode1,8,0.85,dsp,43101.540,2.5
+1.82,WireAreaLowkAgr,0.0421164,mode1,8,0.90,dsp,45627.003,1.81
+1.96,WireAreaLowkAgr,0.0373565,mode1,7,0.95,dsp,40583.547,2.0
+1.97,WireAreaLowkAgr,0.0363421,mode2,5,0.95,dsp,40583.547,2.0
+2.5,WireAreaLowkAgr,0.0295935,mode0,8,0.95,dsp,38565.072,2.5
+1.95,WireAreaLowkAgr,0.0373582,mode1,8,0.95,dsp,40583.547,2.0
+2.49,WireAreaLowkAgr,0.0295947,mode0,7,0.95,dsp,38565.072,2.5
+2.4,WireAreaLowkAgr,0.0301979,mode3,5,0.95,dsp,38565.072,2.5
+1.54,WireAreaLowkAgr,0.0510703,mode3,8,0.95,dsp,51389.991,1.53
+1.56,WireAreaLowkAgr,0.051137,mode3,7,0.95,dsp,51389.991,1.53
+2.49,WireAreaLowkAgr,0.0297807,none,5,0.90,dsp,40707.072,2.5
+2.49,WireAreaLowkAgr,0.0301064,none,7,0.95,dsp,38565.072,2.5
+2.5,WireAreaLowkAgr,0.0301082,none,8,0.95,dsp,38565.072,2.5
+1.97,WireAreaLowkAgr,0.0372526,none,7,0.85,dsp,45358.020,2.0
+1.96,WireAreaLowkAgr,0.0372499,none,8,0.85,dsp,45358.020,2.0
+1.55,WireAreaLowkAgr,0.0510934,mode0,6,0.85,dsp,57436.848,1.53
+1.57,WireAreaLowkAgr,0.051609,mode1,5,0.95,dsp,51389.991,1.53
+2.49,WireAreaLowkAgr,0.0291751,mode0,5,0.90,dsp,40707.072,2.5
+2.44,WireAreaLowkAgr,0.0296334,mode3,7,0.90,dsp,40707.072,2.5
+1.97,WireAreaLowkAgr,0.0363523,mode2,8,0.90,dsp,42837.885,2.0
+2.44,WireAreaLowkAgr,0.029614,mode3,8,0.90,dsp,40707.072,2.5
+1.96,WireAreaLowkAgr,0.0375534,mode1,5,0.90,dsp,45358.020,2.0
+1.97,WireAreaLowkAgr,0.0363483,mode2,7,0.90,dsp,42837.885,2.0
+1.81,WireAreaLowkAgr,0.0419168,mode3,5,0.90,dsp,45627.003,1.81
+1.52,WireAreaLowkAgr,0.0512255,mode3,5,0.90,dsp,54244.242,1.53
+1.99,WireAreaLowkAgr,0.0370469,none,6,0.95,dsp,40583.547,2.0
+1.6,WireAreaLowkAgr,0.0503564,none,5,0.95,dsp,51389.991,1.53
+2.48,WireAreaLowkAgr,0.029674,none,6,0.85,dsp,43101.540,2.5
+1.6,WireAreaLowkAgr,0.0503613,mode0,7,0.95,dsp,51389.991,1.53
+1.98,WireAreaLowkAgr,0.0370397,mode3,6,0.90,dsp,42837.885,2.0
+2.46,WireAreaLowkAgr,0.0291146,mode2,6,0.90,dsp,40707.072,2.5
+1.61,WireAreaLowkAgr,0.0502925,mode0,8,0.95,dsp,51389.991,1.53
+1.51,WireAreaLowkAgr,0.0505149,mode2,8,0.90,dsp,54244.242,1.53
+1.81,WireAreaLowkAgr,0.0409926,mode2,8,0.90,dsp,45627.003,1.81
+1.54,WireAreaLowkAgr,0.0504273,mode2,7,0.90,dsp,54244.242,1.53
+1.97,WireAreaLowkAgr,0.0374628,mode1,6,0.85,dsp,45358.020,2.0
+2.48,WireAreaLowkAgr,0.0291131,mode0,6,0.85,dsp,43101.540,2.5
+2.46,WireAreaLowkAgr,0.0303835,mode1,6,0.95,dsp,38565.072,2.5
+1.99,WireAreaLowkAgr,0.0363469,mode0,6,0.95,dsp,40583.547,2.0
+1.85,WireAreaLowkAgr,0.0412924,mode0,5,0.90,dsp,45627.003,1.81
+1.58,WireAreaLowkAgr,0.0504908,mode0,5,0.90,dsp,54244.242,1.53
+1.58,WireAreaLowkAgr,0.0502381,mode2,5,0.95,dsp,51389.991,1.53
+1.52,WireAreaLowkAgr,0.0517303,mode3,6,0.85,dsp,57436.848,1.53
+1.85,WireAreaLowkAgr,0.0410574,none,8,0.90,dsp,45627.003,1.81
+1.59,WireAreaLowkAgr,0.0506271,none,8,0.90,dsp,54244.242,1.53
+1.57,WireAreaLowkAgr,0.0505446,none,7,0.90,dsp,54244.242,1.53
+1.98,WireAreaLowkAgr,0.0371744,none,6,0.85,dsp,45358.020,2.0
+1.55,WireAreaLowkAgr,0.0512166,none,5,0.85,dsp,57436.848,1.53
+2.49,WireAreaLowkAgr,0.0301021,none,6,0.95,dsp,38565.072,2.5
+1.69,WireAreaLowkAgr,0.045987,none,5,0.90,dsp,48331.764,1.66
+1.98,WireAreaLowkAgr,0.0364487,mode2,6,0.90,dsp,42837.885,2.0
+2.43,WireAreaLowkAgr,0.0295903,mode3,6,0.90,dsp,40707.072,2.5
+1.55,WireAreaLowkAgr,0.0512508,mode0,8,0.85,dsp,57436.848,1.53
+1.55,WireAreaLowkAgr,0.0511243,mode0,7,0.85,dsp,57436.848,1.53
+2.17,WireAreaLowkAgr,0.0321567,mode2,5,0.90,dsp,41936.661,2.22
+1.71,WireAreaLowkAgr,0.0460939,mode0,8,0.90,dsp,48331.764,1.66
+2.49,WireAreaLowkAgr,0.0295837,mode0,6,0.95,dsp,38565.072,2.5
+1.98,WireAreaLowkAgr,0.037355,mode1,6,0.95,dsp,40583.547,2.0
+1.98,WireAreaLowkAgr,0.036455,mode0,6,0.85,dsp,45358.020,2.0
+1.64,WireAreaLowkAgr,0.0458925,mode2,5,0.90,dsp,48331.764,1.66
+1.55,WireAreaLowkAgr,0.0517896,mode1,6,0.90,dsp,54244.242,1.53
+2.45,WireAreaLowkAgr,0.0298967,mode1,6,0.85,dsp,43101.540,2.5
+1.56,WireAreaLowkAgr,0.0511442,mode3,6,0.95,dsp,51389.991,1.53
+2.19,WireAreaLowkAgr,0.0321895,mode0,8,0.90,dsp,41936.661,2.22
+1.51,WireAreaLowkAgr,0.0510716,mode2,5,0.85,dsp,57436.848,1.53
+2.2,WireAreaLowkAgr,0.0328243,none,5,0.90,dsp,41936.661,2.22
+2.46,WireAreaLowkAgr,0.0303981,mode1,8,0.95,dsp,38565.072,2.5
+1.99,WireAreaLowkAgr,0.0363567,mode0,7,0.95,dsp,40583.547,2.0
+1.97,WireAreaLowkAgr,0.0369377,mode3,5,0.95,dsp,40583.547,2.0
+2.48,WireAreaLowkAgr,0.0303957,mode1,7,0.95,dsp,38565.072,2.5
+1.65,WireAreaLowkAgr,0.0467966,mode3,8,0.90,dsp,48331.764,1.66
+2.4,WireAreaLowkAgr,0.0297153,mode2,5,0.95,dsp,38565.072,2.5
+1.99,WireAreaLowkAgr,0.036357,mode0,8,0.95,dsp,40583.547,2.0
+2.47,WireAreaLowkAgr,0.0291263,mode0,7,0.85,dsp,43101.540,2.5
+2.41,WireAreaLowkAgr,0.0295738,mode3,5,0.85,dsp,43101.540,2.5
+1.96,WireAreaLowkAgr,0.0375062,mode1,8,0.85,dsp,45358.020,2.0
+2.49,WireAreaLowkAgr,0.0290775,mode0,8,0.85,dsp,43101.540,2.5
+1.93,WireAreaLowkAgr,0.0375269,mode1,7,0.85,dsp,45358.020,2.0
+1.96,WireAreaLowkAgr,0.0365478,mode2,5,0.85,dsp,45358.020,2.0
+2.17,WireAreaLowkAgr,0.0330415,mode1,5,0.90,dsp,41936.661,2.22
+1.5,WireAreaLowkAgr,0.0517252,mode3,7,0.85,dsp,57436.848,1.53
+1.51,WireAreaLowkAgr,0.0518918,mode3,8,0.85,dsp,57436.848,1.53
+1.59,WireAreaLowkAgr,0.0505731,none,6,0.90,dsp,54244.242,1.53
+2.0,WireAreaLowkAgr,0.0373043,none,5,0.90,dsp,45358.020,2.0
+2.49,WireAreaLowkAgr,0.0296377,none,8,0.85,dsp,43101.540,2.5
+2.47,WireAreaLowkAgr,0.0296868,none,7,0.85,dsp,43101.540,2.5
+1.99,WireAreaLowkAgr,0.0370461,none,8,0.95,dsp,40583.547,2.0
+1.99,WireAreaLowkAgr,0.0370532,none,7,0.95,dsp,40583.547,2.0
+1.94,WireAreaLowkAgr,0.0369404,mode3,8,0.90,dsp,42837.885,2.0
+2.45,WireAreaLowkAgr,0.0299703,mode1,5,0.90,dsp,40707.072,2.5
+1.5,WireAreaLowkAgr,0.0524305,mode1,5,0.85,dsp,57436.848,1.53
+2.46,WireAreaLowkAgr,0.029159,mode2,7,0.90,dsp,40707.072,2.5
+2.0,WireAreaLowkAgr,0.0365472,mode0,5,0.90,dsp,45358.020,2.0
+1.97,WireAreaLowkAgr,0.0369374,mode3,7,0.90,dsp,42837.885,2.0
+2.17,WireAreaLowkAgr,0.0327108,mode3,8,0.90,dsp,41936.661,2.22
+1.6,WireAreaLowkAgr,0.0503668,mode0,6,0.95,dsp,51389.991,1.53
+2.48,WireAreaLowkAgr,0.0291368,mode2,8,0.90,dsp,40707.072,2.5
+1.63,WireAreaLowkAgr,0.0470838,mode1,5,0.90,dsp,48331.764,1.66
+1.54,WireAreaLowkAgr,0.0504489,mode2,6,0.90,dsp,54244.242,1.53
+1.61,WireAreaLowkAgr,0.0503802,none,8,0.95,dsp,51389.991,1.53
+1.6,WireAreaLowkAgr,0.0504482,none,7,0.95,dsp,51389.991,1.53
+1.81,WireAreaLowkAgr,0.0412662,mode2,5,0.90,dsp,45627.003,1.81
+1.52,WireAreaLowkAgr,0.0504615,mode2,5,0.90,dsp,54244.242,1.53
+1.51,WireAreaLowkAgr,0.0523058,mode1,6,0.85,dsp,57436.848,1.53
+2.43,WireAreaLowkAgr,0.0299144,mode1,6,0.90,dsp,40707.072,2.5
+1.99,WireAreaLowkAgr,0.0364457,mode0,6,0.90,dsp,42837.885,2.0
+1.6,WireAreaLowkAgr,0.0502463,mode0,5,0.95,dsp,51389.991,1.53
+1.54,WireAreaLowkAgr,0.0502788,mode2,8,0.95,dsp,51389.991,1.53
+1.56,WireAreaLowkAgr,0.0503458,mode2,7,0.95,dsp,51389.991,1.53
+1.57,WireAreaLowkAgr,0.0504502,mode0,7,0.90,dsp,54244.242,1.53
+1.98,WireAreaLowkAgr,0.0369409,mode3,6,0.95,dsp,40583.547,2.0
+1.59,WireAreaLowkAgr,0.0505485,mode0,8,0.90,dsp,54244.242,1.53
+2.49,WireAreaLowkAgr,0.029579,mode2,6,0.95,dsp,38565.072,2.5
+1.85,WireAreaLowkAgr,0.0410243,mode0,8,0.90,dsp,45627.003,1.81
+2.45,WireAreaLowkAgr,0.0295732,mode3,6,0.85,dsp,43101.540,2.5
+1.98,WireAreaLowkAgr,0.0364537,mode2,6,0.85,dsp,45358.020,2.0
+1.58,WireAreaLowkAgr,0.0505759,none,5,0.90,dsp,54244.242,1.53
+1.85,WireAreaLowkAgr,0.0413302,none,5,0.90,dsp,45627.003,1.81
+1.99,WireAreaLowkAgr,0.0371539,none,6,0.90,dsp,42837.885,2.0
+1.58,WireAreaLowkAgr,0.0510244,mode3,5,0.95,dsp,51389.991,1.53
+1.52,WireAreaLowkAgr,0.0509735,mode2,6,0.85,dsp,57436.848,1.53
+2.48,WireAreaLowkAgr,0.0300661,mode3,7,0.95,dsp,38565.072,2.5
+2.48,WireAreaLowkAgr,0.0297115,mode0,5,0.95,dsp,38565.072,2.5
+1.97,WireAreaLowkAgr,0.0363503,mode2,8,0.95,dsp,40583.547,2.0
+2.46,WireAreaLowkAgr,0.0300664,mode3,8,0.95,dsp,38565.072,2.5
+1.97,WireAreaLowkAgr,0.0363542,mode2,7,0.95,dsp,40583.547,2.0
+1.97,WireAreaLowkAgr,0.0373457,mode1,5,0.95,dsp,40583.547,2.0
+2.48,WireAreaLowkAgr,0.0290715,mode2,8,0.85,dsp,43101.540,2.5
+1.93,WireAreaLowkAgr,0.0371141,mode3,7,0.85,dsp,45358.020,2.0
+2.0,WireAreaLowkAgr,0.0365472,mode0,5,0.85,dsp,45358.020,2.0
+1.79,WireAreaLowkAgr,0.0423824,mode1,5,0.90,dsp,45627.003,1.81
+2.47,WireAreaLowkAgr,0.0291169,mode2,7,0.85,dsp,43101.540,2.5
+2.41,WireAreaLowkAgr,0.0299025,mode1,5,0.85,dsp,43101.540,2.5
+1.55,WireAreaLowkAgr,0.0518046,mode1,5,0.90,dsp,54244.242,1.53
+1.96,WireAreaLowkAgr,0.0370939,mode3,8,0.85,dsp,45358.020,2.0
+2.49,WireAreaLowkAgr,0.0297566,none,7,0.90,dsp,40707.072,2.5
+2.49,WireAreaLowkAgr,0.0297386,none,8,0.90,dsp,40707.072,2.5
+2.0,WireAreaLowkAgr,0.0373043,none,5,0.85,dsp,45358.020,2.0
+1.55,WireAreaLowkAgr,0.0511177,none,6,0.85,dsp,57436.848,1.53
+2.48,WireAreaLowkAgr,0.030242,none,5,0.95,dsp,38565.072,2.5
+1.51,WireAreaLowkAgr,0.0512787,mode3,8,0.90,dsp,54244.242,1.53
+1.81,WireAreaLowkAgr,0.0416461,mode3,8,0.90,dsp,45627.003,1.81
+1.54,WireAreaLowkAgr,0.0511857,mode3,7,0.90,dsp,54244.242,1.53
+1.96,WireAreaLowkAgr,0.0365478,mode2,5,0.90,dsp,45358.020,2.0
+1.97,WireAreaLowkAgr,0.0373471,mode1,7,0.90,dsp,42837.885,2.0
+2.49,WireAreaLowkAgr,0.0291461,mode0,8,0.90,dsp,40707.072,2.5
+1.94,WireAreaLowkAgr,0.0373501,mode1,8,0.90,dsp,42837.885,2.0
+2.45,WireAreaLowkAgr,0.0296446,mode3,5,0.90,dsp,40707.072,2.5
+2.49,WireAreaLowkAgr,0.029166,mode0,7,0.90,dsp,40707.072,2.5
+1.57,WireAreaLowkAgr,0.0517309,mode1,7,0.95,dsp,51389.991,1.53
+1.57,WireAreaLowkAgr,0.0516606,mode1,8,0.95,dsp,51389.991,1.53
+2.17,WireAreaLowkAgr,0.0330662,mode1,8,0.90,dsp,41936.661,2.22
+1.56,WireAreaLowkAgr,0.0503494,mode2,6,0.95,dsp,51389.991,1.53
+1.51,WireAreaLowkAgr,0.0518349,mode3,5,0.85,dsp,57436.848,1.53
+1.97,WireAreaLowkAgr,0.0365183,mode2,7,0.85,dsp,45358.020,2.0
+1.96,WireAreaLowkAgr,0.0375534,mode1,5,0.85,dsp,45358.020,2.0
+2.43,WireAreaLowkAgr,0.0295375,mode3,8,0.85,dsp,43101.540,2.5
+1.96,WireAreaLowkAgr,0.0364995,mode2,8,0.85,dsp,45358.020,2.0
+2.43,WireAreaLowkAgr,0.0295862,mode3,7,0.85,dsp,43101.540,2.5
+2.48,WireAreaLowkAgr,0.0291135,mode0,5,0.85,dsp,43101.540,2.5
+1.95,WireAreaLowkAgr,0.0369466,mode3,8,0.95,dsp,40583.547,2.0
+2.48,WireAreaLowkAgr,0.0295886,mode2,7,0.95,dsp,38565.072,2.5
+2.4,WireAreaLowkAgr,0.0305283,mode1,5,0.95,dsp,38565.072,2.5
+1.96,WireAreaLowkAgr,0.0369503,mode3,7,0.95,dsp,40583.547,2.0
+1.99,WireAreaLowkAgr,0.0363429,mode0,5,0.95,dsp,40583.547,2.0
+2.49,WireAreaLowkAgr,0.0295873,mode2,8,0.95,dsp,38565.072,2.5
+1.64,WireAreaLowkAgr,0.0466126,mode3,5,0.90,dsp,48331.764,1.66
+1.59,WireAreaLowkAgr,0.0504824,mode0,6,0.90,dsp,54244.242,1.53
+1.97,WireAreaLowkAgr,0.0370519,none,8,0.90,dsp,42837.885,2.0
+1.98,WireAreaLowkAgr,0.0370479,none,7,0.90,dsp,42837.885,2.0
+1.99,WireAreaLowkAgr,0.0370372,none,5,0.95,dsp,40583.547,2.0
+1.6,WireAreaLowkAgr,0.0504607,none,6,0.95,dsp,51389.991,1.53
+2.48,WireAreaLowkAgr,0.0296881,none,5,0.85,dsp,43101.540,2.5
+1.66,WireAreaLowkAgr,0.0472617,mode1,8,0.90,dsp,48331.764,1.66
+1.52,WireAreaLowkAgr,0.0524762,mode1,8,0.85,dsp,57436.848,1.53
+2.44,WireAreaLowkAgr,0.0299422,mode1,8,0.90,dsp,40707.072,2.5
+1.96,WireAreaLowkAgr,0.0371464,mode3,5,0.90,dsp,45358.020,2.0
+1.98,WireAreaLowkAgr,0.0363501,mode0,7,0.90,dsp,42837.885,2.0
+2.47,WireAreaLowkAgr,0.0291681,mode2,5,0.90,dsp,40707.072,2.5
+2.44,WireAreaLowkAgr,0.0299586,mode1,7,0.90,dsp,40707.072,2.5
+2.17,WireAreaLowkAgr,0.0326891,mode3,5,0.90,dsp,41936.661,2.22
+1.51,WireAreaLowkAgr,0.0523326,mode1,7,0.85,dsp,57436.848,1.53
+1.97,WireAreaLowkAgr,0.0363608,mode0,8,0.90,dsp,42837.885,2.0
+1.71,WireAreaLowkAgr,0.0461666,none,8,0.90,dsp,48331.764,1.66
+1.55,WireAreaLowkAgr,0.0510625,none,7,0.85,dsp,57436.848,1.53
+1.55,WireAreaLowkAgr,0.0512834,none,8,0.85,dsp,57436.848,1.53
+1.69,WireAreaLowkAgr,0.0459201,mode0,5,0.90,dsp,48331.764,1.66
+1.54,WireAreaLowkAgr,0.0512172,mode3,6,0.90,dsp,54244.242,1.53
+1.55,WireAreaLowkAgr,0.0512399,mode0,5,0.85,dsp,57436.848,1.53
+1.57,WireAreaLowkAgr,0.0517429,mode1,6,0.95,dsp,51389.991,1.53
+2.17,WireAreaLowkAgr,0.03218,mode2,8,0.90,dsp,41936.661,2.22
+2.48,WireAreaLowkAgr,0.0291217,mode0,6,0.90,dsp,40707.072,2.5
+1.98,WireAreaLowkAgr,0.0374454,mode1,6,0.90,dsp,42837.885,2.0
+1.5,WireAreaLowkAgr,0.0509715,mode2,7,0.85,dsp,57436.848,1.53
+2.2,WireAreaLowkAgr,0.032165,mode0,5,0.90,dsp,41936.661,2.22
+1.51,WireAreaLowkAgr,0.051133,mode2,8,0.85,dsp,57436.848,1.53
+2.48,WireAreaLowkAgr,0.0291045,mode2,6,0.85,dsp,43101.540,2.5
+1.97,WireAreaLowkAgr,0.0370525,mode3,6,0.85,dsp,45358.020,2.0
+1.65,WireAreaLowkAgr,0.0460727,mode2,8,0.90,dsp,48331.764,1.66
+1.98,WireAreaLowkAgr,0.0363406,mode2,6,0.95,dsp,40583.547,2.0
+2.46,WireAreaLowkAgr,0.0300588,mode3,6,0.95,dsp,38565.072,2.5
+2.19,WireAreaLowkAgr,0.0328403,none,8,0.90,dsp,41936.661,2.22
+2.48,WireAreaLowkAgr,0.0297067,none,6,0.90,dsp,40707.072,2.5
diff --git a/analyze_results/results_archive/fig_archives/area_fig.png b/analyze_results/results_archive/fig_archives/area_fig.png
new file mode 100644
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diff --git a/analyze_results/results_archive/final_full_custom_flow_report.txt b/analyze_results/results_archive/final_full_custom_flow_report.txt
new file mode 100644
index 0000000..d7e4065
--- /dev/null
+++ b/analyze_results/results_archive/final_full_custom_flow_report.txt
@@ -0,0 +1,220 @@
+Created 2022-10-12 23:43:42.670014
+
+----------------------------------------------
+  RUN OPTIONS:
+----------------------------------------------
+
+  Transistor sizing: on
+  Optimization type: global
+  Number of top combos to re-ERF: 1
+  Area optimization weight: 1
+  Delay optimization weight: 1
+  Maximum number of sizing iterations: 1
+
+
+-------------------------------------------------
+  ARCHITECTURE PARAMETERS:
+-------------------------------------------------
+
+  Number of BLEs per cluster (N): 10
+  LUT size (K): 6
+  Channel width (W): 320
+  Wire segment length (L): 4
+  Number of cluster inputs (I): 40
+  Number of BLE outputs to general routing (Or): 2
+  Number of BLE outputs to local routing (Ofb): 1
+  Total number of cluster outputs (N*Or): 20
+  Switch block flexibility (Fs): 3
+  Cluster input flexibility (Fcin): 0.2
+  Cluster output flexibility (Fcout): 0.025
+  Local MUX population (Fclocal): 0.5
+  LUT input for register selection MUX (Rsel): c
+  LUT input(s) for register feedback MUX(es) (Rfb): c
+
+-------------------------------------------------
+  PROCESS TECHNOLOGY PARAMETERS:
+-------------------------------------------------
+
+  transistor_type = bulk
+  switch_type = pass_transistor
+  vdd = 0.8
+  vsram = 1.0
+  vsram_n = 0.0
+  gate_length = 22
+  min_tran_width = 45
+  min_width_tran_area = 33864
+  sram_cell_area = 4.0
+  model_path = /autofs/fs1.ece/fs1.eecg.vaughn/morestep/COFFE/spice_models/ptm_22nm_bulk_hp.l
+  model_library = 22NM_BULK_HP
+  metal = [(0.054825, 0.000175), (0.007862, 0.000215), (0.02924, 0.000139), (0.227273, 0.0)]
+
+
+|------------------------------------------------------------------------------|
+|   FPGA Implementation Details                                                |
+|------------------------------------------------------------------------------|
+
+  SWITCH BLOCK DETAILS:
+  Style: two-level MUX
+  Required MUX size: 10:1
+  Implemented MUX size: 12:1
+  Level 1 size = 4
+  Level 2 size = 3
+  Number of unused inputs = 2
+  Number of MUXes per tile: 160
+  Number of SRAM cells per MUX: 7
+
+  CONNECTION BLOCK DETAILS:
+  Style: two-level MUX
+  Required MUX size: 64:1
+  Implemented MUX size: 64:1
+  Level 1 size = 8
+  Level 2 size = 8
+  Number of unused inputs = 0
+  Number of MUXes per tile: 40
+  Number of SRAM cells per MUX: 16
+
+  LOCAL MUX DETAILS:
+  Style: two-level MUX
+  Required MUX size: 25:1
+  Implemented MUX size: 25:1
+  Level 1 size = 5
+  Level 2 size = 5
+  Number of unused inputs = 0
+  Number of MUXes per tile: 60
+  Number of SRAM cells per MUX: 10
+
+  LUT DETAILS:
+  Style: Fully encoded MUX tree
+  Size: 6-LUT
+  Internal buffering: 2-stage buffer betweens levels 3 and 4
+  Isolation inverters between SRAM and LUT inputs
+
+  LUT INPUT DRIVER DETAILS:
+  LUT input a type: default
+  LUT input c type: reg_fb_rsel
+  LUT input b type: default
+  LUT input e type: default
+  LUT input d type: default
+  LUT input f type: default
+
+  CLUSTER OUTPUT LOAD DETAILS:
+  Total number of SB inputs connected to cluster output: 8
+  Number of 'on' SB MUXes (assumed): 1
+  Number of 'partial' SB MUXes: 1
+  Number of 'off' SB MUXes: 6
+
+  ROUTING WIRE LOAD DETAILS:
+  Number of SB inputs connected to routing wire = 9
+  Wire: SB (on = 1, partial = 1, off = 7)
+  Number of CB inputs connected to routing wire = 16
+  Wire: CB (on = 1, partial = 1, off = 14)
+  Tile 1: SB (on = 1, partial = 1, off = 1); CB (on = 1, partial = 1, off = 2)
+  Tile 2: SB (on = 0, partial = 0, off = 2); CB (on = 0, partial = 0, off = 4)
+  Tile 3: SB (on = 0, partial = 0, off = 2); CB (on = 0, partial = 0, off = 4)
+  Tile 4: SB (on = 0, partial = 0, off = 2); CB (on = 0, partial = 0, off = 4)
+
+  DETAILS OF HARD BLOCK: hard_block
+  Localmux:
+  Style: two-level MUX
+  Required MUX size: 144:1
+  Implemented MUX size: 144:1
+  Level 1 size = 12
+  Level 2 size = 12
+  Number of unused inputs = 0
+  Number of MUXes per tile: 288
+  Number of SRAM cells per MUX: 24
+
+|------------------------------------------------------------------------------|
+
+
+|--------------------------------------------------------------------------------------------------|
+|    Area and Delay Report                                                                         |
+|--------------------------------------------------------------------------------------------------|
+
+  SUBCIRCUIT AREA, DELAY & POWER
+  ------------------------------
+  Subcircuit                    Area (um^2)  Delay (ps)   tfall (ps)   trise (ps)   Power at 250MHz (uW)  
+  sb_mux                        1.522        189.1        186.8        189.1        25.55                 
+  sb_mux(with sram)             2.47         189.1        186.8        189.1        25.55                 
+  cb_mux                        2.702        174.0        174.0        167.4        3.443
+  cb_mux(with sram)             4.869        174.0        174.0        167.4        3.443
+  local_mux                     1.155        57.59        57.59        56.45        0.336
+  local_mux(with sram)          2.51         57.59        57.59        56.45        0.336
+  local_ble_output(with sram)   0.748        155.6        155.6        121.5        2.625
+  general_ble_output(with sram) 0.559        30.19        30.19        30.05        1.086
+  ff                            1.228        n/a          n/a          n/a          n/a
+  lut (with sram)               28.576       160.8        160.8        160.4        n/a                   
+  lut_a                         n/a          445.9        445.9        132.5        2.642                 
+  lut_a_driver                  0.341        14.79        14.79        13.81        0.7863                
+  lut_a_driver_not              0.398        24.39        23.07        24.39        0.7834                
+  lut_b                         n/a          443.0        443.0        129.9        2.603                 
+  lut_b_driver                  0.311        13.84        13.84        13.83        0.5785                
+  lut_b_driver_not              0.385        23.05        21.41        23.05        0.6214                
+  lut_c                         n/a          439.5        439.5        119.3        2.573                 
+  lut_c_driver                  0.791        32.52        32.52        32.15        1.129                 
+  lut_c_driver_not              0.297        39.13        38.5         39.13        0.5226                
+  lut_d                         n/a          272.6        272.6        77.11        1.841                 
+  lut_d_driver                  0.191        16.62        16.62        15.77        0.4516                
+  lut_d_driver_not              0.27         24.92        22.14        24.92        0.504                 
+  lut_e                         n/a          272.3        272.3        72.45        1.734                 
+  lut_e_driver                  0.148        18.09        18.09        17.73        0.4111                
+  lut_e_driver_not              0.213        28.5         24.69        28.5         0.4716                
+  lut_f                         n/a          264.1        264.1        57.47        1.625                 
+  lut_f_driver                  0.163        13.63        13.63        12.58        0.3934                
+  lut_f_driver_not              0.238        23.22        20.36        23.22        0.464                 
+  hard_block mux              10.199       200.6        114.1        200.6        3.707                 
+
+
+  TILE AREA CONTRIBUTIONS
+  -----------------------
+  Block             Total Area (um^2)   Fraction of total tile area
+  Tile              1094.718            100%
+  LUT               323.236             29.527%
+  FF                12.275              1.121%
+  BLE output        18.649              1.704%
+  Local mux         150.578             13.755%
+  Connection block  194.765             17.791%
+  Switch block      395.214             36.102%
+
+  HARDBLOCK INFORMATION
+  ---------------------
+  Name: hard_block
+  Core area: 5358.42216
+  Local mux area: 2001.0290619
+  Local mux area with sram: 2937.3009339
+  Total area: 8295.7230939
+
+  VPR DELAYS
+  ----------
+  Path                                            Delay (ps)
+  Tdel (routing switch)                           1.891e-10
+  T_ipin_cblock (connection block mux)            1.74e-10
+  CLB input -> BLE input (local CLB routing)      5.759e-11
+  LUT output -> BLE input (local feedback)        1.556e-10
+  LUT output -> CLB output (logic block output)   3.019e-11
+  lut_a                                           4.7029e-10
+  lut_b                                           4.6605e-10
+  lut_c                                           4.7863e-10
+  lut_d                                           2.9752e-10
+  lut_e                                           3.008e-10
+  lut_f                                           2.8732e-10
+
+  VPR AREAS
+  ----------
+  grid_logic_tile_area                            14904.8765232
+  ipin_mux_trans_size (connection block mux)      0.966
+  mux_trans_size (routing switch)                 1.50823186576
+  buf_size (routing switch)                       21.6196626435
+
+  SUMMARY
+  -------
+  Tile Area                            1094.72 um^2
+  Representative Critical Path Delay   224.6 ps
+  Cost (area^1 x delay^1)              0.24588
+
+|--------------------------------------------------------------------------------------------------|
+
+Number of HSPICE simulations performed: 73322
+Total time elapsed: 4 hours 7 minutes 2 seconds
+
+