About employing diffusion sharing for multi-input gates like nand2 nor2.

[yc2367]

Hi,

I am currently using COFFE to run simulations for a modified BRAM and I am using many nand gates, nor gates, sense amplifiers and write drivers as in Aman's CoMeFa paper.
But I wonder if the current COFFE's transistor area model can correctly capture the diffusion sharing (similar to fingering) for multi-input gates. For example, in a nand2 gate, the 2 pmos can share their source (or drain) since they are connected in parallel. In this case, if we make all pmos/nmos minimum-width, the correct minimum-width transistor area for this nand2 should be smaller than 4 due to diffusion sharing, and this sharing can actually reduce the area a lot.

Source: https://pages.cs.wisc.edu/~david/courses/cs755/cs755/tutorials2002/tut4/diffandfold.html

Best regards,
Yuzong

[vaughnbetz]

COFFE does take that multi-fingering into account for its area model, but doesn't take diffusion sharing in stacks of transistors into account. See Section IV of this paper: https://www.eecg.utoronto.ca/~vaughn/papers/fpt2013_coffe.pdf

In practice, there are various inefficiencies in trying to wire up different transistors that mean assuming you can perfectly pack small transistors is optimistic. So we left in the pessimism of assuming independent transistors didn't share a diffusion to balance out where we are pessimistic and where we are optimistic. You are correct that some structures will pack better than others; a more sophisticated area model could try to account for that by giving different areas based on transistor topology. It may be challenging to get more accurate results that way though (or at least a lot of work to create the models) as I think you'd have to carefully create sample layouts for various types of gates/transistors and pick the closest one for each structure.