About the meaning of crit_path_delay

[luck-codeer]

Hello, Professor Betz. Thank you for your previous reply. This time, I would like to ask if the critical path delay in COFFE is different from that in VTR, and what the reason is for the absence of wire delay within channels in COFFE. Is it correct to understand that the critical path delay in COFFE is solely designed to optimize the transistors within a tile, and it does not provide any guidance or reflect the actual critical path delay of a specific circuit? The connection between the two approaches lies in the fact that the delay weights of various module components in COFFE are determined based on the probabilities obtained from a series of actual benchmarks. Am I understanding this correctly? Or is there another understanding?

[vaughnbetz]

Yes, that is exactly correct. The representative critical path delay given to COFFE just lets it properly weigh the delay impact of various sub-circuits. It is an approximation; the idea is that the representative critical path is extracted from CAD tool runs in the relevant (or a similar) architecture. A default one is given in COFFE, and can be changed to weight different components differently. For the other question: wire delay is aggregated into the delay of the driving element (routing switch, LUT output, etc.). Wire lengths are estimated and the R and C taken into account, but the end delay is simply added together with the transistor delays and output as the delay of the relevant element (e.g. L4 wire, LUT, etc.).

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On Thu, Jul 20, 2023 at 10:48 AM luck-codeer ***@***.***> wrote: Hello, Professor Betz. Thank you for your previous reply. This time, I would like to ask if the critical path delay in COFFE is different from that in VTR, and what the reason is for the absence of wire delay within channels in COFFE. Is it correct to understand that the critical path delay in COFFE is solely designed to optimize the transistors within a tile, and it does not provide any guidance or reflect the actual critical path delay of a specific circuit? The connection between the two approaches lies in the fact that the delay weights of various module components in COFFE are determined based on the probabilities obtained from a series of actual benchmarks. Am I understanding this correctly? Or is there another understanding? — Reply to this email directly, view it on GitHub <#51>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABNDPJ7OQR442KMVC7XRRLLXRFAKTANCNFSM6AAAAAA2RRQ23U> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>