diff --git a/designs/black-parrot/LICENSE b/designs/black-parrot/LICENSE new file mode 100644 index 0000000..9b3db23 --- /dev/null +++ b/designs/black-parrot/LICENSE @@ -0,0 +1,24 @@ +Copyright (c) 2019, University of Washington +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the University of Washington nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL UNIVERSITY OF WASHINGTON BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/designs/black-parrot/descriptor.yaml b/designs/black-parrot/descriptor.yaml new file mode 100644 index 0000000..aa24772 --- /dev/null +++ b/designs/black-parrot/descriptor.yaml @@ -0,0 +1,432 @@ +origin: + - repository: https://github.com/black-parrot/black-parrot.git + revision: 45a28bf96e58f55687f8e09b2521ceada121ad95 + licenses: + - LICENSE + +compile: + verilogSourceFiles: + # Packages + # Basejump Packages + - src/basejump_stl/bsg_axi_pkg.sv + - src/basejump_stl/bsg_cache_pkg.sv + - src/basejump_stl/bsg_noc_pkg.sv + - src/basejump_stl/bsg_wormhole_router_pkg.sv + # BP Packages + - src/bp/bp_common_pkg.sv + - src/bp/bp_be_pkg.sv + - src/bp/bp_fe_pkg.sv + - src/bp/bp_me_pkg.sv + - src/bp/bp_top_pkg.sv + # Basejump RTL + - src/basejump_stl/bsg_async_fifo.sv + - src/basejump_stl/bsg_launch_sync_sync.sv + - src/basejump_stl/bsg_sync_sync.sv + - src/basejump_stl/bsg_async_ptr_gray.sv + - src/basejump_stl/bsg_cache.sv + - src/basejump_stl/bsg_cache_dma.sv + - src/basejump_stl/bsg_cache_dma_to_wormhole.sv + - src/basejump_stl/bsg_cache_miss.sv + - src/basejump_stl/bsg_cache_decode.sv + - src/basejump_stl/bsg_cache_sbuf.sv + - src/basejump_stl/bsg_cache_tbuf.sv + - src/basejump_stl/bsg_cache_buffer_queue.sv + - src/basejump_stl/bsg_wormhole_to_cache_dma_fanout.sv + - src/basejump_stl/bsg_channel_tunnel.sv + - src/basejump_stl/bsg_channel_tunnel_in.sv + - src/basejump_stl/bsg_channel_tunnel_out.sv + - src/basejump_stl/bsg_1_to_n_tagged_fifo.sv + - src/basejump_stl/bsg_1_to_n_tagged.sv + - src/basejump_stl/bsg_fifo_1r1w_large.sv + - src/basejump_stl/bsg_fifo_1r1w_pseudo_large.sv + - src/basejump_stl/bsg_fifo_1r1w_small.sv + - src/basejump_stl/bsg_fifo_1r1w_small_unhardened.sv + - src/basejump_stl/bsg_fifo_1rw_large.sv + - src/basejump_stl/bsg_fifo_tracker.sv + - src/basejump_stl/bsg_flow_counter.sv + - src/basejump_stl/bsg_one_fifo.sv + - src/basejump_stl/bsg_parallel_in_serial_out.sv + - src/basejump_stl/bsg_parallel_in_serial_out_dynamic.sv + - src/basejump_stl/bsg_parallel_in_serial_out_passthrough.sv + - src/bp/bsg_parallel_in_serial_out_passthrough_dynamic.sv + - src/bp/bsg_serial_in_parallel_out_passthrough_dynamic.sv + - src/basejump_stl/bsg_round_robin_1_to_n.sv + - src/basejump_stl/bsg_round_robin_2_to_2.sv + - src/basejump_stl/bsg_round_robin_n_to_1.sv + - src/basejump_stl/bsg_serial_in_parallel_out.sv + - src/basejump_stl/bsg_serial_in_parallel_out_dynamic.sv + - src/basejump_stl/bsg_serial_in_parallel_out_full.sv + - src/basejump_stl/bsg_serial_in_parallel_out_passthrough.sv + - src/basejump_stl/bsg_shift_reg.sv + - src/basejump_stl/bsg_two_fifo.sv + - src/basejump_stl/bsg_cam_1r1w_replacement.sv + - src/basejump_stl/bsg_cam_1r1w_sync.sv + - src/basejump_stl/bsg_cam_1r1w_tag_array.sv + - src/basejump_stl/bsg_mem_1r1w.sv + - src/basejump_stl/bsg_mem_1r1w_one_hot.sv + - src/basejump_stl/bsg_mem_1r1w_sync_synth.sv + - src/basejump_stl/bsg_mem_1r1w_sync.sv + - src/basejump_stl/bsg_mem_1r1w_synth.sv + - src/basejump_stl/bsg_mem_1rw_sync.sv + - src/basejump_stl/bsg_mem_1rw_sync_mask_write_bit.sv + - src/basejump_stl/bsg_mem_1rw_sync_mask_write_bit_synth.sv + - src/basejump_stl/bsg_mem_1rw_sync_mask_write_byte.sv + - src/basejump_stl/bsg_mem_1rw_sync_mask_write_byte_synth.sv + - src/basejump_stl/bsg_mem_1rw_sync_synth.sv + - src/basejump_stl/bsg_mem_2r1w_sync.sv + - src/basejump_stl/bsg_mem_2r1w_sync_synth.sv + - src/basejump_stl/bsg_mem_3r1w_sync.sv + - src/basejump_stl/bsg_mem_3r1w_sync_synth.sv + - src/basejump_stl/bsg_adder_cin.sv + - src/basejump_stl/bsg_adder_one_hot.sv + - src/basejump_stl/bsg_adder_ripple_carry.sv + - src/basejump_stl/bsg_arb_fixed.sv + - src/basejump_stl/bsg_arb_round_robin.sv + - src/basejump_stl/bsg_array_concentrate_static.sv + - src/basejump_stl/bsg_buf.sv + - src/basejump_stl/bsg_buf_ctrl.sv + - src/basejump_stl/bsg_circular_ptr.sv + - src/basejump_stl/bsg_concentrate_static.sv + - src/basejump_stl/bsg_counting_leading_zeros.sv + - src/basejump_stl/bsg_counter_clear_up.sv + - src/basejump_stl/bsg_counter_clear_up_one_hot.sv + - src/basejump_stl/bsg_counter_clock_downsample.sv + - src/basejump_stl/bsg_counter_set_down.sv + - src/basejump_stl/bsg_counter_set_en.sv + - src/basejump_stl/bsg_counter_up_down.sv + - src/basejump_stl/bsg_counter_up_down_variable.sv + - src/basejump_stl/bsg_crossbar_o_by_i.sv + - src/basejump_stl/bsg_crossbar_control_locking_o_by_i.sv + - src/basejump_stl/bsg_cycle_counter.sv + - src/basejump_stl/bsg_decode.sv + - src/basejump_stl/bsg_decode_with_v.sv + - src/basejump_stl/bsg_dff.sv + - src/basejump_stl/bsg_dff_chain.sv + - src/basejump_stl/bsg_dff_en.sv + - src/basejump_stl/bsg_dff_en_bypass.sv + - src/basejump_stl/bsg_dff_reset.sv + - src/basejump_stl/bsg_dff_reset_en.sv + - src/basejump_stl/bsg_dff_reset_en_bypass.sv + - src/basejump_stl/bsg_dff_reset_set_clear.sv + - src/basejump_stl/bsg_dlatch.sv + - src/basejump_stl/bsg_edge_detect.sv + - src/basejump_stl/bsg_encode_one_hot.sv + - src/basejump_stl/bsg_expand_bitmask.sv + - src/basejump_stl/bsg_gray_to_binary.sv + - src/basejump_stl/bsg_hash_bank.sv + - src/basejump_stl/bsg_hash_bank_reverse.sv + - src/basejump_stl/bsg_imul_iterative.sv + - src/basejump_stl/bsg_idiv_iterative.sv + - src/basejump_stl/bsg_idiv_iterative_controller.sv + - src/basejump_stl/bsg_lfsr.sv + - src/basejump_stl/bsg_lru_pseudo_tree_backup.sv + - src/basejump_stl/bsg_lru_pseudo_tree_decode.sv + - src/basejump_stl/bsg_lru_pseudo_tree_encode.sv + - src/basejump_stl/bsg_locking_arb_fixed.sv + - src/basejump_stl/bsg_mul_add_unsigned.sv + - src/basejump_stl/bsg_mux.sv + - src/basejump_stl/bsg_mux_bitwise.sv + - src/basejump_stl/bsg_mux_butterfly.sv + - src/basejump_stl/bsg_mux_one_hot.sv + - src/basejump_stl/bsg_mux_segmented.sv + - src/basejump_stl/bsg_muxi2_gatestack.sv + - src/basejump_stl/bsg_nor2.sv + - src/basejump_stl/bsg_nor3.sv + - src/basejump_stl/bsg_nand.sv + - src/basejump_stl/bsg_popcount.sv + - src/basejump_stl/bsg_priority_encode.sv + - src/basejump_stl/bsg_priority_encode_one_hot_out.sv + - src/basejump_stl/bsg_reduce.sv + - src/basejump_stl/bsg_reduce_segmented.sv + - src/basejump_stl/bsg_rotate_left.sv + - src/basejump_stl/bsg_rotate_right.sv + - src/basejump_stl/bsg_round_robin_arb.sv + - src/basejump_stl/bsg_scan.sv + - src/basejump_stl/bsg_strobe.sv + - src/basejump_stl/bsg_swap.sv + - src/basejump_stl/bsg_thermometer_count.sv + - src/basejump_stl/bsg_transpose.sv + - src/basejump_stl/bsg_unconcentrate_static.sv + - src/basejump_stl/bsg_xnor.sv + - src/basejump_stl/bsg_mesh_stitch.sv + - src/basejump_stl/bsg_noc_repeater_node.sv + - src/basejump_stl/bsg_wormhole_concentrator.sv + - src/basejump_stl/bsg_wormhole_concentrator_in.sv + - src/basejump_stl/bsg_wormhole_concentrator_out.sv + - src/basejump_stl/bsg_wormhole_router.sv + - src/basejump_stl/bsg_wormhole_router_adapter_in.sv + - src/basejump_stl/bsg_wormhole_router_adapter_out.sv + - src/basejump_stl/bsg_wormhole_router_decoder_dor.sv + - src/basejump_stl/bsg_wormhole_router_input_control.sv + - src/basejump_stl/bsg_wormhole_router_output_control.sv + # HardFloat RTL + - src/hardfloat/compareRecFN.v + - src/hardfloat/divSqrtRecFN.v + - src/hardfloat/divSqrtRecFN_medium.v + - src/hardfloat/divSqrtRecFN_small.v + - src/hardfloat/fNToRecFN.v + - src/hardfloat/HardFloat_primitives.v + - src/hardfloat/HardFloat_rawFN.v + - src/hardfloat/iNToRecFN.v + - src/hardfloat/isSigNaNRecFN.v + - src/hardfloat/mulAddRecFN.v + - src/hardfloat/mulRecFN.v + - src/hardfloat/recFNToFN.v + - src/hardfloat/recFNToIN.v + - src/hardfloat/recFNToRecFN.v + - src/hardfloat/HardFloat_specialize.v + #BP Common Files + - src/bp/bsg_fifo_1r1w_rolly.sv + - src/bp/bsg_bus_pack.sv + - src/bp/bp_mmu.sv + - src/bp/bp_pma.sv + - src/bp/bp_tlb.sv + # BP RTL + - src/bp/bp_be_top.sv + - src/bp/bp_be_calculator_top.sv + - src/bp/bp_be_csr.sv + - src/bp/bp_be_fp_box.sv + - src/bp/bp_be_fp_rebox.sv + - src/bp/bp_be_fp_unbox.sv + - src/bp/bp_be_int_unbox.sv + - src/bp/bp_be_int_box.sv + - src/bp/bp_be_pipe_int.sv + - src/bp/bp_be_pipe_aux.sv + - src/bp/bp_be_pipe_fma.sv + - src/bp/bp_be_pipe_long.sv + - src/bp/bp_be_pipe_mem.sv + - src/bp/bp_be_pipe_sys.sv + - src/bp/bp_be_ptw.sv + - src/bp/bp_be_rec_to_raw.sv + - src/bp/bp_be_reservation.sv + - src/bp/bp_be_cmd_queue.sv + - src/bp/bp_be_detector.sv + - src/bp/bp_be_director.sv + - src/bp/bp_be_expander.sv + - src/bp/bp_be_instr_decoder.sv + - src/bp/bp_be_issue_queue.sv + - src/bp/bp_be_regfile.sv + - src/bp/bp_be_scheduler.sv + - src/bp/bp_be_scoreboard.sv + - src/bp/bp_be_dcache.sv + - src/bp/bp_be_dcache_decoder.sv + - src/bp/bp_be_dcache_wbuf.sv + - src/bp/bp_fe_ras.sv + - src/bp/bp_fe_bht.sv + - src/bp/bp_fe_btb.sv + - src/bp/bp_fe_controller.sv + - src/bp/bp_fe_icache.sv + - src/bp/bp_fe_scan.sv + - src/bp/bp_fe_pc_gen.sv + - src/bp/bp_fe_realigner.sv + - src/bp/bp_fe_top.sv + - src/bp/bp_lce.sv + - src/bp/bp_lce_req.sv + - src/bp/bp_lce_cmd.sv + - src/bp/bp_me_bedrock_register.sv + - src/bp/bp_me_cache_controller.sv + - src/bp/bp_me_dram_hash_decode.sv + - src/bp/bp_me_dram_hash_encode.sv + - src/bp/bp_me_cache_slice.sv + - src/bp/bp_me_cfg_slice.sv + - src/bp/bp_me_clint_slice.sv + - src/bp/bp_me_loopback.sv + - src/bp/bp_cce.sv + - src/bp/bp_cce_alu.sv + - src/bp/bp_cce_arbitrate.sv + - src/bp/bp_cce_branch.sv + - src/bp/bp_cce_dir.sv + - src/bp/bp_cce_dir_lru_extract.sv + - src/bp/bp_cce_dir_segment.sv + - src/bp/bp_cce_dir_tag_checker.sv + - src/bp/bp_cce_gad.sv + - src/bp/bp_cce_inst_decode.sv + - src/bp/bp_cce_inst_predecode.sv + - src/bp/bp_cce_inst_ram.sv + - src/bp/bp_cce_inst_stall.sv + - src/bp/bp_cce_msg.sv + - src/bp/bp_cce_pending_bits.sv + - src/bp/bp_cce_pma.sv + - src/bp/bp_cce_reg.sv + - src/bp/bp_cce_spec_bits.sv + - src/bp/bp_cce_src_sel.sv + - src/bp/bp_io_cce.sv + - src/bp/bp_cce_fsm.sv + - src/bp/bp_cce_wrapper.sv + - src/bp/bp_bedrock_size_to_len.sv + - src/bp/bp_uce.sv + - src/bp/bp_me_addr_to_cce_id.sv + - src/bp/bp_me_cce_id_to_cord.sv + - src/bp/bp_me_cord_to_id.sv + - src/bp/bp_me_lce_id_to_cord.sv + - src/bp/bp_me_stream_pump.sv + - src/bp/bp_me_stream_pump_in.sv + - src/bp/bp_me_stream_pump_out.sv + - src/bp/bp_me_stream_pump_control.sv + - src/bp/bp_me_stream_to_wormhole.sv + - src/bp/bp_me_wormhole_header_encode.sv + - src/bp/bp_me_wormhole_to_stream.sv + - src/bp/bp_me_wormhole_stream_control.sv + - src/bp/bp_me_xbar_stream.sv + - src/bp/bp_me_stream_gearbox.sv + - src/bp/bp_nd_socket.sv + - src/bp/bp_cacc_vdp.sv + - src/bp/bp_cacc_tile.sv + - src/bp/bp_cacc_tile_node.sv + - src/bp/bp_cacc_complex.sv + - src/bp/bp_sacc_vdp.sv + - src/bp/bp_sacc_scratchpad.sv + - src/bp/bp_sacc_tile.sv + - src/bp/bp_sacc_tile_node.sv + - src/bp/bp_sacc_complex.sv + - src/bp/bp_core.sv + - src/bp/bp_core_lite.sv + - src/bp/bp_core_minimal.sv + - src/bp/bp_core_complex.sv + - src/bp/bp_l2e_tile.sv + - src/bp/bp_l2e_tile_node.sv + - src/bp/bp_io_complex.sv + - src/bp/bp_io_link_to_lce.sv + - src/bp/bp_io_tile.sv + - src/bp/bp_io_tile_node.sv + - src/bp/bp_mem_complex.sv + - src/bp/bp_multicore.sv + - src/bp/bp_unicore.sv + - src/bp/bp_unicore_lite.sv + - src/bp/bp_core_tile.sv + - src/bp/bp_core_tile_node.sv + - src/bp/bp_processor.sv + - src/bp/bsg_async_noc_link.sv + - src/bp/bsg_dff_sync_read.sv + - src/bp/bsg_rom_param.sv + - src/bp/wrapper.sv + #Basejump Memory Files + - src/basejump_stl/bsg_tag_pkg.sv + - src/basejump_stl/bsg_dramsim3_pkg.sv + - src/basejump_stl/bsg_cache_to_axi.sv + - src/basejump_stl/bsg_cache_to_axi_rx.sv + - src/basejump_stl/bsg_cache_to_axi_tx.sv + - src/basejump_stl/bsg_cache_to_axi_ordering.sv + - src/basejump_stl/bsg_cache_to_test_dram.sv + - src/basejump_stl/bsg_cache_to_test_dram_rx.sv + - src/basejump_stl/bsg_cache_to_test_dram_rx_reorder.sv + - src/basejump_stl/bsg_cache_to_test_dram_tx.sv + - src/basejump_stl/bsg_fifo_reorder.sv + - src/basejump_stl/bsg_flatten_2D_array.sv + - src/basejump_stl/bsg_make_2D_array.sv + - src/basejump_stl/bsg_fsb_node_trace_replay.v + - src/basejump_stl/bsg_cam_1r1w_unmanaged.sv + - src/basejump_stl/bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.sv + - src/basejump_stl/bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma.sv + - src/basejump_stl/bsg_mux2_gatestack.sv + - src/basejump_stl/bsg_tag_trace_replay.sv + - src/basejump_stl/bsg_tag_master.sv + - src/basejump_stl/bsg_tag_client.sv + - src/basejump_stl/bsg_tag_client_unsync.sv + - src/basejump_stl/bsg_nonsynth_axi_mem.sv + - src/basejump_stl/bsg_nonsynth_test_rom.sv + - src/bp/bp_me_nonsynth_pkg.sv + - src/bp/bp_me_nonsynth_cce_tracer.sv + - src/bp/bp_me_nonsynth_cce_inst_tracer.sv + - src/bp/bp_me_nonsynth_cce_pending_tracer.sv + - src/bp/bp_me_nonsynth_cce_perf.sv + - src/bp/bp_me_nonsynth_dev_tracer.sv + - src/bp/bp_me_nonsynth_lce_tracer.sv + - src/bp/bp_be_nonsynth_dcache_tracer.sv + - src/bp/bp_fe_nonsynth_icache_tracer.sv + - src/bp/bp_nonsynth_watchdog.sv + - src/bp/bp_nonsynth_vm_tracer.sv + - src/bp/bp_nonsynth_cosim.sv + - src/bp/bp_nonsynth_host.sv + - src/bp/bp_nonsynth_if_verif.sv + - src/bp/bp_nonsynth_nbf_loader.sv + - src/bp/bp_nonsynth_core_profiler.sv + - src/bp/bp_nonsynth_pc_profiler.sv + - src/bp/bp_nonsynth_branch_profiler.sv + - src/bp/bp_nonsynth_perf.sv + - src/bp/bp_monitor.cpp + - src/bp/bp_nonsynth_dram.sv + - src/bp/testbench.sv + - src/basejump_stl/bsg_nonsynth_reset_gen.sv + - src/basejump_stl/bsg_nonsynth_clock_gen.sv + - src/basejump_stl/bsg_nonsynth_dramsim3.sv + - src/basejump_stl/bsg_nonsynth_dramsim3_map.sv + - src/basejump_stl/bsg_nonsynth_dramsim3_unmap.sv + + verilogIncludeFiles: + - src/bp/bp_be_ctl_pkgdef.svh + - src/bp/bp_be_dcache_defines.svh + - src/bp/bp_be_dcache_pkgdef.svh + - src/bp/bp_be_defines.svh + - src/basejump_stl/bsg_defines.sv + - src/basejump_stl/bsg_noc_links.svh + - src/basejump_stl/bsg_wormhole_router.svh + - src/bp/bp_common_accelerator_pkgdef.svh + - src/bp/bp_common_addr_defines.svh + - src/bp/bp_common_addr_pkgdef.svh + - src/bp/bp_common_aviary_cfg_pkgdef.svh + - src/bp/bp_common_aviary_custom_defines.svh + - src/bp/bp_common_aviary_defines.svh + - src/bp/bp_common_aviary_pkgdef.svh + - src/bp/bp_common_bedrock_if.svh + - src/bp/bp_common_bedrock_pkgdef.svh + - src/bp/bp_common_bedrock_wormhole_defines.svh + - src/bp/bp_common_cache_engine_if.svh + - src/bp/bp_common_cache_engine_pkgdef.svh + - src/bp/bp_common_cache_pkgdef.svh + - src/bp/bp_common_cfg_bus_defines.svh + - src/bp/bp_common_cfg_bus_pkgdef.svh + - src/bp/bp_common_clint_pkgdef.svh + - src/bp/bp_common_core_if.svh + - src/bp/bp_common_core_pkgdef.svh + - src/bp/bp_common_defines.svh + - src/bp/bp_common_host_pkgdef.svh + - src/bp/bp_common_log_defines.svh + - src/bp/bp_common_rv64_csr_defines.svh + - src/bp/bp_common_rv64_instr_defines.svh + - src/bp/bp_common_rv64_pkgdef.svh + - src/bp/bp_fe_pc_gen_pkgdef.svh + - src/bp/bp_fe_icache_defines.svh + - src/bp/bp_fe_icache_pkgdef.svh + - src/bp/bp_fe_defines.svh + - src/bp/bp_me_cce_defines.svh + - src/bp/bp_me_cce_inst_defines.svh + - src/bp/bp_me_cce_inst_pkgdef.svh + - src/bp/bp_me_cce_pkgdef.svh + - src/bp/bp_me_defines.svh + - src/bp/bp_top_defines.svh + - src/hardfloat/HardFloat_consts.vi + - src/hardfloat/HardFloat_specialize.vi + - src/hardfloat/HardFloat_localFuncs.vi + - src/basejump_stl/bsg_cache.svh + - src/basejump_stl/bsg_tag.svh + verilogDefines: + BP_SIM_CLK_PERIOD: 1000 + BP_RT_CLK_PERIOD: 1000000 + den2048Mb: 1 + sg5: 1 + x16: 1 + FULL_MEM: 1 + TRACE_ENABLE: 1 + cppSourceFiles: + - src/basejump_stl/bsg_mem_dma.cpp + - src/bp/null_cosim.cpp + cppIncludeFiles: + - src/basejump_stl/bsg_mem_dma.hpp + topModule: testbench + mainClock: testbench.clk_i + verilatorArgs: + - -pvalue+preload_mem_p=1 + +execute: + common: + postHook: tests/post.bash + tests: + hello: + files: + - tests/hello/prog.mem + - tests/hello/prog.nbf + - tests/hello/prog.riscv + tags: + - sanity + \ No newline at end of file diff --git a/designs/black-parrot/src/basejump_stl/bsg_1_to_n_tagged.sv b/designs/black-parrot/src/basejump_stl/bsg_1_to_n_tagged.sv new file mode 100644 index 0000000..824da86 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_1_to_n_tagged.sv @@ -0,0 +1,60 @@ +// MBT 6/8/2016 +// +// bsg_1_to_n_tagged +// +// this is intended to take one input and send it to +// one of several channels according to tag. +// +// see bsg_round_robin_n_to_1 for how the tags are assembled +// and for maintaining consistency between the two modules +// +// assumes a valid->yumi interface for input channel +// and valid/ready for output +// +// we do not include the data portion since it is just replicated +// + +`include "bsg_defines.sv" + +module bsg_1_to_n_tagged #( + parameter `BSG_INV_PARAM(num_out_p) + ,parameter tag_width_lp = `BSG_SAFE_CLOG2(num_out_p) + ) + (input clk_i + , input reset_i + + , input v_i + , input [tag_width_lp-1:0] tag_i + , output yumi_o + + , output [num_out_p-1:0] v_o + , input [num_out_p-1:0] ready_and_i + + // to downstream + ); + + wire unused0 = clk_i; + wire unused1 = reset_i; + + if (num_out_p == 1) + begin : one + assign v_o = v_i; + assign yumi_o = ready_and_i & v_i; + end + else + begin: many + + genvar i; + + bsg_decode_with_v #(.num_out_p(num_out_p)) bdv + (.i(tag_i) + ,.v_i(v_i) + ,.o(v_o) + ); + + assign yumi_o = ready_and_i[tag_i] & v_i; + end + +endmodule // bsg_1_to_n_tagged + +`BSG_ABSTRACT_MODULE(bsg_1_to_n_tagged) diff --git a/designs/black-parrot/src/basejump_stl/bsg_1_to_n_tagged_fifo.sv b/designs/black-parrot/src/basejump_stl/bsg_1_to_n_tagged_fifo.sv new file mode 100644 index 0000000..89c74da --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_1_to_n_tagged_fifo.sv @@ -0,0 +1,103 @@ +// MBT 7/7/2016 +// +// This module implements a FIFO that takes in a multiplexed stream +// on one end, and provides demultiplexed access on the other. +// +// Each stream is guaranteed to have els_p worth of storage. +// +// The parameter unbuffered_mask_p allows you to select some channels +// to come out without a FIFO. This is useful, for example, for credit +// channels that do not need buffering. The yumi_i signal is ignored +// for these channels; they are assumed to always be ready. +// + +`include "bsg_defines.sv" + +module bsg_1_to_n_tagged_fifo #(parameter `BSG_INV_PARAM(width_p) + ,parameter `BSG_INV_PARAM(num_out_p) + ,parameter `BSG_INV_PARAM(els_p) // these are elements per channel + ,parameter unbuffered_mask_p = '0 + ,parameter use_pseudo_large_fifo_p = 0 + ,parameter harden_small_fifo_p = 0 + ,parameter tag_width_lp = `BSG_SAFE_CLOG2(num_out_p) + ) + (input clk_i + , input reset_i + + , input v_i + , input [tag_width_lp-1:0] tag_i + , input [ width_p-1:0] data_i + , output yumi_o + + , output [num_out_p-1:0] v_o + , input [num_out_p-1:0] yumi_i + , output [num_out_p-1:0] [width_p-1:0] data_o + + ); + + wire [num_out_p-1:0] valid_lo; + wire [num_out_p-1:0] ready_and_li; + + bsg_1_to_n_tagged #(.num_out_p (num_out_p ) + ) _1_to_n + (.clk_i + ,.reset_i + + ,.v_i + ,.tag_i + ,.yumi_o + + ,.v_o(valid_lo) + ,.ready_and_i(ready_and_li) + ); + + genvar i; + + for (i = 0; i < num_out_p; i=i+1) + begin: rof + if (unbuffered_mask_p[i]) + begin: unbuf + assign v_o [i] = valid_lo[i]; + assign data_o [i] = data_i; + assign ready_and_li[i] = 1'b1; + end + else if (use_pseudo_large_fifo_p) + begin : psdlrg + bsg_fifo_1r1w_pseudo_large #(.width_p(width_p) + ,.els_p(els_p) + ) fifo + (.clk_i + ,.reset_i + + ,.v_i (valid_lo [i]) + ,.data_i + ,.ready_and_o(ready_and_li[i]) + + ,.v_o (v_o [i]) + ,.data_o (data_o [i]) + ,.yumi_i (yumi_i [i]) + ); + end + else + begin: buff + bsg_fifo_1r1w_small #(.width_p(width_p) + ,.els_p (els_p ) + ,.harden_p(harden_small_fifo_p) + ) fifo + (.clk_i + ,.reset_i + + ,.v_i (valid_lo [i]) + ,.data_i (data_i ) + ,.ready_param_o (ready_and_li[i]) + + ,.v_o (v_o [i]) + ,.data_o (data_o [i]) + ,.yumi_i (yumi_i [i]) + ); + end // block: fi + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_1_to_n_tagged_fifo) diff --git a/designs/black-parrot/src/basejump_stl/bsg_adder_cin.sv b/designs/black-parrot/src/basejump_stl/bsg_adder_cin.sv new file mode 100644 index 0000000..0b67df9 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_adder_cin.sv @@ -0,0 +1,16 @@ +//This module implements a simple adder with cin +`include "bsg_defines.sv" + +module bsg_adder_cin #(parameter `BSG_INV_PARAM(width_p) + , harden_p=1) + ( input [width_p-1:0] a_i + , input [width_p-1:0] b_i + , input cin_i + , output [width_p-1:0] o + ); + + assign o = a_i + b_i + { {(width_p-1){1'b0}}, cin_i }; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_adder_cin) diff --git a/designs/black-parrot/src/basejump_stl/bsg_adder_one_hot.sv b/designs/black-parrot/src/basejump_stl/bsg_adder_one_hot.sv new file mode 100644 index 0000000..0e06979 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_adder_one_hot.sv @@ -0,0 +1,56 @@ +// bsg_adder_one_hot +// +// adder whose inputs and outputs are all one hot signals +// +// the adder is by default a modulo adder, so it will wrap around +// if there is a carry out. +// +// if you don't want modulo, then make the output signal wide enough; i.e. set output_width_p>=2*width_p-1 +// + +`include "bsg_defines.sv" + +module bsg_adder_one_hot #(parameter `BSG_INV_PARAM(width_p), parameter output_width_p=width_p) + (input [width_p-1:0] a_i + , input [width_p-1:0] b_i + , output [output_width_p-1:0] o + ); + + genvar i,j; + + initial assert (output_width_p >= width_p) + else begin $error("%m: unsupported output_width_p < width_p"); + $finish(); + end + + for (i=0; i < output_width_p; i++) // for each output wire + begin: rof + wire [width_p-1:0] aggregate; + + // for each input a_i + // compute what bit is necessary to make it total to i + // including wrap around in the modulo case + + for (j=0; j < width_p; j=j+1) + begin: rof2 + if (i < j) + begin: rof3 + if (output_width_p+i-j < width_p) + assign aggregate[j] = a_i[j] & b_i[output_width_p+i-j]; + else + assign aggregate[j] = 1'b0; + end + else + if (i-j < width_p) + assign aggregate[j] = a_i[j] & b_i[i-j]; + else + assign aggregate[j] = 1'b0; + end // block: rof2 + + assign o[i] = | aggregate; + + end // block: rof + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_adder_one_hot) diff --git a/designs/black-parrot/src/basejump_stl/bsg_adder_ripple_carry.sv b/designs/black-parrot/src/basejump_stl/bsg_adder_ripple_carry.sv new file mode 100644 index 0000000..f9f3a18 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_adder_ripple_carry.sv @@ -0,0 +1,21 @@ +/** + * bsg_adder_ripple_carry.sv + * + * @author Tommy Jung + */ + +`include "bsg_defines.sv" + +module bsg_adder_ripple_carry #(parameter `BSG_INV_PARAM(width_p )) + ( + input [width_p-1:0] a_i + , input [width_p-1:0] b_i + , output logic [width_p-1:0] s_o + , output logic c_o + ); + + assign {c_o, s_o} = a_i + b_i; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_adder_ripple_carry) diff --git a/designs/black-parrot/src/basejump_stl/bsg_arb_fixed.sv b/designs/black-parrot/src/basejump_stl/bsg_arb_fixed.sv new file mode 100644 index 0000000..b42e821 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_arb_fixed.sv @@ -0,0 +1,30 @@ +// MBT 5-22-2016 +// fixed priority arbitration unit +// +// + +`include "bsg_defines.sv" + +module bsg_arb_fixed #(parameter `BSG_INV_PARAM( inputs_p ) + , parameter `BSG_INV_PARAM(lo_to_hi_p )) + ( input ready_then_i + , input [inputs_p-1:0] reqs_i + , output [inputs_p-1:0] grants_o + ); + + logic [inputs_p-1:0] grants_unmasked_lo; + + bsg_priority_encode_one_hot_out #(.width_p (inputs_p) + ,.lo_to_hi_p(lo_to_hi_p) + ) enc + (.i ( reqs_i ) + ,.o( grants_unmasked_lo) + ,.v_o( ) + ); + + // mask with ready bits + assign grants_o = grants_unmasked_lo & { (inputs_p) { ready_then_i } }; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_arb_fixed) diff --git a/designs/black-parrot/src/basejump_stl/bsg_arb_round_robin.sv b/designs/black-parrot/src/basejump_stl/bsg_arb_round_robin.sv new file mode 100644 index 0000000..7c1d704 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_arb_round_robin.sv @@ -0,0 +1,74 @@ +// bsg_arb_round_robin +// +// generally prefer this arbiter instead of bsg_round_robin_arb +// if the interface works for you (eventually we would like to deprecate bsg_round_robin_arb +// as the interface is too complex) +// +// note: (| reqs_i) can be used to determine if something is available to route (i.e. v_o) +// bsg_encode_one_hot(grants_o) can be used to determine what item was selected +// +// compared to bsg_round_robin_arb this design is more scalable but uses more registers +// +// priority goes high-to-low, wrapping around +// +// todo: maybe use some hardcoded case statements to optimize small cases +// +// + +`include "bsg_defines.sv" + +module bsg_arb_round_robin #(parameter `BSG_INV_PARAM(width_p)) + (input clk_i + , input reset_i + + , input [width_p-1:0] reqs_i // which items would like to go; OR this to get v_o equivalent + , output logic [width_p-1:0] grants_o // one hot, selected item + , input yumi_i // the user of the arbiter accepts the arb output, change MRU + ); + + if (width_p == 1) + begin: fi + assign grants_o = reqs_i; + end + else + begin: fi2 + // the current start location is represented as a thermometer code + logic [width_p-1-1:0] thermocode_r, thermocode_n; + + always_ff @(posedge clk_i) + if (reset_i) + thermocode_r <= '0; // initialize thermometer to all 0's + else + if (yumi_i) + thermocode_r <= thermocode_n; + + // this is essentially implementing a cyclic scan + wire [width_p*2-1:0] scan_li = { 1'b0, thermocode_r & reqs_i[width_p-1-1:0], reqs_i }; + wire [width_p*2-1:0] scan_lo; + + // default is high-to-lo + bsg_scan #(.width_p(width_p*2) + ,.or_p(1) + ) scan + ( + .i(scan_li) + ,.o(scan_lo) // thermometer code of the next item + ); + + // finds the first 1 + wire [width_p*2-1:0] edge_detect = ~(scan_lo >> 1) & scan_lo; + + // collapse the cyclic scan + assign grants_o = edge_detect[width_p*2-1-:width_p] | edge_detect[width_p-1:0]; + + always_comb + begin + if (|scan_li[width_p*2-1-:width_p]) // no wrap around + thermocode_n = scan_lo[width_p*2-1-:width_p-1]; + else // wrap around + thermocode_n = scan_lo[width_p-1:1]; + end + end +endmodule + +`BSG_ABSTRACT_MODULE(bsg_arb_round_robin) diff --git a/designs/black-parrot/src/basejump_stl/bsg_array_concentrate_static.sv b/designs/black-parrot/src/basejump_stl/bsg_array_concentrate_static.sv new file mode 100644 index 0000000..c757753 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_array_concentrate_static.sv @@ -0,0 +1,24 @@ +`include "bsg_defines.sv" + +module bsg_array_concentrate_static + #(parameter `BSG_INV_PARAM(pattern_els_p) + , parameter `BSG_INV_PARAM(width_p) + , dense_els_lp=$bits(pattern_els_p) + , sparse_els_lp=`BSG_COUNTONES_SYNTH(pattern_els_p)) + (input [dense_els_lp-1:0][width_p-1:0] i + ,output [sparse_els_lp-1:0][width_p-1:0] o +); + genvar j; + + if (pattern_els_p[0]) + assign o[0]=i[0]; + + for (j = 1; j < dense_els_lp; j=j+1) + begin : rof + if (pattern_els_p[j]) + assign o[`BSG_COUNTONES_SYNTH(pattern_els_p[j-1:0])] = i[j]; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_array_cocentrate_static) diff --git a/designs/black-parrot/src/basejump_stl/bsg_async_fifo.sv b/designs/black-parrot/src/basejump_stl/bsg_async_fifo.sv new file mode 100644 index 0000000..c84a0f6 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_async_fifo.sv @@ -0,0 +1,152 @@ +// MBT 7/24/2014 +// async fifo +// uses synchronous reset for both sides +// +// note: special attention should be paid to +// how reset is done. you cannot just tie +// the two resets together. talk to MBT. +// +// talk to MBT if you intend to change this +// it has been specially designed to cross +// clock domains. +// + +`include "bsg_defines.sv" + +module bsg_async_fifo #(parameter `BSG_INV_PARAM( lg_size_p ) + , parameter `BSG_INV_PARAM( width_p ) + // we allow the control bits to be separated from + // the data bits to allow for better control optimization. + // control_width_p is how many of the width_p bits are control bits; + // these bits should be at the top of the array + , parameter control_width_p = 0 + // When the fifo is empty, the rdata output of this fifo changes based + // on wvalid, while rvalid is synchronized to the rclk. This can cause + // timing violations on flops which directly latch the rdata without + // considering the enable signal. This parameter zeros out data when + // the fifo is empty to avoid these glitches. If receiving logic uses + // the rvalid signal, this extra hardware is unnecessary + , parameter and_data_with_valid_p = 0) + ( + input w_clk_i + , input w_reset_i + // not legal to w_enq_i if w_full_o is not low. + , input w_enq_i + , input [width_p-1:0] w_data_i + , output w_full_o + + // not legal to r_deq_i if r_valid_o is not high. + , input r_clk_i + , input r_reset_i + , input r_deq_i + , output [width_p-1:0] r_data_o + , output r_valid_o + ); + + localparam size_lp = 1 << lg_size_p; + + // we use an extra bit for the pointers to detect wraparound + logic [lg_size_p:0] r_ptr_gray_r; + + logic [lg_size_p:0] w_ptr_gray_r; + logic [lg_size_p:0] w_ptr_gray_r_rsync, r_ptr_gray_r_wsync, r_ptr_binary_r, w_ptr_binary_r; + + wire r_valid_o_tmp; // remove inout warning from Lint + assign r_valid_o = r_valid_o_tmp; + + wire [width_p-1:0] r_data_o_tmp; + if (and_data_with_valid_p) + begin : fi + wire [width_p-1:0] r_valid_o_exp = { width_p { r_valid_o_tmp } }; + bsg_and #(.width_p(width_p), .harden_p(1)) ba + (.a_i (r_data_o_tmp) + ,.b_i (r_valid_o_exp) + ,.o (r_data_o) + ); + end + else + begin : fi + assign r_data_o = r_data_o_tmp; + end + + bsg_mem_1r1w #(.width_p(width_p-control_width_p) + ,.els_p(size_lp) + ,.read_write_same_addr_p(0) + ) MSYNC_1r1w + (.w_clk_i (w_clk_i ) + ,.w_reset_i (w_reset_i) + + ,.w_v_i (w_enq_i ) + ,.w_addr_i(w_ptr_binary_r[0+:lg_size_p] ) + ,.w_data_i(w_data_i[0+:(width_p - control_width_p)] ) + + ,.r_v_i (r_valid_o_tmp ) + ,.r_addr_i(r_ptr_binary_r[0+:lg_size_p] ) + ,.r_data_o(r_data_o_tmp[0+:(width_p - control_width_p)] ) + ); + + if (control_width_p > 0) + begin : ctrl + bsg_mem_1r1w #(.width_p(control_width_p) + ,.els_p(size_lp) + ,.read_write_same_addr_p(0) + ) MSYNC_1r1w + (.w_clk_i (w_clk_i ) + ,.w_reset_i(w_reset_i) + + ,.w_v_i (w_enq_i ) + ,.w_addr_i (w_ptr_binary_r[0+:lg_size_p] ) + ,.w_data_i (w_data_i[(width_p-1)-:control_width_p]) + + ,.r_v_i (r_valid_o_tmp ) + ,.r_addr_i (r_ptr_binary_r[0+:lg_size_p] ) + ,.r_data_o (r_data_o_tmp[(width_p-1)-:control_width_p]) + ); + end + + // pointer from writer to reader (input to output of FIFO) + bsg_async_ptr_gray #(.lg_size_p(lg_size_p+1)) bapg_wr + (.w_clk_i(w_clk_i) + ,.w_reset_i(w_reset_i) + ,.w_inc_i(w_enq_i) + ,.r_clk_i(r_clk_i) + ,.w_ptr_binary_r_o(w_ptr_binary_r) + ,.w_ptr_gray_r_o(w_ptr_gray_r) + ,.w_ptr_gray_r_rsync_o(w_ptr_gray_r_rsync) + ); + + // pointer from reader to writer (output to input of FIFO) + // note this pointer travels backwards so the order is reverse + + bsg_async_ptr_gray #(.lg_size_p(lg_size_p+1)) bapg_rd + (.w_clk_i(r_clk_i) + ,.w_reset_i(r_reset_i) + ,.w_inc_i(r_deq_i) + ,.r_clk_i(w_clk_i) + ,.w_ptr_binary_r_o(r_ptr_binary_r) + ,.w_ptr_gray_r_o(r_ptr_gray_r) // after launch flop + ,.w_ptr_gray_r_rsync_o(r_ptr_gray_r_wsync) // after sync flops + ); + + // data is available if the two pointers are not equal + assign r_valid_o_tmp = (r_ptr_gray_r != w_ptr_gray_r_rsync); + + // compare two gray code values whose binaries values differ + // by top bit; this corresponds to the full conditions + + assign w_full_o = (w_ptr_gray_r == { ~r_ptr_gray_r_wsync[lg_size_p-:2] + , r_ptr_gray_r_wsync[0+:lg_size_p-1] }); + + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always @(negedge w_clk_i) + assert(!(w_full_o===1 && w_enq_i===1)) else $error("enqueing data on bsg_async_fifo when full"); + + always @(negedge r_clk_i) + assert(!(r_valid_o_tmp===0 && r_deq_i===1)) else $error("dequeing data on bsg_async_fifo when empty"); + +`endif + +endmodule // bsg_async_fifo + +`BSG_ABSTRACT_MODULE(bsg_async_fifo) diff --git a/designs/black-parrot/src/basejump_stl/bsg_async_ptr_gray.sv b/designs/black-parrot/src/basejump_stl/bsg_async_ptr_gray.sv new file mode 100644 index 0000000..75f4ec6 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_async_ptr_gray.sv @@ -0,0 +1,164 @@ +// MBT 7/25/2014 +// async pointer +// +// In this design, there are two clock domains. The first +// clock domain (w_) increments the grey-coded pointer; and the +// clock domain (r_) reads the grey-coded pointer. +// +// w_: signals in "receive credits" clock domain +// r_: signals in "spend credits" clock domain +// + +// RESET: both resets must be asserted and w_ clock most be posedge toggled +// at least once; and the r_ clock posedge toggled at least three times after that. +// This will be a sufficient number of clocks to pass through the synchronizers. + +// ASYNC RESET: w_ clock cannot toggle during reset + +`include "bsg_defines.sv" + +module bsg_async_ptr_gray #(parameter `BSG_INV_PARAM(lg_size_p ) + ,parameter use_negedge_for_launch_p=0 + ,parameter use_async_reset_p = 0) + ( + input w_clk_i + , input w_reset_i + , input w_inc_i // increment pointer + , input r_clk_i + , output [lg_size_p-1:0] w_ptr_binary_r_o // ptr value; binary + , output [lg_size_p-1:0] w_ptr_gray_r_o // same; gray coded; value before synchronizers + , output [lg_size_p-1:0] w_ptr_gray_r_rsync_o // value after synchronizers + ); + + logic [lg_size_p-1:0] w_ptr_r, w_ptr_n; + logic [lg_size_p-1:0] w_ptr_p1_r, w_ptr_p1_n, w_ptr_p2; + logic [lg_size_p-1:0] w_ptr_gray_n, w_ptr_gray_r, w_ptr_gray_r_rsync; + + // minor fixme: this could possibly be done more efficiently or at least more elegantly + // with a bsg_binary_plus_one_to_gray module. something like + // assign w_ptr_n = w_inc_i ? w_ptr_r+1 : w_ptr_r; + // assign w_ptr_gray_n = w_inc_i ? (bsg_binary_plus_one_to_gray(w_ptr_r) : (wptr_r >> 1) ^ wptr_r; + +// cycle time optimization +// assign w_ptr_n = w_ptr_r + w_inc_i; +// assign w_ptr_gray_n = (w_ptr_n >> 1) ^ w_ptr_n; + + assign w_ptr_p2 = w_ptr_p1_r + 1'b1; + assign w_ptr_n = w_inc_i ? w_ptr_p1_r : w_ptr_r; + assign w_ptr_p1_n = w_inc_i ? w_ptr_p2 : w_ptr_p1_r; + + assign w_ptr_gray_n = w_inc_i ? ((w_ptr_p1_r >> 1) ^ w_ptr_p1_r) : w_ptr_gray_r; + + // pointer, in binary + // feature wish: pass in negedge or posedge as parameter! + + if (use_async_reset_p == 0) begin: sync + + if (use_negedge_for_launch_p) + begin + + // synopsys sync_set_reset "w_reset_i" + always @(negedge w_clk_i) + if (w_reset_i) + begin + w_ptr_r <= 0; + w_ptr_p1_r <= 1; + end + else + begin + w_ptr_r <= w_ptr_n; + w_ptr_p1_r <= w_ptr_p1_n; + end + end + else + begin + // synopsys sync_set_reset "w_reset_i" + always @(posedge w_clk_i) + if (w_reset_i) + begin + w_ptr_r <= 0; + w_ptr_p1_r <= 1; + end + else + begin + w_ptr_r <= w_ptr_n; + w_ptr_p1_r <= w_ptr_p1_n; + end + end + + end + else begin: async + + // we declare shadow registers inside this block + // so that they will pick up the BSG_NO_CLOCK_GATE_X tag + + if (use_negedge_for_launch_p) + begin : BSG_NO_CLOCK_GATE_1 + logic [lg_size_p-1:0] async_reset_w_ptr_r; + logic [lg_size_p-1:0] async_reset_w_ptr_p1_r; + + assign w_ptr_r = async_reset_w_ptr_r; + assign w_ptr_p1_r = async_reset_w_ptr_p1_r; + + // synopsys async_set_reset "w_reset_i" + always @(negedge w_clk_i or posedge w_reset_i) + if (w_reset_i) + begin + async_reset_w_ptr_r <= 0; + async_reset_w_ptr_p1_r <= 1; + end + else + begin + async_reset_w_ptr_r <= w_ptr_n; + async_reset_w_ptr_p1_r <= w_ptr_p1_n; + end + end + else + begin : BSG_NO_CLOCK_GATE_2 + logic [lg_size_p-1:0] async_reset_w_ptr_r; + logic [lg_size_p-1:0] async_reset_w_ptr_p1_r; + + assign w_ptr_r = async_reset_w_ptr_r; + assign w_ptr_p1_r = async_reset_w_ptr_p1_r; + + // synopsys async_set_reset "w_reset_i" + always @(posedge w_clk_i or posedge w_reset_i) + if (w_reset_i) + begin + async_reset_w_ptr_r <= 0; + async_reset_w_ptr_p1_r <= 1; + end + else + begin + async_reset_w_ptr_r <= w_ptr_n; + async_reset_w_ptr_p1_r <= w_ptr_p1_n; + end + end + end + + assign w_ptr_binary_r_o = w_ptr_r; + + // synchronize the grey coded pointer across clock domains + // we use these to send pointers across clock boundaries + // this includes both launch flops and synchronization flops + // these should be abutted in physical design + + bsg_launch_sync_sync #(.width_p(lg_size_p) + ,.use_negedge_for_launch_p(use_negedge_for_launch_p) + ,.use_async_reset_p(use_async_reset_p)) ptr_sync + ( + .iclk_i(w_clk_i) + ,.iclk_reset_i(w_reset_i) + ,.oclk_i(r_clk_i) + ,.iclk_data_i(w_ptr_gray_n) + ,.iclk_data_o(w_ptr_gray_r) + ,.oclk_data_o(w_ptr_gray_r_rsync) + ); + + // fixme: probably wise to put a dont_touch'ed buffer cell on the launch flop. + assign w_ptr_gray_r_o = w_ptr_gray_r; + assign w_ptr_gray_r_rsync_o = w_ptr_gray_r_rsync; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_async_ptr_gray) diff --git a/designs/black-parrot/src/basejump_stl/bsg_axi_pkg.sv b/designs/black-parrot/src/basejump_stl/bsg_axi_pkg.sv new file mode 100644 index 0000000..9253415 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_axi_pkg.sv @@ -0,0 +1,97 @@ + +package bsg_axi_pkg; + + typedef enum logic [1:0] + { + e_axi_resp_okay = 2'b00 + ,e_axi_resp_exokay = 2'b01 + ,e_axi_resp_slverr = 2'b10 + ,e_axi_resp_decerr = 2'b11 + } axi_resp_type_e; + + // bit : 0 / 1 + // prot[2] : data / instruction + // prot[1] : secure / non-secure + // prot[0] : normal / privileged + typedef enum logic [2:0] + { + // Normal / Non-Secure / Data + e_axi_prot_dsn = 3'b000 + ,e_axi_prot_dsp = 3'b001 + ,e_axi_prot_dnn = 3'b010 + ,e_axi_prot_dnp = 3'b011 + ,e_axi_prot_isn = 3'b100 + ,e_axi_prot_isp = 3'b101 + ,e_axi_prot_inn = 3'b110 + ,e_axi_prot_inp = 3'b111 + } axi_prot_type_e; + + // bit : 0 / 1 + // cache[3] : write no-allocate / write allocate + // cache[2] : read no-allocate / read allocate + // cache[1] : non-modifiable / modifiable + // cache[0] : non-bufferable / bufferable + typedef enum logic [3:0] + { + e_axi_cache_wnarnanmnb = 4'b0000 + ,e_axi_cache_wnarnanmb = 4'b0001 + ,e_axi_cache_wnarnamnb = 4'b0010 + ,e_axi_cache_wnarnamb = 4'b0011 + ,e_axi_cache_wnaramnb = 4'b0110 + ,e_axi_cache_wnaramb = 4'b0111 + ,e_axi_cache_waramnb = 4'b1110 + ,e_axi_cache_warnamnb = 4'b1010 + ,e_axi_cache_warnamb = 4'b1011 + ,e_axi_cache_waramb = 4'b1111 + } axi_cache_type_e; + + typedef enum logic [1:0] + { + e_axi_burst_fixed = 2'b00 + ,e_axi_burst_incr = 2'b01 + ,e_axi_burst_wrap = 2'b10 + ,e_axi_burst_reserved = 2'b11 + } axi_burst_type_e; + + typedef enum logic [3:0] + { + e_axi_qos_none = 4'b0000 + // The AXI spec does not provide any official definitions of qos + } axi_qos_type_e; + + typedef enum logic [2:0] + { + e_axi_size_1B = 3'b000 + ,e_axi_size_2B = 3'b001 + ,e_axi_size_4B = 3'b010 + ,e_axi_size_8B = 3'b011 + ,e_axi_size_16B = 3'b100 + ,e_axi_size_32B = 3'b101 + ,e_axi_size_64B = 3'b110 + ,e_axi_size_128B = 3'b111 + } axi_size_e; + + // AXI defines burst lengths of 1-16 for bursts not incr + // and 1-256 for bursts that are incr + typedef enum logic [3:0] + { + e_axi_len_1 = 4'b0000 + ,e_axi_len_2 = 4'b0001 + ,e_axi_len_3 = 4'b0010 + ,e_axi_len_4 = 4'b0011 + ,e_axi_len_5 = 4'b0100 + ,e_axi_len_6 = 4'b0101 + ,e_axi_len_7 = 4'b0110 + ,e_axi_len_8 = 4'b0111 + ,e_axi_len_9 = 4'b1000 + ,e_axi_len_10 = 4'b1001 + ,e_axi_len_11 = 4'b1010 + ,e_axi_len_12 = 4'b1011 + ,e_axi_len_13 = 4'b1100 + ,e_axi_len_14 = 4'b1101 + ,e_axi_len_15 = 4'b1110 + ,e_axi_len_16 = 4'b1111 + } axi_len_e; + +endpackage + diff --git a/designs/black-parrot/src/basejump_stl/bsg_buf.sv b/designs/black-parrot/src/basejump_stl/bsg_buf.sv new file mode 100644 index 0000000..5e6c383 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_buf.sv @@ -0,0 +1,13 @@ +`include "bsg_defines.sv" + +module bsg_buf #(parameter `BSG_INV_PARAM(width_p) + , harden_p=1) + (input [width_p-1:0] i + , output [width_p-1:0] o + ); + + assign o = i; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_buf) diff --git a/designs/black-parrot/src/basejump_stl/bsg_buf_ctrl.sv b/designs/black-parrot/src/basejump_stl/bsg_buf_ctrl.sv new file mode 100644 index 0000000..a67e3f1 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_buf_ctrl.sv @@ -0,0 +1,14 @@ +//This module buff 1 bit control signal to width_p vector +`include "bsg_defines.sv" + +module bsg_buf_ctrl #(parameter `BSG_INV_PARAM(width_p) + , harden_p=1) + (input i + , output [width_p-1:0] o + ); + + assign o = { width_p{i}}; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_buf_ctrl) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache.sv b/designs/black-parrot/src/basejump_stl/bsg_cache.sv new file mode 100644 index 0000000..6f2e2e4 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache.sv @@ -0,0 +1,1242 @@ +/** + * bsg_cache.sv + * + * - two-stage pipelined. + * - n-way set associative. + * - pseudo-tree LRU replacement policy. + * - write-back, write-allocate + * + * @author tommy + * + * See https://docs.google.com/document/d/1AIjhuwTbOYwyZHdu-Uc4dr9Fwxi6ZKscKSGTiUeQEYo/edit for design doc + */ + + +`include "bsg_defines.sv" +`include "bsg_cache.svh" + +module bsg_cache + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(addr_width_p) // byte addr + ,parameter `BSG_INV_PARAM(data_width_p) // word size + ,parameter `BSG_INV_PARAM(block_size_in_words_p) + ,parameter `BSG_INV_PARAM(sets_p) + ,parameter `BSG_INV_PARAM(ways_p) + ,parameter `BSG_INV_PARAM(word_tracking_p) + + // Explicit size prevents size inference and allows for ((foo == bar) << e_cache_amo_swap) + ,parameter [31:0] amo_support_p=(1 << e_cache_amo_swap) + | (1 << e_cache_amo_or) + + // dma burst width + ,parameter dma_data_width_p=data_width_p // default value. it can also be pow2 multiple of data_width_p. + + ,localparam bsg_cache_pkt_width_lp=`bsg_cache_pkt_width(addr_width_p,data_width_p) + ,localparam bsg_cache_dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p, block_size_in_words_p) + ,localparam burst_size_in_words_lp=(dma_data_width_p/data_width_p) + + ,parameter debug_p=0 + ) + ( + input clk_i + ,input reset_i + + ,input [bsg_cache_pkt_width_lp-1:0] cache_pkt_i + ,input v_i + ,output logic yumi_o + + ,output logic [data_width_p-1:0] data_o + ,output logic v_o + ,input yumi_i + + ,output logic [bsg_cache_dma_pkt_width_lp-1:0] dma_pkt_o + ,output logic dma_pkt_v_o + ,input dma_pkt_yumi_i + + ,input [dma_data_width_p-1:0] dma_data_i + ,input dma_data_v_i + ,output logic dma_data_ready_and_o + + ,output logic [dma_data_width_p-1:0] dma_data_o + ,output logic dma_data_v_o + ,input dma_data_yumi_i + + // this signal tells the outside world that the instruction is moving from + // TL to TV stage. It can be used for some metadata outside the cache that + // needs to move together with the corresponding instruction. The usage of + // this signal is totally optional. + ,output logic v_we_o + ); + + + // localparam + // + localparam lg_sets_lp=`BSG_SAFE_CLOG2(sets_p); + localparam data_mask_width_lp=(data_width_p>>3); + localparam lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_mask_width_lp); + localparam lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p); + localparam block_offset_width_lp=(block_size_in_words_p > 1) ? lg_data_mask_width_lp+lg_block_size_in_words_lp : lg_data_mask_width_lp; + localparam way_offset_width_lp=(sets_p == 1) ? block_offset_width_lp : block_offset_width_lp+lg_sets_lp; + localparam tag_width_lp=(sets_p == 1) ? (addr_width_p-block_offset_width_lp) : (addr_width_p-lg_sets_lp-block_offset_width_lp); + localparam tag_info_width_lp=`bsg_cache_tag_info_width(tag_width_lp); + localparam lg_ways_lp=`BSG_SAFE_CLOG2(ways_p); + localparam stat_info_width_lp = `bsg_cache_stat_info_width(ways_p); + localparam data_sel_mux_els_lp = `BSG_MIN(4,lg_data_mask_width_lp+1); + localparam lg_data_sel_mux_els_lp = `BSG_SAFE_CLOG2(data_sel_mux_els_lp); + + localparam lg_burst_size_in_words_lp=`BSG_SAFE_CLOG2(burst_size_in_words_lp); + localparam burst_len_lp=(block_size_in_words_p*data_width_p/dma_data_width_p); + localparam lg_burst_len_lp=`BSG_SAFE_CLOG2(burst_len_lp); + localparam dma_data_mask_width_lp=(dma_data_width_p>>3); + localparam data_mem_els_lp = sets_p*burst_len_lp; + localparam lg_data_mem_els_lp = `BSG_SAFE_CLOG2(data_mem_els_lp); + localparam sbuf_data_mem_addr_offset_lp=(burst_len_lp == block_size_in_words_p) ? lg_block_size_in_words_lp+$clog2(sets_p) : lg_burst_len_lp+$clog2(sets_p); + + // instruction decoding + // + logic [lg_ways_lp-1:0] addr_way; + logic [lg_sets_lp-1:0] addr_index; + + `declare_bsg_cache_pkt_s(addr_width_p, data_width_p); + bsg_cache_pkt_s cache_pkt; + + assign cache_pkt = cache_pkt_i; + + bsg_cache_decode_s decode; + + bsg_cache_decode decode0 ( + .opcode_i(cache_pkt.opcode) + ,.decode_o(decode) + ); + + assign addr_way + = cache_pkt.addr[way_offset_width_lp+:lg_ways_lp]; + assign addr_index + = cache_pkt.addr[block_offset_width_lp+:lg_sets_lp]; + + logic [lg_data_mem_els_lp-1:0] ld_data_mem_addr; + + if (burst_len_lp == 1) begin + assign ld_data_mem_addr = addr_index; + end + else if (burst_len_lp == block_size_in_words_p) begin + assign ld_data_mem_addr = {{(sets_p>1){addr_index}}, cache_pkt.addr[lg_data_mask_width_lp+:lg_block_size_in_words_lp]}; + end + else begin + assign ld_data_mem_addr = {addr_index, cache_pkt.addr[lg_data_mask_width_lp+lg_burst_size_in_words_lp+:lg_burst_len_lp]}; + end + + + // tl_stage + // + logic tl_we; + logic v_tl_r; + bsg_cache_decode_s decode_tl_r; + logic [data_mask_width_lp-1:0] mask_tl_r; + logic [addr_width_p-1:0] addr_tl_r; + logic [data_width_p-1:0] data_tl_r; + logic sbuf_hazard; + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + v_tl_r <= 1'b0; + {mask_tl_r + ,addr_tl_r + ,data_tl_r + ,decode_tl_r} <= '0; + end + else begin + if (tl_we) begin + v_tl_r <= v_i; + if (v_i) begin + mask_tl_r <= cache_pkt.mask; + addr_tl_r <= cache_pkt.addr; + data_tl_r <= cache_pkt.data; + decode_tl_r <= decode; + end + end + else begin + if (sbuf_hazard) begin + v_tl_r <= 1'b0; + end + end + end + end + + logic [lg_sets_lp-1:0] addr_index_tl; + + assign addr_index_tl = + addr_tl_r[block_offset_width_lp+:lg_sets_lp]; + + logic [lg_data_mem_els_lp-1:0] recover_data_mem_addr; + + if (burst_len_lp == 1) begin + assign recover_data_mem_addr = addr_index_tl; + end + else if (burst_len_lp == block_size_in_words_p) begin + assign recover_data_mem_addr = {{(sets_p>1){addr_index_tl}}, addr_tl_r[lg_data_mask_width_lp+:lg_block_size_in_words_lp]}; + end + else begin + assign recover_data_mem_addr = {addr_index_tl, addr_tl_r[lg_data_mask_width_lp+lg_burst_size_in_words_lp+:lg_burst_len_lp]}; + end + + + // tag_mem + // + `declare_bsg_cache_tag_info_s(tag_width_lp); + + logic tag_mem_v_li; + logic tag_mem_w_li; + logic [lg_sets_lp-1:0] tag_mem_addr_li; + bsg_cache_tag_info_s [ways_p-1:0] tag_mem_data_li; + bsg_cache_tag_info_s [ways_p-1:0] tag_mem_w_mask_li; + bsg_cache_tag_info_s [ways_p-1:0] tag_mem_data_lo; + + bsg_mem_1rw_sync_mask_write_bit #( + .width_p(tag_info_width_lp*ways_p) + ,.els_p(sets_p) + ,.latch_last_read_p(1) + ) tag_mem ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(tag_mem_v_li) + ,.w_i(tag_mem_w_li) + ,.addr_i(tag_mem_addr_li) + ,.data_i(tag_mem_data_li) + ,.w_mask_i(tag_mem_w_mask_li) + ,.data_o(tag_mem_data_lo) + ); + + logic [ways_p-1:0] valid_tl; + logic [ways_p-1:0][tag_width_lp-1:0] tag_tl; + logic [ways_p-1:0] lock_tl; + + for (genvar i = 0; i < ways_p; i++) begin + assign valid_tl[i] = tag_mem_data_lo[i].valid; + assign tag_tl[i] = tag_mem_data_lo[i].tag; + assign lock_tl[i] = tag_mem_data_lo[i].lock; + end + + + // data_mem + // + logic data_mem_v_li; + logic data_mem_w_li; + logic [lg_data_mem_els_lp-1:0] data_mem_addr_li; + logic [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_li; + logic [ways_p-1:0][dma_data_mask_width_lp-1:0] data_mem_w_mask_li; + logic [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_lo; + + bsg_mem_1rw_sync_mask_write_byte #( + .data_width_p(dma_data_width_p*ways_p) + ,.els_p(data_mem_els_lp) + ,.latch_last_read_p(1) + ) data_mem ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(data_mem_v_li) + ,.w_i(data_mem_w_li) + ,.addr_i(data_mem_addr_li) + ,.data_i(data_mem_data_li) + ,.write_mask_i(data_mem_w_mask_li) + ,.data_o(data_mem_data_lo) + ); + + + // track_mem + // + logic track_mem_v_li; + logic track_mem_w_li; + logic [lg_sets_lp-1:0] track_mem_addr_li; + logic [ways_p-1:0][block_size_in_words_p-1:0] track_mem_data_li; + logic [ways_p-1:0][block_size_in_words_p-1:0] track_mem_w_mask_li; + logic [ways_p-1:0][block_size_in_words_p-1:0] track_mem_data_lo; + +if (word_tracking_p) begin : track_mem_gen + bsg_mem_1rw_sync_mask_write_bit #( + .width_p(block_size_in_words_p*ways_p) + ,.els_p(sets_p) + ,.latch_last_read_p(1) + ) track_mem ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(track_mem_v_li) + ,.w_i(track_mem_w_li) + ,.addr_i(track_mem_addr_li) + ,.data_i(track_mem_data_li) + ,.w_mask_i(track_mem_w_mask_li) + ,.data_o(track_mem_data_lo) + ); +end +else begin + for (genvar i = 0; i < ways_p; i++) begin + assign track_mem_data_lo[i] = {block_size_in_words_p{1'b1}}; + end +end + + // v stage + // + logic v_we; + logic v_v_r; + bsg_cache_decode_s decode_v_r; + logic [data_mask_width_lp-1:0] mask_v_r; + logic [addr_width_p-1:0] addr_v_r; + logic [data_width_p-1:0] data_v_r; + logic [ways_p-1:0] valid_v_r; + logic [ways_p-1:0] lock_v_r; + logic [ways_p-1:0][tag_width_lp-1:0] tag_v_r; + logic [ways_p-1:0][dma_data_width_p-1:0] ld_data_v_r; + logic [ways_p-1:0][block_size_in_words_p-1:0] track_data_v_r; + logic retval_op_v; + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + v_v_r <= 1'b0; + {mask_v_r + ,decode_v_r + ,addr_v_r + ,data_v_r + ,valid_v_r + ,lock_v_r + ,tag_v_r + ,track_data_v_r} <= '0; + end + else begin + if (v_we) begin + v_v_r <= v_tl_r; + if (v_tl_r) begin + mask_v_r <= mask_tl_r; + decode_v_r <= decode_tl_r; + addr_v_r <= addr_tl_r; + data_v_r <= data_tl_r; + valid_v_r <= valid_tl; + tag_v_r <= tag_tl; + lock_v_r <= lock_tl; + ld_data_v_r <= data_mem_data_lo; + track_data_v_r <= track_mem_data_lo; + end + end + end + end + + assign v_we_o = v_we; + + logic [tag_width_lp-1:0] addr_tag_v; + logic [lg_sets_lp-1:0] addr_index_v; + logic [lg_ways_lp-1:0] addr_way_v; + logic [lg_block_size_in_words_lp-1:0] addr_block_offset_v; + logic [ways_p-1:0] tag_hit_v; + + assign addr_tag_v = + addr_v_r[way_offset_width_lp+:tag_width_lp]; + assign addr_index_v = + addr_v_r[block_offset_width_lp+:lg_sets_lp]; + assign addr_way_v = + addr_v_r[way_offset_width_lp+:lg_ways_lp]; + assign addr_block_offset_v = (block_size_in_words_p > 1) + ? addr_v_r[lg_data_mask_width_lp+:lg_block_size_in_words_lp] + : 1'b0; + + for (genvar i = 0; i < ways_p; i++) begin + assign tag_hit_v[i] = (addr_tag_v == tag_v_r[i]) & valid_v_r[i]; + end + + + logic [lg_ways_lp-1:0] tag_hit_way_id; + logic tag_hit_found; + + bsg_priority_encode #( + .width_p(ways_p) + ,.lo_to_hi_p(1) + ) tag_hit_pe ( + .i(tag_hit_v) + ,.addr_o(tag_hit_way_id) + ,.v_o(tag_hit_found) + ); + + logic bypass_track_lo; + + wire partial_st = decode.st_op & (decode.mask_op + ? ~(&cache_pkt.mask) + : (decode.data_size_op < lg_data_mask_width_lp)); + wire partial_st_tl = decode_tl_r.st_op & (decode_tl_r.mask_op + ? ~(&mask_tl_r) + : (decode_tl_r.data_size_op < lg_data_mask_width_lp)); + wire partial_st_v = decode_v_r.st_op & (decode_v_r.mask_op + ? ~(&mask_v_r) + : (decode_v_r.data_size_op < lg_data_mask_width_lp)); + + wire ld_st_amo_tag_miss = (decode_v_r.ld_op | decode_v_r.st_op | decode_v_r.atomic_op) & ~tag_hit_found; + wire track_miss = (decode_v_r.ld_op | decode_v_r.atomic_op | partial_st_v) + & tag_hit_found & ~(track_data_v_r[tag_hit_way_id][addr_block_offset_v] | bypass_track_lo); + wire tagfl_hit = decode_v_r.tagfl_op & valid_v_r[addr_way_v]; + wire aflinv_hit = (decode_v_r.afl_op | decode_v_r.aflinv_op| decode_v_r.ainv_op) & tag_hit_found; + wire alock_miss = decode_v_r.alock_op & (tag_hit_found ? ~lock_v_r[tag_hit_way_id] : 1'b1); // either the line is miss, or the line is unlocked. + wire aunlock_hit = decode_v_r.aunlock_op & (tag_hit_found ? lock_v_r[tag_hit_way_id] : 1'b0); // the line is hit and locked. + + // miss_v signal activates the miss handling unit. + // MBT: the ~decode_v_r.tagst_op is necessary at the top of this expression + // to avoid X-pessimism post synthesis due to X's coming out of the tags + wire miss_v = (~decode_v_r.tagst_op) & v_v_r + & (ld_st_amo_tag_miss | track_miss | tagfl_hit | aflinv_hit | alock_miss | aunlock_hit); + + // ops that return some value other than '0. + assign retval_op_v = decode_v_r.ld_op | decode_v_r.taglv_op | decode_v_r.tagla_op | decode_v_r.atomic_op; + + // stat_mem + // + `declare_bsg_cache_stat_info_s(ways_p); + + logic stat_mem_v_li; + logic stat_mem_w_li; + logic [lg_sets_lp-1:0] stat_mem_addr_li; + bsg_cache_stat_info_s stat_mem_data_li; + bsg_cache_stat_info_s stat_mem_w_mask_li; + bsg_cache_stat_info_s stat_mem_data_lo; + + bsg_mem_1rw_sync_mask_write_bit #( + .width_p(stat_info_width_lp) + ,.els_p(sets_p) + ,.latch_last_read_p(1) + ) stat_mem ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(stat_mem_v_li) + ,.w_i(stat_mem_w_li) + ,.addr_i(stat_mem_addr_li) + ,.data_i(stat_mem_data_li) + ,.w_mask_i(stat_mem_w_mask_li) + ,.data_o(stat_mem_data_lo) + ); + + // miss handler + // + bsg_cache_dma_cmd_e dma_cmd_lo; + logic [addr_width_p-1:0] dma_addr_lo; + logic [lg_ways_lp-1:0] dma_way_lo; + logic dma_done_li; + + logic recover_lo; + logic miss_done_lo; + + logic miss_stat_mem_v_lo; + logic miss_stat_mem_w_lo; + logic [lg_sets_lp-1:0] miss_stat_mem_addr_lo; + bsg_cache_stat_info_s miss_stat_mem_data_lo; + bsg_cache_stat_info_s miss_stat_mem_w_mask_lo; + + logic miss_tag_mem_v_lo; + logic miss_tag_mem_w_lo; + logic [lg_sets_lp-1:0] miss_tag_mem_addr_lo; + bsg_cache_tag_info_s [ways_p-1:0] miss_tag_mem_data_lo; + bsg_cache_tag_info_s [ways_p-1:0] miss_tag_mem_w_mask_lo; + + logic miss_track_mem_v_lo; + logic miss_track_mem_w_lo; + logic [lg_sets_lp-1:0] miss_track_mem_addr_lo; + logic [ways_p-1:0][block_size_in_words_p-1:0] miss_track_mem_w_mask_lo; + logic [ways_p-1:0][block_size_in_words_p-1:0] miss_track_mem_data_lo; + + logic sbuf_empty_lo, tbuf_empty_lo; + logic [lg_ways_lp-1:0] chosen_way_lo; + logic select_snoop_data_r_lo; + logic miss_track_data_we_lo; + + bsg_cache_miss #( + .addr_width_p(addr_width_p) + ,.data_width_p(data_width_p) + ,.sets_p(sets_p) + ,.block_size_in_words_p(block_size_in_words_p) + ,.ways_p(ways_p) + ,.word_tracking_p(word_tracking_p) + ) miss ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.miss_v_i(miss_v) + ,.track_miss_i(track_miss) + ,.decode_v_i(decode_v_r) + ,.addr_v_i(addr_v_r) + ,.mask_v_i(mask_v_r) + + ,.tag_v_i(tag_v_r) + ,.valid_v_i(valid_v_r) + ,.lock_v_i(lock_v_r) + ,.tag_hit_v_i(tag_hit_v) + ,.tag_hit_way_id_i(tag_hit_way_id) + ,.tag_hit_found_i(tag_hit_found) + + ,.sbuf_empty_i(sbuf_empty_lo) + ,.tbuf_empty_i(tbuf_empty_lo) + + ,.dma_cmd_o(dma_cmd_lo) + ,.dma_way_o(dma_way_lo) + ,.dma_addr_o(dma_addr_lo) + ,.dma_done_i(dma_done_li) + + ,.track_data_we_o(miss_track_data_we_lo) + + ,.stat_info_i(stat_mem_data_lo) + + ,.stat_mem_v_o(miss_stat_mem_v_lo) + ,.stat_mem_w_o(miss_stat_mem_w_lo) + ,.stat_mem_addr_o(miss_stat_mem_addr_lo) + ,.stat_mem_data_o(miss_stat_mem_data_lo) + ,.stat_mem_w_mask_o(miss_stat_mem_w_mask_lo) + + ,.tag_mem_v_o(miss_tag_mem_v_lo) + ,.tag_mem_w_o(miss_tag_mem_w_lo) + ,.tag_mem_addr_o(miss_tag_mem_addr_lo) + ,.tag_mem_data_o(miss_tag_mem_data_lo) + ,.tag_mem_w_mask_o(miss_tag_mem_w_mask_lo) + + ,.track_mem_v_o(miss_track_mem_v_lo) + ,.track_mem_w_o(miss_track_mem_w_lo) + ,.track_mem_addr_o(miss_track_mem_addr_lo) + ,.track_mem_w_mask_o(miss_track_mem_w_mask_lo) + ,.track_mem_data_o(miss_track_mem_data_lo) + + ,.recover_o(recover_lo) + ,.done_o(miss_done_lo) + + ,.chosen_way_o(chosen_way_lo) + + ,.ack_i(v_o & yumi_i) + ,.select_snoop_data_r_o(select_snoop_data_r_lo) + ); + + // dma + // + logic [data_width_p-1:0] snoop_word_lo; + logic dma_data_mem_v_lo; + logic dma_data_mem_w_lo; + logic [lg_data_mem_els_lp-1:0] dma_data_mem_addr_lo; + logic [ways_p-1:0][dma_data_mask_width_lp-1:0] dma_data_mem_w_mask_lo; + logic [ways_p-1:0][dma_data_width_p-1:0] dma_data_mem_data_lo; + logic dma_evict_lo; + + bsg_cache_dma #( + .addr_width_p(addr_width_p) + ,.data_width_p(data_width_p) + ,.block_size_in_words_p(block_size_in_words_p) + ,.sets_p(sets_p) + ,.ways_p(ways_p) + ,.word_tracking_p(word_tracking_p) + ,.dma_data_width_p(dma_data_width_p) + ,.debug_p(debug_p) + ) dma ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.dma_cmd_i(dma_cmd_lo) + ,.dma_way_i(dma_way_lo) + ,.dma_addr_i(dma_addr_lo) + ,.done_o(dma_done_li) + + ,.track_data_we_i(miss_track_data_we_lo) + + ,.snoop_word_o(snoop_word_lo) + + ,.dma_pkt_o(dma_pkt_o) + ,.dma_pkt_v_o(dma_pkt_v_o) + ,.dma_pkt_yumi_i(dma_pkt_yumi_i) + + ,.dma_data_i(dma_data_i) + ,.dma_data_v_i(dma_data_v_i) + ,.dma_data_ready_and_o(dma_data_ready_and_o) + + ,.dma_data_o(dma_data_o) + ,.dma_data_v_o(dma_data_v_o) + ,.dma_data_yumi_i(dma_data_yumi_i) + + ,.data_mem_v_o(dma_data_mem_v_lo) + ,.data_mem_w_o(dma_data_mem_w_lo) + ,.data_mem_addr_o(dma_data_mem_addr_lo) + ,.data_mem_w_mask_o(dma_data_mem_w_mask_lo) + ,.data_mem_data_o(dma_data_mem_data_lo) + ,.data_mem_data_i(data_mem_data_lo) + + ,.track_miss_i(track_miss) + ,.track_mem_data_i(track_mem_data_lo) + + ,.dma_evict_o(dma_evict_lo) + ); + + // store buffer + // + `declare_bsg_cache_sbuf_entry_s(addr_width_p, data_width_p, ways_p); + + logic sbuf_v_li; + bsg_cache_sbuf_entry_s sbuf_entry_li; + + logic sbuf_v_lo; + logic sbuf_yumi_li; + bsg_cache_sbuf_entry_s sbuf_entry_lo; + + logic [addr_width_p-1:0] sbuf_bypass_addr_li; + logic sbuf_bypass_v_li; + logic [data_width_p-1:0] bypass_data_lo; + logic [data_mask_width_lp-1:0] bypass_mask_lo; + logic sbuf_full_lo; + + bsg_cache_sbuf #( + .data_width_p(data_width_p) + ,.addr_width_p(addr_width_p) + ,.ways_p(ways_p) + ) sbuf ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.sbuf_entry_i(sbuf_entry_li) + ,.v_i(sbuf_v_li) + + ,.sbuf_entry_o(sbuf_entry_lo) + ,.v_o(sbuf_v_lo) + ,.yumi_i(sbuf_yumi_li) + + ,.empty_o(sbuf_empty_lo) + ,.full_o(sbuf_full_lo) + + ,.bypass_addr_i(sbuf_bypass_addr_li) + ,.bypass_v_i(sbuf_bypass_v_li) + ,.bypass_data_o(bypass_data_lo) + ,.bypass_mask_o(bypass_mask_lo) + ); + + logic [ways_p-1:0] sbuf_way_decode; + + bsg_decode #( + .num_out_p(ways_p) + ) sbuf_way_demux ( + .i(sbuf_entry_lo.way_id) + ,.o(sbuf_way_decode) + ); + + logic [burst_size_in_words_lp-1:0] sbuf_burst_offset_decode; + bsg_decode #( + .num_out_p(burst_size_in_words_lp) + ) sbuf_bo_demux ( + .i(sbuf_entry_lo.addr[lg_data_mask_width_lp+:lg_burst_size_in_words_lp]) + ,.o(sbuf_burst_offset_decode) + ); + + logic [dma_data_mask_width_lp-1:0] sbuf_expand_mask; + bsg_expand_bitmask #( + .in_width_p(burst_size_in_words_lp) + ,.expand_p(data_mask_width_lp) + ) expand0 ( + .i(sbuf_burst_offset_decode) + ,.o(sbuf_expand_mask) + ); + + logic [ways_p-1:0][dma_data_mask_width_lp-1:0] sbuf_data_mem_w_mask; + logic [ways_p-1:0][dma_data_width_p-1:0] sbuf_data_mem_data; + logic [lg_data_mem_els_lp-1:0] sbuf_data_mem_addr; + + for (genvar i = 0 ; i < ways_p; i++) begin + assign sbuf_data_mem_data[i] = {burst_size_in_words_lp{sbuf_entry_lo.data}}; + assign sbuf_data_mem_w_mask[i] = sbuf_way_decode[i] + ? (sbuf_expand_mask & {burst_size_in_words_lp{sbuf_entry_lo.mask}}) + : '0; + end + if (burst_len_lp == 1) begin + assign sbuf_data_mem_addr = sbuf_entry_lo.addr[block_offset_width_lp+:lg_sets_lp]; + end + else if (burst_len_lp == block_size_in_words_p) begin + assign sbuf_data_mem_addr = sbuf_entry_lo.addr[lg_data_mask_width_lp+:sbuf_data_mem_addr_offset_lp]; + end + else begin + assign sbuf_data_mem_addr = sbuf_entry_lo.addr[lg_data_mask_width_lp+lg_burst_size_in_words_lp+:sbuf_data_mem_addr_offset_lp]; + end + + + // store buffer data/mask input + // + logic [data_sel_mux_els_lp-1:0][data_width_p-1:0] sbuf_data_in_mux_li; + logic [data_sel_mux_els_lp-1:0][data_mask_width_lp-1:0] sbuf_mask_in_mux_li; + logic [data_width_p-1:0] sbuf_data_in; + logic [data_mask_width_lp-1:0] sbuf_mask_in; + logic [data_width_p-1:0] snoop_or_ld_data; + logic [data_sel_mux_els_lp-1:0][data_width_p-1:0] ld_data_final_li; + logic [data_width_p-1:0] ld_data_final_lo; + + bsg_mux #( + .width_p(data_width_p) + ,.els_p(data_sel_mux_els_lp) + ) sbuf_data_in_mux ( + .data_i(sbuf_data_in_mux_li) + ,.sel_i(decode_v_r.data_size_op[0+:lg_data_sel_mux_els_lp]) + ,.data_o(sbuf_data_in) + ); + + bsg_mux #( + .width_p(data_mask_width_lp) + ,.els_p(data_sel_mux_els_lp) + ) sbuf_mask_in_mux ( + .data_i(sbuf_mask_in_mux_li) + ,.sel_i(decode_v_r.data_size_op[0+:lg_data_sel_mux_els_lp]) + ,.data_o(sbuf_mask_in) + ); + + // + // Atomic operations + // Defined only for 32/64 operations + // Data incoming from cache_pkt + logic [`BSG_MIN(data_width_p, 64)-1:0] atomic_reg_data; + // Data read from the cache line + logic [`BSG_MIN(data_width_p, 64)-1:0] atomic_mem_data; + // Result of the atomic + logic [`BSG_MIN(data_width_p, 64)-1:0] atomic_alu_result; + // Final atomic data for store buffer + logic [`BSG_MIN(data_width_p, 64)-1:0] atomic_result; + + // Shift data to high bits for operations less than 64-bits + // This allows us to share the arithmetic operators for 32/64 bit atomics + if (data_width_p >= 64) begin : atomic_64 + wire [63:0] amo32_reg_in = data_v_r[0+:32] << 32; + wire [63:0] amo64_reg_in = data_v_r[0+:64]; + assign atomic_reg_data = decode_v_r.data_size_op[0] ? amo64_reg_in : amo32_reg_in; + + wire [63:0] amo32_mem_in = ld_data_final_li[2][0+:32] << 32; + wire [63:0] amo64_mem_in = ld_data_final_li[3][0+:64]; + assign atomic_mem_data = decode_v_r.data_size_op[0] ? amo64_mem_in : amo32_mem_in; + end + else if (data_width_p >= 32) begin : atomic_32 + assign atomic_reg_data = data_v_r[0+:32]; + assign atomic_mem_data = ld_data_final_li[2]; + end + + // Atomic ALU + always_comb begin + // This logic was confirmed not to synthesize unsupported operators in + // Synopsys DC O-2018.06-SP4 + unique casez({amo_support_p[decode_v_r.amo_subop], decode_v_r.amo_subop}) + {1'b1, e_cache_amo_swap}: atomic_alu_result = atomic_reg_data; + {1'b1, e_cache_amo_and }: atomic_alu_result = atomic_reg_data & atomic_mem_data; + {1'b1, e_cache_amo_or }: atomic_alu_result = atomic_reg_data | atomic_mem_data; + {1'b1, e_cache_amo_xor }: atomic_alu_result = atomic_reg_data ^ atomic_mem_data; + {1'b1, e_cache_amo_add }: atomic_alu_result = atomic_reg_data + atomic_mem_data; + {1'b1, e_cache_amo_min }: atomic_alu_result = + ($signed(atomic_reg_data) < $signed(atomic_mem_data)) ? atomic_reg_data : atomic_mem_data; + {1'b1, e_cache_amo_max }: atomic_alu_result = + ($signed(atomic_reg_data) > $signed(atomic_mem_data)) ? atomic_reg_data : atomic_mem_data; + {1'b1, e_cache_amo_minu}: atomic_alu_result = + (atomic_reg_data < atomic_mem_data) ? atomic_reg_data : atomic_mem_data; + {1'b1, e_cache_amo_maxu}: atomic_alu_result = + (atomic_reg_data > atomic_mem_data) ? atomic_reg_data : atomic_mem_data; + // Noisily fail in simulation if an unsupported AMO operation is requested + {1'b0, 4'b???? }: atomic_alu_result = `BSG_UNDEFINED_IN_SIM(0); + default: atomic_alu_result = '0; + endcase + end + + // Shift data from high bits for operations less than 64-bits + if (data_width_p >= 64) begin : fi + wire [63:0] amo32_out = atomic_alu_result >> 32; + wire [63:0] amo64_out = atomic_alu_result; + assign atomic_result = decode_v_r.data_size_op[0] ? amo64_out : amo32_out; + end + else begin + assign atomic_result = atomic_alu_result; + end + + for (genvar i = 0; i < data_sel_mux_els_lp; i++) begin: sbuf_in_sel + localparam slice_width_lp = (8*(2**i)); + + logic [slice_width_lp-1:0] slice_data; + + // AMO computation + // AMOs are only supported for words and double words + if ((i == 2'b10) || (i == 2'b11)) begin: atomic_in_sel + assign slice_data = decode_v_r.atomic_op + ? atomic_result[0+:slice_width_lp] + : data_v_r[0+:slice_width_lp]; + end + else begin + assign slice_data = data_v_r[0+:slice_width_lp]; + end + + assign sbuf_data_in_mux_li[i] = {(data_width_p/slice_width_lp){slice_data}}; + + logic [(data_width_p/slice_width_lp)-1:0] decode_lo; + + bsg_decode #( + .num_out_p(data_width_p/slice_width_lp) + ) dec ( + .i(addr_v_r[i+:`BSG_MAX(lg_data_mask_width_lp-i,1)]) + ,.o(decode_lo) + ); + + bsg_expand_bitmask #( + .in_width_p(data_width_p/slice_width_lp) + ,.expand_p(2**i) + ) exp ( + .i(decode_lo) + ,.o(sbuf_mask_in_mux_li[i]) + ); + + end + + // store buffer data,mask input + always_comb begin + if (decode_v_r.mask_op) begin + sbuf_entry_li.data = data_v_r; + sbuf_entry_li.mask = mask_v_r; + end + else begin + sbuf_entry_li.data = sbuf_data_in; + sbuf_entry_li.mask = sbuf_mask_in; + end + end + + // track buffer + // + logic tbuf_v_li; + logic [lg_ways_lp-1:0] tbuf_way_li; + logic [addr_width_p-1:0] tbuf_addr_li; + + logic tbuf_v_lo; + logic tbuf_yumi_li; + logic [lg_ways_lp-1:0] tbuf_way_lo; + logic [addr_width_p-1:0] tbuf_addr_lo; + + logic [addr_width_p-1:0] tbuf_bypass_addr_li; + logic tbuf_bypass_v_li; + logic tbuf_full_lo; + +if (word_tracking_p) begin : tbuf_gen + bsg_cache_tbuf #( + .data_width_p(data_width_p) + ,.addr_width_p(addr_width_p) + ,.ways_p(ways_p) + ) tbuf ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.addr_i(tbuf_addr_li) + ,.way_i(tbuf_way_li) + ,.v_i(tbuf_v_li) + + ,.addr_o(tbuf_addr_lo) + ,.way_o(tbuf_way_lo) + ,.v_o(tbuf_v_lo) + ,.yumi_i(tbuf_yumi_li) + + ,.empty_o(tbuf_empty_lo) + ,.full_o(tbuf_full_lo) + + ,.bypass_addr_i(tbuf_bypass_addr_li) + ,.bypass_v_i(tbuf_bypass_v_li) + ,.bypass_track_o(bypass_track_lo) + ); +end +else begin + assign tbuf_v_lo = 1'b0; + assign tbuf_empty_lo = 1'b1; + assign tbuf_full_lo = 1'b0; + assign bypass_track_lo = 1'b0; +end + + logic [ways_p-1:0] tbuf_way_decode; + bsg_decode #( + .num_out_p(ways_p) + ) tbuf_way_demux ( + .i(tbuf_way_lo) + ,.o(tbuf_way_decode) + ); + + logic [block_size_in_words_p-1:0] tbuf_word_offset_decode; + bsg_decode #( + .num_out_p(block_size_in_words_p) + ) tbuf_wo_demux ( + .i(tbuf_addr_lo[lg_data_mask_width_lp+:lg_block_size_in_words_lp]) + ,.o(tbuf_word_offset_decode) + ); + + logic [lg_sets_lp-1:0] tbuf_track_mem_addr; + logic [ways_p-1:0][block_size_in_words_p-1:0] tbuf_track_mem_w_mask; + logic [ways_p-1:0][block_size_in_words_p-1:0] tbuf_track_mem_data; + + assign tbuf_track_mem_addr = tbuf_addr_lo[block_offset_width_lp+:lg_sets_lp]; + for (genvar i = 0 ; i < ways_p; i++) begin + assign tbuf_track_mem_data[i] = {block_size_in_words_p{1'b1}}; + assign tbuf_track_mem_w_mask[i] = tbuf_way_decode[i] ? tbuf_word_offset_decode : {block_size_in_words_p{1'b0}}; + end + + // output stage + // + logic [dma_data_width_p-1:0] ld_data_way_picked; + logic [data_width_p-1:0] ld_data_offset_picked; + logic [data_width_p-1:0] bypass_data_masked; + logic [data_width_p-1:0] ld_data_masked; + + bsg_mux #( + .width_p(dma_data_width_p) + ,.els_p(ways_p) + ) ld_data_mux ( + .data_i(ld_data_v_r) + ,.sel_i(tag_hit_way_id) + ,.data_o(ld_data_way_picked) + ); + + bsg_mux #( + .width_p(data_width_p) + ,.els_p(burst_size_in_words_lp) + ) mux00 ( + .data_i(ld_data_way_picked) + ,.sel_i(addr_v_r[lg_data_mask_width_lp+:lg_burst_size_in_words_lp]) + ,.data_o(ld_data_offset_picked) + ); + + bsg_mux_segmented #( + .segments_p(data_mask_width_lp) + ,.segment_width_p(8) + ) bypass_mux_segmented ( + .data0_i(ld_data_offset_picked) + ,.data1_i(bypass_data_lo) + ,.sel_i(bypass_mask_lo) + ,.data_o(bypass_data_masked) + ); + + + assign snoop_or_ld_data = select_snoop_data_r_lo + ? snoop_word_lo + : bypass_data_masked; + + + logic [data_width_p-1:0] expanded_mask_v; + + bsg_expand_bitmask #( + .in_width_p(data_mask_width_lp) + ,.expand_p(8) + ) mask_v_expand ( + .i(mask_v_r) + ,.o(expanded_mask_v) + ); + + assign ld_data_masked = snoop_or_ld_data & expanded_mask_v; + + // select double/word/half/byte load data + // + + for (genvar i = 0; i < data_sel_mux_els_lp; i++) begin: ld_data_sel + + logic [(8*(2**i))-1:0] byte_sel; + + bsg_mux #( + .width_p(8*(2**i)) + ,.els_p(data_width_p/(8*(2**i))) + ) byte_mux ( + .data_i(snoop_or_ld_data) + ,.sel_i(addr_v_r[i+:`BSG_MAX(lg_data_mask_width_lp-i,1)]) + ,.data_o(byte_sel) + ); + + assign ld_data_final_li[i] = + {{(data_width_p-(8*(2**i))){decode_v_r.sigext_op & byte_sel[(8*(2**i))-1]}}, byte_sel}; + + + end + + bsg_mux #( + .width_p(data_width_p) + ,.els_p(data_sel_mux_els_lp) + ) ld_data_size_mux ( + .data_i(ld_data_final_li) + ,.sel_i(decode_v_r.data_size_op[0+:lg_data_sel_mux_els_lp]) + ,.data_o(ld_data_final_lo) + ); + + // final output mux + always_comb begin + if (retval_op_v) begin + if (decode_v_r.taglv_op) begin + data_o = {{(data_width_p-2){1'b0}}, lock_v_r[addr_way_v], valid_v_r[addr_way_v]}; + end + else if (decode_v_r.tagla_op) begin + data_o = {tag_v_r[addr_way_v], {(sets_p>1){addr_index_v}}, {(block_offset_width_lp){1'b0}}}; + end + else if (decode_v_r.mask_op) begin + data_o = ld_data_masked; + end + else begin + data_o = ld_data_final_lo; + end + end + else begin + data_o = '0; + end + end + + // ctrl logic + // + assign v_o = v_v_r & (miss_v + ? miss_done_lo + : 1'b1); + + assign v_we = v_v_r + ? (v_o & yumi_i) + : 1'b1; + + // when the store buffer is full, and the TV stage is inserting another entry, + // load/atomic cannot enter tl stage. + assign sbuf_hazard = (sbuf_full_lo & (v_o & yumi_i & (decode_v_r.st_op | decode_v_r.atomic_op))) + & (v_i & (decode.ld_op | decode.atomic_op)); + + // during miss, tl pipeline cannot take next instruction when + // 1) input is tagst + // 2) miss handler is writing to tag_mem or track_mem + // 3) dma engine is writing to data_mem + // 4) tl_stage is recovering from tag_miss + // 5) DMA is evicting a block. + wire tl_ready = (miss_v + ? (~(decode.tagst_op & v_i) & ~miss_tag_mem_v_lo & ~miss_track_mem_v_lo & ~dma_data_mem_v_lo & ~recover_lo & ~dma_evict_lo) + : 1'b1) & ~sbuf_hazard; + assign tl_we = tl_ready & (v_tl_r ? v_we : 1'b1); + assign yumi_o = v_i & tl_we; + + // tag_mem + // values written by tagst command + + logic tagst_valid; + logic tagst_lock; + logic [tag_width_lp-1:0] tagst_tag; + logic tagst_write_en; + + assign tagst_valid = cache_pkt.data[data_width_p-1]; + assign tagst_lock = cache_pkt.data[data_width_p-2]; + assign tagst_tag = cache_pkt.data[0+:tag_width_lp]; + assign tagst_write_en = decode.tagst_op & yumi_o; + + logic [ways_p-1:0] addr_way_decode; + bsg_decode #( + .num_out_p(ways_p) + ) addr_way_demux ( + .i(addr_way) + ,.o(addr_way_decode) + ); + + assign tag_mem_v_li = (decode.tag_read_op & yumi_o) + | (recover_lo & decode_tl_r.tag_read_op & v_tl_r) + | miss_tag_mem_v_lo + | (decode.tagst_op & yumi_o); + + assign tag_mem_w_li = miss_v + ? (miss_tag_mem_v_lo & miss_tag_mem_w_lo) + : tagst_write_en; + + always_comb begin + if (miss_v) begin + tag_mem_addr_li = recover_lo + ? addr_index_tl + : (miss_tag_mem_v_lo ? miss_tag_mem_addr_lo : addr_index); + tag_mem_data_li = miss_tag_mem_data_lo; + tag_mem_w_mask_li = miss_tag_mem_w_mask_lo; + end + else begin + // for TAGST + tag_mem_addr_li = addr_index; + for (integer i = 0; i < ways_p; i++) begin + tag_mem_data_li[i] = {tagst_valid, tagst_lock, tagst_tag}; + tag_mem_w_mask_li[i] = {tag_info_width_lp{addr_way_decode[i]}}; + end + end + end + + // data_mem ctrl logic + // + assign data_mem_v_li = ((yumi_o & (decode.ld_op | decode.atomic_op)) + | (v_tl_r & recover_lo & (decode_tl_r.ld_op | decode_tl_r.atomic_op)) + | dma_data_mem_v_lo + | (sbuf_v_lo & sbuf_yumi_li) + ); + + assign data_mem_w_li = dma_data_mem_w_lo | (sbuf_v_lo & sbuf_yumi_li); + + assign data_mem_data_li = dma_data_mem_w_lo + ? dma_data_mem_data_lo + : sbuf_data_mem_data; + + assign data_mem_addr_li = recover_lo + ? recover_data_mem_addr + : (dma_data_mem_v_lo + ? dma_data_mem_addr_lo + : (((decode.ld_op | decode.atomic_op) & yumi_o) + ? ld_data_mem_addr + : sbuf_data_mem_addr)); + + assign data_mem_w_mask_li = dma_data_mem_w_lo + ? dma_data_mem_w_mask_lo + : sbuf_data_mem_w_mask; + + + // track_mem ctrl logic + assign track_mem_v_li = ((yumi_o & (decode.ld_op | decode.atomic_op | partial_st)) + | (v_tl_r & recover_lo & (decode_tl_r.ld_op | decode_tl_r.atomic_op | partial_st_tl)) + | miss_track_mem_v_lo + | (tbuf_v_lo & tbuf_yumi_li) + ); + + assign track_mem_w_li = miss_track_mem_v_lo + ? miss_track_mem_w_lo + : (tbuf_v_lo & tbuf_yumi_li); + + assign track_mem_data_li = miss_track_mem_v_lo + ? miss_track_mem_data_lo + : tbuf_track_mem_data; + + assign track_mem_w_mask_li = miss_track_mem_v_lo + ? miss_track_mem_w_mask_lo + : tbuf_track_mem_w_mask; + + assign track_mem_addr_li = recover_lo + ? addr_index_tl + : (miss_track_mem_v_lo + ? miss_track_mem_addr_lo + : (((decode.ld_op | decode.atomic_op | partial_st) & yumi_o) + ? addr_index + : tbuf_track_mem_addr)); + + // stat_mem ctrl logic + // TAGST clears the stat_info as it exits tv stage. + // If it's load or store, and there is a hit, it updates the dirty bits and LRU. + // If there is a miss, stat_mem may be modified by the miss handler. + + logic [ways_p-2:0] plru_decode_data_lo; + logic [ways_p-2:0] plru_decode_mask_lo; + + bsg_lru_pseudo_tree_decode #( + .ways_p(ways_p) + ) plru_decode ( + .way_id_i(tag_hit_way_id) + ,.data_o(plru_decode_data_lo) + ,.mask_o(plru_decode_mask_lo) + ); + + always_comb begin + if (miss_v) begin + stat_mem_v_li = miss_stat_mem_v_lo; + stat_mem_w_li = miss_stat_mem_w_lo; + stat_mem_addr_li = miss_stat_mem_addr_lo; // essentially same as addr_index_v + stat_mem_data_li = miss_stat_mem_data_lo; + stat_mem_w_mask_li = miss_stat_mem_w_mask_lo; + end + else begin + stat_mem_v_li = ((decode_v_r.st_op | decode_v_r.ld_op | decode_v_r.tagst_op | decode_v_r.atomic_op) & v_o & yumi_i); + stat_mem_w_li = ((decode_v_r.st_op | decode_v_r.ld_op | decode_v_r.tagst_op | decode_v_r.atomic_op) & v_o & yumi_i); + stat_mem_addr_li = addr_index_v; + + if (decode_v_r.tagst_op) begin + // for TAGST + stat_mem_data_li.dirty = {ways_p{1'b0}}; + stat_mem_data_li.lru_bits = {(ways_p-1){1'b0}}; + stat_mem_w_mask_li.dirty = {ways_p{1'b1}}; + stat_mem_w_mask_li.lru_bits = {(ways_p-1){1'b1}}; + end + else begin + // for LD, ST + stat_mem_data_li.dirty = {ways_p{decode_v_r.st_op | decode_v_r.atomic_op}}; + stat_mem_data_li.lru_bits = plru_decode_data_lo; + stat_mem_w_mask_li.dirty = {ways_p{decode_v_r.st_op | decode_v_r.atomic_op}} & tag_hit_v; + stat_mem_w_mask_li.lru_bits = plru_decode_mask_lo; + end + end + end + + + // store buffer + // + assign sbuf_v_li = (decode_v_r.st_op | decode_v_r.atomic_op) & v_o & yumi_i; + assign sbuf_entry_li.way_id = miss_v ? chosen_way_lo : tag_hit_way_id; + assign sbuf_entry_li.addr = addr_v_r; + // store buffer can write to dmem when + // 1) there is valid entry in store buffer. + // 2) incoming request does not read DMEM. + // 3) DMA engine is not accessing DMEM. + // 4) TL read DMEM (and bypass from sbuf), and TV is not stalled (v_we). + // During miss, the store buffer can be drained. + assign sbuf_yumi_li = sbuf_v_lo + & ~((decode.ld_op | decode.atomic_op) & yumi_o) + & (~dma_data_mem_v_lo) + & ~(v_tl_r & (decode_tl_r.ld_op | decode_tl_r.atomic_op) & (~v_we) & (~miss_v)); + + assign sbuf_bypass_addr_li = addr_tl_r; + assign sbuf_bypass_v_li = (decode_tl_r.ld_op | decode_tl_r.atomic_op) & v_tl_r & v_we; + + // track buffer + // + assign tbuf_v_li = (decode_v_r.st_op & ~partial_st_v) & v_o & yumi_i; + assign tbuf_way_li = miss_v ? chosen_way_lo : tag_hit_way_id; + assign tbuf_addr_li = addr_v_r; + // track buffer can write to track mem when + // 1) there is valid entry in track buffer. + // 2) incoming request does not read track mem. + // 3) miss handler is not accessing track mem. + // 4) TL read track mem (and bypass from tbuf), and TV is not stalled (v_we). + // During miss, the track buffer can be drained. + assign tbuf_yumi_li = tbuf_v_lo + & ~((decode.ld_op | decode.atomic_op | partial_st) & yumi_o) + & (~miss_track_mem_v_lo) + & ~(v_tl_r & (decode_tl_r.ld_op | decode_tl_r.atomic_op | partial_st_tl) & (~v_we) & (~miss_v)); + + assign tbuf_bypass_addr_li = addr_tl_r; + assign tbuf_bypass_v_li = (decode_tl_r.ld_op | decode_tl_r.atomic_op | partial_st_tl) & v_tl_r & v_we; + + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + always_ff @ (negedge clk_i) begin + if (~reset_i) begin + if (v_v_r) begin + // check that there is no multiple hit. + assert($countones(tag_hit_v) <= 1) + else $error("[BSG_ERROR][BSG_CACHE] Multiple cache hit detected. %m, T=%t", $time); + + // check that there is at least one unlocked way in a set. + assert($countones(lock_v_r) < ways_p) + else $error("[BSG_ERROR][BSG_CACHE] There should be at least one unlocked way in a set. %m, T=%t", $time); + + // Check that client hasn't required unsupported AMO + assert(~decode_v_r.atomic_op | amo_support_p[decode_v_r.amo_subop]) + else $error("[BSG_ERROR][BSG_CACHE] Unsupported AMO OP %d received. %m, T=%t", decode.amo_subop, $time); + + assert(~decode_v_r.atomic_op || (data_width_p >= 64) || ~decode_v_r.data_size_op[0]) + else $error("[BSG_ERROR][BSG_CACHE] AMO_D performed on data_width < 64. %m T=%t", $time); + assert(~decode_v_r.atomic_op || (data_width_p >= 32)) + else $error("[BSG_ERROR][BSG_CACHE] AMO performed on data_width < 32. %m T=%t", $time); + end + end + end + + + if (debug_p) begin + always_ff @ (posedge clk_i) begin + if (v_o & yumi_i) begin + if (decode_v_r.ld_op) begin + $display(" M[%4h] == %8h // %8t", addr_v_r, data_o, $time); + end + + if (decode_v_r.st_op) begin + $display(" M[%4h] := %8h // %8t", addr_v_r, sbuf_entry_li.data, $time); + end + + end + if (tag_mem_v_li & tag_mem_w_li) begin + $display(" tag_mem_write. addr=%8h data_1=%8h data_0=%8h mask_1=%8h mask_0=%8h // %8t", + tag_mem_addr_li, + tag_mem_data_li[1+tag_width_lp+:1+tag_width_lp], + tag_mem_data_li[0+:1+tag_width_lp], + tag_mem_w_mask_li[1+tag_width_lp+:1+tag_width_lp], + tag_mem_w_mask_li[0+:1+tag_width_lp], + $time + ); + end + end + end + +`endif + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache.svh b/designs/black-parrot/src/basejump_stl/bsg_cache.svh new file mode 100644 index 0000000..9e954a9 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache.svh @@ -0,0 +1,78 @@ + // Enum values in the structs come from bsg_cache_pkg.sv + +`ifndef BSG_CACHE_VH +`define BSG_CACHE_VH + // bsg_cache_pkt_s + // + `define declare_bsg_cache_pkt_s(addr_width_mp, data_width_mp) \ + typedef struct packed { \ + bsg_cache_opcode_e opcode; \ + logic [addr_width_mp-1:0] addr; \ + logic [data_width_mp-1:0] data; \ + logic [(data_width_mp>>3)-1:0] mask; \ + } bsg_cache_pkt_s + + `define bsg_cache_pkt_width(addr_width_mp, data_width_mp) \ + ($bits(bsg_cache_opcode_e)+addr_width_mp+data_width_mp+(data_width_mp>>3)) + + // bsg_cache_dma_pkt_s + // + `define declare_bsg_cache_dma_pkt_s(addr_width_mp, mask_width_mp) \ + typedef struct packed { \ + logic write_not_read; \ + logic [addr_width_mp-1:0] addr; \ + logic [mask_width_mp-1:0] mask; \ + } bsg_cache_dma_pkt_s + + `define bsg_cache_dma_pkt_width(addr_width_mp, mask_width_mp) \ + (1+addr_width_mp+mask_width_mp) + + // tag info s + // + `define declare_bsg_cache_tag_info_s(tag_width_mp) \ + typedef struct packed { \ + logic valid; \ + logic lock; \ + logic [tag_width_mp-1:0] tag; \ + } bsg_cache_tag_info_s + + `define bsg_cache_tag_info_width(tag_width_mp) (tag_width_mp+2) + + // stat info s + // + `define declare_bsg_cache_stat_info_s(ways_mp) \ + typedef struct packed { \ + logic [ways_mp-1:0] dirty; \ + logic [ways_mp-2:0] lru_bits; \ + } bsg_cache_stat_info_s + + `define bsg_cache_stat_info_width(ways_mp) \ + (ways_mp+ways_mp-1) + + // sbuf entry s + // + `define declare_bsg_cache_sbuf_entry_s(addr_width_mp, data_width_mp, ways_mp) \ + typedef struct packed { \ + logic [addr_width_mp-1:0] addr; \ + logic [data_width_mp-1:0] data; \ + logic [(data_width_mp>>3)-1:0] mask; \ + logic [`BSG_SAFE_CLOG2(ways_mp)-1:0] way_id;\ + } bsg_cache_sbuf_entry_s + + `define bsg_cache_sbuf_entry_width(addr_width_mp, data_width_mp, ways_mp) \ + (addr_width_mp+data_width_mp+(data_width_mp>>3)+`BSG_SAFE_CLOG2(ways_mp)) + + // wormhole + // + `define declare_bsg_cache_wh_header_flit_s(wh_flit_width_mp,wh_cord_width_mp,wh_len_width_mp,wh_cid_width_mp) \ + typedef struct packed { \ + logic [wh_flit_width_mp-(wh_cord_width_mp*2)-$bits(bsg_cache_wh_opcode_e)-wh_len_width_mp-(wh_cid_width_mp*2)-1:0] unused; \ + bsg_cache_wh_opcode_e opcode; \ + logic [wh_cid_width_mp-1:0] src_cid; \ + logic [wh_cord_width_mp-1:0] src_cord; \ + logic [wh_cid_width_mp-1:0] cid; \ + logic [wh_len_width_mp-1:0] len; \ + logic [wh_cord_width_mp-1:0] cord; \ + } bsg_cache_wh_header_flit_s + +`endif // `ifndef BSG_CACHE_VH diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_buffer_queue.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_buffer_queue.sv new file mode 100644 index 0000000..cf83034 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_buffer_queue.sv @@ -0,0 +1,140 @@ +/** + * bsg_cache_buffer_queue.sv + * + * Two element buffer queue. + * + * input interface is valid-only. + * output interface is valid-yumi; + * + * el1 is head of the queue. + * el0 is the tail. + * + */ + +`include "bsg_defines.sv" + +module bsg_cache_buffer_queue + #(parameter `BSG_INV_PARAM(width_p)) + ( + input clk_i + , input reset_i + + , input v_i + , input [width_p-1:0] data_i + + , output logic v_o + , output logic [width_p-1:0] data_o + , input yumi_i + + , output logic el0_valid_o + , output logic el1_valid_o + , output logic [width_p-1:0] el0_snoop_o + , output logic [width_p-1:0] el1_snoop_o + + , output logic empty_o + , output logic full_o + ); + + // CTRL logic + logic [1:0] num_els_r; + + logic mux1_sel; + logic mux0_sel; + logic el0_enable; + logic el1_enable; + + always_comb begin + case (num_els_r) + 2'b00: begin + v_o = v_i; + empty_o = 1'b1; + full_o = 1'b0; + el0_valid_o = 1'b0; + el1_valid_o = 1'b0; + el0_enable = 1'b0; + el1_enable = v_i & ~yumi_i; + mux0_sel = 1'b0; + mux1_sel = 1'b0; + end + + 2'b01: begin + v_o = 1'b1; + empty_o = 1'b0; + full_o = 1'b0; + el0_valid_o = 1'b0; + el1_valid_o = 1'b1; + el0_enable = v_i & ~yumi_i; + el1_enable = v_i & yumi_i; + mux0_sel = 1'b0; + mux1_sel = 1'b1; + end + + 2'b10: begin + v_o = 1'b1; + empty_o = 1'b0; + full_o = 1'b1; + el0_valid_o = 1'b1; + el1_valid_o = 1'b1; + el0_enable = v_i & yumi_i; + el1_enable = yumi_i; + mux0_sel = 1'b1; + mux1_sel = 1'b1; + end + + default: begin + // this would never happen. + v_o = 1'b0; + empty_o = 1'b0; + full_o = 1'b0; + el0_valid_o = 1'b0; + el1_valid_o = 1'b0; + el0_enable = 1'b0; + el1_enable = 1'b0; + mux0_sel = 1'b0; + mux1_sel = 1'b0; + end + endcase + end + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + num_els_r <= 2'b0; + end + else begin + num_els_r <= num_els_r + v_i - (v_o & yumi_i); + end + end + + + // Data Flops + logic [width_p-1:0] el0_r, el1_r; + + always_ff @ (posedge clk_i) begin + if (el0_enable) begin + el0_r <= data_i; + end + + if (el1_enable) begin + el1_r <= mux0_sel ? el0_r : data_i; + end + end + + assign data_o = mux1_sel ? el1_r : data_i; + assign el0_snoop_o = el0_r; + assign el1_snoop_o = el1_r; + + + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @ (negedge clk_i) begin + if (~reset_i & num_els_r !== 2'bx) + assert(num_els_r != 3) else $error("bsg_cache_buffer_queue cannot hold more than 2 entries."); + + end +`endif + + +endmodule + + +`BSG_ABSTRACT_MODULE(bsg_cache_buffer_queue) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_decode.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_decode.sv new file mode 100644 index 0000000..c8a420c --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_decode.sv @@ -0,0 +1,94 @@ +/** + * bsg_cache_decode.sv + * + */ + + +`include "bsg_defines.sv" + +module bsg_cache_decode + import bsg_cache_pkg::*; + ( + input bsg_cache_opcode_e opcode_i + , output bsg_cache_decode_s decode_o + ); + + + always_comb begin + case (opcode_i) + // double + AMOSWAP_D, AMOADD_D, AMOAND_D, AMOOR_D, AMOXOR_D, + AMOMIN_D, AMOMAX_D, AMOMINU_D, AMOMAXU_D, + LD, SD, LDU: decode_o.data_size_op = 2'b11; + // word + AMOSWAP_W, AMOADD_W, AMOAND_W, AMOOR_W, AMOXOR_W, + AMOMIN_W, AMOMAX_W, AMOMINU_W, AMOMAXU_W, + LW, SW, LWU: decode_o.data_size_op = 2'b10; + // half + LH, SH, LHU: decode_o.data_size_op = 2'b01; + // byte + LB, SB, LBU: decode_o.data_size_op = 2'b00; + default: decode_o.data_size_op = 2'b00; + endcase + end + + assign decode_o.mask_op = (opcode_i == LM) | (opcode_i == SM); + + assign decode_o.sigext_op = (opcode_i == LB) + || (opcode_i == LH) + || (opcode_i == LW) + || (opcode_i == LD) + || decode_o.atomic_op; + + assign decode_o.ld_op = (opcode_i == LB) + || (opcode_i == LH) + || (opcode_i == LW) + || (opcode_i == LD) + || (opcode_i == LBU) + || (opcode_i == LHU) + || (opcode_i == LWU) + || (opcode_i == LDU) + || (opcode_i == LM); + + assign decode_o.st_op = (opcode_i == SB) + || (opcode_i == SH) + || (opcode_i == SW) + || (opcode_i == SD) + || (opcode_i == SM); + + assign decode_o.tagst_op = (opcode_i == TAGST); + assign decode_o.tagfl_op = (opcode_i == TAGFL); + assign decode_o.taglv_op = (opcode_i == TAGLV); + assign decode_o.tagla_op = (opcode_i == TAGLA); + assign decode_o.afl_op = (opcode_i == AFL); + assign decode_o.aflinv_op = (opcode_i == AFLINV); + assign decode_o.ainv_op = (opcode_i == AINV); + assign decode_o.alock_op = (opcode_i == ALOCK); + assign decode_o.aunlock_op = (opcode_i == AUNLOCK); + + assign decode_o.tag_read_op = ~decode_o.tagst_op; + + // atomic extension + always_comb begin + decode_o.atomic_op = 1'b1; + + // These subopcodes are intended to match the low 4 bits of the + // corresponding bsg_cache_pkt opcode, to simplify decoding + unique case (opcode_i) + AMOSWAP_W, AMOSWAP_D: decode_o.amo_subop = e_cache_amo_swap; + AMOADD_W, AMOADD_D: decode_o.amo_subop = e_cache_amo_add; + AMOXOR_W, AMOXOR_D: decode_o.amo_subop = e_cache_amo_xor; + AMOAND_W, AMOAND_D: decode_o.amo_subop = e_cache_amo_and; + AMOOR_W, AMOOR_D: decode_o.amo_subop = e_cache_amo_or; + AMOMIN_W, AMOMIN_D: decode_o.amo_subop = e_cache_amo_min; + AMOMAX_W, AMOMAX_D: decode_o.amo_subop = e_cache_amo_max; + AMOMINU_W, AMOMINU_D: decode_o.amo_subop = e_cache_amo_minu; + AMOMAXU_W, AMOMAXU_D: decode_o.amo_subop = e_cache_amo_maxu; + default: begin + decode_o.atomic_op = 1'b0; + decode_o.amo_subop = e_cache_amo_swap; + end + endcase + end + +endmodule diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_dma.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_dma.sv new file mode 100644 index 0000000..b0394f7 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_dma.sv @@ -0,0 +1,437 @@ +/** + * bsg_cache_dma.sv + * + * DMA engine. + * + * @author tommy + * + */ + +`include "bsg_defines.sv" +`include "bsg_cache.svh" + +module bsg_cache_dma + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(addr_width_p) + ,parameter `BSG_INV_PARAM(data_width_p) + ,parameter `BSG_INV_PARAM(block_size_in_words_p) + ,parameter `BSG_INV_PARAM(sets_p) + ,parameter `BSG_INV_PARAM(ways_p) + ,parameter `BSG_INV_PARAM(word_tracking_p) + ,parameter dma_data_width_p=data_width_p + + ,parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p) + ,parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p) + ,parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p) + ,parameter data_mask_width_lp=(data_width_p>>3) + ,parameter dma_data_mask_width_lp=(dma_data_width_p>>3) + ,parameter burst_len_lp=(block_size_in_words_p*data_width_p/dma_data_width_p) + ,parameter lg_burst_len_lp=`BSG_SAFE_CLOG2(burst_len_lp) + ,parameter burst_size_in_words_lp=(dma_data_width_p/data_width_p) + ,parameter lg_burst_size_in_words_lp=`BSG_SAFE_CLOG2(burst_size_in_words_lp) + + ,parameter data_mem_els_lp=(sets_p*burst_len_lp) + ,parameter lg_data_mem_els_lp=`BSG_SAFE_CLOG2(data_mem_els_lp) + + ,parameter bsg_cache_dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p, block_size_in_words_p) + + ,parameter debug_p=0 + ) + ( + input clk_i + ,input reset_i + + ,input bsg_cache_dma_cmd_e dma_cmd_i + ,input [lg_ways_lp-1:0] dma_way_i + ,input [addr_width_p-1:0] dma_addr_i + ,output logic done_o + + ,input track_data_we_i + + ,output logic [data_width_p-1:0] snoop_word_o + + ,output logic [bsg_cache_dma_pkt_width_lp-1:0] dma_pkt_o + ,output logic dma_pkt_v_o + ,input dma_pkt_yumi_i + + ,input [dma_data_width_p-1:0] dma_data_i + ,input dma_data_v_i + ,output logic dma_data_ready_and_o + + ,output logic [dma_data_width_p-1:0] dma_data_o + ,output logic dma_data_v_o + ,input dma_data_yumi_i + + ,output logic data_mem_v_o + ,output logic data_mem_w_o + ,output logic [lg_data_mem_els_lp-1:0] data_mem_addr_o + ,output logic [ways_p-1:0][dma_data_mask_width_lp-1:0] data_mem_w_mask_o + ,output logic [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_o + ,input [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_i + + ,input track_miss_i + ,input [ways_p-1:0][block_size_in_words_p-1:0] track_mem_data_i + + ,output logic dma_evict_o // data eviction in progress + ); + + // localparam + // + localparam counter_width_lp=`BSG_SAFE_CLOG2(burst_len_lp+1); + localparam byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3); + localparam block_offset_width_lp=(block_size_in_words_p > 1) ? byte_offset_width_lp+lg_block_size_in_words_lp : byte_offset_width_lp; + + // dma states + // + typedef enum logic [1:0] { + IDLE + ,GET_FILL_DATA + ,SEND_EVICT_DATA + } dma_state_e; + + dma_state_e dma_state_n; + dma_state_e dma_state_r; + + // dma counter + // + logic counter_clear; + logic counter_up; + logic [counter_width_lp-1:0] counter_r; + + bsg_counter_clear_up #( + .max_val_p(burst_len_lp) + ,.init_val_p('0) + ) dma_counter ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(counter_clear) + ,.up_i(counter_up) + ,.count_o(counter_r) + ); + + wire counter_fill_max = counter_r == (burst_len_lp-1); + wire counter_evict_max = counter_r == burst_len_lp; + + + // dma packet + // + `declare_bsg_cache_dma_pkt_s(addr_width_p, block_size_in_words_p); + bsg_cache_dma_pkt_s dma_pkt; + + // in fifo + // + logic in_fifo_v_lo; + logic [dma_data_width_p-1:0] in_fifo_data_lo; + logic in_fifo_yumi_li; + + bsg_fifo_1r1w_small #( + .width_p(dma_data_width_p) + ,.els_p((burst_len_lp<2) ? 2 : burst_len_lp) + ) in_fifo ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(dma_data_i) + ,.v_i(dma_data_v_i) + ,.ready_param_o(dma_data_ready_and_o) + ,.v_o(in_fifo_v_lo) + ,.data_o(in_fifo_data_lo) + ,.yumi_i(in_fifo_yumi_li) + ); + + // out fifo + // + logic out_fifo_v_li; + logic out_fifo_ready_lo; + logic [dma_data_width_p-1:0] out_fifo_data_li; + + bsg_two_fifo #( + .width_p(dma_data_width_p) + ) out_fifo ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(out_fifo_v_li) + ,.data_i(out_fifo_data_li) + ,.ready_param_o(out_fifo_ready_lo) + + ,.v_o(dma_data_v_o) + ,.data_o(dma_data_o) + ,.yumi_i(dma_data_yumi_i) + ); + + assign dma_pkt_o = dma_pkt; + + logic [ways_p-1:0] dma_way_mask; + logic [ways_p-1:0][dma_data_mask_width_lp-1:0] dma_way_mask_expanded; + logic [burst_size_in_words_lp-1:0] track_bits_offset_picked; + logic [dma_data_mask_width_lp-1:0] track_bits_offset_picked_expanded; + logic [dma_data_mask_width_lp-1:0] data_mem_w_mask_way_picked; + + bsg_decode #( + .num_out_p(ways_p) + ) dma_way_demux ( + .i(dma_way_i) + ,.o(dma_way_mask) + ); + + bsg_expand_bitmask #( + .in_width_p(ways_p) + ,.expand_p(dma_data_mask_width_lp) + ) expand0 ( + .i(dma_way_mask) + ,.o(dma_way_mask_expanded) + ); + + logic [ways_p-1:0][block_size_in_words_p-1:0] track_mem_data_r; + logic [block_size_in_words_p-1:0] track_data_way_picked; + + bsg_mux #( + .width_p(block_size_in_words_p) + ,.els_p(ways_p) + ) track_way_mux ( + .data_i(track_mem_data_r) + ,.sel_i(dma_way_i) + ,.data_o(track_data_way_picked) + ); + + bsg_mux #( + .width_p(burst_size_in_words_lp) + ,.els_p(burst_len_lp) + ) track_offset_mux ( + .data_i(track_data_way_picked) + ,.sel_i(counter_r[0+:lg_burst_len_lp]) + ,.data_o(track_bits_offset_picked) + ); + + bsg_expand_bitmask #( + .in_width_p(burst_size_in_words_lp) + ,.expand_p(data_mask_width_lp) + ) expand1 ( + .i(track_bits_offset_picked) + ,.o(track_bits_offset_picked_expanded) + ); + + assign data_mem_w_mask_way_picked = (word_tracking_p & track_miss_i) ? ~track_bits_offset_picked_expanded : {dma_data_mask_width_lp{1'b1}}; + + if (burst_len_lp == 1) begin + assign data_mem_addr_o = dma_addr_i[block_offset_width_lp+:lg_sets_lp]; + end + //else if (burst_len_lp == block_size_in_words_p) begin + // assign data_mem_addr_o = { + // dma_addr_i[block_offset_width_lp+:lg_sets_lp], + // counter_r[0+:lg_burst_len_lp] + // }; + //end + else begin + assign data_mem_addr_o = { + {(sets_p>1){dma_addr_i[block_offset_width_lp+:lg_sets_lp]}}, + counter_r[0+:lg_burst_len_lp] + }; + end + + assign data_mem_data_o = {ways_p{in_fifo_data_lo}}; + assign data_mem_w_mask_o = dma_way_mask_expanded & {ways_p{data_mem_w_mask_way_picked}}; + + bsg_mux #( + .width_p(dma_data_width_p) + ,.els_p(ways_p) + ) write_data_mux ( + .data_i(data_mem_data_i) + ,.sel_i(dma_way_i) + ,.data_o(out_fifo_data_li) + ); + + always_comb begin + done_o = 1'b0; + + dma_pkt_v_o = 1'b0; + dma_pkt.write_not_read = 1'b0; + dma_pkt.addr = { + dma_addr_i[addr_width_p-1:block_offset_width_lp], + {(block_offset_width_lp){1'b0}} + }; + dma_pkt.mask = '0; + + data_mem_v_o = 1'b0; + data_mem_w_o = 1'b0; + + in_fifo_yumi_li = 1'b0; + dma_state_n = IDLE; + out_fifo_v_li = 1'b0; + counter_clear = 1'b0; + counter_up = 1'b0; + + dma_evict_o = 1'b0; + + case (dma_state_r) + + // wait for dma_cmd from bsg_cache_miss. + // when transitioning from GET_FILL_DATA or SEND_EVICT_DATA state, + // make sure that counter is cleared to zero. + IDLE: begin + counter_clear = 1'b0; + counter_up = 1'b0; + data_mem_v_o = 1'b0; + dma_pkt_v_o = 1'b0; + dma_pkt.write_not_read = 1'b0; + done_o = 1'b0; + dma_state_n = IDLE; + + case (dma_cmd_i) + e_dma_send_fill_addr: begin + dma_pkt_v_o = 1'b1; + dma_pkt.write_not_read = 1'b0; + done_o = dma_pkt_yumi_i; + dma_state_n = IDLE; + end + + e_dma_send_evict_addr: begin + dma_pkt_v_o = 1'b1; + dma_pkt.write_not_read = 1'b1; + dma_pkt.mask = word_tracking_p ? track_data_way_picked : {block_size_in_words_p{1'b1}}; + done_o = dma_pkt_yumi_i; + dma_state_n = IDLE; + end + + e_dma_get_fill_data: begin + counter_clear = 1'b1; + dma_state_n = GET_FILL_DATA; + end + + e_dma_send_evict_data: begin + // we are reading the first word, as we are transitioning out. + // so the counter is incremented to 1. + counter_clear = 1'b1; + counter_up = 1'b1; + // When word_tracking_p is off, track_data_we_i is always zero, which means track_mem_data_r will always be 'X; + // So if word_tracking_p is off, we tie this to constant 1. + data_mem_v_o = word_tracking_p + ?(|track_bits_offset_picked) + : 1'b1; + dma_state_n = SEND_EVICT_DATA; + end + + e_dma_nop: begin + // nothing happens. + end + + default: begin + // this should never happen. + end + endcase + end + + // receive the block data from dma_data_i + // and write into data_mem word by word. + GET_FILL_DATA: begin + dma_state_n = counter_fill_max & in_fifo_v_lo + ? IDLE + : GET_FILL_DATA; + data_mem_v_o = in_fifo_v_lo; + data_mem_w_o = in_fifo_v_lo; + in_fifo_yumi_li = in_fifo_v_lo; + + counter_up = in_fifo_v_lo & ~counter_fill_max; + counter_clear = in_fifo_v_lo & counter_fill_max; + done_o = counter_fill_max & in_fifo_v_lo; + end + + // read the requested block from data_mem and send it out over + // dma_data_o word by word. + SEND_EVICT_DATA: begin + // counter_r in this context means the number of words read from + // data_mem so far. + dma_state_n = counter_evict_max & out_fifo_ready_lo + ? IDLE + : SEND_EVICT_DATA; + + counter_up = out_fifo_ready_lo & ~counter_evict_max; + counter_clear = out_fifo_ready_lo & counter_evict_max; + + out_fifo_v_li = 1'b1; + + // we only need to read words that have valid data + // for invalid words we just send the previously read word from data_mem + data_mem_v_o = out_fifo_ready_lo & ~counter_evict_max + & (word_tracking_p + ? (|track_bits_offset_picked) + : 1'b1); + + done_o = counter_evict_max & out_fifo_ready_lo; + + dma_evict_o = 1'b1; + end + + default: begin + // this should never happen, but if it does, then go back to IDLE. + dma_state_n = IDLE; + end + endcase + end + + + // snoop_word register + // As the fill data is coming in, grab the word that matches the block + // offset, so that we don't have to read the data_mem again to return the + // load data. + logic [lg_burst_size_in_words_lp-1:0] snoop_word_offset; + logic snoop_word_we; + logic [data_width_p-1:0] snoop_word_n; + + assign snoop_word_offset = dma_addr_i[byte_offset_width_lp+:lg_burst_size_in_words_lp]; + + if (burst_len_lp == 1) begin + assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo; + end + else if (burst_len_lp == block_size_in_words_p) begin + assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo + & (counter_r[0+:lg_burst_len_lp] == dma_addr_i[byte_offset_width_lp+:lg_burst_len_lp]); + end + else begin + assign snoop_word_we = (dma_state_r == GET_FILL_DATA) & in_fifo_v_lo + & (counter_r[0+:lg_burst_len_lp] == dma_addr_i[byte_offset_width_lp+lg_burst_size_in_words_lp+:lg_burst_len_lp]); + end + + + bsg_mux #( + .width_p(data_width_p) + ,.els_p(burst_size_in_words_lp) + ) snoop_mux0 ( + .data_i(in_fifo_data_lo) + ,.sel_i(snoop_word_offset) + ,.data_o(snoop_word_n) + ); + + // synopsys sync_set_reset "reset_i" + always_ff @ (posedge clk_i) begin + if (reset_i) begin + dma_state_r <= IDLE; + end + else begin + dma_state_r <= dma_state_n; + + if (snoop_word_we) begin + snoop_word_o <= snoop_word_n; + end + + if (track_data_we_i) begin + track_mem_data_r <= track_mem_data_i; + end + end + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + always_ff @ (posedge clk_i) begin + if (debug_p) begin + if (dma_pkt_v_o & dma_pkt_yumi_i) begin + $display(" DMA_PKT we:%0d addr:%8h // %8t", + dma_pkt.write_not_read, dma_pkt.addr, $time); + end + end + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_dma) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_dma_to_wormhole.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_dma_to_wormhole.sv new file mode 100644 index 0000000..aafe1bd --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_dma_to_wormhole.sv @@ -0,0 +1,343 @@ +/** + * bsg_cache_dma_to_wormhole.sv + * + * This module interfaces bsg_cache_dma to a wormhole link. + * dma_pkts come in two flavors: + * - Write packets send a wormhole header flit, then an address flit, a mask flit, then N data flits (the + * evicted data) + * - Read packets send a wormhole header flit, then an address flit, then receive + * N data flits (the fill data) asynchronously. + */ + +`include "bsg_defines.sv" +`include "bsg_noc_links.svh" +`include "bsg_cache.svh" + +module bsg_cache_dma_to_wormhole + import bsg_noc_pkg::*; + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(dma_addr_width_p) // cache addr width (byte addr) + , parameter `BSG_INV_PARAM(dma_burst_len_p) // num of data beats in dma transfer + , parameter `BSG_INV_PARAM(dma_mask_width_p) // mask width in the bsg_cache_dma_pkt_s. This should equal to the block_size_in_words_p set for bsg_cache. + + // flit width should match the cache dma width. + , parameter `BSG_INV_PARAM(wh_flit_width_p) + , parameter `BSG_INV_PARAM(wh_cid_width_p) + , parameter `BSG_INV_PARAM(wh_len_width_p) + , parameter `BSG_INV_PARAM(wh_cord_width_p) + + , parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(dma_addr_width_p, dma_mask_width_p) + , parameter wh_link_sif_width_lp=`bsg_ready_and_link_sif_width(wh_flit_width_p) + , parameter dma_data_width_lp=wh_flit_width_p + + // Whether to buffer the returning data flits. May be necessary for timing purposes + , parameter buffer_return_p = 1 + ) + ( + input clk_i + , input reset_i + + , input [dma_pkt_width_lp-1:0] dma_pkt_i + , input dma_pkt_v_i + , output dma_pkt_yumi_o + + , output logic [dma_data_width_lp-1:0] dma_data_o + , output logic dma_data_v_o + , input dma_data_ready_and_i + + , input [dma_data_width_lp-1:0] dma_data_i + , input dma_data_v_i + , output logic dma_data_yumi_o + + , input [wh_link_sif_width_lp-1:0] wh_link_sif_i + , output logic [wh_link_sif_width_lp-1:0] wh_link_sif_o + + , input [wh_cord_width_p-1:0] my_wh_cord_i + , input [wh_cord_width_p-1:0] dest_wh_cord_i + , input [wh_cid_width_p-1:0] my_wh_cid_i + , input [wh_cid_width_p-1:0] dest_wh_cid_i + ); + + `declare_bsg_cache_dma_pkt_s(dma_addr_width_p, dma_mask_width_p); + `declare_bsg_ready_and_link_sif_s(wh_flit_width_p, wh_link_sif_s); + wh_link_sif_s wh_link_sif_in; + wh_link_sif_s wh_link_sif_out; + assign wh_link_sif_in = wh_link_sif_i; + assign wh_link_sif_o = wh_link_sif_out; + + // dma pkt fifo + logic dma_pkt_ready_lo; + logic dma_pkt_v_lo; + logic dma_pkt_yumi_li; + bsg_cache_dma_pkt_s dma_pkt_lo; + + // two fifo is needed here to avoid bubble between consecutive dma_pkts, + // which can occur with during a writeback->fill operation + bsg_two_fifo #( + .width_p(dma_pkt_width_lp) + ) dma_pkt_fifo ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(dma_pkt_v_i) + ,.data_i(dma_pkt_i) + ,.ready_param_o(dma_pkt_ready_lo) + + ,.v_o(dma_pkt_v_lo) + ,.data_o(dma_pkt_lo) + ,.yumi_i(dma_pkt_yumi_li) + ); + + assign dma_pkt_yumi_o = dma_pkt_ready_lo & dma_pkt_v_i; + + // FIFO for wormhole flits coming back to vcache. + logic return_fifo_v_lo; + logic [wh_flit_width_p-1:0] return_fifo_data_lo; + logic return_fifo_ready_li, return_fifo_yumi_li; + + if (buffer_return_p) begin : br + bsg_two_fifo #( + .width_p(wh_flit_width_p) + ) return_fifo ( + .clk_i (clk_i) + ,.reset_i (reset_i) + + ,.v_i (wh_link_sif_in.v) + ,.data_i (wh_link_sif_in.data) + ,.ready_param_o (wh_link_sif_out.ready_and_rev) + + ,.v_o (return_fifo_v_lo) + ,.data_o (return_fifo_data_lo) + ,.yumi_i (return_fifo_yumi_li) + ); + assign return_fifo_yumi_li = return_fifo_ready_li & return_fifo_v_lo; + end else begin : nbr + assign return_fifo_v_lo = wh_link_sif_in.v; + assign return_fifo_data_lo = wh_link_sif_in.data; + assign wh_link_sif_out.ready_and_rev = return_fifo_ready_li; + assign return_fifo_yumi_li = wh_link_sif_out.ready_and_rev & wh_link_sif_in.v; + end + + + // counter + localparam count_width_lp = `BSG_SAFE_CLOG2(dma_burst_len_p); + logic send_clear_li; + logic send_up_li; + logic [count_width_lp-1:0] send_count_lo; + + bsg_counter_clear_up #( + .max_val_p(dma_burst_len_p-1) + ,.init_val_p(0) + ) send_count ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(send_clear_li) + ,.up_i(send_up_li) + ,.count_o(send_count_lo) + ); + + // send FSM + enum logic [2:0] { + SEND_RESET + , SEND_READY + , SEND_ADDR + , SEND_MASK + , SEND_DATA + } send_state_n, send_state_r; + + + // Check if mask bits are all 1. + wire mask_all_one = &dma_pkt_lo.mask; + + // Make a header flit. + `declare_bsg_cache_wh_header_flit_s(wh_flit_width_p,wh_cord_width_p,wh_len_width_p,wh_cid_width_p); + + bsg_cache_wh_header_flit_s header_flit; + assign header_flit.unused = '0; + assign header_flit.opcode = dma_pkt_lo.write_not_read + ? (mask_all_one + ? e_cache_wh_write_non_masked + : e_cache_wh_write_masked) + : e_cache_wh_read; + assign header_flit.src_cid = my_wh_cid_i; + assign header_flit.src_cord = my_wh_cord_i; + assign header_flit.len = dma_pkt_lo.write_not_read + ? (mask_all_one + ? wh_len_width_p'(1+dma_burst_len_p) // header + addr + data + : wh_len_width_p'(2+dma_burst_len_p)) // header + addr + mask + data + : wh_len_width_p'(1); // header + addr + assign header_flit.cord = dest_wh_cord_i; + assign header_flit.cid = dest_wh_cid_i; + + + always_comb begin + + send_state_n = send_state_r; + dma_pkt_yumi_li = 1'b0; + send_clear_li = 1'b0; + send_up_li = 1'b0; + wh_link_sif_out.v = 1'b0; + wh_link_sif_out.data = dma_data_i; + dma_data_yumi_o = 1'b0; + + case (send_state_r) + SEND_RESET: begin + send_state_n = SEND_READY; + end + + SEND_READY: begin + // send header + wh_link_sif_out.data = header_flit; + if (dma_pkt_v_lo) begin + wh_link_sif_out.v = 1'b1; + send_state_n = (wh_link_sif_in.ready_and_rev) + ? SEND_ADDR + : SEND_READY; + end + end + + SEND_ADDR: begin + wh_link_sif_out.data = wh_flit_width_p'(dma_pkt_lo.addr); + if (dma_pkt_v_lo) begin + wh_link_sif_out.v = 1'b1; + + // If it's read, dequeue dma_pkt. + // If it's masked write, don't dequeue yet, because it still needs to send the mask flit. + // If it's non-masked write, dequeue it . + dma_pkt_yumi_li = dma_pkt_lo.write_not_read + ? (mask_all_one + ? wh_link_sif_in.ready_and_rev // non-masked write + : 1'b0) // masked write + : wh_link_sif_in.ready_and_rev; + + send_state_n = wh_link_sif_in.ready_and_rev + ? (dma_pkt_lo.write_not_read + ? (mask_all_one ? SEND_DATA : SEND_MASK) + : SEND_READY) + : SEND_ADDR; + end + end + + SEND_MASK: begin + wh_link_sif_out.data = wh_flit_width_p'(dma_pkt_lo.mask); + if (dma_pkt_v_lo) begin + wh_link_sif_out.v = 1'b1; + dma_pkt_yumi_li = wh_link_sif_in.ready_and_rev; + send_state_n = wh_link_sif_in.ready_and_rev + ? SEND_DATA + : SEND_MASK; + end + end + + SEND_DATA: begin + wh_link_sif_out.data = dma_data_i; + if (dma_data_v_i) begin + wh_link_sif_out.v = 1'b1; + dma_data_yumi_o = wh_link_sif_in.ready_and_rev & wh_link_sif_out.v; + send_up_li = dma_data_yumi_o & (send_count_lo != dma_burst_len_p-1); + send_clear_li = dma_data_yumi_o & (send_count_lo == dma_burst_len_p-1); + send_state_n = send_clear_li + ? SEND_READY + : SEND_DATA; + end + end + + // should never happen + default: begin + send_state_n = SEND_READY; + end + endcase + end + + + + + // receiver FSM + logic recv_clear_li; + logic recv_up_li; + logic [count_width_lp-1:0] recv_count_lo; + + bsg_counter_clear_up #( + .max_val_p(dma_burst_len_p-1) + ,.init_val_p(0) + ) recv_count ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(recv_clear_li) + ,.up_i(recv_up_li) + ,.count_o(recv_count_lo) + ); + + typedef enum logic [1:0] { + RECV_RESET + , RECV_READY + , RECV_DATA + } recv_state_e; + + recv_state_e recv_state_r, recv_state_n; + + + always_comb begin + recv_state_n = recv_state_r; + recv_clear_li = 1'b0; + recv_up_li = 1'b0; + return_fifo_ready_li = 1'b0; + dma_data_v_o = 1'b0; + dma_data_o = return_fifo_data_lo; + + case (recv_state_r) + RECV_RESET: begin + recv_state_n = RECV_READY; + end + + RECV_READY: begin + return_fifo_ready_li = 1'b1; + recv_state_n = return_fifo_yumi_li + ? RECV_DATA + : RECV_READY; + end + + RECV_DATA: begin + return_fifo_ready_li = dma_data_ready_and_i; + dma_data_v_o = return_fifo_v_lo; + recv_up_li = return_fifo_yumi_li & (recv_count_lo != dma_burst_len_p-1); + recv_clear_li = return_fifo_yumi_li & (recv_count_lo == dma_burst_len_p-1); + recv_state_n = recv_clear_li + ? RECV_READY + : RECV_DATA; + end + + default: begin + recv_state_n = RECV_READY; + end + endcase + end + + + + + // sequential logic + // synopsys sync_set_reset "reset_i" + always_ff @ (posedge clk_i) begin + if (reset_i) begin + send_state_r <= SEND_RESET; + recv_state_r <= RECV_RESET; + end + else begin + send_state_r <= send_state_n; + recv_state_r <= recv_state_n; + end + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (wh_flit_width_p != dma_data_width_lp) + $error("WH flit width must be equal to DMA data width"); + if (wh_flit_width_p < dma_addr_width_p) + $error("WH flit width must be larger than address width"); + if (wh_len_width_p < `BSG_WIDTH(dma_burst_len_p+1)) + $error("WH len width %d must be large enough to hold the dma transfer size %d", wh_len_width_p, `BSG_WIDTH(dma_burst_len_p+1)); +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_dma_to_wormhole) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_miss.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_miss.sv new file mode 100644 index 0000000..5e5d68b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_miss.sv @@ -0,0 +1,593 @@ +/** + * bsg_cache_miss.sv + * + * miss handling unit. + * + * @author tommy + * + */ + +`include "bsg_defines.sv" +`include "bsg_cache.svh" + +module bsg_cache_miss + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(addr_width_p) + ,parameter `BSG_INV_PARAM(data_width_p) + ,parameter `BSG_INV_PARAM(block_size_in_words_p) + ,parameter `BSG_INV_PARAM(sets_p) + ,parameter `BSG_INV_PARAM(ways_p) + ,parameter `BSG_INV_PARAM(word_tracking_p) + + ,parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p) + ,parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p) + ,parameter data_mask_width_lp=(data_width_p>>3) + ,parameter lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) + ,parameter block_offset_width_lp=(block_size_in_words_p > 1) ? lg_data_mask_width_lp+lg_block_size_in_words_lp : lg_data_mask_width_lp + ,parameter tag_offset_lp=(sets_p == 1) ? block_offset_width_lp : block_offset_width_lp+lg_sets_lp + ,parameter tag_width_lp=addr_width_p-tag_offset_lp + ,parameter tag_info_width_lp=`bsg_cache_tag_info_width(tag_width_lp) + ,parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p) + ,parameter stat_info_width_lp=`bsg_cache_stat_info_width(ways_p) + ) + ( + input clk_i + ,input reset_i + + // from tv stage + ,input miss_v_i + ,input track_miss_i + ,input bsg_cache_decode_s decode_v_i + ,input [addr_width_p-1:0] addr_v_i + ,input [data_mask_width_lp-1:0] mask_v_i + ,input [ways_p-1:0][tag_width_lp-1:0] tag_v_i + ,input [ways_p-1:0] valid_v_i + ,input [ways_p-1:0] lock_v_i + ,input [ways_p-1:0] tag_hit_v_i + ,input [lg_ways_lp-1:0] tag_hit_way_id_i + ,input tag_hit_found_i + + // from store buffer + ,input sbuf_empty_i + + // from track buffer + ,input tbuf_empty_i + + // to dma engine + ,output bsg_cache_dma_cmd_e dma_cmd_o + ,output logic [lg_ways_lp-1:0] dma_way_o + ,output logic [addr_width_p-1:0] dma_addr_o + ,input dma_done_i + + // to dma engine for flopping track_mem's read data + // used to avoid clk-to-q timing from memory + ,output logic track_data_we_o + + // from stat_mem + ,input [stat_info_width_lp-1:0] stat_info_i + + // to stat_mem + ,output logic stat_mem_v_o + ,output logic stat_mem_w_o + ,output logic [lg_sets_lp-1:0] stat_mem_addr_o + ,output logic [stat_info_width_lp-1:0] stat_mem_data_o + ,output logic [stat_info_width_lp-1:0] stat_mem_w_mask_o + + // to tag_mem + ,output logic tag_mem_v_o + ,output logic tag_mem_w_o + ,output logic [lg_sets_lp-1:0] tag_mem_addr_o + ,output logic [ways_p-1:0][tag_info_width_lp-1:0] tag_mem_data_o + ,output logic [ways_p-1:0][tag_info_width_lp-1:0] tag_mem_w_mask_o + + // to track mem + ,output logic track_mem_v_o + ,output logic track_mem_w_o + ,output logic [lg_sets_lp-1:0] track_mem_addr_o + ,output logic [ways_p-1:0][block_size_in_words_p-1:0] track_mem_w_mask_o + ,output logic [ways_p-1:0][block_size_in_words_p-1:0] track_mem_data_o + + // to pipeline + ,output logic done_o + ,output logic recover_o + ,output logic [lg_ways_lp-1:0] chosen_way_o + ,output logic select_snoop_data_r_o + + ,input ack_i + ); + + // stat/tag info + // + `declare_bsg_cache_tag_info_s(tag_width_lp); + `declare_bsg_cache_stat_info_s(ways_p); + + bsg_cache_stat_info_s stat_info_in; + assign stat_info_in = stat_info_i; + + bsg_cache_tag_info_s [ways_p-1:0] tag_mem_data_out, tag_mem_w_mask_out; + bsg_cache_stat_info_s stat_mem_data_out, stat_mem_w_mask_out; + + assign tag_mem_data_o = tag_mem_data_out; + assign stat_mem_data_o = stat_mem_data_out; + + assign tag_mem_w_mask_o = tag_mem_w_mask_out; + assign stat_mem_w_mask_o = stat_mem_w_mask_out; + + // Find the way that is invalid. + // + logic [lg_ways_lp-1:0] invalid_way_id; + logic invalid_exist; + + bsg_priority_encode #( + .width_p(ways_p) + ,.lo_to_hi_p(1) + ) invalid_way_pe ( + .i(~valid_v_i & ~lock_v_i) // invalid and unlocked + ,.addr_o(invalid_way_id) + ,.v_o(invalid_exist) + ); + + // miss handler FSM + // + typedef enum logic [3:0] { + START + ,FLUSH_OP + ,LOCK_OP + ,SEND_EVICT_ADDR + ,SEND_FILL_ADDR + ,SEND_EVICT_DATA + ,GET_FILL_DATA + ,STORE_TAG_MISS + ,STORE_TAG_MISS_ALLOCATE + ,RECOVER + ,DONE + } miss_state_e; + + miss_state_e miss_state_r; + miss_state_e miss_state_n; + logic [lg_ways_lp-1:0] chosen_way_r, chosen_way_n; + logic [lg_ways_lp-1:0] flush_way_r, flush_way_n; + logic select_snoop_data_r, select_snoop_data_n; + + + // for flush/inv ops, go to FLUSH_OP. + // for AUNLOCK, or ALOCK with tag hit, to go LOCK_OP. + // for store tag miss with data size equal or bigger than a word, do not fetch cache line word tracking is enables + wire goto_flush_op = decode_v_i.tagfl_op| decode_v_i.ainv_op| decode_v_i.afl_op| decode_v_i.aflinv_op; + wire goto_lock_op = decode_v_i.aunlock_op | (decode_v_i.alock_op & tag_hit_found_i); + wire full_word_op = decode_v_i.mask_op + ? (&mask_v_i) + : (decode_v_i.data_size_op >= lg_data_mask_width_lp); + wire st_tag_miss_op = word_tracking_p ? (decode_v_i.st_op & full_word_op & ~tag_hit_found_i) : 1'b0; + + logic [tag_width_lp-1:0] addr_tag_v; + logic [lg_sets_lp-1:0] addr_index_v; + logic [lg_ways_lp-1:0] addr_way_v; + logic [lg_block_size_in_words_lp-1:0] addr_block_offset_v; + + assign addr_index_v + = addr_v_i[block_offset_width_lp+:lg_sets_lp]; + assign addr_tag_v + = addr_v_i[tag_offset_lp+:tag_width_lp]; + assign addr_way_v + = addr_v_i[tag_offset_lp+:lg_ways_lp]; + assign addr_block_offset_v + = addr_v_i[lg_data_mask_width_lp+:lg_block_size_in_words_lp]; + + assign stat_mem_addr_o = addr_index_v; + assign tag_mem_addr_o = addr_index_v; + assign track_mem_addr_o = addr_index_v; + + assign chosen_way_o = chosen_way_r; + + assign dma_way_o = goto_flush_op + ? flush_way_r + : chosen_way_r; + + // chosen way lru decode + // + logic [ways_p-2:0] chosen_way_lru_data; + logic [ways_p-2:0] chosen_way_lru_mask; + + bsg_lru_pseudo_tree_decode #( + .ways_p(ways_p) + ) chosen_way_lru_decode ( + .way_id_i(chosen_way_r) + ,.data_o(chosen_way_lru_data) + ,.mask_o(chosen_way_lru_mask) + ); + + // backup LRU + // When the LRU way designated by the stats_mem_info is locked, a backup way is required for + // cache line replacement. In the current design, bsg_lru_pseudo_tree_backup takes the way with + // the shortest distance from the locked LRU way in the tree, as the backup option by overriding + // some of the LRU bits, so that it avoids "LRU trap" from insufficient update on the LRU bits. + // For now, there is not hardware logic to detect and handle the issue that all the ways in the + // same set are lock. And it is a programmer's responsibility to make sure that there is at least + // one unlock way in a set at any time. + // For future backup LRU enhancement project: For pseudo tree LRU algorithm, an efficient backup + // LRU algorithm should update the active LRU bits as much as possible, otherwise, it is very possible + // that the LRU way falls back to the same locked way soon and then forms "LRU trap" + logic [lg_ways_lp-1:0] lru_way_id; + + logic [ways_p-2:0] modify_mask_lo; + logic [ways_p-2:0] modify_data_lo; + logic [ways_p-2:0] modified_lru_bits; + + bsg_lru_pseudo_tree_backup #( + .ways_p(ways_p) + ) backup_lru ( + .disabled_ways_i(lock_v_i) + ,.modify_mask_o(modify_mask_lo) + ,.modify_data_o(modify_data_lo) + ); + + bsg_mux_bitwise #( + .width_p(ways_p-1) + ) lru_bit_mux ( + .data0_i(stat_info_in.lru_bits) + ,.data1_i(modify_data_lo) + ,.sel_i(modify_mask_lo) + ,.data_o(modified_lru_bits) + ); + + bsg_lru_pseudo_tree_encode #( + .ways_p(ways_p) + ) lru_encode ( + .lru_i(modified_lru_bits) + ,.way_id_o(lru_way_id) + ); + + // chosen way demux + // + logic [ways_p-1:0] chosen_way_decode; + bsg_decode #( + .num_out_p(ways_p) + ) chosen_way_demux ( + .i(chosen_way_n) + ,.o(chosen_way_decode) + ); + + // flush way demux + logic [ways_p-1:0] addr_way_v_decode; + bsg_decode #( + .num_out_p(ways_p) + ) addr_way_v_demux ( + .i(addr_way_v) + ,.o(addr_way_v_decode) + ); + + logic [ways_p-1:0] flush_way_decode; + assign flush_way_decode = decode_v_i.tagfl_op + ? addr_way_v_decode + : tag_hit_v_i; + + assign select_snoop_data_r_o = select_snoop_data_r; + + always_comb begin + + stat_mem_v_o = 1'b0; + stat_mem_w_o = 1'b0; + stat_mem_data_out = '0; + stat_mem_w_mask_out = '0; + + tag_mem_v_o = 1'b0; + tag_mem_w_o = 1'b0; + tag_mem_data_out = '0; + tag_mem_w_mask_out = '0; + + track_mem_v_o = 1'b0; + track_mem_w_o = 1'b0; + track_mem_data_o = '0; + track_mem_w_mask_o = '0; + + chosen_way_n = chosen_way_r; + flush_way_n = flush_way_r; + + dma_addr_o = '0; + dma_cmd_o = e_dma_nop; + + recover_o = '0; + done_o = '0; + + select_snoop_data_n = select_snoop_data_r; + + case (miss_state_r) + + // miss handler waits in this state, until the miss is detected in tv + // stage. + START: begin + stat_mem_v_o = (miss_v_i & sbuf_empty_i & tbuf_empty_i); + track_mem_v_o = word_tracking_p ? (miss_v_i & sbuf_empty_i & tbuf_empty_i) : 1'b0; + miss_state_n = (miss_v_i & sbuf_empty_i & tbuf_empty_i) + ? (goto_flush_op + ? FLUSH_OP + : (goto_lock_op + ? LOCK_OP + : (st_tag_miss_op + ? STORE_TAG_MISS + : SEND_FILL_ADDR))) + : START; + end + + // Send out the missing cache block address (to read). + // Choose a block to replace/fill. + // If the chosen block is dirty, then take evict route. + SEND_FILL_ADDR: begin + + // Replacement Policy: + // If an invalid and unlocked way exists, pick that. + // If not, pick the LRU way. But if the LRU way designated + // by stats_mem_info is locked, it will be overridden by + // the bsg_lru_pseudo_tree_backup. + // On track miss, the chosen way is the tag hit way. + chosen_way_n = track_miss_i ? tag_hit_way_id_i : (invalid_exist ? invalid_way_id : lru_way_id); + + dma_cmd_o = e_dma_send_fill_addr; + dma_addr_o = { + addr_tag_v, + {(sets_p>1){addr_index_v}}, + {(block_offset_width_lp){1'b0}} + }; + + // if the chosen way is dirty and valid, then evict. + miss_state_n = dma_done_i + ? ((~track_miss_i & stat_info_in.dirty[chosen_way_n] & valid_v_i[chosen_way_n]) + ? SEND_EVICT_ADDR + : GET_FILL_DATA) + : SEND_FILL_ADDR; + end + + // Handling the cases for TAGFL, AINV, AFL, AFLINV. + FLUSH_OP: begin + + // for TAGFL, pick whichever way set by the addr input. + // Otherwise, pick the way with the tag hit. + flush_way_n = decode_v_i.tagfl_op + ? addr_way_v + : tag_hit_way_id_i; + + // Clear the dirty bit for the chosen set. + // LRU bit does not need to be updated. + stat_mem_v_o = 1'b1; + stat_mem_w_o = 1'b1; + stat_mem_data_out.dirty = {ways_p{1'b0}}; + stat_mem_data_out.lru_bits = {(ways_p-1){1'b0}}; + stat_mem_w_mask_out.dirty = flush_way_decode; + stat_mem_w_mask_out.lru_bits = {(ways_p-1){1'b0}}; + + // If it's invalidate op, then clear the valid bit for the chosen way. + // Otherwise, do not touch the valid bits. + tag_mem_v_o = 1'b1; + tag_mem_w_o = 1'b1; + + for (integer i = 0; i < ways_p; i++) begin + tag_mem_data_out[i].valid = 1'b0; + tag_mem_data_out[i].lock = 1'b0; + tag_mem_data_out[i].tag = {tag_width_lp{1'b0}}; + tag_mem_w_mask_out[i].valid = (decode_v_i.ainv_op | decode_v_i.aflinv_op) & flush_way_decode[i]; + tag_mem_w_mask_out[i].lock = (decode_v_i.ainv_op | decode_v_i.aflinv_op) & flush_way_decode[i]; + tag_mem_w_mask_out[i].tag = {tag_width_lp{1'b0}}; + end + + // If it's not AINV, and the chosen set is dirty and valid, evict the + // block. + miss_state_n = (~decode_v_i.ainv_op & stat_info_in.dirty[flush_way_n] & valid_v_i[flush_way_n]) + ? SEND_EVICT_ADDR + : RECOVER; + end + + // handling AUNLOCK, and ALOCK with line not missing. + LOCK_OP: begin + tag_mem_v_o = 1'b1; + tag_mem_w_o = 1'b1; + + for (integer i = 0; i < ways_p; i++) begin + tag_mem_data_out[i].valid = 1'b0; + tag_mem_data_out[i].lock = decode_v_i.alock_op; + tag_mem_data_out[i].tag = {tag_width_lp{1'b0}}; + tag_mem_w_mask_out[i].valid = 1'b0; + tag_mem_w_mask_out[i].lock = tag_hit_v_i[i]; + tag_mem_w_mask_out[i].tag = {tag_width_lp{1'b0}}; + end + + miss_state_n = RECOVER; + end + + // Send out the block addr for eviction, before initiating the eviction. + SEND_EVICT_ADDR: begin + dma_cmd_o = e_dma_send_evict_addr; + dma_addr_o = { + tag_v_i[dma_way_o], + {(sets_p>1){addr_index_v}}, + {(block_offset_width_lp){1'b0}} + }; + + miss_state_n = dma_done_i + ? SEND_EVICT_DATA + : SEND_EVICT_ADDR; + end + + // Set the DMA engine to evict the dirty block. + // For the flush ops, go straight to RECOVER. + SEND_EVICT_DATA: begin + dma_cmd_o = e_dma_send_evict_data; + dma_addr_o = { + tag_v_i[dma_way_o], + {(sets_p>1){addr_index_v}}, + {(block_offset_width_lp){1'b0}} + }; + + // set stat mem entry on store tag miss. + stat_mem_v_o = dma_done_i & st_tag_miss_op; + stat_mem_w_o = 1'b1; + stat_mem_data_out.dirty = {ways_p{1'b1}}; + stat_mem_data_out.lru_bits = chosen_way_lru_data; + stat_mem_w_mask_out.dirty = chosen_way_decode; + stat_mem_w_mask_out.lru_bits = chosen_way_lru_mask; + + // set the tag and the valid bit to 1'b1 for the chosen way on store tag miss. + tag_mem_v_o = dma_done_i & st_tag_miss_op; + tag_mem_w_o = 1'b1; + + for (integer i = 0; i < ways_p; i++) begin + tag_mem_data_out[i].tag = addr_tag_v; + tag_mem_data_out[i].lock = decode_v_i.alock_op; + tag_mem_data_out[i].valid = 1'b1; + tag_mem_w_mask_out[i].tag = {tag_width_lp{chosen_way_decode[i]}}; + tag_mem_w_mask_out[i].lock = chosen_way_decode[i]; + tag_mem_w_mask_out[i].valid = chosen_way_decode[i]; + end + + // set track bits to zero for the chosen way on store tag miss. + track_mem_v_o = dma_done_i & st_tag_miss_op; + track_mem_w_o = 1'b1; + for (integer i = 0; i < ways_p; i++) begin + track_mem_data_o[i] = {block_size_in_words_p{1'b0}}; + track_mem_w_mask_o[i] = {block_size_in_words_p{chosen_way_decode[i]}}; + end + + miss_state_n = dma_done_i + ? ((decode_v_i.tagfl_op| decode_v_i.aflinv_op| decode_v_i.afl_op | st_tag_miss_op) ? RECOVER : GET_FILL_DATA) + : SEND_EVICT_DATA; + end + + // Set the DMA engine to start writing the new block to the data_mem. + // Do not start until the store buffer is empty. + GET_FILL_DATA: begin + dma_cmd_o = e_dma_get_fill_data; + dma_addr_o = { + addr_tag_v, + {(sets_p>1){addr_index_v}}, + {(block_size_in_words_p > 1){addr_block_offset_v}}, // used for snoop data in dma. + {(lg_data_mask_width_lp){1'b0}} + }; + + // For store tag miss, set the dirty bit for the chosen way. + // For load tag miss, clear the dirty bit for the chosen way. + // For track miss, do not touch the dirty bit for the chosen way. + // Set the lru_bits, so that the chosen way is not the LRU. + // We are choosing a way to bring in a new block, which is technically + // the MRU. lru decode unit generates the next state LRU bits, so that + // the input way is "not" the LRU way. + stat_mem_v_o = dma_done_i; + stat_mem_w_o = 1'b1; + stat_mem_data_out.dirty = {ways_p{decode_v_i.st_op | decode_v_i.atomic_op}}; + stat_mem_data_out.lru_bits = chosen_way_lru_data; + stat_mem_w_mask_out.dirty = track_miss_i ? {ways_p{1'b0}} : chosen_way_decode; + stat_mem_w_mask_out.lru_bits = chosen_way_lru_mask; + + // set the tag and the valid bit to 1'b1 for the chosen way. + tag_mem_v_o = dma_done_i; + tag_mem_w_o = 1'b1; + + for (integer i = 0; i < ways_p; i++) begin + tag_mem_data_out[i].tag = addr_tag_v; + tag_mem_data_out[i].lock = decode_v_i.alock_op; + tag_mem_data_out[i].valid = 1'b1; + tag_mem_w_mask_out[i].tag = {tag_width_lp{chosen_way_decode[i]}}; + tag_mem_w_mask_out[i].lock = chosen_way_decode[i]; + tag_mem_w_mask_out[i].valid = chosen_way_decode[i]; + end + + // set track bits to one for the chosen way on store tag miss. + track_mem_v_o = word_tracking_p ? dma_done_i : 1'b0; + track_mem_w_o = 1'b1; + for (integer i = 0; i < ways_p; i++) begin + track_mem_data_o[i] = {block_size_in_words_p{1'b1}}; + track_mem_w_mask_o[i] = {block_size_in_words_p{chosen_way_decode[i]}}; + end + + select_snoop_data_n = dma_done_i + ? 1'b1 + : select_snoop_data_r; + + miss_state_n = dma_done_i + ? RECOVER + : GET_FILL_DATA; + end + + STORE_TAG_MISS: begin + chosen_way_n = invalid_exist ? invalid_way_id : lru_way_id; + + // if the chosen way is dirty and valid, then evict. + miss_state_n = (stat_info_in.dirty[chosen_way_n] & valid_v_i[chosen_way_n]) + ? SEND_EVICT_ADDR + : STORE_TAG_MISS_ALLOCATE; + end + + STORE_TAG_MISS_ALLOCATE: begin + stat_mem_v_o = 1'b1; + stat_mem_w_o = 1'b1; + stat_mem_data_out.dirty = {ways_p{1'b1}}; + stat_mem_data_out.lru_bits = chosen_way_lru_data; + stat_mem_w_mask_out.dirty = chosen_way_decode; + stat_mem_w_mask_out.lru_bits = chosen_way_lru_mask; + + tag_mem_v_o = 1'b1; + tag_mem_w_o = 1'b1; + for (integer i = 0; i < ways_p; i++) begin + tag_mem_data_out[i].tag = addr_tag_v; + tag_mem_data_out[i].lock = decode_v_i.alock_op; + tag_mem_data_out[i].valid = 1'b1; + tag_mem_w_mask_out[i].tag = {tag_width_lp{chosen_way_decode[i]}}; + tag_mem_w_mask_out[i].lock = chosen_way_decode[i]; + tag_mem_w_mask_out[i].valid = chosen_way_decode[i]; + end + + track_mem_v_o = 1'b1; + track_mem_w_o = 1'b1; + for (integer i = 0; i < ways_p; i++) begin + track_mem_data_o[i] = {block_size_in_words_p{1'b0}}; + track_mem_w_mask_o[i] = {block_size_in_words_p{chosen_way_decode[i]}}; + end + + miss_state_n = RECOVER; + end + + // Spend one cycle to recover the tl stage. + // By recovering, it means re-reading the data_mem and tag_mem for the tl + // stage. + RECOVER: begin + recover_o = 1'b1; + miss_state_n = DONE; + end + + // Miss handling is done. Output is valid. + // Move onto next state, when the output data is taken. + DONE: begin + done_o = 1'b1; + miss_state_n = ack_i ? START : DONE; + select_snoop_data_n = ack_i ? 1'b0 : select_snoop_data_r; + end + + // this should never happen, but if it does, go back to START; + default: begin + miss_state_n = START; + end + + endcase + end + + // synopsys sync_set_reset "reset_i" + always_ff @ (posedge clk_i) begin + if (reset_i) begin + miss_state_r <= START; + chosen_way_r <= '0; + flush_way_r <= '0; + select_snoop_data_r <= 1'b0; + // added to be a little more X pessimism conservative + track_data_we_o <= 1'b0; + end + else begin + miss_state_r <= miss_state_n; + chosen_way_r <= chosen_way_n; + flush_way_r <= flush_way_n; + select_snoop_data_r <= select_snoop_data_n; + track_data_we_o <= track_mem_v_o & ~track_mem_w_o; + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_miss) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_pkg.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_pkg.sv new file mode 100644 index 0000000..f962b32 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_pkg.sv @@ -0,0 +1,153 @@ +/** + * bsg_cache_pkg.sv + * + * @author tommy + */ + +`include "bsg_defines.sv" + +package bsg_cache_pkg; + + // These subopcodes are intended to match the low 4 bits of the + // corresponding bsg_cache_pkt opcode, to simplify decoding + typedef enum logic [3:0] { + e_cache_amo_swap = 4'b0000 + ,e_cache_amo_add = 4'b0001 + ,e_cache_amo_xor = 4'b0010 + ,e_cache_amo_and = 4'b0011 + ,e_cache_amo_or = 4'b0100 + ,e_cache_amo_min = 4'b0101 + ,e_cache_amo_max = 4'b0110 + ,e_cache_amo_minu = 4'b0111 + ,e_cache_amo_maxu = 4'b1000 + } bsg_cache_amo_subop_e; + + localparam amo_support_level_none_lp = '0; + localparam amo_support_level_swap_lp = amo_support_level_none_lp + | (1 << e_cache_amo_swap); + localparam amo_support_level_logical_lp = amo_support_level_swap_lp + | (1 << e_cache_amo_xor) + | (1 << e_cache_amo_and) + | (1 << e_cache_amo_or); + localparam amo_support_level_arithmetic_lp = amo_support_level_logical_lp + | (1 << e_cache_amo_add) + | (1 << e_cache_amo_min) + | (1 << e_cache_amo_max) + | (1 << e_cache_amo_minu) + | (1 << e_cache_amo_maxu); + + // cache opcode + // + typedef enum logic [5:0] { + LB = 6'b000000 // load byte + ,LH = 6'b000001 // load half + ,LW = 6'b000010 // load word + ,LD = 6'b000011 // load double + + ,LBU = 6'b000100 // load byte (unsigned) + ,LHU = 6'b000101 // load half (unsigned) + ,LWU = 6'b000110 // load word (unsigned) + ,LDU = 6'b000111 // load double (unsigned) + + ,SB = 6'b001000 // store byte + ,SH = 6'b001001 // store half + ,SW = 6'b001010 // store word + ,SD = 6'b001011 // store double + + ,LM = 6'b001100 // load mask + ,SM = 6'b001101 // store mask + + ,TAGST = 6'b010000 // tag store + ,TAGFL = 6'b010001 // tag flush + ,TAGLV = 6'b010010 // tag load valid + ,TAGLA = 6'b010011 // tag load address + + ,AFL = 6'b011000 // address flush + ,AFLINV = 6'b011001 // address flush invalidate + ,AINV = 6'b011010 // address invalidate + + ,ALOCK = 6'b011011 // address lock + ,AUNLOCK = 6'b011100 // address unlock + + // 32-bit atomic + ,AMOSWAP_W = 6'b100000 // atomic swap + ,AMOADD_W = 6'b100001 // atomic add + ,AMOXOR_W = 6'b100010 // atomic xor + ,AMOAND_W = 6'b100011 // atomic and + ,AMOOR_W = 6'b100100 // atomic or + ,AMOMIN_W = 6'b100101 // atomic min + ,AMOMAX_W = 6'b100110 // atomic max + ,AMOMINU_W = 6'b100111 // atomic min unsigned + ,AMOMAXU_W = 6'b101000 // atomic max unsigned + + // 64-bit atomic + ,AMOSWAP_D = 6'b110000 // atomic swap + ,AMOADD_D = 6'b110001 // atomic add + ,AMOXOR_D = 6'b110010 // atomic xor + ,AMOAND_D = 6'b110011 // atomic and + ,AMOOR_D = 6'b110100 // atomic or + ,AMOMIN_D = 6'b110101 // atomic min + ,AMOMAX_D = 6'b110110 // atomic max + ,AMOMINU_D = 6'b110111 // atomic min unsigned + ,AMOMAXU_D = 6'b111000 // atomic max unsigned + } bsg_cache_opcode_e; + + + + // cache pkt decode + // + typedef struct packed { + // 00 - byte + // 01 - half + // 10 - word + // 11 - double + logic [1:0] data_size_op; + logic sigext_op; + logic mask_op; + logic ld_op; + logic st_op; + logic tagst_op; + logic tagfl_op; + logic taglv_op; + logic tagla_op; + logic afl_op; + logic aflinv_op; + logic ainv_op; + logic alock_op; + logic aunlock_op; + logic tag_read_op; + + logic atomic_op; + bsg_cache_amo_subop_e amo_subop; + } bsg_cache_decode_s; + + + + // dma opcode (one-hot) + // + typedef enum logic [3:0] { + e_dma_nop = 4'b0000 + ,e_dma_send_fill_addr = 4'b0001 + ,e_dma_send_evict_addr = 4'b0010 + ,e_dma_get_fill_data = 4'b0100 + ,e_dma_send_evict_data = 4'b1000 + } bsg_cache_dma_cmd_e; + + + // cache dma wormhole opcode + // This opcode is included in the cache DMA wormhole header flit. + typedef enum logic [1:0] { + // len = 1 + // header + addr + e_cache_wh_read = 2'b00 + + // len = 1 + (# data flits) + // header + addr + data + ,e_cache_wh_write_non_masked = 2'b10 + + // len = 2 + (# data flits) + // header + addr + mask + data + ,e_cache_wh_write_masked = 2'b11 + } bsg_cache_wh_opcode_e; + +endpackage diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_sbuf.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_sbuf.sv new file mode 100644 index 0000000..cc03aaf --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_sbuf.sv @@ -0,0 +1,150 @@ +/** + * bsg_cache_sbuf.sv + * + * store (write) buffer. + * + * input interface is valid-only. + * output interface is valid-yumi; + * + * el1 is head of the queue. + * el0 is the tail. + * + * @author tommy + */ + +`include "bsg_defines.sv" +`include "bsg_cache.svh" + +module bsg_cache_sbuf + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(data_width_p) + ,parameter `BSG_INV_PARAM(addr_width_p) + ,parameter `BSG_INV_PARAM(ways_p) + + ,localparam data_mask_width_lp=(data_width_p>>3) + ,localparam sbuf_entry_width_lp=`bsg_cache_sbuf_entry_width(addr_width_p,data_width_p,ways_p) + ) + ( + input clk_i + ,input reset_i + + ,input [sbuf_entry_width_lp-1:0] sbuf_entry_i + ,input v_i + + ,output logic [sbuf_entry_width_lp-1:0] sbuf_entry_o + ,output logic v_o + ,input logic yumi_i + + ,output logic empty_o + ,output logic full_o + + ,input [addr_width_p-1:0] bypass_addr_i + ,input bypass_v_i + ,output logic [data_width_p-1:0] bypass_data_o + ,output logic [data_mask_width_lp-1:0] bypass_mask_o + ); + + // localparam + // + localparam lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3); + + `declare_bsg_cache_sbuf_entry_s(addr_width_p, data_width_p, ways_p); + bsg_cache_sbuf_entry_s el0, el1; + logic el0_valid, el1_valid; + + bsg_cache_sbuf_entry_s sbuf_entry_in; + assign sbuf_entry_in = sbuf_entry_i; + + // buffer queue + bsg_cache_buffer_queue #( + .width_p(sbuf_entry_width_lp) + ) q0 ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(v_i) + ,.data_i(sbuf_entry_in) + + ,.v_o(v_o) + ,.data_o(sbuf_entry_o) + ,.yumi_i(yumi_i) + + ,.el0_valid_o(el0_valid) + ,.el1_valid_o(el1_valid) + ,.el0_snoop_o(el0) + ,.el1_snoop_o(el1) + + ,.empty_o(empty_o) + ,.full_o(full_o) + ); + + + // bypassing + // + logic tag_hit0, tag_hit0_n; + logic tag_hit1, tag_hit1_n; + logic tag_hit2, tag_hit2_n; + logic [addr_width_p-lg_data_mask_width_lp-1:0] bypass_word_addr; + + assign bypass_word_addr = bypass_addr_i[addr_width_p-1:lg_data_mask_width_lp]; + assign tag_hit0_n = bypass_word_addr == el0.addr[addr_width_p-1:lg_data_mask_width_lp]; + assign tag_hit1_n = bypass_word_addr == el1.addr[addr_width_p-1:lg_data_mask_width_lp]; + assign tag_hit2_n = bypass_word_addr == sbuf_entry_in.addr[addr_width_p-1:lg_data_mask_width_lp]; + + assign tag_hit0 = tag_hit0_n & el0_valid; + assign tag_hit1 = tag_hit1_n & el1_valid; + assign tag_hit2 = tag_hit2_n & v_i; + + logic [(data_width_p>>3)-1:0] tag_hit0x4; + logic [(data_width_p>>3)-1:0] tag_hit1x4; + logic [(data_width_p>>3)-1:0] tag_hit2x4; + + assign tag_hit0x4 = {(data_width_p>>3){tag_hit0}}; + assign tag_hit1x4 = {(data_width_p>>3){tag_hit1}}; + assign tag_hit2x4 = {(data_width_p>>3){tag_hit2}}; + + logic [data_width_p-1:0] el0or1_data; + logic [data_width_p-1:0] bypass_data_n; + logic [(data_width_p>>3)-1:0] bypass_mask_n; + + assign bypass_mask_n = (tag_hit0x4 & el0.mask) + | (tag_hit1x4 & el1.mask) + | (tag_hit2x4 & sbuf_entry_in.mask); + + bsg_mux_segmented #( + .segments_p(data_width_p>>3) + ,.segment_width_p(8) + ) mux_segmented_merge0 ( + .data0_i(el1.data) + ,.data1_i(el0.data) + ,.sel_i(tag_hit0x4 & el0.mask) + ,.data_o(el0or1_data) + ); + + bsg_mux_segmented #( + .segments_p(data_width_p>>3) + ,.segment_width_p(8) + ) mux_segmented_merge1 ( + .data0_i(el0or1_data) + ,.data1_i(sbuf_entry_in.data) + ,.sel_i(tag_hit2x4 & sbuf_entry_in.mask) + ,.data_o(bypass_data_n) + ); + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + bypass_mask_o <= '0; + bypass_data_o <= '0; + end + else begin + if (bypass_v_i) begin + bypass_mask_o <= bypass_mask_n; + bypass_data_o <= bypass_data_n; + end + end + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_sbuf) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_tbuf.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_tbuf.sv new file mode 100644 index 0000000..af45208 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_tbuf.sv @@ -0,0 +1,110 @@ +/** + * bsg_cache_tbuf.sv + * + * track (write) buffer. + * + * input interface is valid-only. + * output interface is valid-yumi; + * + * el1 is head of the queue. + * el0 is the tail. + * + * @author tommy + */ + +`include "bsg_defines.sv" +`include "bsg_cache.svh" + +module bsg_cache_tbuf + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(data_width_p) + ,parameter `BSG_INV_PARAM(addr_width_p) + ,parameter `BSG_INV_PARAM(ways_p) + + ,localparam way_id_width_lp=`BSG_SAFE_CLOG2(ways_p) + ) + ( + input clk_i + ,input reset_i + + ,input [addr_width_p-1:0] addr_i + ,input [way_id_width_lp-1:0] way_i + ,input v_i + + ,output logic [addr_width_p-1:0] addr_o + ,output logic [way_id_width_lp-1:0] way_o + ,output logic v_o + ,input logic yumi_i + + ,output logic empty_o + ,output logic full_o + + ,input [addr_width_p-1:0] bypass_addr_i + ,input bypass_v_i + ,output logic bypass_track_o + ); + + // localparam + // + localparam lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3); + + logic [addr_width_p-1:0] el0_addr, el1_addr; + logic [way_id_width_lp-1:0] el0_way, el1_way; + logic el0_valid, el1_valid; + + // buffer queue + bsg_cache_buffer_queue #( + .width_p(addr_width_p+way_id_width_lp) + ) q0 ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(v_i) + ,.data_i({addr_i, way_i}) + + ,.v_o(v_o) + ,.data_o({addr_o, way_o}) + ,.yumi_i(yumi_i) + + ,.el0_valid_o(el0_valid) + ,.el1_valid_o(el1_valid) + ,.el0_snoop_o({el0_addr, el0_way}) + ,.el1_snoop_o({el1_addr, el1_way}) + + ,.empty_o(empty_o) + ,.full_o(full_o) + ); + + + // bypassing + // + logic tag_hit0, tag_hit0_n; + logic tag_hit1, tag_hit1_n; + logic tag_hit2, tag_hit2_n; + logic bypass_track_n; + logic [addr_width_p-lg_data_mask_width_lp-1:0] bypass_word_addr; + + assign bypass_word_addr = bypass_addr_i[addr_width_p-1:lg_data_mask_width_lp]; + assign tag_hit0_n = bypass_word_addr == el0_addr[addr_width_p-1:lg_data_mask_width_lp]; + assign tag_hit1_n = bypass_word_addr == el1_addr[addr_width_p-1:lg_data_mask_width_lp]; + assign tag_hit2_n = bypass_word_addr == addr_i[addr_width_p-1:lg_data_mask_width_lp]; + + assign tag_hit0 = tag_hit0_n & el0_valid; + assign tag_hit1 = tag_hit1_n & el1_valid; + assign tag_hit2 = tag_hit2_n & v_i; + + assign bypass_track_n = (tag_hit0 | tag_hit1 | tag_hit2); + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + bypass_track_o <= '0; + end + else if (bypass_v_i) begin + bypass_track_o <= bypass_track_n; + end + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_tbuf) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi.sv new file mode 100644 index 0000000..ef25811 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi.sv @@ -0,0 +1,350 @@ +/** + * bsg_cache_to_axi.sv + * + * @author tommy + */ + +`include "bsg_defines.sv" +`include "bsg_cache.svh" + +module bsg_cache_to_axi + import bsg_axi_pkg::*; + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(addr_width_p) + ,parameter `BSG_INV_PARAM(block_size_in_words_p) + ,parameter `BSG_INV_PARAM(data_width_p) + ,parameter `BSG_INV_PARAM(mask_width_p) + ,parameter `BSG_INV_PARAM(num_cache_p) + + // tag fifo size can be greater than number of cache dma interfaces + // Set to maximum possible outstanding requests to avoid stalling + ,parameter tag_fifo_els_p=num_cache_p + + ,parameter `BSG_INV_PARAM(axi_id_width_p) // 6 + ,parameter `BSG_INV_PARAM(axi_data_width_p) + ,parameter `BSG_INV_PARAM(axi_burst_len_p) + ,parameter `BSG_INV_PARAM(axi_burst_type_p) + + // enables read/write ordering + ,parameter `BSG_INV_PARAM(ordering_en_p) + + ,parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p) + ,parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p, mask_width_p) + + ,parameter axi_strb_width_lp=(axi_data_width_p>>3) + ) + ( + input clk_i + ,input reset_i + + // cache side + ,input [num_cache_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_i + ,input [num_cache_p-1:0] dma_pkt_v_i + ,output logic [num_cache_p-1:0] dma_pkt_yumi_o + + ,output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o + ,output logic [num_cache_p-1:0] dma_data_v_o + ,input [num_cache_p-1:0] dma_data_ready_and_i + + ,input [num_cache_p-1:0][data_width_p-1:0] dma_data_i + ,input [num_cache_p-1:0] dma_data_v_i + ,output logic [num_cache_p-1:0] dma_data_yumi_o + + // axi write address channel + ,output logic [axi_id_width_p-1:0] axi_awid_o + ,output logic [addr_width_p-1:0] axi_awaddr_addr_o + ,output logic [lg_num_cache_lp-1:0] axi_awaddr_cache_id_o + ,output logic [7:0] axi_awlen_o + ,output logic [2:0] axi_awsize_o + ,output logic [1:0] axi_awburst_o + ,output logic [3:0] axi_awcache_o + ,output logic [2:0] axi_awprot_o + ,output logic axi_awlock_o + ,output logic axi_awvalid_o + ,input axi_awready_i + + // axi write data channel + ,output logic [axi_data_width_p-1:0] axi_wdata_o + ,output logic [axi_strb_width_lp-1:0] axi_wstrb_o + ,output logic axi_wlast_o + ,output logic axi_wvalid_o + ,input axi_wready_i + + // axi write response channel + ,input [axi_id_width_p-1:0] axi_bid_i + ,input [1:0] axi_bresp_i + ,input axi_bvalid_i + ,output logic axi_bready_o + + // axi read address channel + ,output logic [axi_id_width_p-1:0] axi_arid_o + ,output logic [addr_width_p-1:0] axi_araddr_addr_o + ,output logic [lg_num_cache_lp-1:0] axi_araddr_cache_id_o + ,output logic [7:0] axi_arlen_o + ,output logic [2:0] axi_arsize_o + ,output logic [1:0] axi_arburst_o + ,output logic [3:0] axi_arcache_o + ,output logic [2:0] axi_arprot_o + ,output logic axi_arlock_o + ,output logic axi_arvalid_o + ,input axi_arready_i + + // axi read data channel + ,input [axi_id_width_p-1:0] axi_rid_i + ,input [axi_data_width_p-1:0] axi_rdata_i + ,input [1:0] axi_rresp_i + ,input axi_rlast_i + ,input axi_rvalid_i + ,output logic axi_rready_o + ); + + // dma packets from caches + // + `declare_bsg_cache_dma_pkt_s(addr_width_p, mask_width_p); + bsg_cache_dma_pkt_s [num_cache_p-1:0] dma_pkt; + assign dma_pkt = dma_pkt_i; + + // reader round-robin + // + logic [num_cache_p-1:0] read_rr_v_li; + logic [num_cache_p-1:0] read_rr_yumi_lo; + logic read_rr_v_lo; + bsg_cache_dma_pkt_s read_rr_dma_pkt; + logic [lg_num_cache_lp-1:0] read_rr_tag_lo; + logic read_rr_yumi_li; + + for (genvar i = 0; i < num_cache_p; i++) begin + assign read_rr_v_li[i] = dma_pkt_v_i[i] & ~dma_pkt[i].write_not_read; + end + + bsg_round_robin_n_to_1 #( + .width_p(dma_pkt_width_lp) + ,.num_in_p(num_cache_p) + ,.strict_p(0) + ) read_rr ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(dma_pkt) + ,.v_i(read_rr_v_li) + ,.yumi_o(read_rr_yumi_lo) + + ,.v_o(read_rr_v_lo) + ,.data_o(read_rr_dma_pkt) + ,.tag_o(read_rr_tag_lo) + ,.yumi_i(read_rr_yumi_li) + ); + + // writer round-robin + // + logic [num_cache_p-1:0] write_rr_v_li; + logic [num_cache_p-1:0] write_rr_yumi_lo; + logic write_rr_v_lo; + bsg_cache_dma_pkt_s write_rr_dma_pkt; + logic [lg_num_cache_lp-1:0] write_rr_tag_lo; + logic write_rr_yumi_li; + + for (genvar i = 0; i < num_cache_p; i++) begin + assign write_rr_v_li[i] = dma_pkt_v_i[i] & dma_pkt[i].write_not_read; + end + + bsg_round_robin_n_to_1 #( + .width_p(dma_pkt_width_lp) + ,.num_in_p(num_cache_p) + ,.strict_p(0) + ) write_rr ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(dma_pkt) + ,.v_i(write_rr_v_li) + ,.yumi_o(write_rr_yumi_lo) + + ,.v_o(write_rr_v_lo) + ,.data_o(write_rr_dma_pkt) + ,.tag_o(write_rr_tag_lo) + ,.yumi_i(write_rr_yumi_li) + ); + + // One example of address translation corresponding to tag and addr + // + // logic [axi_addr_width_p-1:0] rx_axi_addr; + // logic [axi_addr_width_p-1:0] tx_axi_addr; + + // assign rx_axi_addr = { + // {(axi_addr_width_p-lg_num_cache_lp-addr_width_p){1'b0}} + // ,read_rr_tag_lo + // ,read_rr_dma_pkt.addr + // }; + + // assign tx_axi_addr = { + // {(axi_addr_width_p-lg_num_cache_lp-addr_width_p){1'b0}} + // ,write_rr_tag_lo + // ,write_rr_dma_pkt.addr + // }; + + // dma_pkt handshake + // + for (genvar i = 0; i < num_cache_p; i++) begin + assign dma_pkt_yumi_o[i] = dma_pkt[i].write_not_read + ? write_rr_yumi_lo[i] + : read_rr_yumi_lo[i]; + end + + logic r_fence_lo, w_fence_lo; + + // rx + // + bsg_cache_to_axi_rx #( + .num_cache_p(num_cache_p) + ,.addr_width_p(addr_width_p) + ,.data_width_p(data_width_p) + ,.block_size_in_words_p(block_size_in_words_p) + ,.tag_fifo_els_p(tag_fifo_els_p) + ,.axi_id_width_p(axi_id_width_p) + ,.axi_data_width_p(axi_data_width_p) + ,.axi_burst_len_p(axi_burst_len_p) + ,.axi_burst_type_p(axi_burst_type_p) + ) axi_rx ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(read_rr_v_lo) + ,.yumi_o(read_rr_yumi_li) + ,.cache_id_i(read_rr_tag_lo) + ,.addr_i(read_rr_dma_pkt.addr) + + ,.fence_i(r_fence_lo) + + ,.dma_data_o(dma_data_o) + ,.dma_data_v_o(dma_data_v_o) + ,.dma_data_ready_and_i(dma_data_ready_and_i) + + ,.axi_arid_o(axi_arid_o) + ,.axi_araddr_addr_o(axi_araddr_addr_o) + ,.axi_araddr_cache_id_o(axi_araddr_cache_id_o) + ,.axi_arlen_o(axi_arlen_o) + ,.axi_arsize_o(axi_arsize_o) + ,.axi_arburst_o(axi_arburst_o) + ,.axi_arcache_o(axi_arcache_o) + ,.axi_arvalid_o(axi_arvalid_o) + ,.axi_arlock_o(axi_arlock_o) + ,.axi_arprot_o(axi_arprot_o) + ,.axi_arready_i(axi_arready_i) + + ,.axi_rid_i(axi_rid_i) + ,.axi_rdata_i(axi_rdata_i) + ,.axi_rresp_i(axi_rresp_i) + ,.axi_rlast_i(axi_rlast_i) + ,.axi_rvalid_i(axi_rvalid_i) + ,.axi_rready_o(axi_rready_o) + ); + + // tx + // + bsg_cache_to_axi_tx #( + .num_cache_p(num_cache_p) + ,.addr_width_p(addr_width_p) + ,.data_width_p(data_width_p) + ,.mask_width_p(mask_width_p) + ,.block_size_in_words_p(block_size_in_words_p) + ,.tag_fifo_els_p(tag_fifo_els_p) + ,.axi_id_width_p(axi_id_width_p) + ,.axi_data_width_p(axi_data_width_p) + ,.axi_burst_len_p(axi_burst_len_p) + ,.axi_burst_type_p(axi_burst_type_p) + ) axi_tx ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(write_rr_v_lo) + ,.yumi_o(write_rr_yumi_li) + ,.cache_id_i(write_rr_tag_lo) + ,.addr_i(write_rr_dma_pkt.addr) + ,.mask_i(write_rr_dma_pkt.mask) + + ,.fence_i(w_fence_lo) + + ,.dma_data_i(dma_data_i) + ,.dma_data_v_i(dma_data_v_i) + ,.dma_data_yumi_o(dma_data_yumi_o) + + ,.axi_awid_o(axi_awid_o) + ,.axi_awaddr_addr_o(axi_awaddr_addr_o) + ,.axi_awaddr_cache_id_o(axi_awaddr_cache_id_o) + ,.axi_awlen_o(axi_awlen_o) + ,.axi_awsize_o(axi_awsize_o) + ,.axi_awburst_o(axi_awburst_o) + ,.axi_awcache_o(axi_awcache_o) + ,.axi_awprot_o(axi_awprot_o) + ,.axi_awlock_o(axi_awlock_o) + ,.axi_awvalid_o(axi_awvalid_o) + ,.axi_awready_i(axi_awready_i) + + ,.axi_wdata_o(axi_wdata_o) + ,.axi_wstrb_o(axi_wstrb_o) + ,.axi_wlast_o(axi_wlast_o) + ,.axi_wvalid_o(axi_wvalid_o) + ,.axi_wready_i(axi_wready_i) + + ,.axi_bid_i(axi_bid_i) + ,.axi_bresp_i(axi_bresp_i) + ,.axi_bvalid_i(axi_bvalid_i) + ,.axi_bready_o(axi_bready_o) + ); + + // ordering + // + if(ordering_en_p) begin: ordering + bsg_cache_to_axi_ordering #( + .num_cache_p(num_cache_p) + ,.addr_width_p(addr_width_p) + ,.data_width_p(data_width_p) + ,.mask_width_p(mask_width_p) + ,.block_size_in_words_p(block_size_in_words_p) + ,.tag_fifo_els_p(tag_fifo_els_p) + ,.axi_id_width_p(axi_id_width_p) + ,.axi_data_width_p(axi_data_width_p) + ,.axi_burst_len_p(axi_burst_len_p) + ,.axi_burst_type_p(axi_burst_type_p) + ) axi_ordering ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.r_v_i(read_rr_v_lo) + ,.r_addr_i(read_rr_dma_pkt.addr) + ,.r_fence_o(r_fence_lo) + + ,.w_v_i(write_rr_v_lo) + ,.w_addr_i(write_rr_dma_pkt.addr) + ,.w_fence_o(w_fence_lo) + + ,.axi_awvalid_i(axi_awvalid_o) + ,.axi_awready_i(axi_awready_i) + ,.axi_bvalid_i(axi_bvalid_i) + ,.axi_bready_i(axi_bready_o) + + ,.axi_arvalid_i(axi_arvalid_o) + ,.axi_arready_i(axi_arready_i) + ,.axi_rlast_i(axi_rlast_i) + ,.axi_rvalid_i(axi_rvalid_i) + ,.axi_rready_i(axi_rready_o) + ); + end + else begin: noordering + assign r_fence_lo = 1'b0; + assign w_fence_lo = 1'b0; + end + + // assertions + // +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial begin + assert(data_width_p*block_size_in_words_p == axi_data_width_p*axi_burst_len_p) + else $error("cache block size and axi transfer size do not match."); + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_to_axi) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_ordering.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_ordering.sv new file mode 100644 index 0000000..fbef71b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_ordering.sv @@ -0,0 +1,194 @@ +`include "bsg_defines.sv" +`include "bsg_cache.svh" + +module bsg_cache_to_axi_ordering + import bsg_axi_pkg::*; + #(parameter `BSG_INV_PARAM(addr_width_p) + ,parameter `BSG_INV_PARAM(block_size_in_words_p) + ,parameter `BSG_INV_PARAM(data_width_p) + ,parameter `BSG_INV_PARAM(mask_width_p) + ,parameter `BSG_INV_PARAM(num_cache_p) + ,parameter tag_fifo_els_p=num_cache_p + + ,parameter `BSG_INV_PARAM(axi_id_width_p) + ,parameter `BSG_INV_PARAM(axi_data_width_p) + ,parameter `BSG_INV_PARAM(axi_burst_len_p) + ,parameter `BSG_INV_PARAM(axi_burst_type_p) + + ,parameter strb_width_lp=(data_width_p>>3) + ,parameter byte_mask_width_lp=(block_size_in_words_p*strb_width_lp) + ,parameter lg_byte_mask_width_lp=`BSG_SAFE_CLOG2(byte_mask_width_lp) + ,parameter cam_tag_width_lp=(addr_width_p-lg_byte_mask_width_lp) + ) + ( + input clk_i + ,input reset_i + + ,input r_v_i + ,input [addr_width_p-1:0] r_addr_i + ,output logic r_fence_o + + ,input w_v_i + ,input [addr_width_p-1:0] w_addr_i + ,output logic w_fence_o + + ,input axi_awvalid_i + ,input axi_awready_i + ,input axi_bvalid_i + ,input axi_bready_i + + ,input axi_arvalid_i + ,input axi_arready_i + ,input axi_rlast_i + ,input axi_rvalid_i + ,input axi_rready_i + ); + + logic wcam_set_v_li, wcam_clr_v_li; + logic [tag_fifo_els_p-1:0] wcam_set_li, wcam_clr_li; + logic [tag_fifo_els_p-1:0] wcam_w_v_li, wcam_w_empty_lo, wcam_r_match_lo; + logic wcam_set_not_clear_li, wcam_r_v_li; + logic [cam_tag_width_lp-1:0] wcam_w_tag_li, wcam_r_tag_li; + + logic rcam_set_v_li, rcam_clr_v_li; + logic [tag_fifo_els_p-1:0] rcam_set_li, rcam_clr_li; + logic [tag_fifo_els_p-1:0] rcam_w_v_li, rcam_w_empty_lo, rcam_r_match_lo; + logic rcam_set_not_clear_li, rcam_r_v_li; + logic [cam_tag_width_lp-1:0] rcam_w_tag_li, rcam_r_tag_li; + + // fence write or read requests if: + // - there's a pending request in the opposite channel for the same addr + // - the addr CAM is full + // - the addr CAM is being cleared in this cycle + assign r_fence_o = r_v_i & ((|wcam_r_match_lo) | (~|rcam_w_empty_lo) | rcam_clr_v_li); + assign w_fence_o = w_v_i & ((|rcam_r_match_lo) | (~|wcam_w_empty_lo) | wcam_clr_v_li); + + // write channel + assign wcam_set_v_li = axi_awvalid_i & axi_awready_i; + //assign wcam_clr_v_li = axi_bvalid_i & axi_bready_i; + + assign wcam_w_v_li = wcam_clr_v_li ? wcam_clr_li : (wcam_set_v_li ? wcam_set_li : '0); + assign wcam_set_not_clear_li = wcam_set_v_li; + assign wcam_w_tag_li = (w_addr_i >> lg_byte_mask_width_lp); + + assign wcam_r_v_li = r_v_i; + assign wcam_r_tag_li = (r_addr_i >> lg_byte_mask_width_lp); + + bsg_cam_1r1w_tag_array #( + .width_p(cam_tag_width_lp) + ,.els_p(tag_fifo_els_p) + ) w_addr_cam ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(wcam_w_v_li) + ,.w_set_not_clear_i(wcam_set_not_clear_li) + ,.w_tag_i(wcam_w_tag_li) + ,.w_empty_o(wcam_w_empty_lo) + + ,.r_v_i(wcam_r_v_li) + ,.r_tag_i(wcam_r_tag_li) + ,.r_match_o(wcam_r_match_lo) + ); + + bsg_dff_reset #( + .width_p(1) + ) w_reg ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(axi_bvalid_i & axi_bready_i) + ,.data_o(wcam_clr_v_li) + ); + + if(tag_fifo_els_p == 1) begin + assign wcam_set_li = 1'b1; + assign wcam_clr_li = 1'b1; + end + else begin + bsg_counter_clear_up_one_hot #( + .max_val_p(tag_fifo_els_p-1) + ) wcam_set_oh ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(1'b0) + ,.up_i(wcam_set_v_li) + ,.count_r_o(wcam_set_li) + ); + + bsg_counter_clear_up_one_hot #( + .max_val_p(tag_fifo_els_p-1) + ) wcam_clr_oh ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(1'b0) + ,.up_i(wcam_clr_v_li) + ,.count_r_o(wcam_clr_li) + ); + end + + // read channel + assign rcam_set_v_li = axi_arvalid_i & axi_arready_i; + //assign rcam_clr_v_li = axi_rvalid_i & axi_rlast_i & axi_rready_i; + + assign rcam_w_v_li = rcam_clr_v_li ? rcam_clr_li : (rcam_set_v_li ? rcam_set_li : '0); + assign rcam_set_not_clear_li = rcam_set_v_li; + assign rcam_w_tag_li = (r_addr_i >> lg_byte_mask_width_lp); + + assign rcam_r_v_li = w_v_i; + assign rcam_r_tag_li = (w_addr_i >> lg_byte_mask_width_lp); + + bsg_cam_1r1w_tag_array #( + .width_p(cam_tag_width_lp) + ,.els_p(tag_fifo_els_p) + ) r_addr_cam ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(rcam_w_v_li) + ,.w_set_not_clear_i(rcam_set_not_clear_li) + ,.w_tag_i(rcam_w_tag_li) + ,.w_empty_o(rcam_w_empty_lo) + + ,.r_v_i(rcam_r_v_li) + ,.r_tag_i(rcam_r_tag_li) + ,.r_match_o(rcam_r_match_lo) + ); + + bsg_dff_reset #( + .width_p(1) + ) r_reg ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(axi_rvalid_i & axi_rlast_i & axi_rready_i) + ,.data_o(rcam_clr_v_li) + ); + + if(tag_fifo_els_p == 1) begin + assign rcam_set_li = 1'b1; + assign rcam_clr_li = 1'b1; + end + else begin + bsg_counter_clear_up_one_hot #( + .max_val_p(tag_fifo_els_p-1) + ) rcam_set_oh ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(1'b0) + ,.up_i(rcam_set_v_li) + ,.count_r_o(rcam_set_li) + ); + + bsg_counter_clear_up_one_hot #( + .max_val_p(tag_fifo_els_p-1) + ) rcam_clr_oh ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(1'b0) + ,.up_i(rcam_clr_v_li) + ,.count_r_o(rcam_clr_li) + ); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_to_axi_ordering) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_rx.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_rx.sv new file mode 100644 index 0000000..7f459f5 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_rx.sv @@ -0,0 +1,188 @@ +/** + * bsg_cache_to_axi_rx.sv + * + * @author tommy + */ + +`include "bsg_defines.sv" + +module bsg_cache_to_axi_rx + import bsg_axi_pkg::*; + #(parameter `BSG_INV_PARAM(num_cache_p) + ,parameter `BSG_INV_PARAM(addr_width_p) + ,parameter `BSG_INV_PARAM(data_width_p) + ,parameter `BSG_INV_PARAM(block_size_in_words_p) + ,parameter tag_fifo_els_p=num_cache_p + + ,parameter `BSG_INV_PARAM(axi_id_width_p) + ,parameter `BSG_INV_PARAM(axi_data_width_p) + ,parameter `BSG_INV_PARAM(axi_burst_len_p) + ,parameter `BSG_INV_PARAM(axi_burst_type_p) + + ,parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p) + ,parameter data_width_ratio_lp=(axi_data_width_p/data_width_p) + ) + ( + input clk_i + ,input reset_i + + ,input v_i + ,output logic yumi_o + ,input [lg_num_cache_lp-1:0] cache_id_i + ,input [addr_width_p-1:0] addr_i + + ,input fence_i + + // cache dma read channel + ,output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o + ,output logic [num_cache_p-1:0] dma_data_v_o + ,input [num_cache_p-1:0] dma_data_ready_and_i + + // axi read address channel + ,output logic [axi_id_width_p-1:0] axi_arid_o + ,output logic [addr_width_p-1:0] axi_araddr_addr_o + ,output logic [lg_num_cache_lp-1:0] axi_araddr_cache_id_o + ,output logic [7:0] axi_arlen_o + ,output logic [2:0] axi_arsize_o + ,output logic [1:0] axi_arburst_o + ,output logic [3:0] axi_arcache_o + ,output logic [2:0] axi_arprot_o + ,output logic axi_arlock_o + ,output logic axi_arvalid_o + ,input axi_arready_i + + // axi read data channel + ,input [axi_id_width_p-1:0] axi_rid_i + ,input [axi_data_width_p-1:0] axi_rdata_i + ,input [1:0] axi_rresp_i + ,input axi_rlast_i + ,input axi_rvalid_i + ,output logic axi_rready_o + ); + + // suppress unused + // + wire [axi_id_width_p-1:0] unused_rid = axi_rid_i; + wire [1:0] unused_rresp = axi_rresp_i; + wire unused_rlast = axi_rlast_i; + + // tag fifo + // + logic tag_fifo_v_li; + logic tag_fifo_ready_lo; + logic tag_fifo_v_lo; + logic tag_fifo_yumi_li; + logic [lg_num_cache_lp-1:0] tag_lo; + + bsg_fifo_1r1w_small #( + .width_p(lg_num_cache_lp) + ,.els_p(tag_fifo_els_p) + ) tag_fifo ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(tag_fifo_v_li) + ,.ready_param_o(tag_fifo_ready_lo) + ,.data_i(cache_id_i) + + ,.v_o(tag_fifo_v_lo) + ,.data_o(tag_lo) + ,.yumi_i(tag_fifo_yumi_li) + ); + + // yumi when address packet is consumed + assign yumi_o = axi_arvalid_o & axi_arready_i; + // tag_fifo is valid when address packet is consumed + assign tag_fifo_v_li = axi_arvalid_o & axi_arready_i; + + // axi read address channel + // + assign axi_arid_o = {axi_id_width_p{1'b0}}; + assign axi_araddr_addr_o = addr_i; + assign axi_araddr_cache_id_o = cache_id_i; + assign axi_arlen_o = (8)'(axi_burst_len_p-1); // burst length + assign axi_arsize_o = (3)'(`BSG_SAFE_CLOG2(axi_data_width_p>>3)); + assign axi_arburst_o = 2'(axi_burst_type_p); // fixed, incr or wrap + assign axi_arcache_o = e_axi_cache_wnarnanmnb; // non-bufferable + assign axi_arprot_o = e_axi_prot_dsn; // unprivileged + assign axi_arlock_o = 1'b0; // normal access + // axi_ar is valid when tag_fifo is ready and there's no ordering fence + assign axi_arvalid_o = v_i & tag_fifo_ready_lo & ~fence_i; + + + // axi read data channel + // + logic piso_v_lo; + logic [data_width_p-1:0] piso_data_lo; + logic piso_yumi_li; + + bsg_parallel_in_serial_out #( + .width_p(data_width_p) + ,.els_p(data_width_ratio_lp) + ) piso ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.valid_i(axi_rvalid_i) + ,.data_i(axi_rdata_i) + ,.ready_and_o(axi_rready_o) + + ,.valid_o(piso_v_lo) + ,.data_o(piso_data_lo) + ,.yumi_i(piso_yumi_li) + ); + + logic [num_cache_p-1:0] cache_sel; + + // demux + // + bsg_decode_with_v #( + .num_out_p(num_cache_p) + ) demux ( + .i(tag_lo) + ,.v_i(tag_fifo_v_lo) + ,.o(cache_sel) + ); + + assign dma_data_v_o = cache_sel & {num_cache_p{piso_v_lo}}; + + for (genvar i = 0; i < num_cache_p; i++) begin + assign dma_data_o[i] = piso_data_lo; + end + + // counter + // + logic [`BSG_SAFE_CLOG2(block_size_in_words_p)-1:0] count_lo; + logic counter_clear_li; + logic counter_up_li; + + bsg_counter_clear_up #( + .max_val_p(block_size_in_words_p-1) + ,.init_val_p(0) + ) counter ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(counter_clear_li) + ,.up_i(counter_up_li) + ,.count_o(count_lo) + ); + + assign piso_yumi_li = dma_data_ready_and_i[tag_lo] & piso_v_lo & tag_fifo_v_lo; + + always_comb begin + if (count_lo == block_size_in_words_p-1) begin + counter_clear_li = piso_yumi_li; + counter_up_li = 1'b0; + tag_fifo_yumi_li = piso_yumi_li; + end + else begin + counter_clear_li = 1'b0; + counter_up_li = piso_yumi_li; + tag_fifo_yumi_li = 1'b0; + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_to_axi_rx) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_tx.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_tx.sv new file mode 100644 index 0000000..053472b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_to_axi_tx.sv @@ -0,0 +1,278 @@ +/** + * bsg_cache_to_axi_tx.sv + * + * @author tommy + */ + + +`include "bsg_defines.sv" + +module bsg_cache_to_axi_tx + import bsg_axi_pkg::*; + #(parameter `BSG_INV_PARAM(num_cache_p) + ,parameter `BSG_INV_PARAM(addr_width_p) + ,parameter `BSG_INV_PARAM(data_width_p) + ,parameter `BSG_INV_PARAM(mask_width_p) + ,parameter `BSG_INV_PARAM(block_size_in_words_p) + ,parameter tag_fifo_els_p=num_cache_p + + ,parameter `BSG_INV_PARAM(axi_id_width_p) + ,parameter `BSG_INV_PARAM(axi_data_width_p) + ,parameter `BSG_INV_PARAM(axi_burst_len_p) + ,parameter `BSG_INV_PARAM(axi_burst_type_p) + + ,parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p) + + ,parameter strb_width_lp=(data_width_p>>3) + ,parameter axi_strb_width_lp=(axi_data_width_p>>3) + ,parameter data_width_ratio_lp=(axi_data_width_p/data_width_p) + ,parameter byte_mask_width_lp=(block_size_in_words_p*strb_width_lp) + ) + ( + input clk_i + ,input reset_i + + ,input v_i + ,output logic yumi_o + ,input [lg_num_cache_lp-1:0] cache_id_i + ,input [addr_width_p-1:0] addr_i + ,input [mask_width_p-1:0] mask_i + + ,input fence_i + + // cache dma write channel + ,input [num_cache_p-1:0][data_width_p-1:0] dma_data_i + ,input [num_cache_p-1:0] dma_data_v_i + ,output logic [num_cache_p-1:0] dma_data_yumi_o + + // axi write address channel + ,output logic [axi_id_width_p-1:0] axi_awid_o + ,output logic [addr_width_p-1:0] axi_awaddr_addr_o + ,output logic [lg_num_cache_lp-1:0] axi_awaddr_cache_id_o + ,output logic [7:0] axi_awlen_o + ,output logic [2:0] axi_awsize_o + ,output logic [1:0] axi_awburst_o + ,output logic [3:0] axi_awcache_o + ,output logic [2:0] axi_awprot_o + ,output logic axi_awlock_o + ,output logic axi_awvalid_o + ,input axi_awready_i + + // axi write data channel + ,output logic [axi_data_width_p-1:0] axi_wdata_o + ,output logic [axi_strb_width_lp-1:0] axi_wstrb_o + ,output logic axi_wlast_o + ,output logic axi_wvalid_o + ,input axi_wready_i + + // axi write response channel + ,input [axi_id_width_p-1:0] axi_bid_i + ,input [1:0] axi_bresp_i + ,input axi_bvalid_i + ,output logic axi_bready_o + ); + + // tag fifo + // + logic tag_fifo_v_li; + logic tag_fifo_ready_lo; + logic tag_fifo_v_lo; + logic tag_fifo_yumi_li; + logic [lg_num_cache_lp-1:0] tag_lo; + logic [mask_width_p-1:0] mask_lo; + + bsg_fifo_1r1w_small #( + .width_p(lg_num_cache_lp+mask_width_p) + ,.els_p(tag_fifo_els_p) + ) tag_fifo ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(tag_fifo_v_li) + ,.ready_param_o(tag_fifo_ready_lo) + ,.data_i({mask_i, cache_id_i}) + + ,.v_o(tag_fifo_v_lo) + ,.data_o({mask_lo, tag_lo}) + ,.yumi_i(tag_fifo_yumi_li) + ); + + // suppress unused + // + wire [axi_id_width_p-1:0] unused_bid = axi_bid_i; + wire [1:0] unused_bresp = axi_bresp_i; + wire unused_bvalid = axi_bvalid_i; + + // tag + // + // yumi when address packet is consumed + assign yumi_o =axi_awvalid_o & axi_awready_i; + // tag_fifo is valid when address packet is consumed + assign tag_fifo_v_li = axi_awvalid_o & axi_awready_i; + + // axi write address channel + // + assign axi_awid_o = {axi_id_width_p{1'b0}}; + assign axi_awaddr_addr_o = addr_i; + assign axi_awaddr_cache_id_o = cache_id_i; + assign axi_awlen_o = (8)'(axi_burst_len_p-1); // burst len + assign axi_awsize_o = (3)'(`BSG_SAFE_CLOG2(axi_data_width_p>>3)); + assign axi_awburst_o = (2)'(axi_burst_type_p); // fixed, incr or wrap + assign axi_awcache_o = e_axi_cache_wnarnanmnb; // non-bufferable + assign axi_awprot_o = e_axi_prot_dsn; // unprivileged + assign axi_awlock_o = 1'b0; // normal access + // axi_aw is valid when tag_fifo is ready and there's no ordering fence + assign axi_awvalid_o = v_i & tag_fifo_ready_lo & ~fence_i; + + // axi write data channel + // + logic sipo_v_li; + logic sipo_ready_and_lo; + logic [data_width_p-1:0] sipo_data_li; + logic [strb_width_lp-1:0] sipo_strb_li; + logic sipo_yumi_li; + logic sipo_v_lo; + logic [num_cache_p-1:0] cache_sel; + logic [byte_mask_width_lp-1:0] byte_mask_lo; + + bsg_decode_with_v #( + .num_out_p(num_cache_p) + ) demux ( + .i(tag_lo) + ,.v_i(tag_fifo_v_lo) + ,.o(cache_sel) + ); + + bsg_expand_bitmask #( + .in_width_p(mask_width_p) + ,.expand_p(byte_mask_width_lp/mask_width_p) + ) expand ( + .i(mask_lo) + ,.o(byte_mask_lo) + ); + + assign sipo_data_li = dma_data_i[tag_lo]; + assign dma_data_yumi_o = cache_sel & dma_data_v_i & {num_cache_p{sipo_ready_and_lo}}; + + logic [data_width_ratio_lp-1:0][data_width_p-1:0] sipo_data_lo; + bsg_serial_in_parallel_out_full #( + .width_p(data_width_p) + ,.els_p(data_width_ratio_lp) + ) sipo ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(sipo_v_li) + ,.data_i(sipo_data_li) + ,.ready_and_o(sipo_ready_and_lo) + + ,.v_o(sipo_v_lo) + ,.data_o(sipo_data_lo) + ,.yumi_i(sipo_yumi_li) + ); + + logic [data_width_ratio_lp-1:0][strb_width_lp-1:0] sipo_strb_lo; + bsg_serial_in_parallel_out_full #( + .width_p(strb_width_lp) + ,.els_p(data_width_ratio_lp) + ) strb_sipo ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(sipo_v_li) + ,.data_i(sipo_strb_li) + ,.ready_and_o(/* Tracks data sipo */) + + ,.v_o(/* Tracks data sipo */) + ,.data_o(sipo_strb_lo) + ,.yumi_i(sipo_yumi_li) + ); + + assign axi_wstrb_o = sipo_strb_lo; + assign axi_wdata_o = sipo_data_lo; + + assign axi_wvalid_o = sipo_v_lo; + assign sipo_v_li = tag_fifo_v_lo & dma_data_v_i[tag_lo]; + assign sipo_yumi_li = axi_wvalid_o & axi_wready_i; + + // word counter + // + logic [`BSG_SAFE_CLOG2(block_size_in_words_p)-1:0] word_count_lo; + logic word_up_li; + logic word_clear_li; + + bsg_counter_clear_up #( + .max_val_p(block_size_in_words_p-1) + ,.init_val_p(0) + ) word_counter ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(word_clear_li) + ,.up_i(word_up_li) + ,.count_o(word_count_lo) + ); + + bsg_mux #( + .width_p(strb_width_lp) + ,.els_p(block_size_in_words_p) + ) wstrb_mux ( + .data_i(byte_mask_lo) + ,.sel_i(word_count_lo) + ,.data_o(sipo_strb_li) + ); + + logic pop_word; + assign pop_word = dma_data_v_i[tag_lo] & dma_data_yumi_o[tag_lo] & tag_fifo_v_lo; + + always_comb begin + if (word_count_lo == block_size_in_words_p-1) begin + word_clear_li = pop_word; + word_up_li = 1'b0; + tag_fifo_yumi_li = pop_word; + end + else begin + word_clear_li = 1'b0; + word_up_li = pop_word; + tag_fifo_yumi_li = 1'b0; + end + end + + + // burst counter + // + logic [`BSG_SAFE_CLOG2(axi_burst_len_p)-1:0] burst_count_lo; + logic burst_up_li; + logic burst_clear_li; + + bsg_counter_clear_up #( + .max_val_p(axi_burst_len_p-1) + ,.init_val_p(0) + ) burst_counter ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(burst_clear_li) + ,.up_i(burst_up_li) + ,.count_o(burst_count_lo) + ); + + always_comb begin + if (burst_count_lo == axi_burst_len_p-1) begin + burst_clear_li = axi_wvalid_o & axi_wready_i; + burst_up_li = 1'b0; + axi_wlast_o = axi_wvalid_o; + end + else begin + burst_clear_li = 1'b0; + burst_up_li = axi_wvalid_o & axi_wready_i; + axi_wlast_o = 1'b0; + end + end + + // axi write response channel + // + assign axi_bready_o = 1'b1; // don't really care about the resp. + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_to_axi_tx) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram.sv new file mode 100644 index 0000000..41d923b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram.sv @@ -0,0 +1,327 @@ +/** + * bsg_cache_to_test_dram.sv + * + * multiple caches can attach here and connect to one test dram channel. + * + * cache block size must be greater or equal to the dram_data_width_p. + * If the cache block size is greater, this module issues multiple dram commands per one dma_pkt. + * + * @author tommy + * + */ + + +`include "bsg_defines.sv" +`include "bsg_cache.svh" + +module bsg_cache_to_test_dram + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(num_cache_p) + , parameter `BSG_INV_PARAM(addr_width_p) // cache addr (byte) + , parameter `BSG_INV_PARAM(data_width_p) // cache data width + , parameter `BSG_INV_PARAM(block_size_in_words_p) // cache block_size (word) + , parameter `BSG_INV_PARAM(cache_bank_addr_width_p) // actual number of bits used for address (byte) + + , parameter `BSG_INV_PARAM(dram_channel_addr_width_p) // dram channel addr + , parameter `BSG_INV_PARAM(dram_data_width_p) // dram channel data width + + , parameter dma_data_width_p=data_width_p // cache dma data width + + , parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p) // number of DRAM requests sent per cache miss. + , parameter lg_num_req_lp = `BSG_SAFE_CLOG2(num_req_lp) + , parameter dram_byte_offset_width_lp = `BSG_SAFE_CLOG2(dram_data_width_p>>3) + + , parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p) + , parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p, block_size_in_words_p) + ) + ( + // vcache dma interface + input core_clk_i + , input core_reset_i + + , input [num_cache_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_i + , input [num_cache_p-1:0] dma_pkt_v_i + , output logic [num_cache_p-1:0] dma_pkt_yumi_o + + , output logic [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_o + , output logic [num_cache_p-1:0] dma_data_v_o + , input [num_cache_p-1:0] dma_data_ready_and_i + + , input [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_i + , input [num_cache_p-1:0] dma_data_v_i + , output logic [num_cache_p-1:0] dma_data_yumi_o + + // dram + , input dram_clk_i + , input dram_reset_i + + // dram request channel (valid-yumi) + , output logic dram_req_v_o + , output logic dram_write_not_read_o + , output logic [dram_channel_addr_width_p-1:0] dram_ch_addr_o // read done addr + , input dram_req_yumi_i + + // dram write data channel (valid-yumi) + , output logic dram_data_v_o + , output logic [dram_data_width_p-1:0] dram_data_o + , output logic [(dram_data_width_p>>3)-1:0] dram_mask_o + , input dram_data_yumi_i + + // dram read data channel (valid-only) + , input dram_data_v_i + , input [dram_data_width_p-1:0] dram_data_i + , input [dram_channel_addr_width_p-1:0] dram_ch_addr_i // the address of incoming data + ); + + + // dma pkt + // + `declare_bsg_cache_dma_pkt_s(addr_width_p, block_size_in_words_p); + bsg_cache_dma_pkt_s [num_cache_p-1:0] dma_pkt; + assign dma_pkt = dma_pkt_i; + + + // request round robin + // + logic rr_v_lo; + logic rr_yumi_li; + bsg_cache_dma_pkt_s rr_dma_pkt_lo; + logic [lg_num_cache_lp-1:0] rr_tag_lo; + + logic [lg_num_cache_lp-1:0] rr_tag_r, rr_tag_n; + bsg_cache_dma_pkt_s dma_pkt_r, dma_pkt_n; + + bsg_round_robin_n_to_1 #( + .width_p(dma_pkt_width_lp) + ,.num_in_p(num_cache_p) + ,.strict_p(0) + ,.use_scan_p(1) + ) rr0 ( + .clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.data_i(dma_pkt) + ,.v_i(dma_pkt_v_i) + ,.yumi_o(dma_pkt_yumi_o) + + ,.v_o(rr_v_lo) + ,.data_o(rr_dma_pkt_lo) + ,.tag_o(rr_tag_lo) + ,.yumi_i(rr_yumi_li) + ); + + + + logic counter_clear; + logic counter_up; + logic [lg_num_req_lp-1:0] count_r; // this counts the number of DRAM requests sent. + + bsg_counter_clear_up #( + .max_val_p(num_req_lp-1) + ,.init_val_p(0) + ) ccu0 ( + .clk_i(core_clk_i) + ,.reset_i(core_reset_i) + ,.clear_i(counter_clear) + ,.up_i(counter_up) + ,.count_o(count_r) + ); + + logic [dram_channel_addr_width_p-1:0] dram_req_addr; + + + // request async fifo + // + logic req_afifo_enq; + logic req_afifo_full; + + bsg_async_fifo #( + .lg_size_p(`BSG_SAFE_CLOG2(4*num_cache_p)) + ,.width_p(1+dram_channel_addr_width_p) + ) req_afifo ( + .w_clk_i(core_clk_i) + ,.w_reset_i(core_reset_i) + ,.w_enq_i(req_afifo_enq) + ,.w_data_i({dma_pkt_n.write_not_read, dram_req_addr}) + ,.w_full_o(req_afifo_full) + + ,.r_clk_i(dram_clk_i) + ,.r_reset_i(dram_reset_i) + ,.r_deq_i(dram_req_yumi_i) + ,.r_data_o({dram_write_not_read_o, dram_ch_addr_o}) + ,.r_valid_o(dram_req_v_o) + ); + + + // RX + // + bsg_cache_to_test_dram_rx #( + .num_cache_p(num_cache_p) + ,.data_width_p(data_width_p) + ,.dma_data_width_p(dma_data_width_p) + ,.dram_data_width_p(dram_data_width_p) + ,.dram_channel_addr_width_p(dram_channel_addr_width_p) + ,.block_size_in_words_p(block_size_in_words_p) + ) rx0 ( + .core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.dma_data_o(dma_data_o) + ,.dma_data_v_o(dma_data_v_o) + ,.dma_data_ready_and_i(dma_data_ready_and_i) + + ,.dram_clk_i(dram_clk_i) + ,.dram_reset_i(dram_reset_i) + + ,.dram_data_v_i(dram_data_v_i) + ,.dram_data_i(dram_data_i) + ,.dram_ch_addr_i(dram_ch_addr_i) + ); + + + // TX + // + logic tx_v_li; + logic tx_ready_and_lo; + logic [(block_size_in_words_p/num_req_lp)-1:0] tx_mask_li; + + bsg_cache_to_test_dram_tx #( + .num_cache_p(num_cache_p) + ,.data_width_p(data_width_p) + ,.block_size_in_words_p(block_size_in_words_p) + ,.dma_data_width_p(dma_data_width_p) + ,.dram_data_width_p(dram_data_width_p) + ) tx0 ( + .core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.v_i(tx_v_li) + ,.tag_i(rr_tag_n) + ,.mask_i(tx_mask_li) + ,.ready_and_o(tx_ready_and_lo) + + ,.dma_data_i(dma_data_i) + ,.dma_data_v_i(dma_data_v_i) + ,.dma_data_yumi_o(dma_data_yumi_o) + + ,.dram_clk_i(dram_clk_i) + ,.dram_reset_i(dram_reset_i) + + ,.dram_data_v_o(dram_data_v_o) + ,.dram_data_o(dram_data_o) + ,.dram_mask_o(dram_mask_o) + ,.dram_data_yumi_i(dram_data_yumi_i) + ); + + + if (num_req_lp == 1) begin: req1 + assign counter_up = 1'b0; + assign counter_clear = 1'b0; + assign rr_yumi_li = rr_v_lo & ~req_afifo_full & (rr_dma_pkt_lo.write_not_read ? tx_ready_and_lo : 1'b1); + assign req_afifo_enq = rr_v_lo & ~req_afifo_full & (rr_dma_pkt_lo.write_not_read ? tx_ready_and_lo : 1'b1); + assign tx_v_li = rr_v_lo & ~req_afifo_full & rr_dma_pkt_lo.write_not_read & tx_ready_and_lo; + assign rr_tag_n = rr_tag_lo; + assign dma_pkt_n = rr_dma_pkt_lo; + assign tx_mask_li = rr_dma_pkt_lo.mask; + end + else begin: reqn + + always_comb begin + counter_up = 1'b0; + counter_clear = 1'b0; + rr_yumi_li = 1'b0; + req_afifo_enq = 1'b0; + tx_v_li = 1'b0; + rr_tag_n = rr_tag_r; + dma_pkt_n = dma_pkt_r; + + if (count_r == 0) begin + if (rr_v_lo & ~req_afifo_full & (rr_dma_pkt_lo.write_not_read ? tx_ready_and_lo : 1'b1)) begin + counter_up = 1'b1; + rr_yumi_li = 1'b1; + req_afifo_enq = 1'b1; + tx_v_li = rr_dma_pkt_lo.write_not_read; + rr_tag_n = rr_tag_lo; + dma_pkt_n = rr_dma_pkt_lo; + end + end + else if (count_r == num_req_lp-1) begin + if (~req_afifo_full & (dma_pkt_r.write_not_read ? tx_ready_and_lo : 1'b1)) begin + counter_clear = 1'b1; + req_afifo_enq = 1'b1; + tx_v_li = dma_pkt_r.write_not_read; + end + end + else begin + if (~req_afifo_full & (dma_pkt_r.write_not_read ? tx_ready_and_lo : 1'b1)) begin + counter_up = 1'b1; + req_afifo_enq = 1'b1; + tx_v_li = dma_pkt_r.write_not_read; + end + end + end + + bsg_mux #( + .els_p(num_req_lp) + ,.width_p(block_size_in_words_p/num_req_lp) + ) mask_mux ( + .data_i(dma_pkt_n.mask) + ,.sel_i(count_r) + ,.data_o(tx_mask_li) + ); + + end + + + always_ff @ (posedge core_clk_i) begin + if (core_reset_i) begin + dma_pkt_r <= '0; + rr_tag_r <= '0; + end + else begin + dma_pkt_r <= dma_pkt_n; + rr_tag_r <= rr_tag_n; + end + end + + // address logic + if (num_cache_p == 1) begin + if (num_req_lp == 1) begin + assign dram_req_addr = { + {(dram_channel_addr_width_p-cache_bank_addr_width_p){1'b0}}, + dma_pkt_n.addr[cache_bank_addr_width_p-1:dram_byte_offset_width_lp], + {dram_byte_offset_width_lp{1'b0}} + }; + end + else begin + assign dram_req_addr = { + {(dram_channel_addr_width_p-cache_bank_addr_width_p){1'b0}}, + dma_pkt_n.addr[cache_bank_addr_width_p-1:dram_byte_offset_width_lp+lg_num_req_lp], + count_r, + {dram_byte_offset_width_lp{1'b0}} + }; + end + end + else begin + if (num_req_lp == 1) begin + assign dram_req_addr = { + rr_tag_n, + {(dram_channel_addr_width_p-cache_bank_addr_width_p-lg_num_cache_lp){1'b0}}, + dma_pkt_n.addr[cache_bank_addr_width_p-1:dram_byte_offset_width_lp], + {dram_byte_offset_width_lp{1'b0}} + }; + end + else begin + assign dram_req_addr = { + rr_tag_n, + {(dram_channel_addr_width_p-cache_bank_addr_width_p-lg_num_cache_lp){1'b0}}, + dma_pkt_n.addr[cache_bank_addr_width_p-1:dram_byte_offset_width_lp+lg_num_req_lp], + count_r, + {dram_byte_offset_width_lp{1'b0}} + }; + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_rx.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_rx.sv new file mode 100644 index 0000000..4d509e9 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_rx.sv @@ -0,0 +1,154 @@ +/** + * bsg_cache_to_test_dram_rx.sv + * + */ + + +`include "bsg_defines.sv" + +module bsg_cache_to_test_dram_rx + #(parameter `BSG_INV_PARAM(num_cache_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(dma_data_width_p) + , parameter `BSG_INV_PARAM(block_size_in_words_p) + + , parameter `BSG_INV_PARAM(dram_data_width_p) + , parameter `BSG_INV_PARAM(dram_channel_addr_width_p) + + , parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p) + , parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p) + + ) + ( + input core_clk_i + , input core_reset_i + + , output logic [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_o + , output logic [num_cache_p-1:0] dma_data_v_o + , input [num_cache_p-1:0] dma_data_ready_and_i + + , input dram_clk_i + , input dram_reset_i + + , input dram_data_v_i + , input [dram_data_width_p-1:0] dram_data_i + , input [dram_channel_addr_width_p-1:0] dram_ch_addr_i + ); + + + // ch_addr CDC + // + logic ch_addr_afifo_full; + logic ch_addr_afifo_deq; + logic [dram_channel_addr_width_p-1:0] ch_addr_lo; + logic ch_addr_v_lo; + + bsg_async_fifo #( + .lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_req_lp*num_cache_p,4))) + ,.width_p(dram_channel_addr_width_p) + ) ch_addr_afifo ( + .w_clk_i(dram_clk_i) + ,.w_reset_i(dram_reset_i) + ,.w_enq_i(dram_data_v_i) + ,.w_data_i(dram_ch_addr_i) + ,.w_full_o(ch_addr_afifo_full) + + ,.r_clk_i(core_clk_i) + ,.r_reset_i(core_reset_i) + ,.r_deq_i(ch_addr_afifo_deq) + ,.r_data_o(ch_addr_lo) + ,.r_valid_o(ch_addr_v_lo) + ); + + + + // data CDC + // + logic data_afifo_full; + logic data_afifo_deq; + logic [dram_data_width_p-1:0] dram_data_lo; + logic dram_data_v_lo; + + bsg_async_fifo #( + .lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_req_lp*num_cache_p,4))) + ,.width_p(dram_data_width_p) + ) data_afifo ( + .w_clk_i(dram_clk_i) + ,.w_reset_i(dram_reset_i) + ,.w_enq_i(dram_data_v_i) + ,.w_data_i(dram_data_i) + ,.w_full_o(data_afifo_full) + + ,.r_clk_i(core_clk_i) + ,.r_reset_i(core_reset_i) + ,.r_deq_i(data_afifo_deq) + ,.r_data_o(dram_data_lo) + ,.r_valid_o(dram_data_v_lo) + ); + + + // reorder buffer + // + logic [num_cache_p-1:0] reorder_v_li; + + for (genvar i = 0; i < num_cache_p; i++) begin: re + bsg_cache_to_test_dram_rx_reorder #( + .data_width_p(data_width_p) + ,.dma_data_width_p(dma_data_width_p) + ,.block_size_in_words_p(block_size_in_words_p) + + ,.dram_data_width_p(dram_data_width_p) + ,.dram_channel_addr_width_p(dram_channel_addr_width_p) + ) reorder0 ( + .core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.dram_v_i(reorder_v_li[i]) + ,.dram_data_i(dram_data_lo) + ,.dram_ch_addr_i(ch_addr_lo) + + ,.dma_data_o(dma_data_o[i]) + ,.dma_data_v_o(dma_data_v_o[i]) + ,.dma_data_ready_and_i(dma_data_ready_and_i[i]) + ); + end + + + // using the ch address, forward the data to the correct cache. + logic [lg_num_cache_lp-1:0] cache_id; + + if (num_cache_p == 1) begin + assign cache_id = 1'b0; + end + else begin + assign cache_id = ch_addr_lo[dram_channel_addr_width_p-1-:lg_num_cache_lp]; + end + + + bsg_decode_with_v #( + .num_out_p(num_cache_p) + ) demux0 ( + .i(cache_id) + ,.v_i(ch_addr_v_lo & dram_data_v_lo) + ,.o(reorder_v_li) + ); + + assign data_afifo_deq = ch_addr_v_lo & dram_data_v_lo; + assign ch_addr_afifo_deq = ch_addr_v_lo & dram_data_v_lo; + + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + always_ff @ (negedge dram_clk_i) begin + if (~dram_reset_i & dram_data_v_i) begin + assert(~data_afifo_full) else $fatal(1, "data async_fifo full!"); + assert(~ch_addr_afifo_full) else $fatal(1, "ch_addr async_fifo full!"); + end + end + +`endif + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram_rx) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_rx_reorder.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_rx_reorder.sv new file mode 100644 index 0000000..d5a7220 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_rx_reorder.sv @@ -0,0 +1,159 @@ +/** + * bsg_cache_to_test_dram_rx_reorder.sv + * + * This module reorders dram data arriving out of order, and serializes them before feeding into vcache. + * + */ + + +`include "bsg_defines.sv" + +module bsg_cache_to_test_dram_rx_reorder + #(parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(dma_data_width_p) + , parameter `BSG_INV_PARAM(block_size_in_words_p) + + , parameter `BSG_INV_PARAM(dram_data_width_p) + , parameter `BSG_INV_PARAM(dram_channel_addr_width_p) + + , parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p) + , parameter lg_num_req_lp = `BSG_SAFE_CLOG2(num_req_lp) + + , parameter dram_data_byte_offset_width_lp = `BSG_SAFE_CLOG2(dram_data_width_p>>3) + ) + ( + + input core_clk_i + , input core_reset_i + + , input dram_v_i + , input [dram_data_width_p-1:0] dram_data_i + , input [dram_channel_addr_width_p-1:0] dram_ch_addr_i + + , output logic [dma_data_width_p-1:0] dma_data_o + , output logic dma_data_v_o + , input dma_data_ready_and_i + ); + + logic piso_ready_lo; + logic piso_v_li; + logic [dram_data_width_p-1:0] piso_data_li; + + bsg_parallel_in_serial_out #( + .width_p(dma_data_width_p) + ,.els_p(dram_data_width_p/dma_data_width_p) + ) piso ( + .clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.valid_i(piso_v_li) + ,.data_i(piso_data_li) + ,.ready_and_o(piso_ready_lo) + + ,.valid_o(dma_data_v_o) + ,.data_o(dma_data_o) + ,.yumi_i(dma_data_v_o & dma_data_ready_and_i) + ); + + if (num_req_lp == 1) begin: req1 + + // if there is only one DRAM request, there is no need to reorder. + assign piso_data_li = dram_data_i; + assign piso_v_li = dram_v_i; + wire unused = |dram_ch_addr_i; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @ (negedge core_clk_i) begin + if (~core_reset_i & dram_v_i) begin + assert(piso_ready_lo) else $fatal(1, "piso is not ready!"); + end + end +`endif + + end + else begin: reqn + + // reordering logic + // when the data arrives during its turn, go into the piso, if the piso is ready. Then, increment the counter. + // If the piso is not ready, then go into the buffer. + // If the piso is ready, and the data is available in the buffer, put that in piso and increment the counter. + // when the data arrives and it's not its turn, then wait in the buffer. + + wire [lg_num_req_lp-1:0] req_num = dram_ch_addr_i[dram_data_byte_offset_width_lp+:lg_num_req_lp]; + + // data that is not ready to go into piso is buffered here. + logic [dram_data_width_p-1:0] data_buffer_r [num_req_lp-1:0]; + logic [num_req_lp-1:0] data_buffer_v_r; + + logic counter_clear; + logic counter_up; + logic [lg_num_req_lp-1:0] count_r; + + // this counts the number of DRAM data that have arrived and been fed into the piso. + // the data is fed into the piso sequentially in address order. + bsg_counter_clear_up #( + .max_val_p(num_req_lp-1) + ,.init_val_p(0) + ) c0 ( + .clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.clear_i(counter_clear) + ,.up_i(counter_up) + + ,.count_o(count_r) + ); + + logic clear_buffer; + logic write_buffer; + + always_comb begin + + piso_v_li = 1'b0; + piso_data_li = dram_data_i; + counter_clear = 1'b0; + counter_up = 1'b0; + clear_buffer = 1'b0; + write_buffer = 1'b0; + + if (count_r == num_req_lp-1) begin + piso_v_li = data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i); + piso_data_li = data_buffer_v_r[count_r] + ? data_buffer_r[count_r] + : dram_data_i; + counter_clear = piso_ready_lo & (data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i)); + write_buffer = ~piso_ready_lo & dram_v_i; + clear_buffer = piso_ready_lo & (data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i)); + end + else begin + piso_v_li = data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i); + piso_data_li = data_buffer_v_r[count_r] + ? data_buffer_r[count_r] + : dram_data_i; + counter_up = piso_ready_lo & (data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i)); + write_buffer = (dram_v_i & ((req_num != count_r) | ~piso_ready_lo)); + end + + end + + always_ff @ (posedge core_clk_i) begin + if (core_reset_i) begin + data_buffer_v_r <= '0; + end + else begin + if (clear_buffer) begin + data_buffer_v_r <= '0; + end + else if (write_buffer) begin + data_buffer_v_r[req_num] <= 1'b1; + data_buffer_r[req_num] <= dram_data_i; + end + end + end + + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram_rx_reorder) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_tx.sv b/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_tx.sv new file mode 100644 index 0000000..67ef058 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cache_to_test_dram_tx.sv @@ -0,0 +1,177 @@ +/** + * bsg_cache_to_test_dram_tx.sv + * + */ + + +`include "bsg_defines.sv" + +module bsg_cache_to_test_dram_tx + #(parameter `BSG_INV_PARAM(num_cache_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(block_size_in_words_p) + , parameter `BSG_INV_PARAM(dma_data_width_p) + + , parameter `BSG_INV_PARAM(dram_data_width_p) + + , parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p) + , parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p) + ) + ( + input core_clk_i + , input core_reset_i + + , input v_i + , input [lg_num_cache_lp-1:0] tag_i + , input [(block_size_in_words_p/num_req_lp)-1:0] mask_i // one bit per data_width_p + , output logic ready_and_o + + , input [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_i + , input [num_cache_p-1:0] dma_data_v_i + , output logic [num_cache_p-1:0] dma_data_yumi_o + + , input dram_clk_i + , input dram_reset_i + + , output logic dram_data_v_o + , output logic [dram_data_width_p-1:0] dram_data_o + , output logic [(dram_data_width_p>>3)-1:0] dram_mask_o // one bit per byte + , input dram_data_yumi_i + ); + + + // tag + mask fifo + // + logic tag_v_lo; + logic [lg_num_cache_lp-1:0] tag_lo; + logic [(block_size_in_words_p/num_req_lp)-1:0] mask_lo; + logic tag_yumi_li; + + bsg_fifo_1r1w_small #( + .width_p(lg_num_cache_lp+(block_size_in_words_p/num_req_lp)) + ,.els_p(num_cache_p*num_req_lp) + ) tag_fifo ( + .clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.v_i(v_i) + ,.ready_param_o(ready_and_o) + ,.data_i({tag_i, mask_i}) + + ,.v_o(tag_v_lo) + ,.data_o({tag_lo, mask_lo}) + ,.yumi_i(tag_yumi_li) + ); + + + // de-serialization + // + logic [num_cache_p-1:0] sipo_v_li; + logic [num_cache_p-1:0] sipo_ready_lo; + logic [num_cache_p-1:0][dma_data_width_p-1:0] sipo_data_li; + + logic [num_cache_p-1:0] sipo_v_lo; + logic [num_cache_p-1:0][dram_data_width_p-1:0] sipo_data_lo; + logic [num_cache_p-1:0] sipo_yumi_li; + + for (genvar i = 0; i < num_cache_p; i++) begin + + bsg_serial_in_parallel_out_full #( + .width_p(dma_data_width_p) + ,.els_p(dram_data_width_p/dma_data_width_p) + ) sipo ( + .clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.v_i(sipo_v_li[i]) + ,.data_i(sipo_data_li[i]) + ,.ready_and_o(sipo_ready_lo[i]) + + ,.v_o(sipo_v_lo[i]) + ,.data_o(sipo_data_lo[i]) + ,.yumi_i(sipo_yumi_li[i]) + ); + + end + + + if (num_req_lp == 1) begin + assign sipo_v_li = dma_data_v_i; + assign sipo_data_li = dma_data_i; + assign dma_data_yumi_o = dma_data_v_i & sipo_ready_lo; + end + else begin + logic [num_cache_p-1:0] fifo_ready_lo; + + for (genvar i = 0; i < num_cache_p; i++) begin + bsg_fifo_1r1w_small #( + .width_p(dma_data_width_p) + ,.els_p(block_size_in_words_p*data_width_p/dma_data_width_p) + ) fifo0 ( + .clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.v_i(dma_data_v_i[i]) + ,.ready_param_o(fifo_ready_lo[i]) + ,.data_i(dma_data_i[i]) + + ,.v_o(sipo_v_li[i]) + ,.data_o(sipo_data_li[i]) + ,.yumi_i(sipo_v_li[i] & sipo_ready_lo[i]) + ); + + assign dma_data_yumi_o[i] = fifo_ready_lo[i] & dma_data_v_i[i]; + end + + end + + + // async fifo (data + mask) + // + logic afifo_full; + logic [dram_data_width_p-1:0] afifo_data_li; + logic afifo_enq; + logic [(block_size_in_words_p/num_req_lp)-1:0] afifo_mask_lo; + + bsg_async_fifo #( + .lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_cache_p*num_req_lp,4))) + ,.width_p(dram_data_width_p+(block_size_in_words_p/num_req_lp)) + ) data_afifo ( + .w_clk_i(core_clk_i) + ,.w_reset_i(core_reset_i) + ,.w_enq_i(afifo_enq) + ,.w_data_i({mask_lo, afifo_data_li}) + ,.w_full_o(afifo_full) + + ,.r_clk_i(dram_clk_i) + ,.r_reset_i(dram_reset_i) + ,.r_deq_i(dram_data_yumi_i) + ,.r_data_o({afifo_mask_lo, dram_data_o}) + ,.r_valid_o(dram_data_v_o) + ); + + wire send_data = tag_v_lo & ~afifo_full & sipo_v_lo[tag_lo]; + assign afifo_enq = send_data; + assign tag_yumi_li = send_data; + assign afifo_data_li = sipo_data_lo[tag_lo]; + + bsg_decode_with_v #( + .num_out_p(num_cache_p) + ) demux0 ( + .i(tag_lo) + ,.v_i(send_data) + ,.o(sipo_yumi_li) + ); + + bsg_expand_bitmask #( + .in_width_p(block_size_in_words_p/num_req_lp) + ,.expand_p(data_width_p>>3) + ) expand0 ( + .i(afifo_mask_lo) + ,.o(dram_mask_o) + ); + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram_tx) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_replacement.sv b/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_replacement.sv new file mode 100644 index 0000000..2d30a22 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_replacement.sv @@ -0,0 +1,165 @@ + +// +// Maintains the replacement policy for an array of elements +// The scheme is synchronously updated when v_i goes high, and asynchronously +// outputs the selected way for replacement based on internal and emptiness +// +// Currently supported schemes +// LRU: +// - Both alloc and read operations update LRU in parallel +// - Allocation is performed logically before the read update +// - If the read and alloc refer to the same set, all is well, +// since the LRU update is idempotent. +`include "bsg_defines.sv" + +module bsg_cam_1r1w_replacement + #(parameter els_p = 2 + // Which replacement scheme to use + , parameter scheme_p = "lru" + + , parameter safe_els_lp = `BSG_MAX(els_p,1) + ) + (input clk_i + , input reset_i + + // Synchronous update (i.e. indicate that an entry was read) + , input [safe_els_lp-1:0] read_v_i + + // May use combination of internal state and empty vector + // to determine replacement + // Synchronous update (i.e. indicate that an entry was allocated) + , input alloc_v_i + , input [safe_els_lp-1:0] alloc_empty_i + , output [safe_els_lp-1:0] alloc_v_o + ); + + if (els_p == 0) + begin : zero + assign alloc_v_o = 1'b0; + end + else if (els_p == 1) + begin : one + assign alloc_v_o = 1'b1; + end + // Standard tree-based pseudo-lru + else if (scheme_p == "lru") + begin : lru + localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p); + + wire read_v_li = |read_v_i; + wire lru_touch_li = read_v_li | alloc_v_i; + + // LRU storage + logic [els_p-2:0] lru_n, lru_r; + bsg_dff_reset_en + #(.width_p(els_p-1)) + lru_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(lru_touch_li) + + ,.data_i(lru_n) + ,.data_o(lru_r) + ); + + // + // Selection output logic + // + // Encode the one-hot way select based on LRU + logic [lg_els_lp-1:0] lru_way_lo; + bsg_lru_pseudo_tree_encode + #(.ways_p(els_p)) + lru_encoder + (.lru_i(lru_r) + ,.way_id_o(lru_way_lo) + ); + + // Find an empty way if one exists + logic [lg_els_lp-1:0] empty_way_lo; + logic empty_way_v_lo; + bsg_priority_encode + #(.width_p(els_p), .lo_to_hi_p(1)) + empty_encoder + (.i(alloc_empty_i) + ,.addr_o(empty_way_lo) + ,.v_o(empty_way_v_lo) + ); + + // Select the empty way if one exists; else, use LRU + wire [lg_els_lp-1:0] way_lo = empty_way_v_lo ? empty_way_lo : lru_way_lo; + + // Output the one-hot way selected + bsg_decode + #(.num_out_p(els_p)) + way_decoder + (.i(way_lo) + ,.o(alloc_v_o) + ); + + // + // LRU update logic + // + // Encode the one-hot way read inputs to this module + logic [lg_els_lp-1:0] read_way_li; + bsg_encode_one_hot + #(.width_p(els_p)) + read_way_encoder + (.i(read_v_i) + ,.addr_o(read_way_li) + ,.v_o() + ); + + // Decides which way to update based on read MRU + logic [els_p-2:0] read_update_data_lo, read_update_mask_lo; + bsg_lru_pseudo_tree_decode + #(.ways_p(els_p)) + read_decoder + (.way_id_i(read_way_li) + ,.data_o(read_update_data_lo) + ,.mask_o(read_update_mask_lo) + ); + + // Muxes in the update data to compute the next LRU state + // This doesn't get latched in unless there's an active use + logic [els_p-2:0] read_update_lo; + wire [els_p-2:0] read_sel_lo = read_update_mask_lo & {(els_p-1){read_v_li}}; + bsg_mux_bitwise + #(.width_p(els_p-1)) + read_update_mux + (.data0_i(lru_r) + ,.data1_i(read_update_data_lo) + ,.sel_i(read_sel_lo) + ,.data_o(read_update_lo) + ); + + // Decides which way to update based on write MRU + logic [els_p-2:0] alloc_update_data_lo, alloc_update_mask_lo; + bsg_lru_pseudo_tree_decode + #(.ways_p(els_p)) + alloc_decoder + (.way_id_i(way_lo) + ,.data_o(alloc_update_data_lo) + ,.mask_o(alloc_update_mask_lo) + ); + + logic [els_p-2:0] alloc_update_lo; + wire [els_p-2:0] alloc_sel_lo = alloc_update_mask_lo & {(els_p-1){alloc_v_i}}; + bsg_mux_bitwise + #(.width_p(els_p-1)) + alloc_update_mux + (.data0_i(read_update_lo) + ,.data1_i(alloc_update_data_lo) + ,.sel_i(alloc_sel_lo) + ,.data_o(alloc_update_lo) + ); + + assign lru_n = alloc_update_lo; + end + + initial + begin + assert (scheme_p == "lru") else $error("Only LRU scheme is currently supported"); + end + +endmodule + diff --git a/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_sync.sv b/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_sync.sv new file mode 100644 index 0000000..a0ab2d4 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_sync.sv @@ -0,0 +1,76 @@ +/* + * Synchnronous read 1r1w content addressable memory module. + * Each entry has a tag and a data associated with it + * - Read searches the array for any data with r_tag_i + * - Write allocates a new entry, replacing an existing entry with replacement + * scheme repl_scheme_p + * - Write with w_nuke_i flag invalidates the cam + */ + +`include "bsg_defines.sv" + +module bsg_cam_1r1w_sync + #(parameter `BSG_INV_PARAM(els_p) + ,parameter `BSG_INV_PARAM(tag_width_p) + ,parameter `BSG_INV_PARAM(data_width_p) + + // The replacement scheme for the CAM + , parameter repl_scheme_p = "lru" + ) + (input clk_i + , input reset_i + + // Synchronous write/invalidate of a tag + , input w_v_i + // When w_v_i & w_nuke_i, the whole cam array is invalidated + , input w_nuke_i + // Tag/data to set on write + , input [tag_width_p-1:0] w_tag_i + , input [data_width_p-1:0] w_data_i + + // Synchronous read of a tag, if exists + , input r_v_i + , input [tag_width_p-1:0] r_tag_i + + , output logic [data_width_p-1:0] r_data_o + , output logic r_v_o + ); + + // Latch the read request for a synchronous read + logic [tag_width_p-1:0] r_tag_r; + logic r_v_r; + bsg_dff + #(.width_p(1+tag_width_p)) + r_tag_reg + (.clk_i(clk_i) + + ,.data_i({r_v_i, r_tag_i}) + ,.data_o({r_v_r, r_tag_r}) + ); + + // Read from asynchronous CAM + bsg_cam_1r1w + #(.els_p(els_p) + ,.tag_width_p(tag_width_p) + ,.data_width_p(data_width_p) + ,.repl_scheme_p(repl_scheme_p) + ) + cam + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(w_v_i) + ,.w_nuke_i(w_nuke_i) + ,.w_tag_i(w_tag_i) + ,.w_data_i(w_data_i) + + ,.r_v_i(r_v_r) + ,.r_tag_i(r_tag_r) + ,.r_data_o(r_data_o) + ,.r_v_o(r_v_o) + ); + +endmodule + + +`BSG_ABSTRACT_MODULE(bsg_cam_1r1w_sync) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_tag_array.sv b/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_tag_array.sv new file mode 100644 index 0000000..fa0ba66 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_tag_array.sv @@ -0,0 +1,90 @@ +/* + * This module is made for use in bsg_cams, managing the valids and tags for each entry. + * We separate v_rs and tags so that we can support reset with minimal hardware. + * This module does not protect against setting multiple entries to the same value -- this must be + * prevented at a higher protocol level, if desired + */ +`include "bsg_defines.sv" + +module bsg_cam_1r1w_tag_array + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + + , parameter multiple_entries_p = 0 + + , parameter safe_els_lp = `BSG_MAX(els_p,1) + ) + (input clk_i + , input reset_i + + // zero or one-hot + , input [safe_els_lp-1:0] w_v_i + // Mutually exclusive set or clear + , input w_set_not_clear_i + // Tag to set or clear + , input [width_p-1:0] w_tag_i + // Vector of empty CAM entries + , output logic [safe_els_lp-1:0] w_empty_o + + // Async read + , input r_v_i + // Tag to match on read + , input [width_p-1:0] r_tag_i + // one or zero-hot + , output logic [safe_els_lp-1:0] r_match_o + ); + + logic [safe_els_lp-1:0][width_p-1:0] tag_r; + logic [safe_els_lp-1:0] v_r; + + if (els_p == 0) + begin : zero + assign w_empty_o = '0; + assign r_match_o = '0; + end + else + begin : nz + for (genvar i = 0; i < els_p; i++) + begin : tag_array + bsg_dff_reset_en + #(.width_p(1)) + v_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.en_i(w_v_i[i]) + ,.data_i(w_set_not_clear_i) + + ,.data_o(v_r[i]) + ); + + bsg_dff_en + #(.width_p(width_p)) + tag_r_reg + (.clk_i(clk_i) + + ,.en_i(w_v_i[i] & w_set_not_clear_i) + ,.data_i(w_tag_i) + ,.data_o(tag_r[i]) + ); + + assign r_match_o[i] = r_v_i & v_r[i] & (tag_r[i] == r_tag_i); + assign w_empty_o[i] = ~v_r[i]; + end + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @(negedge clk_i) begin + assert(multiple_entries_p || reset_i || $countones(r_match_o) <= 1) + else $error("Multiple similar entries are found in match_array\ + %x while multiple_entries_p parameter is %d\n", r_match_o, + multiple_entries_p); + + assert(reset_i || $countones(w_v_i & {safe_els_lp{w_set_not_clear_i}}) <= 1) + else $error("Inv_r one-hot write address %b\n", w_v_i); + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cam_1r1w_tag_array) diff --git a/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_unmanaged.sv b/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_unmanaged.sv new file mode 100644 index 0000000..6072848 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_cam_1r1w_unmanaged.sv @@ -0,0 +1,84 @@ +/* + * Asynchronous read 1r1w content addressable memory module. + * Each entry has a tag and a data associated with it, and can be + * independently cleared and set + * + * This module is similar to bsg_cam_1r1w, except it allows for an + * external replacement scheme + */ + +`include "bsg_defines.sv" + +module bsg_cam_1r1w_unmanaged + #(parameter `BSG_INV_PARAM(els_p) + , parameter `BSG_INV_PARAM(tag_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + + , parameter safe_els_lp = `BSG_MAX(els_p,1) + ) + (input clk_i + , input reset_i + + // Synchronous write/invalidate of a tag + // one or zero-hot + , input [safe_els_lp-1:0] w_v_i + , input w_set_not_clear_i + // Tag/data to set on write + , input [tag_width_p-1:0] w_tag_i + , input [data_width_p-1:0] w_data_i + // Metadata useful for an external replacement policy + // Whether there's an empty entry in the tag array + , output [safe_els_lp-1:0] w_empty_o + + // Asynchronous read of a tag, if exists + , input r_v_i + , input [tag_width_p-1:0] r_tag_i + , output logic [data_width_p-1:0] r_data_o + , output logic r_v_o + ); + + // The tag storage for the CAM + logic [safe_els_lp-1:0] tag_r_match_lo; + logic [safe_els_lp-1:0] tag_empty_lo; + logic [safe_els_lp-1:0] tag_w_v_li; + bsg_cam_1r1w_tag_array + #(.width_p(tag_width_p) + ,.els_p(safe_els_lp) + ) + cam_tag_array + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(w_v_i) + ,.w_set_not_clear_i(w_set_not_clear_i) + ,.w_tag_i(w_tag_i) + ,.w_empty_o(w_empty_o) + + ,.r_v_i(r_v_i) + ,.r_tag_i(r_tag_i) + ,.r_match_o(tag_r_match_lo) + ); + + // The data storage for the CAM + logic [safe_els_lp-1:0] mem_w_v_li; + bsg_mem_1r1w_one_hot + #(.width_p(data_width_p) + ,.els_p(safe_els_lp) + ) + one_hot_mem + (.w_clk_i(clk_i) + ,.w_reset_i(reset_i) + + ,.w_v_i(w_v_i) + ,.w_data_i(w_data_i) + + ,.r_v_i(tag_r_match_lo) + ,.r_data_o(r_data_o) + ); + + assign r_v_o = |tag_r_match_lo; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_cam_1r1w_unmanaged) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel.sv b/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel.sv new file mode 100644 index 0000000..e343b64 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel.sv @@ -0,0 +1,176 @@ +// MBT 7/7/16 +// +// bsg_channel_tunnel +// +// This module allows you to multiplex multiple streams over a shared +// interconnect without having deadlock occur because of stream interleaving. +// +// There are three models for interleaving streams: +// +// a. Your stream is guaranteed to be sunk by the remote node without +// dependence on external factors, and does not rely upon back pressure. +// In this case you avoid deadlock but may have fairness issues. Here, you +// attach directly to the shared interconnect (e.g. bsg_fsb). +// +// b. Your streams rely upon back pressure from the remote node. Here, you +// can use multiple bsg_channel_tunnel modules, one for each stream. +// This ensures that you do not deadlock, but it does not address unfairness +// in the interconnect that may lead to starvation. +// +// c. Your stream rely upon back pressure from the remote node. In this +// scenario, you use one bsg_channel_tunnel across multiple streams. +// Within this group of streams, you will have round-robin fairness. +// +// Channel tunneling is like virtual channels except that it includes +// credits as part of the channels, and it does not +// require the virtual channels to demultiplex at every step. +// +// Finally, especially when crossing chip boundaries (and using case c), +// we can aggregrate the FIFO space into a single +// large FIFO which is more efficient per bit than many smaller FIFOs. +// +// 1. remote_credits_p typical set to 2X bandwidth delay product of link +// +// ASIC<->ASIC +// +// e.g. if the core frequency is 1000 MHz, and the off-chip frequency +// is 300 MHz, and the off-chip link is 0.4 word/cycle, and the 1-way latency +// in the core domain is 5 cycles, and the latency in the off-chip +// domain is 10 cycles, then: +// +// one-way chip latency = 5 * 1 ns + 10 * 3.3 ns = 38.3 ns +// bandwidth = 0.4 words / 3.33 ns = .133 words / ns +// bandwidth * delay = .133 * 35 = 4.6 words +// +// * 2 ASICS = 9.2 words +// * 2 (roundtrip) = 18.4 words +// +// ASIC<->FPGA +// +// note, if there is an FPGA in the loop, then latencies blow up. +// suppose the FPGA runs at 300*.4 = 120 Mhz=8.3ns, and so the on-FPGA latency +// is 38.3 * (8.3) = 314 ns. then one way latency is 352 ns, and buffering is +// (.133 * (352))*2 = 93 words. +// +// 2. area grows as num_in_p * remote_credits_p +// +// +// 3. area for all channels can be stored in a single place when using alternate +// implementations of virtual fifos +// + +`include "bsg_defines.sv" + +module bsg_channel_tunnel #(parameter width_p = 1 + , parameter `BSG_INV_PARAM(num_in_p) + , parameter `BSG_INV_PARAM(remote_credits_p) + , use_pseudo_large_fifo_p = 0 + , harden_small_fifo_p = 0 + , lg_remote_credits_lp = $clog2(remote_credits_p+1) + , lg_credit_decimation_p = `BSG_MIN(lg_remote_credits_lp,4) + , tag_width_lp = $clog2(num_in_p+1) + , tagged_width_lp = tag_width_lp + width_p + + ) + (input clk_i + ,input reset_i + + // incoming multiplexed data + ,input [tagged_width_lp-1:0] multi_data_i + ,input multi_v_i + ,output multi_yumi_o + + // outgoing multiplexed data + , output [tagged_width_lp-1:0] multi_data_o + , output multi_v_o + , input multi_yumi_i + + // incoming demultiplexed data + , input [num_in_p-1:0][width_p-1:0] data_i + , input [num_in_p-1:0] v_i + , output [num_in_p-1:0] yumi_o + + // outgoing demultiplexed data + , output [num_in_p-1:0][width_p-1:0] data_o + , output [num_in_p-1:0] v_o + , input [num_in_p-1:0] yumi_i + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + assert(lg_credit_decimation_p <= lg_remote_credits_lp) + else + begin + $error("%m bad params; insufficient remote credits 2^%d to allow for decimation factor 2^%d" + ,lg_remote_credits_lp,lg_credit_decimation_p); + $finish; + end + initial + assert(width_p >= num_in_p*lg_remote_credits_lp) + else + begin + $error("%m bad params; channel width (%d) must be at least wide enough to route back credits (%d)" + ,width_p + ,num_in_p*lg_remote_credits_lp); + $finish; + end +`endif + + wire [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_oi; + wire credit_local_return_v_oi; + + wire [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_oi; + wire credit_remote_return_yumi_io; + + + bsg_channel_tunnel_out #(.width_p (width_p) + ,.num_in_p (num_in_p) + ,.remote_credits_p (remote_credits_p) + ,.lg_credit_decimation_p(lg_credit_decimation_p) + ) bcto + (.clk_i + ,.reset_i + + ,.data_i + ,.v_i + ,.yumi_o + + ,.data_o (multi_data_o ) + ,.v_o(multi_v_o) + ,.yumi_i (multi_yumi_i ) + + ,.credit_local_return_data_i (credit_local_return_data_oi ) + ,.credit_local_return_v_i (credit_local_return_v_oi ) + ,.credit_remote_return_data_i(credit_remote_return_data_oi) + ,.credit_remote_return_yumi_o(credit_remote_return_yumi_io) + ); + + bsg_channel_tunnel_in #(.width_p (width_p ) + ,.num_in_p (num_in_p ) + ,.remote_credits_p (remote_credits_p) + ,.use_pseudo_large_fifo_p(use_pseudo_large_fifo_p) + ,.harden_small_fifo_p (harden_small_fifo_p) + ,.lg_credit_decimation_p(lg_credit_decimation_p) + ) bcti + (.clk_i + ,.reset_i + + ,.data_i (multi_data_i ) + ,.v_i (multi_v_i) + ,.yumi_o (multi_yumi_o ) + + ,.data_o + ,.v_o + ,.yumi_i + + ,.credit_local_return_data_o (credit_local_return_data_oi ) + ,.credit_local_return_v_o (credit_local_return_v_oi ) + ,.credit_remote_return_data_o(credit_remote_return_data_oi) + ,.credit_remote_return_yumi_i(credit_remote_return_yumi_io) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_channel_tunnel) + + diff --git a/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel_in.sv b/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel_in.sv new file mode 100644 index 0000000..1f743d9 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel_in.sv @@ -0,0 +1,107 @@ + +// MBT 7-2-2016 +// +// takes N channels and tunnels them, with credit flow control. +// will work even if you have only a single channel. +// +// SV_gripe "output parameters" would make this implementation nicer +// vector parameters would be very useful as well + +`include "bsg_defines.sv" + +module bsg_channel_tunnel_in #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(num_in_p) + , parameter `BSG_INV_PARAM(remote_credits_p) + , use_pseudo_large_fifo_p = 0 + , harden_small_fifo_p = 0 + + // determines when we send out credits remotely + // and consequently how much bandwidth is used on credits + , lg_credit_decimation_p = 4 + + , tag_width_lp = $clog2(num_in_p+1) + , tagged_width_lp = tag_width_lp+width_p + , lg_remote_credits_lp = $clog2(remote_credits_p+1) + ) + (input clk_i + , input reset_i + + // to downstream + , input [tagged_width_lp-1:0] data_i + , input v_i + , output yumi_o + + // to outgoing channels (v/r) + , output [num_in_p-1:0][width_p-1:0] data_o + , output [num_in_p-1:0] v_o + , input [num_in_p-1:0] yumi_i + + // to bsg_channel_tunnel_out; returning credits to them; they always accept + , output [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_o + , output credit_local_return_v_o + + // to bsg_channel_tunnel_out; return credits to remote side + // always v + + , output [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_o + + // bsg_channel_tunnel sent all of the pending credits out + , input credit_remote_return_yumi_i + ); + + // always ready to deque credit_ready + logic credit_v_lo; + logic [width_p-1:0] credit_data_lo; + + // demultiplex the packets. + bsg_1_to_n_tagged_fifo #(.width_p (width_p) + ,.num_out_p (num_in_p+1 ) + ,.els_p (remote_credits_p) + // credit fifo is unbuffered + ,.unbuffered_mask_p (1 << num_in_p ) + ,.use_pseudo_large_fifo_p(use_pseudo_large_fifo_p) + ,.harden_small_fifo_p(harden_small_fifo_p) + ) + b1_ntf + (.clk_i + ,.reset_i + + ,.v_i (v_i) + ,.tag_i (data_i[width_p+:tag_width_lp]) + ,.data_i(data_i[0+:width_p]) + ,.yumi_o + + // v / ready + ,.v_o ( {credit_v_lo, v_o} ) + ,.data_o ( {credit_data_lo , data_o } ) + + // credit fifo is unbuffered, so no yumi signal + ,.yumi_i ( { 1'b0, yumi_i } ) + ); + + // route local credit return to bsg_channel_tunnel_out module + assign credit_local_return_data_o = credit_data_lo[0+:num_in_p*lg_remote_credits_lp]; + assign credit_local_return_v_o = credit_v_lo; + + // compute remote credit arithmetic + wire [num_in_p-1:0] sent = v_o & yumi_i; + + genvar i; + + // keep track of how many credits need to be send back + for (i = 0; i < num_in_p; i=i+1) + begin: rof + bsg_counter_clear_up #(.max_val_p (remote_credits_p) + ,.init_val_p(0) + ) ctr + (.clk_i + ,.reset_i + ,.clear_i (credit_remote_return_yumi_i ) + ,.up_i (sent[i] ) + ,.count_o (credit_remote_return_data_o[i]) + ); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_channel_tunnel_in) diff --git a/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel_out.sv b/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel_out.sv new file mode 100644 index 0000000..2d77dda --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_channel_tunnel_out.sv @@ -0,0 +1,124 @@ + +// MBT 7-2-2016 +// +// takes N channels and tunnels them, with credit flow control. +// +// SV "output parameters" would make this implementation nicer +// +// + +`include "bsg_defines.sv" + +module bsg_channel_tunnel_out #( + parameter `BSG_INV_PARAM(width_p) + ,parameter `BSG_INV_PARAM(num_in_p) + ,parameter `BSG_INV_PARAM(remote_credits_p) + + // determines when we send out credits remotely + , lg_credit_decimation_p = 4 + + , tag_width_lp = $clog2(num_in_p+1) + , tagged_width_lp = tag_width_lp+width_p + , lg_remote_credits_lp = $clog2(remote_credits_p+1) + ) + (input clk_i + , input reset_i + + // to fifos + , input [num_in_p-1:0][width_p-1:0] data_i + , input [num_in_p-1:0] v_i + , output [num_in_p-1:0] yumi_o + + // to downstream + , output [tagged_width_lp-1:0] data_o + , output v_o + , input yumi_i + + // from bsg_channel_tunnel_in; returning credits to us; we always accept + , input [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_i + , input credit_local_return_v_i + + // from bsg_channel_tunnel_in; return credits to remote side + // always v + + , input [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_i + + // yep, we sent all of the credits out + , output credit_remote_return_yumi_o + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + begin + assert(remote_credits_p >= (1 << lg_credit_decimation_p)) + else $error("%m remote_credits_p is smaller than credit decimation factor!"); + end +`endif + + genvar i; + + logic [num_in_p-1:0][lg_remote_credits_lp-1:0] local_credits; + logic [num_in_p-1:0] local_credits_avail, remote_credits_avail; + + // the most scalable way to deal with the below issue is to add more "credit channels" + // that transmit sections of the remote credits + // but we'll wait until we run into that problem before we build it out + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + assert (width_p >= num_in_p*lg_remote_credits_lp) + else $error("%m not enough room in packet to transmit all credit counters"); +`endif + + for (i = 0; i < num_in_p; i=i+1) + begin: rof + bsg_counter_up_down_variable #(.max_val_p (remote_credits_p) + ,.init_val_p(remote_credits_p) + ,.max_step_p(remote_credits_p) + ) bcudv + (.clk_i + ,.reset_i + + // credit return + ,.up_i ( credit_local_return_v_i + ? credit_local_return_data_i[i] + : (lg_remote_credits_lp ' (0)) + ) + + // sending + ,.down_i ( lg_remote_credits_lp ' (yumi_o [i]) ) + ,.count_o (local_credits [i]) + ); + + assign local_credits_avail [i] = |(local_credits[i]); + assign remote_credits_avail[i] + = | (credit_remote_return_data_i[i][lg_remote_credits_lp-1:lg_credit_decimation_p]); + end + + wire credit_v_li = | remote_credits_avail; + + // we are going to round-robin choose between incoming channels, + // adding a tag to the hi bits + + bsg_round_robin_n_to_1 #(.width_p (width_p ) + ,.num_in_p(num_in_p+1) + ,.strict_p(0) + ) + rr + (.clk_i + ,.reset_i + ,.data_i ({ width_p ' (credit_remote_return_data_i), data_i }) + + // we present as v only if there are credits available to send + ,.v_i ({ credit_v_li, v_i & local_credits_avail }) + ,.yumi_o ({ credit_remote_return_yumi_o, yumi_o }) + + ,.data_o (data_o[0+:width_p] ) + ,.tag_o (data_o[width_p+:tag_width_lp]) + ,.v_o (v_o) + ,.yumi_i (yumi_i ) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_channel_tunnel_out) diff --git a/designs/black-parrot/src/basejump_stl/bsg_circular_ptr.sv b/designs/black-parrot/src/basejump_stl/bsg_circular_ptr.sv new file mode 100644 index 0000000..0d73779 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_circular_ptr.sv @@ -0,0 +1,90 @@ +`include "bsg_defines.sv" +// MBT +// +// 10/27/14 +// +// implements a circular pointer that +// can be incremented by at most max_add_p +// and points to slots_p slots. +// + +module bsg_circular_ptr #(parameter `BSG_INV_PARAM(slots_p) + , parameter `BSG_INV_PARAM(max_add_p) + // whether there is a constant increment (e.g. 1 or 4, 5) + , parameter const_incr_p = 1'b0 + // local param + , parameter ptr_width_lp = `BSG_SAFE_CLOG2(slots_p) + ) + (input clk + , input reset_i + , input [$clog2(max_add_p+1)-1:0] add_i + , output [ptr_width_lp-1:0] o + , output [ptr_width_lp-1:0] n_o + ); + + logic [ptr_width_lp-1:0] ptr_r, ptr_n, ptr_nowrap; + logic [ptr_width_lp:0] ptr_wrap; + + assign o = ptr_r; + assign n_o = ptr_n; + + initial + begin + // Check that max_add_p fits in ptr_width_lp bits + assert (max_add_p < (1 << ptr_width_lp)) + else $error("%m: max_add_p parameter too large"); + end + + // increment round robin pointers + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk) + if (reset_i) ptr_r <= '0; + else ptr_r <= ptr_n; + + if (slots_p == 1) + begin + assign ptr_n = 1'b0; + wire ignore = |add_i; + end + else + + // fixme performance optimization: + // we should handle add-by-1 and non-power-of-two + // in the same way as power-of-two and add-by-1 + // with a compare of ptr_r to slots_p-1 to check for + // zeroing the ptr_r_p1 value. + + if (`BSG_IS_POW2(slots_p)) + begin + // reduce critical path on add_i signal + if ((max_add_p == 1) || const_incr_p) + begin + wire [ptr_width_lp-1:0] ptr_r_p1 = ptr_r + max_add_p[ptr_width_lp-1:0]; + assign ptr_n = add_i ? ptr_r_p1 : ptr_r; + end + else + assign ptr_n = ptr_width_lp ' (ptr_r + add_i); + end + else + begin: notpow2 + // compute wrapped and non-wrap cases + // in parallel + assign ptr_wrap = (ptr_width_lp+1)'({ 1'b0, ptr_r } - slots_p + add_i); + assign ptr_nowrap = ptr_r + add_i; + + // if (ptr_r + add_i - slots_p >= 0) + // then we have wrapped around + assign ptr_n = ~ptr_wrap[ptr_width_lp] ? ptr_wrap[0+:ptr_width_lp] : ptr_nowrap; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_comb + begin + assert final( (ptr_n < slots_p) || (|ptr_n === 'X) || reset_i || (add_i > slots_p)) + else $error("bsg_circular_ptr counter overflow (ptr_r=%b/add_i=%b/ptr_wrap=%b/ptr_n=%b)",ptr_r,add_i,ptr_wrap,ptr_n, slots_p); + end +`endif +end +endmodule // bsg_circular_ptr + +`BSG_ABSTRACT_MODULE(bsg_circular_ptr) diff --git a/designs/black-parrot/src/basejump_stl/bsg_concentrate_static.sv b/designs/black-parrot/src/basejump_stl/bsg_concentrate_static.sv new file mode 100644 index 0000000..c9002ef --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_concentrate_static.sv @@ -0,0 +1,27 @@ +`include "bsg_defines.sv" + +// given a bunch of signals, and a bitvector parameter, gather/concentrate +// those bits together into a more condensed vector +// +// example: pattern_els_p = 5'b11101 +// + +module bsg_concentrate_static #(parameter `BSG_INV_PARAM(pattern_els_p), width_lp=$bits(pattern_els_p), set_els_lp=`BSG_COUNTONES_SYNTH(pattern_els_p)) +(input [width_lp-1:0] i + ,output [set_els_lp-1:0] o +); + genvar j; + + if (pattern_els_p[0]) + assign o[0]=i[0]; + + for (j = 1; j < width_lp; j=j+1) + begin : rof + if (pattern_els_p[j]) + assign o[`BSG_COUNTONES_SYNTH(pattern_els_p[j-1:0])] = i[j]; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_concentrate_static) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_counter_clear_up.sv b/designs/black-parrot/src/basejump_stl/bsg_counter_clear_up.sv new file mode 100644 index 0000000..d98e235 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_counter_clear_up.sv @@ -0,0 +1,57 @@ +// This counter counts up and is occasionally cleared. +// If up and clear are applied on the same cycle, the +// clear occurs first, and then the up. +// + +`include "bsg_defines.sv" + +module bsg_counter_clear_up #(parameter `BSG_INV_PARAM(max_val_p) + // this originally had an "invalid" default value of -1 + // which is a bad choice for a counter + ,parameter init_val_p = `BSG_UNDEFINED_IN_SIM('0) + ,parameter ptr_width_lp = + `BSG_SAFE_CLOG2(max_val_p+1) + ,parameter disable_overflow_warning_p = 0 + ) + (input clk_i + , input reset_i + + , input clear_i + , input up_i + // fixme: count_o should be renamed to count_r_o since some modules + // depend on this being a register and we want to indicate this at the interface level + , output logic [ptr_width_lp-1:0] count_o + ); + + // keeping track of number of entries and updating read and + // write pointers, and displaying errors in case of overflow + // or underflow + + always_ff @(posedge clk_i) + begin + if (reset_i) begin + count_o <= init_val_p; + end + else begin + if (clear_i) begin + count_o <= ptr_width_lp'(up_i); + end + else if (up_i) begin + count_o <= count_o + 1'b1; + end + end + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + always_ff @ (negedge clk_i) + begin + if ((count_o==ptr_width_lp '(max_val_p)) && up_i && (reset_i===0) && !disable_overflow_warning_p) + $display("%m error: counter overflow at time %t", $time); + end + +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_counter_clear_up) diff --git a/designs/black-parrot/src/basejump_stl/bsg_counter_clear_up_one_hot.sv b/designs/black-parrot/src/basejump_stl/bsg_counter_clear_up_one_hot.sv new file mode 100644 index 0000000..1af67ab --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_counter_clear_up_one_hot.sv @@ -0,0 +1,51 @@ +// This counter is a one hot counter; so exactly one output bit is set at all times. +// For example if the value of the counter is zero, then bit 0 will be set. +// This counter makes it extremely fast to detect whether the counter is a particular value. +// The logic is relatively expensive, since it scales with the number of values the counter can take on. +// It is most sensible when you need a decoder to select items in an array, and your access pattern through +// that array is sequential. It will minimize critical paths, and the cost is amortized because the +// alternative is a binary counter and a decoder. +// +// The interface of this counter is analogous to bsg_counter_clear_up: +// +// - the reset_i signal ensures that output to init_val_p; default is 2's complement 0 regardless of up_i or clear_i +// - the clear_i signal sets the 2's complement value to 0 (i.e. all bits except low bit are 0; low bit is 1) +// - the up_i signal increments the counter (corresponds to left rotate). it stacks on top of the clear_i +// so it is legal for the user to assert both clear_i and up_i simultaneous and the effects of both to be reflected. +// + +`include "bsg_defines.sv" + +module bsg_counter_clear_up_one_hot + #(parameter `BSG_INV_PARAM(max_val_p), width_lp=max_val_p+1, init_val_p=(width_lp) ' (1)) + (input clk_i + ,input reset_i + ,input clear_i + ,input up_i + ,output [width_lp-1:0] count_r_o + ); + + logic [width_lp-1:0] bits_r, bits_n; + + always_comb + begin + bits_n = bits_r; + if (clear_i) + bits_n = (width_lp) ' (1); + // increment is a rotate operator + if (up_i) + bits_n = { bits_n[width_lp-2:0], bits_n[width_lp-1] }; + if (reset_i) + bits_n = (width_lp) ' (init_val_p); + end + + // clock gate, hopefully + always_ff @(posedge clk_i) + if (reset_i | up_i | clear_i) + bits_r <= bits_n; + + assign count_r_o = bits_r; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_counter_clear_up_one_hot) diff --git a/designs/black-parrot/src/basejump_stl/bsg_counter_clock_downsample.sv b/designs/black-parrot/src/basejump_stl/bsg_counter_clock_downsample.sv new file mode 100644 index 0000000..3ba7d8b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_counter_clock_downsample.sv @@ -0,0 +1,39 @@ +// This counter will counter down from val_i to 0. When the counter +// hits 0, the output clk_r_o will invert. The number of bits wide +// the counter is can be set with the width_p parameter. +// +// Random ideas: could have a variant of this that takes two inputs +// one for the high duty cycle and one for the low duty cycle. +// + +`include "bsg_defines.sv" + +module bsg_counter_clock_downsample #(parameter `BSG_INV_PARAM(width_p ), harden_p=0) + (input clk_i + ,input reset_i + ,input [width_p-1:0] val_i + ,output logic clk_r_o + ); + + wire strobe_r; + + // asserts a "1" every val_i cycles + bsg_strobe #(.width_p(width_p), .harden_p(harden_p)) strobe + (.clk_i + ,.reset_r_i(reset_i) + ,.init_val_r_i(val_i) + ,.strobe_r_o(strobe_r) + ); + + // Clock output register + always_ff @(posedge clk_i) + begin + if (reset_i) + clk_r_o <= 1'b0; + else if (strobe_r) + clk_r_o <= ~clk_r_o; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_counter_clock_downsample) diff --git a/designs/black-parrot/src/basejump_stl/bsg_counter_set_down.sv b/designs/black-parrot/src/basejump_stl/bsg_counter_set_down.sv new file mode 100644 index 0000000..1adb9a2 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_counter_set_down.sv @@ -0,0 +1,67 @@ +// parallel to bsg_counter_clear_up +// set occurs before down, and both events can take place in the same cycle. +// we do not output an overflow flag because there is no == that we would +// want to amortize the cost of + +`include "bsg_defines.sv" + +module bsg_counter_set_down #(parameter `BSG_INV_PARAM(width_p), parameter init_val_p='0, parameter set_and_down_exclusive_p=0) + (input clk_i + , input reset_i + , input set_i + , input [width_p-1:0] val_i + , input down_i + , output [width_p-1:0] count_r_o + ); + + logic [width_p-1:0] ctr_r, ctr_n; + + always_ff @(posedge clk_i) + if (reset_i) + ctr_r <= width_p ' (init_val_p); + else + ctr_r <= ctr_n; + + if (set_and_down_exclusive_p) + begin: excl + always_comb + begin + ctr_n = ctr_r; + + if (set_i) + ctr_n = val_i; + else + if (down_i) + ctr_n = ctr_n - 1; + end + end + else + begin : non_excl + always_comb + begin + ctr_n = ctr_r; + + if (set_i) + ctr_n = val_i; + + if (down_i) + ctr_n = ctr_n - 1; + end + end + + assign count_r_o = ctr_r; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @(negedge clk_i) + begin + if (!reset_i && down_i && (ctr_n == '1)) + $display("%m error: counter underflow at time %t", $time); + + if (~reset_i & set_and_down_exclusive_p & set_i & down_i) + $display("%m error: set and down non-exclusive at time %t", $time); + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_counter_set_down) diff --git a/designs/black-parrot/src/basejump_stl/bsg_counter_set_en.sv b/designs/black-parrot/src/basejump_stl/bsg_counter_set_en.sv new file mode 100644 index 0000000..318f57c --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_counter_set_en.sv @@ -0,0 +1,38 @@ +/** + * bsg_counter_set_en.sv + */ + +`include "bsg_defines.sv" + +module bsg_counter_set_en + #(parameter `BSG_INV_PARAM(max_val_p) + , parameter lg_max_val_lp=`BSG_WIDTH(max_val_p) + , parameter reset_val_p=0 + ) + ( + input clk_i + , input reset_i + + , input set_i + , input en_i + , input [lg_max_val_lp-1:0] val_i + , output logic [lg_max_val_lp-1:0] count_o + ); + + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + count_o <= (lg_max_val_lp)'(reset_val_p); + end + else if (set_i) begin + count_o <= val_i; + end + else if (en_i) begin + count_o <= count_o + 1'b1; + end + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_counter_set_en) diff --git a/designs/black-parrot/src/basejump_stl/bsg_counter_up_down.sv b/designs/black-parrot/src/basejump_stl/bsg_counter_up_down.sv new file mode 100644 index 0000000..a684622 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_counter_up_down.sv @@ -0,0 +1,71 @@ +// +// This is an up-down counter with initial and max values. +// Even for counters that start at max value, it can be useful +// to specify an even greater max. This is useful in case where you want to +// be able to change the max value after hardware design time, +// for example for credit counters between chips. The +// hardware can return the extra credits right after reset. +// +// PO: a bsg_counter_up_down_blind only says whether the count is +// zero, and does not show the actual value. the blind version +// can latch the up_i and down_i signals, for zero input latency. +// It can also precompute whether the high bits are all 0. +// then it can use two simple expressions, +// wire [1:0] same_dec = { up_r ^ down_r, down_r & ~up_r }; +// wire [1:0] one_zero = { ctr[0] & high_bits_zero_r, ~ctr[0] & high_bits_zero_r }; +// +// wire zero_o = (one_zero[0] & same_dec[1]) | (one_zero[1] & same_dec[0]); +// +// alternatively, using four bits, we could output a 2-in, 1-out truth table that +// is indexed by up_r and down_r. +// +// merged bsg_counter_up_down_variable into this module june 2018 + +`include "bsg_defines.sv" + +module bsg_counter_up_down #( parameter `BSG_INV_PARAM(max_val_p ) + , parameter `BSG_INV_PARAM(init_val_p ) + , parameter `BSG_INV_PARAM(max_step_p ) + + //localpara + , parameter step_width_lp = + `BSG_WIDTH(max_step_p) + , parameter ptr_width_lp = + `BSG_WIDTH(max_val_p)) + ( input clk_i + , input reset_i + + , input [step_width_lp-1:0] up_i + , input [step_width_lp-1:0] down_i + + , output logic [ptr_width_lp-1:0] count_o + ); + +// keeping track of number of entries and updating read and +// write pointers, and displaying errors in case of overflow +// or underflow + +always_ff @(posedge clk_i) + begin + if (reset_i) + count_o <= init_val_p; + else + // It was tested on Design Compiler that using a + // simple minus and plus operation results in smaller + // design, rather than using xor or other ideas + // between down_i and up_i + count_o <= count_o - down_i + up_i; + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @ (negedge clk_i) begin + if ((count_o==max_val_p) & up_i & ~down_i & (reset_i === 1'b0)) + $display("%m error: counter overflow at time %t", $time); + if ((count_o==0) & down_i & ~up_i & (reset_i === 1'b0)) + $display("%m error: counter underflow at time %t", $time); + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_counter_up_down) diff --git a/designs/black-parrot/src/basejump_stl/bsg_counter_up_down_variable.sv b/designs/black-parrot/src/basejump_stl/bsg_counter_up_down_variable.sv new file mode 100644 index 0000000..9fbba6a --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_counter_up_down_variable.sv @@ -0,0 +1,53 @@ +// This is an up-down counter with initial and max values. +// Moreover, it has an parameter for extra bits to be used +// for counter, in case of using for credit counters. Also +// up and down values could be variable, having max threshold +// of max_step_p. +`include "bsg_defines.sv" + +module bsg_counter_up_down_variable #( parameter `BSG_INV_PARAM(max_val_p ) + , parameter `BSG_INV_PARAM(init_val_p ) + , parameter `BSG_INV_PARAM(max_step_p ) + + //localpara + , parameter step_width_lp = + `BSG_WIDTH(max_step_p) + , parameter ptr_width_lp = + `BSG_WIDTH(max_val_p) + ) + ( input clk_i + , input reset_i + + , input [step_width_lp-1:0] up_i + , input [step_width_lp-1:0] down_i + + , output logic [ptr_width_lp-1:0] count_o + ); + +// keeping track of number of entries and updating read and +// write poniteres, and displaying errors in case of overflow +// or underflow +always_ff @(posedge clk_i) + begin + if (reset_i) + count_o <= init_val_p; + else + // It was tested on Design Compiler that using a + // simple minus and plus operation results in smaller + // design, rather than using xor or other ideas + // between down_i and up_i + count_o <= count_o - down_i + up_i; + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @ (posedge clk_i) begin + if ((count_o==max_val_p) & up_i & (reset_i===0)) + $display("%m error: counter overflow at time %t", $time); + if ((count_o==0) & down_i & (reset_i===0)) + $display("%m error: counter underflow at time %t", $time); + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_counter_up_down_variable) diff --git a/designs/black-parrot/src/basejump_stl/bsg_counting_leading_zeros.sv b/designs/black-parrot/src/basejump_stl/bsg_counting_leading_zeros.sv new file mode 100644 index 0000000..f12dcc8 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_counting_leading_zeros.sv @@ -0,0 +1,37 @@ +/** + * bsg_counting_leading_zeros.sv + * + * @author Tommy Jung + */ + +`include "bsg_defines.sv" + +module bsg_counting_leading_zeros #( + parameter `BSG_INV_PARAM(width_p) + , parameter num_zero_width_lp=`BSG_WIDTH(width_p) +) +( + input [width_p-1:0] a_i + ,output logic [num_zero_width_lp-1:0] num_zero_o +); + + + logic [width_p:0] reversed; + genvar i; + for (i = 0; i < width_p; i++) begin + assign reversed[i] = a_i[width_p-1-i]; + end + assign reversed[width_p] = 1'b1; + + bsg_priority_encode #( + .width_p(width_p+1) + ,.lo_to_hi_p(1) + ) pe0 ( + .i(reversed) + ,.addr_o(num_zero_o) + ,.v_o() + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_counting_leading_zeros) diff --git a/designs/black-parrot/src/basejump_stl/bsg_crossbar_control_locking_o_by_i.sv b/designs/black-parrot/src/basejump_stl/bsg_crossbar_control_locking_o_by_i.sv new file mode 100644 index 0000000..91d03c6 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_crossbar_control_locking_o_by_i.sv @@ -0,0 +1,120 @@ +/** + * bsg_crossbar_control_locking_o_by_i.sv + * + * This module generates the control signals for bsg_router_crossbar_o_by_i. + * In addition to bsg_crossbar_control_basic_o_by_i.sv, it also "locks" the + * outputs so that streams of data will not be interleaved if multiple + * sources attempt to send to the same sink. + */ + + +`include "bsg_defines.sv" + +module bsg_crossbar_control_locking_o_by_i + #(parameter `BSG_INV_PARAM(i_els_p) + , parameter `BSG_INV_PARAM(o_els_p) + , parameter lg_o_els_lp=`BSG_SAFE_CLOG2(o_els_p) + ) + ( + input clk_i + , input reset_i + + , input [i_els_p-1:0] valid_i + , input [i_els_p-1:0][lg_o_els_lp-1:0] sel_io_i + , output [i_els_p-1:0] yumi_o + + // crossbar outputs (ready & valid interface) + // unlock is expected 1 cycle before the next head flit + // (or equivalently with the tail of a previous message) + // The crossbar will stay locked until unlocked ("hold-on-valid" mode) + // To unlock whenever there is an available slot, a user could set + // unlock_i = (valid & is_tail) | (valid & is_head & ~ready) + , input [o_els_p-1:0] unlock_i + , input [o_els_p-1:0] ready_and_i + , output [o_els_p-1:0] valid_o + , output [o_els_p-1:0][i_els_p-1:0] grants_oi_one_hot_o + ); + + + // select logic + logic [i_els_p-1:0][o_els_p-1:0] o_select; + logic [o_els_p-1:0][i_els_p-1:0] o_select_t; + + for (genvar i = 0; i < i_els_p; i++) begin: dv + bsg_decode_with_v #( + .num_out_p(o_els_p) + ) dv0 ( + .i(sel_io_i[i]) + ,.v_i(valid_i[i]) + ,.o(o_select[i]) + ); + end + + bsg_transpose #( + .width_p(o_els_p) + ,.els_p(i_els_p) + ) trans0 ( + .i(o_select) + ,.o(o_select_t) + ); + + + // round robin + logic [o_els_p-1:0] rr_yumi_li; + logic [o_els_p-1:0][i_els_p-1:0] rr_yumi_lo; + logic [i_els_p-1:0][o_els_p-1:0] rr_yumi_lo_t; + + for (genvar i = 0 ; i < o_els_p; i++) begin: rr + + logic [i_els_p-1:0] not_req_mask_r, req_mask_r, reqs_li; + + bsg_dff_reset_en #( .width_p(i_els_p) ) + req_words_reg + ( .clk_i ( clk_i ) + , .reset_i( reset_i || unlock_i[i] ) + , .en_i ( (&req_mask_r) & (|grants_oi_one_hot_o[i]) ) + , .data_i ( ~grants_oi_one_hot_o[i] ) + , .data_o ( not_req_mask_r ) + ); + + assign req_mask_r = ~not_req_mask_r; + + assign reqs_li = o_select_t[i] & req_mask_r; + + assign valid_o[i] = |reqs_li; + assign rr_yumi_li[i] = valid_o[i] & ready_and_i[i]; + + bsg_arb_round_robin #( + .width_p(i_els_p) + ) rr0 ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.reqs_i(reqs_li) + ,.grants_o(grants_oi_one_hot_o[i]) + ,.yumi_i(rr_yumi_li[i]) + ); + + assign rr_yumi_lo[i] = grants_oi_one_hot_o[i] & {i_els_p{rr_yumi_li[i]}}; + + end + + + bsg_transpose #( + .width_p(i_els_p) + ,.els_p(o_els_p) + ) trans1 ( + .i(rr_yumi_lo) + ,.o(rr_yumi_lo_t) + ); + + + for (genvar i = 0; i < i_els_p; i++) begin + assign yumi_o[i] = |rr_yumi_lo_t[i]; + end + + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_crossbar_control_locking_o_by_i) diff --git a/designs/black-parrot/src/basejump_stl/bsg_crossbar_o_by_i.sv b/designs/black-parrot/src/basejump_stl/bsg_crossbar_o_by_i.sv new file mode 100644 index 0000000..7b71ada --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_crossbar_o_by_i.sv @@ -0,0 +1,29 @@ +// NB: for larger sizes, may make sense to have a benes network implementation option +// since it is assymptotically better than a full crossbar for datapath. + +`include "bsg_defines.sv" + +module bsg_crossbar_o_by_i #( parameter `BSG_INV_PARAM(i_els_p) + ,parameter `BSG_INV_PARAM(o_els_p) + ,parameter `BSG_INV_PARAM(width_p) + ) + ( input [i_els_p-1:0][width_p-1:0] i + ,input [o_els_p-1:0][i_els_p-1:0] sel_oi_one_hot_i + ,output [o_els_p-1:0][width_p-1:0] o + ); + + genvar lineout; + + for(lineout=0; lineout(y)) ? (x) : (y)) +`define BSG_MIN(x,y) (((x)<(y)) ? (x) : (y)) + +`define BSG_SIGN_EXTEND(sig, width) \ + ({{`BSG_MAX(width-$bits(sig),0){sig[$bits(sig)-1]}}, sig[0+:`BSG_MIN(width, $bits(sig))]}) +`define BSG_ZERO_EXTEND(sig, width) \ + ({{`BSG_MAX(width-$bits(sig),0){1'b0}}, sig[0+:`BSG_MIN(width, $bits(sig))]}) + +// place this macro at the end of a verilog module file if that module has invalid parameters +// that must be specified by the user. this will prevent that module from becoming a top-level +// module per the discussion here: https://github.com/SymbiFlow/sv-tests/issues/1160 and the +// SystemVerilog Standard + +// "Top-level modules are modules that are included in the SystemVerilog +// source text, but do not appear in any module instantiation statement, as +// described in 23.3.2. This applies even if the module instantiation appears +// in a generate block that is not itself instantiated (see 27.3). A design +// shall contain at least one top-level module. A top-level module is +// implicitly instantiated once, and its instance name is the same as the +// module name. Such an instance is called a top-level instance." +// + +`define BSG_ABSTRACT_MODULE(fn) \ + /*verilator lint_off DECLFILENAME*/ \ + /*verilator lint_off PINMISSING*/ \ + module fn``__abstract(); if (0) begin : abstract fn not_used(); end endmodule \ + /*verilator lint_on PINMISSING*/ \ + /*verilator lint_on DECLFILENAME*/ + +// macro for defining invalid parameter; with the abstract module declaration +// it should be sufficient to omit the "inv" but we include this for tool portability +// if later we find that all tools are compatible, we can remove the use of this from BaseJump STL + +`ifdef XCELIUM // Bare default parameters are incompatible as of 20.09.012 + // = "inv" causes type inference mismatch as of 20.09.012 +`define BSG_INV_PARAM(param) param = -1 +`elsif YOSYS // Bare default parameters are incompatible as of 0.9 +`define BSG_INV_PARAM(param) param = "inv" +`else // VIVADO, DC, VERILATOR, GENUS, SURELOG +`define BSG_INV_PARAM(param) param +`endif + + +// maps 1 --> 1 instead of to 0 +`define BSG_SAFE_CLOG2(x) ( (((x)==1) || ((x)==0))? 1 : $clog2((x))) +`define BSG_IS_POW2(x) ( (1 << $clog2(x)) == (x)) +`define BSG_WIDTH(x) ($clog2(x+1)) +`define BSG_SAFE_MINUS(x, y) (((x)<(y))) ? 0 : ((x)-(y)) + +// these "SAFE" shift functions handle a common problem that shifts default to 32 bits wide even +// though the result may be more bits than that. + +// these macros ensure that a left shift is done with sufficient bits of precision not to lose data +// extra is used if you want some extra bits of margin +`define BSG_SAFE_SHIFT_LEFT_BY_CONST(a,b_const,extra) (( ($bits(a) + (b_const) + extra )'(a)) << (b_const)) + +// b_max is the maximum value that b_variable can take on +`define BSG_SAFE_SHIFT_LEFT_CONST_BY_VARIABLE(a_const,b_variable,b_max,extra) (( ($clog2( (a_const)+1)+(b_max)+(extra)) ' (a_const)) << (b_variable) ) + + +// calculate ceil(x/y) +`define BSG_CDIV(x,y) (((x)+(y)-1)/(y)) + +`ifdef SYNTHESIS +`define BSG_UNDEFINED_IN_SIM(val) (val) +`else +`define BSG_UNDEFINED_IN_SIM(val) ('X) +`endif + +`ifdef VERILATOR +`define BSG_HIDE_FROM_VERILATOR(val) +`else +`define BSG_HIDE_FROM_VERILATOR(val) val +`endif + +`ifdef SYNTHESIS +`define BSG_DISCONNECTED_IN_SIM(val) (val) +`elsif VERILATOR +`define BSG_DISCONNECTED_IN_SIM(val) (val) +`else +`define BSG_DISCONNECTED_IN_SIM(val) ('z) +`endif + +// Ufortunately per the Xilinx forums, Xilinx does not define +// any variable that indicates that Vivado Synthesis is running +// so as a result we identify Vivado merely as the exclusion of +// Synopsys Design Compiler (DC). Support beyond DC and Vivado +// will require modification of this macro. + +`ifdef SYNTHESIS + `ifdef DC + `define BSG_VIVADO_SYNTH_FAILS + `elsif CDS_TOOL_DEFINE + `define BSG_VIVADO_SYNTH_FAILS + `elsif SURELOG + `define BSG_VIVADO_SYNTH_FAILS + `elsif YOSYS + `define BSG_VIVADO_SYNTH_FAILS + `else + `define BSG_VIVADO_SYNTH_FAILS this_module_is_not_synthesizeable_in_vivado + `endif +`else +`define BSG_VIVADO_SYNTH_FAILS +`endif + +// macro for denoting that a code snippet is unsynthesiable + +`ifdef SYNTHESIS + `define BSG_HIDE_FROM_SYNTHESIS +`endif + +`define BSG_STRINGIFY(x) `"x`" + + +// For the modules that must be hardened, add this macro at the top. +`ifdef SYNTHESIS +`define BSG_SYNTH_MUST_HARDEN this_module_must_be_hardened +`else +`define BSG_SYNTH_MUST_HARDEN +`endif + + +// using C-style shifts instead of a[i] allows the parameter of BSG_GET_BIT to be a parameter subrange +// e.g., parameter[4:1][1], which DC 2016.12 does not allow + +`define BSG_GET_BIT(X,NUM) (((X)>>(NUM))&1'b1) + +// This version of countones works in synthesis, but only up to 64 bits +// we do a funny thing where we propagate X's in simulation if it is more than 64 bits +// and in synthesis, go ahead and ignore the high bits + +`define BSG_COUNTONES_SYNTH(y) (($bits(y) < 65) ? 1'b0 : `BSG_UNDEFINED_IN_SIM(1'b0)) + (`BSG_GET_BIT(y,0) +`BSG_GET_BIT(y,1) +`BSG_GET_BIT(y,2) +`BSG_GET_BIT(y,3) +`BSG_GET_BIT(y,4) +`BSG_GET_BIT(y,5) +`BSG_GET_BIT(y,6)+`BSG_GET_BIT(y,7) +`BSG_GET_BIT(y,8)+`BSG_GET_BIT(y,9) \ + +`BSG_GET_BIT(y,10)+`BSG_GET_BIT(y,11)+`BSG_GET_BIT(y,12)+`BSG_GET_BIT(y,13)+`BSG_GET_BIT(y,14)+`BSG_GET_BIT(y,15)+`BSG_GET_BIT(y,16)+`BSG_GET_BIT(y,17)+`BSG_GET_BIT(y,18)+`BSG_GET_BIT(y,19) \ + +`BSG_GET_BIT(y,20)+`BSG_GET_BIT(y,21)+`BSG_GET_BIT(y,22)+`BSG_GET_BIT(y,23)+`BSG_GET_BIT(y,24)+`BSG_GET_BIT(y,25)+`BSG_GET_BIT(y,26)+`BSG_GET_BIT(y,27)+`BSG_GET_BIT(y,28)+`BSG_GET_BIT(y,29) \ + +`BSG_GET_BIT(y,30)+`BSG_GET_BIT(y,31)+`BSG_GET_BIT(y,32)+`BSG_GET_BIT(y,33)+`BSG_GET_BIT(y,34)+`BSG_GET_BIT(y,35)+`BSG_GET_BIT(y,36)+`BSG_GET_BIT(y,37)+`BSG_GET_BIT(y,38)+`BSG_GET_BIT(y,39) \ + +`BSG_GET_BIT(y,40)+`BSG_GET_BIT(y,41)+`BSG_GET_BIT(y,42)+`BSG_GET_BIT(y,43)+`BSG_GET_BIT(y,44)+`BSG_GET_BIT(y,45)+`BSG_GET_BIT(y,46)+`BSG_GET_BIT(y,47)+`BSG_GET_BIT(y,48)+`BSG_GET_BIT(y,49) \ + +`BSG_GET_BIT(y,50)+`BSG_GET_BIT(y,51)+`BSG_GET_BIT(y,52)+`BSG_GET_BIT(y,53)+`BSG_GET_BIT(y,54)+`BSG_GET_BIT(y,55)+`BSG_GET_BIT(y,56)+`BSG_GET_BIT(y,57)+`BSG_GET_BIT(y,58)+`BSG_GET_BIT(y,59) \ + +`BSG_GET_BIT(y,60)+`BSG_GET_BIT(y,61)+`BSG_GET_BIT(y,62)+`BSG_GET_BIT(y,63)) + +// nullify rpgroups +`ifndef rpgroup +`define rpgroup(x) +`endif + +// verilog preprocessing -> if defined(A) && defined(B) then define C +`define BSG_DEFIF_A_AND_B(A,B,C) \ + `undef C \ + `ifdef A \ + `ifdef B \ + `define C \ + `endif \ + `endif + +// verilog preprocessing -> if defined(A) && !defined(B) then define C +`define BSG_DEFIF_A_AND_NOT_B(A,B,C) \ + `undef C \ + `ifdef A \ + `ifndef B \ + `define C \ + `endif \ + `endif + +// verilog preprocessing -> if !defined(A) && defined(B) then define C +`define BSG_DEFIF_NOT_A_AND_B(A,B,C) `BSG_DEFIF_A_AND_NOT_B(B,A,C) + +// verilog preprocessing -> if !defined(A) && !defined(B) then define C +`define BSG_DEFIF_NOT_A_AND_NOT_B(A,B,C) \ + `undef C \ + `ifndef A \ + `ifndef B \ + `define C \ + `endif \ + `endif + +// verilog preprocessing -> if defined(A) || defined(B) then define C +`define BSG_DEFIF_A_OR_B(A,B,C) \ + `undef C \ + `ifdef A \ + `define C \ + `endif \ + `ifdef B \ + `define C \ + `endif + +// verilog preprocessing -> if defined(A) || !defined(B) then define C +`define BSG_DEFIF_A_OR_NOT_B(A,B,C) \ + `undef C \ + `ifdef A \ + `define C \ + `endif \ + `ifndef B \ + `define C \ + `endif + +// verilog preprocessing -> if !defined(A) || defined(B) then define C +`define BSG_DEFIF_NOT_A_OR_B(A,B,C) `BSG_DEFIF_A_OR_NOT_B(B,A,C) + +// verilog preprocessing -> if !defined(A) || !defined(B) then define C +`define BSG_DEFIF_NOT_A_OR_NOT_B(A,B,C) \ + `undef C \ + `ifndef A \ + `define C \ + `endif \ + `ifndef B \ + `define C \ + `endif + +`endif diff --git a/designs/black-parrot/src/basejump_stl/bsg_dff.sv b/designs/black-parrot/src/basejump_stl/bsg_dff.sv new file mode 100644 index 0000000..e43b2d4 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dff.sv @@ -0,0 +1,22 @@ + +`include "bsg_defines.sv" + +module bsg_dff #(parameter `BSG_INV_PARAM(width_p) + ,harden_p=0 + ,strength_p=1 // set drive strength + ) + (input clk_i + ,input [width_p-1:0] data_i + ,output [width_p-1:0] data_o + ); + + reg [width_p-1:0] data_r; + + assign data_o = data_r; + + always @(posedge clk_i) + data_r <= data_i; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff) diff --git a/designs/black-parrot/src/basejump_stl/bsg_dff_chain.sv b/designs/black-parrot/src/basejump_stl/bsg_dff_chain.sv new file mode 100644 index 0000000..dc93ca1 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dff_chain.sv @@ -0,0 +1,52 @@ +//==================================================================== +// bsg_dff_chain.sv +// 04/01/2018, shawnless.xie@gmail.com +//==================================================================== +// +// Pass the input singal to a chainded DFF registers + +`include "bsg_defines.sv" + +module bsg_dff_chain #( + //the width of the input signal + parameter `BSG_INV_PARAM( width_p ) + + //the stages of the chained DFF register + //can be 0 + ,parameter num_stages_p = 1 + ) + ( + input clk_i + ,input [width_p-1:0] data_i + ,output[width_p-1:0] data_o + ); + + if( num_stages_p == 0) begin:pass_through + wire unused = clk_i; + assign data_o = data_i; + end:pass_through + + else begin:chained + // data_i -- delayed[0] + // + // data_o -- delayed[num_stages_p] + logic [num_stages_p:0][width_p-1:0] data_delayed; + + assign data_delayed[0] = data_i ; + assign data_o = data_delayed[num_stages_p] ; + + genvar i; + for(i=1; i<= num_stages_p; i++) begin + bsg_dff #( .width_p ( width_p ) ) + ch_reg ( + .clk_i ( clk_i ) + ,.data_i ( data_delayed[ i-1 ] ) + ,.data_o ( data_delayed[ i ] ) + ); + end + + end:chained + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff_chain) diff --git a/designs/black-parrot/src/basejump_stl/bsg_dff_en.sv b/designs/black-parrot/src/basejump_stl/bsg_dff_en.sv new file mode 100644 index 0000000..d7bed75 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dff_en.sv @@ -0,0 +1,30 @@ +/** + * bsg_dff_en.sv + * @param width_p data width + */ + +`include "bsg_defines.sv" + +module bsg_dff_en #(parameter `BSG_INV_PARAM(width_p) + ,parameter harden_p=1 // mbt fixme: maybe this should not be a default + ,parameter strength_p=1) +( + input clk_i + ,input [width_p-1:0] data_i + ,input en_i + ,output logic [width_p-1:0] data_o +); + + logic [width_p-1:0] data_r; + + assign data_o = data_r; + + always_ff @ (posedge clk_i) begin + if (en_i) begin + data_r <= data_i; + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff_en) diff --git a/designs/black-parrot/src/basejump_stl/bsg_dff_en_bypass.sv b/designs/black-parrot/src/basejump_stl/bsg_dff_en_bypass.sv new file mode 100644 index 0000000..fcd50d5 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dff_en_bypass.sv @@ -0,0 +1,42 @@ +/** + * bsg_dff_en_bypass.sv + * + */ + + +`include "bsg_defines.sv" + +module bsg_dff_en_bypass + #(parameter `BSG_INV_PARAM(width_p) + , parameter harden_p=0 + , parameter strength_p=0 + ) + ( + input clk_i + , input en_i + , input [width_p-1:0] data_i + , output logic [width_p-1:0] data_o + ); + + logic [width_p-1:0] data_r; + + bsg_dff_en #( + .width_p(width_p) + ,.harden_p(harden_p) + ,.strength_p(strength_p) + ) dff ( + .clk_i(clk_i) + ,.en_i(en_i) + ,.data_i(data_i) + ,.data_o(data_r) + ); + + assign data_o = en_i + ? data_i + : data_r; + + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff_en_bypass) diff --git a/designs/black-parrot/src/basejump_stl/bsg_dff_reset.sv b/designs/black-parrot/src/basejump_stl/bsg_dff_reset.sv new file mode 100644 index 0000000..a9459bc --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dff_reset.sv @@ -0,0 +1,24 @@ +`include "bsg_defines.sv" + +module bsg_dff_reset #(`BSG_INV_PARAM(width_p), reset_val_p=0, harden_p=0) + (input clk_i + ,input reset_i + ,input [width_p-1:0] data_i + ,output [width_p-1:0] data_o + ); + + reg [width_p-1:0] data_r; + + assign data_o = data_r; + + always @(posedge clk_i) + begin + if (reset_i) + data_r <= width_p'(reset_val_p); + else + data_r <= data_i; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff_reset) diff --git a/designs/black-parrot/src/basejump_stl/bsg_dff_reset_en.sv b/designs/black-parrot/src/basejump_stl/bsg_dff_reset_en.sv new file mode 100644 index 0000000..9c6bcaa --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dff_reset_en.sv @@ -0,0 +1,37 @@ +/** + * bsg_dff_reset_en.sv + */ + +`include "bsg_defines.sv" + +module bsg_dff_reset_en + #(parameter `BSG_INV_PARAM(width_p) + , parameter reset_val_p=0 + , parameter harden_p=0 + ) + ( + input clk_i + , input reset_i + , input en_i + , input [width_p-1:0] data_i + , output logic [width_p-1:0] data_o + ); + + logic [width_p-1:0] data_r; + + assign data_o = data_r; + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + data_r <= width_p'(reset_val_p); + end + else begin + if (en_i) begin + data_r <= data_i; + end + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff_reset_en) diff --git a/designs/black-parrot/src/basejump_stl/bsg_dff_reset_en_bypass.sv b/designs/black-parrot/src/basejump_stl/bsg_dff_reset_en_bypass.sv new file mode 100644 index 0000000..049d9c3 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dff_reset_en_bypass.sv @@ -0,0 +1,44 @@ +/** + * bsg_dff_reset_en_bypass.sv + * + */ + + +`include "bsg_defines.sv" + +module bsg_dff_reset_en_bypass + #(parameter `BSG_INV_PARAM(width_p) + , parameter reset_val_p=0 + , parameter harden_p=0 + ) + ( + input clk_i + , input reset_i + , input en_i + , input [width_p-1:0] data_i + , output logic [width_p-1:0] data_o + ); + + logic [width_p-1:0] data_r; + + bsg_dff_reset_en #( + .width_p(width_p) + ,.reset_val_p(reset_val_p) + ,.harden_p(harden_p) + ) dff ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(en_i) + ,.data_i(data_i) + ,.data_o(data_r) + ); + + assign data_o = en_i + ? data_i + : data_r; + + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff_reset_en_bypass) diff --git a/designs/black-parrot/src/basejump_stl/bsg_dff_reset_set_clear.sv b/designs/black-parrot/src/basejump_stl/bsg_dff_reset_set_clear.sv new file mode 100644 index 0000000..6fe1875 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dff_reset_set_clear.sv @@ -0,0 +1,39 @@ +/** + * bsg_dff_reset_set_clear.sv + * + * Reset has priority over set. + * Set has priority over clear (by default). + * + */ + + +`include "bsg_defines.sv" + +module bsg_dff_reset_set_clear + #(parameter `BSG_INV_PARAM(width_p) + , parameter clear_over_set_p=0 // if 1, clear overrides set. + ) + ( + input clk_i + , input reset_i + , input [width_p-1:0] set_i + , input [width_p-1:0] clear_i + , output logic [width_p-1:0] data_o + ); + + logic [width_p-1:0] data_r; + + always_ff @ (posedge clk_i) + if (reset_i) + data_r <= '0; + else + if (clear_over_set_p) + data_r <= (data_r | set_i) & (~clear_i); + else + data_r <= (data_r & ~clear_i) | set_i; + + assign data_o = data_r; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff_reset_set_clear) diff --git a/designs/black-parrot/src/basejump_stl/bsg_dlatch.sv b/designs/black-parrot/src/basejump_stl/bsg_dlatch.sv new file mode 100644 index 0000000..5bbac62 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dlatch.sv @@ -0,0 +1,26 @@ +`include "bsg_defines.sv" + +module bsg_dlatch #(parameter `BSG_INV_PARAM(width_p) + ,parameter i_know_this_is_a_bad_idea_p=0 + ) + (input clk_i + ,input [width_p-1:0] data_i + ,output logic [width_p-1:0] data_o + ); + + if (i_know_this_is_a_bad_idea_p == 0) + $fatal( 1, "Error: you must admit this is a bad idea before you are allowed to use the bsg_dlatch module!" ); + + logic [width_p-1:0] data_r; + always_latch + begin + if (clk_i) + data_r <= data_i; + end + + assign data_o = data_r; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dlatch) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_dramsim3_pkg.sv b/designs/black-parrot/src/basejump_stl/bsg_dramsim3_pkg.sv new file mode 100644 index 0000000..b1d8ab5 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_dramsim3_pkg.sv @@ -0,0 +1,224 @@ +package bsg_dramsim3_pkg; +`include "bsg_defines.sv" + + localparam int max_cfgs = 128; + localparam int lg_max_cfgs = `BSG_SAFE_CLOG2(max_cfgs); + + typedef enum bit [lg_max_cfgs-1:0] { + e_ro_ra_bg_ba_ch_co, + e_ro_ra_bg_ba_co_ch, + e_ro_ch_ra_ba_bg_co + } bsg_dramsim3_address_mapping_e; + +endpackage // bsg_dramsim3_pkg + +// this models 8 legacy-mode channels of an 8gb chip +// x128 is the data width of one legacy mode channel +package bsg_dramsim3_hbm2_8gb_x128_pkg; + parameter int tck_ps = 1000; + parameter int channel_addr_width_p = 30; + parameter int data_width_p=256; + parameter int num_channels_p=8; + parameter int num_columns_p=64; + parameter int num_rows_p=32768; + parameter int num_ba_p=4; + parameter int num_bg_p=4; + parameter int num_ranks_p=1; + parameter longint size_in_bits_p=2**36; // 8GB (64Gb) + parameter string config_p="HBM2_8Gb_x128.ini"; + parameter bsg_dramsim3_pkg::bsg_dramsim3_address_mapping_e address_mapping_p=bsg_dramsim3_pkg::e_ro_ra_bg_ba_ch_co; + + typedef struct packed { + logic [$clog2(num_rows_p)-1:0] ro; + logic [$clog2(num_bg_p)-1:0] bg; + logic [$clog2(num_ba_p)-1:0] ba; + logic [$clog2(num_columns_p)-1:0] co; + logic [$clog2(data_width_p>>3)-1:0] byte_offset; + } dram_ch_addr_s; + +endpackage // bsg_dramsim3_hbm2_8gb_x128_pkg + +// this models 16 pseudo-channels of an 8gb chip +// with 32 banks (4 bank groups, 8 banks per group) +// x64 is due to the halved data width of a pseudo-channel +// from a 128-bit legacy mode channel +package bsg_dramsim3_hbm2_8gb_x64_32ba_pkg; + parameter int tck_ps = 1000; + parameter int channel_addr_width_p = 29; + parameter int data_width_p=256; + parameter int num_channels_p=16; + parameter int num_columns_p=32; + parameter int num_rows_p=16384; + parameter int num_ba_p=4; + parameter int num_bg_p=8; + parameter int num_ranks_p=1; + parameter longint size_in_bits_p=2**36; // 8GB (64Gb) + parameter string config_p="HBM2_8Gb_x64_32ba.ini"; + parameter bsg_dramsim3_pkg::bsg_dramsim3_address_mapping_e address_mapping_p=bsg_dramsim3_pkg::e_ro_ra_bg_ba_ch_co; + + typedef struct packed { + logic [$clog2(num_rows_p)-1:0] ro; + logic [$clog2(num_bg_p)-1:0] bg; + logic [$clog2(num_ba_p)-1:0] ba; + logic [$clog2(num_columns_p)-1:0] co; + logic [$clog2(data_width_p>>3)-1:0] byte_offset; + } dram_ch_addr_s; + +endpackage + +// this models a single pseudo-channel of the 16gb chip +// this lets us model a scaled-down version of the larger chip +// and reduce simulations memory footprint +// x64 is due to the halved data width of a pseudo-channel +// from a 128-bit legacy mode channel +package bsg_dramsim3_hbm2_1gb_x64_32ba_pkg; + parameter int tck_ps = 1000; + parameter int channel_addr_width_p = 30; + parameter int data_width_p=256; + parameter int num_channels_p=1; + parameter int num_columns_p=32; + parameter int num_rows_p=32768; + parameter int num_ba_p=4; + parameter int num_bg_p=8; + parameter int num_ranks_p=1; + parameter longint size_in_bits_p=2**33; // 1GB (8Gb) + parameter string config_p="HBM2_1Gb_x64_32ba.ini"; + parameter bsg_dramsim3_pkg::bsg_dramsim3_address_mapping_e address_mapping_p=bsg_dramsim3_pkg::e_ro_ra_bg_ba_ch_co; + + typedef struct packed { + logic [$clog2(num_rows_p)-1:0] ro; + logic [$clog2(num_bg_p)-1:0] bg; + logic [$clog2(num_ba_p)-1:0] ba; + logic [$clog2(num_columns_p)-1:0] co; + logic [$clog2(data_width_p>>3)-1:0] byte_offset; + } dram_ch_addr_s; + +endpackage + +// this models two pseudo-channels of the 16gb chip +// this lets us model a scaled-down version of the larger chip +// and reduce simulations memory footprint +// x64 is due to the halved data width of a pseudo-channel +// from a 128-bit legacy mode channel +package bsg_dramsim3_hbm2_2gb_x64_32ba_pkg; + parameter int tck_ps = 1000; + parameter int channel_addr_width_p = 30; + parameter int data_width_p=256; + parameter int num_channels_p=2; + parameter int num_columns_p=32; + parameter int num_rows_p=32768; + parameter int num_ba_p=4; + parameter int num_bg_p=8; + parameter int num_ranks_p=1; + parameter longint size_in_bits_p=2**34; // 2GB (16Gb) + parameter string config_p="HBM2_2Gb_x64_32ba.ini"; + parameter bsg_dramsim3_pkg::bsg_dramsim3_address_mapping_e address_mapping_p=bsg_dramsim3_pkg::e_ro_ra_bg_ba_ch_co; + + typedef struct packed { + logic [$clog2(num_rows_p)-1:0] ro; + logic [$clog2(num_bg_p)-1:0] bg; + logic [$clog2(num_ba_p)-1:0] ba; + logic [$clog2(num_columns_p)-1:0] co; + logic [$clog2(data_width_p>>3)-1:0] byte_offset; + } dram_ch_addr_s; + +endpackage + +// this 16 pseudo-channels of the 16gb chip +// x64 is due to the halved data width of a pseudo-channel +// from a 128-bit legacy mode channel +package bsg_dramsim3_hbm2_16gb_x64_pkg; + parameter int tck_ps = 1000; + parameter int channel_addr_width_p = 30; + parameter int data_width_p=256; + parameter int num_channels_p=16; + parameter int num_columns_p=32; + parameter int num_rows_p=32768; + parameter int num_ba_p=4; + parameter int num_bg_p=8; + parameter int num_ranks_p=1; + parameter longint size_in_bits_p=2**37; // 16GB (128Gb) + parameter string config_p="HBM2_16Gb_x64.ini"; + parameter bsg_dramsim3_pkg::bsg_dramsim3_address_mapping_e address_mapping_p=bsg_dramsim3_pkg::e_ro_ra_bg_ba_ch_co; + + typedef struct packed { + logic [$clog2(num_rows_p)-1:0] ro; + logic [$clog2(num_bg_p)-1:0] bg; + logic [$clog2(num_ba_p)-1:0] ba; + logic [$clog2(num_columns_p)-1:0] co; + logic [$clog2(data_width_p>>3)-1:0] byte_offset; + } dram_ch_addr_s; + +endpackage + +// this models 8 legacy-mode channels of the 4gb chip +// x128 is the data width of one legacy mode channel +package bsg_dramsim3_hbm2_4gb_x128_pkg; + parameter int tck_ps = 1000; + parameter int channel_addr_width_p = 29; + parameter int data_width_p=256; + parameter int num_channels_p=8; + parameter int num_columns_p=64; + parameter int num_rows_p=16384; + parameter int num_ba_p=4; + parameter int num_bg_p=4; + parameter int num_ranks_p=1; + parameter longint size_in_bits_p=2**35; // 4GB (32Gb) + parameter string config_p="HBM2_4Gb_x128.ini"; + parameter bsg_dramsim3_pkg::bsg_dramsim3_address_mapping_e address_mapping_p=bsg_dramsim3_pkg::e_ro_ra_bg_ba_ch_co; + + typedef struct packed { + logic [$clog2(num_rows_p)-1:0] ro; + logic [$clog2(num_bg_p)-1:0] bg; + logic [$clog2(num_ba_p)-1:0] ba; + logic [$clog2(num_columns_p)-1:0] co; + logic [$clog2(data_width_p>>3)-1:0] byte_offset; + } dram_ch_addr_s; + +endpackage // bsg_dramsim3_hbm2_8gb_x128_pkg + +package bsg_dramsim3_lpddr3_8gb_x32_1600_pkg; + parameter int tck_ps = 1250; + parameter int channel_addr_width_p = 31; + parameter int data_width_p=512; + parameter int num_channels_p=1; + parameter int num_columns_p=128; + parameter int num_rows_p=32768; + parameter int num_ba_p=8; + parameter int num_bg_p=1; + parameter int num_ranks_p=1; + parameter longint size_in_bits_p=2**34; // 2GB (16Gb) + parameter string config_p="LPDDR3_8Gb_x32_1600.ini"; + parameter bsg_dramsim3_pkg::bsg_dramsim3_address_mapping_e address_mapping_p=bsg_dramsim3_pkg::e_ro_ch_ra_ba_bg_co; + + typedef struct packed { + logic [$clog2(num_rows_p)-1:0] ro; + logic [$clog2(num_ba_p)-1:0] ba; + logic [$clog2(num_columns_p)-1:0] co; + logic [$clog2(data_width_p>>3)-1:0] byte_offset; + } dram_ch_addr_s; + +endpackage // bsg_dramsim3_lpddr3_8gb_x32_1600_pkg + +package bsg_dramsim3_lpddr_2Gb_x16_pkg; + parameter int tck_ps=4800; + parameter int channel_addr_width_p=30; + parameter int data_width_p=512; + parameter int num_channels_p=1; + parameter int num_columns_p=256; + parameter int num_rows_p=16384; + parameter int num_ba_p=4; + parameter int num_bg_p=1; + parameter int num_ranks_p=1; + parameter longint size_in_bits_p=2**33; // 1GB (8Gb) + parameter string config_p="lpddr_2Gb_x16.ini"; + parameter address_mapping_p=bsg_dramsim3_pkg::e_ro_ch_ra_ba_bg_co; + + typedef struct packed { + logic [$clog2(num_rows_p)-1:0] ro; + logic [$clog2(num_ba_p)-1:0] ba; + logic [$clog2(num_columns_p)-1:0] co; + logic [$clog2(data_width_p>>3)-1:0] byte_offset; + } dram_ch_addr_s; + +endpackage // bsg_dramsim3_lpddr_2Gb_x16_pkg diff --git a/designs/black-parrot/src/basejump_stl/bsg_edge_detect.sv b/designs/black-parrot/src/basejump_stl/bsg_edge_detect.sv new file mode 100644 index 0000000..e60a975 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_edge_detect.sv @@ -0,0 +1,34 @@ + +`include "bsg_defines.sv" + +module bsg_edge_detect + #(parameter falling_not_rising_p = 0) + (input clk_i + , input reset_i + + , input sig_i + , output detect_o + ); + + logic sig_r; + bsg_dff_reset + #(.width_p(1)) + sig_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(sig_i) + ,.data_o(sig_r) + ); + + if (falling_not_rising_p == 1) + begin : falling + assign detect_o = ~sig_i & sig_r; + end + else + begin : rising + assign detect_o = sig_i & ~sig_r; + end + +endmodule + diff --git a/designs/black-parrot/src/basejump_stl/bsg_encode_one_hot.sv b/designs/black-parrot/src/basejump_stl/bsg_encode_one_hot.sv new file mode 100644 index 0000000..112f6e8 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_encode_one_hot.sv @@ -0,0 +1,93 @@ +// encodes a one hot signal into an address +// 0001 --> 0, v=1 +// 0010 --> 1, v=1 +// 0100 --> 2, v=1 +// 1000 --> 3, v=1 +// 0000 --> 0, v=0 +// O*1O*1O* --> undefined +`include "bsg_defines.sv" + + +// we implement at this as a parallel prefix computation +// it is basically a big, clever tree of OR's with a +// certain structure (see sample debug output). + +module bsg_encode_one_hot #(parameter width_p=8, parameter lo_to_hi_p=1, parameter debug_p=0) +(input [width_p-1:0] i + ,output [`BSG_SAFE_CLOG2(width_p)-1:0] addr_o + ,output v_o // whether any bits are set +); + + localparam levels_lp = $clog2(width_p); + // adjust for non-power of two input + localparam aligned_width_lp = 1 << $clog2(width_p); + + genvar level; + genvar segment; + + wire [levels_lp:0][aligned_width_lp-1:0] addr; + wire [levels_lp:0][aligned_width_lp-1:0] v; + + // base case, also handle padding for non-power of two inputs + assign v [0] = lo_to_hi_p ? ((aligned_width_lp) ' (i)) : i << (aligned_width_lp - width_p); + assign addr[0] = (width_p == 1) ? '0 : `BSG_UNDEFINED_IN_SIM('0); + + for (level = 1; level < levels_lp+1; level=level+1) + begin : rof + localparam segments_lp = 2**(levels_lp-level); + localparam segment_slot_lp = aligned_width_lp/segments_lp; + localparam segment_width_lp = level; // how many bits are needed at each level + + for (segment = 0; segment < segments_lp; segment=segment+1) + begin : rof1 + wire [1:0] vs = { + v[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)] + , v[level-1][segment*segment_slot_lp] + }; + + assign v[level][segment*segment_slot_lp] = | vs; + + if (level == 1) + assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = { vs[lo_to_hi_p] }; + else + begin : fi + assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] + = { vs[lo_to_hi_p] + , addr[level-1][segment*segment_slot_lp+:segment_width_lp-1] + | addr[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)+:segment_width_lp-1] + }; + end + end + end + + assign v_o = v[levels_lp][0]; + +// BSG_SAFE_CLOG2 handles width_p = 1 case +`ifdef SYNTHESIS + assign addr_o = addr[levels_lp][`BSG_SAFE_CLOG2(width_p)-1:0]; +`else + assign addr_o = (((i-1) & i) == '0) + ? addr[levels_lp][`BSG_SAFE_CLOG2(width_p)-1:0] + : { `BSG_SAFE_CLOG2(width_p){1'bx}}; + +// generates debug output that looks like this: +// (addr) (v) +// xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00000000000000000000000000000100 +// z0z0z0z0z0z0z0z0z0z0z0z0z0z0z0z0 z0z0z0z0z0z0z0z0z0z0z0z0z0z0z1z0 +// zz00zz00zz00zz00zz00zz00zz00zz10 zzz0zzz0zzz0zzz0zzz0zzz0zzz0zzz1 +// zzzzz000zzzzz000zzzzz000zzzzz010 zzzzzzz0zzzzzzz0zzzzzzz0zzzzzzz1 +// zzzzzzzzzzzz0000zzzzzzzzzzzz0010 zzzzzzzzzzzzzzz0zzzzzzzzzzzzzzz1 +// zzzzzzzzzzzzzzzzzzzzzzzzzzz00010 zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz1 +// addr_o=00010 v_o=1 + + if (debug_p) + always @(addr_o or v_o) + begin + `BSG_HIDE_FROM_VERILATOR(#1) + for (integer k = 0; k <= $clog2(width_p); k=k+1) + $display("%b %b",addr[k], v[k]); + $display("addr_o=%b v_o=%b", addr_o, v_o); + end +`endif + +endmodule diff --git a/designs/black-parrot/src/basejump_stl/bsg_expand_bitmask.sv b/designs/black-parrot/src/basejump_stl/bsg_expand_bitmask.sv new file mode 100644 index 0000000..22d96bd --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_expand_bitmask.sv @@ -0,0 +1,40 @@ +/** + * bsg_expand_bitmask.sv + * + * This module expands each bit in the input vector by the factor of + * expand_p. + * + * @author tommy + * + * + * example + * ------------------------ + * in_width_p=2, expand_p=4 + * ------------------------ + * i=00 -> o=0000_0000 + * i=01 -> o=0000_1111 + * i=10 -> o=1111_0000 + * i=11 -> o=1111_1111 + * + */ + + +`include "bsg_defines.sv" + +module bsg_expand_bitmask #(parameter `BSG_INV_PARAM(in_width_p) + ,parameter `BSG_INV_PARAM(expand_p) + ,localparam safe_expand_lp = `BSG_MAX(expand_p, 1)) +( + input [in_width_p-1:0] i + , output logic [(in_width_p*safe_expand_lp)-1:0] o +); + + + always_comb + for (integer k = 0; k < in_width_p; k++) + o[safe_expand_lp*k+:safe_expand_lp] = {safe_expand_lp{i[k]}}; + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_expand_bitmask) diff --git a/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_large.sv b/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_large.sv new file mode 100644 index 0000000..34b4f0d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_large.sv @@ -0,0 +1,310 @@ +// MBT 11/10/14 +// +// +// bsg_fifo_1r1w_large +// +// This implementation is specifically +// intended for processes where 1RW rams +// are much cheaper than 1R1W rams, like +// most ASIC processes, or where 1R1W rams +// are not available. +// +// The idea is that a 1R1W ram is often 1.7X +// or more of the size of a 1RW, so we can +// save area. +// +// There are five+ possible implementations +// of a FIFO using 1RW rams: +// +// a. (bsg_fifo_1r1w_small) synthesize 1R1W RF from DFFs. Area per bit +// of storage is often 10x larger than 1RW SRAM. But the SRAM +// needs a sense-amp for every bit that is accessed per cycle, which is +// about the size of 7 DFF-bits. So, for instance, if you need +// to access 64 bits per cycle, then that incurs ~450 DFF bits of overhead, +// so the DFF-RF will be cheaper up until to 512 bits. If you only need +// to access 32 bits in parallel, then the breakeven would be closer to 256 bits. +// +// b. Use a true 1R1W ram; about 2X larger than 1RW SRAM. Maybe available for FPGA +// but often not available, or not a good deal for ASIC. +// +// c. (not implemented) To get more ports, use two rams of half size, and then round +// robin odd/even elements. We can favor the +// writer, and then use a two-element fifo +// with bypass after each 1RW, and select between +// the two. Net cost is 4 words of DFF plus two 1RW SRAMs of size 1/2 but same width. +// A draft of this code is at the end of this file, but it is incomplete/untested Caveat emptor. +// +// d. (bsg_fifo_1r1w_large) To get "more ports", use a single 1RW of double width +// and read/write two elements at a time, as described in this module. +// The cost is 7 DFF elements for staging plus 1 RW of double width and half words. So for +// a 64-bit wide ram, the overhead is almost 3*450 = 1400 DFF bits; slightly more than +// case c), but since there is only one RAM there are savings. +// +// A single 1RW versus two 1RW's can be a win, but not always. The RAM +// is larger, so there is potential for there is to be more amortization of +// overhead. But on the other hand, # of sense amps is the same, so some of the +// overheads are the same. One problem with this design for smaller RAMs is +// that it doubles the number of sense amps in a single ram, which can make +// the aspect ratio undesirable or even impossible. +// +// e. (bsg_fifo_1r1w_pseudo_large) Use a pseudo 1RW fifo, where it looks like it is 1r1w, but actually +// it is a 1RW that favors writes. Unlike "large", it has the same bandwidth, so we save space +// on sense amps. This only applies when you know data is coming in at 1/2 rate or slower. +// +// Generally speaking, an SRAM's area is proportional to the number of bits, the number of +// sense amps, and the amount of decoder. If we take a wide ram and break it into two rams +// of half the width, but the same total bits, we have the same number of total bits and +// the same number of sense amps, but more decoder area, so there is a slight increase. +// +// The 7 elements overhead coud potentially be significant, +// since they are implemented with ordinary flops, probably 4X per bit versus the +// So we have an equation, area improvement = 1.7 W / (W + 4*7); +// +// 64 --> 20% (probably less than this) +// 128 --> 40% +// 256 --> 53% +// 512 --> 62% + +// +// Rather than use two 1RW and alternate +// between them, we use one 1RW of double +// width. This saves area especially for +// medium size fifos (e.g. 64x64 = 4096 bits). +// +// Since data is bunched in pairs, we create +// a free slot from which we can fetch data from +// the big fifo every other cycle. + +// When there is little data in the FIFO +// data is round robin dispatched to a pair of +// two element fifos (little fifos). If the +// little fifos fill up, then the data is bunched up into +// pairs and written into a double width single +// ported 1RW FIFO (big fifos). Priority is given to +// writing to the big fifos; except if the little fifo +// only has two elements left; then reads are given +// priority so that the data arrives in time. +// +// This policies allows us to guarantee the invariants of +// a FIFO: it will never say it's full if it has less than +// N elements in it; and it will never say it's empty +// if it has more than 0 elements in it. This is not +// that straightforward with this kind of fifo because +// the data could actually be in three different places: +// the buncher, the little FIFO, and the big FIFO. +// +// Note that the FIFO does not guarantee an upper bound +// on how many elements it will accept. This may actually +// be as high as N+4+3. +// +// +// |\ ___ _______ +// _______________| | |R|__/ 2 fifo\ ___ +// /------------\_/ | | |R| \_______/ \ | N \ +// |ser2parallel|_ ________ | |__|2| | to |___ +// \------------/ \ / big \ | | |t| ______ | 1 | +// \/ 1RW FIFO \__| | |2|__/ 2 fifo\_/ |___/ +// \__________/ |/ |_| \_______/ +// +// + +`include "bsg_defines.sv" + +module bsg_fifo_1r1w_large #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + ) + (input clk_i + , input reset_i + + , input [width_p-1:0] data_i + , input v_i + , output ready_and_o + + , output v_o + , output [width_p-1:0] data_o + , input yumi_i + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial assert ((els_p & 1) == 0) else + $error("odd number of elements for two port fifo not handled."); +`endif + + wire [width_p*2-1:0] data_sipo; + wire [1:0] valid_sipo; + + wire [1:0] yumi_cnt_sipo; + + // we had to bump els_p to 3 because of the case + // where the little fifos have 3 elements (blocking + // us from restoring from the 1RW FIFO), and where + // the sipo has only one element (blocking us from + // spooling to the 1RW fifo.) If we simultaneously + // have enque and deque requests, then the sipo will + // need to spool at the same time that we need to + // access the 1RW fifo to prevent empty. the solution + // is to add one extra element to the sipo so that it + // can hold off one more cycle before spooling. then + // we can restore 2 words from the fifo, and spool + // on the next cycle. + + bsg_serial_in_parallel_out #(.width_p(width_p) + ,.els_p(3) + ,.out_els_p(2) + ) sipo + (.clk_i (clk_i) + ,.reset_i (reset_i) + ,.valid_i (v_i) + ,.data_i (data_i) + ,.ready_and_o (ready_and_o) + ,.valid_o (valid_sipo) + ,.data_o (data_sipo) + + ,.yumi_cnt_i(yumi_cnt_sipo) + ); + + wire [2*width_p-1:0] big_data_lo; + wire big_valid, big_full_lo, big_empty_lo; + logic big_enq, big_deq, big_deq_r; + + always_ff @(posedge clk_i) + big_deq_r <= big_deq; + + bsg_fifo_1rw_large #(.width_p(width_p*2) + ,.els_p (els_p >> 1) + ) big1p + (.clk_i (clk_i ) + ,.reset_i (reset_i ) + + // low bits are older element + ,.data_i (data_sipo ) + + ,.v_i (big_valid) + ,.enq_not_deq_i(big_enq) + + ,.full_o (big_full_lo ) + ,.empty_o (big_empty_lo) + ,.data_o (big_data_lo ) + ); + + wire [2*width_p-1:0] little_data_rot; + wire [1:0] little_valid, little_ready; + wire [1:0] little_ready_rot, little_valid_rot; + wire [1:0] valid_int; + + // we are in bypass mode if we can directly bypass + // to the small fifos. + // - we cannot have on the previous cycle loaded + // data from the big fifo; the small fifo we would like + // to use cannot be full, and the big fifo must be empty. + + wire bypass_mode = ~big_deq_r & little_ready[0] & big_empty_lo; + + wire can_spill = ~big_full_lo & ~bypass_mode; + + // we have an emergency if both little fifos can receive data + // (i.e. <= 2 elements) and we did not just fetch from the big fifo + // and we have data in the big fifo. if we don't transfer now, we + // will have a bubble. + + wire emergency = (&little_ready_rot) & ~big_empty_lo & ~big_deq_r; + + // we will spill if we are in spill mode; and we have two elements + // to spill, and the big fifo is not full. + + wire will_spill = can_spill & (&valid_sipo) & ~emergency; + + // we deque if we are not spilling, big fifo has data available + // and the small fifos has two elements free with an enque pending + // or one element free with no enque pending + + assign big_deq = ~will_spill & ~big_empty_lo + & (big_deq_r + ? (~|valid_int) // small fifos are empty + : (&little_ready_rot)); // both fifos > 1 el free, no enq pending + + assign big_valid = will_spill | big_deq; + assign big_enq = will_spill; + + wire [2*width_p-1:0] little_data = big_deq_r ? big_data_lo : data_sipo; + wire [1:0] bypass_vector = valid_sipo & { bypass_mode, bypass_mode }; + assign little_valid = big_deq_r ? 2'b11 : bypass_vector; + + wire [1:0] cnt; + + bsg_thermometer_count #(.width_p(2)) thermo(.i(little_ready & bypass_vector) + ,.o(cnt)); + + assign yumi_cnt_sipo = will_spill + ? 2'b10 + : cnt; + + bsg_round_robin_2_to_2 #(.width_p(width_p)) + rr222 + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(little_data) + ,.v_i (little_valid) + ,.ready_o(little_ready) + + ,.data_o(little_data_rot) + ,.v_o (little_valid_rot) + ,.ready_i(little_ready_rot) + ); + + + wire [1:0][width_p-1:0] data_int; + wire [1:0] yumi_int; + + genvar i; + + for (i = 0; i < 2; i++) + begin : twofer + bsg_two_fifo #(.width_p(width_p)) little + (.clk_i (clk_i) + ,.reset_i (reset_i) + + ,.ready_param_o (little_ready_rot[i] ) + ,.data_i (little_data_rot [i*width_p+:width_p]) + ,.v_i (little_valid_rot[i] ) + + ,.v_o (valid_int [i]) + ,.data_o (data_int [i]) + ,.yumi_i (yumi_int [i]) + ); + end + + bsg_round_robin_n_to_1 #(.width_p(width_p) + ,.num_in_p(2) + ,.strict_p(1) + ) round_robin_n_to_1 + (.clk_i (clk_i ) + ,.reset_i(reset_i ) + + ,.data_i (data_int ) + ,.v_i(valid_int) + ,.yumi_o (yumi_int ) + + ,.data_o (data_o ) + ,.v_o(v_o ) + ,.tag_o () + ,.yumi_i (yumi_i ) + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + // this sums up all of the storage in this fifo + wire [31:0] num_elements_debug + = 2*big1p.num_elements_debug + + valid_int[0] + valid_int[1] + + sipo.valid_r[0] + sipo.valid_r[1] + + !little_ready_rot[0] + !little_ready_rot[1]; + +`endif + + +endmodule + + +`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_large) diff --git a/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_pseudo_large.sv b/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_pseudo_large.sv new file mode 100644 index 0000000..5d6149f --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_pseudo_large.sv @@ -0,0 +1,268 @@ +// +// bsg_fifo_1r1w_pseudo_large +// +// MBT 3/11/15 +// +// This fifo looks like a 1R1W fifo but actually is implemented +// with a 1RW FIFO for the bulk of its storage, and has a +// small 1R1W FIFO to help decouple reads and writes that may +// conflict. This FIFO is useful for cases where reads and writes +// each individually have a duty cycle of 50% or less. +// +// In 180 nm, the area of a 128x70 1R1W is about 1.75 the equivalent 1RW. +// The 2-element little fifo is about 0.25 the above 1RW. So the net +// savings is 1.25 versus 1.75; but that assumes the 1R1W has no overhead +// when in reality, it would probably have a 2-el fifo as well (e.g. 2.00). +// So this module does actually save area. +// +// For example, an element is written into the +// FIFO every other cycle, and an element is read from the FIFO +// every other cycle. +// +// _______________________________ +// \ __________ \__|\ ____________ +// \___/ 1RW FIFO \___| |__/ 1R1W FIFO \______ +// \___big____/ | | \___little___/ +// |/ +// +// Data is inserted directly into the little fifo until +// that fifo is full. Then it is stored in +// the 1 port ram. When data is not enqued into the big fifo, +// and there is sufficient gauranteed space in the little fifo +// then data is transferred from the big fifo to the little fifo. +// +// Although both bsg_fifo_1r1w_pseudo_large and bsg_fifo_1r1w_large +// use 1RW rams, the pseudo fifo will be more area efficient for +// smaller FIFO sizes, because 1) it does not read as much data at a time +// and thus does not require as many sense amps (see your RAM compiler) +// and 2) the little FIFO is smaller than the associated "little fifo" +// serial-to-parallel registers of the 1r1w_large. +// +// * Enque Guarantees: +// +// In order to maintain the appearance of the 1R1W FIFO, this +// FIFO will always accept up to els_p data elements without saying +// that it is full. (These elements can be sent back-to-back, but this +// may starve out the little FIFO since it will not be able to +// access the 1RW FIFO.) +// +// * Deque non-guarantees and guarantees: +// +// As long as the duty cycle is <= 50 percent in any window of the input data stream +// that is twice the size of the parameter max_conflict_run_p, the FIFO will report +// that data is available when there is data available. If the user violates this +// parameter, the FIFO may be busy receiving data and potentially could report not +// having data when there is in fact data inside the FIFO. +// +// As long as you check the v_o signal, you will not lose data; but you may have periods +// where are unable to read because writes are occupying the bandwidth. +// +// On the other hand, if you have code that counts how many elements went into the FIFO, +// and then expects to deque that number of elements without checking the v_o bit, that +// code could fail.) +// +// (Another example: if the incoming data comes in bursts of N words, followed by +// a pause of at least N cycles, and the receiver reads data at most one word +// every other two cycles; then the FIFO will never report empty if it has data.) +// +// Parameters: +// +// max_conflict_run_p (N): +// +// First, the maximum # of sequential writes, N, that the FIFO can sustain before dropping +// below an average throughput of 1/2 because of structural hazards on the 1RW ram. +// This conflict run property is useful, for example, if we know that traffic comes in bursts +// of consecutive packets. + +// Second, how many elements must be queued up before the FIFO starts +// using the large 1RW FIFO, which will likely consume a lot more power, +// after how many elements the effective throughput of the FIFO drops to 1/2. + +// early_yumi_p: this parameter says whether the yumi signal comes in earlier +// which allows us to reduce latency between deque and the next element +// being transferred from the internal ram to the output, which in turns +// reduces how many FIFO elements are required by the setting of max_conflict_run_p +// Without early_yumi, this latency is +// 2+n cycles (yumi->BF deq->LF enq) where n is the number BF enques. early yumi +// changes this to (yumi/BF deq -> LF enq) or 1+n cycles. +// early_yumi_p can be used if the yumi signal is known early, and reduces the +// required little fifo size by 1 element to 1+n. + +// [ Assertion to be formally proved: the FIFO size required for a conflict run size of n is 2+n. +// (yumi->BF deq->LF enq)+conflicts. So, your basic small FIFO should be at least 3 elements for +// enque patterns that do every-other cycle with an unknown relationship to the output, which +// is also every other cycle. The early yumi flag changes this parameter to +// (yumi/BF deq -> LF enq) +conflicts = 1+n = 2 elements ] +// +// (early_yumi_p allows the fifo to support 1/2 rate inputs and outputs with conflict runs of 1 +// and only a twofer.) + +// TODO: make max_conflict_run_p a parameter (and correspondingly parameterize little FIFO size +// and update control logic) +// add assertions that detect violation of the max conflict run +// + +`include "bsg_defines.sv" + +module bsg_fifo_1r1w_pseudo_large #(parameter `BSG_INV_PARAM(width_p ) + , parameter `BSG_INV_PARAM(els_p ) + // Future extensions: need to add max_conflict_run_p; + // currently it is "1" and only if early_yumi_p = 1. + // to implement this, we need to parameterize the fifo + // to be of size (max_conflict_run_p+2-early_yumi_p) + + // if yumi is on critical path; you can change this to 0. + // but to maintain performance, we would need to + // implement the max_conflict_run_p parameter. + , parameter early_yumi_p = 1 + , parameter verbose_p = 0 + ) + (input clk_i + , input reset_i + + , input [width_p-1:0] data_i + , input v_i + , output ready_and_o + + , output v_o + , output [width_p-1:0] data_o + , input yumi_i + ); + + wire big_full_lo, big_empty_lo; + wire [width_p-1:0] big_data_lo; + + logic big_enq, big_deq, big_deq_r; + + wire little_ready_lo, little_will_have_space; + + logic little_valid, big_valid; + + if (early_yumi_p) + assign little_will_have_space = little_ready_lo | yumi_i; + else + assign little_will_have_space = little_ready_lo; + + // whether we dequed something on the last cycle + + always_ff @(posedge clk_i) + if (reset_i) + big_deq_r <= 1'b0; + else + big_deq_r <= big_deq; + + // if the big fifo is not full, then we can take more data + wire ready_and_o_int = ~big_full_lo; + assign ready_and_o = ready_and_o_int; + + // ***** DEBUG ****** + // for debugging; whether we are bypassing the big fifo +`ifndef BSG_HIDE_FROM_SYNTHESIS + + wire bypass_mode = v_i & ~ big_enq; + + // sum up all of the storage in this fifo + wire [31:0] num_elements_debug = big1p.num_elements_debug + big_deq_r + little2p.num_elements_debug; + + logic big_enq_r; + + always_ff @(posedge clk_i) + if (reset_i) + big_enq_r <= 0; + else + big_enq_r <= big_enq_r | big_enq; + + always_ff @(negedge clk_i) + if (verbose_p & (reset_i === 0) & (~big_enq_r & big_enq)) + $display("## %L: overflowing into big fifo for the first time (%m)"); + +`endif + + // + // ***** END DEBUG ****** + + always_comb + begin + // if we fetch an element last cycle, we need to enque + // it into the little fifo + if (big_deq_r) + begin + // we dequed last cycle, so there must be room + // in both big and little fifos + little_valid = 1'b1; + big_enq = v_i; + + // if there is data in big fifo + // and we are not enqueing to the big fifo + // and the little fifo is empty + // we can grab another word + + // we do not test for the yumi signal here + // because an empty little fifo cannot have a yumi. + big_deq = (~big_empty_lo & ~big_enq & ~v_o); + end + else + begin + // clean through bypass mode; skip + // big fifo and go to little fifo + if (big_empty_lo) + begin + little_valid = v_i & little_will_have_space; + big_enq = v_i & ~little_will_have_space; + big_deq = 1'b0; // big FIFO is empty, can't deque + end + else + // there is data in the big fifo + // but we did not fetch from it + // last cycle. + // we cannot enque anything into + // the little fifo this cycle. + begin + little_valid = 1'b0; + big_enq = v_i & ~big_full_lo; + big_deq = ~big_enq & little_will_have_space; + end + end // else: !if(big_deq_r) + + big_valid = big_enq | big_deq; + end + + // if we dequed from the big queue last cycle + // then we enque it into the little fifo + + wire [width_p-1:0] little_data = big_deq_r ? big_data_lo : data_i; + + bsg_fifo_1rw_large #(.width_p(width_p) + ,.els_p(els_p) + ,.verbose_p(verbose_p) + ) big1p + (.clk_i (clk_i ) + ,.reset_i (reset_i ) + ,.data_i (data_i ) + + ,.v_i (big_valid) + ,.enq_not_deq_i(big_enq) + + ,.full_o (big_full_lo ) + ,.empty_o (big_empty_lo) + ,.data_o (big_data_lo ) + ); + + bsg_two_fifo #(.width_p(width_p) + ,. verbose_p(verbose_p) + ,. allow_enq_deq_on_full_p(early_yumi_p)) little2p + (.clk_i (clk_i) + ,.reset_i (reset_i) + ,.ready_param_o (little_ready_lo) + ,.data_i (little_data) + ,.v_i (little_valid) + + ,.v_o (v_o) + ,.data_o (data_o) + ,.yumi_i (yumi_i) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_pseudo_large) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_small.sv b/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_small.sv new file mode 100644 index 0000000..738680e --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_small.sv @@ -0,0 +1,67 @@ +// bsg_fifo_1r1w_small +// +// bsg_fifo with 1 read and 1 write +// +// When harden=0 (default), it uses async-read memory implementation +// Otherwise, it uses sync-read hardened memory implementation +// *** Two implementations above are functionally equivalent *** +// +// used for smaller fifos. +// +// input handshake protocol (based on ready_THEN_valid_p parameter): +// valid-and-ready or +// ready-then-valid +// +// output protocol is valid-yumi (like typical fifo) +// aka valid-then-ready +// +// + +`include "bsg_defines.sv" + +module bsg_fifo_1r1w_small #( parameter `BSG_INV_PARAM(width_p ) + , parameter `BSG_INV_PARAM(els_p ) + , parameter harden_p = 0 + , parameter ready_THEN_valid_p = 0 + ) + ( input clk_i + , input reset_i + + , input v_i + , output ready_param_o + , input [width_p-1:0] data_i + + , output v_o + , output [width_p-1:0] data_o + , input yumi_i + ); + + if (harden_p == 0) + begin: unhardened + if (els_p == 2) begin:tf + bsg_two_fifo #(.width_p(width_p) + ,.ready_THEN_valid_p(ready_THEN_valid_p) + ) twof + (.ready_param_o + ,.*); + end + else begin:un + bsg_fifo_1r1w_small_unhardened #(.width_p(width_p) + ,.els_p(els_p) + ,.ready_THEN_valid_p(ready_THEN_valid_p) + ) fifo + (.*); + end + end + else + begin: hardened + bsg_fifo_1r1w_small_hardened #(.width_p(width_p) + ,.els_p(els_p) + ,.ready_THEN_valid_p(ready_THEN_valid_p) + ) fifo + (.*); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_small) diff --git a/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_small_unhardened.sv b/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_small_unhardened.sv new file mode 100644 index 0000000..731b0af --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_fifo_1r1w_small_unhardened.sv @@ -0,0 +1,115 @@ +// bsg_fifo_1r1w_small_unhardened +// *** Renamed from bsg_fifo_1r1w_small *** +// +// bsg_fifo with 1 read and 1 write, using +// 1-write 1-async-read register file implementation. +// +// used for smaller fifos. +// +// input handshake protocol (based on ready_THEN_valid_p parameter): +// valid-and-ready or +// ready-then-valid +// +// output protocol is valid-yumi (like typical fifo) +// aka valid-then-ready +// +// + +`include "bsg_defines.sv" + +module bsg_fifo_1r1w_small_unhardened #( parameter `BSG_INV_PARAM(width_p ) + , parameter `BSG_INV_PARAM(els_p ) + , parameter ready_THEN_valid_p = 0 + ) + ( input clk_i + , input reset_i + + , input v_i + , output ready_param_o + , input [width_p-1:0] data_i + + , output v_o + , output [width_p-1:0] data_o + , input yumi_i + ); + + wire deque = yumi_i; + wire v_o_tmp; + + assign v_o = v_o_tmp; + + // vivado bug prohibits declaring wire inside of generate block + wire enque; + logic ready_param_lo; + + if (ready_THEN_valid_p) + begin: rtv + assign enque = v_i; + end + else + begin: rav + assign enque = v_i & ready_param_lo; + end + + localparam ptr_width_lp = `BSG_SAFE_CLOG2(els_p); + + // one read pointer, one write pointer; + logic [ptr_width_lp-1:0] rptr_r, wptr_r; + logic full, empty; + + bsg_fifo_tracker #(.els_p(els_p) + ) ft + (.clk_i + ,.reset_i + ,.enq_i (enque) + ,.deq_i (deque) + ,.wptr_r_o(wptr_r) + ,.rptr_r_o(rptr_r) + ,.rptr_n_o() + ,.full_o (full) + ,.empty_o (empty) + ); + + // async read + bsg_mem_1r1w #(.width_p (width_p) + ,.els_p (els_p ) + // MBT: this should be zero + ,.read_write_same_addr_p(0) + ) mem_1r1w + (.w_clk_i (clk_i ) + ,.w_reset_i(reset_i) + ,.w_v_i (enque ) + ,.w_addr_i (wptr_r ) + ,.w_data_i (data_i ) + ,.r_v_i (v_o_tmp) + ,.r_addr_i (rptr_r ) + ,.r_data_o (data_o ) + ); + + // during reset, we keep ready low + // even though fifo is empty + + //assign ready_param_lo = ~full & ~reset_i; + assign ready_param_lo = ~full; + assign ready_param_o = ready_param_lo; + assign v_o_tmp = ~empty; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @ (negedge clk_i) + begin + if (ready_THEN_valid_p & full & v_i & ~reset_i) + $display("%m error: enque full fifo at time %t", $time); + if (empty & yumi_i & ~reset_i) + $display("%m error: deque empty fifo at time %t", $time); + end +`endif + +/* + always_ff @(negedge clk_i) + begin + $display("%m v_i=%x yumi_i=%x wptr=%b rptr=%b enque=%b full=%d empty=%d ready_param_o=%d",v_i,yumi_i,wptr_r, rptr_r, enque, full,empty,ready_param_o); + end + */ +endmodule + +`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_small_unhardened) diff --git a/designs/black-parrot/src/basejump_stl/bsg_fifo_1rw_large.sv b/designs/black-parrot/src/basejump_stl/bsg_fifo_1rw_large.sv new file mode 100644 index 0000000..49c24c2 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_fifo_1rw_large.sv @@ -0,0 +1,127 @@ +`include "bsg_defines.sv" +// MBT +// 11/9/14 +// +// a fifo with only one read or write port, +// using a 1RW *synchronous read* ram. +// +// NOTE: read results appear on next cycle +// + +module bsg_fifo_1rw_large #(parameter `BSG_INV_PARAM(width_p ) + , parameter `BSG_INV_PARAM(els_p ) + , parameter verbose_p = 0 + ) + (input clk_i + , input reset_i + , input [width_p-1:0] data_i + , input v_i + , input enq_not_deq_i + + // full and empty are richer + // than ready_enq and ready_deq + // which could mean just this cycle + + , output full_o + , output empty_o + , output [width_p-1:0] data_o + ); + + localparam ptr_width_lp = `BSG_SAFE_CLOG2(els_p); + + logic [ptr_width_lp-1:0] rd_ptr, wr_ptr; + + logic last_op_is_read_r; + + + wire mem_we = enq_not_deq_i & v_i; + wire mem_re = ~enq_not_deq_i & v_i; + + always_ff @(posedge clk_i) + if (reset_i) + last_op_is_read_r <= 1; + else + if (v_i) + last_op_is_read_r <= mem_re; + + // empty versus full detection. very nice for + // one port case. if ptrs match and last op was a read + // a read, it must be empty; if last op was a write, + // it must be full. + + wire fifo_empty = (rd_ptr == wr_ptr) & last_op_is_read_r; + wire fifo_full = (rd_ptr == wr_ptr) & ~last_op_is_read_r; + + assign full_o = fifo_full; + assign empty_o = fifo_empty; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + always_ff @(posedge clk_i) + assert (reset_i + | ((fifo_full & mem_we) !== 1) + ) else $error("enque on full fifo"); + + always_ff @(posedge clk_i) + assert (reset_i + | ((fifo_empty & mem_re) !== 1) + ) else $error("deque on empty fifo %x %x", fifo_empty, mem_re, v_i, enq_not_deq_i); + + always_ff @(posedge clk_i) + if (verbose_p) + if (v_i) + begin + if (enq_not_deq_i) + $display("### %m enq %x onto fifo (r=%x w=%x)",data_i,rd_ptr,wr_ptr); + else + $display("### %m deq fifo (r=%x w=%x)",rd_ptr,wr_ptr); + end + + + wire [31:0] num_elements_debug = (fifo_empty + ? 0 + : (fifo_full + ? els_p + : (wr_ptr > rd_ptr + ? (wr_ptr - rd_ptr) + : (els_p - (rd_ptr - wr_ptr))))); + +`endif + + bsg_circular_ptr #(.slots_p(els_p) + ,.max_add_p(1) + ) rd_circ_ptr + (.clk (clk_i) + , .reset_i(reset_i) + , .add_i (mem_re) + , .o (rd_ptr ) + , .n_o() + ); + + bsg_circular_ptr #(.slots_p(els_p) + ,.max_add_p(1) + ) wr_circ_ptr + (.clk (clk_i ) + , .reset_i(reset_i) + , .add_i (mem_we) + , .o (wr_ptr ) + , .n_o() + ); + + bsg_mem_1rw_sync #(.width_p(width_p) + ,.els_p(els_p) + ) + mem_1srw (.clk_i + ,.reset_i + ,.data_i (data_i ) + ,.addr_i (mem_we ? wr_ptr : rd_ptr ) + ,.v_i (v_i ) + ,.w_i (mem_we ) + ,.data_o (data_o ) + ); + + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_fifo_1rw_large) diff --git a/designs/black-parrot/src/basejump_stl/bsg_fifo_reorder.sv b/designs/black-parrot/src/basejump_stl/bsg_fifo_reorder.sv new file mode 100644 index 0000000..dec96d9 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_fifo_reorder.sv @@ -0,0 +1,159 @@ +/** + * bsg_fifo_reorder.sv + * + * This module implements a circular FIFO where entries are allocated in order + * and deallocated/dequed in order, but writing the entries can occur out of order. + * + * It can be used to implement things like reorder buffers or store buffers. + */ + + +`include "bsg_defines.sv" + +module bsg_fifo_reorder + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter lg_els_lp=`BSG_SAFE_CLOG2(els_p) + ) + ( + input clk_i + , input reset_i + + // FIFO allocates the next available addr + , output fifo_alloc_v_o + , output [lg_els_lp-1:0] fifo_alloc_id_o + , input fifo_alloc_yumi_i + + // random access write + // data can be written out of order + , input write_v_i + , input [lg_els_lp-1:0] write_id_i + , input [width_p-1:0] write_data_i + + // dequeue written items in order + , output fifo_deq_v_o + , output [width_p-1:0] fifo_deq_data_o + // id of the currently dequeueing fifo entry. This can be used to select + // metadata from a separate memory storage, written at a different time + , output [lg_els_lp-1:0] fifo_deq_id_o + , input fifo_deq_yumi_i + + // this signals that the FIFO is empty + // i.e. there is no reserved spot for returning data, + // and all valid data in the FIFO has been consumed. + , output logic empty_o + ); + + + // fifo tracker + // enque when id is allocated. + // deque when data is dequeued. + logic [lg_els_lp-1:0] wptr_r, rptr_r; + logic full, empty; + logic enq, deq; + + bsg_fifo_tracker #( + .els_p(els_p) + ) tracker0 ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.enq_i(enq) + ,.deq_i(deq) + ,.wptr_r_o(wptr_r) + ,.rptr_r_o(rptr_r) + ,.rptr_n_o() + + ,.full_o(full) + ,.empty_o(empty) + ); + + assign fifo_alloc_v_o = ~full; + assign enq = ~full & fifo_alloc_yumi_i; + assign fifo_alloc_id_o = wptr_r; + + assign empty_o = empty; + + + // valid bit for each entry + // this valid bit is cleared, when the valid data is dequeued. + // this valid bit is set, when the valid data is written. + logic [els_p-1:0] valid_r; + logic [els_p-1:0] set_valid; + logic [els_p-1:0] clear_valid; + + bsg_decode_with_v #( + .num_out_p(els_p) + ) set_demux0 ( + .i(write_id_i) + ,.v_i(write_v_i) + ,.o(set_valid) + ); + + bsg_decode_with_v #( + .num_out_p(els_p) + ) clear_demux0 ( + .i(rptr_r) + ,.v_i(deq) + ,.o(clear_valid) + ); + + bsg_dff_reset_set_clear #( + .width_p(els_p) + ) dff_valid0 ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.set_i(set_valid) + ,.clear_i(clear_valid) + ,.data_o(valid_r) + ); + + + // deque logic + wire fifo_deq_v_lo = valid_r[rptr_r] & ~empty; + assign fifo_deq_v_o = fifo_deq_v_lo; + assign deq = fifo_deq_yumi_i; + + + // data storage + bsg_mem_1r1w #( + .width_p(width_p) + ,.els_p(els_p) + ) mem0 ( + .w_clk_i(clk_i) + ,.w_reset_i(reset_i) + + ,.w_v_i(write_v_i) + ,.w_addr_i(write_id_i) + ,.w_data_i(write_data_i) + + ,.r_v_i(fifo_deq_v_lo) + ,.r_addr_i(rptr_r) + ,.r_data_o(fifo_deq_data_o) + ); + assign fifo_deq_id_o = rptr_r; + + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + always_ff @ (negedge clk_i) begin + if (~reset_i) begin + + if (fifo_alloc_yumi_i) + assert(fifo_alloc_v_o) else $error("Handshaking error. fifo_alloc_yumi_i raised without fifo_alloc_v_o."); + + if (fifo_deq_yumi_i) + assert(fifo_deq_v_o) else $error("Handshaking error. fifo_deq_yumi_i raised without fifo_deq_v_o."); + + if (write_v_i) + assert(~valid_r[write_id_i]) else $error("Cannot write to an already valid data."); + + end + end + +`endif + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_fifo_reorder) diff --git a/designs/black-parrot/src/basejump_stl/bsg_fifo_tracker.sv b/designs/black-parrot/src/basejump_stl/bsg_fifo_tracker.sv new file mode 100644 index 0000000..145785e --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_fifo_tracker.sv @@ -0,0 +1,100 @@ +// bsg_fifo_tracker +// +// MBT 7/7/16 +// + +`include "bsg_defines.sv" + +module bsg_fifo_tracker #(parameter `BSG_INV_PARAM(els_p ) + , ptr_width_lp = `BSG_SAFE_CLOG2(els_p) + ) + (input clk_i + , input reset_i + + , input enq_i + , input deq_i + + , output [ptr_width_lp-1:0] wptr_r_o + , output [ptr_width_lp-1:0] rptr_r_o + , output [ptr_width_lp-1:0] rptr_n_o + + , output full_o + , output empty_o + ); + + // one read pointer, one write pointer; + logic [ptr_width_lp-1:0] rptr_r, rptr_n, wptr_r; + + assign wptr_r_o = wptr_r; + assign rptr_r_o = rptr_r; + assign rptr_n_o = rptr_n; + + // Used to latch last operation, to determine fifo full or empty + logic enq_r, deq_r; + + // internal signals + logic empty, full, equal_ptrs; + + bsg_circular_ptr #(.slots_p (els_p) + ,.max_add_p(1 ) + ) rptr + ( .clk (clk_i ) + , .reset_i(reset_i) + , .add_i (deq_i ) + , .o (rptr_r ) + , .n_o (rptr_n) + ); + + bsg_circular_ptr #(.slots_p (els_p) + ,.max_add_p(1 ) + ) wptr + ( .clk (clk_i ) + , .reset_i(reset_i) + , .add_i (enq_i ) + , .o (wptr_r ) + , .n_o () + ); + + // registering last operation + // for reset, last op is deque, so + // equal w and r pointers signal empty FIFO + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + begin + enq_r <= 1'b0; + deq_r <= 1'b1; + end + else + begin + // update "last operation" when + // either enque or dequing + if (enq_i | deq_i) + begin + enq_r <= enq_i; + deq_r <= deq_i; + end + end // else: !if(reset_i) + + // if read and write pointers are equal + // empty or fullness is determined by whether + // the last request was a deque or enque. + + // no need to check both enque and deque for each of the + // empty and full signals, since during full or empty state one + // of the enque or deque cannot be asserted (no enque when it is + // not ready and no yumi when no data is valid to be sent out) + // Moreover, other than full or empty state only one of deque or + // enque signals would not make the counters equal + + assign equal_ptrs = (rptr_r == wptr_r); + assign empty = equal_ptrs & deq_r; + assign full = equal_ptrs & enq_r; + + assign full_o = full; + assign empty_o = empty; + +endmodule // bsg_fifo_tracker + +`BSG_ABSTRACT_MODULE(bsg_fifo_tracker) diff --git a/designs/black-parrot/src/basejump_stl/bsg_flatten_2D_array.sv b/designs/black-parrot/src/basejump_stl/bsg_flatten_2D_array.sv new file mode 100644 index 0000000..4de8d6a --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_flatten_2D_array.sv @@ -0,0 +1,18 @@ +`include "bsg_defines.sv" + +module bsg_flatten_2D_array #(parameter `BSG_INV_PARAM( width_p ) + , parameter `BSG_INV_PARAM(items_p )) + (input [width_p-1:0] i [items_p-1:0] + , output [width_p*items_p-1:0] o + ); + + genvar j; + + for (j = 0; j < items_p; j=j+1) + begin + assign o[j*width_p+:width_p] = i[j]; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_flatten_2D_array) diff --git a/designs/black-parrot/src/basejump_stl/bsg_flow_counter.sv b/designs/black-parrot/src/basejump_stl/bsg_flow_counter.sv new file mode 100644 index 0000000..17b54cb --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_flow_counter.sv @@ -0,0 +1,79 @@ +// bsg_flow_counter, would be attached to a module or set of +// modules which have ready-and-valid or ready-then-valid +// (base on the ready_THEN_valid_p parameter) input protocol +// and valid-then-yumi protocol for the output. Based on the +// count_free_p it will count the number of free elements or +// number of existing elements in the connected module. + +`include "bsg_defines.sv" + +module bsg_flow_counter #(parameter `BSG_INV_PARAM(els_p ) + , parameter count_free_p = 0 + , parameter ready_THEN_valid_p = 0 + + //localpara + , parameter ptr_width_lp = + `BSG_WIDTH(els_p) + ) + + ( input clk_i + , input reset_i + + , input v_i + , input ready_param_i + , input yumi_i + + , output [ptr_width_lp-1:0] count_o + ); + +// internal signals +logic enque; + +// In valid-ready protocol both ends assert their signal at the +// beginning of the cycle, and if the sender end finds that receiver +// was not ready it would send it again. So in the receiver side +// valid means enque if it could accept it +if (ready_THEN_valid_p) begin: gen_blk_protocol_select + assign enque = v_i; +end else begin: gen_blk_protocol_select + assign enque = v_i & ready_param_i; +end + +generate + if (count_free_p) begin: gen_blk_0 + // An up-down counter is used for counting free slots. + // it starts with number of elements and that is also + // the max value it can reach. + bsg_counter_up_down #( .max_val_p(els_p) + , .init_val_p(els_p) + , .max_step_p(1) + ) counter + + ( .clk_i(clk_i) + , .reset_i(reset_i) + + , .up_i(yumi_i) + , .down_i(enque) + + , .count_o(count_o) + ); + end else begin: gen_blk_0 + bsg_counter_up_down #( .max_val_p(els_p) + , .init_val_p(0) + , .max_step_p(1) + ) counter + + ( .clk_i(clk_i) + , .reset_i(reset_i) + + , .up_i(enque) + , .down_i(yumi_i) + + , .count_o(count_o) + ); + end +endgenerate + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_flow_counter) diff --git a/designs/black-parrot/src/basejump_stl/bsg_fsb_node_trace_replay.v b/designs/black-parrot/src/basejump_stl/bsg_fsb_node_trace_replay.v new file mode 100644 index 0000000..44a993a --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_fsb_node_trace_replay.v @@ -0,0 +1,251 @@ +`include "bsg_defines.sv" + +// MBT 11/26/2014 +// +// bsg_fsb_node_trace_replay +// +// trace format (see enum below) +// +// +// note: this trace replay module essentially +// could be used to replay communication over +// any latency insensitive channel. later, it +// may make sense to rename it. +// + +module bsg_fsb_node_trace_replay + #(parameter ring_width_p=80 + , parameter rom_addr_width_p=6 + , parameter counter_width_p=`BSG_MIN(ring_width_p,16) + , parameter uptime_p=0 + ) + (input clk_i + , input reset_i + , input en_i + + // input channel + , input v_i + , input [ring_width_p-1:0] data_i + , output logic ready_o + + // output channel + , output logic v_o + , output logic [ring_width_p-1:0] data_o + , input yumi_i + + // connection to rom + // note: asynchronous reads + + , output [rom_addr_width_p-1:0] rom_addr_o + , input [ring_width_p+4-1:0] rom_data_i + + // true outputs + , output logic done_o + , output logic error_o + ); + + initial + begin + $display("## WARNING: bsg_fsb_node_trace_replay will be DEPRECATED soon; please discontinue use (%m)."); + end + + // 0: wait one cycle + // 1: send data + // 2: receive data (and check its value) + // 3: assert done_o; test complete. + // 4: end test; call $finish + // 5: decrement cycle counter; wait for cycle_counter == 0 + // 6: initialized cycle counter with 16 bits + // in theory, we could add branching, etc. + // before we know it, we have a processor =) + + typedef enum logic [3:0] { + eNop=4'd0, + eSend=4'd1, + eReceive=4'd2, + eDone=4'd3, + eFinish=4'd4, + eCycleDec=4'd5, + eCycleInit=4'd6 + } eOp; + + + logic [counter_width_p-1:0] cycle_ctr_r, cycle_ctr_n; + + logic [rom_addr_width_p-1:0] addr_r, addr_n; + logic done_r, done_n; + logic error_r, error_n; + + assign rom_addr_o = addr_r; + assign data_o = rom_data_i[0+:ring_width_p]; + assign done_o = done_r; + assign error_o = error_r; + + always_ff @(posedge clk_i) + begin + if (reset_i) + begin + addr_r <= 0; + done_r <= 0; + error_r <= 0; + cycle_ctr_r <= 16'b1; + end + else + begin + addr_r <= addr_n; + done_r <= done_n; + error_r <= error_n; + cycle_ctr_r <= cycle_ctr_n; + end + end // always_ff @ + + logic [3:0] op; + assign op = rom_data_i[ring_width_p+:4]; + + logic instr_completed; + + assign addr_n = instr_completed ? (addr_r+1'b1) : addr_r; + + // handle outputs + always_comb + begin + // defaults; not sending and not receiving unless done + v_o = 1'b0; + ready_o = done_r; + done_n = done_r; + + if (!done_r & en_i & ~reset_i) + begin + case (op) + eSend: v_o = 1'b1; + eReceive: ready_o = 1'b1; + eDone: done_n = 1'b1; + default: + begin + end + endcase + end + end // always_comb + + // next instruction logic + always_comb + begin + instr_completed = 1'b0; + error_n = error_r; + cycle_ctr_n = cycle_ctr_r; + + if (!done_r & en_i & ~reset_i) + begin + case (op) + eNop: instr_completed = 1'b1; + eSend: + begin + if (yumi_i) + instr_completed = 1'b1; + end + eReceive: + begin + if (v_i) + begin + instr_completed = 1'b1; + if (error_r == 0) + error_n = data_i != data_o; + end + end + eDone: instr_completed = 1'b1; + eFinish: instr_completed = 1'b1; + eCycleDec: + begin + cycle_ctr_n = cycle_ctr_r - 1'b1; + instr_completed = ~(|cycle_ctr_r); + end + eCycleInit: + begin + cycle_ctr_n = rom_data_i[counter_width_p-1:0]; + instr_completed = 1; + end + default: + begin + end + endcase // case (op) + end + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + // non-synthesizeable components + always @(negedge clk_i) + begin + if (instr_completed & ~reset_i & ~done_r) + begin + case(op) + eSend: + begin + string localtime; + if (uptime_p) + begin + int fd; + + fd=$fopen("/proc/uptime","r"); + void'($fscanf(fd,"%s",localtime)); + $fclose(fd); + end + else + localtime = ""; + + $display("### bsg_fsb_node_trace_replay SEND %d'b%b (%m), time=%t uptime=%s", ring_width_p,data_o,$time,localtime); + end + eReceive: + begin + if (data_i !== data_o) + begin + $display("############################################################################"); + $display("### bsg_fsb_node_trace_replay RECEIVE unmatched (%m) "); + $display("### "); + $display("### FAIL (trace mismatch) = %h", data_i); + $display("### expected = %h\n", data_o); + $display("### diff = %h\n", data_o ^ data_i); + $display("############################################################################"); + $finish(); + end + else + begin + $display("### bsg_fsb_node_trace_replay RECEIVE matched %h (%m)", data_o); + end // else: !if(data_i != data_o) + end + eDone: + begin + $display("############################################################################"); + $display("###### bsg_fsb_node_trace_replay DONE done_o=1 (trace finished addr=%x) (%m)",rom_addr_o); + $display("############################################################################"); + end + eFinish: + begin + $display("############################################################################"); + $display("###### bsg_fsb_node_trace_replay FINISH (trace finished; CALLING $finish) (%m)"); + $display("############################################################################"); + $finish; + end + eCycleDec: + begin + $display("### bsg_fsb_node_trace_replay CYCLE DEC cycle_ctr_r = %x (%m)",cycle_ctr_r); + end + eCycleInit: + begin + $display("### bsg_fsb_node_trace_replay CYCLE INIT = %x (%m)",cycle_ctr_n); + end + default: + begin + + end + endcase // case (op) + case (op) + eNop, eSend, eReceive, eDone, eFinish, eCycleDec, eCycleInit: + begin + end + default: $display("### bsg_fsb_node_trace_replay UNKNOWN op %x (%m)\n", op); + endcase // case (op) + end // if (instr_completed & ~reset_i & ~done_r) + end // always @ (negedge clk_i) +`endif + +endmodule diff --git a/designs/black-parrot/src/basejump_stl/bsg_gray_to_binary.sv b/designs/black-parrot/src/basejump_stl/bsg_gray_to_binary.sv new file mode 100644 index 0000000..a6a3c9d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_gray_to_binary.sv @@ -0,0 +1,42 @@ +// MBT 7/25/14 +// +// From "advanced chip design: practical examples in verilog" +// p. 183. +// + +`include "bsg_defines.sv" + +module bsg_gray_to_binary #(parameter `BSG_INV_PARAM(width_p )) + (input [width_p-1:0] gray_i + , output [width_p-1:0] binary_o + ); + + // or alternatively + // the entertaining: + // assign binary_o[width_p-1:0] = ({1'b0, binary_o[width_p-1:1]} ^ gray_i[width_p-1:0]); + +/* + assign binary_o[width_p-1] = gray_i[width_p-1]; + + generate + genvar i; + + for (i = 0; i < width_p-1; i=i+1) + begin + assign binary_o[i] = binary_o[i+1] ^ gray_i[i]; + end + + endgenerate + */ + + // logarithmic depth of the above + + bsg_scan #(.width_p(width_p) + ,.xor_p(1) + ) scan_xor + (.i(gray_i) + ,.o(binary_o)); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_gray_to_binary) diff --git a/designs/black-parrot/src/basejump_stl/bsg_hash_bank.sv b/designs/black-parrot/src/basejump_stl/bsg_hash_bank.sv new file mode 100644 index 0000000..f41a75b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_hash_bank.sv @@ -0,0 +1,297 @@ +// bsg_hash_bank +// +// This module takes a binary address, and a constant number of banks, and then hashes the +// address across the banks efficiently; outputing the bank #, and the index at that bank. +// This is useful for banking memories; or spreading cache coherence directory information +// across multiple directories. Alternatively, it could be viewed as divide and modulo by +// a constant, for certain constants. +// +// Since we support non-power of two banks, some banks will be larger than others. +// The hash function guarantees that the difference in size of the banks is no greater than 1. +// +// Here is what is supported: +// +// Bank counts of 2^n * (2^m-1), where n=0,1,2... and m = 1,2,3,4,5... +// +// i.e., 2,3,4,6=2*3,7,8,12=3*4,14=7*2,15,16,24=3*8,28=4*7,30=15*2,32 +// 1 3 7 15 31 63 127 +// ------------------------ +// 1| 1 3 7 15 31 63 127 +// 2| 2 6 14 30 62 126 254 --> Bank counts of 1,2,3,4,6,7,8,12,14,15,16,24,28,30,31,32 +// 4| 4 12 28 60 124 252 508 +// 8| 8 24 56 120 248 504 .... +// 16|16 48 112 240 496 +// 32|32 96 224 +// 64|64 192 +// +// The function uses the higher-order bits to select the bank number +// to use lower-order bits, you can reverse the bit sequence on input to the module +// using the {<< {i}} operator. +// +// see also the module bsg_hash_bank_reverse, which takes a bank and index +// and produces the original address +// +// TODO: it may make sense to add support for other #'s of banks via +// the Verilog modulo operator; it may be sufficiently efficient for small binary addresses +// +// TODO: evaluate PPA versus yosys and DC modulo operator +// +// TODO: a pathway to support hash functions that are a factor of 2^n+1 seems possible but is only onlined in this code +// see comments for how the math would work. This would support banking of 5,9 and maybe higher. +// +// + +`include "bsg_defines.sv" + +module bsg_hash_bank #(parameter `BSG_INV_PARAM(banks_p) + ,parameter `BSG_INV_PARAM(width_p), + index_width_lp=$clog2((2**width_p+banks_p-1)/banks_p), + lg_banks_lp=`BSG_SAFE_CLOG2(banks_p), debug_lp=0) + (/* input clk,*/ + input [width_p-1:0] i + ,output [lg_banks_lp-1:0] bank_o + ,output [index_width_lp-1:0] index_o + ); + + genvar j; + + + if (banks_p == 1) + begin: hash1 + assign index_o = i; + assign bank_o = 1'b0; + end + else + if (banks_p == 2) + begin: hash2 + assign bank_o = i[width_p-1]; + assign index_o = i[width_p-2:0]; + end + else + if (~banks_p[0]) + begin: hashpow2 + assign bank_o [0] = i[width_p-1]; + bsg_hash_bank #(.banks_p(banks_p >> 1),.width_p(width_p-1)) bhb (/* .clk(clk), */.i(i[width_p-2:0]),.bank_o(bank_o[lg_banks_lp-1:1]),.index_o(index_o)); + end + else + if ((banks_p & (banks_p+1))==0) // test for (2^N)-1 + begin : hash3 + if ((width_p % lg_banks_lp)!=0) + begin : odd + wire _unused; + + bsg_hash_bank #(.banks_p(banks_p),.width_p(width_p+1)) + hf (/* .clk,*/ .i({i,1'b0}),.bank_o(bank_o),.index_o({index_o,_unused})); + end + else + begin : even + localparam frac_width_lp = width_p/lg_banks_lp; + wire [lg_banks_lp-1:0][frac_width_lp-1:0] unzippered; + +// This is the hash function we implement. + +// banks=3 + +// 00 XX XX -> Bank 0, 00 XX XX +// 01 XX XX -> Bank 1, 00 XX XX +// 10 XX XX -> Bank 2, 00 XX XX +// 11 00 XX -> Bank 0, 01 00 XX +// 11 01 XX -> Bank 1, 01 00 XX +// 11 10 XX -> Bank 2, 01 00 XX +// 11 11 00 -> Bank 0, 01 01 00 +// 11 11 01 -> Bank 1, 01 01 00 +// 11 11 10 -> Bank 2, 01 01 00 +// 11 11 11 -> Bank 3, 01 01 01 + +// banks=5 --> partially reuse 2^N-1 = 15 trick +// banks=9 --> partially reuse 2^N-1 = 63 trick +// banks=21 --> partially reuse 2^N-1 = 63 trick +// banks=15 --> partially reuse 2^N-1 = 255 trick +// banks=17 --> partially reuse 2^N-1 = 255 trick +// banks=51 --> " +// banks=85 --> +// banks=73 --> 2^N-1=511 +// banks=11,31,33,93,341 --> 2^N-1=1023 +// banks=23,89->2047 + +// H +// Bank Index +// +// 0000 XXXX XXXX 0 00 XXXX XXXX +// 0001 XXXX XXXX 1 00 XXXX XXXX +// 0010 XXXX XXXX 2 00 XXXX XXXX +// 0011 XXXX XXXX 3 00 XXXX XXXX + +// 0100 XXXX XXXX 4 00 XXXX XXXX +// 0101 XXXX XXXX 0 01 XXXX XXXX +// 0101 XXXX XXXX 0 01 XXXX XXXX +// 0101 XXXX XXXX 0 01 XXXX XXXX +// 0110 XXXX XXXX 1 01 XXXX XXXX +// 0111 XXXX XXXX 2 01 XXXX XXXX + +// 1000 XXXX XXXX 3 01 XXXX XXXX +// 1001 XXXX XXXX 4 01 XXXX XXXX +// 1010 XXXX XXXX 0 10 XXXX XXXX +// 1011 XXXX XXXX 1 10 XXXX XXXX + +// 1100 XXXX XXXX 2 10 XXXX XXXX +// 1101 XXXX XXXX 3 10 XXXX XXXX +// 1110 XXXX XXXX 4 10 XXXX XXXX + +// 1111 0000 XXXX 0 11 0000 XXXX +// 1111 0001 XXXX 1 11 0000 XXXX +// 1111 0010 XXXX 2 11 0000 XXXX +// 1111 0011 XXXX 3 11 0000 XXXX +// 1111 0100 XXXX 4 11 0000 XXXX +// 1111 0101 XXXX 0 11 0001 XXXX +// 1111 0110 XXXX 1 11 0001 XXXX +// 1111 0111 XXXX 2 11 0001 XXXX +// 1111 1000 XXXX 3 11 0001 XXXX +// 1111 1001 XXXX 4 11 0001 XXXX +// 1111 1010 XXXX 0 11 0010 XXXX +// 1111 1011 XXXX 1 11 0010 XXXX +// 1111 1100 XXXX 2 11 0010 XXXX +// 1111 1101 XXXX 3 11 0010 XXXX +// 1111 1110 XXXX 4 11 0010 XXXX +// 1111 1111 XXXX 0 11 0011 XXXX + +// 1111 1111 0000 0 11 0011 0000 +// 1111 1111 0001 1 11 0011 0000 +// 1111 1111 0010 2 11 0011 0000 +// 1111 1111 0011 3 11 0011 0000 +// 1111 1111 0100 4 11 0011 0000 +// 1111 1111 0101 0 11 0011 0001 +// 1111 1111 0110 1 11 0011 0001 +// 1111 1111 0111 2 11 0011 0001 +// 1111 1111 1000 3 11 0011 0001 +// 1111 1111 1001 4 11 0011 0001 +// 1111 1111 1010 0 11 0011 0010 +// 1111 1111 1011 1 11 0011 0010 +// 1111 1111 1100 2 11 0011 0010 +// 1111 1111 1101 3 11 0011 0010 +// 1111 1111 1110 4 11 0011 0010 +// 1111 1111 1111 0 11 0011 0011 +// +// So basically, for conversion: +// 1) replace 1111 with 0011 (base/5). +// 2) for first non-1111 value Y replace with Y/5 +// (this generalizes for normal case of 15 banks --> 15/15 -> 1. +// +// banks=7 +// bank index +// 000 XXX XXX --> 0 0 XXX XXX +// 001 XXX XXX --> 1 0 XXX XXX +// 010 XXX XXX --> 2 0 XXX XXX +// 011 XXX XXX --> 3 0 XXX XXX +// 100 XXX XXX --> 4 0 XXX XXX +// 101 XXX XXX --> 5 0 XXX XXX +// 110 XXX XXX --> 6 0 XXX XXX +// 111 000 XXX --> 0 1 000 XXX +// 111 001 XXX --> 1 1 000 XXX +// ... +// 111 110 XXX --> 6 1 000 XXX +// 111 111 000 --> 0 1 001 000 +// 111 111 001 --> 1 1 001 000 +// .. +// 111 111 110 --> 6 1 001 000 +// 111 111 111 --> 0 1 001 001 + +// Notice the pattern -- if there is a 11 or 111, we skip to the next pair of bits +// to find the bank index. + +// To compute the index, we use a 01 if it is a 11, a 00 if it the pair of +// bits after the last 11, othwerise we use the same bits as the input. + + // for odd numbers of bits; add a zero to the end, invoke even routine, and then drop low bit of the index at the end. +// +// A D (a = add, d=drop) +// 00 XX X 0 -> Bank 0, 00 XX X0 +// 01 XX X 0 -> Bank 1, 00 XX X0 +// 10 XX X 0 -> Bank 2, 00 XX X0 +// 11 00 X 0 -> Bank 0, 01 00 X0 +// 11 01 X 0 -> Bank 1, 01 00 X0 +// 11 10 X 0 -> Bank 2, 01 00 X0 +// 11 11 0 0 -> Bank 0, 01 01 00 +// 11 11 1 0 -> Bank 2, 01 01 00 + + // and tuplets of bank_p-1 consecutive bits + wire [frac_width_lp-1:0] one_one; + + bsg_reduce_segmented #(.segments_p(frac_width_lp),.segment_width_p(lg_banks_lp),.and_p(1'b1)) brs + (.i(i),.o(one_one)); + + bsg_transpose #(.width_p(lg_banks_lp), .els_p(frac_width_lp)) unzip (.i(i),.o(unzippered)); + + wire [frac_width_lp-1:0] one_one_and_scan; + + // and bits from top to bottom, zeroing everything out after first + // zero; this is the mask the determines when 11's end. + + bsg_scan #(.width_p(frac_width_lp),.and_p(1)) scan(.i(one_one),.o(one_one_and_scan)); + + // 111000 + // 111100 + // ------ + // 000100 + + wire [frac_width_lp-1:0] not_one_one_and_scan = ~one_one_and_scan; + wire [frac_width_lp-1:0] shifty; + + if (frac_width_lp > 1) + assign shifty = { 1'b1, one_one_and_scan[frac_width_lp-1:1] }; + else + assign shifty = { 1'b1 }; + + // wire [even_width_lp/2-1:0] border + // = (~one_one_and_scan) & {1'b1, one_one_and_scan >> 1}; + + wire [frac_width_lp-1:0] border = not_one_one_and_scan & shifty; + + // for the top bit of each pair, it should be 0 if it + // is border or one_one_and_scan; otherwise it should be the top bit + // from the original sequence. + + // for the bottom bit of each pair, it should be a 0 if border + // a one if one_one_and_scan, otherwise it should be the bit from the original + // sequence. + + wire [lg_banks_lp-1:0][frac_width_lp-1:0] bits; + + for (j = 1; j < lg_banks_lp; j = j + 1) + begin: rof2 + assign bits[j] = unzippered[j] & ~(border | one_one_and_scan); + end + + assign bits[0] = (one_one_and_scan) | (unzippered[0] & ~one_one_and_scan & ~border); + + wire [width_p-1:0] transpose_lo; + + bsg_transpose #(.els_p(lg_banks_lp), .width_p(frac_width_lp)) zip (.i({bits}),.o(transpose_lo)); + + assign index_o = transpose_lo[index_width_lp-1:0]; + + for (j = 0; j < lg_banks_lp; j = j + 1) + begin: rof1 + // mask out all but border bits and use as the hash index bit + assign bank_o[j] = | (border & unzippered[j]); + end + +/* if (debug_lp) + always @(negedge clk) + begin + $display ("%b -> %b %b %b %b %b %b %b %b %b %b", + i, one_one, one_one_and_scan, not_one_one_and_scan, shifty, border, unzippered[1], + unzippered[0], bits[1], bits[0], index_o); + end + */ + end + end + else + initial + begin + assert(0) else $error("unhandled case, banks_p = ", banks_p); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_hash_bank) diff --git a/designs/black-parrot/src/basejump_stl/bsg_hash_bank_reverse.sv b/designs/black-parrot/src/basejump_stl/bsg_hash_bank_reverse.sv new file mode 100644 index 0000000..134da3b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_hash_bank_reverse.sv @@ -0,0 +1,125 @@ +// bsg_hash_bank_reverse +// +// See paired module bsg_hash_bank. +// This module is the inverse; taking a bank number and an index, and producing the original address. +// + +`include "bsg_defines.sv" + +module bsg_hash_bank_reverse #(parameter `BSG_INV_PARAM(banks_p), parameter `BSG_INV_PARAM(width_p), index_width_lp=$clog2((2**width_p+banks_p-1)/banks_p), lg_banks_lp=`BSG_SAFE_CLOG2(banks_p), debug_lp=0) + (/* input clk,*/ + + input [index_width_lp-1:0] index_i + , input [lg_banks_lp-1:0] bank_i + , output [width_p-1:0] o + ); + + if (banks_p == 1) + begin: hash1 + assign o = index_i; + end + else + if (banks_p == 2) + begin: hash2 + assign o = { bank_i, index_i }; + end + else + if (~banks_p[0]) + begin: hashpow2 + assign o[width_p-1] = bank_i[0]; + bsg_hash_bank_reverse #(.banks_p(banks_p >> 1),.width_p(width_p-1)) bhbr (/* .clk(clk) , */ .index_i(index_i[index_width_lp-1:0]),.bank_i(bank_i[lg_banks_lp-1:1]),.o(o[width_p-2:0])); + end + else + if ((banks_p & (banks_p+1)) == 0) // test for (2^N)-1 + begin : hash3 + if (width_p % lg_banks_lp) + begin : odd + wire _unused; + + bsg_hash_bank_reverse #(.banks_p(banks_p),.width_p(width_p+1)) rhf + ( /* .clk(clk),*/ .index_i({index_i, 1'b0}), .bank_i(bank_i), .o({o[width_p-1:0], _unused})); + + end + else + begin : even + /* This is the hash function we implement. + + Bank Zero, 0 XX XX --> 00 XX XX + Bank One, 0 XX XX --> 01 XX XX + Bank Two, 0 XX XX --> 10 XX XX + Bank Zero, 1 00 XX --> 11 00 XX + Bank One, 1 00 XX --> 11 01 XX + Bank Two, 1 00 XX --> 11 10 XX + Bank Zero, 1 01 00 --> 11 11 00 + Bank One, 1 01 00 --> 11 11 01 + Bank Two, 1 01 00 --> 11 11 10 + Bank Zero, 1 01 01 --> 11 11 11 + + the algorithm is: + + starting from the left; the first 00 you see, substitute the bank number + starting from the left; as long as you see 01, substitute 11. + + */ + + localparam frac_width_lp = width_p/lg_banks_lp; + wire [lg_banks_lp-1:0][frac_width_lp-1:0] unzippered; + wire [width_p-1:0] index_i_ext = (width_p) ' (index_i); // add 0's on + + bsg_transpose #(.width_p(lg_banks_lp), .els_p(frac_width_lp)) unzip (.i(index_i_ext),.o(unzippered)); + + genvar j; + + // and tuplets of lg_bank_lp-1 consecutive 0 bits + wire [frac_width_lp-1:0] zero_pair; + + bsg_reduce_segmented #(.segments_p(frac_width_lp),.segment_width_p(lg_banks_lp),.nor_p(1)) brs + (.i(index_i_ext),.o(zero_pair)); + + wire [frac_width_lp-1:0] zero_pair_or_scan; + + bsg_scan #(.width_p(frac_width_lp),.or_p(1)) scan + (.i(zero_pair),.o(zero_pair_or_scan)); + + // everything that is 0 should be converted to a 11 + // the first 1 should be converted to the bank # + // the following 1's should just take the old bit values. + + wire [frac_width_lp-1:0] first_one; + + if (frac_width_lp > 1) + assign first_one = zero_pair_or_scan & ~{1'b0, zero_pair_or_scan[frac_width_lp-1:1]}; + else + assign first_one = zero_pair_or_scan; + + wire [lg_banks_lp-1:0][frac_width_lp-1:0] bits; + + for (j = 0; j < lg_banks_lp; j=j+1) + begin: rof2 + assign bits[j] = (zero_pair_or_scan & ~first_one & unzippered[j]) | (first_one & { frac_width_lp { bank_i[j] }}) | ~zero_pair_or_scan; + end + + /* if (debug_lp) + begin + always @(negedge clk) + begin + $display ("%b %b -> ZP(%b) ZPS(%b) FO(%b) TB(%b) BB(%b) %b ", + index_i, bank_i, zero_pair, zero_pair_or_scan, first_one, top_bits, bot_bits, o); + end + end + */ + wire [width_p-1:0] transpose_lo; + bsg_transpose #(.els_p(lg_banks_lp), .width_p(frac_width_lp)) zip (.i({bits}),.o(transpose_lo)); + + assign o = transpose_lo[width_p-1:0]; + end + end + else + initial + begin + assert(0) else $error("unhandled case, banks_p = ", banks_p); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_hash_bank_reverse) diff --git a/designs/black-parrot/src/basejump_stl/bsg_idiv_iterative.sv b/designs/black-parrot/src/basejump_stl/bsg_idiv_iterative.sv new file mode 100644 index 0000000..d34fe8d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_idiv_iterative.sv @@ -0,0 +1,262 @@ +//==================================================================== +// bsg_idiv_iterative.sv +// 11/14/2016, shawnless.xie@gmail.com +//==================================================================== +// +// An N-bit integer iterative divider, capable of signed & unsigned division +// Code refactored based on Sam Larser's work +// ------------------------------------------- +// Cycles Operation +// ------------------------------------------- +// 1 latch inputs +// 2 negate divisor (if necessary) +// 3 negate dividend (if necessary) +// 4 shift in msb of the dividend +// 5-37 iterate +// 38 repair remainder (if necessary) +// 39 negate remainder (if necessary) +// 40 negate quotient (if necessary) +// ------------------------------------------- +// +// Schematic: https://docs.google.com/presentation/d/1F7Lam7fMCp-v9K1PsjTvypWHJFFXfqoX6pJrmgf-_JE/ +// +// TODO +// 1. added register to hold the previous operands, if the current operands +// are the same with prevous one, we can output the results instantly. This +// is useful for a RISC ISA, in which only quotient or remainder is need in +// one instruction. +// 2. usging data detection logic to reduce the iteration cycles. +`include "bsg_defines.sv" + +module bsg_idiv_iterative #(parameter width_p=32, parameter bitstack_p=0, parameter bits_per_iter_p = 1) + (input clk_i + ,input reset_i + + ,input v_i //there is a request + ,output ready_and_o //idiv is idle + + ,input [width_p-1: 0] dividend_i + ,input [width_p-1: 0] divisor_i + ,input signed_div_i + + ,output v_o //result is valid + ,output [width_p-1: 0] quotient_o + ,output [width_p-1: 0] remainder_o + ,input yumi_i + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial begin + assert (bits_per_iter_p == 1 || bits_per_iter_p == 2) + else $error("Illegal value for parameters bits_per_iter_p given: (%0d). Legal values are 1 or 2.", bits_per_iter_p); + + assert (bits_per_iter_p == 1 || (bits_per_iter_p == 2 && (width_p % 2 == 0))) + else $error("Illegal value for parameter width_p: (%0d) given bits_per_iter_p: (%0d). Width must be even when resolving 2 bits per iteration", width_p, bits_per_iter_p); + end +`endif + + wire [width_p:0] opA_r; + assign remainder_o = opA_r[width_p-1:0]; + + wire [width_p:0] opC_r; + assign quotient_o = opC_r[width_p-1:0]; + + wire signed_div_r; + wire divisor_msb = signed_div_i & divisor_i[width_p-1]; + wire dividend_msb = signed_div_i & dividend_i[width_p-1]; + + wire latch_signed_div_lo; + bsg_dff_en#(.width_p(1)) req_reg + (.data_i (signed_div_i) + ,.data_o (signed_div_r) + ,.en_i (latch_signed_div_lo) + ,.clk_i(clk_i) + ); + + //if the divisor is zero + wire zero_divisor_li = ~(| opA_r); + + wire [1:0] opA_sel_lo; + wire [width_p:0] opA_mux; + + wire [width_p:0] add1_out, add2_out; + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(2)) muxA + ( .data_i({ {divisor_msb, divisor_i}, add1_out } ) + ,.data_o( opA_mux ) + ,.sel_one_hot_i(opA_sel_lo) + ); + + wire [width_p:0] opB_mux, opC_mux; + wire [bits_per_iter_p + 1:0] opB_sel_lo, opC_sel_lo; + + if (bits_per_iter_p == 2) begin + + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxB + (.data_i( {opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}, {add2_out[width_p-1:0], opC_r[width_p-1]}} ) + ,.data_o( opB_mux ) + ,.sel_one_hot_i(opB_sel_lo) + ); + + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(4)) muxC + (.data_i( {{dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}, {opC_r[width_p-2:0], ~add1_out[width_p], ~add2_out[width_p]}}) + ,.data_o( opC_mux ) + ,.sel_one_hot_i(opC_sel_lo) + ); + + end else begin + + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxB + (.data_i( {opC_r, add1_out, {add1_out[width_p-1:0], opC_r[width_p]}} ) + ,.data_o( opB_mux ) + ,.sel_one_hot_i(opB_sel_lo) + ); + + bsg_mux_one_hot #(.width_p(width_p+1), .els_p(3)) muxC + (.data_i( {{dividend_msb, dividend_i},add1_out, {opC_r[width_p-1:0], ~add1_out[width_p]}} ) + ,.data_o( opC_mux ) + ,.sel_one_hot_i(opC_sel_lo) + ); + + end + + wire opA_ld_lo; + bsg_dff_en#(.width_p(width_p+1)) opA_reg + (.data_i (opA_mux) + ,.data_o (opA_r ) + ,.en_i (opA_ld_lo ) + ,.clk_i(clk_i) + ); + + wire opB_ld_lo; + wire [width_p:0] opB_r; + bsg_dff_en#(.width_p(width_p+1)) opB_reg + (.data_i (opB_mux) + ,.data_o (opB_r ) + ,.en_i (opB_ld_lo ) + ,.clk_i(clk_i) + ); + + wire opC_ld_lo; + bsg_dff_en#(.width_p(width_p+1)) opC_reg + (.data_i (opC_mux) + ,.data_o (opC_r ) + ,.en_i (opC_ld_lo ) + ,.clk_i(clk_i) + ); + + wire opA_inv_lo; + wire opB_inv_lo; + wire opA_clr_lo; + wire opB_clr_lo; + + wire [width_p:0] add1_in0; + wire [width_p:0] add1_in1; + wire [width_p:0] add2_in0; + wire [width_p:0] add2_in1; + + // this logic is sandwiched between bitstacks -- MBT + if (bitstack_p) begin: bs + + wire [width_p:0] opA_xnor; + bsg_xnor#(.width_p(width_p+1)) xnor_opA + (.a_i({(width_p+1){opA_inv_lo}}) + ,.b_i(opA_r) + ,.o (opA_xnor) + ); + + wire [width_p:0] opB_xnor; + bsg_xnor#(.width_p(width_p+1)) xnor_opB + (.a_i({(width_p+1){opB_inv_lo}}) + ,.b_i(opB_r) + ,.o (opB_xnor) + ); + + bsg_nor2 #(.width_p(width_p+1)) nor_opA + ( .a_i( opA_xnor ) + ,.b_i({(width_p+1){~opA_clr_lo}}) + ,.o (add1_in0) + ); + + bsg_nor2 #(.width_p(width_p+1)) nor_opB + ( .a_i( opB_xnor ) + ,.b_i( {(width_p+1){~opB_clr_lo}}) + ,.o (add1_in1) + ); + + if (bits_per_iter_p == 2) begin + bsg_xor#(.width_p(width_p+1)) xor_add1 + (.a_i({(width_p+1){~add1_out[width_p]}}) + ,.b_i(opA_r) + ,.o (add2_in0) + ); + assign add2_in1 = {add1_out[width_p-1:0], opC_r[width_p]}; + end + + end + else begin: nbs + assign add1_in0 = (opA_r ^ {width_p+1{opA_inv_lo}}) & {width_p+1{opA_clr_lo}}; + assign add1_in1 = (opB_r ^ {width_p+1{opB_inv_lo}}) & {width_p+1{opB_clr_lo}}; + + if (bits_per_iter_p == 2) begin + assign add2_in0 = (opA_r ^ {width_p+1{~add1_out[width_p]}}); + assign add2_in1 = {add1_out[width_p-1:0], opC_r[width_p]}; + end + + end + + + wire adder1_cin_lo; + bsg_adder_cin #(.width_p(width_p+1)) adder1 + (.a_i (add1_in0) + ,.b_i (add1_in1) + ,.cin_i(adder1_cin_lo) + ,.o (add1_out) + ); + + if (bits_per_iter_p == 2) begin + wire adder2_cin = ~add1_out[width_p]; + bsg_adder_cin #(.width_p(width_p+1)) adder2 + (.a_i (add2_in0) + ,.b_i (add2_in1) + ,.cin_i(adder2_cin) + ,.o (add2_out) + ); + end + else begin + assign add2_out = '0; + end + + bsg_idiv_iterative_controller #(.width_p(width_p), .bits_per_iter_p(bits_per_iter_p)) control + ( .reset_i (reset_i) + ,.clk_i (clk_i) + + ,.v_i (v_i) + ,.ready_and_o (ready_and_o) + + ,.zero_divisor_i (zero_divisor_li) + ,.signed_div_r_i (signed_div_r) + ,.adder1_result_is_neg_i (add1_out[width_p]) + ,.adder2_result_is_neg_i (add2_out[width_p]) + ,.opA_is_neg_i (opA_r[width_p]) + ,.opC_is_neg_i (opC_r[width_p]) + + ,.opA_sel_o (opA_sel_lo) + ,.opA_ld_o (opA_ld_lo) + ,.opA_inv_o (opA_inv_lo) + ,.opA_clr_l_o (opA_clr_lo) + + ,.opB_sel_o (opB_sel_lo) + ,.opB_ld_o (opB_ld_lo) + ,.opB_inv_o (opB_inv_lo) + ,.opB_clr_l_o (opB_clr_lo) + + ,.opC_sel_o (opC_sel_lo) + ,.opC_ld_o (opC_ld_lo) + + ,.latch_signed_div_o (latch_signed_div_lo) + ,.adder1_cin_o (adder1_cin_lo) + + ,.v_o(v_o) + ,.yumi_i(yumi_i) + ); +endmodule // divide diff --git a/designs/black-parrot/src/basejump_stl/bsg_idiv_iterative_controller.sv b/designs/black-parrot/src/basejump_stl/bsg_idiv_iterative_controller.sv new file mode 100644 index 0000000..ad0e045 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_idiv_iterative_controller.sv @@ -0,0 +1,267 @@ +//==================================================================== +// bsg_idiv_iterative_controller.sv +// 11/14/2016, shawnless.xie@gmail.com +//==================================================================== +// +// The controller of bsg_idiv_iterative module. +// Code refactored based on Sam Larser's work + +`include "bsg_defines.sv" + +module bsg_idiv_iterative_controller #(parameter width_p=32, parameter bits_per_iter_p = 1) + (input clk_i + ,input reset_i + + ,input v_i + ,output ready_and_o + + ,input zero_divisor_i + ,input signed_div_r_i + ,input adder1_result_is_neg_i + ,input adder2_result_is_neg_i + ,input opA_is_neg_i + ,input opC_is_neg_i + + ,output logic [1:0] opA_sel_o + ,output logic opA_ld_o + ,output logic opA_inv_o + ,output logic opA_clr_l_o + + ,output logic [bits_per_iter_p + 1:0] opB_sel_o + ,output logic opB_ld_o + ,output logic opB_inv_o + ,output logic opB_clr_l_o + + ,output logic [bits_per_iter_p + 1:0] opC_sel_o + ,output logic opC_ld_o + + ,output logic latch_signed_div_o + ,output logic adder1_cin_o + + ,output logic v_o + ,input yumi_i + ); + + logic q_neg_r; + logic r_neg_r; + logic neg_ld; + logic add1_neg_last_r, add2_neg_last_r; + + typedef enum logic[5:0] + {WAIT, NEG0, NEG1, SHIFT, + CALC, + REPAIR, REMAIN, + QUOT,DONE } idiv_ctrl_stat; + idiv_ctrl_stat state, next_state; + + always @(posedge clk_i) begin + add1_neg_last_r <= adder1_result_is_neg_i; + add2_neg_last_r <= adder2_result_is_neg_i; + + if (neg_ld) begin + // the quotient is negated if the signs of the operands differ + q_neg_r <= (opA_is_neg_i ^ opC_is_neg_i) & signed_div_r_i; + + // the remainder is negated if the dividend is negative + r_neg_r <= opC_is_neg_i & signed_div_r_i; + end + end + + logic [`BSG_WIDTH(width_p/bits_per_iter_p)-1:0] calc_cnt; + wire calc_up_li = (state == CALC) && (calc_cnt < width_p/bits_per_iter_p); + wire calc_done = (calc_cnt == width_p/bits_per_iter_p); + bsg_counter_clear_up#(.max_val_p(width_p/bits_per_iter_p) + ,.init_val_p(0) + ,.disable_overflow_warning_p(1)) calc_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + // We rely on natural overflow + ,.clear_i(calc_done) + ,.up_i(calc_up_li) + + ,.count_o(calc_cnt) + ); + +// synopsys sync_set_reset "reset_i" + always @(posedge clk_i) begin + if (reset_i) state <= WAIT; + else state <= next_state; + end + + always_comb begin + opA_sel_o = 2'b00; + opA_ld_o = 1'b0; + + if (bits_per_iter_p == 2) + opA_inv_o = !add2_neg_last_r; + else + opA_inv_o = !add1_neg_last_r; + + opA_clr_l_o = 1'b1; + + if (bits_per_iter_p == 2) + opB_sel_o = 4'b0001; + else + opB_sel_o = 3'b001; + + opB_ld_o = 1'b0; + opB_inv_o = 1'b0; + opB_clr_l_o = 1'b1; + opC_sel_o = 3'b001; + opC_ld_o = 1'b0; + + if (bits_per_iter_p == 2) + adder1_cin_o = !add2_neg_last_r; + else + adder1_cin_o = !add1_neg_last_r; + + neg_ld = 1'b0; + latch_signed_div_o = 1'b0; + next_state = WAIT; + + case (state) + + WAIT: begin + if (v_i) begin + opA_ld_o = 1'b1; + opC_ld_o = 1'b1; + latch_signed_div_o = 1'b1; + next_state = NEG0; + opA_sel_o = 2'b10; + + if (bits_per_iter_p == 2) + opC_sel_o = 4'b1000; + else + opC_sel_o = 3'b100; + end + + end + + NEG0: begin + next_state = (opC_is_neg_i & signed_div_r_i) ? NEG1 : SHIFT; + opA_sel_o = 2'b01; + opA_inv_o = 1'b1; + opB_clr_l_o = 1'b0; + opB_ld_o = 1'b1; + opC_ld_o = 1'b0; + neg_ld = 1'b1; + adder1_cin_o = 1'b1; + opA_ld_o = opA_is_neg_i & signed_div_r_i; + + if (bits_per_iter_p == 2) + opB_sel_o = 4'b1000; + else + opB_sel_o = 3'b100; + end + + NEG1: begin + next_state = SHIFT; + opA_clr_l_o = 1'b0; + opB_inv_o = 1'b1; + opB_ld_o = 1'b0; + opC_ld_o = 1'b1; + adder1_cin_o = 1'b1; + + if (bits_per_iter_p == 2) + opC_sel_o = 4'b0100; + else + opC_sel_o = 3'b010; + end + + SHIFT: begin + next_state = CALC; + opB_ld_o = 1'b1; + opC_ld_o = 1'b1; + opA_clr_l_o = 1'b0; + opB_clr_l_o = 1'b0; + adder1_cin_o = 1'b0; + + if (bits_per_iter_p == 2) begin + opC_sel_o = 4'b0010; + opB_sel_o = 4'b0010; + end else begin + opC_sel_o = 3'b001; + opB_sel_o = 3'b001; + end + end + + CALC: begin + opB_ld_o = 1'b1; + opC_ld_o = 1'b1; + if (bits_per_iter_p == 2) begin + opB_sel_o = calc_done ? 4'b0100 : 4'b0001; + opC_sel_o = calc_done ? 4'b0010 : 4'b0001; + if (calc_cnt == 0) begin + opA_inv_o = !add1_neg_last_r; + adder1_cin_o = !add1_neg_last_r; + end + end else + opB_sel_o = calc_done ? 3'b010 : 3'b001; + + if (calc_done) begin + if (adder1_result_is_neg_i) next_state = REPAIR; + else next_state = REMAIN; + end else + next_state = CALC; + end + + REPAIR: begin + next_state = REMAIN; + opA_inv_o = 1'b0; + opB_ld_o = 1'b1; + opC_ld_o = 1'b0; + adder1_cin_o = 1'b0; + + if (bits_per_iter_p == 2) + opB_sel_o = 4'b0100; + else + opB_sel_o = 3'b010; + end + + REMAIN: begin + next_state = (zero_divisor_i | !q_neg_r) ? DONE: QUOT; + opA_sel_o = 2'b01; + opA_ld_o = 1'b1; + opA_clr_l_o = 1'b0; + opB_ld_o = 1'b1; + opC_ld_o = 1'b0; + opB_inv_o = r_neg_r; + adder1_cin_o = r_neg_r; + + if (bits_per_iter_p == 2) + opB_sel_o = 4'b1000; + else + opB_sel_o = 3'b100; + end + + QUOT: begin + next_state = DONE; + opA_clr_l_o = 1'b0; + opB_inv_o = 1'b1; + opB_ld_o = 1'b0; + opC_ld_o = 1'b1; + adder1_cin_o = 1'b1; + + if (bits_per_iter_p == 2) + opC_sel_o = 4'b0100; + else + opC_sel_o = 3'b010; + end + + DONE:begin + if( yumi_i ) next_state = WAIT; + else next_state = DONE; + + opA_ld_o = 1'b0; + opB_ld_o = 1'b0; + opC_ld_o = 1'b0; + end + + endcase + end + + assign ready_and_o = ( state == WAIT ); + assign v_o = ( state == DONE ); + +endmodule // divide_control diff --git a/designs/black-parrot/src/basejump_stl/bsg_imul_iterative.sv b/designs/black-parrot/src/basejump_stl/bsg_imul_iterative.sv new file mode 100644 index 0000000..67d0fb5 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_imul_iterative.sv @@ -0,0 +1,245 @@ +//==================================================================== +// bsg_imul_iterative.sv +// 11/15/2016, shawnless.xie@gmail.com +//==================================================================== +// +// An 32bit integer iterative multiplier, capable of signed & unsigned division +// a3 a2 a1 a0 +// b3 b2 b1 b0 +// ------------------------------------------------------------------ +// |  a3b0 a2b0 a1b0 a0b0 +// a3b1 | a2b1 a1b1 a0b1 +// a3b2 a2b2 | a1b2 a0b2 +// a3b3 a2b3 a1b3 | a0b3 +// ------------------------------------------------------------------ +// High Part | Low Part +// +// 1. for LOW part output: +// def imul( a, b ): +// result = 0 +// for i in range(32): +// if b & 0x1 == 1: +// result += a +// a = a << 1 +// b = b >> 1 +// return result +// +// 2. for HIGH part output +// def imul( a, b ): +// result = 0 +// for i in range(31): +// if b & 0x1 == 1: +// result = ( {1'b0,result} + {1'b0,a}) >> 1 +// else: +// result = result >> 1 +// +// b = b >> 1 +// return result +// 3. for negtive high part output, we have to check if the low part of the +// abs(result) are all zeros. If it is all zero, we have to add 1 to the +// neg high part, otherwise we onely have to neg the high part +// -(4'b10_00) = ~(4'b10 00) + 1 = 4'b01_11 + 1= 4'b10_00 +// -(4'b10_10) = ~(4'b10_10) + 1 = 4'b01_01 + 1= 4'b01_10 +// +// We add a one bit register to track whether the shifted out LSB of the result +// are all zeros +// +`include "bsg_defines.sv" + +module bsg_imul_iterative #( width_p = 32) + (input clk_i + ,input reset_i + + ,input v_i //there is a request + ,output ready_and_o //idiv is idle + + ,input [width_p-1: 0] opA_i + ,input signed_opA_i + ,input [width_p-1: 0] opB_i + ,input signed_opB_i + //needs the high part result or low part result + ,input gets_high_part_i + + ,output v_o //result is valid + ,output [width_p-1: 0] result_o + ,input yumi_i + ); + + localparam lg_width_lp = `BSG_SAFE_CLOG2( width_p + 1); + +/////////////////////////////////////////////////////////////////////////////// +// counter for the shift operation + logic[lg_width_lp-1:0] shift_counter_r; + logic gets_high_part_r; + + wire shift_counter_full = gets_high_part_r + ? ( shift_counter_r == (width_p-1) ) + : ( shift_counter_r == width_p ); +/////////////////////////////////////////////////////////////////////////////// +// The state machine + typedef enum logic[2:0] {IDLE, NEG_A, NEG_B, CALC, NEG_R, DONE } imul_ctrl_stat; + imul_ctrl_stat curr_state_r, next_state; + + // state machine register + always_ff@( posedge clk_i ) begin + if( reset_i ) curr_state_r <= IDLE; + else curr_state_r <= next_state; + end + + //determing next state + always_comb begin + unique case(curr_state_r ) + IDLE: begin + if( v_i ) next_state = NEG_A; + else next_state = IDLE; + end + + NEG_A: next_state = NEG_B; + NEG_B: next_state = CALC ; + + CALC: begin + if( !shift_counter_full ) next_state = CALC; + else next_state = NEG_R; + end + + NEG_R: next_state = DONE; + + DONE: begin + if( yumi_i ) next_state = IDLE; + else next_state = DONE; + end + + default: next_state = IDLE; + endcase + end + +/////////////////////////////////////////////////////////////////////////////// +// update the shift_counter_r + always_ff@( posedge clk_i ) begin + if ( reset_i ) shift_counter_r <= 'b0; //reset + else if( curr_state_r != CALC && next_state == CALC ) + shift_counter_r <= 'b0; //new request + else if( curr_state_r == CALC) + shift_counter_r <= shift_counter_r + 1; + end + +/////////////////////////////////////////////////////////////////////////////// +// the computation logic + logic [width_p-1:0] opA_r, opB_r, result_r; + logic [width_p-1:0] adder_a, adder_b; + logic [width_p :0] adder_result,shifted_adder_result; + + // -opA_r = ~opA_r + 1, reunsing the adder here + assign adder_a = (curr_state_r == NEG_A) ? ~opA_r : + (curr_state_r == NEG_B) ? ~opB_r : + (curr_state_r == NEG_R) ? ~result_r : result_r; + + wire adder_neg_op = (curr_state_r == NEG_A + || curr_state_r == NEG_B + || curr_state_r == NEG_R); + + assign adder_b = adder_neg_op ? { {(width_p-1){1'b0}}, 1'b1} + : opA_r ; + + assign adder_result = {1'b0, adder_a} + {1'b0, adder_b}; + + assign shifted_adder_result = adder_result >> 1; + +/////////////////////////////////////////////////////////////////////////////// +// control register update logic + + wire latch_input = v_i & ready_and_o; + logic signed_opA_r, signed_opB_r, need_neg_result_r; + + wire signed_opA = signed_opA_i & opA_i[width_p-1]; + wire signed_opB = signed_opB_i & opB_i[width_p-1]; + + always_ff@(posedge clk_i ) begin + if( reset_i ) signed_opA_r <= 1'b0; + else if( latch_input ) signed_opA_r <= signed_opA; + end + + always_ff@(posedge clk_i ) begin + if( reset_i ) signed_opB_r <= 1'b0; + else if( latch_input ) signed_opB_r <= signed_opB; + end + + always_ff@(posedge clk_i ) begin + if( reset_i ) need_neg_result_r <= 1'b0; + else if( latch_input ) need_neg_result_r <= signed_opA ^ signed_opB ; + end + + always_ff@(posedge clk_i ) begin + if( reset_i ) gets_high_part_r <= 1'b0; + else if( latch_input ) gets_high_part_r <= gets_high_part_i; + end + +/////////////////////////////////////////////////////////////////////////////// +// operands update logic + always_ff@(posedge clk_i) begin + if( reset_i ) opA_r <= 'b0; + else if( latch_input ) opA_r <= opA_i; + + //opA only shifts when we want low part result + else if(curr_state_r == CALC && (!gets_high_part_r ) ) + opA_r <= opA_r << 1 ; + + else if(curr_state_r == NEG_A && signed_opA_r) //get the abs(opA) + opA_r <= adder_result[width_p-1:0]; + end + + always_ff@(posedge clk_i) begin + if( reset_i ) opB_r <= 'b0; + else if( latch_input ) opB_r <= opB_i; + else if(curr_state_r == CALC) opB_r <= opB_r >> 1 ; + + else if(curr_state_r == NEG_B && signed_opB_r) //get the abs(opB) + opB_r <= adder_result[width_p-1:0]; + end + +/////////////////////////////////////////////////////////////////////////////// +// track the LSB of the result which is shifted out for high part computation + + wire shifted_lsb = opB_r[0] ? adder_result[0] : result_r[0]; + + logic all_sh_lsb_zero_r; + always_ff@(posedge clk_i ) begin + if( reset_i ) all_sh_lsb_zero_r <= 1'b0; + else if( latch_input ) all_sh_lsb_zero_r <= 1'b1; + else if( curr_state_r == CALC ) all_sh_lsb_zero_r <= all_sh_lsb_zero_r + & (~shifted_lsb); + end + +/////////////////////////////////////////////////////////////////////////////// +// update the result register +// synopsys sync_set_reset "reset_i, latch_input" + always_ff@(posedge clk_i) begin + if( reset_i ) result_r <= 'b0; + else if( latch_input ) result_r <= 'b0; + + else if(curr_state_r == NEG_R && need_neg_result_r) //get the signed result + //1. High part Neg in case Low part are not all zeros + if( gets_high_part_r && !all_sh_lsb_zero_r ) //No cin, just reverse + result_r <= ~result_r; + //1. Low part Neg + //2. High part Neg in case Low part are all zeros, ~(result_r) +1 + else + result_r <= adder_result[width_p-1:0]; + + else if(curr_state_r == CALC && opB_r[0]) begin //get the accumulated result + if( gets_high_part_r ) result_r <= shifted_adder_result[width_p-1:0]; + else result_r <= adder_result [width_p-1:0]; + end + else if(curr_state_r == CALC && !opB_r[0])begin //No addition + if( gets_high_part_r ) result_r <= result_r >>1 ; + end + end + + +/////////////////////////////////////////////////////////////////////////////// +// the output logic + + assign ready_and_o = ( curr_state_r == IDLE ); + assign result_o = result_r; + assign v_o = ( curr_state_r == DONE ); +endmodule diff --git a/designs/black-parrot/src/basejump_stl/bsg_launch_sync_sync.sv b/designs/black-parrot/src/basejump_stl/bsg_launch_sync_sync.sv new file mode 100644 index 0000000..a5b38a5 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_launch_sync_sync.sv @@ -0,0 +1,352 @@ +// MBT 7/24/2014 +// +// This is a launch/synchronization complex. +// The launch flop prevents combinational glitching. +// The two sync flops reduce probability of metastability. +// See MBT's note on async design and CDC. +// +// The three flops should be don't touched in synopsys +// and abutted in physical design to reduce chances of metastability. +// +// Use of reset is optional; it can be used to hold a known value during reset +// if for instance, the value is coming off chip. +// + +// the code is structured this way because synopsys's +// support for hierarchical placement groups appears +// not to work for parameterized modules. +// so we must have a non-parameterized module +// in order to abut the three registers, which +// have two different clocks. +// + +// ASYNC RESET: iclk cannot toggle at deassertion of reset + +`include "bsg_defines.sv" + +`ifndef rp_group + `define rp_group(x) + `define rp_place(x) + `define rp_endgroup(x) + `define rp_fill(x) + `define rp_array_dir(up) +`endif + +`define bsg_launch_sync_sync_unit(EDGE,bits) \ + \ +module bsg_launch_sync_sync_``EDGE``_``bits``_unit \ + (input iclk_i \ + , input iclk_reset_i \ + , input oclk_i \ + , input [bits-1:0] iclk_data_i \ + , output [bits-1:0] iclk_data_o \ + , output [bits-1:0] oclk_data_o \ + ); \ + \ + `rp_group (blss_bank) \ + `rp_place (hier blss_launch_1 0 0) \ + `rp_place (hier blss_1 1 0) \ + `rp_place (hier blss_2 2 0) \ + `rp_endgroup (blss_bank) \ + \ + logic [bits-1:0] bsg_SYNC_LNCH_r; \ + assign iclk_data_o = bsg_SYNC_LNCH_r; \ + \ + always_ff @(EDGE iclk_i) \ + begin \ + `rp_group(blss_launch_1) \ + `rp_fill(0 0 UX) \ + `rp_array_dir(up) \ + `rp_endgroup(blss_launch_1) \ + \ + if (iclk_reset_i) \ + bsg_SYNC_LNCH_r <= {bits{1'b0}}; \ + else \ + bsg_SYNC_LNCH_r <= iclk_data_i; \ + end \ + \ + logic [bits-1:0] bsg_SYNC_1_r; \ + logic [bits-1:0] bsg_SYNC_2_r; \ + \ + assign oclk_data_o = bsg_SYNC_2_r; \ + \ + always_ff @(posedge oclk_i) \ + begin \ + `rp_group(blss_1) \ + `rp_fill(0 0 UX) \ + `rp_array_dir(up) \ + `rp_endgroup(blss_1) \ + bsg_SYNC_1_r <= bsg_SYNC_LNCH_r; \ + end \ + \ + always_ff @(posedge oclk_i) \ + begin \ + `rp_group(blss_2) \ + `rp_fill(0 0 UX) \ + `rp_array_dir(up) \ + `rp_endgroup(blss_2) \ + bsg_SYNC_2_r <= bsg_SYNC_1_r; \ + end \ +endmodule + +`define bsg_launch_sync_sync_async_reset_unit(EDGE,bits) \ + \ +module bsg_launch_sync_sync_async_reset_``EDGE``_``bits``_unit \ + (input iclk_i \ + , input iclk_reset_i \ + , input oclk_i \ + , input [bits-1:0] iclk_data_i \ + , output [bits-1:0] iclk_data_o \ + , output [bits-1:0] oclk_data_o \ + ); \ + \ + `rp_group (blss_bank) \ + `rp_place (hier blss_launch_1 0 0) \ + `rp_place (hier blss_1 1 0) \ + `rp_place (hier blss_2 2 0) \ + `rp_endgroup (blss_bank) \ + \ + logic [bits-1:0] bsg_SYNC_LNCH_r; \ + assign iclk_data_o = bsg_SYNC_LNCH_r; \ + \ + always_ff @(EDGE iclk_i or posedge iclk_reset_i) \ + begin \ + `rp_group(blss_launch_1) \ + `rp_fill(0 0 UX) \ + `rp_array_dir(up) \ + `rp_endgroup(blss_launch_1) \ + \ + if (iclk_reset_i) \ + bsg_SYNC_LNCH_r <= {bits{1'b0}}; \ + else \ + bsg_SYNC_LNCH_r <= iclk_data_i; \ + end \ + \ + logic [bits-1:0] bsg_SYNC_1_r; \ + logic [bits-1:0] bsg_SYNC_2_r; \ + \ + assign oclk_data_o = bsg_SYNC_2_r; \ + \ + always_ff @(posedge oclk_i or posedge iclk_reset_i) \ + begin \ + `rp_group(blss_1) \ + `rp_fill(0 0 UX) \ + `rp_array_dir(up) \ + `rp_endgroup(blss_1) \ + if (iclk_reset_i) \ + bsg_SYNC_1_r <= {bits{1'b0}}; \ + else \ + bsg_SYNC_1_r <= bsg_SYNC_LNCH_r; \ + end \ + \ + always_ff @(posedge oclk_i or posedge iclk_reset_i) \ + begin \ + `rp_group(blss_2) \ + `rp_fill(0 0 UX) \ + `rp_array_dir(up) \ + `rp_endgroup(blss_2) \ + if (iclk_reset_i) \ + bsg_SYNC_2_r <= {bits{1'b0}}; \ + else \ + bsg_SYNC_2_r <= bsg_SYNC_1_r; \ + end \ +endmodule + +// bsg_launch_sync_sync_posedge_1_unit +`bsg_launch_sync_sync_unit(posedge,1) +`bsg_launch_sync_sync_unit(posedge,2) +`bsg_launch_sync_sync_unit(posedge,3) +`bsg_launch_sync_sync_unit(posedge,4) +`bsg_launch_sync_sync_unit(posedge,5) +`bsg_launch_sync_sync_unit(posedge,6) +`bsg_launch_sync_sync_unit(posedge,7) +`bsg_launch_sync_sync_unit(posedge,8) + +// bsg_launch_sync_sync_negedge_1_unit +`bsg_launch_sync_sync_unit(negedge,1) +`bsg_launch_sync_sync_unit(negedge,2) +`bsg_launch_sync_sync_unit(negedge,3) +`bsg_launch_sync_sync_unit(negedge,4) +`bsg_launch_sync_sync_unit(negedge,5) +`bsg_launch_sync_sync_unit(negedge,6) +`bsg_launch_sync_sync_unit(negedge,7) +`bsg_launch_sync_sync_unit(negedge,8) + +// bsg_launch_sync_sync_async_reset_posedge_1_unit +`bsg_launch_sync_sync_async_reset_unit(posedge,1) +`bsg_launch_sync_sync_async_reset_unit(posedge,2) +`bsg_launch_sync_sync_async_reset_unit(posedge,3) +`bsg_launch_sync_sync_async_reset_unit(posedge,4) +`bsg_launch_sync_sync_async_reset_unit(posedge,5) +`bsg_launch_sync_sync_async_reset_unit(posedge,6) +`bsg_launch_sync_sync_async_reset_unit(posedge,7) +`bsg_launch_sync_sync_async_reset_unit(posedge,8) + +// bsg_launch_sync_sync_async_reset_negedge_1_unit +`bsg_launch_sync_sync_async_reset_unit(negedge,1) +`bsg_launch_sync_sync_async_reset_unit(negedge,2) +`bsg_launch_sync_sync_async_reset_unit(negedge,3) +`bsg_launch_sync_sync_async_reset_unit(negedge,4) +`bsg_launch_sync_sync_async_reset_unit(negedge,5) +`bsg_launch_sync_sync_async_reset_unit(negedge,6) +`bsg_launch_sync_sync_async_reset_unit(negedge,7) +`bsg_launch_sync_sync_async_reset_unit(negedge,8) + +// warning: if you make this != 8, you need +// to modify other parts of this code + +`define blss_max_block 8 + +// handle trailer bits +`define blss_if_clause(EDGE,num) if ((width_p % `blss_max_block) == num) begin: z \ + bsg_launch_sync_sync_``EDGE``_``num``_unit blss \ + (.iclk_i \ + ,.iclk_reset_i \ + ,.oclk_i \ + ,.iclk_data_i(iclk_data_i[width_p-1-:num]) \ + ,.iclk_data_o(iclk_data_o[width_p-1-:num]) \ + ,.oclk_data_o(oclk_data_o[width_p-1-:num]) \ + ); end + +`define blssar_if_clause(EDGE,num) if ((width_p % `blss_max_block) == num) begin: z \ + bsg_launch_sync_sync_async_reset_``EDGE``_``num``_unit blss \ + (.iclk_i \ + ,.iclk_reset_i \ + ,.oclk_i \ + ,.iclk_data_i(iclk_data_i[width_p-1-:num]) \ + ,.iclk_data_o(iclk_data_o[width_p-1-:num]) \ + ,.oclk_data_o(oclk_data_o[width_p-1-:num]) \ + ); end + +module bsg_launch_sync_sync #(parameter `BSG_INV_PARAM(width_p) + , parameter use_negedge_for_launch_p = 0 + , parameter use_async_reset_p = 0) + (input iclk_i + , input iclk_reset_i + , input oclk_i + , input [width_p-1:0] iclk_data_i + , output [width_p-1:0] iclk_data_o // after launch flop + , output [width_p-1:0] oclk_data_o // after sync flops + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + +/* initial + begin + $display("%m: instantiating blss of size %d",width_p); + end + */ +`ifndef VERILATOR + // The comparison to z makes verilator think that iclk_reset_i is a + // tri-state top-level (unsupported in Verilator v4.036) + initial assert (iclk_reset_i !== 'z) + else + begin + $error("%m iclk_reset should be connected"); + $finish(); + end +`endif +`endif + + genvar i; + + if (use_async_reset_p == 0) begin: sync + + if (use_negedge_for_launch_p) + begin: n + for (i = 0; i < (width_p/`blss_max_block); i = i + 1) + begin : maxb + bsg_launch_sync_sync_negedge_8_unit blss + (.iclk_i + ,.iclk_reset_i + ,.oclk_i + ,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block]) + ,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block]) + ,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block]) + ); + end + + `blss_if_clause(negedge,1) else + `blss_if_clause(negedge,2) else + `blss_if_clause(negedge,3) else + `blss_if_clause(negedge,4) else + `blss_if_clause(negedge,5) else + `blss_if_clause(negedge,6) else + `blss_if_clause(negedge,7) + end + else + begin: p + for (i = 0; i < (width_p/`blss_max_block); i = i + 1) + begin : maxb + bsg_launch_sync_sync_posedge_8_unit blss + (.iclk_i + ,.iclk_reset_i + ,.oclk_i + ,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block]) + ,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block]) + ,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block]) + ); + end + + `blss_if_clause(posedge,1) else + `blss_if_clause(posedge,2) else + `blss_if_clause(posedge,3) else + `blss_if_clause(posedge,4) else + `blss_if_clause(posedge,5) else + `blss_if_clause(posedge,6) else + `blss_if_clause(posedge,7) + end + + end + else begin: async + + if (use_negedge_for_launch_p) + begin: n + for (i = 0; i < (width_p/`blss_max_block); i = i + 1) + begin : maxb + bsg_launch_sync_sync_async_reset_negedge_8_unit blss + (.iclk_i + ,.iclk_reset_i + ,.oclk_i + ,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block]) + ,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block]) + ,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block]) + ); + end + + `blssar_if_clause(negedge,1) else + `blssar_if_clause(negedge,2) else + `blssar_if_clause(negedge,3) else + `blssar_if_clause(negedge,4) else + `blssar_if_clause(negedge,5) else + `blssar_if_clause(negedge,6) else + `blssar_if_clause(negedge,7) + end + else + begin: p + for (i = 0; i < (width_p/`blss_max_block); i = i + 1) + begin : maxb + bsg_launch_sync_sync_async_reset_posedge_8_unit blss + (.iclk_i + ,.iclk_reset_i + ,.oclk_i + ,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block]) + ,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block]) + ,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block]) + ); + end + + `blssar_if_clause(posedge,1) else + `blssar_if_clause(posedge,2) else + `blssar_if_clause(posedge,3) else + `blssar_if_clause(posedge,4) else + `blssar_if_clause(posedge,5) else + `blssar_if_clause(posedge,6) else + `blssar_if_clause(posedge,7) + end + + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_launch_sync_sync) diff --git a/designs/black-parrot/src/basejump_stl/bsg_lfsr.sv b/designs/black-parrot/src/basejump_stl/bsg_lfsr.sv new file mode 100644 index 0000000..4afcd7c --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_lfsr.sv @@ -0,0 +1,58 @@ +// note XOR mask starts at bit 0; which may +// be shifted from mathematician's notation. + +`include "bsg_defines.sv" + +module bsg_lfsr #(parameter `BSG_INV_PARAM(width_p) + , init_val_p = 1 // an initial value of zero is typically the null point for LFSR's. + , xor_mask_p = 0) + (input clk + , input reset_i + , input yumi_i + , output logic [width_p-1:0] o + ); + + logic [width_p-1:0] o_r, o_n, xor_mask; + + assign o = o_r; + + // auto mask value + if (xor_mask_p == 0) + begin : automask + // fixme fill this in: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf + case (width_p) + 32: + assign xor_mask = (1 << 31) | (1 << 29) | (1 << 26) | (1 << 25); + 60: + assign xor_mask = (1 << 59) | (1 << 58); + 64: + assign xor_mask = (1 << 63) | (1 << 62) | (1 << 60) | (1 << 59); + + default: + initial assert(width_p==-1) + else + begin + $display("unhandled default mask for width %d in bsg_lfsr",width_p); $finish(); + end + endcase // case (width_p) + end + else + begin: fi + assign xor_mask = xor_mask_p; + end + + always @(posedge clk) + begin + if (reset_i) + o_r <= (width_p) ' (init_val_p); + else if (yumi_i) + o_r <= o_n; + end + + assign o_n = (o_r >> 1) ^ ({width_p {o_r[0]}} & xor_mask); + + +endmodule // bsg_lfsr + +`BSG_ABSTRACT_MODULE(bsg_lfsr) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_locking_arb_fixed.sv b/designs/black-parrot/src/basejump_stl/bsg_locking_arb_fixed.sv new file mode 100644 index 0000000..7119a59 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_locking_arb_fixed.sv @@ -0,0 +1,42 @@ +`include "bsg_defines.sv" + +module bsg_locking_arb_fixed #( parameter `BSG_INV_PARAM(inputs_p) + , parameter lo_to_hi_p=0 + ) + ( input clk_i + , input ready_then_i + + // to have continuous throughput, you will need to unlock on the same cycle + // as the last word of a packet going through + , input unlock_i + + , input [inputs_p-1:0] reqs_i + , output logic [inputs_p-1:0] grants_o + ); + + wire [inputs_p-1:0] not_req_mask_r, req_mask_r; + + bsg_dff_reset_en #( .width_p(inputs_p) ) + req_words_reg + ( .clk_i ( clk_i ) + , .reset_i( unlock_i ) + // lock in a request mask, if the current request mask is "everybody" + // and somebody was granted their request. + , .en_i ( (&req_mask_r) & (|grants_o) ) + , .data_i ( ~grants_o ) + , .data_o ( not_req_mask_r ) + ); + + assign req_mask_r = ~not_req_mask_r; + + bsg_arb_fixed #( .inputs_p(inputs_p), .lo_to_hi_p(lo_to_hi_p) ) + fixed_arb + ( .ready_then_i ( ready_then_i ) + , .reqs_i ( reqs_i & req_mask_r ) + , .grants_o( grants_o ) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_locking_arb_fixed) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_lru_pseudo_tree_backup.sv b/designs/black-parrot/src/basejump_stl/bsg_lru_pseudo_tree_backup.sv new file mode 100644 index 0000000..bc0b037 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_lru_pseudo_tree_backup.sv @@ -0,0 +1,82 @@ +/** + * bsg_lru_pseudo_tree_backup.sv + * + * tree pseudo LRU backup finder. + * + * Given the bit vector of disabled ways, it will tell + * you bit-mask and data to modify the original LRU bits to obtain + * the backup LRU. + * + * The algorithm to find backup_LRU is: + * start from the root of the LRU tree, and traverse down the tree in the + * direction of the LRU bits, if there is at least one unlocked way in that + * direction. If not, take the opposite direction. + * + * + * ==== Example ============================================== + * + * rank=0 [0] + * 0 + * / \ + * rank=1 [1] [2] + * 1 0 + * / \ / \ + * rank=2 [3] [4] [5] [6] + * 1 0 1 1 + * / \ / \ / \ / \ + * way w0 w1 w2 w3 w4 w5 w6 w7 + * + * + * Let say LRU bits were 7'b110_1010 so that LRU way is w2. + * If the disabled ways are {w2}, then backup_LRU = w3. + * If the disabled are {w2,w3}, then backup_LRU = w1 + * If the disabled are {w0,w1,w2,w3}, the backup_LRU = w5. + * + * ============================================================ + * + * @author tommy + * + * + */ + + + +`include "bsg_defines.sv" + +module bsg_lru_pseudo_tree_backup + #(parameter `BSG_INV_PARAM(ways_p) + , parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p) + ) + ( + input [ways_p-1:0] disabled_ways_i + , output logic [`BSG_SAFE_MINUS(ways_p, 2):0] modify_mask_o + , output logic [`BSG_SAFE_MINUS(ways_p, 2):0] modify_data_o + ); + + // If direct-mapped there is no meaning to backup LRU + if (ways_p == 1) begin: no_lru + assign modify_mask_o = 1'b1; + assign modify_data_o = 1'b0; + end + else begin: lru + // backup LRU logic + // i = rank + for (genvar i = 0; i < lg_ways_lp; i++) begin + + logic [(2**(i+1))-1:0] and_reduce; + + // j = bucket + for (genvar j = 0; j < (2**(i+1)); j++) + assign and_reduce[j] = &disabled_ways_i[(ways_p/(2**(i+1)))*j+:(ways_p/(2**(i+1)))]; + + // k = start index in LRU bits + for (genvar k = 0; k < (2**(i+1))/2; k++) begin + assign modify_data_o[(2**i)-1+k] = and_reduce[2*k]; + assign modify_mask_o[(2**i)-1+k] = |and_reduce[2*k+:2]; + end + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_lru_pseudo_tree_backup) diff --git a/designs/black-parrot/src/basejump_stl/bsg_lru_pseudo_tree_decode.sv b/designs/black-parrot/src/basejump_stl/bsg_lru_pseudo_tree_decode.sv new file mode 100644 index 0000000..ae77f7c --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_lru_pseudo_tree_decode.sv @@ -0,0 +1,51 @@ +/** + * Name: + * bsg_lru_pseudo_tree_decode.sv + * + * Description: + * Pseudo-Tree-LRU decode unit. + * Given input referred way_id, generates data and mask that updates + * the pseudo-LRU tree. Data and mask are chosen in a way that referred way_id is + * no longer the LRU way. The mask and data signals can be given to a + * bitmaskable memory to update the corresponding LRU bits. + */ + +`include "bsg_defines.sv" + +module bsg_lru_pseudo_tree_decode + #(parameter `BSG_INV_PARAM(ways_p) + ,localparam lg_ways_lp = `BSG_SAFE_CLOG2(ways_p) + ) + (input [lg_ways_lp-1:0] way_id_i + , output logic [`BSG_SAFE_MINUS(ways_p, 2):0] data_o + , output logic [`BSG_SAFE_MINUS(ways_p, 2):0] mask_o + ); + + genvar i; + generate + if (ways_p == 1) begin: no_lru + assign mask_o[0] = 1'b1; + assign data_o[0] = 1'b0; + end + else begin: lru + for(i=0; i 256) + $display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)" + ,width_p,els_p,read_write_same_addr_p,harden_p); + end + + always_ff @(negedge w_clk_i) + if (w_v_i===1'b1) + begin + assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || (w_addr_i < els_p) || (els_p <= 1)) + else $error("Invalid address %x to %m of size %x (w_reset_i=%b, w_v_i=%b)\n", w_addr_i, els_p, w_reset_i, w_v_i); + assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || !(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p)) + else $error("%m: Attempt to read and write same address %x (w_v_i = %b, w_reset_i = %b)",w_addr_i,w_v_i,w_reset_i); + end + +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_mem_1r1w) diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_one_hot.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_one_hot.sv new file mode 100644 index 0000000..6f39462 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_one_hot.sv @@ -0,0 +1,76 @@ +// MBT 11/9/2014 +// DWP 5/9/2020 +// +// 1 read-port, 1 write-port ram with a onehot address scheme +// +// reads are asynchronous +// + +`include "bsg_defines.sv" + +module bsg_mem_1r1w_one_hot #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + + , parameter safe_els_lp=`BSG_MAX(els_p,1) + ) + (input w_clk_i + // Currently unused + , input w_reset_i + + // one or zero-hot + , input [safe_els_lp-1:0] w_v_i + , input [width_p-1:0] w_data_i + + // one or zero-hot + , input [safe_els_lp-1:0] r_v_i + , output logic [width_p-1:0] r_data_o + ); + + logic [safe_els_lp-1:0][width_p-1:0] data_r; + + wire unused0 = w_reset_i; + + for (genvar i = 0; i < els_p; i++) + begin : mem_array + bsg_dff_en + #(.width_p(width_p)) + mem_reg + (.clk_i(w_clk_i) + ,.en_i(w_v_i[i]) + ,.data_i(w_data_i) + ,.data_o(data_r[i]) + ); + end + + bsg_mux_one_hot + #(.width_p(width_p) + ,.els_p(safe_els_lp) + ) + one_hot_sel + (.data_i(data_r) + ,.sel_one_hot_i(r_v_i) + ,.data_o(r_data_o) + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + initial + begin + if (width_p*els_p >= 64) + $display("## %L: instantiating width_p=%d, els_p=%d (%m)" + ,width_p,els_p); + end + + always_ff @(negedge w_clk_i) + begin + assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || $countones(w_v_i) <= 1) + else $error("Invalid write address %b to %m is not onehot (w_reset_i=%b)\n", w_v_i, w_reset_i); + assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || $countones(r_v_i) <= 1) + else $error("Invalid read address %b to %m is not onehot (w_reset_i=%b)\n", r_v_i, w_reset_i); + end + +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_one_hot) diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_sync.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_sync.sv new file mode 100644 index 0000000..b95013d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_sync.sv @@ -0,0 +1,101 @@ +// MBT 7/7/2016 +// +// 1 read-port, 1 write-port ram +// +// reads are synchronous +// +// although we could merge this with normal bsg_mem_1r1w +// and select with a parameter, we do not do this because +// it's typically a very big change to the instantiating code +// to move to/from sync/async, and we want to reflect this. +// + +`include "bsg_defines.sv" + +module bsg_mem_1r1w_sync #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter read_write_same_addr_p=0 // specifically write_then_read_p + , parameter latch_last_read_p=0 + , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) + , parameter harden_p=0 + , parameter disable_collision_warning_p=0 + , parameter enable_clock_gating_p=0 + , parameter verbose_if_synth_p=1 + ) + (input clk_i + , input reset_i + + , input w_v_i + , input [addr_width_lp-1:0] w_addr_i + , input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i + + // currently unused + , input r_v_i + , input [addr_width_lp-1:0] r_addr_i + + , output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o + ); + + wire clk_lo; + + if (enable_clock_gating_p) + begin + bsg_clkgate_optional icg + (.clk_i( clk_i ) + ,.en_i( w_v_i | r_v_i ) + ,.bypass_i( 1'b0 ) + ,.gated_clock_o( clk_lo ) + ); + end + else + begin + assign clk_lo = clk_i; + end + + bsg_mem_1r1w_sync_synth + #(.width_p(width_p) + ,.els_p(els_p) + ,.read_write_same_addr_p(read_write_same_addr_p) + ,.latch_last_read_p(latch_last_read_p) + ,.verbose_p(verbose_if_synth_p) // disables reprinting out a masked synth ram + // that has been split into many synth rams + ) synth + (.clk_i( clk_lo ) + ,.reset_i + ,.w_v_i + ,.w_addr_i + ,.w_data_i + ,.r_v_i + ,.r_addr_i + ,.r_data_o + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + begin + // we warn if els_p >= 16 because it is a good candidate for hardening + // and we warn for width_p >= 128 because this starts to add up to some real memory + if ((els_p >= 16) || (width_p >= 128) || (width_p*els_p > 256)) + $display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p); + + if (disable_collision_warning_p) + $display("## %L: disable_collision_warning_p is set; you should not have this on unless you have broken code. fix it!\n"); + end + + always_ff @(negedge clk_lo) + if (w_v_i) + begin + assert ((reset_i === 'X) || (reset_i === 1'b1) || ((32 ' (w_addr_i)) < els_p) || (els_p <= 1)) + else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p); + + assert ((reset_i === 'X) || (reset_i === 1'b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p)) + else + begin + $error("X'ing matched read address %x (%m)",r_addr_i); + end + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync) diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_sync_synth.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_sync_synth.sv new file mode 100644 index 0000000..a12b808 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_sync_synth.sv @@ -0,0 +1,126 @@ +// MBT 7/7/2016 +// +// 1 read-port, 1 write-port ram +// +// reads are synchronous +// +// although we could merge this with normal bsg_mem_1r1w +// and select with a parameter, we do not do this because +// it's typically a very big change to the instantiating code +// to move to/from sync/async, and we want to reflect this. +// +// NOTE: Users of BaseJump STL should not instantiate this module directly +// they should use bsg_mem_1r1w_sync. + +`include "bsg_defines.sv" + +module bsg_mem_1r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter read_write_same_addr_p=0 + , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) + , parameter latch_last_read_p=0 + , parameter verbose_p=1 + ) + (input clk_i + , input reset_i + + , input w_v_i + , input [addr_width_lp-1:0] w_addr_i + , input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i + + // currently unused + , input r_v_i + , input [addr_width_lp-1:0] r_addr_i + + , output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o + ); + + wire unused = reset_i; + + if (width_p == 0 || els_p == 0) + begin: z + wire unused0 = &{clk_i, w_v_i, w_addr_i, r_v_i, r_addr_i}; + assign r_data_o = '0; + end + else + begin: nz + + logic [width_p-1:0] mem [els_p-1:0]; + logic read_en; + logic [width_p-1:0] data_out; + + // this treats the ram as an array of registers for which the + // read addr is latched on the clock, the write + // is done on the clock edge, and actually multiplexing + // of the registers for reading is done after the clock edge. + + // logically, this means that reads happen in time after + // the writes, and "simultaneous" reads and writes to the + // register file are allowed -- IF read_write_same_addr is set. + + // note that this behavior is generally incompatible with + // hardened 1r1w rams, so it's better not to take advantage + // of it if not necessary + + // we explicitly 'X out the read address if valid is not set + // to avoid accidental use of data when the valid signal was not + // asserted. without this, the output of the register file would + // "auto-update" based on new writes to the ram, a spooky behavior + // that would never correspond to that of a hardened ram. + + logic [addr_width_lp-1:0] r_addr_r; + wire [addr_width_lp-1:0] r_addr_li = (els_p > 1) ? r_addr_i:'0; + wire [addr_width_lp-1:0] w_addr_li = (els_p > 1) ? w_addr_i:'0; + + assign read_en = r_v_i; + assign data_out = mem[r_addr_r]; + + always_ff @(posedge clk_i) + if (r_v_i) + r_addr_r <= r_addr_li; + else + r_addr_r <= 'X; + + if (latch_last_read_p) + begin: llr + logic read_en_r; + + bsg_dff #( + .width_p(1) + ) read_en_dff ( + .clk_i(clk_i) + ,.data_i(read_en) + ,.data_o(read_en_r) + ); + + bsg_dff_en_bypass #( + .width_p(width_p) + ) dff_bypass ( + .clk_i(clk_i) + ,.en_i(read_en_r) + ,.data_i(data_out) + ,.data_o(r_data_o) + ); + end + else + begin: no_llr + assign r_data_o = data_out; + end + + always_ff @(posedge clk_i) + if (w_v_i) + mem[w_addr_li] <= w_data_i; + + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + begin + if (verbose_p) + $display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p); + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_synth) \ No newline at end of file diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_synth.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_synth.sv new file mode 100644 index 0000000..c7c5266 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1r1w_synth.sv @@ -0,0 +1,59 @@ +// MBT +// +// 1 read-port, 1 write-port ram +// +// reads are asynchronous +// +// for synthesizable internal version, we omit assertions +// these should be placed in the outer wrapper +// + +`include "bsg_defines.sv" + +module bsg_mem_1r1w_synth #(parameter `BSG_INV_PARAM(width_p) + ,parameter `BSG_INV_PARAM(els_p) + ,parameter read_write_same_addr_p=0 + ,parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)) +( + input w_clk_i + ,input w_reset_i + + ,input w_v_i + ,input [addr_width_lp-1:0] w_addr_i + ,input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i + + // currently unused + ,input r_v_i + ,input [addr_width_lp-1:0] r_addr_i + + ,output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o +); + + wire unused0 = w_reset_i; + wire unused1 = r_v_i; + + if (width_p == 0 || els_p == 0) + begin: z + wire unused2 = &{w_clk_i, w_addr_i, w_data_i, r_addr_i}; + assign r_data_o = '0; + end + else + begin: nz + + logic [width_p-1:0] mem [els_p-1:0]; + + wire [addr_width_lp-1:0] r_addr_li = (els_p > 0) ? r_addr_i:'0; + wire [addr_width_lp-1:0] w_addr_li = (els_p > 0) ? w_addr_i:'0; + + // this implementation ignores the r_v_i + assign r_data_o = mem[r_addr_li]; + + always_ff @(posedge w_clk_i) begin + if (w_v_i) begin + mem[w_addr_li] <= w_data_i; + end + end + end +endmodule + +`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_synth) diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync.sv new file mode 100644 index 0000000..5fbf4fc --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync.sv @@ -0,0 +1,59 @@ +// MBT 11/9/2014 +// +// Synchronous 1-port ram. +// Only one read or one write may be done per cycle. +// + +`include "bsg_defines.sv" + +module bsg_mem_1rw_sync #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter latch_last_read_p=0 + , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) + , parameter enable_clock_gating_p=0 + , parameter verbose_if_synth_p=1 + ) + (input clk_i + , input reset_i + , input [`BSG_SAFE_MINUS(width_p, 1):0] data_i + , input [addr_width_lp-1:0] addr_i + , input v_i + , input w_i + , output logic [`BSG_SAFE_MINUS(width_p, 1):0] data_o + ); + + wire clk_lo; + + if (enable_clock_gating_p) + begin + bsg_clkgate_optional icg + (.clk_i( clk_i ) + ,.en_i( v_i ) + ,.bypass_i( 1'b0 ) + ,.gated_clock_o( clk_lo ) + ); + end + else + begin + assign clk_lo = clk_i; + end + + bsg_mem_1rw_sync_synth + #(.width_p(width_p) + ,.els_p(els_p) + ,.latch_last_read_p(latch_last_read_p) + ,.verbose_p(verbose_if_synth_p) // disables reprinting out a masked synth ram + // that has been split into many synth rams + ) synth + (.clk_i( clk_lo ) + ,.reset_i + ,.data_i + ,.addr_i + ,.v_i + ,.w_i + ,.data_o + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync) diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_bit.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_bit.sv new file mode 100644 index 0000000..eaa2726 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_bit.sv @@ -0,0 +1,70 @@ +// MBT 11/9/2014 +// +// Synchronous 1-port ram. +// Only one read or one write may be done per cycle. + +`include "bsg_defines.sv" + +module bsg_mem_1rw_sync_mask_write_bit #( + parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter latch_last_read_p=0 + , parameter enable_clock_gating_p=0 + , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) +) (input clk_i + , input reset_i + , input [`BSG_SAFE_MINUS(width_p, 1):0] data_i + , input [addr_width_lp-1:0] addr_i + , input v_i + , input [`BSG_SAFE_MINUS(width_p, 1):0] w_mask_i + , input w_i + , output [`BSG_SAFE_MINUS(width_p, 1):0] data_o +); + + wire clk_lo; + + if (enable_clock_gating_p) + begin + bsg_clkgate_optional icg + (.clk_i( clk_i ) + ,.en_i( v_i ) + ,.bypass_i( 1'b0 ) + ,.gated_clock_o( clk_lo ) + ); + end + else + begin + assign clk_lo = clk_i; + end + + bsg_mem_1rw_sync_mask_write_bit_synth + #(.width_p(width_p) + ,.els_p(els_p) + ,.latch_last_read_p(latch_last_read_p) + ) synth + (.clk_i (clk_lo) + ,.reset_i + ,.data_i + ,.addr_i + ,.v_i + ,.w_mask_i + ,.w_i + ,.data_o + ); + + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @(negedge clk_lo) + if (((els_p > 1) && (v_i === 1))) + assert (((reset_i === 'X) || (reset_i === 1'b1) || (els_p <= 1) || (addr_i < els_p))) + else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", addr_i, els_p, reset_i, v_i, clk_lo); + initial + begin + $display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p); + end +`endif + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit) diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_bit_synth.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_bit_synth.sv new file mode 100644 index 0000000..56e173a --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_bit_synth.sv @@ -0,0 +1,117 @@ +// MBT 11/9/2014 +// +// Synchronous 1-port ram. +// Only one read or one write may be done per cycle. +// +// NOTE: Users of BaseJump STL should not instantiate this module directly +// they should use bsg_mem_1rw_sync_mask_write_bit. +// + +`include "bsg_defines.sv" + +module bsg_mem_1rw_sync_mask_write_bit_synth + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter latch_last_read_p=0 + , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) + ) + (input clk_i + , input reset_i + , input [`BSG_SAFE_MINUS(width_p, 1):0] data_i + , input [addr_width_lp-1:0] addr_i + , input v_i + , input [`BSG_SAFE_MINUS(width_p, 1):0] w_mask_i + , input w_i + , output logic [`BSG_SAFE_MINUS(width_p, 1):0] data_o + ); + + wire unused = reset_i; + + if (width_p == 0 || els_p == 0) + begin: z + wire unused0 = &{clk_i, data_i, addr_i, v_i, w_mask_i, w_i}; + assign data_o = '0; + end + else + begin: nz + + logic [addr_width_lp-1:0] addr_r; + logic [width_p-1:0] mem [els_p-1:0]; + logic read_en; + + wire [addr_width_lp-1:0] addr_li = (els_p>1) ? addr_i:'0; + + assign read_en = v_i & ~w_i; + + always_ff @(posedge clk_i) + if (read_en) + addr_r <= addr_li; + else + addr_r <= 'X; + + logic [width_p-1:0] data_out; + + assign data_out = mem[addr_r]; + + if (latch_last_read_p) + begin: llr + logic read_en_r; + + bsg_dff #( + .width_p(1) + ) read_en_dff ( + .clk_i(clk_i) + ,.data_i(read_en) + ,.data_o(read_en_r) + ); + + bsg_dff_en_bypass #( + .width_p(width_p) + ) dff_bypass ( + .clk_i(clk_i) + ,.en_i(read_en_r) + ,.data_i(data_out) + ,.data_o(data_o) + ); + end + else + begin: no_llr + assign data_o = data_out; + end + + + +// The Verilator and non-Verilator models are functionally equivalent. However, Verilator +// cannot handle an array of non-blocking assignments in a for loop. It would be nice to +// see if these two models synthesize the same, because we can then reduce to the Verilator +// model and avoid double maintenence. One could also add this feature to Verilator... +// (Identified in Verilator 4.011) +`ifdef VERILATOR + logic [width_p-1:0] data_n; + + for (genvar i = 0; i < width_p; i++) + begin : rof1 + assign data_n[i] = w_mask_i[i] ? data_i[i] : mem[addr_li][i]; + end // rof1 + + always_ff @(posedge clk_i) + if (v_i & w_i) + mem[addr_li] <= data_n; + +`else + +// this code does not map correctly with Xilinx Ultrascale FPGAs +// in Vivado, substitute this file with hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv + +`BSG_VIVADO_SYNTH_FAILS + + always_ff @(posedge clk_i) + if (v_i & w_i) + for (integer i = 0; i < width_p; i=i+1) + if (w_mask_i[i]) + mem[addr_li][i] <= data_i[i]; +`endif + end +endmodule + +`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit_synth) diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_byte.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_byte.sv new file mode 100644 index 0000000..d878ef4 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_byte.sv @@ -0,0 +1,69 @@ +`include "bsg_defines.sv" + +module bsg_mem_1rw_sync_mask_write_byte #(parameter `BSG_INV_PARAM(els_p) + ,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p) + + ,parameter `BSG_INV_PARAM(data_width_p ) + ,parameter latch_last_read_p=0 + ,parameter write_mask_width_lp = data_width_p>>3 + ,parameter enable_clock_gating_p=0 + ) + ( input clk_i + ,input reset_i + + ,input v_i + ,input w_i + + ,input [addr_width_lp-1:0] addr_i + ,input [`BSG_SAFE_MINUS(data_width_p, 1):0] data_i + // for each bit set in the mask, a byte is written + ,input [`BSG_SAFE_MINUS(write_mask_width_lp, 1):0] write_mask_i + + ,output logic [`BSG_SAFE_MINUS(data_width_p, 1):0] data_o + ); + + wire clk_lo; + + if (enable_clock_gating_p) + begin + bsg_clkgate_optional icg + (.clk_i( clk_i ) + ,.en_i( v_i ) + ,.bypass_i( 1'b0 ) + ,.gated_clock_o( clk_lo ) + ); + end + else + begin + assign clk_lo = clk_i; + end + + bsg_mem_1rw_sync_mask_write_byte_synth + #(.els_p(els_p), .data_width_p(data_width_p), .latch_last_read_p(latch_last_read_p)) + synth + (.clk_i(clk_lo) + ,.reset_i + ,.v_i + ,.w_i + ,.addr_i + ,.data_i + ,.write_mask_i + ,.data_o + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + + always_comb + assert (data_width_p % 8 == 0) + else $error("data width should be a multiple of 8 for byte masking"); + + initial + begin + $display("## %L: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p); + end + +`endif + + +endmodule +`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte) diff --git a/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_byte_synth.sv b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_byte_synth.sv new file mode 100644 index 0000000..ace904b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_mem_1rw_sync_mask_write_byte_synth.sv @@ -0,0 +1,59 @@ +// NOTE: Users of BaseJump STL should not instantiate this module directly +// they should use bsg_mem_1r1w_sync_mask_write_byte. + +`include "bsg_defines.sv" + +module bsg_mem_1rw_sync_mask_write_byte_synth + #(parameter `BSG_INV_PARAM(els_p) + , parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p) + , parameter latch_last_read_p=0 + + , parameter `BSG_INV_PARAM(data_width_p ) + , parameter write_mask_width_lp = data_width_p>>3 + ) + ( input clk_i + ,input reset_i + + ,input v_i + ,input w_i + + ,input [addr_width_lp-1:0] addr_i + ,input [`BSG_SAFE_MINUS(data_width_p, 1):0] data_i + // for each bit set in the mask, a byte is written + ,input [`BSG_SAFE_MINUS(write_mask_width_lp, 1):0] write_mask_i + + ,output [`BSG_SAFE_MINUS(data_width_p, 1):0] data_o + ); + + genvar i; + + if (data_width_p == 0 || els_p == 0) + begin: z + wire unused0 = &{clk_i, reset_i, v_i, w_i, addr_i, data_i, write_mask_i}; + assign data_o = '0; + end + else + begin: nz + + for(i=0; ivalid +`define bsg_ready_then_link_sif_width(in_data_width) ((in_data_width)+2) + +// aka valid->ready +`define bsg_then_ready_link_sif_width(in_data_width) ((in_data_width)+2) + +`define declare_bsg_ready_and_link_sif_s(in_data_width,in_struct_name) \ + typedef struct packed { \ + logic v; \ + logic ready_and_rev; \ + logic [in_data_width-1:0] data; \ + } in_struct_name + +`define declare_bsg_ready_then_link_sif_s(in_data_width,in_struct_name) \ + typedef struct packed { \ + logic v; \ + logic ready_then_rev; \ + logic [in_data_width-1:0] data; \ + } in_struct_name + +`define declare_bsg_then_ready_link_sif_s(in_data_width,in_struct_name)\ + typedef struct packed { \ + logic v; \ + logic then_ready_rev; \ + logic [in_data_width-1:0] data; \ + } in_struct_name + +`define bsg_ready_and_link_sif_s_cast(link_i, link_o, link_i_cast, link_o_cast) \ + assign link_i_cast = link_i; \ + assign link_o = link_o_cast // no semicolon + +/******************* bsg wormhole packet definition ******************/ + +`define bsg_wormhole_packet_width(reserved_width, x_cord_width, y_cord_width, len_width, data_width) \ + (reserved_width+x_cord_width+y_cord_width+len_width+data_width) + +`define declare_bsg_wormhole_packet_s(reserved_width, x_cord_width, y_cord_width, len_width, data_width, in_struct_name) \ + typedef struct packed { \ + logic [data_width-1:0] data; \ + logic [reserved_width-1:0] reserved; \ + logic [len_width-1:0] len; \ + logic [y_cord_width-1:0] y_cord; \ + logic [x_cord_width-1:0] x_cord; \ + } in_struct_name + +/******************* bsg wormhole header flit definition ******************/ + +`define declare_bsg_header_flit_no_reserved_s(width, x_cord_width, y_cord_width, len_width, in_struct_name) \ + typedef struct packed { \ + logic [width-x_cord_width-y_cord_width-len_width-1:0] data_and_reserved; \ + logic [len_width-1:0] len; \ + logic [y_cord_width-1:0] y_cord; \ + logic [x_cord_width-1:0] x_cord; \ + } in_struct_name + +`define declare_bsg_header_flit_s(width, reserved_width, x_cord_width, y_cord_width, len_width, in_struct_name) \ + typedef struct packed { \ + logic [width-reserved_width-x_cord_width-y_cord_width-len_width-1:0] data; \ + logic [reserved_width-1:0] reserved; \ + logic [len_width-1:0] len; \ + logic [y_cord_width-1:0] y_cord; \ + logic [x_cord_width-1:0] x_cord; \ + } in_struct_name + +`define declare_bsg_channel_tunnel_header_flit_s(width, reserved_width, x_cord_width, y_cord_width, len_width, in_struct_name) \ + typedef struct packed { \ + logic [reserved_width-1:0] reserved; \ + logic [width-reserved_width-x_cord_width-y_cord_width-len_width-1:0] data; \ + logic [len_width-1:0] len; \ + logic [y_cord_width-1:0] y_cord; \ + logic [x_cord_width-1:0] x_cord; \ + } in_struct_name + + `endif // BSG_NOC_LINKS_VH diff --git a/designs/black-parrot/src/basejump_stl/bsg_noc_pkg.sv b/designs/black-parrot/src/basejump_stl/bsg_noc_pkg.sv new file mode 100644 index 0000000..253f5f6 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_noc_pkg.sv @@ -0,0 +1,8 @@ + +// direction type +package bsg_noc_pkg; + // Explictly sizing enum values (P=3'd0, not P=0) is necessary per Verilator 4.015 + // https://www.veripool.org/issues/1442-Verilator-Enum-values-without-explicit-widths-are-considered-unsized + typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; +endpackage + diff --git a/designs/black-parrot/src/basejump_stl/bsg_noc_repeater_node.sv b/designs/black-parrot/src/basejump_stl/bsg_noc_repeater_node.sv new file mode 100644 index 0000000..c7e872d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_noc_repeater_node.sv @@ -0,0 +1,74 @@ +// +// This module instantiates num_nodes_p two-element-fifos in chains +// It supports multiple bsg_noc_links in parallel +// +// Insert this module into long routings on chip, which can become critical path +// +// Node that side_A_reset_i signal shoule be close to side A +// If reset happens to be close to side B, please swap side A and side B connection, +// since side A and side B are symmetric, functionality will not be affected. +// + +`include "bsg_defines.sv" +`include "bsg_noc_links.svh" + +module bsg_noc_repeater_node + +#(parameter `BSG_INV_PARAM(width_p ) +, parameter bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(width_p) +) + +( input clk_i +, input reset_i + +, input [bsg_ready_and_link_sif_width_lp-1:0] side_A_links_i +, output [bsg_ready_and_link_sif_width_lp-1:0] side_A_links_o + +, input [bsg_ready_and_link_sif_width_lp-1:0] side_B_links_i +, output [bsg_ready_and_link_sif_width_lp-1:0] side_B_links_o +); + + // declare the bsg_ready_and_link_sif_s struct + `declare_bsg_ready_and_link_sif_s(width_p, bsg_ready_and_link_sif_s); + + // noc links + bsg_ready_and_link_sif_s links_A_cast_i, links_B_cast_i; + bsg_ready_and_link_sif_s links_A_cast_o, links_B_cast_o; + + assign links_A_cast_i = side_A_links_i; + assign links_B_cast_i = side_B_links_i; + + assign side_A_links_o = links_A_cast_o; + assign side_B_links_o = links_B_cast_o; + + bsg_two_fifo #(.width_p(width_p)) + A_to_B + (.clk_i ( clk_i ) + ,.reset_i ( reset_i ) + + ,.v_i ( links_A_cast_i.v ) + ,.data_i ( links_A_cast_i.data ) + ,.ready_param_o ( links_A_cast_o.ready_and_rev ) + + ,.v_o ( links_B_cast_o.v ) + ,.data_o ( links_B_cast_o.data ) + ,.yumi_i ( links_B_cast_i.ready_and_rev & links_B_cast_o.v ) + ); + + bsg_two_fifo #(.width_p(width_p)) + B_to_A + (.clk_i ( clk_i ) + ,.reset_i ( reset_i ) + + ,.v_i ( links_B_cast_i.v ) + ,.data_i ( links_B_cast_i.data ) + ,.ready_param_o ( links_B_cast_o.ready_and_rev ) + + ,.v_o ( links_A_cast_o.v ) + ,.data_o ( links_A_cast_o.data ) + ,.yumi_i ( links_A_cast_i.ready_and_rev & links_A_cast_o.v ) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_noc_repeater_node) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_axi_mem.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_axi_mem.sv new file mode 100644 index 0000000..fa76b14 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_axi_mem.sv @@ -0,0 +1,395 @@ +/** + * bsg_nonsynth_axi_mem.sv + */ + +`include "bsg_defines.sv" + +module bsg_nonsynth_axi_mem + import bsg_axi_pkg::*; + #(parameter `BSG_INV_PARAM(axi_id_width_p) + , parameter `BSG_INV_PARAM(axi_addr_width_p) + , parameter `BSG_INV_PARAM(axi_data_width_p) + , parameter `BSG_INV_PARAM(axi_len_width_p) + , parameter `BSG_INV_PARAM(mem_els_p) + , parameter init_data_p = 32'hdead_beef // 32 bits + , parameter rd_delay_p = 0 + , parameter wr_delay_p = 0 + + , parameter lg_mem_els_lp=`BSG_SAFE_CLOG2(mem_els_p) + , parameter axi_strb_width_lp=(axi_data_width_p>>3) + ) + ( + input clk_i + , input reset_i + + , input [axi_id_width_p-1:0] axi_awid_i + , input [axi_addr_width_p-1:0] axi_awaddr_i + , input [axi_len_width_p-1:0] axi_awlen_i + , input [1:0] axi_awburst_i + , input axi_awvalid_i + , output logic axi_awready_o + + , input [axi_data_width_p-1:0] axi_wdata_i + , input [axi_strb_width_lp-1:0] axi_wstrb_i + , input axi_wlast_i + , input axi_wvalid_i + , output logic axi_wready_o + + , output logic [axi_id_width_p-1:0] axi_bid_o + , output logic [1:0] axi_bresp_o + , output logic axi_bvalid_o + , input axi_bready_i + + , input [axi_id_width_p-1:0] axi_arid_i + , input [axi_addr_width_p-1:0] axi_araddr_i + , input [axi_len_width_p-1:0] axi_arlen_i + , input [1:0] axi_arburst_i + , input axi_arvalid_i + , output logic axi_arready_o + + , output logic [axi_id_width_p-1:0] axi_rid_o + , output logic [axi_data_width_p-1:0] axi_rdata_o + , output logic [1:0] axi_rresp_o + , output logic axi_rlast_o + , output logic axi_rvalid_o + , input axi_rready_i + ); + + logic [axi_data_width_p-1:0] ram [mem_els_p-1:0]; + + // write channel + // + typedef enum logic [1:0] { + WR_RESET, + WR_WAIT_ADDR, + WR_WAIT_DATA, + WR_RESP + } wr_state_e; + + wr_state_e wr_state_r, wr_state_n; + logic [axi_id_width_p-1:0] awid_r, awid_n; + logic [axi_addr_width_p-1:0] awaddr_lo, awaddr_r, awaddr_n; + logic [axi_len_width_p-1:0] wr_burst_r, wr_burst_n; + logic [1:0] awburst_r, awburst_n; + logic [axi_len_width_p-1:0] awlen_r, awlen_n; + + logic [lg_mem_els_lp-1:0] wr_ram_idx; + assign wr_ram_idx = awaddr_lo[$clog2(axi_data_width_p>>3)+:lg_mem_els_lp]; + + wire [axi_addr_width_p-1:0] awaddr_bytes_in_burst = (axi_data_width_p>>3) * (awlen_r+1); + wire [axi_addr_width_p-1:0] awaddr_wrap_boundary = (awaddr_r/awaddr_bytes_in_burst)*awaddr_bytes_in_burst; + wire [axi_addr_width_p-1:0] awaddr_wrap_upper = awaddr_wrap_boundary + awaddr_bytes_in_burst; + wire [axi_addr_width_p-1:0] awaddr_incr = (awaddr_r+(wr_burst_r<<$clog2(axi_data_width_p>>3))); + wire [axi_addr_width_p-1:0] awaddr_wrap = + (awaddr_incr == awaddr_wrap_upper) + ? awaddr_wrap_boundary + : (awaddr_incr > awaddr_wrap_upper) + ? awaddr_r + ((wr_burst_r-(awlen_r+1))<<$clog2(axi_data_width_p>>3)) + : awaddr_incr; + + logic wr_cnt_clr_li, wr_cnt_up_li; + logic [`BSG_SAFE_CLOG2(wr_delay_p)-1:0] wr_cnt_lo; + + logic wfifo_v_lo, wfifo_ready_lo, wfifo_yumi_li; + logic [axi_data_width_p-1:0] wfifo_data_lo; + logic [axi_strb_width_lp-1:0] wfifo_strb_lo; + + always_comb begin + + axi_awready_o = 1'b0; + awaddr_lo = '0; + + axi_wready_o = 1'b0; + + axi_bid_o = awid_r; + axi_bresp_o = '0; + axi_bvalid_o = 1'b0; + + awaddr_n = awaddr_r; + awid_n = awid_r; + + wr_cnt_clr_li = 1'b0; + wr_cnt_up_li = 1'b0; + + case (wr_state_r) + WR_RESET: begin + axi_awready_o = 1'b0; + + wr_state_n = WR_WAIT_ADDR; + end + + WR_WAIT_ADDR: begin + axi_awready_o = 1'b1; + wr_cnt_clr_li = 1'b1; + + awid_n = axi_awvalid_i + ? axi_awid_i + : awid_r; + awaddr_n = axi_awvalid_i + ? axi_awaddr_i + : awaddr_r; + awburst_n = axi_awvalid_i + ? axi_awburst_i + : awburst_r; + awlen_n = axi_awvalid_i + ? axi_awlen_i + : awlen_r; + + wr_burst_n = axi_awvalid_i + ? '0 + : wr_burst_r; + + wr_state_n = axi_awvalid_i + ? WR_WAIT_DATA + : WR_WAIT_ADDR; + end + + WR_WAIT_DATA: begin + axi_wready_o = wfifo_ready_lo; + wr_cnt_up_li = (wr_cnt_lo != wr_delay_p-1); + + wr_burst_n = wfifo_yumi_li + ? wr_burst_r + 1 + : wr_burst_r; + + awaddr_lo = + (awburst_r == e_axi_burst_incr) + ? awaddr_incr + : (awburst_r == e_axi_burst_wrap) + ? awaddr_wrap + : awaddr_r; + + wr_state_n = ((wr_burst_r == awlen_r) & wfifo_yumi_li) + ? WR_RESP + : WR_WAIT_DATA; + end + + WR_RESP: begin + axi_bvalid_o = 1'b1; + wr_state_n = axi_bready_i + ? WR_WAIT_ADDR + : WR_RESP; + end + endcase + end + + // read channel + // + typedef enum logic [1:0] { + RD_RESET + ,RD_WAIT_ADDR + ,RD_DELAY + ,RD_SEND_DATA + } rd_state_e; + + rd_state_e rd_state_r, rd_state_n; + logic [axi_id_width_p-1:0] arid_r, arid_n; + logic [axi_addr_width_p-1:0] araddr_lo, araddr_r, araddr_n; + logic [axi_len_width_p-1:0] rd_burst_r, rd_burst_n; + logic [1:0] arburst_r, arburst_n; + logic [axi_len_width_p-1:0] arlen_r, arlen_n; + + logic [lg_mem_els_lp-1:0] rd_ram_idx; + assign rd_ram_idx = araddr_lo[$clog2(axi_data_width_p>>3)+:lg_mem_els_lp]; + + // uninitialized data + // + logic [axi_data_width_p-1:0] uninit_data; + assign uninit_data = {(`BSG_MAX(1, axi_data_width_p/32)){init_data_p}}; + + for (genvar i = 0; i < axi_data_width_p; i++) begin + assign axi_rdata_o[i] = (ram[rd_ram_idx][i] === 1'bx) + ? uninit_data[i] + : ram[rd_ram_idx][i]; + end + + // https://developer.arm.com/documentation/ihi0022/c/Addressing-Options/Burst-address + wire [axi_addr_width_p-1:0] araddr_bytes_in_burst = (axi_data_width_p>>3) * (arlen_r+1); + wire [axi_addr_width_p-1:0] araddr_wrap_boundary = (araddr_r/araddr_bytes_in_burst)*araddr_bytes_in_burst; + wire [axi_addr_width_p-1:0] araddr_wrap_upper = araddr_wrap_boundary + araddr_bytes_in_burst; + wire [axi_addr_width_p-1:0] araddr_incr = (araddr_r+(rd_burst_r<<$clog2(axi_data_width_p>>3))); + wire [axi_addr_width_p-1:0] araddr_wrap = + (araddr_incr == araddr_wrap_upper) + ? araddr_wrap_boundary + : (araddr_incr > araddr_wrap_upper) + ? araddr_r + ((rd_burst_r-(arlen_r+1))<<$clog2(axi_data_width_p>>3)) + : araddr_incr; + + logic rd_cnt_clr_li, rd_cnt_up_li; + logic [`BSG_SAFE_CLOG2(rd_delay_p)-1:0] rd_cnt_lo; + + always_comb begin + + axi_rvalid_o = 1'b0; + axi_rlast_o = 1'b0; + axi_rid_o = arid_r; + axi_rresp_o = '0; + axi_arready_o = 1'b0; + araddr_lo = '0; + + rd_cnt_clr_li = 1'b0; + rd_cnt_up_li = 1'b0; + + case (rd_state_r) + RD_RESET: begin + axi_arready_o = 1'b0; + + rd_state_n = RD_WAIT_ADDR; + end + + RD_WAIT_ADDR: begin + axi_arready_o = 1'b1; + rd_cnt_clr_li = 1'b1; + + arid_n = axi_arvalid_i + ? axi_arid_i + : arid_r; + araddr_n = axi_arvalid_i + ? axi_araddr_i + : araddr_r; + arburst_n = axi_arvalid_i + ? axi_arburst_i + : arburst_r; + arlen_n = axi_arvalid_i + ? axi_arlen_i + : arlen_r; + + rd_burst_n = axi_arvalid_i + ? '0 + : rd_burst_r; + + rd_state_n = axi_arvalid_i + ? (rd_delay_p == 0) + ? RD_SEND_DATA + : RD_DELAY + : RD_WAIT_ADDR; + end + + RD_DELAY: begin + rd_cnt_up_li = 1'b1; + + rd_state_n = (rd_cnt_lo == rd_delay_p-1) + ? RD_SEND_DATA + : RD_DELAY; + end + + RD_SEND_DATA: begin + axi_rvalid_o = 1'b1; + + axi_rlast_o = (rd_burst_r == arlen_r); + + rd_burst_n = axi_rready_i + ? rd_burst_r + 1 + : rd_burst_r; + + araddr_lo = + (arburst_r == e_axi_burst_incr) + ? araddr_incr + : (arburst_r == e_axi_burst_wrap) + ? araddr_wrap + : araddr_r; + + rd_state_n = ((rd_burst_r == arlen_r) & axi_rready_i) + ? RD_WAIT_ADDR + : RD_SEND_DATA; + + end + endcase + end + + // sequential logic + // + always_ff @ (posedge clk_i) begin + if (reset_i) begin + wr_state_r <= WR_RESET; + awid_r <= '0; + awaddr_r <= '0; + awburst_r <= '0; + awlen_r <= '0; + wr_burst_r <= '0; + + rd_state_r <= RD_RESET; + arid_r <= '0; + araddr_r <= '0; + arburst_r <= '0; + arlen_r <= '0; + rd_burst_r <= '0; + end + else begin + wr_state_r <= wr_state_n; + awid_r <= awid_n; + awaddr_r <= awaddr_n; + awburst_r <= awburst_n; + awlen_r <= awlen_n; + wr_burst_r <= wr_burst_n; + + if (wfifo_yumi_li) begin + for (integer i = 0; i < axi_strb_width_lp; i++) begin + if (wfifo_strb_lo[i]) begin + ram[wr_ram_idx][i*8+:8] <= wfifo_data_lo[i*8+:8]; + end + end + end + + rd_state_r <= rd_state_n; + arid_r <= arid_n; + araddr_r <= araddr_n; + arburst_r <= arburst_n; + arlen_r <= arlen_n; + rd_burst_r <= rd_burst_n; + + end + end + + if(rd_delay_p == 0) begin + assign rd_cnt_lo = '0; + end + else begin + bsg_counter_clear_up + #(.max_val_p(rd_delay_p), .init_val_p(0)) + rd_dly_cnt + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(rd_cnt_clr_li) + ,.up_i(rd_cnt_up_li) + ,.count_o(rd_cnt_lo) + ); + end + + if(wr_delay_p == 0) begin + assign wfifo_yumi_li = axi_wvalid_i & axi_wready_o; + assign wfifo_ready_lo = 1'b1; + assign wfifo_v_lo = axi_wvalid_i; + assign wfifo_data_lo = axi_wdata_i; + assign wfifo_strb_lo = axi_wstrb_i; + assign wr_cnt_lo = '0; + end + else begin + assign wfifo_yumi_li = wfifo_v_lo & (wr_cnt_lo == wr_delay_p-1); + bsg_fifo_1r1w_small + #(.width_p(axi_data_width_p+axi_strb_width_lp), .els_p(wr_delay_p+1)) + wr_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(axi_wvalid_i) + ,.data_i({axi_wdata_i, axi_wstrb_i}) + ,.ready_param_o(wfifo_ready_lo) + ,.v_o(wfifo_v_lo) + ,.data_o({wfifo_data_lo, wfifo_strb_lo}) + ,.yumi_i(wfifo_yumi_li) + ); + + bsg_counter_clear_up + #(.max_val_p(wr_delay_p), .init_val_p(0)) + wr_dly_cnt + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(wr_cnt_clr_li) + ,.up_i(wr_cnt_up_li) + ,.count_o(wr_cnt_lo) + ); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_axi_mem) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_clock_gen.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_clock_gen.sv new file mode 100644 index 0000000..3860f4e --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_clock_gen.sv @@ -0,0 +1,36 @@ +// we use bit for the output so that it starts at 0 +// this helps with x prop mode in VCS +`include "bsg_defines.sv" + +`ifndef BSG_NO_TIMESCALE + `timescale 1ps/1ps +`endif + +`BSG_DEFIF_NOT_A_OR_B(VERILATOR, VERILATOR_TIMING, USE_DELAY_CLOCK_GEN) + +module bsg_nonsynth_clock_gen + #(parameter `BSG_INV_PARAM(cycle_time_p)) + (output bit o); + +`ifdef USE_DELAY_CLOCK_GEN + initial begin + $display("%m with cycle_time_p ",cycle_time_p); + assert(cycle_time_p >= 2) + else $error("cannot simulate cycle time less than 2"); + end + + always #(cycle_time_p/2.0) begin + o = ~o; + end +`else + initial begin + $info("[BSG INFO]: bsg_nonsynth_clock_gen is not supported in Verilator due to delay statement (#)"); + $info("[BSG INFO]: Falling back to bsg_nonsynth_dpi_clock_gen"); + end + bsg_nonsynth_dpi_clock_gen #(.cycle_time_p(cycle_time_p)) bcg (.*); +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_clock_gen) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3.sv new file mode 100644 index 0000000..8fb5d3d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3.sv @@ -0,0 +1,307 @@ +/** + * bsg_nonsynth_dramsim3.sv + * + */ + +`include "bsg_defines.sv" + +module bsg_nonsynth_dramsim3 + #(parameter `BSG_INV_PARAM(channel_addr_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(num_channels_p) + , parameter `BSG_INV_PARAM(num_columns_p) + , parameter `BSG_INV_PARAM(num_rows_p) + , parameter `BSG_INV_PARAM(num_ba_p) + , parameter `BSG_INV_PARAM(num_bg_p) + , parameter `BSG_INV_PARAM(num_ranks_p) + , parameter `BSG_INV_PARAM(address_mapping_p) + , parameter size_in_bits_p=0 + , parameter masked_p=0 + , parameter debug_p=0 + , parameter init_mem_p=0 // zero out values in memory at the beginning + , parameter `BSG_INV_PARAM(string config_p) + , parameter string trace_file_p="bsg_nonsynth_dramsim3_trace.txt" + , parameter base_id_p=0 // use this for multiple instances of this module + , parameter mem_addr_width_lp=$clog2(num_channels_p)+channel_addr_width_p + , parameter data_mask_width_lp=(data_width_p>>3) + , parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) + , parameter tag_width_p=32 + ) + ( + input clk_i + , input reset_i + + , input [num_channels_p-1:0] v_i + , input [num_channels_p-1:0] write_not_read_i + , input [num_channels_p-1:0][channel_addr_width_p-1:0] ch_addr_i + , output logic [num_channels_p-1:0] yumi_o + + , input [num_channels_p-1:0] data_v_i + , input [num_channels_p-1:0][data_width_p-1:0] data_i + , input [num_channels_p-1:0][data_mask_width_lp-1:0] mask_i + + //stats info + // print_stat clk can be asynchronous to the dram clk. + , input print_stat_clk_i + , input print_stat_reset_i + , input print_stat_v_i + , input [tag_width_p-1:0] print_stat_tag_i + + , output logic [num_channels_p-1:0] data_yumi_o + + , output logic [num_channels_p-1:0] data_v_o + , output logic [num_channels_p-1:0][data_width_p-1:0] data_o + , output logic [num_channels_p-1:0][channel_addr_width_p-1:0] read_done_ch_addr_o + + // this is for debugging/measuring performance. + // its usage is optional. + , output logic [num_channels_p-1:0] write_done_o + , output logic [num_channels_p-1:0][channel_addr_width_p-1:0] write_done_ch_addr_o + ); + + // memory addr + logic [num_channels_p-1:0][mem_addr_width_lp-1:0] mem_addr; + + // request tracking registers + logic [num_channels_p-1:0] read_req_r, read_req_n; + logic [num_channels_p-1:0] write_req_r, write_req_n; + logic [num_channels_p-1:0][mem_addr_width_lp-1:0] read_addr_r, read_addr_n; + logic [num_channels_p-1:0][mem_addr_width_lp-1:0] write_addr_r, write_addr_n; + + for (genvar i = 0; i < num_channels_p; i++) begin + bsg_nonsynth_dramsim3_map + #(.channel_addr_width_p(channel_addr_width_p) + ,.data_width_p(data_width_p) + ,.num_channels_p(num_channels_p) + ,.num_columns_p(num_columns_p) + ,.num_rows_p(num_rows_p) + ,.num_ba_p(num_ba_p) + ,.num_bg_p(num_bg_p) + ,.num_ranks_p(num_ranks_p) + ,.address_mapping_p(address_mapping_p) + ,.channel_select_p(i) + ,.debug_p(debug_p)) + map + (.ch_addr_i(ch_addr_i[i]) + ,.mem_addr_o(mem_addr[i])); + end + + + // request yumi + logic [num_channels_p-1:0] yumi_lo; + for (genvar i = 0; i < num_channels_p; i++) + assign yumi_o[i] = yumi_lo[i] & v_i[i]; + + // read channel signal + logic [num_channels_p-1:0] read_done; + logic [num_channels_p-1:0][mem_addr_width_lp-1:0] read_done_addr; + logic [num_channels_p-1:0][channel_addr_width_p-1:0] read_done_ch_addr; + + for (genvar i = 0; i < num_channels_p; i++) begin + bsg_nonsynth_dramsim3_unmap + #(.channel_addr_width_p(channel_addr_width_p) + ,.data_width_p(data_width_p) + ,.num_channels_p(num_channels_p) + ,.num_columns_p(num_columns_p) + ,.num_rows_p(num_rows_p) + ,.num_ba_p(num_ba_p) + ,.num_bg_p(num_bg_p) + ,.num_ranks_p(num_ranks_p) + ,.address_mapping_p(address_mapping_p) + ,.channel_select_p(i) + ,.debug_p(debug_p)) + unmap_read_done_addr + (.mem_addr_i(read_done_addr[i]) + ,.ch_addr_o(read_done_ch_addr[i])); + + end + + // write channel signal + logic [num_channels_p-1:0][mem_addr_width_lp-1:0] write_done_addr; + + for (genvar i = 0; i < num_channels_p; i++) begin + + bsg_nonsynth_dramsim3_unmap + #(.channel_addr_width_p(channel_addr_width_p) + ,.data_width_p(data_width_p) + ,.num_channels_p(num_channels_p) + ,.num_columns_p(num_columns_p) + ,.num_rows_p(num_rows_p) + ,.num_ba_p(num_ba_p) + ,.num_bg_p(num_bg_p) + ,.num_ranks_p(num_ranks_p) + ,.address_mapping_p(address_mapping_p) + ,.channel_select_p(i) + ,.debug_p(debug_p)) + unmap_write_done_addr + (.mem_addr_i(write_done_addr[i]) + ,.ch_addr_o(write_done_ch_addr_o[i])); + + end + + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + read_done <= '0; + read_done_addr <= '0; + write_done_o <= '0; + write_done_addr <= '0; + end + else begin + + // getting read/write done + for (integer i = 0; i < num_channels_p; i++) begin + read_done[i] <= read_req_r[i]; + if (read_req_r[i]) + read_done_addr[i] <= read_addr_r[i]; + + write_done_o[i] <= write_req_r[i]; + if (write_req_r[i]) + write_done_addr[i] <= write_addr_r[i]; + end + end + end + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + write_req_r <= '0; + read_req_r <= '0; + write_addr_r <= '0; + read_addr_r <= '0; + end else begin + write_req_r <= write_req_n; + read_req_r <= read_req_n; + write_addr_r <= write_addr_n; + read_addr_r <= read_addr_n; + end + end + + always_comb begin + write_req_n = '0; + read_req_n = '0; + write_addr_n = '0; + read_addr_n = '0; + for (integer i = 0; i < num_channels_p; i++) begin + if (v_i[i]) begin + if (write_not_read_i[i]) begin + if (data_v_i[i]) begin + write_req_n[i] = 1'b1; + write_addr_n[i] = mem_addr[i]; + end + end + else begin + read_req_n[i] = 1'b1; + read_addr_n[i] = mem_addr[i]; + end + end + end + end + + always_ff @ (negedge clk_i) begin + if (reset_i) begin + yumi_lo <= '0; + end + else begin + // sending requests + for (integer i = 0; i < num_channels_p; i++) begin + if (v_i[i]) begin + if (write_not_read_i[i]) begin + if (data_v_i[i]) + yumi_lo[i] <= 1'b1; + else + yumi_lo[i] <= 1'b0; + end + else begin + yumi_lo[i] <= 1'b1; + end + end + else begin + yumi_lo[i] <= 1'b0; + end + end + end + end + + // channels + logic [num_channels_p-1:0] read_v_li; + logic [num_channels_p-1:0][channel_addr_width_p-1:0] read_addr_li; + logic [num_channels_p-1:0] write_v_li; + logic [num_channels_p-1:0][data_mask_width_lp-1:0] mask_li; + + for (genvar i = 0; i < num_channels_p; i++) begin: channels + bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma + #(.width_p(data_width_p) + ,.els_p((size_in_bits_p/num_channels_p)/data_width_p) + ,.id_p(base_id_p+i) + ,.init_mem_p(init_mem_p)) + channel + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.r_v_i(read_v_li[i]) + ,.r_addr_i(read_addr_li[i][channel_addr_width_p-1:byte_offset_width_lp]) + + ,.w_v_i(write_v_li[i]) + ,.w_addr_i(ch_addr_i[i][channel_addr_width_p-1:byte_offset_width_lp]) + ,.w_data_i(data_i[i]) + ,.w_mask_i(mask_li[i]) + + ,.data_o(data_o[i]) + ); + + assign read_v_li[i] = read_done[i]; + assign read_addr_li[i] = read_done_ch_addr[i]; + + assign mask_li[i] = masked_p ? mask_i[i] : '1; + + assign write_v_li[i] = data_v_i[i] & v_i[i] & write_not_read_i[i] & yumi_o[i]; + assign data_yumi_o[i] = data_v_i[i] & write_not_read_i[i] & yumi_o[i]; + + end + + // aligning valid and address with the output data + always_ff @(posedge clk_i) begin + if (reset_i) begin + data_v_o <= '0; + read_done_ch_addr_o <= '0; + end + else begin + data_v_o <= read_v_li; + read_done_ch_addr_o <= read_done_ch_addr; + end + end + + // debugging + integer file; + initial begin + if (debug_p) begin + file = $fopen(trace_file_p, "w"); + $fwrite(file, "request,time,channel,write_not_read,address\n"); + end + end + + always_ff @ (posedge clk_i) begin + if (~reset_i & debug_p) begin + for (integer i = 0; i < num_channels_p; i++) begin + if (yumi_o[i]) + begin + $display("req sent: t=%012t, channel=%0d, write_not_read=%0b, addr=%010x", $time, i, write_not_read_i[i], ch_addr_i[i]); + $fwrite(file, "send,%t,%0d,%0b,%08h\n", $time, i, write_not_read_i[i], ch_addr_i[i]); + end + if (read_done[i]) + begin + $display("read done: t=%012t, channel=%0d, addr=%010x", $time, i, read_done_ch_addr[i]); + $fwrite(file, "recv,%t,%0d,,%08h\n", $time, i, read_done_ch_addr[i]); + end + if (write_done_o[i]) + begin + $display("write done: t=%012t, channel=%0d, addr=%010x", $time, i, write_done_ch_addr_o[i]); + end + end + end + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_dramsim3) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3_map.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3_map.sv new file mode 100644 index 0000000..a5252e6 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3_map.sv @@ -0,0 +1,73 @@ +///////////////////////////////// +// bsg_nonsynth_dramsim3_map.sv // +///////////////////////////////// +`include "bsg_defines.sv" + +module bsg_nonsynth_dramsim3_map + import bsg_dramsim3_pkg::*; + #(parameter `BSG_INV_PARAM(channel_addr_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(num_channels_p) + , parameter `BSG_INV_PARAM(num_columns_p) + , parameter `BSG_INV_PARAM(num_rows_p) + , parameter `BSG_INV_PARAM(num_ba_p) + , parameter `BSG_INV_PARAM(num_bg_p) + , parameter `BSG_INV_PARAM(num_ranks_p) + , parameter `BSG_INV_PARAM(address_mapping_p) + , parameter `BSG_INV_PARAM(channel_select_p) + , parameter debug_p=0 + , parameter lg_num_channels_lp=$clog2(num_channels_p) + , parameter lg_num_columns_lp=$clog2(num_columns_p) + , parameter lg_num_rows_lp=$clog2(num_rows_p) + , parameter lg_num_ba_lp=$clog2(num_ba_p) + , parameter lg_num_bg_lp=$clog2(num_bg_p) + , parameter lg_num_ranks_lp=$clog2(num_ranks_p) + , parameter data_mask_width_lp=(data_width_p>>3) + , parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) + , parameter addr_width_lp=lg_num_channels_lp+channel_addr_width_p + ) + ( + input logic [channel_addr_width_p-1:0] ch_addr_i + , output logic [addr_width_lp-1:0] mem_addr_o + ); + + localparam co_pos_lp = byte_offset_width_lp; + localparam ba_pos_lp = co_pos_lp + lg_num_columns_lp; + localparam bg_pos_lp = ba_pos_lp + lg_num_ba_lp; + localparam ra_pos_lp = bg_pos_lp + lg_num_bg_lp; + localparam ro_pos_lp = ra_pos_lp + lg_num_ranks_lp; + + if (address_mapping_p == e_ro_ra_bg_ba_co_ch) begin + assign mem_addr_o + = { + ch_addr_i[channel_addr_width_p-1:byte_offset_width_lp], + {lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}}, + {byte_offset_width_lp{1'b0}} + }; + end + + else if (address_mapping_p == e_ro_ra_bg_ba_ch_co) begin + assign mem_addr_o + = { + ch_addr_i[channel_addr_width_p-1:lg_num_columns_lp+byte_offset_width_lp], + {lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}}, + ch_addr_i[lg_num_columns_lp+byte_offset_width_lp-1:byte_offset_width_lp], + {byte_offset_width_lp{1'b0}} + }; + end + else if (address_mapping_p == e_ro_ch_ra_ba_bg_co) begin + assign mem_addr_o + = { + ch_addr_i[ro_pos_lp+:lg_num_rows_lp], + {lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}}, + {lg_num_ranks_lp!=0{ch_addr_i[ra_pos_lp+:`BSG_MAX(lg_num_ranks_lp, 1)]}}, + {lg_num_ba_lp!=0{ch_addr_i[ba_pos_lp+:`BSG_MAX(lg_num_ba_lp, 1)]}}, + {lg_num_bg_lp!=0{ch_addr_i[bg_pos_lp+:`BSG_MAX(lg_num_bg_lp, 1)]}}, + ch_addr_i[co_pos_lp+:lg_num_columns_lp], + {byte_offset_width_lp{1'b0}} + }; + end + +endmodule // bsg_nonsynth_dramsim3_map + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_dramsim3_map) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3_unmap.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3_unmap.sv new file mode 100644 index 0000000..b5ec167 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_dramsim3_unmap.sv @@ -0,0 +1,72 @@ +///////////////////////////////// +// bsg_nonsynth_dramsim3_unmap // +///////////////////////////////// +`include "bsg_defines.sv" + +module bsg_nonsynth_dramsim3_unmap + import bsg_dramsim3_pkg::*; + #(parameter `BSG_INV_PARAM(channel_addr_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(num_channels_p) + , parameter `BSG_INV_PARAM(num_columns_p) + , parameter `BSG_INV_PARAM(num_rows_p) + , parameter `BSG_INV_PARAM(num_ba_p) + , parameter `BSG_INV_PARAM(num_bg_p) + , parameter `BSG_INV_PARAM(num_ranks_p) + , parameter `BSG_INV_PARAM(address_mapping_p) + , parameter `BSG_INV_PARAM(channel_select_p) + , parameter debug_p=0 + , parameter lg_num_channels_lp=$clog2(num_channels_p) + , parameter lg_num_columns_lp=$clog2(num_columns_p) + , parameter lg_num_rows_lp=$clog2(num_rows_p) + , parameter lg_num_ba_lp=$clog2(num_ba_p) + , parameter lg_num_bg_lp=$clog2(num_bg_p) + , parameter lg_num_ranks_lp=$clog2(num_ranks_p) + , parameter data_mask_width_lp=(data_width_p>>3) + , parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) + , parameter addr_width_lp=lg_num_channels_lp+channel_addr_width_p + ) + ( + input logic [addr_width_lp-1:0] mem_addr_i + , output logic [channel_addr_width_p-1:0] ch_addr_o + ); + + if (address_mapping_p == e_ro_ra_bg_ba_co_ch) begin + assign ch_addr_o + = { + mem_addr_i[addr_width_lp-1:byte_offset_width_lp+lg_num_channels_lp], + {byte_offset_width_lp{1'b0}} + }; + end + + else if (address_mapping_p == e_ro_ra_bg_ba_ch_co) begin + assign ch_addr_o + = { + mem_addr_i[addr_width_lp-1:lg_num_channels_lp+lg_num_columns_lp+byte_offset_width_lp], + mem_addr_i[lg_num_columns_lp+byte_offset_width_lp-1:byte_offset_width_lp], + {byte_offset_width_lp{1'b0}} + }; + end + else if (address_mapping_p == e_ro_ch_ra_ba_bg_co) begin + + localparam mem_co_pos_lp = byte_offset_width_lp; + localparam mem_bg_pos_lp = mem_co_pos_lp + lg_num_columns_lp; + localparam mem_ba_pos_lp = mem_bg_pos_lp + lg_num_bg_lp; + localparam mem_ra_pos_lp = mem_ba_pos_lp + lg_num_ba_lp; + localparam mem_ch_pos_lp = mem_ra_pos_lp + lg_num_ranks_lp; + localparam mem_ro_pos_lp = mem_ch_pos_lp + lg_num_channels_lp; + + assign ch_addr_o + = { + mem_addr_i[mem_ro_pos_lp+:lg_num_rows_lp], + {lg_num_ranks_lp!=0{mem_addr_i[mem_ra_pos_lp+:`BSG_MAX(lg_num_ranks_lp, 1)]}}, + {lg_num_bg_lp!=0{mem_addr_i[mem_bg_pos_lp+:`BSG_MAX(lg_num_bg_lp, 1)]}}, + {lg_num_ba_lp!=0{mem_addr_i[mem_ba_pos_lp+:`BSG_MAX(lg_num_ba_lp, 1)]}}, + mem_addr_i[mem_co_pos_lp+:lg_num_columns_lp], + {byte_offset_width_lp{1'b0}} + }; + end + +endmodule // bsg_nonsynth_dramsim3_unmap + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_dramsim3_unmap) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.sv new file mode 100644 index 0000000..607b34a --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.sv @@ -0,0 +1,111 @@ +/** + * bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.sv + * + * If a read and write are issued to the same address the new value is read back. + * + */ + +`include "bsg_defines.sv" + +module bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter `BSG_INV_PARAM(id_p) + , parameter data_width_in_bytes_lp=(width_p>>3) + , parameter write_mask_width_lp=data_width_in_bytes_lp + , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) + , parameter byte_offset_width_lp=$clog2(data_width_in_bytes_lp) + , parameter init_mem_p=0 + ) + ( + input clk_i + , input reset_i + + // ctrl interface + , input r_v_i + , input [addr_width_lp-1:0] r_addr_i + + , input w_v_i + , input [addr_width_lp-1:0] w_addr_i + , input [width_p-1:0] w_data_i + , input [write_mask_width_lp-1:0] w_mask_i + + // read channel + , output logic [width_p-1:0] data_o + ); + + import "DPI-C" context function + chandle bsg_mem_dma_init(longint unsigned id, + longint unsigned channel_addr_width_fp, + longint unsigned data_width_fp, + longint unsigned mem_els_fp, + longint unsigned init_mem_fp); + + import "DPI-C" context function + void bsg_mem_dma_exit(longint unsigned id); + + import "DPI-C" context function + byte unsigned bsg_mem_dma_get(chandle handle, longint unsigned addr); + + import "DPI-C" context function + void bsg_mem_dma_set(chandle handle, longint unsigned addr, byte val); + + chandle memory; + + + initial begin + memory + = bsg_mem_dma_init(id_p, addr_width_lp, width_p, els_p, init_mem_p); + end + + final begin + bsg_mem_dma_exit(id_p); + end + + //////////////// + // read logic // + //////////////// + logic [addr_width_lp+byte_offset_width_lp-1:0] read_byte_addr; + assign read_byte_addr = { r_addr_i, {(byte_offset_width_lp){1'b0}} }; + + logic [width_p-1:0] data_r; + + always_ff @(negedge clk_i) begin + if (r_v_i) begin + for (integer byte_id = 0; byte_id < data_width_in_bytes_lp; byte_id++) begin + data_r[byte_id*8+:8] <= bsg_mem_dma_get(memory, read_byte_addr+byte_id); + end + end + + end + + // most client code expects outputs to change at the positive edge + always_ff @(posedge clk_i) begin + data_o <= data_r; + end + + + ///////////////// + // write logic // + ///////////////// + logic [addr_width_lp+byte_offset_width_lp-1:0] write_byte_addr; + assign write_byte_addr = { w_addr_i, {(byte_offset_width_lp){1'b0}} }; + + logic [width_p-1:0] mem_data_li; + logic write_valid; + + assign write_valid = ~reset_i & w_v_i; + + assign mem_data_li = w_data_i; + + always_ff @(posedge clk_i) begin + for (integer byte_id = 0; byte_id < data_width_in_bytes_lp; byte_id++) begin + if (write_valid & w_mask_i[byte_id]) + bsg_mem_dma_set(memory, write_byte_addr+byte_id, mem_data_li[byte_id*8+:8]); + + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma.sv new file mode 100644 index 0000000..d8dd8a8 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma.sv @@ -0,0 +1,56 @@ +/** + * bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma.sv + * + */ + +`include "bsg_defines.sv" + +module bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter `BSG_INV_PARAM(id_p) + , parameter data_width_in_bytes_lp=(width_p>>3) + , parameter write_mask_width_lp=data_width_in_bytes_lp + , parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p) + , parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_in_bytes_lp) + , parameter init_mem_p=0 + ) + ( + input clk_i + , input reset_i + + // ctrl interface + , input v_i + , input w_i + + , input [addr_width_lp-1:0] addr_i + , input [width_p-1:0] data_i + + , input [write_mask_width_lp-1:0] w_mask_i + + // read channel + , output logic [width_p-1:0] data_o + ); + + bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma + #(.width_p(width_p) + ,.els_p(els_p) + ,.id_p(id_p) + ,.init_mem_p(init_mem_p)) + mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.r_v_i(v_i & ~w_i) + ,.r_addr_i(addr_i) + + ,.w_v_i(v_i & w_i) + ,.w_addr_i(addr_i) + ,.w_data_i(data_i) + ,.w_mask_i(w_mask_i) + + ,.data_o(data_o)); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_reset_gen.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_reset_gen.sv new file mode 100644 index 0000000..ece31ab --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_reset_gen.sv @@ -0,0 +1,80 @@ +//********************************************************************** +// Reset +// ______ _______ ______ _______ _______ +// (_____ \(_______)/ _____|_______|_______) +// _____) )_____ ( (____ _____ _ +// | __ /| ___) \____ \| ___) | | +// | | \ \| |_____ _____) ) |_____ | | +// |_| |_|_______|______/|_______) |_| +// +//********************************************************************** + + +`include "bsg_defines.sv" + +module bsg_nonsynth_reset_gen #(parameter num_clocks_p=1 + , parameter `BSG_INV_PARAM(reset_cycles_lo_p) + , parameter `BSG_INV_PARAM(reset_cycles_hi_p)) + (input bit [num_clocks_p-1:0] clk_i + , output bit async_reset_o); + + genvar i; + + // This module relies on the input clock wires starting at 0 at + // time 0 and not transitioning from X to 0 at time 0, and causing + // a spurious negedge. To accomplish this in > VCS 2020, the input + // must be declared as a bit. Moreover, the expectation is that + // this module's input comes from a clock generation module that + // uses bit, such as bsg_nonsynth_clk_gen, AND that the wire + // between them is a bit. + + // use bit instead of logic to default to 0 initialization value + // this makes it non-synthesizeable, but also allows X prop mode to work + + bit [num_clocks_p-1:0][$clog2(reset_cycles_lo_p+1)-1:0] ctr_lo_r; + bit [num_clocks_p-1:0][$clog2(reset_cycles_hi_p+1)-1:0] ctr_hi_r; + + bit [num_clocks_p-1:0] phase_lo_r; + bit [num_clocks_p-1:0] phase_hi_r; + + wire in_phase_1 = & phase_lo_r; + wire in_phase_2 = & phase_hi_r; + + for (i = 0; i < num_clocks_p; i=i+1) + begin : rof + assign phase_lo_r[i] = (ctr_lo_r[i] == reset_cycles_lo_p[$bits(ctr_lo_r)-1:0]); + assign phase_hi_r[i] = (ctr_hi_r[i] == reset_cycles_hi_p[$bits(ctr_hi_r)-1:0]); + + always @(negedge clk_i[i]) + if (~phase_lo_r[i]) + ctr_lo_r[i] <= ctr_lo_r[i] + 1'b1; + else if (~phase_hi_r[i]) + ctr_hi_r[i] <= ctr_hi_r[i] + in_phase_1; + end + + assign async_reset_o = (in_phase_1 ^ in_phase_2); + + always @(negedge async_reset_o) + begin + $display("__________ ___________ _______________________________"); + $display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/"); + $display(" | _/ | __)_ \\_____ \\ | __)_ | | "); + $display(" | | \\ | \\ / \\ | \\ | | 1->0 time = ",$stime); + $display(" |____|_ //_______ //_______ //_______ / |____| "); + $display(" ASYNC \\/ \\/ \\/ \\/ "); + end + + always @(posedge async_reset_o) + begin + $display("__________ ___________ _______________________________"); + $display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/"); + $display(" | _/ | __)_ \\_____ \\ | __)_ | | "); + $display(" | | \\ | \\ / \\ | \\ | | 0->1 time = ",$stime); + $display(" |____|_ //_______ //_______ //_______ / |____| "); + $display(" ASYNC \\/ \\/ \\/ \\/ "); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_reset_gen) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_nonsynth_test_rom.sv b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_test_rom.sv new file mode 100644 index 0000000..0614e94 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nonsynth_test_rom.sv @@ -0,0 +1,37 @@ +/** + * bsg_nonsynth_test_rom.sv + * + * async read test_rom that uses readmemb to read its contents. + * + */ + + +`include "bsg_defines.sv" + +module bsg_nonsynth_test_rom + #(parameter `BSG_INV_PARAM(filename_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(addr_width_p) + , parameter hex_not_bin_p = 0 + ) + ( + input [addr_width_p-1:0] addr_i + , output logic [data_width_p-1:0] data_o + ); + + localparam els_lp = 2**addr_width_p; + + logic [data_width_p-1:0] rom [els_lp-1:0]; + + initial + if (hex_not_bin_p) + $readmemh(filename_p, rom); + else + $readmemb(filename_p, rom); + + assign data_o = rom[addr_i]; + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nonsynth_test_rom) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nor2.sv b/designs/black-parrot/src/basejump_stl/bsg_nor2.sv new file mode 100644 index 0000000..eedbd61 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nor2.sv @@ -0,0 +1,14 @@ +`include "bsg_defines.sv" + +module bsg_nor2 #(parameter `BSG_INV_PARAM(width_p) + , harden_p=1) + (input [width_p-1:0] a_i + , input [width_p-1:0] b_i + , output [width_p-1:0] o + ); + + assign o = ~(a_i | b_i ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nor2) diff --git a/designs/black-parrot/src/basejump_stl/bsg_nor3.sv b/designs/black-parrot/src/basejump_stl/bsg_nor3.sv new file mode 100644 index 0000000..fbcc9e7 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_nor3.sv @@ -0,0 +1,15 @@ +`include "bsg_defines.sv" + +module bsg_nor3 #(parameter `BSG_INV_PARAM(width_p) + , harden_p=1) + (input [width_p-1:0] a_i + , input [width_p-1:0] b_i + , input [width_p-1:0] c_i + , output [width_p-1:0] o + ); + + assign o = ~(a_i | b_i | c_i); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_nor3) diff --git a/designs/black-parrot/src/basejump_stl/bsg_one_fifo.sv b/designs/black-parrot/src/basejump_stl/bsg_one_fifo.sv new file mode 100644 index 0000000..eff1478 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_one_fifo.sv @@ -0,0 +1,58 @@ +// one element fifo +// +// use to pipeline links and convert interfaces +// from valid/ready to valid->yumi. +// (similar circumstances to bsg_two_fifo) +// +// This fifo can do at most +// 1 word/per 2 cycles bandwidth +// even at the shortest time scales. +// +// However, in some scenarios +// you know that you will not be pushing data +// through the FIFO at that rate, so you can +// save area by using this module. +// + +`include "bsg_defines.sv" + +module bsg_one_fifo #(parameter `BSG_INV_PARAM(width_p) + ) + (input clk_i + , input reset_i + + // input side + , output ready_and_o // early + , input [width_p-1:0] data_i // late + , input v_i // late + + // output side + , output v_o // early + , output[width_p-1:0] data_o // early + , input yumi_i // late + ); + + logic full_r; + + assign ready_and_o = ~full_r; + assign v_o = full_r; + + bsg_dff_reset #(.width_p(1)) dff_full + (.clk_i + ,.reset_i + ,.data_i(full_r ? ~yumi_i: v_i) + ,.data_o(full_r) + ); + + bsg_dff_en #(.width_p(width_p), .harden_p(0)) dff + (.clk_i + ,.data_i + // although technically it is okay to just look at v_o + // this will cause unnecessary toggling of flip flops + ,.en_i(v_i & ready_and_o) + ,.data_o + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_one_fifo) diff --git a/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out.sv b/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out.sv new file mode 100644 index 0000000..63835e1 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out.sv @@ -0,0 +1,212 @@ +// +// This data structure takes in a multi-word data and serializes +// it to a single word output. +// +// The input channel handshake is a ready-and-valid interface +// and the output channel handshake is a valid-then-yumi +// interface. This makes both channels "helpful" style +// handshakes. +// +// There are two options for this module: +// 1) zero bubbles, no dependence, 2 element buffer for last data word +// 2) one bubble, no dependence, 1 element buffer for last data word +// By default option 1 is used, option 2 can be enabled by setting +// use_minimal_buffering_p = 1 +// + +`include "bsg_defines.sv" + +module bsg_parallel_in_serial_out + + #(parameter `BSG_INV_PARAM(width_p) + ,parameter `BSG_INV_PARAM(els_p) + ,parameter hi_to_lo_p = 0 // sending from high bits to low bits + ,parameter use_minimal_buffering_p = 0 // using single element buffer + ) + + (input clk_i + ,input reset_i + + // Data Input Channel (Ready and Valid) + ,input valid_i + ,input [els_p-1:0][width_p-1:0] data_i + ,output ready_and_o + + // Data Output Channel (Valid then Yumi) + ,output valid_o + ,output [width_p-1:0] data_o + ,input yumi_i + ); + + // Reverse the input data array if send from HI to LO + logic [els_p-1:0][width_p-1:0] data_li; + if (hi_to_lo_p == 0) + begin: lo2hi + assign data_li = data_i; + end + else + begin: hi2lo + bsg_array_reverse + #(.width_p(width_p) + ,.els_p(els_p) + ) bar + (.i(data_i) + ,.o(data_li) + ); + end + + /** + * Buffering the LAST input data word + * + * By default a two-element fifo is used to eleminate bubbling. + * One-element fifo is optional for minimal resource utilization. + */ + logic fifo0_ready_and_lo, fifo_v_li; + logic fifo_v_lo, fifo0_yumi_li; + logic [els_p-1:0][width_p-1:0] fifo_data_lo; + + if (use_minimal_buffering_p == 0) + begin: two_fifo + bsg_two_fifo + #(.width_p (width_p) + ) fifo0 + (.clk_i (clk_i) + ,.reset_i (reset_i) + ,.ready_param_o (fifo0_ready_and_lo) + ,.data_i (data_li[els_p-1]) + ,.v_i (fifo_v_li) + ,.v_o (fifo_v_lo) + ,.data_o (fifo_data_lo[els_p-1]) + ,.yumi_i (fifo0_yumi_li) + ); + end + else + begin: one_fifo + bsg_one_fifo + #(.width_p(width_p) + ) fifo0 + (.clk_i (clk_i) + ,.reset_i (reset_i) + ,.ready_and_o(fifo0_ready_and_lo) + ,.data_i (data_li[els_p-1]) + ,.v_i (fifo_v_li) + ,.v_o (fifo_v_lo) + ,.data_o (fifo_data_lo[els_p-1]) + ,.yumi_i (fifo0_yumi_li) + ); + end + + if (els_p == 1) + begin: bypass + + // When conversion ratio is 1, only one data word exists + // Connect fifo0 signals directly to input/output ports + + assign fifo_v_li = valid_i; + assign ready_and_o = fifo0_ready_and_lo; + + assign valid_o = fifo_v_lo; + assign data_o = fifo_data_lo; + assign fifo0_yumi_li = yumi_i; + + end + else + begin: piso + + /** + * Buffering the rest of the data words + * + * Single element buffering is sufficient for bubble-free transmission. + * + * Output data of fifo1 is guaranteed to be valid if output data of fifo0 is + * valid and shift_ctr_r != (els_p-1). + * Therefore v_o signal of fifo1 is unused to minimize hardware utilization. + */ + logic fifo1_ready_and_lo, fifo1_yumi_li; + + bsg_one_fifo + #(.width_p((els_p-1)*width_p) + ) fifo1 + (.clk_i (clk_i) + ,.reset_i (reset_i) + ,.ready_and_o(fifo1_ready_and_lo) + ,.data_i (data_li[els_p-2:0]) + ,.v_i (fifo_v_li) + ,.v_o () + ,.data_o (fifo_data_lo[els_p-2:0]) + ,.yumi_i (fifo1_yumi_li) + ); + + /** + * Enqueue data into fifo iff both fifos are ready + */ + assign ready_and_o = fifo0_ready_and_lo & fifo1_ready_and_lo; + assign fifo_v_li = valid_i & ready_and_o; + + /** + * Data fifo yumi signals + * + * Dequeue from fifo1 when second-last data word has been sent out, freeing + * space for the following data words to avoid bubbling. + * Dequeue from fifo0 when last data word has been sent out, indicating + * done of transmission. + */ + localparam clog2els_lp = $clog2(els_p); + logic [clog2els_lp-1:0] shift_ctr_r; + + assign fifo0_yumi_li = (shift_ctr_r == clog2els_lp ' (els_p-1)) && yumi_i; + assign fifo1_yumi_li = (shift_ctr_r == clog2els_lp ' (els_p-2)) && yumi_i; + + /** + * Shift Counter Logic + * + * The shift_ctr_r register stores the word we are transmitting. Whenever + * we reset or done transmitting data, we clear the shift_ctr_r register. + * When data fifo has valid data output, we will increment the register if + * the outside world is going to accept our data (ie. yumi_i). + * + * Possible optimization + * + * Can instead use bsg_counter_clear_up_one_hot and one-hot mux down below + * for faster hardware by getting rid of a comparator and decoder on the paths. + * The downside is that there are more registers for counter (N vs lgN). + * Can do some PPA analysis for the tradeoff. + */ + bsg_counter_clear_up + #(.max_val_p (els_p-1) + ,.init_val_p('0) + ) shift_ctr + (.clk_i (clk_i) + ,.reset_i (reset_i) + ,.clear_i (fifo0_yumi_li) + ,.up_i (~fifo0_yumi_li & yumi_i) + ,.count_o (shift_ctr_r) + ); + + /** + * Valid Output Signal + * + * The valid_o signal means the output data is valid. For this + * module, the output is valid iff data fifo has valid output data. + */ + assign valid_o = fifo_v_lo; + + /** + * Data Output Signal + * + * Assign data_o to the word that we have shifted to. + */ + bsg_mux + #(.width_p(width_p) + ,.els_p (els_p) + ) data_o_mux + (.data_i (fifo_data_lo) + ,.sel_i (shift_ctr_r) + ,.data_o (data_o) + ); + + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_parallel_in_serial_out) diff --git a/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out_dynamic.sv b/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out_dynamic.sv new file mode 100644 index 0000000..ca67ded --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out_dynamic.sv @@ -0,0 +1,116 @@ +/** + * bsg_parallel_in_serial_out_dynamic.sv + * + * Paul Gao 06/2019 + * + */ + +`include "bsg_defines.sv" + +module bsg_parallel_in_serial_out_dynamic + + #(parameter `BSG_INV_PARAM(width_p) + ,parameter `BSG_INV_PARAM(max_els_p) + ,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p) + ) + + (input clk_i + ,input reset_i + + // Input side + ,input v_i + ,input [lg_max_els_lp-1:0] len_i + ,input [max_els_p-1:0][width_p-1:0] data_i + ,output ready_and_o + + // Output side + ,output v_o + ,output len_v_o + ,output [width_p-1:0] data_o + ,input yumi_i + ); + + logic go_fifo_yumi_li; + logic [lg_max_els_lp-1:0] len_lo; + logic [max_els_p-1:0][width_p-1:0] fifo_data_lo; + + // Go fifo and data fifo share the same control logic + // They always contain same number of elements in memory + + // Go fifo + bsg_two_fifo + #(.width_p (lg_max_els_lp ) + ) go_fifo + (.clk_i (clk_i ) + ,.reset_i (reset_i ) + + ,.ready_param_o (ready_and_o ) + ,.data_i (len_i ) + ,.v_i (v_i ) + + ,.v_o (v_o ) + ,.data_o (len_lo ) + ,.yumi_i (go_fifo_yumi_li) + ); + + // Data fifo + bsg_two_fifo + #(.width_p (max_els_p*width_p) + ) data_fifo + (.clk_i (clk_i ) + ,.reset_i (reset_i ) + + ,.ready_param_o ( ) + ,.data_i (data_i ) + ,.v_i (v_i ) + + ,.v_o ( ) + ,.data_o (fifo_data_lo ) + ,.yumi_i (go_fifo_yumi_li ) + ); + + logic [lg_max_els_lp-1:0] count_r, count_lo; + logic clear_li, up_li; + logic count_r_is_zero, count_r_is_last; + + // fix evaluate to Z problem in simulation + assign count_lo = count_r; + + assign count_r_is_zero = (count_lo == lg_max_els_lp'(0)); + assign count_r_is_last = (count_lo == len_lo ); + + // Indicate if output word is first word of packet + assign len_v_o = count_r_is_zero; + + // Count up if current word is not last word of packet. + assign up_li = yumi_i & ~count_r_is_last; + + // Clear counter when whole packet finish sending + assign clear_li = yumi_i & count_r_is_last; + assign go_fifo_yumi_li = clear_li; + + // Length counter + bsg_counter_clear_up + #(.max_val_p (max_els_p-1) + ,.init_val_p(0) + ) ctr + (.clk_i (clk_i ) + ,.reset_i (reset_i ) + ,.clear_i (clear_li) + ,.up_i (up_li ) + ,.count_o (count_r ) + ); + + // Output mux + bsg_mux + #(.width_p(width_p ) + ,.els_p (max_els_p ) + ) data_mux + (.data_i (fifo_data_lo) + ,.sel_i (count_lo ) + ,.data_o (data_o ) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_parallel_in_serial_out_dynamic) diff --git a/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out_passthrough.sv b/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out_passthrough.sv new file mode 100644 index 0000000..a171540 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_parallel_in_serial_out_passthrough.sv @@ -0,0 +1,115 @@ +// +// This data structure takes in a multi-word data and serializes +// it to a single word output. +// v_i passes through to v_o +// data_i passes through to data_o (with a mux delay) +// ready_and_i passes through to ready_and_o +// +// Note: +// A transaction starts when ready_and_o & v_i. data_i must +// stay constant for the entirety of the transaction until +// ready_and_o is asserted. +// This may make the module incompatible with upstream modules that +// multiplex multiple inputs and can change which input they multiplex +// on the fly based on arrival of new inputs. Importantly, the wormhole router +// needs to be instantiated with the hold_on_valid_p parameter. + +`include "bsg_defines.sv" + +module bsg_parallel_in_serial_out_passthrough #( parameter `BSG_INV_PARAM(width_p ) + , parameter `BSG_INV_PARAM(els_p ) + , parameter hi_to_lo_p = 0 + ) + ( input clk_i + , input reset_i + + // Data Input Channel + , input v_i + , input [els_p-1:0][width_p-1:0] data_i + , output ready_and_o + + // Data Output Channel + , output v_o + , output [width_p-1:0] data_o + , input ready_and_i + ); + + logic [els_p-1:0] count_r; + // For single word piso, we're just passing through the signals + if (els_p == 1) + begin : single_word + assign count_r = 1'b1; + assign ready_and_o = ready_and_i; + end + else + begin : multi_word + logic last_word; + bsg_counter_clear_up_one_hot + #(.max_val_p(els_p-1), .init_val_p(1)) + counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(ready_and_o & v_i) + ,.up_i(v_o & ready_and_i & ~last_word) + ,.count_r_o(count_r) + ); + assign last_word = count_r[els_p-1]; + + assign ready_and_o = ready_and_i & last_word; + end + + // If send hi_to_lo, reverse the input data array + logic [els_p-1:0][width_p-1:0] data_li; + + if (hi_to_lo_p == 0) + begin: lo2hi + assign data_li = data_i; + end + else + begin: hi2lo + bsg_array_reverse + #(.width_p(width_p), .els_p(els_p)) + bar + (.i(data_i) + ,.o(data_li) + ); + end + + bsg_mux_one_hot + #(.width_p(width_p), .els_p(els_p)) + data_mux + (.data_i(data_li) + ,.sel_one_hot_i(count_r) + ,.data_o(data_o) + ); + assign v_o = v_i; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + logic [els_p-1:0][width_p-1:0] initial_data_r; + bsg_dff_en + #(.width_p(width_p*els_p)) + initial_data_reg + (.clk_i(clk_i) + ,.en_i(count_r[0] & v_i) + + ,.data_i(data_i) + ,.data_o(initial_data_r) + ); + + always_ff @(negedge clk_i) + begin + if (~reset_i & (count_r[0] === 1'b0)) + begin + assert (v_i) + else $error("v_i must be held high during the entire PISO transaction"); + assert (data_i == initial_data_r) + else $error("data_i must be held constant during the entire PISO transaction"); + end + end +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_parallel_in_serial_out_passthrough) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_popcount.sv b/designs/black-parrot/src/basejump_stl/bsg_popcount.sv new file mode 100644 index 0000000..62668a5 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_popcount.sv @@ -0,0 +1,78 @@ +`include "bsg_defines.sv" + +// MBT popcount +// +// 10-24-14 +// + +module bsg_popcount #(parameter `BSG_INV_PARAM(width_p)) + (input [width_p-1:0] i + , output [$clog2(width_p+1)-1:0] o + ); + + // perf fixme: better to round up to nearest power of two and then + // recurse with side full and one side minimal + // + // e.g-> 80 -> 128/2 = 64 --> (64,16) + // + // possibly slightly better is to use 2^N-1: + // + // for items that are 5..7 bits wide, we make sure to + // split into a 4 and a 1/2/3; since the four is relatively optimized. + // + + localparam first_half_lp = `BSG_MAX(4,width_p - (width_p >> 1)); + localparam second_half_lp = width_p - first_half_lp; + + if (width_p <= 3) + begin : lt3 + assign o[0] = ^i; + + if (width_p == 2) + assign o[1] = & i; + else + if (width_p == 3) + assign o[1] = (&i[1:0]) | (&i[2:1]) | (i[0]&i[2]); + end + else + // http://www.wseas.us/e-library/conferences/2006hangzhou/papers/531-262.pdf + + if (width_p == 4) + begin : four + // half adders + wire [1:0] s0 = { ^i[3:2], ^i[1:0]}; + wire [1:0] c0 = { &i[3:2], &i[1:0]}; + + // low bit is xor of all bits + assign o[0] = ^s0; + + // middle bit is: ab ^ cd + // or (a^b) & (c^d) + + assign o[1] = (^c0) | (&s0); + + // high bit is and of all bits + + assign o[2] = &c0; + end + else + begin : recurse + wire [$clog2(first_half_lp+1)-1:0] lo; + wire [$clog2(second_half_lp+1)-1:0] hi; + + bsg_popcount #(.width_p(first_half_lp)) + left(.i(i[0+:first_half_lp]) + ,.o(lo) + ); + + bsg_popcount #(.width_p(second_half_lp)) + right(.i(i[first_half_lp+:second_half_lp]) + ,.o(hi) + ); + + assign o = lo+hi; + end + +endmodule // bsg_popcount + +`BSG_ABSTRACT_MODULE(bsg_popcount) diff --git a/designs/black-parrot/src/basejump_stl/bsg_priority_encode.sv b/designs/black-parrot/src/basejump_stl/bsg_priority_encode.sv new file mode 100644 index 0000000..fb9ea2f --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_priority_encode.sv @@ -0,0 +1,47 @@ +// MBT 5-22-16 +// +// Given a bit vector, return binary value +// corresponding to first bit that is set, starting from the low bit. +// +// e.g. 0001 --> 0, v= 1 +// 0011 --> 0, v= 1 +// 0101 --> 0, v= 1 +// 0100 --> 2, v= 1 +// 0000 --> 0, v= 0 +// +// + +`include "bsg_defines.sv" + +module bsg_priority_encode #(parameter `BSG_INV_PARAM( width_p ) + , parameter `BSG_INV_PARAM(lo_to_hi_p ) + ) + + (input [width_p-1:0] i + , output [`BSG_SAFE_CLOG2(width_p)-1:0] addr_o + , output v_o + ); + + logic [width_p-1:0] enc_lo; + + // We use this v_o instead of the v_o of bsg_encode_one_hot + // because it has better critical path + bsg_priority_encode_one_hot_out #(.width_p(width_p) + ,.lo_to_hi_p(lo_to_hi_p) + ) a + (.i(i) + ,.o(enc_lo) + ,.v_o(v_o) + ); + + bsg_encode_one_hot #(.width_p(width_p) + ,.lo_to_hi_p(lo_to_hi_p) + ) b + (.i (enc_lo) + ,.addr_o(addr_o) + ,.v_o () + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_priority_encode) diff --git a/designs/black-parrot/src/basejump_stl/bsg_priority_encode_one_hot_out.sv b/designs/black-parrot/src/basejump_stl/bsg_priority_encode_one_hot_out.sv new file mode 100644 index 0000000..29bcefb --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_priority_encode_one_hot_out.sv @@ -0,0 +1,51 @@ +// MBT 5-22-16 +// +// Given a bit vector, return a one-hot bit vector +// that has the latest/earliest bit selected. +// +// Can combine with bsg_encode_one_hot +// to get typical priority encoder. +// + +`include "bsg_defines.sv" + +module bsg_priority_encode_one_hot_out #(parameter `BSG_INV_PARAM(width_p ) + , parameter `BSG_INV_PARAM(lo_to_hi_p ) + ) + + (input [width_p-1:0] i + , output [width_p-1:0] o + , output v_o + ); + + logic [width_p-1:0] scan_lo; + + if (width_p == 1) + begin: w1 + assign o = i; + assign v_o = i; + end + else + begin: nw1 + bsg_scan #(.width_p(width_p) + ,.or_p (1) + ,.lo_to_hi_p(lo_to_hi_p) + ) scan (.i (i) + ,.o(scan_lo) + ); + + // edge detect + if (lo_to_hi_p) + begin : fi1 + assign o = scan_lo & { (~scan_lo[width_p-2:0]), 1'b1 }; + assign v_o = scan_lo[width_p-1]; + end + else + begin : fi1 + assign o = scan_lo & { 1'b1, (~scan_lo[width_p-1:1]) }; + assign v_o = scan_lo[0]; + end + end +endmodule + +`BSG_ABSTRACT_MODULE(bsg_priority_encode_one_hot_out) diff --git a/designs/black-parrot/src/basejump_stl/bsg_reduce.sv b/designs/black-parrot/src/basejump_stl/bsg_reduce.sv new file mode 100644 index 0000000..ff58703 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_reduce.sv @@ -0,0 +1,33 @@ +// MBT 9/3/2016 +// +// note: this does a reduction +// + +`include "bsg_defines.sv" + +module bsg_reduce #(parameter `BSG_INV_PARAM(width_p ) + , parameter xor_p = 0 + , parameter and_p = 0 + , parameter or_p = 0 + , parameter harden_p = 0 + ) + (input [width_p-1:0] i + , output o + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + assert( $countones({xor_p & 1'b1, and_p & 1'b1, or_p & 1'b1}) == 1) + else $error("bsg_reduce: exactly one function may be selected\n"); +`endif + + if (xor_p) + assign o = ^i; + else if (and_p) + assign o = &i; + else if (or_p) + assign o = |i; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_reduce) diff --git a/designs/black-parrot/src/basejump_stl/bsg_reduce_segmented.sv b/designs/black-parrot/src/basejump_stl/bsg_reduce_segmented.sv new file mode 100644 index 0000000..3cdf6db --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_reduce_segmented.sv @@ -0,0 +1,39 @@ +`include "bsg_defines.sv" + +module bsg_reduce_segmented #(parameter `BSG_INV_PARAM(segments_p ) + ,parameter `BSG_INV_PARAM(segment_width_p ) + + , parameter xor_p = 0 + , parameter and_p = 0 + , parameter or_p = 0 + , parameter nor_p = 0 + ) + (input [segments_p*segment_width_p-1:0] i + , output [segments_p-1:0] o + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + assert( $countones({xor_p[0], and_p[0], or_p[0], nor_p[0]}) == 1) + else $error("%m: exactly one function may be selected\n"); + +`endif + + + genvar j; + + for (j = 0; j < segments_p; j=j+1) + begin: rof2 + if (xor_p) + assign o[j] = ^i[(j*segment_width_p)+:segment_width_p]; + else if (and_p) + assign o[j] = &i[(j*segment_width_p)+:segment_width_p]; + else if (or_p) + assign o[j] = |i[(j*segment_width_p)+:segment_width_p]; + else if (nor_p) + assign o[j] = ~(|i[(j*segment_width_p)+:segment_width_p]); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_reduce_segmented) diff --git a/designs/black-parrot/src/basejump_stl/bsg_rotate_left.sv b/designs/black-parrot/src/basejump_stl/bsg_rotate_left.sv new file mode 100644 index 0000000..7733882 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_rotate_left.sv @@ -0,0 +1,14 @@ +`include "bsg_defines.sv" + +module bsg_rotate_left #(parameter `BSG_INV_PARAM(width_p)) + (input [width_p-1:0] data_i + , input [`BSG_SAFE_CLOG2(width_p)-1:0] rot_i + , output [width_p-1:0] o + ); + + wire [width_p*3-1:0] temp = { 2 { data_i } } << rot_i; + assign o = temp[width_p*2-1:width_p]; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_rotate_left) diff --git a/designs/black-parrot/src/basejump_stl/bsg_rotate_right.sv b/designs/black-parrot/src/basejump_stl/bsg_rotate_right.sv new file mode 100644 index 0000000..300d3fc --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_rotate_right.sv @@ -0,0 +1,14 @@ +`include "bsg_defines.sv" + +module bsg_rotate_right #(parameter `BSG_INV_PARAM(width_p)) + (input [width_p-1:0] data_i + , input [`BSG_SAFE_CLOG2(width_p)-1:0] rot_i + , output [width_p-1:0] o + ); + + wire [width_p*2-1:0] temp = { 2 { data_i } } >> rot_i; + assign o = temp[0+:width_p]; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_rotate_right) diff --git a/designs/black-parrot/src/basejump_stl/bsg_round_robin_1_to_n.sv b/designs/black-parrot/src/basejump_stl/bsg_round_robin_1_to_n.sv new file mode 100644 index 0000000..ff449c0 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_round_robin_1_to_n.sv @@ -0,0 +1,66 @@ +// MBT 11/10/14 +// +// bsg_round_robin_1_to_n +// +// this is intended to take one input and send it to +// one of several channels in round robin order. +// +// assumings a valid/ready interface +// +// we omit the data part as it is just duplication. +// + +`include "bsg_defines.sv" + +module bsg_round_robin_1_to_n #(parameter `BSG_INV_PARAM(width_p ) + ,parameter num_out_p = 2) + (input clk_i + , input reset_i + + // from one fifo + , input valid_i + , output ready_and_o + + // to many + , output [num_out_p-1:0] valid_o + , input [num_out_p-1:0] ready_and_i + + // to downstream + ); + + // If only one output, feed through the signals + if (num_out_p == 1) + begin: one_to_one + assign valid_o = valid_i; + assign ready_and_o = ready_and_i; + end + else + begin: one_to_n + + wire [`BSG_SAFE_CLOG2(num_out_p)-1:0] ptr_r; + // The data for the current fifo has been consumed + wire yumi_li = valid_i & ready_and_o; + + bsg_circular_ptr #(.slots_p(num_out_p) + ,.max_add_p(1) + ) circular_ptr + (.clk (clk_i ) + ,.reset_i(reset_i) + ,.add_i (yumi_li ) + ,.o (ptr_r ) + ,.n_o () + ); + + // bsg_decode_with_v could potentially be used to optimize this critical path + // at the cost of area + assign valid_o = (valid_i << ptr_r); + + // binary to one hot + assign ready_and_o = ready_and_i[ptr_r]; + + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_round_robin_1_to_n) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_round_robin_2_to_2.sv b/designs/black-parrot/src/basejump_stl/bsg_round_robin_2_to_2.sv new file mode 100644 index 0000000..bbd5d65 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_round_robin_2_to_2.sv @@ -0,0 +1,41 @@ +// this is intended for round robining +// on the input to a pair of fifos. +// +// the model is that you have a one or two parallel elements +// that you want to enqueue into a pair of FIFOs. +// because at times you will only enque one element, the next +// fifo to enque may be the second fifo. This module swizzles +// the inputs to the two fifos accordingly. + +`include "bsg_defines.sv" + +module bsg_round_robin_2_to_2 #(parameter `BSG_INV_PARAM(width_p ) + ) + (input clk_i + , input reset_i + , input [width_p*2-1:0] data_i + , input [1:0] v_i + , output [1:0] ready_o + + , output [width_p*2-1:0] data_o + , output [1:0] v_o + , input [1:0] ready_i + ); + + logic head_r; + + always_ff @(posedge clk_i) + if (reset_i) + head_r <= 0; + else + // or ^ {head_r, v_o & ready_i}; + head_r <= ^ {head_r, v_i & ready_o}; + + assign data_o = head_r ? { data_i[0+:width_p], data_i[width_p+:width_p] } : data_i; + assign v_o = head_r ? { v_i[0], v_i[1] } : v_i; + assign ready_o = head_r ? { ready_i[0], ready_i[1] } : ready_i; + +endmodule // bsg_round_robin_2_to_2 + +`BSG_ABSTRACT_MODULE(bsg_round_robin_2_to_2) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_round_robin_arb.sv b/designs/black-parrot/src/basejump_stl/bsg_round_robin_arb.sv new file mode 100644 index 0000000..e95873b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_round_robin_arb.sv @@ -0,0 +1,2454 @@ +// Round robin arbitration unit +// NOTE: generally prefer https://github.com/bespoke-silicon-group/basejump_stl/blob/master/bsg_misc/bsg_arb_round_robin.sv to this module. +// Automatically generated using bsg_round_robin_arb.py +// DO NOT MODIFY + +// this arbiter has a few usage scenarios which explains the somewhat complicated interface. +// Informal description of the interface: +// grants_en_i - Whether to suppress grant_o signals and tag_o, which are computed based on reqs_i +// sel_one_hot_o- The selection signal after the arbitration. +// grant_o - The grant signals that taking grant_en_i into consideration. +// v_o - Whether any reqs_i signals were valid. computed without grants_en_i. +// yumi_i - Whether to advance "least priority" pointer to the selected item +// in some typical use cases, grants_en_i comes from a downstream consumer to indicate readiness; +// this can be used with v_o to implement ready/valid protocol at both producer (fed into yumi_i) and consumer + +`include "bsg_defines.sv" + + +module bsg_round_robin_arb #(parameter `BSG_INV_PARAM(inputs_p) + ,lg_inputs_p =`BSG_SAFE_CLOG2(inputs_p) + ,reset_on_sr_p = 1'b0 + ,hold_on_sr_p = 1'b0 + // Hold on valid sets the arbitration policy such that once + // a output tag is selected, it remains selected until it is + // acked. This is consistent with BaseJump STL handshake + // assumptions. Notably, this parameter is required to work + // with bsg_parallel_in_serial_out_passthrough. This policy + // has a slight throughput degradation but effectively + // arbitrates based on age, so minimizes worst case latency. + ,hold_on_valid_p = 1'b0) + (input clk_i + , input reset_i + , input grants_en_i // whether to suppress grants_o + + // these are "third-party" inputs/outputs + // that are part of the "data plane" + + , input [inputs_p-1:0] reqs_i + , output logic [inputs_p-1:0] grants_o + , output logic [inputs_p-1:0] sel_one_hot_o + + // end third-party inputs/outputs + + , output v_o // if grants_en_i (i.e. ready_i) were set, would a grant signal be asserted? + , output logic [lg_inputs_p-1:0] tag_o // to which input the grant was given + , input yumi_i // yes, go ahead with whatever grants_o proposed + ); + +logic [lg_inputs_p-1:0] last, last_n, last_r; +logic hold_on_sr, reset_on_sr; + + + +if(inputs_p == 1) +begin: inputs_1 + +logic [1-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 2'b?_0: begin sel_one_hot_n = 1'b0; tag_o = (lg_inputs_p) ' (0); end // X + 2'b0_1: begin sel_one_hot_n= 1'b1; tag_o = (lg_inputs_p) ' (0); end + default: begin sel_one_hot_n= {1{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {1{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 1'b0 : hold_on_sr = ( reqs_i == 1'b1 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_1 + assign reset_on_sr = ( reqs_i == 1'b1 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_1 + +if(inputs_p == 2) +begin: inputs_2 + +logic [2-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 3'b?_00: begin sel_one_hot_n = 2'b00; tag_o = (lg_inputs_p) ' (0); end // X + 3'b0_1?: begin sel_one_hot_n= 2'b10; tag_o = (lg_inputs_p) ' (1); end + 3'b0_01: begin sel_one_hot_n= 2'b01; tag_o = (lg_inputs_p) ' (0); end + 3'b1_?1: begin sel_one_hot_n= 2'b01; tag_o = (lg_inputs_p) ' (0); end + 3'b1_10: begin sel_one_hot_n= 2'b10; tag_o = (lg_inputs_p) ' (1); end + default: begin sel_one_hot_n= {2{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {2{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 1'b0 : hold_on_sr = ( reqs_i == 2'b01 ); + default: hold_on_sr = ( reqs_i == 2'b10 ); + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_2 + assign reset_on_sr = ( reqs_i == 2'b01 ) + | ( reqs_i == 2'b10 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_2 + +if(inputs_p == 3) +begin: inputs_3 + +logic [3-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 5'b??_000: begin sel_one_hot_n = 3'b000; tag_o = (lg_inputs_p) ' (0); end // X + 5'b00_?1?: begin sel_one_hot_n= 3'b010; tag_o = (lg_inputs_p) ' (1); end + 5'b00_10?: begin sel_one_hot_n= 3'b100; tag_o = (lg_inputs_p) ' (2); end + 5'b00_001: begin sel_one_hot_n= 3'b001; tag_o = (lg_inputs_p) ' (0); end + 5'b01_1??: begin sel_one_hot_n= 3'b100; tag_o = (lg_inputs_p) ' (2); end + 5'b01_0?1: begin sel_one_hot_n= 3'b001; tag_o = (lg_inputs_p) ' (0); end + 5'b01_010: begin sel_one_hot_n= 3'b010; tag_o = (lg_inputs_p) ' (1); end + 5'b10_??1: begin sel_one_hot_n= 3'b001; tag_o = (lg_inputs_p) ' (0); end + 5'b10_?10: begin sel_one_hot_n= 3'b010; tag_o = (lg_inputs_p) ' (1); end + 5'b10_100: begin sel_one_hot_n= 3'b100; tag_o = (lg_inputs_p) ' (2); end + default: begin sel_one_hot_n= {3{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {3{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 2'b00 : hold_on_sr = ( reqs_i == 3'b010 ); + 2'b01 : hold_on_sr = ( reqs_i == 3'b001 ); + 2'b10 : hold_on_sr = ( reqs_i == 3'b100 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_3 + assign reset_on_sr = ( reqs_i == 3'b010 ) + | ( reqs_i == 3'b001 ) + | ( reqs_i == 3'b100 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_3 + +if(inputs_p == 4) +begin: inputs_4 + +logic [4-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 6'b??_0000: begin sel_one_hot_n = 4'b0000; tag_o = (lg_inputs_p) ' (0); end // X + 6'b00_??1?: begin sel_one_hot_n= 4'b0010; tag_o = (lg_inputs_p) ' (1); end + 6'b00_?10?: begin sel_one_hot_n= 4'b0100; tag_o = (lg_inputs_p) ' (2); end + 6'b00_100?: begin sel_one_hot_n= 4'b1000; tag_o = (lg_inputs_p) ' (3); end + 6'b00_0001: begin sel_one_hot_n= 4'b0001; tag_o = (lg_inputs_p) ' (0); end + 6'b01_?1??: begin sel_one_hot_n= 4'b0100; tag_o = (lg_inputs_p) ' (2); end + 6'b01_10??: begin sel_one_hot_n= 4'b1000; tag_o = (lg_inputs_p) ' (3); end + 6'b01_00?1: begin sel_one_hot_n= 4'b0001; tag_o = (lg_inputs_p) ' (0); end + 6'b01_0010: begin sel_one_hot_n= 4'b0010; tag_o = (lg_inputs_p) ' (1); end + 6'b10_1???: begin sel_one_hot_n= 4'b1000; tag_o = (lg_inputs_p) ' (3); end + 6'b10_0??1: begin sel_one_hot_n= 4'b0001; tag_o = (lg_inputs_p) ' (0); end + 6'b10_0?10: begin sel_one_hot_n= 4'b0010; tag_o = (lg_inputs_p) ' (1); end + 6'b10_0100: begin sel_one_hot_n= 4'b0100; tag_o = (lg_inputs_p) ' (2); end + 6'b11_???1: begin sel_one_hot_n= 4'b0001; tag_o = (lg_inputs_p) ' (0); end + 6'b11_??10: begin sel_one_hot_n= 4'b0010; tag_o = (lg_inputs_p) ' (1); end + 6'b11_?100: begin sel_one_hot_n= 4'b0100; tag_o = (lg_inputs_p) ' (2); end + 6'b11_1000: begin sel_one_hot_n= 4'b1000; tag_o = (lg_inputs_p) ' (3); end + default: begin sel_one_hot_n= {4{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {4{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 2'b00 : hold_on_sr = ( reqs_i == 4'b0100 ); + 2'b01 : hold_on_sr = ( reqs_i == 4'b0010 ); + 2'b10 : hold_on_sr = ( reqs_i == 4'b0001 ); + default: hold_on_sr = ( reqs_i == 4'b1000 ); + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_4 + assign reset_on_sr = ( reqs_i == 4'b0100 ) + | ( reqs_i == 4'b0010 ) + | ( reqs_i == 4'b0001 ) + | ( reqs_i == 4'b1000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_4 + +if(inputs_p == 5) +begin: inputs_5 + +logic [5-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 8'b???_00000: begin sel_one_hot_n = 5'b00000; tag_o = (lg_inputs_p) ' (0); end // X + 8'b000_???1?: begin sel_one_hot_n= 5'b00010; tag_o = (lg_inputs_p) ' (1); end + 8'b000_??10?: begin sel_one_hot_n= 5'b00100; tag_o = (lg_inputs_p) ' (2); end + 8'b000_?100?: begin sel_one_hot_n= 5'b01000; tag_o = (lg_inputs_p) ' (3); end + 8'b000_1000?: begin sel_one_hot_n= 5'b10000; tag_o = (lg_inputs_p) ' (4); end + 8'b000_00001: begin sel_one_hot_n= 5'b00001; tag_o = (lg_inputs_p) ' (0); end + 8'b001_??1??: begin sel_one_hot_n= 5'b00100; tag_o = (lg_inputs_p) ' (2); end + 8'b001_?10??: begin sel_one_hot_n= 5'b01000; tag_o = (lg_inputs_p) ' (3); end + 8'b001_100??: begin sel_one_hot_n= 5'b10000; tag_o = (lg_inputs_p) ' (4); end + 8'b001_000?1: begin sel_one_hot_n= 5'b00001; tag_o = (lg_inputs_p) ' (0); end + 8'b001_00010: begin sel_one_hot_n= 5'b00010; tag_o = (lg_inputs_p) ' (1); end + 8'b010_?1???: begin sel_one_hot_n= 5'b01000; tag_o = (lg_inputs_p) ' (3); end + 8'b010_10???: begin sel_one_hot_n= 5'b10000; tag_o = (lg_inputs_p) ' (4); end + 8'b010_00??1: begin sel_one_hot_n= 5'b00001; tag_o = (lg_inputs_p) ' (0); end + 8'b010_00?10: begin sel_one_hot_n= 5'b00010; tag_o = (lg_inputs_p) ' (1); end + 8'b010_00100: begin sel_one_hot_n= 5'b00100; tag_o = (lg_inputs_p) ' (2); end + 8'b011_1????: begin sel_one_hot_n= 5'b10000; tag_o = (lg_inputs_p) ' (4); end + 8'b011_0???1: begin sel_one_hot_n= 5'b00001; tag_o = (lg_inputs_p) ' (0); end + 8'b011_0??10: begin sel_one_hot_n= 5'b00010; tag_o = (lg_inputs_p) ' (1); end + 8'b011_0?100: begin sel_one_hot_n= 5'b00100; tag_o = (lg_inputs_p) ' (2); end + 8'b011_01000: begin sel_one_hot_n= 5'b01000; tag_o = (lg_inputs_p) ' (3); end + 8'b100_????1: begin sel_one_hot_n= 5'b00001; tag_o = (lg_inputs_p) ' (0); end + 8'b100_???10: begin sel_one_hot_n= 5'b00010; tag_o = (lg_inputs_p) ' (1); end + 8'b100_??100: begin sel_one_hot_n= 5'b00100; tag_o = (lg_inputs_p) ' (2); end + 8'b100_?1000: begin sel_one_hot_n= 5'b01000; tag_o = (lg_inputs_p) ' (3); end + 8'b100_10000: begin sel_one_hot_n= 5'b10000; tag_o = (lg_inputs_p) ' (4); end + default: begin sel_one_hot_n= {5{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {5{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 3'b000 : hold_on_sr = ( reqs_i == 5'b01000 ); + 3'b001 : hold_on_sr = ( reqs_i == 5'b00100 ); + 3'b010 : hold_on_sr = ( reqs_i == 5'b00010 ); + 3'b011 : hold_on_sr = ( reqs_i == 5'b00001 ); + 3'b100 : hold_on_sr = ( reqs_i == 5'b10000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_5 + assign reset_on_sr = ( reqs_i == 5'b01000 ) + | ( reqs_i == 5'b00100 ) + | ( reqs_i == 5'b00010 ) + | ( reqs_i == 5'b00001 ) + | ( reqs_i == 5'b10000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_5 + +if(inputs_p == 6) +begin: inputs_6 + +logic [6-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 9'b???_000000: begin sel_one_hot_n = 6'b000000; tag_o = (lg_inputs_p) ' (0); end // X + 9'b000_????1?: begin sel_one_hot_n= 6'b000010; tag_o = (lg_inputs_p) ' (1); end + 9'b000_???10?: begin sel_one_hot_n= 6'b000100; tag_o = (lg_inputs_p) ' (2); end + 9'b000_??100?: begin sel_one_hot_n= 6'b001000; tag_o = (lg_inputs_p) ' (3); end + 9'b000_?1000?: begin sel_one_hot_n= 6'b010000; tag_o = (lg_inputs_p) ' (4); end + 9'b000_10000?: begin sel_one_hot_n= 6'b100000; tag_o = (lg_inputs_p) ' (5); end + 9'b000_000001: begin sel_one_hot_n= 6'b000001; tag_o = (lg_inputs_p) ' (0); end + 9'b001_???1??: begin sel_one_hot_n= 6'b000100; tag_o = (lg_inputs_p) ' (2); end + 9'b001_??10??: begin sel_one_hot_n= 6'b001000; tag_o = (lg_inputs_p) ' (3); end + 9'b001_?100??: begin sel_one_hot_n= 6'b010000; tag_o = (lg_inputs_p) ' (4); end + 9'b001_1000??: begin sel_one_hot_n= 6'b100000; tag_o = (lg_inputs_p) ' (5); end + 9'b001_0000?1: begin sel_one_hot_n= 6'b000001; tag_o = (lg_inputs_p) ' (0); end + 9'b001_000010: begin sel_one_hot_n= 6'b000010; tag_o = (lg_inputs_p) ' (1); end + 9'b010_??1???: begin sel_one_hot_n= 6'b001000; tag_o = (lg_inputs_p) ' (3); end + 9'b010_?10???: begin sel_one_hot_n= 6'b010000; tag_o = (lg_inputs_p) ' (4); end + 9'b010_100???: begin sel_one_hot_n= 6'b100000; tag_o = (lg_inputs_p) ' (5); end + 9'b010_000??1: begin sel_one_hot_n= 6'b000001; tag_o = (lg_inputs_p) ' (0); end + 9'b010_000?10: begin sel_one_hot_n= 6'b000010; tag_o = (lg_inputs_p) ' (1); end + 9'b010_000100: begin sel_one_hot_n= 6'b000100; tag_o = (lg_inputs_p) ' (2); end + 9'b011_?1????: begin sel_one_hot_n= 6'b010000; tag_o = (lg_inputs_p) ' (4); end + 9'b011_10????: begin sel_one_hot_n= 6'b100000; tag_o = (lg_inputs_p) ' (5); end + 9'b011_00???1: begin sel_one_hot_n= 6'b000001; tag_o = (lg_inputs_p) ' (0); end + 9'b011_00??10: begin sel_one_hot_n= 6'b000010; tag_o = (lg_inputs_p) ' (1); end + 9'b011_00?100: begin sel_one_hot_n= 6'b000100; tag_o = (lg_inputs_p) ' (2); end + 9'b011_001000: begin sel_one_hot_n= 6'b001000; tag_o = (lg_inputs_p) ' (3); end + 9'b100_1?????: begin sel_one_hot_n= 6'b100000; tag_o = (lg_inputs_p) ' (5); end + 9'b100_0????1: begin sel_one_hot_n= 6'b000001; tag_o = (lg_inputs_p) ' (0); end + 9'b100_0???10: begin sel_one_hot_n= 6'b000010; tag_o = (lg_inputs_p) ' (1); end + 9'b100_0??100: begin sel_one_hot_n= 6'b000100; tag_o = (lg_inputs_p) ' (2); end + 9'b100_0?1000: begin sel_one_hot_n= 6'b001000; tag_o = (lg_inputs_p) ' (3); end + 9'b100_010000: begin sel_one_hot_n= 6'b010000; tag_o = (lg_inputs_p) ' (4); end + 9'b101_?????1: begin sel_one_hot_n= 6'b000001; tag_o = (lg_inputs_p) ' (0); end + 9'b101_????10: begin sel_one_hot_n= 6'b000010; tag_o = (lg_inputs_p) ' (1); end + 9'b101_???100: begin sel_one_hot_n= 6'b000100; tag_o = (lg_inputs_p) ' (2); end + 9'b101_??1000: begin sel_one_hot_n= 6'b001000; tag_o = (lg_inputs_p) ' (3); end + 9'b101_?10000: begin sel_one_hot_n= 6'b010000; tag_o = (lg_inputs_p) ' (4); end + 9'b101_100000: begin sel_one_hot_n= 6'b100000; tag_o = (lg_inputs_p) ' (5); end + default: begin sel_one_hot_n= {6{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {6{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 3'b000 : hold_on_sr = ( reqs_i == 6'b010000 ); + 3'b001 : hold_on_sr = ( reqs_i == 6'b001000 ); + 3'b010 : hold_on_sr = ( reqs_i == 6'b000100 ); + 3'b011 : hold_on_sr = ( reqs_i == 6'b000010 ); + 3'b100 : hold_on_sr = ( reqs_i == 6'b000001 ); + 3'b101 : hold_on_sr = ( reqs_i == 6'b100000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_6 + assign reset_on_sr = ( reqs_i == 6'b010000 ) + | ( reqs_i == 6'b001000 ) + | ( reqs_i == 6'b000100 ) + | ( reqs_i == 6'b000010 ) + | ( reqs_i == 6'b000001 ) + | ( reqs_i == 6'b100000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_6 + +if(inputs_p == 7) +begin: inputs_7 + +logic [7-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 10'b???_0000000: begin sel_one_hot_n = 7'b0000000; tag_o = (lg_inputs_p) ' (0); end // X + 10'b000_?????1?: begin sel_one_hot_n= 7'b0000010; tag_o = (lg_inputs_p) ' (1); end + 10'b000_????10?: begin sel_one_hot_n= 7'b0000100; tag_o = (lg_inputs_p) ' (2); end + 10'b000_???100?: begin sel_one_hot_n= 7'b0001000; tag_o = (lg_inputs_p) ' (3); end + 10'b000_??1000?: begin sel_one_hot_n= 7'b0010000; tag_o = (lg_inputs_p) ' (4); end + 10'b000_?10000?: begin sel_one_hot_n= 7'b0100000; tag_o = (lg_inputs_p) ' (5); end + 10'b000_100000?: begin sel_one_hot_n= 7'b1000000; tag_o = (lg_inputs_p) ' (6); end + 10'b000_0000001: begin sel_one_hot_n= 7'b0000001; tag_o = (lg_inputs_p) ' (0); end + 10'b001_????1??: begin sel_one_hot_n= 7'b0000100; tag_o = (lg_inputs_p) ' (2); end + 10'b001_???10??: begin sel_one_hot_n= 7'b0001000; tag_o = (lg_inputs_p) ' (3); end + 10'b001_??100??: begin sel_one_hot_n= 7'b0010000; tag_o = (lg_inputs_p) ' (4); end + 10'b001_?1000??: begin sel_one_hot_n= 7'b0100000; tag_o = (lg_inputs_p) ' (5); end + 10'b001_10000??: begin sel_one_hot_n= 7'b1000000; tag_o = (lg_inputs_p) ' (6); end + 10'b001_00000?1: begin sel_one_hot_n= 7'b0000001; tag_o = (lg_inputs_p) ' (0); end + 10'b001_0000010: begin sel_one_hot_n= 7'b0000010; tag_o = (lg_inputs_p) ' (1); end + 10'b010_???1???: begin sel_one_hot_n= 7'b0001000; tag_o = (lg_inputs_p) ' (3); end + 10'b010_??10???: begin sel_one_hot_n= 7'b0010000; tag_o = (lg_inputs_p) ' (4); end + 10'b010_?100???: begin sel_one_hot_n= 7'b0100000; tag_o = (lg_inputs_p) ' (5); end + 10'b010_1000???: begin sel_one_hot_n= 7'b1000000; tag_o = (lg_inputs_p) ' (6); end + 10'b010_0000??1: begin sel_one_hot_n= 7'b0000001; tag_o = (lg_inputs_p) ' (0); end + 10'b010_0000?10: begin sel_one_hot_n= 7'b0000010; tag_o = (lg_inputs_p) ' (1); end + 10'b010_0000100: begin sel_one_hot_n= 7'b0000100; tag_o = (lg_inputs_p) ' (2); end + 10'b011_??1????: begin sel_one_hot_n= 7'b0010000; tag_o = (lg_inputs_p) ' (4); end + 10'b011_?10????: begin sel_one_hot_n= 7'b0100000; tag_o = (lg_inputs_p) ' (5); end + 10'b011_100????: begin sel_one_hot_n= 7'b1000000; tag_o = (lg_inputs_p) ' (6); end + 10'b011_000???1: begin sel_one_hot_n= 7'b0000001; tag_o = (lg_inputs_p) ' (0); end + 10'b011_000??10: begin sel_one_hot_n= 7'b0000010; tag_o = (lg_inputs_p) ' (1); end + 10'b011_000?100: begin sel_one_hot_n= 7'b0000100; tag_o = (lg_inputs_p) ' (2); end + 10'b011_0001000: begin sel_one_hot_n= 7'b0001000; tag_o = (lg_inputs_p) ' (3); end + 10'b100_?1?????: begin sel_one_hot_n= 7'b0100000; tag_o = (lg_inputs_p) ' (5); end + 10'b100_10?????: begin sel_one_hot_n= 7'b1000000; tag_o = (lg_inputs_p) ' (6); end + 10'b100_00????1: begin sel_one_hot_n= 7'b0000001; tag_o = (lg_inputs_p) ' (0); end + 10'b100_00???10: begin sel_one_hot_n= 7'b0000010; tag_o = (lg_inputs_p) ' (1); end + 10'b100_00??100: begin sel_one_hot_n= 7'b0000100; tag_o = (lg_inputs_p) ' (2); end + 10'b100_00?1000: begin sel_one_hot_n= 7'b0001000; tag_o = (lg_inputs_p) ' (3); end + 10'b100_0010000: begin sel_one_hot_n= 7'b0010000; tag_o = (lg_inputs_p) ' (4); end + 10'b101_1??????: begin sel_one_hot_n= 7'b1000000; tag_o = (lg_inputs_p) ' (6); end + 10'b101_0?????1: begin sel_one_hot_n= 7'b0000001; tag_o = (lg_inputs_p) ' (0); end + 10'b101_0????10: begin sel_one_hot_n= 7'b0000010; tag_o = (lg_inputs_p) ' (1); end + 10'b101_0???100: begin sel_one_hot_n= 7'b0000100; tag_o = (lg_inputs_p) ' (2); end + 10'b101_0??1000: begin sel_one_hot_n= 7'b0001000; tag_o = (lg_inputs_p) ' (3); end + 10'b101_0?10000: begin sel_one_hot_n= 7'b0010000; tag_o = (lg_inputs_p) ' (4); end + 10'b101_0100000: begin sel_one_hot_n= 7'b0100000; tag_o = (lg_inputs_p) ' (5); end + 10'b110_??????1: begin sel_one_hot_n= 7'b0000001; tag_o = (lg_inputs_p) ' (0); end + 10'b110_?????10: begin sel_one_hot_n= 7'b0000010; tag_o = (lg_inputs_p) ' (1); end + 10'b110_????100: begin sel_one_hot_n= 7'b0000100; tag_o = (lg_inputs_p) ' (2); end + 10'b110_???1000: begin sel_one_hot_n= 7'b0001000; tag_o = (lg_inputs_p) ' (3); end + 10'b110_??10000: begin sel_one_hot_n= 7'b0010000; tag_o = (lg_inputs_p) ' (4); end + 10'b110_?100000: begin sel_one_hot_n= 7'b0100000; tag_o = (lg_inputs_p) ' (5); end + 10'b110_1000000: begin sel_one_hot_n= 7'b1000000; tag_o = (lg_inputs_p) ' (6); end + default: begin sel_one_hot_n= {7{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {7{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 3'b000 : hold_on_sr = ( reqs_i == 7'b0100000 ); + 3'b001 : hold_on_sr = ( reqs_i == 7'b0010000 ); + 3'b010 : hold_on_sr = ( reqs_i == 7'b0001000 ); + 3'b011 : hold_on_sr = ( reqs_i == 7'b0000100 ); + 3'b100 : hold_on_sr = ( reqs_i == 7'b0000010 ); + 3'b101 : hold_on_sr = ( reqs_i == 7'b0000001 ); + 3'b110 : hold_on_sr = ( reqs_i == 7'b1000000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_7 + assign reset_on_sr = ( reqs_i == 7'b0100000 ) + | ( reqs_i == 7'b0010000 ) + | ( reqs_i == 7'b0001000 ) + | ( reqs_i == 7'b0000100 ) + | ( reqs_i == 7'b0000010 ) + | ( reqs_i == 7'b0000001 ) + | ( reqs_i == 7'b1000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_7 + +if(inputs_p == 8) +begin: inputs_8 + +logic [8-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 11'b???_00000000: begin sel_one_hot_n = 8'b00000000; tag_o = (lg_inputs_p) ' (0); end // X + 11'b000_??????1?: begin sel_one_hot_n= 8'b00000010; tag_o = (lg_inputs_p) ' (1); end + 11'b000_?????10?: begin sel_one_hot_n= 8'b00000100; tag_o = (lg_inputs_p) ' (2); end + 11'b000_????100?: begin sel_one_hot_n= 8'b00001000; tag_o = (lg_inputs_p) ' (3); end + 11'b000_???1000?: begin sel_one_hot_n= 8'b00010000; tag_o = (lg_inputs_p) ' (4); end + 11'b000_??10000?: begin sel_one_hot_n= 8'b00100000; tag_o = (lg_inputs_p) ' (5); end + 11'b000_?100000?: begin sel_one_hot_n= 8'b01000000; tag_o = (lg_inputs_p) ' (6); end + 11'b000_1000000?: begin sel_one_hot_n= 8'b10000000; tag_o = (lg_inputs_p) ' (7); end + 11'b000_00000001: begin sel_one_hot_n= 8'b00000001; tag_o = (lg_inputs_p) ' (0); end + 11'b001_?????1??: begin sel_one_hot_n= 8'b00000100; tag_o = (lg_inputs_p) ' (2); end + 11'b001_????10??: begin sel_one_hot_n= 8'b00001000; tag_o = (lg_inputs_p) ' (3); end + 11'b001_???100??: begin sel_one_hot_n= 8'b00010000; tag_o = (lg_inputs_p) ' (4); end + 11'b001_??1000??: begin sel_one_hot_n= 8'b00100000; tag_o = (lg_inputs_p) ' (5); end + 11'b001_?10000??: begin sel_one_hot_n= 8'b01000000; tag_o = (lg_inputs_p) ' (6); end + 11'b001_100000??: begin sel_one_hot_n= 8'b10000000; tag_o = (lg_inputs_p) ' (7); end + 11'b001_000000?1: begin sel_one_hot_n= 8'b00000001; tag_o = (lg_inputs_p) ' (0); end + 11'b001_00000010: begin sel_one_hot_n= 8'b00000010; tag_o = (lg_inputs_p) ' (1); end + 11'b010_????1???: begin sel_one_hot_n= 8'b00001000; tag_o = (lg_inputs_p) ' (3); end + 11'b010_???10???: begin sel_one_hot_n= 8'b00010000; tag_o = (lg_inputs_p) ' (4); end + 11'b010_??100???: begin sel_one_hot_n= 8'b00100000; tag_o = (lg_inputs_p) ' (5); end + 11'b010_?1000???: begin sel_one_hot_n= 8'b01000000; tag_o = (lg_inputs_p) ' (6); end + 11'b010_10000???: begin sel_one_hot_n= 8'b10000000; tag_o = (lg_inputs_p) ' (7); end + 11'b010_00000??1: begin sel_one_hot_n= 8'b00000001; tag_o = (lg_inputs_p) ' (0); end + 11'b010_00000?10: begin sel_one_hot_n= 8'b00000010; tag_o = (lg_inputs_p) ' (1); end + 11'b010_00000100: begin sel_one_hot_n= 8'b00000100; tag_o = (lg_inputs_p) ' (2); end + 11'b011_???1????: begin sel_one_hot_n= 8'b00010000; tag_o = (lg_inputs_p) ' (4); end + 11'b011_??10????: begin sel_one_hot_n= 8'b00100000; tag_o = (lg_inputs_p) ' (5); end + 11'b011_?100????: begin sel_one_hot_n= 8'b01000000; tag_o = (lg_inputs_p) ' (6); end + 11'b011_1000????: begin sel_one_hot_n= 8'b10000000; tag_o = (lg_inputs_p) ' (7); end + 11'b011_0000???1: begin sel_one_hot_n= 8'b00000001; tag_o = (lg_inputs_p) ' (0); end + 11'b011_0000??10: begin sel_one_hot_n= 8'b00000010; tag_o = (lg_inputs_p) ' (1); end + 11'b011_0000?100: begin sel_one_hot_n= 8'b00000100; tag_o = (lg_inputs_p) ' (2); end + 11'b011_00001000: begin sel_one_hot_n= 8'b00001000; tag_o = (lg_inputs_p) ' (3); end + 11'b100_??1?????: begin sel_one_hot_n= 8'b00100000; tag_o = (lg_inputs_p) ' (5); end + 11'b100_?10?????: begin sel_one_hot_n= 8'b01000000; tag_o = (lg_inputs_p) ' (6); end + 11'b100_100?????: begin sel_one_hot_n= 8'b10000000; tag_o = (lg_inputs_p) ' (7); end + 11'b100_000????1: begin sel_one_hot_n= 8'b00000001; tag_o = (lg_inputs_p) ' (0); end + 11'b100_000???10: begin sel_one_hot_n= 8'b00000010; tag_o = (lg_inputs_p) ' (1); end + 11'b100_000??100: begin sel_one_hot_n= 8'b00000100; tag_o = (lg_inputs_p) ' (2); end + 11'b100_000?1000: begin sel_one_hot_n= 8'b00001000; tag_o = (lg_inputs_p) ' (3); end + 11'b100_00010000: begin sel_one_hot_n= 8'b00010000; tag_o = (lg_inputs_p) ' (4); end + 11'b101_?1??????: begin sel_one_hot_n= 8'b01000000; tag_o = (lg_inputs_p) ' (6); end + 11'b101_10??????: begin sel_one_hot_n= 8'b10000000; tag_o = (lg_inputs_p) ' (7); end + 11'b101_00?????1: begin sel_one_hot_n= 8'b00000001; tag_o = (lg_inputs_p) ' (0); end + 11'b101_00????10: begin sel_one_hot_n= 8'b00000010; tag_o = (lg_inputs_p) ' (1); end + 11'b101_00???100: begin sel_one_hot_n= 8'b00000100; tag_o = (lg_inputs_p) ' (2); end + 11'b101_00??1000: begin sel_one_hot_n= 8'b00001000; tag_o = (lg_inputs_p) ' (3); end + 11'b101_00?10000: begin sel_one_hot_n= 8'b00010000; tag_o = (lg_inputs_p) ' (4); end + 11'b101_00100000: begin sel_one_hot_n= 8'b00100000; tag_o = (lg_inputs_p) ' (5); end + 11'b110_1???????: begin sel_one_hot_n= 8'b10000000; tag_o = (lg_inputs_p) ' (7); end + 11'b110_0??????1: begin sel_one_hot_n= 8'b00000001; tag_o = (lg_inputs_p) ' (0); end + 11'b110_0?????10: begin sel_one_hot_n= 8'b00000010; tag_o = (lg_inputs_p) ' (1); end + 11'b110_0????100: begin sel_one_hot_n= 8'b00000100; tag_o = (lg_inputs_p) ' (2); end + 11'b110_0???1000: begin sel_one_hot_n= 8'b00001000; tag_o = (lg_inputs_p) ' (3); end + 11'b110_0??10000: begin sel_one_hot_n= 8'b00010000; tag_o = (lg_inputs_p) ' (4); end + 11'b110_0?100000: begin sel_one_hot_n= 8'b00100000; tag_o = (lg_inputs_p) ' (5); end + 11'b110_01000000: begin sel_one_hot_n= 8'b01000000; tag_o = (lg_inputs_p) ' (6); end + 11'b111_???????1: begin sel_one_hot_n= 8'b00000001; tag_o = (lg_inputs_p) ' (0); end + 11'b111_??????10: begin sel_one_hot_n= 8'b00000010; tag_o = (lg_inputs_p) ' (1); end + 11'b111_?????100: begin sel_one_hot_n= 8'b00000100; tag_o = (lg_inputs_p) ' (2); end + 11'b111_????1000: begin sel_one_hot_n= 8'b00001000; tag_o = (lg_inputs_p) ' (3); end + 11'b111_???10000: begin sel_one_hot_n= 8'b00010000; tag_o = (lg_inputs_p) ' (4); end + 11'b111_??100000: begin sel_one_hot_n= 8'b00100000; tag_o = (lg_inputs_p) ' (5); end + 11'b111_?1000000: begin sel_one_hot_n= 8'b01000000; tag_o = (lg_inputs_p) ' (6); end + 11'b111_10000000: begin sel_one_hot_n= 8'b10000000; tag_o = (lg_inputs_p) ' (7); end + default: begin sel_one_hot_n= {8{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {8{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 3'b000 : hold_on_sr = ( reqs_i == 8'b01000000 ); + 3'b001 : hold_on_sr = ( reqs_i == 8'b00100000 ); + 3'b010 : hold_on_sr = ( reqs_i == 8'b00010000 ); + 3'b011 : hold_on_sr = ( reqs_i == 8'b00001000 ); + 3'b100 : hold_on_sr = ( reqs_i == 8'b00000100 ); + 3'b101 : hold_on_sr = ( reqs_i == 8'b00000010 ); + 3'b110 : hold_on_sr = ( reqs_i == 8'b00000001 ); + default: hold_on_sr = ( reqs_i == 8'b10000000 ); + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_8 + assign reset_on_sr = ( reqs_i == 8'b01000000 ) + | ( reqs_i == 8'b00100000 ) + | ( reqs_i == 8'b00010000 ) + | ( reqs_i == 8'b00001000 ) + | ( reqs_i == 8'b00000100 ) + | ( reqs_i == 8'b00000010 ) + | ( reqs_i == 8'b00000001 ) + | ( reqs_i == 8'b10000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_8 + +if(inputs_p == 9) +begin: inputs_9 + +logic [9-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 13'b????_000000000: begin sel_one_hot_n = 9'b000000000; tag_o = (lg_inputs_p) ' (0); end // X + 13'b0000_???????1?: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b0000_??????10?: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b0000_?????100?: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b0000_????1000?: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b0000_???10000?: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b0000_??100000?: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b0000_?1000000?: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b0000_10000000?: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + 13'b0000_000000001: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b0001_??????1??: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b0001_?????10??: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b0001_????100??: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b0001_???1000??: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b0001_??10000??: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b0001_?100000??: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b0001_1000000??: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + 13'b0001_0000000?1: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b0001_000000010: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b0010_?????1???: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b0010_????10???: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b0010_???100???: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b0010_??1000???: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b0010_?10000???: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b0010_100000???: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + 13'b0010_000000??1: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b0010_000000?10: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b0010_000000100: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b0011_????1????: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b0011_???10????: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b0011_??100????: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b0011_?1000????: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b0011_10000????: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + 13'b0011_00000???1: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b0011_00000??10: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b0011_00000?100: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b0011_000001000: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b0100_???1?????: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b0100_??10?????: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b0100_?100?????: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b0100_1000?????: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + 13'b0100_0000????1: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b0100_0000???10: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b0100_0000??100: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b0100_0000?1000: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b0100_000010000: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b0101_??1??????: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b0101_?10??????: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b0101_100??????: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + 13'b0101_000?????1: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b0101_000????10: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b0101_000???100: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b0101_000??1000: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b0101_000?10000: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b0101_000100000: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b0110_?1???????: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b0110_10???????: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + 13'b0110_00??????1: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b0110_00?????10: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b0110_00????100: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b0110_00???1000: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b0110_00??10000: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b0110_00?100000: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b0110_001000000: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b0111_1????????: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + 13'b0111_0???????1: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b0111_0??????10: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b0111_0?????100: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b0111_0????1000: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b0111_0???10000: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b0111_0??100000: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b0111_0?1000000: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b0111_010000000: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b1000_????????1: begin sel_one_hot_n= 9'b000000001; tag_o = (lg_inputs_p) ' (0); end + 13'b1000_???????10: begin sel_one_hot_n= 9'b000000010; tag_o = (lg_inputs_p) ' (1); end + 13'b1000_??????100: begin sel_one_hot_n= 9'b000000100; tag_o = (lg_inputs_p) ' (2); end + 13'b1000_?????1000: begin sel_one_hot_n= 9'b000001000; tag_o = (lg_inputs_p) ' (3); end + 13'b1000_????10000: begin sel_one_hot_n= 9'b000010000; tag_o = (lg_inputs_p) ' (4); end + 13'b1000_???100000: begin sel_one_hot_n= 9'b000100000; tag_o = (lg_inputs_p) ' (5); end + 13'b1000_??1000000: begin sel_one_hot_n= 9'b001000000; tag_o = (lg_inputs_p) ' (6); end + 13'b1000_?10000000: begin sel_one_hot_n= 9'b010000000; tag_o = (lg_inputs_p) ' (7); end + 13'b1000_100000000: begin sel_one_hot_n= 9'b100000000; tag_o = (lg_inputs_p) ' (8); end + default: begin sel_one_hot_n= {9{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {9{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 4'b0000 : hold_on_sr = ( reqs_i == 9'b010000000 ); + 4'b0001 : hold_on_sr = ( reqs_i == 9'b001000000 ); + 4'b0010 : hold_on_sr = ( reqs_i == 9'b000100000 ); + 4'b0011 : hold_on_sr = ( reqs_i == 9'b000010000 ); + 4'b0100 : hold_on_sr = ( reqs_i == 9'b000001000 ); + 4'b0101 : hold_on_sr = ( reqs_i == 9'b000000100 ); + 4'b0110 : hold_on_sr = ( reqs_i == 9'b000000010 ); + 4'b0111 : hold_on_sr = ( reqs_i == 9'b000000001 ); + 4'b1000 : hold_on_sr = ( reqs_i == 9'b100000000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_9 + assign reset_on_sr = ( reqs_i == 9'b010000000 ) + | ( reqs_i == 9'b001000000 ) + | ( reqs_i == 9'b000100000 ) + | ( reqs_i == 9'b000010000 ) + | ( reqs_i == 9'b000001000 ) + | ( reqs_i == 9'b000000100 ) + | ( reqs_i == 9'b000000010 ) + | ( reqs_i == 9'b000000001 ) + | ( reqs_i == 9'b100000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_9 + +if(inputs_p == 10) +begin: inputs_10 + +logic [10-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 14'b????_0000000000: begin sel_one_hot_n = 10'b0000000000; tag_o = (lg_inputs_p) ' (0); end // X + 14'b0000_????????1?: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b0000_???????10?: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b0000_??????100?: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b0000_?????1000?: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b0000_????10000?: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b0000_???100000?: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b0000_??1000000?: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b0000_?10000000?: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b0000_100000000?: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b0000_0000000001: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b0001_???????1??: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b0001_??????10??: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b0001_?????100??: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b0001_????1000??: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b0001_???10000??: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b0001_??100000??: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b0001_?1000000??: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b0001_10000000??: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b0001_00000000?1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b0001_0000000010: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b0010_??????1???: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b0010_?????10???: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b0010_????100???: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b0010_???1000???: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b0010_??10000???: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b0010_?100000???: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b0010_1000000???: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b0010_0000000??1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b0010_0000000?10: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b0010_0000000100: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b0011_?????1????: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b0011_????10????: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b0011_???100????: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b0011_??1000????: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b0011_?10000????: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b0011_100000????: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b0011_000000???1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b0011_000000??10: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b0011_000000?100: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b0011_0000001000: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b0100_????1?????: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b0100_???10?????: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b0100_??100?????: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b0100_?1000?????: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b0100_10000?????: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b0100_00000????1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b0100_00000???10: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b0100_00000??100: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b0100_00000?1000: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b0100_0000010000: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b0101_???1??????: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b0101_??10??????: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b0101_?100??????: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b0101_1000??????: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b0101_0000?????1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b0101_0000????10: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b0101_0000???100: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b0101_0000??1000: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b0101_0000?10000: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b0101_0000100000: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b0110_??1???????: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b0110_?10???????: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b0110_100???????: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b0110_000??????1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b0110_000?????10: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b0110_000????100: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b0110_000???1000: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b0110_000??10000: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b0110_000?100000: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b0110_0001000000: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b0111_?1????????: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b0111_10????????: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b0111_00???????1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b0111_00??????10: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b0111_00?????100: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b0111_00????1000: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b0111_00???10000: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b0111_00??100000: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b0111_00?1000000: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b0111_0010000000: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b1000_1?????????: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + 14'b1000_0????????1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b1000_0???????10: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b1000_0??????100: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b1000_0?????1000: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b1000_0????10000: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b1000_0???100000: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b1000_0??1000000: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b1000_0?10000000: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b1000_0100000000: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b1001_?????????1: begin sel_one_hot_n= 10'b0000000001; tag_o = (lg_inputs_p) ' (0); end + 14'b1001_????????10: begin sel_one_hot_n= 10'b0000000010; tag_o = (lg_inputs_p) ' (1); end + 14'b1001_???????100: begin sel_one_hot_n= 10'b0000000100; tag_o = (lg_inputs_p) ' (2); end + 14'b1001_??????1000: begin sel_one_hot_n= 10'b0000001000; tag_o = (lg_inputs_p) ' (3); end + 14'b1001_?????10000: begin sel_one_hot_n= 10'b0000010000; tag_o = (lg_inputs_p) ' (4); end + 14'b1001_????100000: begin sel_one_hot_n= 10'b0000100000; tag_o = (lg_inputs_p) ' (5); end + 14'b1001_???1000000: begin sel_one_hot_n= 10'b0001000000; tag_o = (lg_inputs_p) ' (6); end + 14'b1001_??10000000: begin sel_one_hot_n= 10'b0010000000; tag_o = (lg_inputs_p) ' (7); end + 14'b1001_?100000000: begin sel_one_hot_n= 10'b0100000000; tag_o = (lg_inputs_p) ' (8); end + 14'b1001_1000000000: begin sel_one_hot_n= 10'b1000000000; tag_o = (lg_inputs_p) ' (9); end + default: begin sel_one_hot_n= {10{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {10{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 4'b0000 : hold_on_sr = ( reqs_i == 10'b0100000000 ); + 4'b0001 : hold_on_sr = ( reqs_i == 10'b0010000000 ); + 4'b0010 : hold_on_sr = ( reqs_i == 10'b0001000000 ); + 4'b0011 : hold_on_sr = ( reqs_i == 10'b0000100000 ); + 4'b0100 : hold_on_sr = ( reqs_i == 10'b0000010000 ); + 4'b0101 : hold_on_sr = ( reqs_i == 10'b0000001000 ); + 4'b0110 : hold_on_sr = ( reqs_i == 10'b0000000100 ); + 4'b0111 : hold_on_sr = ( reqs_i == 10'b0000000010 ); + 4'b1000 : hold_on_sr = ( reqs_i == 10'b0000000001 ); + 4'b1001 : hold_on_sr = ( reqs_i == 10'b1000000000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_10 + assign reset_on_sr = ( reqs_i == 10'b0100000000 ) + | ( reqs_i == 10'b0010000000 ) + | ( reqs_i == 10'b0001000000 ) + | ( reqs_i == 10'b0000100000 ) + | ( reqs_i == 10'b0000010000 ) + | ( reqs_i == 10'b0000001000 ) + | ( reqs_i == 10'b0000000100 ) + | ( reqs_i == 10'b0000000010 ) + | ( reqs_i == 10'b0000000001 ) + | ( reqs_i == 10'b1000000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_10 + +if(inputs_p == 11) +begin: inputs_11 + +logic [11-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 15'b????_00000000000: begin sel_one_hot_n = 11'b00000000000; tag_o = (lg_inputs_p) ' (0); end // X + 15'b0000_?????????1?: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b0000_????????10?: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b0000_???????100?: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b0000_??????1000?: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b0000_?????10000?: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b0000_????100000?: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b0000_???1000000?: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b0000_??10000000?: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b0000_?100000000?: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b0000_1000000000?: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b0000_00000000001: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b0001_????????1??: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b0001_???????10??: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b0001_??????100??: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b0001_?????1000??: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b0001_????10000??: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b0001_???100000??: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b0001_??1000000??: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b0001_?10000000??: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b0001_100000000??: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b0001_000000000?1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b0001_00000000010: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b0010_???????1???: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b0010_??????10???: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b0010_?????100???: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b0010_????1000???: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b0010_???10000???: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b0010_??100000???: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b0010_?1000000???: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b0010_10000000???: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b0010_00000000??1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b0010_00000000?10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b0010_00000000100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b0011_??????1????: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b0011_?????10????: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b0011_????100????: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b0011_???1000????: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b0011_??10000????: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b0011_?100000????: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b0011_1000000????: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b0011_0000000???1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b0011_0000000??10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b0011_0000000?100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b0011_00000001000: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b0100_?????1?????: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b0100_????10?????: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b0100_???100?????: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b0100_??1000?????: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b0100_?10000?????: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b0100_100000?????: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b0100_000000????1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b0100_000000???10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b0100_000000??100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b0100_000000?1000: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b0100_00000010000: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b0101_????1??????: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b0101_???10??????: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b0101_??100??????: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b0101_?1000??????: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b0101_10000??????: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b0101_00000?????1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b0101_00000????10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b0101_00000???100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b0101_00000??1000: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b0101_00000?10000: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b0101_00000100000: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b0110_???1???????: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b0110_??10???????: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b0110_?100???????: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b0110_1000???????: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b0110_0000??????1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b0110_0000?????10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b0110_0000????100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b0110_0000???1000: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b0110_0000??10000: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b0110_0000?100000: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b0110_00001000000: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b0111_??1????????: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b0111_?10????????: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b0111_100????????: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b0111_000???????1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b0111_000??????10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b0111_000?????100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b0111_000????1000: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b0111_000???10000: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b0111_000??100000: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b0111_000?1000000: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b0111_00010000000: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b1000_?1?????????: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b1000_10?????????: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b1000_00????????1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b1000_00???????10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b1000_00??????100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b1000_00?????1000: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b1000_00????10000: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b1000_00???100000: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b1000_00??1000000: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b1000_00?10000000: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b1000_00100000000: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b1001_1??????????: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + 15'b1001_0?????????1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b1001_0????????10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b1001_0???????100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b1001_0??????1000: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b1001_0?????10000: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b1001_0????100000: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b1001_0???1000000: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b1001_0??10000000: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b1001_0?100000000: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b1001_01000000000: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b1010_??????????1: begin sel_one_hot_n= 11'b00000000001; tag_o = (lg_inputs_p) ' (0); end + 15'b1010_?????????10: begin sel_one_hot_n= 11'b00000000010; tag_o = (lg_inputs_p) ' (1); end + 15'b1010_????????100: begin sel_one_hot_n= 11'b00000000100; tag_o = (lg_inputs_p) ' (2); end + 15'b1010_???????1000: begin sel_one_hot_n= 11'b00000001000; tag_o = (lg_inputs_p) ' (3); end + 15'b1010_??????10000: begin sel_one_hot_n= 11'b00000010000; tag_o = (lg_inputs_p) ' (4); end + 15'b1010_?????100000: begin sel_one_hot_n= 11'b00000100000; tag_o = (lg_inputs_p) ' (5); end + 15'b1010_????1000000: begin sel_one_hot_n= 11'b00001000000; tag_o = (lg_inputs_p) ' (6); end + 15'b1010_???10000000: begin sel_one_hot_n= 11'b00010000000; tag_o = (lg_inputs_p) ' (7); end + 15'b1010_??100000000: begin sel_one_hot_n= 11'b00100000000; tag_o = (lg_inputs_p) ' (8); end + 15'b1010_?1000000000: begin sel_one_hot_n= 11'b01000000000; tag_o = (lg_inputs_p) ' (9); end + 15'b1010_10000000000: begin sel_one_hot_n= 11'b10000000000; tag_o = (lg_inputs_p) ' (10); end + default: begin sel_one_hot_n= {11{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {11{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 4'b0000 : hold_on_sr = ( reqs_i == 11'b01000000000 ); + 4'b0001 : hold_on_sr = ( reqs_i == 11'b00100000000 ); + 4'b0010 : hold_on_sr = ( reqs_i == 11'b00010000000 ); + 4'b0011 : hold_on_sr = ( reqs_i == 11'b00001000000 ); + 4'b0100 : hold_on_sr = ( reqs_i == 11'b00000100000 ); + 4'b0101 : hold_on_sr = ( reqs_i == 11'b00000010000 ); + 4'b0110 : hold_on_sr = ( reqs_i == 11'b00000001000 ); + 4'b0111 : hold_on_sr = ( reqs_i == 11'b00000000100 ); + 4'b1000 : hold_on_sr = ( reqs_i == 11'b00000000010 ); + 4'b1001 : hold_on_sr = ( reqs_i == 11'b00000000001 ); + 4'b1010 : hold_on_sr = ( reqs_i == 11'b10000000000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_11 + assign reset_on_sr = ( reqs_i == 11'b01000000000 ) + | ( reqs_i == 11'b00100000000 ) + | ( reqs_i == 11'b00010000000 ) + | ( reqs_i == 11'b00001000000 ) + | ( reqs_i == 11'b00000100000 ) + | ( reqs_i == 11'b00000010000 ) + | ( reqs_i == 11'b00000001000 ) + | ( reqs_i == 11'b00000000100 ) + | ( reqs_i == 11'b00000000010 ) + | ( reqs_i == 11'b00000000001 ) + | ( reqs_i == 11'b10000000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_11 + +if(inputs_p == 12) +begin: inputs_12 + +logic [12-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 16'b????_000000000000: begin sel_one_hot_n = 12'b000000000000; tag_o = (lg_inputs_p) ' (0); end // X + 16'b0000_??????????1?: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b0000_?????????10?: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b0000_????????100?: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b0000_???????1000?: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b0000_??????10000?: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b0000_?????100000?: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b0000_????1000000?: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b0000_???10000000?: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b0000_??100000000?: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b0000_?1000000000?: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b0000_10000000000?: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b0000_000000000001: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b0001_?????????1??: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b0001_????????10??: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b0001_???????100??: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b0001_??????1000??: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b0001_?????10000??: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b0001_????100000??: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b0001_???1000000??: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b0001_??10000000??: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b0001_?100000000??: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b0001_1000000000??: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b0001_0000000000?1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b0001_000000000010: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b0010_????????1???: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b0010_???????10???: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b0010_??????100???: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b0010_?????1000???: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b0010_????10000???: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b0010_???100000???: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b0010_??1000000???: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b0010_?10000000???: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b0010_100000000???: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b0010_000000000??1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b0010_000000000?10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b0010_000000000100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b0011_???????1????: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b0011_??????10????: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b0011_?????100????: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b0011_????1000????: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b0011_???10000????: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b0011_??100000????: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b0011_?1000000????: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b0011_10000000????: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b0011_00000000???1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b0011_00000000??10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b0011_00000000?100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b0011_000000001000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b0100_??????1?????: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b0100_?????10?????: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b0100_????100?????: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b0100_???1000?????: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b0100_??10000?????: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b0100_?100000?????: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b0100_1000000?????: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b0100_0000000????1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b0100_0000000???10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b0100_0000000??100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b0100_0000000?1000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b0100_000000010000: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b0101_?????1??????: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b0101_????10??????: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b0101_???100??????: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b0101_??1000??????: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b0101_?10000??????: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b0101_100000??????: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b0101_000000?????1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b0101_000000????10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b0101_000000???100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b0101_000000??1000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b0101_000000?10000: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b0101_000000100000: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b0110_????1???????: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b0110_???10???????: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b0110_??100???????: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b0110_?1000???????: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b0110_10000???????: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b0110_00000??????1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b0110_00000?????10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b0110_00000????100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b0110_00000???1000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b0110_00000??10000: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b0110_00000?100000: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b0110_000001000000: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b0111_???1????????: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b0111_??10????????: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b0111_?100????????: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b0111_1000????????: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b0111_0000???????1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b0111_0000??????10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b0111_0000?????100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b0111_0000????1000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b0111_0000???10000: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b0111_0000??100000: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b0111_0000?1000000: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b0111_000010000000: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b1000_??1?????????: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b1000_?10?????????: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b1000_100?????????: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b1000_000????????1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b1000_000???????10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b1000_000??????100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b1000_000?????1000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b1000_000????10000: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b1000_000???100000: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b1000_000??1000000: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b1000_000?10000000: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b1000_000100000000: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b1001_?1??????????: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b1001_10??????????: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b1001_00?????????1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b1001_00????????10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b1001_00???????100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b1001_00??????1000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b1001_00?????10000: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b1001_00????100000: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b1001_00???1000000: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b1001_00??10000000: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b1001_00?100000000: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b1001_001000000000: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b1010_1???????????: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + 16'b1010_0??????????1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b1010_0?????????10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b1010_0????????100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b1010_0???????1000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b1010_0??????10000: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b1010_0?????100000: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b1010_0????1000000: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b1010_0???10000000: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b1010_0??100000000: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b1010_0?1000000000: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b1010_010000000000: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b1011_???????????1: begin sel_one_hot_n= 12'b000000000001; tag_o = (lg_inputs_p) ' (0); end + 16'b1011_??????????10: begin sel_one_hot_n= 12'b000000000010; tag_o = (lg_inputs_p) ' (1); end + 16'b1011_?????????100: begin sel_one_hot_n= 12'b000000000100; tag_o = (lg_inputs_p) ' (2); end + 16'b1011_????????1000: begin sel_one_hot_n= 12'b000000001000; tag_o = (lg_inputs_p) ' (3); end + 16'b1011_???????10000: begin sel_one_hot_n= 12'b000000010000; tag_o = (lg_inputs_p) ' (4); end + 16'b1011_??????100000: begin sel_one_hot_n= 12'b000000100000; tag_o = (lg_inputs_p) ' (5); end + 16'b1011_?????1000000: begin sel_one_hot_n= 12'b000001000000; tag_o = (lg_inputs_p) ' (6); end + 16'b1011_????10000000: begin sel_one_hot_n= 12'b000010000000; tag_o = (lg_inputs_p) ' (7); end + 16'b1011_???100000000: begin sel_one_hot_n= 12'b000100000000; tag_o = (lg_inputs_p) ' (8); end + 16'b1011_??1000000000: begin sel_one_hot_n= 12'b001000000000; tag_o = (lg_inputs_p) ' (9); end + 16'b1011_?10000000000: begin sel_one_hot_n= 12'b010000000000; tag_o = (lg_inputs_p) ' (10); end + 16'b1011_100000000000: begin sel_one_hot_n= 12'b100000000000; tag_o = (lg_inputs_p) ' (11); end + default: begin sel_one_hot_n= {12{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {12{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 4'b0000 : hold_on_sr = ( reqs_i == 12'b010000000000 ); + 4'b0001 : hold_on_sr = ( reqs_i == 12'b001000000000 ); + 4'b0010 : hold_on_sr = ( reqs_i == 12'b000100000000 ); + 4'b0011 : hold_on_sr = ( reqs_i == 12'b000010000000 ); + 4'b0100 : hold_on_sr = ( reqs_i == 12'b000001000000 ); + 4'b0101 : hold_on_sr = ( reqs_i == 12'b000000100000 ); + 4'b0110 : hold_on_sr = ( reqs_i == 12'b000000010000 ); + 4'b0111 : hold_on_sr = ( reqs_i == 12'b000000001000 ); + 4'b1000 : hold_on_sr = ( reqs_i == 12'b000000000100 ); + 4'b1001 : hold_on_sr = ( reqs_i == 12'b000000000010 ); + 4'b1010 : hold_on_sr = ( reqs_i == 12'b000000000001 ); + 4'b1011 : hold_on_sr = ( reqs_i == 12'b100000000000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_12 + assign reset_on_sr = ( reqs_i == 12'b010000000000 ) + | ( reqs_i == 12'b001000000000 ) + | ( reqs_i == 12'b000100000000 ) + | ( reqs_i == 12'b000010000000 ) + | ( reqs_i == 12'b000001000000 ) + | ( reqs_i == 12'b000000100000 ) + | ( reqs_i == 12'b000000010000 ) + | ( reqs_i == 12'b000000001000 ) + | ( reqs_i == 12'b000000000100 ) + | ( reqs_i == 12'b000000000010 ) + | ( reqs_i == 12'b000000000001 ) + | ( reqs_i == 12'b100000000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_12 + +if(inputs_p == 13) +begin: inputs_13 + +logic [13-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 17'b????_0000000000000: begin sel_one_hot_n = 13'b0000000000000; tag_o = (lg_inputs_p) ' (0); end // X + 17'b0000_???????????1?: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b0000_??????????10?: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b0000_?????????100?: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b0000_????????1000?: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b0000_???????10000?: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b0000_??????100000?: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b0000_?????1000000?: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b0000_????10000000?: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b0000_???100000000?: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b0000_??1000000000?: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b0000_?10000000000?: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b0000_100000000000?: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b0000_0000000000001: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b0001_??????????1??: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b0001_?????????10??: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b0001_????????100??: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b0001_???????1000??: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b0001_??????10000??: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b0001_?????100000??: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b0001_????1000000??: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b0001_???10000000??: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b0001_??100000000??: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b0001_?1000000000??: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b0001_10000000000??: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b0001_00000000000?1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b0001_0000000000010: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b0010_?????????1???: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b0010_????????10???: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b0010_???????100???: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b0010_??????1000???: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b0010_?????10000???: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b0010_????100000???: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b0010_???1000000???: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b0010_??10000000???: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b0010_?100000000???: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b0010_1000000000???: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b0010_0000000000??1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b0010_0000000000?10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b0010_0000000000100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b0011_????????1????: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b0011_???????10????: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b0011_??????100????: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b0011_?????1000????: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b0011_????10000????: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b0011_???100000????: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b0011_??1000000????: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b0011_?10000000????: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b0011_100000000????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b0011_000000000???1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b0011_000000000??10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b0011_000000000?100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b0011_0000000001000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b0100_???????1?????: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b0100_??????10?????: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b0100_?????100?????: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b0100_????1000?????: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b0100_???10000?????: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b0100_??100000?????: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b0100_?1000000?????: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b0100_10000000?????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b0100_00000000????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b0100_00000000???10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b0100_00000000??100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b0100_00000000?1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b0100_0000000010000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b0101_??????1??????: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b0101_?????10??????: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b0101_????100??????: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b0101_???1000??????: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b0101_??10000??????: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b0101_?100000??????: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b0101_1000000??????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b0101_0000000?????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b0101_0000000????10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b0101_0000000???100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b0101_0000000??1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b0101_0000000?10000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b0101_0000000100000: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b0110_?????1???????: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b0110_????10???????: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b0110_???100???????: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b0110_??1000???????: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b0110_?10000???????: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b0110_100000???????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b0110_000000??????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b0110_000000?????10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b0110_000000????100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b0110_000000???1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b0110_000000??10000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b0110_000000?100000: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b0110_0000001000000: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b0111_????1????????: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b0111_???10????????: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b0111_??100????????: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b0111_?1000????????: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b0111_10000????????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b0111_00000???????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b0111_00000??????10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b0111_00000?????100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b0111_00000????1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b0111_00000???10000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b0111_00000??100000: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b0111_00000?1000000: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b0111_0000010000000: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b1000_???1?????????: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b1000_??10?????????: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b1000_?100?????????: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b1000_1000?????????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b1000_0000????????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b1000_0000???????10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b1000_0000??????100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b1000_0000?????1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b1000_0000????10000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b1000_0000???100000: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b1000_0000??1000000: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b1000_0000?10000000: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b1000_0000100000000: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b1001_??1??????????: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b1001_?10??????????: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b1001_100??????????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b1001_000?????????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b1001_000????????10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b1001_000???????100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b1001_000??????1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b1001_000?????10000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b1001_000????100000: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b1001_000???1000000: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b1001_000??10000000: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b1001_000?100000000: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b1001_0001000000000: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b1010_?1???????????: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b1010_10???????????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b1010_00??????????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b1010_00?????????10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b1010_00????????100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b1010_00???????1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b1010_00??????10000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b1010_00?????100000: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b1010_00????1000000: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b1010_00???10000000: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b1010_00??100000000: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b1010_00?1000000000: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b1010_0010000000000: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b1011_1????????????: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + 17'b1011_0???????????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b1011_0??????????10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b1011_0?????????100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b1011_0????????1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b1011_0???????10000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b1011_0??????100000: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b1011_0?????1000000: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b1011_0????10000000: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b1011_0???100000000: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b1011_0??1000000000: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b1011_0?10000000000: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b1011_0100000000000: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b1100_????????????1: begin sel_one_hot_n= 13'b0000000000001; tag_o = (lg_inputs_p) ' (0); end + 17'b1100_???????????10: begin sel_one_hot_n= 13'b0000000000010; tag_o = (lg_inputs_p) ' (1); end + 17'b1100_??????????100: begin sel_one_hot_n= 13'b0000000000100; tag_o = (lg_inputs_p) ' (2); end + 17'b1100_?????????1000: begin sel_one_hot_n= 13'b0000000001000; tag_o = (lg_inputs_p) ' (3); end + 17'b1100_????????10000: begin sel_one_hot_n= 13'b0000000010000; tag_o = (lg_inputs_p) ' (4); end + 17'b1100_???????100000: begin sel_one_hot_n= 13'b0000000100000; tag_o = (lg_inputs_p) ' (5); end + 17'b1100_??????1000000: begin sel_one_hot_n= 13'b0000001000000; tag_o = (lg_inputs_p) ' (6); end + 17'b1100_?????10000000: begin sel_one_hot_n= 13'b0000010000000; tag_o = (lg_inputs_p) ' (7); end + 17'b1100_????100000000: begin sel_one_hot_n= 13'b0000100000000; tag_o = (lg_inputs_p) ' (8); end + 17'b1100_???1000000000: begin sel_one_hot_n= 13'b0001000000000; tag_o = (lg_inputs_p) ' (9); end + 17'b1100_??10000000000: begin sel_one_hot_n= 13'b0010000000000; tag_o = (lg_inputs_p) ' (10); end + 17'b1100_?100000000000: begin sel_one_hot_n= 13'b0100000000000; tag_o = (lg_inputs_p) ' (11); end + 17'b1100_1000000000000: begin sel_one_hot_n= 13'b1000000000000; tag_o = (lg_inputs_p) ' (12); end + default: begin sel_one_hot_n= {13{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {13{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 4'b0000 : hold_on_sr = ( reqs_i == 13'b0100000000000 ); + 4'b0001 : hold_on_sr = ( reqs_i == 13'b0010000000000 ); + 4'b0010 : hold_on_sr = ( reqs_i == 13'b0001000000000 ); + 4'b0011 : hold_on_sr = ( reqs_i == 13'b0000100000000 ); + 4'b0100 : hold_on_sr = ( reqs_i == 13'b0000010000000 ); + 4'b0101 : hold_on_sr = ( reqs_i == 13'b0000001000000 ); + 4'b0110 : hold_on_sr = ( reqs_i == 13'b0000000100000 ); + 4'b0111 : hold_on_sr = ( reqs_i == 13'b0000000010000 ); + 4'b1000 : hold_on_sr = ( reqs_i == 13'b0000000001000 ); + 4'b1001 : hold_on_sr = ( reqs_i == 13'b0000000000100 ); + 4'b1010 : hold_on_sr = ( reqs_i == 13'b0000000000010 ); + 4'b1011 : hold_on_sr = ( reqs_i == 13'b0000000000001 ); + 4'b1100 : hold_on_sr = ( reqs_i == 13'b1000000000000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_13 + assign reset_on_sr = ( reqs_i == 13'b0100000000000 ) + | ( reqs_i == 13'b0010000000000 ) + | ( reqs_i == 13'b0001000000000 ) + | ( reqs_i == 13'b0000100000000 ) + | ( reqs_i == 13'b0000010000000 ) + | ( reqs_i == 13'b0000001000000 ) + | ( reqs_i == 13'b0000000100000 ) + | ( reqs_i == 13'b0000000010000 ) + | ( reqs_i == 13'b0000000001000 ) + | ( reqs_i == 13'b0000000000100 ) + | ( reqs_i == 13'b0000000000010 ) + | ( reqs_i == 13'b0000000000001 ) + | ( reqs_i == 13'b1000000000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_13 + +if(inputs_p == 14) +begin: inputs_14 + +logic [14-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 18'b????_00000000000000: begin sel_one_hot_n = 14'b00000000000000; tag_o = (lg_inputs_p) ' (0); end // X + 18'b0000_????????????1?: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b0000_???????????10?: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b0000_??????????100?: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b0000_?????????1000?: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b0000_????????10000?: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b0000_???????100000?: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b0000_??????1000000?: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b0000_?????10000000?: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b0000_????100000000?: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b0000_???1000000000?: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b0000_??10000000000?: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b0000_?100000000000?: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b0000_1000000000000?: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b0000_00000000000001: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b0001_???????????1??: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b0001_??????????10??: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b0001_?????????100??: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b0001_????????1000??: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b0001_???????10000??: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b0001_??????100000??: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b0001_?????1000000??: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b0001_????10000000??: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b0001_???100000000??: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b0001_??1000000000??: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b0001_?10000000000??: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b0001_100000000000??: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b0001_000000000000?1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b0001_00000000000010: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b0010_??????????1???: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b0010_?????????10???: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b0010_????????100???: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b0010_???????1000???: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b0010_??????10000???: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b0010_?????100000???: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b0010_????1000000???: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b0010_???10000000???: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b0010_??100000000???: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b0010_?1000000000???: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b0010_10000000000???: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b0010_00000000000??1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b0010_00000000000?10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b0010_00000000000100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b0011_?????????1????: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b0011_????????10????: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b0011_???????100????: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b0011_??????1000????: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b0011_?????10000????: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b0011_????100000????: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b0011_???1000000????: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b0011_??10000000????: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b0011_?100000000????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b0011_1000000000????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b0011_0000000000???1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b0011_0000000000??10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b0011_0000000000?100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b0011_00000000001000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b0100_????????1?????: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b0100_???????10?????: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b0100_??????100?????: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b0100_?????1000?????: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b0100_????10000?????: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b0100_???100000?????: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b0100_??1000000?????: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b0100_?10000000?????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b0100_100000000?????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b0100_000000000????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b0100_000000000???10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b0100_000000000??100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b0100_000000000?1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b0100_00000000010000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b0101_???????1??????: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b0101_??????10??????: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b0101_?????100??????: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b0101_????1000??????: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b0101_???10000??????: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b0101_??100000??????: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b0101_?1000000??????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b0101_10000000??????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b0101_00000000?????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b0101_00000000????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b0101_00000000???100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b0101_00000000??1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b0101_00000000?10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b0101_00000000100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b0110_??????1???????: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b0110_?????10???????: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b0110_????100???????: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b0110_???1000???????: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b0110_??10000???????: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b0110_?100000???????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b0110_1000000???????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b0110_0000000??????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b0110_0000000?????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b0110_0000000????100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b0110_0000000???1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b0110_0000000??10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b0110_0000000?100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b0110_00000001000000: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b0111_?????1????????: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b0111_????10????????: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b0111_???100????????: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b0111_??1000????????: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b0111_?10000????????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b0111_100000????????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b0111_000000???????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b0111_000000??????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b0111_000000?????100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b0111_000000????1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b0111_000000???10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b0111_000000??100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b0111_000000?1000000: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b0111_00000010000000: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b1000_????1?????????: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b1000_???10?????????: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b1000_??100?????????: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b1000_?1000?????????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b1000_10000?????????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b1000_00000????????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b1000_00000???????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b1000_00000??????100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b1000_00000?????1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b1000_00000????10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b1000_00000???100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b1000_00000??1000000: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b1000_00000?10000000: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b1000_00000100000000: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b1001_???1??????????: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b1001_??10??????????: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b1001_?100??????????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b1001_1000??????????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b1001_0000?????????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b1001_0000????????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b1001_0000???????100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b1001_0000??????1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b1001_0000?????10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b1001_0000????100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b1001_0000???1000000: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b1001_0000??10000000: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b1001_0000?100000000: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b1001_00001000000000: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b1010_??1???????????: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b1010_?10???????????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b1010_100???????????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b1010_000??????????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b1010_000?????????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b1010_000????????100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b1010_000???????1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b1010_000??????10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b1010_000?????100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b1010_000????1000000: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b1010_000???10000000: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b1010_000??100000000: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b1010_000?1000000000: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b1010_00010000000000: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b1011_?1????????????: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b1011_10????????????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b1011_00???????????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b1011_00??????????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b1011_00?????????100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b1011_00????????1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b1011_00???????10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b1011_00??????100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b1011_00?????1000000: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b1011_00????10000000: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b1011_00???100000000: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b1011_00??1000000000: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b1011_00?10000000000: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b1011_00100000000000: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b1100_1?????????????: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + 18'b1100_0????????????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b1100_0???????????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b1100_0??????????100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b1100_0?????????1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b1100_0????????10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b1100_0???????100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b1100_0??????1000000: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b1100_0?????10000000: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b1100_0????100000000: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b1100_0???1000000000: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b1100_0??10000000000: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b1100_0?100000000000: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b1100_01000000000000: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b1101_?????????????1: begin sel_one_hot_n= 14'b00000000000001; tag_o = (lg_inputs_p) ' (0); end + 18'b1101_????????????10: begin sel_one_hot_n= 14'b00000000000010; tag_o = (lg_inputs_p) ' (1); end + 18'b1101_???????????100: begin sel_one_hot_n= 14'b00000000000100; tag_o = (lg_inputs_p) ' (2); end + 18'b1101_??????????1000: begin sel_one_hot_n= 14'b00000000001000; tag_o = (lg_inputs_p) ' (3); end + 18'b1101_?????????10000: begin sel_one_hot_n= 14'b00000000010000; tag_o = (lg_inputs_p) ' (4); end + 18'b1101_????????100000: begin sel_one_hot_n= 14'b00000000100000; tag_o = (lg_inputs_p) ' (5); end + 18'b1101_???????1000000: begin sel_one_hot_n= 14'b00000001000000; tag_o = (lg_inputs_p) ' (6); end + 18'b1101_??????10000000: begin sel_one_hot_n= 14'b00000010000000; tag_o = (lg_inputs_p) ' (7); end + 18'b1101_?????100000000: begin sel_one_hot_n= 14'b00000100000000; tag_o = (lg_inputs_p) ' (8); end + 18'b1101_????1000000000: begin sel_one_hot_n= 14'b00001000000000; tag_o = (lg_inputs_p) ' (9); end + 18'b1101_???10000000000: begin sel_one_hot_n= 14'b00010000000000; tag_o = (lg_inputs_p) ' (10); end + 18'b1101_??100000000000: begin sel_one_hot_n= 14'b00100000000000; tag_o = (lg_inputs_p) ' (11); end + 18'b1101_?1000000000000: begin sel_one_hot_n= 14'b01000000000000; tag_o = (lg_inputs_p) ' (12); end + 18'b1101_10000000000000: begin sel_one_hot_n= 14'b10000000000000; tag_o = (lg_inputs_p) ' (13); end + default: begin sel_one_hot_n= {14{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {14{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 4'b0000 : hold_on_sr = ( reqs_i == 14'b01000000000000 ); + 4'b0001 : hold_on_sr = ( reqs_i == 14'b00100000000000 ); + 4'b0010 : hold_on_sr = ( reqs_i == 14'b00010000000000 ); + 4'b0011 : hold_on_sr = ( reqs_i == 14'b00001000000000 ); + 4'b0100 : hold_on_sr = ( reqs_i == 14'b00000100000000 ); + 4'b0101 : hold_on_sr = ( reqs_i == 14'b00000010000000 ); + 4'b0110 : hold_on_sr = ( reqs_i == 14'b00000001000000 ); + 4'b0111 : hold_on_sr = ( reqs_i == 14'b00000000100000 ); + 4'b1000 : hold_on_sr = ( reqs_i == 14'b00000000010000 ); + 4'b1001 : hold_on_sr = ( reqs_i == 14'b00000000001000 ); + 4'b1010 : hold_on_sr = ( reqs_i == 14'b00000000000100 ); + 4'b1011 : hold_on_sr = ( reqs_i == 14'b00000000000010 ); + 4'b1100 : hold_on_sr = ( reqs_i == 14'b00000000000001 ); + 4'b1101 : hold_on_sr = ( reqs_i == 14'b10000000000000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_14 + assign reset_on_sr = ( reqs_i == 14'b01000000000000 ) + | ( reqs_i == 14'b00100000000000 ) + | ( reqs_i == 14'b00010000000000 ) + | ( reqs_i == 14'b00001000000000 ) + | ( reqs_i == 14'b00000100000000 ) + | ( reqs_i == 14'b00000010000000 ) + | ( reqs_i == 14'b00000001000000 ) + | ( reqs_i == 14'b00000000100000 ) + | ( reqs_i == 14'b00000000010000 ) + | ( reqs_i == 14'b00000000001000 ) + | ( reqs_i == 14'b00000000000100 ) + | ( reqs_i == 14'b00000000000010 ) + | ( reqs_i == 14'b00000000000001 ) + | ( reqs_i == 14'b10000000000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_14 + +if(inputs_p == 15) +begin: inputs_15 + +logic [15-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 19'b????_000000000000000: begin sel_one_hot_n = 15'b000000000000000; tag_o = (lg_inputs_p) ' (0); end // X + 19'b0000_?????????????1?: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b0000_????????????10?: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b0000_???????????100?: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b0000_??????????1000?: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b0000_?????????10000?: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b0000_????????100000?: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b0000_???????1000000?: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b0000_??????10000000?: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b0000_?????100000000?: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b0000_????1000000000?: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b0000_???10000000000?: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b0000_??100000000000?: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b0000_?1000000000000?: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b0000_10000000000000?: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b0000_000000000000001: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b0001_????????????1??: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b0001_???????????10??: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b0001_??????????100??: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b0001_?????????1000??: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b0001_????????10000??: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b0001_???????100000??: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b0001_??????1000000??: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b0001_?????10000000??: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b0001_????100000000??: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b0001_???1000000000??: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b0001_??10000000000??: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b0001_?100000000000??: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b0001_1000000000000??: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b0001_0000000000000?1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b0001_000000000000010: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b0010_???????????1???: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b0010_??????????10???: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b0010_?????????100???: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b0010_????????1000???: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b0010_???????10000???: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b0010_??????100000???: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b0010_?????1000000???: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b0010_????10000000???: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b0010_???100000000???: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b0010_??1000000000???: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b0010_?10000000000???: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b0010_100000000000???: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b0010_000000000000??1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b0010_000000000000?10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b0010_000000000000100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b0011_??????????1????: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b0011_?????????10????: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b0011_????????100????: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b0011_???????1000????: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b0011_??????10000????: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b0011_?????100000????: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b0011_????1000000????: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b0011_???10000000????: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b0011_??100000000????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b0011_?1000000000????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b0011_10000000000????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b0011_00000000000???1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b0011_00000000000??10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b0011_00000000000?100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b0011_000000000001000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b0100_?????????1?????: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b0100_????????10?????: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b0100_???????100?????: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b0100_??????1000?????: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b0100_?????10000?????: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b0100_????100000?????: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b0100_???1000000?????: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b0100_??10000000?????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b0100_?100000000?????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b0100_1000000000?????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b0100_0000000000????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b0100_0000000000???10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b0100_0000000000??100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b0100_0000000000?1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b0100_000000000010000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b0101_????????1??????: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b0101_???????10??????: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b0101_??????100??????: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b0101_?????1000??????: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b0101_????10000??????: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b0101_???100000??????: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b0101_??1000000??????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b0101_?10000000??????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b0101_100000000??????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b0101_000000000?????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b0101_000000000????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b0101_000000000???100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b0101_000000000??1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b0101_000000000?10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b0101_000000000100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b0110_???????1???????: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b0110_??????10???????: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b0110_?????100???????: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b0110_????1000???????: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b0110_???10000???????: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b0110_??100000???????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b0110_?1000000???????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b0110_10000000???????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b0110_00000000??????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b0110_00000000?????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b0110_00000000????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b0110_00000000???1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b0110_00000000??10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b0110_00000000?100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b0110_000000001000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b0111_??????1????????: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b0111_?????10????????: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b0111_????100????????: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b0111_???1000????????: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b0111_??10000????????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b0111_?100000????????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b0111_1000000????????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b0111_0000000???????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b0111_0000000??????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b0111_0000000?????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b0111_0000000????1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b0111_0000000???10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b0111_0000000??100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b0111_0000000?1000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b0111_000000010000000: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b1000_?????1?????????: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b1000_????10?????????: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b1000_???100?????????: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b1000_??1000?????????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b1000_?10000?????????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b1000_100000?????????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b1000_000000????????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b1000_000000???????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b1000_000000??????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b1000_000000?????1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b1000_000000????10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b1000_000000???100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b1000_000000??1000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b1000_000000?10000000: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b1000_000000100000000: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b1001_????1??????????: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b1001_???10??????????: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b1001_??100??????????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b1001_?1000??????????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b1001_10000??????????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b1001_00000?????????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b1001_00000????????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b1001_00000???????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b1001_00000??????1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b1001_00000?????10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b1001_00000????100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b1001_00000???1000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b1001_00000??10000000: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b1001_00000?100000000: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b1001_000001000000000: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b1010_???1???????????: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b1010_??10???????????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b1010_?100???????????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b1010_1000???????????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b1010_0000??????????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b1010_0000?????????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b1010_0000????????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b1010_0000???????1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b1010_0000??????10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b1010_0000?????100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b1010_0000????1000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b1010_0000???10000000: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b1010_0000??100000000: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b1010_0000?1000000000: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b1010_000010000000000: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b1011_??1????????????: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b1011_?10????????????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b1011_100????????????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b1011_000???????????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b1011_000??????????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b1011_000?????????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b1011_000????????1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b1011_000???????10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b1011_000??????100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b1011_000?????1000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b1011_000????10000000: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b1011_000???100000000: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b1011_000??1000000000: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b1011_000?10000000000: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b1011_000100000000000: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b1100_?1?????????????: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b1100_10?????????????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b1100_00????????????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b1100_00???????????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b1100_00??????????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b1100_00?????????1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b1100_00????????10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b1100_00???????100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b1100_00??????1000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b1100_00?????10000000: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b1100_00????100000000: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b1100_00???1000000000: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b1100_00??10000000000: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b1100_00?100000000000: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b1100_001000000000000: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b1101_1??????????????: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + 19'b1101_0?????????????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b1101_0????????????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b1101_0???????????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b1101_0??????????1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b1101_0?????????10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b1101_0????????100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b1101_0???????1000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b1101_0??????10000000: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b1101_0?????100000000: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b1101_0????1000000000: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b1101_0???10000000000: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b1101_0??100000000000: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b1101_0?1000000000000: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b1101_010000000000000: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b1110_??????????????1: begin sel_one_hot_n= 15'b000000000000001; tag_o = (lg_inputs_p) ' (0); end + 19'b1110_?????????????10: begin sel_one_hot_n= 15'b000000000000010; tag_o = (lg_inputs_p) ' (1); end + 19'b1110_????????????100: begin sel_one_hot_n= 15'b000000000000100; tag_o = (lg_inputs_p) ' (2); end + 19'b1110_???????????1000: begin sel_one_hot_n= 15'b000000000001000; tag_o = (lg_inputs_p) ' (3); end + 19'b1110_??????????10000: begin sel_one_hot_n= 15'b000000000010000; tag_o = (lg_inputs_p) ' (4); end + 19'b1110_?????????100000: begin sel_one_hot_n= 15'b000000000100000; tag_o = (lg_inputs_p) ' (5); end + 19'b1110_????????1000000: begin sel_one_hot_n= 15'b000000001000000; tag_o = (lg_inputs_p) ' (6); end + 19'b1110_???????10000000: begin sel_one_hot_n= 15'b000000010000000; tag_o = (lg_inputs_p) ' (7); end + 19'b1110_??????100000000: begin sel_one_hot_n= 15'b000000100000000; tag_o = (lg_inputs_p) ' (8); end + 19'b1110_?????1000000000: begin sel_one_hot_n= 15'b000001000000000; tag_o = (lg_inputs_p) ' (9); end + 19'b1110_????10000000000: begin sel_one_hot_n= 15'b000010000000000; tag_o = (lg_inputs_p) ' (10); end + 19'b1110_???100000000000: begin sel_one_hot_n= 15'b000100000000000; tag_o = (lg_inputs_p) ' (11); end + 19'b1110_??1000000000000: begin sel_one_hot_n= 15'b001000000000000; tag_o = (lg_inputs_p) ' (12); end + 19'b1110_?10000000000000: begin sel_one_hot_n= 15'b010000000000000; tag_o = (lg_inputs_p) ' (13); end + 19'b1110_100000000000000: begin sel_one_hot_n= 15'b100000000000000; tag_o = (lg_inputs_p) ' (14); end + default: begin sel_one_hot_n= {15{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {15{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 4'b0000 : hold_on_sr = ( reqs_i == 15'b010000000000000 ); + 4'b0001 : hold_on_sr = ( reqs_i == 15'b001000000000000 ); + 4'b0010 : hold_on_sr = ( reqs_i == 15'b000100000000000 ); + 4'b0011 : hold_on_sr = ( reqs_i == 15'b000010000000000 ); + 4'b0100 : hold_on_sr = ( reqs_i == 15'b000001000000000 ); + 4'b0101 : hold_on_sr = ( reqs_i == 15'b000000100000000 ); + 4'b0110 : hold_on_sr = ( reqs_i == 15'b000000010000000 ); + 4'b0111 : hold_on_sr = ( reqs_i == 15'b000000001000000 ); + 4'b1000 : hold_on_sr = ( reqs_i == 15'b000000000100000 ); + 4'b1001 : hold_on_sr = ( reqs_i == 15'b000000000010000 ); + 4'b1010 : hold_on_sr = ( reqs_i == 15'b000000000001000 ); + 4'b1011 : hold_on_sr = ( reqs_i == 15'b000000000000100 ); + 4'b1100 : hold_on_sr = ( reqs_i == 15'b000000000000010 ); + 4'b1101 : hold_on_sr = ( reqs_i == 15'b000000000000001 ); + 4'b1110 : hold_on_sr = ( reqs_i == 15'b100000000000000 ); + default : hold_on_sr = 1'b0; + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_15 + assign reset_on_sr = ( reqs_i == 15'b010000000000000 ) + | ( reqs_i == 15'b001000000000000 ) + | ( reqs_i == 15'b000100000000000 ) + | ( reqs_i == 15'b000010000000000 ) + | ( reqs_i == 15'b000001000000000 ) + | ( reqs_i == 15'b000000100000000 ) + | ( reqs_i == 15'b000000010000000 ) + | ( reqs_i == 15'b000000001000000 ) + | ( reqs_i == 15'b000000000100000 ) + | ( reqs_i == 15'b000000000010000 ) + | ( reqs_i == 15'b000000000001000 ) + | ( reqs_i == 15'b000000000000100 ) + | ( reqs_i == 15'b000000000000010 ) + | ( reqs_i == 15'b000000000000001 ) + | ( reqs_i == 15'b100000000000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_15 + +if(inputs_p == 16) +begin: inputs_16 + +logic [16-1: 0 ] sel_one_hot_n; + +always_comb +begin + unique casez({last_r, reqs_i}) + 20'b????_0000000000000000: begin sel_one_hot_n = 16'b0000000000000000; tag_o = (lg_inputs_p) ' (0); end // X + 20'b0000_??????????????1?: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b0000_?????????????10?: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b0000_????????????100?: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b0000_???????????1000?: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b0000_??????????10000?: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b0000_?????????100000?: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b0000_????????1000000?: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b0000_???????10000000?: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b0000_??????100000000?: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b0000_?????1000000000?: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b0000_????10000000000?: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b0000_???100000000000?: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b0000_??1000000000000?: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b0000_?10000000000000?: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b0000_100000000000000?: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b0000_0000000000000001: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b0001_?????????????1??: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b0001_????????????10??: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b0001_???????????100??: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b0001_??????????1000??: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b0001_?????????10000??: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b0001_????????100000??: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b0001_???????1000000??: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b0001_??????10000000??: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b0001_?????100000000??: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b0001_????1000000000??: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b0001_???10000000000??: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b0001_??100000000000??: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b0001_?1000000000000??: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b0001_10000000000000??: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b0001_00000000000000?1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b0001_0000000000000010: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b0010_????????????1???: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b0010_???????????10???: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b0010_??????????100???: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b0010_?????????1000???: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b0010_????????10000???: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b0010_???????100000???: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b0010_??????1000000???: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b0010_?????10000000???: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b0010_????100000000???: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b0010_???1000000000???: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b0010_??10000000000???: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b0010_?100000000000???: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b0010_1000000000000???: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b0010_0000000000000??1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b0010_0000000000000?10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b0010_0000000000000100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b0011_???????????1????: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b0011_??????????10????: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b0011_?????????100????: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b0011_????????1000????: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b0011_???????10000????: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b0011_??????100000????: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b0011_?????1000000????: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b0011_????10000000????: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b0011_???100000000????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b0011_??1000000000????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b0011_?10000000000????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b0011_100000000000????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b0011_000000000000???1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b0011_000000000000??10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b0011_000000000000?100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b0011_0000000000001000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b0100_??????????1?????: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b0100_?????????10?????: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b0100_????????100?????: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b0100_???????1000?????: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b0100_??????10000?????: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b0100_?????100000?????: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b0100_????1000000?????: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b0100_???10000000?????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b0100_??100000000?????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b0100_?1000000000?????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b0100_10000000000?????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b0100_00000000000????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b0100_00000000000???10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b0100_00000000000??100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b0100_00000000000?1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b0100_0000000000010000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b0101_?????????1??????: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b0101_????????10??????: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b0101_???????100??????: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b0101_??????1000??????: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b0101_?????10000??????: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b0101_????100000??????: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b0101_???1000000??????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b0101_??10000000??????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b0101_?100000000??????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b0101_1000000000??????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b0101_0000000000?????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b0101_0000000000????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b0101_0000000000???100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b0101_0000000000??1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b0101_0000000000?10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b0101_0000000000100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b0110_????????1???????: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b0110_???????10???????: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b0110_??????100???????: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b0110_?????1000???????: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b0110_????10000???????: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b0110_???100000???????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b0110_??1000000???????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b0110_?10000000???????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b0110_100000000???????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b0110_000000000??????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b0110_000000000?????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b0110_000000000????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b0110_000000000???1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b0110_000000000??10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b0110_000000000?100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b0110_0000000001000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b0111_???????1????????: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b0111_??????10????????: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b0111_?????100????????: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b0111_????1000????????: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b0111_???10000????????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b0111_??100000????????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b0111_?1000000????????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b0111_10000000????????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b0111_00000000???????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b0111_00000000??????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b0111_00000000?????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b0111_00000000????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b0111_00000000???10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b0111_00000000??100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b0111_00000000?1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b0111_0000000010000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1000_??????1?????????: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b1000_?????10?????????: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b1000_????100?????????: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b1000_???1000?????????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b1000_??10000?????????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b1000_?100000?????????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b1000_1000000?????????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b1000_0000000????????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b1000_0000000???????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b1000_0000000??????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b1000_0000000?????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b1000_0000000????10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b1000_0000000???100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b1000_0000000??1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b1000_0000000?10000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1000_0000000100000000: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b1001_?????1??????????: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b1001_????10??????????: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b1001_???100??????????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b1001_??1000??????????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b1001_?10000??????????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b1001_100000??????????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b1001_000000?????????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b1001_000000????????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b1001_000000???????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b1001_000000??????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b1001_000000?????10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b1001_000000????100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b1001_000000???1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b1001_000000??10000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1001_000000?100000000: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b1001_0000001000000000: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b1010_????1???????????: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b1010_???10???????????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b1010_??100???????????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b1010_?1000???????????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b1010_10000???????????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b1010_00000??????????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b1010_00000?????????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b1010_00000????????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b1010_00000???????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b1010_00000??????10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b1010_00000?????100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b1010_00000????1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b1010_00000???10000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1010_00000??100000000: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b1010_00000?1000000000: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b1010_0000010000000000: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b1011_???1????????????: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b1011_??10????????????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b1011_?100????????????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b1011_1000????????????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b1011_0000???????????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b1011_0000??????????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b1011_0000?????????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b1011_0000????????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b1011_0000???????10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b1011_0000??????100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b1011_0000?????1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b1011_0000????10000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1011_0000???100000000: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b1011_0000??1000000000: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b1011_0000?10000000000: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b1011_0000100000000000: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b1100_??1?????????????: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b1100_?10?????????????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b1100_100?????????????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b1100_000????????????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b1100_000???????????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b1100_000??????????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b1100_000?????????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b1100_000????????10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b1100_000???????100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b1100_000??????1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b1100_000?????10000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1100_000????100000000: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b1100_000???1000000000: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b1100_000??10000000000: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b1100_000?100000000000: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b1100_0001000000000000: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b1101_?1??????????????: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b1101_10??????????????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b1101_00?????????????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b1101_00????????????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b1101_00???????????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b1101_00??????????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b1101_00?????????10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b1101_00????????100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b1101_00???????1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b1101_00??????10000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1101_00?????100000000: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b1101_00????1000000000: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b1101_00???10000000000: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b1101_00??100000000000: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b1101_00?1000000000000: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b1101_0010000000000000: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b1110_1???????????????: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + 20'b1110_0??????????????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b1110_0?????????????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b1110_0????????????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b1110_0???????????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b1110_0??????????10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b1110_0?????????100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b1110_0????????1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b1110_0???????10000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1110_0??????100000000: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b1110_0?????1000000000: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b1110_0????10000000000: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b1110_0???100000000000: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b1110_0??1000000000000: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b1110_0?10000000000000: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b1110_0100000000000000: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b1111_???????????????1: begin sel_one_hot_n= 16'b0000000000000001; tag_o = (lg_inputs_p) ' (0); end + 20'b1111_??????????????10: begin sel_one_hot_n= 16'b0000000000000010; tag_o = (lg_inputs_p) ' (1); end + 20'b1111_?????????????100: begin sel_one_hot_n= 16'b0000000000000100; tag_o = (lg_inputs_p) ' (2); end + 20'b1111_????????????1000: begin sel_one_hot_n= 16'b0000000000001000; tag_o = (lg_inputs_p) ' (3); end + 20'b1111_???????????10000: begin sel_one_hot_n= 16'b0000000000010000; tag_o = (lg_inputs_p) ' (4); end + 20'b1111_??????????100000: begin sel_one_hot_n= 16'b0000000000100000; tag_o = (lg_inputs_p) ' (5); end + 20'b1111_?????????1000000: begin sel_one_hot_n= 16'b0000000001000000; tag_o = (lg_inputs_p) ' (6); end + 20'b1111_????????10000000: begin sel_one_hot_n= 16'b0000000010000000; tag_o = (lg_inputs_p) ' (7); end + 20'b1111_???????100000000: begin sel_one_hot_n= 16'b0000000100000000; tag_o = (lg_inputs_p) ' (8); end + 20'b1111_??????1000000000: begin sel_one_hot_n= 16'b0000001000000000; tag_o = (lg_inputs_p) ' (9); end + 20'b1111_?????10000000000: begin sel_one_hot_n= 16'b0000010000000000; tag_o = (lg_inputs_p) ' (10); end + 20'b1111_????100000000000: begin sel_one_hot_n= 16'b0000100000000000; tag_o = (lg_inputs_p) ' (11); end + 20'b1111_???1000000000000: begin sel_one_hot_n= 16'b0001000000000000; tag_o = (lg_inputs_p) ' (12); end + 20'b1111_??10000000000000: begin sel_one_hot_n= 16'b0010000000000000; tag_o = (lg_inputs_p) ' (13); end + 20'b1111_?100000000000000: begin sel_one_hot_n= 16'b0100000000000000; tag_o = (lg_inputs_p) ' (14); end + 20'b1111_1000000000000000: begin sel_one_hot_n= 16'b1000000000000000; tag_o = (lg_inputs_p) ' (15); end + default: begin sel_one_hot_n= {16{1'bx}}; tag_o = (lg_inputs_p) ' (0); end // X + endcase +end + +assign sel_one_hot_o = sel_one_hot_n; +assign grants_o = sel_one_hot_n & {16{grants_en_i}} ; + + +if ( hold_on_sr_p ) begin + + always_comb begin + unique casez( last_r ) + 4'b0000 : hold_on_sr = ( reqs_i == 16'b0100000000000000 ); + 4'b0001 : hold_on_sr = ( reqs_i == 16'b0010000000000000 ); + 4'b0010 : hold_on_sr = ( reqs_i == 16'b0001000000000000 ); + 4'b0011 : hold_on_sr = ( reqs_i == 16'b0000100000000000 ); + 4'b0100 : hold_on_sr = ( reqs_i == 16'b0000010000000000 ); + 4'b0101 : hold_on_sr = ( reqs_i == 16'b0000001000000000 ); + 4'b0110 : hold_on_sr = ( reqs_i == 16'b0000000100000000 ); + 4'b0111 : hold_on_sr = ( reqs_i == 16'b0000000010000000 ); + 4'b1000 : hold_on_sr = ( reqs_i == 16'b0000000001000000 ); + 4'b1001 : hold_on_sr = ( reqs_i == 16'b0000000000100000 ); + 4'b1010 : hold_on_sr = ( reqs_i == 16'b0000000000010000 ); + 4'b1011 : hold_on_sr = ( reqs_i == 16'b0000000000001000 ); + 4'b1100 : hold_on_sr = ( reqs_i == 16'b0000000000000100 ); + 4'b1101 : hold_on_sr = ( reqs_i == 16'b0000000000000010 ); + 4'b1110 : hold_on_sr = ( reqs_i == 16'b0000000000000001 ); + default: hold_on_sr = ( reqs_i == 16'b1000000000000000 ); + endcase + end //end of always_comb + +end else begin:not_hold_on_sr_p + assign hold_on_sr = '0; +end //end of hold_on_sr_p + +if ( reset_on_sr_p ) begin:reset_on_16 + assign reset_on_sr = ( reqs_i == 16'b0100000000000000 ) + | ( reqs_i == 16'b0010000000000000 ) + | ( reqs_i == 16'b0001000000000000 ) + | ( reqs_i == 16'b0000100000000000 ) + | ( reqs_i == 16'b0000010000000000 ) + | ( reqs_i == 16'b0000001000000000 ) + | ( reqs_i == 16'b0000000100000000 ) + | ( reqs_i == 16'b0000000010000000 ) + | ( reqs_i == 16'b0000000001000000 ) + | ( reqs_i == 16'b0000000000100000 ) + | ( reqs_i == 16'b0000000000010000 ) + | ( reqs_i == 16'b0000000000001000 ) + | ( reqs_i == 16'b0000000000000100 ) + | ( reqs_i == 16'b0000000000000010 ) + | ( reqs_i == 16'b0000000000000001 ) + | ( reqs_i == 16'b1000000000000000 ) + ; + +end else begin:not_reset_on_sr_p + assign reset_on_sr = '0; +end //end of reset_on_sr_p + +end: inputs_16 + + +assign v_o = | reqs_i ; + +if(inputs_p == 1) + assign last_r = 1'b0; +else + begin + always_comb + if( hold_on_sr_p ) begin: last_n_gen + last_n = hold_on_sr ? last_r : + ( yumi_i ? tag_o : last_r ); + end else if( reset_on_sr_p ) begin: reset_on_last_n_gen + last_n = reset_on_sr? (inputs_p-2'd2) : + ( yumi_i ?tag_o : last_r ); + end else if( hold_on_valid_p ) begin: hold_on_last_n_gen + // Need to manually handle wrap around on non-power of two case, else reuse subtraction + last_n = yumi_i ? tag_o + : v_o ? ((~`BSG_IS_POW2(inputs_p) && tag_o == '0) ? (lg_inputs_p)'(inputs_p-1) : (tag_o-1'b1)) + : last_r; + end else + last_n = (yumi_i ? tag_o:last_r); + + always_ff @(posedge clk_i) + last_r <= (reset_i) ? (lg_inputs_p)'(0):last_n; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_round_robin_arb) diff --git a/designs/black-parrot/src/basejump_stl/bsg_round_robin_n_to_1.sv b/designs/black-parrot/src/basejump_stl/bsg_round_robin_n_to_1.sv new file mode 100644 index 0000000..82cd590 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_round_robin_n_to_1.sv @@ -0,0 +1,134 @@ +// MBT 11/10/14 +// +// bsg_round_robin_n_to_1 +// +// this is intended to merge the outputs of several fifos +// together to act as one. +// +// assumes a valid yumi interface +// +// strict_p: determines whether the round_robin +// module blocks until the head FIFO is valid, or if it just +// goes to the next one. +// +// + +`include "bsg_defines.sv" + +module bsg_round_robin_n_to_1 #(parameter `BSG_INV_PARAM(width_p ) + ,parameter `BSG_INV_PARAM(num_in_p ) + ,parameter `BSG_INV_PARAM(strict_p ) + ,parameter use_scan_p = 0 + ,parameter tag_width_lp = `BSG_SAFE_CLOG2(num_in_p) + ) + (input clk_i + , input reset_i + + // to fifos + , input [num_in_p-1:0][width_p-1:0] data_i + , input [num_in_p-1:0] v_i + , output [num_in_p-1:0] yumi_o + + // to downstream + , output v_o + , output [width_p-1:0] data_o + , output [tag_width_lp-1:0] tag_o + , input yumi_i + ); + + if (strict_p) + begin : strict + wire [tag_width_lp-1:0] ptr_r; + + bsg_circular_ptr #(.slots_p(num_in_p) + ,.max_add_p(1) + ) circular_ptr + (.clk (clk_i ) + ,.reset_i(reset_i) + ,.add_i (yumi_i ) + ,.o (ptr_r ) + ,.n_o () + ); + + assign v_o = v_i [ptr_r]; + assign data_o = data_i [ptr_r]; + + assign tag_o = ptr_r; + + // binary to one hot + assign yumi_o = (num_in_p) ' (yumi_i << tag_o); + + end + else + begin : greedy + + wire [num_in_p-1:0] grants_lo; + + // we have valid output if any input is valid + // we do not need the arb to determine this + // the signal yumi_i is computed from this + + // assign v_o = | v_i; + + if (use_scan_p) begin: scan1 + // scan version + bsg_arb_round_robin #( + .width_p(num_in_p) + ) rr ( + .clk_i (clk_i) + ,.reset_i (reset_i) + ,.reqs_i (v_i) + ,.grants_o (grants_lo) + ,.yumi_i (yumi_i) + ); + + assign v_o = | v_i; + + bsg_encode_one_hot #( + .width_p(num_in_p) + ) enc ( + .i(grants_lo) + ,.addr_o(tag_o) + ,.v_o() + ); + + end + else begin: scan0 + bsg_round_robin_arb #(.inputs_p(num_in_p)) + rr_arb_ctrl + (.clk_i + ,.reset_i + ,.grants_en_i(1'b1) + + // "data plane" + ,.reqs_i (v_i ) // from each of the nodes + ,.grants_o (grants_lo) + ,.sel_one_hot_o() + + ,.v_o ( v_o ) + ,.tag_o (tag_o ) + ,.yumi_i (yumi_i & v_o ) // based on v_o, downstream + // node decides if it will accept + ); + + end + + bsg_crossbar_o_by_i #(.i_els_p (num_in_p) + ,.o_els_p(1 ) + ,.width_p(width_p) + ) xbar + (.i (data_i ) + ,.sel_oi_one_hot_i(grants_lo) + ,.o (data_o ) + ); + + // mask grants with yumi signal + assign yumi_o = grants_lo & { num_in_p { yumi_i }}; + + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_round_robin_n_to_1) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_scan.sv b/designs/black-parrot/src/basejump_stl/bsg_scan.sv new file mode 100644 index 0000000..bccc467 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_scan.sv @@ -0,0 +1,130 @@ +// MBT 10/16/14 +// +// note: this does a scan from hi bit to lo +// so the high bit is always unchanged +// +// note: implements Kogge-Stone style prefix tree +// which may have excessive wiring as width_p grows +// + +`include "bsg_defines.sv" + +module bsg_scan #(parameter `BSG_INV_PARAM(width_p) + , parameter xor_p = 0 + , parameter and_p = 0 + , parameter or_p = 0 + , parameter lo_to_hi_p = 0 + , parameter debug_p = 0 + ) + (input [width_p-1:0] i + , output logic [width_p-1:0] o + ); + + // derivation of the scan code (xor case): + + // width_p = 1 1 + // t1 = i + // + // width_p = 4 1111 + // t1 = i ^ (i >> 1) 1111 ^ 0111 --> 1000 + // t2 = t1 ^ (t1 >> 2) 1000 ^ 0010 --> 1010 + // t4 = t2 ^ (t2 >> 4) 1010 ^ 0000 --> 1010 (not needed) + + // width_p = 5 11111 + // t1 = i ^ (i >> 1) 11111 ^ 01111 --> 10000 + // t2 = t1 ^ (t1 >> 2) 10000 ^ 00100 --> 10100 + // t4 = t2 ^ (t2 >> 4) 10100 ^ 00001 --> 10101 (needed) + + // width_p = 8 1111_1111 + // t1 = i ^ (i >> 1) 1111_1111 ^ 0111_1111 --> 1000_0000 + // t2 = t1 ^ (t1 >> 2) 1000_0000 ^ 0010_0000 --> 1010_0000 + // t4 = t2 ^ (t2 >> 4) 1010_0000 ^ 0000_1010 --> 1010_1010 (needed) + + // + // 1 2 3 4 5 6 7 8 9 + // clog2 0 1 2 2 3 3 3 3 4 + + genvar j; + + wire [$clog2(width_p):0][width_p-1:0] t; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + assert( $countones({xor_p[0], and_p[0], or_p[0]}) == 1) + else $error("bsg_scan: only one function may be selected\n"); + + if (debug_p) + always @(o) + begin + `BSG_HIDE_FROM_VERILATOR(#1) + for (integer k = 0; k <= $clog2(width_p); k=k+1) + $display("%b",t[k]); + $display("i=%b, o=%b",i, o); + end + +`endif + + // streaming operation; reverses bits + if (lo_to_hi_p) + assign t[0] = {<< {i}}; + else + assign t[0] = i; + + // we optimize for the common case of small and-scans + // used in round_robin_fifo_to_fifo + // we could generalize for OR/XORs as well. + // fixme style: use a loop instead + + if ((width_p == 4) & and_p) + begin : scand4 + assign t[$clog2(width_p)] = { t[0][3], &t[0][3:2], &t[0][3:1], &t[0][3:0] }; + end + else if ((width_p == 3) & and_p) + begin: scand3 + assign t[$clog2(width_p)] = { t[0][2], &t[0][2:1], &t[0][2:0] }; + end + else if ((width_p == 2) & and_p) + begin: scand3 + assign t[$clog2(width_p)] = { t[0][1], &t[0][1:0] }; + end + else + begin : scanN + for (j = 0; j < $clog2(width_p); j = j + 1) + begin : row + wire [width_p-1:0] fill; + wire [width_p-1:0] shifted = width_p ' ({fill, t[j]} >> (1 << j)); + + if (xor_p) + begin + assign fill = { width_p {1'b0} }; + assign t[j+1] = t[j] ^ shifted; + end + else if (and_p) + begin + assign fill = { width_p {1'b1} }; + assign t[j+1] = t[j] & shifted; + end + else if (or_p) + begin + assign fill = { width_p {1'b0} }; + assign t[j+1] = t[j] | shifted; + end + end + end // block: scanN + + // reverse bits + if (lo_to_hi_p) + //assign o = {<< {t[$clog2(width_p)]}}; + for (j = 0; j < width_p; j++) begin + assign o[j] = t[$clog2(width_p)][width_p-1-j]; + end + + else + assign o = t[$clog2(width_p)]; + + // always @(o) + // $display("bsg_scan (xor_p %b and_p %b or_p %b) %b = %b",xor_p[0],and_p[0],or_p[0],i,o); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_scan) diff --git a/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out.sv b/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out.sv new file mode 100644 index 0000000..e93afc0 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out.sv @@ -0,0 +1,102 @@ +// MBT BSG 11/13/2014 +// +// Single-Enque, Multi-Deque FIFO +// +// A FIFO that takes in one word per cycle +// and allows more than one word per cycle to be removed. +// The number of words removed is determined by downstream consumer +// on a cycle-by-cycle basis. +// +// This module is likely to be much more expensive than other +// bsg_serial_in_parallel_out_* modules, and probably should be renamed. +// +// els_p and out_els_p can be set differently in order +// to increase the amount of buffering internal to the module +// +// this data structure supports bypassing, so can +// have zero latency (but possibly a larger cycle time.) +// +// this is a shifting-based fifo; so this is probably +// not ideal from power perspective +// +// + +`include "bsg_defines.sv" + +module bsg_serial_in_parallel_out #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter out_els_p = els_p) + (input clk_i + , input reset_i + , input valid_i + , input [width_p-1:0] data_i + , output ready_and_o + + , output logic [out_els_p-1:0] valid_o + , output logic [out_els_p-1:0][width_p-1:0] data_o + + , input [$clog2(out_els_p+1)-1:0] yumi_cnt_i + ); + + localparam double_els_lp = els_p * 2; + + logic [els_p-1:0][width_p-1:0] data_r, data_nn; + logic [2*els_p-1:0 ][width_p-1:0] data_n; + logic [els_p-1:0] valid_r, valid_nn; + logic [double_els_lp-1:0] valid_n; + + logic [$clog2(els_p+1)-1:0] num_els_r, num_els_n; + + always_ff @(posedge clk_i) + begin + if (reset_i) + begin + num_els_r <= 0; + valid_r <= 0; + end + else + begin + num_els_r <= num_els_n; + valid_r <= valid_nn; + end + end + + always_ff @(posedge clk_i) begin + data_r <= data_nn; + end + + + // we are ready if we have at least + // one spot that is not full + + assign ready_and_o = ~valid_r[els_p-1]; + + // update element count + assign num_els_n = (num_els_r + (valid_i & ready_and_o)) - yumi_cnt_i; + + always_comb begin + data_n = data_r; + valid_n = (double_els_lp) ' (valid_r); + + data_n[els_p+:els_p] = 0; + + // bypass in values + data_n [num_els_r] = data_i; + valid_n[num_els_r] = valid_i & ready_and_o; + + // this temporary value is + // the output of this function + valid_o = valid_n[out_els_p-1:0]; + data_o = data_n [out_els_p-1:0]; + + // now we calculate the update + for (integer i = 0; i < els_p; i++) begin + data_nn[i] = data_n[yumi_cnt_i+i]; + end + valid_nn = valid_n[yumi_cnt_i+:els_p]; + end + +endmodule + + +`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out) diff --git a/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_dynamic.sv b/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_dynamic.sv new file mode 100644 index 0000000..5e6bb32 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_dynamic.sv @@ -0,0 +1,187 @@ +/** + * bsg_serial_in_parallel_out_dynamic.sv + * + * This SIPO supports a changing in/out ratio; but the + * output count must be presented with the first data word + * in the stream to the module. Because of this limitation, + * the hardware is much simpler than in bsg_serial_in_parallel_out. + * + * Paul Gao 06/2019 + * + */ + +`include "bsg_defines.sv" + +module bsg_serial_in_parallel_out_dynamic + + #(parameter `BSG_INV_PARAM(width_p ) + ,parameter `BSG_INV_PARAM(max_els_p ) + ,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p) + ) + + (input clk_i + ,input reset_i + + // Input side + ,input v_i + ,input [lg_max_els_lp-1:0] len_i + ,input [width_p-1:0] data_i + ,output ready_and_o + ,output len_ready_o + + // Output side + ,output v_o + ,output [max_els_p-1:0][width_p-1:0] data_o + ,input yumi_i + ); + + genvar i; + + logic yumi_lo; + assign yumi_lo = v_i & ready_and_o; + + logic [lg_max_els_lp-1:0] count_r, count_lo, len_r, len_lo; + logic clear_li, up_li, dff_en_li, go_fifo_v_li; + logic count_r_is_zero, count_r_is_last; + + // fix evaluate to Z problem in simulation + assign count_lo = count_r; + + // When new packet coming, use new length, otherwise use registered length + assign len_lo = (count_r_is_zero)? len_i : len_r; + + assign count_r_is_zero = (count_lo == lg_max_els_lp'(0)); + assign count_r_is_last = (count_lo == len_lo ); + + // We accept new length when first word comes in + // At this time, counter is at initial value 0 + assign len_ready_o = count_r_is_zero; + + // Count up if data word is not last word of current packet. + assign up_li = yumi_lo & ~count_r_is_last; + + // Clear counter when it reaches target length + assign clear_li = yumi_lo & count_r_is_last; + assign go_fifo_v_li = clear_li; + + // Update length register when new packet comes in + assign dff_en_li = yumi_lo & count_r_is_zero; + + // Length counter + bsg_counter_clear_up + #(.max_val_p (max_els_p-1) + ,.init_val_p(0) + ) ctr + (.clk_i (clk_i ) + ,.reset_i (reset_i ) + ,.clear_i (clear_li) + ,.up_i (up_li ) + ,.count_o (count_r ) + ); + + // Length register + bsg_dff_reset_en + #(.width_p (lg_max_els_lp) + ,.reset_val_p(0) + ) dff_len + (.clk_i (clk_i ) + ,.reset_i (reset_i ) + ,.en_i (dff_en_li) + ,.data_i (len_i ) + ,.data_o (len_r ) + ); + + // Go fifo + // Notify output side that packet is ready to send + // Must use two element fifo to match lowest word data fifo! + logic one_word_lo; + + bsg_two_fifo + #(.width_p (1) + ) go_fifo + (.clk_i (clk_i ) + ,.reset_i (reset_i ) + ,.ready_param_o (/* This fifo has same size of lowest word data fifo + No need to check ready_o here */) + ,.data_i (count_r_is_zero) // Indicate whether it is single word packet + ,.v_i (go_fifo_v_li ) + ,.v_o (v_o ) + ,.data_o (one_word_lo ) + ,.yumi_i (yumi_i ) + ); + + logic [max_els_p-1:0] fifo_valid_li, fifo_ready_and_lo; + logic [max_els_p-1:0] fifo_valid_lo, fifo_yumi_li; + + // Ready signal from selected fifo + assign ready_and_o = fifo_ready_and_lo[count_lo]; + + for (i = 0; i < max_els_p; i++) + begin: rof0 + if (i == 0) + // Lowest word fifo always dequeue (packet should have at least one word) + assign fifo_yumi_li[i] = yumi_i; + else + // Rest are bsg_one_fifo, only dequeue when they have valid data + // + // Corner case: a single-word packet comes in firstly, then a + // multi-word packet comes. Use one_word_lo to determine whether + // first packet is one-word or not. + // + // Case above can be prevented if we use bsg_one_fifo everywhere, but + // there will be one-cycle bubble between packets. + assign fifo_yumi_li[i] = fifo_valid_lo[i] & yumi_i & ~one_word_lo; + end + + // Trigger selected valid signal + bsg_decode_with_v + #(.num_out_p(max_els_p) + ) bdwv + (.i (count_lo ) + ,.v_i(v_i ) + ,.o (fifo_valid_li) + ); + + // Data fifos + for (i = 0; i < max_els_p; i++) + begin: fifos + if (i == 0) + begin: twofifo + // Use two element fifo to avoid bubble + bsg_two_fifo + #(.width_p(width_p) + ) fifo + (.clk_i (clk_i ) + ,.reset_i (reset_i) + + ,.ready_param_o (fifo_ready_and_lo[i]) + ,.data_i (data_i ) + ,.v_i (fifo_valid_li[i] ) + + ,.v_o (fifo_valid_lo[i]) + ,.data_o (data_o [i]) + ,.yumi_i (fifo_yumi_li [i]) + ); + end + else + begin: onefifo + // one element FIFO is sufficient to enable full pipelined dataflow + bsg_one_fifo + #(.width_p(width_p) + ) fifo + (.clk_i (clk_i ) + ,.reset_i (reset_i) + + ,.ready_and_o(fifo_ready_and_lo[i]) + ,.data_i (data_i ) + ,.v_i (fifo_valid_li[i]) + + ,.v_o (fifo_valid_lo[i]) + ,.data_o (data_o [i]) + ,.yumi_i (fifo_yumi_li [i]) + ); + end + end + +endmodule +`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out_dynamic) diff --git a/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_full.sv b/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_full.sv new file mode 100644 index 0000000..cc94f6b --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_full.sv @@ -0,0 +1,146 @@ +/** + * bsg_serial_in_parallel_out_full.sv + * + * This module is a serial in parallel out module with a constant in/out ratio. + * The implementation is much simpler than bsg_serial_in_parallel_out.sv, presumably + * leading to better timing and less area and power. + * + * This module is like bsg_serial_in_parallel_out_passthru, except that it buffers + * data with FIFOs and introduces one cycle of extra latency beyond the in/out ratio. + * + * Output is only valid, when the output array is fully assembled. + * + * This module allows for the setting of extra_buffers_p, which allows for more + * than minimum number of buffers. If this is set to 0, there will be 1-cycle bubbles + * between parallel deques. By default, extra_buffers_p is set to 1, which allows + * for no bubbles during standard propagation. The value may also be set to a greater number, + * to allow for greater amounts of buffering. + * + * The module currently does not support extra_buffers_p > els_p. + * + * use_minimal_buffering_p is a backwards compatible interface that sets extra_buffers_p to 0 + * it is ignored if extra_buffers_p is also set. + * + * @author tommy 02/2019 + * Paul Gao 06/2019 + * + * BaseJump 3.0 suggestion: rename to bsg_serial_in_parallel_out_const + */ + +`include "bsg_defines.sv" + +module bsg_serial_in_parallel_out_full + + #(parameter `BSG_INV_PARAM(width_p) + ,parameter `BSG_INV_PARAM(els_p) + ,parameter hi_to_lo_p = 0 + ,parameter use_minimal_buffering_p = 0 + ,parameter extra_buffers_p = (use_minimal_buffering_p ? 0 : 1) + ) + + (input clk_i + ,input reset_i + + ,input v_i + ,output logic ready_and_o + ,input [width_p-1:0] data_i + + ,output logic [els_p-1:0][width_p-1:0] data_o + ,output logic v_o + ,input yumi_i + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + assert (extra_buffers_p <= els_p) + else $error("%m bsg_serial_in_parallel_out_full does not support extra_buffers_p (%d) > els_p (%d)",extra_buffers_p, els_p); +`endif + + localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p); + + // If send hi_to_lo, reverse the output data array + logic [els_p-1:0][width_p-1:0] data_lo; + + if (hi_to_lo_p == 0) + begin: lo2hi + assign data_o = data_lo; + end + else + begin: hi2lo + bsg_array_reverse + #(.width_p(width_p) + ,.els_p(els_p) + ) bar + (.i(data_lo) + ,.o(data_o) + ); + end + + + logic [els_p-1:0] fifo_valid_li, fifo_ready_and_lo; + logic [els_p-1:0] fifo_valid_lo; + + // Full array is valid when all fifos have valid data + assign v_o = & fifo_valid_lo; + + // Push received data into fifos in round-robin way + bsg_round_robin_1_to_n + #(.width_p(width_p) + ,.num_out_p(els_p) + ) brr + (.clk_i (clk_i) + ,.reset_i (reset_i) + ,.valid_i (v_i) + ,.ready_and_o(ready_and_o) + ,.valid_o (fifo_valid_li) + ,.ready_and_i(fifo_ready_and_lo) + ); + + // Data fifos + genvar i; + + for (i = 0; i < els_p; i++) + begin: fifos + // Lowest word fifo selection depends on use_minimal_buffering_p + if (i < extra_buffers_p) //(i == 0 && use_minimal_buffering_p == 0) + begin: twofifo + // Use two element fifo to avoid bubble + bsg_two_fifo + #(.width_p(width_p) + ) fifo + (.clk_i (clk_i) + ,.reset_i (reset_i) + + ,.ready_param_o (fifo_ready_and_lo[i]) + ,.data_i (data_i) + ,.v_i (fifo_valid_li[i]) + + ,.v_o (fifo_valid_lo[i]) + ,.data_o (data_lo[i]) + ,.yumi_i (yumi_i) + ); + end + else + begin: onefifo + // Use one element fifo to minimize hardware + bsg_one_fifo + #(.width_p(width_p) + ) fifo + (.clk_i (clk_i) + ,.reset_i (reset_i) + + ,.ready_and_o(fifo_ready_and_lo[i]) + ,.data_i (data_i) + ,.v_i (fifo_valid_li[i]) + + ,.v_o (fifo_valid_lo[i]) + ,.data_o (data_lo[i]) + ,.yumi_i (yumi_i) + ); + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out_full) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_passthrough.sv b/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_passthrough.sv new file mode 100644 index 0000000..1a4d63e --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_serial_in_parallel_out_passthrough.sv @@ -0,0 +1,99 @@ +/** + * bsg_serial_in_parallel_out_passthrough + * + * This module is a serial in parallel out module with a constant in/out ratio. + * The implementation is much simpler than bsg_serial_in_parallel_out.sv, presumably + * leading to better timing and less area and power. + * + * This module is like bsg_serial_in_parallel_out_full, except that it uses registers to buffer + * data and does not introduce an extra cycle of latency beyond the in/out ratio. + * v_o and data_o depend combinationally on v_i and data_i. + * + * Output is only valid, when the output array is fully assembled. + * + * BaseJump 3.0 suggestion: rename to bsg_serial_in_parallel_out_const_passthrough + */ + +`include "bsg_defines.sv" + +module bsg_serial_in_parallel_out_passthrough + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , hi_to_lo_p = 0 + ) + (input clk_i + , input reset_i + + , input v_i + , output logic ready_and_o + , input [width_p-1:0] data_i + + , output logic [els_p-1:0][width_p-1:0] data_o + , output logic v_o + , input ready_and_i + ); + + localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p); + + logic [els_p-1:0] count_r; + + assign v_o = v_i & count_r[els_p-1]; // means we received all of the words + assign ready_and_o = ~count_r[els_p-1] | ready_and_i; // have space, or we are dequeing; (one gate delay in-to-out) + + wire sending = v_o & ready_and_i; // we have all the items, and downstream is ready + wire receiving = v_i & ready_and_o; // data is coming in, and we have space + + // counts one hot, from 0 to width_p + // contains one hot pointer to word to write to + // simultaneous restart and increment are allowed + + if (els_p == 1) + begin : single_word + assign count_r = 1'b1; + end + else + begin : multi_word + bsg_counter_clear_up_one_hot + #(.max_val_p(els_p-1)) + bcoh + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(sending) + ,.up_i(receiving & ~count_r[els_p-1]) + ,.count_r_o(count_r) + ); + end + + logic [els_p-1:0][width_p-1:0] data_lo; + + for (genvar i = 0; i < els_p-1; i++) + begin: rof + wire my_turn = v_i & count_r[i]; + bsg_dff_en #(.width_p(width_p)) dff + (.clk_i + ,.data_i + ,.en_i (my_turn) + ,.data_o (data_lo [i]) + ); + end + assign data_lo[els_p-1] = data_i; + + // If send hi_to_lo, reverse the output data array + if (hi_to_lo_p == 0) + begin: lo2hi + assign data_o = data_lo; + end + else + begin: hi2lo + bsg_array_reverse + #(.width_p(width_p), .els_p(els_p)) + bar + (.i(data_lo) + ,.o(data_o) + ); + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out_passthrough) diff --git a/designs/black-parrot/src/basejump_stl/bsg_shift_reg.sv b/designs/black-parrot/src/basejump_stl/bsg_shift_reg.sv new file mode 100644 index 0000000..d496bde --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_shift_reg.sv @@ -0,0 +1,35 @@ +// MBT 10-29-14 +// +// implements a shift register of fixed latency +// +// + +`include "bsg_defines.sv" + +module bsg_shift_reg #(parameter `BSG_INV_PARAM(width_p ) + , parameter `BSG_INV_PARAM(stages_p ) + ) + (input clk + , input reset_i + , input valid_i + , input [width_p-1:0] data_i + , output valid_o + , output [width_p-1:0] data_o + ); + + logic [stages_p-1:0][width_p+1-1:0] shift_r; + + always_ff @(posedge clk) + if (reset_i) + shift_r <= '0; + else + begin + // maxes and mins are for handling stages_p=1 + shift_r[stages_p-1:`BSG_MIN(stages_p-1,1)] <= shift_r[`BSG_MAX(stages_p-2,0):0]; + shift_r[0] <= { valid_i, data_i }; + end + assign { valid_o, data_o } = shift_r[stages_p-1]; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_shift_reg) diff --git a/designs/black-parrot/src/basejump_stl/bsg_strobe.sv b/designs/black-parrot/src/basejump_stl/bsg_strobe.sv new file mode 100644 index 0000000..befadf0 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_strobe.sv @@ -0,0 +1,147 @@ +// bsg_strobe +// +// N +// Outputs sequence ( 1 0 )* for 0 <= N=init_val_i <= (1< 1) + always @(negedge bsg_tag_i.clk) + begin + if (reset_op & ~(~bsg_tag_i.op & bsg_tag_i.param)) + $display("## bsg_tag_client (send) RESET DEASSERTED (%m)"); + if (~reset_op & (~bsg_tag_i.op & bsg_tag_i.param)) + $display("## bsg_tag_client (send) RESET ASSERTED (%m)"); + if (send_now) + $display("## bsg_tag_client (send) SENDING %b (%m)",tag_data_r); + end +`endif + + logic recv_toggle_r, recv_toggle_n; + + // cross clock boundary + bsg_launch_sync_sync #(.width_p(1)) blss + (.iclk_i (bsg_tag_i.clk) + ,.iclk_reset_i(reset_op) + ,.iclk_data_i (tag_toggle_r ^ send_now) + ,.iclk_data_o (tag_toggle_r) // this is the flop that is reset + + ,.oclk_i (recv_clk_i ) + ,.oclk_data_o(recv_toggle_n) + ); + + // note: bsg_tag_i.en is wired from off-chip and should be + // only toggled when there is no attempt to transmit data + + wire recv_new = (recv_toggle_r ^ recv_toggle_n) & bsg_tag_i.en; + + // we had to add recv_new_r_r to pipeline the receive logic + // and the fanout to the recv_data_r register at the maximum + // frequency on the chip (i.e. the clock generator) + + logic recv_new_r, recv_new_r_r; + + always_ff @(posedge recv_clk_i) + begin + recv_toggle_r <= recv_toggle_n; + recv_new_r <= recv_new; + recv_new_r_r <= recv_new_r; + end + + bsg_dff_en #(.width_p(width_p),.harden_p(harden_p)) recv + (.clk_i(recv_clk_i) + ,.en_i(recv_new_r) + ,.data_i(tag_data_r) + ,.data_o(recv_data_r) + ); + + // the recv_en_i signal has to come after the flop + // so this works even when the clock is not working + + assign recv_new_r_o = recv_new_r_r & bsg_tag_i.en; + assign recv_data_r_o = recv_data_r; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_tag_client) diff --git a/designs/black-parrot/src/basejump_stl/bsg_tag_client_unsync.sv b/designs/black-parrot/src/basejump_stl/bsg_tag_client_unsync.sv new file mode 100644 index 0000000..6d5c46c --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_tag_client_unsync.sv @@ -0,0 +1,109 @@ +// +// bsg_tag_client_unsync +// +// simple serial on-chip configuration network +// +// this client has only the shift register that captures data from the client +// no attempt is made to perform any synchronzation, or to hide intermediate toggles +// of bits as values are shifted in. +// +// generally speaking, this version should only be used in special cases: +// +// - where values are not intended to be updated on the fly as the chip runs; +// i.e. configuration prior to reset +// +// - where receive logic has been explicitly coded separately +// +// 5/26/2018 MBT +// +// +// RESET SEMANTICS +// +// 1. Shift in the value you want to use. +// 2. Deassert reset on the receive side module. +// + +`include "bsg_defines.sv" + +module bsg_tag_client_unsync + import bsg_tag_pkg::bsg_tag_s; + #(parameter `BSG_INV_PARAM(width_p), harden_p=1, debug_level_lp=0) + ( + input bsg_tag_s bsg_tag_i + + ,output [width_p-1:0] data_async_r_o + ); + + logic op_r, param_r; + + always_ff @(posedge bsg_tag_i.clk) + begin + op_r <= bsg_tag_i.op; + param_r <= bsg_tag_i.param; + end + + wire shift_op = op_r; + wire no_op = ~op_r & ~param_r; + + logic [width_p-1:0] tag_data_r, tag_data_n, tag_data_shift; + + // shift in new state + if (width_p > 1) + begin : fi + assign tag_data_shift = { param_r, tag_data_r[width_p-1:1] }; + end + else + begin: fi + assign tag_data_shift = param_r; + end + + bsg_mux2_gatestack #(.width_p(width_p),.harden_p(harden_p)) tag_data_mux + (.i0 (tag_data_r ) // sel=0 + ,.i1(tag_data_shift ) // sel=1 + ,.i2({ width_p {shift_op} }) // sel var + ,.o (tag_data_n) + ); + + + // Veri lator did not like bsg_dff_gatestack with the replicated clock signal + // hopefully this replacement does not cause inordinate problems =) + + bsg_dff #(.width_p(width_p), .harden_p(harden_p)) tag_data_reg + (.clk_i(bsg_tag_i.clk) + ,.data_i(tag_data_n) + ,.data_o(tag_data_r) + ); + +/* + bsg_dff_gatestack #(.width_p(width_p),.harden_p(harden_p)) tag_data_reg + ( + .i0 (tag_data_n ) + ,.i1( { width_p { bsg_tag_i.clk } }) + ,.o (tag_data_r ) + ); + */ + + +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (debug_level_lp > 1) + begin: debug + wire reset_op = ~op_r & param_r; + always @(negedge bsg_tag_i.clk) + begin + //if (reset_op) + // $display("## bsg_tag_client RESET HI (%m)"); + if (reset_op & ~(~bsg_tag_i.op & bsg_tag_i.param)) + $display("## bsg_tag_client RESET DEASSERTED time %t (%m)",$time); + if (~reset_op & (~bsg_tag_i.op & bsg_tag_i.param)) + $display("## bsg_tag_client RESET ASSERTED time %t (%m)",$time); + if (shift_op) + $display("## bsg_tag_client (send) SHIFTING %b (%m)",tag_data_r); + end + end +`endif + + assign data_async_r_o = tag_data_r; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_tag_client_unsync) diff --git a/designs/black-parrot/src/basejump_stl/bsg_tag_master.sv b/designs/black-parrot/src/basejump_stl/bsg_tag_master.sv new file mode 100644 index 0000000..4ae0a2d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_tag_master.sv @@ -0,0 +1,260 @@ +// bsg_tag_master +// +// 8/30/2016 +// +// Usage: send a stream of 0's to reset master node and/or noop. +// Then, send a single <1> followed by a packet: +// < id > < data_not_reset > < payload length > < payload > +// **************************************************************************** +// $clog2(els_p+1) 1 $clog2(max_payload_length+1) (variable size) +// +// To reset client nodes, set data_not_reset to 0, and payload to 1's. +// +// + +`include "bsg_defines.sv" + +`include "bsg_tag.svh" + +// will not build in verilator without this +// possibly resulting incorrect behavior :( + +// verilator lint_off BLKANDNBLK + +module bsg_tag_master + import bsg_tag_pkg::bsg_tag_s; + + // els_p is the number of clients to attach + // lg_width_p is the number of bits used to describe the payload size + + #(parameter `BSG_INV_PARAM(els_p), `BSG_INV_PARAM(lg_width_p), debug_level_lp=2) + ( + // from pins + input clk_i + ,input en_i + ,input data_i + , output bsg_tag_s [els_p-1:0] clients_r_o + ); + + `declare_bsg_tag_header_s(els_p,lg_width_p) + + localparam max_packet_len_lp = `bsg_tag_max_packet_len(els_p,lg_width_p); + + localparam reset_len_lp = `bsg_tag_reset_len(els_p,lg_width_p); + + // counts 0..max_packet_len_lp + localparam lg_max_packet_len_lp = `BSG_SAFE_CLOG2(max_packet_len_lp+1); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (debug_level_lp > 2) + always @(negedge clk_i) + $display("## bsg_tag_master clients=%b (%m)",clients_r_o); +`endif + + logic data_i_r; + + always @(posedge clk_i) + data_i_r <= data_i; + + // *************************** + // RESET LOGIC + // extra bit to detect carry out in counter + + localparam ctr_width_lp = lg_max_packet_len_lp+1; + logic [ctr_width_lp-1:0] zeros_ctr_r; + + + wire tag_reset_req = zeros_ctr_r[ctr_width_lp-1]; + + // this self-clearing counter detects a certain number + // of consecutive 0's + // indicating a tag_master reset condition + // + + bsg_counter_clear_up #(.max_val_p((1 << ctr_width_lp)-1) + ,.init_val_p(0) + ) bccu + (.clk_i (clk_i) + ,.reset_i(1'b0) + // we clear the counter if we hit the limit + ,.clear_i(data_i_r | tag_reset_req) + ,.up_i (~data_i_r) + ,.count_o(zeros_ctr_r) + ); + + // veri lator doesn't support -d +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial + $display("## %m instantiating bsg_tag_master with els_p=%d, lg_width_p=%d, max_packet_len_lp=%d, reset_zero_len=%d" + ,els_p,lg_width_p,max_packet_len_lp,reset_len_lp); +`endif + + // + // END RESET LOGIC + // *************************** + + logic [lg_max_packet_len_lp-1:0] hdr_ptr_r, hdr_ptr_n; + bsg_tag_header_s hdr_r, hdr_n; + + // sending + logic v_n; + // value to send + bsg_tag_s bsg_tag_n; + + typedef enum logic [1:0] {eStart, eHeader, eTransfer, eStuck} state_e; + + state_e state_r, state_n; + + // synopsys sync_set_reset "tag_reset_req, data_i_r" + + always_ff @(posedge clk_i) + // if we hit the counter AND (subtle bug) there is no valid incoming data that would get lost + if (tag_reset_req & ~data_i_r) + begin +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (debug_level_lp > 2) $display("## bsg_tag_master RESET time %t (%m)",$time); +`endif + state_r <= eStart; + + // we put this here because DC did not currently infer "reset" logic + hdr_ptr_r <= 0; + end + else + begin + state_r <= state_n; + hdr_ptr_r <= hdr_ptr_n; + end + + always_ff @(posedge clk_i) + hdr_r <= hdr_n; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @(negedge clk_i) + if (state_n != state_r) + if (debug_level_lp > 1) $display("## bsg_tag_master STATE CHANGE # %s --> %s #",state_r.name(),state_n.name()); +`endif + + always_comb + begin + state_n = state_r; + hdr_ptr_n = hdr_ptr_r; + hdr_n = hdr_r; + + // outgoing + v_n = 1'b0; + bsg_tag_n.op = 1'b0; + bsg_tag_n.param = 1'b0; + + case (state_r) + // first 1 after zero indicates beginning of packet + eStart: + begin + if (data_i_r) + state_n = eHeader; + + hdr_ptr_n = 0; + hdr_n = 0; + end + eHeader: + begin +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (debug_level_lp > 1) + $display("## bsg_tag_master RECEIVING HEADER (%m) (%d) = %b",hdr_ptr_r,data_i_r); +`endif + + hdr_n = { data_i_r, hdr_r[1+:($bits(bsg_tag_header_s)-1)] }; + hdr_ptr_n = hdr_ptr_r + 1'b1; + // if we are at the next to last value + if (hdr_ptr_r == lg_max_packet_len_lp'($bits(bsg_tag_header_s)-1)) + begin + if (hdr_n.len == 0) + begin + state_n = eStart; +`ifndef BSG_HIDE_FROM_SYNTHESIS + $display("## bsg_tag_master NULL PACKET, len=0 (%m)"); +`endif + end + else + begin + +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (debug_level_lp > 1) + $display("## bsg_tag_master PACKET HEADER RECEIVED (length=%b,data_not_reset=%b,nodeID=%b) (%m) " + ,hdr_n.len,hdr_n.data_not_reset,hdr_n.nodeID); +`endif + + // if we have data to transfer go to transfer state + state_n = eTransfer; + end + end + end // case: eHeader + eTransfer: + begin + // transmit data + // if hdr_r.reset = 1, then we send <0,data> for hdr_r.len cycles + // otherwise we send <1,data> for hdr_r.len cycles + // typically for reset, we will send 1's. + + v_n = 1'b1; + bsg_tag_n.op = hdr_r.data_not_reset; + bsg_tag_n.param = data_i_r; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (debug_level_lp > 2) + $display("## bsg_tag_master PACKET TRANSFER op,param=<%b,%b> (%m)", bsg_tag_n.op, bsg_tag_n.param); +`endif + + // finishing words + if (hdr_r.len== lg_width_p ' (1)) + begin + state_n = eStart; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (debug_level_lp > 1) $display("## bsg_tag_master PACKET END (%m)"); +`endif + + end + hdr_n.len = hdr_r.len - 1; + end + eStuck: + state_n = eStuck; + + default: + begin + state_n = eStuck; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + $display("## bsg_tag_master transitioning to error state; be sure to run gate-level netlist to avoid sim/synth mismatch (%m)"); +`endif + + end + endcase // case (state_r) + + end // always_comb + + genvar i; + + // demultiplex the stream to the target node + + wire [els_p-1:0] clients_decode = (v_n << hdr_r.nodeID); + + + for (i = 0; i < els_p; i=i+1) + begin: rof + always_ff @(posedge clk_i) + begin + clients_r_o[i].op <= clients_decode[i] & bsg_tag_n.op; + clients_r_o[i].param <= clients_decode[i] & bsg_tag_n.param; + end + + + assign clients_r_o[i].clk = clk_i; + assign clients_r_o[i].en = en_i; + end + + +endmodule // bsg_tag_master + +`BSG_ABSTRACT_MODULE(bsg_tag_master) + +// verilator lint_on BLKANDNBLK diff --git a/designs/black-parrot/src/basejump_stl/bsg_tag_pkg.sv b/designs/black-parrot/src/basejump_stl/bsg_tag_pkg.sv new file mode 100644 index 0000000..b1ae38d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_tag_pkg.sv @@ -0,0 +1,15 @@ +package bsg_tag_pkg; + typedef struct packed { + logic clk; + // op param + logic op; // 1 D shift D + logic param; // 0 0 nop (also "send", immediately after shift operation) + // 0 1 reset + + logic en; // this signal disables thru-transmit of new values +} bsg_tag_s; + + +endpackage // bsg_tag_pkg + + diff --git a/designs/black-parrot/src/basejump_stl/bsg_tag_trace_replay.sv b/designs/black-parrot/src/basejump_stl/bsg_tag_trace_replay.sv new file mode 100644 index 0000000..f6d5f62 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_tag_trace_replay.sv @@ -0,0 +1,163 @@ +// This module uses the synthesizable bsg_fsb_node_trace_replay module +// to communicate over bsg_tag. This module instantitates a trace-replay, +// removes the output data to match what bsg_tag is expecting, and +// finally it serializes the trace data down to a single bit. +// +// Each trace should be in the following format: +// +// M = number of masters +// N = clog2( #_of_tag_clients ) ) +// D = max( client_1_width, client_2_width, ..., client_n_width ) +// L = clog2( D + 1 ) ) +// +// |< 4-bits >|< M-bits >|< N-bits >|< 1-bit >|< L-bits >|< D-bits >| +// +----------------+----------+----------+----------------+----------+----------+ +// | replay command | masterEn | nodeID | data_not_reset | length | data | +// +----------------+----------+----------+----------------+----------+----------+ +// +// Replay Commands +// 0 = 0000 = Wait a cycle +// 1 = 0001 = Send data +// 2 = 0010 = Receive data +// 3 = 0011 = Assert done_o ouput signal +// 4 = 0100 = End test (calls $finish) +// 5 = 0101 = Wait for cycle_counter == 0 +// 6 = 0110 = Initialize cycle_counter with a 16 bit number +// +// To reset the bsg_tag_master, we just need to send a bunch of 0's, +// so we can send a trace of all 0's and just wait for many cycles. This +// will continuously send 0's down bsg_tag thus reseting the master. +// +// To reset a client, set the nodeID, data_not_reset=0, and length +// fields correctly, then set the data to all 1's. +// + +`include "bsg_defines.sv" + +module bsg_tag_trace_replay + + #( parameter `BSG_INV_PARAM(rom_addr_width_p ) + , parameter `BSG_INV_PARAM(rom_data_width_p ) + , parameter num_masters_p = 0 + , parameter `BSG_INV_PARAM(num_clients_p ) + , parameter `BSG_INV_PARAM(max_payload_width_p ) + , parameter uptime_p = 0) + + ( input clk_i + , input reset_i + , input en_i + + , output [rom_addr_width_p-1:0] rom_addr_o + , input [rom_data_width_p-1:0] rom_data_i + + , input valid_i + , input [max_payload_width_p-1:0] data_i + , output ready_o + + , output valid_o + , output [`BSG_MAX(1,num_masters_p)-1:0] en_r_o + , output tag_data_o + , input yumi_i + + , output done_o + , output error_o + ) ; + + `include "bsg_tag.svh" + + // The trace ring width is the size of the rom data width + // minus the 4-bits for the trace-replay command. + localparam trace_ring_width_lp = rom_data_width_p - 4; + + // The number of bits needed to represent the length of the + // payload inside bsg_tag. + localparam lg_max_payload_width_lp = `BSG_SAFE_CLOG2(max_payload_width_p + 1); + + // The number of bits in the header of the tag packet. + `declare_bsg_tag_header_s(num_clients_p, lg_max_payload_width_lp); + localparam bsg_tag_header_width_lp = $bits(bsg_tag_header_s); + + // Data signals between trace_replay and parallel_in_serial_out. + logic tr_valid_lo; + logic [trace_ring_width_lp-1:0] tr_data_lo; + logic tr_yumi_li; + + // Instantiate the trace replay + bsg_trace_replay #( .payload_width_p(trace_ring_width_lp) + ,.rom_addr_width_p(rom_addr_width_p) + ,.debug_p(0) + ) + trace_replay + (.clk_i (clk_i) + ,.reset_i (reset_i) + ,.en_i (en_i) + + /* input channel */ + ,.v_i (valid_i) + ,.data_i (trace_ring_width_lp ' (data_i)) + ,.ready_o (ready_o) + + /* output channel */ + ,.v_o (tr_valid_lo) + ,.data_o (tr_data_lo) + ,.yumi_i (tr_yumi_li) + + /* rom connections */ + ,.rom_addr_o (rom_addr_o) + ,.rom_data_i (rom_data_i) + + /* signals */ + ,.done_o (done_o) + ,.error_o (error_o) + ); + + // Reform the data between the trace-replay and the piso + // to properly act like a bsg_tag packet. This includes adding + // a 1-bit to the beginning of the data and a 0-bit to the + // end. Furthermore, swap the header and payload order. + wire [bsg_tag_header_width_lp-1:0] header_n = tr_data_lo[max_payload_width_p+:bsg_tag_header_width_lp]; + wire [max_payload_width_p-1:0] payload_n = tr_data_lo[0+:max_payload_width_p]; + wire [trace_ring_width_lp + 2 - 1:0] data_n = {1'b0, payload_n, header_n, 1'b1}; + + wire piso_ready_lo; + assign tr_yumi_li = piso_ready_lo & tr_valid_lo; + + // Instantiate the paralle-in serial-out data structure. + bsg_parallel_in_serial_out #( .width_p(1) + , .els_p(trace_ring_width_lp + 2) ) + trace_piso + (.clk_i (clk_i) + ,.reset_i (reset_i) + + /* Data Input Channel (Valid then Yumi) */ + ,.valid_i (tr_valid_lo) + ,.data_i (data_n) + ,.ready_and_o (piso_ready_lo) + + /* Data Output Channel (Valid then Yumi) */ + ,.valid_o (valid_o) + ,.data_o (tag_data_o) + ,.yumi_i (yumi_i) + ); + + // If there are "no masters" (or at least none required to drive the enables + // for) then we will disconnect en_r_o, otherwise we will instantiate a + // register to capture the enables. + if (num_masters_p == 0) + begin + assign en_r_o = 1'bz; + end + else + begin + bsg_dff_en #( .width_p(num_masters_p) ) + en_reg + (.clk_i (clk_i) + ,.en_i (tr_valid_lo & piso_ready_lo) + ,.data_i (tr_data_lo[(max_payload_width_p+bsg_tag_header_width_lp)+:num_masters_p]) + ,.data_o (en_r_o) + ); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_tag_trace_replay) diff --git a/designs/black-parrot/src/basejump_stl/bsg_thermometer_count.sv b/designs/black-parrot/src/basejump_stl/bsg_thermometer_count.sv new file mode 100644 index 0000000..5a014e7 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_thermometer_count.sv @@ -0,0 +1,68 @@ +// MBT 10-26-14 +// +// +// Counts the number of set bits in a thermometer code. +// A thermometer code is of the form 0*1*. +// + +`include "bsg_defines.sv" + +module bsg_thermometer_count #(parameter `BSG_INV_PARAM(width_p )) + (input [width_p-1:0] i + // we need to represent width_p+1 values (0..width_p), so + // we need the +1. + , output [$clog2(width_p+1)-1:0] o + ); + + // parallel prefix is a bit slow for these cases + + if (width_p == 1) + assign o = i; + else + if (width_p == 2) + assign o = { i[1], i[0] & ~ i[1] }; + else + // 000 0 0 + // 001 0 1 + // 011 1 0 + // 111 1 1 + + if (width_p == 3) + assign o = { i[1], i[2] | (i[0] & ~i[1]) }; + else + // 3210 + // 0000 0 0 0 + // 0001 0 0 1 + // 0011 0 1 0 + // 0111 0 1 1 + // 1111 1 0 0 + + if (width_p == 4) + // assign o = {i[3], ~i[3] & i[1], (~i[3] & i[0]) & ~(i[2]^i[1]) }; + // DC likes the xor's + assign o = {i[3], ~i[3] & i[1], ^i }; + else + + // this converts from a thermometer code (01111) + // to a one hot code (10000) + // basically by edge-detecting it. + // + // the important parts are the corner cases: + // 0000 --> ~(0_0000) & (0000_1) --> 0000_1 (0) + // 1111 --> ~(0_1111) & (1111_0) --> 1_0000 (4) + // + + begin : big + wire [width_p:0] one_hot = ( ~{ 1'b0, i } ) + & ( { i , 1'b1 } ); + + bsg_encode_one_hot #(.width_p(width_p+1)) encode_one_hot + (.i(one_hot) + ,.addr_o(o) + ,.v_o() + ); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_thermometer_count) diff --git a/designs/black-parrot/src/basejump_stl/bsg_transpose.sv b/designs/black-parrot/src/basejump_stl/bsg_transpose.sv new file mode 100644 index 0000000..b27e18a --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_transpose.sv @@ -0,0 +1,20 @@ +`include "bsg_defines.sv" + +module bsg_transpose #(`BSG_INV_PARAM(width_p) + ,`BSG_INV_PARAM(els_p) + ) (input [els_p-1:0 ][width_p-1:0] i + , output [width_p-1:0][els_p-1:0] o + ); + genvar x, y; + + for (x = 0; x < els_p; x++) + begin: rof + for (y = 0; y < width_p; y++) + begin: rof2 + assign o[y][x] = i[x][y]; + end + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_transpose) diff --git a/designs/black-parrot/src/basejump_stl/bsg_two_fifo.sv b/designs/black-parrot/src/basejump_stl/bsg_two_fifo.sv new file mode 100644 index 0000000..b6c65fd --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_two_fifo.sv @@ -0,0 +1,147 @@ +// MBT 9-7-2014 +// +// two element fifo +// +// helpful interface on both input and output +// +// input : ready/valid flow control (rv->&) +// output: valid->yumi flow control ( v->r) +// +// see https://github.com/bespoke-silicon-group/basejump_stl/blob/master/docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf +// to understand the flow control standards in BaseJump STL. +// +// INPUTS: although this module's inputs adheres to +// ready/valid protocol where both sender and receiver +// AND the two signals together to determine +// if transaction happened; in some cases, we +// know that the sender takes into account the +// ready signal before sending out valid, and the +// check is unnecessary. We use ready_THEN_valid_p +// to remove the check if it is unnecessary. +// +// +// note: ~v_o == fifo is empty. +// + +`include "bsg_defines.sv" + +module bsg_two_fifo #(parameter `BSG_INV_PARAM(width_p) + , parameter verbose_p=0 + // whether we should allow simultaneous enque and deque on full + , parameter allow_enq_deq_on_full_p=0 + // necessarily, if we allow enq on ready low, then + // we are not using a ready/valid protocol + , parameter ready_THEN_valid_p=allow_enq_deq_on_full_p + ) + (input clk_i + , input reset_i + + // input side + , output ready_param_o // early + , input [width_p-1:0] data_i // late + , input v_i // late + + // output side + , output v_o // early + , output[width_p-1:0] data_o // early + , input yumi_i // late + ); + + wire deq_i = yumi_i; + wire enq_i; + + logic head_r, tail_r; + logic empty_r, full_r; + + bsg_mem_1r1w #(.width_p(width_p) + ,.els_p(2) + ,.read_write_same_addr_p(allow_enq_deq_on_full_p) + ) mem_1r1w + (.w_clk_i (clk_i ) + ,.w_reset_i(reset_i) + ,.w_v_i (enq_i ) + ,.w_addr_i (tail_r ) + ,.w_data_i (data_i ) + ,.r_v_i (~empty_r) + ,.r_addr_i (head_r ) + ,.r_data_o (data_o ) + ); + + assign v_o = ~empty_r; + assign ready_param_o = ~full_r; + + if (ready_THEN_valid_p) + assign enq_i = v_i; + else + assign enq_i = v_i & ~full_r; + + always_ff @(posedge clk_i) + begin + if (reset_i) + begin + tail_r <= 1'b0; + head_r <= 1'b0; + empty_r <= 1'b1; + full_r <= 1'b0; + end + else + begin + if (enq_i) + tail_r <= ~tail_r; + + if (deq_i) + head_r <= ~head_r; + + // logic simplifies nicely for 2 element case + empty_r <= ( empty_r & ~enq_i) + | (~full_r & deq_i & ~enq_i); + + if (allow_enq_deq_on_full_p) + full_r <= ( ~empty_r & enq_i & ~deq_i) + | ( full_r & ~(deq_i^enq_i)); + else + full_r <= ( ~empty_r & enq_i & ~deq_i) + | ( full_r & ~deq_i); + end // else: !if(reset_i) + end // always_ff @ + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @(posedge clk_i) + begin + if (~reset_i) + begin + assert ({empty_r, deq_i} !== 2'b11) + else $error("invalid deque on empty fifo ", empty_r, deq_i); + + if (allow_enq_deq_on_full_p) + begin + assert ({full_r,enq_i,deq_i} !== 3'b110) + else $error("invalid enque on full fifo ", full_r, enq_i); + end + else + assert ({full_r,enq_i} !== 2'b11) + else $error("invalid enque on full fifo ", full_r, enq_i); + + assert ({full_r,empty_r} !== 2'b11) + else $error ("fifo full and empty at same time ", full_r, empty_r); + end // if (~reset_i) + end // always_ff @ + + always_ff @(posedge clk_i) + if (verbose_p) + begin + if (enq_i) + $display("### %m enq %x onto fifo",data_i); + + if (deq_i) + $display("### %m deq %x from fifo",data_o); + end + + // for debugging + wire [31:0] num_elements_debug = full_r + (empty_r==0); + +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_two_fifo) diff --git a/designs/black-parrot/src/basejump_stl/bsg_unconcentrate_static.sv b/designs/black-parrot/src/basejump_stl/bsg_unconcentrate_static.sv new file mode 100644 index 0000000..433b810 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_unconcentrate_static.sv @@ -0,0 +1,29 @@ +// takes an input vector and spreads the elements according to a bit pattern +// example width_p=3, pattern_els_p=5'b10101 +`include "bsg_defines.sv" + +module bsg_unconcentrate_static #(`BSG_INV_PARAM(pattern_els_p) + , width_lp=`BSG_COUNTONES_SYNTH(pattern_els_p) + , unconnected_val_p=`BSG_DISCONNECTED_IN_SIM(1'b0) + ) +(input [width_lp-1:0] i + ,output [$bits(pattern_els_p)-1:0] o + ); + genvar j; + + if (pattern_els_p[0]) + assign o[0] = i[0]; + else + assign o[0] = unconnected_val_p; + + for (j = 1; j < $bits(pattern_els_p); j=j+1) + begin: rof + if (pattern_els_p[j]) + assign o[j] = i[`BSG_COUNTONES_SYNTH(pattern_els_p[j-1:0])]; + else + assign o[j] = unconnected_val_p; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_unconcentrate_static) diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator.sv new file mode 100644 index 0000000..3403b48 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator.sv @@ -0,0 +1,136 @@ +// +// bsg_wormhole_concentrator.sv +// +// 08/2019 +// +// This is an adapter between 1 concentrated wormhole link and N unconcentrated wormhole links. +// Extra bits (cid) are used in wormhole header to indicate wormhole packet destination. +// +// From implementation perspective this is a simplified version bsg_wormhole_router. +// Wormhole_router relies on 2D routing_matrix, while wormhole_concentrator has fixed 1-to-n +// and n-to-1 routing. This concentrator reuses most of the building blocks of wormhole_router, +// concentrator header struct is defined in bsg_wormhole_router.svh. +// +// This concentrator has 1-cycle delay from input wormhole link(s) to output wormhole link(s). +// It has zero bubble between wormhole packets. +// +// + +`include "bsg_defines.sv" +`include "bsg_noc_links.svh" +`include "bsg_wormhole_router.svh" + +module bsg_wormhole_concentrator + + #(parameter `BSG_INV_PARAM(flit_width_p) + ,parameter `BSG_INV_PARAM(len_width_p) + ,parameter `BSG_INV_PARAM(cid_width_p) + ,parameter `BSG_INV_PARAM(cord_width_p) + ,parameter num_in_p = 1 + ,parameter debug_lp = 0 + ,parameter link_width_lp = `bsg_ready_and_link_sif_width(flit_width_p) + // Hold on valid sets the arbitration policy such that once an output tag is selected, it + // remains selected until it is acked, then the round-robin scheduler continues cycling + // from the selected tag. This is consistent with BaseJump STL handshake assumptions. + // Notably, this parameter is required to work with bsg_parallel_in_serial_out_passthrough. + // This policy has a slight throughput degradation but effectively arbitrates based on age, + // so minimizes worst case latency. + ,parameter hold_on_valid_p = 0 + ) + + (input clk_i + ,input reset_i + + // unconcentrated multiple links + ,input [num_in_p-1:0][link_width_lp-1:0] links_i + ,output [num_in_p-1:0][link_width_lp-1:0] links_o + + // concentrated single link + ,input [link_width_lp-1:0] concentrated_link_i + ,output [link_width_lp-1:0] concentrated_link_o + ); + + + logic [num_in_p-1:0] links_v_li; + logic [num_in_p-1:0][flit_width_p-1:0] links_data_li; + + `declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s); + + bsg_ready_and_link_sif_s [num_in_p-1:0] links_i_cast, links_o_cast; + logic [num_in_p-1:0] links_ready_and_rev_lo, links_ready_and_rev_li; + + bsg_ready_and_link_sif_s concentrated_link_i_cast, concentrated_link_o_cast; + + logic [num_in_p-1:0][flit_width_p-1:0] links_data_lo; + logic [num_in_p-1:0] links_v_lo; + + logic concentrated_link_ready_and_rev_lo; + + assign links_i_cast = links_i; + assign links_o = links_o_cast; + + assign concentrated_link_i_cast = concentrated_link_i; + assign concentrated_link_o = concentrated_link_o_cast; + + for (genvar i = 0; i < num_in_p; i++) + begin : cast + assign links_o_cast[i].v = links_v_lo [i]; + assign links_o_cast[i].data = links_data_lo[i]; + + assign links_o_cast[i].ready_and_rev = links_ready_and_rev_lo[i]; + + assign links_ready_and_rev_li[i] = links_i_cast[i].ready_and_rev; + + assign links_v_li[i] = links_i_cast[i].v; + assign links_data_li[i] = links_i_cast[i].data; + end + + assign concentrated_link_o_cast.ready_and_rev = concentrated_link_ready_and_rev_lo; + + bsg_wormhole_concentrator_in + #(.flit_width_p(flit_width_p) + ,.len_width_p(len_width_p) + ,.num_in_p(num_in_p) + ,.cord_width_p(cord_width_p) + ,.debug_lp(debug_lp) + ,.hold_on_valid_p(hold_on_valid_p) + ) + concentrator_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.links_v_i (links_v_li) + ,.links_data_i (links_data_li) + ,.links_ready_and_rev_o(links_ready_and_rev_lo) + + ,.concentrated_link_ready_and_rev_i(concentrated_link_i_cast.ready_and_rev) + ,.concentrated_link_v_o (concentrated_link_o_cast.v) + ,.concentrated_link_data_o (concentrated_link_o_cast.data) + ); + + bsg_wormhole_concentrator_out + #(.flit_width_p(flit_width_p) + ,.len_width_p(len_width_p) + ,.cid_width_p(cid_width_p) + ,.num_in_p(num_in_p) + ,.cord_width_p(cord_width_p) + ,.debug_lp(debug_lp) + ,.hold_on_valid_p(hold_on_valid_p) + ) + concentrator_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.links_v_o (links_v_lo) + ,.links_data_o (links_data_lo) + ,.links_ready_and_rev_i(links_ready_and_rev_li) + + ,.concentrated_link_v_i (concentrated_link_i_cast.v ) + ,.concentrated_link_data_i (concentrated_link_i_cast.data ) + ,.concentrated_link_ready_and_rev_o(concentrated_link_ready_and_rev_lo) + ); + +endmodule + + +`BSG_ABSTRACT_MODULE(bsg_wormhole_concentrator) diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator_in.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator_in.sv new file mode 100644 index 0000000..3b8f5f0 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator_in.sv @@ -0,0 +1,127 @@ +// +// bsg_wormhole_concentrator_in.sv +// +// 08/2019 +// +// This is an adapter from N unconcentrated wormhole links to one concentrated wormhole link. +// Extra bits (cid) can be used in wormhole header to indicate wormhole packet destination, but these +// are set by the sender and not by the concentrator. +// +// From implementation perspective this is a simplified version bsg_wormhole_router. +// Wormhole_router relies on 2D routing_matrix, while wormhole_concentrator has fixed 1-to-n +// and n-to-1 routing. This concentrator reuses most of the building blocks of wormhole_router, +// concentrator header struct is defined in bsg_wormhole_router.svh. +// +// This concentrator has 1-cycle delay from input wormhole link(s) to output wormhole link(s). +// It has zero bubble between wormhole packets. +// +// + +`include "bsg_defines.sv" +`include "bsg_noc_links.svh" +`include "bsg_wormhole_router.svh" + +module bsg_wormhole_concentrator_in + + #(parameter `BSG_INV_PARAM(flit_width_p) + ,parameter `BSG_INV_PARAM(len_width_p) + ,parameter `BSG_INV_PARAM(cord_width_p) + ,parameter num_in_p = 1 + ,parameter debug_lp = 0 + ,parameter hold_on_valid_p = 0 + ) + + (input clk_i + ,input reset_i + + // unconcentrated multiple links + ,input [num_in_p-1:0] links_v_i + ,input [num_in_p-1:0][flit_width_p-1:0] links_data_i + ,output [num_in_p-1:0] links_ready_and_rev_o + + // concentrated single link + ,input concentrated_link_ready_and_rev_i + ,output concentrated_link_v_o + ,output [flit_width_p-1:0] concentrated_link_data_o + ); + + // we use bsg_wormhole_router_header_s here instead of bsg_wormhole_concentrator_header_s to allow for cid_width_p=0 + // this requires that they have the same layout + `declare_bsg_wormhole_router_header_s(cord_width_p, len_width_p, bsg_wormhole_router_header_s); + + + genvar i,j; + + /********** From unconcentrated side to concentrated side **********/ + + wire [num_in_p-1:0][flit_width_p-1:0] fifo_data_lo; + wire [num_in_p-1:0] fifo_valid_lo; + + // one for each input channel; it broadcasts that it is finished to all of the outputs + wire [num_in_p-1:0] releases; + + // from each input to concentrated output + wire [num_in_p-1:0] reqs; + + // from concentrated output to each input + wire [num_in_p-1:0] yumis; + + for (i = 0; i < num_in_p; i=i+1) + begin: in_ch + + bsg_two_fifo #(.width_p(flit_width_p)) twofer + (.clk_i + ,.reset_i + + ,.v_i (links_v_i [i]) + ,.data_i (links_data_i[i]) + ,.ready_param_o (links_ready_and_rev_o[i]) + + ,.v_o (fifo_valid_lo[i]) + ,.data_o (fifo_data_lo [i]) + ,.yumi_i (yumis[i]) + ); + + bsg_wormhole_router_header_s concentrated_hdr; + assign concentrated_hdr = fifo_data_lo[i][$bits(bsg_wormhole_router_header_s)-1:0]; + + bsg_wormhole_router_input_control #(.output_dirs_p(1), .payload_len_bits_p($bits(concentrated_hdr.len))) wic + (.clk_i + ,.reset_i + ,.fifo_v_i (fifo_valid_lo[i]) + ,.fifo_yumi_i (yumis[i]) + ,.fifo_decoded_dest_i(1'b1) + ,.fifo_payload_len_i (concentrated_hdr.len) + ,.reqs_o (reqs[i]) + ,.release_o (releases[i]) // broadcast to all + ,.detected_header_o () + ); + + end + + wire [num_in_p-1:0] data_sel_lo; + + bsg_wormhole_router_output_control + #(.input_dirs_p(num_in_p), .hold_on_valid_p(hold_on_valid_p)) woc + (.clk_i + ,.reset_i + ,.reqs_i (reqs ) + ,.release_i (releases ) + ,.valid_i (fifo_valid_lo) + ,.yumi_o (yumis ) + ,.ready_and_i (concentrated_link_ready_and_rev_i) + ,.valid_o (concentrated_link_v_o) + ,.data_sel_o (data_sel_lo) + ); + + bsg_mux_one_hot #(.width_p(flit_width_p) + ,.els_p (num_in_p) + ) data_mux + (.data_i (fifo_data_lo) + ,.sel_one_hot_i(data_sel_lo) + ,.data_o (concentrated_link_data_o) + ); + +endmodule // bsg_wormhole_concentrator_in + +`BSG_ABSTRACT_MODULE(bsg_wormhole_concentrator_in) diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator_out.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator_out.sv new file mode 100644 index 0000000..4efaa4d --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_concentrator_out.sv @@ -0,0 +1,124 @@ +// +// bsg_wormhole_concentrator_out.sv +// +// 08/2019 +// +// This is an adapter from 1 concentrated wormhole link to N unconcentrated wormhole links. +// The field CID in the header determines which of the unconcentrated links the packet is routed to, +// this is set by the sender. +// +// From implementation perspective this is a simplified version bsg_wormhole_router. +// Wormhole_router relies on 2D routing_matrix, while wormhole_concentrator has fixed 1-to-n +// and n-to-1 routing. This concentrator reuses most of the building blocks of wormhole_router, +// concentrator header struct is defined in bsg_wormhole_router.svh. +// +// This concentrator has 1-cycle delay from input wormhole link(s) to output wormhole link(s). +// It has zero bubble between wormhole packets. +// +// + +`include "bsg_defines.sv" +`include "bsg_noc_links.svh" +`include "bsg_wormhole_router.svh" + +module bsg_wormhole_concentrator_out + + #(parameter `BSG_INV_PARAM(flit_width_p) + ,parameter `BSG_INV_PARAM(len_width_p) + ,parameter `BSG_INV_PARAM(cid_width_p) + ,parameter `BSG_INV_PARAM(cord_width_p) + ,parameter num_in_p = 1 + ,parameter debug_lp = 0 + ,parameter hold_on_valid_p = 0 + ) + + (input clk_i + ,input reset_i + + // unconcentrated multiple links + ,output [num_in_p-1:0] links_v_o + ,output [num_in_p-1:0][flit_width_p-1:0] links_data_o + ,input [num_in_p-1:0] links_ready_and_rev_i + + // concentrated single link + ,input concentrated_link_v_i + ,input [flit_width_p-1:0] concentrated_link_data_i + ,output concentrated_link_ready_and_rev_o + ); + + `declare_bsg_wormhole_concentrator_header_s(cord_width_p, len_width_p, cid_width_p, bsg_wormhole_concentrator_header_s); + + genvar i,j; + + /********** From concentrated side to unconcentrated side **********/ + + wire [flit_width_p-1:0] concentrated_fifo_data_lo; + wire concentrated_fifo_valid_lo; + + // one for each input channel; it broadcasts that it is finished to all of the outputs + wire concentrated_releases; + + // from concentrated input to each output + wire [num_in_p-1:0] concentrated_reqs; + + // from each output to concentrated input + wire [num_in_p-1:0] concentrated_yumis; + + wire concentrated_any_yumi = | concentrated_yumis; + + bsg_two_fifo #(.width_p(flit_width_p)) concentrated_twofer + (.clk_i + ,.reset_i + ,.ready_param_o (concentrated_link_ready_and_rev_o) + ,.data_i (concentrated_link_data_i) + ,.v_i (concentrated_link_v_i) + ,.v_o (concentrated_fifo_valid_lo) + ,.data_o (concentrated_fifo_data_lo ) + ,.yumi_i (concentrated_any_yumi) + ); + + bsg_wormhole_concentrator_header_s concentrated_hdr; + assign concentrated_hdr = concentrated_fifo_data_lo[$bits(bsg_wormhole_concentrator_header_s)-1:0]; + + wire [num_in_p-1:0] concentrated_decoded_dest_lo; + bsg_decode #(.num_out_p(num_in_p)) concentrated_decoder + (.i(concentrated_hdr.cid[0+:`BSG_SAFE_CLOG2(num_in_p)]) + ,.o(concentrated_decoded_dest_lo) + ); + + bsg_wormhole_router_input_control #(.output_dirs_p(num_in_p), .payload_len_bits_p($bits(concentrated_hdr.len))) concentrated_wic + (.clk_i + ,.reset_i + ,.fifo_v_i (concentrated_fifo_valid_lo) + ,.fifo_yumi_i (concentrated_any_yumi) + ,.fifo_decoded_dest_i(concentrated_decoded_dest_lo) + ,.fifo_payload_len_i (concentrated_hdr.len) + ,.reqs_o (concentrated_reqs) + ,.release_o (concentrated_releases) // broadcast to all + ,.detected_header_o () + ); + + // iterate through each output channel + for (i = 0; i < num_in_p; i=i+1) + begin: out_ch + + bsg_wormhole_router_output_control + #(.input_dirs_p(1), .hold_on_valid_p(hold_on_valid_p)) concentrated_woc + (.clk_i + ,.reset_i + ,.reqs_i (concentrated_reqs[i] ) + ,.release_i (concentrated_releases) + ,.valid_i (concentrated_fifo_valid_lo) + ,.yumi_o (concentrated_yumis[i]) + ,.ready_and_i (links_ready_and_rev_i[i]) + ,.valid_o (links_v_o[i]) + ,.data_sel_o() + ); + + assign links_data_o[i] = concentrated_fifo_data_lo; + + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_wormhole_concentrator_out) diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_router.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router.sv new file mode 100644 index 0000000..d81f610 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router.sv @@ -0,0 +1,268 @@ +`include "bsg_defines.sv" +`include "bsg_noc_links.svh" +`include "bsg_wormhole_router.svh" + +module bsg_wormhole_router + import bsg_wormhole_router_pkg::StrictXY; + import bsg_wormhole_router_pkg::StrictX; + #(parameter `BSG_INV_PARAM(flit_width_p) + ,parameter dims_p = 2 // 1 + ,parameter dirs_lp = dims_p*2+1 + + // this list determines the range of bit values used to determine each dimension in the N-D router + // cord_dims_p is normally the same as dims_p. However, the override allows users to pass + // a larger cord array than necessary, useful for parameterizing between 1d/nd networks + ,parameter cord_dims_p = dims_p + ,parameter int cord_markers_pos_p[cord_dims_p:0] = '{ 5, 4, 0 } // '{5,0} // + ,parameter bit [1:0][dirs_lp-1:0][dirs_lp-1:0] routing_matrix_p = (dims_p == 2) ? StrictXY : StrictX + ,parameter reverse_order_p = 0 + ,parameter `BSG_INV_PARAM(len_width_p) + ,parameter debug_lp = 0 + // Hold on valid sets the arbitration policy such that once an output tag is selected, it + // remains selected until it is acked, then the round-robin scheduler continues cycling + // from the selected tag. This is consistent with BaseJump STL handshake assumptions. + // Notably, this parameter is required to work with bsg_parallel_in_serial_out_passthrough. + // This policy has a slight throughput degradation but effectively arbitrates based on age, + // so minimizes worst case latency. + ,parameter hold_on_valid_p = 0 + ) + + (input clk_i + ,input reset_i + + // Traffics + ,input [dirs_lp-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] link_i + ,output [dirs_lp-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] link_o + + // My coordinate data + ,input [cord_markers_pos_p[dims_p]-1:0] my_cord_i + ); + + localparam input_dirs_lp = dirs_lp; + localparam output_dirs_lp = dirs_lp; + + // FIXME: move to bsg_wormhole_router.svh + `declare_bsg_wormhole_router_header_s(cord_markers_pos_p[dims_p], len_width_p, bsg_wormhole_router_header_s); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + wire [dirs_lp-1:0][dirs_lp-1:0] matrix_out_in_transpose; + + bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) tr (.i(routing_matrix_p[0]) + ,.o(matrix_out_in_transpose) + ); + always_ff @(negedge reset_i) + begin + assert (routing_matrix_p[1] == matrix_out_in_transpose) + else $error("inconsistent matrixes"); + end +`endif + + // we collect the information for each FIFO here + wire [input_dirs_lp-1:0][flit_width_p-1:0] fifo_data_lo; + wire [input_dirs_lp-1:0] fifo_valid_lo; + + // one for each input channel; it broadcasts that it is finished to all of the outputs + wire [dirs_lp-1:0] releases; + + // from each input to each output + wire [dirs_lp-1:0][dirs_lp-1:0] reqs, reqs_transpose; + + // from each output to each input + wire [dirs_lp-1:0][dirs_lp-1:0] yumis, yumis_transpose; + + `declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s); + bsg_ready_and_link_sif_s [dirs_lp-1:0] link_i_cast, link_o_cast; + + assign link_i_cast = link_i; + assign link_o = link_o_cast; + + genvar i,j; + + for (i = 0; i < input_dirs_lp; i=i+1) + begin: in_ch + localparam output_dirs_sparse_lp = `BSG_COUNTONES_SYNTH(routing_matrix_p[0][i]); + + // live decoding of output dirs from header + + wire [output_dirs_lp-1:0] decoded_dest_lo; + wire [output_dirs_sparse_lp-1:0] decoded_dest_sparse_lo; + wire [output_dirs_sparse_lp-1:0] reqs_lo, yumis_li; + + bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) conc + (.i(yumis_transpose[i]) + ,.o(yumis_li) + ); + + wire any_yumi = | yumis_li; + + bsg_two_fifo #(.width_p(flit_width_p)) twofer + (.clk_i + ,.reset_i + ,.ready_param_o (link_o_cast[i].ready_and_rev) + ,.data_i (link_i_cast[i].data) + ,.v_i (link_i_cast[i].v) + ,.v_o (fifo_valid_lo[i]) + ,.data_o (fifo_data_lo [i]) + ,.yumi_i (any_yumi) + ); + + bsg_wormhole_router_header_s hdr; + + assign hdr = fifo_data_lo[i][$bits(bsg_wormhole_router_header_s)-1:0]; + +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (debug_lp) + begin + logic release_r; + + always_ff @(posedge clk_i) + release_r <= releases[i]; + + always_ff @(negedge clk_i) + begin + if (releases[i] & ~release_r) + $display("%m in ch%2d: packet finished last cycle",i); + + if ((reset_i === 1'b0) && link_i_cast[i].v && !link_o_cast[i].ready_and_rev) + $display("%m in ch%2d: nacking packet %h",i,link_i_cast[i].data); + else + if ((reset_i === 1'b0) && link_i_cast[i].v && link_o_cast[i].ready_and_rev) + $display("%m in ch%2d: accepting packet %h",i,link_i_cast[i].data); + if ((reset_i === 1'b0) && any_yumi) + begin + assert (fifo_valid_lo[i]) else $error("Error dequeing when data not available"); + if (reqs_lo) + $display("%m in ch%2d: dequeing header %h (outch=%b,len=%b,dest=%b)",i,fifo_data_lo[i],reqs_lo,hdr.len,hdr.cord); + else + $display ("%m in ch%2d: dequeing packet %h",i, fifo_data_lo[i]); + end + + end // always_ff @ + end +`endif + + bsg_wormhole_router_decoder_dor #(.dims_p(dims_p) + ,.cord_dims_p(cord_dims_p) + ,.reverse_order_p(reverse_order_p) + ,.cord_markers_pos_p(cord_markers_pos_p) + ) dor + (.target_cord_i(hdr.cord) + ,.my_cord_i + ,.req_o(decoded_dest_lo) + ); + + bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) conc_dec + (.i(decoded_dest_lo) + ,.o(decoded_dest_sparse_lo) + ); + + // fixme: add assertions for stubbed out parameters + + wire detected_header_lo; + + bsg_wormhole_router_input_control #(.output_dirs_p(output_dirs_sparse_lp), .payload_len_bits_p($bits(hdr.len))) wic + (.clk_i + ,.reset_i + ,.fifo_v_i (fifo_valid_lo[i]) + ,.fifo_yumi_i (any_yumi) + ,.fifo_decoded_dest_i(decoded_dest_sparse_lo) + ,.fifo_payload_len_i (hdr.len) + ,.reqs_o (reqs_lo) + ,.release_o (releases[i]) // broadcast to all + ,.detected_header_o (detected_header_lo) + ); + + // switch to dense matrix form + bsg_unconcentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) unc + (.i (reqs_lo) + ,.o (reqs[i]) // unicast + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @(negedge clk_i) + if (debug_lp) + assert (detected_header_lo!==1'b1 || !(decoded_dest_lo & ~ routing_matrix_p[0][i])) + else $error("%m input port %d request to route in direction not supported by router %b %b",i,decoded_dest_lo, routing_matrix_p[0][i]); +`endif + + end + + // flip signal wires from input-indexed to output-indexed + // this is swizzling the wires that connect input ports and output ports + bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) reqs_trans + (.i(reqs) + ,.o(reqs_transpose) + ); + + // iterate through each output channel + for (i = 0; i < output_dirs_lp; i=i+1) + begin: out_ch + localparam input_dirs_sparse_lp = `BSG_COUNTONES_SYNTH(routing_matrix_p[1][i]); + wire [input_dirs_sparse_lp-1:0] reqs_li, release_li, valids_li, yumis_lo, data_sel_lo; + wire [input_dirs_sparse_lp-1:0][flit_width_p-1:0] fifo_data_sparse_lo; + + bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc + (.i(reqs_transpose[i]),.o(reqs_li)); + + bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc2 + (.i(releases),.o(release_li)); + + bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc3 + (.i(fifo_valid_lo),.o(valids_li)); + + bsg_array_concentrate_static #(.width_p(flit_width_p), .pattern_els_p(routing_matrix_p[1][i])) conc4 + (.i(fifo_data_lo),.o(fifo_data_sparse_lo)); + + bsg_wormhole_router_output_control + #(.input_dirs_p(input_dirs_sparse_lp), .hold_on_valid_p(hold_on_valid_p)) woc + (.clk_i + ,.reset_i + ,.reqs_i (reqs_li ) + ,.release_i (release_li) + ,.valid_i (valids_li ) + ,.yumi_o (yumis_lo ) + ,.ready_and_i (link_i_cast[i].ready_and_rev) + ,.valid_o (link_o_cast[i].v) + ,.data_sel_o (data_sel_lo) + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @(negedge clk_i) + begin + if (debug_lp) + begin + if ((reset_i === 1'b0) && link_o_cast[i].v) + begin + if (link_i_cast[i].ready_and_rev) + begin + $display("%m out ch%2d: sending packet %h",i,link_o_cast[i].data); + end + end + end + end +`endif + + bsg_mux_one_hot #(.width_p(flit_width_p) + ,.els_p(input_dirs_sparse_lp) + ) data_mux + (.data_i(fifo_data_sparse_lo) + ,.sel_one_hot_i(data_sel_lo) + ,.data_o(link_o_cast[i].data) + ); + + bsg_unconcentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) unc1 + (.i (yumis_lo) + ,.o (yumis[i]) + ); + end + + // flip signal wires from output-indexed to input-indexed + // this is swizzling the wires that connect input ports and output ports + bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) yumis_trans + (.i(yumis) + ,.o(yumis_transpose) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_wormhole_router) diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_router.svh b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router.svh new file mode 100644 index 0000000..8dd80c3 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router.svh @@ -0,0 +1,49 @@ +// this is a partial packet header should always go at the bottom bits of a header flit +// move to bsg_wormhole_router.svh +// FIXME: have them pass in the cord_markers_pos_p +// struct, then it will match bsg_wormhole_router +// + +`define declare_bsg_wormhole_router_header_s(cord_width_mp, len_width_mp, struct_name_mp) \ +typedef struct packed { \ + logic [len_width_mp-1:0] len; \ + logic [cord_width_mp-1:0 ] cord; \ +} struct_name_mp + +// the low bits of this should have exactly the same format as the header above +// this is particularly important for bsg_wormhole_concentrator_in.sv + +`define declare_bsg_wormhole_concentrator_header_s(cord_width_mp, len_width_mp, cid_width, struct_name_mp) \ + typedef struct packed { \ + logic [cid_width-1:0] cid; \ + logic [len_width_mp-1:0] len; \ + logic [cord_width_mp-1:0] cord; \ + } struct_name_mp + +`define declare_bsg_wormhole_router_packet_s(cord_width_mp, len_width_mp, payload_width_mp, struct_name_mp) \ +typedef struct packed { \ + logic [payload_width_mp-1:0] payload; \ + logic [len_width_mp-1:0] len; \ + logic [cord_width_mp-1:0] cord; \ +} struct_name_mp + +`define declare_bsg_wormhole_concentrator_packet_s(cord_width_mp, len_width_mp, cid_width_mp, payload_width_mp, struct_name_mp) \ +typedef struct packed { \ + logic [payload_width_mp-1:0] payload; \ + logic [cid_width_mp-1:0] cid; \ + logic [len_width_mp-1:0] len; \ + logic [cord_width_mp-1:0] cord; \ +} struct_name_mp + +`define bsg_wormhole_router_header_width(cord_width_mp, len_width_mp) \ + (cord_width_mp + len_width_mp) + +`define bsg_wormhole_concentrator_header_width(cord_width_mp, len_width_mp, cid_width_mp) \ + (cord_width_mp + len_width_mp + cid_width_mp) + +`define bsg_wormhole_concentrator_packet_width(cord_width_mp, len_width_mp, cid_width_mp, payload_width_mp) \ + (cord_width_mp + len_width_mp + cid_width_mp + payload_width_mp) + +`define bsg_wormhole_router_packet_width(cord_width_mp, len_width_mp, payload_width_mp) \ + (cord_width_mp + len_width_mp + payload_width_mp) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_adapter_in.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_adapter_in.sv new file mode 100644 index 0000000..5f871e4 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_adapter_in.sv @@ -0,0 +1,75 @@ +/** + * bsg_wormhole_router_adapter_in.sv + * + * packet = {payload, length, cord} + * + * Goes from a wide register containing an entire packet to a serialized packet. + * Most useful for testbenches, and in hardware, shorter packets where the data is + * not naturally serialized. + */ + +`include "bsg_defines.sv" + +`include "bsg_noc_links.svh" +`include "bsg_wormhole_router.svh" + +module bsg_wormhole_router_adapter_in + #(parameter `BSG_INV_PARAM(max_payload_width_p ) + , parameter `BSG_INV_PARAM(len_width_p ) + , parameter `BSG_INV_PARAM(cord_width_p ) + , parameter `BSG_INV_PARAM(flit_width_p ) + + , localparam bsg_ready_and_link_sif_width_lp = + `bsg_ready_and_link_sif_width(flit_width_p) + , localparam bsg_wormhole_packet_width_lp = + `bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p) + ) + (input clk_i + , input reset_i + + , input [bsg_wormhole_packet_width_lp-1:0] packet_i + , input packet_v_i + , output packet_ready_and_o + + , output [flit_width_p-1:0] link_data_o + , output link_v_o + , input link_ready_and_i + ); + + `declare_bsg_wormhole_router_packet_s(cord_width_p, len_width_p, max_payload_width_p, bsg_wormhole_packet_s); + bsg_wormhole_packet_s packet_cast_i; + assign packet_cast_i = packet_i; + + localparam max_num_flits_lp = `BSG_CDIV($bits(bsg_wormhole_packet_s), flit_width_p); + localparam protocol_len_lp = `BSG_SAFE_CLOG2(max_num_flits_lp); + wire [max_num_flits_lp*flit_width_p-1:0] packet_padded_li = packet_i; + + bsg_parallel_in_serial_out_dynamic + #(.width_p(flit_width_p) + ,.max_els_p(max_num_flits_lp) + ) + piso + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(packet_v_i) + ,.len_i(protocol_len_lp'(packet_cast_i.len)) + ,.data_i(packet_padded_li) + ,.ready_and_o(packet_ready_and_o) + + ,.v_o(link_v_o) + ,.len_v_o(/* unused */) + ,.data_o(link_data_o) + ,.yumi_i(link_ready_and_i & link_v_o) + ); + +`ifndef BSG_HIDE_FROM_SYNTHESIS + always_ff @(negedge clk_i) + assert(reset_i || ~packet_v_i || (packet_cast_i.len <= max_num_flits_lp)) + else + $error("Packet received with len: %x > max_num_flits: %x", packet_cast_i.len, max_num_flits_lp); +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_wormhole_router_adapter_in) diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_adapter_out.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_adapter_out.sv new file mode 100644 index 0000000..ba35f45 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_adapter_out.sv @@ -0,0 +1,95 @@ +/** + * bsg_wormhole_router_adapter_out.sv + * + * packet = {payload, length, cord} + * + * Basic module that deserializes an incoming wormhole packet into a wide register. + * This is especially useful for testbenches. (For hardware, + * full deserialization adds latency and area, this is often undesireable, but for + * small packets, it may make sense to use it.) + */ + +`include "bsg_defines.sv" + +`include "bsg_noc_links.svh" +`include "bsg_wormhole_router.svh" + +module bsg_wormhole_router_adapter_out + #(parameter `BSG_INV_PARAM(max_payload_width_p ) + , parameter `BSG_INV_PARAM(len_width_p ) + , parameter `BSG_INV_PARAM(cord_width_p ) + , parameter `BSG_INV_PARAM(flit_width_p ) + + , localparam bsg_ready_and_link_sif_width_lp = + `bsg_ready_and_link_sif_width(flit_width_p) + , localparam bsg_wormhole_packet_width_lp = + `bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p) + ) + (input clk_i + , input reset_i + + , input link_v_i + , input [max_payload_width_p-1:0] link_data_i + , output link_ready_and_o + + , output [bsg_wormhole_packet_width_lp-1:0] packet_o + , output packet_v_o + , input packet_yumi_i + ); + + `declare_bsg_wormhole_router_header_s(cord_width_p, len_width_p, bsg_wormhole_header_s); + bsg_wormhole_header_s header_li; + assign header_li = link_data_i; + + `declare_bsg_wormhole_router_packet_s(cord_width_p,len_width_p,max_payload_width_p,bsg_wormhole_packet_s); + + localparam max_num_flits_lp = `BSG_CDIV($bits(bsg_wormhole_packet_s), flit_width_p); + localparam protocol_len_lp = `BSG_SAFE_CLOG2(max_num_flits_lp); + logic [max_num_flits_lp*flit_width_p-1:0] packet_padded_lo; + bsg_serial_in_parallel_out_dynamic + #(.width_p(flit_width_p) + ,.max_els_p(max_num_flits_lp) + ) + sipo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(link_data_i) + ,.len_i(protocol_len_lp'(header_li.len)) + ,.ready_and_o(link_ready_and_o) + ,.len_ready_o(/* unused */) + ,.v_i(link_v_i) + + ,.v_o(packet_v_o) + ,.data_o(packet_padded_lo) + ,.yumi_i(packet_yumi_i) + ); + assign packet_o = packet_padded_lo[0+:bsg_wormhole_packet_width_lp]; + + + +`ifndef BSG_HIDE_FROM_SYNTHESIS + logic recv_r; + bsg_dff_reset_en + #(.width_p(1)) + recv_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(link_v_i || packet_yumi_i) + + ,.data_i(link_v_i) + ,.data_o(recv_r) + ); + wire new_header_li = ~recv_r & link_v_i; + + // TODO: This assertion is buggy and fires erroneously + //always_ff @(negedge clk_i) + // assert(reset_i || ~new_header_li || (header_li.len <= max_num_flits_lp)) + // else + // $error("Header received with len: %x > max_num_flits: %x", header_li.len, max_num_flits_lp); +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_wormhole_router_adapter_out) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_decoder_dor.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_decoder_dor.sv new file mode 100644 index 0000000..308daa6 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_decoder_dor.sv @@ -0,0 +1,82 @@ +// +// N-dimensional wormhole dimension ordered decoder +// +// given input coordinates for the target of a message, and for the current node +// it will output a one hot vector which is which direction that header should be routed +// +// + +`include "bsg_defines.sv" + +module bsg_wormhole_router_decoder_dor +#(parameter dims_p=2 + // cord_dims_p is normally the same as dims_p. However, the override allows users to pass + // a larger cord array than necessary, useful for parameterizing between 1d/nd networks + ,parameter cord_dims_p=dims_p + ,parameter reverse_order_p=0 // e.g., 1->Y THEN X, 0->X THEN Y routing + // pass in the markers that delineates storage of dimension fields + // so for example {5, 4, 0} means dim0=[4-1:0], dim1=[5-1:4] + , parameter int cord_markers_pos_p[cord_dims_p:0] = '{ 5, 4, 0 } + , parameter output_dirs_lp=2*dims_p+1 + ) + (input [cord_markers_pos_p[dims_p]-1:0] target_cord_i + , input [cord_markers_pos_p[dims_p]-1:0] my_cord_i + , output [output_dirs_lp-1:0] req_o + ); + + genvar i; + + logic [dims_p-1:0] eq, lt, gt; + + for (i = 0; i < dims_p; i=i+1) + begin: rof + localparam upper_marker_lp = cord_markers_pos_p[i+1]; + localparam lower_marker_lp = cord_markers_pos_p[i]; + localparam local_cord_width_p = upper_marker_lp - lower_marker_lp; + + wire [local_cord_width_p-1:0] targ_cord = target_cord_i[upper_marker_lp-1:lower_marker_lp]; + wire [local_cord_width_p-1:0] my_cord = my_cord_i[upper_marker_lp-1:lower_marker_lp]; + + assign eq[i] = (targ_cord == my_cord); + assign lt[i] = (targ_cord < my_cord); + assign gt[i] = ~eq[i] & ~lt[i]; + end // block: rof + + // handle base case + assign req_o[0] = & eq; // processor is at 0 in enum + + if (reverse_order_p) + begin: rev + assign req_o[(dims_p-1)*2+1] = lt[dims_p-1]; + assign req_o[(dims_p-1)*2+1+1] = gt[dims_p-1]; + + if (dims_p > 1) + begin : fi1 + for (i = (dims_p-1)-1; i >= 0; i--) + begin: rof3 + assign req_o[i*2+1] = &eq[dims_p-1:i+1] & lt[i]; + assign req_o[i*2+1+1] = &eq[dims_p-1:i+1] & gt[i]; + end + end + end // if (reverse_order_p) + else + begin: fwd + assign req_o[1] = lt[0]; // down (W,N) + assign req_o[2] = gt[0]; // up (E,S) + + for (i = 1; i < dims_p; i++) + begin: rof2 + assign req_o[i*2+1] = (&eq[i-1:0]) & lt[i]; + assign req_o[i*2+1+1] = (&eq[i-1:0]) & gt[i]; + end + end // else: !if(reverse_order_p) + +`ifndef BSG_HIDE_FROM_SYNTHESIS + initial assert(bsg_noc_pkg::P == 0 + && bsg_noc_pkg::W == 1 + && bsg_noc_pkg::E == 2 + && bsg_noc_pkg::N == 3 + && bsg_noc_pkg::S == 4) else $error("%m: bsg_noc_pkg dirs are inconsistent with this module"); +`endif + +endmodule diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_input_control.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_input_control.sv new file mode 100644 index 0000000..3c68435 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_input_control.sv @@ -0,0 +1,49 @@ +`include "bsg_defines.sv" + +// This module is primarily used by the wormhole router, but can also be used +// as an endpoint decoder with output_dirs_p=1, fifo_decoder_dest_i = '0, and reqs_o ignored, and release_o +// signaling the end of the packet. + +module bsg_wormhole_router_input_control #(parameter `BSG_INV_PARAM(output_dirs_p), parameter `BSG_INV_PARAM(payload_len_bits_p)) + (input clk_i + , input reset_i + , input fifo_v_i + , input [output_dirs_p-1:0] fifo_decoded_dest_i + , input [payload_len_bits_p-1:0] fifo_payload_len_i + + // a word was sent by the output channel + , input fifo_yumi_i + + // a wire is high only if there is a header flit at the head of the fifo + // that is targeted to the output channel + // only a single wire can be high + + , output [output_dirs_p-1:0] reqs_o + + // we transferred all of the words on the previous cycle + , output release_o + + , output detected_header_o + ); + + wire [payload_len_bits_p-1:0] payload_ctr_r; + wire counter_expired = (!payload_ctr_r); + wire fifo_has_hdr = counter_expired & fifo_v_i; + + bsg_counter_set_down #(.width_p(payload_len_bits_p), .set_and_down_exclusive_p(1'b1)) ctr + (.clk_i + ,.reset_i + ,.set_i (fifo_yumi_i & counter_expired) // somebody accepted our header + // note: reset puts the counter in expired state + ,.val_i (fifo_payload_len_i) + ,.down_i (fifo_yumi_i & ~counter_expired) // we decrement if somebody grabbed a word and it was not a header + ,.count_r_o(payload_ctr_r) // decrement after we no longer have a header + ); + + assign reqs_o = fifo_has_hdr ? fifo_decoded_dest_i : '0; + assign release_o = counter_expired; + assign detected_header_o = fifo_has_hdr; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_wormhole_router_input_control) diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_output_control.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_output_control.sv new file mode 100644 index 0000000..ddb7576 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_output_control.sv @@ -0,0 +1,67 @@ +`include "bsg_defines.sv" + +module bsg_wormhole_router_output_control + #(parameter `BSG_INV_PARAM(input_dirs_p) + // Hold on valid sets the arbitration policy such that once an output tag is selected, it + // remains selected until it is acked, then the round-robin scheduler continues cycling + // from the selected tag. This is consistent with BaseJump STL handshake assumptions. + // Notably, this parameter is required to work with bsg_parallel_in_serial_out_passthrough. + // This policy has a slight throughput degradation but effectively arbitrates based on age, + // so minimizes worst case latency. + , parameter hold_on_valid_p = 0 + ) + (input clk_i + , input reset_i + + // this input channel has a header packet at the head of the FIFO for this output + , input [input_dirs_p-1:0] reqs_i + + // the input channel finished a packet on the previous cycle + // note: it is up to this module to verify that the input channel was allocated to this output channel + , input [input_dirs_p-1:0] release_i + + // from input fifos + , input [input_dirs_p-1:0] valid_i + , output [input_dirs_p-1:0] yumi_o + + // channel outputs + , input ready_and_i + , output valid_o + , output [input_dirs_p-1:0] data_sel_o + ); + + wire [input_dirs_p-1:0] scheduled_r, scheduled_with_release, scheduled_n, grants_lo; + + bsg_dff_reset #(.width_p(input_dirs_p)) scheduled_reg (.clk_i, .reset_i, .data_i(scheduled_n), .data_o(scheduled_r)); + + assign scheduled_with_release = scheduled_r & ~release_i; + + wire free_to_schedule = !scheduled_with_release; + + bsg_round_robin_arb + #(.inputs_p(input_dirs_p), .hold_on_valid_p(hold_on_valid_p)) + brr + (.clk_i + ,.reset_i + ,.grants_en_i (free_to_schedule) // ports are all free + ,.reqs_i (reqs_i) // requests from input ports + ,.grants_o (grants_lo) // output grants, takes into account grants_en_i + ,.sel_one_hot_o() // output grants, does not take into account grants_en_i + ,.v_o () // some reqs_i was set + ,.tag_o () + // make sure to only allocate the port if we succeeded in transmitting the header + // otherwise the input will try to allocate again on the next cycle + ,.yumi_i (free_to_schedule & ready_and_i & valid_o) // update round_robin + ); + + assign scheduled_n = grants_lo | scheduled_with_release; + assign data_sel_o = scheduled_n; + assign valid_o = (|(scheduled_n & valid_i)); + assign yumi_o = ready_and_i ? (scheduled_n & valid_i) : '0; +endmodule + +`BSG_ABSTRACT_MODULE(bsg_wormhole_router_output_control) + + + + diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_pkg.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_pkg.sv new file mode 100644 index 0000000..2dd7d59 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_router_pkg.sv @@ -0,0 +1,145 @@ +`include "bsg_defines.sv" + +package bsg_wormhole_router_pkg; + localparam bit [1:0][2:0][2:0] StrictX + = { // EWP (input) + { 3'b011 // E + ,3'b101 // W + ,3'b111 // P (output) + } + , // EWP (output) + { 3'b011 // E + ,3'b101 // W + ,3'b111 // P (input) + } + }; + + localparam bit [1:0][2:0][2:0] X_AllowLoopBack // for testing only; you should never build a machine like this + = { // EWP (input) // it will deadlock + { 3'b100 // E + ,3'b010 // W + ,3'b000 // P (output) + } + , // EWP (output) + { 3'b111 // E + ,3'b111 // W + ,3'b111 // P (input) + } + }; + + localparam bit [1:0][4:0][4:0] StrictXY + = { + {// SNEWP (input) + 5'b01111 // S + ,5'b10111 // N + ,5'b00011 // E + ,5'b00101 // W + ,5'b11111 // P (output) + } + , + {// SNEWP (output) + 5'b01001 // S + ,5'b10001 // N + ,5'b11011 // E + ,5'b11101 // W + ,5'b11111 // P (input) + } + }; + + localparam bit [1:0][4:0][4:0] StrictYX + = { + {// SNEWP (input) + 5'b01001 // S + ,5'b10001 // N + ,5'b11011 // E + ,5'b11101 // W + ,5'b11111 // P (output) + } + , + {// SNEWP (output) + 5'b01111 // S + ,5'b10111 // N + ,5'b00011 // E + ,5'b00101 // W + ,5'b11111 // P (input) + } + }; + + // These are "OR-in" matrices, that are intended to be layered upon StrictYX or Strict XY. + localparam bit [1:0][4:0][4:0] XY_Allow_S + = { + {// SNEWP (input) + 5'b00000 // S + ,5'b00000 // N + ,5'b10000 // E + ,5'b10000 // W + ,5'b00000 // P (output) + } + , + {// SNEWP (output) + 5'b00110 // S + ,5'b00000 // N + ,5'b00000 // E + ,5'b00000 // W + ,5'b00000 // P (input) + } + }; + + localparam bit [1:0][4:0][4:0] XY_Allow_N + = { + {// SNEWP (input) + 5'b00000 // S + ,5'b00000 // N + ,5'b01000 // E + ,5'b01000 // W + ,5'b00000 // P (output) + } + , + {// SNEWP (output) + 5'b00000 // S + ,5'b00110 // N + ,5'b00000 // E + ,5'b00000 // W + ,5'b00000 // P (input) + } + }; + + localparam bit + [1:0][4:0][4:0] YX_Allow_W = { + {// SNEWP (input) + 5'b00010 // S + ,5'b00010 // N + ,5'b00000 // E + ,5'b00000 // W + ,5'b00000 // P (output) + } + , + {// SNEWP (output) + 5'b00000 // S + ,5'b00000 // N + ,5'b00000 // E + ,5'b11000 // W + ,5'b00000 // P (input) + } + }; + + localparam bit + [1:0][4:0][4:0] YX_Allow_E = { + {// SNEWP (input) + 5'b00100 // S + ,5'b00100 // N + ,5'b00000 // E + ,5'b00000 // W + ,5'b00000 // P (output) + } + , + {// SNEWP (output) + 5'b00000 // S + ,5'b00000 // N + ,5'b11000 // E + ,5'b00000 // W + ,5'b00000 // P (input) + } + }; + +endpackage diff --git a/designs/black-parrot/src/basejump_stl/bsg_wormhole_to_cache_dma_fanout.sv b/designs/black-parrot/src/basejump_stl/bsg_wormhole_to_cache_dma_fanout.sv new file mode 100644 index 0000000..5e677c0 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_wormhole_to_cache_dma_fanout.sv @@ -0,0 +1,420 @@ +/** + * bsg_wormhole_to_cache_dma.v + * + * This module converts a bsg_cache_dma wormhole link to an array of bsg_cache_dma interfaces. + * It can then be connected to other endpoints such as bsg_cache_to_axi or bsg_cache_to_test_dram. + * + * Caution: large fanouts may struggle with timing + */ + +`include "bsg_defines.sv" +`include "bsg_noc_links.svh" +`include "bsg_cache.svh" + +module bsg_wormhole_to_cache_dma_fanout + import bsg_noc_pkg::*; + import bsg_cache_pkg::*; + #(parameter `BSG_INV_PARAM(num_dma_p) + , parameter `BSG_INV_PARAM(dma_addr_width_p) // cache addr width (in bytes) + , parameter `BSG_INV_PARAM(dma_burst_len_p) // num of data beats in dma transfer + , parameter `BSG_INV_PARAM(dma_mask_width_p) // mask width in the bsg_cache_dma_pkt_s. This should equal to the block_size_in_words_p set for bsg_cache. + + // flit width must match the cache dma width. + , parameter `BSG_INV_PARAM(wh_flit_width_p) + , parameter `BSG_INV_PARAM(wh_cid_width_p) + , parameter `BSG_INV_PARAM(wh_len_width_p) + , parameter `BSG_INV_PARAM(wh_cord_width_p) + + // FIFO parameters + , parameter lg_num_dma_lp=`BSG_SAFE_CLOG2(num_dma_p) + , parameter count_width_lp=`BSG_SAFE_CLOG2(dma_burst_len_p) + + , parameter wh_ready_and_link_sif_width_lp=`bsg_ready_and_link_sif_width(wh_flit_width_p) + , parameter wh_then_ready_link_sif_width_lp=`bsg_then_ready_link_sif_width(wh_flit_width_p) + , parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(dma_addr_width_p, dma_mask_width_p) + , parameter dma_data_width_p=wh_flit_width_p + ) + ( + input clk_i + , input reset_i + + + // Incoming wormhole link is valid->ready, while outgoing is standard ready-valid-and + // While one can functionally connect a valid->ready consumer to a ready-valid-and producer, + // it may be desirable for timing or congestion to buffer input flits + , input [wh_ready_and_link_sif_width_lp-1:0] wh_link_sif_i + , input [lg_num_dma_lp-1:0] wh_dma_id_i + , output logic [wh_then_ready_link_sif_width_lp-1:0] wh_link_sif_o + + // cache DMA + , output logic [num_dma_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_o + , output logic [num_dma_p-1:0] dma_pkt_v_o + , input [num_dma_p-1:0] dma_pkt_yumi_i + + , input [num_dma_p-1:0][dma_data_width_p-1:0] dma_data_i + , input [num_dma_p-1:0] dma_data_v_i + , output logic [num_dma_p-1:0] dma_data_ready_and_o + + , output logic [num_dma_p-1:0][dma_data_width_p-1:0] dma_data_o + , output logic [num_dma_p-1:0] dma_data_v_o + , input [num_dma_p-1:0] dma_data_yumi_i + ); + + + // structs + `declare_bsg_ready_and_link_sif_s(wh_flit_width_p,wh_ready_and_link_sif_s); + `declare_bsg_then_ready_link_sif_s(wh_flit_width_p,wh_then_ready_link_sif_s); + `declare_bsg_cache_dma_pkt_s(dma_addr_width_p, dma_mask_width_p); + `declare_bsg_cache_wh_header_flit_s(wh_flit_width_p,wh_cord_width_p,wh_len_width_p,wh_cid_width_p); + + + // cast wormhole links + wh_ready_and_link_sif_s wh_link_sif_in; + wh_then_ready_link_sif_s wh_link_sif_out; + assign wh_link_sif_in = wh_link_sif_i; + assign wh_link_sif_o = wh_link_sif_out; + + // DMA pkt going out + bsg_cache_dma_pkt_s dma_pkt_out; + assign dma_pkt_o = {num_dma_p{dma_pkt_out}}; + + // header flits coming in and going out + bsg_cache_wh_header_flit_s header_flit_in, header_flit_out; + assign header_flit_in = wh_link_sif_in.data; + + // cid, src_cord table + logic [num_dma_p-1:0][wh_cid_width_p-1:0] src_cid_r; + logic [num_dma_p-1:0][wh_cord_width_p-1:0] src_cord_r; + logic [wh_cid_width_p-1:0] src_cid_n; + logic [wh_cord_width_p-1:0] src_cord_n; + logic [lg_num_dma_lp-1:0] table_w_addr; + logic table_we; + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + src_cid_r <= '0; + src_cord_r <= '0; + end + else begin + if (table_we) begin + src_cid_r[table_w_addr] <= src_cid_n; + src_cord_r[table_w_addr] <= src_cord_n; + end + end + end + + + + // send FSM + // receives wh packets and send cache dma pkts, and evict data. + typedef enum logic [2:0] { + SEND_RESET, + SEND_READY, + SEND_DMA_PKT, + SEND_DMA_PKT_WITH_MASK, + SEND_EVICT_DATA + } send_state_e; + + send_state_e send_state_r, send_state_n; + bsg_cache_wh_opcode_e opcode_r, opcode_n; + logic [lg_num_dma_lp-1:0] send_cache_id_r, send_cache_id_n; + logic [dma_addr_width_p-1:0] addr_r, addr_n; + + logic send_clear_li; + logic send_up_li; + logic [count_width_lp-1:0] send_count_lo; + bsg_counter_clear_up #( + .max_val_p(dma_burst_len_p-1) + ,.init_val_p(0) + ) send_count ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(send_clear_li) + ,.up_i(send_up_li) + ,.count_o(send_count_lo) + ); + + always_comb begin + send_state_n = send_state_r; + opcode_n = opcode_r; + send_cache_id_n = send_cache_id_r; + addr_n = addr_r; + table_we = 1'b0; + table_w_addr = '0; + src_cord_n = '0; + src_cid_n = '0; + + wh_link_sif_out.then_ready_rev = 1'b0; + + send_clear_li = 1'b0; + send_up_li = 1'b0; + dma_pkt_v_o = '0; + dma_pkt_out = '0; + + dma_data_v_o = '0; + dma_data_o = '0; + + case (send_state_r) + // coming out of reset + SEND_RESET: begin + send_state_n = SEND_READY; + end + + // wait for a header flit. + // store the opcode, src_cord. + // save the cid in a table. + SEND_READY: begin + if (wh_link_sif_in.v) begin + wh_link_sif_out.then_ready_rev = 1'b1; + opcode_n = header_flit_in.opcode; + src_cord_n = header_flit_in.src_cord; + src_cid_n = header_flit_in.src_cid; + table_w_addr = wh_dma_id_i; + table_we = 1'b1; + send_cache_id_n = wh_dma_id_i; + send_state_n = SEND_DMA_PKT; + end + end + + // take the addr flit and send out the dma pkt (for read, non-mask write). + // For read and non-mask write, return to SEND_READY. + // For mask write, flop the addr flit, and move to SEND_DMA_PKT_WITH_MASK. + SEND_DMA_PKT: begin + dma_pkt_v_o[send_cache_id_r] = wh_link_sif_in.v & (opcode_r != e_cache_wh_write_masked); + dma_pkt_out.write_not_read = (opcode_r != e_cache_wh_read); + dma_pkt_out.addr = dma_addr_width_p'(wh_link_sif_in.data); + dma_pkt_out.mask = '1; // Don't care for read. This is for non-masked write. + + wh_link_sif_out.then_ready_rev = dma_pkt_yumi_i[send_cache_id_r] | (opcode_r == e_cache_wh_write_masked); + addr_n = (wh_link_sif_in.v & (opcode_r == e_cache_wh_write_masked)) + ? dma_addr_width_p'(wh_link_sif_in.data) + : addr_r; + + case (opcode_r) + e_cache_wh_read: begin + send_state_n = dma_pkt_yumi_i[send_cache_id_r] + ? SEND_READY + : SEND_DMA_PKT; + end + e_cache_wh_write_non_masked: begin + send_state_n = dma_pkt_yumi_i[send_cache_id_r] + ? SEND_EVICT_DATA + : SEND_DMA_PKT; + end + e_cache_wh_write_masked: begin + send_state_n = wh_link_sif_in.v + ? SEND_DMA_PKT_WITH_MASK + : SEND_DMA_PKT; + end + // never happens: + default: begin + send_state_n = SEND_READY; + end + endcase + + end + + // Take mask flit, and send the dma pkt (for write). + SEND_DMA_PKT_WITH_MASK: begin + dma_pkt_v_o[send_cache_id_r] = wh_link_sif_in.v; + dma_pkt_out.write_not_read = 1'b1; + dma_pkt_out.addr = addr_r; + dma_pkt_out.mask = dma_mask_width_p'(wh_link_sif_in.data); + + wh_link_sif_out.then_ready_rev = dma_pkt_yumi_i[send_cache_id_r]; + + send_state_n = dma_pkt_yumi_i[send_cache_id_r] + ? SEND_EVICT_DATA + : SEND_DMA_PKT_WITH_MASK; + end + + + // once all evict data has been passed along return to SEND_READY + SEND_EVICT_DATA: begin + dma_data_v_o[send_cache_id_r] = wh_link_sif_in.v; + dma_data_o[send_cache_id_r] = wh_link_sif_in.data; + if (dma_data_yumi_i[send_cache_id_r]) begin + wh_link_sif_out.then_ready_rev = 1'b1; + send_up_li = send_count_lo != dma_burst_len_p-1; + send_clear_li = send_count_lo == dma_burst_len_p-1; + send_state_n = send_clear_li + ? SEND_READY + : SEND_EVICT_DATA; + end + end + + default: begin + // this should never happen. + send_state_n = SEND_READY; + end + + endcase + + end + + + + always_ff @ (posedge clk_i) begin + if (reset_i) begin + send_state_r <= SEND_RESET; + opcode_r <= e_cache_wh_read; + send_cache_id_r <= '0; + addr_r <= '0; + end + else begin + send_state_r <= send_state_n; + opcode_r <= opcode_n; + send_cache_id_r <= send_cache_id_n; + addr_r <= addr_n; + end + end + + + + // receiver FSM + // receives dma_data_i and send them to the vcaches using wh link. + typedef enum logic [1:0] { + RECV_RESET, + RECV_READY, + RECV_HEADER, + RECV_FILL_DATA + } recv_state_e; + + recv_state_e recv_state_r, recv_state_n; + logic [lg_num_dma_lp-1:0] recv_cache_id_r, recv_cache_id_n; + + + logic rr_v_lo; + logic rr_yumi_li; + logic [lg_num_dma_lp-1:0] rr_addr_lo; + logic [num_dma_p-1:0] rr_grants_lo; + bsg_arb_round_robin #( + .width_p(num_dma_p) + ) rr0 ( + .clk_i(clk_i) + ,.reset_i(reset_i) + + ,.reqs_i(dma_data_v_i) + ,.grants_o(rr_grants_lo) + ,.yumi_i(rr_yumi_li) + ); + assign rr_v_lo = |dma_data_v_i; + bsg_encode_one_hot #( + .width_p(num_dma_p) + ) eoh ( + .i(rr_grants_lo) + ,.addr_o(rr_addr_lo) + ,.v_o() + ); + + + logic recv_clear_li; + logic recv_up_li; + logic [count_width_lp-1:0] recv_count_lo; + bsg_counter_clear_up #( + .max_val_p(dma_burst_len_p-1) + ,.init_val_p(0) + ) recv_count ( + .clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(recv_clear_li) + ,.up_i(recv_up_li) + ,.count_o(recv_count_lo) + ); + + + + + always_comb begin + + wh_link_sif_out.v = 1'b0; + wh_link_sif_out.data = '0; + + rr_yumi_li = 1'b0; + + recv_state_n = recv_state_r; + recv_cache_id_n = recv_cache_id_r; + + recv_clear_li = 1'b0; + recv_up_li = 1'b0; + + header_flit_out.unused = '0; + header_flit_out.opcode = e_cache_wh_read; // doesn't matter + header_flit_out.src_cord = '0; // doesn't matter + header_flit_out.src_cid = '0; // doesn't matter + header_flit_out.len = dma_burst_len_p; + header_flit_out.cord = src_cord_r[recv_cache_id_r]; + header_flit_out.cid = src_cid_r[recv_cache_id_r]; + + dma_data_ready_and_o = '0; + + case (recv_state_r) + + // coming out of reset + RECV_RESET: begin + recv_state_n = RECV_READY; + end + + // wait for one of dma_data_v_i to be 1. + // save the cache id. + RECV_READY: begin + if (rr_v_lo) begin + rr_yumi_li = 1'b1; + recv_cache_id_n = rr_addr_lo; + recv_state_n = RECV_HEADER; + end + end + + // send out header to dest vcache + RECV_HEADER: begin + wh_link_sif_out.v = 1'b1; + wh_link_sif_out.data = header_flit_out; + if (wh_link_sif_in.ready_and_rev) begin + recv_state_n = RECV_FILL_DATA; + end + end + + // send the data flits to the vcache. + // once it's done, go back to RECV_READY. + RECV_FILL_DATA: begin + wh_link_sif_out.v = dma_data_v_i[recv_cache_id_r]; + wh_link_sif_out.data = dma_data_i[recv_cache_id_r]; + dma_data_ready_and_o[recv_cache_id_r] = wh_link_sif_in.ready_and_rev; + if (dma_data_ready_and_o[recv_cache_id_r] & dma_data_v_i[recv_cache_id_r]) begin + recv_clear_li = (recv_count_lo == dma_burst_len_p-1); + recv_up_li = (recv_count_lo != dma_burst_len_p-1); + recv_state_n = recv_clear_li + ? RECV_READY + : RECV_FILL_DATA; + end + end + + endcase + end + + + // synopsys sync_set_reset "reset_i" + always_ff @ (posedge clk_i) begin + if (reset_i) begin + recv_state_r <= RECV_RESET; + recv_cache_id_r <= '0; + end + else begin + recv_state_r <= recv_state_n; + recv_cache_id_r <= recv_cache_id_n; + end + end + +`ifndef BSG_HIDE_FROM_SYNTHESIS + if (wh_flit_width_p != dma_data_width_p) + $error("WH flit width must be equal to DMA data width"); + if (wh_flit_width_p < dma_addr_width_p) + $error("WH flit width must be larger than address width"); + if (wh_len_width_p < `BSG_WIDTH(dma_burst_len_p+1)) + $error("WH len width %d must be large enough to hold the dma transfer size %d", wh_len_width_p, `BSG_WIDTH(dma_burst_len_p+1)); +`endif + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_wormhole_to_cache_dma_fanout) + diff --git a/designs/black-parrot/src/basejump_stl/bsg_xnor.sv b/designs/black-parrot/src/basejump_stl/bsg_xnor.sv new file mode 100644 index 0000000..e80bc40 --- /dev/null +++ b/designs/black-parrot/src/basejump_stl/bsg_xnor.sv @@ -0,0 +1,14 @@ +`include "bsg_defines.sv" + +module bsg_xnor #(parameter `BSG_INV_PARAM(width_p) + , harden_p=1) + (input [width_p-1:0] a_i + , input [width_p-1:0] b_i + , output [width_p-1:0] o + ); + + assign o = ~(a_i ^ b_i); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_xnor) diff --git a/designs/black-parrot/src/bp/bp_be_calculator_top.sv b/designs/black-parrot/src/bp/bp_be_calculator_top.sv new file mode 100644 index 0000000..d2d0b1d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_calculator_top.sv @@ -0,0 +1,606 @@ +/** + * + * Name: + * bp_be_calculator_top.v + * + * Description: + * + * Notes: + * Should subdivide this module into a few helper modules to reduce complexity. Perhaps + * issuer, exe_pipe, completion_pipe, status_gen? + * Exception aggregation could be simplified with constants and more thought. Should fix + * once code is more stable, fixing in cleanup could cause regressions + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_calculator_top + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, dcache_tag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_gp, dcache_block_width_p, dcache_fill_width_p, dcache_req_id_width_p) + + // Generated parameters + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // Calculator - Checker interface + , input [dispatch_pkt_width_lp-1:0] dispatch_pkt_i + + , output logic idiv_busy_o + , output logic fdiv_busy_o + , output logic mem_busy_o + , output logic mem_ordered_o + , output logic [decode_info_width_lp-1:0] decode_info_o + , output logic [trans_info_width_lp-1:0] trans_info_o + , input cmd_full_n_i + + , output logic [commit_pkt_width_lp-1:0] commit_pkt_o + , output logic [branch_pkt_width_lp-1:0] br_pkt_o + , output logic [wb_pkt_width_lp-1:0] iwb_pkt_o + , output logic [wb_pkt_width_lp-1:0] fwb_pkt_o + + , output logic [wb_pkt_width_lp-1:0] late_wb_pkt_o + , output logic late_wb_v_o + , output logic late_wb_force_o + , input late_wb_yumi_i + + , input debug_irq_i + , input timer_irq_i + , input software_irq_i + , input m_external_irq_i + , input s_external_irq_i + , output logic irq_waiting_o + , output logic irq_pending_o + + , output logic [dcache_req_width_lp-1:0] cache_req_o + , output logic cache_req_v_o + , input cache_req_yumi_i + , input cache_req_lock_i + , output logic [dcache_req_metadata_width_lp-1:0] cache_req_metadata_o + , output logic cache_req_metadata_v_o + , input [dcache_req_id_width_p-1:0] cache_req_id_i + , input cache_req_critical_i + , input cache_req_last_i + , input cache_req_credits_full_i + , input cache_req_credits_empty_i + + , input data_mem_pkt_v_i + , input [dcache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , output logic data_mem_pkt_yumi_o + , output logic [dcache_block_width_p-1:0] data_mem_o + + , input tag_mem_pkt_v_i + , input [dcache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , output logic tag_mem_pkt_yumi_o + , output logic [dcache_tag_info_width_lp-1:0] tag_mem_o + + , input stat_mem_pkt_v_i + , input [dcache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , output logic stat_mem_pkt_yumi_o + , output logic [dcache_stat_info_width_lp-1:0] stat_mem_o + ); + + // Declare parameterizable structs + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + `bp_cast_i(bp_be_dispatch_pkt_s, dispatch_pkt); + `bp_cast_o(bp_be_commit_pkt_s, commit_pkt); + `bp_cast_o(bp_be_branch_pkt_s, br_pkt); + `bp_cast_o(bp_be_wb_pkt_s, iwb_pkt); + `bp_cast_o(bp_be_wb_pkt_s, fwb_pkt); + `bp_cast_o(bp_be_wb_pkt_s, late_wb_pkt); + + // Pipeline stage registers + localparam pipe_stage_els_lp = 5; + bp_be_exc_stage_s [pipe_stage_els_lp :0] exc_stage_n; + bp_be_exc_stage_s [pipe_stage_els_lp-1:0] exc_stage_r; + + bp_be_wb_pkt_s [pipe_stage_els_lp :0] comp_stage_n; + bp_be_wb_pkt_s [pipe_stage_els_lp-1:0] comp_stage_r; + + rv64_frm_e frm_dyn_lo; + + bp_be_wb_pkt_s pipe_long_iwb_pkt, pipe_long_fwb_pkt; + + logic pipe_int_early_instr_misaligned_lo; + logic pipe_int_catchup_instr_misaligned_lo, pipe_int_catchup_mispredict_lo; + + logic pipe_mem_dtlb_load_miss_lo, pipe_mem_dtlb_store_miss_lo; + logic pipe_mem_dcache_load_miss_lo, pipe_mem_dcache_miss_lo, pipe_mem_dcache_replay_lo; + logic pipe_mem_load_misaligned_lo, pipe_mem_load_access_fault_lo, pipe_mem_load_page_fault_lo; + logic pipe_mem_store_misaligned_lo, pipe_mem_store_access_fault_lo, pipe_mem_store_page_fault_lo; + + logic pipe_sys_illegal_instr_lo; + + logic pipe_int_early_data_v_lo, pipe_int_catchup_data_v_lo, pipe_aux_data_v_lo, pipe_mem_early_data_v_lo, pipe_mem_final_data_v_lo, pipe_sys_data_v_lo, pipe_mul_data_v_lo, pipe_fma_data_v_lo; + logic pipe_long_idata_v_lo, pipe_long_idata_yumi_lo, pipe_long_fdata_v_lo, pipe_long_fdata_yumi_lo; + logic [dpath_width_gp-1:0] pipe_int_early_data_lo, pipe_int_catchup_data_lo, pipe_aux_data_lo, pipe_mem_early_data_lo, pipe_mem_final_data_lo, pipe_sys_data_lo, pipe_mul_data_lo, pipe_fma_data_lo; + rv64_fflags_s pipe_aux_fflags_lo, pipe_fma_fflags_lo; + + logic [vaddr_width_p-1:0] pipe_int_early_npc_lo; + logic pipe_int_early_branch_lo, pipe_int_early_btaken_lo; + + logic [vaddr_width_p-1:0] pipe_int_catchup_npc_lo; + logic pipe_int_catchup_branch_lo, pipe_int_catchup_btaken_lo; + + bp_be_wb_pkt_s pipe_mem_late_wb_pkt; + logic pipe_mem_late_wb_v, pipe_mem_late_wb_yumi; + + // Generating match vector for bypass + logic [2:0][pipe_stage_els_lp-1:0] match_rs; + logic [pipe_stage_els_lp-1:0][dpath_width_gp-1:0] forward_data; + for (genvar i = 0; i < pipe_stage_els_lp; i++) + begin : forward_match + assign match_rs[0][i] = ((i < 4) & dispatch_pkt_cast_i.decode.irs1_r_v & comp_stage_r[i].ird_w_v & (dispatch_pkt_cast_i.instr.t.fmatype.rs1_addr == comp_stage_r[i].rd_addr)) + || (dispatch_pkt_cast_i.decode.frs1_r_v & comp_stage_r[i].frd_w_v & (dispatch_pkt_cast_i.instr.t.fmatype.rs1_addr == comp_stage_r[i].rd_addr)); + assign match_rs[1][i] = ((i < 4) & dispatch_pkt_cast_i.decode.irs2_r_v & comp_stage_r[i].ird_w_v & (dispatch_pkt_cast_i.instr.t.fmatype.rs2_addr == comp_stage_r[i].rd_addr)) + || (dispatch_pkt_cast_i.decode.frs2_r_v & comp_stage_r[i].frd_w_v & (dispatch_pkt_cast_i.instr.t.fmatype.rs2_addr == comp_stage_r[i].rd_addr)); + assign match_rs[2][i] = (dispatch_pkt_cast_i.decode.frs3_r_v & comp_stage_r[i].frd_w_v & (dispatch_pkt_cast_i.instr.t.fmatype.rs3_addr == comp_stage_r[i].rd_addr)); + + assign forward_data[i] = comp_stage_n[i+1].rd_data; + end + + logic [2:0][dpath_width_gp-1:0] bypass_rs; + wire [2:0][dpath_width_gp-1:0] dispatch_data = {dispatch_pkt_cast_i.imm, dispatch_pkt_cast_i.rs2, dispatch_pkt_cast_i.rs1}; + for (genvar i = 0; i < 3; i++) + begin : pencode + logic [pipe_stage_els_lp:0] match_rs_onehot; + bsg_priority_encode_one_hot_out + #(.width_p(pipe_stage_els_lp+1), .lo_to_hi_p(1)) + pencode_oh + (.i({1'b1, match_rs[i]}) + ,.o(match_rs_onehot) + ,.v_o() + ); + + bsg_mux_one_hot + #(.width_p(dpath_width_gp), .els_p(pipe_stage_els_lp+1)) + fwd_mux_oh + (.data_i({dispatch_data[i], forward_data}) + ,.sel_one_hot_i(match_rs_onehot) + ,.data_o(bypass_rs[i]) + ); + end + + bp_be_reservation_s reservation_r; + bp_be_reservation + #(.bp_params_p(bp_params_p)) + reservation_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.dispatch_pkt_i(dispatch_pkt_cast_i) + ,.bypass_rs_i(bypass_rs) + ,.reservation_o(reservation_r) + ); + + // Computation pipelines + // System pipe: 1 cycle latency + bp_be_pipe_sys + #(.bp_params_p(bp_params_p)) + pipe_sys + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.cfg_bus_i(cfg_bus_i) + + ,.reservation_i(reservation_r) + ,.flush_i(commit_pkt_cast_o.npc_w_v) + + ,.retire_v_i(exc_stage_r[2].v) + ,.retire_queue_v_i(exc_stage_r[2].queue_v) + ,.retire_data_i(comp_stage_r[2].rd_data) + ,.retire_exception_i(exc_stage_r[2].exc) + ,.retire_special_i(exc_stage_r[2].spec) + ,.commit_pkt_o(commit_pkt_cast_o) + ,.iwb_pkt_i(iwb_pkt_o) + ,.fwb_pkt_i(fwb_pkt_o) + + ,.debug_irq_i(debug_irq_i) + ,.timer_irq_i(timer_irq_i) + ,.software_irq_i(software_irq_i) + ,.m_external_irq_i(m_external_irq_i) + ,.s_external_irq_i(s_external_irq_i) + ,.irq_pending_o(irq_pending_o) + ,.irq_waiting_o(irq_waiting_o) + + ,.illegal_instr_o(pipe_sys_illegal_instr_lo) + ,.data_o(pipe_sys_data_lo) + ,.v_o(pipe_sys_data_v_lo) + + ,.decode_info_o(decode_info_o) + ,.trans_info_o(trans_info_o) + ,.frm_dyn_o(frm_dyn_lo) + ); + + // Integer pipe: 1 cycle latency + bp_be_pipe_int + #(.bp_params_p(bp_params_p)) + pipe_int_early + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.en_i(~exc_stage_r[0].ispec_v) + ,.reservation_i(reservation_r) + ,.flush_i(commit_pkt_cast_o.npc_w_v) + + ,.data_o(pipe_int_early_data_lo) + ,.v_o(pipe_int_early_data_v_lo) + ,.npc_o(pipe_int_early_npc_lo) + ,.branch_o(pipe_int_early_branch_lo) + ,.btaken_o(pipe_int_early_btaken_lo) + ,.instr_misaligned_v_o(pipe_int_early_instr_misaligned_lo) + ); + + assign br_pkt_cast_o.v = exc_stage_r[0].v & exc_stage_r[0].queue_v; + assign br_pkt_cast_o.branch = br_pkt_cast_o.v & pipe_int_early_branch_lo; + assign br_pkt_cast_o.btaken = br_pkt_cast_o.v & pipe_int_early_btaken_lo; + assign br_pkt_cast_o.bspec = br_pkt_cast_o.v & exc_stage_r[0].ispec_v; + assign br_pkt_cast_o.npc = pipe_int_early_npc_lo; + + logic [dword_width_gp-1:0] rs2_val_r; + if (integer_support_p[e_catchup]) + begin : catchup + logic [int_rec_width_gp-1:0] catchup_bypass_src1; + bp_be_int_unbox + #(.bp_params_p(bp_params_p)) + irs1_unbox + (.reg_i(comp_stage_n[2].rd_data) + ,.tag_i(reservation_r.decode.irs1_tag) + ,.unsigned_i(reservation_r.decode.irs1_unsigned) + ,.val_o(catchup_bypass_src1) + ); + + logic [int_rec_width_gp-1:0] catchup_bypass_src2; + bp_be_int_unbox + #(.bp_params_p(bp_params_p)) + irs2_unbox + (.reg_i(comp_stage_n[2].rd_data) + ,.tag_i(reservation_r.decode.irs2_tag) + ,.unsigned_i(reservation_r.decode.irs2_unsigned) + ,.val_o(catchup_bypass_src2) + ); + + bp_be_reservation_s catchup_reservation_n, catchup_reservation_r; + always_comb + begin + catchup_reservation_n = reservation_r; + if (reservation_r.decode.irs1_r_v && comp_stage_r[1].ird_w_v && (comp_stage_r[1].rd_addr == reservation_r.instr.t.rtype.rs1_addr)) + catchup_reservation_n.isrc1 = catchup_bypass_src1; + if (reservation_r.decode.irs2_r_v && comp_stage_r[1].ird_w_v && (comp_stage_r[1].rd_addr == reservation_r.instr.t.rtype.rs2_addr)) + catchup_reservation_n.isrc2 = catchup_bypass_src2; + end + + bsg_dff + #(.width_p($bits(bp_be_reservation_s))) + catchup_reservation_reg + (.clk_i(clk_i) + ,.data_i(catchup_reservation_n) + ,.data_o(catchup_reservation_r) + ); + + // Catchup integer pipe: 1 cycle latency, starts at EX2 + bp_be_pipe_int + #(.bp_params_p(bp_params_p)) + pipe_int_catchup + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.en_i(exc_stage_r[1].ispec_v) + ,.reservation_i(catchup_reservation_r) + ,.flush_i(commit_pkt_cast_o.npc_w_v) + + ,.data_o(pipe_int_catchup_data_lo) + ,.v_o(pipe_int_catchup_data_v_lo) + ,.npc_o(pipe_int_catchup_npc_lo) + ,.branch_o(pipe_int_catchup_branch_lo) + ,.btaken_o(pipe_int_catchup_btaken_lo) + ,.instr_misaligned_v_o(pipe_int_catchup_instr_misaligned_lo) + ); + assign pipe_int_catchup_mispredict_lo = exc_stage_r[1].ispec_v & (pipe_int_catchup_npc_lo != reservation_r.pc); + + assign rs2_val_r = + catchup_reservation_r.decode.irs2_r_v ? catchup_reservation_r.isrc2 : catchup_reservation_r.fsrc2; + end + else + begin : no_catchup + assign pipe_int_catchup_data_lo = '0; + assign pipe_int_catchup_data_v_lo = '0; + assign pipe_int_catchup_mispredict_lo = '0; + assign pipe_int_catchup_instr_misaligned_lo = '0; + + wire [dword_width_gp-1:0] rs2_val_n = + reservation_r.decode.irs2_r_v ? reservation_r.isrc2 : reservation_r.fsrc2; + bsg_dff + #(.width_p(dword_width_gp)) + rs2_reg + (.clk_i(clk_i) + ,.data_i(rs2_val_n) + ,.data_o(rs2_val_r) + ); + end + + // Aux pipe: 2 cycle latency + bp_be_pipe_aux + #(.bp_params_p(bp_params_p)) + pipe_aux + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.reservation_i(reservation_r) + ,.flush_i(commit_pkt_cast_o.npc_w_v) + ,.frm_dyn_i(frm_dyn_lo) + + ,.data_o(pipe_aux_data_lo) + ,.fflags_o(pipe_aux_fflags_lo) + ,.v_o(pipe_aux_data_v_lo) + ); + + // Memory pipe: 2/3 cycle latency + bp_be_pipe_mem + #(.bp_params_p(bp_params_p)) + pipe_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_i) + + ,.flush_i(commit_pkt_cast_o.npc_w_v) + ,.sfence_i(commit_pkt_cast_o.sfence) + + ,.busy_o(mem_busy_o) + ,.ordered_o(mem_ordered_o) + + ,.reservation_i(reservation_r) + ,.rs2_val_i(rs2_val_r) + + ,.commit_pkt_i(commit_pkt_cast_o) + + ,.cache_req_o(cache_req_o) + ,.cache_req_v_o(cache_req_v_o) + ,.cache_req_yumi_i(cache_req_yumi_i) + ,.cache_req_lock_i(cache_req_lock_i) + ,.cache_req_metadata_o(cache_req_metadata_o) + ,.cache_req_metadata_v_o(cache_req_metadata_v_o) + ,.cache_req_id_i(cache_req_id_i) + ,.cache_req_critical_i(cache_req_critical_i) + ,.cache_req_last_i(cache_req_last_i) + ,.cache_req_credits_full_i(cache_req_credits_full_i) + ,.cache_req_credits_empty_i(cache_req_credits_empty_i) + + ,.data_mem_pkt_i(data_mem_pkt_i) + ,.data_mem_pkt_v_i(data_mem_pkt_v_i) + ,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o) + ,.data_mem_o(data_mem_o) + + ,.tag_mem_pkt_i(tag_mem_pkt_i) + ,.tag_mem_pkt_v_i(tag_mem_pkt_v_i) + ,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o) + ,.tag_mem_o(tag_mem_o) + + ,.stat_mem_pkt_i(stat_mem_pkt_i) + ,.stat_mem_pkt_v_i(stat_mem_pkt_v_i) + ,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o) + ,.stat_mem_o(stat_mem_o) + + ,.tlb_store_miss_v_o(pipe_mem_dtlb_store_miss_lo) + ,.tlb_load_miss_v_o(pipe_mem_dtlb_load_miss_lo) + ,.cache_replay_v_o(pipe_mem_dcache_replay_lo) + ,.cache_miss_v_o(pipe_mem_dcache_miss_lo) + ,.load_misaligned_v_o(pipe_mem_load_misaligned_lo) + ,.load_access_fault_v_o(pipe_mem_load_access_fault_lo) + ,.load_page_fault_v_o(pipe_mem_load_page_fault_lo) + ,.store_misaligned_v_o(pipe_mem_store_misaligned_lo) + ,.store_access_fault_v_o(pipe_mem_store_access_fault_lo) + ,.store_page_fault_v_o(pipe_mem_store_page_fault_lo) + + ,.early_data_o(pipe_mem_early_data_lo) + ,.early_v_o(pipe_mem_early_data_v_lo) + + ,.final_data_o(pipe_mem_final_data_lo) + ,.final_v_o(pipe_mem_final_data_v_lo) + + ,.late_wb_pkt_o(pipe_mem_late_wb_pkt) + ,.late_wb_v_o(pipe_mem_late_wb_v) + + ,.trans_info_i(trans_info_o) + ); + + // Floating point pipe: 3/4 cycle latency + bp_be_pipe_fma + #(.bp_params_p(bp_params_p)) + pipe_fma + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.reservation_i(reservation_r) + ,.flush_i(commit_pkt_cast_o.npc_w_v) + ,.frm_dyn_i(frm_dyn_lo) + + ,.imul_data_o(pipe_mul_data_lo) + ,.imul_v_o(pipe_mul_data_v_lo) + ,.fma_data_o(pipe_fma_data_lo) + ,.fma_fflags_o(pipe_fma_fflags_lo) + ,.fma_v_o(pipe_fma_data_v_lo) + ); + + // Variable length pipeline, used for long (potentially scoreboarded operations) + bp_be_pipe_long + #(.bp_params_p(bp_params_p)) + pipe_long + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.reservation_i(reservation_r) + ,.flush_i(commit_pkt_cast_o.npc_w_v) + ,.ibusy_o(idiv_busy_o) + ,.fbusy_o(fdiv_busy_o) + ,.frm_dyn_i(frm_dyn_lo) + + ,.iwb_pkt_o(pipe_long_iwb_pkt) + ,.iwb_v_o(pipe_long_idata_v_lo) + ,.iwb_yumi_i(pipe_long_idata_yumi_lo) + + ,.fwb_pkt_o(pipe_long_fwb_pkt) + ,.fwb_v_o(pipe_long_fdata_v_lo) + ,.fwb_yumi_i(pipe_long_fdata_yumi_lo) + ); + + localparam num_late_wb_lp = 3; + logic [num_late_wb_lp-1:0] late_wb_reqs_li, late_wb_grants_lo; + assign {pipe_long_fdata_yumi_lo, pipe_long_idata_yumi_lo, pipe_mem_late_wb_yumi} = + late_wb_grants_lo & {num_late_wb_lp{late_wb_yumi_i}}; + assign late_wb_reqs_li = {pipe_long_fdata_v_lo, pipe_long_idata_v_lo, pipe_mem_late_wb_v}; + bsg_arb_fixed + #(.inputs_p(num_late_wb_lp), .lo_to_hi_p(1)) + late_wb_arb + (.ready_then_i(1'b1) + ,.reqs_i(late_wb_reqs_li) + ,.grants_o(late_wb_grants_lo) + ); + + bp_be_wb_pkt_s late_wb_pkt_sel; + wire [num_late_wb_lp-1:0][$bits(bp_be_wb_pkt_s)-1:0] late_wb_pkts_li = + {pipe_long_fwb_pkt, pipe_long_iwb_pkt, pipe_mem_late_wb_pkt}; + bsg_mux_one_hot + #(.width_p($bits(bp_be_wb_pkt_s)), .els_p(num_late_wb_lp)) + late_wb_mux_oh + (.data_i(late_wb_pkts_li) + ,.sel_one_hot_i(late_wb_grants_lo) + ,.data_o(late_wb_pkt_sel) + ); + + assign late_wb_pkt_cast_o = late_wb_pkt_sel; + assign late_wb_v_o = |late_wb_grants_lo; + assign late_wb_force_o = pipe_mem_late_wb_v; + + // If a pipeline has completed an instruction (pipe_xxx_v), then mux in the calculated result. + // Else, mux in the previous stage of the completion pipe. Since we are single issue and have + // static latencies, we cannot have two pipelines complete at the same time. + wire injection = dispatch_pkt_cast_i.v & ~dispatch_pkt_cast_i.queue_v; + always_comb + begin + for (integer i = 0; i <= pipe_stage_els_lp; i++) + begin : comp_stage + // Normally, shift down in the pipe + comp_stage_n[i] = (i == 0) + ? '{ird_w_v : dispatch_pkt_cast_i.decode.irf_w_v + ,frd_w_v : dispatch_pkt_cast_i.decode.frf_w_v + ,rd_addr : dispatch_pkt_cast_i.instr.t.rtype.rd_addr + ,default: '0 + } + : comp_stage_r[i-1]; + end + // Injected instructions can carry a payload in rs2 + comp_stage_n[0].rd_data |= injection ? dispatch_pkt_cast_i.rs2 : '0; + comp_stage_n[1].rd_data |= pipe_int_early_data_v_lo ? pipe_int_early_data_lo : '0; + comp_stage_n[1].rd_data |= pipe_sys_data_v_lo ? pipe_sys_data_lo : '0; + comp_stage_n[2].rd_data |= pipe_mem_early_data_v_lo ? pipe_mem_early_data_lo : '0; + comp_stage_n[2].rd_data |= pipe_aux_data_v_lo ? pipe_aux_data_lo : '0; + comp_stage_n[2].rd_data |= pipe_int_catchup_data_v_lo ? pipe_int_catchup_data_lo : '0; + comp_stage_n[3].rd_data |= pipe_mem_final_data_v_lo ? pipe_mem_final_data_lo : '0; + comp_stage_n[3].rd_data |= pipe_mul_data_v_lo ? pipe_mul_data_lo : '0; + comp_stage_n[4].rd_data |= pipe_fma_data_v_lo ? pipe_fma_data_lo : '0; + + // Injected instructions can carry a payload in imm + comp_stage_n[0].fflags |= injection ? dispatch_pkt_cast_i.imm : '0; + comp_stage_n[2].fflags |= pipe_aux_data_v_lo ? pipe_aux_fflags_lo : '0; + comp_stage_n[4].fflags |= pipe_fma_data_v_lo ? pipe_fma_fflags_lo : '0; + + comp_stage_n[0].ird_w_v &= exc_stage_n[0].v; + comp_stage_n[1].ird_w_v &= exc_stage_n[1].v; + comp_stage_n[2].ird_w_v &= exc_stage_n[2].v; + comp_stage_n[3].ird_w_v &= exc_stage_n[3].v; + comp_stage_n[4].ird_w_v &= exc_stage_n[4].v; + + comp_stage_n[0].frd_w_v &= exc_stage_n[0].v; + comp_stage_n[1].frd_w_v &= exc_stage_n[1].v; + comp_stage_n[2].frd_w_v &= exc_stage_n[2].v; + comp_stage_n[3].frd_w_v &= exc_stage_n[3].v; + comp_stage_n[4].frd_w_v &= exc_stage_n[4].v; + + comp_stage_n[0].fflags &= {5{exc_stage_n[0].v}}; + comp_stage_n[1].fflags &= {5{exc_stage_n[1].v}}; + comp_stage_n[2].fflags &= {5{exc_stage_n[2].v}}; + comp_stage_n[3].fflags &= {5{exc_stage_n[3].v}}; + comp_stage_n[4].fflags &= {5{exc_stage_n[4].v}}; + + comp_stage_n[3].ird_w_v &= ~commit_pkt_cast_o.iscore_v; + comp_stage_n[3].frd_w_v &= ~commit_pkt_cast_o.fscore_v; + end + + bsg_dff + #(.width_p($bits(bp_be_wb_pkt_s)*pipe_stage_els_lp)) + comp_stage_reg + (.clk_i(clk_i) + ,.data_i(comp_stage_n[0+:pipe_stage_els_lp]) + ,.data_o(comp_stage_r) + ); + assign iwb_pkt_cast_o = comp_stage_r[3]; + assign fwb_pkt_cast_o = comp_stage_r[4]; + + always_comb + begin + // Exception aggregation + for (integer i = 0; i <= pipe_stage_els_lp; i++) + begin : exc_stage + // Normally, shift down in the pipe + exc_stage_n[i] = (i == 0) ? '0 : exc_stage_r[i-1]; + end + exc_stage_n[0].v |= dispatch_pkt_cast_i.v; + exc_stage_n[0].queue_v |= dispatch_pkt_cast_i.queue_v; + exc_stage_n[0].ispec_v |= dispatch_pkt_cast_i.ispec_v; + exc_stage_n[0].nspec_v |= dispatch_pkt_cast_i.nspec_v; + exc_stage_n[0].spec |= dispatch_pkt_cast_i.special; + exc_stage_n[0].exc |= dispatch_pkt_cast_i.exception; + + exc_stage_n[0].v &= ~commit_pkt_cast_o.npc_w_v | dispatch_pkt_cast_i.nspec_v; + exc_stage_n[1].v &= ~commit_pkt_cast_o.npc_w_v | exc_stage_r[0].nspec_v; + exc_stage_n[2].v &= ~commit_pkt_cast_o.npc_w_v | exc_stage_r[1].nspec_v; + exc_stage_n[3].v &= commit_pkt_cast_o.instret | exc_stage_r[2].nspec_v; + + exc_stage_n[0].queue_v &= ~commit_pkt_cast_o.npc_w_v; + exc_stage_n[1].queue_v &= ~commit_pkt_cast_o.npc_w_v; + exc_stage_n[2].queue_v &= ~commit_pkt_cast_o.npc_w_v; + + exc_stage_n[1].exc.illegal_instr |= pipe_sys_illegal_instr_lo; + + exc_stage_n[1].exc.instr_misaligned |= pipe_int_early_instr_misaligned_lo; + + exc_stage_n[1].exc.dtlb_store_miss |= pipe_mem_dtlb_store_miss_lo; + exc_stage_n[1].exc.dtlb_load_miss |= pipe_mem_dtlb_load_miss_lo; + exc_stage_n[1].exc.load_misaligned |= pipe_mem_load_misaligned_lo; + exc_stage_n[1].exc.load_access_fault |= pipe_mem_load_access_fault_lo; + exc_stage_n[1].exc.load_page_fault |= pipe_mem_load_page_fault_lo; + exc_stage_n[1].exc.store_misaligned |= pipe_mem_store_misaligned_lo; + exc_stage_n[1].exc.store_access_fault |= pipe_mem_store_access_fault_lo; + exc_stage_n[1].exc.store_page_fault |= pipe_mem_store_page_fault_lo; + + exc_stage_n[2].exc.instr_misaligned |= pipe_int_catchup_instr_misaligned_lo; + exc_stage_n[2].exc.mispredict |= pipe_int_catchup_mispredict_lo; + + exc_stage_n[2].exc.dcache_replay |= pipe_mem_dcache_replay_lo; + exc_stage_n[2].spec.dcache_miss |= pipe_mem_dcache_miss_lo; + exc_stage_n[2].exc.cmd_full |= |{exc_stage_r[2].exc, exc_stage_r[2].spec} & cmd_full_n_i; + end + + // Exception pipeline + bsg_dff + #(.width_p($bits(bp_be_exc_stage_s)*pipe_stage_els_lp)) + exc_stage_reg + (.clk_i(clk_i) + ,.data_i(exc_stage_n[0+:pipe_stage_els_lp]) + ,.data_o(exc_stage_r) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_cmd_queue.sv b/designs/black-parrot/src/bp/bp_be_cmd_queue.sv new file mode 100644 index 0000000..9f0d1dc --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_cmd_queue.sv @@ -0,0 +1,75 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_cmd_queue + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + , localparam ptr_width_lp = `BSG_SAFE_CLOG2(fe_cmd_fifo_els_p) + ) + (input clk_i + , input reset_i + + , input [fe_cmd_width_lp-1:0] fe_cmd_i + , input fe_cmd_v_i + + , output logic [fe_cmd_width_lp-1:0] fe_cmd_o + , output logic fe_cmd_v_o + , input fe_cmd_yumi_i + + , output logic empty_n_o + , output logic empty_r_o + , output logic full_n_o + , output logic full_r_o + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + + wire enq = fe_cmd_v_i; + wire deq = fe_cmd_yumi_i; + + logic [ptr_width_lp-1:0] wptr_r, rptr_n, rptr_r; + logic full_lo, empty_lo; + bsg_fifo_tracker + #(.els_p(fe_cmd_fifo_els_p)) + ft + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.enq_i(enq) + ,.deq_i(deq) + ,.wptr_r_o(wptr_r) + ,.rptr_r_o(rptr_r) + ,.rptr_n_o(rptr_n) + ,.full_o(full_lo) + ,.empty_o(empty_lo) + ); + + bsg_mem_1r1w + #(.width_p($bits(bp_fe_cmd_s)), .els_p(fe_cmd_fifo_els_p)) + fifo_mem + (.w_clk_i(clk_i) + ,.w_reset_i(reset_i) + ,.w_v_i(enq) + ,.w_addr_i(wptr_r) + ,.w_data_i(fe_cmd_i) + ,.r_v_i(fe_cmd_v_o) + ,.r_addr_i(rptr_r) + ,.r_data_o(fe_cmd_o) + ); + + assign fe_cmd_v_o = ~empty_lo; + + wire almost_full = (rptr_r == wptr_r+1'b1); + wire almost_empty = (rptr_r == wptr_r-1'b1); + + assign empty_r_o = empty_lo; + assign empty_n_o = (empty_lo | (almost_empty & deq)) & ~enq; + assign full_r_o = full_lo; + assign full_n_o = (full_lo | (almost_full & enq)) & ~deq; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_csr.sv b/designs/black-parrot/src/bp/bp_be_csr.sv new file mode 100644 index 0000000..4440d1b --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_csr.sv @@ -0,0 +1,700 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_csr + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // CSR check interface + , input csr_r_v_i + , input [rv64_csr_addr_width_gp-1:0] csr_r_addr_i + , output logic [dword_width_gp-1:0] csr_r_data_o + , output logic csr_r_illegal_o + + // Misc interface + , input [retire_pkt_width_lp-1:0] retire_pkt_i + , input rv64_fflags_s fflags_acc_i + , input frf_w_v_i + + // Interrupts + , input debug_irq_i + , input timer_irq_i + , input software_irq_i + , input m_external_irq_i + , input s_external_irq_i + , output logic irq_pending_o + , output logic irq_waiting_o + + // The final commit packet + , output logic [commit_pkt_width_lp-1:0] commit_pkt_o + + // Slow signals + , output logic [decode_info_width_lp-1:0] decode_info_o + , output logic [trans_info_width_lp-1:0] trans_info_o + , output rv64_frm_e frm_dyn_o + ); + + // Declare parameterizable structs + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + `declare_csr_structs(vaddr_width_p, paddr_width_p); + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + `bp_cast_i(bp_be_retire_pkt_s, retire_pkt); + `bp_cast_o(bp_be_commit_pkt_s, commit_pkt); + `bp_cast_o(bp_be_decode_info_s, decode_info); + `bp_cast_o(bp_be_trans_info_s, trans_info); + + // The muxed and demuxed CSR outputs + logic [dword_width_gp-1:0] csr_data_lo; + logic exception_v_lo, interrupt_v_lo; + + rv64_mstatus_s sstatus_wmask_li, sstatus_rmask_li; + rv64_mie_s sie_rwmask_li; + rv64_mip_s sip_wmask_li, sip_rmask_li, mip_wmask_li; + + logic [rv64_priv_width_gp-1:0] priv_mode_n, priv_mode_r; + logic debug_mode_n, debug_mode_r; + logic translation_en_n, translation_en_r; + + wire is_debug_mode = debug_mode_r; + // Debug Mode grants pseudo M-mode permission + wire is_m_mode = is_debug_mode | (priv_mode_r == `PRIV_MODE_M); + wire is_s_mode = (priv_mode_r == `PRIV_MODE_S); + wire is_u_mode = (priv_mode_r == `PRIV_MODE_U); + + `declare_csr(dcsr); + `declare_csr_addr(dpc, vaddr_width_p, paddr_width_p); + `declare_csr(dscratch0); + `declare_csr(dscratch1); + + // We have no vendorid currently + wire [dword_width_gp-1:0] mvendorid_lo = 64'h0; + // https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md + // Lucky 13 (*v*) + wire [dword_width_gp-1:0] marchid_lo = 13; + // 0: Tapeout 0, July 2019 + // 1: Tapeout 1, June 2021 + // 2: Tapeout 2, Sept 2022 + // 3: Current + wire [dword_width_gp-1:0] mimpid_lo = 64'd3; + wire [dword_width_gp-1:0] mhartid_lo = cfg_bus_cast_i.core_id; + + `declare_csr(mstatus); + // MISA is optionally read-write, but all fields are read-only in BlackParrot + // 64 bit MXLEN, IMACFDSUB extensions + wire [dword_width_gp-1:0] misa_lo = {2'b10, 36'b0, 26'h14112f}; + `declare_csr(medeleg); + `declare_csr(mideleg); + `declare_csr(mie); + `declare_csr_addr(mtvec, vaddr_width_p, paddr_width_p); + `declare_csr(mcounteren); + + `declare_csr(mscratch); + `declare_csr_addr(mepc, vaddr_width_p, paddr_width_p); + `declare_csr(mcause); + `declare_csr_addr(mtval, vaddr_width_p, paddr_width_p); + `declare_csr(mip); + + // No support for PMP currently + + `declare_csr(mcycle); + `declare_csr(minstret); + // mhpmcounter not implemented + // This is non-compliant. We should hardcode to 0 instead of trapping + `declare_csr(mcountinhibit); + // mhpmevent not implemented + // This is non-compliant. We should hardcode to 0 instead of trapping + + // sstatus subset of mstatus + wire [dword_width_gp-1:0] sstatus_lo = mstatus_lo & sstatus_rmask_li; + wire [dword_width_gp-1:0] sedeleg_lo = '0; + wire [dword_width_gp-1:0] sideleg_lo = '0; + wire [dword_width_gp-1:0] sie_lo = mie_lo & sie_rwmask_li; + `declare_csr_addr(stvec, vaddr_width_p, paddr_width_p); + `declare_csr(scounteren); + + `declare_csr(sscratch); + `declare_csr_addr(sepc, vaddr_width_p, paddr_width_p); + `declare_csr(scause); + `declare_csr_addr(stval, vaddr_width_p, paddr_width_p); + // sip subset of mip + wire [dword_width_gp-1:0] sip_lo = mip_lo & sip_rmask_li; + + `declare_csr_addr(satp, vaddr_width_p, paddr_width_p); + + `declare_csr(fcsr); + wire [dword_width_gp-1:0] fflags_lo = fcsr_lo.fflags; + wire [dword_width_gp-1:0] frm_lo = fcsr_lo.frm; + + wire dgie = ~is_debug_mode; + wire mgie = ~is_debug_mode & (mstatus_r.mie & is_m_mode) | is_s_mode | is_u_mode; + wire sgie = ~is_debug_mode & (mstatus_r.sie & is_s_mode) | is_u_mode; + + wire mti_v = mie_r.mtie & mip_r.mtip; + wire msi_v = mie_r.msie & mip_r.msip; + wire mei_v = mie_r.meie & mip_r.meip; + + wire sti_v = mie_r.stie & mip_r.stip; + wire ssi_v = mie_r.ssie & mip_r.ssip; + wire sei_v = mie_r.seie & (mip_r.seip | s_external_irq_i); + + // TODO: interrupt priority is non-compliant with the spec. + wire [15:0] interrupt_icode_dec_li = + {4'b0 + + ,mei_v + ,1'b0 + ,sei_v + ,1'b0 + + ,mti_v + ,1'b0 // Reserved + ,sti_v + ,1'b0 + + ,msi_v + ,1'b0 // Reserved + ,ssi_v + ,1'b0 + }; + + assign irq_waiting_o = |interrupt_icode_dec_li; + + rv64_exception_dec_s exception_dec_li; + assign exception_dec_li = + '{instr_misaligned : retire_pkt_cast_i.exception.instr_misaligned + ,instr_access_fault : retire_pkt_cast_i.exception.instr_access_fault + ,illegal_instr : retire_pkt_cast_i.exception.illegal_instr + ,breakpoint : retire_pkt_cast_i.exception.ebreak + ,load_misaligned : retire_pkt_cast_i.exception.load_misaligned + ,load_access_fault : retire_pkt_cast_i.exception.load_access_fault + ,store_misaligned : retire_pkt_cast_i.exception.store_misaligned + ,store_access_fault : retire_pkt_cast_i.exception.store_access_fault + ,ecall_u_mode : retire_pkt_cast_i.exception.ecall_u + ,ecall_s_mode : retire_pkt_cast_i.exception.ecall_s + ,ecall_m_mode : retire_pkt_cast_i.exception.ecall_m + ,instr_page_fault : retire_pkt_cast_i.exception.instr_page_fault + ,load_page_fault : retire_pkt_cast_i.exception.load_page_fault + ,store_page_fault : retire_pkt_cast_i.exception.store_page_fault + ,default : '0 + }; + + logic [3:0] exception_ecode_li; + logic exception_ecode_v_li; + bsg_priority_encode + #(.width_p($bits(exception_dec_li)), .lo_to_hi_p(1)) + mcause_exception_enc + (.i(exception_dec_li) + ,.addr_o(exception_ecode_li) + ,.v_o(exception_ecode_v_li) + ); + + wire d_interrupt_icode_v_li = debug_irq_i; + + logic [3:0] m_interrupt_icode_li, s_interrupt_icode_li; + logic m_interrupt_icode_v_li, s_interrupt_icode_v_li; + bsg_priority_encode + #(.width_p($bits(exception_dec_li)), .lo_to_hi_p(1)) + m_interrupt_enc + (.i(interrupt_icode_dec_li & ~mideleg_lo[0+:$bits(exception_dec_li)]) + ,.addr_o(m_interrupt_icode_li) + ,.v_o(m_interrupt_icode_v_li) + ); + + bsg_priority_encode + #(.width_p($bits(exception_dec_li)), .lo_to_hi_p(1)) + s_interrupt_enc + (.i(interrupt_icode_dec_li & mideleg_lo[0+:$bits(exception_dec_li)]) + ,.addr_o(s_interrupt_icode_li) + ,.v_o(s_interrupt_icode_v_li) + ); + + wire csr_w_v_li = retire_pkt_cast_i.special.csrw; + wire [rv64_reg_data_width_gp-1:0] csr_data_li = retire_pkt_cast_i.data; + wire [rv64_csr_addr_width_gp-1:0] csr_addr_li = retire_pkt_cast_i.instr.t.itype.imm12; + wire [rv64_funct3_width_gp-1:0] csr_func_li = retire_pkt_cast_i.instr.t.itype.funct3; + + wire csr_fany_li = csr_addr_li inside {`CSR_ADDR_FCSR, `CSR_ADDR_FFLAGS, `CSR_ADDR_FRM}; + wire instr_fany_li = retire_pkt_cast_i.instr.t.rtype.opcode inside + {`RV64_FLOAD_OP, `RV64_FMADD_OP, `RV64_FMSUB_OP, `RV64_FNMSUB_OP, `RV64_FP_OP}; + + logic enter_debug, exit_debug; + bsg_dff_reset_set_clear + #(.width_p(1)) + debug_mode_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.set_i(enter_debug) + ,.clear_i(exit_debug) + + ,.data_o(debug_mode_r) + ); + + logic [vaddr_width_p-1:0] apc_n, apc_r; + bsg_dff_reset + #(.width_p(vaddr_width_p)) + apc_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(apc_n) + ,.data_o(apc_r) + ); + + // Just for timing, could remove and save some regs... + logic [vaddr_width_p-1:0] cfg_npc_r; + wire [vaddr_width_p-1:0] cfg_npc_n = cfg_bus_cast_i.npc; + bsg_dff + #(.width_p(vaddr_width_p)) + cfg_npc_reg + (.clk_i(clk_i) + ,.data_i(cfg_npc_n) + ,.data_o(cfg_npc_r) + ); + // This currently depends on specific offsets in the debug module which are + // compatible with the pulp-platform debug rom: + // https://github.com/pulp-platform/riscv-dbg/blob/64f48cd8ef3ed4269ab3dfcc32e8a137a871e3e1/src/dm_pkg.sv#L28 + // For now, assume that debug_halt_pc is 16 byte aligned to avoid another mux + wire [vaddr_width_p-1:0] debug_halt_pc = {cfg_npc_r[vaddr_width_p-1:4], 4'b0000}; + wire [vaddr_width_p-1:0] debug_resume_pc = {cfg_npc_r[vaddr_width_p-1:4], 4'b0100}; + wire [vaddr_width_p-1:0] debug_exception_pc = {cfg_npc_r[vaddr_width_p-1:4], 4'b1000}; + + wire [vaddr_width_p-1:0] ret_pc = + retire_pkt_cast_i.special.sret + ? sepc_lo + : retire_pkt_cast_i.special.mret + ? mepc_lo + : dpc_lo; + wire [vaddr_width_p-1:0] tvec_pc = + is_debug_mode ? debug_exception_pc + : (priv_mode_n == `PRIV_MODE_S) + ? {stvec_lo.base, 2'b00} + : {mtvec_lo.base, 2'b00}; + + wire [vaddr_width_p-1:0] core_npc = + (exception_v_lo | interrupt_v_lo) + ? tvec_pc + : commit_pkt_cast_o.eret + ? ret_pc + : retire_pkt_cast_i.instret + ? retire_pkt_cast_i.npc + : apc_r; + + assign apc_n = (enter_debug | cfg_bus_cast_i.freeze) ? debug_halt_pc : core_npc; + + assign translation_en_n = ((priv_mode_n < `PRIV_MODE_M) & (satp_li.mode == 4'd8)); + bsg_dff_reset + #(.width_p(3), .reset_val_p({1'b0, `PRIV_MODE_M})) + priv_mode_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i({translation_en_n, priv_mode_n}) + ,.data_o({translation_en_r, priv_mode_r}) + ); + + // sstatus mask + assign sstatus_wmask_li = '{fs: 2'b11 + ,mxr: 1'b1, sum: 1'b1 + ,mpp: 2'b00, spp: 2'b11 + ,mpie: 1'b0, spie: 1'b1 + ,mie: 1'b0, sie: 1'b1 + ,default: '0 + }; + assign sstatus_rmask_li = '{sd: 1'b1, uxl: 2'b11, fs: 2'b11 + ,mxr: 1'b1, sum: 1'b1 + ,mpp: 2'b00, spp: 2'b11 + ,mpie: 1'b0, spie: 1'b1 + ,mie: 1'b0, sie: 1'b1 + ,default: '0 + }; + + // sie mask + assign sie_rwmask_li = mideleg_lo; + + // sip mask + assign sip_rmask_li = mideleg_lo; + assign sip_wmask_li = '{meip: 1'b0, seip: 1'b0 + ,mtip: 1'b0, stip: 1'b0 + ,msip: 1'b0, ssip: mideleg_lo.ssi + ,default: '0 + }; + + // CSR read + always_comb + begin + csr_r_illegal_o = 1'b0; + unique casez (csr_r_addr_i) + {`CSR_ADDR_FFLAGS }: csr_data_lo = fcsr_lo.fflags; + {`CSR_ADDR_FRM }: csr_data_lo = fcsr_lo.frm; + {`CSR_ADDR_FCSR }: csr_data_lo = fcsr_lo; + {`CSR_ADDR_CYCLE }: csr_data_lo = mcycle_lo; + {`CSR_ADDR_INSTRET }: csr_data_lo = minstret_lo; + {`CSR_ADDR_SSTATUS }: csr_data_lo = sstatus_lo; + {`CSR_ADDR_SEDELEG }: csr_data_lo = sedeleg_lo; + {`CSR_ADDR_SIDELEG }: csr_data_lo = sideleg_lo; + {`CSR_ADDR_SIE }: csr_data_lo = sie_lo; + {`CSR_ADDR_STVEC }: csr_data_lo = stvec_lo; + {`CSR_ADDR_SCOUNTEREN }: csr_data_lo = scounteren_lo; + {`CSR_ADDR_SSCRATCH }: csr_data_lo = sscratch_lo; + {`CSR_ADDR_SEPC }: csr_data_lo = sepc_lo; + {`CSR_ADDR_SCAUSE }: csr_data_lo = scause_lo; + {`CSR_ADDR_STVAL }: csr_data_lo = stval_lo; + {`CSR_ADDR_SIP }: csr_data_lo = sip_lo; + {`CSR_ADDR_SATP }: csr_data_lo = satp_lo; + {`CSR_ADDR_MVENDORID }: csr_data_lo = mvendorid_lo; + {`CSR_ADDR_MARCHID }: csr_data_lo = marchid_lo; + {`CSR_ADDR_MIMPID }: csr_data_lo = mimpid_lo; + {`CSR_ADDR_MHARTID }: csr_data_lo = mhartid_lo; + {`CSR_ADDR_MSTATUS }: csr_data_lo = mstatus_lo; + {`CSR_ADDR_MISA }: csr_data_lo = misa_lo; + {`CSR_ADDR_MEDELEG }: csr_data_lo = medeleg_lo; + {`CSR_ADDR_MIDELEG }: csr_data_lo = mideleg_lo; + {`CSR_ADDR_MIE }: csr_data_lo = mie_lo; + {`CSR_ADDR_MTVEC }: csr_data_lo = mtvec_lo; + {`CSR_ADDR_MCOUNTEREN }: csr_data_lo = mcounteren_lo; + {`CSR_ADDR_MIP }: csr_data_lo = mip_lo; + {`CSR_ADDR_MSCRATCH }: csr_data_lo = mscratch_lo; + {`CSR_ADDR_MEPC }: csr_data_lo = mepc_lo; + {`CSR_ADDR_MCAUSE }: csr_data_lo = mcause_lo; + {`CSR_ADDR_MTVAL }: csr_data_lo = mtval_lo; + {`CSR_ADDR_MCYCLE }: csr_data_lo = mcycle_lo; + {`CSR_ADDR_MINSTRET }: csr_data_lo = minstret_lo; + {`CSR_ADDR_MCOUNTINHIBIT}: csr_data_lo = mcountinhibit_lo; + {`CSR_ADDR_DCSR }: csr_data_lo = dcsr_lo; + {`CSR_ADDR_DPC }: csr_data_lo = dpc_lo; + {`CSR_ADDR_DSCRATCH0 }: csr_data_lo = dscratch0_lo; + {`CSR_ADDR_DSCRATCH1 }: csr_data_lo = dscratch1_lo; + default: + begin + csr_data_lo = '0; + csr_r_illegal_o = csr_r_v_i; + end + endcase + end + + // CSR update + always_comb + begin + priv_mode_n = priv_mode_r; + + fcsr_li = fcsr_lo; + + stvec_li = stvec_lo; + scounteren_li = scounteren_lo; + + sscratch_li = sscratch_lo; + sepc_li = sepc_lo; + scause_li = scause_lo; + stval_li = stval_lo; + + satp_li = satp_lo; + + mstatus_li = mstatus_lo; + medeleg_li = medeleg_lo; + mideleg_li = mideleg_lo; + mie_li = mie_lo; + mtvec_li = mtvec_lo; + mcounteren_li = mcounteren_lo; + + mscratch_li = mscratch_lo; + mepc_li = mepc_lo; + mcause_li = mcause_lo; + mtval_li = mtval_lo; + mip_li = mip_lo; + + mcycle_li = mcycle_lo; + minstret_li = minstret_lo; + mcountinhibit_li = mcountinhibit_lo; + + dcsr_li = dcsr_lo; + dpc_li = dpc_lo; + dscratch0_li = dscratch0_lo; + dscratch1_li = dscratch1_lo; + + enter_debug = '0; + exit_debug = '0; + exception_v_lo = '0; + interrupt_v_lo = '0; + + unique casez ({csr_w_v_li, csr_addr_li}) + {1'b1, `CSR_ADDR_FFLAGS }: fcsr_li = '{frm: fcsr_lo.frm, fflags: csr_data_li, default: '0}; + {1'b1, `CSR_ADDR_FRM }: fcsr_li = '{frm: csr_data_li, fflags: fcsr_lo.fflags, default: '0}; + {1'b1, `CSR_ADDR_FCSR }: fcsr_li = csr_data_li; + // Time must be done by trapping, since we can't stall at this point + {1'b1, `CSR_ADDR_INSTRET }: minstret_li = csr_data_li; + // SSTATUS subset of MSTATUS + {1'b1, `CSR_ADDR_SSTATUS }: mstatus_li = (mstatus_lo & ~sstatus_wmask_li) | (csr_data_li & sstatus_wmask_li); + // Read-only because we don't support N-extension + // Read-only because we don't support N-extension + {1'b1, `CSR_ADDR_SEDELEG }: begin end + {1'b1, `CSR_ADDR_SIDELEG }: begin end + {1'b1, `CSR_ADDR_SIE }: mie_li = (mie_lo & ~sie_rwmask_li) | (csr_data_li & sie_rwmask_li); + {1'b1, `CSR_ADDR_STVEC }: stvec_li = csr_data_li; + {1'b1, `CSR_ADDR_SCOUNTEREN }: scounteren_li = csr_data_li; + {1'b1, `CSR_ADDR_SSCRATCH }: sscratch_li = csr_data_li; + {1'b1, `CSR_ADDR_SEPC }: sepc_li = csr_data_li; + {1'b1, `CSR_ADDR_SCAUSE }: scause_li = csr_data_li; + {1'b1, `CSR_ADDR_STVAL }: stval_li = csr_data_li; + // SIP subset of MIP + {1'b1, `CSR_ADDR_SIP }: mip_li = (mip_lo & ~sip_wmask_li) | (csr_data_li & sip_wmask_li); + {1'b1, `CSR_ADDR_SATP }: satp_li = csr_data_li; + {1'b1, `CSR_ADDR_MSTATUS }: mstatus_li = csr_data_li; + {1'b1, `CSR_ADDR_MISA }: begin end + {1'b1, `CSR_ADDR_MEDELEG }: medeleg_li = csr_data_li; + {1'b1, `CSR_ADDR_MIDELEG }: mideleg_li = csr_data_li; + {1'b1, `CSR_ADDR_MIE }: mie_li = csr_data_li; + {1'b1, `CSR_ADDR_MTVEC }: mtvec_li = csr_data_li; + {1'b1, `CSR_ADDR_MCOUNTEREN }: mcounteren_li = csr_data_li; + {1'b1, `CSR_ADDR_MIP }: mip_li = csr_data_li; + {1'b1, `CSR_ADDR_MSCRATCH }: mscratch_li = csr_data_li; + {1'b1, `CSR_ADDR_MEPC }: mepc_li = csr_data_li; + {1'b1, `CSR_ADDR_MCAUSE }: mcause_li = csr_data_li; + {1'b1, `CSR_ADDR_MTVAL }: mtval_li = csr_data_li; + {1'b1, `CSR_ADDR_MCYCLE }: mcycle_li = csr_data_li; + {1'b1, `CSR_ADDR_MINSTRET }: minstret_li = csr_data_li; + {1'b1, `CSR_ADDR_MCOUNTINHIBIT}: mcountinhibit_li = csr_data_li; + {1'b1, `CSR_ADDR_DCSR }: dcsr_li = csr_data_li; + {1'b1, `CSR_ADDR_DPC }: dpc_li = csr_data_li; + {1'b1, `CSR_ADDR_DSCRATCH0 }: dscratch0_li = csr_data_li; + {1'b1, `CSR_ADDR_DSCRATCH1 }: dscratch1_li = csr_data_li; + default: begin end + endcase + + if (retire_pkt_cast_i.exception._interrupt) + begin + if (m_interrupt_icode_v_li & mgie) + begin + priv_mode_n = `PRIV_MODE_M; + + mstatus_li.mpp = priv_mode_r; + mstatus_li.mpie = mstatus_lo.mie; + mstatus_li.mie = 1'b0; + + mepc_li = `BSG_SIGN_EXTEND(apc_r, dword_width_gp); + mtval_li = '0; + mcause_li._interrupt = 1'b1; + mcause_li.ecode = m_interrupt_icode_li; + + interrupt_v_lo = 1'b1; + end + else if (s_interrupt_icode_v_li & sgie) + begin + priv_mode_n = `PRIV_MODE_S; + + mstatus_li.spp = priv_mode_r; + mstatus_li.spie = mstatus_lo.sie; + mstatus_li.sie = 1'b0; + + sepc_li = `BSG_SIGN_EXTEND(apc_r, dword_width_gp); + stval_li = '0; + scause_li._interrupt = 1'b1; + scause_li.ecode = s_interrupt_icode_li; + + interrupt_v_lo = 1'b1; + end + end + else if (exception_ecode_v_li) + begin + if (is_debug_mode) + begin + // Trap back into debug mode, don't set any CSRs + exception_v_lo = 1'b1; + end + else if (medeleg_lo[exception_ecode_li] & ~is_m_mode) + begin + priv_mode_n = `PRIV_MODE_S; + + mstatus_li.spp = priv_mode_r; + mstatus_li.spie = mstatus_lo.sie; + mstatus_li.sie = 1'b0; + + sepc_li = `BSG_SIGN_EXTEND(apc_r, dword_width_gp); + stval_li = (exception_ecode_li == 2) + ? retire_pkt_cast_i.instr + : `BSG_SIGN_EXTEND(retire_pkt_cast_i.vaddr, dword_width_gp); + + scause_li._interrupt = 1'b0; + scause_li.ecode = exception_ecode_li; + + exception_v_lo = 1'b1; + end + else + begin + priv_mode_n = `PRIV_MODE_M; + + mstatus_li.mpp = priv_mode_r; + mstatus_li.mpie = mstatus_lo.mie; + mstatus_li.mie = 1'b0; + + mepc_li = `BSG_SIGN_EXTEND(apc_r, dword_width_gp); + mtval_li = (exception_ecode_li == 2) + ? retire_pkt_cast_i.instr + : `BSG_SIGN_EXTEND(retire_pkt_cast_i.vaddr, dword_width_gp); + + mcause_li._interrupt = 1'b0; + mcause_li.ecode = exception_ecode_li; + + exception_v_lo = 1'b1; + end + end + + // Re-enter debug mode if ebreaking during debug sequence + if (is_debug_mode) + begin + enter_debug = retire_pkt_cast_i.special.dbreak; + end + else if (retire_pkt_cast_i.exception._interrupt & d_interrupt_icode_v_li & dgie) + begin + enter_debug = 1'b1; + dpc_li = `BSG_SIGN_EXTEND(apc_r, dword_width_gp); + dcsr_li.cause = 3; // Debugger + dcsr_li.prv = priv_mode_r; + end + else if (retire_pkt_cast_i.special.dbreak) + begin + enter_debug = 1'b1; + dpc_li = `BSG_SIGN_EXTEND(apc_r, dword_width_gp); + dcsr_li.cause = 1; // Ebreak + dcsr_li.prv = priv_mode_r; + end + // Always break in single step mode + else if (retire_pkt_cast_i.queue_v & dcsr_lo.step) + begin + enter_debug = 1'b1; + dpc_li = `BSG_SIGN_EXTEND(core_npc, dword_width_gp); + dcsr_li.cause = 4; + dcsr_li.prv = priv_mode_r; + end + + // Only exit debug mode through dret + if (retire_pkt_cast_i.special.dret) + begin + exit_debug = 1'b1; + priv_mode_n = dcsr_lo.prv; + end + + if (retire_pkt_cast_i.special.mret) + begin + priv_mode_n = mstatus_lo.mpp; + + mstatus_li.mpp = `PRIV_MODE_U; + mstatus_li.mpie = 1'b1; + mstatus_li.mie = mstatus_lo.mpie; + mstatus_li.mprv = (priv_mode_n < `PRIV_MODE_M) ? '0 : mstatus_li.mprv; + end + + if (retire_pkt_cast_i.special.sret) + begin + priv_mode_n = {1'b0, mstatus_lo.spp}; + + mstatus_li.spp = `PRIV_MODE_U; + mstatus_li.spie = 1'b1; + mstatus_li.sie = mstatus_lo.spie; + mstatus_li.mprv = (priv_mode_n < `PRIV_MODE_M) ? '0 : mstatus_li.mprv; + end + + // Accumulate interrupts + mip_li.mtip = timer_irq_i; + mip_li.msip = software_irq_i; + mip_li.meip = m_external_irq_i; + + // Accumulate FFLAGS if we're not writing them this cycle + if (~(csr_w_v_li & csr_addr_li inside {`CSR_ADDR_FFLAGS, `CSR_ADDR_FCSR})) + fcsr_li.fflags |= fflags_acc_i; + + // Accumulate counters if we're not writing them + if (~(csr_w_v_li & csr_addr_li inside {`CSR_ADDR_CYCLE, `CSR_ADDR_MCYCLE}) & ~mcountinhibit_lo.cy) + mcycle_li = mcycle_lo + 1'b1; + if (~(csr_w_v_li & csr_addr_li inside {`CSR_ADDR_INSTRET, `CSR_ADDR_MINSTRET}) & ~mcountinhibit_lo.ir) + minstret_li = minstret_lo + retire_pkt_cast_i.instret; + + // Set FS to dirty if: fflags set, frf written, fcsr written + mstatus_li.fs |= {2{csr_w_v_li & csr_fany_li}}; + mstatus_li.fs |= {2{retire_pkt_cast_i.instret & instr_fany_li}}; + end + + assign irq_pending_o = (~dcsr_lo.step | dcsr_lo.stepie) + & ((d_interrupt_icode_v_li & dgie) | (m_interrupt_icode_v_li & mgie) | (s_interrupt_icode_v_li & sgie)); + + // The supervisor external interrupt line does not impact the supervisor software interrupt bit of MIP. + // However, software read operations return as if it does. bit 9 is supervisor software interrupt + always_comb + unique casez (csr_addr_li) + `CSR_ADDR_SIP : csr_r_data_o = csr_data_lo | ((s_external_irq_i & sip_rmask_li) << 9); + `CSR_ADDR_MIP : csr_r_data_o = csr_data_lo | (s_external_irq_i << 9); + `CSR_ADDR_FFLAGS + ,`CSR_ADDR_FCSR : csr_r_data_o = csr_data_lo | fflags_acc_i; + default: csr_r_data_o = csr_data_lo; + endcase + + assign commit_pkt_cast_o.npc_w_v = |{retire_pkt_cast_i.special, retire_pkt_cast_i.exception}; + assign commit_pkt_cast_o.queue_v = retire_pkt_cast_i.queue_v & ~|retire_pkt_cast_i.exception; + assign commit_pkt_cast_o.instret = retire_pkt_cast_i.instret; + assign commit_pkt_cast_o.size = retire_pkt_cast_i.size; + assign commit_pkt_cast_o.count = retire_pkt_cast_i.count; + assign commit_pkt_cast_o.pc = apc_r; + assign commit_pkt_cast_o.npc = apc_n; + assign commit_pkt_cast_o.vaddr = retire_pkt_cast_i.vaddr; + assign commit_pkt_cast_o.instr = retire_pkt_cast_i.instr; + assign commit_pkt_cast_o.pte_leaf = retire_pkt_cast_i.data; + assign commit_pkt_cast_o.priv_n = priv_mode_n; + assign commit_pkt_cast_o.translation_en_n = translation_en_n; + assign commit_pkt_cast_o.exception = exception_v_lo; + // Debug mode acts as a pseudo-interrupt + assign commit_pkt_cast_o._interrupt = interrupt_v_lo | enter_debug; + assign commit_pkt_cast_o.fencei = retire_pkt_cast_i.special.fencei; + assign commit_pkt_cast_o.sfence = retire_pkt_cast_i.special.sfence_vma; + assign commit_pkt_cast_o.wfi = retire_pkt_cast_i.special.wfi; + assign commit_pkt_cast_o.eret = |{retire_pkt_cast_i.special.dret, retire_pkt_cast_i.special.mret, retire_pkt_cast_i.special.sret}; + assign commit_pkt_cast_o.csrw = retire_pkt_cast_i.special.csrw; + assign commit_pkt_cast_o.resume = retire_pkt_cast_i.exception.resume; + assign commit_pkt_cast_o.itlb_miss = retire_pkt_cast_i.exception.itlb_miss; + assign commit_pkt_cast_o.icache_miss = retire_pkt_cast_i.exception.icache_miss; + assign commit_pkt_cast_o.dtlb_store_miss = retire_pkt_cast_i.exception.dtlb_store_miss; + assign commit_pkt_cast_o.dtlb_load_miss = retire_pkt_cast_i.exception.dtlb_load_miss; + assign commit_pkt_cast_o.dcache_replay = retire_pkt_cast_i.exception.dcache_replay; + assign commit_pkt_cast_o.dcache_miss = retire_pkt_cast_i.special.dcache_miss; + assign commit_pkt_cast_o.itlb_fill_v = retire_pkt_cast_i.exception.itlb_fill; + assign commit_pkt_cast_o.dtlb_fill_v = retire_pkt_cast_i.exception.dtlb_fill; + assign commit_pkt_cast_o.iscore_v = retire_pkt_cast_i.iscore; + assign commit_pkt_cast_o.fscore_v = retire_pkt_cast_i.fscore; + + assign trans_info_cast_o.priv_mode = priv_mode_r; + assign trans_info_cast_o.base_ppn = satp_lo.ppn; + assign trans_info_cast_o.translation_en = translation_en_r + | ((~is_debug_mode | dcsr_lo.mprven) & mstatus_lo.mprv & (mstatus_lo.mpp < `PRIV_MODE_M) & (satp_lo.mode == 4'd8)); + assign trans_info_cast_o.mstatus_sum = mstatus_lo.sum; + assign trans_info_cast_o.mstatus_mxr = mstatus_lo.mxr; + + assign decode_info_cast_o.m_mode = is_m_mode; + assign decode_info_cast_o.s_mode = is_s_mode; + assign decode_info_cast_o.u_mode = is_u_mode; + assign decode_info_cast_o.debug_mode = debug_mode_r; + assign decode_info_cast_o.tsr = mstatus_lo.tsr; + assign decode_info_cast_o.tw = mstatus_lo.tw; + assign decode_info_cast_o.tvm = mstatus_lo.tvm; + assign decode_info_cast_o.ebreakm = dcsr_lo.ebreakm; + assign decode_info_cast_o.ebreaks = dcsr_lo.ebreaks; + assign decode_info_cast_o.ebreaku = dcsr_lo.ebreaku; + assign decode_info_cast_o.fpu_en = (mstatus_lo.fs != 2'b00); + assign decode_info_cast_o.cycle_en = is_m_mode | (is_s_mode & mcounteren_lo.cy) | (is_u_mode & scounteren_lo.cy); + assign decode_info_cast_o.instret_en = is_m_mode | (is_m_mode & mcounteren_lo.ir) | (is_u_mode & mcounteren_lo.ir); + + assign frm_dyn_o = rv64_frm_e'(fcsr_lo.frm); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_ctl_pkgdef.svh b/designs/black-parrot/src/bp/bp_be_ctl_pkgdef.svh new file mode 100644 index 0000000..58969ff --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_ctl_pkgdef.svh @@ -0,0 +1,284 @@ + +`ifndef BP_BE_CTL_PKGDEF_SVH +`define BP_BE_CTL_PKGDEF_SVH + + typedef enum logic [5:0] + { + e_int_op_add = 6'b000000 + ,e_int_op_slt = 6'b000010 + ,e_int_op_sge = 6'b001010 + ,e_int_op_sltu = 6'b000011 + ,e_int_op_sgeu = 6'b001011 + ,e_int_op_xor = 6'b000100 + ,e_int_op_eq = 6'b001100 + ,e_int_op_sll = 6'b001111 + ,e_int_op_srl = 6'b000101 + ,e_int_op_sra = 6'b001101 + ,e_int_op_or = 6'b000110 + ,e_int_op_ne = 6'b001110 + ,e_int_op_and = 6'b000111 + ,e_int_op_cpop = 6'b010000 + ,e_int_op_clz = 6'b010001 + ,e_int_op_min = 6'b010010 + ,e_int_op_minu = 6'b010011 + ,e_int_op_max = 6'b010100 + ,e_int_op_maxu = 6'b010101 + ,e_int_op_orcb = 6'b010110 + ,e_int_op_rev8 = 6'b010111 + ,e_int_op_bclr = 6'b100000 + ,e_int_op_bext = 6'b100001 + ,e_int_op_binv = 6'b100010 + ,e_int_op_binvi = 6'b100011 + ,e_int_op_bset = 6'b100100 + } bp_be_int_fu_op_e; + + typedef enum logic [5:0] + { + // Movement instructions + e_aux_op_f2f = 6'b000000 + ,e_aux_op_f2i = 6'b000001 + ,e_aux_op_i2f = 6'b000010 + ,e_aux_op_f2iu = 6'b000011 + ,e_aux_op_iu2f = 6'b000100 + ,e_aux_op_imvf = 6'b000101 + ,e_aux_op_fmvi = 6'b000110 + ,e_aux_op_fsgnj = 6'b000111 + ,e_aux_op_fsgnjn = 6'b001000 + ,e_aux_op_fsgnjx = 6'b001001 + + // FCMP instructions + ,e_aux_op_feq = 6'b001010 + ,e_aux_op_flt = 6'b001011 + ,e_aux_op_fle = 6'b001100 + ,e_aux_op_fmax = 6'b001101 + ,e_aux_op_fmin = 6'b001110 + ,e_aux_op_fclass = 6'b001111 + } bp_be_aux_fu_op_e; + + typedef enum logic [5:0] + { + e_dcache_op_lb = 6'b000000 + ,e_dcache_op_lh = 6'b000001 + ,e_dcache_op_lw = 6'b000010 + ,e_dcache_op_ld = 6'b000011 + ,e_dcache_op_lbu = 6'b000100 + ,e_dcache_op_lhu = 6'b000101 + ,e_dcache_op_lwu = 6'b000110 + + ,e_dcache_op_sb = 6'b001000 + ,e_dcache_op_sh = 6'b001001 + ,e_dcache_op_sw = 6'b001010 + ,e_dcache_op_sd = 6'b001011 + + ,e_dcache_op_lrw = 6'b000111 + ,e_dcache_op_scw = 6'b001100 + + ,e_dcache_op_lrd = 6'b001101 + ,e_dcache_op_scd = 6'b001110 + + ,e_dcache_op_flw = 6'b100010 + ,e_dcache_op_fld = 6'b100011 + + ,e_dcache_op_fsw = 6'b100100 + ,e_dcache_op_fsd = 6'b100101 + + ,e_dcache_op_amoswapw = 6'b010000 + ,e_dcache_op_amoaddw = 6'b010001 + ,e_dcache_op_amoxorw = 6'b010010 + ,e_dcache_op_amoandw = 6'b010011 + ,e_dcache_op_amoorw = 6'b010100 + ,e_dcache_op_amominw = 6'b010101 + ,e_dcache_op_amomaxw = 6'b010110 + ,e_dcache_op_amominuw = 6'b010111 + ,e_dcache_op_amomaxuw = 6'b011000 + + ,e_dcache_op_amoswapd = 6'b011001 + ,e_dcache_op_amoaddd = 6'b011010 + ,e_dcache_op_amoxord = 6'b011011 + ,e_dcache_op_amoandd = 6'b011100 + ,e_dcache_op_amoord = 6'b011101 + ,e_dcache_op_amomind = 6'b011110 + ,e_dcache_op_amomaxd = 6'b011111 + ,e_dcache_op_amominud = 6'b100000 + ,e_dcache_op_amomaxud = 6'b100001 + + ,e_dcache_op_ptw = 6'b111000 + + ,e_dcache_op_bzero = 6'b110000 + ,e_dcache_op_bclean = 6'b110001 + ,e_dcache_op_binval = 6'b110010 + ,e_dcache_op_bflush = 6'b110100 + ,e_dcache_op_clean = 6'b111110 + ,e_dcache_op_inval = 6'b111101 + ,e_dcache_op_flush = 6'b111111 + } bp_be_dcache_fu_op_e; + + typedef enum logic [5:0] + { + e_fma_op_fadd = 6'b000000 + ,e_fma_op_fsub = 6'b000001 + ,e_fma_op_fmul = 6'b000010 + ,e_fma_op_fmadd = 6'b000011 + ,e_fma_op_fmsub = 6'b000100 + ,e_fma_op_fnmsub = 6'b000101 + ,e_fma_op_fnmadd = 6'b000110 + ,e_fma_op_imul = 6'b000111 + } bp_be_fma_fu_op_e; + + typedef enum logic [5:0] + { + e_long_op_div = 6'b000001 + ,e_long_op_divu = 6'b000010 + ,e_long_op_rem = 6'b000011 + ,e_long_op_remu = 6'b000100 + ,e_long_op_mulh = 6'b000101 + ,e_long_op_mulhsu = 6'b000110 + ,e_long_op_mulhu = 6'b000111 + ,e_long_op_fdiv = 6'b001000 + ,e_long_op_fsqrt = 6'b001001 + } bp_be_long_fu_op_e; + + typedef struct packed + { + union packed + { + bp_be_int_fu_op_e int_fu_op; + bp_be_aux_fu_op_e aux_fu_op; + bp_be_dcache_fu_op_e dcache_fu_op; + bp_be_fma_fu_op_e fma_fu_op; + bp_be_long_fu_op_e long_fu_op; + } t; + } bp_be_fu_op_s; + + typedef enum logic [2:0] + { + e_src1_is_rs1 = 3'b000 + ,e_src1_is_rs1_lsh = 3'b011 + ,e_src1_is_rs1_lshn = 3'b100 + ,e_src1_is_rs1_rev = 3'b101 + ,e_src1_is_zero = 3'b010 + } bp_be_src1_e; + + typedef enum logic [2:0] + { + e_src2_is_rs2 = 3'b000 + ,e_src2_is_rs1_rsh = 3'b100 + ,e_src2_is_rs1_rshn = 3'b110 + ,e_src2_is_rs2n = 3'b011 + ,e_src2_is_zero = 3'b010 + } bp_be_src2_e; + + typedef enum logic + { + e_baddr_is_pc = 1'b0 + ,e_baddr_is_rs1 = 1'b1 + } bp_be_baddr_e; + + typedef struct packed + { + logic pipe_int_v; + logic pipe_mem_early_v; + logic pipe_aux_v; + logic pipe_mem_final_v; + logic pipe_sys_v; + logic pipe_mul_v; + logic pipe_fma_v; + logic pipe_long_v; + + logic irs1_r_v; + logic irs2_r_v; + logic frs1_r_v; + logic frs2_r_v; + logic frs3_r_v; + logic irf_w_v; + logic frf_w_v; + logic br_v; + logic j_v; + logic jr_v; + logic fence_v; + logic dcache_r_v; + logic dcache_w_v; + logic dcache_cbo_v; + logic dcache_mmu_v; + logic csr_w_v; + logic csr_r_v; + logic mem_v; + logic score_v; + logic spec_w_v; + logic fmove_v; + logic carryin; + + logic irs1_unsigned; + logic [$bits(bp_be_int_tag_e)-1:0] irs1_tag; + logic irs2_unsigned; + logic [$bits(bp_be_int_tag_e)-1:0] irs2_tag; + logic [$bits(bp_be_fp_tag_e)-1:0] frs1_tag; + logic [$bits(bp_be_fp_tag_e)-1:0] frs2_tag; + logic [$bits(bp_be_fp_tag_e)-1:0] frs3_tag; + + bp_be_fu_op_s fu_op; + logic [$bits(bp_be_fp_tag_e)-1:0] frd_tag; + logic [$bits(bp_be_int_tag_e)-1:0] ird_tag; + + logic [$bits(bp_be_src1_e)-1:0] src1_sel; + logic [$bits(bp_be_src2_e)-1:0] src2_sel; + } bp_be_decode_s; + + typedef struct packed + { + // True exceptions + logic store_page_fault; + logic load_page_fault; + logic instr_page_fault; + logic ecall_m; + logic ecall_s; + logic ecall_u; + logic store_access_fault; + logic store_misaligned; + logic load_access_fault; + logic load_misaligned; + logic ebreak; + logic illegal_instr; + logic instr_access_fault; + logic instr_misaligned; + + // BP "exceptions" + logic resume; + logic itlb_miss; + logic icache_miss; + logic dcache_replay; + logic dtlb_load_miss; + logic dtlb_store_miss; + logic itlb_fill; + logic dtlb_fill; + logic _interrupt; + logic cmd_full; + logic mispredict; + } bp_be_exception_s; + + typedef struct packed + { + logic dcache_miss; + logic fencei; + logic sfence_vma; + logic dbreak; + logic dret; + logic mret; + logic sret; + logic wfi; + logic csrw; + } bp_be_special_s; + + typedef struct packed + { + logic v; + logic queue_v; + logic ispec_v; + logic nspec_v; + + bp_be_exception_s exc; + bp_be_special_s spec; + } bp_be_exc_stage_s; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_be_dcache.sv b/designs/black-parrot/src/bp/bp_be_dcache.sv new file mode 100644 index 0000000..106bb27 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_dcache.sv @@ -0,0 +1,1270 @@ +/** + * Name: + * bp_be_dcache.v + * + * Description: + * L1 Data Cache. Features: + * - Virtually-indexed, physically-tagged + * - 1-8 way set-associative + * - 64-512 bit block size (minimum 64-bit data mem bank size) + * + * There are three large 1rw memory blocks: data_mem, tag_mem, stat_mem: + * - data_mem is divided into 1 bank per way, and cache blocks are + * interleaved among the banks. The governing relationship is "bank_id = + * word_offset + way_id" (with modular arithmetic). + * + * - tag_mem contains tag and coherence state bits. + * + * - stat_mem contains information about dirty bits for each cache block and + * LRU info about each way group (pseudo-LRU replacement policy). + * + * There are two pipeline stages: tag lookup (TL), tag verify (TV) stages. + * Signals and registers are suffixed by stage name. + * + * - Before TL, a dcache_pkt containing opcode, address and store data arrives + * at the cache. It is decoded and latched. + * + * - In TL, data mem and tag mem are synchronously accessed. Addtionally, the + * physical tag and PMA attributes arrive and are latched. Hit detection is + * also performed in this stage. + * + * - In TV, the data read is muxed down to the correct word based on the bank hash + * of the hit vector and the word offset. + * + * There is a write buffer which allows holding write data from tv stage, delaying the + * physical write until data_mem becomes from from incoming loads. To prevent data + * hazards, it also supports bypassing from TV to TL if there is an address match in + * the write buffer + * + * An address is broken down as follows: + * physical address = [physical tag | virtual index | block offset] + * + * Load reserved and store conditional are implemented at a cache line granularity. + * A load reserved acts as a normal load with the following addtional properties: + * 1) If the block is not in an exclusive ownership state (M or E in MESI), then the cache + * will send an upgrade request (store miss). + * 2) If the LR is successful, a reservation is placed on the cache line. This reservation is + * valid for the current hart only. + * A store conditional will succeed (return 0) if there is a valid reservation on the address of + * the SC. Else, it will fail (return nonzero and will not commit the store). A failing store + * conditional will not produce a cache miss. + * + * The reservation can be cleared by: + * 1) Any SC to any address by this hart. + * 2) A second LR (this will not clear the reservation, but it will change the reservation + * address). + * 3) An invalidate received from the LCE. This command covers all cases of losing exclusive + * access to the block in this hart, including eviction and a cache miss. + + * RISC-V guarantees forward progress for LR/SC sequences that match a set of conditions. + * BlackParrot guarantees progress by blocking remote invalidations until a following SC + * (subject to a timeout). Tradeoffs between local and remote QoS can be made by adjusting + * the lock time. + * + * LR/SC aq/rl semantics are irrelevant for BlackParrot. Since we are in-order single issue and + * do not use a store buffer that allows stores before cache lines have been fetched, all + * memory requests are inherently ordered within a hart. + * + * The dcache supports multi-cycle fill/eviction with the following constraints: + * - bank_width = block_width / assoc >= dword_width + * - fill_width = N*bank_width <= block_width + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_dcache + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Default to dcache parameters, but can override if needed + , parameter coherent_p = dcache_features_p[e_cfg_coherent] + , parameter writeback_p = dcache_features_p[e_cfg_writeback] + , parameter [31:0] amo_support_p = (((dcache_features_p[e_cfg_lr_sc]) << e_dcache_subop_lr) + | ((dcache_features_p[e_cfg_lr_sc]) << e_dcache_subop_sc) + | ((dcache_features_p[e_cfg_amo_swap]) << e_dcache_subop_amoswap) + | ((dcache_features_p[e_cfg_amo_fetch_arithmetic]) << e_dcache_subop_amoadd) + | ((dcache_features_p[e_cfg_amo_fetch_logic]) << e_dcache_subop_amoxor) + | ((dcache_features_p[e_cfg_amo_fetch_logic]) << e_dcache_subop_amoand) + | ((dcache_features_p[e_cfg_amo_fetch_logic]) << e_dcache_subop_amoor) + | ((dcache_features_p[e_cfg_amo_fetch_arithmetic]) << e_dcache_subop_amomin) + | ((dcache_features_p[e_cfg_amo_fetch_arithmetic]) << e_dcache_subop_amomax) + | ((dcache_features_p[e_cfg_amo_fetch_arithmetic]) << e_dcache_subop_amominu) + | ((dcache_features_p[e_cfg_amo_fetch_arithmetic]) << e_dcache_subop_amomaxu) + ) + , parameter hit_under_miss_p = dcache_features_p[e_cfg_hit_under_miss] + , parameter sets_p = dcache_sets_p + , parameter assoc_p = dcache_assoc_p + , parameter block_width_p = dcache_block_width_p + , parameter fill_width_p = dcache_fill_width_p + , parameter data_width_p = dcache_data_width_p + , parameter tag_width_p = dcache_tag_width_p + , parameter mshr_p = dcache_mshr_p + , parameter id_width_p = dcache_req_id_width_p + + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + , localparam dcache_pkt_width_lp = $bits(bp_be_dcache_pkt_s) + ) + (input clk_i + , input reset_i + + // Unused except for tracers + , input [cfg_bus_width_lp-1:0] cfg_bus_i + , output logic busy_o + , output logic ordered_o + + // Cycle 0: "Request" + // New D$ packet comes in + , input [dcache_pkt_width_lp-1:0] dcache_pkt_i + , input v_i + + // Cycle 1: "Tag Lookup" + // TLB and PMA information comes in this cycle + , input [ptag_width_p-1:0] ptag_i + , input ptag_v_i + , input ptag_uncached_i + , input ptag_dram_i + , input [data_width_p-1:0] st_data_i + , input flush_i + + // Cycle 2: "Tag Verify" + // Data (or miss result) comes out of the cache + , output logic v_o + , output logic [data_width_p-1:0] data_o + , output logic [reg_addr_width_gp-1:0] rd_addr_o + , output logic [$bits(bp_be_int_tag_e)-1:0] tag_o + , output logic unsigned_o + , output logic int_o + , output logic float_o + , output logic ptw_o + , output logic ret_o + , output logic late_o + + // Cache Engine Interface + // This is considered the "slow path", handling uncached requests + // and fill DMAs. It also handles coherence transactions for + // configurations which support that behavior + , output logic [dcache_req_width_lp-1:0] cache_req_o + , output logic cache_req_v_o + , input cache_req_yumi_i + , input cache_req_lock_i + , output logic [dcache_req_metadata_width_lp-1:0] cache_req_metadata_o + , output logic cache_req_metadata_v_o + , input [id_width_p-1:0] cache_req_id_i + , input cache_req_critical_i + , input cache_req_last_i + // Unused + , input cache_req_credits_full_i + , input cache_req_credits_empty_i + + , input data_mem_pkt_v_i + , input [dcache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , output logic data_mem_pkt_yumi_o + , output logic [block_width_p-1:0] data_mem_o + + , input tag_mem_pkt_v_i + , input [dcache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , output logic tag_mem_pkt_yumi_o + , output logic [dcache_tag_info_width_lp-1:0] tag_mem_o + + , input stat_mem_pkt_v_i + , input [dcache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , output logic stat_mem_pkt_yumi_o + , output logic [dcache_stat_info_width_lp-1:0] stat_mem_o + ); + + `declare_bp_be_dcache_engine_if(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p); + + localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p); + localparam bank_width_lp = block_width_p / assoc_p; + localparam num_words_per_bank_lp = bank_width_lp / data_width_p; + localparam wbuf_data_mask_width_lp = (data_width_p >> 3); + localparam data_mem_mask_width_lp = (bank_width_lp >> 3); + localparam byte_offset_width_lp = `BSG_SAFE_CLOG2(bank_width_lp>>3); + localparam bindex_width_lp = `BSG_SAFE_CLOG2(assoc_p); + localparam sindex_width_lp = `BSG_SAFE_CLOG2(sets_p); + localparam block_size_in_fill_lp = block_width_p / fill_width_p; + localparam fill_size_in_bank_lp = fill_width_p / bank_width_lp; + localparam block_offset_width_lp = (assoc_p > 1) + ? (bindex_width_lp+byte_offset_width_lp) + : byte_offset_width_lp; + + // State machine + enum logic [1:0] {e_ready, e_primary, e_serial} state_n, state_r; + wire is_ready = (state_r == e_ready); + wire is_primary = (state_r == e_primary); + wire is_serial = (state_r == e_serial); + + // Global signals + logic tl_we, tv_we; + logic safe_tl_we, safe_tv_we; + logic v_tl_r, v_tv_r; + logic tag_mem_write_hazard, data_mem_write_hazard, blocking_hazard, nonblocking_hazard, fill_hazard; + logic blocking_req, blocking_sent; + logic nonblocking_req, nonblocking_sent; + logic lrsc_lock; + + wire flush_tv = flush_i | tag_mem_write_hazard | blocking_hazard | nonblocking_hazard | fill_hazard; + wire flush_tl = flush_tv | data_mem_write_hazard; + wire critical_recv = cache_req_critical_i + & (~stat_mem_pkt_v_i | stat_mem_pkt_yumi_o) + & (~tag_mem_pkt_v_i | tag_mem_pkt_yumi_o) + & (~data_mem_pkt_v_i | data_mem_pkt_yumi_o); + wire complete_recv = cache_req_last_i + & (~stat_mem_pkt_v_i | stat_mem_pkt_yumi_o) + & (~tag_mem_pkt_v_i | tag_mem_pkt_yumi_o) + & (~data_mem_pkt_v_i | data_mem_pkt_yumi_o); + + // Snoop signals + logic snoop_v; + logic [block_width_p-1:0] snoop_ld_data; + logic [paddr_width_p-1:0] snoop_paddr; + logic [data_width_p-1:0] snoop_st_data; + logic [2:0][assoc_p-1:0] snoop_hit; + logic [assoc_p-1:0] snoop_bank_sel_one_hot; + bp_be_dcache_decode_s snoop_decode; + logic snoop_uncached; + + ///////////////////////////////////////////////////////////////////////////// + // Decode Stage + ///////////////////////////////////////////////////////////////////////////// + `bp_cast_i(bp_be_dcache_pkt_s, dcache_pkt); + + bp_be_dcache_decode_s decode_lo; + bp_be_dcache_decoder + #(.bp_params_p(bp_params_p), .amo_support_p(amo_support_p)) + pkt_decoder + (.pkt_i(dcache_pkt_i) + ,.decode_o(decode_lo) + ); + + wire [page_offset_width_gp-1:0] offset = dcache_pkt_cast_i.offset; + wire [sindex_width_lp-1:0] index = offset[block_offset_width_lp+:sindex_width_lp]; + wire [bindex_width_lp-1:0] bank = offset[byte_offset_width_lp+:bindex_width_lp]; + + /////////////////////////// + // Tag Mem Storage + /////////////////////////// + `bp_cast_i(bp_be_dcache_tag_mem_pkt_s, tag_mem_pkt); + logic tag_mem_v_li; + logic tag_mem_w_li; + logic [sindex_width_lp-1:0] tag_mem_addr_li; + bp_be_dcache_tag_info_s [assoc_p-1:0] tag_mem_data_li; + bp_be_dcache_tag_info_s [assoc_p-1:0] tag_mem_mask_li; + bp_be_dcache_tag_info_s [assoc_p-1:0] tag_mem_data_lo; + + bsg_mem_1rw_sync_mask_write_bit + #(.width_p(dcache_tag_info_width_lp*assoc_p) + ,.els_p(sets_p) + ,.latch_last_read_p(1) + ) + tag_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(tag_mem_v_li) + ,.w_i(tag_mem_w_li) + ,.addr_i(tag_mem_addr_li) + ,.data_i(tag_mem_data_li) + ,.w_mask_i(tag_mem_mask_li) + ,.data_o(tag_mem_data_lo) + ); + + /////////////////////////// + // Data Mem Storage + /////////////////////////// + localparam data_mem_addr_width_lp = (assoc_p > 1) ? (sindex_width_lp+bindex_width_lp) : sindex_width_lp; + `bp_cast_i(bp_be_dcache_data_mem_pkt_s, data_mem_pkt); + logic [assoc_p-1:0] data_mem_v_li; + logic [assoc_p-1:0] data_mem_w_li; + logic [assoc_p-1:0][data_mem_addr_width_lp-1:0] data_mem_addr_li; + logic [assoc_p-1:0][bank_width_lp-1:0] data_mem_data_li; + logic [assoc_p-1:0][data_mem_mask_width_lp-1:0] data_mem_mask_li; + logic [assoc_p-1:0][bank_width_lp-1:0] data_mem_data_lo; + + for (genvar i = 0; i < assoc_p; i++) + begin : d + bsg_mem_1rw_sync_mask_write_byte + #(.data_width_p(bank_width_lp) + ,.els_p(sets_p*assoc_p) + ,.latch_last_read_p(1) + ) + data_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(data_mem_v_li[i]) + ,.w_i(data_mem_w_li[i]) + ,.addr_i(data_mem_addr_li[i]) + ,.data_i(data_mem_data_li[i]) + ,.write_mask_i(data_mem_mask_li[i]) + ,.data_o(data_mem_data_lo[i]) + ); + end + + ///////////////////////////////////////////////////////////////////////////// + // TL Stage + ///////////////////////////////////////////////////////////////////////////// + bp_be_dcache_decode_s decode_tl_r; + logic [page_offset_width_gp-1:0] offset_tl_r; + + assign safe_tl_we = v_i & ~busy_o; + assign tl_we = safe_tl_we & ~flush_tl; + bsg_dff_reset + #(.width_p(1)) + v_tl_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(tl_we) + ,.data_o(v_tl_r) + ); + + // Save stage information + bsg_dff + #(.width_p(page_offset_width_gp+$bits(bp_be_dcache_decode_s))) + tl_stage_reg + (.clk_i(clk_i) + ,.data_i({offset, decode_lo}) + ,.data_o({offset_tl_r, decode_tl_r}) + ); + + wire [paddr_width_p-1:0] paddr_tl = {ptag_i, offset_tl_r}; + wire [sindex_width_lp-1:0] index_tl = paddr_tl[block_offset_width_lp+:sindex_width_lp]; + wire [bindex_width_lp-1:0] bank_tl = paddr_tl[byte_offset_width_lp+:bindex_width_lp]; + + // Concatenate unused bits from offset if any cache way size is not 4kb + localparam ctag_vbits_lp = page_offset_width_gp - (block_offset_width_lp + sindex_width_lp); + wire [ctag_vbits_lp-1:0] ctag_vbits = offset_tl_r[page_offset_width_gp-1-:`BSG_MAX(ctag_vbits_lp,1)]; + // Causes segfault in Synopsys DC O-2018.06-SP4 + // wire [tag_width_p-1:0] ctag_li = {ptag_i, {ctag_vbits_lp!=0{ctag_vbits}}}; + wire [tag_width_p-1:0] ctag_li = ctag_vbits_lp ? {ptag_i, ctag_vbits} : ptag_i; + wire [ptag_width_p-1:tag_width_p] ptag_high_li = ptag_i >> tag_width_p; + + logic [assoc_p-1:0] way_v_tl, load_hit_tl, store_hit_tl; + for (genvar i = 0; i < assoc_p; i++) begin: tag_comp_tl + wire tag_match_tl = ptag_v_i & ~|ptag_high_li & (ctag_li == tag_mem_data_lo[i].tag); + assign way_v_tl[i] = (tag_mem_data_lo[i].state != e_COH_I); + assign load_hit_tl[i] = tag_match_tl & (tag_mem_data_lo[i].state != e_COH_I); + assign store_hit_tl[i] = tag_match_tl & (tag_mem_data_lo[i].state inside {e_COH_M, e_COH_E}); + end + + logic [assoc_p-1:0] bank_sel_one_hot_tl; + bsg_decode + #(.num_out_p(assoc_p)) + offset_decode + (.i(bank_tl) + ,.o(bank_sel_one_hot_tl) + ); + + wire uncached_tl = ~decode_tl_r.cache_op & (decode_tl_r.uncached_op | ptag_uncached_i); + wire dram_tl = decode_tl_r.cache_op | ptag_dram_i; + wire [data_width_p-1:0] st_data_tl = st_data_i; + + ///////////////////////////////////////////////////////////////////////////// + // TV Stage + ///////////////////////////////////////////////////////////////////////////// + logic uncached_tv_r, snoop_tv_r; + logic [paddr_width_p-1:0] paddr_tv_r; + logic [data_width_p-1:0] st_data_tv_r; + logic [assoc_p-1:0][bank_width_lp-1:0] ld_data_tv_r; + logic [assoc_p-1:0] load_hit_v_tv_r, store_hit_v_tv_r, way_v_tv_r, bank_sel_one_hot_tv_r; + bp_be_dcache_decode_s decode_tv_r; + logic sc_success_tv, sc_fail_tv; + logic fill_restart_tv; + + wire [bindex_width_lp-1:0] paddr_bank_tv = paddr_tv_r[byte_offset_width_lp+:bindex_width_lp]; + wire [sindex_width_lp-1:0] paddr_index_tv = paddr_tv_r[block_offset_width_lp+:sindex_width_lp]; + wire [tag_width_p-1:0] paddr_tag_tv = paddr_tv_r[block_offset_width_lp+sindex_width_lp+:tag_width_p]; + + // cache block ops do not require a ptag + assign safe_tv_we = v_tl_r & (ptag_v_i | decode_tl_r.cache_op); + assign tv_we = safe_tv_we & ~flush_tv; + bsg_dff_reset + #(.width_p(1)) + v_tv_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(tv_we | fill_restart_tv) + ,.data_o(v_tv_r) + ); + + logic [assoc_p-1:0] way_v_tv_n, store_hit_tv_n, load_hit_tv_n; + logic [block_width_p-1:0] ld_data_tv_n; + logic [paddr_width_p-1:0] paddr_tv_n; + logic [data_width_p-1:0] st_data_tv_n; + logic [assoc_p-1:0] bank_sel_one_hot_tv_n; + logic uncached_tv_n; + bp_be_dcache_decode_s decode_tv_n; + bsg_mux + #(.width_p(3*assoc_p+block_width_p+data_width_p+paddr_width_p+assoc_p+1+$bits(bp_be_dcache_decode_s)), .els_p(2)) + tv_snoop_mux + (.data_i({{snoop_hit, snoop_ld_data, snoop_st_data, snoop_paddr, snoop_bank_sel_one_hot + ,snoop_uncached, snoop_decode} + ,{way_v_tl, store_hit_tl, load_hit_tl, data_mem_data_lo, st_data_tl, paddr_tl, bank_sel_one_hot_tl + ,uncached_tl, decode_tl_r} + }) + ,.sel_i(snoop_v) + ,.data_o({way_v_tv_n, store_hit_tv_n, load_hit_tv_n, ld_data_tv_n, st_data_tv_n, paddr_tv_n, bank_sel_one_hot_tv_n + ,uncached_tv_n, decode_tv_n + }) + ); + + wire snoop_tv_n = snoop_v; + bsg_dff + #(.width_p(1+3*assoc_p+paddr_width_p+block_width_p+data_width_p+assoc_p+1+$bits(bp_be_dcache_decode_s))) + tv_stage_reg + (.clk_i(clk_i) + ,.data_i({snoop_tv_n, way_v_tv_n, store_hit_tv_n, load_hit_tv_n, paddr_tv_n, ld_data_tv_n + ,st_data_tv_n, bank_sel_one_hot_tv_n, uncached_tv_n, decode_tv_n}) + ,.data_o({snoop_tv_r, way_v_tv_r, store_hit_v_tv_r, load_hit_v_tv_r, paddr_tv_r, ld_data_tv_r + ,st_data_tv_r, bank_sel_one_hot_tv_r, uncached_tv_r, decode_tv_r}) + ); + + logic [lg_assoc_lp-1:0] store_hit_way_tv; + logic store_hit_tv; + bsg_encode_one_hot + #(.width_p(assoc_p) ,.lo_to_hi_p(1)) + store_hit_index_encoder + (.i(store_hit_v_tv_r) + ,.addr_o(store_hit_way_tv) + ,.v_o(store_hit_tv) + ); + + logic [lg_assoc_lp-1:0] load_hit_way_tv; + logic load_hit_tv; + bsg_encode_one_hot + #(.width_p(assoc_p) ,.lo_to_hi_p(1)) + load_hit_index_encoder + (.i(load_hit_v_tv_r) + ,.addr_o(load_hit_way_tv) + ,.v_o(load_hit_tv) + ); + wire uncached_hit_tv = uncached_tv_r & load_hit_tv; + + logic [assoc_p-1:0] ld_data_way_select_tv; + bsg_adder_one_hot + #(.width_p(assoc_p)) + select_adder + (.a_i(load_hit_v_tv_r) + ,.b_i(bank_sel_one_hot_tv_r) + ,.o(ld_data_way_select_tv) + ); + + logic [bank_width_lp-1:0] ld_data_way_picked; + bsg_mux_one_hot + #(.width_p(bank_width_lp), .els_p(assoc_p)) + ld_data_set_select_mux + (.data_i(ld_data_tv_r) + ,.sel_one_hot_i(ld_data_way_select_tv) + ,.data_o(ld_data_way_picked) + ); + + logic [data_width_p-1:0] ld_data_dword_raw; + wire [`BSG_SAFE_CLOG2(num_words_per_bank_lp)-1:0] ld_data_dword_sel = + paddr_tv_r[3+:`BSG_SAFE_CLOG2(num_words_per_bank_lp)]; + bsg_mux + #(.width_p(data_width_p), .els_p(num_words_per_bank_lp)) + dword_mux + (.data_i(ld_data_way_picked) + ,.sel_i(ld_data_dword_sel) + ,.data_o(ld_data_dword_raw) + ); + + logic [data_width_p-1:0] ld_data_dword_merged; + wire [`BSG_SAFE_CLOG2(data_width_p)-1:0] ld_data_shift_tv = paddr_tv_r << 3; + + wire [data_width_p-1:0] final_data_tv = ld_data_dword_merged >> ld_data_shift_tv; + + // Store no-allocate, so keep going if we have a store miss on a writethrough cache + wire store_miss_tv = (decode_tv_r.store_op | decode_tv_r.lr_op) & ~store_hit_tv & ~sc_fail_tv & ~nonblocking_req & writeback_p; + wire load_miss_tv = decode_tv_r.load_op & ~load_hit_tv & ~sc_fail_tv & ~nonblocking_req; + + wire blocking_miss_tv = blocking_req; + wire nonblocking_miss_tv = nonblocking_req & ~cache_req_yumi_i; + wire engine_miss_tv = cache_req_v_o & ~cache_req_yumi_i; + wire any_miss_tv = blocking_miss_tv | nonblocking_miss_tv | engine_miss_tv; + wire cache_hit_tv = v_tv_r & ~any_miss_tv; + + assign v_o = cache_hit_tv; + assign data_o = sc_success_tv ? 1'b0 : sc_fail_tv ? 1'b1 : final_data_tv; + assign rd_addr_o = decode_tv_r.rd_addr; + assign unsigned_o = !decode_tv_r.signed_op; + assign tag_o = decode_tv_r.tag; + assign int_o = decode_tv_r.int_op; + assign float_o = decode_tv_r.float_op; + assign ptw_o = decode_tv_r.ptw_op; + assign ret_o = decode_tv_r.ret_op; + assign late_o = snoop_tv_r; + + /////////////////////////// + // Stat Mem Storage + /////////////////////////// + `bp_cast_i(bp_be_dcache_stat_mem_pkt_s, stat_mem_pkt); + logic stat_mem_v_li; + logic stat_mem_w_li; + logic [sindex_width_lp-1:0] stat_mem_addr_li; + bp_be_dcache_stat_info_s stat_mem_data_li; + bp_be_dcache_stat_info_s stat_mem_mask_li; + bp_be_dcache_stat_info_s stat_mem_data_lo; + + bsg_mem_1rw_sync_mask_write_bit + #(.width_p(dcache_stat_info_width_lp) + ,.els_p(sets_p) + ,.latch_last_read_p(1) + ) + stat_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(stat_mem_v_li) + ,.w_i(stat_mem_w_li) + ,.addr_i(stat_mem_addr_li) + ,.data_i(stat_mem_data_li) + ,.w_mask_i(stat_mem_mask_li) + ,.data_o(stat_mem_data_lo) + ); + + logic [lg_assoc_lp-1:0] lru_encode; + bsg_lru_pseudo_tree_encode + #(.ways_p(assoc_p)) + lru_encoder + (.lru_i(stat_mem_data_lo.lru) + ,.way_id_o(lru_encode) + ); + + /////////////////////////// + // Write buffer + /////////////////////////// + `declare_bp_be_dcache_wbuf_entry_s(caddr_width_p, assoc_p); + bp_be_dcache_wbuf_entry_s wbuf_entry_in, wbuf_entry_out; + logic wbuf_v_li, wbuf_v_lo, wbuf_force_lo, wbuf_snoop_match_lo, wbuf_yumi_li; + + assign wbuf_v_li = v_tv_r + & decode_tv_r.store_op & store_hit_tv & ~sc_fail_tv & ~uncached_tv_r + & ~any_miss_tv; + + // + // Atomic operations + logic [dword_width_gp-1:0] atomic_reg_data, atomic_mem_data; + logic [dword_width_gp-1:0] atomic_alu_result, atomic_result; + + // Shift data to high bits for operations less than 64-bits + // This allows us to share the arithmetic operators for 32/64 bit atomics + wire [dword_width_gp-1:0] amo32_reg_in = st_data_tv_r[0+:word_width_gp] << word_width_gp; + wire [dword_width_gp-1:0] amo64_reg_in = st_data_tv_r[0+:dword_width_gp]; + assign atomic_reg_data = decode_tv_r.double_op ? amo64_reg_in : amo32_reg_in; + + wire [dword_width_gp-1:0] amo32_mem_in = final_data_tv << word_width_gp; + wire [dword_width_gp-1:0] amo64_mem_in = final_data_tv; + assign atomic_mem_data = decode_tv_r.double_op ? amo64_mem_in : amo32_mem_in; + + // Atomic ALU + always_comb + // This logic was confirmed not to synthesize unsupported operators in + // Synopsys DC O-2018.06-SP4 + unique casez ({amo_support_p[decode_tv_r.amo_subop], decode_tv_r.amo_subop}) + {1'b1, e_dcache_subop_amoand }: atomic_alu_result = atomic_reg_data & atomic_mem_data; + {1'b1, e_dcache_subop_amoor }: atomic_alu_result = atomic_reg_data | atomic_mem_data; + {1'b1, e_dcache_subop_amoxor }: atomic_alu_result = atomic_reg_data ^ atomic_mem_data; + {1'b1, e_dcache_subop_amoadd }: atomic_alu_result = atomic_reg_data + atomic_mem_data; + {1'b1, e_dcache_subop_amomin }: atomic_alu_result = + ($signed(atomic_reg_data) < $signed(atomic_mem_data)) ? atomic_reg_data : atomic_mem_data; + {1'b1, e_dcache_subop_amomax }: atomic_alu_result = + ($signed(atomic_reg_data) > $signed(atomic_mem_data)) ? atomic_reg_data : atomic_mem_data; + {1'b1, e_dcache_subop_amominu}: atomic_alu_result = + (atomic_reg_data < atomic_mem_data) ? atomic_reg_data : atomic_mem_data; + {1'b1, e_dcache_subop_amomaxu}: atomic_alu_result = + (atomic_reg_data > atomic_mem_data) ? atomic_reg_data : atomic_mem_data; + //{1'b1, e_dcache_subop_amoswap} + //{1'b1, e_dcache_subop_sc } + default : atomic_alu_result = atomic_reg_data; + endcase + + wire [dword_width_gp-1:0] amo32_out = atomic_alu_result >> word_width_gp; + wire [dword_width_gp-1:0] amo64_out = atomic_alu_result; + assign atomic_result = decode_tv_r.double_op ? amo64_out : amo32_out; + + logic [3:0][dword_width_gp-1:0] wbuf_data_in; + logic [3:0][wbuf_data_mask_width_lp-1:0] wbuf_data_mem_mask_in; + for (genvar i = 0; i < 4; i++) + begin : wbuf_in + localparam slice_width_lp = 8*(2**i); + logic [slice_width_lp-1:0] slice_data; + + logic [(dword_width_gp/slice_width_lp)-1:0] addr_dec; + bsg_decode + #(.num_out_p(dword_width_gp/slice_width_lp)) + decode + (.i(paddr_tv_r[i+:`BSG_MAX(3-i,1)]) + ,.o(addr_dec) + ); + + bsg_expand_bitmask + #(.in_width_p(dword_width_gp/slice_width_lp), .expand_p(2**i)) + expand + (.i(addr_dec) + ,.o(wbuf_data_mem_mask_in[i]) + ); + + if ((i == 2'b10) || (i == 2'b11)) + begin : atomic + assign slice_data = decode_tv_r.amo_op + ? atomic_result[0+:slice_width_lp] + : st_data_tv_r[0+:slice_width_lp]; + end + else + begin : non_atomic + assign slice_data = st_data_tv_r[0+:slice_width_lp]; + end + + assign wbuf_data_in[i] = {(dword_width_gp/slice_width_lp){slice_data}}; + end + + bsg_mux_one_hot + #(.width_p(dword_width_gp), .els_p(4)) + wbuf_data_in_mux + (.data_i(wbuf_data_in) + ,.sel_one_hot_i({decode_tv_r.double_op, decode_tv_r.word_op, decode_tv_r.half_op, decode_tv_r.byte_op}) + ,.data_o(wbuf_entry_in.data) + ); + + bsg_mux_one_hot + #(.width_p(wbuf_data_mask_width_lp), .els_p(4)) + wbuf_data_mem_mask_in_mux + (.data_i(wbuf_data_mem_mask_in) + ,.sel_one_hot_i({decode_tv_r.double_op, decode_tv_r.word_op, decode_tv_r.half_op, decode_tv_r.byte_op}) + ,.data_o(wbuf_entry_in.mask) + ); + assign wbuf_entry_in.bank_sel = ld_data_way_select_tv | {assoc_p{decode_tv_r.block_op}}; + assign wbuf_entry_in.caddr = paddr_tv_r; + assign wbuf_entry_in.snoop = snoop_tv_r; + + wire [caddr_width_p-1:0] ld_addr_tl = paddr_tl; + bp_be_dcache_wbuf + #(.bp_params_p(bp_params_p) + ,.sets_p(dcache_sets_p) + ,.assoc_p(dcache_assoc_p) + ,.block_width_p(dcache_block_width_p) + ,.fill_width_p(dcache_fill_width_p) + ,.tag_width_p(dcache_tag_width_p) + ) + wbuf + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(wbuf_v_li) + ,.wbuf_entry_i(wbuf_entry_in) + + ,.v_o(wbuf_v_lo) + ,.force_o(wbuf_force_lo) + ,.yumi_i(wbuf_yumi_li) + ,.wbuf_entry_o(wbuf_entry_out) + + ,.tag_mem_pkt_i(tag_mem_pkt_i) + ,.tag_mem_pkt_v_i(tag_mem_pkt_v_i) + ,.data_mem_pkt_i(data_mem_pkt_i) + ,.data_mem_pkt_v_i(data_mem_pkt_v_i) + ,.stat_mem_pkt_i(stat_mem_pkt_i) + ,.stat_mem_pkt_v_i(stat_mem_pkt_v_i) + ,.snoop_match_o(wbuf_snoop_match_lo) + + ,.v_tl_i(v_tl_r) + ,.addr_tl_i(ld_addr_tl) + ,.data_tv_i(ld_data_dword_raw) + ,.data_merged_o(ld_data_dword_merged) + ); + wire [bindex_width_lp-1:0] wbuf_entry_out_bank_offset = wbuf_entry_out.caddr[byte_offset_width_lp+:bindex_width_lp]; + wire [sindex_width_lp-1:0] wbuf_entry_out_index = wbuf_entry_out.caddr[block_offset_width_lp+:sindex_width_lp]; + + ///////////////////////////////////////////////////////////////////////////// + // Slow Path + ///////////////////////////////////////////////////////////////////////////// + localparam bp_cache_req_size_e block_req_size = bp_cache_req_size_e'(`BSG_SAFE_CLOG2(block_width_p/8)); + `bp_cast_o(bp_be_dcache_req_s, cache_req); + `bp_cast_o(bp_be_dcache_req_metadata_s, cache_req_metadata); + + wire load_req = v_tv_r & ~uncached_tv_r & load_miss_tv & ~snoop_tv_r; + wire store_req = v_tv_r & ~uncached_tv_r & store_miss_tv & ~snoop_tv_r; + wire uncached_amo_req = v_tv_r & uncached_tv_r & decode_tv_r.amo_op & decode_tv_r.ret_op & ~snoop_tv_r; + wire uncached_load_req = v_tv_r & uncached_tv_r & ~decode_tv_r.amo_op & decode_tv_r.load_op & ~snoop_tv_r; + wire uncached_store_req = v_tv_r & uncached_tv_r & decode_tv_r.store_op & ~decode_tv_r.ret_op & ~snoop_tv_r; + wire binval_req = v_tv_r & ~uncached_tv_r & decode_tv_r.binval_op & ~decode_tv_r.bclean_op & coherent_p & ~snoop_tv_r; + wire bclean_req = v_tv_r & ~uncached_tv_r & decode_tv_r.bclean_op & (~decode_tv_r.binval_op | !coherent_p) & (store_hit_tv | coherent_p) & ~snoop_tv_r; + wire bflush_req = v_tv_r & ~uncached_tv_r & decode_tv_r.bclean_op & decode_tv_r.binval_op & coherent_p & ~snoop_tv_r; + wire inval_req = v_tv_r & ~uncached_tv_r & decode_tv_r.inval_op & ~decode_tv_r.clean_op & ~snoop_tv_r; + wire clean_req = v_tv_r & ~uncached_tv_r & decode_tv_r.clean_op & ~decode_tv_r.inval_op & ~snoop_tv_r; + wire flush_req = v_tv_r & ~uncached_tv_r & decode_tv_r.inval_op & decode_tv_r.clean_op & ~snoop_tv_r; + wire wt_req = v_tv_r & ~uncached_tv_r & decode_tv_r.store_op & ~sc_fail_tv & !writeback_p & ~snoop_tv_r; + + // Uncached stores and writethrough requests are non-blocking + assign nonblocking_req = (uncached_store_req) + || wt_req + || (binval_req | bclean_req | bflush_req); + assign blocking_req = (load_req | store_req | uncached_amo_req | uncached_load_req) + || (inval_req | clean_req | flush_req); + assign nonblocking_sent = nonblocking_req & cache_req_yumi_i; + assign blocking_sent = blocking_req & cache_req_yumi_i; + + assign cache_req_v_o = is_ready & (blocking_req | nonblocking_req); + + assign blocking_hazard = cache_req_v_o & blocking_req; + assign nonblocking_hazard = nonblocking_req & ~cache_req_yumi_i; + + always_comb + begin + cache_req_cast_o = '0; + cache_req_cast_o.addr = paddr_tv_r; + cache_req_cast_o.data = nonblocking_req ? wbuf_entry_in.data : st_data_tv_r; + cache_req_cast_o.hit = load_hit_tv; + cache_req_cast_o.id = '0; + + // Assigning sizes to cache miss packet + if (load_req | store_req | bclean_req | binval_req | inval_req | clean_req) + begin + cache_req_cast_o.size = block_req_size; + end + else + begin + if (decode_tv_r.block_op) + cache_req_cast_o.size = block_req_size; + else if (decode_tv_r.double_op) + cache_req_cast_o.size = e_size_8B; + else if (decode_tv_r.word_op) + cache_req_cast_o.size = e_size_4B; + else if (decode_tv_r.half_op) + cache_req_cast_o.size = e_size_2B; + else if (decode_tv_r.byte_op) + cache_req_cast_o.size = e_size_1B; + end + + unique casez ({decode_tv_r.amo_op, decode_tv_r.amo_subop}) + {1'b1, e_dcache_subop_lr }: cache_req_cast_o.subop = e_req_amolr; + {1'b1, e_dcache_subop_sc }: cache_req_cast_o.subop = e_req_amosc; + {1'b1, e_dcache_subop_amoswap}: cache_req_cast_o.subop = e_req_amoswap; + {1'b1, e_dcache_subop_amoadd }: cache_req_cast_o.subop = e_req_amoadd; + {1'b1, e_dcache_subop_amoxor }: cache_req_cast_o.subop = e_req_amoxor; + {1'b1, e_dcache_subop_amoand }: cache_req_cast_o.subop = e_req_amoand; + {1'b1, e_dcache_subop_amoor }: cache_req_cast_o.subop = e_req_amoor; + {1'b1, e_dcache_subop_amomin }: cache_req_cast_o.subop = e_req_amomin; + {1'b1, e_dcache_subop_amomax }: cache_req_cast_o.subop = e_req_amomax; + {1'b1, e_dcache_subop_amominu}: cache_req_cast_o.subop = e_req_amominu; + {1'b1, e_dcache_subop_amomaxu}: cache_req_cast_o.subop = e_req_amomaxu; + default: cache_req_cast_o.subop = e_req_store; + endcase + + if (bflush_req) + cache_req_cast_o.msg_type = e_cache_bflush; + else if (bclean_req) + cache_req_cast_o.msg_type = e_cache_bclean; + else if (binval_req) + cache_req_cast_o.msg_type = e_cache_binval; + else if (inval_req) + cache_req_cast_o.msg_type = e_cache_inval; + else if (clean_req) + cache_req_cast_o.msg_type = e_cache_clean; + else if (flush_req) + cache_req_cast_o.msg_type = e_cache_flush; + else if (store_req) + cache_req_cast_o.msg_type = e_miss_store; + else if (load_req) + cache_req_cast_o.msg_type = e_miss_load; + else if (uncached_amo_req) + cache_req_cast_o.msg_type = e_uc_amo; + else if (uncached_store_req) + cache_req_cast_o.msg_type = e_uc_store; + else if (uncached_load_req) + cache_req_cast_o.msg_type = e_uc_load; + else + cache_req_cast_o.msg_type = e_wt_store; + end + + wire cache_req_metadata_v_n = cache_req_yumi_i; + bsg_dff_reset + #(.width_p(1)) + cache_req_v_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(cache_req_metadata_v_n) + ,.data_o(cache_req_metadata_v_o) + ); + + logic metadata_hit_r; + logic [lg_assoc_lp-1:0] metadata_hit_index_r; + logic [assoc_p-1:0] metadata_way_v_r; + bsg_dff + #(.width_p(assoc_p+1+lg_assoc_lp)) + cached_hit_reg + (.clk_i(clk_i) + ,.data_i({way_v_tv_r, load_hit_tv, load_hit_way_tv}) + ,.data_o({metadata_way_v_r, metadata_hit_r, metadata_hit_index_r}) + ); + + logic metadata_invalid_exist; + logic [lg_assoc_lp-1:0] metadata_invalid_way; + bsg_priority_encode + #(.width_p(assoc_p), .lo_to_hi_p(1)) + pe_invalid + (.i(~metadata_way_v_r) + ,.v_o(metadata_invalid_exist) + ,.addr_o(metadata_invalid_way) + ); + + // If there is invalid way, then it takes priority over LRU way. + wire [lg_assoc_lp-1:0] lru_way_li = metadata_invalid_exist ? metadata_invalid_way : lru_encode; + wire [assoc_p-1:0] hit_or_repl_way = metadata_hit_r ? metadata_hit_index_r : lru_way_li; + assign cache_req_metadata_cast_o.hit_or_repl_way = hit_or_repl_way; + assign cache_req_metadata_cast_o.dirty = stat_mem_data_lo.dirty[hit_or_repl_way]; + + assign busy_o = cache_req_lock_i | ~(is_ready | is_primary); + assign ordered_o = ~v_tl_r & ~v_tv_r & cache_req_credits_empty_i; + + ///////////////////////////////////////////////////////////////////////////// + // SRAM Control + ///////////////////////////////////////////////////////////////////////////// + + /////////////////////////// + // Tag Mem Control + /////////////////////////// + wire tag_mem_fast_read = safe_tl_we & ~decode_lo.cache_op; + wire tag_mem_slow_read = tag_mem_pkt_yumi_o & (tag_mem_pkt_cast_i.opcode == e_cache_tag_mem_read); + wire tag_mem_slow_write = tag_mem_pkt_yumi_o & (tag_mem_pkt_cast_i.opcode != e_cache_tag_mem_read); + wire tag_mem_fast_write = (v_tv_r & uncached_tv_r & load_hit_tv & ~snoop_tv_r) + || (v_tv_r & decode_tv_r.binval_op & load_hit_tv & ~snoop_tv_r); + assign tag_mem_write_hazard = tag_mem_fast_write; + + assign tag_mem_v_li = tag_mem_fast_read | tag_mem_slow_read | tag_mem_slow_write | tag_mem_fast_write; + assign tag_mem_w_li = tag_mem_slow_write | tag_mem_fast_write; + assign tag_mem_addr_li = tag_mem_fast_write + ? paddr_index_tv + : tag_mem_fast_read + ? index + : tag_mem_pkt_cast_i.index; + assign tag_mem_pkt_yumi_o = tag_mem_pkt_v_i + & ~lrsc_lock + & ~tag_mem_fast_read + & ~tag_mem_fast_write + & ~wbuf_snoop_match_lo; + + logic [assoc_p-1:0] tag_mem_way_one_hot; + bsg_decode + #(.num_out_p(assoc_p)) + tag_mem_way_decode + (.i(tag_mem_pkt_cast_i.way_id) + ,.o(tag_mem_way_one_hot) + ); + + always_comb + for (integer i = 0; i < assoc_p; i++) + casez ({tag_mem_fast_write, tag_mem_pkt_cast_i.opcode}) + {1'b1, 3'b???}: + begin + tag_mem_data_li[i] = '{state: bp_coh_states_e'('0), tag: '0}; + tag_mem_mask_li[i] = '{state: {$bits(bp_coh_states_e){(load_hit_way_tv == i)}} + ,tag : '0 + }; + end + {1'b0, e_cache_tag_mem_set_tag}: + begin + tag_mem_data_li[i] = '{state: tag_mem_pkt_cast_i.state, tag: tag_mem_pkt_cast_i.tag}; + tag_mem_mask_li[i] = '{state: {$bits(bp_coh_states_e){tag_mem_way_one_hot[i]}} + ,tag : {tag_width_p{tag_mem_way_one_hot[i]}} + }; + end + {1'b0, e_cache_tag_mem_set_state}: + begin + tag_mem_data_li[i] = '{state: tag_mem_pkt_cast_i.state, tag: '0}; + tag_mem_mask_li[i] = '{state: {$bits(bp_coh_states_e){tag_mem_way_one_hot[i]}}, tag: '0}; + end + {1'b0, e_cache_tag_mem_set_inval}: + begin + tag_mem_data_li[i] = '{state: bp_coh_states_e'('0), tag: '0}; + tag_mem_mask_li[i] = '{state: bp_coh_states_e'('1), tag: '0}; + end + default: // e_cache_tag_mem_set_clear + begin + tag_mem_data_li[i] = '{state: bp_coh_states_e'('0), tag: '0}; + tag_mem_mask_li[i] = '{state: bp_coh_states_e'('1), tag: '1}; + end + endcase + + logic [lg_assoc_lp-1:0] tag_mem_pkt_way_r; + bsg_dff + #(.width_p(lg_assoc_lp)) + tag_mem_pkt_way_reg + (.clk_i(clk_i) + ,.data_i(tag_mem_pkt_cast_i.way_id) + ,.data_o(tag_mem_pkt_way_r) + ); + + assign tag_mem_o = tag_mem_data_lo[tag_mem_pkt_way_r]; + + /////////////////////////// + // Data Mem Control + /////////////////////////// + logic [block_size_in_fill_lp-1:0][fill_size_in_bank_lp-1:0] data_mem_pkt_fill_mask_expanded; + bsg_expand_bitmask + #(.in_width_p(block_size_in_fill_lp), .expand_p(fill_size_in_bank_lp)) + fill_mask_expand + (.i(data_mem_pkt_cast_i.fill_index), .o(data_mem_pkt_fill_mask_expanded)); + + logic [assoc_p-1:0] data_mem_write_bank_mask; + wire [`BSG_SAFE_CLOG2(assoc_p)-1:0] write_mask_rot_li = data_mem_pkt_cast_i.way_id; + bsg_rotate_left + #(.width_p(assoc_p)) + write_mask_rotate + (.data_i(data_mem_pkt_fill_mask_expanded) + ,.rot_i(write_mask_rot_li) + ,.o(data_mem_write_bank_mask) + ); + + wire [`BSG_SAFE_CLOG2(fill_width_p)-1:0] write_data_rot_li = data_mem_pkt_cast_i.way_id*bank_width_lp; + logic [fill_width_p-1:0] data_mem_pkt_fill_data_li; + bsg_rotate_left + #(.width_p(fill_width_p)) + write_data_rotate + (.data_i(data_mem_pkt_cast_i.data) + ,.rot_i(write_data_rot_li) + ,.o(data_mem_pkt_fill_data_li) + ); + wire [assoc_p-1:0][bank_width_lp-1:0] data_mem_pkt_data_li = {block_size_in_fill_lp{data_mem_pkt_fill_data_li}}; + + localparam dword_mask_width_lp = `BSG_SAFE_CLOG2(num_words_per_bank_lp); + wire [dword_mask_width_lp-1:0] wbuf_dword_sel = wbuf_entry_out.caddr[3+:dword_mask_width_lp]; + wire [byte_offset_width_lp-1:0] mask_shift = (num_words_per_bank_lp > 1) + ? (wbuf_dword_sel << 3) + : '0; + wire [data_mem_mask_width_lp-1:0] wbuf_data_mem_mask = wbuf_entry_out.mask << mask_shift; + + logic [assoc_p-1:0] data_mem_fast_read, data_mem_fast_write, data_mem_slow_read, data_mem_slow_write; + logic [assoc_p-1:0] data_mem_force_write; + wire data_mem_assoc_read = safe_tl_we & decode_lo.load_op; + for (genvar i = 0; i < assoc_p; i++) + begin : data_mem_lines + assign data_mem_force_write[i] = wbuf_v_lo & wbuf_force_lo & wbuf_entry_out.bank_sel[i]; + assign data_mem_slow_write[i] = data_mem_pkt_yumi_o + & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_write) & data_mem_write_bank_mask[i]; + assign data_mem_slow_read[i] = data_mem_pkt_yumi_o + & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_read); + assign data_mem_fast_read[i] = data_mem_assoc_read; + assign data_mem_fast_write[i] = wbuf_yumi_li & wbuf_entry_out.bank_sel[i]; + + assign data_mem_v_li[i] = data_mem_fast_read[i] + | data_mem_fast_write[i] + | data_mem_slow_read[i] + | data_mem_slow_write[i]; + assign data_mem_w_li[i] = data_mem_fast_write[i] + | data_mem_slow_write[i]; + + assign data_mem_mask_li[i] = data_mem_fast_write[i] + ? wbuf_data_mem_mask + : {data_mem_mask_width_lp{data_mem_write_bank_mask[i]}}; + + wire [bindex_width_lp-1:0] data_mem_pkt_offset = (bindex_width_lp'(i) - data_mem_pkt_cast_i.way_id); + assign data_mem_addr_li[i] = data_mem_fast_write[i] + ? {wbuf_entry_out_index, {(assoc_p > 1){wbuf_entry_out_bank_offset}}} + : data_mem_fast_read[i] + ? {index, {(assoc_p > 1){bank}}} + : {data_mem_pkt_cast_i.index, {(assoc_p > 1){data_mem_pkt_offset}}}; + + assign data_mem_data_li[i] = data_mem_fast_write[i] + ? {num_words_per_bank_lp{wbuf_entry_out.data}} + : data_mem_pkt_data_li[i]; + end + assign wbuf_yumi_li = wbuf_v_lo && (~|{data_mem_fast_read & wbuf_entry_out.bank_sel} || wbuf_force_lo); + // If we didn't read all banks, this could be more efficient + assign data_mem_write_hazard = |{data_mem_fast_read & data_mem_force_write}; + + assign data_mem_pkt_yumi_o = data_mem_pkt_v_i + & ~lrsc_lock + & ~{|data_mem_fast_read & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_read)} + & ~{|data_mem_fast_write & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_read)} + & ~|{data_mem_fast_read & data_mem_write_bank_mask} + & ~|{data_mem_fast_write & data_mem_write_bank_mask} + & ~(v_tl_r & cache_req_critical_i) + & ~(wbuf_snoop_match_lo); + + logic [lg_assoc_lp-1:0] data_mem_pkt_way_r; + bsg_dff + #(.width_p(lg_assoc_lp)) + data_mem_pkt_way_reg + (.clk_i(clk_i) + ,.data_i(data_mem_pkt_cast_i.way_id) + ,.data_o(data_mem_pkt_way_r) + ); + + wire [`BSG_SAFE_CLOG2(block_width_p)-1:0] read_data_rot_li = data_mem_pkt_way_r*bank_width_lp; + bsg_rotate_right + #(.width_p(block_width_p)) + read_data_rotate + (.data_i(data_mem_data_lo) + ,.rot_i(read_data_rot_li) + ,.o(data_mem_o) + ); + + /////////////////////////// + // Stat Mem Control + /////////////////////////// + wire stat_mem_fast_read = (v_tv_r & cache_req_metadata_v_n & ~decode_tv_r.cache_op); + wire stat_mem_fast_write = (v_tv_r & load_hit_tv & ~decode_tv_r.cache_op & ~uncached_tv_r & ~cache_req_metadata_v_n); + wire stat_mem_slow_write = stat_mem_pkt_yumi_o & (stat_mem_pkt_cast_i.opcode != e_cache_stat_mem_read); + wire stat_mem_slow_read = stat_mem_pkt_yumi_o & (stat_mem_pkt_cast_i.opcode == e_cache_stat_mem_read); + assign stat_mem_v_li = stat_mem_fast_read | stat_mem_fast_write + | (stat_mem_slow_write | stat_mem_slow_read); + assign stat_mem_w_li = stat_mem_fast_write | stat_mem_slow_write; + assign stat_mem_addr_li = (stat_mem_fast_write | stat_mem_fast_read) + ? paddr_tv_r[block_offset_width_lp+:sindex_width_lp] + : stat_mem_pkt_cast_i.index; + assign stat_mem_pkt_yumi_o = stat_mem_pkt_v_i + & ~lrsc_lock + & ~stat_mem_fast_read + & ~stat_mem_fast_write + & ~(wbuf_snoop_match_lo & (stat_mem_pkt_cast_i.opcode == e_cache_stat_mem_read)); + + logic [`BSG_SAFE_MINUS(assoc_p, 2):0] lru_decode_data_lo; + logic [`BSG_SAFE_MINUS(assoc_p, 2):0] lru_decode_mask_lo; + wire [lg_assoc_lp-1:0] lru_decode_way_li = + v_tv_r ? decode_tv_r.store_op ? store_hit_way_tv : load_hit_way_tv : stat_mem_pkt_cast_i.way_id; + bsg_lru_pseudo_tree_decode + #(.ways_p(assoc_p)) + lru_decode + (.way_id_i(lru_decode_way_li) + ,.data_o(lru_decode_data_lo) + ,.mask_o(lru_decode_mask_lo) + ); + + logic [assoc_p-1:0] dirty_mask_lo; + if (writeback_p) + begin : tdm + wire dirty_mask_v_li = stat_mem_slow_write || (v_tv_r & decode_tv_r.store_op); + wire [lg_assoc_lp-1:0] dirty_mask_way_li = v_tv_r ? store_hit_way_tv : stat_mem_pkt_cast_i.way_id; + bsg_decode_with_v + #(.num_out_p(assoc_p)) + dirty_mask_decode + (.i(dirty_mask_way_li) + ,.v_i(dirty_mask_v_li) + ,.o(dirty_mask_lo) + ); + end + else + begin : ntdm + // We don't track dirty + // Note: This will synthesize out of stat_mem...unless hardened + assign dirty_mask_lo = '0; + end + + always_comb + case ({v_tv_r, stat_mem_pkt_cast_i.opcode}) + {1'b0, e_cache_stat_mem_set_clear}: + begin + stat_mem_data_li = '0; + stat_mem_mask_li = '{lru: '1, dirty: '1}; + end + {1'b0, e_cache_stat_mem_clear_dirty}: + begin + stat_mem_data_li = '0; + stat_mem_mask_li = '{lru: '0, dirty: dirty_mask_lo}; + end + default : // v_tv_r + begin + stat_mem_data_li = '{lru: lru_decode_data_lo, dirty: '1}; + stat_mem_mask_li = '{lru: lru_decode_mask_lo, dirty: dirty_mask_lo}; + end + endcase + + logic [lg_assoc_lp-1:0] stat_mem_pkt_way_r; + bsg_dff + #(.width_p(lg_assoc_lp)) + stat_mem_pkt_way_reg + (.clk_i(clk_i) + ,.data_i(stat_mem_pkt_cast_i.way_id) + ,.data_o(stat_mem_pkt_way_r) + ); + + assign stat_mem_o = stat_mem_data_lo; + + ///////////////////////////////////////////////////////////////////////////// + // Load Reservation + ///////////////////////////////////////////////////////////////////////////// + if (amo_support_p[e_dcache_subop_lr] && amo_support_p[e_dcache_subop_sc]) + begin : l1_lrsc + logic [sindex_width_lp-1:0] load_reserved_index_r; + logic [tag_width_p-1:0] load_reserved_tag_r; + logic load_reserved_v_r; + + // Set reservation on successful LR, without a cache miss or upgrade request + wire set_reservation = v_tv_r & decode_tv_r.lr_op & store_hit_tv; + // All SCs clear the reservation (regardless of success) + // Invalidates from other harts which match the reservation address clear the reservation + // Also invalidate on trap + wire clear_reservation = (v_tv_r & decode_tv_r.sc_op) + || (tag_mem_pkt_yumi_o + & load_reserved_v_r + & (tag_mem_pkt_cast_i.index == load_reserved_index_r) + & (tag_mem_pkt_cast_i.tag == load_reserved_tag_r) + ); + bsg_dff_reset_set_clear + #(.width_p(1), .clear_over_set_p(1)) + load_reserved_v_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.set_i(set_reservation) + ,.clear_i(clear_reservation) + ,.data_o(load_reserved_v_r) + ); + + bsg_dff_en + #(.width_p(tag_width_p+sindex_width_lp)) + load_reserved_addr + (.clk_i(clk_i) + ,.en_i(set_reservation) + ,.data_i({paddr_tag_tv, paddr_index_tv}) + ,.data_o({load_reserved_tag_r, load_reserved_index_r}) + ); + + wire load_reservation_match_tv = load_reserved_v_r + & (load_reserved_index_r == paddr_index_tv) + & (load_reserved_tag_r == paddr_tag_tv); + + // Succeed if the address matches and we have a store hit + assign sc_success_tv = v_tv_r & decode_tv_r.sc_op & store_hit_tv & load_reservation_match_tv; + // Fail if we have a store conditional without success + assign sc_fail_tv = v_tv_r & decode_tv_r.sc_op & ~sc_success_tv; + + localparam lock_max_cnt_lp = 15; // Should be sufficent to guarantee progress + logic [`BSG_WIDTH(lock_max_cnt_lp)-1:0] lrsc_lock_cnt; + wire lrsc_lock_clr = sc_success_tv; + wire lrsc_lock_up = sc_fail_tv | lrsc_lock; + bsg_counter_clear_up + #(.max_val_p(lock_max_cnt_lp), .init_val_p(0), .disable_overflow_warning_p(1)) + lrsc_lock_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(lrsc_lock_clr) + ,.up_i(lrsc_lock_up) + ,.count_o(lrsc_lock_cnt) + ); + assign lrsc_lock = (lrsc_lock_cnt != '0); + end + else + begin : no_l1_lrsc + assign sc_fail_tv = '0; + assign sc_success_tv = '0; + assign lrsc_lock = '0; + end + + ///////////////////////////////////////////////////////////////////////////// + // State Machine + ///////////////////////////////////////////////////////////////////////////// + always_comb + if (!is_ready & complete_recv) + state_n = e_ready; + else if (is_ready & blocking_sent) + state_n = (!hit_under_miss_p | decode_tv_r.cache_op) ? e_serial : e_primary; + else if (is_primary & v_tv_r & any_miss_tv) + state_n = e_serial; + else + state_n = state_r; + + assign fill_restart_tv = critical_recv; + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_ready; + else + state_r <= state_n; + + ///////////////////////////////////////////////////////////////////////////// + // MSHR + ///////////////////////////////////////////////////////////////////////////// + logic fill_uncached_r; + logic [paddr_width_p-1:0] fill_paddr_r; + logic [dword_width_gp-1:0] fill_st_data_r; + bp_be_dcache_decode_s fill_decode_r; + bsg_dff_en + #(.width_p(1+dword_width_gp+paddr_width_p+$bits(bp_be_dcache_decode_s))) + mshr_reg + (.clk_i(clk_i) + ,.en_i(blocking_sent) + ,.data_i({uncached_tv_r, st_data_tv_r, paddr_tv_r, decode_tv_r}) + ,.data_o({fill_uncached_r, fill_st_data_r, fill_paddr_r, fill_decode_r}) + ); + + if (hit_under_miss_p) + begin : hum + wire fill_v = data_mem_pkt_v_i & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_write); + wire fill_recv = fill_v + & (~stat_mem_pkt_v_i | stat_mem_pkt_yumi_o) + & (~tag_mem_pkt_v_i | tag_mem_pkt_yumi_o) + & (~data_mem_pkt_v_i | data_mem_pkt_yumi_o); + wire [sindex_width_lp-1:0] fill_index = fill_paddr_r[block_offset_width_lp+:sindex_width_lp]; + + logic [assoc_p-1:0] fill_hit_r; + logic [assoc_p-1:0] fill_bank_mask_r; + wire [assoc_p-1:0] fill_bank_mask_n = fill_v + ? (fill_bank_mask_r & ~data_mem_pkt_fill_mask_expanded) + : '1; + wire [assoc_p-1:0] fill_hit_n = fill_v + ? (1'b1 << data_mem_pkt_cast_i.way_id) + : '1; + bsg_dff_reset_en + #(.width_p(2*assoc_p)) + fill_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(fill_recv | blocking_sent) + ,.data_i({fill_bank_mask_n, fill_hit_n}) + ,.data_o({fill_bank_mask_r, fill_hit_r}) + ); + + assign snoop_v = fill_restart_tv; + assign fill_hazard = !is_ready & v_tl_r + & |(fill_index == index_tl) + & |(fill_hit_r & load_hit_tl) + & |(fill_bank_mask_r & bank_sel_one_hot_tl); + end + else + begin : nhum + assign snoop_v = !is_ready | blocking_sent; + assign fill_hazard = '0; + end + + ///////////////////////////////////////////////////////////////////////////// + // Snoop Logic + ///////////////////////////////////////////////////////////////////////////// + wire [assoc_p-1:0] pseudo_hit = + (data_mem_pkt_v_i << data_mem_pkt_cast_i.way_id) | (tag_mem_pkt_v_i << tag_mem_pkt_cast_i.way_id); + assign snoop_hit = {3{pseudo_hit}}; + assign snoop_ld_data = data_mem_data_li; + assign snoop_paddr = fill_paddr_r; + assign snoop_st_data = fill_st_data_r; + assign snoop_decode = fill_decode_r; + assign snoop_uncached = fill_uncached_r; + + wire [bindex_width_lp-1:0] snoop_bank = snoop_paddr[byte_offset_width_lp+:bindex_width_lp]; + bsg_decode + #(.num_out_p(assoc_p)) + snoop_offset_decode + (.i(snoop_bank) + ,.o(snoop_bank_sel_one_hot) + ); + + // synopsys translate_off + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + + always_ff @(negedge clk_i) + begin + assert(reset_i !== '0 || ~v_tv_r || $countones(load_hit_tl) <= 1) + else $error("multiple hit: %b. id = %0d. addr = %H", load_hit_tl, cfg_bus_cast_i.dcache_id, ptag_i); + end + // synopsys translate_on + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_dcache_decoder.sv b/designs/black-parrot/src/bp/bp_be_dcache_decoder.sv new file mode 100644 index 0000000..5bda961 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_dcache_decoder.sv @@ -0,0 +1,137 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_dcache_decoder + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + , parameter amo_support_p = 0 + + , localparam dcache_pkt_width_lp = $bits(bp_be_dcache_pkt_s) + , localparam dcache_decode_width_lp = $bits(bp_be_dcache_decode_s) + ) + (input [dcache_pkt_width_lp-1:0] pkt_i + , output logic [dcache_decode_width_lp-1:0] decode_o + ); + + `bp_cast_i(bp_be_dcache_pkt_s, pkt); + `bp_cast_o(bp_be_dcache_decode_s, decode); + + always_comb begin + decode_cast_o = '0; + + // Atomic op decoding + decode_cast_o.lr_op = pkt_cast_i.opcode inside {e_dcache_op_lrw, e_dcache_op_lrd}; + decode_cast_o.sc_op = pkt_cast_i.opcode inside {e_dcache_op_scw, e_dcache_op_scd}; + + // Atomic subop decoding + unique casez (pkt_cast_i.opcode) + e_dcache_op_lrw, e_dcache_op_lrd : decode_cast_o.amo_subop = e_dcache_subop_lr; + e_dcache_op_scw, e_dcache_op_scd : decode_cast_o.amo_subop = e_dcache_subop_sc; + e_dcache_op_amoswapw, e_dcache_op_amoswapd: decode_cast_o.amo_subop = e_dcache_subop_amoswap; + e_dcache_op_amoaddw, e_dcache_op_amoaddd : decode_cast_o.amo_subop = e_dcache_subop_amoadd; + e_dcache_op_amoxorw, e_dcache_op_amoxord : decode_cast_o.amo_subop = e_dcache_subop_amoxor; + e_dcache_op_amoandw, e_dcache_op_amoandd : decode_cast_o.amo_subop = e_dcache_subop_amoand; + e_dcache_op_amoorw, e_dcache_op_amoord : decode_cast_o.amo_subop = e_dcache_subop_amoor; + e_dcache_op_amominw, e_dcache_op_amomind : decode_cast_o.amo_subop = e_dcache_subop_amomin; + e_dcache_op_amomaxw, e_dcache_op_amomaxd : decode_cast_o.amo_subop = e_dcache_subop_amomax; + e_dcache_op_amominuw, e_dcache_op_amominud: decode_cast_o.amo_subop = e_dcache_subop_amominu; + e_dcache_op_amomaxuw, e_dcache_op_amomaxud: decode_cast_o.amo_subop = e_dcache_subop_amomaxu; + default : decode_cast_o.amo_subop = e_dcache_subop_none; + endcase + + decode_cast_o.amo_op = (decode_cast_o.amo_subop != e_dcache_subop_none); + decode_cast_o.binval_op = pkt_cast_i.opcode inside {e_dcache_op_binval, e_dcache_op_bflush}; + decode_cast_o.bclean_op = pkt_cast_i.opcode inside {e_dcache_op_bclean, e_dcache_op_bflush}; + decode_cast_o.bzero_op = pkt_cast_i.opcode inside {e_dcache_op_bzero}; + + decode_cast_o.inval_op = pkt_cast_i.opcode inside {e_dcache_op_inval, e_dcache_op_flush}; + decode_cast_o.clean_op = pkt_cast_i.opcode inside {e_dcache_op_clean, e_dcache_op_flush}; + + decode_cast_o.uncached_op = + ((!amo_support_p[e_dcache_subop_lr]) && (decode_cast_o.lr_op)) + || ((!amo_support_p[e_dcache_subop_sc]) && (decode_cast_o.sc_op)) + || ((!amo_support_p[e_dcache_subop_amoswap]) && decode_cast_o.amo_subop == e_dcache_subop_amoswap) + || ((!amo_support_p[e_dcache_subop_amoadd]) && decode_cast_o.amo_subop == e_dcache_subop_amoadd) + || ((!amo_support_p[e_dcache_subop_amomin]) && decode_cast_o.amo_subop == e_dcache_subop_amomin) + || ((!amo_support_p[e_dcache_subop_amomax]) && decode_cast_o.amo_subop == e_dcache_subop_amomax) + || ((!amo_support_p[e_dcache_subop_amominu]) && decode_cast_o.amo_subop == e_dcache_subop_amominu) + || ((!amo_support_p[e_dcache_subop_amomaxu]) && decode_cast_o.amo_subop == e_dcache_subop_amomaxu) + || ((!amo_support_p[e_dcache_subop_amoxor]) && decode_cast_o.amo_subop == e_dcache_subop_amoxor) + || ((!amo_support_p[e_dcache_subop_amoand]) && decode_cast_o.amo_subop == e_dcache_subop_amoand) + || ((!amo_support_p[e_dcache_subop_amoor]) && decode_cast_o.amo_subop == e_dcache_subop_amoor); + + decode_cast_o.load_op = (decode_cast_o.amo_op | decode_cast_o.lr_op) || pkt_cast_i.opcode inside + {e_dcache_op_flw, e_dcache_op_fld + ,e_dcache_op_ld, e_dcache_op_lw, e_dcache_op_lh, e_dcache_op_lb + ,e_dcache_op_lwu, e_dcache_op_lhu, e_dcache_op_lbu + ,e_dcache_op_ptw + }; + + decode_cast_o.store_op = (decode_cast_o.amo_op & ~decode_cast_o.lr_op) || pkt_cast_i.opcode inside + {e_dcache_op_sd, e_dcache_op_sw, e_dcache_op_sh, e_dcache_op_sb + ,e_dcache_op_fsw, e_dcache_op_fsd + ,e_dcache_op_bzero + }; + + // Type decoding + decode_cast_o.int_op = pkt_cast_i.opcode inside + {e_dcache_op_lb, e_dcache_op_lh, e_dcache_op_lw, e_dcache_op_ld + ,e_dcache_op_lbu, e_dcache_op_lhu, e_dcache_op_lwu + ,e_dcache_op_sb, e_dcache_op_sh, e_dcache_op_sw, e_dcache_op_sd + ,e_dcache_op_lrw, e_dcache_op_scw, e_dcache_op_lrd, e_dcache_op_scd + ,e_dcache_op_amoswapw, e_dcache_op_amoaddw, e_dcache_op_amoxorw + ,e_dcache_op_amoandw, e_dcache_op_amoorw, e_dcache_op_amominw + ,e_dcache_op_amomaxw, e_dcache_op_amominuw, e_dcache_op_amomaxuw + ,e_dcache_op_amoswapd, e_dcache_op_amoaddd, e_dcache_op_amoxord + ,e_dcache_op_amoandd, e_dcache_op_amoord, e_dcache_op_amomind + ,e_dcache_op_amomaxd, e_dcache_op_amominud, e_dcache_op_amomaxud + }; + decode_cast_o.float_op = pkt_cast_i.opcode inside + {e_dcache_op_flw, e_dcache_op_fld, e_dcache_op_fsw, e_dcache_op_fsd}; + decode_cast_o.ptw_op = pkt_cast_i.opcode inside {e_dcache_op_ptw}; + + // Size decoding + unique case (pkt_cast_i.opcode) + e_dcache_op_inval, e_dcache_op_clean, e_dcache_op_flush: + decode_cast_o.cache_op = 1'b1; + e_dcache_op_bzero, e_dcache_op_binval, e_dcache_op_bclean, e_dcache_op_bflush: + decode_cast_o.block_op = 1'b1; + e_dcache_op_lb, e_dcache_op_lbu, e_dcache_op_sb: decode_cast_o.byte_op = 1'b1; + e_dcache_op_lh, e_dcache_op_lhu, e_dcache_op_sh: decode_cast_o.half_op = 1'b1; + e_dcache_op_amoswapw, e_dcache_op_amoaddw, e_dcache_op_amoxorw + ,e_dcache_op_amoandw, e_dcache_op_amoorw, e_dcache_op_amominw + ,e_dcache_op_amomaxw, e_dcache_op_amominuw, e_dcache_op_amomaxuw + ,e_dcache_op_lw, e_dcache_op_lwu, e_dcache_op_sw + ,e_dcache_op_flw, e_dcache_op_fsw + ,e_dcache_op_lrw, e_dcache_op_scw: decode_cast_o.word_op = 1'b1; + default: decode_cast_o.double_op = 1'b1; + endcase + + // Signed op decoding + decode_cast_o.signed_op = (decode_cast_o.byte_op | decode_cast_o.half_op | decode_cast_o.word_op) + && !(pkt_cast_i.opcode inside {e_dcache_op_lwu, e_dcache_op_lhu, e_dcache_op_lbu}); + + // The destination register of the cache request + decode_cast_o.rd_addr = pkt_cast_i.rd_addr; + + if (decode_cast_o.int_op & decode_cast_o.byte_op) + decode_cast_o.tag = e_int_byte; + else if (decode_cast_o.int_op & decode_cast_o.half_op) + decode_cast_o.tag = e_int_hword; + else if (decode_cast_o.int_op & decode_cast_o.word_op) + decode_cast_o.tag = e_int_word; + else if (decode_cast_o.float_op & decode_cast_o.word_op) + decode_cast_o.tag = e_fp_sp; + + // Return + decode_cast_o.ret_op = decode_cast_o.load_op + & (decode_cast_o.ptw_op + | decode_cast_o.float_op + | (decode_cast_o.int_op && (decode_cast_o.rd_addr != '0)) + ); + end + +endmodule diff --git a/designs/black-parrot/src/bp/bp_be_dcache_defines.svh b/designs/black-parrot/src/bp/bp_be_dcache_defines.svh new file mode 100644 index 0000000..a69ce52 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_dcache_defines.svh @@ -0,0 +1,25 @@ + +`ifndef BP_BE_DCACHE_DEFINES_SVH +`define BP_BE_DCACHE_DEFINES_SVH + + `define declare_bp_be_dcache_wbuf_entry_s(caddr_width_mp, ways_mp) \ + typedef struct packed \ + { \ + logic snoop; \ + logic [ways_mp-1:0] bank_sel; \ + logic [(dword_width_gp>>3)-1:0] mask; \ + logic [dword_width_gp-1:0] data; \ + logic [caddr_width_mp-1:0] caddr; \ + } bp_be_dcache_wbuf_entry_s + + `define bp_be_dcache_wbuf_entry_width(caddr_width_mp, ways_mp) \ + (1+ways_mp+(dword_width_gp>>3)+dword_width_gp+caddr_width_mp) + + `define declare_bp_be_dcache_engine_if(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp) \ + `declare_bp_cache_engine_generic_if(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp, be_dcache) + + `define declare_bp_be_dcache_engine_if_widths(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp) \ + `declare_bp_cache_engine_generic_if_widths(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp, dcache) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_be_dcache_pkgdef.svh b/designs/black-parrot/src/bp/bp_be_dcache_pkgdef.svh new file mode 100644 index 0000000..e5fd6f4 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_dcache_pkgdef.svh @@ -0,0 +1,64 @@ + +`ifndef BP_BE_DCACHE_PKGDEF_SVH +`define BP_BE_DCACHE_PKGDEF_SVH + + typedef enum logic [3:0] + { + e_dcache_subop_none + ,e_dcache_subop_lr + ,e_dcache_subop_sc + ,e_dcache_subop_amoswap + ,e_dcache_subop_amoadd + ,e_dcache_subop_amoxor + ,e_dcache_subop_amoand + ,e_dcache_subop_amoor + ,e_dcache_subop_amomin + ,e_dcache_subop_amomax + ,e_dcache_subop_amominu + ,e_dcache_subop_amomaxu + } bp_be_amo_subop_e; + + typedef struct packed + { + logic [$bits(bp_be_int_tag_e)-1:0] tag; + logic load_op; + logic ret_op; + logic store_op; + logic signed_op; + logic float_op; + logic int_op; + logic ptw_op; + logic cache_op; + logic block_op; + logic double_op; + logic word_op; + logic half_op; + logic byte_op; + logic uncached_op; + logic lr_op; + logic sc_op; + logic amo_op; + logic clean_op; + logic inval_op; + logic bclean_op; + logic binval_op; + logic bzero_op; + bp_be_amo_subop_e amo_subop; + logic [reg_addr_width_gp-1:0] rd_addr; + } bp_be_dcache_decode_s; + + typedef struct packed + { + bp_be_dcache_decode_s decode; + logic uncached; + } bp_be_dcache_req_payload_s; + + typedef struct packed + { + logic [reg_addr_width_gp-1:0] rd_addr; + bp_be_dcache_fu_op_e opcode; + logic [page_offset_width_gp-1:0] offset; + } bp_be_dcache_pkt_s; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_be_dcache_wbuf.sv b/designs/black-parrot/src/bp/bp_be_dcache_wbuf.sv new file mode 100644 index 0000000..198c561 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_dcache_wbuf.sv @@ -0,0 +1,227 @@ +/** + * Name: + * bp_be_dcache_wbuf.sv + * + * Description: + * Data cache write buffer. + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_dcache_wbuf + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + , parameter sets_p = dcache_sets_p + , parameter assoc_p = dcache_assoc_p + , parameter block_width_p = dcache_block_width_p + , parameter fill_width_p = dcache_fill_width_p + , parameter tag_width_p = dcache_tag_width_p + , parameter id_width_p = dcache_req_id_width_p + + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, dword_width_gp, block_width_p, fill_width_p, id_width_p) + + , localparam wbuf_entry_width_lp=`bp_be_dcache_wbuf_entry_width(caddr_width_p, dcache_assoc_p) + ) + (input clk_i + , input reset_i + + , input [wbuf_entry_width_lp-1:0] wbuf_entry_i + , input v_i + + , output logic [wbuf_entry_width_lp-1:0] wbuf_entry_o + , output logic v_o + , output logic force_o + , input yumi_i + + , input [dcache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , input data_mem_pkt_v_i + , input [dcache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , input tag_mem_pkt_v_i + , input [dcache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , input stat_mem_pkt_v_i + , output logic snoop_match_o + + , input v_tl_i + , input [caddr_width_p-1:0] addr_tl_i + , input [dword_width_gp-1:0] data_tv_i + , output logic [dword_width_gp-1:0] data_merged_o + ); + + `declare_bp_be_dcache_wbuf_entry_s(caddr_width_p, dcache_assoc_p); + `declare_bp_be_dcache_engine_if(paddr_width_p, tag_width_p, sets_p, assoc_p, dword_width_gp, block_width_p, fill_width_p, id_width_p); + `bp_cast_i(bp_be_dcache_wbuf_entry_s, wbuf_entry); + `bp_cast_i(bp_be_dcache_data_mem_pkt_s, data_mem_pkt); + `bp_cast_i(bp_be_dcache_tag_mem_pkt_s, tag_mem_pkt); + `bp_cast_i(bp_be_dcache_stat_mem_pkt_s, stat_mem_pkt); + + localparam data_mask_width_lp = dword_width_gp >> 3; + localparam byte_offset_width_lp = `BSG_SAFE_CLOG2(data_mask_width_lp); + localparam bindex_width_lp = `BSG_SAFE_CLOG2(assoc_p); + localparam sindex_width_lp = `BSG_SAFE_CLOG2(sets_p); + localparam block_offset_width_lp = (assoc_p > 1) + ? (bindex_width_lp+byte_offset_width_lp) + : byte_offset_width_lp; + + logic [1:0] num_els_r; + bsg_counter_up_down + #(.max_val_p(2), .init_val_p(0), .max_step_p(1)) + num_els_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.up_i(v_i) + ,.down_i(yumi_i) + ,.count_o(num_els_r) + ); + + logic el0_valid, el1_valid; + logic el0_enable, el1_enable; + logic mux0_sel, mux1_sel; + always_comb begin + unique case (num_els_r) + 2'd0: begin + v_o = v_i; + el0_valid = 1'b0; + el1_valid = 1'b0; + el0_enable = 1'b0; + el1_enable = v_i & ~yumi_i; + mux0_sel = 1'b0; + mux1_sel = 1'b0; + end + 2'd1: begin + v_o = 1'b1; + el0_valid = 1'b0; + el1_valid = 1'b1; + el0_enable = v_i & ~yumi_i; + el1_enable = v_i & yumi_i; + mux0_sel = 1'b0; + mux1_sel = 1'b1; + end + //2'd2 + default : begin + v_o = 1'b1; + el0_valid = 1'b1; + el1_valid = 1'b1; + el0_enable = v_i & yumi_i; + el1_enable = yumi_i; + mux0_sel = 1'b1; + mux1_sel = 1'b1; + end + endcase + end + + assign force_o = v_i & (num_els_r == 2'd2); + + // wbuf queue + // + bp_be_dcache_wbuf_entry_s wbuf_entry_el0_n, wbuf_entry_el0_r; + bp_be_dcache_wbuf_entry_s wbuf_entry_el1_n, wbuf_entry_el1_r; + + assign wbuf_entry_el0_n = wbuf_entry_cast_i; + bsg_dff_en + #(.width_p($bits(bp_be_dcache_wbuf_entry_s))) + wbuf_entry0_reg + (.clk_i(clk_i) + ,.en_i(el0_enable) + ,.data_i(wbuf_entry_el0_n) + ,.data_o(wbuf_entry_el0_r) + ); + + assign wbuf_entry_el1_n = mux0_sel ? wbuf_entry_el0_r : wbuf_entry_cast_i; + bsg_dff_en + #(.width_p($bits(bp_be_dcache_wbuf_entry_s))) + wbuf_entry1_reg + (.clk_i(clk_i) + ,.en_i(el1_enable) + ,.data_i(wbuf_entry_el1_n) + ,.data_o(wbuf_entry_el1_r) + ); + assign wbuf_entry_o = mux1_sel ? wbuf_entry_el1_r : wbuf_entry_cast_i; + + // bypassing + // + localparam word_addr_width_lp = caddr_width_p-byte_offset_width_lp; + wire [word_addr_width_lp-1:0] bypass_word_addr = addr_tl_i[byte_offset_width_lp+:word_addr_width_lp]; + wire tag_hit0_n = bypass_word_addr == wbuf_entry_el0_r.caddr[byte_offset_width_lp+:word_addr_width_lp]; + wire tag_hit1_n = bypass_word_addr == wbuf_entry_el1_r.caddr[byte_offset_width_lp+:word_addr_width_lp]; + wire tag_hit2_n = bypass_word_addr == wbuf_entry_cast_i.caddr[byte_offset_width_lp+:word_addr_width_lp]; + + wire tag_hit0 = v_tl_i & tag_hit0_n & el0_valid; + wire tag_hit1 = v_tl_i & tag_hit1_n & el1_valid; + wire tag_hit2 = v_tl_i & tag_hit2_n & v_i; + + wire [data_mask_width_lp-1:0] tag_hit0x4 = {data_mask_width_lp{tag_hit0}}; + wire [data_mask_width_lp-1:0] tag_hit1x4 = {data_mask_width_lp{tag_hit1}}; + wire [data_mask_width_lp-1:0] tag_hit2x4 = {data_mask_width_lp{tag_hit2}}; + + logic [dword_width_gp-1:0] el0or1_data; + bsg_mux_segmented + #(.segments_p(data_mask_width_lp), .segment_width_p(byte_width_gp)) + mux_segmented_merge0 + (.data0_i(wbuf_entry_el1_r.data) + ,.data1_i(wbuf_entry_el0_r.data) + ,.sel_i(tag_hit0x4 & wbuf_entry_el0_r.mask) + ,.data_o(el0or1_data) + ); + + logic [dword_width_gp-1:0] bypass_data_n; + bsg_mux_segmented + #(.segments_p(data_mask_width_lp), .segment_width_p(byte_width_gp)) + mux_segmented_merge1 + (.data0_i(el0or1_data) + ,.data1_i(wbuf_entry_cast_i.data) + ,.sel_i(tag_hit2x4 & wbuf_entry_cast_i.mask) + ,.data_o(bypass_data_n) + ); + + wire [data_mask_width_lp-1:0] bypass_mask_n = (tag_hit0x4 & wbuf_entry_el0_r.mask) + | (tag_hit1x4 & wbuf_entry_el1_r.mask) + | (tag_hit2x4 & wbuf_entry_cast_i.mask); + + logic [dword_width_gp-1:0] bypass_data_r; + logic [data_mask_width_lp-1:0] bypass_mask_r; + bsg_dff_reset + #(.width_p(dword_width_gp+data_mask_width_lp)) + bypass_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i({bypass_mask_n, bypass_data_n}) + ,.data_o({bypass_mask_r, bypass_data_r}) + ); + + logic [dword_width_gp-1:0] bypass_data_masked; + bsg_mux_segmented + #(.segments_p(data_mask_width_lp), .segment_width_p(byte_width_gp)) + bypass_mux_segmented + (.data0_i(data_tv_i) + ,.data1_i(bypass_data_r) + ,.sel_i(bypass_mask_r) + ,.data_o(data_merged_o) + ); + + // This is slightly pessimistic because it blocks all ways. However, putting the SRAM read + // and tag match on the slow path seems like a bad idea. + wire snoop_tag_match = v_tl_i & tag_mem_pkt_v_i + & (addr_tl_i[block_offset_width_lp+:sindex_width_lp] == tag_mem_pkt_cast_i.index); + wire snoop_stat_match = v_tl_i & stat_mem_pkt_v_i + & (addr_tl_i[block_offset_width_lp+:sindex_width_lp] == stat_mem_pkt_cast_i.index); + wire snoop_el0_match = el0_valid & ~wbuf_entry_cast_i.snoop & data_mem_pkt_v_i + & (wbuf_entry_el0_r.caddr[block_offset_width_lp+:sindex_width_lp] == data_mem_pkt_cast_i.index); + wire snoop_el1_match = el1_valid & ~wbuf_entry_el1_r.snoop & data_mem_pkt_v_i + & (wbuf_entry_el1_r.caddr[block_offset_width_lp+:sindex_width_lp] == data_mem_pkt_cast_i.index); + wire snoop_el2_match = v_i & ~wbuf_entry_cast_i.snoop & data_mem_pkt_v_i + & (wbuf_entry_cast_i.caddr[block_offset_width_lp+:sindex_width_lp] == data_mem_pkt_cast_i.index); + + assign snoop_match_o = snoop_tag_match | snoop_stat_match | snoop_el0_match | snoop_el1_match | snoop_el2_match; + + // synopsys translate_off + always_ff @(negedge clk_i) begin + assert(reset_i !== '0 || num_els_r < 2'd3) else $error("Write buffer overflow\n"); + end + // synopsys translate_on + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_defines.svh b/designs/black-parrot/src/bp/bp_be_defines.svh new file mode 100644 index 0000000..22becd1 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_defines.svh @@ -0,0 +1,285 @@ +/** + * + * bp_be_defines.svh + * + */ + +`ifndef BP_BE_DEFINES_SVH +`define BP_BE_DEFINES_SVH + + `include "bsg_defines.sv" + `include "bp_common_core_if.svh" + `include "bp_be_dcache_defines.svh" + `include "HardFloat_consts.vi" + `include "HardFloat_specialize.vi" + + /* + * Clients need only use this macro to declare all parameterized structs for FE<->BE interface. + */ + `define declare_bp_be_if(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + \ + typedef struct packed \ + { \ + logic irs1_v; \ + logic irs2_v; \ + logic frs1_v; \ + logic frs2_v; \ + logic frs3_v; \ + rv64_instr_s instr; \ + logic [issue_ptr_mp-1:0] size; \ + } bp_be_preissue_pkt_s; \ + \ + typedef struct packed \ + { \ + logic v; \ + logic fetch; \ + logic itlb_miss; \ + logic instr_access_fault; \ + logic instr_page_fault; \ + logic icache_miss; \ + logic illegal_instr; \ + logic ecall_m; \ + logic ecall_s; \ + logic ecall_u; \ + logic ebreak; \ + logic dbreak; \ + logic dret; \ + logic mret; \ + logic sret; \ + logic wfi; \ + logic sfence_vma; \ + logic fencei; \ + logic csrw; \ + \ + logic [vaddr_width_mp-1:0] pc; \ + rv64_instr_s instr; \ + logic [fetch_ptr_mp-1:0] count; \ + logic [issue_ptr_mp-1:0] size; \ + bp_be_decode_s decode; \ + logic [dpath_width_gp-1:0] imm; \ + logic [branch_metadata_fwd_width_mp-1:0] branch_metadata_fwd; \ + } bp_be_issue_pkt_s; \ + \ + typedef struct packed \ + { \ + logic v; \ + logic queue_v; \ + logic ispec_v; \ + logic nspec_v; \ + logic [vaddr_width_mp-1:0] pc; \ + rv64_instr_s instr; \ + logic [fetch_ptr_mp-1:0] count; \ + logic [issue_ptr_mp-1:0] size; \ + bp_be_decode_s decode; \ + \ + logic [dpath_width_gp-1:0] rs1; \ + logic [dpath_width_gp-1:0] rs2; \ + logic [dpath_width_gp-1:0] imm; \ + bp_be_exception_s exception; \ + bp_be_special_s special; \ + } bp_be_dispatch_pkt_s; \ + \ + typedef struct packed \ + { \ + logic v; \ + logic [vaddr_width_mp-1:0] pc; \ + rv64_instr_s instr; \ + bp_be_decode_s decode; \ + logic [fetch_ptr_mp-1:0] count; \ + logic [issue_ptr_mp-1:0] size; \ + \ + logic [int_rec_width_gp-1:0] isrc1; \ + logic [int_rec_width_gp-1:0] isrc2; \ + logic [int_rec_width_gp-1:0] isrc3; \ + logic [dp_rec_width_gp-1:0] fsrc1; \ + logic [dp_rec_width_gp-1:0] fsrc2; \ + logic [dp_rec_width_gp-1:0] fsrc3; \ + } bp_be_reservation_s; \ + \ + typedef struct packed \ + { \ + logic v; \ + logic fflags_v; \ + logic aux_iwb_v; \ + logic aux_fwb_v; \ + logic eint_iwb_v; \ + logic eint_fwb_v; \ + logic fint_iwb_v; \ + logic fint_fwb_v; \ + logic emem_iwb_v; \ + logic emem_fwb_v; \ + logic fmem_iwb_v; \ + logic fmem_fwb_v; \ + logic mul_iwb_v; \ + logic mul_fwb_v; \ + logic fma_iwb_v; \ + logic fma_fwb_v; \ + logic long_iwb_v; \ + logic long_fwb_v; \ + \ + logic [rv64_reg_addr_width_gp-1:0] rd_addr; \ + } bp_be_dep_status_s; \ + \ + typedef struct packed \ + { \ + logic v; \ + logic branch; \ + logic btaken; \ + logic bspec; \ + logic [vaddr_width_mp-1:0] npc; \ + } bp_be_branch_pkt_s; \ + \ + typedef struct packed \ + { \ + logic v; \ + logic queue_v; \ + logic instret; \ + logic [vaddr_width_mp-1:0] npc; \ + logic [vaddr_width_mp-1:0] vaddr; \ + logic [dpath_width_gp-1:0] data; \ + rv64_instr_s instr; \ + logic [fetch_ptr_mp-1:0] count; \ + logic [issue_ptr_mp-1:0] size; \ + bp_be_exception_s exception; \ + bp_be_special_s special; \ + logic iscore; \ + logic fscore; \ + } bp_be_retire_pkt_s; \ + \ + typedef struct packed \ + { \ + logic [paddr_width_mp-page_offset_width_gp-1:0] ptag; \ + logic gigapage; \ + logic megapage; \ + logic a; \ + logic d; \ + logic u; \ + logic x; \ + logic w; \ + logic r; \ + } bp_be_pte_leaf_s; \ + \ + typedef struct packed \ + { \ + logic npc_w_v; \ + logic queue_v; \ + logic instret; \ + logic [fetch_ptr_mp-1:0] count; \ + logic [issue_ptr_mp-1:0] size; \ + logic [vaddr_width_mp-1:0] pc; \ + logic [vaddr_width_mp-1:0] npc; \ + logic [vaddr_width_mp-1:0] vaddr; \ + rv64_instr_s instr; \ + bp_be_pte_leaf_s pte_leaf; \ + logic [rv64_priv_width_gp-1:0] priv_n; \ + logic translation_en_n; \ + logic exception; \ + logic _interrupt; \ + logic resume; \ + logic eret; \ + logic fencei; \ + logic sfence; \ + logic csrw; \ + logic wfi; \ + logic itlb_miss; \ + logic icache_miss; \ + logic dtlb_store_miss; \ + logic dtlb_load_miss; \ + logic dcache_miss; \ + logic dcache_replay; \ + logic itlb_fill_v; \ + logic dtlb_fill_v; \ + logic iscore_v; \ + logic fscore_v; \ + } bp_be_commit_pkt_s; \ + \ + typedef struct packed \ + { \ + logic ird_w_v; \ + logic frd_w_v; \ + logic ptw_w_v; \ + logic [reg_addr_width_gp-1:0] rd_addr; \ + logic [dpath_width_gp-1:0] rd_data; \ + rv64_fflags_s fflags; \ + } bp_be_wb_pkt_s; \ + \ + typedef struct packed \ + { \ + logic [rv64_priv_width_gp-1:0] priv_mode; \ + logic [paddr_width_mp-page_offset_width_gp-1:0] base_ppn; \ + logic translation_en; \ + logic mstatus_sum; \ + logic mstatus_mxr; \ + } bp_be_trans_info_s; \ + \ + typedef struct packed \ + { \ + logic u_mode; \ + logic s_mode; \ + logic m_mode; \ + logic debug_mode; \ + logic tsr; \ + logic tw; \ + logic tvm; \ + logic ebreakm; \ + logic ebreaks; \ + logic ebreaku; \ + logic fpu_en; \ + logic cycle_en; \ + logic instret_en; \ + } bp_be_decode_info_s + + + /* Declare width macros so that clients can use structs in ports before struct declaration + * Each of these macros needs to be kept in sync with the struct definition. The computation + * comes from literally counting bits in the struct definition, which is ugly, error-prone, + * and an unfortunate, necessary consequence of parameterized structs. + */ + `define declare_bp_be_if_widths(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + , localparam preissue_pkt_width_lp = `bp_be_preissue_pkt_width(issue_ptr_mp) \ + , localparam issue_pkt_width_lp = `bp_be_issue_pkt_width(vaddr_width_mp, branch_metadata_fwd_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + , localparam dispatch_pkt_width_lp = `bp_be_dispatch_pkt_width(vaddr_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + , localparam reservation_width_lp = `bp_be_reservation_width(vaddr_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + , localparam branch_pkt_width_lp = `bp_be_branch_pkt_width(vaddr_width_mp) \ + , localparam retire_pkt_width_lp = `bp_be_retire_pkt_width(vaddr_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + , localparam pte_leaf_width_lp = `bp_be_pte_leaf_width(paddr_width_mp) \ + , localparam commit_pkt_width_lp = `bp_be_commit_pkt_width(vaddr_width_mp, paddr_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + , localparam wb_pkt_width_lp = `bp_be_wb_pkt_width(vaddr_width_mp) \ + , localparam trans_info_width_lp = `bp_be_trans_info_width(paddr_width_mp) \ + , localparam decode_info_width_lp = `bp_be_decode_info_width + + `define bp_be_preissue_pkt_width(issue_ptr_mp) \ + (5+rv64_instr_width_gp+issue_ptr_mp) + + `define bp_be_issue_pkt_width(vaddr_width_mp, branch_metadata_fwd_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + (6+vaddr_width_mp+instr_width_gp+fetch_ptr_mp+issue_ptr_mp+$bits(bp_be_decode_s)+dpath_width_gp+branch_metadata_fwd_width_mp+13) + + `define bp_be_dispatch_pkt_width(vaddr_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + (4+vaddr_width_mp+rv64_instr_width_gp+fetch_ptr_mp+issue_ptr_mp+3*dpath_width_gp+$bits(bp_be_decode_s)+$bits(bp_be_exception_s)+$bits(bp_be_special_s)) + + `define bp_be_reservation_width(vaddr_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + (1+vaddr_width_mp+rv64_instr_width_gp+fetch_ptr_mp+issue_ptr_mp+$bits(bp_be_decode_s)+3*int_rec_width_gp+3*dp_rec_width_gp) + + `define bp_be_branch_pkt_width(vaddr_width_mp) \ + (4+vaddr_width_mp) + + `define bp_be_retire_pkt_width(vaddr_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + (5+dpath_width_gp+2*vaddr_width_mp+instr_width_gp+fetch_ptr_mp+issue_ptr_mp+$bits(bp_be_exception_s)+$bits(bp_be_special_s)) + + `define bp_be_pte_leaf_width(paddr_width_mp) \ + (paddr_width_mp-page_offset_width_gp+8) + + `define bp_be_commit_pkt_width(vaddr_width_mp, paddr_width_mp, fetch_ptr_mp, issue_ptr_mp) \ + (4+`bp_be_pte_leaf_width(paddr_width_mp)+3*vaddr_width_mp+instr_width_gp+fetch_ptr_mp+issue_ptr_mp+rv64_priv_width_gp+18) + + `define bp_be_wb_pkt_width(vaddr_width_mp) \ + (3+reg_addr_width_gp+dpath_width_gp+$bits(rv64_fflags_s)) + + `define bp_be_trans_info_width(paddr_width_mp) \ + (rv64_priv_width_gp+paddr_width_mp-page_offset_width_gp+3) + + `define bp_be_decode_info_width \ + (rv64_priv_width_gp+11) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_be_detector.sv b/designs/black-parrot/src/bp/bp_be_detector.sv new file mode 100644 index 0000000..34c6492 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_detector.sv @@ -0,0 +1,300 @@ +/** + * + * Name: + * bp_be_detector.v + * + * Description: + * + * + * Notes: + * We should get rid of the magic numbers here and replace with constants based on pipeline + * stages. However, like the calculator, this is a high risk change that should be postponed + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_detector + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + // Generated parameters + ) + (input clk_i + , input reset_i + + // Dependency information + , input [issue_pkt_width_lp-1:0] issue_pkt_i + , input cmd_full_i + , input credits_full_i + , input credits_empty_i + , input idiv_busy_i + , input fdiv_busy_i + , input mem_busy_i + , input mem_ordered_i + + // Pipeline control signals from the checker to the calculator + , output logic hazard_v_o + , output logic ordered_v_o + , input [dispatch_pkt_width_lp-1:0] dispatch_pkt_i + , input [commit_pkt_width_lp-1:0] commit_pkt_i + + , input [wb_pkt_width_lp-1:0] late_wb_pkt_i + , input late_wb_yumi_i + + , output logic ispec_v_o + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + `bp_cast_i(bp_be_issue_pkt_s, issue_pkt); + `bp_cast_i(bp_be_dispatch_pkt_s, dispatch_pkt); + `bp_cast_i(bp_be_commit_pkt_s, commit_pkt); + `bp_cast_i(bp_be_wb_pkt_s, late_wb_pkt); + + // Integer data hazards + logic irs1_sb_raw_haz_v, irs2_sb_raw_haz_v; + logic ird_sb_waw_haz_v; + logic [2:0] irs1_data_haz_v , irs2_data_haz_v; + // Floating point data hazards + logic frs1_sb_raw_haz_v, frs2_sb_raw_haz_v, frs3_sb_raw_haz_v; + logic frd_sb_waw_haz_v; + logic [2:0] frs1_data_haz_v, frs2_data_haz_v, frs3_data_haz_v; + logic [2:0] rs1_match_vector, rs2_match_vector, rs3_match_vector, rd_match_vector; + logic score_rs1_match, score_rs2_match, score_rs3_match, score_rd_match; + + bp_be_decode_s decode; + rv64_instr_s instr; + assign decode = issue_pkt_cast_i.decode; + bp_be_dep_status_s [3:0] dep_status_r; + + logic fence_haz_v, cmd_haz_v, fflags_haz_v, iscore_haz_v, fscore_haz_v; + logic data_haz_v, control_haz_v, struct_haz_v; + + wire [reg_addr_width_gp-1:0] score_rd_li = commit_pkt_cast_i.instr.t.fmatype.rd_addr; + wire [reg_addr_width_gp-1:0] check_rs1_li = issue_pkt_cast_i.instr.t.fmatype.rs1_addr; + wire [reg_addr_width_gp-1:0] check_rs2_li = issue_pkt_cast_i.instr.t.fmatype.rs2_addr; + wire [reg_addr_width_gp-1:0] check_rs3_li = issue_pkt_cast_i.instr.t.fmatype.rs3_addr; + wire [reg_addr_width_gp-1:0] check_rd_li = issue_pkt_cast_i.instr.t.fmatype.rd_addr; + + wire [reg_addr_width_gp-1:0] clear_rd_li = late_wb_pkt_cast_i.rd_addr; + + wire irs1_ispec_v = decode.irs1_r_v & rs1_match_vector[0] + & decode.pipe_int_v + & (dep_status_r[0].aux_iwb_v | dep_status_r[0].emem_iwb_v | dep_status_r[0].fint_iwb_v) + & integer_support_p[e_catchup]; + + wire irs2_ispec_v = decode.irs2_r_v & rs2_match_vector[0] + & decode.pipe_int_v + & (dep_status_r[0].aux_iwb_v | dep_status_r[0].emem_iwb_v | dep_status_r[0].fint_iwb_v) + & integer_support_p[e_catchup]; + + wire irs2_store_v = decode.irs2_r_v & rs2_match_vector[0] + & decode.dcache_w_v + & (dep_status_r[0].aux_iwb_v | dep_status_r[0].emem_iwb_v | dep_status_r[0].fint_iwb_v) + & integer_support_p[e_catchup]; + + assign ispec_v_o = irs1_ispec_v | irs2_ispec_v; + + logic [1:0] irs_match_lo; + logic ird_match_lo; + wire score_int_v_li = commit_pkt_cast_i.iscore_v; + wire clear_int_v_li = late_wb_pkt_cast_i.ird_w_v & late_wb_yumi_i; + bp_be_scoreboard + #(.bp_params_p(bp_params_p), .num_rs_p(2)) + int_scoreboard + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.score_v_i(score_int_v_li) + ,.score_rd_i(score_rd_li) + + ,.clear_v_i(clear_int_v_li) + ,.clear_rd_i(clear_rd_li) + + ,.check_rs_i({check_rs2_li, check_rs1_li}) + ,.check_rd_i(check_rd_li) + ,.rs_match_o(irs_match_lo) + ,.rd_match_o(ird_match_lo) + ); + + logic [2:0] frs_match_lo; + logic frd_match_lo; + wire score_fp_v_li = commit_pkt_cast_i.fscore_v; + wire clear_fp_v_li = late_wb_pkt_cast_i.frd_w_v & late_wb_yumi_i; + bp_be_scoreboard + #(.bp_params_p(bp_params_p), .num_rs_p(3)) + fp_scoreboard + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.score_v_i(score_fp_v_li) + ,.score_rd_i(score_rd_li) + + ,.clear_v_i(clear_fp_v_li) + ,.clear_rd_i(clear_rd_li) + + ,.check_rs_i({check_rs3_li, check_rs2_li, check_rs1_li}) + ,.check_rd_i(check_rd_li) + ,.rs_match_o(frs_match_lo) + ,.rd_match_o(frd_match_lo) + ); + + always_comb + begin + // Generate matches for rs1, rs2, rs3 + // 3 stages because we only care about ex1, ex2, and iwb dependencies. fwb dependencies + // can be handled through forwarding + for (integer i = 0; i < 3; i++) + begin + rs1_match_vector[i] = (issue_pkt_cast_i.instr.t.fmatype.rs1_addr == dep_status_r[i].rd_addr); + rs2_match_vector[i] = (issue_pkt_cast_i.instr.t.fmatype.rs2_addr == dep_status_r[i].rd_addr); + rs3_match_vector[i] = (issue_pkt_cast_i.instr.t.fmatype.rs3_addr == dep_status_r[i].rd_addr); + rd_match_vector [i] = (issue_pkt_cast_i.instr.t.fmatype.rd_addr == dep_status_r[i].rd_addr); + end + score_rs1_match = (issue_pkt_cast_i.instr.t.fmatype.rs1_addr == score_rd_li); + score_rs2_match = (issue_pkt_cast_i.instr.t.fmatype.rs2_addr == score_rd_li); + score_rs3_match = (issue_pkt_cast_i.instr.t.fmatype.rs3_addr == score_rd_li); + score_rd_match = (issue_pkt_cast_i.instr.t.fmatype.rd_addr == score_rd_li); + + // Detect scoreboard hazards + irs1_sb_raw_haz_v = (decode.irs1_r_v & irs_match_lo[0]); + irs2_sb_raw_haz_v = (decode.irs2_r_v & irs_match_lo[1]); + ird_sb_waw_haz_v = (decode.irf_w_v & ird_match_lo); + + frs1_sb_raw_haz_v = (decode.frs1_r_v & frs_match_lo[0]); + frs2_sb_raw_haz_v = (decode.frs2_r_v & frs_match_lo[1]); + frs3_sb_raw_haz_v = (decode.frs3_r_v & frs_match_lo[2]); + frd_sb_waw_haz_v = (decode.frf_w_v & frd_match_lo); + + iscore_haz_v = (decode.irf_w_v & dep_status_r[0].long_iwb_v & rd_match_vector[0]) + | (decode.irf_w_v & dep_status_r[1].long_iwb_v & rd_match_vector[1]) + | (decode.irf_w_v & dep_status_r[2].long_iwb_v & rd_match_vector[2]); + + fscore_haz_v = (decode.frf_w_v & dep_status_r[0].long_fwb_v & rd_match_vector[0]) + | (decode.frf_w_v & dep_status_r[1].long_fwb_v & rd_match_vector[1]) + | (decode.frf_w_v & dep_status_r[2].long_fwb_v & rd_match_vector[2]); + + // Detect integer and float data hazards for EX1 + irs1_data_haz_v[0] = (decode.irs1_r_v & rs1_match_vector[0]) + & (dep_status_r[0].fint_iwb_v | dep_status_r[0].aux_iwb_v | dep_status_r[0].mul_iwb_v | dep_status_r[0].emem_iwb_v | dep_status_r[0].fmem_iwb_v | dep_status_r[0].long_iwb_v) + & ~irs1_ispec_v; + + irs2_data_haz_v[0] = (decode.irs2_r_v & rs2_match_vector[0]) + & (dep_status_r[0].fint_iwb_v | dep_status_r[0].aux_iwb_v | dep_status_r[0].mul_iwb_v | dep_status_r[0].emem_iwb_v | dep_status_r[0].fmem_iwb_v | dep_status_r[0].long_iwb_v) + & ~irs2_ispec_v + & ~irs2_store_v; + + frs1_data_haz_v[0] = (decode.frs1_r_v & rs1_match_vector[0]) + & (dep_status_r[0].fint_fwb_v | dep_status_r[0].aux_fwb_v | dep_status_r[0].emem_fwb_v | dep_status_r[0].fmem_fwb_v | dep_status_r[0].fma_fwb_v | dep_status_r[0].long_fwb_v); + + frs2_data_haz_v[0] = (decode.frs2_r_v & rs2_match_vector[0]) + & (dep_status_r[0].fint_fwb_v | dep_status_r[0].aux_fwb_v | dep_status_r[0].emem_fwb_v | dep_status_r[0].fmem_fwb_v | dep_status_r[0].fma_fwb_v | dep_status_r[0].long_fwb_v); + + frs3_data_haz_v[0] = (decode.frs3_r_v & rs3_match_vector[0]) + & (dep_status_r[0].fint_fwb_v | dep_status_r[0].aux_fwb_v | dep_status_r[0].emem_fwb_v | dep_status_r[0].fmem_fwb_v | dep_status_r[0].fma_fwb_v | dep_status_r[0].long_fwb_v); + + // Detect integer and float data hazards for EX2 + irs1_data_haz_v[1] = (decode.irs1_r_v & rs1_match_vector[1]) + & (dep_status_r[1].fmem_iwb_v | dep_status_r[1].mul_iwb_v | dep_status_r[1].long_iwb_v); + + irs2_data_haz_v[1] = (decode.irs2_r_v & rs2_match_vector[1]) + & (dep_status_r[1].fmem_iwb_v | dep_status_r[1].mul_iwb_v | dep_status_r[1].long_iwb_v); + + frs1_data_haz_v[1] = (decode.frs1_r_v & rs1_match_vector[1]) + & (dep_status_r[1].fmem_fwb_v | dep_status_r[1].fma_fwb_v | dep_status_r[1].long_fwb_v); + + frs2_data_haz_v[1] = (decode.frs2_r_v & rs2_match_vector[1]) + & (dep_status_r[1].fmem_fwb_v | dep_status_r[1].fma_fwb_v | dep_status_r[1].long_fwb_v); + + frs3_data_haz_v[1] = (decode.frs3_r_v & rs3_match_vector[1]) + & (dep_status_r[1].fmem_fwb_v | dep_status_r[1].fma_fwb_v | dep_status_r[1].long_fwb_v); + + irs1_data_haz_v[2] = (decode.irs1_r_v & rs1_match_vector[2]) + & (dep_status_r[2].long_iwb_v); + + irs2_data_haz_v[2] = (decode.irs2_r_v & rs2_match_vector[2]) + & (dep_status_r[2].long_iwb_v); + + frs1_data_haz_v[2] = (decode.frs1_r_v & rs1_match_vector[2]) + & (dep_status_r[2].fma_fwb_v | dep_status_r[2].long_fwb_v); + + frs2_data_haz_v[2] = (decode.frs2_r_v & rs2_match_vector[2]) + & (dep_status_r[2].fma_fwb_v | dep_status_r[2].long_fwb_v); + + frs3_data_haz_v[2] = (decode.frs3_r_v & rs3_match_vector[2]) + & (dep_status_r[2].fma_fwb_v | dep_status_r[2].long_fwb_v); + + fence_haz_v = decode.fence_v & ~mem_ordered_i; + cmd_haz_v = cmd_full_i; + + fflags_haz_v = (decode.csr_r_v | decode.csr_w_v) + & (dep_status_r[0].fflags_v + | dep_status_r[1].fflags_v + | dep_status_r[2].fflags_v + | dep_status_r[3].fflags_v + | fdiv_busy_i + ); + + control_haz_v = fence_haz_v | fflags_haz_v; + + // Combine all data hazard information + // TODO: Parameterize away floating point data hazards without hardware support + data_haz_v = (|irs1_data_haz_v) + | (|irs2_data_haz_v) + | (|frs1_data_haz_v) + | (|frs2_data_haz_v) + | (|frs3_data_haz_v) + | (irs1_sb_raw_haz_v | irs2_sb_raw_haz_v | ird_sb_waw_haz_v) + | (frs1_sb_raw_haz_v | frs2_sb_raw_haz_v | frs3_sb_raw_haz_v | frd_sb_waw_haz_v); + + // Combine all structural hazard information + struct_haz_v = cmd_haz_v + | fscore_haz_v | iscore_haz_v + | (mem_busy_i & decode.pipe_mem_early_v) + | (mem_busy_i & decode.pipe_mem_final_v) + | (fdiv_busy_i & decode.pipe_long_v) + | (idiv_busy_i & decode.pipe_long_v); + end + + assign hazard_v_o = struct_haz_v | control_haz_v | data_haz_v; + assign ordered_v_o = ~(mem_busy_i | fdiv_busy_i | idiv_busy_i) & mem_ordered_i; + + bp_be_decode_s dep_decode; + bp_be_dep_status_s dep_status_n; + assign dep_decode = dispatch_pkt_cast_i.decode; + always_comb + begin + dep_status_n.v = dispatch_pkt_cast_i.v; + // nspec == writeback, could reduce to only fflags setting + dep_status_n.fflags_v = dispatch_pkt_cast_i.nspec_v | dep_decode.pipe_aux_v | dep_decode.pipe_fma_v; + dep_status_n.eint_iwb_v = dep_decode.pipe_int_v & dep_decode.irf_w_v & ~ispec_v_o; + dep_status_n.eint_fwb_v = dep_decode.pipe_int_v & dep_decode.frf_w_v; + dep_status_n.fint_iwb_v = dep_decode.pipe_int_v & dep_decode.irf_w_v & ispec_v_o; + dep_status_n.fint_fwb_v = dep_decode.pipe_int_v & dep_decode.frf_w_v; + dep_status_n.aux_iwb_v = dep_decode.pipe_aux_v & dep_decode.irf_w_v; + dep_status_n.aux_fwb_v = dep_decode.pipe_aux_v & dep_decode.frf_w_v; + dep_status_n.emem_iwb_v = dep_decode.pipe_mem_early_v & dep_decode.irf_w_v; + dep_status_n.emem_fwb_v = dep_decode.pipe_mem_early_v & dep_decode.frf_w_v; + dep_status_n.fmem_iwb_v = dep_decode.pipe_mem_final_v & dep_decode.irf_w_v; + dep_status_n.fmem_fwb_v = dep_decode.pipe_mem_final_v & dep_decode.frf_w_v; + dep_status_n.mul_iwb_v = dep_decode.pipe_mul_v & dep_decode.irf_w_v; + dep_status_n.mul_fwb_v = dep_decode.pipe_mul_v & dep_decode.frf_w_v; + dep_status_n.fma_iwb_v = dep_decode.pipe_fma_v & dep_decode.irf_w_v; + dep_status_n.fma_fwb_v = dep_decode.pipe_fma_v & dep_decode.frf_w_v; + dep_status_n.long_iwb_v = dep_decode.pipe_long_v & dep_decode.irf_w_v; + dep_status_n.long_fwb_v = dep_decode.pipe_long_v & dep_decode.frf_w_v; + dep_status_n.rd_addr = dispatch_pkt_cast_i.instr.t.rtype.rd_addr; + end + + always_ff @(posedge clk_i) + begin + dep_status_r[0] <= dispatch_pkt_cast_i.v ? dep_status_n : '0; + dep_status_r[3:1] <= dep_status_r[2:0]; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_director.sv b/designs/black-parrot/src/bp/bp_be_director.sv new file mode 100644 index 0000000..7050581 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_director.sv @@ -0,0 +1,284 @@ +/** + * + * Name: + * bp_be_director.v + * + * Description: + * Directs the PC for the FE and the calculator. Keeps track of the next PC + * and sends redirect signals to the FE when a misprediction is detected. + * + * Notes: + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_director + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + // Generated parameters + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // Dependency information + , input [issue_pkt_width_lp-1:0] issue_pkt_i + , output logic [vaddr_width_p-1:0] expected_npc_o + , output logic poison_isd_o + , output logic clear_iss_o + , output logic suppress_iss_o + , output logic resume_o + , input irq_waiting_i + , input mem_busy_i + , output logic cmd_full_n_o + , output logic cmd_full_r_o + + // FE-BE interface + , output logic [fe_cmd_width_lp-1:0] fe_cmd_o + , output logic fe_cmd_v_o + , input fe_cmd_yumi_i + + , input [branch_pkt_width_lp-1:0] br_pkt_i + , input [commit_pkt_width_lp-1:0] commit_pkt_i + ); + + // Declare parameterized structures + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + `bp_cast_i(bp_be_issue_pkt_s, issue_pkt); + `bp_cast_i(bp_be_branch_pkt_s, br_pkt); + `bp_cast_i(bp_be_commit_pkt_s, commit_pkt); + + bp_fe_cmd_s fe_cmd_li; + bp_fe_cmd_pc_redirect_operands_s fe_cmd_pc_redirect_operands; + logic fe_cmd_v_li; + logic cmd_empty_n_lo, cmd_empty_r_lo; + logic cmd_full_n_lo, cmd_full_r_lo; + + // Declare intermediate signals + enum logic [3:0] {e_freeze, e_fencei, e_run, e_cmd_fence, e_wait} state_n, state_r; + wire is_freeze = (state_r == e_freeze); + wire is_fencei = (state_r == e_fencei); + wire is_run = (state_r == e_run); + wire is_cmd_fence = (state_r == e_cmd_fence); + wire is_wait = (state_r == e_wait); + + // Module instantiations + // Update the NPC on a valid instruction in ex1 or upon commit + logic [vaddr_width_p-1:0] npc_n, npc_r; + wire npc_w_v = commit_pkt_cast_i.npc_w_v | br_pkt_cast_i.v; + + assign npc_n = commit_pkt_cast_i.npc_w_v ? commit_pkt_cast_i.npc : br_pkt_cast_i.bspec ? issue_pkt_cast_i.pc : br_pkt_cast_i.npc; + bsg_dff_reset_en_bypass + #(.width_p(vaddr_width_p)) + npc_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(npc_w_v) + + ,.data_i(npc_n) + ,.data_o(npc_r) + ); + assign expected_npc_o = npc_r; + + wire npc_mismatch_v = issue_pkt_cast_i.v & (expected_npc_o != issue_pkt_cast_i.pc); + wire npc_match_v = issue_pkt_cast_i.v & (expected_npc_o == issue_pkt_cast_i.pc); + assign poison_isd_o = npc_mismatch_v; + + logic btaken_pending, attaboy_pending; + bsg_dff_reset_set_clear + #(.width_p(2), .clear_over_set_p(1)) + attaboy_pending_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.set_i({br_pkt_cast_i.btaken, br_pkt_cast_i.branch}) + ,.clear_i({fe_cmd_v_li, fe_cmd_v_li}) + ,.data_o({btaken_pending, attaboy_pending}) + ); + wire last_instr_was_branch = attaboy_pending | br_pkt_cast_i.branch; + wire last_instr_was_btaken = btaken_pending | br_pkt_cast_i.btaken; + + wire fe_cmd_nonattaboy_v = fe_cmd_v_li & (fe_cmd_li.opcode != e_op_attaboy); + + // Boot logic + wire freeze_li = cfg_bus_cast_i.freeze | reset_i; + always_comb + begin + unique casez (state_r) + e_run : state_n = freeze_li + ? e_freeze + : commit_pkt_cast_i.wfi + ? e_wait + : commit_pkt_cast_i.fencei + ? e_fencei + : fe_cmd_nonattaboy_v + ? e_cmd_fence + : state_r; + e_freeze + ,e_fencei + ,e_wait : state_n = commit_pkt_cast_i.resume ? e_cmd_fence : state_r; + // e_cmd_fence: + default : state_n = cmd_empty_r_lo ? e_run : state_r; + endcase + end + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_freeze; + else + state_r <= state_n; + + assign suppress_iss_o = !is_run || cmd_full_r_lo || commit_pkt_cast_i.npc_w_v; + assign clear_iss_o = is_cmd_fence & cmd_empty_r_lo; + assign resume_o = (is_freeze & ~freeze_li) + || (is_wait & irq_waiting_i) + || (is_fencei & ~mem_busy_i); + + always_comb + begin + fe_cmd_li = 'b0; + fe_cmd_v_li = 1'b0; + fe_cmd_pc_redirect_operands = '0; + + if (commit_pkt_cast_i.resume) + begin + fe_cmd_li.opcode = is_freeze ? e_op_state_reset : is_fencei ? e_op_icache_fence : e_op_pc_redirection; + fe_cmd_li.npc = npc_n; + + fe_cmd_pc_redirect_operands.priv = commit_pkt_cast_i.priv_n; + fe_cmd_pc_redirect_operands.translation_en = commit_pkt_cast_i.translation_en_n; + fe_cmd_pc_redirect_operands.subopcode = e_subop_resume; + fe_cmd_li.operands.pc_redirect_operands = fe_cmd_pc_redirect_operands; + + fe_cmd_v_li = 1'b1; + end + else if (commit_pkt_cast_i.itlb_fill_v) + begin + fe_cmd_li.opcode = e_op_itlb_fill_response; + fe_cmd_li.npc = commit_pkt_cast_i.vaddr; + fe_cmd_li.operands.itlb_fill_response.pte_leaf = commit_pkt_cast_i.pte_leaf; + fe_cmd_li.operands.itlb_fill_response.instr = commit_pkt_cast_i.instr; + fe_cmd_li.operands.itlb_fill_response.count = commit_pkt_cast_i.count; + + fe_cmd_v_li = 1'b1; + end + else if (commit_pkt_cast_i.sfence) + begin + fe_cmd_li.opcode = e_op_itlb_fence; + fe_cmd_li.npc = commit_pkt_cast_i.npc; + + fe_cmd_v_li = 1'b1; + end + else if (commit_pkt_cast_i.csrw) + begin + fe_cmd_li.opcode = e_op_pc_redirection; + fe_cmd_li.npc = commit_pkt_cast_i.npc; + fe_cmd_pc_redirect_operands.subopcode = e_subop_translation_switch; + fe_cmd_pc_redirect_operands.translation_en = commit_pkt_cast_i.translation_en_n; + fe_cmd_li.operands.pc_redirect_operands = fe_cmd_pc_redirect_operands; + + fe_cmd_v_li = 1'b1; + end + else if (commit_pkt_cast_i.wfi) + begin + fe_cmd_li.opcode = e_op_wait; + fe_cmd_li.npc = commit_pkt_cast_i.npc; + + fe_cmd_v_li = 1'b1; + end + else if (commit_pkt_cast_i.icache_miss) + begin + fe_cmd_li.opcode = e_op_icache_fill_response; + fe_cmd_li.npc = commit_pkt_cast_i.vaddr; + fe_cmd_li.operands.icache_fill_response.instr = commit_pkt_cast_i.instr; + fe_cmd_li.operands.icache_fill_response.count = commit_pkt_cast_i.count; + + + fe_cmd_v_li = 1'b1; + end + else if (commit_pkt_cast_i.eret) + begin + fe_cmd_li.opcode = e_op_pc_redirection; + fe_cmd_li.npc = commit_pkt_cast_i.npc; + fe_cmd_pc_redirect_operands.subopcode = e_subop_eret; + fe_cmd_pc_redirect_operands.priv = commit_pkt_cast_i.priv_n; + fe_cmd_pc_redirect_operands.translation_en = commit_pkt_cast_i.translation_en_n; + fe_cmd_li.operands.pc_redirect_operands = fe_cmd_pc_redirect_operands; + + fe_cmd_v_li = 1'b1; + end + else if (commit_pkt_cast_i.exception | commit_pkt_cast_i._interrupt) + begin + fe_cmd_li.opcode = e_op_pc_redirection; + fe_cmd_li.npc = commit_pkt_cast_i.npc; + fe_cmd_pc_redirect_operands.subopcode = commit_pkt_cast_i.exception ? e_subop_trap : e_subop_interrupt; + fe_cmd_pc_redirect_operands.priv = commit_pkt_cast_i.priv_n; + fe_cmd_pc_redirect_operands.translation_en = commit_pkt_cast_i.translation_en_n; + fe_cmd_li.operands.pc_redirect_operands = fe_cmd_pc_redirect_operands; + + fe_cmd_v_li = 1'b1; + end + else if (npc_mismatch_v) + begin + fe_cmd_li.opcode = e_op_pc_redirection; + fe_cmd_li.npc = expected_npc_o; + fe_cmd_pc_redirect_operands.subopcode = e_subop_branch_mispredict; + fe_cmd_pc_redirect_operands.branch_metadata_fwd = issue_pkt_cast_i.branch_metadata_fwd; + fe_cmd_pc_redirect_operands.misprediction_reason = last_instr_was_branch + ? last_instr_was_btaken + ? e_incorrect_pred_taken + : e_incorrect_pred_ntaken + : e_not_a_branch; + fe_cmd_li.operands.pc_redirect_operands = fe_cmd_pc_redirect_operands; + + fe_cmd_v_li = 1'b1; + end + // Send an attaboy if there's a correct prediction + else if (npc_match_v & last_instr_was_branch) + begin + fe_cmd_li.opcode = e_op_attaboy; + fe_cmd_li.npc = expected_npc_o; + fe_cmd_li.operands.attaboy.taken = last_instr_was_btaken; + fe_cmd_li.operands.attaboy.branch_metadata_fwd = issue_pkt_cast_i.branch_metadata_fwd; + + fe_cmd_v_li = 1'b1; + end + end + + bp_be_cmd_queue + #(.bp_params_p(bp_params_p)) + fe_cmd_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.fe_cmd_i(fe_cmd_li) + ,.fe_cmd_v_i(fe_cmd_v_li) + + ,.fe_cmd_o(fe_cmd_o) + ,.fe_cmd_v_o(fe_cmd_v_o) + ,.fe_cmd_yumi_i(fe_cmd_yumi_i) + + ,.empty_n_o(cmd_empty_n_lo) + ,.empty_r_o(cmd_empty_r_lo) + ,.full_n_o(cmd_full_n_lo) + ,.full_r_o(cmd_full_r_lo) + ); + assign cmd_full_n_o = cmd_full_n_lo; + assign cmd_full_r_o = cmd_full_r_lo; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_expander.sv b/designs/black-parrot/src/bp/bp_be_expander.sv new file mode 100644 index 0000000..155a9af --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_expander.sv @@ -0,0 +1,209 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_expander + import bp_common_pkg::*; + import bp_be_pkg::*; + (input [cinstr_width_gp-1:0] cinstr_i + + , output logic [instr_width_gp-1:0] instr_o + ); + + logic [rv64_reg_addr_width_gp-1:0] rs1, rs2, rd; + logic [dword_width_gp-1:0] imm; + wire [11:0] zero_imm = '0; + + localparam rv64_zero_addr_gp = 5'd0; + localparam rv64_link_addr_gp = 5'd1; + localparam rv64_sp_addr_gp = 5'd2; + + rv64_cinstr_s cinstr; + assign cinstr = cinstr_i; + + always_comb + begin + instr_o = cinstr_i; + + // Different per quadrant + casez (cinstr_i) + `RV64_C2_INSTR, `RV64_CADDI, `RV64_CADDIW, `RV64_CLI, `RV64_CADDI16SP, `RV64_CLUI: + begin + rs1 = cinstr_i[11:7]; + rs2 = cinstr_i[6:2]; + rd = cinstr_i[11:7]; + end + `RV64_C1_INSTR: + begin + rs1 = {2'b01, cinstr_i[9:7]}; + rs2 = {2'b01, cinstr_i[4:2]}; + rd = {2'b01, cinstr_i[9:7]}; + end + // `RV64_C0_INSTR: + default: + begin + rs1 = {2'b01, cinstr_i[9:7]}; + rs2 = {2'b01, cinstr_i[4:2]}; + rd = {2'b01, cinstr_i[4:2]}; + end + endcase + + casez (cinstr_i) + `RV64_CADDI16SP: + imm = dword_width_gp'($signed({cinstr_i[12], cinstr_i[4:3], cinstr_i[5], cinstr_i[2], cinstr_i[6], 4'b0000})); + `RV64_CADDI4SPN: + imm = dword_width_gp'($unsigned({cinstr_i[10:7], cinstr_i[12:11], cinstr_i[5], cinstr_i[6], 2'b00})); + `RV64_CLWSP: + imm = dword_width_gp'($unsigned({cinstr_i[3:2], cinstr_i[12], cinstr_i[6:4], 2'b00})); + `RV64_CFLDSP, `RV64_CLDSP: + imm = dword_width_gp'($unsigned({cinstr_i[4:2], cinstr_i[12], cinstr_i[6:5], 3'b000})); + `RV64_CSWSP: + imm = dword_width_gp'($unsigned({cinstr_i[8:7], cinstr_i[12:9], 2'b00})); + `RV64_CFSDSP, `RV64_CSDSP: + imm = dword_width_gp'($unsigned({cinstr_i[9:7], cinstr_i[12:10], 3'b000})); + `RV64_CLW, `RV64_CSW: + imm = dword_width_gp'($unsigned({cinstr_i[5], cinstr_i[12:10], cinstr_i[6], 2'b00})); + `RV64_CFLD, `RV64_CLD, `RV64_CFSD, `RV64_CSD: + imm = dword_width_gp'($unsigned({cinstr_i[6:5], cinstr_i[12:10], 3'b000})); + `RV64_CJ: + imm = dword_width_gp'($signed({cinstr_i[12], cinstr_i[8], cinstr_i[10:9], cinstr_i[6] ,cinstr_i[7], cinstr_i[2], cinstr_i[11], cinstr_i[5:3], 1'b0})); + `RV64_CBEQZ, `RV64_CBNEZ: + imm = dword_width_gp'($signed({cinstr_i[12], cinstr_i[6:5], cinstr_i[2], cinstr_i[11:10], cinstr_i[4:3], 1'b0})); + `RV64_CLUI: + imm = dword_width_gp'($signed({cinstr_i[12], cinstr_i[6:2], 12'b0})); + `RV64_CNOP, `RV64_CADDI, `RV64_CADDIW, `RV64_CLI, `RV64_CANDI: + imm = dword_width_gp'($signed({cinstr_i[12], cinstr_i[6:2]})); + `RV64_CSLLI, `RV64_CSRLI: + imm = dword_width_gp'($unsigned({6'b000000, cinstr_i[12], cinstr_i[6:2]})); + `RV64_CSRAI: + imm = dword_width_gp'($unsigned({6'b010000, cinstr_i[12], cinstr_i[6:2]})); + default: imm = '0; + endcase + + casez (cinstr_i) + // C.ILL -> 0000_0000_0000_0000 + `RV64_CILL: instr_o = '0; + // C.ADDI4SPN -> addi rd', x2, nzuimm[9:2] + `RV64_CADDI4SPN: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rd, 3'b000, rv64_sp_addr_gp, imm); + // C.ADDI16SP -> addi x2, x2, nzimm[9:4] + `RV64_CADDI16SP: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rv64_sp_addr_gp, 3'b000, rv64_sp_addr_gp, imm); + // C.EBREAK -> ebreak + `RV64_CEBREAK: instr_o = `RV64_EBREAK; + // C.LWSP -> lw rd, offset[7:2] (x2) + `RV64_CLWSP: instr_o = + `rv64_i_type_exp(`RV64_LOAD_OP, rd, 3'b010, rv64_sp_addr_gp, imm); + // C.LDSP -> ld rd, offset[8:3] (x2) + `RV64_CLDSP: instr_o = + `rv64_i_type_exp(`RV64_LOAD_OP, rd, 3'b011, rv64_sp_addr_gp, imm); + // C.SWSP -> sw rs2, offset[7:2] (x2) + `RV64_CSWSP: instr_o = + `rv64_s_type_exp(`RV64_STORE_OP, 3'b010, rv64_sp_addr_gp, rs2, imm); + // C.SDSP -> sd rs2, offset[8:3] (x2) + `RV64_CSDSP: instr_o = + `rv64_s_type_exp(`RV64_STORE_OP, 3'b011, rv64_sp_addr_gp, rs2, imm); + // C.FLDSP -> fld rd, offset(x2) + `RV64_CFLDSP: instr_o = + `rv64_i_type_exp(`RV64_FLOAD_OP, rd, 3'b011, rv64_sp_addr_gp, imm); + // C.FSDSP -> fsd rs2, offset(x2) + `RV64_CFSDSP: instr_o = + `rv64_s_type_exp(`RV64_FSTORE_OP, 3'b011, rv64_sp_addr_gp, rs2, imm); + // C.LW -> lw rd', offset[6:2] (rs1') + `RV64_CLW: instr_o = + `rv64_i_type_exp(`RV64_LOAD_OP, rd, 3'b010, rs1, imm); + // C.LD -> ld rd', offset[7:3] (rs1') + `RV64_CLD: instr_o = + `rv64_i_type_exp(`RV64_LOAD_OP, rd, 3'b011, rs1, imm); + // C.SW -> sw rs2', offset[6:2] (rs1') + `RV64_CSW: instr_o = + `rv64_s_type_exp(`RV64_STORE_OP, 3'b010, rs1, rs2, imm); + // C.SD -> sd rs2', offset[7:3] (rs1') + `RV64_CSD: instr_o = + `rv64_s_type_exp(`RV64_STORE_OP, 3'b011, rs1, rs2, imm); + // C.FLD -> fld rd', offset(rs1') + `RV64_CFLD: instr_o = + `rv64_i_type_exp(`RV64_FLOAD_OP, rd, 3'b011, rs1, imm); + // C.FSD -> fsd rs2', offset(rs1') + `RV64_CFSD: instr_o = + `rv64_s_type_exp(`RV64_FSTORE_OP, 3'b011, rs1, rs2, imm); + // C.J -> jal x0, offset[11:1] + `RV64_CJ: instr_o = + `rv64_j_type_exp(`RV64_JAL_OP, rv64_zero_addr_gp, imm); + // C.JR -> jalr x0, 0(rs1) + `RV64_CJR: instr_o = + `rv64_i_type_exp(`RV64_JALR_OP, rv64_zero_addr_gp, 3'b000, rs1, zero_imm); + // C.JALR -> jalr x1, 0(rs1) + `RV64_CJALR: instr_o = + `rv64_i_type_exp(`RV64_JALR_OP, rv64_link_addr_gp, 3'b000, rs1, zero_imm); + // C.BEQZ -> beq rs1', x0, offset[8:1] + `RV64_CBEQZ: instr_o = + `rv64_b_type_exp(`RV64_BRANCH_OP, 3'b000, rs1, rv64_zero_addr_gp, imm); + // C.BNEZ -> bne rs1', x0, offset[8:1] + `RV64_CBNEZ: instr_o = + `rv64_b_type_exp(`RV64_BRANCH_OP, 3'b001, rs1, rv64_zero_addr_gp, imm); + // C.LI -> addi rd, x0, imm[5:0] + `RV64_CLI: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rd, 3'b000, rv64_zero_addr_gp, imm); + // C.LUI -> lui rd, nzimm[17:12] + `RV64_CLUI: instr_o = + `rv64_u_type_exp(`RV64_LUI_OP, rd, imm); + // C.NOP -> addi x0, x0, 0 + `RV64_CNOP: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rv64_zero_addr_gp, 3'b000, rv64_zero_addr_gp, zero_imm); + // C.ADDI -> addi rd, rd, nzimm[5:0] + `RV64_CADDI: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rd, 3'b000, rd, imm); + // C.ADDIW -> addiw rd, rd, imm[5:0] + `RV64_CADDIW: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_32_OP, rd, 3'b000, rd, imm); + // C.SLLI -> slli rd, rd, shamt[5:0] + `RV64_CSLLI: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rd, 3'b001, rd, imm); + // C.SRLI -> srli rd', rd', shamt[5:0] + `RV64_CSRLI: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rd, 3'b101, rd, imm); + // C.SRAI -> srai rd', rd', shamt[5:0] + `RV64_CSRAI: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rd, 3'b101, rd, imm); + // C.ANDI -> andi rd', rd', imm[5:0] + `RV64_CANDI: instr_o = + `rv64_i_type_exp(`RV64_OP_IMM_OP, rd, 3'b111, rd, imm); + // C.MV -> add rd, x0, rs2 + `RV64_CMV: instr_o = + `rv64_r_type_exp(`RV64_OP_OP, rd, 3'b000, rv64_zero_addr_gp, rs2, 7'b0); + // C.ADD -> add rd, rd, rs2 + `RV64_CADD: instr_o = + `rv64_r_type_exp(`RV64_OP_OP, rd, 3'b000, rd, rs2, 7'b0); + // C.AND -> and rd', rd', rs2' + `RV64_CAND: instr_o = + `rv64_r_type_exp(`RV64_OP_OP, rd, 3'b111, rd, rs2, 7'b0); + // C.OR -> or rd', rd', rs2' + `RV64_COR: instr_o = + `rv64_r_type_exp(`RV64_OP_OP, rd, 3'b110, rd, rs2, 7'b0); + // C.XOR -> xor rd', rd', rs2' + `RV64_CXOR: instr_o = + `rv64_r_type_exp(`RV64_OP_OP, rd, 3'b100, rd, rs2, 7'b0); + // C.SUB -> sub rd', rd', rs2' + `RV64_CSUB: instr_o = + `rv64_r_type_exp(`RV64_OP_OP, rd, 3'b000, rd, rs2, 7'b010_0000); + // C.ADDW -> addw rd', rd', rs2' + `RV64_CADDW: instr_o = + `rv64_r_type_exp(`RV64_OP_32_OP, rd, 3'b000, rd, rs2, 7'b0); + // C.SUBW -> subw rd', rd', rs2' + `RV64_CSUBW: instr_o = + `rv64_r_type_exp(`RV64_OP_32_OP, rd, 3'b000, rd, rs2, 7'b010_0000); + default: begin end + endcase + + // Check for reserved encodings + casez (cinstr_i) + `RV64_CLWSP, `RV64_CLDSP: instr_o = ~|cinstr_i[11:7] ? '0 : instr_o; + `RV64_CLUI, `RV64_CADDI16SP, `RV64_CADDI4SPN + : instr_o = ~|imm ? '0 : instr_o; + default: begin end + endcase + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_fp_box.sv b/designs/black-parrot/src/bp/bp_be_fp_box.sv new file mode 100644 index 0000000..0052368 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_fp_box.sv @@ -0,0 +1,74 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_fp_box + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (// RAW floating point input + input [dword_width_gp-1:0] ieee_i + , input [$bits(bp_be_fp_tag_e)-1:0] tag_i + , output [dpath_width_gp-1:0] reg_o + ); + + `bp_cast_o(bp_be_fp_reg_s, reg); + + // The control bits control tininess, which is fixed in RISC-V + wire [`floatControlWidth-1:0] control_li = `flControl_default; + // We also convert from 32 bit inputs to 64 bit recoded inputs. + // This double rounding behavior was formally proved correct in + // "Innocuous Double Rounding of Basic Arithmetic Operations" by Pierre Roux + + bp_hardfloat_rec_sp_s in_sp_rec_li; + wire [sp_float_width_gp-1:0] in_sp_li = ieee_i[0+:sp_float_width_gp]; + fNToRecFN + #(.expWidth(sp_exp_width_gp) + ,.sigWidth(sp_sig_width_gp) + ) + in32_rec + (.in(in_sp_li) + ,.out(in_sp_rec_li) + ); + + bp_hardfloat_rec_dp_s in_dp_rec_li; + wire [dp_float_width_gp-1:0] in_dp_li = ieee_i[0+:dp_float_width_gp]; + fNToRecFN + #(.expWidth(dp_exp_width_gp) + ,.sigWidth(dp_sig_width_gp) + ) + in64_rec + (.in(in_dp_li) + ,.out(in_dp_rec_li) + ); + + // + // Unsafe upconvert + // + localparam bias_adj_lp = (1 << dp_exp_width_gp) - (1 << sp_exp_width_gp); + bp_hardfloat_rec_sp_s sp_rec; + bp_hardfloat_rec_dp_s sp2dp_rec; + assign sp_rec = in_sp_rec_li; + + wire [dp_exp_width_gp:0] adjusted_exp = sp_rec.exp + bias_adj_lp; + wire [2:0] exp_code = sp_rec.exp[sp_exp_width_gp-:3]; + wire special = (exp_code == '0) || (exp_code >= 3'd6); + + assign sp2dp_rec = '{sign : sp_rec.sign + ,exp : special ? {exp_code, adjusted_exp[0+:dp_exp_width_gp-2]} : adjusted_exp + ,fract: {sp_rec.fract, (dp_sig_width_gp-sp_sig_width_gp)'(0)} + }; + + wire nanbox_v_li = &ieee_i[word_width_gp+:word_width_gp]; + wire encode_as_sp = nanbox_v_li || (tag_i == e_fp_sp); + + bp_be_fp_reg_s reg32, reg64; + assign reg32 = '{tag: e_fp_sp, rec: sp2dp_rec}; + assign reg64 = '{tag: e_fp_dp, rec: in_dp_rec_li}; + + assign reg_cast_o = encode_as_sp ? reg32 : reg64; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_fp_rebox.sv b/designs/black-parrot/src/bp/bp_be_fp_rebox.sv new file mode 100644 index 0000000..11e7c00 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_fp_rebox.sv @@ -0,0 +1,62 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_fp_rebox + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input [dp_raw_width_gp-1:0] raw_i + , input [$bits(bp_be_fp_tag_e)-1:0] tag_i + , input [$bits(rv64_frm_e)-1:0] frm_i + , input invalid_exc_i + , input infinite_exc_i + + , output logic [dpath_width_gp-1:0] reg_o + , output logic [4:0] fflags_o + ); + + `bp_cast_i(bp_hardfloat_raw_dp_s, raw); + `bp_cast_o(bp_be_fp_reg_s, reg); + + wire [`floatControlWidth-1:0] control_li = `flControl_default; + + logic [dp_rec_width_gp-1:0] result_dp, result_sp; + rv64_fflags_s fflags_dp, fflags_sp; + roundRawFNtoRecFN_mixed + #(.fullExpWidth(dp_exp_width_gp) + ,.fullSigWidth(dp_sig_width_gp) + ,.midExpWidth(sp_exp_width_gp) + ,.midSigWidth(sp_sig_width_gp) + ,.outExpWidth(dp_exp_width_gp) + ,.outSigWidth(dp_sig_width_gp) + ) + round_mixed + (.control(control_li) + ,.invalidExc(invalid_exc_i) + ,.infiniteExc(infinite_exc_i) + ,.in_isNaN(raw_cast_i.is_nan) + ,.in_isInf(raw_cast_i.is_inf) + ,.in_isZero(raw_cast_i.is_zero) + ,.in_sign(raw_cast_i.sign) + ,.in_sExp(raw_cast_i.sexp) + ,.in_sig(raw_cast_i.sig) + ,.roundingMode(frm_i) + ,.fullOut(result_dp) + ,.fullExceptionFlags(fflags_dp) + ,.midOut(result_sp) + ,.midExceptionFlags(fflags_sp) + ); + + bp_be_fp_reg_s sp_reg_lo, dp_reg_lo; + rv64_fflags_s fflags_lo; + assign sp_reg_lo = '{tag: e_fp_sp, rec: result_sp}; + assign dp_reg_lo = '{tag: e_fp_dp, rec: result_dp}; + + assign reg_cast_o = (tag_i == e_fp_sp) ? sp_reg_lo : dp_reg_lo; + assign fflags_o = (tag_i == e_fp_sp) ? fflags_sp : fflags_dp; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_fp_unbox.sv b/designs/black-parrot/src/bp/bp_be_fp_unbox.sv new file mode 100644 index 0000000..a2fd8bd --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_fp_unbox.sv @@ -0,0 +1,66 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_fp_unbox + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input [dpath_width_gp-1:0] reg_i + , input [$bits(bp_be_fp_tag_e)-1:0] tag_i + , input raw_i + , output logic [dp_rec_width_gp-1:0] val_o + ); + + `bp_cast_i(bp_be_fp_reg_s, reg); + + // The control bits control tininess, which is fixed in RISC-V + wire [`floatControlWidth-1:0] control_li = `flControl_default; + + localparam bias_adj_lp = (1 << sp_exp_width_gp) - (1 << dp_exp_width_gp); + bp_hardfloat_rec_dp_s dp_rec; + bp_hardfloat_rec_sp_s dp2sp_rec_unsafe; + assign dp_rec = reg_cast_i.rec; + + wire [sp_exp_width_gp:0] adjusted_exp = dp_rec.exp + bias_adj_lp; + wire [2:0] exp_code = dp_rec.exp[dp_exp_width_gp-:3]; + wire special = (exp_code == '0) || (exp_code >= 3'd6); + + assign dp2sp_rec_unsafe = '{sign : dp_rec.sign + ,exp : special ? {exp_code, adjusted_exp[0+:sp_exp_width_gp-2]} : adjusted_exp + ,fract: dp_rec.fract[dp_sig_width_gp-2:dp_sig_width_gp-sp_sig_width_gp] + }; + + logic [word_width_gp-1:0] dp2sp_raw_lo; + recFNToFN + #(.expWidth(sp_exp_width_gp) + ,.sigWidth(sp_sig_width_gp) + ) + out_sp_rec + (.in(dp2sp_rec_unsafe) + ,.out(dp2sp_raw_lo) + ); + wire [dword_width_gp-1:0] sp_raw_lo = {{word_width_gp{1'b1}}, dp2sp_raw_lo}; + + logic [dword_width_gp-1:0] dp_raw_lo; + recFNToFN + #(.expWidth(dp_exp_width_gp) + ,.sigWidth(dp_sig_width_gp) + ) + out_dp_rec + (.in(dp_rec) + ,.out(dp_raw_lo) + ); + + assign val_o = raw_i + ? (reg_cast_i.tag == e_fp_dp) + ? dp_raw_lo + : sp_raw_lo + : (reg_cast_i.tag != tag_i) + ? dp_canonical_rec + : dp_rec; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_instr_decoder.sv b/designs/black-parrot/src/bp/bp_be_instr_decoder.sv new file mode 100644 index 0000000..ef1ecea --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_instr_decoder.sv @@ -0,0 +1,822 @@ +/** + * + * Name: + * bp_be_instr_decode.v + * + * Description: + * BlackParrot instruction decoder for translating RISC-V instructions into pipeline control + * signals. Currently supports most of rv64i with the exception of fences and csrs. + * + * Notes: + * We may want to break this up into a decoder for each standard extension. + * Each pipe may need different signals. Use a union in decode_s to save bits? + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_instr_decoder + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + // Generated parameters + , localparam decode_width_lp = $bits(bp_be_decode_s) + ) + (input [preissue_pkt_width_lp-1:0] preissue_pkt_i + , input [decode_info_width_lp-1:0] decode_info_i + + , output logic [decode_width_lp-1:0] decode_o + , output logic illegal_instr_o + , output logic ecall_m_o + , output logic ecall_s_o + , output logic ecall_u_o + , output logic ebreak_o + , output logic dbreak_o + , output logic dret_o + , output logic mret_o + , output logic sret_o + , output logic wfi_o + , output logic sfence_vma_o + , output logic fencei_o + , output logic csrw_o + + , output logic [dword_width_gp-1:0] imm_o + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + `bp_cast_i(bp_be_preissue_pkt_s, preissue_pkt); + `bp_cast_i(bp_be_decode_info_s, decode_info); + `bp_cast_o(bp_be_decode_s, decode); + + rv64_instr_fmatype_s instr; + assign instr = preissue_pkt_cast_i.instr; + + // Decode logic + always_comb + begin + decode_cast_o = '0; + + decode_cast_o.irs1_r_v = preissue_pkt_cast_i.irs1_v; + decode_cast_o.irs2_r_v = preissue_pkt_cast_i.irs2_v; + decode_cast_o.frs1_r_v = preissue_pkt_cast_i.frs1_v; + decode_cast_o.frs2_r_v = preissue_pkt_cast_i.frs2_v; + decode_cast_o.frs3_r_v = preissue_pkt_cast_i.frs3_v; + + illegal_instr_o = '0; + ecall_m_o = '0; + ecall_s_o = '0; + ecall_u_o = '0; + ebreak_o = '0; + dbreak_o = '0; + dret_o = '0; + mret_o = '0; + sret_o = '0; + wfi_o = '0; + sfence_vma_o = '0; + fencei_o = '0; + csrw_o = '0; + + imm_o = '0; + + unique casez (instr.opcode) + `RV64_OP_OP, `RV64_OP_32_OP: + begin + if (instr inside {`RV64_MUL, `RV64_MULW}) + decode_cast_o.pipe_mul_v = 1'b1; + else if (instr inside {`RV64_MULH, `RV64_MULHSU, `RV64_MULHU + ,`RV64_DIV, `RV64_DIVU, `RV64_DIVW, `RV64_DIVUW + ,`RV64_REM, `RV64_REMU, `RV64_REMW, `RV64_REMUW + }) + begin + decode_cast_o.pipe_long_v = 1'b1; + decode_cast_o.score_v = 1'b1; + end + else + decode_cast_o.pipe_int_v = 1'b1; + + // The writeback for long latency ops comes out of band + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + if (instr.opcode == `RV64_OP_32_OP) + begin + decode_cast_o.irs1_tag = e_int_word; + decode_cast_o.irs2_tag = instr inside {`RV64_ADDUW, `RV64_SH1ADDUW, `RV64_SH2ADDUW, `RV64_SH3ADDUW} ? e_int_dword : e_int_word; + decode_cast_o.ird_tag = instr inside {`RV64_ADDUW, `RV64_SH1ADDUW, `RV64_SH2ADDUW, `RV64_SH3ADDUW} ? e_int_dword : e_int_word; + end + + if (instr inside {`RV64_ZEXTH}) + decode_cast_o.irs1_tag = e_int_hword; + + if (instr inside {`RV64_MULHU,`RV64_DIVU, `RV64_DIVUW, `RV64_REMU, `RV64_REMUW, `RV64_SRL, `RV64_SRLW, `RV64_ADDUW + ,`RV64_SH1ADDUW, `RV64_SH2ADDUW, `RV64_SH3ADDUW, `RV64_ZEXTH + ,`RV64_ROR, `RV64_RORW, `RV64_ROL, `RV64_ROLW}) + decode_cast_o.irs1_unsigned = 1'b1; + + if (instr inside {`RV64_MULHSU, `RV64_MULHU, `RV64_DIVU, `RV64_DIVUW, `RV64_REMU, `RV64_REMUW}) + decode_cast_o.irs2_unsigned = 1'b1; + + unique casez (instr) + `RV64_ADD, `RV64_ADDW , `RV64_ADDUW, + `RV64_SUB, `RV64_SUBW , + `RV64_SLL, `RV64_SLLW , + `RV64_SRL, `RV64_SRLW , + `RV64_SH1ADD, `RV64_SH1ADDUW, + `RV64_SH2ADD, `RV64_SH2ADDUW, + `RV64_SH3ADD, `RV64_SH3ADDUW, + `RV64_ZEXTH , + `RV64_SRA, `RV64_SRAW : decode_cast_o.fu_op = e_int_op_add; + `RV64_SLT : decode_cast_o.fu_op = e_int_op_slt; + `RV64_SLTU : decode_cast_o.fu_op = e_int_op_sltu; + `RV64_MIN : decode_cast_o.fu_op = e_int_op_min; + `RV64_MINU : decode_cast_o.fu_op = e_int_op_minu; + `RV64_MAX : decode_cast_o.fu_op = e_int_op_max; + `RV64_MAXU : decode_cast_o.fu_op = e_int_op_maxu; + `RV64_XOR, `RV64_XNOR : decode_cast_o.fu_op = e_int_op_xor; + `RV64_ROL, `RV64_ROLW , + `RV64_ROR, `RV64_RORW , + `RV64_OR, `RV64_ORN : decode_cast_o.fu_op = e_int_op_or; + `RV64_AND, `RV64_ANDN : decode_cast_o.fu_op = e_int_op_and; + `RV64_BCLR : decode_cast_o.fu_op = e_int_op_bclr; + `RV64_BEXT : decode_cast_o.fu_op = e_int_op_bext; + `RV64_BINV : decode_cast_o.fu_op = e_int_op_binv; + `RV64_BSET : decode_cast_o.fu_op = e_int_op_bset; + + `RV64_MUL, `RV64_MULW : decode_cast_o.fu_op = e_fma_op_imul; + `RV64_MULH : decode_cast_o.fu_op = e_long_op_mulh; + `RV64_MULHSU : decode_cast_o.fu_op = e_long_op_mulhsu; + `RV64_MULHU : decode_cast_o.fu_op = e_long_op_mulhu; + `RV64_DIV, `RV64_DIVW : decode_cast_o.fu_op = e_long_op_div; + `RV64_DIVU, `RV64_DIVUW : decode_cast_o.fu_op = e_long_op_divu; + `RV64_REM, `RV64_REMW : decode_cast_o.fu_op = e_long_op_rem; + `RV64_REMU, `RV64_REMUW : decode_cast_o.fu_op = e_long_op_remu; + default : illegal_instr_o = 1'b1; + endcase + + if (instr inside {`RV64_SUB, `RV64_SUBW, `RV64_SLT, `RV64_SLTU, `RV64_MIN, `RV64_MINU, `RV64_MAX, `RV64_MAXU}) + begin + decode_cast_o.src1_sel = e_src1_is_rs1; + decode_cast_o.src2_sel = e_src2_is_rs2n; + decode_cast_o.carryin = 1'b1; + end + + if (instr inside {`RV64_ANDN, `RV64_ORN, `RV64_XNOR}) + begin + decode_cast_o.src2_sel = e_src2_is_rs2n; + end + + if (instr inside {`RV64_SLL, `RV64_SLLW}) + begin + decode_cast_o.src1_sel = e_src1_is_rs1_lsh; + decode_cast_o.src2_sel = e_src2_is_zero; + end + + if (instr inside {`RV64_SRL, `RV64_SRLW, `RV64_SRA, `RV64_SRAW}) + begin + decode_cast_o.src1_sel = e_src1_is_zero; + decode_cast_o.src2_sel = e_src2_is_rs1_rsh; + end + + if (instr inside {`RV64_ROL, `RV64_ROLW}) + begin + decode_cast_o.src1_sel = e_src1_is_rs1_lsh; + decode_cast_o.src2_sel = e_src2_is_rs1_rshn; + end + + if (instr inside {`RV64_ROR, `RV64_RORW}) + begin + decode_cast_o.src1_sel = e_src1_is_rs1_lshn; + decode_cast_o.src2_sel = e_src2_is_rs1_rsh; + end + + if (instr inside {`RV64_ZEXTH}) + begin + decode_cast_o.src2_sel = e_src2_is_zero; + end + + if (instr inside {`RV64_SH1ADD, `RV64_SH1ADDUW, `RV64_SH2ADD, `RV64_SH2ADDUW, `RV64_SH3ADD, `RV64_SH3ADDUW}) + begin + decode_cast_o.src1_sel = e_src1_is_rs1_lsh; + end + end + `RV64_OP_IMM_OP, `RV64_OP_IMM_32_OP: + begin + decode_cast_o.pipe_int_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + if (instr.opcode == `RV64_OP_IMM_32_OP) + begin + decode_cast_o.irs1_tag = e_int_word; + decode_cast_o.ird_tag = instr inside {`RV64_SLLIUW} ? e_int_dword : e_int_word; + end + + unique casez (instr) + `RV64_SEXTB: decode_cast_o.irs1_tag = e_int_byte; + `RV64_SEXTH: decode_cast_o.irs1_tag = e_int_hword; + default: begin end + endcase + + unique casez (instr) + `RV64_ADDI, `RV64_ADDIW , + `RV64_SLLI, `RV64_SLLIW , `RV64_SLLIUW, + `RV64_SRLI, `RV64_SRLIW , + `RV64_SEXTB, `RV64_SEXTH, + `RV64_SRAI, `RV64_SRAIW : decode_cast_o.fu_op = e_int_op_add; + `RV64_SLTI : decode_cast_o.fu_op = e_int_op_slt; + `RV64_SLTIU : decode_cast_o.fu_op = e_int_op_sltu; + `RV64_XORI : decode_cast_o.fu_op = e_int_op_xor; + `RV64_RORI, `RV64_RORIW , + `RV64_ORI : decode_cast_o.fu_op = e_int_op_or; + `RV64_ANDI : decode_cast_o.fu_op = e_int_op_and; + `RV64_CPOP, `RV64_CPOPW : decode_cast_o.fu_op = e_int_op_cpop; + `RV64_CTZ, `RV64_CTZW , + `RV64_CLZ, `RV64_CLZW : decode_cast_o.fu_op = e_int_op_clz; + `RV64_ORCB : decode_cast_o.fu_op = e_int_op_orcb; + `RV64_REV8 : decode_cast_o.fu_op = e_int_op_rev8; + `RV64_BCLRI : decode_cast_o.fu_op = e_int_op_bclr; + `RV64_BEXTI : decode_cast_o.fu_op = e_int_op_bext; + `RV64_BINVI : decode_cast_o.fu_op = e_int_op_binv; + `RV64_BSETI : decode_cast_o.fu_op = e_int_op_bset; + default : illegal_instr_o = 1'b1; + endcase + + if (instr inside {`RV64_CTZ, `RV64_CTZW}) + begin + decode_cast_o.src1_sel = e_src1_is_rs1_rev; + end + + if (instr inside {`RV64_SRLI, `RV64_SRLIW, `RV64_SLLIUW, `RV64_CPOPW, `RV64_CLZW, `RV64_CTZW}) + begin + decode_cast_o.irs1_unsigned = 1'b1; + decode_cast_o.src2_sel = e_src2_is_zero; + end + + if (instr inside {`RV64_SEXTB, `RV64_SEXTH}) + begin + decode_cast_o.src2_sel = e_src2_is_zero; + end + + if (instr inside {`RV64_SLLI, `RV64_SLLIW, `RV64_SLLIUW}) + begin + decode_cast_o.src1_sel = e_src1_is_rs1_lsh; + decode_cast_o.src2_sel = e_src2_is_zero; + end + + if (instr inside {`RV64_RORI, `RV64_RORIW}) + begin + decode_cast_o.irs1_unsigned = 1'b1; + decode_cast_o.src1_sel = e_src1_is_rs1_lshn; + decode_cast_o.src2_sel = e_src2_is_rs1_rsh; + end + + if (instr inside {`RV64_SRLI, `RV64_SRLIW, `RV64_SRAI, `RV64_SRAIW}) + begin + decode_cast_o.src1_sel = e_src1_is_zero; + decode_cast_o.src2_sel = e_src2_is_rs1_rsh; + end + + if (instr inside {`RV64_SLTI, `RV64_SLTIU}) + begin + decode_cast_o.carryin = 1'b1; + end + end + `RV64_LUI_OP: + begin + decode_cast_o.pipe_int_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_int_op_add; + decode_cast_o.src1_sel = e_src1_is_zero; + end + `RV64_AUIPC_OP: + begin + decode_cast_o.pipe_int_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_int_op_add; + end + `RV64_JAL_OP, `RV64_JALR_OP: + begin + decode_cast_o.pipe_int_v = 1'b1; + decode_cast_o.j_v = instr inside {`RV64_JAL}; + decode_cast_o.jr_v = instr inside {`RV64_JALR}; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_int_op_add; + + illegal_instr_o = ~(instr inside {`RV64_JAL, `RV64_JALR}); + end + `RV64_BRANCH_OP: + begin + decode_cast_o.pipe_int_v = 1'b1; + decode_cast_o.br_v = 1'b1; + unique casez (instr) + `RV64_BEQ : decode_cast_o.fu_op = e_int_op_eq; + `RV64_BNE : decode_cast_o.fu_op = e_int_op_ne; + `RV64_BLT : decode_cast_o.fu_op = e_int_op_slt; + `RV64_BGE : decode_cast_o.fu_op = e_int_op_sge; + `RV64_BLTU : decode_cast_o.fu_op = e_int_op_sltu; + `RV64_BGEU : decode_cast_o.fu_op = e_int_op_sgeu; + default : illegal_instr_o = 1'b1; + endcase + + decode_cast_o.src1_sel = e_src1_is_rs1; + decode_cast_o.src2_sel = e_src2_is_rs2n; + decode_cast_o.carryin = 1'b1; + end + `RV64_LOAD_OP: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.spec_w_v = 1'b1; + decode_cast_o.score_v = 1'b1; + decode_cast_o.dcache_r_v = 1'b1; + decode_cast_o.mem_v = 1'b1; + unique casez (instr) + `RV64_LB : decode_cast_o.fu_op = e_dcache_op_lb; + `RV64_LH : decode_cast_o.fu_op = e_dcache_op_lh; + `RV64_LW : decode_cast_o.fu_op = e_dcache_op_lw; + `RV64_LBU: decode_cast_o.fu_op = e_dcache_op_lbu; + `RV64_LHU: decode_cast_o.fu_op = e_dcache_op_lhu; + `RV64_LWU: decode_cast_o.fu_op = e_dcache_op_lwu; + `RV64_LD : decode_cast_o.fu_op = e_dcache_op_ld; + default : illegal_instr_o = 1'b1; + endcase + end + `RV64_FLOAD_OP: + begin + decode_cast_o.pipe_mem_final_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fmove_v = 1'b1; + decode_cast_o.spec_w_v = 1'b1; + decode_cast_o.score_v = 1'b1; + decode_cast_o.dcache_r_v = 1'b1; + decode_cast_o.mem_v = 1'b1; + if (instr inside {`RV64_FL_W}) + decode_cast_o.frd_tag = e_fp_sp; + + illegal_instr_o = ~decode_info_cast_i.fpu_en; + + unique casez (instr) + `RV64_FL_W: decode_cast_o.fu_op = e_dcache_op_flw; + `RV64_FL_D: decode_cast_o.fu_op = e_dcache_op_fld; + default: illegal_instr_o = 1'b1; + endcase + end + `RV64_STORE_OP: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.dcache_w_v = 1'b1; + decode_cast_o.mem_v = 1'b1; + unique casez (instr) + `RV64_SB : decode_cast_o.fu_op = e_dcache_op_sb; + `RV64_SH : decode_cast_o.fu_op = e_dcache_op_sh; + `RV64_SW : decode_cast_o.fu_op = e_dcache_op_sw; + `RV64_SD : decode_cast_o.fu_op = e_dcache_op_sd; + default : illegal_instr_o = 1'b1; + endcase + end + `RV64_FSTORE_OP: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.dcache_w_v = 1'b1; + decode_cast_o.fmove_v = 1'b1; + decode_cast_o.mem_v = 1'b1; + + illegal_instr_o = ~decode_info_cast_i.fpu_en; + + unique casez (instr) + `RV64_FS_W : decode_cast_o.fu_op = e_dcache_op_fsw; + `RV64_FS_D : decode_cast_o.fu_op = e_dcache_op_fsd; + default: illegal_instr_o = 1'b1; + endcase + end + `RV64_MISC_MEM_OP: + begin + unique casez (instr) + `RV64_FENCE : + begin + decode_cast_o.fence_v = 1'b1; + end + `RV64_FENCE_I : + begin + decode_cast_o.fence_v = 1'b1; + decode_cast_o.pipe_mem_early_v = !dcache_features_p[e_cfg_coherent]; + decode_cast_o.fu_op = e_dcache_op_clean; + fencei_o = 1'b1; + end + `RV64_CMO_INVAL_ALL: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.fu_op = e_dcache_op_inval; + // TODO: Implement for multicore + illegal_instr_o = dcache_features_p[e_cfg_coherent]; + end + `RV64_CMO_CLEAN_ALL: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.fu_op = e_dcache_op_clean; + // TODO: Implement for multicore + illegal_instr_o = dcache_features_p[e_cfg_coherent]; + end + `RV64_CMO_FLUSH_ALL: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.fu_op = e_dcache_op_flush; + // TODO: Implement for multicore + illegal_instr_o = dcache_features_p[e_cfg_coherent]; + end + `RV64_CBO_ZERO: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.dcache_cbo_v = 1'b1; + decode_cast_o.dcache_w_v = 1'b1; + decode_cast_o.fu_op = e_dcache_op_bzero; + end + `RV64_CBO_CLEAN: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.dcache_cbo_v = 1'b1; + decode_cast_o.fu_op = e_dcache_op_bclean; + // TODO: Implement for ucode + illegal_instr_o = (cce_type_p == e_cce_ucode); + end + `RV64_CBO_INVAL: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.dcache_cbo_v = 1'b1; + decode_cast_o.fu_op = e_dcache_op_binval; + // TODO: Implement for ucode + illegal_instr_o = (cce_type_p == e_cce_ucode); + end + `RV64_CBO_FLUSH: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.dcache_cbo_v = 1'b1; + decode_cast_o.fu_op = e_dcache_op_bflush; + // TODO: Implement for ucode + illegal_instr_o = (cce_type_p == e_cce_ucode); + end + `RV64_CMO_PREFETCHI: + begin + // NOP for now + end + `RV64_CMO_PREFETCHR: + begin + // NOP for now + end + `RV64_CMO_PREFETCHW: + begin + // NOP for now + end + default : illegal_instr_o = 1'b1; + endcase + end + `RV64_SYSTEM_OP: + begin + decode_cast_o.pipe_sys_v = 1'b1; + unique casez (instr) + `RV64_ECALL: + begin + ecall_m_o = decode_info_cast_i.m_mode; + ecall_s_o = decode_info_cast_i.s_mode; + ecall_u_o = decode_info_cast_i.u_mode; + end + `RV64_EBREAK: + begin + dbreak_o = decode_info_cast_i.debug_mode + | (decode_info_cast_i.ebreakm & decode_info_cast_i.m_mode) + | (decode_info_cast_i.ebreaks & decode_info_cast_i.s_mode) + | (decode_info_cast_i.ebreaku & decode_info_cast_i.u_mode); + ebreak_o = ~dbreak_o; + end + `RV64_DRET: + begin + illegal_instr_o = ~decode_info_cast_i.debug_mode; + dret_o = ~illegal_instr_o; + end + `RV64_MRET: + begin + illegal_instr_o = (decode_info_cast_i.s_mode | decode_info_cast_i.u_mode); + mret_o = ~illegal_instr_o; + end + `RV64_SRET: + begin + illegal_instr_o = decode_info_cast_i.u_mode | (decode_info_cast_i.tsr & decode_info_cast_i.s_mode); + sret_o = ~illegal_instr_o; + end + `RV64_WFI: + begin + // WFI operates as NOP in debug mode + illegal_instr_o = decode_info_cast_i.tw; + wfi_o = ~illegal_instr_o & ~decode_info_cast_i.debug_mode; + end + `RV64_SFENCE_VMA: + begin + decode_cast_o.fence_v = 1'b1; + illegal_instr_o = (decode_info_cast_i.s_mode & decode_info_cast_i.tvm) | decode_info_cast_i.u_mode; + sfence_vma_o = ~illegal_instr_o; + end + `RV64_CSRRW, `RV64_CSRRWI, `RV64_CSRRS, `RV64_CSRRSI, `RV64_CSRRC, `RV64_CSRRCI: + begin + decode_cast_o.csr_w_v = instr inside {`RV64_CSRRW, `RV64_CSRRWI} || (instr.rs1_addr != '0); + decode_cast_o.csr_r_v = ~(instr inside {`RV64_CSRRW, `RV64_CSRRWI}) || (instr.rd_addr != '0); + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + csrw_o = decode_cast_o.csr_w_v; + + casez (instr[31-:12]) + `CSR_ADDR_FCSR + ,`CSR_ADDR_FFLAGS + ,`CSR_ADDR_FRM : illegal_instr_o = !decode_info_cast_i.fpu_en; + `CSR_ADDR_CYCLE : illegal_instr_o = !decode_info_cast_i.cycle_en; + `CSR_ADDR_INSTRET : illegal_instr_o = !decode_info_cast_i.instret_en; + `CSR_ADDR_SATP : illegal_instr_o = decode_info_cast_i.s_mode & decode_info_cast_i.tvm; + {12'b11??_????_????}: illegal_instr_o = csrw_o; + {12'b??01_????_????}: illegal_instr_o = decode_info_cast_i.u_mode; + {12'b??10_????_????}: illegal_instr_o = decode_info_cast_i.s_mode | decode_info_cast_i.u_mode; + {12'b??11_????_????}: illegal_instr_o = decode_info_cast_i.s_mode | decode_info_cast_i.u_mode; + endcase + end + default: illegal_instr_o = 1'b1; + endcase + end + `RV64_FP_OP: + begin + illegal_instr_o = ~decode_info_cast_i.fpu_en; + + if (instr inside {`RV64_FSGNJ_S, `RV64_FSGNJN_S, `RV64_FSGNJX_S + ,`RV64_FMIN_S, `RV64_FMAX_S, `RV64_FEQ_S, `RV64_FLT_S, `RV64_FLE_S, `RV64_FCLASS_S + ,`RV64_FADD_S, `RV64_FSUB_S, `RV64_FMUL_S, `RV64_FDIV_S, `RV64_FSQRT_S + }) + begin + decode_cast_o.frs1_tag = e_fp_sp; + decode_cast_o.frs2_tag = e_fp_sp; + decode_cast_o.frd_tag = e_fp_sp; + end + + unique casez (instr) + `RV64_FCVT_SD, `RV64_FCVT_DS: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_f2f; + decode_cast_o.frs1_tag = instr inside {`RV64_FCVT_SD} ? e_fp_dp : e_fp_sp; + decode_cast_o.frs2_tag = instr inside {`RV64_FCVT_SD} ? e_fp_dp : e_fp_sp; + decode_cast_o.frd_tag = instr inside {`RV64_FCVT_DS} ? e_fp_dp : e_fp_sp; + end + `RV64_FCVT_WS, `RV64_FCVT_LS, `RV64_FCVT_WD, `RV64_FCVT_LD: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_aux_op_f2i; + decode_cast_o.frs1_tag = instr inside {`RV64_FCVT_WS, `RV64_FCVT_LS} ? e_fp_sp : e_fp_dp; + decode_cast_o.ird_tag = instr inside {`RV64_FCVT_WS, `RV64_FCVT_WD} ? e_int_word : e_int_dword; + end + `RV64_FCVT_WUS, `RV64_FCVT_LUS, `RV64_FCVT_WUD, `RV64_FCVT_LUD: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_aux_op_f2iu; + decode_cast_o.frs1_tag = instr inside {`RV64_FCVT_WUS, `RV64_FCVT_LUS} ? e_fp_sp : e_fp_dp; + decode_cast_o.ird_tag = instr inside {`RV64_FCVT_WUS, `RV64_FCVT_WUD} ? e_int_word : e_int_dword; + end + `RV64_FCVT_SW, `RV64_FCVT_SL, `RV64_FCVT_DW, `RV64_FCVT_DL: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_i2f; + decode_cast_o.irs1_tag = instr inside {`RV64_FCVT_SW, `RV64_FCVT_DW} ? e_int_word : e_int_dword; + decode_cast_o.frd_tag = instr inside {`RV64_FCVT_SW, `RV64_FCVT_SL} ? e_fp_sp : e_fp_dp; + end + `RV64_FCVT_SWU, `RV64_FCVT_SLU, `RV64_FCVT_DWU, `RV64_FCVT_DLU: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.irs1_unsigned = 1'b1; + decode_cast_o.fu_op = e_aux_op_iu2f; + decode_cast_o.irs1_tag = instr inside {`RV64_FCVT_SWU, `RV64_FCVT_DWU} ? e_int_word : e_int_dword; + decode_cast_o.frd_tag = instr inside {`RV64_FCVT_SWU, `RV64_FCVT_SLU} ? e_fp_sp : e_fp_dp; + end + `RV64_FMV_XW, `RV64_FMV_XD: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fmove_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_fmvi; + decode_cast_o.frs1_tag = instr inside {`RV64_FMV_XW} ? e_fp_sp : e_fp_dp; + decode_cast_o.ird_tag = instr inside {`RV64_FMV_XW} ? e_int_word : e_int_dword; + end + `RV64_FMV_WX, `RV64_FMV_DX: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fmove_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_imvf; + decode_cast_o.irs1_tag = instr inside {`RV64_FMV_WX} ? e_int_word : e_int_dword; + decode_cast_o.frd_tag = instr inside {`RV64_FMV_WX} ? e_fp_sp : e_fp_dp; + end + `RV64_FSGNJ_S, `RV64_FSGNJ_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fmove_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_fsgnj; + end + `RV64_FSGNJN_S, `RV64_FSGNJN_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fmove_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_fsgnjn; + end + `RV64_FSGNJX_S, `RV64_FSGNJX_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fmove_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_fsgnjx; + end + `RV64_FMIN_S, `RV64_FMIN_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_fmin; + end + `RV64_FMAX_S, `RV64_FMAX_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fu_op = e_aux_op_fmax; + end + `RV64_FEQ_S, `RV64_FEQ_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_aux_op_feq; + end + `RV64_FLT_S, `RV64_FLT_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_aux_op_flt; + end + `RV64_FLE_S, `RV64_FLE_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_aux_op_fle; + end + `RV64_FCLASS_S, `RV64_FCLASS_D: + begin + decode_cast_o.pipe_aux_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.fu_op = e_aux_op_fclass; + end + `RV64_FADD_S, `RV64_FADD_D: + begin + decode_cast_o.pipe_fma_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fu_op = e_fma_op_fadd; + end + `RV64_FSUB_S, `RV64_FSUB_D: + begin + decode_cast_o.pipe_fma_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fu_op = e_fma_op_fsub; + end + `RV64_FMUL_S, `RV64_FMUL_D: + begin + decode_cast_o.pipe_fma_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.fu_op = e_fma_op_fmul; + end + `RV64_FDIV_S, `RV64_FDIV_D: + begin + decode_cast_o.pipe_long_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.score_v = 1'b1; + decode_cast_o.fu_op = e_long_op_fdiv; + end + `RV64_FSQRT_S, `RV64_FSQRT_D: + begin + decode_cast_o.pipe_long_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + decode_cast_o.score_v = 1'b1; + decode_cast_o.fu_op = e_long_op_fsqrt; + end + default: illegal_instr_o = 1'b1; + endcase + end + + + `RV64_FMADD_OP, `RV64_FMSUB_OP, `RV64_FNMSUB_OP, `RV64_FNMADD_OP: + begin + decode_cast_o.pipe_fma_v = 1'b1; + decode_cast_o.frf_w_v = 1'b1; + if (instr.fmt == e_fmt_single) + begin + decode_cast_o.frs1_tag = e_fp_sp; + decode_cast_o.frs2_tag = e_fp_sp; + decode_cast_o.frs3_tag = e_fp_sp; + decode_cast_o.frd_tag = e_fp_sp; + end + + casez (instr.opcode) + `RV64_FMADD_OP : decode_cast_o.fu_op = e_fma_op_fmadd; + `RV64_FMSUB_OP : decode_cast_o.fu_op = e_fma_op_fmsub; + `RV64_FNMSUB_OP: decode_cast_o.fu_op = e_fma_op_fnmsub; + `RV64_FNMADD_OP: decode_cast_o.fu_op = e_fma_op_fnmadd; + default: decode_cast_o.fu_op = e_fma_op_fmadd; + endcase + + illegal_instr_o = ~decode_info_cast_i.fpu_en; + end + + `RV64_AMO_OP: + begin + decode_cast_o.pipe_mem_early_v = 1'b1; + decode_cast_o.irf_w_v = (instr.rd_addr != '0); + decode_cast_o.spec_w_v = 1'b1; + decode_cast_o.score_v = 1'b1; + decode_cast_o.dcache_r_v = (instr inside {`RV64_LRD, `RV64_LRW}); + decode_cast_o.dcache_w_v = ~(instr inside {`RV64_LRD, `RV64_LRW}); + decode_cast_o.mem_v = 1'b1; + // Note: could do a more efficent decoding here by having atomic be a flag + // And having the op simply taken from funct3 + unique casez (instr) + `RV64_LRD : decode_cast_o.fu_op = e_dcache_op_lrd; + `RV64_LRW : decode_cast_o.fu_op = e_dcache_op_lrw; + `RV64_SCD : decode_cast_o.fu_op = e_dcache_op_scd; + `RV64_SCW : decode_cast_o.fu_op = e_dcache_op_scw; + `RV64_AMOSWAPD : decode_cast_o.fu_op = e_dcache_op_amoswapd; + `RV64_AMOSWAPW : decode_cast_o.fu_op = e_dcache_op_amoswapw; + `RV64_AMOADDD : decode_cast_o.fu_op = e_dcache_op_amoaddd; + `RV64_AMOADDW : decode_cast_o.fu_op = e_dcache_op_amoaddw; + `RV64_AMOXORD : decode_cast_o.fu_op = e_dcache_op_amoxord; + `RV64_AMOXORW : decode_cast_o.fu_op = e_dcache_op_amoxorw; + `RV64_AMOANDD : decode_cast_o.fu_op = e_dcache_op_amoandd; + `RV64_AMOANDW : decode_cast_o.fu_op = e_dcache_op_amoandw; + `RV64_AMOORD : decode_cast_o.fu_op = e_dcache_op_amoord; + `RV64_AMOORW : decode_cast_o.fu_op = e_dcache_op_amoorw; + `RV64_AMOMIND : decode_cast_o.fu_op = e_dcache_op_amomind; + `RV64_AMOMINW : decode_cast_o.fu_op = e_dcache_op_amominw; + `RV64_AMOMAXD : decode_cast_o.fu_op = e_dcache_op_amomaxd; + `RV64_AMOMAXW : decode_cast_o.fu_op = e_dcache_op_amomaxw; + `RV64_AMOMINUD : decode_cast_o.fu_op = e_dcache_op_amominud; + `RV64_AMOMINUW : decode_cast_o.fu_op = e_dcache_op_amominuw; + `RV64_AMOMAXUD : decode_cast_o.fu_op = e_dcache_op_amomaxud; + `RV64_AMOMAXUW : decode_cast_o.fu_op = e_dcache_op_amomaxuw; + default : illegal_instr_o = 1'b1; + endcase + + // Detect AMO support level + unique casez (instr) + `RV64_LRD, `RV64_LRW, `RV64_SCD, `RV64_SCW: + illegal_instr_o = + ~|{dcache_features_p[e_cfg_lr_sc], l2_features_p[e_cfg_lr_sc]}; + `RV64_AMOSWAPD, `RV64_AMOSWAPW: + illegal_instr_o = + ~|{dcache_features_p[e_cfg_amo_swap], l2_features_p[e_cfg_amo_swap]}; + `RV64_AMOANDD, `RV64_AMOANDW + ,`RV64_AMOORD, `RV64_AMOORW + ,`RV64_AMOXORD, `RV64_AMOXORW: + illegal_instr_o = + ~|{dcache_features_p[e_cfg_amo_fetch_logic], l2_features_p[e_cfg_amo_fetch_logic]}; + `RV64_AMOADDD, `RV64_AMOADDW + ,`RV64_AMOMIND, `RV64_AMOMINW, `RV64_AMOMAXD, `RV64_AMOMAXW + ,`RV64_AMOMINUD, `RV64_AMOMINUW, `RV64_AMOMAXUD, `RV64_AMOMAXUW: + illegal_instr_o = + ~|{dcache_features_p[e_cfg_amo_fetch_arithmetic], l2_features_p[e_cfg_amo_fetch_arithmetic]}; + default: begin end + endcase + end + default : illegal_instr_o = 1'b1; + endcase + + // Immediate extraction + // This may be overwritten by exception injection + unique casez (instr.opcode) + `RV64_LUI_OP, `RV64_AUIPC_OP: + imm_o = `rv64_signext_u_imm(instr); + `RV64_JAL_OP: + imm_o = `rv64_signext_j_imm(instr); + `RV64_BRANCH_OP: + imm_o = `rv64_signext_b_imm(instr); + `RV64_STORE_OP, `RV64_FSTORE_OP: + imm_o = `rv64_signext_s_imm(instr); + `RV64_JALR_OP, `RV64_LOAD_OP, `RV64_OP_IMM_OP, `RV64_OP_IMM_32_OP, `RV64_FLOAD_OP: + imm_o = `rv64_signext_i_imm(instr); + //`RV64_AMO_OP: + default: imm_o = '0; + endcase + + // Instruction-specific overrides + unique casez (instr) + `RV64_SLTI, `RV64_SLTIU : imm_o = ~`rv64_signext_i_imm(instr); + `RV64_SH1ADD, `RV64_SH1ADDUW: imm_o = 3'd1; + `RV64_SH2ADD, `RV64_SH2ADDUW: imm_o = 3'd2; + `RV64_SH3ADD, `RV64_SH3ADDUW: imm_o = 3'd3; + default: begin end + endcase + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_int_box.sv b/designs/black-parrot/src/bp/bp_be_int_box.sv new file mode 100644 index 0000000..3319221 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_int_box.sv @@ -0,0 +1,38 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_int_box + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input [dword_width_gp-1:0] raw_i + , input [$bits(bp_be_int_tag_e)-1:0] tag_i + , input unsigned_i + , output logic [dpath_width_gp-1:0] reg_o + ); + + `bp_cast_o(bp_be_int_reg_s, reg); + + logic sig; + always_comb + case (tag_i) + e_int_byte : sig = raw_i[7]; + e_int_hword: sig = raw_i[15]; + e_int_word : sig = raw_i[31]; + // e_int_dword + default: sig = raw_i[63]; + endcase + + always_comb + begin + reg_cast_o.tag = tag_i; + reg_cast_o.val = raw_i; + if (tag_i != e_int_dword) + reg_cast_o.val[63] = sig & ~unsigned_i; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_int_unbox.sv b/designs/black-parrot/src/bp/bp_be_int_unbox.sv new file mode 100644 index 0000000..317dab2 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_int_unbox.sv @@ -0,0 +1,55 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_int_unbox + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input [dpath_width_gp-1:0] reg_i + , input [$bits(bp_be_int_tag_e)-1:0] tag_i + , input unsigned_i + , output logic [int_rec_width_gp-1:0] val_o + ); + + `bp_cast_i(bp_be_int_reg_s, reg); + wire [dword_width_gp-1:0] val = reg_cast_i.val; + + logic [dword_width_gp-1:0] raw; + always_comb + case (reg_cast_i.tag) + e_int_byte : raw = {{56{val[63]}}, val[0+: 8]}; + e_int_hword: raw = {{48{val[63]}}, val[0+:16]}; + e_int_word : raw = {{32{val[63]}}, val[0+:32]}; + // e_int_dword + default: raw = {{0{val[63]}}, val[0+:64]}; + endcase + + wire sigbox = tag_i >= reg_cast_i.tag; + always_comb + unique casez ({unsigned_i, sigbox, tag_i}) + // Unsigned output always zero extends + {2'b1?, e_int_dword}: val_o = {{ 1{1'b0 }}, raw[0+:64]}; + {2'b1?, e_int_word }: val_o = {{33{1'b0 }}, raw[0+:32]}; + {2'b1?, e_int_hword}: val_o = {{49{1'b0 }}, raw[0+:16]}; + {2'b1?, e_int_byte }: val_o = {{57{1'b0 }}, raw[0+: 8]}; + + // sigboxes uses the wider sign extension + {2'b01, e_int_dword}: val_o = {{ 1{raw[63]}}, raw[0+:64]}; + {2'b01, e_int_word }: val_o = {{33{raw[31]}}, raw[0+:32]}; + {2'b01, e_int_hword}: val_o = {{49{raw[15]}}, raw[0+:16]}; + {2'b01, e_int_byte }: val_o = {{57{raw[ 7]}}, raw[0+: 8]}; + + // Valid boxes use the raw sign extension + {2'b00, e_int_dword}: val_o = {{ 1{raw[63]}}, raw[0+:64]}; + {2'b00, e_int_word }: val_o = {{33{raw[63]}}, raw[0+:32]}; + {2'b00, e_int_hword}: val_o = {{49{raw[63]}}, raw[0+:16]}; + {2'b00, e_int_byte }: val_o = {{57{raw[63]}}, raw[0+: 8]}; + + default: begin end + endcase + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_issue_queue.sv b/designs/black-parrot/src/bp/bp_be_issue_queue.sv new file mode 100644 index 0000000..e47c63e --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_issue_queue.sv @@ -0,0 +1,318 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_issue_queue + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + , localparam entry_cinstr_gp = 2**fetch_sel_p + , localparam op_ptr_width_lp = `BSG_WIDTH(entry_cinstr_gp) + ) + (input clk_i + , input reset_i + + , input en_i + , input clr_i + , input roll_i + , input read_i + , input [op_ptr_width_lp-1:0] read_cnt_i + , input [op_ptr_width_lp-1:0] read_size_i + , input cmt_i + , input [op_ptr_width_lp-1:0] cmt_cnt_i + , input [op_ptr_width_lp-1:0] cmt_size_i + + , input [fe_queue_width_lp-1:0] fe_queue_i + , input fe_queue_v_i + , output logic fe_queue_ready_and_o + + , input [decode_info_width_lp-1:0] decode_info_i + , output logic [preissue_pkt_width_lp-1:0] preissue_pkt_o + , output logic [issue_pkt_width_lp-1:0] issue_pkt_o + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + `bp_cast_i(bp_fe_queue_s, fe_queue); + `bp_cast_o(bp_be_preissue_pkt_s, preissue_pkt); + `bp_cast_o(bp_be_issue_pkt_s, issue_pkt); + + localparam entry_ptr_width_lp = fetch_sel_p; + localparam mem_ptr_width_lp = `BSG_SAFE_CLOG2(fe_queue_fifo_els_p); + localparam ptr_width_lp = mem_ptr_width_lp+entry_ptr_width_lp+1; + + localparam ptr_wrap_bit_lp = ptr_width_lp-1; + localparam ptr_base_bit_lp = entry_ptr_width_lp; + localparam ptr_slots_lp = 1 << ptr_width_lp; + + // One read pointer, one write pointer, one checkpoint pointer + struct packed + { + logic wrap; + logic [mem_ptr_width_lp-1:0] mem; + logic [entry_ptr_width_lp-1:0] entry; + } wptr_n, wptr_r, rptr_n, rptr_r, cptr_n, cptr_r; + + // Status + wire ack = (fe_queue_ready_and_o & fe_queue_v_i); + wire empty = (rptr_r == wptr_r); + wire empty_n = (rptr_n == wptr_n); + wire full = (cptr_r.mem == wptr_r.mem) && (cptr_r.wrap != wptr_r.wrap); + wire full_n = (cptr_n.mem == wptr_n.mem) && (cptr_n.wrap != wptr_n.wrap); + + // Operations + logic [op_ptr_width_lp-1:0] enq, deq, read; + wire enq_catchup = 1'b1; // Enqueue always allocates a new queue entry + wire read_catchup = (rptr_r.entry + read_size_i >= read_cnt_i); + wire deq_catchup = (cptr_r.entry + cmt_size_i >= cmt_cnt_i ); + + assign enq = ack ? enq_catchup ? (entry_cinstr_gp - wptr_r.entry) : '0 : '0; + assign read = read_i ? read_catchup ? (entry_cinstr_gp - rptr_r.entry) : read_size_i : '0; + assign deq = cmt_i ? deq_catchup ? (entry_cinstr_gp - cptr_r.entry) : cmt_size_i : '0; + + // Calculate next pointer jump + logic [ptr_width_lp-1:0] wptr_jmp, rptr_jmp, cptr_jmp; + assign rptr_jmp = clr_i ? -rptr_r : roll_i ? (cptr_r - rptr_r + deq) : read; + assign wptr_jmp = clr_i ? -wptr_r : enq; + assign cptr_jmp = clr_i ? -cptr_r : deq; + + bsg_circular_ptr + #(.slots_p(ptr_slots_lp), .max_add_p(ptr_slots_lp-1)) + cptr + (.clk(clk_i) + ,.reset_i(reset_i) + ,.add_i(cptr_jmp) + ,.o(cptr_r) + ,.n_o(cptr_n) + ); + + bsg_circular_ptr + #(.slots_p(ptr_slots_lp), .max_add_p(ptr_slots_lp-1)) + wptr + (.clk(clk_i) + ,.reset_i(reset_i) + ,.add_i(wptr_jmp) + ,.o(wptr_r) + ,.n_o(wptr_n) + ); + + bsg_circular_ptr + #(.slots_p(ptr_slots_lp), .max_add_p(ptr_slots_lp-1)) + rptr + (.clk(clk_i) + ,.reset_i(reset_i) + ,.add_i(rptr_jmp) + ,.o(rptr_r) + ,.n_o(rptr_n) + ); + + logic [fetch_width_p-1:0] queue_instr, queue_instr_n; + assign queue_instr = fe_queue_cast_i.instr; + wire preissue_v = (|read & ~empty_n) | roll_i | (|enq & empty); + wire bypass_preissue = (wptr_r == rptr_n); + bsg_mem_1r1w + #(.width_p(fetch_width_p), .els_p(fe_queue_fifo_els_p)) + preissue_fifo_mem + (.w_clk_i(clk_i) + ,.w_reset_i(reset_i) + ,.w_v_i(|enq) + ,.w_addr_i(wptr_r.mem) + ,.w_data_i(queue_instr) + ,.r_v_i(~bypass_preissue) + ,.r_addr_i(rptr_n.mem) + ,.r_data_o(queue_instr_n) + ); + + wire [entry_ptr_width_lp-1:0] preissue_entry_sel = bypass_preissue ? wptr_r.entry : rptr_n.entry; + logic [fetch_cinstr_p:0][cinstr_width_gp-1:0] queue_instr_raw; + assign queue_instr_raw[0+:fetch_cinstr_p] = bypass_preissue ? queue_instr : queue_instr_n; + assign queue_instr_raw[fetch_cinstr_p] = '0; + + rv64_instr_s [fetch_cinstr_p-1:0] preissue_instr; + logic [fetch_cinstr_p-1:0][fetch_ptr_p-1:0] preissue_size; + for (genvar i = 0; i < fetch_cinstr_p; i++) + begin : e + logic [instr_width_gp-1:0] instr; + wire [cinstr_width_gp-1:0] cinstr = queue_instr_raw[i]; + bp_be_expander + expander + (.cinstr_i(cinstr) + ,.instr_o(instr) + ); + assign preissue_size[i] = ~&cinstr[0+:2] ? 2'b01 : 2'b10; + assign preissue_instr[i] = (preissue_size[i] == 2'b01) ? instr : queue_instr_raw[i+:2]; + end + + // Pre-decode + always_comb + begin + preissue_pkt_cast_o = '0; + preissue_pkt_cast_o.size = preissue_size[preissue_entry_sel]; + preissue_pkt_cast_o.instr = preissue_instr[preissue_entry_sel]; + + // Decide whether to read from regfile + casez (preissue_instr[preissue_entry_sel].t.fmatype.opcode) + `RV64_JALR_OP, `RV64_LOAD_OP, `RV64_OP_IMM_OP, `RV64_OP_IMM_32_OP, `RV64_SYSTEM_OP : + begin + preissue_pkt_cast_o.irs1_v = preissue_v; + end + `RV64_BRANCH_OP, `RV64_STORE_OP, `RV64_OP_OP, `RV64_OP_32_OP, `RV64_AMO_OP: + begin + preissue_pkt_cast_o.irs1_v = preissue_v; + preissue_pkt_cast_o.irs2_v = preissue_v; + end + `RV64_MISC_MEM_OP: + casez (preissue_pkt_cast_o.instr) + `RV64_CBO_ZERO + ,`RV64_CBO_CLEAN + ,`RV64_CBO_INVAL + ,`RV64_CBO_FLUSH: + begin + preissue_pkt_cast_o.irs1_v = preissue_v; + preissue_pkt_cast_o.irs2_v = preissue_v; + end + endcase + `RV64_FLOAD_OP: + begin + preissue_pkt_cast_o.irs1_v = preissue_v; + end + `RV64_FSTORE_OP: + begin + preissue_pkt_cast_o.irs1_v = preissue_v; + preissue_pkt_cast_o.frs2_v = preissue_v; + end + `RV64_FP_OP: + casez (preissue_pkt_cast_o.instr) + `RV64_FCVT_WS, `RV64_FCVT_WUS, `RV64_FCVT_LS, `RV64_FCVT_LUS + ,`RV64_FCVT_WD, `RV64_FCVT_WUD, `RV64_FCVT_LD, `RV64_FCVT_LUD + ,`RV64_FCVT_SD, `RV64_FCVT_DS + ,`RV64_FMV_XW, `RV64_FMV_XD + ,`RV64_FCLASS_S, `RV64_FCLASS_D: + begin + preissue_pkt_cast_o.frs1_v = preissue_v; + end + `RV64_FCVT_SW, `RV64_FCVT_SWU, `RV64_FCVT_SL, `RV64_FCVT_SLU + ,`RV64_FCVT_DW, `RV64_FCVT_DWU, `RV64_FCVT_DL, `RV64_FCVT_DLU + ,`RV64_FMV_WX, `RV64_FMV_DX: + begin + preissue_pkt_cast_o.irs1_v = preissue_v; + end + default: + begin + preissue_pkt_cast_o.frs1_v = preissue_v; + preissue_pkt_cast_o.frs2_v = preissue_v; + end + endcase + `RV64_FMADD_OP, `RV64_FMSUB_OP, `RV64_FNMSUB_OP, `RV64_FNMADD_OP: + begin + preissue_pkt_cast_o.frs1_v = preissue_v; + preissue_pkt_cast_o.frs2_v = preissue_v; + preissue_pkt_cast_o.frs3_v = preissue_v; + end + default: begin end + endcase + end + + bp_be_preissue_pkt_s preissue_pkt_r; + bsg_dff_reset_en + #(.width_p($bits(bp_be_preissue_pkt_s))) + issue_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(preissue_v) + ,.data_i(preissue_pkt_cast_o) + ,.data_o(preissue_pkt_r) + ); + + bp_fe_queue_s fe_queue_lo; + wire bypass_issue = (wptr_r.mem == rptr_r.mem); + bsg_mem_1r1w + #(.width_p(fe_queue_width_lp), .els_p(fe_queue_fifo_els_p)) + queue_fifo_mem + (.w_clk_i(clk_i) + ,.w_reset_i(reset_i) + ,.w_v_i(|enq) + ,.w_addr_i(wptr_r.mem) + ,.w_data_i(fe_queue_cast_i) + ,.r_v_i(~bypass_issue) + ,.r_addr_i(rptr_r.mem) + ,.r_data_o(fe_queue_lo) + ); + assign fe_queue_ready_and_o = ~full; + + wire [vaddr_width_p-1:0] issue_pc = fe_queue_lo.pc + (rptr_r.entry << 1'b1); + wire [instr_width_gp-1:0] issue_instr = preissue_pkt_r.instr; + wire [fetch_ptr_p-1:0] issue_size = issue_pkt_cast_o.fetch ? preissue_pkt_r.size : entry_ptr_width_lp; + wire [fetch_ptr_p-1:0] issue_count = fe_queue_lo.count; + + // Decode the dispatched instruction + bp_be_decode_s decoded_instr_lo; + logic [dword_width_gp-1:0] decoded_imm_lo; + logic illegal_instr_lo; + logic ecall_m_lo, ecall_s_lo, ecall_u_lo; + logic ebreak_lo, dbreak_lo; + logic dret_lo, mret_lo, sret_lo; + logic wfi_lo, sfence_vma_lo, fencei_lo, csrw_lo; + bp_be_instr_decoder + #(.bp_params_p(bp_params_p)) + instr_decoder + (.preissue_pkt_i(preissue_pkt_r) + ,.decode_info_i(decode_info_i) + + ,.decode_o(decoded_instr_lo) + ,.imm_o(decoded_imm_lo) + + ,.illegal_instr_o(illegal_instr_lo) + ,.ecall_m_o(ecall_m_lo) + ,.ecall_s_o(ecall_s_lo) + ,.ecall_u_o(ecall_u_lo) + ,.ebreak_o(ebreak_lo) + ,.dbreak_o(dbreak_lo) + ,.dret_o(dret_lo) + ,.mret_o(mret_lo) + ,.sret_o(sret_lo) + ,.wfi_o(wfi_lo) + ,.sfence_vma_o(sfence_vma_lo) + ,.fencei_o(fencei_lo) + ,.csrw_o(csrw_lo) + ); + + always_comb + begin + issue_pkt_cast_o = '0; + + issue_pkt_cast_o.v = en_i & ~empty; + issue_pkt_cast_o.fetch = (fe_queue_lo.msg_type == e_instr_fetch) & !illegal_instr_lo; + issue_pkt_cast_o.itlb_miss = (fe_queue_lo.msg_type == e_itlb_miss); + issue_pkt_cast_o.instr_access_fault = (fe_queue_lo.msg_type == e_instr_access_fault); + issue_pkt_cast_o.instr_page_fault = (fe_queue_lo.msg_type == e_instr_page_fault); + issue_pkt_cast_o.icache_miss = (fe_queue_lo.msg_type == e_icache_miss); + issue_pkt_cast_o.illegal_instr = (fe_queue_lo.msg_type == e_instr_fetch) & illegal_instr_lo; + issue_pkt_cast_o.ecall_m = ecall_m_lo; + issue_pkt_cast_o.ecall_s = ecall_s_lo; + issue_pkt_cast_o.ecall_u = ecall_u_lo; + issue_pkt_cast_o.ebreak = ebreak_lo; + issue_pkt_cast_o.dbreak = dbreak_lo; + issue_pkt_cast_o.dret = dret_lo; + issue_pkt_cast_o.mret = mret_lo; + issue_pkt_cast_o.sret = sret_lo; + issue_pkt_cast_o.wfi = wfi_lo; + issue_pkt_cast_o.sfence_vma = sfence_vma_lo; + issue_pkt_cast_o.fencei = fencei_lo; + issue_pkt_cast_o.csrw = csrw_lo; + + issue_pkt_cast_o.pc = issue_pc; + issue_pkt_cast_o.instr = issue_instr; + issue_pkt_cast_o.size = issue_size; + issue_pkt_cast_o.count = issue_count; + issue_pkt_cast_o.decode = decoded_instr_lo; + issue_pkt_cast_o.imm = decoded_imm_lo; + issue_pkt_cast_o.branch_metadata_fwd = fe_queue_lo.branch_metadata_fwd; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_nonsynth_dcache_tracer.sv b/designs/black-parrot/src/bp/bp_be_nonsynth_dcache_tracer.sv new file mode 100644 index 0000000..d9c802b --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_nonsynth_dcache_tracer.sv @@ -0,0 +1,212 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_be_nonsynth_dcache_tracer + import bp_common_pkg::*; + import bp_be_pkg::*; + #( parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + , parameter assoc_p = 8 + , parameter sets_p = 64 + , parameter block_width_p = 512 + , parameter fill_width_p = 512 + , parameter trace_file_p = "dcache" + , parameter tag_width_p = dcache_tag_width_p + , parameter id_width_p = 1 + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, dword_width_gp, block_width_p, fill_width_p, id_width_p) + + // Calculated parameters + , localparam mhartid_width_lp = `BSG_SAFE_CLOG2(num_core_p) + , localparam bank_width_lp = block_width_p / assoc_p + , localparam dcache_pkt_width_lp = $bits(bp_be_dcache_pkt_s) + , localparam wbuf_entry_width_lp = `bp_be_dcache_wbuf_entry_width(caddr_width_p, assoc_p) + ) + ( input clk_i + , input reset_i + , input [mhartid_width_lp-1:0] mhartid_i + + , input [dcache_pkt_width_lp-1:0] dcache_pkt_i + , input v_i + + , input [dword_width_gp-1:0] data_o + , input v_o + + , input [dcache_req_width_lp-1:0] cache_req_o + , input cache_req_v_o + , input cache_req_yumi_i + , input cache_req_lock_i + , input [dcache_req_metadata_width_lp-1:0] cache_req_metadata_o + , input cache_req_metadata_v_o + , input cache_req_critical_i + , input cache_req_last_i + // Unused + , input cache_req_credits_full_i + , input cache_req_credits_empty_i + + , input data_mem_pkt_v_i + , input [dcache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , input data_mem_pkt_yumi_o + , input [block_width_p-1:0] data_mem_o + + , input tag_mem_pkt_v_i + , input [dcache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , input tag_mem_pkt_yumi_o + , input [dcache_tag_info_width_lp-1:0] tag_mem_o + + , input stat_mem_pkt_v_i + , input [dcache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , input stat_mem_pkt_yumi_o + , input [dcache_stat_info_width_lp-1:0] stat_mem_o + + , input [wbuf_entry_width_lp-1:0] wbuf_entry_out + , input wbuf_yumi_li + + , input bp_be_dcache_decode_s decode_tl_r + , input [paddr_width_p-1:0] paddr_tl + , input bp_be_dcache_decode_s decode_tv_r + , input [paddr_width_p-1:0] paddr_tv_r + , input [dword_width_gp-1:0] st_data_tv_r + , input snoop_tv_r + + , input [assoc_p-1:0] data_mem_slow_read + , input [assoc_p-1:0] data_mem_slow_write + , input [assoc_p-1:0] data_mem_fast_read + , input [assoc_p-1:0] data_mem_fast_write + + , input tag_mem_slow_read + , input tag_mem_slow_write + , input tag_mem_fast_read + , input tag_mem_fast_write + + , input stat_mem_slow_read + , input stat_mem_slow_write + , input stat_mem_fast_read + , input stat_mem_fast_write + ); + + `declare_bp_be_dcache_engine_if(paddr_width_p, tag_width_p, sets_p, assoc_p, dword_width_gp, block_width_p, fill_width_p, id_width_p); + bp_be_dcache_pkt_s dcache_pkt_cast_i; + assign dcache_pkt_cast_i = dcache_pkt_i; + + bp_be_dcache_req_s cache_req_cast_o; + bp_be_dcache_req_metadata_s cache_req_metadata_cast_o; + assign cache_req_cast_o = cache_req_o; + assign cache_req_metadata_cast_o = cache_req_metadata_o; + + bp_be_dcache_data_mem_pkt_s data_mem_pkt_cast_i; + bp_be_dcache_tag_mem_pkt_s tag_mem_pkt_cast_i; + bp_be_dcache_stat_mem_pkt_s stat_mem_pkt_cast_i; + assign data_mem_pkt_cast_i = data_mem_pkt_i; + assign tag_mem_pkt_cast_i = tag_mem_pkt_i; + assign stat_mem_pkt_cast_i = stat_mem_pkt_i; + + logic [assoc_p-1:0][bank_width_lp-1:0] data_mem_cast_o; + bp_be_dcache_tag_info_s tag_mem_info_cast_o; + bp_be_dcache_stat_info_s stat_mem_info_cast_o; + assign data_mem_cast_o = data_mem_o; + assign tag_mem_info_cast_o = tag_mem_o; + assign stat_mem_info_cast_o = stat_mem_o; + + `declare_bp_be_dcache_wbuf_entry_s(caddr_width_p, assoc_p); + bp_be_dcache_wbuf_entry_s wbuf_entry_out_cast; + assign wbuf_entry_out_cast = wbuf_entry_out; + + integer info_file, eng_file, mem_file, acc_file; + string info_file_name, eng_file_name, mem_file_name, acc_file_name; + always_ff @(negedge reset_i) + begin + info_file_name = $sformatf("%s_%x.info.trace", trace_file_p, mhartid_i); + info_file = $fopen(info_file_name, "w"); + $fwrite(info_file, "Coherent L1: %x\n", dcache_features_p[e_cfg_coherent]); + + eng_file_name = $sformatf("%s_%x.eng.trace", trace_file_p, mhartid_i); + eng_file = $fopen(eng_file_name, "w"); + + mem_file_name = $sformatf("%s_%x.mem.trace", trace_file_p, mhartid_i); + mem_file = $fopen(mem_file_name, "w"); + + acc_file_name = $sformatf("%s_%x.acc.trace", trace_file_p, mhartid_i); + acc_file = $fopen(acc_file_name, "w"); + end + + logic data_mem_read_r, tag_mem_read_r, stat_mem_read_r; + always_ff @(posedge clk_i) + if (reset_i) + begin + data_mem_read_r <= '0; + tag_mem_read_r <= '0; + stat_mem_read_r <= '0; + end + else + begin + data_mem_read_r <= data_mem_pkt_yumi_o & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_read); + tag_mem_read_r <= tag_mem_pkt_yumi_o & (tag_mem_pkt_cast_i.opcode == e_cache_tag_mem_read); + stat_mem_read_r <= stat_mem_pkt_yumi_o & (stat_mem_pkt_cast_i.opcode == e_cache_stat_mem_read); + end + + always_ff @(posedge clk_i) + begin + if (v_i) + $fwrite(acc_file, "%12t | access: %p\n", $time, dcache_pkt_cast_i); + if (v_o & decode_tv_r.load_op) + $fwrite(acc_file, "%12t | load: [%x]->%x\n", $time, paddr_tv_r, data_o); + if (v_o & decode_tv_r.store_op) + $fwrite(acc_file, "%12t | store: [%x]<-%x\n", $time, paddr_tv_r, st_data_tv_r); + if (wbuf_yumi_li) + $fwrite(acc_file, "%12t | wbuf: %p\n", $time, wbuf_entry_out_cast); + + if (cache_req_yumi_i) + $fwrite(eng_file, "%12t | cache_req: %p\n", $time, cache_req_cast_o); + if (cache_req_metadata_v_o) + $fwrite(eng_file, "%12t | cache_req_metadata: %p\n", $time, cache_req_metadata_cast_o); + if (cache_req_critical_i) + $fwrite(eng_file, "%12t | cache_req_critical_i: %b \n", $time, cache_req_critical_i); + if (cache_req_last_i) + $fwrite(eng_file, "%12t | cache_req_last_i: %b \n", $time, cache_req_last_i); + + if (data_mem_pkt_yumi_o) + $fwrite(eng_file, "%12t | data_mem_pkt: %p\n", $time, data_mem_pkt_cast_i); + if (data_mem_read_r) + $fwrite(eng_file, "%12t | data_mem_read: %x\n", $time, data_mem_cast_o); + + if (tag_mem_pkt_yumi_o) + $fwrite(eng_file, "%12t | tag_mem_pkt: %p\n", $time, tag_mem_pkt_cast_i); + if (tag_mem_read_r) + $fwrite(eng_file, "%12t | tag_mem_read: %x\n", $time, tag_mem_info_cast_o); + + if (stat_mem_pkt_yumi_o) + $fwrite(eng_file, "%12t | stat_mem_pkt: %p\n", $time, stat_mem_pkt_cast_i); + if (stat_mem_read_r) + $fwrite(eng_file, "%12t | stat_mem_read: %x\n", $time, stat_mem_info_cast_o); + + if (|data_mem_fast_read) + $fwrite(mem_file, "%12t | data_mem_fast_read: %b\n", $time, data_mem_fast_read); + if (|data_mem_fast_write) + $fwrite(mem_file, "%12t | data_mem_fast_write: %b\n", $time, data_mem_fast_write); + if (|data_mem_slow_read) + $fwrite(mem_file, "%12t | data_mem_slow_read: %b\n", $time, data_mem_slow_read); + if (|data_mem_slow_write) + $fwrite(mem_file, "%12t | data_mem_slow_write: %b\n", $time, data_mem_slow_write); + + if (tag_mem_fast_read) + $fwrite(mem_file, "%12t | tag_mem_fast_read : %b\n", $time, tag_mem_fast_read); + if (tag_mem_fast_write) + $fwrite(mem_file, "%12t | tag_mem_fast_write : %b\n", $time, tag_mem_fast_write); + if (tag_mem_slow_read) + $fwrite(mem_file, "%12t | tag_mem_slow_read : %b\n", $time, tag_mem_slow_read); + if (tag_mem_slow_write) + $fwrite(mem_file, "%12t | tag_mem_slow_write : %b\n", $time, tag_mem_slow_write); + + if (stat_mem_fast_read) + $fwrite(mem_file, "%12t | stat_mem_fast_read: %b\n", $time, stat_mem_fast_read); + if (stat_mem_fast_write) + $fwrite(mem_file, "%12t | stat_mem_fast_write: %b\n", $time, stat_mem_fast_write); + if (stat_mem_slow_read) + $fwrite(mem_file, "%12t | stat_mem_slow_read: %b\n", $time, stat_mem_slow_read); + if (stat_mem_slow_write) + $fwrite(mem_file, "%12t | stat_mem_slow_write: %b\n", $time, stat_mem_slow_write); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_pipe_aux.sv b/designs/black-parrot/src/bp/bp_be_pipe_aux.sv new file mode 100644 index 0000000..037917d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_pipe_aux.sv @@ -0,0 +1,388 @@ +/** + * + * Name: + * bp_be_pipe_aux.v + * + * Description: + * Pipeline for RISC-V floating point auxiliary instructions + * + * Notes: + * + */ +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_pipe_aux + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + ) + (input clk_i + , input reset_i + + , input [reservation_width_lp-1:0] reservation_i + , input flush_i + , input rv64_frm_e frm_dyn_i + + // Pipeline results + , output logic [dpath_width_gp-1:0] data_o + , output rv64_fflags_s fflags_o + , output logic v_o + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + bp_be_reservation_s reservation; + bp_be_decode_s decode; + rv64_instr_s instr; + + assign reservation = reservation_i; + assign decode = reservation.decode; + assign instr = reservation.instr; + wire [dp_rec_width_gp-1:0] frs1 = reservation.fsrc1; + wire [dp_rec_width_gp-1:0] frs2 = reservation.fsrc2; + wire [dword_width_gp-1:0] irs1 = reservation.isrc1; + wire [dword_width_gp-1:0] irs2 = reservation.isrc2; + + wire ops_v = decode.frd_tag == e_fp_sp; + wire opw_v = decode.ird_tag == e_int_word; + + // + // Control bits for the FPU + // The control bits control tininess, which is fixed in RISC-V + rv64_frm_e frm_li; + // VCS / DVE 2016.1 has an issue with the 'assign' variant of the following code + always_comb frm_li = rv64_frm_e'((instr.t.fmatype.rm == e_dyn) ? frm_dyn_i : instr.t.fmatype.rm); + wire [`floatControlWidth-1:0] control_li = `flControl_default; + + // + // FCLASS + // + bp_hardfloat_raw_dp_s frs1_raw; + bp_be_rec_to_raw + #(.bp_params_p(bp_params_p)) + frs1_to_raw + (.rec_i(frs1) + ,.tag_i(decode.frs1_tag) + ,.raw_o(frs1_raw) + ); + + bp_hardfloat_raw_dp_s frs2_raw; + bp_be_rec_to_raw + #(.bp_params_p(bp_params_p)) + frs2_to_raw + (.rec_i(frs2) + ,.tag_i(decode.frs2_tag) + ,.raw_o(frs2_raw) + ); + + rv64_fclass_s fclass_result; + rv64_fflags_s fclass_fflags; + assign fclass_result = '{q_nan : frs1_raw.is_nan & ~frs1_raw.is_snan + ,s_nan : frs1_raw.is_nan & frs1_raw.is_snan + ,p_inf : ~frs1_raw.sign & frs1_raw.is_inf + ,p_norm: ~frs1_raw.sign & ~frs1_raw.is_sub & ~frs1_raw.is_zero & ~frs1_raw.is_inf & ~frs1_raw.is_nan + ,p_sub : ~frs1_raw.sign & frs1_raw.is_sub + ,p_zero: ~frs1_raw.sign & frs1_raw.is_zero + ,n_zero: frs1_raw.sign & frs1_raw.is_zero + ,n_sub : frs1_raw.sign & frs1_raw.is_sub + ,n_norm: frs1_raw.sign & ~frs1_raw.is_sub & ~frs1_raw.is_zero & ~frs1_raw.is_inf & ~frs1_raw.is_nan + ,n_inf : frs1_raw.sign & frs1_raw.is_inf + ,default: '0 + }; + assign fclass_fflags = '0; + + // + // Move Float -> Int + // + logic [dword_width_gp-1:0] fmvi_result; + rv64_fflags_s fmvi_fflags; + + assign fmvi_result = frs1; + assign fmvi_fflags = '0; + + // + // FCVT Int -> Float + // + bp_hardfloat_raw_dp_s i2f_result; + rv64_fflags_s i2f_fflags; + + bp_hardfloat_rec_dp_s i2f_rec; + wire irs1_unsigned = decode.fu_op inside {e_aux_op_iu2f}; + iNToRecFN + #(.intWidth(dword_width_gp) + ,.expWidth(dp_exp_width_gp) + ,.sigWidth(dp_sig_width_gp) + ) + i2f + (.control(control_li) + ,.signedIn(!irs1_unsigned) + ,.in(irs1) + ,.roundingMode(frm_li) + ,.out(i2f_rec) + ,.exceptionFlags(i2f_fflags) + ); + + bp_hardfloat_raw_dp_s i2f_raw; + logic [dp_sig_width_gp:0] i2f_sig; + recFNToRawFN + #(.expWidth(dp_exp_width_gp), .sigWidth(dp_sig_width_gp)) + i2f_rec_to_raw + (.in(i2f_rec) + ,.isNaN(i2f_result.is_nan) + ,.isInf(i2f_result.is_inf) + ,.isZero(i2f_result.is_zero) + ,.sign(i2f_result.sign) + ,.sExp(i2f_result.sexp) + ,.sig(i2f_sig) + ); + assign i2f_result.sig = i2f_sig << 2'b10; + + // + // FCVT Float -> Int + // + logic [dword_width_gp-1:0] f2i_result; + rv64_fflags_s f2i_fflags; + + // Double -> dword conversion + logic [dword_width_gp-1:0] f2dw_out; + rv64_iflags_s f2dw_iflags; + rv64_fflags_s dword_fflags; + wire signed_f2i = (decode.fu_op inside {e_aux_op_f2i}); + recFNToIN + #(.expWidth(dp_exp_width_gp), .sigWidth(dp_sig_width_gp), .intWidth(dword_width_gp)) + f2dw + (.control(control_li) + ,.in(frs1) + ,.roundingMode(frm_li) + ,.signedOut(signed_f2i) + ,.out(f2dw_out) + ,.intExceptionFlags(f2dw_iflags) + ); + assign dword_fflags = '{nv: f2dw_iflags.nv | f2dw_iflags.of, nx: f2dw_iflags.nx, default: '0}; + + logic [word_width_gp-1:0] f2w_out; + rv64_iflags_s f2w_iflags; + rv64_fflags_s word_fflags; + recFNToIN + #(.expWidth(dp_exp_width_gp), .sigWidth(dp_sig_width_gp), .intWidth(word_width_gp)) + f2w + (.control(control_li) + ,.in(frs1) + ,.roundingMode(frm_li) + ,.signedOut(signed_f2i) + ,.out(f2w_out) + ,.intExceptionFlags(f2w_iflags) + ); + assign word_fflags = '{nv: f2w_iflags.nv | f2w_iflags.of, nx: f2w_iflags.nx, default: '0}; + + assign f2i_result = opw_v ? f2w_out : f2dw_out; + assign f2i_fflags = opw_v ? word_fflags : dword_fflags; + + // + // Float to Float + // + bp_hardfloat_raw_dp_s f2f_result; + rv64_fflags_s f2f_fflags; + + assign f2f_result = frs1_raw; + assign f2f_fflags = '0; + + // + // FMV Int -> Float + // + logic [dword_width_gp-1:0] imvf_result; + wire [dword_width_gp-1:0] imvf_mask = {{word_width_gp{opw_v}}} << word_width_gp; + + assign imvf_result = irs1 | imvf_mask; + + // + // FSGNJ + // + logic [dword_width_gp-1:0] fsgnj_result; + wire [`BSG_SAFE_CLOG2(dword_width_gp)-1:0] signbit = + (decode.frd_tag == e_fp_dp) ? (dword_width_gp-1) : (word_width_gp-1); + wire invbox_frs1 = ops_v & ~&frs1[word_width_gp+:word_width_gp]; + wire invbox_frs2 = ops_v & ~&frs2[word_width_gp+:word_width_gp]; + wire [dword_width_gp-1:0] fsgnj_a = invbox_frs1 ? sp_canonical_nan : frs1; + wire [dword_width_gp-1:0] fsgnj_b = invbox_frs2 ? sp_canonical_nan : frs2; + always_comb + begin + fsgnj_result = fsgnj_a; + unique case (decode.fu_op) + e_aux_op_fsgnjn: fsgnj_result[signbit] = ~fsgnj_b[signbit]; + e_aux_op_fsgnjx: fsgnj_result[signbit] = fsgnj_b[signbit] ^ fsgnj_a[signbit]; + e_aux_op_fsgnj : fsgnj_result[signbit] = fsgnj_b[signbit]; + default: begin end + endcase + end + + // + // FEQ, FLT, FLE + // + logic fcmp_result; + rv64_fflags_s fcmp_fflags; + + logic flt_lo, feq_lo, fgt_lo, unordered_lo; + wire is_feq_li = (decode.fu_op == e_aux_op_feq); + wire is_flt_li = (decode.fu_op == e_aux_op_flt); + wire is_fle_li = (decode.fu_op == e_aux_op_fle); + wire is_fmax_li = (decode.fu_op == e_aux_op_fmax); + wire is_fmin_li = (decode.fu_op == e_aux_op_fmin); + wire signaling_li = is_flt_li | is_fle_li; + compareRecFN + #(.expWidth(dp_exp_width_gp), .sigWidth(dp_sig_width_gp)) + fcmp + (.a(frs1) + ,.b(frs2) + ,.signaling(signaling_li) + ,.lt(flt_lo) + ,.eq(feq_lo) + ,.gt(fgt_lo) + ,.unordered(unordered_lo) + ,.exceptionFlags(fcmp_fflags) + ); + wire fle_lo = ~fgt_lo; + wire fcmp_out = (is_feq_li & feq_lo) | (is_flt_li & flt_lo) | (is_fle_li & (flt_lo | feq_lo)); + assign fcmp_result = fcmp_out; + + // + // FMIN-MAX + // + bp_hardfloat_raw_dp_s fminmax_result; + rv64_fflags_s fminmax_fflags; + + always_comb + if (frs1_raw.is_nan & frs2_raw.is_nan) + fminmax_result = '1; + else if (frs1_raw.is_nan & ~frs2_raw.is_nan) + fminmax_result = frs2_raw; + else if (~frs1_raw.is_nan & frs2_raw.is_nan) + fminmax_result = frs1_raw; + else if (feq_lo) + fminmax_result = (is_fmin_li ^ frs1_raw.sign) ? frs2_raw : frs1_raw; + else + fminmax_result = (is_fmax_li ^ flt_lo) ? frs1_raw : frs2_raw; + + assign fminmax_fflags = fcmp_fflags; + + // + // Get the final result + // + bp_be_fp_reg_s frd_data_lo; + rv64_fflags_s frd_fflags; + + logic [dword_width_gp-1:0] ieee_result; + always_comb + case (decode.fu_op) + e_aux_op_imvf: ieee_result = imvf_result; + // e_aux_op_fsgnj, e_aux_op_fsgnjx, e_aux_op_fsgnjn; + default: ieee_result = fsgnj_result; + endcase + + bp_be_fp_reg_s ieee_data_lo; + rv64_fflags_s ieee_fflags; + bp_be_fp_box + #(.bp_params_p(bp_params_p)) + fp_box + (.ieee_i(ieee_result) + ,.tag_i(decode.frd_tag) + ,.reg_o(ieee_data_lo) + ); + assign ieee_fflags = '0; + + bp_hardfloat_raw_dp_s raw_result; + rv64_fflags_s raw_fflags; + always_comb + case (decode.fu_op) + e_aux_op_i2f, e_aux_op_iu2f: + begin + raw_result = i2f_result; + raw_fflags = i2f_fflags; + end + e_aux_op_f2f: + begin + raw_result = f2f_result; + raw_fflags = f2f_fflags; + end + // e_aux_op_fmin, e_aux_op_fmax: + default: + begin + raw_result = fminmax_result; + raw_fflags = fminmax_fflags; + end + endcase + + bp_be_fp_reg_s rebox_data_lo; + rv64_fflags_s rebox_fflags; + bp_be_fp_rebox + #(.bp_params_p(bp_params_p)) + rebox + (.raw_i(raw_result) + ,.tag_i(decode.frd_tag) + ,.frm_i(frm_li) + ,.invalid_exc_i(1'b0) + ,.infinite_exc_i(1'b0) + + ,.reg_o(rebox_data_lo) + ,.fflags_o(rebox_fflags) + ); + + assign frd_data_lo = decode.fmove_v ? ieee_data_lo : rebox_data_lo; + assign frd_fflags = decode.fmove_v ? ieee_fflags : (raw_fflags | rebox_fflags); + + logic [dword_width_gp-1:0] iaux_result; + rv64_fflags_s ird_fflags; + always_comb + case (decode.fu_op) + e_aux_op_fmvi: + begin + iaux_result = fmvi_result; + ird_fflags = fmvi_fflags; + end + e_aux_op_f2i, e_aux_op_f2iu: + begin + iaux_result = f2i_result; + ird_fflags = f2i_fflags; + end + e_aux_op_feq, e_aux_op_flt, e_aux_op_fle: + begin + iaux_result = fcmp_result; + ird_fflags = fcmp_fflags; + end + // e_aux_op_fclass + default: + begin + iaux_result = fclass_result; + ird_fflags = fclass_fflags; + end + endcase + + logic [dpath_width_gp-1:0] ird_data_lo; + bp_be_int_box + #(.bp_params_p(bp_params_p)) + int_box + (.raw_i(iaux_result) + ,.tag_i(decode.ird_tag) + ,.unsigned_i(1'b0) + ,.reg_o(ird_data_lo) + ); + + wire [dpath_width_gp-1:0] aux_result = decode.irf_w_v ? ird_data_lo : frd_data_lo; + wire [$bits(rv64_fflags_s)-1:0] aux_fflags = decode.irf_w_v ? ird_fflags : frd_fflags; + + wire aux_v_li = reservation.v & reservation.decode.pipe_aux_v; + bsg_dff_chain + #(.width_p($bits(bp_be_fp_reg_s)+$bits(rv64_fflags_s)+1), .num_stages_p(1)) + retiming_chain + (.clk_i(clk_i) + + ,.data_i({aux_fflags, aux_result, aux_v_li}) + ,.data_o({fflags_o, data_o, v_o}) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bp_be_pipe_aux) + diff --git a/designs/black-parrot/src/bp/bp_be_pipe_fma.sv b/designs/black-parrot/src/bp/bp_be_pipe_fma.sv new file mode 100644 index 0000000..e3915dc --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_pipe_fma.sv @@ -0,0 +1,260 @@ +/** + * + * Name: + * bp_be_pipe_fma.v + * + * Description: + * Pipeline for RISC-V float instructions. Handles float and double computation. + * + * Notes: + * This module relies on cross-boundary flattening and retiming to achieve + * good QoR + * + * ASIC tools prefer to have retiming chains be pure register chains at the end of + * a combinational logic cloud, whereas FPGA tools prefer explicitly instantiated registers. + * With this FPGA optimization, we've achieved 50MHz on a Zynq 7020 + * + * This module: + * ... + * fma 3 cycles reservation + * / \ | + * round imul_out imul meta + * | | + * fma_out fma meta + * + */ +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_pipe_fma + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + ) + (input clk_i + , input reset_i + + , input [reservation_width_lp-1:0] reservation_i + , input flush_i + , input rv64_frm_e frm_dyn_i + + // Pipeline results + , output logic [dpath_width_gp-1:0] imul_data_o + , output logic imul_v_o + , output logic [dpath_width_gp-1:0] fma_data_o + , output rv64_fflags_s fma_fflags_o + , output logic fma_v_o + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + bp_be_reservation_s reservation; + bp_be_decode_s decode; + rv64_instr_s instr; + + assign reservation = reservation_i; + assign decode = reservation.decode; + assign instr = reservation.instr; + wire [dp_rec_width_gp-1:0] frs1 = reservation.fsrc1; + wire [dp_rec_width_gp-1:0] frs2 = reservation.fsrc2; + wire [dp_rec_width_gp-1:0] frs3 = reservation.fsrc3; + wire [dword_width_gp-1:0] irs1 = reservation.isrc1; + wire [dword_width_gp-1:0] irs2 = reservation.isrc2; + + // + // Control bits for the FPU + // The control bits control tininess, which is fixed in RISC-V + rv64_frm_e frm_li; + // VCS / DVE 2016.1 has an issue with the 'assign' variant of the following code + always_comb frm_li = rv64_frm_e'((instr.t.fmatype.rm == e_dyn) ? frm_dyn_i : instr.t.fmatype.rm); + wire [`floatControlWidth-1:0] control_li = `flControl_default; + + wire is_fadd_li = (decode.fu_op == e_fma_op_fadd); + wire is_fsub_li = (decode.fu_op == e_fma_op_fsub); + wire is_faddsub_li = is_fadd_li | is_fsub_li; + wire is_fmul_li = (decode.fu_op == e_fma_op_fmul); + wire is_fmadd_li = (decode.fu_op == e_fma_op_fmadd); + wire is_fmsub_li = (decode.fu_op == e_fma_op_fmsub); + wire is_fnmsub_li = (decode.fu_op == e_fma_op_fnmsub); + wire is_fnmadd_li = (decode.fu_op == e_fma_op_fnmadd); + wire is_imul_li = (decode.fu_op == e_fma_op_imul); + // FMA op list + // enc | semantics | RISC-V equivalent + // 0 0 0 : (a x b) + c : fmadd + // 0 0 1 : (a x b) - c : fmsub + // 0 1 0 : - (a x b) + c : fnmsub + // 0 1 1 : - (a x b) - c : fnmadd + // 1 x x : (a x b) : integer multiplication + logic [2:0] fma_op_li; + always_comb + begin + if (is_fmadd_li | is_fadd_li | is_fmul_li) + fma_op_li = 3'b000; + else if (is_fmsub_li | is_fsub_li) + fma_op_li = 3'b001; + else if (is_fnmsub_li) + fma_op_li = 3'b010; + else if (is_fnmadd_li) + fma_op_li = 3'b011; + else // if is_imul + fma_op_li = 3'b100; + end + + // We emulate A*B with A*B+0 and A+B with A*1+B + // According to IEEE special arithmetic rules for signed 0 + // (https://en.wikipedia.org/wiki/Signed_zero): + // x + (+-0) = x for x different from zero + // In order to correct for this we compute the sign of of A*B + // and match it to maintain the correct signedness of the result + wire negate_sign = frs1[dp_rec_width_gp-1] ^ frs2[dp_rec_width_gp-1]; + wire [dp_rec_width_gp-1:0] fma_one = dp_rec_1_0; + wire [dp_rec_width_gp-1:0] fma_zero = negate_sign ? dp_rec_m0_0 : dp_rec_0_0; + + wire [dp_rec_width_gp-1:0] fma_a_li = decode.irs1_r_v ? irs1 : frs1; + wire [dp_rec_width_gp-1:0] fma_b_li = decode.irs2_r_v ? irs2 : is_faddsub_li ? fma_one : frs2; + wire [dp_rec_width_gp-1:0] fma_c_li = is_faddsub_li ? frs2 : is_fmul_li ? fma_zero : frs3; + + // Here, we switch the implementation based on synthesizing for Vivado or not. If this is + // a knob you'd like to turn, consider modifying the define yourself. + localparam fma_latency_lp = 4; + localparam imul_latency_lp = 3; + `ifdef SYNTHESIS + `ifdef DC + localparam int fma_pipeline_stages_lp [1:0] = '{0,0}; + `elsif CDS_TOOL_DEFINE + localparam int fma_pipeline_stages_lp [1:0] = '{0,0}; + `else + localparam int fma_pipeline_stages_lp [1:0] = '{1,imul_latency_lp-1}; + `endif + `else + localparam int fma_pipeline_stages_lp [1:0] = '{0,0}; + `endif + localparam imul_retime_latency_lp = imul_latency_lp - fma_pipeline_stages_lp[0]; + localparam fma_retime_latency_lp = fma_latency_lp - fma_pipeline_stages_lp[1] - fma_pipeline_stages_lp[0]; + + rv64_frm_e frm_r; + bp_be_fp_tag_e frd_tag_r; + bsg_dff_chain + #(.width_p($bits(rv64_frm_e)+1) + ,.num_stages_p(fma_pipeline_stages_lp[0]+fma_pipeline_stages_lp[1]) + ) + fma_info_chain + (.clk_i(clk_i) + ,.data_i({frm_li, decode.frd_tag}) + ,.data_o({frm_r, frd_tag_r}) + ); + + logic [$bits(bp_be_int_tag_e)-1:0] ird_tag_r; + bsg_dff_chain + #(.width_p($bits(bp_be_int_tag_e)), .num_stages_p(fma_pipeline_stages_lp[0])) + mul_info_chain + (.clk_i(clk_i) + ,.data_i(decode.ird_tag) + ,.data_o(ird_tag_r) + ); + + logic invalid_exc, is_nan, is_inf, is_zero, fma_out_sign; + logic [dword_width_gp-1:0] imul_out; + bp_hardfloat_raw_dp_s fma_raw_lo; + mulAddRecFNToRaw + #(.expWidth(dp_exp_width_gp) + ,.sigWidth(dp_sig_width_gp) + ,.pipelineStages(fma_pipeline_stages_lp[0]) + ,.imulEn(1) + ) + fma + (.clock(clk_i), + .control(control_li) + ,.op(fma_op_li) + ,.a(fma_a_li) + ,.b(fma_b_li) + ,.c(fma_c_li) + ,.roundingMode(frm_li) + + ,.invalidExc(invalid_exc) + ,.out_isNaN(fma_raw_lo.is_nan) + ,.out_isInf(fma_raw_lo.is_inf) + ,.out_isZero(fma_raw_lo.is_zero) + ,.out_sign(fma_raw_lo.sign) + ,.out_sExp(fma_raw_lo.sexp) + ,.out_sig(fma_raw_lo.sig) + ,.out_imul(imul_out) + ); + + logic [dpath_width_gp-1:0] ird_data_lo; + bp_be_int_box + #(.bp_params_p(bp_params_p)) + imul_box + (.raw_i(imul_out) + ,.tag_i(ird_tag_r) + ,.unsigned_i(1'b0) + ,.reg_o(ird_data_lo) + ); + + bp_hardfloat_raw_dp_s fma_raw_r; + logic invalid_exc_r; + bsg_dff_chain + #(.width_p(1+$bits(bp_hardfloat_raw_dp_s)), .num_stages_p(fma_pipeline_stages_lp[1])) + round_info_chain + (.clk_i(clk_i) + ,.data_i({invalid_exc, fma_raw_lo}) + ,.data_o({invalid_exc_r, fma_raw_r}) + ); + + bp_be_fp_reg_s frd_data_lo; + rv64_fflags_s fflags_lo; + bp_be_fp_rebox + #(.bp_params_p(bp_params_p)) + rebox + (.raw_i(fma_raw_r) + ,.tag_i(frd_tag_r) + ,.frm_i(frm_r) + ,.invalid_exc_i(invalid_exc_r) + ,.infinite_exc_i(1'b0) + + ,.reg_o(frd_data_lo) + ,.fflags_o(fflags_lo) + ); + + // TODO: Can combine the registers here if DC doesn't do it automatically + bsg_dff_chain + #(.width_p(dpath_width_gp), .num_stages_p(imul_retime_latency_lp-1)) + imul_retiming_chain + (.clk_i(clk_i) + + ,.data_i(ird_data_lo) + ,.data_o(imul_data_o) + ); + + bsg_dff_chain + #(.width_p($bits(bp_be_fp_reg_s)+$bits(rv64_fflags_s)), .num_stages_p(fma_retime_latency_lp-1)) + fma_retiming_chain + (.clk_i(clk_i) + + ,.data_i({fflags_lo, frd_data_lo}) + ,.data_o({fma_fflags_o, fma_data_o}) + ); + + wire imul_v_li = reservation.v & reservation.decode.pipe_mul_v; + bsg_dff_chain + #(.width_p(1), .num_stages_p(imul_latency_lp-1)) + imul_v_chain + (.clk_i(clk_i) + + ,.data_i(imul_v_li) + ,.data_o(imul_v_o) + ); + + wire fma_v_li = reservation.v & reservation.decode.pipe_fma_v; + bsg_dff_chain + #(.width_p(1), .num_stages_p(fma_latency_lp-1)) + fma_v_chain + (.clk_i(clk_i) + + ,.data_i(fma_v_li) + ,.data_o(fma_v_o) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_pipe_int.sv b/designs/black-parrot/src/bp/bp_be_pipe_int.sv new file mode 100644 index 0000000..f0cd450 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_pipe_int.sv @@ -0,0 +1,204 @@ +/** + * + * Name: + * bp_be_pipe_int.v + * + * Description: + * Pipeline for RISC-V integer instructions. Handles integer computation. + * + * Notes: + * + */ +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_pipe_int + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + ) + (input clk_i + , input reset_i + + , input en_i + , input [reservation_width_lp-1:0] reservation_i + , input flush_i + + // Pipeline results + , output logic [dpath_width_gp-1:0] data_o + , output logic v_o + , output logic branch_o + , output logic btaken_o + , output logic [vaddr_width_p-1:0] npc_o + , output logic instr_misaligned_v_o + ); + + // Suppress unused signal warning + wire unused = &{clk_i, reset_i, flush_i}; + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + bp_be_reservation_s reservation; + bp_be_decode_s decode; + rv64_instr_s instr; + + assign reservation = reservation_i; + assign decode = reservation.decode; + assign instr = reservation.instr; + wire [vaddr_width_p-1:0] pc = reservation.pc; + wire [int_rec_width_gp-1:0] rs1 = reservation.isrc1; + wire [int_rec_width_gp-1:0] rs2 = reservation.isrc2; + wire [int_rec_width_gp-1:0] imm = reservation.isrc3; + wire opw_v = (decode.irs1_tag == e_int_word); + + localparam num_bytes_lp = dword_width_gp>>3; + localparam lg_bits_lp = `BSG_SAFE_CLOG2(dword_width_gp); + + // Shift calculation + logic [rv64_shamt_width_gp-1:0] shamt, shamtn; + wire [rv64_shamt_width_gp-1:0] shmask = {!opw_v, 5'b11111}; + assign shamt = (decode.irs2_r_v ? rs2 : imm) & shmask; + assign shamtn = (opw_v ? 32 : 64) - shamt; + + // We need a separate adder here to do branch comparison + address calc + wire [vaddr_width_p-1:0] baddr = decode.jr_v ? rs1 : pc; + wire [vaddr_width_p-1:0] taken_raw = baddr + imm; + wire [vaddr_width_p-1:0] taken_tgt = taken_raw & {{vaddr_width_p-1{1'b1}}, 1'b0}; + wire [vaddr_width_p-1:0] ntaken_tgt = pc + (reservation.size << 1'b1); + wire [dword_width_gp-1:0] ntaken_data = `BSG_SIGN_EXTEND(ntaken_tgt, dword_width_gp); + wire [dword_width_gp-1:0] pc_data = `BSG_SIGN_EXTEND(pc, dword_width_gp); + + logic [dword_width_gp-1:0] src1; + wire [int_rec_width_gp-1:0] rs1_rev = {<<{rs1}}; + always_comb + case (decode.src1_sel) + e_src1_is_rs1 : src1 = decode.irs1_r_v ? rs1 : pc_data; + e_src1_is_rs1_rev : src1 = rs1_rev >> 1'b1; + e_src1_is_rs1_lsh : src1 = rs1 << shamt; + e_src1_is_rs1_lshn: src1 = rs1 << shamtn; + e_src1_is_zero : src1 = '0; + // e_src1_is_zero + default : src1 = '0; + endcase + + logic [dword_width_gp-1:0] src2; + always_comb + case (decode.src2_sel) + e_src2_is_rs2 : src2 = decode.irs2_r_v ? rs2 : imm; + e_src2_is_rs2n : src2 = ~rs2; + e_src2_is_rs1_rsh : src2 = $signed(rs1) >>> shamt; + e_src2_is_rs1_rshn: src2 = $signed(rs1) >>> shamtn; + // e_src2_is_zero + default : src2 = '0; + endcase + + // Main adder + logic carry; + logic [dword_width_gp:0] sum; + assign {carry, sum} = {src1[dword_width_gp-1], src1} + {src2[dword_width_gp-1], src2} + decode.carryin; + wire sum_zero = ~|sum; + wire sum_sign = sum[dword_width_gp]; + + // Comparator (also used for branching) + logic comp_result; + always_comb + unique case (decode.fu_op) + // Comparator + e_int_op_min , + e_int_op_slt : comp_result = sum_sign; + e_int_op_minu , + e_int_op_sltu : comp_result = !carry; + e_int_op_max , + e_int_op_sge : comp_result = !sum_sign; + e_int_op_maxu , + e_int_op_sgeu : comp_result = carry; + + e_int_op_ne : comp_result = !sum_zero; + // e_int_op_eq + default : comp_result = sum_zero; + endcase + + // Bitmanip + logic [`BSG_WIDTH(dword_width_gp)-1:0] popcount; + bsg_popcount + #(.width_p(dword_width_gp)) + popc + (.i(rs1[0+:dword_width_gp]), .o(popcount)); + + logic [`BSG_WIDTH(word_width_gp)-1:0] clzh, clzl; + wire [`BSG_WIDTH(dword_width_gp)-1:0] clz = !clzh[5] ? clzh : (!opw_v << 5) | clzl; + bsg_counting_leading_zeros + #(.width_p(word_width_gp)) + bclzh + (.a_i(rs1[word_width_gp+:word_width_gp]), .num_zero_o(clzh)); + + bsg_counting_leading_zeros + #(.width_p(word_width_gp)) + bclzl + (.a_i(rs1[0+:word_width_gp]), .num_zero_o(clzl)); + + logic [num_bytes_lp-1:0][7:0] orcb; + for (genvar i = 0; i < num_bytes_lp; i++) + begin : rof_orcb + assign orcb[i] = {8{|rs1[8*i+:8]}}; + end + + logic [num_bytes_lp-1:0][7:0] rev8; + for (genvar i = 0; i < num_bytes_lp; i++) + begin : rof_rev8 + assign rev8[i] = rs1[(7-i)*8+:8]; + end + + // ALU + logic [dword_width_gp-1:0] alu_result; + wire [lg_bits_lp-1:0] bindex = src2 & shmask; + always_comb + unique case (decode.fu_op) + // Arithmetic + e_int_op_add : alu_result = sum; + + // Logic + e_int_op_xor : alu_result = src1 ^ src2; + e_int_op_or : alu_result = src1 | src2; + e_int_op_and : alu_result = src1 & src2; + + // Bitmanip + e_int_op_cpop : alu_result = popcount; + e_int_op_clz : alu_result = clz; + e_int_op_max, e_int_op_maxu, e_int_op_min, e_int_op_minu + : alu_result = comp_result ? rs1 : rs2; + e_int_op_orcb : alu_result = orcb; + e_int_op_rev8 : alu_result = rev8; + + // Bit ops + e_int_op_bclr : alu_result = rs1 & ~(1'b1 << bindex); + e_int_op_bext : alu_result = (rs1 >> bindex) & 1'b1; + e_int_op_binv : alu_result = rs1 ^ (1'b1 << bindex); + e_int_op_bset : alu_result = rs1 | (1'b1 << bindex); + + // Comparator + default : alu_result = comp_result; + endcase + + logic [dpath_width_gp-1:0] ird_data_lo; + bp_be_int_box + #(.bp_params_p(bp_params_p)) + box + (.raw_i(alu_result) + ,.tag_i(decode.ird_tag) + ,.unsigned_i(1'b0) + ,.reg_o(ird_data_lo) + ); + + assign data_o = (decode.j_v | decode.jr_v) ? ntaken_data : ird_data_lo; + assign v_o = en_i & reservation.v & reservation.decode.pipe_int_v; + + assign instr_misaligned_v_o = en_i & btaken_o & (taken_tgt[1:0] != 2'b00) & !compressed_support_p; + + assign branch_o = decode.br_v | decode.j_v | decode.jr_v; + assign btaken_o = (decode.br_v & comp_result) || decode.j_v || decode.jr_v; + assign npc_o = btaken_o ? taken_tgt : ntaken_tgt; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_pipe_long.sv b/designs/black-parrot/src/bp/bp_be_pipe_long.sv new file mode 100644 index 0000000..6a997cd --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_pipe_long.sv @@ -0,0 +1,253 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_pipe_long + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + ) + (input clk_i + , input reset_i + + , input [reservation_width_lp-1:0] reservation_i + , output logic ibusy_o + , output logic fbusy_o + , input rv64_frm_e frm_dyn_i + + , input flush_i + + , output logic [wb_pkt_width_lp-1:0] iwb_pkt_o + , output logic iwb_v_o + , input iwb_yumi_i + + , output logic [wb_pkt_width_lp-1:0] fwb_pkt_o + , output logic fwb_v_o + , input fwb_yumi_i + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + `bp_cast_o(bp_be_wb_pkt_s, iwb_pkt); + `bp_cast_o(bp_be_wb_pkt_s, fwb_pkt); + bp_be_reservation_s reservation; + rv64_instr_s instr; + bp_be_decode_s decode; + + assign reservation = reservation_i; + assign decode = reservation.decode; + assign instr = reservation.instr; + wire [vaddr_width_p-1:0] pc = reservation.pc; + wire [dp_rec_width_gp-1:0] frs1 = reservation.fsrc1; + wire [dp_rec_width_gp-1:0] frs2 = reservation.fsrc2; + wire [dp_rec_width_gp-1:0] frs3 = reservation.fsrc3; + wire [dword_width_gp-1:0] irs1 = reservation.isrc1; + wire [dword_width_gp-1:0] irs2 = reservation.isrc2; + wire [dword_width_gp-1:0] irs3 = reservation.isrc3; + + wire int_v_li = reservation.v & reservation.decode.pipe_long_v & reservation.decode.irf_w_v; + wire fp_v_li = reservation.v & reservation.decode.pipe_long_v & reservation.decode.frf_w_v; + + logic fmask_r, imask_r; + bsg_dff + #(.width_p(2)) + mask_reg + (.clk_i(clk_i) + ,.data_i({fp_v_li, int_v_li}) + ,.data_o({fmask_r, imask_r}) + ); + wire flush_int_li = flush_i & (imask_r | int_v_li); + wire flush_fp_li = flush_i & (fmask_r | fp_v_li); + + wire signed_div_li = decode.fu_op inside {e_long_op_div, e_long_op_rem}; + wire rem_not_div_li = decode.fu_op inside {e_long_op_rem, e_long_op_remu}; + + wire signed_opA_li = decode.fu_op inside {e_long_op_div, e_long_op_rem, e_long_op_mulh, e_long_op_mulhsu}; + wire signed_opB_li = decode.fu_op inside {e_long_op_div, e_long_op_rem, e_long_op_mulh}; + + logic [dword_width_gp-1:0] imulh_result_lo; + logic imulh_ready_lo, imulh_v_lo; + wire imulh_v_li = int_v_li & (decode.fu_op inside {e_long_op_mulh, e_long_op_mulhsu, e_long_op_mulhu}); + bsg_imul_iterative + #(.width_p(dword_width_gp)) + imulh + (.clk_i(clk_i) + ,.reset_i(reset_i | flush_int_li) + ,.v_i(imulh_v_li) + ,.ready_and_o(imulh_ready_lo) + ,.opA_i(irs1) + ,.signed_opA_i(signed_opA_li) + ,.opB_i(irs2) + ,.signed_opB_i(signed_opB_li) + ,.gets_high_part_i(1'b1) + ,.v_o(imulh_v_lo) + ,.result_o(imulh_result_lo) + ,.yumi_i(imulh_v_lo & iwb_yumi_i) + ); + + // We actual could exit early here + logic [dword_width_gp-1:0] quotient_lo, remainder_lo; + logic idiv_ready_and_lo; + logic idiv_v_lo; + wire idiv_v_li = int_v_li & (decode.fu_op inside {e_long_op_div, e_long_op_divu}); + wire irem_v_li = int_v_li & (decode.fu_op inside {e_long_op_rem, e_long_op_remu}); + localparam idiv_bits_per_iter_lp = muldiv_support_p[e_idiv2b] ? 2'b10 : 2'b01; + bsg_idiv_iterative + #(.width_p(dword_width_gp), .bits_per_iter_p(idiv_bits_per_iter_lp)) + idiv + (.clk_i(clk_i) + ,.reset_i(reset_i | flush_int_li) + + ,.dividend_i(irs1) + ,.divisor_i(irs2) + ,.signed_div_i(signed_div_li) + ,.v_i(idiv_v_li | irem_v_li) + ,.ready_and_o(idiv_ready_and_lo) + + ,.quotient_o(quotient_lo) + ,.remainder_o(remainder_lo) + ,.v_o(idiv_v_lo) + ,.yumi_i(idiv_v_lo & iwb_yumi_i) + ); + + logic [reg_addr_width_gp-1:0] ird_addr_r; + bp_be_fu_op_s fu_op_r; + logic [$bits(bp_be_int_tag_e)-1:0] ird_tag_r; + bsg_dff_en + #(.width_p(reg_addr_width_gp+$bits(bp_be_fu_op_s)+$bits(ird_tag_r))) + iwb_reg + (.clk_i(clk_i) + ,.en_i(imulh_v_li | idiv_v_li | irem_v_li) + + ,.data_i({instr.t.fmatype.rd_addr, decode.fu_op, decode.ird_tag}) + ,.data_o({ird_addr_r, fu_op_r, ird_tag_r}) + ); + + logic [dword_width_gp-1:0] iresult; + always_comb + case (fu_op_r) + e_long_op_rem, e_long_op_remu: iresult = remainder_lo; + e_long_op_div, e_long_op_divu: iresult = quotient_lo; + // e_long_op_mulh, e_long_op_mulhsu, e_long_op_mulhu + default: iresult = imulh_result_lo; + endcase + + logic [dpath_width_gp-1:0] ird_data_lo; + bp_be_int_box + #(.bp_params_p(bp_params_p)) + ird_box + (.raw_i(iresult) + ,.tag_i(ird_tag_r) + ,.unsigned_i(1'b0) + ,.reg_o(ird_data_lo) + ); + + assign ibusy_o = int_v_li | ~imulh_ready_lo | ~idiv_ready_and_lo | imask_r; + assign iwb_v_o = ~imask_r & (imulh_v_lo | idiv_v_lo); + assign iwb_pkt_cast_o = '{ird_w_v : iwb_v_o + ,rd_addr: ird_addr_r + ,rd_data: ird_data_lo + ,default: '0 + }; + + // + // Control bits for the FPU + // The control bits control tininess, which is fixed in RISC-V + rv64_frm_e frm_li; + // VCS / DVE 2016.1 has an issue with the 'assign' variant of the following code + always_comb frm_li = rv64_frm_e'((instr.t.fmatype.rm == e_dyn) ? frm_dyn_i : instr.t.fmatype.rm); + wire [`floatControlWidth-1:0] control_li = `flControl_default; + + wire fdiv_v_li = fp_v_li & (decode.fu_op inside {e_long_op_fdiv}); + wire fsqrt_v_li = fp_v_li & (decode.fu_op inside {e_long_op_fsqrt}); + wire fdivsqrt_v_li = fdiv_v_li | fsqrt_v_li; + + logic fdivsqrt_ready_and_lo, fdivsqrt_v_lo; + logic sqrt_lo, invalid_exc, infinite_exc; + logic [2:0] frm_lo; + bp_hardfloat_raw_dp_s fdivsqrt_raw_lo; + localparam fdivsqrt_bits_per_iter_lp = fpu_support_p[e_fdivsqrt2b] ? 2'b10 : 2'b01; + divSqrtRecFNToRaw + #(.expWidth(dp_exp_width_gp) + ,.sigWidth(dp_sig_width_gp) + ,.bits_per_iter_p(fdivsqrt_bits_per_iter_lp) + ) + fdiv + (.clock(clk_i) + ,.nReset(~reset_i & ~flush_fp_li) + ,.control(control_li) + + ,.inReady(fdivsqrt_ready_and_lo) + ,.inValid(fdivsqrt_v_li) + ,.sqrtOp(fsqrt_v_li) + ,.a(frs1) + ,.b(frs2) + ,.roundingMode(frm_li) + + ,.outValid(fdivsqrt_v_lo) + ,.sqrtOpOut(sqrt_lo) + ,.roundingModeOut(frm_lo) + ,.invalidExc(invalid_exc) + ,.infiniteExc(infinite_exc) + + ,.out_isNaN(fdivsqrt_raw_lo.is_nan) + ,.out_isInf(fdivsqrt_raw_lo.is_inf) + ,.out_isZero(fdivsqrt_raw_lo.is_zero) + ,.out_sign(fdivsqrt_raw_lo.sign) + ,.out_sExp(fdivsqrt_raw_lo.sexp) + ,.out_sig(fdivsqrt_raw_lo.sig) + ); + + // outValid of fdivsqrt only goes high one cycle + logic fdivsqrt_pending_r; + bsg_dff_reset_en + #(.width_p(1)) + fdivsqrt_pending_reg + (.clk_i(clk_i) + ,.reset_i(reset_i | flush_fp_li) + ,.en_i(fdivsqrt_v_lo | fwb_yumi_i) + ,.data_i(fdivsqrt_v_lo & ~fwb_yumi_i) + ,.data_o(fdivsqrt_pending_r) + ); + wire fdivsqrt_pending = fdivsqrt_v_lo | fdivsqrt_pending_r; + + bp_be_fp_tag_e frd_tag_r; + logic [reg_addr_width_gp-1:0] frd_addr_r; + rv64_frm_e frm_r; + bsg_dff_en + #(.width_p($bits(rv64_frm_e)+reg_addr_width_gp+1)) + fwb_reg + (.clk_i(clk_i) + ,.en_i(fdivsqrt_v_li) + + ,.data_i({frm_li, instr.t.fmatype.rd_addr, decode.frd_tag}) + ,.data_o({frm_r, frd_addr_r, frd_tag_r}) + ); + + bp_be_fp_reg_s frd_data_lo; + rv64_fflags_s fflags_lo; + bp_be_fp_rebox + #(.bp_params_p(bp_params_p)) + rebox + (.raw_i(fdivsqrt_raw_lo) + ,.tag_i(frd_tag_r) + ,.frm_i(frm_r) + ,.invalid_exc_i(invalid_exc) + ,.infinite_exc_i(infinite_exc) + + ,.reg_o(frd_data_lo) + ,.fflags_o(fflags_lo) + ); + + assign fbusy_o = fdivsqrt_v_li | ~fdivsqrt_ready_and_lo | fmask_r | fdivsqrt_pending; + assign fwb_v_o = ~fmask_r & (fdivsqrt_v_lo | fdivsqrt_pending); + assign fwb_pkt_cast_o = '{frd_w_v : fwb_v_o + ,rd_addr: frd_addr_r + ,rd_data: frd_data_lo + ,fflags : fflags_lo & {5{fwb_v_o}} + ,default: '0 + }; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_pipe_mem.sv b/designs/black-parrot/src/bp/bp_be_pipe_mem.sv new file mode 100644 index 0000000..742b244 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_pipe_mem.sv @@ -0,0 +1,386 @@ +/** + * + * Name: + * bp_be_pipe_mem.v + * + * Description: + * Pipeline for RISC-V memory instructions. This includes both int + float loads + stores. + * + * Notes: + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_pipe_mem + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, dcache_tag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_gp, dcache_block_width_p, dcache_fill_width_p, dcache_req_id_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + // Generated parameters + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + , input flush_i + , input sfence_i + + , output logic busy_o + , output logic ordered_o + + , input [reservation_width_lp-1:0] reservation_i + , input [dword_width_gp-1:0] rs2_val_i + + , input [commit_pkt_width_lp-1:0] commit_pkt_i + + , output logic tlb_load_miss_v_o + , output logic tlb_store_miss_v_o + , output logic cache_miss_v_o + , output logic cache_replay_v_o + , output logic load_misaligned_v_o + , output logic load_access_fault_v_o + , output logic load_page_fault_v_o + , output logic store_misaligned_v_o + , output logic store_access_fault_v_o + , output logic store_page_fault_v_o + + , output logic [dpath_width_gp-1:0] early_data_o + , output logic early_v_o + , output logic [dpath_width_gp-1:0] final_data_o + , output logic final_v_o + + , output logic [wb_pkt_width_lp-1:0] late_wb_pkt_o + , output logic late_wb_v_o + + , input [trans_info_width_lp-1:0] trans_info_i + + // D$-LCE Interface + // signals to LCE + , output logic [dcache_req_width_lp-1:0] cache_req_o + , output logic cache_req_v_o + , input cache_req_yumi_i + , input cache_req_lock_i + , output logic [dcache_req_metadata_width_lp-1:0] cache_req_metadata_o + , output logic cache_req_metadata_v_o + , input [dcache_req_id_width_p-1:0] cache_req_id_i + , input cache_req_critical_i + , input cache_req_last_i + , input cache_req_credits_full_i + , input cache_req_credits_empty_i + + , input data_mem_pkt_v_i + , input [dcache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , output logic data_mem_pkt_yumi_o + , output logic [dcache_block_width_p-1:0] data_mem_o + + , input tag_mem_pkt_v_i + , input [dcache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , output logic tag_mem_pkt_yumi_o + , output logic [dcache_tag_info_width_lp-1:0] tag_mem_o + + , input stat_mem_pkt_v_i + , input [dcache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , output logic stat_mem_pkt_yumi_o + , output logic [dcache_stat_info_width_lp-1:0] stat_mem_o + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_be_dcache_engine_if(paddr_width_p, dcache_tag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_gp, dcache_block_width_p, dcache_fill_width_p, dcache_req_id_width_p); + `bp_cast_o(bp_be_dcache_req_s, cache_req); + `bp_cast_o(bp_be_wb_pkt_s, late_wb_pkt); + `bp_cast_i(bp_be_trans_info_s, trans_info); + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + `bp_cast_i(bp_be_commit_pkt_s, commit_pkt); + + wire negedge_clk = ~clk_i; + wire posedge_clk = clk_i; + + // Cast input and output ports + bp_be_reservation_s reservation; + bp_be_decode_s decode; + rv64_instr_s instr; + + assign reservation = reservation_i; + assign decode = reservation.decode; + assign instr = reservation.instr; + wire [vaddr_width_p-1:0] pc = reservation.pc; + wire [dword_width_gp-1:0] rs1 = reservation.isrc1; + wire [dword_width_gp-1:0] rs2 = reservation.isrc2; + wire [dword_width_gp-1:0] imm = reservation.isrc3; + + wire is_req = reservation.v & (decode.pipe_mem_early_v | decode.pipe_mem_final_v); + wire [rv64_eaddr_width_gp-1:0] eaddr = rs1 + imm; + + logic early_v_r; + bsg_dff_chain + #(.width_p(1), .num_stages_p(2)) + req_chain + (.clk_i(negedge_clk) + ,.data_i(is_req) + ,.data_o(early_v_r) + ); + + // D-TLB connections + wire dtlb_r_store = is_req & (decode.dcache_w_v | decode.dcache_cbo_v); + wire dtlb_r_load = is_req & decode.dcache_r_v; + wire dtlb_r_cbo = is_req & decode.dcache_cbo_v; + wire dtlb_r_ptw = is_req & decode.dcache_mmu_v; + wire dtlb_r_v = dtlb_r_store | dtlb_r_load | dtlb_r_cbo | dtlb_r_ptw; + + logic [vtag_width_p-1:0] dtlb_w_vtag; + bp_pte_leaf_s dtlb_w_entry; + wire dtlb_w_v = commit_pkt_cast_i.dtlb_fill_v; + assign dtlb_w_vtag = commit_pkt_cast_i.vaddr[page_offset_width_gp+:vtag_width_p]; + assign dtlb_w_entry = commit_pkt_cast_i.pte_leaf; + + // Some duplicated decode logic from dcache_decoder. Can send this information + // as part of dcache_pkt to reduce overhead + logic [1:0] dtlb_r_size; + always_comb + unique case (decode.fu_op) + e_dcache_op_lb, e_dcache_op_lbu, e_dcache_op_sb: dtlb_r_size = 2'b00; + e_dcache_op_lh, e_dcache_op_lhu, e_dcache_op_sh: dtlb_r_size = 2'b01; + e_dcache_op_amoswapw, e_dcache_op_amoaddw, e_dcache_op_amoxorw + ,e_dcache_op_amoandw, e_dcache_op_amoorw, e_dcache_op_amominw + ,e_dcache_op_amomaxw, e_dcache_op_amominuw, e_dcache_op_amomaxuw + ,e_dcache_op_lw, e_dcache_op_lwu, e_dcache_op_sw + ,e_dcache_op_flw, e_dcache_op_fsw + ,e_dcache_op_lrw, e_dcache_op_scw: dtlb_r_size = 2'b10; + default: dtlb_r_size = 2'b11; + endcase + + logic dtlb_v_lo; + logic [ptag_width_p-1:0] dtlb_ptag_lo; + logic dtlb_ptag_uncached_lo, dtlb_ptag_dram_lo; + wire uncached_mode_li = cfg_bus_cast_i.dcache_mode == e_lce_mode_uncached; + wire nonspec_mode_li = cfg_bus_cast_i.dcache_mode == e_lce_mode_nonspec; + bp_mmu + #(.bp_params_p(bp_params_p) + ,.tlb_els_4k_p(dtlb_els_4k_p) + ,.tlb_els_2m_p(dtlb_els_2m_p) + ,.tlb_els_1g_p(dtlb_els_1g_p) + ,.latch_last_read_p(0) + ) + dmmu + (.clk_i(negedge_clk) + ,.reset_i(reset_i) + + ,.flush_i(flush_i) + ,.fence_i(sfence_i) + ,.priv_mode_i(trans_info_cast_i.priv_mode) + ,.sum_i(trans_info_cast_i.mstatus_sum) + ,.mxr_i(trans_info_cast_i.mstatus_mxr) + ,.trans_en_i(trans_info_cast_i.translation_en) + ,.uncached_mode_i(uncached_mode_li) + ,.nonspec_mode_i(nonspec_mode_li) + ,.hio_mask_i(cfg_bus_cast_i.hio_mask) + + ,.w_v_i(dtlb_w_v) + ,.w_vtag_i(dtlb_w_vtag) + ,.w_entry_i(dtlb_w_entry) + + ,.r_v_i(dtlb_r_v) + ,.r_instr_i('0) + ,.r_load_i(dtlb_r_load) + ,.r_store_i(dtlb_r_store) + ,.r_cbo_i(dtlb_r_cbo) + ,.r_ptw_i(dtlb_r_ptw) + ,.r_eaddr_i(eaddr) + ,.r_size_i(dtlb_r_size) + + ,.r_v_o(dtlb_v_lo) + ,.r_ptag_o(dtlb_ptag_lo) + ,.r_instr_miss_o() + ,.r_load_miss_o(tlb_load_miss_v_o) + ,.r_store_miss_o(tlb_store_miss_v_o) + ,.r_uncached_o(dtlb_ptag_uncached_lo) + ,.r_nonidem_o(/* All D$ misses are non-speculative */) + ,.r_dram_o(dtlb_ptag_dram_lo) + ,.r_instr_access_fault_o() + ,.r_load_access_fault_o(load_access_fault_v_o) + ,.r_store_access_fault_o(store_access_fault_v_o) + ,.r_instr_misaligned_o() + ,.r_load_misaligned_o(load_misaligned_v_o) + ,.r_store_misaligned_o(store_misaligned_v_o) + ,.r_instr_page_fault_o() + ,.r_load_page_fault_o(load_page_fault_v_o) + ,.r_store_page_fault_o(store_page_fault_v_o) + ); + + bp_be_dcache_pkt_s dcache_pkt; + wire dcache_pkt_v = is_req; + assign dcache_pkt = '{rd_addr : instr.t.rtype.rd_addr + ,opcode : decode.fu_op.t.dcache_fu_op + ,offset : eaddr + }; + logic frs2_r_v_r; + bsg_dff + #(.width_p(1)) + freg + (.clk_i(posedge_clk) + ,.data_i(decode.frs2_r_v) + ,.data_o(frs2_r_v_r) + ); + + // D$ can't handle misaligned accesses + wire dcache_ptag_v = dtlb_v_lo & ~load_misaligned_v_o & ~store_misaligned_v_o; + + logic dcache_v; + logic [dword_width_gp-1:0] dcache_data; + logic [$bits(bp_be_int_tag_e)-1:0] dcache_tag; + logic [reg_addr_width_gp-1:0] dcache_rd_addr; + logic dcache_unsigned, dcache_int, dcache_float, dcache_ptw, dcache_ret, dcache_late; + logic dcache_busy_lo, dcache_ordered_lo; + wire [dword_width_gp-1:0] dcache_st_data = rs2_val_i; + bp_be_dcache + #(.bp_params_p(bp_params_p)) + dcache + (.clk_i(negedge_clk) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_i) + + ,.busy_o(dcache_busy_lo) + ,.ordered_o(dcache_ordered_lo) + + ,.v_i(dcache_pkt_v) + ,.dcache_pkt_i(dcache_pkt) + + ,.ptag_v_i(dcache_ptag_v) + ,.ptag_i(dtlb_ptag_lo) + ,.ptag_uncached_i(dtlb_ptag_uncached_lo) + ,.ptag_dram_i(dtlb_ptag_dram_lo) + + ,.st_data_i(dcache_st_data) + ,.flush_i(flush_i) + + ,.v_o(dcache_v) + ,.data_o(dcache_data) + ,.rd_addr_o(dcache_rd_addr) + ,.unsigned_o(dcache_unsigned) + ,.tag_o(dcache_tag) + ,.int_o(dcache_int) + ,.float_o(dcache_float) + ,.ptw_o(dcache_ptw) + ,.ret_o(dcache_ret) + ,.late_o(dcache_late) + + // D$-LCE Interface + ,.cache_req_o(cache_req_cast_o) + ,.cache_req_v_o(cache_req_v_o) + ,.cache_req_yumi_i(cache_req_yumi_i) + ,.cache_req_lock_i(cache_req_lock_i) + ,.cache_req_metadata_o(cache_req_metadata_o) + ,.cache_req_metadata_v_o(cache_req_metadata_v_o) + ,.cache_req_id_i(cache_req_id_i) + ,.cache_req_critical_i(cache_req_critical_i) + ,.cache_req_last_i(cache_req_last_i) + ,.cache_req_credits_full_i(cache_req_credits_full_i) + ,.cache_req_credits_empty_i(cache_req_credits_empty_i) + + ,.data_mem_pkt_v_i(data_mem_pkt_v_i) + ,.data_mem_pkt_i(data_mem_pkt_i) + ,.data_mem_o(data_mem_o) + ,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o) + ,.tag_mem_pkt_v_i(tag_mem_pkt_v_i) + ,.tag_mem_pkt_i(tag_mem_pkt_i) + ,.tag_mem_o(tag_mem_o) + ,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o) + ,.stat_mem_pkt_v_i(stat_mem_pkt_v_i) + ,.stat_mem_pkt_i(stat_mem_pkt_i) + ,.stat_mem_o(stat_mem_o) + ,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o) + ); + + wire early_v_li = reservation.v & reservation.decode.pipe_mem_early_v; + bsg_dff_chain + #(.width_p(1), .num_stages_p(1)) + early_chain + (.clk_i(posedge_clk) + + ,.data_i(early_v_li) + ,.data_o(early_v_o) + ); + + assign cache_miss_v_o = early_v_r & ~(dcache_v | dcache_late) & cache_req_yumi_i; + assign cache_replay_v_o = early_v_r & ~(dcache_v & ~dcache_late) & ~cache_req_yumi_i; + + bp_be_int_reg_s dcache_idata; + bp_be_int_box + #(.bp_params_p(bp_params_p)) + int_box + (.raw_i(dcache_data) + ,.tag_i(dcache_tag) + ,.unsigned_i(dcache_unsigned) + ,.reg_o(dcache_idata) + ); + assign early_data_o = dcache_idata; + + bp_be_fp_reg_s dcache_fdata; + bp_be_fp_box + #(.bp_params_p(bp_params_p)) + fp_box + (.ieee_i(dcache_data) + ,.tag_i(dcache_tag[0]) + ,.reg_o(dcache_fdata) + ); + + logic [dpath_width_gp-1:0] dcache_data_r; + logic [reg_addr_width_gp-1:0] dcache_rd_addr_r; + wire [dpath_width_gp-1:0] dcache_data_n = dcache_float ? dcache_fdata : dcache_idata; + bsg_dff + #(.width_p(dpath_width_gp+reg_addr_width_gp)) + data_reg + (.clk_i(negedge_clk) + ,.data_i({dcache_data_n, dcache_rd_addr}) + ,.data_o({dcache_data_r, dcache_rd_addr_r}) + ); + + logic dcache_v_r, dcache_int_r, dcache_float_r, dcache_ptw_r, dcache_late_r, dcache_ret_r; + bsg_dff + #(.width_p(6)) + final_reg + (.clk_i(posedge_clk) + ,.data_i({dcache_v, dcache_int, dcache_float, dcache_ptw, dcache_late, dcache_ret}) + ,.data_o({dcache_v_r, dcache_int_r, dcache_float_r, dcache_ptw_r, dcache_late_r, dcache_ret_r}) + ); + + wire final_v_li = reservation.v & reservation.decode.pipe_mem_final_v; + bsg_dff_chain + #(.width_p(1), .num_stages_p(2)) + final_chain + (.clk_i(posedge_clk) + + ,.data_i(final_v_li) + ,.data_o(final_v_o) + ); + assign final_data_o = dcache_data_r; + + // Pipeline these slow signals + bsg_dff + #(.width_p(2)) + sync_reg + (.clk_i(posedge_clk) + ,.data_i({dcache_ordered_lo, dcache_busy_lo}) + ,.data_o({ordered_o, busy_o}) + ); + + assign late_wb_v_o = dcache_v_r & dcache_ret_r & (dcache_late_r | dcache_ptw_r); + assign late_wb_pkt_cast_o = '{ird_w_v : dcache_int_r + ,frd_w_v : dcache_float_r + ,ptw_w_v : dcache_ptw_r + ,rd_addr : dcache_rd_addr_r + ,rd_data : dcache_data_r + ,default : '0 + }; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_pipe_sys.sv b/designs/black-parrot/src/bp/bp_be_pipe_sys.sv new file mode 100644 index 0000000..1140755 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_pipe_sys.sv @@ -0,0 +1,195 @@ +/** + * + * Name: + * bp_be_pipe_sys.v + * + * Description: + * + * Notes: + * + */ +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_pipe_sys + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + // Generated parameters + , localparam exception_width_lp = $bits(bp_be_exception_s) + , localparam special_width_lp = $bits(bp_be_special_s) + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + , input [reservation_width_lp-1:0] reservation_i + , input flush_i + + , input retire_v_i + , input retire_queue_v_i + , input [dpath_width_gp-1:0] retire_data_i + , input [exception_width_lp-1:0] retire_exception_i + , input [special_width_lp-1:0] retire_special_i + + , output logic [dpath_width_gp-1:0] data_o + , output logic v_o + , output logic illegal_instr_o + + , input [wb_pkt_width_lp-1:0] iwb_pkt_i + , input [wb_pkt_width_lp-1:0] fwb_pkt_i + , output logic [commit_pkt_width_lp-1:0] commit_pkt_o + + , input debug_irq_i + , input timer_irq_i + , input software_irq_i + , input m_external_irq_i + , input s_external_irq_i + , output logic irq_pending_o + , output logic irq_waiting_o + + , output logic [decode_info_width_lp-1:0] decode_info_o + , output logic [trans_info_width_lp-1:0] trans_info_o + , output rv64_frm_e frm_dyn_o + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + bp_be_reservation_s reservation; + bp_be_decode_s decode; + rv64_instr_s instr; + `bp_cast_i(bp_be_wb_pkt_s, iwb_pkt); + `bp_cast_i(bp_be_wb_pkt_s, fwb_pkt); + `bp_cast_o(bp_be_commit_pkt_s, commit_pkt); + `bp_cast_o(bp_be_decode_info_s, decode_info); + `bp_cast_o(bp_be_trans_info_s, trans_info); + + assign reservation = reservation_i; + assign decode = reservation.decode; + assign instr = reservation.instr; + wire [vaddr_width_p-1:0] pc = reservation.pc; + wire [dword_width_gp-1:0] rs1 = reservation.isrc1; + wire [dword_width_gp-1:0] rs2 = reservation.isrc2; + wire [dword_width_gp-1:0] imm = reservation.isrc3; + + wire csr_v_li = reservation.decode.csr_r_v | reservation.decode.csr_w_v; + wire [rv64_csr_addr_width_gp-1:0] csr_addr_li = instr.t.itype.imm12; + + bp_be_retire_pkt_s retire_pkt; + logic [dword_width_gp-1:0] csr_data_lo; + wire [4:0] fflags_acc_li = iwb_pkt_cast_i.fflags | fwb_pkt_cast_i.fflags; + bp_be_csr + #(.bp_params_p(bp_params_p)) + csr + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_i) + + ,.csr_r_v_i(csr_v_li) + ,.csr_r_addr_i(csr_addr_li) + ,.csr_r_data_o(csr_data_lo) + ,.csr_r_illegal_o(illegal_instr_o) + + ,.fflags_acc_i(fflags_acc_li) + ,.frf_w_v_i(fwb_pkt_cast_i.frd_w_v) + + ,.debug_irq_i(debug_irq_i) + ,.timer_irq_i(timer_irq_i) + ,.software_irq_i(software_irq_i) + ,.m_external_irq_i(m_external_irq_i) + ,.s_external_irq_i(s_external_irq_i) + ,.irq_pending_o(irq_pending_o) + ,.irq_waiting_o(irq_waiting_o) + + ,.retire_pkt_i(retire_pkt) + ,.commit_pkt_o(commit_pkt_cast_o) + ,.decode_info_o(decode_info_cast_o) + ,.trans_info_o(trans_info_cast_o) + ,.frm_dyn_o(frm_dyn_o) + ); + + logic [vaddr_width_p-1:0] retire_npc_r; + logic [dword_width_gp-1:0] retire_nvaddr_r, retire_vaddr_r; + logic [dword_width_gp-1:0] retire_ndata_r, retire_data_r; + logic [fetch_ptr_p-1:0] retire_nsize_r, retire_size_r; + logic [fetch_ptr_p-1:0] retire_ncount_r, retire_count_r; + rv64_instr_s retire_ninstr_r, retire_instr_r; + logic retire_niscore_r, retire_iscore_r; + logic retire_nfscore_r, retire_fscore_r; + logic retire_nspec_w_r, retire_spec_w_r; + always_ff @(posedge clk_i) + begin + retire_npc_r <= reservation.pc; + + retire_nvaddr_r <= rs1+imm; + retire_vaddr_r <= retire_nvaddr_r; + + retire_ndata_r <= rs2; + retire_data_r <= retire_ndata_r; + + retire_nsize_r <= reservation.size; + retire_size_r <= retire_nsize_r; + + retire_ncount_r <= reservation.count; + retire_count_r <= retire_ncount_r; + + retire_ninstr_r <= reservation.instr; + retire_instr_r <= retire_ninstr_r; + + retire_niscore_r <= reservation.decode.score_v & reservation.decode.irf_w_v; + retire_iscore_r <= retire_niscore_r; + + retire_nfscore_r <= reservation.decode.score_v & reservation.decode.frf_w_v; + retire_fscore_r <= retire_nfscore_r; + + retire_nspec_w_r <= reservation.decode.score_v & reservation.decode.spec_w_v; + retire_spec_w_r <= retire_nspec_w_r; + end + + // Compute input CSR data + logic [dword_width_gp-1:0] retire_data_li; + wire [dword_width_gp-1:0] retire_imm_li = retire_instr_r.t.fmatype.rs1_addr; + always_comb + unique casez ({retire_queue_v_i, retire_instr_r}) + {1'b1, `RV64_CSRRSI}: retire_data_li = retire_imm_li | retire_data_i; + {1'b1, `RV64_CSRRCI}: retire_data_li = ~retire_imm_li & retire_data_i; + {1'b1, `RV64_CSRRWI}: retire_data_li = retire_imm_li; + + {1'b1, `RV64_CSRRS }: retire_data_li = retire_vaddr_r | retire_data_i; + {1'b1, `RV64_CSRRC }: retire_data_li = ~retire_vaddr_r & retire_data_i; + {1'b1, `RV64_CSRRW }: retire_data_li = retire_vaddr_r; + default : retire_data_li = retire_data_i; + endcase + + wire instret_li = retire_v_i & retire_queue_v_i & ~|retire_exception_i; + wire iscore_li = + (~retire_spec_w_r & retire_iscore_r) | (retire_spec_w_r & retire_iscore_r & |retire_special_i); + wire fscore_li = + (~retire_spec_w_r & retire_fscore_r) | (retire_spec_w_r & retire_fscore_r & |retire_special_i); + assign retire_pkt = + '{v : retire_v_i + ,queue_v : retire_queue_v_i + ,instret : instret_li + ,size : retire_size_r + ,count : retire_count_r + ,npc : retire_npc_r + ,vaddr : retire_vaddr_r + ,data : retire_data_li + ,instr : retire_instr_r + ,exception : retire_v_i ? retire_exception_i : '0 + ,special : instret_li ? retire_special_i : '0 + ,iscore : instret_li ? iscore_li : '0 + ,fscore : instret_li ? fscore_li : '0 + }; + + assign v_o = csr_v_li; + assign data_o = csr_data_lo; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_pkg.sv b/designs/black-parrot/src/bp/bp_be_pkg.sv new file mode 100644 index 0000000..4bb8751 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_pkg.sv @@ -0,0 +1,104 @@ + + `include "bp_be_defines.svh" + +package bp_be_pkg; + + import bp_common_pkg::*; + + localparam sp_float_width_gp = 32; + localparam sp_rec_width_gp = 33; + localparam sp_exp_width_gp = 8; + localparam sp_sig_width_gp = 24; + + localparam dp_float_width_gp = 64; + localparam dp_rec_width_gp = 65; + localparam dp_exp_width_gp = 11; + localparam dp_sig_width_gp = 53; + + localparam [dp_float_width_gp-1:0] dp_canonical_nan = 64'h7ff80000_00000000; + localparam [dp_float_width_gp-1:0] sp_canonical_nan = 64'hffffffff_7fc00000; + + localparam [dp_rec_width_gp-1:0] dp_rec_1_0 = 65'h0_80000000_00000000; + localparam [dp_rec_width_gp-1:0] dp_rec_0_0 = 65'h0_00000000_00000000; + localparam [dp_rec_width_gp-1:0] dp_rec_m0_0 = 65'h1_00000000_00000000; + + localparam [dp_rec_width_gp-1:0] dp_canonical_rec = 65'h0_e0080000_00000000; + + localparam int_rec_width_gp = 65; + + typedef enum logic + { + e_fp_dp = 1'b0 + ,e_fp_sp = 1'b1 + } bp_be_fp_tag_e; + + typedef enum logic [1:0] + { + e_int_dword = 2'b00 + ,e_int_word = 2'b01 + ,e_int_hword = 2'b10 + ,e_int_byte = 2'b11 + } bp_be_int_tag_e; + + typedef struct packed + { + logic sign; + logic [sp_exp_width_gp:0] exp; + logic [sp_sig_width_gp-2:0] fract; + } bp_hardfloat_rec_sp_s; + + typedef struct packed + { + logic sign; + logic [dp_exp_width_gp:0] exp; + logic [dp_sig_width_gp-2:0] fract; + } bp_hardfloat_rec_dp_s; + + typedef struct packed + { + logic is_nan; + logic is_inf; + logic is_zero; + logic is_snan; + logic is_sub; + logic sign; + logic [dp_exp_width_gp+1:0] sexp; + logic [dp_sig_width_gp+2:0] sig; + } bp_hardfloat_raw_dp_s; + localparam dp_raw_width_gp = $bits(bp_hardfloat_raw_dp_s); + + typedef struct packed + { + logic is_nan; + logic is_inf; + logic is_zero; + logic is_snan; + logic is_sub; + logic sign; + logic [sp_exp_width_gp+1:0] sexp; + logic [sp_sig_width_gp+2:0] sig; + } bp_hardfloat_raw_sp_s; + localparam sp_raw_width_gp = $bits(bp_hardfloat_raw_sp_s); + + typedef struct packed + { + logic [$bits(bp_be_fp_tag_e)-1:0] tag; + bp_hardfloat_rec_dp_s rec; + } bp_be_fp_reg_s; + + typedef struct packed + { + logic [$bits(bp_be_int_tag_e)-1:0] tag; + logic [dword_width_gp-1:0] val; + } bp_be_int_reg_s; + + localparam dpath_width_gp = $bits(bp_be_fp_reg_s); + + localparam [dpath_width_gp-1:0] dp_canonical_reg = 66'h0_e0080000_00000000; + localparam [dpath_width_gp-1:0] sp_canonical_reg = 66'h2_e0080000_00000000; + + `include "bp_be_ctl_pkgdef.svh" + `include "bp_be_dcache_pkgdef.svh" + +endpackage + diff --git a/designs/black-parrot/src/bp/bp_be_ptw.sv b/designs/black-parrot/src/bp/bp_be_ptw.sv new file mode 100644 index 0000000..a2b2b9c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_ptw.sv @@ -0,0 +1,193 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_ptw + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + , parameter `BSG_INV_PARAM(pte_width_p) + , parameter `BSG_INV_PARAM(page_table_depth_p) + , parameter `BSG_INV_PARAM(pte_size_in_bytes_p) + , parameter `BSG_INV_PARAM(page_idx_width_p) + + ) + (input clk_i + , input reset_i + + // Slow control signals + , output busy_o + , input [commit_pkt_width_lp-1:0] commit_pkt_i + , input [trans_info_width_lp-1:0] trans_info_i + , input ordered_i + + , output logic v_o + , output logic walk_o + , output logic itlb_fill_o + , output logic dtlb_fill_o + , output logic instr_page_fault_o + , output logic load_page_fault_o + , output logic store_page_fault_o + , output logic [fetch_ptr_p-1:0] count_o + , output logic [dword_width_gp-1:0] addr_o + , output logic [dword_width_gp-1:0] pte_o + + , input v_i + , input [dword_width_gp-1:0] data_i + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + `bp_cast_i(bp_be_commit_pkt_s, commit_pkt); + `bp_cast_i(bp_be_trans_info_s, trans_info); + + enum logic [1:0] {e_idle, e_wait, e_send_load, e_writeback} state_n, state_r; + wire is_idle = (state_r == e_idle); + wire is_wait = (state_r == e_wait); + wire is_send = (state_r == e_send_load); + wire is_write = (state_r == e_writeback); + + localparam lg_pte_size_in_bytes_lp = `BSG_SAFE_CLOG2(pte_size_in_bytes_p); + localparam lg_page_table_depth_lp = `BSG_SAFE_CLOG2(page_table_depth_p); + localparam pte_ptag_offset_lp = (page_table_depth_p-1)*page_idx_width_p; + + sv39_pte_s dcache_pte; + assign dcache_pte = data_i; + + logic [ptag_width_p-1:0] ppn_r, ppn_n; + logic [lg_page_table_depth_lp-1:0] level_n, level_r; + logic instr_n, instr_r; + logic store_n, store_r; + logic load_n, load_r; + logic [fetch_ptr_p-1:0] count_n, count_r; + logic [vaddr_width_p-1:0] vaddr_n, vaddr_r; + + logic [dword_width_gp-1:0] vpn; + logic [dword_width_gp-1:0] ppn; + logic [page_table_depth_p-1:0][page_idx_width_p-1:0] partial_vpn; + logic [page_table_depth_p-1:0][page_idx_width_p-1:0] partial_ppn; + + assign vpn = vaddr_r >> sv39_page_offset_width_gp; + for (genvar i = 0; i < page_table_depth_p; i++) + begin : rof1 + assign partial_vpn[i] = vpn[page_idx_width_p*i+:page_idx_width_p]; + assign partial_ppn[i] = ppn[page_idx_width_p*i+:page_idx_width_p]; + end + wire [ptag_width_p-1:0] writeback_ppn = + (((level_r > 0) ? partial_vpn[0] : partial_ppn[0]) << 0*page_idx_width_p) + | (((level_r > 1) ? partial_vpn[1] : partial_ppn[1]) << 1*page_idx_width_p) + | (((level_r > 2) ? partial_vpn[2] : partial_ppn[2]) << 2*page_idx_width_p) + | (dcache_pte.ppn[ptag_width_p-1:pte_ptag_offset_lp] << pte_ptag_offset_lp); + + // PMA attributes + assign busy_o = ~is_idle; + + wire pte_is_leaf = dcache_pte.x | dcache_pte.w | dcache_pte.r; + wire pte_is_kilopage = (level_r == 2'd0); + wire pte_is_megapage = (level_r == 2'd1); + wire pte_is_gigapage = (level_r == 2'd2); + + wire pte_invalid = ~dcache_pte.v | (~dcache_pte.r & dcache_pte.w); + wire leaf_not_found = pte_is_kilopage & ~pte_is_leaf; + wire s_priv_req = pte_is_leaf & (trans_info_cast_i.priv_mode == `PRIV_MODE_S) & (instr_r | ~trans_info_cast_i.mstatus_sum); + wire u_priv_req = pte_is_leaf & (trans_info_cast_i.priv_mode == `PRIV_MODE_U); + wire priv_fault = pte_is_leaf & ((dcache_pte.u & s_priv_req) | (~dcache_pte.u & u_priv_req)); + wire misaligned_superpage = pte_is_leaf & |level_r & |dcache_pte.ppn[page_idx_width_p*(level_r-1'b1)+:page_idx_width_p]; + + wire ad_fault = pte_is_leaf & (~dcache_pte.a | (store_r & ~dcache_pte.d)); + wire common_faults = pte_invalid | leaf_not_found | priv_fault | misaligned_superpage | ad_fault; + + wire instr_page_fault = instr_r & (common_faults | (pte_is_leaf & ~dcache_pte.x)); + wire load_page_fault = load_r & (common_faults | (pte_is_leaf & ~(dcache_pte.r | (dcache_pte.x & trans_info_cast_i.mstatus_mxr)))); + wire store_page_fault = store_r & (common_faults | (pte_is_leaf & ~dcache_pte.w)); + wire page_fault_v = instr_page_fault | load_page_fault | store_page_fault; + wire fill_v = pte_is_leaf & ~page_fault_v; + + wire tlb_miss_v = commit_pkt_cast_i.itlb_miss | commit_pkt_cast_i.dtlb_store_miss | commit_pkt_cast_i.dtlb_load_miss; + + wire walk_start = is_idle & tlb_miss_v; + wire walk_ready = is_wait & ordered_i; + wire walk_send = is_send; + wire walk_replay = commit_pkt_cast_i.dcache_replay; + wire walk_next = v_i & ~(pte_is_leaf | page_fault_v); + wire walk_done = v_i & (pte_is_leaf | page_fault_v); + + wire [page_offset_width_gp-1:0] walk_offset = (partial_vpn[level_n] << lg_pte_size_in_bytes_lp); + wire [paddr_width_p-1:0] walk_addr = {ppn, walk_offset}; + + assign instr_n = commit_pkt_cast_i.itlb_miss; + assign load_n = commit_pkt_cast_i.dtlb_load_miss; + assign store_n = commit_pkt_cast_i.dtlb_store_miss; + assign count_n = commit_pkt_cast_i.count; + assign vaddr_n = commit_pkt_cast_i.vaddr; + bsg_dff_en + #(.width_p(3+fetch_ptr_p+vaddr_width_p)) + miss_reg + (.clk_i(clk_i) + ,.en_i(walk_start) + ,.data_i({instr_n, load_n, store_n, count_n, vaddr_n}) + ,.data_o({instr_r, load_r, store_r, count_r, vaddr_r}) + ); + + assign ppn_n = walk_start ? trans_info_cast_i.base_ppn : dcache_pte.ppn; + assign level_n = walk_start ? page_table_depth_p-1'b1 : level_r-walk_next; + wire walk_en = walk_start | walk_next | walk_done; + bsg_dff_en + #(.width_p(lg_page_table_depth_lp+ptag_width_p)) + walk_reg + (.clk_i(clk_i) + ,.en_i(walk_en) + ,.data_i({level_n, ppn_n}) + ,.data_o({level_r, ppn_r}) + ); + assign ppn = walk_en ? ppn_n : ppn_r; + + bp_be_pte_leaf_s tlb_w_entry; + assign tlb_w_entry.ptag = writeback_ppn; + assign tlb_w_entry.gigapage = pte_is_gigapage; + assign tlb_w_entry.megapage = pte_is_megapage; + assign tlb_w_entry.a = dcache_pte.a; + assign tlb_w_entry.d = dcache_pte.d; + assign tlb_w_entry.u = dcache_pte.u; + assign tlb_w_entry.x = dcache_pte.x; + assign tlb_w_entry.w = dcache_pte.w; + assign tlb_w_entry.r = dcache_pte.r; + + assign v_o = walk_send | walk_next | walk_done; + assign walk_o = walk_send | walk_next; + assign itlb_fill_o = walk_done & instr_r & ~page_fault_v; + assign dtlb_fill_o = walk_done & ~instr_r & ~page_fault_v; + assign instr_page_fault_o = walk_done & instr_page_fault; + assign load_page_fault_o = walk_done & load_page_fault; + assign store_page_fault_o = walk_done & store_page_fault; + assign count_o = walk_done ? count_r : '0; + assign addr_o = walk_done ? vaddr_r : walk_addr; + assign pte_o = tlb_w_entry; + + // Because internal dcache flushing is a possibility, we need to manually replay + // rather than relying on the late writeback + always_comb + case (state_r) + e_idle : state_n = walk_start ? e_wait : e_idle; + e_wait : state_n = walk_ready ? e_send_load : e_wait; + e_send_load : state_n = walk_send ? e_writeback : e_send_load; + e_writeback : state_n = walk_replay + ? e_wait + : walk_done + ? e_idle + : e_writeback; + default : state_n = e_idle; + endcase + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_idle; + else + state_r <= state_n; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_be_ptw) + diff --git a/designs/black-parrot/src/bp/bp_be_rec_to_raw.sv b/designs/black-parrot/src/bp/bp_be_rec_to_raw.sv new file mode 100644 index 0000000..17a6b29 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_rec_to_raw.sv @@ -0,0 +1,54 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_rec_to_raw + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam raw_width_lp = $bits(bp_hardfloat_raw_dp_s) + ) + (input [dp_rec_width_gp-1:0] rec_i + , input tag_i + , output logic [raw_width_lp-1:0] raw_o + ); + + `bp_cast_i(bp_hardfloat_rec_dp_s, rec); + `bp_cast_o(bp_hardfloat_raw_dp_s, raw); + + logic [dp_sig_width_gp:0] raw_sig; + recFNToRawFN + #(.expWidth(dp_exp_width_gp) ,.sigWidth(dp_sig_width_gp)) + rec2raw + (.in(rec_cast_i) + ,.isNaN(raw_cast_o.is_nan) + ,.isInf(raw_cast_o.is_inf) + ,.isZero(raw_cast_o.is_zero) + ,.sign(raw_cast_o.sign) + ,.sExp(raw_cast_o.sexp) + ,.sig(raw_sig) + ); + assign raw_cast_o.sig = raw_sig << 2'b10; + + isSigNaNRecFN + #(.expWidth(dp_exp_width_gp), .sigWidth(dp_sig_width_gp)) + is_snan + (.in(rec_cast_i) + ,.isSigNaN(raw_cast_o.is_snan) + ); + + localparam [dp_exp_width_gp:0] minNormDpExp = (1<<(dp_exp_width_gp - 1)) + 2; + localparam [sp_exp_width_gp:0] minNormSpExp = (1<<(sp_exp_width_gp - 1)) + 2; + + localparam bias_adj_lp = (1 << sp_exp_width_gp) - (1 << dp_exp_width_gp); + wire [sp_exp_width_gp:0] biased_sp = raw_cast_o.sexp + bias_adj_lp; + wire [dp_exp_width_gp:0] biased_dp = raw_cast_o.sexp + 0; + + assign raw_cast_o.is_sub = tag_i + ? ~raw_cast_o.is_zero & ~raw_cast_o.is_inf & ~raw_cast_o.is_nan & (biased_sp < minNormSpExp) + : ~raw_cast_o.is_zero & ~raw_cast_o.is_inf & ~raw_cast_o.is_nan & (biased_dp < minNormDpExp); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_regfile.sv b/designs/black-parrot/src/bp/bp_be_regfile.sv new file mode 100644 index 0000000..1321556 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_regfile.sv @@ -0,0 +1,160 @@ +/** + * + * Name: + * bp_be_regfile.v + * + * Description: + * Synchronous register file wrapper for integer and floating point RISC-V registers. Inlcudes + * logic to maintain the source register values during pipeline stalls. + * + * Notes: + * - Is it okay to continuously read on stalls? There's no switching, so energy may not + * be an issue. An alternative would be to save the read data, but that's more flops / power + * - Should we read the regfile at all for x0? The memory will be a power of 2 size, so it comes + * down to if writing / reading x0 and then muxing is less power than checking x == 0 on input. + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_regfile + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(read_ports_p) + , parameter `BSG_INV_PARAM(zero_x0_p) + ) + (input clk_i + , input reset_i + + // rs read bus + , input [read_ports_p-1:0] rs_r_v_i + , input [read_ports_p-1:0][reg_addr_width_gp-1:0] rs_addr_i + , output [read_ports_p-1:0][data_width_p-1:0] rs_data_o + + // rd write bus + , input rd_w_v_i + , input [reg_addr_width_gp-1:0] rd_addr_i + , input [data_width_p-1:0] rd_data_i + ); + + localparam rf_els_lp = 2**reg_addr_width_gp; + logic [read_ports_p-1:0] rs_v_li; + logic [read_ports_p-1:0][reg_addr_width_gp-1:0] rs_addr_li; + logic [read_ports_p-1:0][data_width_p-1:0] rs_data_lo; + if (read_ports_p == 2) + begin : tworonew + bsg_mem_2r1w_sync + #(.width_p(data_width_p), .els_p(rf_els_lp)) + rf + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(rd_w_v_i) + ,.w_addr_i(rd_addr_i) + ,.w_data_i(rd_data_i) + + ,.r0_v_i(rs_v_li[0]) + ,.r0_addr_i(rs_addr_li[0]) + ,.r0_data_o(rs_data_lo[0]) + + ,.r1_v_i(rs_v_li[1]) + ,.r1_addr_i(rs_addr_li[1]) + ,.r1_data_o(rs_data_lo[1]) + ); + end + else if (read_ports_p == 3) + begin : threeronew + bsg_mem_3r1w_sync + #(.width_p(data_width_p), .els_p(rf_els_lp)) + rf + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(rd_w_v_i) + ,.w_addr_i(rd_addr_i) + ,.w_data_i(rd_data_i) + + ,.r0_v_i(rs_v_li[0]) + ,.r0_addr_i(rs_addr_li[0]) + ,.r0_data_o(rs_data_lo[0]) + + ,.r1_v_i(rs_v_li[1]) + ,.r1_addr_i(rs_addr_li[1]) + ,.r1_data_o(rs_data_lo[1]) + + ,.r2_v_i(rs_v_li[2]) + ,.r2_addr_i(rs_addr_li[2]) + ,.r2_data_o(rs_data_lo[2]) + ); + end + else + begin : error + $error("Error: unsupported number of read ports"); + end + + // Save the written data for forwarding + logic [data_width_p-1:0] rd_data_r; + bsg_dff + #(.width_p(data_width_p)) + rd_reg + (.clk_i(clk_i) + ,.data_i(rd_data_i) + ,.data_o(rd_data_r) + ); + + for (genvar i = 0; i < read_ports_p; i++) + begin : bypass + logic zero_rs_r, fwd_rs_r, rs_r_v_r; + logic [data_width_p-1:0] fwd_data_lo; + wire zero_rs = rs_r_v_i[i] & (rs_addr_i[i] == '0) & (zero_x0_p == 1); + wire fwd_rs = rd_w_v_i & rs_r_v_i[i] & (rd_addr_i == rs_addr_i[i]); + bsg_dff + #(.width_p(3)) + rs_r_v_reg + (.clk_i(clk_i) + + ,.data_i({zero_rs, fwd_rs, rs_r_v_i[i]}) + ,.data_o({zero_rs_r, fwd_rs_r, rs_r_v_r}) + ); + assign fwd_data_lo = zero_rs_r ? '0 : fwd_rs_r ? rd_data_r : rs_data_lo[i]; + + logic [reg_addr_width_gp-1:0] rs_addr_r; + bsg_dff_en + #(.width_p(reg_addr_width_gp)) + rs_addr_reg + (.clk_i(clk_i) + ,.en_i(rs_r_v_i[i]) + + ,.data_i(rs_addr_i[i]) + ,.data_o(rs_addr_r) + ); + + logic [data_width_p-1:0] rs_data_n, rs_data_r; + wire replace_rs = rd_w_v_i & (rs_addr_r == rd_addr_i); + assign rs_data_n = replace_rs ? rd_data_i : fwd_data_lo; + bsg_dff_en + #(.width_p(data_width_p)) + rs_data_reg + (.clk_i(clk_i) + + ,.en_i(rs_r_v_r | replace_rs) + ,.data_i(rs_data_n) + ,.data_o(rs_data_r) + ); + + // Technically, this is unnecessary, since most hardened SRAMs still write correctly + // on read-write conflicts, and the read is handled by forwarding. But this avoids + // nasty warnings and possible power sink. + assign rs_v_li[i] = rs_r_v_i[i] & ~fwd_rs; + assign rs_addr_li[i] = rs_addr_i[i]; + // Forward if we read/wrote, else pass out the register data + assign rs_data_o[i] = rs_r_v_r ? fwd_data_lo : rs_data_r; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_be_regfile) + diff --git a/designs/black-parrot/src/bp/bp_be_reservation.sv b/designs/black-parrot/src/bp/bp_be_reservation.sv new file mode 100644 index 0000000..e832069 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_reservation.sv @@ -0,0 +1,122 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_reservation + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + ) + (input clk_i + , input reset_i + + , input [dispatch_pkt_width_lp-1:0] dispatch_pkt_i + , input [2:0][dpath_width_gp-1:0] bypass_rs_i + + , output logic [reservation_width_lp-1:0] reservation_o + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + `bp_cast_i(bp_be_dispatch_pkt_s, dispatch_pkt); + `bp_cast_o(bp_be_reservation_s, reservation); + + // TODO: Input boxing + bp_be_dispatch_pkt_s dispatch_pkt_n, dispatch_pkt_r; + always_comb + begin + dispatch_pkt_n = dispatch_pkt_cast_i; + dispatch_pkt_n.rs1 = bypass_rs_i[0]; + dispatch_pkt_n.rs2 = bypass_rs_i[1]; + dispatch_pkt_n.imm = bypass_rs_i[2]; + end + + bsg_dff + #(.width_p(dispatch_pkt_width_lp)) + dispatch_pkt_reg + (.clk_i(clk_i) + ,.data_i(dispatch_pkt_n) + ,.data_o(dispatch_pkt_r) + ); + + // Output unboxing + // TODO: Investigate retiming potential + bp_be_decode_s decode; + assign decode = dispatch_pkt_r.decode; + + bp_hardfloat_rec_dp_s frs1; + bp_be_fp_unbox + #(.bp_params_p(bp_params_p)) + frs1_unbox + (.reg_i(dispatch_pkt_r.rs1) + ,.tag_i(decode.frs1_tag) + ,.raw_i(decode.fmove_v) + ,.val_o(frs1) + ); + + bp_hardfloat_rec_dp_s frs2; + bp_be_fp_unbox + #(.bp_params_p(bp_params_p)) + frs2_unbox + (.reg_i(dispatch_pkt_r.rs2) + ,.tag_i(decode.frs2_tag) + ,.raw_i(decode.fmove_v) + ,.val_o(frs2) + ); + + bp_hardfloat_rec_dp_s frs3; + bp_be_fp_unbox + #(.bp_params_p(bp_params_p)) + frs3_unbox + (.reg_i(dispatch_pkt_r.imm) + ,.tag_i(decode.frs3_tag) + ,.raw_i(decode.fmove_v) + ,.val_o(frs3) + ); + + logic [int_rec_width_gp-1:0] rs1; + bp_be_int_unbox + #(.bp_params_p(bp_params_p)) + irs1_unbox + (.reg_i(dispatch_pkt_r.rs1) + ,.tag_i(decode.irs1_tag) + ,.unsigned_i(decode.irs1_unsigned) + ,.val_o(rs1) + ); + + logic [int_rec_width_gp-1:0] rs2; + bp_be_int_unbox + #(.bp_params_p(bp_params_p)) + irs2_unbox + (.reg_i(dispatch_pkt_r.rs2) + ,.tag_i(decode.irs2_tag) + ,.unsigned_i(decode.irs2_unsigned) + ,.val_o(rs2) + ); + + wire [int_rec_width_gp-1:0] imm = dispatch_pkt_r.imm; + + bp_be_reservation_s reservation; + always_comb + begin + reservation = '0; + reservation.v = dispatch_pkt_r.v; + reservation.pc = dispatch_pkt_r.pc; + reservation.instr = dispatch_pkt_r.instr; + reservation.decode = dispatch_pkt_r.decode; + reservation.size = dispatch_pkt_r.size; + reservation.count = dispatch_pkt_r.count; + + reservation.isrc1 = rs1; + reservation.isrc2 = rs2; + reservation.isrc3 = imm; + reservation.fsrc1 = frs1; + reservation.fsrc2 = frs2; + reservation.fsrc3 = frs3; + end + + assign reservation_cast_o = reservation; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_scheduler.sv b/designs/black-parrot/src/bp/bp_be_scheduler.sv new file mode 100644 index 0000000..ffd3708 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_scheduler.sv @@ -0,0 +1,267 @@ +/** + * + * Name: + * bp_be_scheduler.v + * + * Description: + * Schedules instruction issue from the FE queue to the Calculator. + * + * Notes: + * It might make sense to use an enum for RISC-V opcodes rather than `defines. + * Floating point instruction decoding is not implemented, so we do not predecode. + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_scheduler + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + ) + (input clk_i + , input reset_i + + , output logic [issue_pkt_width_lp-1:0] issue_pkt_o + , input [vaddr_width_p-1:0] expected_npc_i + , input clear_iss_i + , input suppress_iss_i + , input resume_i + , input [decode_info_width_lp-1:0] decode_info_i + , input hazard_v_i + , input irq_pending_i + , input ispec_v_i + , input poison_isd_i + , input ordered_v_i + , input [trans_info_width_lp-1:0] trans_info_i + + // Fetch interface + , input [fe_queue_width_lp-1:0] fe_queue_i + , input fe_queue_v_i + , output logic fe_queue_ready_and_o + + // Dispatch interface + , output logic [dispatch_pkt_width_lp-1:0] dispatch_pkt_o + , input [commit_pkt_width_lp-1:0] commit_pkt_i + , input [wb_pkt_width_lp-1:0] iwb_pkt_i + , input [wb_pkt_width_lp-1:0] fwb_pkt_i + + , input [wb_pkt_width_lp-1:0] late_wb_pkt_i + , input late_wb_v_i + , input late_wb_force_i + , output logic late_wb_yumi_o + ); + + // Declare parameterizable structures + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + `bp_cast_o(bp_be_issue_pkt_s, issue_pkt); + `bp_cast_o(bp_be_dispatch_pkt_s, dispatch_pkt); + `bp_cast_i(bp_be_commit_pkt_s, commit_pkt); + `bp_cast_i(bp_be_wb_pkt_s, iwb_pkt); + `bp_cast_i(bp_be_wb_pkt_s, fwb_pkt); + `bp_cast_i(bp_be_wb_pkt_s, late_wb_pkt); + `bp_cast_i(bp_be_trans_info_s, trans_info); + + logic ptw_busy_lo; + logic ptw_v_lo, ptw_walk_lo, ptw_itlb_fill_lo, ptw_dtlb_fill_lo; + logic [fetch_ptr_p-1:0] ptw_count_lo; + logic ptw_instr_page_fault_lo, ptw_load_page_fault_lo, ptw_store_page_fault_lo; + logic [dword_width_gp-1:0] ptw_addr_lo, ptw_pte_lo; + wire ptw_v_li = late_wb_yumi_o & late_wb_pkt_cast_i.ptw_w_v; + wire [dword_width_gp-1:0] ptw_data_li = late_wb_pkt_cast_i.rd_data; + bp_be_ptw + #(.bp_params_p(bp_params_p) + ,.pte_width_p(sv39_pte_width_gp) + ,.page_table_depth_p(sv39_levels_gp) + ,.pte_size_in_bytes_p(sv39_pte_size_in_bytes_gp) + ,.page_idx_width_p(sv39_page_idx_width_gp) + ) + ptw + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.busy_o(ptw_busy_lo) + ,.commit_pkt_i(commit_pkt_cast_i) + ,.trans_info_i(trans_info_cast_i) + ,.ordered_i(ordered_v_i) + + ,.v_o(ptw_v_lo) + ,.walk_o(ptw_walk_lo) + ,.itlb_fill_o(ptw_itlb_fill_lo) + ,.dtlb_fill_o(ptw_dtlb_fill_lo) + ,.instr_page_fault_o(ptw_instr_page_fault_lo) + ,.load_page_fault_o(ptw_load_page_fault_lo) + ,.store_page_fault_o(ptw_store_page_fault_lo) + ,.count_o(ptw_count_lo) + ,.addr_o(ptw_addr_lo) + ,.pte_o(ptw_pte_lo) + + ,.v_i(ptw_v_li) + ,.data_i(ptw_data_li) + ); + + // Prioritization is: + // 1/2) ptw_fill_pkt/writeback pkt, since there is no backpressure + // 2) resume request + // 3) interrupt request + // 4) finally, fe queue + wire writeback_v = late_wb_v_i & (late_wb_force_i | ~issue_pkt_cast_o.v); + wire resume_v = ~writeback_v & ~ptw_busy_lo & resume_i; + wire interrupt_v = ~writeback_v & ~ptw_busy_lo & ~resume_i & irq_pending_i; + + wire be_exc_not_instr_li = ptw_v_lo | writeback_v | resume_v | interrupt_v; + wire fe_exc_not_instr_li = ~be_exc_not_instr_li & issue_pkt_cast_o.v & !issue_pkt_cast_o.fetch; + wire fe_instr_not_exc_li = ~be_exc_not_instr_li & issue_pkt_cast_o.v & issue_pkt_cast_o.fetch; + + localparam entry_cinstr_gp = 2**fetch_sel_p; + localparam op_ptr_width_lp = `BSG_WIDTH(entry_cinstr_gp); + wire fe_queue_en_li = ~suppress_iss_i & ~ptw_busy_lo & ~hazard_v_i; + wire fe_queue_clr_li = clear_iss_i; + wire fe_queue_roll_li = commit_pkt_cast_i.npc_w_v; + wire fe_queue_read_li = fe_instr_not_exc_li | fe_exc_not_instr_li; + wire [op_ptr_width_lp-1:0] fe_queue_read_size_li = issue_pkt_cast_o.size; + wire [op_ptr_width_lp-1:0] fe_queue_read_cnt_li = issue_pkt_cast_o.count; + wire fe_queue_cmt_li = commit_pkt_cast_i.instret; + wire [op_ptr_width_lp-1:0] fe_queue_cmt_size_li = commit_pkt_cast_i.size; + wire [op_ptr_width_lp-1:0] fe_queue_cmt_cnt_li = commit_pkt_cast_i.count; + + // Could more intelligently schedule these late writebacks, based on availability and dependencies + assign late_wb_yumi_o = writeback_v; + + bp_be_preissue_pkt_s preissue_pkt; + bp_be_issue_queue + #(.bp_params_p(bp_params_p)) + issue_queue + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.en_i(fe_queue_en_li) + ,.clr_i(fe_queue_clr_li) + ,.roll_i(fe_queue_roll_li) + ,.read_i(fe_queue_read_li) + ,.read_cnt_i(fe_queue_read_cnt_li) + ,.read_size_i(fe_queue_read_size_li) + ,.cmt_i(fe_queue_cmt_li) + ,.cmt_cnt_i(fe_queue_cmt_cnt_li) + ,.cmt_size_i(fe_queue_cmt_size_li) + + ,.fe_queue_i(fe_queue_i) + ,.fe_queue_v_i(fe_queue_v_i) + ,.fe_queue_ready_and_o(fe_queue_ready_and_o) + + ,.decode_info_i(decode_info_i) + ,.preissue_pkt_o(preissue_pkt) + ,.issue_pkt_o(issue_pkt_cast_o) + ); + rv64_instr_fmatype_s preissue_instr; + assign preissue_instr = preissue_pkt.instr; + + logic [dpath_width_gp-1:0] irf_rs1, irf_rs2; + bp_be_regfile + #(.bp_params_p(bp_params_p), .read_ports_p(2), .zero_x0_p(1), .data_width_p($bits(bp_be_int_reg_s))) + int_regfile + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.rd_w_v_i(iwb_pkt_cast_i.ird_w_v) + ,.rd_addr_i(iwb_pkt_cast_i.rd_addr) + ,.rd_data_i(iwb_pkt_cast_i.rd_data) + + ,.rs_r_v_i({preissue_pkt.irs2_v, preissue_pkt.irs1_v}) + ,.rs_addr_i({preissue_instr.rs2_addr, preissue_instr.rs1_addr}) + ,.rs_data_o({irf_rs2, irf_rs1}) + ); + + logic [dpath_width_gp-1:0] frf_rs1, frf_rs2, frf_rs3; + bp_be_regfile + #(.bp_params_p(bp_params_p), .read_ports_p(3), .zero_x0_p(0), .data_width_p($bits(bp_be_fp_reg_s))) + fp_regfile + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.rd_w_v_i(fwb_pkt_cast_i.frd_w_v) + ,.rd_addr_i(fwb_pkt_cast_i.rd_addr) + ,.rd_data_i(fwb_pkt_cast_i.rd_data) + + ,.rs_r_v_i({preissue_pkt.frs3_v, preissue_pkt.frs2_v, preissue_pkt.frs1_v}) + ,.rs_addr_i({preissue_instr.rs3_addr, preissue_instr.rs2_addr, preissue_instr.rs1_addr}) + ,.rs_data_o({frf_rs3, frf_rs2, frf_rs1}) + ); + + bp_be_decode_s fe_exc_decode_li; + rv64_instr_fmatype_s fe_exc_instr_li; + wire [vaddr_width_p-1:0] fe_exc_pc_li = issue_pkt_cast_o.pc; + wire [vaddr_width_p-1:0] fe_exc_vaddr_li = fe_exc_pc_li + (issue_pkt_cast_o.count << 1'b1); + wire [dpath_width_gp-1:0] fe_exc_data_li = '0; + wire [dpath_width_gp-1:0] fe_exc_imm_li = '0; + assign fe_exc_decode_li = '0; + assign fe_exc_instr_li = issue_pkt_cast_o.instr; + wire [fetch_ptr_p-1:0] fe_exc_size_li = issue_pkt_cast_o.size; + wire [fetch_ptr_p-1:0] fe_exc_count_li = issue_pkt_cast_o.count; + + bp_be_decode_s be_exc_decode_li, wb_decode_li, walk_decode_li; + rv64_instr_fmatype_s be_exc_instr_li, wb_instr_li; + wire [dpath_width_gp-1:0] be_exc_vaddr_li = ptw_v_lo ? ptw_addr_lo : writeback_v ? '0 : '0; + wire [dpath_width_gp-1:0] be_exc_data_li = ptw_v_lo ? ptw_pte_lo : writeback_v ? late_wb_pkt_cast_i.rd_data : '0; + wire [dpath_width_gp-1:0] be_exc_imm_li = ptw_v_lo ? '0 : writeback_v ? late_wb_pkt_cast_i.fflags : '0; + assign be_exc_decode_li = ptw_v_lo ? walk_decode_li : writeback_v ? wb_decode_li : '0; + assign be_exc_instr_li = ptw_v_lo ? issue_pkt_cast_o.instr : writeback_v ? wb_instr_li : '0; + wire [fetch_ptr_p-1:0] be_exc_size_li = '0; + wire [fetch_ptr_p-1:0] be_exc_count_li = ptw_v_lo ? ptw_count_lo : writeback_v ? '0 : '0; + + assign wb_instr_li = '{rd_addr: late_wb_pkt_cast_i.rd_addr, default: '0}; + assign wb_decode_li = '{irf_w_v: late_wb_pkt_cast_i.ird_w_v, frf_w_v: late_wb_pkt_cast_i.frd_w_v, default: '0}; + assign walk_decode_li = '{pipe_mem_final_v: ptw_walk_lo, dcache_mmu_v: ptw_walk_lo, fu_op: e_dcache_op_ptw, default: '0}; + + always_comb + begin + // Form dispatch packet + dispatch_pkt_cast_o = '0; + dispatch_pkt_cast_o.v = (fe_queue_read_li & ~poison_isd_i) || be_exc_not_instr_li; + dispatch_pkt_cast_o.queue_v = (fe_queue_read_li & ~poison_isd_i); + dispatch_pkt_cast_o.ispec_v = fe_instr_not_exc_li & ispec_v_i; + dispatch_pkt_cast_o.nspec_v = ptw_v_lo | writeback_v; + dispatch_pkt_cast_o.pc = expected_npc_i; + dispatch_pkt_cast_o.instr = be_exc_not_instr_li ? be_exc_instr_li : fe_exc_not_instr_li ? fe_exc_instr_li : issue_pkt_cast_o.instr; + dispatch_pkt_cast_o.size = be_exc_not_instr_li ? be_exc_size_li : fe_exc_not_instr_li ? fe_exc_size_li : issue_pkt_cast_o.size; + dispatch_pkt_cast_o.count = be_exc_not_instr_li ? be_exc_count_li : fe_exc_not_instr_li ? fe_exc_count_li : issue_pkt_cast_o.count; + dispatch_pkt_cast_o.rs1 = be_exc_not_instr_li ? be_exc_vaddr_li : fe_exc_not_instr_li ? fe_exc_vaddr_li : issue_pkt_cast_o.decode.frs1_r_v ? frf_rs1 : irf_rs1; + dispatch_pkt_cast_o.rs2 = be_exc_not_instr_li ? be_exc_data_li : fe_exc_not_instr_li ? fe_exc_data_li : issue_pkt_cast_o.decode.frs2_r_v ? frf_rs2 : irf_rs2; + dispatch_pkt_cast_o.imm = be_exc_not_instr_li ? be_exc_imm_li : fe_exc_not_instr_li ? fe_exc_imm_li : issue_pkt_cast_o.decode.frs3_r_v ? frf_rs3 : issue_pkt_cast_o.imm; + dispatch_pkt_cast_o.decode = be_exc_not_instr_li ? be_exc_decode_li : fe_exc_not_instr_li ? fe_exc_decode_li : issue_pkt_cast_o.decode; + + dispatch_pkt_cast_o.exception.instr_page_fault |= be_exc_not_instr_li & ptw_instr_page_fault_lo; + dispatch_pkt_cast_o.exception.load_page_fault |= be_exc_not_instr_li & ptw_load_page_fault_lo; + dispatch_pkt_cast_o.exception.store_page_fault |= be_exc_not_instr_li & ptw_store_page_fault_lo; + dispatch_pkt_cast_o.exception.itlb_fill |= be_exc_not_instr_li & ptw_itlb_fill_lo; + dispatch_pkt_cast_o.exception.dtlb_fill |= be_exc_not_instr_li & ptw_dtlb_fill_lo; + dispatch_pkt_cast_o.exception.resume |= be_exc_not_instr_li & resume_v; + dispatch_pkt_cast_o.exception._interrupt |= be_exc_not_instr_li & interrupt_v; + + dispatch_pkt_cast_o.exception.instr_access_fault |= fe_exc_not_instr_li & issue_pkt_cast_o.instr_access_fault; + dispatch_pkt_cast_o.exception.instr_page_fault |= fe_exc_not_instr_li & issue_pkt_cast_o.instr_page_fault; + dispatch_pkt_cast_o.exception.itlb_miss |= fe_exc_not_instr_li & issue_pkt_cast_o.itlb_miss; + dispatch_pkt_cast_o.exception.icache_miss |= fe_exc_not_instr_li & issue_pkt_cast_o.icache_miss; + dispatch_pkt_cast_o.exception.illegal_instr |= fe_exc_not_instr_li & issue_pkt_cast_o.illegal_instr; + + dispatch_pkt_cast_o.exception.ecall_m |= fe_instr_not_exc_li & issue_pkt_cast_o.ecall_m; + dispatch_pkt_cast_o.exception.ecall_s |= fe_instr_not_exc_li & issue_pkt_cast_o.ecall_s; + dispatch_pkt_cast_o.exception.ecall_u |= fe_instr_not_exc_li & issue_pkt_cast_o.ecall_u; + dispatch_pkt_cast_o.exception.ebreak |= fe_instr_not_exc_li & issue_pkt_cast_o.ebreak; + dispatch_pkt_cast_o.special.dbreak |= fe_instr_not_exc_li & issue_pkt_cast_o.dbreak; + dispatch_pkt_cast_o.special.dret |= fe_instr_not_exc_li & issue_pkt_cast_o.dret; + dispatch_pkt_cast_o.special.mret |= fe_instr_not_exc_li & issue_pkt_cast_o.mret; + dispatch_pkt_cast_o.special.sret |= fe_instr_not_exc_li & issue_pkt_cast_o.sret; + dispatch_pkt_cast_o.special.wfi |= fe_instr_not_exc_li & issue_pkt_cast_o.wfi; + dispatch_pkt_cast_o.special.sfence_vma |= fe_instr_not_exc_li & issue_pkt_cast_o.sfence_vma; + dispatch_pkt_cast_o.special.fencei |= fe_instr_not_exc_li & issue_pkt_cast_o.fencei; + dispatch_pkt_cast_o.special.csrw |= fe_instr_not_exc_li & issue_pkt_cast_o.csrw; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_be_scoreboard.sv b/designs/black-parrot/src/bp/bp_be_scoreboard.sv new file mode 100644 index 0000000..2cf079c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_scoreboard.sv @@ -0,0 +1,70 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_scoreboard + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(num_rs_p) + ) + (input clk_i + , input reset_i + + , input score_v_i + , input [reg_addr_width_gp-1:0] score_rd_i + + , input clear_v_i + , input [reg_addr_width_gp-1:0] clear_rd_i + + , input [num_rs_p-1:0][reg_addr_width_gp-1:0] check_rs_i + , input [reg_addr_width_gp-1:0] check_rd_i + + , output logic [num_rs_p-1:0] rs_match_o + , output logic rd_match_o + ); + + localparam rf_els_lp = 2**reg_addr_width_gp; + logic [rf_els_lp-1:0] scoreboard_r; + + logic [rf_els_lp-1:0] score_onehot_li; + bsg_decode_with_v + #(.num_out_p(rf_els_lp)) + score_decode + (.i(score_rd_i) + ,.v_i(score_v_i) + ,.o(score_onehot_li) + ); + + logic [rf_els_lp-1:0] clear_onehot_li; + bsg_decode_with_v + #(.num_out_p(rf_els_lp)) + clear_decode + (.i(clear_rd_i) + ,.v_i(clear_v_i) + ,.o(clear_onehot_li) + ); + + bsg_dff_reset_set_clear + #(.width_p(rf_els_lp), .clear_over_set_p(1)) + scoreboard_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.set_i(score_onehot_li) + ,.clear_i(clear_onehot_li) + ,.data_o(scoreboard_r) + ); + + for (genvar i = 0; i < num_rs_p; i++) + begin : rs + assign rs_match_o[i] = scoreboard_r[check_rs_i[i]]; + end + assign rd_match_o = scoreboard_r[check_rd_i]; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_be_scoreboard) + diff --git a/designs/black-parrot/src/bp/bp_be_top.sv b/designs/black-parrot/src/bp/bp_be_top.sv new file mode 100644 index 0000000..448c853 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_be_top.sv @@ -0,0 +1,252 @@ +/** + * + * Name: + * bp_be_top.v + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_be_top + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, dcache_tag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_gp, dcache_block_width_p, dcache_fill_width_p, dcache_req_id_width_p) + + // Default parameters + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + // Processor configuration + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // FE queue interface + , input [fe_queue_width_lp-1:0] fe_queue_i + , input fe_queue_v_i + , output logic fe_queue_ready_and_o + + // FE cmd interface + , output logic [fe_cmd_width_lp-1:0] fe_cmd_o + , output logic fe_cmd_v_o + , input fe_cmd_yumi_i + + // D$-LCE Interface + // signals to LCE + , output logic [dcache_req_width_lp-1:0] cache_req_o + , output logic cache_req_v_o + , input cache_req_yumi_i + , input cache_req_lock_i + , output logic [dcache_req_metadata_width_lp-1:0] cache_req_metadata_o + , output logic cache_req_metadata_v_o + , input [dcache_req_id_width_p-1:0] cache_req_id_i + , input cache_req_critical_i + , input cache_req_last_i + , input cache_req_credits_full_i + , input cache_req_credits_empty_i + + // tag_mem + , input tag_mem_pkt_v_i + , input [dcache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , output logic [dcache_tag_info_width_lp-1:0] tag_mem_o + , output logic tag_mem_pkt_yumi_o + + // data_mem + , input data_mem_pkt_v_i + , input [dcache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , output logic [dcache_block_width_p-1:0] data_mem_o + , output logic data_mem_pkt_yumi_o + + // stat_mem + , input stat_mem_pkt_v_i + , input [dcache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , output logic [dcache_stat_info_width_lp-1:0] stat_mem_o + , output logic stat_mem_pkt_yumi_o + + , input debug_irq_i + , input timer_irq_i + , input software_irq_i + , input m_external_irq_i + , input s_external_irq_i + ); + + // Declare parameterized structures + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + // Top-level interface connections + bp_be_dispatch_pkt_s dispatch_pkt; + bp_be_branch_pkt_s br_pkt; + + logic ordered_v, hazard_v, ispec_v; + logic irq_pending_lo, irq_waiting_lo; + + bp_be_commit_pkt_s commit_pkt; + bp_be_wb_pkt_s iwb_pkt, fwb_pkt; + bp_be_decode_info_s decode_info_lo; + bp_be_trans_info_s trans_info_lo; + + logic [wb_pkt_width_lp-1:0] late_wb_pkt; + logic late_wb_v_lo, late_wb_force_lo, late_wb_yumi_li; + + bp_be_issue_pkt_s issue_pkt; + logic [vaddr_width_p-1:0] expected_npc_lo; + logic npc_mismatch_lo, poison_isd_lo, clear_iss_lo, suppress_iss_lo, resume_lo; + + logic cmd_full_n_lo, cmd_full_r_lo, cmd_empty_n_lo, cmd_empty_r_lo; + logic mem_ordered_lo, mem_busy_lo, idiv_busy_lo, fdiv_busy_lo; + + bp_be_director + #(.bp_params_p(bp_params_p)) + director + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.cfg_bus_i(cfg_bus_i) + + ,.issue_pkt_i(issue_pkt) + ,.expected_npc_o(expected_npc_lo) + + ,.fe_cmd_o(fe_cmd_o) + ,.fe_cmd_v_o(fe_cmd_v_o) + ,.fe_cmd_yumi_i(fe_cmd_yumi_i) + + ,.resume_o(resume_lo) + ,.poison_isd_o(poison_isd_lo) + ,.clear_iss_o(clear_iss_lo) + ,.suppress_iss_o(suppress_iss_lo) + ,.irq_waiting_i(irq_waiting_lo) + ,.mem_busy_i(mem_busy_lo) + ,.cmd_full_n_o(cmd_full_n_lo) + ,.cmd_full_r_o(cmd_full_r_lo) + + ,.br_pkt_i(br_pkt) + ,.commit_pkt_i(commit_pkt) + ); + + bp_be_detector + #(.bp_params_p(bp_params_p)) + detector + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.issue_pkt_i(issue_pkt) + ,.cmd_full_i(cmd_full_r_lo) + ,.credits_full_i(cache_req_credits_full_i) + ,.credits_empty_i(cache_req_credits_empty_i) + ,.mem_busy_i(mem_busy_lo) + ,.mem_ordered_i(mem_ordered_lo) + ,.fdiv_busy_i(fdiv_busy_lo) + ,.idiv_busy_i(idiv_busy_lo) + ,.ispec_v_o(ispec_v) + ,.hazard_v_o(hazard_v) + ,.ordered_v_o(ordered_v) + ,.dispatch_pkt_i(dispatch_pkt) + ,.commit_pkt_i(commit_pkt) + + ,.late_wb_pkt_i(late_wb_pkt) + ,.late_wb_yumi_i(late_wb_yumi_li) + ); + + bp_be_scheduler + #(.bp_params_p(bp_params_p)) + scheduler + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.poison_isd_i(poison_isd_lo) + ,.resume_i(resume_lo) + ,.decode_info_i(decode_info_lo) + ,.trans_info_i(trans_info_lo) + ,.issue_pkt_o(issue_pkt) + ,.suppress_iss_i(suppress_iss_lo) + ,.clear_iss_i(clear_iss_lo) + ,.expected_npc_i(expected_npc_lo) + ,.hazard_v_i(hazard_v) + ,.ispec_v_i(ispec_v) + ,.irq_pending_i(irq_pending_lo) + ,.ordered_v_i(ordered_v) + + ,.fe_queue_i(fe_queue_i) + ,.fe_queue_v_i(fe_queue_v_i) + ,.fe_queue_ready_and_o(fe_queue_ready_and_o) + + ,.dispatch_pkt_o(dispatch_pkt) + ,.commit_pkt_i(commit_pkt) + ,.iwb_pkt_i(iwb_pkt) + ,.fwb_pkt_i(fwb_pkt) + + ,.late_wb_pkt_i(late_wb_pkt) + ,.late_wb_v_i(late_wb_v_lo) + ,.late_wb_force_i(late_wb_force_lo) + ,.late_wb_yumi_o(late_wb_yumi_li) + ); + + bp_be_calculator_top + #(.bp_params_p(bp_params_p)) + calculator + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.cfg_bus_i(cfg_bus_i) + + ,.decode_info_o(decode_info_lo) + ,.trans_info_o(trans_info_lo) + ,.mem_busy_o(mem_busy_lo) + ,.mem_ordered_o(mem_ordered_lo) + ,.idiv_busy_o(idiv_busy_lo) + ,.fdiv_busy_o(fdiv_busy_lo) + + ,.dispatch_pkt_i(dispatch_pkt) + ,.br_pkt_o(br_pkt) + ,.commit_pkt_o(commit_pkt) + ,.iwb_pkt_o(iwb_pkt) + ,.fwb_pkt_o(fwb_pkt) + + ,.late_wb_pkt_o(late_wb_pkt) + ,.late_wb_v_o(late_wb_v_lo) + ,.late_wb_force_o(late_wb_force_lo) + ,.late_wb_yumi_i(late_wb_yumi_li) + + ,.cache_req_o(cache_req_o) + ,.cache_req_metadata_o(cache_req_metadata_o) + ,.cache_req_v_o(cache_req_v_o) + ,.cache_req_yumi_i(cache_req_yumi_i) + ,.cache_req_lock_i(cache_req_lock_i) + ,.cache_req_metadata_v_o(cache_req_metadata_v_o) + ,.cache_req_id_i(cache_req_id_i) + ,.cache_req_critical_i(cache_req_critical_i) + ,.cache_req_last_i(cache_req_last_i) + ,.cache_req_credits_full_i(cache_req_credits_full_i) + ,.cache_req_credits_empty_i(cache_req_credits_empty_i) + + ,.tag_mem_pkt_v_i(tag_mem_pkt_v_i) + ,.tag_mem_pkt_i(tag_mem_pkt_i) + ,.tag_mem_o(tag_mem_o) + ,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o) + + ,.data_mem_pkt_v_i(data_mem_pkt_v_i) + ,.data_mem_pkt_i(data_mem_pkt_i) + ,.data_mem_o(data_mem_o) + ,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o) + + ,.stat_mem_pkt_v_i(stat_mem_pkt_v_i) + ,.stat_mem_pkt_i(stat_mem_pkt_i) + ,.stat_mem_o(stat_mem_o) + ,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o) + + ,.debug_irq_i(debug_irq_i) + ,.timer_irq_i(timer_irq_i) + ,.software_irq_i(software_irq_i) + ,.m_external_irq_i(m_external_irq_i) + ,.s_external_irq_i(s_external_irq_i) + ,.irq_pending_o(irq_pending_lo) + ,.irq_waiting_o(irq_waiting_lo) + ,.cmd_full_n_i(cmd_full_n_lo) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_bedrock_size_to_len.sv b/designs/black-parrot/src/bp/bp_bedrock_size_to_len.sv new file mode 100644 index 0000000..5374f7d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_bedrock_size_to_len.sv @@ -0,0 +1,66 @@ +/** + * + * Name: + * bp_bedrock_size_to_len.sv + * + * Description: + * This module computes the number of data beats required to send the data field of + * a BedRock message based on a BedRock size field and the specified data beat width. + * + * len_width_p is the width to use for the output length integer + * + * beat_width_p is the number of bits per data beat + * + * The len_o output is zero-based and equal to msg_size_bytes / data beat width - 1 + * + * (1 << e_bedrock_msg_size_X) gives the number of bytes for the message size enum value + * + */ + +`include "bp_common_defines.svh" + +module bp_bedrock_size_to_len + import bp_common_pkg::*; + #(parameter `BSG_INV_PARAM(beat_width_p) + , parameter `BSG_INV_PARAM(len_width_p) + ) + (input bp_bedrock_msg_size_e size_i + , output logic [len_width_p-1:0] len_o + ); + + localparam msg_size_1_beats_lp = `BSG_CDIV((1 << e_bedrock_msg_size_1)*8, beat_width_p) - 1; + localparam msg_size_2_beats_lp = `BSG_CDIV((1 << e_bedrock_msg_size_2)*8, beat_width_p) - 1; + localparam msg_size_4_beats_lp = `BSG_CDIV((1 << e_bedrock_msg_size_4)*8, beat_width_p) - 1; + localparam msg_size_8_beats_lp = `BSG_CDIV((1 << e_bedrock_msg_size_8)*8, beat_width_p) - 1; + localparam msg_size_16_beats_lp = `BSG_CDIV((1 << e_bedrock_msg_size_16)*8, beat_width_p) - 1; + localparam msg_size_32_beats_lp = `BSG_CDIV((1 << e_bedrock_msg_size_32)*8, beat_width_p) - 1; + localparam msg_size_64_beats_lp = `BSG_CDIV((1 << e_bedrock_msg_size_64)*8, beat_width_p) - 1; + localparam msg_size_128_beats_lp = `BSG_CDIV((1 << e_bedrock_msg_size_128)*8, beat_width_p) - 1; + + // parameter checks + if (!(len_width_p >= `BSG_SAFE_CLOG2(msg_size_128_beats_lp))) + $error("len_width_p must be large enough for max size messages, !(%d >= %d)" + , len_width_p, `BSG_SAFE_CLOG2(msg_size_128_beats_lp)); + if (!(`BSG_IS_POW2(beat_width_p))) + $error("beat_width_p must be a power of two"); + if (beat_width_p < 8) + $error("beat_width_p must be at least 8 bits wide"); + + always_comb begin + unique case (size_i) + e_bedrock_msg_size_1: len_o = len_width_p'(msg_size_1_beats_lp); + e_bedrock_msg_size_2: len_o = len_width_p'(msg_size_2_beats_lp); + e_bedrock_msg_size_4: len_o = len_width_p'(msg_size_4_beats_lp); + e_bedrock_msg_size_8: len_o = len_width_p'(msg_size_8_beats_lp); + e_bedrock_msg_size_16: len_o = len_width_p'(msg_size_16_beats_lp); + e_bedrock_msg_size_32: len_o = len_width_p'(msg_size_32_beats_lp); + e_bedrock_msg_size_64: len_o = len_width_p'(msg_size_64_beats_lp); + e_bedrock_msg_size_128: len_o = len_width_p'(msg_size_128_beats_lp); + default: len_o = '0; + endcase + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_bedrock_size_to_len) + diff --git a/designs/black-parrot/src/bp/bp_cacc_complex.sv b/designs/black-parrot/src/bp/bp_cacc_complex.sv new file mode 100644 index 0000000..073aa54 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cacc_complex.sv @@ -0,0 +1,184 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_cacc_complex + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + ) + (input core_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input [cac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_link_i + , output [cac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_link_o + + , input [cac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_i + , output [cac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_o + + , input [cac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_link_i + , output [cac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_link_o + + , input [cac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_link_i + , output [cac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_link_o + ); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + + bp_coh_ready_and_link_s [cac_y_dim_p-1:0][S:W] lce_req_link_li, lce_req_link_lo; + bp_coh_ready_and_link_s [E:W][cac_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; + bp_coh_ready_and_link_s [S:N] lce_req_ver_link_li, lce_req_ver_link_lo; + + bp_coh_ready_and_link_s [cac_y_dim_p-1:0][S:W] lce_cmd_link_li, lce_cmd_link_lo; + bp_coh_ready_and_link_s [E:W][cac_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; + bp_coh_ready_and_link_s [S:N] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; + + bp_coh_ready_and_link_s [cac_y_dim_p-1:0][S:W] lce_fill_link_li, lce_fill_link_lo; + bp_coh_ready_and_link_s [E:W][cac_y_dim_p-1:0] lce_fill_hor_link_li, lce_fill_hor_link_lo; + bp_coh_ready_and_link_s [S:N] lce_fill_ver_link_li, lce_fill_ver_link_lo; + + bp_coh_ready_and_link_s [cac_y_dim_p-1:0][S:W] lce_resp_link_li, lce_resp_link_lo; + bp_coh_ready_and_link_s [E:W][cac_y_dim_p-1:0] lce_resp_hor_link_li, lce_resp_hor_link_lo; + bp_coh_ready_and_link_s [S:N] lce_resp_ver_link_li, lce_resp_ver_link_lo; + + + for (genvar j=0; j < cac_y_dim_p; j++) + begin : y + wire [coh_noc_cord_width_p-1:0] cord_li = {coh_noc_y_cord_width_p'(ic_y_dim_p+j), + coh_noc_x_cord_width_p'(sac_x_dim_p+cc_x_dim_p)}; + if (cac_x_dim_p > 0) + begin: node + bp_cacc_tile_node + #(.bp_params_p(bp_params_p)) + accel_tile_node + (.core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.my_cord_i(cord_li) + + ,.coh_lce_req_link_i(lce_req_link_li[j]) + ,.coh_lce_resp_link_i(lce_resp_link_li[j]) + ,.coh_lce_cmd_link_i(lce_cmd_link_li[j]) + ,.coh_lce_fill_link_i(lce_fill_link_li[j]) + + ,.coh_lce_req_link_o(lce_req_link_lo[j]) + ,.coh_lce_resp_link_o(lce_resp_link_lo[j]) + ,.coh_lce_cmd_link_o(lce_cmd_link_lo[j]) + ,.coh_lce_fill_link_o(lce_fill_link_lo[j]) + ); + end + else + begin : stub + assign lce_req_link_lo[j] = '0; + assign lce_cmd_link_lo[j] = '0; + assign lce_fill_link_lo[j] = '0; + assign lce_resp_link_lo[j] = '0; + end + end + + + if (cac_x_dim_p > 0) + begin : ac_stitch + assign lce_req_ver_link_li = '0; + assign lce_req_hor_link_li[E] = '0; + assign lce_req_hor_link_li[W] = coh_req_link_i; + + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(cac_x_dim_p) + ,.y_max_p(cac_y_dim_p) + ) + coh_req_mesh + (.outs_i(lce_req_link_lo) + ,.ins_o(lce_req_link_li) + + ,.hor_i(lce_req_hor_link_li) + ,.hor_o(lce_req_hor_link_lo) + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); + assign coh_req_link_o = lce_req_hor_link_lo[W]; + + assign lce_cmd_ver_link_li = '0; + assign lce_cmd_hor_link_li[E] = '0; + assign lce_cmd_hor_link_li[W] = coh_cmd_link_i; + + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(cac_x_dim_p) + ,.y_max_p(cac_y_dim_p) + ) + coh_cmd_mesh + (.outs_i(lce_cmd_link_lo) + ,.ins_o(lce_cmd_link_li) + + ,.hor_i(lce_cmd_hor_link_li) + ,.hor_o(lce_cmd_hor_link_lo) + ,.ver_i(lce_cmd_ver_link_li) + ,.ver_o(lce_cmd_ver_link_lo) + ); + assign coh_cmd_link_o = lce_cmd_hor_link_lo[W]; + + assign lce_fill_ver_link_li = '0; + assign lce_fill_hor_link_li[E] = '0; + assign lce_fill_hor_link_li[W] = coh_fill_link_i; + + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(cac_x_dim_p) + ,.y_max_p(cac_y_dim_p) + ) + coh_fill_mesh + (.outs_i(lce_fill_link_lo) + ,.ins_o(lce_fill_link_li) + + ,.hor_i(lce_fill_hor_link_li) + ,.hor_o(lce_fill_hor_link_lo) + ,.ver_i(lce_fill_ver_link_li) + ,.ver_o(lce_fill_ver_link_lo) + ); + assign coh_fill_link_o = lce_fill_hor_link_lo[W]; + + assign lce_resp_ver_link_li = '0; + assign lce_resp_hor_link_li[E] = '0; + assign lce_resp_hor_link_li[W] = coh_resp_link_i; + + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(cac_x_dim_p) + ,.y_max_p(cac_y_dim_p) + ) + coh_resp_mesh + (.outs_i(lce_resp_link_lo) + ,.ins_o(lce_resp_link_li) + + ,.hor_i(lce_resp_hor_link_li) + ,.hor_o(lce_resp_hor_link_lo) + ,.ver_i(lce_resp_ver_link_li) + ,.ver_o(lce_resp_ver_link_lo) + ); + assign coh_resp_link_o = lce_resp_hor_link_lo[W]; + + end + else + begin : stub + assign coh_req_link_o = '0; + assign coh_cmd_link_o = '0; + assign coh_fill_link_o = '0; + assign coh_resp_link_o = '0; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_cacc_tile.sv b/designs/black-parrot/src/bp/bp_cacc_tile.sv new file mode 100644 index 0000000..29c6e57 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cacc_tile.sv @@ -0,0 +1,444 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" +`include "bsg_cache.svh" +`include "bsg_noc_links.svh" + +module bp_cacc_tile + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + import bp_top_pkg::*; + import bsg_cache_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) + , parameter accelerator_type_p = e_cacc_vdp + ) + (input clk_i + , input reset_i + + , input [coh_noc_cord_width_p-1:0] my_cord_i + + , input [coh_noc_ral_link_width_lp-1:0] lce_req_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_req_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_fill_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_fill_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_resp_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_resp_link_o + + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + + // LCE-CCE link casts + `bp_cast_i(bp_coh_ready_and_link_s, lce_req_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_req_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_cmd_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_cmd_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_fill_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_fill_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_resp_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_resp_link); + + //io-cce-side connections + bp_bedrock_lce_cmd_header_s lce_cmd_header_lo; + logic [acache_fill_width_p-1:0] lce_cmd_data_lo; + logic lce_cmd_v_lo, lce_cmd_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_cmd_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_cmd_dst_cid_lo; + + bp_bedrock_lce_req_header_s lce_req_header_li; + logic [acache_fill_width_p-1:0] lce_req_data_li; + logic lce_req_v_li, lce_req_ready_and_lo; + + bp_bedrock_mem_fwd_header_s mem_fwd_header_lo; + logic [acache_fill_width_p-1:0] mem_fwd_data_lo; + logic mem_fwd_v_lo, mem_fwd_ready_and_li; + + bp_bedrock_mem_rev_header_s mem_rev_header_li; + logic [acache_fill_width_p-1:0] mem_rev_data_li; + logic mem_rev_v_li, mem_rev_ready_and_lo; + + // accelerator-side connections network connections + bp_bedrock_lce_req_header_s lce_req_header_lo; + logic [acache_fill_width_p-1:0] lce_req_data_lo; + logic lce_req_v_lo, lce_req_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_req_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_req_dst_cid_lo; + + bp_bedrock_lce_cmd_header_s lce_cmd_header_li; + logic [acache_fill_width_p-1:0] lce_cmd_data_li; + logic lce_cmd_v_li, lce_cmd_ready_and_lo; + + bp_bedrock_lce_fill_header_s lce_fill_header_li; + logic [acache_fill_width_p-1:0] lce_fill_data_li; + logic lce_fill_v_li, lce_fill_ready_and_lo; + + bp_bedrock_lce_fill_header_s lce_fill_header_lo; + logic [acache_fill_width_p-1:0] lce_fill_data_lo; + logic lce_fill_v_lo, lce_fill_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_fill_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_fill_dst_cid_lo; + + bp_bedrock_lce_resp_header_s lce_resp_header_lo; + logic [acache_fill_width_p-1:0] lce_resp_data_lo; + logic lce_resp_v_lo, lce_resp_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_resp_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_resp_dst_cid_lo; + + logic reset_r; + always_ff @(posedge clk_i) + reset_r <= reset_i; + + logic [cce_id_width_p-1:0] cce_id_li; + logic [lce_id_width_p-1:0] lce_id_li; + bp_me_cord_to_id + #(.bp_params_p(bp_params_p)) + id_map + (.cord_i(my_cord_i) + ,.core_id_o() + ,.cce_id_o(cce_id_li) + ,.lce_id0_o(lce_id_li) + ,.lce_id1_o() + ); + + bp_io_cce + #(.bp_params_p(bp_params_p)) + io_cce + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.cce_id_i(cce_id_li) + + ,.lce_req_header_i(lce_req_header_li) + ,.lce_req_data_i(lce_req_data_li) + ,.lce_req_v_i(lce_req_v_li) + ,.lce_req_ready_and_o(lce_req_ready_and_lo) + + ,.lce_cmd_header_o(lce_cmd_header_lo) + ,.lce_cmd_data_o(lce_cmd_data_lo) + ,.lce_cmd_v_o(lce_cmd_v_lo) + ,.lce_cmd_ready_and_i(lce_cmd_ready_and_li) + + ,.mem_fwd_header_o(mem_fwd_header_lo) + ,.mem_fwd_data_o(mem_fwd_data_lo) + ,.mem_fwd_v_o(mem_fwd_v_lo) + ,.mem_fwd_ready_and_i(mem_fwd_ready_and_li) + + ,.mem_rev_header_i(mem_rev_header_li) + ,.mem_rev_data_i(mem_rev_data_li) + ,.mem_rev_v_i(mem_rev_v_li) + ,.mem_rev_ready_and_o(mem_rev_ready_and_lo) + ); + + if (cacc_type_p == e_cacc_vdp) + begin : cacc_vdp + bp_cacc_vdp + #(.bp_params_p(bp_params_p)) + accelerator_link + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.lce_id_i(lce_id_li) + + ,.mem_fwd_header_i(mem_fwd_header_lo) + ,.mem_fwd_data_i(mem_fwd_data_lo) + ,.mem_fwd_v_i(mem_fwd_v_lo) + ,.mem_fwd_ready_and_o(mem_fwd_ready_and_li) + + ,.mem_rev_header_o(mem_rev_header_li) + ,.mem_rev_data_o(mem_rev_data_li) + ,.mem_rev_v_o(mem_rev_v_li) + ,.mem_rev_ready_and_i(mem_rev_ready_and_lo) + + ,.lce_req_header_o(lce_req_header_lo) + ,.lce_req_data_o(lce_req_data_lo) + ,.lce_req_v_o(lce_req_v_lo) + ,.lce_req_ready_and_i(lce_req_ready_and_li) + + ,.lce_cmd_header_i(lce_cmd_header_li) + ,.lce_cmd_data_i(lce_cmd_data_li) + ,.lce_cmd_v_i(lce_cmd_v_li) + ,.lce_cmd_ready_and_o(lce_cmd_ready_and_lo) + + ,.lce_fill_header_i(lce_fill_header_li) + ,.lce_fill_data_i(lce_fill_data_li) + ,.lce_fill_v_i(lce_fill_v_li) + ,.lce_fill_ready_and_o(lce_fill_ready_and_lo) + + ,.lce_fill_header_o(lce_fill_header_lo) + ,.lce_fill_data_o(lce_fill_data_lo) + ,.lce_fill_v_o(lce_fill_v_lo) + ,.lce_fill_ready_and_i(lce_fill_ready_and_li) + + ,.lce_resp_header_o(lce_resp_header_lo) + ,.lce_resp_data_o(lce_resp_data_lo) + ,.lce_resp_v_o(lce_resp_v_lo) + ,.lce_resp_ready_and_i(lce_resp_ready_and_li) + ); + end + else + begin : none + assign mem_fwd_ready_and_li = '0; + + assign mem_rev_header_li = '0; + assign mem_rev_data_li = '0; + assign mem_rev_v_li = '0; + + assign lce_req_header_lo = '0; + assign lce_req_data_lo = '0; + assign lce_req_v_lo = '0; + + assign lce_cmd_ready_and_lo = '0; + + assign lce_fill_header_lo = '0; + assign lce_fill_data_lo = '0; + assign lce_fill_v_lo = '0; + + assign lce_fill_ready_and_lo = '0; + + assign lce_resp_header_lo = '0; + assign lce_resp_data_lo = '0; + assign lce_resp_v_lo = '0; + end + + // Burst to WH (lce_req_header_lo) + bp_me_cce_id_to_cord + #(.bp_params_p(bp_params_p)) + req_router_cord + (.cce_id_i(lce_req_header_lo.payload.dst_id) + ,.cce_cord_o(lce_req_dst_cord_lo) + ,.cce_cid_o(lce_req_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_req_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_req_header_lo) + ,.pr_data_i(lce_req_data_lo) + ,.pr_v_i(lce_req_v_lo) + ,.pr_ready_and_o(lce_req_ready_and_li) + ,.dst_cord_i(lce_req_dst_cord_lo) + ,.dst_cid_i(lce_req_dst_cid_lo) + + ,.link_data_o(lce_req_link_cast_o.data) + ,.link_v_o(lce_req_link_cast_o.v) + ,.link_ready_and_i(lce_req_link_cast_i.ready_and_rev) + ); + + // WH to Burst (lce_cmd_header_li) + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_cmd_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_cmd_link_cast_i.data) + ,.link_v_i(lce_cmd_link_cast_i.v) + ,.link_ready_and_o(lce_cmd_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_cmd_header_li) + ,.pr_data_o(lce_cmd_data_li) + ,.pr_v_o(lce_cmd_v_li) + ,.pr_ready_and_i(lce_cmd_ready_and_lo) + ); + + // WH to Burst (lce_fill_header_li) + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_fill_header_width_lp) + ,.pr_payload_width_p(lce_fill_payload_width_lp) + ,.pr_stream_mask_p(lce_fill_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_fill_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_fill_link_cast_i.data) + ,.link_v_i(lce_fill_link_cast_i.v) + ,.link_ready_and_o(lce_fill_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_fill_header_li) + ,.pr_data_o(lce_fill_data_li) + ,.pr_v_o(lce_fill_v_li) + ,.pr_ready_and_i(lce_fill_ready_and_lo) + ); + + // Burst to WH (lce_fill_header_lo) + bp_me_lce_id_to_cord + #(.bp_params_p(bp_params_p)) + fill_router_cord + (.lce_id_i(lce_fill_header_lo.payload.dst_id) + ,.lce_cord_o(lce_fill_dst_cord_lo) + ,.lce_cid_o(lce_fill_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_fill_header_width_lp) + ,.pr_payload_width_p(lce_fill_payload_width_lp) + ,.pr_stream_mask_p(lce_fill_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_fill_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_fill_header_lo) + ,.pr_data_i(lce_fill_data_lo) + ,.pr_v_i(lce_fill_v_lo) + ,.pr_ready_and_o(lce_fill_ready_and_li) + ,.dst_cord_i(lce_fill_dst_cord_lo) + ,.dst_cid_i(lce_fill_dst_cid_lo) + + ,.link_data_o(lce_fill_link_cast_o.data) + ,.link_v_o(lce_fill_link_cast_o.v) + ,.link_ready_and_i(lce_fill_link_cast_i.ready_and_rev) + ); + + // Burst to WH (lce_resp_header_lo) + bp_me_cce_id_to_cord + #(.bp_params_p(bp_params_p)) + resp_router_cord + (.cce_id_i(lce_resp_header_lo.payload.dst_id) + ,.cce_cord_o(lce_resp_dst_cord_lo) + ,.cce_cid_o(lce_resp_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_resp_header_width_lp) + ,.pr_payload_width_p(lce_resp_payload_width_lp) + ,.pr_stream_mask_p(lce_resp_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_resp_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_resp_header_lo) + ,.pr_data_i(lce_resp_data_lo) + ,.pr_v_i(lce_resp_v_lo) + ,.pr_ready_and_o(lce_resp_ready_and_li) + ,.dst_cord_i(lce_resp_dst_cord_lo) + ,.dst_cid_i(lce_resp_dst_cid_lo) + + ,.link_data_o(lce_resp_link_cast_o.data) + ,.link_v_o(lce_resp_link_cast_o.v) + ,.link_ready_and_i(lce_resp_link_cast_i.ready_and_rev) + ); + assign lce_resp_link_cast_o.ready_and_rev = 1'b0; + + // WH to Burst (lce_req_header_li) + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_req_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_req_link_cast_i.data) + ,.link_v_i(lce_req_link_cast_i.v) + ,.link_ready_and_o(lce_req_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_req_header_li) + ,.pr_data_o(lce_req_data_li) + ,.pr_v_o(lce_req_v_li) + ,.pr_ready_and_i(lce_req_ready_and_lo) + ); + + // Burst to WH (lce_cmd_header_lo) + bp_me_lce_id_to_cord + #(.bp_params_p(bp_params_p)) + cmd_router_cord + (.lce_id_i(lce_cmd_header_lo.payload.dst_id) + ,.lce_cord_o(lce_cmd_dst_cord_lo) + ,.lce_cid_o(lce_cmd_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_cmd_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_cmd_header_lo) + ,.pr_data_i(lce_cmd_data_lo) + ,.pr_v_i(lce_cmd_v_lo) + ,.pr_ready_and_o(lce_cmd_ready_and_li) + ,.dst_cord_i(lce_cmd_dst_cord_lo) + ,.dst_cid_i(lce_cmd_dst_cid_lo) + + ,.link_data_o(lce_cmd_link_cast_o.data) + ,.link_v_o(lce_cmd_link_cast_o.v) + ,.link_ready_and_i(lce_cmd_link_cast_i.ready_and_rev) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_cacc_tile_node.sv b/designs/black-parrot/src/bp/bp_cacc_tile_node.sv new file mode 100644 index 0000000..3ba43a4 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cacc_tile_node.sv @@ -0,0 +1,97 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_cacc_tile_node + import bp_common_pkg::*; + import bp_be_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + , parameter accelerator_type_p = 1 + ) + (input core_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input [coh_noc_cord_width_p-1:0] my_cord_i + // Connected to other tiles on east and west + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_fill_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_fill_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_o + ); + + // Declare the routing links + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + + // Tile-side coherence connections + bp_coh_ready_and_link_s accel_lce_req_link_li, accel_lce_req_link_lo; + bp_coh_ready_and_link_s accel_lce_cmd_link_li, accel_lce_cmd_link_lo; + bp_coh_ready_and_link_s accel_lce_fill_link_li, accel_lce_fill_link_lo; + bp_coh_ready_and_link_s accel_lce_resp_link_li, accel_lce_resp_link_lo; + + + bp_cacc_tile + #(.bp_params_p(bp_params_p)) + accel_tile + (.clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.my_cord_i(my_cord_i) + + ,.lce_req_link_i(accel_lce_req_link_li) + ,.lce_req_link_o(accel_lce_req_link_lo) + + ,.lce_cmd_link_i(accel_lce_cmd_link_li) + ,.lce_cmd_link_o(accel_lce_cmd_link_lo) + + ,.lce_fill_link_i(accel_lce_fill_link_li) + ,.lce_fill_link_o(accel_lce_fill_link_lo) + + ,.lce_resp_link_i(accel_lce_resp_link_li) + ,.lce_resp_link_o(accel_lce_resp_link_lo) + + ); + + + bp_nd_socket + #(.flit_width_p(coh_noc_flit_width_p) + ,.dims_p(coh_noc_dims_p) + ,.cord_dims_p(coh_noc_dims_p) + ,.cord_markers_pos_p(coh_noc_cord_markers_pos_p) + ,.len_width_p(coh_noc_len_width_p) + ,.routing_matrix_p(StrictYX | YX_Allow_W) + ,.async_clk_p(async_coh_clk_p) + ,.els_p(4) + ) + cac_coh_socket + (.tile_clk_i(core_clk_i) + ,.tile_reset_i(core_reset_i) + ,.network_clk_i(coh_clk_i) + ,.network_reset_i(coh_reset_i) + ,.my_cord_i(my_cord_i) + ,.network_link_i({coh_lce_req_link_i, coh_lce_cmd_link_i, coh_lce_fill_link_i, coh_lce_resp_link_i}) + ,.network_link_o({coh_lce_req_link_o, coh_lce_cmd_link_o, coh_lce_fill_link_o, coh_lce_resp_link_o}) + ,.tile_link_i({accel_lce_req_link_lo, accel_lce_cmd_link_lo, accel_lce_fill_link_lo, accel_lce_resp_link_lo}) + ,.tile_link_o({accel_lce_req_link_li, accel_lce_cmd_link_li, accel_lce_fill_link_li, accel_lce_resp_link_li}) + ); + + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_cacc_vdp.sv b/designs/black-parrot/src/bp/bp_cacc_vdp.sv new file mode 100644 index 0000000..351b41e --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cacc_vdp.sv @@ -0,0 +1,434 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" +`include "bp_me_defines.svh" + +module bp_cacc_vdp + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, acache_tag_width_p, acache_sets_p, acache_assoc_p, dword_width_gp, acache_block_width_p, acache_fill_width_p, acache_req_id_width_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [lce_id_width_p-1:0] lce_id_i + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , output logic [lce_req_header_width_lp-1:0] lce_req_header_o + , output logic [acache_fill_width_p-1:0] lce_req_data_o + , output logic lce_req_v_o + , input lce_req_ready_and_i + + , input [lce_cmd_header_width_lp-1:0] lce_cmd_header_i + , input [acache_fill_width_p-1:0] lce_cmd_data_i + , input lce_cmd_v_i + , output logic lce_cmd_ready_and_o + + , input [lce_fill_header_width_lp-1:0] lce_fill_header_i + , input [acache_fill_width_p-1:0] lce_fill_data_i + , input lce_fill_v_i + , output logic lce_fill_ready_and_o + + , output logic [lce_fill_header_width_lp-1:0] lce_fill_header_o + , output logic [acache_fill_width_p-1:0] lce_fill_data_o + , output logic lce_fill_v_o + , input lce_fill_ready_and_i + + , output logic [lce_resp_header_width_lp-1:0] lce_resp_header_o + , output logic [acache_fill_width_p-1:0] lce_resp_data_o + , output logic lce_resp_v_o + , input lce_resp_ready_and_i + + // BedRock Stream + // may only support single beat messages + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [acache_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [acache_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + ); + + // CCE-IO interface is used for uncached requests-read/write memory mapped CSR + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + + localparam reg_els_lp = 1; + + logic r_v_li, w_v_li; + logic [paddr_width_p-1:0] addr_lo; + logic [reg_els_lp-1:0][dword_width_gp-1:0] data_li; + logic [dword_width_gp-1:0] data_lo; + bp_me_bedrock_register + #(.bp_params_p(bp_params_p) + ,.els_p(reg_els_lp) + ,.reg_addr_width_p(paddr_width_p) + ,.base_addr_p({64'b????????????????}) + ) + register + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.r_v_o(r_v_li) + ,.w_v_o(w_v_li) + ,.addr_o(addr_lo) + ,.size_o() + ,.data_o(data_lo) + ,.data_i(data_li) + + ,.* + ); + + bp_local_addr_s local_addr_lo; + bp_global_addr_s global_addr_lo; + assign global_addr_lo = addr_lo; + assign local_addr_lo = addr_lo; + + bp_be_dcache_pkt_s acache_pkt_li; + logic acache_busy_lo, acache_v_li; + logic [dword_width_gp-1:0] acache_data_lo; + logic acache_v_lo; + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + bp_cfg_bus_s cfg_bus_cast_i; + assign cfg_bus_cast_i.dcache_id = lce_id_i; + assign cfg_bus_cast_i.dcache_mode = e_lce_mode_normal; + + `declare_bp_be_dcache_engine_if(paddr_width_p, acache_tag_width_p, acache_sets_p, acache_assoc_p, dword_width_gp, acache_block_width_p, acache_fill_width_p, acache_req_id_width_p); + bp_be_dcache_req_s acache_req_lo; + logic acache_req_v_lo, acache_req_yumi_li, acache_req_lock_li; + bp_be_dcache_req_metadata_s acache_req_metadata_lo; + logic acache_req_metadata_v_lo; + logic [acache_req_id_width_p-1:0] acache_req_id_lo; + logic acache_req_last_lo, acache_req_critical_lo; + logic acache_req_credits_full_lo, acache_req_credits_empty_lo; + bp_be_dcache_data_mem_pkt_s acache_data_mem_pkt_li; + logic acache_data_mem_pkt_v_li, acache_data_mem_pkt_yumi_lo; + logic [acache_block_width_p-1:0] acache_data_mem_lo; + bp_be_dcache_tag_mem_pkt_s acache_tag_mem_pkt_li; + logic acache_tag_mem_pkt_v_li, acache_tag_mem_pkt_yumi_lo; + bp_be_dcache_tag_info_s acache_tag_mem_lo; + bp_be_dcache_stat_mem_pkt_s acache_stat_mem_pkt_li; + logic acache_stat_mem_pkt_v_li, acache_stat_mem_pkt_yumi_lo; + bp_be_dcache_stat_info_s acache_stat_mem_lo; + + logic [ptag_width_p-1:0] acache_ptag_li; + logic [dword_width_gp-1:0] acache_st_data_r; + + bp_be_dcache + #(.bp_params_p(bp_params_p) + ,.sets_p(acache_sets_p) + ,.assoc_p(acache_assoc_p) + ,.block_width_p(acache_block_width_p) + ,.fill_width_p(acache_fill_width_p) + ) + acache + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_cast_i) + + ,.dcache_pkt_i(acache_pkt_li) + ,.v_i(acache_v_li) + ,.busy_o(acache_busy_lo) + ,.flush_i(1'b0) + ,.ordered_o() + + ,.ptag_v_i(1'b1) + ,.ptag_i(acache_ptag_li) + ,.ptag_uncached_i(1'b0) + ,.ptag_dram_i(1'b1) + ,.st_data_i(acache_st_data_r) + + ,.v_o(acache_v_lo) + ,.data_o(acache_data_lo) + ,.rd_addr_o() + ,.int_o() + ,.float_o() + ,.ptw_o() + ,.ret_o() + ,.late_o() + ,.tag_o() + ,.unsigned_o() + + // D$-LCE Interface + ,.cache_req_o(acache_req_lo) + ,.cache_req_v_o(acache_req_v_lo) + ,.cache_req_yumi_i(acache_req_yumi_li) + ,.cache_req_lock_i(acache_req_lock_li) + ,.cache_req_metadata_o(acache_req_metadata_lo) + ,.cache_req_metadata_v_o(acache_req_metadata_v_lo) + ,.cache_req_credits_full_i(acache_req_credits_full_lo) + ,.cache_req_credits_empty_i(acache_req_credits_empty_lo) + ,.cache_req_id_i(acache_req_id_lo) + ,.cache_req_critical_i(acache_req_critical_lo) + ,.cache_req_last_i(acache_req_last_lo) + + ,.data_mem_pkt_v_i(acache_data_mem_pkt_v_li) + ,.data_mem_pkt_i(acache_data_mem_pkt_li) + ,.data_mem_pkt_yumi_o(acache_data_mem_pkt_yumi_lo) + ,.data_mem_o(acache_data_mem_lo) + + ,.tag_mem_pkt_v_i(acache_tag_mem_pkt_v_li) + ,.tag_mem_pkt_i(acache_tag_mem_pkt_li) + ,.tag_mem_pkt_yumi_o(acache_tag_mem_pkt_yumi_lo) + ,.tag_mem_o(acache_tag_mem_lo) + + ,.stat_mem_pkt_v_i(acache_stat_mem_pkt_v_li) + ,.stat_mem_pkt_i(acache_stat_mem_pkt_li) + ,.stat_mem_pkt_yumi_o(acache_stat_mem_pkt_yumi_lo) + ,.stat_mem_o(acache_stat_mem_lo) + ); + + + bp_lce + #(.bp_params_p(bp_params_p) + ,.assoc_p(acache_assoc_p) + ,.sets_p(acache_sets_p) + ,.block_width_p(acache_block_width_p) + ,.fill_width_p(acache_fill_width_p) + ,.data_width_p(acache_data_width_p) + ,.tag_width_p(acache_tag_width_p) + ,.id_width_p(acache_req_id_width_p) + ,.timeout_max_limit_p(4) + ,.credits_p(coh_noc_max_credits_p) + ) + lce + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.lce_id_i(cfg_bus_cast_i.dcache_id) + ,.did_i(cfg_bus_cast_i.did) + ,.lce_mode_i(cfg_bus_cast_i.dcache_mode) + + ,.cache_req_i(acache_req_lo) + ,.cache_req_v_i(acache_req_v_lo) + ,.cache_req_yumi_o(acache_req_yumi_li) + ,.cache_req_lock_o(acache_req_lock_li) + ,.cache_req_metadata_i(acache_req_metadata_lo) + ,.cache_req_metadata_v_i(acache_req_metadata_v_lo) + ,.cache_req_id_o(acache_req_id_lo) + ,.cache_req_critical_o(acache_req_critical_lo) + ,.cache_req_last_o(acache_req_last_lo) + ,.cache_req_credits_full_o(acache_req_credits_full_lo) + ,.cache_req_credits_empty_o(acache_req_credits_empty_lo) + + ,.data_mem_pkt_o(acache_data_mem_pkt_li) + ,.data_mem_pkt_v_o(acache_data_mem_pkt_v_li) + ,.data_mem_pkt_yumi_i(acache_data_mem_pkt_yumi_lo) + ,.data_mem_i(acache_data_mem_lo) + + ,.tag_mem_pkt_o(acache_tag_mem_pkt_li) + ,.tag_mem_pkt_v_o(acache_tag_mem_pkt_v_li) + ,.tag_mem_pkt_yumi_i(acache_tag_mem_pkt_yumi_lo) + ,.tag_mem_i(acache_tag_mem_lo) + + ,.stat_mem_pkt_v_o(acache_stat_mem_pkt_v_li) + ,.stat_mem_pkt_o(acache_stat_mem_pkt_li) + ,.stat_mem_pkt_yumi_i(acache_stat_mem_pkt_yumi_lo) + ,.stat_mem_i(acache_stat_mem_lo) + + // LCE-CCE Interface + ,.* + ); + + logic [63:0] start_cmd, input_a_ptr, input_b_ptr, input_len, + res_ptr, res_len, operation, dot_product_res; + logic [63:0] vector_a [0:7]; + logic [63:0] vector_b [0:7]; + logic [63:0] vdp_result; + logic [2:0] len_a_cnt, len_b_cnt; + logic load, second_operand; + + enum logic [3:0] + { + e_reset + ,e_wait_start + ,e_wait_fetch + ,e_fetch_vec1 + ,e_wait_dcache_c1 + ,e_wait_dcache_c2 + ,e_check_vec1_len + ,e_fetch_vec2 + ,e_check_vec2_len + ,e_wb_result + ,e_done + } state_n, state_r; + + wire done = (state_r inside {e_done}); + wire res_status = (state_r inside {e_wait_start}); + + always_ff @(posedge clk_i) + begin + if (reset_i || done) + begin + len_a_cnt <= '0; + len_b_cnt <= '0; + end + else if (acache_v_lo & load & ~second_operand) + begin + vector_a[len_a_cnt] <= acache_data_lo; + len_a_cnt <= len_a_cnt + 1'b1; + end + else if (acache_v_lo & load & second_operand) + begin + vector_b[len_b_cnt] <= acache_data_lo; + len_b_cnt <= len_b_cnt + 1'b1; + end + end + + wire csr_w_v_li = w_v_li && (global_addr_lo.hio == 0); + wire csr_r_v_li = r_v_li && (global_addr_lo.hio == 0); + + always_ff @(posedge clk_i) + begin + if (reset_i) + begin + input_a_ptr <= '0; + input_b_ptr <= '0; + input_len <= '0; + start_cmd <= '0; + res_ptr <= '0; + res_len <= '0; + operation <= '0; + end + else if (csr_w_v_li) + unique casez (local_addr_lo.addr) + inputa_ptr_csr_idx_gp : input_a_ptr <= data_lo; + inputb_ptr_csr_idx_gp : input_b_ptr <= data_lo; + input_len_csr_idx_gp : input_len <= data_lo; + start_cmd_csr_idx_gp : start_cmd <= data_lo; + res_ptr_csr_idx_gp : res_ptr <= data_lo; + res_len_csr_idx_gp : res_len <= data_lo; + operation_csr_idx_gp : operation <= data_lo; + default : begin end + endcase + + if (state_r == e_done) + start_cmd <= '0; + end + + logic input_a_ptr_r_v_r, input_b_ptr_r_v_r, input_len_r_v_r, operation_r_v_r; + logic start_cmd_r_v_r, res_status_r_v_r, res_ptr_r_v_r, res_len_r_v_r; + always_ff @(posedge clk_i) + begin + input_a_ptr_r_v_r <= csr_r_v_li && (local_addr_lo.addr == inputa_ptr_csr_idx_gp); + input_b_ptr_r_v_r <= csr_r_v_li && (local_addr_lo.addr == inputb_ptr_csr_idx_gp); + input_len_r_v_r <= csr_r_v_li && (local_addr_lo.addr == input_len_csr_idx_gp); + start_cmd_r_v_r <= csr_r_v_li && (local_addr_lo.addr == start_cmd_csr_idx_gp); + res_status_r_v_r <= csr_r_v_li && (local_addr_lo.addr == res_status_csr_idx_gp); + res_ptr_r_v_r <= csr_r_v_li && (local_addr_lo.addr == res_ptr_csr_idx_gp); + res_len_r_v_r <= csr_r_v_li && (local_addr_lo.addr == res_len_csr_idx_gp); + operation_r_v_r <= csr_r_v_li && (local_addr_lo.addr == operation_csr_idx_gp); + end + + logic [dword_width_gp-1:0] csr_data_lo; + always_comb + unique casez (local_addr_lo.addr) + inputa_ptr_csr_idx_gp : csr_data_lo = input_a_ptr; + inputb_ptr_csr_idx_gp : csr_data_lo = input_b_ptr; + input_len_csr_idx_gp : csr_data_lo = input_len; + start_cmd_csr_idx_gp : csr_data_lo = start_cmd; + res_status_csr_idx_gp : csr_data_lo = res_status; + res_ptr_csr_idx_gp : csr_data_lo = res_ptr; + res_len_csr_idx_gp : csr_data_lo = res_len; + //operation_csr_idx_gp : csr_data_lo = operation; + default: csr_data_lo = operation; + endcase + + assign data_li = csr_data_lo; + + wire [vaddr_width_p-1:0] vaddr = load ? second_operand + ? (input_b_ptr+len_b_cnt*8) + : (input_a_ptr+len_a_cnt*8) + : res_ptr; + assign acache_pkt_li = '{opcode: load ? e_dcache_op_ld : e_dcache_op_sd + ,offset: vaddr[0+:page_offset_width_gp] + ,default: '0 + }; + + always_ff @(posedge clk_i) begin + acache_ptag_li <= vaddr[page_offset_width_gp+:ptag_width_p]; + acache_st_data_r <= dot_product_res; + end + + always_comb + begin + load = 0; + second_operand = 0; + acache_v_li = 0; + dot_product_res = '0; + + state_n = state_r; + case (state_r) + e_reset: begin + state_n = reset_i ? e_reset : e_wait_start; + end + e_wait_start: begin + load = 1; + state_n = start_cmd ? e_wait_fetch : e_wait_start; + end + e_wait_fetch: begin + state_n = !acache_busy_lo ? e_fetch_vec1 : e_wait_fetch; + end + e_fetch_vec1: begin + acache_v_li = '1; + state_n = e_wait_dcache_c1; + end + e_wait_dcache_c1: begin + state_n = acache_v_lo ? (load ? (second_operand ? e_check_vec2_len : e_check_vec1_len) : e_done) : e_wait_dcache_c2; + end + e_wait_dcache_c2: begin + //if load: load both input vectors + //if store: go to e_done after store + state_n = ~(lce_cmd_v_i | lce_fill_v_i) ? e_wait_dcache_c2 : e_wait_fetch; + end + e_check_vec1_len: begin + state_n = (len_a_cnt == input_len) ? e_fetch_vec2 : e_wait_fetch; + end + e_fetch_vec2: begin + second_operand = 1; + state_n = e_wait_fetch; + end + e_check_vec2_len: begin + second_operand = 1; + dot_product_res = vdp_result; + state_n = (len_b_cnt == input_len) ? e_wb_result : e_wait_fetch; + end + e_wb_result: begin + state_n = e_wait_fetch; + end + e_done: begin + state_n = acache_req_credits_empty_lo ? e_reset : e_done; + end + endcase + end + + // dot_product unit + logic [63:0] product_res [0:7]; + logic [63:0] sum_l1 [0:3]; + logic [63:0] sum_l2 [0:1]; + for (genvar i = 0; i < 8; i++) assign product_res[i] = vector_a[i] * vector_b[i]; + for (genvar i = 0; i < 4; i++) assign sum_l1[i] = product_res[2*i] + product_res[2*i+1]; + for (genvar i = 0; i < 2; i++) assign sum_l2[i] = sum_l1[2*i] + sum_l1[2*i+1]; + assign vdp_result = (sum_l2[0] + sum_l2[1]); + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if(reset_i) + state_r <= e_reset; + else + state_r <= state_n; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_cce.sv b/designs/black-parrot/src/bp/bp_cce.sv new file mode 100644 index 0000000..7def1a0 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce.sv @@ -0,0 +1,870 @@ +/** + * + * Name: + * bp_cce.sv + * + * Description: + * This is the top level module for the microcoded CCE. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Derived parameters + , localparam block_size_in_bytes_lp = (bedrock_block_width_p/8) + , localparam lg_block_size_in_bytes_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_lp) + + // number of way groups managed by this CCE + , localparam num_way_groups_lp = `BSG_CDIV(cce_way_groups_p, num_cce_p) + , localparam lg_num_way_groups_lp = `BSG_SAFE_CLOG2(num_way_groups_lp) + , localparam lg_cce_way_groups_lp = `BSG_SAFE_CLOG2(cce_way_groups_p) + + // Interface Widths + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + ) + (input clk_i + , input reset_i + + // Configuration Interface + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // ucode programming interface, synchronous read, direct connection to RAM + , input ucode_v_i + , input ucode_w_i + , input [cce_pc_width_p-1:0] ucode_addr_i + , input [cce_instr_width_gp-1:0] ucode_data_i + , output logic [cce_instr_width_gp-1:0] ucode_data_o + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input [bedrock_fill_width_p-1:0] lce_req_data_i + , input lce_req_v_i + , output logic lce_req_ready_and_o + + , input [lce_resp_header_width_lp-1:0] lce_resp_header_i + , input [bedrock_fill_width_p-1:0] lce_resp_data_i + , input lce_resp_v_i + , output logic lce_resp_ready_and_o + + , output logic [lce_cmd_header_width_lp-1:0] lce_cmd_header_o + , output logic [bedrock_fill_width_p-1:0] lce_cmd_data_o + , output logic lce_cmd_v_o + , input lce_cmd_ready_and_i + + // CCE-MEM Interface + // BedRock Stream protocol: ready&valid + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + ); + + // parameter checks + if (bedrock_block_width_p < `bp_cce_inst_gpr_width) + $error("CCE block width must be greater than CCE GPR width"); + + + // LCE-CCE and Mem-CCE Interface + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + // MSHR + `declare_bp_cce_mshr_s(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + // Config Interface + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + + // LCE-CCE Interface structs + `bp_cast_i(bp_bedrock_lce_req_header_s, lce_req_header); + `bp_cast_o(bp_bedrock_lce_cmd_header_s, lce_cmd_header); + `bp_cast_i(bp_bedrock_lce_resp_header_s, lce_resp_header); + + // Config bus + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + + // Inter-module signals + + // From Fetch to Execute/Pre-Decode + logic [cce_pc_width_p-1:0] fetch_pc_lo; + bp_cce_inst_s fetch_inst_lo; + logic fetch_inst_v_lo; + + // From Predecode to Fetch + logic [cce_pc_width_p-1:0] predicted_fetch_pc_lo; + + // From Decoder to rest of Execute + bp_cce_inst_decoded_s decoded_inst_lo; + logic [cce_pc_width_p-1:0] ex_pc_lo; + + // From Execute to Fetch/Decode + logic [cce_pc_width_p-1:0] branch_resolution_pc_lo; + logic stall_lo, mispredict_lo; + + // From ALU + logic [`bp_cce_inst_gpr_width-1:0] alu_res_lo; + + // From Source Selector to Execute + logic [`bp_cce_inst_gpr_width-1:0] src_a, src_b; + logic [paddr_width_p-1:0] addr_lo; + logic addr_bypass_lo; + logic [lce_id_width_p-1:0] lce_lo; + logic [lce_assoc_width_p-1:0] way_lo, lru_way_lo; + bp_coh_states_e state_lo; + + // From Arbitration to Directory + logic [paddr_width_p-1:0] dir_addr_li; + logic dir_addr_bypass_li; + logic [lce_id_width_p-1:0] dir_lce_li; + logic [lce_assoc_width_p-1:0] dir_way_li; + bp_coh_states_e dir_coh_state_li; + bp_cce_inst_minor_dir_op_e dir_cmd_li; + logic dir_w_v_li; + // From Arbitration to Pending Bits + logic pending_li; + logic pending_w_v_li; + logic [paddr_width_p-1:0] pending_w_addr_li; + logic pending_w_addr_bypass_li; + // From Arbitration to Spec Bits + logic spec_r_v_li; + logic [paddr_width_p-1:0] spec_r_addr_li; + logic spec_r_addr_bypass_li; + + // From Directory + logic dir_busy_lo; + logic sharers_v_lo; + logic [num_lce_p-1:0] sharers_hits_lo; + logic [num_lce_p-1:0][lce_assoc_width_p-1:0] sharers_ways_lo; + bp_coh_states_e [num_lce_p-1:0] sharers_coh_states_lo; + logic dir_addr_v_lo, dir_lru_v_lo; + bp_coh_states_e dir_lru_coh_state_lo; + logic [paddr_width_p-1:0] dir_addr_lo, dir_lru_addr_lo; + bp_cce_inst_opd_gpr_e dir_addr_dst_gpr_lo; + + // From Pending Bits + logic pending_lo; + + // From Spec Bits + bp_cce_spec_s spec_bits_lo; + + // From GAD + logic [lce_assoc_width_p-1:0] gad_req_addr_way_lo; + logic [lce_id_width_p-1:0] gad_owner_lce_lo; + logic [lce_assoc_width_p-1:0] gad_owner_way_lo; + bp_coh_states_e gad_owner_coh_state_lo; + logic gad_replacement_flag_lo; + logic gad_upgrade_flag_lo; + logic gad_cached_shared_flag_lo; + logic gad_cached_exclusive_flag_lo; + logic gad_cached_modified_flag_lo; + logic gad_cached_owned_flag_lo; + logic gad_cached_forward_flag_lo; + + // From Register File + bp_cce_mshr_s mshr_lo; + logic [`bp_cce_inst_num_gpr-1:0][`bp_cce_inst_gpr_width-1:0] gpr_lo; + bp_coh_states_e coh_state_default_lo; + logic auto_fwd_msg_lo; + + // From Message Unit + logic [paddr_width_p-1:0] msg_dir_addr_lo; + logic msg_dir_addr_bypass_lo; + logic [lce_id_width_p-1:0] msg_dir_lce_lo; + logic [lce_assoc_width_p-1:0] msg_dir_way_lo; + bp_coh_states_e msg_dir_coh_state_lo; + bp_cce_inst_minor_dir_op_e msg_dir_w_cmd_lo; + logic msg_dir_w_v_lo; + + logic msg_pending_w_v_lo; + logic [paddr_width_p-1:0] msg_pending_w_addr_lo; + logic msg_pending_w_addr_bypass_lo; + logic msg_pending_lo; + + logic msg_spec_r_v_lo; + logic [paddr_width_p-1:0] msg_spec_r_addr_lo; + logic msg_spec_r_addr_bypass_lo; + + // From Message Unit to Stall + logic msg_lce_cmd_busy_lo; + logic msg_lce_resp_busy_lo; + logic msg_mem_rev_busy_lo; + logic msg_busy_lo; + logic msg_mem_credits_empty_lo; + logic msg_mem_fwd_stall_lo; + + /* + * Fetch Stage + */ + + // Inst Fetch and microcode RAM + bp_cce_inst_ram + #(.bp_params_p(bp_params_p) + ) + inst_ram + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_i) + + ,.ucode_v_i(ucode_v_i) + ,.ucode_w_i(ucode_w_i) + ,.ucode_addr_i(ucode_addr_i) + ,.ucode_data_i(ucode_data_i) + ,.ucode_data_o(ucode_data_o) + + ,.predicted_fetch_pc_i(predicted_fetch_pc_lo) + ,.branch_resolution_pc_i(branch_resolution_pc_lo) + ,.stall_i(stall_lo) + ,.mispredict_i(mispredict_lo) + ,.fetch_pc_o(fetch_pc_lo) + ,.inst_o(fetch_inst_lo) + ,.inst_v_o(fetch_inst_v_lo) + ); + + // Inst Pre-decode + bp_cce_inst_predecode + #(.width_p(cce_pc_width_p) + ) + inst_predecode + (.inst_i(fetch_inst_lo) + ,.pc_i(fetch_pc_lo) + ,.predicted_next_pc_o(predicted_fetch_pc_lo) + ); + + /* + * Stream pumps + * + * The CCE logic interacts with the FSM side of the stream pumps, including all signals used + * for arbitration, data routing, stall detection, etc. + * + * The FSM side of the stream pumps is considered part of the CCE's execute stage. + */ + + bp_bedrock_lce_req_header_s fsm_req_header_li; + logic [bedrock_fill_width_p-1:0] fsm_req_data_li; + logic fsm_req_v_li, fsm_req_yumi_lo; + logic [paddr_width_p-1:0] fsm_req_addr_li; + logic fsm_req_new_li, fsm_req_critical_li, fsm_req_last_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_req_payload_width_lp) + ,.msg_stream_mask_p(lce_req_stream_mask_gp) + ,.fsm_stream_mask_p(lce_req_stream_mask_gp) + ) + lce_req_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(lce_req_header_cast_i) + ,.msg_data_i(lce_req_data_i) + ,.msg_v_i(lce_req_v_i) + ,.msg_ready_and_o(lce_req_ready_and_o) + + ,.fsm_header_o(fsm_req_header_li) + ,.fsm_data_o(fsm_req_data_li) + ,.fsm_v_o(fsm_req_v_li) + ,.fsm_yumi_i(fsm_req_yumi_lo) + ,.fsm_addr_o(fsm_req_addr_li) + ,.fsm_new_o(fsm_req_new_li) + ,.fsm_critical_o(fsm_req_critical_li) + ,.fsm_last_o(fsm_req_last_li) + ); + + localparam block_size_in_fill_lp = bedrock_block_width_p / bedrock_fill_width_p; + localparam fill_cnt_width_lp = `BSG_SAFE_CLOG2(block_size_in_fill_lp); + bp_bedrock_lce_cmd_header_s fsm_cmd_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_cmd_data_lo; + logic fsm_cmd_v_lo, fsm_cmd_ready_then_li; + logic [paddr_width_p-1:0] fsm_cmd_addr_lo; + logic fsm_cmd_new_lo, fsm_cmd_critical_lo, fsm_cmd_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_cmd_payload_width_lp) + ,.msg_stream_mask_p(lce_cmd_stream_mask_gp) + ,.fsm_stream_mask_p(lce_cmd_stream_mask_gp) + ) + lce_cmd_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(lce_cmd_header_cast_o) + ,.msg_data_o(lce_cmd_data_o) + ,.msg_v_o(lce_cmd_v_o) + ,.msg_ready_and_i(lce_cmd_ready_and_i) + + ,.fsm_header_i(fsm_cmd_header_lo) + ,.fsm_data_i(fsm_cmd_data_lo) + ,.fsm_v_i(fsm_cmd_v_lo) + ,.fsm_ready_then_o(fsm_cmd_ready_then_li) + ,.fsm_addr_o(fsm_cmd_addr_lo) + ,.fsm_new_o(fsm_cmd_new_lo) + ,.fsm_critical_o(fsm_cmd_critical_lo) + ,.fsm_last_o(fsm_cmd_last_lo) + ); + + bp_bedrock_lce_resp_header_s fsm_resp_header_li; + logic [bedrock_fill_width_p-1:0] fsm_resp_data_li; + logic fsm_resp_v_li, fsm_resp_yumi_lo; + logic [paddr_width_p-1:0] fsm_resp_addr_li; + logic fsm_resp_new_li, fsm_resp_critical_li, fsm_resp_last_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_resp_payload_width_lp) + ,.msg_stream_mask_p(lce_resp_stream_mask_gp) + ,.fsm_stream_mask_p(lce_resp_stream_mask_gp) + ) + lce_resp_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(lce_resp_header_cast_i) + ,.msg_data_i(lce_resp_data_i) + ,.msg_v_i(lce_resp_v_i) + ,.msg_ready_and_o(lce_resp_ready_and_o) + + ,.fsm_header_o(fsm_resp_header_li) + ,.fsm_addr_o(fsm_resp_addr_li) + ,.fsm_data_o(fsm_resp_data_li) + ,.fsm_v_o(fsm_resp_v_li) + ,.fsm_yumi_i(fsm_resp_yumi_lo) + ,.fsm_new_o(fsm_resp_new_li) + ,.fsm_critical_o(fsm_resp_critical_li) + ,.fsm_last_o(fsm_resp_last_li) + ); + + // Memory Rev Stream Pump + // From memory response stream pump to CCE + bp_bedrock_mem_rev_header_s fsm_rev_header_li; + logic [bedrock_fill_width_p-1:0] fsm_rev_data_li; + logic fsm_rev_v_li, fsm_rev_yumi_lo; + logic [paddr_width_p-1:0] fsm_rev_addr_li; + logic fsm_rev_new_li, fsm_rev_critical_li, fsm_rev_last_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.msg_stream_mask_p(mem_rev_stream_mask_gp) + ,.fsm_stream_mask_p(mem_rev_stream_mask_gp) + ) + mem_rev_stream_pump + (.clk_i(clk_i) + ,.reset_i(reset_i) + // from memory response input + ,.msg_header_i(mem_rev_header_i) + ,.msg_data_i(mem_rev_data_i) + ,.msg_v_i(mem_rev_v_i) + ,.msg_ready_and_o(mem_rev_ready_and_o) + // to FSM CCE + ,.fsm_header_o(fsm_rev_header_li) + ,.fsm_data_o(fsm_rev_data_li) + ,.fsm_v_o(fsm_rev_v_li) + ,.fsm_yumi_i(fsm_rev_yumi_lo) + ,.fsm_addr_o(fsm_rev_addr_li) + ,.fsm_new_o(fsm_rev_new_li) + ,.fsm_critical_o(fsm_rev_critical_li) + ,.fsm_last_o(fsm_rev_last_li) + ); + + // Memory Fwd Stream Pump + // From CCE to memory command stream pump + bp_bedrock_mem_fwd_header_s fsm_fwd_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_fwd_data_lo; + logic fsm_fwd_v_lo, fsm_fwd_ready_then_li; + logic [paddr_width_p-1:0] fsm_fwd_addr_lo; + logic fsm_fwd_new_lo, fsm_fwd_critical_lo, fsm_fwd_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.msg_stream_mask_p(mem_fwd_stream_mask_gp) + ,.fsm_stream_mask_p(mem_fwd_stream_mask_gp) + ) + mem_fwd_stream_pump + (.clk_i(clk_i) + ,.reset_i(reset_i) + // to memory command output + ,.msg_header_o(mem_fwd_header_o) + ,.msg_data_o(mem_fwd_data_o) + ,.msg_v_o(mem_fwd_v_o) + ,.msg_ready_and_i(mem_fwd_ready_and_i) + + // from FSM CCE + ,.fsm_header_i(fsm_fwd_header_lo) + ,.fsm_data_i(fsm_fwd_data_lo) + ,.fsm_v_i(fsm_fwd_v_lo) + ,.fsm_ready_then_o(fsm_fwd_ready_then_li) + ,.fsm_addr_o(fsm_fwd_addr_lo) + ,.fsm_new_o(fsm_fwd_new_lo) + ,.fsm_critical_o(fsm_fwd_critical_lo) + ,.fsm_last_o(fsm_fwd_last_lo) + ); + + /* + * Decode/Execute Stage + */ + // Instruction Decode + bp_cce_inst_decode + #(.cce_pc_width_p(cce_pc_width_p)) + inst_decode + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.inst_i(fetch_inst_lo) + ,.pc_i(fetch_pc_lo) + ,.inst_v_i(fetch_inst_v_lo) + ,.stall_i(stall_lo) + ,.mispredict_i(mispredict_lo) + ,.decoded_inst_o(decoded_inst_lo) + ,.pc_o(ex_pc_lo) + ); + + // ALU + bp_cce_alu + #(.width_p(`bp_cce_inst_gpr_width) + ) + alu + (.opd_a_i(src_a) + ,.opd_b_i(src_b) + ,.alu_op_i(decoded_inst_lo.alu_op) + ,.res_o(alu_res_lo) + ); + + // Branch Unit + bp_cce_branch + #(.width_p(`bp_cce_inst_gpr_width) + ,.cce_pc_width_p(cce_pc_width_p) + ) + branch + (.opd_a_i(src_a) + ,.opd_b_i(src_b) + ,.branch_i(decoded_inst_lo.branch) + ,.predicted_taken_i(decoded_inst_lo.predict_taken) + ,.branch_op_i(decoded_inst_lo.branch_op) + ,.execute_pc_i(ex_pc_lo) + ,.branch_target_i(decoded_inst_lo.branch_target[0+:cce_pc_width_p]) + ,.mispredict_o(mispredict_lo) + ,.pc_o(branch_resolution_pc_lo) + ); + + // Source Select + bp_cce_src_sel + #(.bp_params_p(bp_params_p)) + source_selector + (.src_a_sel_i(decoded_inst_lo.src_a_sel) + ,.src_a_i(decoded_inst_lo.src_a) + ,.src_b_sel_i(decoded_inst_lo.src_b_sel) + ,.src_b_i(decoded_inst_lo.src_b) + ,.addr_sel_i(decoded_inst_lo.addr_sel) + ,.lce_sel_i(decoded_inst_lo.lce_sel) + ,.way_sel_i(decoded_inst_lo.way_sel) + ,.lru_way_sel_i(decoded_inst_lo.lru_way_sel) + ,.coh_state_sel_i(decoded_inst_lo.coh_state_sel) + ,.cfg_bus_i(cfg_bus_i) + ,.mshr_i(mshr_lo) + ,.gpr_i(gpr_lo) + ,.imm_i(decoded_inst_lo.imm) + ,.auto_fwd_msg_i(auto_fwd_msg_lo) + ,.coh_state_default_i(coh_state_default_lo) + ,.sharers_hits_i(sharers_hits_lo) + ,.sharers_ways_i(sharers_ways_lo) + ,.sharers_coh_states_i(sharers_coh_states_lo) + ,.mem_rev_v_i(fsm_rev_v_li) + ,.lce_resp_v_i(fsm_resp_v_li) + ,.lce_req_v_i(fsm_req_v_li) + ,.lce_req_header_i(fsm_req_header_li) + ,.lce_resp_header_i(fsm_resp_header_li) + ,.mem_rev_header_i(fsm_rev_header_li) + ,.lce_req_data_i(fsm_req_data_li) + ,.lce_resp_data_i(fsm_resp_data_li) + ,.mem_rev_data_i(fsm_rev_data_li) + ,.src_a_o(src_a) + ,.src_b_o(src_b) + ,.addr_o(addr_lo) + ,.addr_bypass_o(addr_bypass_lo) + ,.lce_o(lce_lo) + ,.way_o(way_lo) + ,.lru_way_o(lru_way_lo) + ,.state_o(state_lo) + ); + + // Arbitration Unit for Directory, Spec Bits, Pending Bits + bp_cce_arbitrate + #(.bp_params_p(bp_params_p) + ) + arbitration + (.stall_i(stall_lo) + ,.dir_addr_i(addr_lo) + ,.dir_addr_bypass_i(addr_bypass_lo) + ,.dir_lce_i(lce_lo) + ,.dir_way_i(way_lo) + ,.dir_coh_state_i(state_lo) + ,.dir_cmd_i(decoded_inst_lo.minor_op_u.dir_minor_op) + ,.dir_w_v_i(decoded_inst_lo.dir_w_v) + ,.msg_dir_addr_i(msg_dir_addr_lo) + ,.msg_dir_addr_bypass_i(msg_dir_addr_bypass_lo) + ,.msg_dir_lce_i(msg_dir_lce_lo) + ,.msg_dir_way_i(msg_dir_way_lo) + ,.msg_dir_coh_state_i(msg_dir_coh_state_lo) + ,.msg_dir_w_cmd_i(msg_dir_w_cmd_lo) + ,.msg_dir_w_v_i(msg_dir_w_v_lo) + ,.dir_addr_o(dir_addr_li) + ,.dir_addr_bypass_o(dir_addr_bypass_li) + ,.dir_lce_o(dir_lce_li) + ,.dir_way_o(dir_way_li) + ,.dir_coh_state_o(dir_coh_state_li) + ,.dir_cmd_o(dir_cmd_li) + ,.dir_w_v_o(dir_w_v_li) + ,.pending_w_v_i(decoded_inst_lo.pending_w_v) + ,.pending_w_addr_i(addr_lo) + ,.pending_w_addr_bypass_i(addr_bypass_lo) + ,.pending_i(decoded_inst_lo.pending_bit) + ,.msg_pending_w_v_i(msg_pending_w_v_lo) + ,.msg_pending_w_addr_i(msg_pending_w_addr_lo) + ,.msg_pending_w_addr_bypass_i(msg_pending_w_addr_bypass_lo) + ,.msg_pending_i(msg_pending_lo) + ,.pending_w_v_o(pending_w_v_li) + ,.pending_w_addr_o(pending_w_addr_li) + ,.pending_w_addr_bypass_o(pending_w_addr_bypass_li) + ,.pending_o(pending_li) + ,.spec_r_v_i(decoded_inst_lo.spec_r_v) + ,.spec_r_addr_i(addr_lo) + ,.spec_r_addr_bypass_i(addr_bypass_lo) + ,.msg_spec_r_v_i(msg_spec_r_v_lo) + ,.msg_spec_r_addr_i(msg_spec_r_addr_lo) + ,.msg_spec_r_addr_bypass_i(msg_spec_r_addr_bypass_lo) + ,.spec_r_v_o(spec_r_v_li) + ,.spec_r_addr_o(spec_r_addr_li) + ,.spec_r_addr_bypass_o(spec_r_addr_bypass_li) + ); + + // Directory + bp_cce_dir + #(.bp_params_p(bp_params_p) + ) + directory + (.clk_i(clk_i) + ,.reset_i(reset_i) + // Inputs + ,.addr_i(dir_addr_li) + ,.addr_bypass_i(dir_addr_bypass_li) + ,.lce_i(dir_lce_li) + ,.way_i(dir_way_li) + ,.lru_way_i(lru_way_lo) // only used for reads, therefore not arbitrated with message unit + ,.coh_state_i(dir_coh_state_li) + ,.addr_dst_gpr_i(decoded_inst_lo.dst.gpr) // only used for reads, not arbitrated + ,.cmd_i(dir_cmd_li) + ,.r_v_i(decoded_inst_lo.dir_r_v) // only ucode reads directory + ,.w_v_i(dir_w_v_li) + // Outputs + ,.busy_o(dir_busy_lo) + ,.sharers_v_o(sharers_v_lo) + ,.sharers_hits_o(sharers_hits_lo) + ,.sharers_ways_o(sharers_ways_lo) + ,.sharers_coh_states_o(sharers_coh_states_lo) + ,.lru_v_o(dir_lru_v_lo) + ,.lru_coh_state_o(dir_lru_coh_state_lo) + ,.lru_addr_o(dir_lru_addr_lo) + ,.addr_v_o(dir_addr_v_lo) + ,.addr_o(dir_addr_lo) + ,.addr_dst_gpr_o(dir_addr_dst_gpr_lo) + // Debug + ,.cce_id_i(cfg_bus_cast_i.cce_id) + ); + + // Pending Bits + bp_cce_pending_bits + #(.num_way_groups_p(num_way_groups_lp) + ,.cce_way_groups_p(cce_way_groups_p) + ,.num_cce_p(num_cce_p) + ,.paddr_width_p(paddr_width_p) + ,.addr_offset_p(lg_block_size_in_bytes_lp) + ,.cce_id_width_p(cce_id_width_p) + ) + pending_bits + (.clk_i(clk_i) + ,.reset_i(reset_i) + // from arbitration - message or ucode + ,.w_v_i(pending_w_v_li) + ,.w_addr_i(pending_w_addr_li) + ,.w_addr_bypass_hash_i(pending_w_addr_bypass_li) + ,.pending_i(pending_li) + ,.clear_i(decoded_inst_lo.pending_clear) // only ucode can clear pending bit + // reads - only ucode + ,.r_v_i(decoded_inst_lo.pending_r_v) + ,.r_addr_i(addr_lo) + ,.r_addr_bypass_hash_i(addr_bypass_lo) + // output of read + ,.pending_o(pending_lo) + // Debug + ,.cce_id_i(cfg_bus_cast_i.cce_id) + ); + + // GAD logic - auxiliary directory information logic + bp_cce_gad + #(.bp_params_p(bp_params_p) + ) + gad + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.gad_v_i(decoded_inst_lo.gad_v) + + ,.sharers_v_i(sharers_v_lo) + ,.sharers_hits_i(sharers_hits_lo) + ,.sharers_ways_i(sharers_ways_lo) + ,.sharers_coh_states_i(sharers_coh_states_lo) + + ,.req_lce_i(mshr_lo.lce_id) + ,.req_type_flag_i(mshr_lo.flags.write_not_read) + ,.lru_coh_state_i(mshr_lo.lru_coh_state) + ,.atomic_req_flag_i(mshr_lo.flags.atomic) + ,.uncached_req_flag_i(mshr_lo.flags.uncached) + + ,.req_addr_way_o(gad_req_addr_way_lo) + ,.owner_lce_o(gad_owner_lce_lo) + ,.owner_way_o(gad_owner_way_lo) + ,.owner_coh_state_o(gad_owner_coh_state_lo) + ,.replacement_flag_o(gad_replacement_flag_lo) + ,.upgrade_flag_o(gad_upgrade_flag_lo) + ,.cached_shared_flag_o(gad_cached_shared_flag_lo) + ,.cached_exclusive_flag_o(gad_cached_exclusive_flag_lo) + ,.cached_modified_flag_o(gad_cached_modified_flag_lo) + ,.cached_owned_flag_o(gad_cached_owned_flag_lo) + ,.cached_forward_flag_o(gad_cached_forward_flag_lo) + ); + + // Register File + bp_cce_reg + #(.bp_params_p(bp_params_p) + ) + registers + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.decoded_inst_i(decoded_inst_lo) + ,.dir_lru_v_i(dir_lru_v_lo) + ,.dir_addr_v_i(dir_addr_v_lo) + + ,.stall_i(stall_lo) + + ,.src_a_i(src_a) + ,.alu_res_i(alu_res_lo) + + ,.lce_req_header_i(fsm_req_header_li) + ,.lce_req_v_i(fsm_req_v_li) + ,.lce_resp_header_i(fsm_resp_header_li) + ,.mem_rev_header_i(fsm_rev_header_li) + + ,.pending_i(pending_lo) + + ,.dir_lru_coh_state_i(dir_lru_coh_state_lo) + ,.dir_lru_addr_i(dir_lru_addr_lo) + + ,.dir_addr_i(dir_addr_lo) + ,.dir_addr_dst_gpr_i(dir_addr_dst_gpr_lo) + + ,.gad_req_addr_way_i(gad_req_addr_way_lo) + ,.gad_owner_lce_i(gad_owner_lce_lo) + ,.gad_owner_way_i(gad_owner_way_lo) + ,.gad_owner_coh_state_i(gad_owner_coh_state_lo) + ,.gad_replacement_flag_i(gad_replacement_flag_lo) + ,.gad_upgrade_flag_i(gad_upgrade_flag_lo) + ,.gad_cached_shared_flag_i(gad_cached_shared_flag_lo) + ,.gad_cached_exclusive_flag_i(gad_cached_exclusive_flag_lo) + ,.gad_cached_modified_flag_i(gad_cached_modified_flag_lo) + ,.gad_cached_owned_flag_i(gad_cached_owned_flag_lo) + ,.gad_cached_forward_flag_i(gad_cached_forward_flag_lo) + + ,.spec_sf_i(spec_bits_lo.spec) + + // register state outputs + ,.mshr_o(mshr_lo) + ,.gpr_o(gpr_lo) + ,.coh_state_o(coh_state_default_lo) + ,.auto_fwd_msg_o(auto_fwd_msg_lo) + ); + + // Message unit + bp_cce_msg + #(.bp_params_p(bp_params_p)) + message + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_i) + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + // inbound headers use valid->yumi + ,.lce_req_header_i(fsm_req_header_li) + ,.lce_req_data_i(fsm_req_data_li) + ,.lce_req_v_i(fsm_req_v_li) + ,.lce_req_yumi_o(fsm_req_yumi_lo) + ,.lce_req_new_i(fsm_req_new_li) + ,.lce_req_last_i(fsm_req_last_li) + + ,.lce_cmd_header_o(fsm_cmd_header_lo) + ,.lce_cmd_data_o(fsm_cmd_data_lo) + ,.lce_cmd_v_o(fsm_cmd_v_lo) + ,.lce_cmd_ready_then_i(fsm_cmd_ready_then_li) + ,.lce_cmd_new_i(fsm_cmd_new_lo) + ,.lce_cmd_last_i(fsm_cmd_last_lo) + + ,.lce_resp_header_i(fsm_resp_header_li) + ,.lce_resp_data_i(fsm_resp_data_li) + ,.lce_resp_v_i(fsm_resp_v_li) + ,.lce_resp_yumi_o(fsm_resp_yumi_lo) + ,.lce_resp_new_i(fsm_resp_new_li) + ,.lce_resp_last_i(fsm_resp_last_li) + + // CCE-MEM Interface + // BedRock Burst protocol: ready&valid + // inbound headers use valid->yumi + ,.mem_rev_header_i(fsm_rev_header_li) + ,.mem_rev_data_i(fsm_rev_data_li) + ,.mem_rev_v_i(fsm_rev_v_li) + ,.mem_rev_yumi_o(fsm_rev_yumi_lo) + ,.mem_rev_new_i(fsm_rev_new_li) + ,.mem_rev_last_i(fsm_rev_last_li) + + ,.mem_fwd_header_o(fsm_fwd_header_lo) + ,.mem_fwd_data_o(fsm_fwd_data_lo) + ,.mem_fwd_v_o(fsm_fwd_v_lo) + ,.mem_fwd_ready_then_i(fsm_fwd_ready_then_li) + ,.mem_fwd_new_i(fsm_fwd_new_lo) + ,.mem_fwd_last_i(fsm_fwd_last_lo) + + // Inputs + ,.lce_i(lce_lo) + ,.addr_i(addr_lo) + ,.way_i(way_lo) + ,.coh_state_i(state_lo) + ,.sharers_v_i(sharers_v_lo) + ,.sharers_hits_i(sharers_hits_lo) + ,.sharers_ways_i(sharers_ways_lo) + + ,.decoded_inst_i(decoded_inst_lo) + ,.mshr_i(mshr_lo) + ,.src_a_i(src_a) + ,.auto_fwd_msg_i(auto_fwd_msg_lo) + + // Outputs to Pending Bits + ,.pending_w_v_o(msg_pending_w_v_lo) + ,.pending_w_addr_o(msg_pending_w_addr_lo) + ,.pending_w_addr_bypass_o(msg_pending_w_addr_bypass_lo) + ,.pending_o(msg_pending_lo) + + // Outputs to Spec Bits + ,.spec_r_v_o(msg_spec_r_v_lo) + ,.spec_r_addr_o(msg_spec_r_addr_lo) + ,.spec_r_addr_bypass_o(msg_spec_r_addr_bypass_lo) + ,.spec_bits_i(spec_bits_lo) + + // Outputs to Directory + ,.dir_addr_o(msg_dir_addr_lo) + ,.dir_addr_bypass_o(msg_dir_addr_bypass_lo) + ,.dir_lce_o(msg_dir_lce_lo) + ,.dir_way_o(msg_dir_way_lo) + ,.dir_coh_state_o(msg_dir_coh_state_lo) + ,.dir_w_cmd_o(msg_dir_w_cmd_lo) + ,.dir_w_v_o(msg_dir_w_v_lo) + + // Outputs to Stall + // LCE Command used by auto-forward + ,.lce_cmd_busy_o(msg_lce_cmd_busy_lo) + // LCE Response used by auto-forward + ,.lce_resp_busy_o(msg_lce_resp_busy_lo) + // Mem Response used by auto-forward + ,.mem_rev_busy_o(msg_mem_rev_busy_lo) + // Stall ucode (as in inv command being processed) + ,.busy_o(msg_busy_lo) + // memory credits empty + ,.mem_credits_empty_o(msg_mem_credits_empty_lo) + // memory command send stall + ,.mem_fwd_stall_o(msg_mem_fwd_stall_lo) + ); + + // Speculative Access Bits + bp_cce_spec_bits + #(.num_way_groups_p(num_way_groups_lp) + ,.cce_way_groups_p(cce_way_groups_p) + ,.num_cce_p(num_cce_p) + ,.paddr_width_p(paddr_width_p) + ,.addr_offset_p(lg_block_size_in_bytes_lp) + ) + spec_bits + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(decoded_inst_lo.spec_w_v) + ,.w_addr_i(addr_lo) + ,.w_addr_bypass_hash_i(addr_bypass_lo) + + ,.spec_v_i(decoded_inst_lo.spec_v) + ,.squash_v_i(decoded_inst_lo.spec_squash_v) + ,.fwd_mod_v_i(decoded_inst_lo.spec_fwd_mod_v) + ,.state_v_i(decoded_inst_lo.spec_state_v) + ,.spec_i(decoded_inst_lo.spec_bits) + + ,.r_v_i(spec_r_v_li) + ,.r_addr_i(spec_r_addr_li) + ,.r_addr_bypass_hash_i(spec_r_addr_bypass_li) + + ,.spec_o(spec_bits_lo) + ); + + // Instruction Stall Detection + bp_cce_inst_stall + #() + inst_stall + (.decoded_inst_i(decoded_inst_lo) + + ,.lce_req_v_i(fsm_req_v_li) + ,.lce_resp_v_i(fsm_resp_v_li) + ,.mem_rev_v_i(fsm_rev_v_li) + ,.pending_v_i('0) + + ,.lce_cmd_yumi_i(fsm_cmd_v_lo) + ,.mem_credits_empty_i(msg_mem_credits_empty_lo) + + // From Messague Unit + ,.msg_busy_i(msg_busy_lo) + ,.msg_pending_w_busy_i(msg_pending_w_v_lo) + ,.msg_lce_cmd_busy_i(msg_lce_cmd_busy_lo) + ,.msg_lce_resp_busy_i(msg_lce_resp_busy_lo) + ,.msg_mem_rev_busy_i(msg_mem_rev_busy_lo) + ,.msg_spec_r_busy_i(msg_spec_r_v_lo) + ,.msg_dir_w_busy_i(msg_dir_w_v_lo) + ,.msg_mem_fwd_stall_i(msg_mem_fwd_stall_lo) + + // From Directory + ,.dir_busy_i(dir_busy_lo) + + ,.stall_o(stall_lo) + ); + + + // Debug and tracing signals + // synopsys translate_off + wire req_start = fsm_req_v_li & decoded_inst_lo.v & decoded_inst_lo.poph + & (decoded_inst_lo.popq_qsel == e_src_q_sel_lce_req); + // current microcode has clm instruction at ready label + wire req_end = decoded_inst_lo.v + & (decoded_inst_lo.op == e_op_reg_data) + & (decoded_inst_lo.minor_op_u.reg_data_minor_op == e_clm_op); + // synopsys translate_on + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_alu.sv b/designs/black-parrot/src/bp/bp_cce_alu.sv new file mode 100644 index 0000000..7f04a0a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_alu.sv @@ -0,0 +1,49 @@ +/** + * + * Name: + * bp_cce_alu.sv + * + * Description: + * A simple ALU for the CCE implementing addition, subtraction, logical shift, and bitwise + * operations (and, or, xor, negate). + * + * Some microcode operations such as addi and inc are implemented via assembler/softwware + * transforms and appropriate source selection. For example, inc is really an add where opd_b_i + * is an immediate from the instruction (source select), and the immediate has value 1 (assembler + * transform). See bp_cce_inst.svh for SW supported operations. + * + * The arithmetic width is parameterizable, and set based on the microarchitecture design. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_alu + import bp_me_pkg::*; + #(parameter `BSG_INV_PARAM(width_p)) + (input [width_p-1:0] opd_a_i + , input [width_p-1:0] opd_b_i + , input bp_cce_inst_alu_op_e alu_op_i + , output logic [width_p-1:0] res_o + ); + + always_comb begin : alu + unique case (alu_op_i) + e_alu_add: res_o = opd_a_i + opd_b_i; + e_alu_sub: res_o = opd_a_i - opd_b_i; + e_alu_lsh: res_o = opd_a_i << opd_b_i; + e_alu_rsh: res_o = opd_a_i >> opd_b_i; + e_alu_and: res_o = opd_a_i & opd_b_i; + e_alu_or: res_o = opd_a_i | opd_b_i; + e_alu_xor: res_o = opd_a_i ^ opd_b_i; + e_alu_neg: res_o = ~opd_a_i; + e_alu_not: res_o = !opd_a_i; + e_alu_nand: res_o = !(opd_a_i & opd_b_i); + e_alu_nor: res_o = !(opd_a_i | opd_b_i); + default: res_o = '0; + endcase + end +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_alu) diff --git a/designs/black-parrot/src/bp/bp_cce_arbitrate.sv b/designs/black-parrot/src/bp/bp_cce_arbitrate.sv new file mode 100644 index 0000000..1373365 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_arbitrate.sv @@ -0,0 +1,137 @@ +/** + * + * Name: + * bp_cce_arbitrate.sv + * + * Description: + * The arbitration unit controls access to the directory, pending bits, and + * speculative bits. Arbitration is between CCE modules and the microcode. + * + * auto-forward functionality uses the msg_pending_w port, which has priority over ucode + * ucode push/pop decoded instruction contains pending write signals + * - msg unit does not provide the pending_w signals for ucode push/pop + * If ucode push/pop writes pending (not all will), then it arbitrates with msg w port + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_arbitrate + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input stall_i + + // Directory Write from Microcode + , input [paddr_width_p-1:0] dir_addr_i + , input dir_addr_bypass_i + , input [lce_id_width_p-1:0] dir_lce_i + , input [lce_assoc_width_p-1:0] dir_way_i + , input bp_coh_states_e dir_coh_state_i + , input bp_cce_inst_minor_dir_op_e dir_cmd_i + , input dir_w_v_i + + // Directory Write from Message + , input [paddr_width_p-1:0] msg_dir_addr_i + , input msg_dir_addr_bypass_i + , input [lce_id_width_p-1:0] msg_dir_lce_i + , input [lce_assoc_width_p-1:0] msg_dir_way_i + , input bp_coh_states_e msg_dir_coh_state_i + , input bp_cce_inst_minor_dir_op_e msg_dir_w_cmd_i + , input msg_dir_w_v_i + + // Directory Write Output + , output logic [paddr_width_p-1:0] dir_addr_o + , output logic dir_addr_bypass_o + , output logic [lce_id_width_p-1:0] dir_lce_o + , output logic [lce_assoc_width_p-1:0] dir_way_o + , output bp_coh_states_e dir_coh_state_o + , output bp_cce_inst_minor_dir_op_e dir_cmd_o + , output logic dir_w_v_o + + // Pending Write from Microcode + , input pending_w_v_i + , input [paddr_width_p-1:0] pending_w_addr_i + , input pending_w_addr_bypass_i + , input pending_i + + // Pending Write from Message + , input msg_pending_w_v_i + , input [paddr_width_p-1:0] msg_pending_w_addr_i + , input msg_pending_w_addr_bypass_i + , input msg_pending_i + + // Pending Write Output + , output logic pending_w_v_o + , output logic [paddr_width_p-1:0] pending_w_addr_o + , output logic pending_w_addr_bypass_o + , output logic pending_o + + // Spec Read from Microcode + , input spec_r_v_i + , input [paddr_width_p-1:0] spec_r_addr_i + , input spec_r_addr_bypass_i + + // Spec Write from Message + , input msg_spec_r_v_i + , input [paddr_width_p-1:0] msg_spec_r_addr_i + , input msg_spec_r_addr_bypass_i + + // Spec Read Output + , output logic spec_r_v_o + , output logic [paddr_width_p-1:0] spec_r_addr_o + , output logic spec_r_addr_bypass_o + + ); + + always_comb begin + + // Directory Write + if (msg_dir_w_v_i) begin + dir_addr_o = msg_dir_addr_i; + dir_addr_bypass_o = msg_dir_addr_bypass_i; + dir_lce_o = msg_dir_lce_i; + dir_way_o = msg_dir_way_i; + dir_coh_state_o = msg_dir_coh_state_i; + dir_cmd_o = msg_dir_w_cmd_i; + dir_w_v_o = msg_dir_w_v_i; + end else begin + dir_addr_o = dir_addr_i; + dir_addr_bypass_o = dir_addr_bypass_i; + dir_lce_o = dir_lce_i; + dir_way_o = dir_way_i; + dir_coh_state_o = dir_coh_state_i; + dir_cmd_o = dir_cmd_i; + dir_w_v_o = dir_w_v_i & ~stall_i; + end + + // Pending Bit Write + if (msg_pending_w_v_i) begin + pending_w_v_o = msg_pending_w_v_i; + pending_w_addr_o = msg_pending_w_addr_i; + pending_w_addr_bypass_o = msg_pending_w_addr_bypass_i; + pending_o = msg_pending_i; + end else begin + pending_w_v_o = pending_w_v_i & ~stall_i; + pending_w_addr_o = pending_w_addr_i; + pending_w_addr_bypass_o = pending_w_addr_bypass_i; + pending_o = pending_i; + end + + // Spec Bits Read + if (msg_spec_r_v_i) begin + spec_r_v_o = msg_spec_r_v_i; + spec_r_addr_o = msg_spec_r_addr_i; + spec_r_addr_bypass_o = msg_spec_r_addr_bypass_i; + end else begin + // register file does not change state of spec flag unless not stalling + spec_r_v_o = spec_r_v_i; + spec_r_addr_o = spec_r_addr_i; + spec_r_addr_bypass_o = spec_r_addr_bypass_i; + end + + end + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_branch.sv b/designs/black-parrot/src/bp/bp_cce_branch.sv new file mode 100644 index 0000000..3469f4a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_branch.sv @@ -0,0 +1,70 @@ +/** + * + * Name: + * bp_cce_branch.sv + * + * Description: + * Branch evaluation logic for the CCE implementing equality/inequality and less than comparison. + * The branch unit also performs misprediction resolution, if needed. + * + * Some microcode operations such as bgt are implemented via assembler/softwware transforms. + * See bp_cce_inst.svh for SW supported operations. + * + * The operand width is parameterizable, and set based on the microarchitecture design. + * + * The branch unit also computes and outputs the correct next PC for all instructions. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_branch + import bp_me_pkg::*; + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(cce_pc_width_p) + ) + (input [width_p-1:0] opd_a_i + , input [width_p-1:0] opd_b_i + , input branch_i + , input predicted_taken_i + , input bp_cce_inst_branch_op_e branch_op_i + , input [cce_pc_width_p-1:0] execute_pc_i + , input [cce_pc_width_p-1:0] branch_target_i + , output logic mispredict_o + , output logic [cce_pc_width_p-1:0] pc_o + ); + + wire equal = (opd_a_i == opd_b_i); + wire not_equal = ~equal; + wire less = (opd_a_i < opd_b_i); + + wire [cce_pc_width_p-1:0] execute_pc_plus_one = cce_pc_width_p'(execute_pc_i + 'd1); + + logic branch_res; + always_comb begin : branch + unique case (branch_op_i) + e_branch_eq: branch_res = equal; + e_branch_neq: branch_res = not_equal; + e_branch_lt: branch_res = less; + e_branch_le: branch_res = (less | equal); + default: branch_res = '0; + endcase + + // Misprediction happens if instruction is branch and: + // a) branch was predicted not taken, but branch should have been taken + // b) branch was predicted taken, but branch should not have been taken + mispredict_o = branch_i & ((!predicted_taken_i & branch_res) + | (predicted_taken_i & !branch_res)); + + // Output correct next PC (for all instructions) + // If the current instruction is a branch and the branch evaluates to taken, the next PC + // is the branch target. Else, the next PC is the current PC plus one. + pc_o = (branch_i & branch_res) + ? branch_target_i + : execute_pc_plus_one; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_branch) diff --git a/designs/black-parrot/src/bp/bp_cce_dir.sv b/designs/black-parrot/src/bp/bp_cce_dir.sv new file mode 100644 index 0000000..6f1bd7d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_dir.sv @@ -0,0 +1,379 @@ +/** + * + * Name: + * bp_cce_dir.sv + * + * Description: + * The directory stores the coherence state and tags for all cache blocks tracked by + * a CCE. The directory supports a small set of operations such as reading a way-group or entry, + * and writing an entry's coherence state and tag. + * + * The directory is partitioned into directory segments, where each segment tracks the + * coherence for a single type of LCE (I$, D$, A$, etc.). + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_dir + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Derived parameters + , localparam block_size_in_bytes_lp = (bedrock_block_width_p/8) + + // I$ and D$ LCE ID's are [0, (2*num_core_p)-1] + // A$ LCE ID's start at (2*num_core_p) + , localparam acc_lce_id_offset_lp = (num_core_p*2) + ) + (input clk_i + , input reset_i + + , input [paddr_width_p-1:0] addr_i + , input addr_bypass_i + + , input [lce_id_width_p-1:0] lce_i + , input [lce_assoc_width_p-1:0] way_i + , input [lce_assoc_width_p-1:0] lru_way_i + , input bp_coh_states_e coh_state_i + , input bp_cce_inst_opd_gpr_e addr_dst_gpr_i + + , input bp_cce_inst_minor_dir_op_e cmd_i + , input r_v_i + , input w_v_i + + , output logic busy_o + + , output logic sharers_v_o + , output logic [num_lce_p-1:0] sharers_hits_o + , output logic [num_lce_p-1:0][lce_assoc_width_p-1:0] sharers_ways_o + , output bp_coh_states_e [num_lce_p-1:0] sharers_coh_states_o + + , output logic lru_v_o + , output bp_coh_states_e lru_coh_state_o + , output logic [paddr_width_p-1:0] lru_addr_o + + , output logic addr_v_o + , output logic [paddr_width_p-1:0] addr_o + , output bp_cce_inst_opd_gpr_e addr_dst_gpr_o + + // Debug + , input [cce_id_width_p-1:0] cce_id_i + ); + + // cce_id_i is used for debugging / tracing the directory + wire unused = &{cce_id_i}; + + // Number of CCEs must be at least as large as the minimal number of sets in any of the + // LCE types (dcache, icache, acache). This ensures that every tag set is wholly stored + // in a *single* CCE (equivalently, tag sets are not split across CCEs). + // LCEs and CCEs use the set index bits from the physical address to map address to CCE. + // The minimal number of sets is computed in aviary as cce_way_groups_p + if (cce_way_groups_p < num_cce_p) + $error("Number of CCEs must be at least as large as the minimal number of LCE sets"); + + // directory does not support caches with only 1 set + if (dcache_sets_p <= 1) $error("D$ must have more than 1 set"); + if (icache_sets_p <= 1) $error("I$ must have more than 1 set"); + if ((num_cacc_p > 0) && (acache_sets_p <= 1)) $error("A$ must have more than 1 set"); + + + wire lce_is_icache = (~lce_i[0] && (lce_i < acc_lce_id_offset_lp)); + wire lce_is_dcache = (lce_i[0] && (lce_i < acc_lce_id_offset_lp)); + wire lce_is_acache = (lce_i >= acc_lce_id_offset_lp); + + // I$ directory segment + + // I$ segment parameters + localparam icache_dir_sets_lp = `BSG_CDIV(icache_sets_p, num_cce_p); + localparam lg_icache_assoc_lp = `BSG_SAFE_CLOG2(icache_assoc_p); + localparam icache_lce_id_width_lp = `BSG_SAFE_CLOG2(num_core_p); + + wire [icache_lce_id_width_lp-1:0] icache_lce_id = lce_i[1+:icache_lce_id_width_lp]; + + // I$ segment signals + wire icache_r_v = r_v_i & ((cmd_i == e_rdw_op) + | ((cmd_i == e_rde_op) && lce_is_icache)); + wire icache_w_v = w_v_i & lce_is_icache; + + logic icache_sharers_v; + logic [num_core_p-1:0] icache_sharers_hits; + logic [num_core_p-1:0][lg_icache_assoc_lp-1:0] icache_sharers_ways; + bp_coh_states_e [num_core_p-1:0] icache_sharers_coh_states; + + logic icache_busy, icache_lru_v, icache_addr_v; + logic [paddr_width_p-1:0] icache_lru_addr_lo, icache_addr_lo; + bp_cce_inst_opd_gpr_e icache_addr_dst_gpr_lo; + bp_coh_states_e icache_lru_coh_state_lo; + + bp_cce_dir_segment + #(.tag_sets_p(icache_dir_sets_lp) + ,.num_lce_p(num_core_p) + ,.sets_p(icache_sets_p) + ,.assoc_p(icache_assoc_p) + ,.paddr_width_p(paddr_width_p) + ,.tag_width_p(icache_tag_width_p) + ,.num_cce_p(num_cce_p) + ,.block_size_in_bytes_p(block_size_in_bytes_lp) + ) + icache_dir_segment + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.addr_i(addr_i) + ,.addr_bypass_i(addr_bypass_i) + ,.lce_i(icache_lce_id) + ,.way_i(way_i[0+:lg_icache_assoc_lp]) + ,.lru_way_i(lru_way_i[0+:lg_icache_assoc_lp]) + ,.coh_state_i(coh_state_i) + ,.addr_dst_gpr_i(addr_dst_gpr_i) + ,.cmd_i(cmd_i) + ,.r_v_i(icache_r_v) + ,.r_lru_v_i(lce_is_icache) + ,.w_v_i(icache_w_v) + ,.busy_o(icache_busy) + ,.sharers_v_o(icache_sharers_v) + ,.sharers_hits_o(icache_sharers_hits) + ,.sharers_ways_o(icache_sharers_ways) + ,.sharers_coh_states_o(icache_sharers_coh_states) + ,.lru_v_o(icache_lru_v) + ,.lru_coh_state_o(icache_lru_coh_state_lo) + ,.lru_addr_o(icache_lru_addr_lo) + ,.addr_v_o(icache_addr_v) + ,.addr_o(icache_addr_lo) + ,.addr_dst_gpr_o(icache_addr_dst_gpr_lo) + ); + + // D$ directory segment + + // D$ segment parameters + localparam dcache_dir_sets_lp = `BSG_CDIV(dcache_sets_p, num_cce_p); + localparam lg_dcache_assoc_lp = `BSG_SAFE_CLOG2(dcache_assoc_p); + localparam dcache_lce_id_width_lp = `BSG_SAFE_CLOG2(num_core_p); + + // D$ segment signals + logic dcache_sharers_v; + logic [num_core_p-1:0] dcache_sharers_hits; + logic [num_core_p-1:0][lg_dcache_assoc_lp-1:0] dcache_sharers_ways; + bp_coh_states_e [num_core_p-1:0] dcache_sharers_coh_states; + + logic dcache_busy, dcache_lru_v, dcache_addr_v; + logic [paddr_width_p-1:0] dcache_lru_addr_lo, dcache_addr_lo; + bp_cce_inst_opd_gpr_e dcache_addr_dst_gpr_lo; + bp_coh_states_e dcache_lru_coh_state_lo; + + if (num_lce_p > 1) begin : dcache + + wire [dcache_lce_id_width_lp-1:0] dcache_lce_id = lce_i[1+:dcache_lce_id_width_lp]; + + wire dcache_r_v = r_v_i & ((cmd_i == e_rdw_op) + | ((cmd_i == e_rde_op) && lce_is_dcache)); + wire dcache_w_v = w_v_i & lce_is_dcache; + + bp_cce_dir_segment + #(.tag_sets_p(dcache_dir_sets_lp) + ,.num_lce_p(num_core_p) + ,.sets_p(dcache_sets_p) + ,.assoc_p(dcache_assoc_p) + ,.paddr_width_p(paddr_width_p) + ,.tag_width_p(dcache_tag_width_p) + ,.num_cce_p(num_cce_p) + ,.block_size_in_bytes_p(block_size_in_bytes_lp) + ) + dcache_dir_segment + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.addr_i(addr_i) + ,.addr_bypass_i(addr_bypass_i) + ,.lce_i(dcache_lce_id) + ,.way_i(way_i[0+:lg_dcache_assoc_lp]) + ,.lru_way_i(lru_way_i[0+:lg_dcache_assoc_lp]) + ,.coh_state_i(coh_state_i) + ,.addr_dst_gpr_i(addr_dst_gpr_i) + ,.cmd_i(cmd_i) + ,.r_v_i(dcache_r_v) + ,.r_lru_v_i(lce_is_dcache) + ,.w_v_i(dcache_w_v) + ,.busy_o(dcache_busy) + ,.sharers_v_o(dcache_sharers_v) + ,.sharers_hits_o(dcache_sharers_hits) + ,.sharers_ways_o(dcache_sharers_ways) + ,.sharers_coh_states_o(dcache_sharers_coh_states) + ,.lru_v_o(dcache_lru_v) + ,.lru_coh_state_o(dcache_lru_coh_state_lo) + ,.lru_addr_o(dcache_lru_addr_lo) + ,.addr_v_o(dcache_addr_v) + ,.addr_o(dcache_addr_lo) + ,.addr_dst_gpr_o(dcache_addr_dst_gpr_lo) + ); + end else begin + // No dcache in system (i.e., half_core_cfg), assign all outputs from dcache segment to 0. + // (and hope the tool optimizes them away) + always_comb begin + dcache_busy = '0; + dcache_sharers_v = 1'b1; + dcache_sharers_hits = '0; + dcache_sharers_ways = '0; + dcache_sharers_coh_states = e_COH_I; + dcache_lru_v = '0; + dcache_lru_coh_state_lo = e_COH_I; + dcache_lru_addr_lo = '0; + dcache_addr_v = '0; + dcache_addr_lo = '0; + dcache_addr_dst_gpr_lo = e_opd_r0; + end + end + + // A$ directory segment + + // A$ segment parameters + localparam acache_dir_sets_lp = `BSG_CDIV(acache_sets_p, num_cce_p); + localparam lg_acache_assoc_lp = `BSG_SAFE_CLOG2(acache_assoc_p); + localparam acache_lce_id_width_lp = `BSG_SAFE_CLOG2(num_cacc_p); + // local param that is set to 1 if there are 0 CACC's, so the acache_sharers vectors + // are sized properly when there are no accelerators. This is only used to size the vectors + // as 1 element vectors when there are no accelerators present. + localparam num_cacc_lp = (num_cacc_p == 0) ? 1 : num_cacc_p; + + logic acache_sharers_v; + logic [num_cacc_lp-1:0] acache_sharers_hits; + logic [num_cacc_lp-1:0][lg_acache_assoc_lp-1:0] acache_sharers_ways; + bp_coh_states_e [num_cacc_lp-1:0] acache_sharers_coh_states; + + logic acache_busy, acache_lru_v, acache_addr_v; + logic [paddr_width_p-1:0] acache_lru_addr_lo, acache_addr_lo; + bp_cce_inst_opd_gpr_e acache_addr_dst_gpr_lo; + bp_coh_states_e acache_lru_coh_state_lo; + + if (num_cacc_p > 0) begin : acache + // A$ segment signals + wire [acache_lce_id_width_lp-1:0] acache_lce_id = + acache_lce_id_width_lp'(lce_i - acc_lce_id_offset_lp); + + wire acache_r_v = r_v_i & ((cmd_i == e_rdw_op) + | ((cmd_i == e_rde_op) && lce_is_acache)); + wire acache_w_v = w_v_i & lce_is_acache; + + // Accelerator LCEs exist, instantiate a directory segmenet to track them + bp_cce_dir_segment + #(.tag_sets_p(acache_dir_sets_lp) + ,.num_lce_p(num_cacc_p) + ,.sets_p(acache_sets_p) + ,.assoc_p(acache_assoc_p) + ,.paddr_width_p(paddr_width_p) + ,.tag_width_p(acache_tag_width_p) + ,.num_cce_p(num_cce_p) + ,.block_size_in_bytes_p(block_size_in_bytes_lp) + ) + acache_dir_segment + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.addr_i(addr_i) + ,.addr_bypass_i(addr_bypass_i) + ,.lce_i(acache_lce_id) + ,.way_i(way_i[0+:lg_acache_assoc_lp]) + ,.lru_way_i(lru_way_i[0+:lg_acache_assoc_lp]) + ,.coh_state_i(coh_state_i) + ,.addr_dst_gpr_i(addr_dst_gpr_i) + ,.cmd_i(cmd_i) + ,.r_v_i(acache_r_v) + ,.r_lru_v_i(lce_is_acache) + ,.w_v_i(acache_w_v) + ,.busy_o(acache_busy) + ,.sharers_v_o(acache_sharers_v) + ,.sharers_hits_o(acache_sharers_hits) + ,.sharers_ways_o(acache_sharers_ways) + ,.sharers_coh_states_o(acache_sharers_coh_states) + ,.lru_v_o(acache_lru_v) + ,.lru_coh_state_o(acache_lru_coh_state_lo) + ,.lru_addr_o(acache_lru_addr_lo) + ,.addr_v_o(acache_addr_v) + ,.addr_o(acache_addr_lo) + ,.addr_dst_gpr_o(acache_addr_dst_gpr_lo) + ); + + end else begin + // No accelerators in system, assign all outputs from acache segment to 0. + // (and hope the tool optimizes them away) + always_comb begin + acache_busy = '0; + acache_sharers_v = 1'b1; + acache_sharers_hits = '0; + acache_sharers_ways = '0; + acache_sharers_coh_states = e_COH_I; + acache_lru_v = '0; + acache_lru_coh_state_lo = e_COH_I; + acache_lru_addr_lo = '0; + acache_addr_v = '0; + acache_addr_lo = '0; + acache_addr_dst_gpr_lo = e_opd_r0; + end + end + + // Output combination + assign busy_o = icache_busy | dcache_busy | acache_busy; + assign sharers_v_o = icache_sharers_v & dcache_sharers_v & acache_sharers_v; + always_comb begin + sharers_hits_o = '0; + sharers_ways_o = '0; + sharers_coh_states_o = {((2*num_core_p)+num_cacc_p){e_COH_I}}; + for (int i = 0; i < num_core_p; i++) begin + sharers_hits_o[(2*i)] = icache_sharers_hits[i]; + sharers_ways_o[(2*i)][0+:lg_icache_assoc_lp] = icache_sharers_ways[i]; + sharers_coh_states_o[(2*i)] = icache_sharers_coh_states[i]; + sharers_hits_o[(2*i)+1] = dcache_sharers_hits[i]; + sharers_ways_o[(2*i)+1][0+:lg_dcache_assoc_lp] = dcache_sharers_ways[i]; + sharers_coh_states_o[(2*i)+1] = dcache_sharers_coh_states[i]; + end + for (int i = 0; i < num_cacc_p; i++) begin + sharers_hits_o[i+(2*num_core_p)] = acache_sharers_hits[i]; + sharers_ways_o[i+(2*num_core_p)][0+:lg_acache_assoc_lp] = acache_sharers_ways[i]; + sharers_coh_states_o[i+(2*num_core_p)] = acache_sharers_coh_states[i]; + end + end + + assign lru_v_o = icache_lru_v | dcache_lru_v | acache_lru_v; + assign lru_addr_o = icache_lru_v + ? icache_lru_addr_lo + : dcache_lru_v + ? dcache_lru_addr_lo + : acache_lru_v + ? acache_lru_addr_lo + : '0; + assign lru_coh_state_o = icache_lru_v + ? icache_lru_coh_state_lo + : dcache_lru_v + ? dcache_lru_coh_state_lo + : acache_lru_v + ? acache_lru_coh_state_lo + : e_COH_I; + + assign addr_v_o = icache_addr_v | dcache_addr_v | acache_addr_v; + assign addr_o = icache_addr_v + ? icache_addr_lo + : dcache_addr_v + ? dcache_addr_lo + : acache_addr_v + ? acache_addr_lo + : '0; + assign addr_dst_gpr_o = icache_addr_v + ? icache_addr_dst_gpr_lo + : dcache_addr_v + ? dcache_addr_dst_gpr_lo + : acache_addr_v + ? acache_addr_dst_gpr_lo + : e_opd_r0; + + // synopsys translate_off + always_ff @(negedge clk_i) begin + if (~reset_i) begin + assert(reset_i !== '0 || $countones({icache_lru_v, dcache_lru_v, acache_lru_v}) <= 1) + else $error("Multiple directory segments attempting to output LRU information in same cycle"); + assert(reset_i !== '0 || $countones({icache_addr_v, dcache_addr_v, acache_addr_v}) <= 1) + else $error("Multiple directory segments attempting to output addr information in same cycle"); + end + end + // synopsys translate_on + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_dir_lru_extract.sv b/designs/black-parrot/src/bp/bp_cce_dir_lru_extract.sv new file mode 100644 index 0000000..66a318e --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_dir_lru_extract.sv @@ -0,0 +1,61 @@ +/** + * + * Name: + * bp_cce_dir_lru_extract.sv + * + * Description: + * This module extracts information about the LRU entry of the requesting LCE + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_dir_lru_extract + import bp_common_pkg::*; + #(parameter `BSG_INV_PARAM(tag_sets_per_row_p) + , parameter `BSG_INV_PARAM(row_width_p) + , parameter `BSG_INV_PARAM(num_lce_p) + , parameter `BSG_INV_PARAM(assoc_p) + , parameter `BSG_INV_PARAM(rows_per_set_p) + , parameter `BSG_INV_PARAM(tag_width_p) + + , localparam lg_num_lce_lp = `BSG_SAFE_CLOG2(num_lce_p) + , localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p) + , localparam lg_rows_per_set_lp = `BSG_SAFE_CLOG2(rows_per_set_p) + ) + ( + // input row from directory RAM, per tag set valid bit, and row number + input [row_width_p-1:0] row_i + , input [tag_sets_per_row_p-1:0] row_v_i + , input [lg_rows_per_set_lp-1:0] row_num_i + + // requesting LCE and LRU way for the request + , input [lg_num_lce_lp-1:0] lce_i + , input [lg_assoc_lp-1:0] lru_way_i + + , output logic lru_v_o + , output bp_coh_states_e lru_coh_state_o + , output logic [tag_width_p-1:0] lru_tag_o + + ); + + `declare_bp_cce_dir_entry_s(tag_width_p); + dir_entry_s [tag_sets_per_row_p-1:0][assoc_p-1:0] row; + + always_comb begin + // cast directory row for easy access to state and tag + row = row_i; + + // LRU output is valid if: + // 1. tag set input is valid + // 2. target LCE's tag set is stored on the input row + lru_v_o = (row_v_i[lce_i[0]]) & ((lce_i >> 1) == row_num_i); + lru_coh_state_o = row[lce_i[0]][lru_way_i].state; + lru_tag_o = row[lce_i[0]][lru_way_i].tag; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_dir_lru_extract) + diff --git a/designs/black-parrot/src/bp/bp_cce_dir_segment.sv b/designs/black-parrot/src/bp/bp_cce_dir_segment.sv new file mode 100644 index 0000000..d488198 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_dir_segment.sv @@ -0,0 +1,538 @@ +/** + * + * Name: + * bp_cce_dir_segment.sv + * + * Description: + * A directory segment stores the coherence state and tags for a set of cache blocks tracked + * by the CCE. Each segment tracks coherence info for a single type of LCE in the system. + * Different LCE types include data caches, instruction caches, and accelerator caches. + * + * The physical directory SRAM is a synchronous read 1RW memory. + * + * All write operations take 1 cycle, but read operations take multiple cycles. The busy_o + * signal will be asserted until the read operation is completed. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_dir_segment + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter `BSG_INV_PARAM(tag_sets_p) // number of tag sets tracked by this directory + , parameter `BSG_INV_PARAM(num_lce_p) // number of LCEs tracked in this directory + // parameters of cache type being tracked + , parameter `BSG_INV_PARAM(sets_p) // number of cache sets + , parameter `BSG_INV_PARAM(assoc_p) // associativity of each set + , parameter `BSG_INV_PARAM(paddr_width_p) // physical address width + , parameter `BSG_INV_PARAM(tag_width_p) // tag width of cacheable memory + , parameter `BSG_INV_PARAM(block_size_in_bytes_p) // size of cache blocks in bytes + + , parameter `BSG_INV_PARAM(num_cce_p) // number of CCEs that blocks are banked across + + // This is set as a constant based on prior physical design work showing 2 tag sets + // per row gives good PPA, assuming 64-set, 8-way associative LCEs. + // For even numbers of LCEs, all rows are fully utilized + // For odd numbers of LCEs, last row for a way group will only have 1 tag set in use + // Warning: changing this to another value will likely break the directory implementation + , localparam tag_sets_per_row_lp = 2 + + // Derived parameters + , localparam lg_tag_sets_per_row_lp = `BSG_SAFE_CLOG2(tag_sets_per_row_lp) + , localparam lg_tag_sets_lp = `BSG_SAFE_CLOG2(tag_sets_p) + , localparam lg_num_lce_lp = `BSG_SAFE_CLOG2(num_lce_p) + + , localparam lg_sets_lp = `BSG_SAFE_CLOG2(sets_p) + , localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p) + , localparam lg_block_size_in_bytes_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_p) + , localparam lg_num_cce_lp = `BSG_SAFE_CLOG2(num_cce_p) + + // For VIPT L1 caches, should be equivalent to page_offset_width + , localparam tag_offset_lp = (lg_sets_lp+lg_block_size_in_bytes_lp) + + , localparam hash_index_width_lp = $clog2((2**lg_sets_lp+num_cce_p-1)/num_cce_p) + + // Directory information width + , localparam entry_width_lp = (tag_width_p+$bits(bp_coh_states_e)) + , localparam tag_set_width_lp = (entry_width_lp*assoc_p) + , localparam row_width_lp = (tag_set_width_lp*tag_sets_per_row_lp) + + // Number of rows to hold one set from all LCEs + // Note: If there is an odd number of LCEs managed by this directory segment, the + // last row per set will only utilize one of the 2 entries. + // if num_lce_p == 1, rows_per_set_lp = CDIV(1,2) = ceil(1/2) = 1 + , localparam rows_per_set_lp = `BSG_CDIV(num_lce_p, tag_sets_per_row_lp) + , localparam lg_rows_per_set_lp = `BSG_SAFE_CLOG2(rows_per_set_lp) + + // Total number of rows in the directory RAM + , localparam rows_lp = (rows_per_set_lp*tag_sets_p) + , localparam lg_rows_lp = `BSG_SAFE_CLOG2(rows_lp) + + // Is the last directory row for each set fully utilized? + , localparam last_row_full_lp = ((num_lce_p % tag_sets_per_row_lp) == 0) + + , localparam counter_max_lp = (rows_lp+1) + , localparam counter_width_lp = `BSG_SAFE_CLOG2(counter_max_lp) + + ) + (input clk_i + , input reset_i + + // input address, fed to bsg_hash_bank + , input [paddr_width_p-1:0] addr_i + // bypass signal to use low bits of raw address instead of hashed address + , input addr_bypass_i + + , input [lg_num_lce_lp-1:0] lce_i + , input [lg_assoc_lp-1:0] way_i + , input [lg_assoc_lp-1:0] lru_way_i + , input bp_coh_states_e coh_state_i + , input bp_cce_inst_opd_gpr_e addr_dst_gpr_i + + , input bp_cce_inst_minor_dir_op_e cmd_i + , input r_v_i + , input r_lru_v_i + , input w_v_i + + , output logic busy_o + + , output logic sharers_v_o + , output logic [num_lce_p-1:0] sharers_hits_o + , output logic [num_lce_p-1:0][lg_assoc_lp-1:0] sharers_ways_o + , output bp_coh_states_e [num_lce_p-1:0] sharers_coh_states_o + + , output logic lru_v_o + , output bp_coh_states_e lru_coh_state_o + , output logic [paddr_width_p-1:0] lru_addr_o + + , output logic addr_v_o + , output logic [paddr_width_p-1:0] addr_o + , output bp_cce_inst_opd_gpr_e addr_dst_gpr_o + ); + + // parameter checks + // If value of tag_sets_per_row_lp changes (is no longer 2) the directory logic + // needs to be re-written. + if (tag_sets_per_row_lp != 2) + $error("Unsupported configuration: number of sets per row must equal 2"); + if (sets_p <= 1) + $error("Number of cache sets must be greater than 1; direct-mapped caches not supported"); + if (tag_sets_p < 1) + $error("Number of tag sets must be at least 1"); + + // input address hashing + logic [lg_num_cce_lp-1:0] cce_id_lo; + logic [hash_index_width_lp-1:0] set_id_lo; + // NOTE: reverse the address to use the low order bits for striping cache blocks across CCEs + wire [lg_sets_lp-1:0] hash_addr_rev = { <<{addr_i[lg_block_size_in_bytes_lp+:lg_sets_lp]}}; + + bsg_hash_bank + #(.banks_p(num_cce_p) // number of CCE's to spread way groups over + ,.width_p(lg_sets_lp) // width of address input + ) + addr_to_cce_id + (.i(hash_addr_rev) + ,.bank_o(cce_id_lo) + ,.index_o(set_id_lo) + ); + + // Bypass hashing if input wants to use raw address input + logic [lg_rows_lp-1:0] set_id; + assign set_id = addr_bypass_i ? {'0, addr_i[0+:lg_tag_sets_lp]} : {'0, set_id_lo}; + + // address offset table + logic [rows_per_set_lp-1:0][lg_rows_lp-1:0] addr_offset_table; + genvar i; + generate + for (i = 0; i < rows_per_set_lp; i++) begin + assign addr_offset_table[i] = lg_rows_lp'(i * tag_sets_p); + end + endgenerate + logic [lg_rows_per_set_lp-1:0] addr_lce; + if (rows_per_set_lp > 1) begin + // lookup: lce_i[1+:], assuming tag_sets_per_row_lp == 2 + assign addr_lce = lce_i[1+:lg_rows_per_set_lp]; + end else begin + assign addr_lce = '0; + end + wire [lg_rows_lp-1:0] addr_offset = addr_offset_table[addr_lce]; + + // directory address for single entry operations + wire [lg_rows_lp-1:0] entry_row_addr = addr_offset + set_id; + + // Struct for directory entries + `declare_bp_cce_dir_entry_s(tag_width_p); + + // Directory signals + // read / write valid signals + logic dir_ram_w_v; + logic dir_ram_v; + // address input and address register + logic [lg_rows_lp-1:0] dir_ram_addr; + logic [lg_rows_lp-1:0] dir_ram_addr_r, dir_ram_addr_n; + // write mask and data in + dir_entry_s [tag_sets_per_row_lp-1:0][assoc_p-1:0] dir_ram_w_mask, dir_ram_w_data; + // data out + dir_entry_s [tag_sets_per_row_lp-1:0][assoc_p-1:0] dir_row_entries; + + // Counter + logic cnt_clr, cnt_inc; + logic [counter_width_lp-1:0] cnt; + + // State machine + typedef enum logic [2:0] { + RESET + ,INIT + ,READY + ,READ_FULL + ,READ_ENTRY + } dir_state_e; + + dir_state_e state_r, state_n; + + // Registers + logic [lg_num_lce_lp-1:0] lce_r, lce_n; + logic [lg_assoc_lp-1:0] way_r, way_n; + logic [lg_assoc_lp-1:0] lru_way_r, lru_way_n; + logic [paddr_width_p-1:0] addr_r, addr_n; + wire [tag_width_p-1:0] addr_r_tag = addr_r[tag_offset_lp +: tag_width_p]; + logic [tag_sets_per_row_lp-1:0] dir_data_o_v_r, dir_data_o_v_n; + bp_cce_inst_opd_gpr_e addr_dst_gpr_r, addr_dst_gpr_n; + // this registers is set when a rdw operation occurs and this segment must output the LRU + // information for the read because the requesting LCE is tracked by this segment. + logic r_lru_v_r, r_lru_v_n; + + assign addr_dst_gpr_o = addr_dst_gpr_r; + + // Sharers registers + logic sharers_v_r, sharers_v_n; + logic [num_lce_p-1:0] sharers_hits_r, sharers_hits_n; + logic [num_lce_p-1:0][lg_assoc_lp-1:0] sharers_ways_r, sharers_ways_n; + bp_coh_states_e [num_lce_p-1:0] sharers_coh_states_r, sharers_coh_states_n; + + assign sharers_v_o = sharers_v_r; + assign sharers_hits_o = sharers_hits_r; + assign sharers_ways_o = sharers_ways_r; + assign sharers_coh_states_o = sharers_coh_states_r; + + logic [tag_sets_per_row_lp-1:0] sharers_hits; + logic [tag_sets_per_row_lp-1:0][lg_assoc_lp-1:0] sharers_ways; + bp_coh_states_e [tag_sets_per_row_lp-1:0] sharers_coh_states; + + // synopsys sync_set_reset reset_i + always_ff @(posedge clk_i) begin + if (reset_i) begin + state_r <= RESET; + lce_r <= '0; + way_r <= '0; + lru_way_r <= '0; + addr_r <= '0; + dir_data_o_v_r <= '0; + dir_ram_addr_r <= '0; + + addr_dst_gpr_r <= e_opd_r0; + + r_lru_v_r <= '0; + + sharers_v_r <= '0; + sharers_hits_r <= '0; + sharers_ways_r <= '0; + sharers_coh_states_r <= e_COH_I; + + end else begin + state_r <= state_n; + lce_r <= lce_n; + way_r <= way_n; + lru_way_r <= lru_way_n; + addr_r <= addr_n; + dir_data_o_v_r <= dir_data_o_v_n; + dir_ram_addr_r <= dir_ram_addr_n; + + addr_dst_gpr_r <= addr_dst_gpr_n; + + r_lru_v_r <= r_lru_v_n; + + sharers_v_r <= sharers_v_n; + sharers_hits_r <= sharers_hits_n; + sharers_ways_r <= sharers_ways_n; + sharers_coh_states_r <= sharers_coh_states_n; + + end + end + + // Directory State Machine logic + always_comb begin + // state - hold by default + state_n = state_r; + + // counter inputs + cnt_clr = 1'b0; + cnt_inc = 1'b0; + + // directory inputs + dir_ram_w_mask = '0; + dir_ram_w_data = '0; + dir_ram_v = '0; + dir_ram_w_v = '0; + dir_ram_addr = '0; + + lce_n = lce_r; + way_n = way_r; + lru_way_n = lru_way_r; + addr_n = addr_r; + dir_data_o_v_n = '0; + dir_ram_addr_n = dir_ram_addr_r; + + addr_dst_gpr_n = addr_dst_gpr_r; + + r_lru_v_n = r_lru_v_r; + + sharers_v_n = sharers_v_r; + sharers_hits_n = sharers_hits_r; + sharers_ways_n = sharers_ways_r; + sharers_coh_states_n = sharers_coh_states_r; + + // outputs + busy_o = '0; + addr_v_o = '0; + addr_o = '0; + + case (state_r) + RESET: begin + state_n = INIT; + cnt_clr = 1'b1; + end + INIT: begin + // clear every row in directory after reset + dir_ram_v = 1'b1; + dir_ram_w_v = 1'b1; + dir_ram_addr = cnt[0+:lg_rows_lp]; + dir_ram_w_mask = '1; + dir_ram_w_data = '0; + cnt_clr = (cnt == counter_width_lp'(rows_lp-1)); + state_n = cnt_clr ? READY : INIT; + cnt_inc = ~cnt_clr; + // directory is busy and cannot accept commands + busy_o = 1'b1; + end + READY: begin + + if (r_v_i) begin + + // reset the sharers vectors for the new read; new values will be prepared for writing + // starting in the next cycle, when the first read data is valid + sharers_v_n = '0; + sharers_hits_n = '0; + sharers_ways_n = '0; + sharers_coh_states_n = e_COH_I; + + // capture inputs into registers + lce_n = lce_i; + way_n = way_i; + lru_way_n = lru_way_i; + addr_n = addr_i; + + addr_dst_gpr_n = addr_dst_gpr_i; + + r_lru_v_n = 1'b0; + + // ensure counter is reset to 0 + cnt_clr = 1'b1; + + // setup the read + dir_ram_v = 1'b1; + dir_ram_addr_n = '0; + + // initiate directory read of first row of way group + // first row will be valid on output of directory next cycle (in READ) + if (cmd_i == e_rdw_op) begin + state_n = READ_FULL; + + // setup directory ram inputs + dir_ram_addr = set_id; + + // next address to read from directory + dir_ram_addr_n = dir_ram_addr + lg_rows_lp'(tag_sets_p); + + // next cycle, the data coming out of the RAM will be valid + dir_data_o_v_n = + (num_lce_p < tag_sets_per_row_lp) + ? {'0, {num_lce_p{1'b1}}} + : '1; + + r_lru_v_n = r_lru_v_i; + + // read entry + end else if (cmd_i == e_rde_op) begin + state_n = READ_ENTRY; + + // entry read does not use LRU way, override register next value to 0 + lru_way_n = '0; + + // The address to read depends on how many rows per way group there are. + // If there is only one row per wg, then the input way group is the address. + // If there is more than one row per wg, then the input way group is the high bits + // and the rd_wg_row_select is the low bits since RDE op takes only one read (read a + // single entry from a single tag set) + dir_ram_addr = entry_row_addr; + + end + + // directory write + end else if (w_v_i) begin + r_lru_v_n = 1'b0; + + // mark sharers info as invalid after a write, since it is possible the write + // changes data in the way-group that generated the sharers vectors + sharers_v_n = '0; + + addr_n = '0; + addr_dst_gpr_n = e_opd_r0; + + state_n = READY; + dir_ram_v = 1'b1; + dir_ram_w_v = 1'b1; + + dir_ram_addr = entry_row_addr; + dir_ram_addr_n = entry_row_addr; + + if (cmd_i == e_clr_op) begin + dir_ram_w_data = '0; + dir_ram_w_mask = '1; + end else if (cmd_i == e_wde_op) begin + dir_ram_w_mask[lce_i[0]][way_i] = '1; + dir_ram_w_data[lce_i[0]][way_i].tag = addr_i[tag_offset_lp+:tag_width_p]; + dir_ram_w_data[lce_i[0]][way_i].state = coh_state_i; + end else if (cmd_i == e_wds_op) begin + dir_ram_w_mask[lce_i[0]][way_i].state = bp_coh_states_e'('1); + dir_ram_w_data[lce_i[0]][way_i].state = coh_state_i; + end + end + + end + READ_FULL: begin + // directory is busy + busy_o = 1'b1; + + // cnt should be shifted based on LOG2(tag_sets_per_row_lp) + // would require tag_sets_per_row_lp to be a power of two + for(int j = 0; j < tag_sets_per_row_lp; j++) begin + sharers_hits_n[(cnt << 1) + j] = sharers_hits[j]; + sharers_ways_n[(cnt << 1) + j] = sharers_ways[j]; + sharers_coh_states_n[(cnt << 1) + j] = sharers_coh_states[j]; + end + + // do another read if required (num_lce_p > 2 and rows_per_set_lp >= 2) + if (cnt < counter_width_lp'(rows_per_set_lp-1)) begin + dir_ram_v = 1'b1; + dir_ram_addr = dir_ram_addr_r; + dir_ram_addr_n = dir_ram_addr_r + lg_rows_lp'(tag_sets_p); + dir_data_o_v_n = (cnt == counter_width_lp'(rows_per_set_lp-2)) + ? (last_row_full_lp) + ? '1 + : 2'b01 + : '1; + end else begin + state_n = READY; + cnt_clr = 1'b1; + // sharers will be valid next cycle + sharers_v_n = 1'b1; + end + cnt_inc = ~cnt_clr; + end + READ_ENTRY: begin + busy_o = 1'b1; + sharers_hits_n[0] = (addr_r_tag == dir_row_entries[lce_r[0]][way_r].tag) + & |dir_row_entries[lce_r[0]][way_r].state; + sharers_ways_n[0] = way_r; + sharers_coh_states_n[0] = dir_row_entries[lce_r[0]][way_r].state; + sharers_v_n = 1'b1; + // output the tag in the entry so it can be stored in a register + addr_v_o = 1'b1; + addr_o = {dir_row_entries[lce_r[0]][way_r].tag, tag_offset_lp'(0)}; + addr_n = {dir_row_entries[lce_r[0]][way_r].tag, tag_offset_lp'(0)}; + state_n = READY; + end + default: begin + state_n = RESET; + end + endcase + end + + // Instantiated modules + + // Reads are synchronous, with the address latched in the current cycle, and data available next + // Writes take 1 cycle + bsg_mem_1rw_sync_mask_write_bit + #(.width_p(row_width_lp) + ,.els_p(rows_lp) + ) + directory + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.w_i(dir_ram_w_v) + ,.w_mask_i(dir_ram_w_mask) + ,.addr_i(dir_ram_addr) + ,.data_i(dir_ram_w_data) + ,.v_i(dir_ram_v) + ,.data_o(dir_row_entries) + ); + + // counter + bsg_counter_clear_up + #(.max_val_p(counter_max_lp) + ,.init_val_p(0) + ) + counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(cnt_clr) + ,.up_i(cnt_inc) + ,.count_o(cnt) + ); + + // combinational logic to determine hit, way, and state for current directory row output + bp_cce_dir_tag_checker + #(.tag_sets_per_row_p(tag_sets_per_row_lp) + ,.row_width_p(row_width_lp) + ,.assoc_p(assoc_p) + ,.tag_width_p(tag_width_p) + ) + tag_checker + (.row_i(dir_row_entries) + ,.row_v_i(dir_data_o_v_r) + ,.tag_i(addr_r_tag) + ,.sharers_hits_o(sharers_hits) + ,.sharers_ways_o(sharers_ways) + ,.sharers_coh_states_o(sharers_coh_states) + ); + + logic lru_v_lo; + logic [tag_width_p-1:0] lru_tag_lo; + bp_cce_dir_lru_extract + #(.tag_sets_per_row_p(tag_sets_per_row_lp) + ,.rows_per_set_p(rows_per_set_lp) + ,.row_width_p(row_width_lp) + ,.assoc_p(assoc_p) + ,.num_lce_p(num_lce_p) + ,.tag_width_p(tag_width_p) + ) + lru_extract + (.row_i(dir_row_entries) + ,.row_v_i(dir_data_o_v_r) + ,.row_num_i(cnt[0+:lg_rows_per_set_lp]) + ,.lce_i(lce_r) + ,.lru_way_i(lru_way_r) + ,.lru_v_o(lru_v_lo) + ,.lru_coh_state_o(lru_coh_state_o) + ,.lru_tag_o(lru_tag_lo) + ); + wire [lg_sets_lp-1:0] lru_set = addr_r[lg_block_size_in_bytes_lp +: lg_sets_lp]; + assign lru_addr_o = {lru_tag_lo, lru_set, lg_block_size_in_bytes_lp'(0)}; + assign lru_v_o = lru_v_lo & r_lru_v_r; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_dir_segment) diff --git a/designs/black-parrot/src/bp/bp_cce_dir_tag_checker.sv b/designs/black-parrot/src/bp/bp_cce_dir_tag_checker.sv new file mode 100644 index 0000000..2f1ec77 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_dir_tag_checker.sv @@ -0,0 +1,72 @@ +/** + * + * Name: + * bp_cce_dir_tag_checker.sv + * + * Description: + * This module performs the parallel tag comparison on a row of tag sets from the directory. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_dir_tag_checker + import bp_common_pkg::*; + #(parameter `BSG_INV_PARAM(tag_sets_per_row_p) + , parameter `BSG_INV_PARAM(row_width_p) + , parameter `BSG_INV_PARAM(assoc_p) + , parameter `BSG_INV_PARAM(tag_width_p) + + , localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p) + ) + ( + // input row from directory RAM + input [row_width_p-1:0] row_i + , input [tag_sets_per_row_p-1:0] row_v_i + , input [tag_width_p-1:0] tag_i + + , output logic [tag_sets_per_row_p-1:0] sharers_hits_o + , output logic [tag_sets_per_row_p-1:0][lg_assoc_lp-1:0] sharers_ways_o + , output bp_coh_states_e [tag_sets_per_row_p-1:0] sharers_coh_states_o + ); + + `declare_bp_cce_dir_entry_s(tag_width_p); + + // Directory RAM row cast + dir_entry_s [tag_sets_per_row_p-1:0][assoc_p-1:0] row; + assign row = row_i; + + // one bit per way per tag set indicating if a target block is cached in valid state + logic [tag_sets_per_row_p-1:0][assoc_p-1:0] row_hits; + + // compute hit per way per tag set + for (genvar i = 0; i < tag_sets_per_row_p; i++) begin : row_hits_tag_set + for (genvar j = 0; j < assoc_p; j++) begin : row_hits_way + assign row_hits[i][j] = row_v_i[i] & (row[i][j].tag == tag_i) & |(row[i][j].state); + end + end + + // extract way and valid bit per tag set + for (genvar i = 0; i < tag_sets_per_row_p; i++) begin : sharers_ways_gen + bsg_encode_one_hot + #(.width_p(assoc_p) + ) + row_hits_to_way_ids_and_v + (.i(row_hits[i]) + ,.addr_o(sharers_ways_o[i]) + ,.v_o(sharers_hits_o[i]) + ); + end + + // extract coherence state for tag sets that have block cached + for (genvar i = 0; i < tag_sets_per_row_p; i++) begin : sharers_states_gen + assign sharers_coh_states_o[i] = (sharers_hits_o[i]) + ? row[i][sharers_ways_o[i]].state + : e_COH_I; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_dir_tag_checker) + diff --git a/designs/black-parrot/src/bp/bp_cce_fsm.sv b/designs/black-parrot/src/bp/bp_cce_fsm.sv new file mode 100644 index 0000000..1ad7884 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_fsm.sv @@ -0,0 +1,1860 @@ +/** + * + * Name: + * bp_cce_fsm.sv + * + * Description: + * This is an FSM based CCE + * + * It has two modes of operation: + * 1. uncached only - all requests are treated as uncached + * 2. normal - requests obey coherence and cacheability properties. The following accesses are + * supported: + * - locally cached from globally cacheable memory + * - locally uncached from globally uncacheable memory + * - locally uncached from globally cacheable memory + * + * Atomics in L2/Mem will be supported in a future change. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_fsm + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Derived parameters + , localparam block_size_in_bytes_lp = (bedrock_block_width_p/8) + , localparam lg_num_lce_lp = `BSG_SAFE_CLOG2(num_lce_p) + , localparam lg_num_cce_lp = `BSG_SAFE_CLOG2(num_cce_p) + , localparam lg_block_size_in_bytes_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_lp) + , localparam num_way_groups_lp = `BSG_CDIV(cce_way_groups_p, num_cce_p) + , localparam lg_num_way_groups_lp = `BSG_SAFE_CLOG2(num_way_groups_lp) + , localparam inst_ram_addr_width_lp = `BSG_SAFE_CLOG2(num_cce_instr_ram_els_p) + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + + // maximal number of tag sets stored in the directory for all LCE types + , localparam max_tag_sets_lp = `BSG_CDIV(lce_sets_p, num_cce_p) + , localparam lg_max_tag_sets_lp = `BSG_SAFE_CLOG2(max_tag_sets_lp) + + // byte offset bits required per bedrock data channel beat + , localparam lg_bedrock_data_bytes_lp = `BSG_SAFE_CLOG2(bedrock_fill_width_p/8) + + // interface width + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam counter_max_lp = 512 + ) + (input clk_i + , input reset_i + + // Config channel + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input [bedrock_fill_width_p-1:0] lce_req_data_i + , input lce_req_v_i + , output logic lce_req_ready_and_o + + , input [lce_resp_header_width_lp-1:0] lce_resp_header_i + , input [bedrock_fill_width_p-1:0] lce_resp_data_i + , input lce_resp_v_i + , output logic lce_resp_ready_and_o + + , output logic [lce_cmd_header_width_lp-1:0] lce_cmd_header_o + , output logic [bedrock_fill_width_p-1:0] lce_cmd_data_o + , output logic lce_cmd_v_o + , input lce_cmd_ready_and_i + + // CCE-MEM Interface + // BedRock Stream protocol: ready&valid + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + ); + + // parameter checks + if (counter_max_lp < num_way_groups_lp) $error("Counter max value not large enough"); + if (counter_max_lp < max_tag_sets_lp) $error("Counter max value not large enough"); + + // Define structure variables for output queues + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + // LCE-CCE Interface structs + `bp_cast_i(bp_bedrock_lce_resp_header_s, lce_resp_header); + `bp_cast_i(bp_bedrock_lce_req_header_s, lce_req_header); + `bp_cast_o(bp_bedrock_lce_cmd_header_s, lce_cmd_header); + + bp_bedrock_lce_req_header_s fsm_req_header_li; + logic [bedrock_fill_width_p-1:0] fsm_req_data_li; + logic fsm_req_v_li, fsm_req_yumi_lo; + logic [paddr_width_p-1:0] fsm_req_addr_li; + logic fsm_req_new_li, fsm_req_critical_li, fsm_req_last_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_req_payload_width_lp) + ,.msg_stream_mask_p(lce_req_stream_mask_gp) + ,.fsm_stream_mask_p(lce_req_stream_mask_gp) + ) + lce_req_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(lce_req_header_cast_i) + ,.msg_data_i(lce_req_data_i) + ,.msg_v_i(lce_req_v_i) + ,.msg_ready_and_o(lce_req_ready_and_o) + + ,.fsm_header_o(fsm_req_header_li) + ,.fsm_data_o(fsm_req_data_li) + ,.fsm_v_o(fsm_req_v_li) + ,.fsm_yumi_i(fsm_req_yumi_lo) + ,.fsm_addr_o(fsm_req_addr_li) + ,.fsm_new_o(fsm_req_new_li) + ,.fsm_critical_o(fsm_req_critical_li) + ,.fsm_last_o(fsm_req_last_li) + ); + + bp_bedrock_lce_cmd_header_s fsm_cmd_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_cmd_data_lo; + logic fsm_cmd_v_lo, fsm_cmd_ready_then_li; + logic [paddr_width_p-1:0] fsm_cmd_addr_lo; + logic fsm_cmd_new_lo, fsm_cmd_critical_lo, fsm_cmd_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_cmd_payload_width_lp) + ,.msg_stream_mask_p(lce_cmd_stream_mask_gp) + ,.fsm_stream_mask_p(lce_cmd_stream_mask_gp) + ) + lce_cmd_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(lce_cmd_header_cast_o) + ,.msg_data_o(lce_cmd_data_o) + ,.msg_v_o(lce_cmd_v_o) + ,.msg_ready_and_i(lce_cmd_ready_and_i) + + ,.fsm_header_i(fsm_cmd_header_lo) + ,.fsm_addr_o(fsm_cmd_addr_lo) + ,.fsm_data_i(fsm_cmd_data_lo) + ,.fsm_v_i(fsm_cmd_v_lo) + ,.fsm_ready_then_o(fsm_cmd_ready_then_li) + ,.fsm_new_o(fsm_cmd_new_lo) + ,.fsm_critical_o(fsm_cmd_critical_lo) + ,.fsm_last_o(fsm_cmd_last_lo) + ); + + bp_bedrock_lce_resp_header_s fsm_resp_header_li; + logic [bedrock_fill_width_p-1:0] fsm_resp_data_li; + logic fsm_resp_v_li, fsm_resp_yumi_lo; + logic [paddr_width_p-1:0] fsm_resp_addr_li; + logic fsm_resp_new_li, fsm_resp_critical_li, fsm_resp_last_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_resp_payload_width_lp) + ,.msg_stream_mask_p(lce_resp_stream_mask_gp) + ,.fsm_stream_mask_p(lce_resp_stream_mask_gp) + ) + lce_resp_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(lce_resp_header_cast_i) + ,.msg_data_i(lce_resp_data_i) + ,.msg_v_i(lce_resp_v_i) + ,.msg_ready_and_o(lce_resp_ready_and_o) + + ,.fsm_header_o(fsm_resp_header_li) + ,.fsm_data_o(fsm_resp_data_li) + ,.fsm_v_o(fsm_resp_v_li) + ,.fsm_yumi_i(fsm_resp_yumi_lo) + ,.fsm_addr_o(fsm_resp_addr_li) + ,.fsm_new_o(fsm_resp_new_li) + ,.fsm_critical_o(fsm_resp_critical_li) + ,.fsm_last_o(fsm_resp_last_li) + ); + + // Memory Rev Stream Pump + bp_bedrock_mem_rev_header_s fsm_rev_header_li; + logic [bedrock_fill_width_p-1:0] fsm_rev_data_li; + logic fsm_rev_v_li, fsm_rev_yumi_lo; + logic [paddr_width_p-1:0] fsm_rev_addr_li; + logic fsm_rev_new_li, fsm_rev_critical_li, fsm_rev_last_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.msg_stream_mask_p(mem_rev_stream_mask_gp) + ,.fsm_stream_mask_p(mem_rev_stream_mask_gp) + ) + rev_stream_pump + (.clk_i(clk_i) + ,.reset_i(reset_i) + // from memory response input + ,.msg_header_i(mem_rev_header_i) + ,.msg_data_i(mem_rev_data_i) + ,.msg_v_i(mem_rev_v_i) + ,.msg_ready_and_o(mem_rev_ready_and_o) + // to FSM CCE + ,.fsm_header_o(fsm_rev_header_li) + ,.fsm_data_o(fsm_rev_data_li) + ,.fsm_v_o(fsm_rev_v_li) + ,.fsm_yumi_i(fsm_rev_yumi_lo) + ,.fsm_addr_o(fsm_rev_addr_li) + ,.fsm_new_o(fsm_rev_new_li) + ,.fsm_critical_o(fsm_rev_critical_li) + ,.fsm_last_o(fsm_rev_last_li) + ); + + // Memory Fwd Stream Pump + bp_bedrock_mem_fwd_header_s fsm_fwd_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_fwd_data_lo; + logic fsm_fwd_v_lo, fsm_fwd_ready_then_li; + logic [paddr_width_p-1:0] fsm_fwd_addr_lo; + logic fsm_fwd_new_lo, fsm_fwd_critical_lo, fsm_fwd_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.msg_stream_mask_p(mem_fwd_stream_mask_gp) + ,.fsm_stream_mask_p(mem_fwd_stream_mask_gp) + ) + fwd_stream_pump + (.clk_i(clk_i) + ,.reset_i(reset_i) + // to memory command output + ,.msg_header_o(mem_fwd_header_o) + ,.msg_data_o(mem_fwd_data_o) + ,.msg_v_o(mem_fwd_v_o) + ,.msg_ready_and_i(mem_fwd_ready_and_i) + // from FSM CCE + ,.fsm_header_i(fsm_fwd_header_lo) + ,.fsm_data_i(fsm_fwd_data_lo) + ,.fsm_v_i(fsm_fwd_v_lo) + ,.fsm_ready_then_o(fsm_fwd_ready_then_li) + ,.fsm_addr_o(fsm_fwd_addr_lo) + ,.fsm_new_o(fsm_fwd_new_lo) + ,.fsm_critical_o(fsm_fwd_critical_lo) + ,.fsm_last_o(fsm_fwd_last_lo) + ); + + // Config bus + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + bp_cfg_bus_s cfg_bus_cast_i; + assign cfg_bus_cast_i = cfg_bus_i; + wire cce_normal_mode_li = (cfg_bus_cast_i.cce_mode == e_cce_mode_normal); + logic cce_normal_mode_r, cce_normal_mode_n; + + // MSHR + `declare_bp_cce_mshr_s(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + bp_cce_mshr_s mshr_r, mshr_n; + + // Pending Bits + logic pending_li, pending_clear_li, pending_lo; + logic pending_w_v, pending_r_v; + logic [paddr_width_p-1:0] pending_w_addr, pending_r_addr; + // The read address always comes from the MSHR + assign pending_r_addr = mshr_r.paddr; + + // bit to tell FSM that it can't use pending bit module write port + logic pending_busy; + + // bit to tell FSM that it can't use LCE Command network because memory response is using it + logic lce_cmd_busy; + + bp_cce_pending_bits + #(.num_way_groups_p(num_way_groups_lp) // number of way groups managed in this CCE + ,.cce_way_groups_p(cce_way_groups_p) // total number of way groups in system + ,.num_cce_p(num_cce_p) + ,.paddr_width_p(paddr_width_p) + ,.addr_offset_p(lg_block_size_in_bytes_lp) + ,.cce_id_width_p(cce_id_width_p) + ) + pending_bits + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.w_v_i(pending_w_v) + ,.w_addr_i(pending_w_addr) + ,.w_addr_bypass_hash_i('0) + ,.pending_i(pending_li) + ,.clear_i(pending_clear_li) + ,.r_v_i(pending_r_v) + ,.r_addr_i(pending_r_addr) + ,.r_addr_bypass_hash_i('0) + ,.pending_o(pending_lo) + // Debug + ,.cce_id_i(cfg_bus_cast_i.cce_id) + ); + + // Directory signals + logic dir_r_v, dir_w_v; + bp_cce_inst_minor_dir_op_e dir_cmd; + logic sharers_v_lo; + logic [num_lce_p-1:0] sharers_hits_lo; + logic [num_lce_p-1:0][lce_assoc_width_p-1:0] sharers_ways_lo; + bp_coh_states_e [num_lce_p-1:0] sharers_coh_states_lo; + logic dir_lru_v_lo; + logic [paddr_width_p-1:0] dir_lru_addr_lo, dir_addr_lo; + bp_coh_states_e dir_lru_coh_state_lo; + logic dir_busy_lo; + + logic [paddr_width_p-1:0] dir_addr_li; + logic dir_addr_bypass_li; + logic [lce_id_width_p-1:0] dir_lce_li; + logic [lce_assoc_width_p-1:0] dir_way_li, dir_lru_way_li; + bp_coh_states_e dir_coh_state_li; + + // GAD signals + logic [lce_assoc_width_p-1:0] gad_req_addr_way_lo; + logic [lce_id_width_p-1:0] gad_owner_lce_lo; + logic [lce_assoc_width_p-1:0] gad_owner_lce_way_lo; + bp_coh_states_e gad_owner_coh_state_lo; + logic gad_rf_lo; + logic gad_uf_lo; + logic gad_csf_lo; + logic gad_cef_lo; + logic gad_cmf_lo; + logic gad_cof_lo; + logic gad_cff_lo; + + // Directory + bp_cce_dir + #(.bp_params_p(bp_params_p)) + directory + (.clk_i(clk_i) + ,.reset_i(reset_i) + // Inputs + ,.addr_i(dir_addr_li) + ,.addr_bypass_i(dir_addr_bypass_li) + ,.lce_i(dir_lce_li) + ,.way_i(dir_way_li) + ,.lru_way_i(mshr_r.lru_way_id) + ,.coh_state_i(dir_coh_state_li) + ,.addr_dst_gpr_i(e_opd_r0) // only used for RDE + ,.cmd_i(dir_cmd) + ,.r_v_i(dir_r_v) + ,.w_v_i(dir_w_v) + // Outputs + ,.busy_o(dir_busy_lo) + ,.sharers_v_o(sharers_v_lo) + ,.sharers_hits_o(sharers_hits_lo) + ,.sharers_ways_o(sharers_ways_lo) + ,.sharers_coh_states_o(sharers_coh_states_lo) + ,.lru_v_o(dir_lru_v_lo) + ,.lru_coh_state_o(dir_lru_coh_state_lo) + ,.lru_addr_o(dir_lru_addr_lo) + ,.addr_v_o() // only for RDE, can be left unconnected in FSM CCE + ,.addr_o() + ,.addr_dst_gpr_o() + // Debug + ,.cce_id_i(cfg_bus_cast_i.cce_id) + ); + + // GAD logic - auxiliary directory information logic + bp_cce_gad + #(.bp_params_p(bp_params_p)) + gad + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.gad_v_i(sharers_v_lo & ~dir_busy_lo) + + ,.sharers_v_i(sharers_v_lo) + ,.sharers_hits_i(sharers_hits_lo) + ,.sharers_ways_i(sharers_ways_lo) + ,.sharers_coh_states_i(sharers_coh_states_lo) + + ,.req_lce_i(mshr_r.lce_id) + ,.req_type_flag_i(mshr_r.flags.write_not_read) + ,.lru_coh_state_i(mshr_r.lru_coh_state) + ,.atomic_req_flag_i(mshr_r.flags.atomic) + ,.uncached_req_flag_i(mshr_r.flags.uncached) + + ,.req_addr_way_o(gad_req_addr_way_lo) + ,.owner_lce_o(gad_owner_lce_lo) + ,.owner_way_o(gad_owner_lce_way_lo) + ,.owner_coh_state_o(gad_owner_coh_state_lo) + ,.replacement_flag_o(gad_rf_lo) + ,.upgrade_flag_o(gad_uf_lo) + ,.cached_shared_flag_o(gad_csf_lo) + ,.cached_exclusive_flag_o(gad_cef_lo) + ,.cached_modified_flag_o(gad_cmf_lo) + ,.cached_owned_flag_o(gad_cof_lo) + ,.cached_forward_flag_o(gad_cff_lo) + ); + + // CCE PMA - LCE requests + logic req_pma_cacheable_addr_lo; + bp_cce_pma + #(.bp_params_p(bp_params_p)) + req_pma + (.paddr_i(fsm_req_header_li.addr) + ,.cacheable_addr_o(req_pma_cacheable_addr_lo) + ); + + // synopsys translate_off + always @(negedge clk_i) begin + if (~reset_i) begin + // Cacheable requests must target cacheable memory + assert(reset_i !== '0 || + !(fsm_req_v_li && ~req_pma_cacheable_addr_lo + && ((fsm_req_header_li.msg_type.req == e_bedrock_req_rd_miss) + || (fsm_req_header_li.msg_type.req == e_bedrock_req_wr_miss)) + ) + ) else + $error("CCE PMA violation - cacheable requests must target cacheable memory"); + end + end + // synopsys translate_on + + // CCE PMA - Mem responses + logic fwd_pma_cacheable_addr_lo; + bp_cce_pma + #(.bp_params_p(bp_params_p)) + fwd_pma + (.paddr_i(fsm_fwd_header_lo.addr) + ,.cacheable_addr_o(fwd_pma_cacheable_addr_lo) + ); + + logic rev_pma_cacheable_addr_lo; + bp_cce_pma + #(.bp_params_p(bp_params_p)) + rev_pma + (.paddr_i(fsm_rev_header_li.addr) + ,.cacheable_addr_o(rev_pma_cacheable_addr_lo) + ); + + enum logic [5:0] { + e_reset + , e_clear_dir + , e_uncached_only + , e_send_sync + , e_sync_ack + , e_ready + + , e_uncached_req + , e_uncached_data + , e_read_pending + , e_coherent_req + , e_read_mem_spec + , e_read_dir + , e_wait_dir_gad + + , e_write_next_state + + , e_inv_cmd + , e_inv_ack + + , e_replacement + , e_replacement_wb_resp + + , e_uc_coherent_cmd + , e_uc_coherent_resp + , e_uc_coherent_mem_fwd + + , e_upgrade_stw_cmd + + , e_transfer + , e_transfer_cmd + , e_transfer_st_cmd + , e_transfer_wb_cmd + , e_transfer_wb_resp + + , e_resolve_speculation + + , e_error + + } state_n, state_r; + + // Counter for message send/receive + logic cnt_rst; + logic [`BSG_WIDTH(1)-1:0] cnt_inc, cnt_dec; + logic [`BSG_WIDTH(num_lce_p+1)-1:0] cnt; + bsg_counter_up_down + #(.max_val_p(num_lce_p+1) + ,.init_val_p(0) + ,.max_step_p(1) + ) + counter + (.clk_i(clk_i) + ,.reset_i(reset_i | cnt_rst) + ,.up_i(cnt_inc) + ,.down_i(cnt_dec) + ,.count_o(cnt) + ); + + // General use counter + logic cnt_0_clr, cnt_0_inc; + logic [`BSG_SAFE_CLOG2(counter_max_lp+1)-1:0] cnt_0; + bsg_counter_clear_up + #(.max_val_p(counter_max_lp) + ,.init_val_p(0) + ) + counter_0 + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(cnt_0_clr) + ,.up_i(cnt_0_inc) + ,.count_o(cnt_0) + ); + + // General use counter + logic cnt_1_clr, cnt_1_inc; + logic [`BSG_SAFE_CLOG2(counter_max_lp+1)-1:0] cnt_1; + bsg_counter_clear_up + #(.max_val_p(counter_max_lp) + ,.init_val_p(0) + ) + counter_1 + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(cnt_1_clr) + ,.up_i(cnt_1_inc) + ,.count_o(cnt_1) + ); + + // memory command/response counter + logic [`BSG_WIDTH(dma_noc_max_credits_p)-1:0] mem_credit_count_lo; + bsg_flow_counter + #(.els_p(dma_noc_max_credits_p), .ready_THEN_valid_p(1)) + mem_credit_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + // memory commands consume credits + ,.v_i(fsm_fwd_v_lo & fsm_fwd_last_lo) + ,.ready_param_i(fsm_fwd_ready_then_li) + // memory responses return credits + ,.yumi_i(fsm_rev_yumi_lo & fsm_rev_last_li) + ,.count_o(mem_credit_count_lo) + ); + + wire mem_credits_empty = (mem_credit_count_lo == dma_noc_max_credits_p); + wire mem_credits_full = (mem_credit_count_lo == 0); + + // Speculative memory access management + bp_cce_spec_s spec_bits_li, spec_bits_lo; + logic spec_w_v; + logic spec_v_li, squash_v_li, fwd_mod_v_li, state_v_li; + + bp_cce_spec_bits + #(.num_way_groups_p(num_way_groups_lp) + ,.cce_way_groups_p(cce_way_groups_p) + ,.num_cce_p(num_cce_p) + ,.paddr_width_p(paddr_width_p) + ,.addr_offset_p(lg_block_size_in_bytes_lp) + ) + spec_bits + (.clk_i(clk_i) + ,.reset_i(reset_i) + + // write-port + ,.w_v_i(spec_w_v) + ,.w_addr_i(mshr_r.paddr) + ,.w_addr_bypass_hash_i('0) + + ,.spec_v_i(spec_v_li) + ,.squash_v_i(squash_v_li) + ,.fwd_mod_v_i(fwd_mod_v_li) + ,.state_v_i(state_v_li) + ,.spec_i(spec_bits_li) + + // read-port + ,.r_v_i(fsm_rev_v_li & fsm_rev_header_li.payload.speculative) + ,.r_addr_i(fsm_rev_header_li.addr) + ,.r_addr_bypass_hash_i('0) + + // output + ,.spec_o(spec_bits_lo) + ); + + // One hot of request LCE ID + logic [num_lce_p-1:0] req_lce_id_one_hot; + bsg_decode + #(.num_out_p(num_lce_p)) + req_lce_id_to_one_hot + (.i(mshr_r.lce_id[0+:lg_num_lce_lp]) + ,.o(req_lce_id_one_hot) + ); + + // One hot of owner LCE ID + logic [num_lce_p-1:0] owner_lce_id_one_hot; + bsg_decode + #(.num_out_p(num_lce_p)) + owner_lce_id_to_one_hot + (.i(mshr_r.owner_lce_id[0+:lg_num_lce_lp]) + ,.o(owner_lce_id_one_hot) + ); + + // Extract index of first bit set in sharers hits + // Provides LCE ID to send invalidation to + logic [num_lce_p-1:0] pe_sharers_r, pe_sharers_n; + logic [lg_num_lce_lp-1:0] pe_lce_id; + logic pe_v; + bsg_priority_encode + #(.width_p(num_lce_p) + ,.lo_to_hi_p(1) + ) + sharers_pri_enc + (.i(pe_sharers_r) + ,.addr_o(pe_lce_id) + ,.v_o(pe_v) + ); + + logic [num_lce_p-1:0][lce_assoc_width_p-1:0] sharers_ways_r, sharers_ways_n; + logic [num_lce_p-1:0] sharers_hits_r, sharers_hits_n; + + // Convert first index back to one hot + logic [num_lce_p-1:0] pe_lce_id_one_hot; + bsg_decode + #(.num_out_p(num_lce_p)) + pe_lce_id_to_one_hot + (.i(pe_lce_id) + ,.o(pe_lce_id_one_hot) + ); + + wire lce_resp_coh_ack_yumi = fsm_resp_v_li & (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_coh_ack) & ~pending_busy; + + // flags for cacheable requests + // transfer occurs if any cache has block in E, M, O, or F (ownerhsip states) + // and not doing an upgrade and not uncached access. + wire transfer_flag = (mshr_r.flags.cached_exclusive | mshr_r.flags.cached_modified + | mshr_r.flags.cached_owned | mshr_r.flags.cached_forward) + & ~mshr_r.flags.upgrade & ~mshr_r.flags.uncached; + // Upgrade with block in O or F in other LCE should invalidate owner. + // No need to writeback because requestor will get read/write permissions and has up-to-date block + // Upgrade flag only set if cacheable request + wire upgrade_inv_owner = mshr_r.flags.upgrade + & (mshr_r.flags.cached_owned | mshr_r.flags.cached_forward); + // invalidations occur if write request and any block in S state (shared, not owner) + // also need to invalidate owner in O or F when doing upgrade + wire inv_sharers = (~mshr_r.flags.uncached & mshr_r.flags.write_not_read & mshr_r.flags.cached_shared); + + // flags for uncached requests + // all sharers need to be invalidated, regardless of read or write request + wire uc_inv_sharers = mshr_r.flags.uncached & mshr_r.flags.cached_shared; + wire uc_inv_owner = mshr_r.flags.uncached + & (mshr_r.flags.cached_forward | mshr_r.flags.cached_exclusive + | mshr_r.flags.cached_modified | mshr_r.flags.cached_owned); + + wire invalidate_flag = inv_sharers | uc_inv_sharers | upgrade_inv_owner; + + always_comb begin + state_n = state_r; + mshr_n = mshr_r; + sharers_ways_n = sharers_ways_r; + sharers_hits_n = sharers_hits_r; + pe_sharers_n = pe_sharers_r; + cce_normal_mode_n = cce_normal_mode_r; + + // memory response stream pump + fsm_rev_yumi_lo = '0; + + // memory command stream pump + fsm_fwd_header_lo = '0; + fsm_fwd_v_lo = '0; + fsm_fwd_data_lo = '0; + + // LCE request and response input control + fsm_req_yumi_lo = '0; + fsm_resp_yumi_lo = '0; + + // LCE command output control + fsm_cmd_header_lo = '0; + fsm_cmd_header_lo.payload.src_id = cfg_bus_cast_i.cce_id; + fsm_cmd_header_lo.payload.src_did = cfg_bus_cast_i.did; + fsm_cmd_data_lo = '0; + fsm_cmd_v_lo = '0; + + // up down counter + cnt_inc = '0; + cnt_dec = '0; + cnt_rst = '0; + + cnt_1_clr = '0; + cnt_1_inc = '0; + cnt_0_clr = '0; + cnt_0_inc = '0; + + pending_li = '0; + pending_clear_li = '0; + pending_r_v = '0; + pending_w_v = '0; + pending_w_addr = '0; + + dir_r_v = '0; + dir_w_v = '0; + dir_cmd = e_rdw_op; + dir_lce_li = mshr_r.lce_id; + dir_way_li = mshr_r.way_id; + dir_lru_way_li = mshr_r.lru_way_id; + dir_addr_li = mshr_r.paddr; + dir_addr_bypass_li = '0; + dir_coh_state_li = mshr_r.next_coh_state; + + // speculative memory access + spec_w_v = '0; + spec_bits_li = '0; + spec_v_li = '0; + squash_v_li = '0; + fwd_mod_v_li = '0; + state_v_li = '0; + + // By default, pending write port is available + pending_busy = '0; + lce_cmd_busy = '0; + + // Mem Response auto-processing and forwarding to LCE Command logic + // The pending bit is written when the LCE Command header sends. + // The main FSM will stall if it wants to write to the pending bits in the same cycle. + if (fsm_rev_v_li) begin + + // Speculative access response + // Note: speculative access is only supported for cached read requests + if (fsm_rev_header_li.payload.speculative && fsm_rev_header_li.msg_type == e_bedrock_mem_rd) begin + + if (spec_bits_lo.spec) begin // speculation not resolved yet + // do nothing, wait for speculation to be resolved + // Note: this blocks memory responses behind the speculative response from being + // forwarded. However, the CCE will not move on to a new LCE request until it + // resolves the speculation for the current request. + end // speculative bit sill set + + else if (spec_bits_lo.squash) begin // speculation resolved, squash + fsm_rev_yumi_lo = fsm_rev_v_li; + + // decrement pending bit on mem response dequeue + pending_w_v = fsm_rev_yumi_lo & fsm_rev_last_li & rev_pma_cacheable_addr_lo; + pending_busy = pending_w_v; + pending_w_addr = fsm_rev_header_li.addr; + pending_li = 1'b0; + + end // squash + + else if (spec_bits_lo.fwd_mod) begin // speculation resolved, forward with modified state + // forward the header this cycle + // forward data next cycle(s) + + // inform ucode decode that this unit is using the LCE Command network + lce_cmd_busy = 1'b1; + + fsm_cmd_v_lo = fsm_cmd_ready_then_li & fsm_rev_v_li; + fsm_rev_yumi_lo = fsm_cmd_v_lo; + + // command header + fsm_cmd_header_lo.msg_type.cmd = e_bedrock_cmd_data; + fsm_cmd_header_lo.addr = fsm_rev_header_li.addr; + fsm_cmd_header_lo.size = fsm_rev_header_li.size; + + // command payload + // modify the coherence state + fsm_cmd_header_lo.payload.dst_id = fsm_rev_header_li.payload.lce_id; + fsm_cmd_header_lo.payload.way_id = fsm_rev_header_li.payload.way_id; + fsm_cmd_header_lo.payload.src_did = fsm_rev_header_li.payload.src_did; + fsm_cmd_header_lo.payload.state = bp_coh_states_e'(spec_bits_lo.state); + + // data payload + fsm_cmd_data_lo = fsm_rev_data_li; + + // decrement pending bit on lce cmd header send + pending_w_v = fsm_rev_yumi_lo & fsm_rev_last_li & rev_pma_cacheable_addr_lo; + pending_busy = pending_w_v; + pending_w_addr = fsm_cmd_header_lo.addr; + pending_li = 1'b0; + + end // fwd_mod + + else begin // speculation resolved, forward unmodified + // forward the header this cycle + // forward data next cycle(s) + + // inform ucode decode that this unit is using the LCE Command network + lce_cmd_busy = 1'b1; + + // send LCE command header, but don't ack the mem response beat since its data + // will send after the header sends. + fsm_cmd_v_lo = fsm_cmd_ready_then_li & fsm_rev_v_li; + fsm_rev_yumi_lo = fsm_cmd_v_lo; + + // command header + fsm_cmd_header_lo.msg_type.cmd = e_bedrock_cmd_data; + fsm_cmd_header_lo.addr = fsm_rev_header_li.addr; + fsm_cmd_header_lo.size = fsm_rev_header_li.size; + + // command payload + fsm_cmd_header_lo.payload.dst_id = fsm_rev_header_li.payload.lce_id; + fsm_cmd_header_lo.payload.way_id = fsm_rev_header_li.payload.way_id; + fsm_cmd_header_lo.payload.src_did = fsm_rev_header_li.payload.src_did; + fsm_cmd_header_lo.payload.state = fsm_rev_header_li.payload.state; + + // data payload + fsm_cmd_data_lo = fsm_rev_data_li; + + // decrement pending bit on lce cmd header send + pending_w_v = fsm_rev_yumi_lo & fsm_rev_last_li & rev_pma_cacheable_addr_lo; + pending_busy = pending_w_v; + pending_w_addr = fsm_rev_header_li.addr; + pending_li = 1'b0; + end // forward unmodified + + end // speculative response + + // non-speculative memory access, forward directly to LCE + else if (fsm_rev_header_li.msg_type == e_bedrock_mem_rd) begin + // forward the header this cycle + // forward data next cycle(s) + + // inform ucode decode that this unit is using the LCE Command network + lce_cmd_busy = 1'b1; + + // send LCE command header, but don't ack the mem response beat since its data + // will send after the header sends. + fsm_cmd_v_lo = fsm_cmd_ready_then_li & fsm_rev_v_li; + fsm_rev_yumi_lo = fsm_cmd_v_lo; + + // command header + fsm_cmd_header_lo.msg_type.cmd = fsm_rev_header_li.payload.uncached ? e_bedrock_cmd_uc_data : e_bedrock_cmd_data; + fsm_cmd_header_lo.addr = fsm_rev_header_li.addr; + fsm_cmd_header_lo.size = fsm_rev_header_li.size; + + // command payload + fsm_cmd_header_lo.payload.dst_id = fsm_rev_header_li.payload.lce_id; + fsm_cmd_header_lo.payload.way_id = fsm_rev_header_li.payload.way_id; + fsm_cmd_header_lo.payload.src_did = fsm_rev_header_li.payload.src_did; + fsm_cmd_header_lo.payload.state = fsm_rev_header_li.payload.state; + + // data payload + fsm_cmd_data_lo = fsm_rev_data_li; + + // decrement pending bit on mem response dequeue (same as lce cmd send) + pending_w_v = fsm_rev_yumi_lo & fsm_rev_last_li & rev_pma_cacheable_addr_lo; + pending_busy = pending_w_v; + pending_w_addr = fsm_rev_header_li.addr; + pending_li = 1'b0; + end // rd, wr miss from LCE + + // non-speculative store response from memory + else if (fsm_rev_header_li.msg_type == e_bedrock_mem_wr) begin + // If the uncached bit is set, this response is to an uncached store + // and we need to forward an uc_st_done to the LCE. + // Otherwise, this response came from a writeback and is sunk at the CCE. + if (fsm_rev_header_li.payload.uncached) begin + // block LCE command network + lce_cmd_busy = 1'b1; + + // handshaking + // r&v for LCE command header + // valid->yumi for mem response header + fsm_cmd_v_lo = fsm_cmd_ready_then_li & fsm_rev_v_li; + fsm_rev_yumi_lo = fsm_cmd_v_lo; + + // command header + fsm_cmd_header_lo.msg_type.cmd = e_bedrock_cmd_uc_st_done; + fsm_cmd_header_lo.addr = fsm_rev_header_li.addr; + // leave size as '0 equivalent, no data in this message + + // command payload + fsm_cmd_header_lo.payload.dst_id = fsm_rev_header_li.payload.lce_id; + fsm_cmd_header_lo.payload.src_did = fsm_rev_header_li.payload.src_did; + end else begin + fsm_rev_yumi_lo = fsm_rev_v_li; + end + + // decrement pending bit on last mem response transfer if targeting L1 cacheable address + // cce_normal_mode accounted for by rev_pma + pending_w_v = fsm_rev_yumi_lo & fsm_rev_last_li & rev_pma_cacheable_addr_lo; + pending_busy = pending_w_v; + pending_w_addr = fsm_rev_header_li.addr; + pending_li = 1'b0; + + end // wr + + end // mem_rev handling + + // Dequeue coherence ack when it arrives + // Does not conflict with other dequeues of LCE Response + // Decrements pending bit on arrival, so arbitrate with memory ports for access + if (fsm_resp_v_li & (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_coh_ack) & ~pending_busy) begin + fsm_resp_yumi_lo = fsm_resp_v_li; + // inform FSM that pending bit is being used + pending_w_v = fsm_resp_yumi_lo & fsm_resp_last_li; + pending_busy = pending_w_v; + pending_w_addr = fsm_resp_header_li.addr; + pending_li = 1'b0; + end + + // FSM + case (state_r) + e_reset: begin + state_n = e_clear_dir; + cce_normal_mode_n = 1'b0; + cnt_rst = 1'b1; + cnt_0_clr = 1'b1; + cnt_1_clr = 1'b1; + end // e_reset + + // After reset, clear the directory, then operate based on the current operating mode + // If normal mode is set, perform the sync sequence with the LCEs + e_clear_dir: begin + dir_w_v = 1'b1; + dir_cmd = e_clr_op; + + // increment through maximal number of tag sets (outer loop) and all LCE's (inner loop) + // tag set number is cnt_0 + // LCE is cnt_1 + + // bypass the address hashing in bp_cce_dir_segment, using dir_addr_li directly as the + // tag set number for the operation + dir_addr_bypass_li = 1'b1; + dir_addr_li = '0; + dir_addr_li[0+:lg_max_tag_sets_lp] = cnt_0[0+:lg_max_tag_sets_lp]; + dir_lce_li = cnt_1[0+:lce_id_width_p]; + + // inner loop - LCE + // clear the LCE counter back to 0 after reaching max LCE ID to reset for next tag set + cnt_1_clr = (cnt_1 == (num_lce_p-1)); + // increment the LCE counter if not clearing + cnt_1_inc = ~cnt_1_clr; + + // outer loop - tag set + // cnt_0 clears after all LCEs in the last tag set have been cleared + cnt_0_clr = (cnt_0 == (max_tag_sets_lp-1)) & cnt_1_clr; + // move to next tag set when cnt_1 clears back to LCE 0 + // don't increment when exiting this state (and clearing the counter) + cnt_0_inc = cnt_1_clr & ~cnt_0_clr; + + // Stay in e_clear_dir until cnt_0_clr goes high + // Next state depends on the CCE mode, as set by config bus + state_n = cnt_0_clr + ? cce_normal_mode_li + ? e_send_sync + : e_uncached_only + : e_clear_dir; + + end // e_clear_dir + + // Uncached only mode + // This mode supports uncached rd/wr operations + // All of memory is treated as globally uncacheable in this mode + e_uncached_only: begin + + // clear the MSHR + mshr_n = '0; + // clear the counters + cnt_0_clr = 1'b1; + cnt_1_clr = 1'b1; + cnt_rst = 1'b1; + + state_n = e_uncached_only; + + // transition to normal/coherent operation as soon as config bus indicates + if (cce_normal_mode_li) begin + state_n = e_send_sync; + + // only issue memory command if memory credit is available + // only process uncached requests + // cached requests will stall on the input port + // cached requests not allowed, go to error state and stall + end else if (fsm_req_v_li + & ((fsm_req_header_li.msg_type.req == e_bedrock_req_rd_miss) + | (fsm_req_header_li.msg_type.req == e_bedrock_req_wr_miss))) begin + state_n = e_error; + + // uncached store + end else if (fsm_req_v_li & (fsm_req_header_li.msg_type.req == e_bedrock_req_uc_wr)) begin + // first beat of memory command must include data + // handshake is r&v on both LCE request data and memory command stream, and + // valid->yumi on LCE request header + fsm_fwd_v_lo = fsm_fwd_ready_then_li & fsm_req_v_li & ~mem_credits_empty; + fsm_req_yumi_lo = fsm_fwd_v_lo & fsm_fwd_last_lo; + + // form message + fsm_fwd_header_lo.addr = fsm_req_header_li.addr; + fsm_fwd_header_lo.size = fsm_req_header_li.size; + fsm_fwd_header_lo.msg_type.fwd = e_bedrock_mem_wr; + fsm_fwd_header_lo.subop = fsm_req_header_li.subop; + fsm_fwd_header_lo.payload.lce_id = fsm_req_header_li.payload.src_id; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + fsm_fwd_header_lo.payload.uncached = 1'b1; + fsm_fwd_data_lo = fsm_req_data_li; + end // uncached store + + // uncached load + else if (fsm_req_v_li & (fsm_req_header_li.msg_type.req == e_bedrock_req_uc_rd)) begin + // uncached load has no data + fsm_fwd_v_lo = fsm_fwd_ready_then_li & fsm_req_v_li & ~mem_credits_empty; + fsm_req_yumi_lo = fsm_fwd_v_lo & fsm_fwd_last_lo; + + fsm_fwd_header_lo.addr = fsm_req_header_li.addr; + fsm_fwd_header_lo.size = fsm_req_header_li.size; + fsm_fwd_header_lo.payload.lce_id = fsm_req_header_li.payload.src_id; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + fsm_fwd_header_lo.payload.uncached = 1'b1; + fsm_fwd_header_lo.msg_type.fwd = e_bedrock_mem_rd; + + end // uncached load + + // TODO: add amo support here + + end // e_uncached_only + + e_send_sync: begin + // register that normal mode is active (can still be doing sync) and all outstanding + // uncached accesses are complete + cce_normal_mode_n = (~cce_normal_mode_r & mem_credits_full) + ? 1'b1 + : cce_normal_mode_r; + + // after first entering e_send_sync from e_uncached_only, wait for all oustanding uncached + // accesses to complete before sending first sync commnad + if (mem_credits_full & ~lce_cmd_busy) begin + fsm_cmd_v_lo = fsm_cmd_ready_then_li; + + fsm_cmd_header_lo.msg_type.cmd = e_bedrock_cmd_sync; + fsm_cmd_header_lo.payload.dst_id[0+:lg_num_lce_lp] = cnt_1[0+:lg_num_lce_lp]; + + cnt_1_inc = fsm_cmd_v_lo; + state_n = cnt_1_inc ? e_sync_ack : e_send_sync; + + end + end // e_send_sync + + e_sync_ack: begin + if (~lce_resp_coh_ack_yumi) begin + fsm_resp_yumi_lo = fsm_resp_v_li; + state_n = (fsm_resp_v_li) + ? (cnt_0 == (num_lce_p-1)) + ? e_ready + : e_send_sync + : e_sync_ack; + state_n = (fsm_resp_v_li & (fsm_resp_header_li.msg_type.resp != e_bedrock_resp_sync_ack)) + ? e_error + : state_n; + cnt_0_clr = (state_n == e_ready); + cnt_0_inc = fsm_resp_v_li & ~cnt_0_clr; + cnt_1_clr = (state_n == e_ready); + end + end // e_sync_ack + + e_ready: begin + // clear the MSHR + mshr_n = '0; + // clear the ack counter + cnt_0_clr = 1'b1; + cnt_1_clr = 1'b1; + cnt_rst = 1'b1; + + if (fsm_req_v_li) begin + mshr_n.lce_id = fsm_req_header_li.payload.src_id; + mshr_n.src_did = fsm_req_header_li.payload.src_did; + state_n = e_error; + // cached request + if (fsm_req_header_li.msg_type.req == e_bedrock_req_rd_miss + | fsm_req_header_li.msg_type.req == e_bedrock_req_wr_miss) begin + + mshr_n.paddr = fsm_req_header_li.addr; + mshr_n.msg_size = fsm_req_header_li.size; + mshr_n.lru_way_id = fsm_req_header_li.payload.lru_way_id; + mshr_n.flags.write_not_read = (fsm_req_header_li.msg_type.req == e_bedrock_req_wr_miss); + mshr_n.flags.non_exclusive = fsm_req_header_li.payload.non_exclusive; + + // query PMA for coherence property - it is a violation for a cached request + // to be incoherent. + mshr_n.flags.cacheable_address = req_pma_cacheable_addr_lo; + + state_n = ~req_pma_cacheable_addr_lo + ? e_error + : e_read_pending; + + // uncached request + end else if (fsm_req_header_li.msg_type.req == e_bedrock_req_uc_rd + | fsm_req_header_li.msg_type.req == e_bedrock_req_uc_wr) begin + + mshr_n.paddr = fsm_req_header_li.addr; + mshr_n.msg_size = fsm_req_header_li.size; + mshr_n.msg_subop = fsm_req_header_li.subop; + mshr_n.flags.uncached = 1'b1; + mshr_n.flags.write_not_read = (fsm_req_header_li.msg_type.req == e_bedrock_req_uc_wr); + + // query PMA for coherence property + // uncached requests can be made to coherent or incoherent memory regions + mshr_n.flags.cacheable_address = req_pma_cacheable_addr_lo; + + // a coherent, but uncached request must serialize with other coherent operations + // using the pending bits + state_n = req_pma_cacheable_addr_lo + ? e_read_pending + : e_uncached_req; + + // TODO: handle amo requests here with else if block on msg_type + + end else begin + state_n = e_error; + end + end // fsm_req_v_li + end // e_ready + + // process uncached request + e_uncached_req: begin + + // uncached store + if (mshr_r.flags.write_not_read) begin + // first beat of memory command must include data + // handshake is r&v on both LCE request data and memory command stream, and + // valid->yumi on LCE request header + fsm_fwd_v_lo = fsm_fwd_ready_then_li & fsm_req_v_li & ~mem_credits_empty; + fsm_req_yumi_lo = fsm_fwd_v_lo; + + // form message + fsm_fwd_header_lo.addr = mshr_r.paddr; + fsm_fwd_header_lo.size = mshr_r.msg_size; + fsm_fwd_header_lo.msg_type.fwd = e_bedrock_mem_wr; + fsm_fwd_header_lo.subop = mshr_r.msg_subop; + fsm_fwd_header_lo.payload.lce_id = mshr_r.lce_id; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + fsm_fwd_header_lo.payload.uncached = 1'b1; + fsm_fwd_data_lo = fsm_req_data_li; + + // if mem command is acked, check if stream is done or not to determine if need to + // send additional data. If command is not acked, try again next cycle. + state_n = (fsm_req_yumi_lo & fsm_req_last_li) + ? e_ready + : e_uncached_req; + + end // uncached store + + // uncached load + else begin + // uncached load has no data + fsm_fwd_v_lo = fsm_fwd_ready_then_li & fsm_req_v_li & ~mem_credits_empty; + fsm_req_yumi_lo = fsm_fwd_v_lo & fsm_fwd_last_lo; + + fsm_fwd_header_lo.addr = mshr_r.paddr; + fsm_fwd_header_lo.size = mshr_r.msg_size; + fsm_fwd_header_lo.msg_type.fwd = e_bedrock_mem_rd; + fsm_fwd_header_lo.payload.lce_id = mshr_r.lce_id; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + fsm_fwd_header_lo.payload.uncached = 1'b1; + + state_n = fsm_req_yumi_lo ? e_ready : e_uncached_req; + + end // uncached load + + end // e_uncached_req + + // process requests that need coherence/serialization of the pending bits + // the request can be uncached or uncached + e_read_pending: begin + pending_r_v = 1'b1; + state_n = (pending_lo) + ? e_read_pending + : e_coherent_req; + end // e_read_pending + + // Coherent/cacheable memory space has three request types: + // 1. normal, cached request + // 2. uncached request + // 3. amo request + // only normal, cached requests will issue a speculative memory read + e_coherent_req: begin + if (fsm_req_v_li & ~pending_busy) begin + // write the pending bit if not amo or uncached to coherent memory + // because those ops do not send coh_ack back to CCE after request completes + pending_w_v = ~(mshr_r.flags.atomic | mshr_r.flags.uncached); + pending_w_addr = fsm_req_header_li.addr; + pending_li = 1'b1; + + // skip speculative memory access if amo/uncached + state_n = (mshr_r.flags.atomic | mshr_r.flags.uncached) + ? e_read_dir + : e_read_mem_spec; + + // only dequeue the request now if it is a normal cached request + fsm_req_yumi_lo = ~(mshr_r.flags.atomic | mshr_r.flags.uncached); + + end else begin + // pending bit write port is busy, stay in e_ready state and try to consume request + // next cycle + state_n = e_coherent_req; + end + end // e_coherent_req + + e_read_mem_spec: begin + // Mem Cmd needs to write pending bit, so only send if Mem Resp / LCE Cmd is not + // writing the pending bit + if (~pending_busy) begin + // handshake is r&v + fsm_fwd_v_lo = fsm_fwd_ready_then_li & ~mem_credits_empty; + fsm_fwd_header_lo.msg_type.fwd = e_bedrock_mem_rd; + fsm_fwd_header_lo.addr = mshr_r.paddr; + fsm_fwd_header_lo.size = mshr_r.msg_size; + fsm_fwd_header_lo.payload.lce_id = mshr_r.lce_id; + fsm_fwd_header_lo.payload.way_id = mshr_r.lru_way_id; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + // speculatively issue request for E state + fsm_fwd_header_lo.payload.state = e_COH_E; + fsm_fwd_header_lo.payload.speculative = 1'b1; + + // set the spec bit and clear all other bits for this entry + spec_w_v = fsm_fwd_v_lo; + spec_v_li = 1'b1; + squash_v_li = 1'b1; + fwd_mod_v_li = 1'b1; + state_v_li = 1'b1; + spec_bits_li.spec = 1'b1; + spec_bits_li.squash = 1'b0; + spec_bits_li.fwd_mod = 1'b0; + spec_bits_li.state = e_COH_I; + + // write spec bit on first beat + pending_w_v = fsm_fwd_v_lo & fsm_fwd_new_lo & fwd_pma_cacheable_addr_lo; + pending_li = 1'b1; + pending_w_addr = mshr_r.paddr; + + state_n = fsm_fwd_v_lo ? e_read_dir : e_read_mem_spec; + end + + end // e_read_mem_spec + + e_read_dir: begin + // initiate the directory read + // At the earliest, data will be valid in the next cycle + dir_r_v = 1'b1; + dir_addr_li = mshr_r.paddr; + dir_cmd = e_rdw_op; + dir_lce_li = mshr_r.lce_id; + dir_lru_way_li = mshr_r.lru_way_id; + state_n = e_wait_dir_gad; + end // e_read_dir + + e_wait_dir_gad: begin + + // capture LRU outputs when they appear + if (dir_lru_v_lo) begin + mshr_n.lru_paddr = dir_lru_addr_lo; + mshr_n.lru_coh_state = dir_lru_coh_state_lo; + end + + if (sharers_v_lo) begin + sharers_ways_n = sharers_ways_lo; + sharers_hits_n = sharers_hits_lo; + end + + if (sharers_v_lo & ~dir_busy_lo) begin + + mshr_n.way_id = gad_req_addr_way_lo; + + mshr_n.flags.replacement = gad_rf_lo; + mshr_n.flags.upgrade = gad_uf_lo; + mshr_n.flags.cached_shared = gad_csf_lo; + mshr_n.flags.cached_exclusive = gad_cef_lo; + mshr_n.flags.cached_modified = gad_cmf_lo; + mshr_n.flags.cached_owned = gad_cof_lo; + mshr_n.flags.cached_forward = gad_cff_lo; + + mshr_n.owner_lce_id = gad_owner_lce_lo; + mshr_n.owner_way_id = gad_owner_lce_way_lo; + mshr_n.owner_coh_state = gad_owner_coh_state_lo; + + // determine next state for MOESIF protocol + // atomic or uncached requests to coherent memory will set block to Invalid if it is + // present in the requesting LCE + mshr_n.next_coh_state = + (mshr_r.flags.atomic | mshr_r.flags.uncached) + ? e_COH_I + : (mshr_r.flags.write_not_read) + ? e_COH_M + : (mshr_r.flags.non_exclusive | gad_csf_lo | gad_cef_lo + | gad_cmf_lo | gad_cof_lo | gad_cff_lo) + ? e_COH_S + : e_COH_E; + + state_n = e_write_next_state; + end + + end // e_wait_dir_gad + + e_write_next_state: begin + // writing to the directory will make the sharers_v_lo signal go low, but in this FSM + // CCE we know that the sharers vectors are still valid in the state we need from the + // previous read, so we perform the coherence state update for the requesting LCE anyway + + dir_lce_li = mshr_r.lce_id; + dir_addr_li = mshr_r.paddr; + dir_coh_state_li = mshr_r.next_coh_state; + + // upgrade detected, only change state + if (mshr_r.flags.upgrade) begin + dir_w_v = 1'b1; + dir_cmd = e_wds_op; + dir_way_li = mshr_r.way_id; + + // amo or uncached to coherent memory + // only write directory if replacement flag is set indicating the requsting LCE has + // the block cached already + end else if (mshr_r.flags.atomic | mshr_r.flags.uncached) begin + dir_w_v = mshr_r.flags.replacement; + dir_cmd = e_wds_op; + // the block, if cached at the LCE, is in the way indicated by the way_id field of + // the MSHR as produced by the GAD module + dir_way_li = mshr_r.way_id; + + // normal requests, write tag and state + end else begin + dir_w_v = 1'b1; + dir_cmd = e_wde_op; + dir_way_li = mshr_r.lru_way_id; + end + + // Ordering of coherence actions: + // Replacement, if needed + // - also set if amo or uncached to coherent memory and requesting LCE needs block + // - invalidated and (possibly) written back + // Invalidations, if needed + // Upgrade, Transfer, or Memory access (resolve speculative access) + state_n = + (mshr_r.flags.replacement) + ? e_replacement + : (invalidate_flag) + ? e_inv_cmd + : (mshr_r.flags.atomic | mshr_r.flags.uncached) + ? e_uc_coherent_cmd + : (mshr_r.flags.upgrade) + ? e_upgrade_stw_cmd + : (transfer_flag) + ? e_transfer + : e_resolve_speculation; + + // setup required state for sending invalidations + // only if next state is invalidations (i.e., not doing a replacement) + if (~mshr_r.flags.replacement & invalidate_flag) begin + // don't invalidate the requesting LCE + pe_sharers_n = sharers_hits_r & ~req_lce_id_one_hot; + // if doing a transfer, also remove owner LCE since transfer + // routine will take care of setting owner into correct new state + pe_sharers_n = (transfer_flag | uc_inv_owner) + ? pe_sharers_n & ~owner_lce_id_one_hot + : pe_sharers_n; + cnt_rst = 1'b1; + end + + end // e_write_next_state + + e_replacement: begin + // Send replacement writeback command if LCE Cmd port is free, else try again next cycle + if (~lce_cmd_busy) begin + fsm_cmd_v_lo = fsm_cmd_ready_then_li; + + // set state to invalid and writeback + fsm_cmd_header_lo.msg_type.cmd = e_bedrock_cmd_st_wb; + // for an uc/amo request, the mshr way_id field indicates the way in which the requesting + // LCE's copy of the cache block is stored at the LCE + if (mshr_r.flags.atomic | mshr_r.flags.uncached) begin + fsm_cmd_header_lo.payload.way_id = mshr_r.way_id; + fsm_cmd_header_lo.addr = mshr_r.paddr; + end else begin + fsm_cmd_header_lo.payload.way_id = mshr_r.lru_way_id; + fsm_cmd_header_lo.addr = mshr_r.lru_paddr; + end + + fsm_cmd_header_lo.payload.dst_id = mshr_r.lce_id; + // Note: this state must be e_COH_I to properly handle amo or uncached access to + // coherent memory that requires invalidating the requesting LCE if it has the block + fsm_cmd_header_lo.payload.state = e_COH_I; + + state_n = fsm_cmd_v_lo + ? e_replacement_wb_resp + : e_replacement; + end + end // e_replacement + + e_replacement_wb_resp: begin + if (fsm_resp_v_li) begin + if (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_null_wb) begin + fsm_resp_yumi_lo = fsm_resp_v_li; + // replacement done, not an upgrade, so either do invalidations, transfer, or resolve + // the speculative memory access + state_n = (invalidate_flag) + ? e_inv_cmd + : (mshr_r.flags.atomic | mshr_r.flags.uncached) + ? e_uc_coherent_cmd + : (transfer_flag) + ? e_transfer + : e_resolve_speculation; + + // clear the replacement flag + mshr_n.flags.replacement = 1'b0; + + // setup required state for sending invalidations + if (invalidate_flag) begin + // don't invalidate the requesting LCE + pe_sharers_n = sharers_hits_r & ~req_lce_id_one_hot; + // if doing a transfer, also remove owner LCE since transfer + // routine will take care of setting owner into correct new state + pe_sharers_n = (transfer_flag | uc_inv_owner) + ? pe_sharers_n & ~owner_lce_id_one_hot + : pe_sharers_n; + cnt_rst = 1'b1; + end + + end + else if ((fsm_resp_header_li.msg_type.resp == e_bedrock_resp_wb) & ~pending_busy & ~mem_credits_empty) begin + // Mem Data Cmd needs to write pending bit, so only send if Mem Data Resp / LCE Data Cmd is + // not writing the pending bit. Mem command also requires a credit, so only proceed if + // there is at least one credit availabe. + + // r&v on mem cmd header + // v->y on lce resp header, but wait to dequeue until last data beat sends + // r&v on lce resp data + + // send memory command if data is valid (header already guaranteed valid) + fsm_fwd_v_lo = fsm_fwd_ready_then_li & fsm_resp_v_li; + fsm_resp_yumi_lo = fsm_fwd_v_lo; + + fsm_fwd_header_lo.msg_type = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = fsm_resp_header_li.addr; + fsm_fwd_header_lo.size = fsm_resp_header_li.size; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + fsm_fwd_header_lo.payload.lce_id = mshr_r.lce_id; + fsm_fwd_header_lo.payload.way_id = '0; + fsm_fwd_data_lo = fsm_resp_data_li; + + // set the pending bit on first beat + pending_w_v = fsm_fwd_v_lo & fsm_fwd_new_lo & fwd_pma_cacheable_addr_lo; + pending_li = 1'b1; + pending_w_addr = fsm_resp_header_li.addr; + + // clear the replacement flag + mshr_n.flags.replacement = 1'b0; + + // setup required state for sending invalidations + if (fsm_fwd_v_lo & fsm_fwd_last_lo & invalidate_flag) begin + // don't invalidate the requesting LCE + pe_sharers_n = sharers_hits_r & ~req_lce_id_one_hot; + // if doing a transfer, also remove owner LCE since transfer + // routine will take care of setting owner into correct new state + pe_sharers_n = (transfer_flag | uc_inv_owner) + ? pe_sharers_n & ~owner_lce_id_one_hot + : pe_sharers_n; + cnt_rst = 1'b1; + end + + // send remaining beats + state_n = (fsm_fwd_v_lo & fsm_fwd_last_lo) + ? (invalidate_flag) + ? e_inv_cmd + : (transfer_flag) + ? e_transfer + : e_resolve_speculation + : e_replacement_wb_resp; + end // wb & pending bit available + end // fsm_resp_v_li + end // e_replacement_wb_resp + + e_inv_cmd: begin + + // only send invalidation if priority encode has valid output + // this indicates the sharers vector has a valid bit set + if (pe_v) begin + if (~lce_cmd_busy) begin + + fsm_cmd_v_lo = fsm_cmd_ready_then_li; + fsm_cmd_header_lo.msg_type.cmd = e_bedrock_cmd_inv; + fsm_cmd_header_lo.addr = mshr_r.paddr; + + // destination and way come from sharers information + fsm_cmd_header_lo.payload.dst_id[0+:lg_num_lce_lp] = pe_lce_id; + fsm_cmd_header_lo.payload.way_id = sharers_ways_r[pe_lce_id]; + + // message sent, increment count, write directory, clear bit for the destination LCE + cnt_inc = fsm_cmd_v_lo & fsm_cmd_new_lo; + dir_w_v = cnt_inc; + dir_cmd = e_wds_op; + dir_addr_li = mshr_r.paddr; + dir_lce_li = '0; + dir_lce_li[0+:lg_num_lce_lp] = pe_lce_id; + dir_way_li = sharers_ways_r[pe_lce_id]; + dir_coh_state_li = e_COH_I; + + // update sharers hit vector to feed back to priority encode module + pe_sharers_n = dir_w_v + ? pe_sharers_r & ~pe_lce_id_one_hot + : pe_sharers_r; + + // move to response state if none of the sharer bits are set, indicating + // that the last command is sending this cycle + if (pe_sharers_n == '0) begin + state_n = e_inv_ack; + end + end else begin + // could not send message, don't clear bit for first sharer + pe_sharers_n = pe_sharers_r; + end + end // pe_v + + // dequeue responses as they arrive + if (fsm_resp_v_li & (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_inv_ack)) begin + fsm_resp_yumi_lo = fsm_resp_v_li; + cnt_dec = fsm_resp_yumi_lo; + end + end // e_inv_cmd + + e_inv_ack: begin + if (cnt == '0) begin + state_n = (mshr_r.flags.atomic | mshr_r.flags.uncached) + ? e_uc_coherent_cmd + : (mshr_r.flags.upgrade) + ? e_upgrade_stw_cmd + : (transfer_flag) + ? e_transfer + : e_resolve_speculation; + + end else begin + // dequeue responses as they arrive + if (fsm_resp_v_li & (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_inv_ack)) begin + fsm_resp_yumi_lo = fsm_resp_v_li; + cnt_dec = fsm_resp_yumi_lo; + if (cnt == 'd1) begin + state_n = (mshr_r.flags.atomic | mshr_r.flags.uncached) + ? e_uc_coherent_cmd + : (mshr_r.flags.upgrade) + ? e_upgrade_stw_cmd + : (transfer_flag) + ? e_transfer + : e_resolve_speculation; + end // cnt == 'd1 + end // inv ack + end // else + end // e_inv_ack + + // Process uncached request to coherent memory space + e_uc_coherent_cmd: begin + // at this point for amo/uncached request to coherent memory, the requesting LCE + // has had block invalidated and written back if needed. All sharers (COH_S) blocks were + // also invalidated. + + // now, if an owner has block it needs to be invalidated and written back (if required) + if (uc_inv_owner) begin + if (~lce_cmd_busy) begin + fsm_cmd_v_lo = fsm_cmd_ready_then_li; + + fsm_cmd_header_lo.addr = mshr_r.paddr; + fsm_cmd_header_lo.payload.dst_id = mshr_r.owner_lce_id; + fsm_cmd_header_lo.payload.way_id = mshr_r.owner_way_id; + fsm_cmd_header_lo.payload.state = e_COH_I; + + // either invalidate or set tag and writeback + // if owner is in F state, block is clean, so only need to invalidate + // else, block in E, M, or O, need to invalidate and writeback + fsm_cmd_header_lo.msg_type.cmd = mshr_r.flags.cached_forward + ? e_bedrock_cmd_inv + : e_bedrock_cmd_st_wb; + + // update state of owner in directory + dir_w_v = fsm_cmd_v_lo; + dir_cmd = e_wds_op; + dir_addr_li = mshr_r.paddr; + dir_lce_li = mshr_r.owner_lce_id; + dir_way_li = mshr_r.owner_way_id; + dir_coh_state_li = e_COH_I; + + state_n = dir_w_v + ? e_uc_coherent_resp + : e_uc_coherent_cmd; + end // ~lce_cmd_busy + // no other LCE is owner, transfer flag not set + end else begin + state_n = e_uc_coherent_mem_fwd; + end + end // e_uc_coherent_cmd + + // amo/uc wait for replacement writeback or invalidation ack if sent + e_uc_coherent_resp: begin + if (fsm_resp_v_li) begin + if (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_wb & ~pending_busy & ~mem_credits_empty) begin + if (~pending_busy) begin + // Mem Data Cmd needs to write pending bit, so only send if Mem Data Resp / LCE Data Cmd is + // not writing the pending bit + // r&v on mem cmd header + // v->y on lce resp header + // r&v on lce resp data + fsm_fwd_v_lo = fsm_fwd_ready_then_li & fsm_resp_v_li; + fsm_resp_yumi_lo = fsm_fwd_v_lo; + + fsm_fwd_header_lo.msg_type.fwd = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = fsm_resp_header_li.addr; + fsm_fwd_header_lo.size = fsm_resp_header_li.size; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + fsm_fwd_header_lo.payload.lce_id = mshr_r.lce_id; + fsm_fwd_data_lo = fsm_resp_data_li; + + // set the pending bit on first beat + pending_w_v = fsm_fwd_v_lo & fsm_fwd_new_lo & fwd_pma_cacheable_addr_lo; + pending_li = 1'b1; + pending_w_addr = fsm_resp_header_li.addr; + + state_n = (fsm_resp_yumi_lo & fsm_resp_last_li) + ? e_uc_coherent_mem_fwd + : e_uc_coherent_resp; + + end + end else if (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_null_wb) begin + fsm_resp_yumi_lo = fsm_resp_v_li; + state_n = e_uc_coherent_mem_fwd; + end else if (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_inv_ack) begin + fsm_resp_yumi_lo = fsm_resp_v_li; + state_n = e_uc_coherent_mem_fwd; + end + end + + end // e_uc_coherent_resp + + // amo/uc after inv_ack/wb_response, issue op to memory + // writes pending bit + e_uc_coherent_mem_fwd: begin + if (~pending_busy & ~mem_credits_empty) begin + // r&v on mem cmd header + // v->y on lce req header + // r&v on lce req data + fsm_fwd_v_lo = fsm_fwd_ready_then_li & fsm_req_v_li; + fsm_req_yumi_lo = fsm_fwd_v_lo; + + // set message type based on request message type + unique case (fsm_req_header_li.msg_type.req) + e_bedrock_req_uc_wr: fsm_fwd_header_lo.msg_type = e_bedrock_mem_wr; + e_bedrock_req_uc_amo: fsm_fwd_header_lo.msg_type = e_bedrock_mem_amo; + // e_bedrock_req_uc_rd: + default: fsm_fwd_header_lo.msg_type = e_bedrock_mem_rd; + endcase + // uncached/amo address must be aligned appropriate to the request size + // in the LCE request (which is stored in the MSHR) + fsm_fwd_header_lo.subop = mshr_r.msg_subop; + fsm_fwd_header_lo.addr = mshr_r.paddr; + fsm_fwd_header_lo.size = mshr_r.msg_size; + // TODO: uncomment/modify when implementing atomics + //fsm_fwd_header_lo.amo_no_return = mshr_r.flags.atomic_no_return; + fsm_fwd_header_lo.payload.lce_id = mshr_r.lce_id; + fsm_fwd_header_lo.payload.way_id = '0; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + // this op is uncached in LCE for both amo or uncached requests + fsm_fwd_header_lo.payload.uncached = 1'b1; + fsm_fwd_data_lo = fsm_req_data_li; + + // set the pending bit on first beat + pending_w_v = fsm_fwd_v_lo & fsm_fwd_new_lo & fwd_pma_cacheable_addr_lo; + pending_li = 1'b1; + pending_w_addr = mshr_r.paddr; + + state_n = (fsm_req_yumi_lo & fsm_req_last_li) + ? e_ready + : e_uc_coherent_mem_fwd; + + end + + end // e_uc_coherent_mem_fwd + + e_transfer: begin + // Transfer required, three options: + // 1. transfer: read request to block in O or F state + // 2. set state and transfer: read request to block in O or write request to E, M, O, or F + // 3. set state, transfer, writeback: read request, block in E + if (~lce_cmd_busy) begin + fsm_cmd_v_lo = fsm_cmd_ready_then_li; + + fsm_cmd_header_lo.payload.dst_id = mshr_r.owner_lce_id; + fsm_cmd_header_lo.payload.way_id = mshr_r.owner_way_id; + + // note: transfer command causes a block-sized transfer from one LCE to another. + // the msg_size field is not set to the block size since the transfer command itself + // carries no data. The LCE sets the size of the data command it sends to the block size. + fsm_cmd_header_lo.msg_type.cmd = mshr_r.flags.write_not_read | mshr_r.flags.cached_modified + ? e_bedrock_cmd_st_tr + : mshr_r.flags.cached_owned | mshr_r.flags.cached_forward + ? e_bedrock_cmd_tr + // transfer & not cached in M, O, or F -> cached in E + : e_bedrock_cmd_st_tr_wb; + + fsm_cmd_header_lo.addr = mshr_r.paddr; + + // either Invalidate or Downgrade Owner, depending on request type + // write request invalidates owner (can only have 1 writer!) + // read request downgrades owner: M->O, E->F + // else set state field to I in message, but it will not be used by LCE sending transfer + fsm_cmd_header_lo.payload.state = mshr_r.flags.write_not_read + ? e_COH_I + : mshr_r.flags.cached_modified + ? e_COH_O + : mshr_r.flags.cached_exclusive + ? e_COH_F + : e_COH_I; + + // transfer information + fsm_cmd_header_lo.payload.target = mshr_r.lce_id; + fsm_cmd_header_lo.payload.target_way_id = mshr_r.lru_way_id; + fsm_cmd_header_lo.payload.target_state = mshr_r.next_coh_state; + + // update state of owner in directory if required + // transfer from owner in O or F does not require update to owner state + dir_w_v = fsm_cmd_v_lo + & (mshr_r.flags.write_not_read | mshr_r.flags.cached_modified | mshr_r.flags.cached_exclusive); + dir_cmd = e_wds_op; + dir_addr_li = mshr_r.paddr; + dir_lce_li = mshr_r.owner_lce_id; + dir_way_li = mshr_r.owner_way_id; + dir_coh_state_li = mshr_r.flags.write_not_read + ? e_COH_I + : mshr_r.flags.cached_modified + ? e_COH_O + : mshr_r.flags.cached_exclusive + ? e_COH_F + : e_COH_I; + + // only transfer from owner in E for read miss requires a writeback + state_n = fsm_cmd_v_lo + ? mshr_r.flags.cached_exclusive & ~mshr_r.flags.write_not_read + ? e_transfer_wb_resp + : e_resolve_speculation + : state_r; + end // ~lce_cmd_busy + end // e_transfer + + e_transfer_wb_resp: begin + if (fsm_resp_v_li) begin + if (fsm_resp_header_li.msg_type.resp == e_bedrock_resp_null_wb) begin + fsm_resp_yumi_lo = fsm_resp_v_li; + state_n = e_resolve_speculation; + + end + else if ((fsm_resp_header_li.msg_type.resp == e_bedrock_resp_wb) & ~pending_busy & ~mem_credits_empty) begin + // Mem Data Cmd needs to write pending bit, so only send if Mem Data Resp / LCE Data Cmd is + // not writing the pending bit. Mem command also needs a credit, only process if one is + // available. + + // handshake + // lce resp is v->yumi + // mem cmd is r&v + // lce resp data is r&v + fsm_fwd_v_lo = fsm_fwd_ready_then_li & fsm_resp_v_li; + fsm_resp_yumi_lo = fsm_fwd_v_lo; + + fsm_fwd_header_lo.msg_type.fwd = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = fsm_resp_header_li.addr; + fsm_fwd_header_lo.payload.lce_id = mshr_r.lce_id; + fsm_fwd_header_lo.payload.way_id = '0; + fsm_fwd_header_lo.payload.src_did = fsm_req_header_li.payload.src_did; + fsm_fwd_header_lo.size = fsm_resp_header_li.size; + fsm_fwd_data_lo = fsm_resp_data_li; + + // set the pending bit + pending_w_v = fsm_fwd_v_lo & fsm_fwd_new_lo & fwd_pma_cacheable_addr_lo; + pending_li = 1'b1; + pending_w_addr = fsm_resp_header_li.addr; + + state_n = (fsm_resp_yumi_lo & fsm_resp_last_li) + ? e_resolve_speculation + : e_transfer_wb_resp; + end + end + end // e_transfer_wb_resp + + e_upgrade_stw_cmd: begin + // r&v handshake + if (~lce_cmd_busy) begin + fsm_cmd_v_lo = fsm_cmd_ready_then_li; + + fsm_cmd_header_lo.msg_type.cmd = e_bedrock_cmd_st_wakeup; + fsm_cmd_header_lo.addr = mshr_r.paddr; + fsm_cmd_header_lo.payload.dst_id = mshr_r.lce_id; + fsm_cmd_header_lo.payload.way_id = mshr_r.way_id; + fsm_cmd_header_lo.payload.state = mshr_r.next_coh_state; + + state_n = fsm_cmd_v_lo + ? e_resolve_speculation + : e_upgrade_stw_cmd; + end + end // e_upgrade_stw_cmd + + e_resolve_speculation: begin + // Resolve speculation + if (transfer_flag | mshr_r.flags.upgrade) begin + // squash speculative memory request if transfer or upgrade + spec_w_v = 1'b1; + // no longer speculative + spec_v_li = 1'b1; + spec_bits_li.spec = 1'b0; + // squash the response + squash_v_li = 1'b1; + spec_bits_li.squash = 1'b1; + end else if (mshr_r.flags.write_not_read) begin + // forward with M state + spec_w_v = 1'b1; + spec_v_li = 1'b1; + fwd_mod_v_li = 1'b1; + state_v_li = 1'b1; + spec_bits_li.spec = 1'b0; + spec_bits_li.state = e_COH_M; + spec_bits_li.fwd_mod = 1'b1; + end else if (mshr_r.flags.cached_shared | mshr_r.flags.non_exclusive) begin + // forward with S state + spec_w_v = 1'b1; + spec_v_li = 1'b1; + fwd_mod_v_li = 1'b1; + state_v_li = 1'b1; + spec_bits_li.spec = 1'b0; + spec_bits_li.state = e_COH_S; + spec_bits_li.fwd_mod = 1'b1; + end else begin + // forward with E state (as requested) + spec_w_v = 1'b1; + spec_v_li = 1'b1; + spec_bits_li.spec = 1'b0; + end + state_n = e_ready; + end // e_resolve_speculation + + e_error: begin + state_n = e_error; + end // e_error + + default: begin + // use defaults above + end + + endcase + end // always_comb + + // Sequential Logic + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) begin + if (reset_i) begin + state_r <= e_reset; + mshr_r <= '0; + sharers_ways_r <= '0; + sharers_hits_r <= '0; + pe_sharers_r <= '0; + cce_normal_mode_r <= '0; + end else begin + state_r <= state_n; + mshr_r <= mshr_n; + sharers_ways_r <= sharers_ways_n; + sharers_hits_r <= sharers_hits_n; + pe_sharers_r <= pe_sharers_n; + cce_normal_mode_r <= cce_normal_mode_n; + end + end + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_gad.sv b/designs/black-parrot/src/bp/bp_cce_gad.sv new file mode 100644 index 0000000..270a600 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_gad.sv @@ -0,0 +1,162 @@ +/** + * + * Name: + * bp_cce_gad.sv + * + * Description: + * The GAD (Generate Auxiliary Directory Information) module computes the values of a number of + * control flags used by the CCE, based on the information stored in a way-group in the + * coherence directory. The directory information is consolidated as it is read out of the + * directory RAM into a few vectors that indicate for each LCE if there is a hit for the target + * address, which way in the LCE the hit occurred in, and the coherence state of that entry. + * + * + * This block supports any valid subset of MOESIF. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_gad + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Derived parameters + , localparam lg_num_lce_lp = `BSG_SAFE_CLOG2(num_lce_p) + ) + (input clk_i + , input reset_i + + // high if the current op is a GAD op + , input gad_v_i + + // from Directory + , input sharers_v_i + , input [num_lce_p-1:0] sharers_hits_i + , input [num_lce_p-1:0][lce_assoc_width_p-1:0] sharers_ways_i + , input bp_coh_states_e [num_lce_p-1:0] sharers_coh_states_i + + // from MSHR - request details + , input [lce_id_width_p-1:0] req_lce_i + , input req_type_flag_i + , input bp_coh_states_e lru_coh_state_i + , input atomic_req_flag_i + , input uncached_req_flag_i + + // Outputs + , output logic [lce_assoc_width_p-1:0] req_addr_way_o + + , output logic [lce_id_width_p-1:0] owner_lce_o + , output logic [lce_assoc_width_p-1:0] owner_way_o + , output bp_coh_states_e owner_coh_state_o + + , output logic replacement_flag_o + , output logic upgrade_flag_o + , output logic cached_shared_flag_o + , output logic cached_exclusive_flag_o + , output logic cached_modified_flag_o + , output logic cached_owned_flag_o + , output logic cached_forward_flag_o + ); + + // Suppress unused signal warnings + wire unused = &{clk_i, reset_i, sharers_v_i}; + + wire [lg_num_lce_lp-1:0] req_lce_id = req_lce_i[0+:lg_num_lce_lp]; + + // one hot decoding of request LCE ID + logic [num_lce_p-1:0] lce_id_one_hot; + bsg_decode + #(.num_out_p(num_lce_p) + ) + lce_id_to_one_hot + (.i(req_lce_id) + ,.o(lce_id_one_hot) + ); + + // Cache hit per LCE + logic [num_lce_p-1:0] lce_cached; + assign lce_cached = sharers_hits_i; + + logic [num_lce_p-1:0] lce_cached_S; + logic [num_lce_p-1:0] lce_cached_E; + logic [num_lce_p-1:0] lce_cached_M; + logic [num_lce_p-1:0] lce_cached_O; + logic [num_lce_p-1:0] lce_cached_F; + for (genvar i = 0; i < num_lce_p; i=i+1) begin : lce_cached_flags + assign lce_cached_S[i] = lce_cached[i] & (sharers_coh_states_i[i] == e_COH_S); + assign lce_cached_E[i] = lce_cached[i] & (sharers_coh_states_i[i] == e_COH_E); + assign lce_cached_M[i] = lce_cached[i] & (sharers_coh_states_i[i] == e_COH_M); + assign lce_cached_O[i] = lce_cached[i] & (sharers_coh_states_i[i] == e_COH_O); + assign lce_cached_F[i] = lce_cached[i] & (sharers_coh_states_i[i] == e_COH_F); + end + + // Block cached in some state in LCE other than requestor + assign cached_shared_flag_o = |(lce_cached_S & ~lce_id_one_hot); + assign cached_exclusive_flag_o = |(lce_cached_E & ~lce_id_one_hot); + assign cached_modified_flag_o = |(lce_cached_M & ~lce_id_one_hot); + assign cached_owned_flag_o = |(lce_cached_O & ~lce_id_one_hot); + assign cached_forward_flag_o = |(lce_cached_F & ~lce_id_one_hot); + + // hit in requesting LCE + logic req_lce_cached; + assign req_lce_cached = lce_cached[req_lce_id] & (req_lce_id < num_lce_p); + // read-only permissions in requesting LCE (block in S, F, or O) + logic req_lce_ro; + assign req_lce_ro = req_lce_cached & ((sharers_coh_states_i[req_lce_id] == e_COH_S) + | (sharers_coh_states_i[req_lce_id] == e_COH_F) + | (sharers_coh_states_i[req_lce_id] == e_COH_O)); + + assign req_addr_way_o = req_lce_cached + ? sharers_ways_i[req_lce_id] + : '0; + + // Flag outputs + + // Upgrade from read-only to read-write + // Requesting LCE has block cached in read-only state and request is a store-miss + // Only for cached access + assign upgrade_flag_o = req_type_flag_i & req_lce_ro & ~uncached_req_flag_i; + + // Replace the LRU block if not doing an upgrade and the lru block might be dirty + // also set replacement flag when the block is cached (in any state) by the requesting + // LCE and the request is an atomic operation or an uncached operation. + assign replacement_flag_o = (uncached_req_flag_i | atomic_req_flag_i) + ? req_lce_cached + : (~upgrade_flag_o & ((lru_coh_state_i == e_COH_E) + | (lru_coh_state_i == e_COH_M) + | (lru_coh_state_i == e_COH_O)) + ); + + // Owner LCE + logic [num_lce_p-1:0] owner_lce_one_hot; + // output owner even if it is same as requestor + // Owner will be in one of states: E, M, O, or F; and only one LCE may be in those states + // It is an error if more than one LCE is in one of these states (or the two LCE's are in some + // pair of these states) for a given cache block. + assign owner_lce_one_hot = (gad_v_i) + ? (lce_cached_E | lce_cached_M | lce_cached_O | lce_cached_F) + : '0; + + logic [lg_num_lce_lp-1:0] owner_lce_lo; + logic owner_lce_v; + bsg_encode_one_hot + #(.width_p(num_lce_p) + ,.lo_to_hi_p(1) + ) + lce_cached_to_lce_id + (.i(owner_lce_one_hot) + ,.addr_o(owner_lce_lo) + ,.v_o(owner_lce_v) + ); + + assign owner_lce_o = (gad_v_i & owner_lce_v) + ? {'0, owner_lce_lo} : '0; + assign owner_way_o = (gad_v_i & owner_lce_v) + ? sharers_ways_i[owner_lce_lo] : '0; + assign owner_coh_state_o = (gad_v_i & owner_lce_v) + ? sharers_coh_states_i[owner_lce_lo] : e_COH_I; + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_inst_decode.sv b/designs/black-parrot/src/bp/bp_cce_inst_decode.sv new file mode 100644 index 0000000..f1953a0 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_inst_decode.sv @@ -0,0 +1,818 @@ +/** + * + * Name: + * bp_cce_inst_decode.sv + * + * Description: + * The decoder holds the decode+execute stage PC, instruction, and valid bit. The decoder also + * contains the instruction decode logic and outputs the decoded instruction used to control + * all of the other modules in the CCE. + * + * The decoder does not check if the instruction can actually be executed, rather it outputs + * the instruction assuming it will be executed. The stall unit and other arbitration logic + * in the CCE will nullify the instruction if it cannot be executed this cycle. The decoder + * is informed of this through the stall_i signal, which causes the current PC, instruction, + * and valid bit to be retained at the end of the cycle. The current instruction is then + * replayed next cycle. + * + * A mispredict event detected by the branch unit causes the next instruction to be invalid + * since the Fetch stage must re-direct instruction fetch. The instruction being produced + * by Fetch when a mispredict is detected becomes invalid and therefore there is a 1 cycle + * bubble/penalty for a mispredicted branch. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_inst_decode + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter `BSG_INV_PARAM(cce_pc_width_p) + ) + (input clk_i + , input reset_i + + // Instruction, PC, and valid bit from bp_cce_inst_ram + , input bp_cce_inst_s inst_i + , input [cce_pc_width_p-1:0] pc_i + , input inst_v_i + + // Stall signal from stall detection unit + , input stall_i + + // Mispredict signal from branch unit + , input mispredict_i + + // Decoded instruction + , output bp_cce_inst_decoded_s decoded_inst_o + , output logic [cce_pc_width_p-1:0] pc_o + + ); + + // Execute Stage Instruction Register and PC + bp_cce_inst_s inst_r, inst_n; + logic [cce_pc_width_p-1:0] ex_pc_r, ex_pc_n; + logic inst_v_r, inst_v_n; + always_ff @(posedge clk_i) begin + if (reset_i) begin + inst_r <= '0; + ex_pc_r <= '0; + inst_v_r <= '0; + end else begin + inst_r <= inst_n; + ex_pc_r <= ex_pc_n; + inst_v_r <= inst_v_n; + end + end + + // Instruction Fields + bp_cce_inst_op_e op; + bp_cce_inst_minor_op_u minor_op_u; + bp_cce_inst_type_u op_type_u; + + always_comb begin + + // Next instruction determination + + // The next instruction and its PC that will be seen by the Execute stage comes from + // the output of the instruction RAM and the fetch_pc register in bp_cce_inst_ram. + inst_n = stall_i ? inst_r : inst_i; + ex_pc_n = stall_i ? ex_pc_r : pc_i; + // The next instruction is valid as long as there was not a mispredict detected in the + // Execute stage. A mispredict squashes the next instruction, by setting the valid bit + // to 0 for the next cycle, which then gates off the decoder next cycle. + // If the current instruction stalls (which is detected after decoding due to interactions + // between the current ucode instruction and resource conflicts with functional units), + // the stall signal is sent back to the Fetch stage and the current instruction, PC, and + // valid bit are retained for the next cycle. The stall signal also causes the valid + // bit to hold its state. + inst_v_n = stall_i + ? inst_v_r + : mispredict_i + ? 1'b0 + : inst_v_i; + + + // Current instruction decoding - does not depend on stall or mispredict. + + pc_o = ex_pc_r; + + decoded_inst_o = '0; + decoded_inst_o.v = inst_v_r; + + op = inst_r.op; + minor_op_u = inst_r.minor_op_u; + op_type_u = inst_r.type_u; + + // only finish decoding if current instruction is valid + if (inst_v_r) begin + + decoded_inst_o.branch = inst_r.branch; + decoded_inst_o.predict_taken = inst_r.predict_taken; + + decoded_inst_o.op = op; + decoded_inst_o.minor_op_u = minor_op_u; + + unique case (op) + + // ALU Operations + e_op_alu: begin + + // Note: decoding ALU ops relies on the dst field being in the same location + // in both rtype and itype instruction encodings. + + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.rtype.src_a.gpr; + + unique case (minor_op_u.alu_minor_op) + e_add_op: begin + decoded_inst_o.alu_op = e_alu_add; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.rtype.src_b.gpr; + end + e_sub_op: begin + decoded_inst_o.alu_op = e_alu_sub; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.rtype.src_b.gpr; + end + e_lsh_op: begin + decoded_inst_o.alu_op = e_alu_lsh; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.rtype.src_b.gpr; + end + e_rsh_op: begin + decoded_inst_o.alu_op = e_alu_rsh; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.rtype.src_b.gpr; + end + e_and_op: begin + decoded_inst_o.alu_op = e_alu_and; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.rtype.src_b.gpr; + end + e_or_op: begin + decoded_inst_o.alu_op = e_alu_or; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.rtype.src_b.gpr; + end + e_xor_op: begin + decoded_inst_o.alu_op = e_alu_xor; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.rtype.src_b.gpr; + end + e_neg_op: begin // only one source operand + decoded_inst_o.alu_op = e_alu_neg; + end + e_addi_op: begin + decoded_inst_o.alu_op = e_alu_add; + decoded_inst_o.src_b_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.itype.imm; + end + e_subi_op: begin + decoded_inst_o.alu_op = e_alu_sub; + decoded_inst_o.src_b_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.itype.imm; + end + e_lshi_op: begin + decoded_inst_o.alu_op = e_alu_lsh; + decoded_inst_o.src_b_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.itype.imm; + end + e_rshi_op: begin + decoded_inst_o.alu_op = e_alu_rsh; + decoded_inst_o.src_b_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.itype.imm; + end + e_not_op: begin // only one source operand + decoded_inst_o.alu_op = e_alu_not; + end + default: begin + end + endcase + end + + // Branch Operations (except branch flag, which are under Flag) + e_op_branch: begin + + // Note: Decoding branches relies the target field being in the same location + // for btype, bitype, and bftype instruction encodings. + + decoded_inst_o.branch_target = op_type_u.btype.target; + + unique case (minor_op_u.branch_minor_op) + e_beq_op: begin + decoded_inst_o.branch_op = e_branch_eq; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.btype.src_a.gpr; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.btype.src_b.gpr; + end + e_bne_op: begin + decoded_inst_o.branch_op = e_branch_neq; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.btype.src_a.gpr; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.btype.src_b.gpr; + end + e_blt_op: begin + decoded_inst_o.branch_op = e_branch_lt; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.btype.src_a.gpr; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.btype.src_b.gpr; + end + e_ble_op: begin + decoded_inst_o.branch_op = e_branch_le; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.btype.src_a.gpr; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.btype.src_b.gpr; + end + e_bs_op: begin // src_a = special, src_b = gpr + decoded_inst_o.branch_op = e_branch_eq; + decoded_inst_o.src_a_sel = e_src_sel_special; + decoded_inst_o.src_a.special = op_type_u.btype.src_a.special; + decoded_inst_o.src_b_sel = e_src_sel_gpr; + decoded_inst_o.src_b.gpr = op_type_u.btype.src_b.gpr; + end + e_bss_op: begin // src_a and src_b = special + decoded_inst_o.branch_op = e_branch_eq; + decoded_inst_o.src_a_sel = e_src_sel_special; + decoded_inst_o.src_a.special = op_type_u.btype.src_a.special; + decoded_inst_o.src_b_sel = e_src_sel_special; + decoded_inst_o.src_b.special = op_type_u.btype.src_b.special; + end + e_beqi_op: begin // src_a = gpr, src_b = imm + decoded_inst_o.branch_op = e_branch_eq; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.bitype.src_a.gpr; + decoded_inst_o.src_b_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm8_width] = op_type_u.bitype.imm; + end + e_bsi_op: begin // src_a = special, src_b = imm + decoded_inst_o.branch_op = e_branch_eq; + decoded_inst_o.src_a_sel = e_src_sel_special; + decoded_inst_o.src_a.special = op_type_u.bitype.src_a.special; + decoded_inst_o.src_b_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm8_width] = op_type_u.bitype.imm; + end + default: begin + end + endcase + end + + // Register Data Movement Operations + e_op_reg_data: begin + + unique case (minor_op_u.reg_data_minor_op) + e_mov_op: begin + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.rtype.src_a.gpr; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_movsg_op: begin + decoded_inst_o.src_a_sel = e_src_sel_special; + decoded_inst_o.src_a.special = op_type_u.rtype.src_a.special; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_movgs_op: begin + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.rtype.src_a.gpr; + decoded_inst_o.dst_sel = e_dst_sel_special; + decoded_inst_o.dst.special = op_type_u.rtype.dst.special; + // write enable signal set below + end + e_movfg_op: begin + decoded_inst_o.src_a_sel = e_src_sel_flag; + decoded_inst_o.src_a.flag = op_type_u.rtype.src_a.flag; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_movgf_op: begin + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.rtype.src_a.gpr; + decoded_inst_o.dst_sel = e_dst_sel_flag; + decoded_inst_o.dst.flag = op_type_u.rtype.dst.flag; + decoded_inst_o.flag_w_v[op_type_u.rtype.dst.flag] = 1'b1; + end + e_movpg_op: begin + decoded_inst_o.src_a_sel = e_src_sel_param; + decoded_inst_o.src_a.param = op_type_u.rtype.src_a.param; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_movgp_op: begin + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.rtype.src_a.gpr; + decoded_inst_o.dst_sel = e_dst_sel_param; + decoded_inst_o.dst.param = op_type_u.rtype.dst.param; + end + e_movi_op: begin + decoded_inst_o.src_a_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.itype.imm; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.itype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.itype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_movis_op: begin + decoded_inst_o.src_a_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.itype.imm; + decoded_inst_o.dst_sel = e_dst_sel_special; + decoded_inst_o.dst.special = op_type_u.itype.dst.special; + // write enable signal set below + end + e_movip_op: begin + decoded_inst_o.src_a_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.itype.imm; + decoded_inst_o.dst_sel = e_dst_sel_param; + decoded_inst_o.dst.param = op_type_u.itype.dst.param; + // write enable signal set below + end + e_clm_op: begin + decoded_inst_o.mshr_clear = 1'b1; + end + default: begin + end + endcase + + if ((minor_op_u.reg_data_minor_op == e_movgs_op) + | (minor_op_u.reg_data_minor_op == e_movis_op)) begin + if (op_type_u.itype.dst.special == e_opd_req_lce) begin + decoded_inst_o.lce_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_req_addr) begin + decoded_inst_o.addr_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_req_way) begin + decoded_inst_o.way_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_lru_addr) begin + decoded_inst_o.lru_addr_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_lru_way) begin + decoded_inst_o.lru_way_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_owner_lce) begin + decoded_inst_o.owner_lce_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_owner_way) begin + decoded_inst_o.owner_way_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_next_coh_state) begin + decoded_inst_o.next_coh_state_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_lru_coh_state) begin + decoded_inst_o.lru_coh_state_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_owner_coh_state) begin + decoded_inst_o.owner_coh_state_w_v = 1'b1; + end + if (op_type_u.itype.dst.special == e_opd_flags) begin + decoded_inst_o.flag_w_v = '1; + decoded_inst_o.imm = '1; + end + if (op_type_u.itype.dst.special == e_opd_msg_size) begin + decoded_inst_o.msg_size_w_v = 1'b1; + end + end + + if ((minor_op_u.reg_data_minor_op == e_movgp_op) + | (minor_op_u.reg_data_minor_op == e_movip_op)) begin + if (op_type_u.itype.dst.param == e_opd_auto_fwd_msg) begin + decoded_inst_o.auto_fwd_msg_w_v = 1'b1; + end + if (op_type_u.itype.dst.param == e_opd_coh_state_default) begin + decoded_inst_o.coh_state_w_v = 1'b1; + end + end + + end + + // Flag Operations + e_op_flag: begin + + unique case (minor_op_u.flag_minor_op) + e_sf_op: begin + decoded_inst_o.src_a_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.itype.imm; + decoded_inst_o.dst_sel = e_dst_sel_flag; + decoded_inst_o.flag_w_v[op_type_u.itype.dst.flag] = 1'b1; + end + e_andf_op: begin + decoded_inst_o.alu_op = e_alu_and; + decoded_inst_o.src_a_sel = e_src_sel_flag; + decoded_inst_o.src_a.flag = op_type_u.rtype.src_a.flag; + decoded_inst_o.src_b_sel = e_src_sel_flag; + decoded_inst_o.src_b.flag = op_type_u.rtype.src_b.flag; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_orf_op: begin + decoded_inst_o.alu_op = e_alu_or; + decoded_inst_o.src_a_sel = e_src_sel_flag; + decoded_inst_o.src_a.flag = op_type_u.rtype.src_a.flag; + decoded_inst_o.src_b_sel = e_src_sel_flag; + decoded_inst_o.src_b.flag = op_type_u.rtype.src_b.flag; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_nandf_op: begin + decoded_inst_o.alu_op = e_alu_nand; + decoded_inst_o.src_a_sel = e_src_sel_flag; + decoded_inst_o.src_a.flag = op_type_u.rtype.src_a.flag; + decoded_inst_o.src_b_sel = e_src_sel_flag; + decoded_inst_o.src_b.flag = op_type_u.rtype.src_b.flag; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_norf_op: begin + decoded_inst_o.alu_op = e_alu_nor; + decoded_inst_o.src_a_sel = e_src_sel_flag; + decoded_inst_o.src_a.flag = op_type_u.rtype.src_a.flag; + decoded_inst_o.src_b_sel = e_src_sel_flag; + decoded_inst_o.src_b.flag = op_type_u.rtype.src_b.flag; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_notf_op: begin + decoded_inst_o.alu_op = e_alu_not; + decoded_inst_o.src_a_sel = e_src_sel_flag; + decoded_inst_o.src_a.flag = op_type_u.rtype.src_a.flag; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.rtype.dst.gpr; + decoded_inst_o.gpr_w_v[op_type_u.rtype.dst.gpr[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + e_bf_op: begin + decoded_inst_o.branch_op = e_branch_eq; + decoded_inst_o.branch_target = op_type_u.bftype.target; + decoded_inst_o.src_a_sel = e_src_sel_special; + decoded_inst_o.src_a.special = e_opd_flags; + decoded_inst_o.src_b_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.bftype.imm; + end + e_bfz_op: begin + decoded_inst_o.branch_op = e_branch_eq; + decoded_inst_o.branch_target = op_type_u.bftype.target; + decoded_inst_o.src_a_sel = e_src_sel_special; + decoded_inst_o.src_a.special = e_opd_flags; + decoded_inst_o.src_b_sel = e_src_sel_zero; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.bftype.imm; + end + e_bfnz_op: begin + decoded_inst_o.branch_op = e_branch_neq; + decoded_inst_o.branch_target = op_type_u.bftype.target; + decoded_inst_o.src_a_sel = e_src_sel_special; + decoded_inst_o.src_a.special = e_opd_flags; + decoded_inst_o.src_b_sel = e_src_sel_zero; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.bftype.imm; + end + e_bfnot_op: begin + decoded_inst_o.branch_op = e_branch_neq; + decoded_inst_o.branch_target = op_type_u.bftype.target; + decoded_inst_o.src_a_sel = e_src_sel_special; + decoded_inst_o.src_a.special = e_opd_flags; + decoded_inst_o.src_b_sel = e_src_sel_imm; + decoded_inst_o.imm[0+:`bp_cce_inst_imm16_width] = op_type_u.bftype.imm; + end + default: begin + end + endcase + end + + // Directory Operations + e_op_dir: begin + + unique case (minor_op_u.flag_minor_op) + e_rdp_op: begin + decoded_inst_o.pending_r_v = 1'b1; + decoded_inst_o.addr_sel = op_type_u.dptype.addr_sel; + decoded_inst_o.flag_w_v[e_opd_pf] = 1'b1; + end + e_rdw_op: begin + decoded_inst_o.dir_r_v = 1'b1; + decoded_inst_o.addr_sel = op_type_u.drtype.addr_sel; + decoded_inst_o.lce_sel = op_type_u.drtype.lce_sel; + decoded_inst_o.lru_way_sel = op_type_u.drtype.lru_way_sel; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.drtype.src_a; + end + e_rde_op: begin + decoded_inst_o.dir_r_v = 1'b1; + decoded_inst_o.addr_sel = op_type_u.drtype.addr_sel; + decoded_inst_o.lce_sel = op_type_u.drtype.lce_sel; + decoded_inst_o.way_sel = op_type_u.drtype.way_sel; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.drtype.dst; + decoded_inst_o.gpr_w_v[op_type_u.drtype.dst[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.drtype.src_a; + end + e_wdp_op: begin + decoded_inst_o.pending_w_v = 1'b1; + decoded_inst_o.addr_sel = op_type_u.dptype.addr_sel; + decoded_inst_o.pending_bit = op_type_u.dptype.pending; + decoded_inst_o.imm[0] = op_type_u.dptype.pending; + end + e_clp_op: begin + decoded_inst_o.pending_w_v = 1'b1; + decoded_inst_o.pending_clear = 1'b1; + decoded_inst_o.addr_sel = op_type_u.dptype.addr_sel; + end + e_clr_op: begin + decoded_inst_o.dir_w_v = 1'b1; + decoded_inst_o.addr_sel = op_type_u.drtype.addr_sel; + decoded_inst_o.lce_sel = op_type_u.drtype.lce_sel; + end + e_wde_op: begin + decoded_inst_o.dir_w_v = 1'b1; + decoded_inst_o.addr_sel = op_type_u.dwtype.addr_sel; + decoded_inst_o.lce_sel = op_type_u.dwtype.lce_sel; + decoded_inst_o.way_sel = op_type_u.dwtype.way_sel; + decoded_inst_o.coh_state_sel = op_type_u.dwtype.state_sel; + decoded_inst_o.imm[0+:$bits(bp_coh_states_e)] = op_type_u.dwtype.state; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.dwtype.src_a; + end + e_wds_op: begin + decoded_inst_o.dir_w_v = 1'b1; + decoded_inst_o.addr_sel = op_type_u.dwtype.addr_sel; + decoded_inst_o.lce_sel = op_type_u.dwtype.lce_sel; + decoded_inst_o.way_sel = op_type_u.dwtype.way_sel; + decoded_inst_o.coh_state_sel = op_type_u.dwtype.state_sel; + decoded_inst_o.imm[0+:$bits(bp_coh_states_e)] = op_type_u.dwtype.state; + decoded_inst_o.src_a_sel = e_src_sel_gpr; + decoded_inst_o.src_a.gpr = op_type_u.dwtype.src_a; + end + e_gad_op: begin + decoded_inst_o.gad_v = 1'b1; + decoded_inst_o.way_w_v = 1'b1; + decoded_inst_o.owner_lce_w_v = 1'b1; + decoded_inst_o.owner_way_w_v = 1'b1; + decoded_inst_o.owner_coh_state_w_v = 1'b1; + decoded_inst_o.flag_w_v[e_opd_rf] = 1'b1; + decoded_inst_o.flag_w_v[e_opd_uf] = 1'b1; + decoded_inst_o.flag_w_v[e_opd_csf] = 1'b1; + decoded_inst_o.flag_w_v[e_opd_cef] = 1'b1; + decoded_inst_o.flag_w_v[e_opd_cmf] = 1'b1; + decoded_inst_o.flag_w_v[e_opd_cof] = 1'b1; + decoded_inst_o.flag_w_v[e_opd_cff] = 1'b1; + end + default: begin + end + endcase + end + + // Queue Operations + e_op_queue: begin + + unique case (minor_op_u.queue_minor_op) + e_wfq_op: begin + decoded_inst_o.wfq_v = 1'b1; + decoded_inst_o.imm[0+:$bits(bp_cce_inst_src_q_e)] = op_type_u.itype.imm[0+:$bits(bp_cce_inst_src_q_e)]; + end + e_pushq_op: begin + // pushq and pushqc have same encoding, except pushq uses + // the way_sel field and pushqc the msg_size field + decoded_inst_o.pushq = 1'b1; + decoded_inst_o.pushq_qsel = op_type_u.pushq.dst_q; + + unique case (op_type_u.pushq.dst_q) + e_dst_q_sel_lce_cmd: begin + decoded_inst_o.lce_cmd_v = 1'b1; + decoded_inst_o.lce_cmd = op_type_u.pushq.cmd.lce_cmd; + end + e_dst_q_sel_mem_fwd: begin + decoded_inst_o.mem_fwd_v = 1'b1; + decoded_inst_o.mem_fwd = op_type_u.pushq.cmd.mem_fwd; + end + default: begin + end + endcase + + decoded_inst_o.addr_sel = op_type_u.pushq.addr_sel; + decoded_inst_o.lce_sel = op_type_u.pushq.lce_sel; + decoded_inst_o.src_a_sel = e_src_sel_queue; + decoded_inst_o.src_a.q = op_type_u.pushq.src_a; + + // set spec bit to 1, clear rest of bits + // Note: spec bit should only be set for mem_fwd + // It is a microcode/program error if it is set when pusing to lce_cmd, + // and there is a check in the assembler to help guard against this + if (op_type_u.pushq.spec) begin + decoded_inst_o.spec_w_v = 1'b1; + decoded_inst_o.spec_v = 1'b1; + decoded_inst_o.spec_squash_v = 1'b1; + decoded_inst_o.spec_fwd_mod_v = 1'b1; + decoded_inst_o.spec_state_v = 1'b1; + decoded_inst_o.spec_bits.spec = 1'b1; + end + + decoded_inst_o.pushq_custom = op_type_u.pushq.custom; + + // custom push commands use msg_size field + decoded_inst_o.msg_size = bp_bedrock_msg_size_e'(op_type_u.pushq.way_or_size.msg_size); + // normal push commands use way_select and coh_state_select + decoded_inst_o.way_sel = op_type_u.pushq.way_or_size.way_sel; + // TODO: make coh_state_sel flexible / set by instruction, not + // fixed to next coherence state in MSHR? + decoded_inst_o.coh_state_sel = e_mux_sel_coh_next_coh_state; + + // if the write_pending bit is set, the ucode instruction will also increment + // the pending bit for the selected address + if (op_type_u.pushq.write_pending) begin + decoded_inst_o.pending_w_v = 1'b1; + decoded_inst_o.pending_bit = 1'b1; + end + + end + e_popq_op: begin + decoded_inst_o.popq = 1'b1; + decoded_inst_o.popq_qsel = op_type_u.popq.src_q; + unique case (op_type_u.popq.src_q) + e_src_q_sel_lce_req: begin + decoded_inst_o.lce_req_yumi = 1'b1; + decoded_inst_o.addr_sel = e_mux_sel_addr_lce_req; + end + e_src_q_sel_lce_resp: begin + decoded_inst_o.lce_resp_yumi = 1'b1; + decoded_inst_o.addr_sel = e_mux_sel_addr_lce_resp; + end + e_src_q_sel_mem_rev: begin + decoded_inst_o.mem_rev_yumi = 1'b1; + decoded_inst_o.addr_sel = e_mux_sel_addr_mem_rev; + end + e_src_q_sel_pending: begin + decoded_inst_o.pending_yumi = 1'b0; + decoded_inst_o.addr_sel = e_mux_sel_addr_pending; + end + default: begin + end + endcase + + // if the write_pending bit is set, the ucode instruction will also increment or + // decrement the pending bit for the selected address if the action is a pop + // or push instruction, respectively. + if (op_type_u.popq.write_pending) begin + decoded_inst_o.pending_w_v = 1'b1; + // increment pending bit on request pop + if (decoded_inst_o.lce_req_yumi | decoded_inst_o.pending_yumi) begin + decoded_inst_o.pending_bit = 1'b1; + end + // decrement pending bit on response pop + else begin + decoded_inst_o.pending_bit = 1'b0; + end + end + + end + e_poph_op: begin + decoded_inst_o.poph = 1'b1; + decoded_inst_o.popq_qsel = op_type_u.popq.src_q; + decoded_inst_o.src_a_sel = e_src_sel_queue; + unique case (op_type_u.popq.src_q) + e_src_q_sel_lce_resp: begin + decoded_inst_o.src_a.q = e_opd_lce_resp_type; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.popq.dst; + decoded_inst_o.gpr_w_v[op_type_u.popq.dst[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + // Note: popping lce response does not write the LCE, address, or data length + // fields in the MSHR. + decoded_inst_o.flag_w_v = e_flag_nwbf; + end + e_src_q_sel_mem_rev: begin + decoded_inst_o.src_a.q = e_opd_mem_rev_type; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.popq.dst; + decoded_inst_o.gpr_w_v[op_type_u.popq.dst[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + // Note: popping mem response does not write the LCE, address, or next coherence + // state fields in the MSHR. + decoded_inst_o.flag_w_v = e_flag_sf; + end + e_src_q_sel_lce_req: begin + decoded_inst_o.lce_w_v = 1'b1; + decoded_inst_o.addr_w_v = 1'b1; + decoded_inst_o.lru_way_w_v = 1'b1; + decoded_inst_o.msg_size_w_v = 1'b1; + decoded_inst_o.flag_w_v = (e_flag_rqf | e_flag_nerf | e_flag_ucf | e_flag_rcf); + end + default: begin + decoded_inst_o.src_a.q = e_opd_lce_resp_type; + end + endcase + end + e_popd_op: begin + // TODO: add full support when removing message deserialization + // pop 64-bits of data from src_q to a GPR + decoded_inst_o.popd = 1'b1; + decoded_inst_o.popq_qsel = op_type_u.popq.src_q; + decoded_inst_o.src_a_sel = e_src_sel_queue; + decoded_inst_o.dst_sel = e_dst_sel_gpr; + decoded_inst_o.dst.gpr = op_type_u.popq.dst; + decoded_inst_o.gpr_w_v[op_type_u.popq.dst[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + unique case (op_type_u.popq.src_q) + e_src_q_sel_lce_resp: begin + decoded_inst_o.src_a.q = e_opd_lce_resp_data; + end + e_src_q_sel_mem_rev: begin + decoded_inst_o.src_a.q = e_opd_mem_rev_data; + end + e_src_q_sel_lce_req: begin + decoded_inst_o.src_a.q = e_opd_lce_req_data; + end + default: begin + decoded_inst_o.src_a.q = e_opd_lce_resp_data; + end + endcase + + end + e_specq_op: begin + + decoded_inst_o.addr_sel = op_type_u.stype.addr_sel; + + // specq instructions manipulate all of the spec_bits + unique case (op_type_u.stype.cmd) + // set pending bit, clear all others + e_spec_set: begin + decoded_inst_o.spec_w_v = 1'b1; + decoded_inst_o.spec_v = 1'b1; + decoded_inst_o.spec_squash_v = 1'b1; + decoded_inst_o.spec_fwd_mod_v = 1'b1; + decoded_inst_o.spec_state_v = 1'b1; + decoded_inst_o.spec_bits.spec = 1'b1; + end + // clear all bits + e_spec_unset: begin + decoded_inst_o.spec_w_v = 1'b1; + decoded_inst_o.spec_v = 1'b1; + decoded_inst_o.spec_squash_v = 1'b1; + decoded_inst_o.spec_fwd_mod_v = 1'b1; + decoded_inst_o.spec_state_v = 1'b1; + end + // set squash bit, clear all others + e_spec_squash: begin + decoded_inst_o.spec_w_v = 1'b1; + decoded_inst_o.spec_v = 1'b1; + decoded_inst_o.spec_squash_v = 1'b1; + decoded_inst_o.spec_fwd_mod_v = 1'b1; + decoded_inst_o.spec_state_v = 1'b1; + decoded_inst_o.spec_bits.squash = 1'b1; + end + // set fwd_mod bit and state field, clear spec and squash bits + e_spec_fwd_mod: begin + decoded_inst_o.spec_w_v = 1'b1; + decoded_inst_o.spec_v = 1'b1; + decoded_inst_o.spec_squash_v = 1'b1; + decoded_inst_o.spec_fwd_mod_v = 1'b1; + decoded_inst_o.spec_state_v = 1'b1; + decoded_inst_o.spec_bits.fwd_mod = 1'b1; + decoded_inst_o.spec_bits.state = op_type_u.stype.state; + end + // read spec bit to spec flag in MSHR + // speculative bit from bp_cce_spec_bits is sent to bp_cce_reg and used as source + // for spec flag + e_spec_rd_spec: begin + decoded_inst_o.spec_r_v = 1'b1; + decoded_inst_o.flag_w_v[e_opd_sf] = 1'b1; + end + default: begin + // shouldn't reach here unless bad instruction + decoded_inst_o.spec_w_v = 1'b0; + end + endcase + end + e_inv_op: begin + // invalidate op consumes sharers hits and sharers ways + // message unit is hard-coded to handle invalidate op + decoded_inst_o.inv_cmd_v = 1'b1; + decoded_inst_o.addr_sel = e_mux_sel_addr_mshr_req; + end + default: begin + end + endcase + end // queue operations + + // Default for operation type - invalid instruction goes here + default: begin + end + endcase // op type + end // instruction valid + end // always_comb + +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_inst_decode) diff --git a/designs/black-parrot/src/bp/bp_cce_inst_predecode.sv b/designs/black-parrot/src/bp/bp_cce_inst_predecode.sv new file mode 100644 index 0000000..42ad755 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_inst_predecode.sv @@ -0,0 +1,44 @@ +/** + * + * Name: + * bp_cce_inst_predecode.sv + * + * Description: + * The pre-decoder examines the branch and predict bits from the instruction, extracts the + * branch target from the instruction, and then outputs the next fetch PC. + * The next fetch PC is either current fetch PC + 1 or the branch target. + * + * The pc_i signal comes directly from the fetch PC register (which has the same value as + * the registered address in the instruction RAM), and the instruction comes from the read of + * the instruction RAM. + * + * The Fetch PC register, through the instruction RAM read, through pre-decode, and then + * through muxes to the input of the Fetch PC register for the next cycle is a likely critical + * path in the CCE. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_inst_predecode + import bp_me_pkg::*; + #(parameter `BSG_INV_PARAM(width_p)) + (input bp_cce_inst_s inst_i + , input [width_p-1:0] pc_i + , output logic [width_p-1:0] predicted_next_pc_o + ); + + // parameter checks + if (width_p > `bp_cce_inst_addr_width) + $error("Desired address width is larger than address width used in instruction encoding"); + + wire [width_p-1:0] pc_plus_one = width_p'(pc_i + 'd1); + wire [width_p-1:0] branch_target = inst_i.type_u.btype.target[0+:width_p]; + wire predict_taken = (inst_i.branch & inst_i.predict_taken); + + assign predicted_next_pc_o = predict_taken ? branch_target : pc_plus_one; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_inst_predecode) diff --git a/designs/black-parrot/src/bp/bp_cce_inst_ram.sv b/designs/black-parrot/src/bp/bp_cce_inst_ram.sv new file mode 100644 index 0000000..1fdb4b2 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_inst_ram.sv @@ -0,0 +1,164 @@ +/** + * + * Name: + * bp_cce_inst_ram.sv + * + * Description: + * Fetch PC register, next PC logic, and instruction memory + * + * Fetch chooses between three PC's. By default, fetching uses the predicted PC from pre-decode. + * If there is a stall, the current PC is re-fetched. If a mispredict is detected in EX stage, + * fetch is re-directed to the correct PC as computed by EX. + * + * The configuration bus can read or write the ucode RAM while CCE is in INIT state + * (uncached mode). A config read or write during normal execution results in undefined behavior. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_inst_ram + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + // Derived parameters + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + // Configuration Interface + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // ucode programming interface, synchronous read, direct connection to RAM + , input ucode_v_i + , input ucode_w_i + , input [cce_pc_width_p-1:0] ucode_addr_i + , input [cce_instr_width_gp-1:0] ucode_data_i + , output logic [cce_instr_width_gp-1:0] ucode_data_o + + , input [cce_pc_width_p-1:0] predicted_fetch_pc_i + , input [cce_pc_width_p-1:0] branch_resolution_pc_i + + , input stall_i + , input mispredict_i + + , output logic [cce_pc_width_p-1:0] fetch_pc_o + , output bp_cce_inst_s inst_o + , output logic inst_v_o + ); + + // parameter checks + if ($bits(bp_cce_inst_s) != cce_instr_width_gp) + $error("Param cce_instr_width_gp does not match width of bp_cce_inst_s"); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + bp_cfg_bus_s cfg_bus_cast_i; + assign cfg_bus_cast_i = cfg_bus_i; + + // Fetch PC Register + // This register has the same value as the instruction RAM's internal address register + logic [cce_pc_width_p-1:0] fetch_pc_r, fetch_pc_n; + assign fetch_pc_o = fetch_pc_r; + logic inst_v_r, inst_v_n; + assign inst_v_o = inst_v_r; + + logic ram_v_li; + bsg_mem_1rw_sync + #(.width_p(cce_instr_width_gp) + ,.els_p(num_cce_instr_ram_els_p) + ,.latch_last_read_p(1) + ) + inst_ram + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(ucode_v_i | ram_v_li) + ,.data_i(ucode_data_i) + ,.addr_i(ucode_v_i ? ucode_addr_i : fetch_pc_n) + ,.w_i(ucode_w_i) + ,.data_o(inst_o) + ); + + // Configuration Bus Microcode Data output + assign ucode_data_o = inst_o; + + + typedef enum logic [1:0] { + RESET + ,INIT + ,INIT_END + ,FETCH + } fetch_state_e; + + fetch_state_e fetch_state_r, fetch_state_n; + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) begin + if (reset_i) begin + fetch_state_r <= RESET; + fetch_pc_r <= '0; + inst_v_r <= '0; + end else begin + fetch_state_r <= fetch_state_n; + fetch_pc_r <= fetch_pc_n; + inst_v_r <= inst_v_n; + end + end + + always_comb begin + fetch_state_n = fetch_state_r; + fetch_pc_n = '0; + inst_v_n = '0; + + ram_v_li = '0; + + case (fetch_state_r) + RESET: begin + fetch_state_n = INIT; + end + INIT: begin + // If mode is uncached, the CCE operates in uncached mode + // and this module stays in the INIT state and does not fetch microcode + fetch_state_n = (cfg_bus_cast_i.cce_mode == e_cce_mode_normal) ? INIT_END : INIT; + end + INIT_END: begin + // This state gives an extra cycle for the RAM to finish the last write command that + // was sent on the config link, if it needs it. + fetch_state_n = FETCH; + fetch_pc_n = '0; + ram_v_li = 1'b1; + // first instruction will be valid + inst_v_n = 1'b1; + end + FETCH: begin + // fetch as long as current instruction in execute stage is not stalling + // RAM will hold last read + ram_v_li = ~stall_i; + + // Select the next instruction to fetch + // If the currently executing instruction is stalling, re-fetch the same instruction as + // last cycle. If there is no stall, but a mispredict use the the PC computed from EX stage + // in branch resolution logic. Otherwise, fetch the predicted fetch PC from the pre-decoder. + fetch_pc_n = stall_i + ? fetch_pc_r + : mispredict_i + ? branch_resolution_pc_i + : predicted_fetch_pc_i; + + // From the point of view of the Fetch stage, the next instruction fetched is always + // valid. It might be an incorrect fetch due to a mispredict, but the output of the + // instruction RAM will be a valid instruction. + inst_v_n = 1'b1; + + end + default: begin + fetch_state_n = RESET; + end + endcase + + + end +endmodule + diff --git a/designs/black-parrot/src/bp/bp_cce_inst_stall.sv b/designs/black-parrot/src/bp/bp_cce_inst_stall.sv new file mode 100644 index 0000000..9e37869 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_inst_stall.sv @@ -0,0 +1,111 @@ +/** + * + * Name: + * bp_cce_inst_stall.sv + * + * Description: + * The stall unit collects the current instruction and status of other functional units to + * determine whether or not a stall must occur. + * + * A stall prevents any changes to architectural state in the cycle asserted, and causes the + * current instruction to be replayed next cycle. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_inst_stall + import bp_me_pkg::*; + #() + (input bp_cce_inst_decoded_s decoded_inst_i + + // input queue valid signals + , input lce_req_v_i + , input lce_resp_v_i + , input mem_rev_v_i + , input pending_v_i + + // output queue valid&ready signals + , input lce_cmd_yumi_i + + , input mem_credits_empty_i + + // Messague Unit resource busy signals + // message unit is busy doing something - block all ucode interactions + , input msg_busy_i + , input msg_pending_w_busy_i + , input msg_lce_cmd_busy_i + , input msg_lce_resp_busy_i + , input msg_mem_rev_busy_i + , input msg_spec_r_busy_i + , input msg_dir_w_busy_i + , input msg_mem_fwd_stall_i + + // Directory busy (e.g., processing read) + , input dir_busy_i + + // Stall outputs + , output logic stall_o + ); + + wire [$bits(bp_cce_inst_src_q_e)-1:0] wfq_v_vec = {lce_req_v_i, lce_resp_v_i, mem_rev_v_i, pending_v_i}; + wire [$bits(bp_cce_inst_src_q_e)-1:0] wfq_mask = decoded_inst_i.imm[0+:$bits(bp_cce_inst_src_q_e)]; + + always_comb begin + stall_o = 1'b0; + + // Microcode instruction stalls - resource not ready + + // Message receive + // Handshake is v->yumi for headers from fifo + stall_o |= (decoded_inst_i.lce_req_yumi & ~lce_req_v_i); + stall_o |= (decoded_inst_i.lce_resp_yumi & ~lce_resp_v_i); + stall_o |= (decoded_inst_i.mem_rev_yumi & ~mem_rev_v_i); + stall_o |= (decoded_inst_i.pending_yumi & ~pending_v_i); + + // Pop Header + stall_o |= (decoded_inst_i.poph & (~lce_req_v_i & (decoded_inst_i.popq_qsel == e_src_q_sel_lce_req))); + stall_o |= (decoded_inst_i.poph & (~lce_resp_v_i & (decoded_inst_i.popq_qsel == e_src_q_sel_lce_resp))); + stall_o |= (decoded_inst_i.poph & (~mem_rev_v_i & (decoded_inst_i.popq_qsel == e_src_q_sel_mem_rev))); + + // Pop Data - TODO: not fully implemented + stall_o |= (decoded_inst_i.popd & (~lce_req_v_i & (decoded_inst_i.popq_qsel == e_src_q_sel_lce_req))); + stall_o |= (decoded_inst_i.popd & (~lce_resp_v_i & (decoded_inst_i.popq_qsel == e_src_q_sel_lce_resp))); + stall_o |= (decoded_inst_i.popd & (~mem_rev_v_i & (decoded_inst_i.popq_qsel == e_src_q_sel_mem_rev))); + + // Message send + // Handshake is r&v + stall_o |= (decoded_inst_i.lce_cmd_v & ~lce_cmd_yumi_i); + // memory command stall is indicated directly by a signal from message unit + stall_o |= (decoded_inst_i.mem_fwd_v & msg_mem_fwd_stall_i); + // sending a memory command requires a memory credit + stall_o |= (decoded_inst_i.mem_fwd_v & mem_credits_empty_i); + + // Wait for queue operation + stall_o |= (decoded_inst_i.wfq_v & ~(|(wfq_mask & wfq_v_vec))); + + + // Functional Unit induced stalls + + // Directory is busy after a read - be safe and block execution until read is done + stall_o |= dir_busy_i; + + // Message unit is stalling all ucode, i.e., invalidation instruction is executing + stall_o |= msg_busy_i; + + // Message Unit Structural Hazards + stall_o |= (decoded_inst_i.pending_w_v & msg_pending_w_busy_i); + stall_o |= (decoded_inst_i.lce_cmd_v & msg_lce_cmd_busy_i); + stall_o |= (decoded_inst_i.lce_resp_yumi & msg_lce_resp_busy_i); + stall_o |= (decoded_inst_i.mem_rev_yumi & msg_mem_rev_busy_i); + stall_o |= (decoded_inst_i.spec_r_v & msg_spec_r_busy_i); + stall_o |= (decoded_inst_i.dir_w_v & msg_dir_w_busy_i); + stall_o |= (decoded_inst_i.dir_r_v & msg_dir_w_busy_i); + + // only stall on valid instruction + stall_o &= decoded_inst_i.v; + + end + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_msg.sv b/designs/black-parrot/src/bp/bp_cce_msg.sv new file mode 100644 index 0000000..e803e30 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_msg.sv @@ -0,0 +1,912 @@ +/** + * + * Name: + * bp_cce_msg.sv + * + * Description: + * This module handles sending and receiving of all messages in the CCE. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_msg + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Derived parameters + , localparam block_size_in_bytes_lp = (bedrock_block_width_p/8) + , localparam lg_block_size_in_bytes_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_lp) + , localparam lg_num_lce_lp = `BSG_SAFE_CLOG2(num_lce_p) + + // number of way groups managed by this CCE + , localparam num_way_groups_lp = `BSG_CDIV(cce_way_groups_p, num_cce_p) + , localparam lg_num_way_groups_lp = `BSG_SAFE_CLOG2(num_way_groups_lp) + + // Interface Widths + , localparam mshr_width_lp = `bp_cce_mshr_width(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + ) + (input clk_i + , input reset_i + + // Configuration Interface + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + // inbound headers use valid->yumi + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input [bedrock_fill_width_p-1:0] lce_req_data_i + , input lce_req_v_i + , output logic lce_req_yumi_o + , input lce_req_new_i + , input lce_req_last_i + + , input [lce_resp_header_width_lp-1:0] lce_resp_header_i + , input [bedrock_fill_width_p-1:0] lce_resp_data_i + , input lce_resp_v_i + , output logic lce_resp_yumi_o + , input lce_resp_new_i + , input lce_resp_last_i + + , output logic [lce_cmd_header_width_lp-1:0] lce_cmd_header_o + , output logic [bedrock_fill_width_p-1:0] lce_cmd_data_o + , output logic lce_cmd_v_o + , input lce_cmd_ready_then_i + , input lce_cmd_new_i + , input lce_cmd_last_i + + // CCE-MEM Interface + // memory response stream pump in + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_yumi_o + , input mem_rev_new_i + , input mem_rev_last_i + + // memory command stream pump out + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_then_i + , input mem_fwd_new_i + , input mem_fwd_last_i + + // Input signals to feed output commands + , input [lce_id_width_p-1:0] lce_i + , input [paddr_width_p-1:0] addr_i + , input [lce_assoc_width_p-1:0] way_i + , input bp_coh_states_e coh_state_i + , input sharers_v_i + , input [num_lce_p-1:0] sharers_hits_i + , input [num_lce_p-1:0][lce_assoc_width_p-1:0] sharers_ways_i + + , input bp_cce_inst_decoded_s decoded_inst_i + , input [mshr_width_lp-1:0] mshr_i + , input [`bp_cce_inst_gpr_width-1:0] src_a_i + , input auto_fwd_msg_i + + // Pending bit write - only during auto-forward + , output logic pending_w_v_o + , output logic [paddr_width_p-1:0] pending_w_addr_o + , output logic pending_w_addr_bypass_o + , output logic pending_o + + // Spec Read Output + , output logic spec_r_v_o + , output logic [paddr_width_p-1:0] spec_r_addr_o + , output logic spec_r_addr_bypass_o + , input bp_cce_spec_s spec_bits_i + + // Directory write interface - when sending invalidates + , output logic [paddr_width_p-1:0] dir_addr_o + , output logic dir_addr_bypass_o + , output logic [lce_id_width_p-1:0] dir_lce_o + , output logic [lce_assoc_width_p-1:0] dir_way_o + , output bp_coh_states_e dir_coh_state_o + , output bp_cce_inst_minor_dir_op_e dir_w_cmd_o + , output logic dir_w_v_o + + // Busy signals + , output logic lce_cmd_busy_o + , output logic lce_resp_busy_o + , output logic mem_rev_busy_o + , output logic mem_fwd_stall_o + , output logic busy_o + + , output logic mem_credits_empty_o + + ); + + // LCE-CCE and Mem-CCE Interface + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + // MSHR + `declare_bp_cce_mshr_s(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + // LCE-CCE Interface structs + `bp_cast_i(bp_bedrock_lce_req_header_s, lce_req_header); + `bp_cast_o(bp_bedrock_lce_cmd_header_s, lce_cmd_header); + `bp_cast_i(bp_bedrock_lce_resp_header_s, lce_resp_header); + + `bp_cast_o(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_i(bp_bedrock_mem_rev_header_s, mem_rev_header); + + // Config bus + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + bp_cfg_bus_s cfg_bus_cast_i; + assign cfg_bus_cast_i = cfg_bus_i; + wire cce_normal_mode_li = (cfg_bus_cast_i.cce_mode == e_cce_mode_normal); + logic cce_normal_mode_r, cce_normal_mode_n; + + // MSHR casting + bp_cce_mshr_s mshr; + assign mshr = mshr_i; + + // address mask for block-aligned operations + wire [paddr_width_p-1:0] addr_block_mask = + {{(paddr_width_p-lg_block_size_in_bytes_lp){1'b1}} + , {(lg_block_size_in_bytes_lp){1'b0}} + }; + + // Counter for message send/receive + logic cnt_rst; + logic cnt_inc, cnt_dec; + logic [`BSG_WIDTH(num_lce_p+1)-1:0] cnt; + bsg_counter_up_down + #(.max_val_p(num_lce_p+1) + ,.init_val_p(0) + ,.max_step_p(1) + ) + counter + (.clk_i(clk_i) + ,.reset_i(reset_i | cnt_rst) + ,.up_i(cnt_inc) + ,.down_i(cnt_dec) + ,.count_o(cnt) + ); + + // memory command/response counter + logic [`BSG_WIDTH(dma_noc_max_credits_p)-1:0] mem_credit_count_lo; + bsg_flow_counter + #(.els_p(dma_noc_max_credits_p), .ready_THEN_valid_p(1)) + mem_credit_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + // memory commands consume credits + ,.v_i(mem_fwd_v_o & mem_fwd_last_i) + ,.ready_param_i(mem_fwd_ready_then_i) + // memory responses return credits + ,.yumi_i(mem_rev_yumi_o & mem_rev_last_i) + ,.count_o(mem_credit_count_lo) + ); + + wire mem_credits_empty = (mem_credit_count_lo == dma_noc_max_credits_p); + wire mem_credits_full = (mem_credit_count_lo == 0); + assign mem_credits_empty_o = mem_credits_empty; + + // Registers for inputs + logic [paddr_width_p-1:0] addr_r, addr_n; + + // One hot of request LCE ID + logic [num_lce_p-1:0] req_lce_id_one_hot; + bsg_decode + #(.num_out_p(num_lce_p)) + req_lce_id_to_one_hot + (.i(mshr.lce_id[0+:lg_num_lce_lp]) + ,.o(req_lce_id_one_hot) + ); + + // One hot of owner LCE ID + logic [num_lce_p-1:0] owner_lce_id_one_hot; + bsg_decode + #(.num_out_p(num_lce_p)) + owner_lce_id_to_one_hot + (.i(mshr.owner_lce_id[0+:lg_num_lce_lp]) + ,.o(owner_lce_id_one_hot) + ); + + // Extract index of first bit set in sharers hits + // Provides LCE ID to send invalidation to + logic [num_lce_p-1:0] pe_sharers_r, pe_sharers_n; + logic [lg_num_lce_lp-1:0] pe_lce_id; + logic pe_v; + bsg_priority_encode + #(.width_p(num_lce_p) + ,.lo_to_hi_p(1) + ) + sharers_pri_enc + (.i(pe_sharers_r) + ,.addr_o(pe_lce_id) + ,.v_o(pe_v) + ); + + logic [num_lce_p-1:0][lce_assoc_width_p-1:0] sharers_ways_r, sharers_ways_n; + + // Convert first index back to one hot + logic [num_lce_p-1:0] pe_lce_id_one_hot; + bsg_decode + #(.num_out_p(num_lce_p)) + pe_lce_id_to_one_hot + (.i(pe_lce_id) + ,.o(pe_lce_id_one_hot) + ); + + // CCE PMA - Mem responses + logic fwd_pma_cacheable_addr_lo; + bp_cce_pma + #(.bp_params_p(bp_params_p)) + fwd_pma + (.paddr_i(mem_fwd_header_cast_o.addr) + ,.cacheable_addr_o(fwd_pma_cacheable_addr_lo) + ); + + logic rev_pma_cacheable_addr_lo; + bp_cce_pma + #(.bp_params_p(bp_params_p)) + rev_pma + (.paddr_i(mem_rev_header_cast_i.addr) + ,.cacheable_addr_o(rev_pma_cacheable_addr_lo) + ); + + // Normal mode FSM states + enum logic [3:0] { + e_reset + ,e_uncached_only + ,e_ready + ,e_inv_cmd + ,e_inv_resp + ,e_error + } state_n, state_r; + + // Sequential Logic + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) begin + if (reset_i) begin + state_r <= e_reset; + pe_sharers_r <= '0; + sharers_ways_r <= '0; + addr_r <= '0; + cce_normal_mode_r <= '0; + end else begin + state_r <= state_n; + pe_sharers_r <= pe_sharers_n; + sharers_ways_r <= sharers_ways_n; + addr_r <= addr_n; + cce_normal_mode_r <= cce_normal_mode_n; + end + end + + // State Machines + // + // Output messages use ready->valid + // Input messages use valid->yumi + // + always_comb begin + + // Register next value defaults + state_n = state_r; + pe_sharers_n = pe_sharers_r; + sharers_ways_n = sharers_ways_r; + addr_n = addr_r; + cce_normal_mode_n = cce_normal_mode_r; + + // memory response stream pump + mem_rev_yumi_o = '0; + + // memory command stream pump + mem_fwd_header_cast_o = '0; + mem_fwd_header_cast_o.payload.src_did = cfg_bus_cast_i.did; + mem_fwd_data_o = '0; + mem_fwd_v_o = '0; + + // LCE request and response input control + lce_req_yumi_o = '0; + lce_resp_yumi_o = '0; + + // LCE command output control + lce_cmd_header_cast_o = '0; + lce_cmd_header_cast_o.payload.src_id = cfg_bus_cast_i.cce_id; + lce_cmd_header_cast_o.payload.src_did = cfg_bus_cast_i.did; + lce_cmd_data_o = '0; + lce_cmd_v_o = '0; + + // Pending bit write - only during auto-forward + pending_w_v_o = '0; + pending_w_addr_o = '0; + pending_w_addr_bypass_o = '0; + pending_o = '0; + + // Spec Read Output + spec_r_v_o = '0; + spec_r_addr_o = '0; + spec_r_addr_bypass_o = '0; + + // Directory write interface - when sending invalidates + dir_addr_o = '0; + dir_addr_bypass_o = '0; + dir_lce_o = '0; + dir_way_o = '0; + dir_coh_state_o = e_COH_I; + dir_w_cmd_o = e_wdp_op; + dir_w_v_o = '0; + + // Busy signals + lce_cmd_busy_o = '0; + lce_resp_busy_o = '0; + mem_rev_busy_o = '0; + mem_fwd_stall_o = '0; + // raised in uncached mode, during invalidate cmd/resp states, and during some mem_fwd + // message sends + busy_o = '0; + + // Counter control + cnt_inc = '0; + cnt_dec = '0; + cnt_rst = '0; + + // Mem Response auto-processing and forwarding to LCE Command logic + // The pending bit is written when the LCE Command header sends. + // The main FSM will stall if it wants to write to the pending bits in the same cycle. + + if (auto_fwd_msg_i | ~cce_normal_mode_r) begin + if (mem_rev_v_i) begin + + // Speculative access response + // Note: speculative access is only supported for cached read requests + if (mem_rev_header_cast_i.payload.speculative && mem_rev_header_cast_i.msg_type == e_bedrock_mem_rd) begin + // read from the speculative bits + spec_r_v_o = 1'b1; + spec_r_addr_o = mem_rev_header_cast_i.addr; + + if (spec_bits_i.spec) begin // speculation not resolved yet + // do nothing, wait for speculation to be resolved + // Note: this blocks memory responses behind the speculative response from being + // forwarded. However, the CCE will not move on to a new LCE request until it + // resolves the speculation for the current request. + + end // speculative bit sill set + + else if (spec_bits_i.squash) begin // speculation resolved, squash + // block ucode from using memory response + mem_rev_busy_o = 1'b1; + + // ack the first beat of the memory response since it doesn't need to be split + // into header and data, and do nothing with it + mem_rev_yumi_o = mem_rev_v_i; + + // decrement pending bit on last beat + // must be on last beat to prevent speculative bit read-write race + pending_w_v_o = mem_rev_yumi_o & mem_rev_last_i & rev_pma_cacheable_addr_lo; + pending_w_addr_o = mem_rev_header_cast_i.addr; + pending_o = 1'b0; + + end // squash + + else if (spec_bits_i.fwd_mod) begin // speculation resolved, forward with modified state + // inform ucode decode that this unit is using the LCE Command network + lce_cmd_busy_o = 1'b1; + mem_rev_busy_o = 1'b1; + + // send LCE command header, but don't ack the mem response beat since its data + // will send after the header sends. + lce_cmd_v_o = lce_cmd_ready_then_i & mem_rev_v_i; + mem_rev_yumi_o = lce_cmd_v_o; + + // command header + lce_cmd_header_cast_o.msg_type = e_bedrock_cmd_data; + lce_cmd_header_cast_o.addr = mem_rev_header_cast_i.addr; + lce_cmd_header_cast_o.size = mem_rev_header_cast_i.size; + + // command payload + // modify the coherence state + lce_cmd_header_cast_o.payload.dst_id = mem_rev_header_cast_i.payload.lce_id; + lce_cmd_header_cast_o.payload.way_id = mem_rev_header_cast_i.payload.way_id; + lce_cmd_header_cast_o.payload.src_did = mem_rev_header_cast_i.payload.src_did; + lce_cmd_header_cast_o.payload.state = bp_coh_states_e'(spec_bits_i.state); + + // command data + lce_cmd_data_o = mem_rev_data_i; + + // decrement pending bit on last beat + // must be on last beat to prevent speculative bit read-write race + pending_w_v_o = mem_rev_yumi_o & mem_rev_last_i & rev_pma_cacheable_addr_lo; + pending_w_addr_o = mem_rev_header_cast_i.addr; + pending_o = 1'b0; + + end // fwd_mod + + else begin // speculation resolved, forward unmodified + // forward the header this cycle + // forward data next cycle(s) + + // inform ucode decode that this unit is using the LCE Command network + lce_cmd_busy_o = 1'b1; + mem_rev_busy_o = 1'b1; + + // send LCE command header, but don't ack the mem response beat since its data + // will send after the header sends. + lce_cmd_v_o = lce_cmd_ready_then_i & mem_rev_v_i; + mem_rev_yumi_o = lce_cmd_v_o; + + // command header + lce_cmd_header_cast_o.msg_type = e_bedrock_cmd_data; + lce_cmd_header_cast_o.addr = mem_rev_header_cast_i.addr; + lce_cmd_header_cast_o.size = mem_rev_header_cast_i.size; + + // command payload + lce_cmd_header_cast_o.payload.dst_id = mem_rev_header_cast_i.payload.lce_id; + lce_cmd_header_cast_o.payload.way_id = mem_rev_header_cast_i.payload.way_id; + lce_cmd_header_cast_o.payload.src_did = mem_rev_header_cast_i.payload.src_did; + lce_cmd_header_cast_o.payload.state = mem_rev_header_cast_i.payload.state; + + // command data + lce_cmd_data_o = mem_rev_data_i; + + // decrement pending bit on last beat + // must be on last beat to prevent speculative bit read-write race + pending_w_v_o = mem_rev_yumi_o & mem_rev_last_i & rev_pma_cacheable_addr_lo; + pending_w_addr_o = mem_rev_header_cast_i.addr; + pending_o = 1'b0; + + end // forward unmodified + + end // speculative response + + // non-speculative memory access, forward directly to LCE + else if (mem_rev_header_cast_i.msg_type == e_bedrock_mem_rd) begin + // forward the header this cycle + // forward data next cycle(s) + + // inform ucode decode that this unit is using the LCE Command network + lce_cmd_busy_o = 1'b1; + mem_rev_busy_o = 1'b1; + + // send LCE command header, but don't ack the mem response beat since its data + // will send after the header sends. + lce_cmd_v_o = lce_cmd_ready_then_i & mem_rev_v_i; + mem_rev_yumi_o = lce_cmd_v_o; + + // command header + lce_cmd_header_cast_o.msg_type = mem_rev_header_cast_i.payload.uncached ? e_bedrock_cmd_uc_data : e_bedrock_cmd_data; + lce_cmd_header_cast_o.addr = mem_rev_header_cast_i.addr; + lce_cmd_header_cast_o.size = mem_rev_header_cast_i.size; + + // command payload + lce_cmd_header_cast_o.payload.dst_id = mem_rev_header_cast_i.payload.lce_id; + lce_cmd_header_cast_o.payload.way_id = mem_rev_header_cast_i.payload.way_id; + lce_cmd_header_cast_o.payload.src_did = mem_rev_header_cast_i.payload.src_did; + lce_cmd_header_cast_o.payload.state = mem_rev_header_cast_i.payload.state; + + // command data + lce_cmd_data_o = mem_rev_data_i; + + // decrement pending bit on last beat + // must be on last beat to prevent speculative bit read-write race + pending_w_v_o = mem_rev_yumi_o & mem_rev_last_i & rev_pma_cacheable_addr_lo; + pending_w_addr_o = mem_rev_header_cast_i.addr; + pending_o = 1'b0; + + end // rd, wr miss from LCE + + // non-speculative store response from memory + else if (mem_rev_header_cast_i.msg_type == e_bedrock_mem_wr) begin + // If the uncached bit is set, this response is to an uncached store + // and we need to forward an uc_st_done to the LCE. + // Otherwise, this response came from a writeback and is sunk at the CCE. + if (mem_rev_header_cast_i.payload.uncached) begin + // forward the header this cycle + // forward data next cycle(s) + + // inform ucode decode that this unit is using the LCE Command network + lce_cmd_busy_o = 1'b1; + mem_rev_busy_o = 1'b1; + + // handshaking + // r&v for LCE command header + // valid->yumi for mem response header + lce_cmd_v_o = lce_cmd_ready_then_i & mem_rev_v_i; + mem_rev_yumi_o = lce_cmd_v_o; + + // command header + lce_cmd_header_cast_o.msg_type = e_bedrock_cmd_uc_st_done; + lce_cmd_header_cast_o.addr = mem_rev_header_cast_i.addr; + // leave size as '0 equivalent, no data in this message + + // command payload + lce_cmd_header_cast_o.payload.dst_id = mem_rev_header_cast_i.payload.lce_id; + lce_cmd_header_cast_o.payload.src_did = mem_rev_header_cast_i.payload.src_did; + end else begin + mem_rev_busy_o = 1'b1; + mem_rev_yumi_o = mem_rev_v_i; + end + + // decrement pending bits if operating in normal mode and request was made + // to coherent memory space + // must be on last beat to prevent speculative bit read-write race + pending_w_v_o = mem_rev_yumi_o & mem_rev_last_i & rev_pma_cacheable_addr_lo; + pending_w_addr_o = mem_rev_header_cast_i.addr; + pending_o = 1'b0; + + end // wr + end // mem_rev handling + end // auto_fwd_i enabled or uncached only mode + + // Dequeue coherence ack when it arrives + // Does not conflict with other dequeues of LCE Response + // Decrements pending bit on arrival, so arbitrate with memory ports for access + if (lce_resp_v_i & (lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_coh_ack) & ~pending_w_v_o) begin + lce_resp_yumi_o = lce_resp_v_i; + lce_resp_busy_o = 1'b1; + // inform FSM that pending bit is being used + pending_w_v_o = lce_resp_yumi_o & lce_resp_last_i; + pending_w_addr_o = lce_resp_header_cast_i.addr; + pending_o = 1'b0; + end + + // Message FSM + unique case (state_r) + + e_reset: begin + state_n = e_uncached_only; + cce_normal_mode_n = 1'b0; + cnt_rst = 1'b1; + busy_o = 1'b1; + end // e_reset; + + // Uncached only mode + // This mode supports uncached rd/wr operations + // All of memory is treated as globally uncacheable in this mode + e_uncached_only: begin + // block ucode engine while in uncached only mode + busy_o = 1'b1; + + // clear the counters + cnt_rst = 1'b1; + + // transition to normal/coherent operation as soon as config bus indicates + if (cce_normal_mode_li) begin + // register that normal mode is active and all outstanding + // uncached accesses are complete + if (~cce_normal_mode_r & mem_credits_full) begin + cce_normal_mode_n = 1'b1; + state_n = e_ready; + end + + // only issue memory command if memory credit is available + // only process uncached requests + // cached requests will stall on the input port + // cached requests not allowed, go to error state and stall + end else if (lce_req_v_i + & ((lce_req_header_cast_i.msg_type.req == e_bedrock_req_rd_miss) + | (lce_req_header_cast_i.msg_type.req == e_bedrock_req_wr_miss))) begin + state_n = e_error; + + // uncached store + end else if (lce_req_v_i & (lce_req_header_cast_i.msg_type.req == e_bedrock_req_uc_wr)) begin + // first beat of memory command must include data + mem_fwd_v_o = mem_fwd_ready_then_i & ~mem_credits_empty; + lce_req_yumi_o = mem_fwd_v_o; + + // form message + mem_fwd_header_cast_o.addr = lce_req_header_cast_i.addr; + mem_fwd_header_cast_o.size = lce_req_header_cast_i.size; + mem_fwd_header_cast_o.msg_type.fwd = e_bedrock_mem_wr; + mem_fwd_header_cast_o.payload.lce_id = lce_req_header_cast_i.payload.src_id; + mem_fwd_header_cast_o.payload.src_did = lce_req_header_cast_i.payload.src_did; + mem_fwd_header_cast_o.payload.uncached = 1'b1; + mem_fwd_data_o = lce_req_data_i; + + mem_fwd_stall_o = ~lce_req_yumi_o; + + end // uncached store + + // uncached load + else if (lce_req_v_i & (lce_req_header_cast_i.msg_type.req == e_bedrock_req_uc_rd)) begin + // uncached load has no data + mem_fwd_v_o = mem_fwd_ready_then_i & ~mem_credits_empty; + lce_req_yumi_o = mem_fwd_v_o; + + mem_fwd_header_cast_o.addr = lce_req_header_cast_i.addr; + mem_fwd_header_cast_o.size = lce_req_header_cast_i.size; + mem_fwd_header_cast_o.payload.lce_id = lce_req_header_cast_i.payload.src_id; + mem_fwd_header_cast_o.payload.src_did = lce_req_header_cast_i.payload.src_did; + mem_fwd_header_cast_o.payload.uncached = 1'b1; + mem_fwd_header_cast_o.msg_type.fwd = e_bedrock_mem_rd; + + mem_fwd_stall_o = ~lce_req_yumi_o; + + end // uncached load + + // TODO: add amo support here + + end // e_uncached_only + + // This state processes ucode commands + e_ready: begin + + // Invalidation command + if (decoded_inst_i.inv_cmd_v) begin + // busy_o not raised this cycle, will raise next cycle after inv instruction is + // executed and captured by the message module. + state_n = e_inv_cmd; + // capture input address for use by invalidation routine + addr_n = addr_i; + // setup inputs for determining LCEs to invalidate + // Requesting LCE and the owner LCE (if present) are excluded + // Thus, only LCE's with the block in Shared (S) state are invalidated + pe_sharers_n = sharers_hits_i & ~req_lce_id_one_hot; + pe_sharers_n = (mshr.flags.cached_owned | mshr.flags.cached_forward) + ? pe_sharers_n & ~owner_lce_id_one_hot + : pe_sharers_n; + sharers_ways_n = sharers_ways_i; + // reset counter + cnt_rst = 1'b1; + end + + // Inbound messages - popq + // Note: popq assumes that inbound message data was drained + + // LCE Request + else if (decoded_inst_i.lce_req_yumi) begin + // NOTE: this pops only a single beat of the lce req + // Pop the request if it is valid and either not doing a pending bit write + // or doing a pending bit write and this module is not using the pending bit + // write port. + lce_req_yumi_o = lce_req_v_i + & ((decoded_inst_i.pending_w_v & ~pending_w_v_o) + | ~decoded_inst_i.pending_w_v); + + end + // LCE Response + else if (decoded_inst_i.lce_resp_yumi) begin + // NOTE: this pops only a single beat of the lce response + // Pop the response if it is valid and either not doing a pending bit write + // or doing a pending bit write and this module is not using the pending bit + // write port. + lce_resp_yumi_o = lce_resp_v_i + & ((decoded_inst_i.pending_w_v & ~pending_w_v_o) + | ~decoded_inst_i.pending_w_v); + + end + // Mem Response + else if (decoded_inst_i.mem_rev_yumi) begin + // NOTE: this pops only a single beat of the memory response + // Pop the response if it is valid and either not doing a pending bit write + // or doing a pending bit write and this module is not using the pending bit + // write port. + mem_rev_yumi_o = mem_rev_v_i + & ((decoded_inst_i.pending_w_v & ~pending_w_v_o) + | ~decoded_inst_i.pending_w_v); + + end + + // Outbound messages - pushq + + // Memory Fwd + else if (decoded_inst_i.mem_fwd_v) begin + + // Can only send Mem command if: + // Write port for pending bits isn't in use if pushq will write pending bit + if ((decoded_inst_i.pending_w_v & ~pending_w_v_o) + | ~decoded_inst_i.pending_w_v) begin + + // defaults + mem_fwd_header_cast_o.msg_type.fwd = decoded_inst_i.mem_fwd; + mem_fwd_header_cast_o.addr = addr_i; + mem_fwd_header_cast_o.size = mshr.msg_size; + mem_fwd_header_cast_o.payload.lce_id = lce_i; + mem_fwd_header_cast_o.payload.way_id = way_i; + mem_fwd_header_cast_o.payload.src_did = mshr.src_did; + mem_fwd_header_cast_o.payload.state = mshr.next_coh_state; + + // set speculative bit if instruction indicates it will be written + mem_fwd_header_cast_o.payload.speculative = decoded_inst_i.spec_w_v & decoded_inst_i.spec_v + & decoded_inst_i.spec_bits.spec; + + unique case (decoded_inst_i.mem_fwd) + e_bedrock_mem_rd: begin + // set uncached bit based on request property + mem_fwd_header_cast_o.payload.uncached = mshr.flags.uncached; + mem_fwd_v_o = mem_fwd_ready_then_i & ~mem_credits_empty; + // stall until the message send completes + mem_fwd_stall_o = ~(mem_fwd_v_o & mem_fwd_last_i); + end + + e_bedrock_mem_wr: begin + // connect data from LCE Req or Resp, as indicated by ucode instruction + if (decoded_inst_i.src_a.q == e_opd_lce_req_data) begin + // set the uncached bit when issuing an uncached store to memory so + // the response state machine knows to send an UC_ST_DONE to the LCE + mem_fwd_header_cast_o.payload.uncached = 1'b1; + mem_fwd_data_o = lce_req_data_i; + mem_fwd_v_o = mem_fwd_ready_then_i & lce_req_v_i & ~mem_credits_empty; + lce_req_yumi_o = mem_fwd_v_o; + end else begin + mem_fwd_data_o = lce_resp_data_i; + mem_fwd_v_o = mem_fwd_ready_then_i & lce_resp_v_i & ~mem_credits_empty; + lce_resp_yumi_o = mem_fwd_v_o; + end + + // stall until the message send completes + mem_fwd_stall_o = ~(mem_fwd_v_o & mem_fwd_last_i); + end + + e_bedrock_mem_pre: begin + // TODO: implement prefetch functionality + mem_fwd_header_cast_o.payload.prefetch = 1'b1; + end + + default: begin + end + endcase + end + + end // Memory Fwd + + // LCE Command + // Note: ucode may only send single-beat LCE command messages and may not write the + // pending bits. An instruction that attempts to write the pending bits may see its write + // get lost if the auto-fwd mechanism performs a write at the same time. This race is not + // handled by the design currently. Multi-beat messages may result in an interleaving + // of LCE command messages between the ucode and auto-fwd mechanism, which has undefined + // behavior. + else if (decoded_inst_i.lce_cmd_v) begin + + // Can only send LCE command if: + // Auto-forward isn't using LCE Command port + if (~lce_cmd_busy_o) begin + // handshake + // lce cmd header is r&v + lce_cmd_v_o = lce_cmd_ready_then_i; + + // all commands set src, dst, message type and address + // defaults provided here, but may be overridden below + lce_cmd_header_cast_o.payload.dst_id = lce_i; + lce_cmd_header_cast_o.payload.src_did = mem_rev_header_cast_i.payload.src_did; + lce_cmd_header_cast_o.msg_type.cmd = decoded_inst_i.lce_cmd; + lce_cmd_header_cast_o.addr = addr_i; + lce_cmd_data_o = mem_rev_data_i; + + if (decoded_inst_i.pushq_custom) begin + // TODO: implement custom push + lce_cmd_header_cast_o.size = decoded_inst_i.msg_size; + end else begin + // all commands set the way_id field + lce_cmd_header_cast_o.payload.way_id = way_i; + + // commands including a set state operation set the state field + if ((decoded_inst_i.lce_cmd == e_bedrock_cmd_st) + | (decoded_inst_i.lce_cmd == e_bedrock_cmd_st_wakeup) + | (decoded_inst_i.lce_cmd == e_bedrock_cmd_st_wb)) begin + // decoder sets coh_state_i to mshr.next_coh_state so any ST_X command + // that doesn't include a transfer needs to set mshr.next_coh_state + // to the correct value before sending the command (pushq) + lce_cmd_header_cast_o.payload.state = coh_state_i; + end + + if ((decoded_inst_i.lce_cmd == e_bedrock_cmd_st_tr) + | (decoded_inst_i.lce_cmd == e_bedrock_cmd_st_tr_wb)) begin + // when doing a set state + transfer, the state field indicates the + // next state for the owner LCE, and target_state (set below) will provide + // the state for the LCE receiving the transfer + lce_cmd_header_cast_o.payload.state = mshr.owner_coh_state; + end + + // Transfer commands set target, target way, and target state fields + // target is the requesting LCE in MSHR, and target_way is its LRU way + // target_state comes from coh_state_i, which is set to mshr.next_coh_state + if ((decoded_inst_i.lce_cmd == e_bedrock_cmd_tr) + | (decoded_inst_i.lce_cmd == e_bedrock_cmd_st_tr) + | (decoded_inst_i.lce_cmd == e_bedrock_cmd_st_tr_wb)) begin + lce_cmd_header_cast_o.payload.target_state = coh_state_i; + lce_cmd_header_cast_o.payload.target = mshr.lce_id; + lce_cmd_header_cast_o.payload.target_way_id = mshr.lru_way_id; + end + end + end + end // LCE Command + + end // e_ready + + e_inv_cmd: begin + busy_o = 1'b1; + + // try to send additional commands, but give priority to mem_rev auto-forward + if (~lce_cmd_busy_o) begin + // handshaking + // r&v for LCE command header + lce_cmd_v_o = lce_cmd_ready_then_i; + + lce_cmd_header_cast_o.msg_type.cmd = e_bedrock_cmd_inv; + + // leave size as '0 equivalent, no data sent for invalidate + + // destination and way come from sharers information + lce_cmd_header_cast_o.payload.dst_id = pe_lce_id; + lce_cmd_header_cast_o.payload.way_id = sharers_ways_r[pe_lce_id]; + + lce_cmd_header_cast_o.addr = addr_r & addr_block_mask; + + // Directory write command + dir_w_v_o = lce_cmd_v_o; + dir_w_cmd_o = e_wds_op; + dir_addr_o = addr_r & addr_block_mask; + dir_addr_bypass_o = '0; + dir_lce_o = {'0, pe_lce_id}; + dir_way_o = sharers_ways_r[pe_lce_id]; + dir_coh_state_o = e_COH_I; + + // message sent, increment count + cnt_inc = dir_w_v_o; + // only remove current LCE from sharers if command sends + pe_sharers_n = cnt_inc + ? (pe_sharers_r & ~pe_lce_id_one_hot) + : pe_sharers_r; + + // move to response state if none of the new sharer bits are set + // and the last command is sending this cycle + state_n = (cnt_inc & (pe_sharers_n == '0)) + ? e_inv_resp + : e_inv_cmd; + end // lce_cmd_busy + + // dequeue responses as they arrive + if (lce_resp_v_i & (lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_inv_ack)) begin + lce_resp_yumi_o = lce_resp_v_i; + cnt_dec = 1'b1; + end + + end // e_inv_cmd + + e_inv_resp: begin + busy_o = 1'b1; + if (cnt == '0) begin + state_n = e_ready; + end else begin + if (lce_resp_v_i & (lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_inv_ack)) begin + lce_resp_yumi_o = lce_resp_v_i; + if (cnt == 'd1) begin + state_n = e_ready; + cnt_rst = 1'b1; + end else begin + cnt_dec = 1'b1; + end + end + end + end // e_inv_resp + + e_error: begin + // message unit error, stall ucode engine + busy_o = 1'b1; + state_n = e_error; + end // e_error + + default: begin + state_n = e_reset; + end + endcase + + + end // always_comb + + // synopsys translate_off + always_ff @(negedge clk_i) begin + if (~reset_i) begin + if (state_r == e_inv_cmd & ~pe_v) begin + $error("bp_cce_msg bad sharers list for invalidate command"); + end // error + if (state_r == e_ready & decoded_inst_i.pushq_custom) begin + $error("custom push commands not yet supported"); + end + end // ~reset + end // always_ff + // synopsys translate_on + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_pending_bits.sv b/designs/black-parrot/src/bp/bp_cce_pending_bits.sv new file mode 100644 index 0000000..517c79d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_pending_bits.sv @@ -0,0 +1,130 @@ +/** + * + * Name: + * bp_cce_pending_bits.sv + * + * Description: + * This module contains the pending bits. Pending bits are actually small counters. + * The pending bit is unset if the count is 0, and set if the count is > 0. + * + * The pending bits are stored in flops and may be read asynchronously. Write to Read + * forwarding is supported. If both clear_i and pending_i are asserted, only the clear + * to 0 is processed. + * + * WARNING: the pending bit counters do not saturate and may over/underflow. Be careful! + * + * The width of address into bsg_hash_bank is log2(cce_way_groups_p), where cce_way_groups_p + * is the total number of way groups in the system. + * num_way_groups_p is the number of way groups managed by this CCE (or that number + * plus one in the event that there is not an even number of way groups per CCE). + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_pending_bits + import bp_common_pkg::*; + #(parameter `BSG_INV_PARAM(num_way_groups_p) + , parameter `BSG_INV_PARAM(cce_way_groups_p) + , parameter `BSG_INV_PARAM(num_cce_p) + , parameter `BSG_INV_PARAM(paddr_width_p) + , parameter `BSG_INV_PARAM(addr_offset_p) + , parameter `BSG_INV_PARAM(cce_id_width_p) + + // Default parameters + , parameter width_p = 3 // pending bit counter width + + // Derived parameters + , localparam lg_num_way_groups_lp = `BSG_SAFE_CLOG2(num_way_groups_p) + , localparam lg_cce_way_groups_lp = `BSG_SAFE_CLOG2(cce_way_groups_p) + , localparam hash_idx_width_lp = $clog2((2**lg_cce_way_groups_lp+num_cce_p-1)/num_cce_p) + + ) + (input clk_i + , input reset_i + + , input w_v_i + , input [paddr_width_p-1:0] w_addr_i + , input w_addr_bypass_hash_i + , input pending_i + , input clear_i + + , input r_v_i + , input [paddr_width_p-1:0] r_addr_i + , input r_addr_bypass_hash_i + + , output logic pending_o + + // Debug + , input [cce_id_width_p-1:0] cce_id_i + ); + + // Address to way group hashing + // The address to use as input starts at addr_offset_p and is lg_cce_way_groups_lp bits in length + logic [hash_idx_width_lp-1:0] r_wg_lo, w_wg_lo; + wire [lg_cce_way_groups_lp-1:0] r_addr_rev = {<< {r_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; + wire [lg_cce_way_groups_lp-1:0] w_addr_rev = {<< {w_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; + logic [lg_num_way_groups_lp-1:0] r_wg, w_wg; + + bsg_hash_bank + #(.banks_p(num_cce_p) // number of CCE's to spread way groups over + ,.width_p(lg_cce_way_groups_lp) // width of address input + ) + r_addr_hash + (.i(r_addr_rev) + ,.bank_o() + ,.index_o(r_wg_lo) + ); + + bsg_hash_bank + #(.banks_p(num_cce_p) // number of CCE's to spread way groups over + ,.width_p(lg_cce_way_groups_lp) // width of address input + ) + w_addr_hash + (.i(w_addr_rev) + ,.bank_o() + ,.index_o(w_wg_lo) + ); + + assign r_wg = (r_addr_bypass_hash_i) ? r_addr_i[0+:lg_num_way_groups_lp] + : r_wg_lo[0+:lg_num_way_groups_lp]; + assign w_wg = (w_addr_bypass_hash_i) ? w_addr_i[0+:lg_num_way_groups_lp] + : w_wg_lo[0+:lg_num_way_groups_lp]; + + // pending bits + logic [num_way_groups_p-1:0][width_p-1:0] pending_bits_r, pending_bits_n; + + always_ff @(posedge clk_i) begin + if (reset_i) begin + pending_bits_r <= '0; + end else begin + pending_bits_r <= pending_bits_n; + end + end + + always_comb begin + pending_bits_n = pending_bits_r; + if (w_v_i) begin + if (clear_i) begin + pending_bits_n[w_wg] = '0; + end + else begin + if (pending_i) begin // increment count + pending_bits_n[w_wg] = pending_bits_r[w_wg] + 'd1; + end else begin // decrement count + pending_bits_n[w_wg] = pending_bits_r[w_wg] - 'd1; + end + end + end + end + + // Pending bit output + // Normally, the output is determined by the read way group and comes from the flopped values + // If reading from the same way group that is being written, output the next value + assign pending_o = (r_v_i & w_v_i & (w_wg == r_wg)) + ? ~(pending_bits_n[r_wg] == 0) + : ~(pending_bits_r[r_wg] == 0); + +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_pending_bits) diff --git a/designs/black-parrot/src/bp/bp_cce_pma.sv b/designs/black-parrot/src/bp/bp_cce_pma.sv new file mode 100644 index 0000000..6848341 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_pma.sv @@ -0,0 +1,36 @@ +/** + * + * Name: + * bp_cce_pma.sv + * + * Description: + * This module defines the physical memory attributes (PMAs) obeyed by the CCE. + * The purpose is to define the cacheability properties of memory. + * + * Only cached, global memory is kept explicitly coherent (i.e., DRAM memory). All other memory + * is uncached. See the BlackParrot Platform Guide (docs/platform_guide.md) + * and the bp_common_pkg files in bp_common/src/include/ for more details on BlackParrot's + * platform memory maps. + * + * Uncacheable requests from an LCE are allowed to cacheable, global memory, and these requests + * will be kept coherent with all LCEs by invalidating (and writing back, if necessary) the block + * from all LCEs prior to performing the uncached operation. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_pma + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input [paddr_width_p-1:0] paddr_i + , output logic cacheable_addr_o + ); + + assign cacheable_addr_o = (paddr_i >= dram_base_addr_gp) && ~|paddr_i[paddr_width_p-1:caddr_width_p]; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_cce_reg.sv b/designs/black-parrot/src/bp/bp_cce_reg.sv new file mode 100644 index 0000000..1c8b911 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_reg.sv @@ -0,0 +1,379 @@ +/** + * + * Name: + * bp_cce_reg.sv + * + * Description: + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_reg + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Derived parameters + , localparam block_size_in_bytes_lp = (bedrock_block_width_p/8) + , localparam lg_block_size_in_bytes_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_lp) + + , localparam mshr_width_lp = `bp_cce_mshr_width(paddr_width_p, lce_id_width_p, cce_width_p, did_width_p, lce_assoc_p) + + // Interface Widths + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + ) + (input clk_i + , input reset_i + + // Control signals + , input bp_cce_inst_decoded_s decoded_inst_i + , input dir_lru_v_i + , input dir_addr_v_i + + , input stall_i + + // Data source inputs + , input [`bp_cce_inst_gpr_width-1:0] src_a_i + , input [`bp_cce_inst_gpr_width-1:0] alu_res_i + + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input lce_req_v_i + , input [lce_resp_header_width_lp-1:0] lce_resp_header_i + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + + // For RDP, output state of pending bits from read operation + , input pending_i + + // From Directory - RDW operation generates LRU Cached Exclusive flag and LRU entry address + , input bp_coh_states_e dir_lru_coh_state_i + , input [paddr_width_p-1:0] dir_lru_addr_i + // From Directory - RDE operation writes address to GPR + , input [paddr_width_p-1:0] dir_addr_i + , input bp_cce_inst_opd_gpr_e dir_addr_dst_gpr_i + + // From GAD unit - written on GAD ucode operation + , input [lce_assoc_width_p-1:0] gad_req_addr_way_i + , input [lce_id_width_p-1:0] gad_owner_lce_i + , input [lce_assoc_width_p-1:0] gad_owner_way_i + , input bp_coh_states_e gad_owner_coh_state_i + , input gad_replacement_flag_i + , input gad_upgrade_flag_i + , input gad_cached_shared_flag_i + , input gad_cached_exclusive_flag_i + , input gad_cached_modified_flag_i + , input gad_cached_owned_flag_i + , input gad_cached_forward_flag_i + + , input spec_sf_i + + // Register outputs + , output logic [mshr_width_lp-1:0] mshr_o + , output logic [`bp_cce_inst_num_gpr-1:0][`bp_cce_inst_gpr_width-1:0] gpr_o + , output bp_coh_states_e coh_state_o + , output logic auto_fwd_msg_o + + ); + + + // Interface Structs + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + bp_bedrock_lce_req_header_s lce_req_hdr; + bp_bedrock_lce_resp_header_s lce_resp_hdr; + bp_bedrock_mem_rev_header_s mem_rev_hdr; + + assign lce_req_hdr = lce_req_header_i; + assign lce_resp_hdr = lce_resp_header_i; + assign mem_rev_hdr = mem_rev_header_i; + + // Registers + `declare_bp_cce_mshr_s(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + bp_cce_mshr_s mshr_r, mshr_n; + logic [`bp_cce_inst_num_gpr-1:0][`bp_cce_inst_gpr_width-1:0] gpr_r; + logic [`bp_cce_inst_gpr_width-1:0] gpr_next; + bp_coh_states_e coh_state_r, coh_state_n; + logic auto_fwd_msg_r, auto_fwd_msg_n; + + assign mshr_o = mshr_r; + assign gpr_o = gpr_r; + assign coh_state_o = coh_state_r; + assign auto_fwd_msg_o = auto_fwd_msg_r; + + // CCE PMA - LCE requests + logic req_pma_cacheable_addr_lo; + bp_cce_pma + #(.bp_params_p(bp_params_p) + ) + req_pma + (.paddr_i(lce_req_hdr.addr) + ,.cacheable_addr_o(req_pma_cacheable_addr_lo) + ); + + // synopsys translate_off + always @(negedge clk_i) begin + if (~reset_i) begin + // Cacheable requests must target cacheable memory + assert(reset_i !== '0 || + !(lce_req_v_i && ~req_pma_cacheable_addr_lo + && ((lce_req_hdr.msg_type.req == e_bedrock_req_rd_miss) + || (lce_req_hdr.msg_type.req == e_bedrock_req_wr_miss)) + ) + ) else + $error("CCE PMA violation - cacheable requests must target cacheable memory"); + end + end + // synopsys translate_on + + // Write mask for GPRs + // This is by default the write mask from the decoded instruction, but it is also modified + // by the Directory on RDE operation to indicate which GPR the address from RDE is written to. + // On a stall, the mask is set to '0 by default. + logic [`bp_cce_inst_num_gpr-1:0] gpr_w_mask; + + // Move operation + wire mov_op = (decoded_inst_i.op == e_op_reg_data); + // Queue operation + wire queue_op = (decoded_inst_i.op == e_op_queue); + + // Flag next values + wire lce_req_rqf = (lce_req_hdr.msg_type.req == e_bedrock_req_wr_miss) + | (lce_req_hdr.msg_type.req == e_bedrock_req_uc_wr); + wire lce_req_ucf = (lce_req_hdr.msg_type.req == e_bedrock_req_uc_rd) + | (lce_req_hdr.msg_type.req == e_bedrock_req_uc_wr); + wire lce_resp_nwbf = (lce_resp_hdr.msg_type.resp == e_bedrock_resp_null_wb); + wire lce_req_nerf = (lce_req_hdr.payload.non_exclusive == e_bedrock_req_non_excl); + + // operation writes all flags in bulk + // branch flag ops only use e_opd_flags as source + // movgs or movis may use e_opd_flags as destination + wire write_all_flags = ((decoded_inst_i.dst_sel == e_dst_sel_special) + & (decoded_inst_i.dst.special == e_opd_flags)); + + // Combinational Logic - next values for registers and write masks + always_comb begin + // Default next values + // Note: whether the next value is written to the register depends on the + // write enable decisions in the sequential logic + mshr_n = mshr_r; + gpr_next = '0; + + // Auto Forward BP Coherence Messages + auto_fwd_msg_n = src_a_i[0]; + + // Default Coherence State Register + coh_state_n = bp_coh_states_e'(src_a_i[0+:$bits(bp_coh_states_e)]); + + // GPR Write Mask + gpr_w_mask = stall_i ? '0 : decoded_inst_i.gpr_w_v; + // RDE operation sets write mask bit for proper GPR destination + // this write only happens when ucode is stalling + if (dir_addr_v_i) begin + gpr_w_mask[dir_addr_dst_gpr_i[0+:`bp_cce_inst_gpr_sel_width]] = 1'b1; + end + + // GPRs + // By default, use the result from the ALU (ALU ops, Flag ALU ops) + gpr_next = alu_res_i; + // Directory read operation (while stalling) takes priority over the stalling instruction's + // decoding for gpr_next. If the stalling instruction is a move, but a directory read is + // happening, we want the directory read to determine the source, not the stalling move. + if (dir_addr_v_i) begin + gpr_next = {'0, dir_addr_i}; + // Move (including set flag) and queue ops use source A + end else if (mov_op | queue_op) begin + gpr_next = src_a_i; + end + + // MSHR + if (decoded_inst_i.mshr_clear) begin + mshr_n = '0; + mshr_n.next_coh_state = coh_state_r; + end else begin + // default to catch any unset fields + mshr_n = mshr_r; + + // LCE ID - from lce_req, lce_resp, mem_rev.payload, or move + // paddr - from lce_req, lce_resp, mem_rev, or move + // LRU Way ID - from lce_req or move + // Next Coh State - from move or mem_rev.payload + // Message Size - from lce_req or move + // Way ID - from move, GAD, or mem_rev + // Owner LCE ID - from GAD or move + // Owner Way ID - from GAD or move + // LRU paddr - from Directory or move + mshr_n.lce_id = src_a_i[0+:lce_id_width_p]; + mshr_n.src_did = src_a_i[lce_id_width_p+:did_width_p]; + mshr_n.paddr = src_a_i[0+:paddr_width_p]; + mshr_n.lru_way_id = src_a_i[0+:lce_assoc_width_p]; + mshr_n.next_coh_state = bp_coh_states_e'(src_a_i[0+:$bits(bp_coh_states_e)]); + mshr_n.lru_coh_state = bp_coh_states_e'(src_a_i[0+:$bits(bp_coh_states_e)]); + mshr_n.msg_size = bp_bedrock_msg_size_e'(src_a_i[0+:$bits(bp_bedrock_msg_size_e)]); + mshr_n.way_id = src_a_i[0+:lce_id_width_p]; + mshr_n.owner_lce_id = src_a_i[0+:lce_id_width_p]; + mshr_n.owner_way_id = src_a_i[0+:lce_assoc_width_p]; + mshr_n.owner_coh_state = bp_coh_states_e'(src_a_i[0+:$bits(bp_coh_states_e)]); + mshr_n.lru_paddr = src_a_i[0+:paddr_width_p]; + + // Flags - by default, next value comes from src_a + for (int i = 0; i < $bits(bp_cce_inst_flag_onehot_e); i=i+1) begin + mshr_n.flags[i] = src_a_i[0]; + end + + // Overrides from defaults - poph + if (decoded_inst_i.poph) begin + unique case (decoded_inst_i.popq_qsel) + e_src_q_sel_lce_req: begin + mshr_n.lce_id = lce_req_hdr.payload.src_id; + mshr_n.src_did = lce_req_hdr.payload.src_did; + mshr_n.paddr = lce_req_hdr.addr; + mshr_n.lru_way_id = lce_req_hdr.payload.lru_way_id; + mshr_n.msg_size = lce_req_hdr.size; + // flags written here must have their flag_w_v bit set by the decoder + mshr_n.flags.write_not_read = lce_req_rqf; + mshr_n.flags.uncached = lce_req_ucf; + mshr_n.flags.non_exclusive = lce_req_nerf; + mshr_n.flags.cacheable_address = req_pma_cacheable_addr_lo; + end + e_src_q_sel_lce_resp: begin + //mshr_n.lce_id = lce_resp_hdr.src_id; + //mshr_n.paddr = lce_resp_hdr.addr; + //mshr_n.msg_size = lce_resp_hdr.size; + mshr_n.flags.null_writeback = lce_resp_nwbf; + end + e_src_q_sel_mem_rev: begin + //mshr_n.lce_id = mem_rev_hdr.payload.lce_id; + //mshr_n.way_id = mem_rev_hdr.payload.way_id; + //mshr_n.paddr = mem_rev_hdr.addr; + //mshr_n.next_coh_state = mem_rev_hdr.payload.state; + //mshr_n.msg_size = mem_rev_hdr.size; + mshr_n.flags.speculative = mem_rev_hdr.payload.speculative; + end + default: begin + end + endcase + end // poph + + // Overrides from defaults - GAD + else if (decoded_inst_i.gad_v) begin + mshr_n.way_id = gad_req_addr_way_i; + mshr_n.owner_lce_id = gad_owner_lce_i; + mshr_n.owner_way_id = gad_owner_way_i; + mshr_n.owner_coh_state = gad_owner_coh_state_i; + mshr_n.flags.replacement = gad_replacement_flag_i; + mshr_n.flags.upgrade = gad_upgrade_flag_i; + mshr_n.flags.cached_shared = gad_cached_shared_flag_i; + mshr_n.flags.cached_exclusive = gad_cached_exclusive_flag_i; + mshr_n.flags.cached_modified = gad_cached_modified_flag_i; + mshr_n.flags.cached_owned = gad_cached_owned_flag_i; + mshr_n.flags.cached_forward = gad_cached_forward_flag_i; + end + + // Overrides from defaults - Directory + if (dir_lru_v_i) begin + mshr_n.lru_paddr = dir_lru_addr_i; + mshr_n.lru_coh_state = dir_lru_coh_state_i; + end + + // RDP instruction writes pending flag from pending bit read + if (decoded_inst_i.pending_r_v) begin + mshr_n.flags.pending = pending_i; + end + + // Spec Bits Read writes speculative flag from spec bit read + if (decoded_inst_i.spec_r_v) begin + mshr_n.flags.speculative = spec_sf_i; + end + + // Flag operation - ldflags, ldflagsi, or clf + if (write_all_flags) begin + mshr_n.flags = src_a_i[0+:$bits(bp_cce_inst_flag_onehot_e)]; + end + + end // MSHR + + end // always_comb + + // Sequential Logic - register state updates + always_ff @(posedge clk_i) + begin + if (reset_i) begin + mshr_r <= '0; + gpr_r <= '0; + coh_state_r <= e_COH_I; + auto_fwd_msg_r <= 1'b1; + end else begin + + // Auto Forward Message control - only from move, only when not stalling + if (~stall_i & decoded_inst_i.auto_fwd_msg_w_v) begin + auto_fwd_msg_r <= auto_fwd_msg_n; + end + + // Default Coherence State for MSHR - only from move, only when not stalling + if (~stall_i & decoded_inst_i.coh_state_w_v) begin + coh_state_r <= coh_state_n; + end + + // GPR + for (int i = 0; i < `bp_cce_inst_num_gpr; i=i+1) begin + if (gpr_w_mask[i]) begin + gpr_r[i] <= gpr_next; + end + end + + // MSHR writes - these occur on a per MSHR item basis + // By default, all fields can only be written while not stalling + + if (~stall_i & decoded_inst_i.mshr_clear) begin + mshr_r <= mshr_n; + end else begin + if (~stall_i & decoded_inst_i.lce_w_v) begin + mshr_r.lce_id <= mshr_n.lce_id; + mshr_r.src_did <= mshr_n.src_did; + end + if (~stall_i & decoded_inst_i.addr_w_v) begin + mshr_r.paddr <= mshr_n.paddr; + end + if (~stall_i & decoded_inst_i.way_w_v) begin + mshr_r.way_id <= mshr_n.way_id; + end + if (~stall_i & decoded_inst_i.lru_way_w_v) begin + mshr_r.lru_way_id <= mshr_n.lru_way_id; + end + // LRU address can be written while stalling, from directory + if ((~stall_i & decoded_inst_i.lru_addr_w_v) | dir_lru_v_i) begin + mshr_r.lru_paddr <= mshr_n.lru_paddr; + end + if ((~stall_i & decoded_inst_i.lru_coh_state_w_v) | dir_lru_v_i) begin + mshr_r.lru_coh_state <= mshr_n.lru_coh_state; + end + if (~stall_i & decoded_inst_i.owner_lce_w_v) begin + mshr_r.owner_lce_id <= mshr_n.owner_lce_id; + end + if (~stall_i & decoded_inst_i.owner_way_w_v) begin + mshr_r.owner_way_id <= mshr_n.owner_way_id; + end + if (~stall_i & decoded_inst_i.owner_coh_state_w_v) begin + mshr_r.owner_coh_state <= mshr_n.owner_coh_state; + end + if (~stall_i & decoded_inst_i.next_coh_state_w_v) begin + mshr_r.next_coh_state <= mshr_n.next_coh_state; + end + for (int i = 0; i < $bits(bp_cce_inst_flag_onehot_e); i=i+1) begin + if (~stall_i & decoded_inst_i.flag_w_v[i]) begin + mshr_r.flags[i] <= mshr_n.flags[i]; + end + end + if (~stall_i & decoded_inst_i.msg_size_w_v) begin + mshr_r.msg_size <= mshr_n.msg_size; + end + end + + end // else + end // always_ff + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_spec_bits.sv b/designs/black-parrot/src/bp/bp_cce_spec_bits.sv new file mode 100644 index 0000000..c0b8788 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_spec_bits.sv @@ -0,0 +1,129 @@ +/** + * + * Name: + * bp_cce_spec_bits.sv + * + * Description: + * This module contains the metadata required for speculative memory accesses. + * + * These bits are stored in flops and may be read asynchronously. + * + * The width of address into bsg_hash_bank is log2(cce_way_groups_p), where cce_way_groups_p + * is the total number of way groups in the system. + * num_way_groups_p is the number of way groups managed by this CCE (or that number + * plus one in the event that there is not an even number of way groups per CCE). + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_spec_bits + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter `BSG_INV_PARAM(num_way_groups_p) + , parameter `BSG_INV_PARAM(cce_way_groups_p) + , parameter `BSG_INV_PARAM(num_cce_p) + , parameter `BSG_INV_PARAM(paddr_width_p) + , parameter `BSG_INV_PARAM(addr_offset_p) + + // Derived parameters + , localparam lg_num_way_groups_lp = `BSG_SAFE_CLOG2(num_way_groups_p) + , localparam lg_cce_way_groups_lp = `BSG_SAFE_CLOG2(cce_way_groups_p) + , localparam hash_idx_width_lp = $clog2((2**lg_cce_way_groups_lp+num_cce_p-1)/num_cce_p) + + ) + (input clk_i + , input reset_i + + // Write port + , input w_v_i + , input [paddr_width_p-1:0] w_addr_i + , input w_addr_bypass_hash_i + + , input spec_v_i + , input squash_v_i + , input fwd_mod_v_i + , input state_v_i + , input bp_cce_spec_s spec_i + + // Read port + , input r_v_i + , input [paddr_width_p-1:0] r_addr_i + , input r_addr_bypass_hash_i + + , output bp_cce_spec_s spec_o + + ); + + // Address to way group hashing + logic [hash_idx_width_lp-1:0] r_wg_lo, w_wg_lo; + wire [lg_cce_way_groups_lp-1:0] r_addr_rev = {<< {r_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; + wire [lg_cce_way_groups_lp-1:0] w_addr_rev = {<< {w_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; + logic [lg_num_way_groups_lp-1:0] r_wg, w_wg; + + bsg_hash_bank + #(.banks_p(num_cce_p) // number of CCE's to spread way groups over + ,.width_p(lg_cce_way_groups_lp) // width of address input + ) + r_addr_hash + (.i(r_addr_rev) + ,.bank_o() + ,.index_o(r_wg_lo) + ); + + bsg_hash_bank + #(.banks_p(num_cce_p) // number of CCE's to spread way groups over + ,.width_p(lg_cce_way_groups_lp) // width of address input + ) + w_addr_hash + (.i(w_addr_rev) + ,.bank_o() + ,.index_o(w_wg_lo) + ); + + assign r_wg = (r_addr_bypass_hash_i) ? r_addr_i[0+:lg_num_way_groups_lp] + : r_wg_lo[0+:lg_num_way_groups_lp]; + assign w_wg = (w_addr_bypass_hash_i) ? w_addr_i[0+:lg_num_way_groups_lp] + : w_wg_lo[0+:lg_num_way_groups_lp]; + + // speculation metadata bits + bp_cce_spec_s [num_way_groups_p-1:0] spec_bits_r, spec_bits_n; + + always_ff @(posedge clk_i) begin + if (reset_i) begin + spec_bits_r <= '0; + end else begin + spec_bits_r <= spec_bits_n; + end + end + + always_comb begin + if (reset_i) begin + spec_bits_n = '0; + end else begin + spec_bits_n = spec_bits_r; + if (w_v_i) begin + if (spec_v_i) begin + spec_bits_n[w_wg].spec = spec_i.spec; + end + if (squash_v_i) begin + spec_bits_n[w_wg].squash = spec_i.squash; + end + if (fwd_mod_v_i) begin + spec_bits_n[w_wg].fwd_mod = spec_i.fwd_mod; + end + if (state_v_i) begin + spec_bits_n[w_wg].state = spec_i.state; + end + end + end + end + + // Output + wire unused0 = r_v_i; + assign spec_o = spec_bits_r[r_wg]; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_cce_spec_bits) diff --git a/designs/black-parrot/src/bp/bp_cce_src_sel.sv b/designs/black-parrot/src/bp/bp_cce_src_sel.sv new file mode 100644 index 0000000..de0a550 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_src_sel.sv @@ -0,0 +1,394 @@ +/** + * + * Name: + * bp_cce_src_sel.sv + * + * Description: + * Source select module for inputs to ALU, Branch unit, directory, GAD, messages, etc. + * This module encapsulates common selection/mux logic so it isn't scattered + * about the top level CCE module. + * + * It generates src_a, src_b, addr, lce, way, lru_way, and state signals. + * + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_src_sel + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Derived parameters + , localparam mshr_width_lp = `bp_cce_mshr_width(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + // number of way groups managed by this CCE + , localparam num_way_groups_lp = `BSG_CDIV(cce_way_groups_p, num_cce_p) + , localparam lg_num_way_groups_lp = `BSG_SAFE_CLOG2(num_way_groups_lp) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + ) + (// Select signals for src_a and src_b - from decoded instruction + input bp_cce_inst_src_sel_e src_a_sel_i + , input bp_cce_inst_src_u src_a_i + , input bp_cce_inst_src_sel_e src_b_sel_i + , input bp_cce_inst_src_u src_b_i + + // Select signals for functional unit inputs (directory, gad, pending, message, etc.) + , input bp_cce_inst_mux_sel_addr_e addr_sel_i + , input bp_cce_inst_mux_sel_lce_e lce_sel_i + , input bp_cce_inst_mux_sel_way_e way_sel_i + , input bp_cce_inst_mux_sel_way_e lru_way_sel_i + , input bp_cce_inst_mux_sel_coh_state_e coh_state_sel_i + + // Data sources - from registered data and functional units + , input [cfg_bus_width_lp-1:0] cfg_bus_i + , input [mshr_width_lp-1:0] mshr_i + , input [`bp_cce_inst_num_gpr-1:0][`bp_cce_inst_gpr_width-1:0] gpr_i + , input [`bp_cce_inst_gpr_width-1:0] imm_i + , input auto_fwd_msg_i + , input bp_coh_states_e coh_state_default_i + , input [num_lce_p-1:0] sharers_hits_i + , input [num_lce_p-1:0][lce_assoc_width_p-1:0] sharers_ways_i + , input bp_coh_states_e [num_lce_p-1:0] sharers_coh_states_i + , input mem_rev_v_i + , input lce_resp_v_i + , input lce_req_v_i + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input [lce_resp_header_width_lp-1:0] lce_resp_header_i + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + // note: data inputs are not guarded by valid + // software must ensure data is valid before use + // note: if data width > cce gpr width, only least significant cce gpr width bits of + // data input are used and sent to src_a|b_o + , input [bedrock_fill_width_p-1:0] lce_req_data_i + , input [bedrock_fill_width_p-1:0] lce_resp_data_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + + // Source A and B outputs + , output logic [`bp_cce_inst_gpr_width-1:0] src_a_o + , output logic [`bp_cce_inst_gpr_width-1:0] src_b_o + + // FU Select Outputs + , output logic [paddr_width_p-1:0] addr_o + , output logic addr_bypass_o + , output logic [lce_id_width_p-1:0] lce_o + , output logic [lce_assoc_width_p-1:0] way_o + , output logic [lce_assoc_width_p-1:0] lru_way_o + , output bp_coh_states_e state_o + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + bp_cfg_bus_s cfg_bus_cast; + assign cfg_bus_cast = cfg_bus_i; + + `declare_bp_cce_mshr_s(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + bp_cce_mshr_s mshr; + assign mshr = mshr_i; + + // LCE-CCE and Mem-CCE Interface + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + // Message casting + bp_bedrock_lce_req_header_s lce_req_header_li; + bp_bedrock_lce_resp_header_s lce_resp_header_li; + bp_bedrock_mem_rev_header_s mem_rev_header_li; + + assign lce_req_header_li = lce_req_header_i; + assign lce_resp_header_li = lce_resp_header_i; + assign mem_rev_header_li = mem_rev_header_i; + + always_comb begin + src_a_o = '0; + unique case (src_a_sel_i) + e_src_sel_gpr: begin + unique case (src_a_i.gpr) + e_opd_r0: src_a_o = gpr_i[e_opd_r0]; + e_opd_r1: src_a_o = gpr_i[e_opd_r1]; + e_opd_r2: src_a_o = gpr_i[e_opd_r2]; + e_opd_r3: src_a_o = gpr_i[e_opd_r3]; + e_opd_r4: src_a_o = gpr_i[e_opd_r4]; + e_opd_r5: src_a_o = gpr_i[e_opd_r5]; + e_opd_r6: src_a_o = gpr_i[e_opd_r6]; + e_opd_r7: src_a_o = gpr_i[e_opd_r7]; + default: src_a_o = '0; + endcase + end + e_src_sel_flag: begin + unique case (src_a_i.flag) + e_opd_rqf: src_a_o[0] = mshr.flags.write_not_read; + e_opd_ucf: src_a_o[0] = mshr.flags.uncached; + e_opd_nerf: src_a_o[0] = mshr.flags.non_exclusive; + e_opd_nwbf: src_a_o[0] = mshr.flags.null_writeback; + e_opd_pf: src_a_o[0] = mshr.flags.pending; + e_opd_sf: src_a_o[0] = mshr.flags.speculative; + e_opd_csf: src_a_o[0] = mshr.flags.cached_shared; + e_opd_cef: src_a_o[0] = mshr.flags.cached_exclusive; + e_opd_cmf: src_a_o[0] = mshr.flags.cached_modified; + e_opd_cof: src_a_o[0] = mshr.flags.cached_owned; + e_opd_cff: src_a_o[0] = mshr.flags.cached_forward; + e_opd_rf: src_a_o[0] = mshr.flags.replacement; + e_opd_uf: src_a_o[0] = mshr.flags.upgrade; + e_opd_arf: src_a_o[0] = mshr.flags.atomic; + e_opd_anrf: src_a_o[0] = mshr.flags.atomic_no_return; + e_opd_rcf: src_a_o[0] = mshr.flags.cacheable_address; + default: src_a_o = '0; + endcase + end + e_src_sel_special: begin + unique case (src_a_i.special) + e_opd_req_lce: src_a_o[0+:did_width_p+lce_id_width_p] = {mshr.src_did, mshr.lce_id}; + e_opd_req_addr: src_a_o[0+:paddr_width_p] = mshr.paddr; + e_opd_req_way: src_a_o[0+:lce_assoc_width_p] = mshr.way_id; + e_opd_lru_addr: src_a_o[0+:paddr_width_p] = mshr.lru_paddr; + e_opd_lru_way: src_a_o[0+:lce_assoc_width_p] = mshr.lru_way_id; + e_opd_owner_lce: src_a_o[0+:lce_id_width_p] = mshr.owner_lce_id; + e_opd_owner_way: src_a_o[0+:lce_assoc_width_p] = mshr.owner_way_id; + e_opd_next_coh_state: src_a_o[0+:$bits(bp_coh_states_e)] = mshr.next_coh_state; + e_opd_flags: src_a_o[0+:$bits(bp_cce_flags_s)] = mshr.flags & imm_i[0+:$bits(bp_cce_flags_s)]; + e_opd_msg_size: src_a_o[0+:$bits(bp_bedrock_msg_size_e)] = mshr.msg_size; + e_opd_lru_coh_state: src_a_o[0+:$bits(bp_coh_states_e)] = mshr.lru_coh_state; + e_opd_owner_coh_state: src_a_o[0+:$bits(bp_coh_states_e)] = mshr.owner_coh_state; + e_opd_sharers_hit: src_a_o[0] = sharers_hits_i[gpr_i[src_b_i.gpr[0+:`bp_cce_inst_gpr_sel_width]]]; + e_opd_sharers_way: src_a_o[0+:lce_assoc_width_p] = sharers_ways_i[gpr_i[src_b_i.gpr[0+:`bp_cce_inst_gpr_sel_width]]]; + e_opd_sharers_state: src_a_o[0+:$bits(bp_coh_states_e)] = sharers_coh_states_i[gpr_i[src_b_i.gpr[0+:`bp_cce_inst_gpr_sel_width]]]; + default: src_a_o = '0; + endcase + end + e_src_sel_param: begin + unique case (src_a_i.param) + e_opd_cce_id: src_a_o[0+:cce_id_width_p] = cfg_bus_cast.cce_id; + e_opd_num_lce: src_a_o[0+:lce_id_width_p] = num_lce_p[0+:lce_id_width_p+1]; + e_opd_num_cce: src_a_o[0+:cce_id_width_p] = num_cce_p[0+:cce_id_width_p+1]; + e_opd_num_wg: src_a_o[0+:lg_num_way_groups_lp] = num_way_groups_lp[0+:lg_num_way_groups_lp]; + e_opd_auto_fwd_msg: src_a_o[0] = auto_fwd_msg_i; + e_opd_coh_state_default: src_a_o[0+:$bits(bp_coh_states_e)] = coh_state_default_i; + default: src_a_o = '0; + endcase + end + e_src_sel_queue: begin + unique case (src_a_i.q) + e_opd_mem_rev_v: src_a_o[0] = mem_rev_v_i; + e_opd_lce_resp_v: src_a_o[0] = lce_resp_v_i; + e_opd_pending_v: src_a_o = '0; + e_opd_lce_req_v: src_a_o[0] = lce_req_v_i; + e_opd_lce_resp_type: src_a_o[0+:$bits(bp_bedrock_resp_type_e)] = lce_resp_header_li.msg_type.resp; + e_opd_mem_rev_type: src_a_o[0+:$bits(bp_bedrock_rev_type_e)] = mem_rev_header_li.msg_type.rev; + e_opd_lce_resp_data: src_a_o = lce_resp_data_i[0+:`bp_cce_inst_gpr_width]; + e_opd_mem_rev_data: src_a_o = mem_rev_data_i[0+:`bp_cce_inst_gpr_width]; + e_opd_lce_req_data: src_a_o = lce_req_data_i[0+:`bp_cce_inst_gpr_width]; + default: src_a_o = '0; + endcase + end + e_src_sel_imm: begin + src_a_o = imm_i; + end + e_src_sel_zero: begin + src_a_o = '0; + end + default: begin + src_a_o = '0; + end + endcase // src_a + + src_b_o = '0; + unique case (src_b_sel_i) + e_src_sel_gpr: begin + unique case (src_b_i.gpr) + e_opd_r0: src_b_o = gpr_i[e_opd_r0]; + e_opd_r1: src_b_o = gpr_i[e_opd_r1]; + e_opd_r2: src_b_o = gpr_i[e_opd_r2]; + e_opd_r3: src_b_o = gpr_i[e_opd_r3]; + e_opd_r4: src_b_o = gpr_i[e_opd_r4]; + e_opd_r5: src_b_o = gpr_i[e_opd_r5]; + e_opd_r6: src_b_o = gpr_i[e_opd_r6]; + e_opd_r7: src_b_o = gpr_i[e_opd_r7]; + default: src_b_o = '0; + endcase + end + e_src_sel_flag: begin + unique case (src_b_i.flag) + e_opd_rqf: src_b_o[0] = mshr.flags.write_not_read; + e_opd_ucf: src_b_o[0] = mshr.flags.uncached; + e_opd_nerf: src_b_o[0] = mshr.flags.non_exclusive; + e_opd_nwbf: src_b_o[0] = mshr.flags.null_writeback; + e_opd_pf: src_b_o[0] = mshr.flags.pending; + e_opd_sf: src_b_o[0] = mshr.flags.speculative; + e_opd_csf: src_b_o[0] = mshr.flags.cached_shared; + e_opd_cef: src_b_o[0] = mshr.flags.cached_exclusive; + e_opd_cmf: src_b_o[0] = mshr.flags.cached_modified; + e_opd_cof: src_b_o[0] = mshr.flags.cached_owned; + e_opd_cff: src_b_o[0] = mshr.flags.cached_forward; + e_opd_rf: src_b_o[0] = mshr.flags.replacement; + e_opd_uf: src_b_o[0] = mshr.flags.upgrade; + e_opd_arf: src_b_o[0] = mshr.flags.atomic; + e_opd_anrf: src_b_o[0] = mshr.flags.atomic_no_return; + e_opd_rcf: src_b_o[0] = mshr.flags.cacheable_address; + default: src_b_o = '0; + endcase + end + e_src_sel_special: begin + unique case (src_b_i.special) + e_opd_req_lce: src_b_o[0+:lce_id_width_p] = mshr.lce_id; + e_opd_req_addr: src_b_o[0+:paddr_width_p] = mshr.paddr; + e_opd_req_way: src_b_o[0+:lce_assoc_width_p] = mshr.way_id; + e_opd_lru_addr: src_b_o[0+:paddr_width_p] = mshr.lru_paddr; + e_opd_lru_way: src_b_o[0+:lce_assoc_width_p] = mshr.lru_way_id; + e_opd_owner_lce: src_b_o[0+:lce_id_width_p] = mshr.owner_lce_id; + e_opd_owner_way: src_b_o[0+:lce_assoc_width_p] = mshr.owner_way_id; + e_opd_next_coh_state: src_b_o[0+:$bits(bp_coh_states_e)] = mshr.next_coh_state; + e_opd_flags: src_b_o[0+:$bits(bp_cce_flags_s)] = mshr.flags & imm_i[0+:$bits(bp_cce_flags_s)]; + e_opd_msg_size: src_b_o[0+:$bits(bp_bedrock_msg_size_e)] = mshr.msg_size; + e_opd_lru_coh_state: src_b_o[0+:$bits(bp_coh_states_e)] = mshr.lru_coh_state; + e_opd_owner_coh_state: src_b_o[0+:$bits(bp_coh_states_e)] = mshr.owner_coh_state; + // Sharers vectors as source b is not supported + //e_opd_sharers_hit: + //e_opd_sharers_way: + //e_opd_sharers_state: + default: src_b_o = '0; + endcase + end + e_src_sel_param: begin + unique case (src_b_i.param) + e_opd_cce_id: src_b_o[0+:cce_id_width_p] = cfg_bus_cast.cce_id; + e_opd_num_lce: src_b_o[0+:lce_id_width_p] = num_lce_p[0+:lce_id_width_p+1]; + e_opd_num_cce: src_b_o[0+:cce_id_width_p] = num_cce_p[0+:cce_id_width_p+1]; + e_opd_num_wg: src_b_o[0+:lg_num_way_groups_lp] = num_way_groups_lp[0+:lg_num_way_groups_lp]; + e_opd_auto_fwd_msg: src_b_o[0] = auto_fwd_msg_i; + e_opd_coh_state_default: src_b_o[0+:$bits(bp_coh_states_e)] = coh_state_default_i; + default: src_b_o = '0; + endcase + end + e_src_sel_queue: begin + unique case (src_b_i.q) + e_opd_mem_rev_v: src_b_o[0] = mem_rev_v_i; + e_opd_lce_resp_v: src_b_o[0] = lce_resp_v_i; + e_opd_pending_v: src_b_o = '0; + e_opd_lce_req_v: src_b_o[0] = lce_req_v_i; + e_opd_lce_resp_type: src_b_o[0+:$bits(bp_bedrock_resp_type_e)] = lce_resp_header_li.msg_type.resp; + e_opd_mem_rev_type: src_b_o[0+:$bits(bp_bedrock_rev_type_e)] = mem_rev_header_li.msg_type.rev; + e_opd_lce_resp_data: src_b_o = lce_resp_data_i[0+:`bp_cce_inst_gpr_width]; + e_opd_mem_rev_data: src_b_o = mem_rev_data_i[0+:`bp_cce_inst_gpr_width]; + e_opd_lce_req_data: src_b_o = lce_req_data_i[0+:`bp_cce_inst_gpr_width]; + default: src_b_o = '0; + endcase + end + e_src_sel_imm: begin + src_b_o = imm_i; + end + e_src_sel_zero: begin + src_b_o = '0; + end + default: src_b_o = '0; + endcase //src_b + + // addr_sel + unique case (addr_sel_i) + e_mux_sel_addr_r0: addr_o = gpr_i[e_opd_r0][0+:paddr_width_p]; + e_mux_sel_addr_r1: addr_o = gpr_i[e_opd_r1][0+:paddr_width_p]; + e_mux_sel_addr_r2: addr_o = gpr_i[e_opd_r2][0+:paddr_width_p]; + e_mux_sel_addr_r3: addr_o = gpr_i[e_opd_r3][0+:paddr_width_p]; + e_mux_sel_addr_r4: addr_o = gpr_i[e_opd_r4][0+:paddr_width_p]; + e_mux_sel_addr_r5: addr_o = gpr_i[e_opd_r5][0+:paddr_width_p]; + e_mux_sel_addr_r6: addr_o = gpr_i[e_opd_r6][0+:paddr_width_p]; + e_mux_sel_addr_r7: addr_o = gpr_i[e_opd_r7][0+:paddr_width_p]; + e_mux_sel_addr_mshr_req: addr_o = mshr.paddr; + e_mux_sel_addr_mshr_lru: addr_o = mshr.lru_paddr; + e_mux_sel_addr_lce_req: addr_o = lce_req_header_li.addr; + e_mux_sel_addr_lce_resp: addr_o = lce_resp_header_li.addr; + e_mux_sel_addr_mem_rev: addr_o = mem_rev_header_li.addr; + e_mux_sel_addr_pending: addr_o = '0; + e_mux_sel_addr_0: addr_o = '0; + default: addr_o = '0; + endcase + + // address bypass - only for GPR or constant 0 as source + unique case (addr_sel_i) + e_mux_sel_addr_r0, e_mux_sel_addr_r1, e_mux_sel_addr_r2, e_mux_sel_addr_r3 + ,e_mux_sel_addr_r4, e_mux_sel_addr_r5, e_mux_sel_addr_r6, e_mux_sel_addr_r7 + , e_mux_sel_addr_0: addr_bypass_o = 1'b1; + default: addr_bypass_o = 1'b0; + endcase + + // lce_sel + unique case (lce_sel_i) + e_mux_sel_lce_r0: lce_o = gpr_i[e_opd_r0][0+:lce_id_width_p]; + e_mux_sel_lce_r1: lce_o = gpr_i[e_opd_r1][0+:lce_id_width_p]; + e_mux_sel_lce_r2: lce_o = gpr_i[e_opd_r2][0+:lce_id_width_p]; + e_mux_sel_lce_r3: lce_o = gpr_i[e_opd_r3][0+:lce_id_width_p]; + e_mux_sel_lce_r4: lce_o = gpr_i[e_opd_r4][0+:lce_id_width_p]; + e_mux_sel_lce_r5: lce_o = gpr_i[e_opd_r5][0+:lce_id_width_p]; + e_mux_sel_lce_r6: lce_o = gpr_i[e_opd_r6][0+:lce_id_width_p]; + e_mux_sel_lce_r7: lce_o = gpr_i[e_opd_r7][0+:lce_id_width_p]; + e_mux_sel_lce_mshr_req: lce_o = mshr.lce_id; + e_mux_sel_lce_mshr_owner: lce_o = mshr.owner_lce_id; + e_mux_sel_lce_lce_req: lce_o = lce_req_header_li.payload.src_id; + e_mux_sel_lce_lce_resp: lce_o = lce_resp_header_li.payload.src_id; + e_mux_sel_lce_mem_rev: lce_o = mem_rev_header_li.payload.lce_id; + e_mux_sel_lce_pending: lce_o = '0; + e_mux_sel_lce_0: lce_o = '0; + default: lce_o = '0; + endcase + + // way_sel + unique case (way_sel_i) + e_mux_sel_way_r0: way_o = gpr_i[e_opd_r0][0+:lce_assoc_width_p]; + e_mux_sel_way_r1: way_o = gpr_i[e_opd_r1][0+:lce_assoc_width_p]; + e_mux_sel_way_r2: way_o = gpr_i[e_opd_r2][0+:lce_assoc_width_p]; + e_mux_sel_way_r3: way_o = gpr_i[e_opd_r3][0+:lce_assoc_width_p]; + e_mux_sel_way_r4: way_o = gpr_i[e_opd_r4][0+:lce_assoc_width_p]; + e_mux_sel_way_r5: way_o = gpr_i[e_opd_r5][0+:lce_assoc_width_p]; + e_mux_sel_way_r6: way_o = gpr_i[e_opd_r6][0+:lce_assoc_width_p]; + e_mux_sel_way_r7: way_o = gpr_i[e_opd_r7][0+:lce_assoc_width_p]; + e_mux_sel_way_mshr_req: way_o = mshr.way_id; + e_mux_sel_way_mshr_owner: way_o = mshr.owner_way_id; + e_mux_sel_way_mshr_lru: way_o = mshr.lru_way_id; + e_mux_sel_way_sh_way: way_o = sharers_ways_i[gpr_i[src_a_i.gpr[0+:`bp_cce_inst_gpr_sel_width]]]; + e_mux_sel_way_0: way_o = '0; + default: way_o = '0; + endcase + + // lru_way_sel + unique case (lru_way_sel_i) + e_mux_sel_way_r0: lru_way_o = gpr_i[e_opd_r0][0+:lce_assoc_width_p]; + e_mux_sel_way_r1: lru_way_o = gpr_i[e_opd_r1][0+:lce_assoc_width_p]; + e_mux_sel_way_r2: lru_way_o = gpr_i[e_opd_r2][0+:lce_assoc_width_p]; + e_mux_sel_way_r3: lru_way_o = gpr_i[e_opd_r3][0+:lce_assoc_width_p]; + e_mux_sel_way_r4: lru_way_o = gpr_i[e_opd_r4][0+:lce_assoc_width_p]; + e_mux_sel_way_r5: lru_way_o = gpr_i[e_opd_r5][0+:lce_assoc_width_p]; + e_mux_sel_way_r6: lru_way_o = gpr_i[e_opd_r6][0+:lce_assoc_width_p]; + e_mux_sel_way_r7: lru_way_o = gpr_i[e_opd_r7][0+:lce_assoc_width_p]; + e_mux_sel_way_mshr_req: lru_way_o = mshr.way_id; + e_mux_sel_way_mshr_owner: lru_way_o = mshr.owner_way_id; + e_mux_sel_way_mshr_lru: lru_way_o = mshr.lru_way_id; + e_mux_sel_way_sh_way: lru_way_o = sharers_ways_i[gpr_i[src_a_i.gpr[0+:`bp_cce_inst_gpr_sel_width]]]; + e_mux_sel_way_0: lru_way_o = '0; + default: lru_way_o = '0; + endcase + + // coh_state_sel + unique case (coh_state_sel_i) + e_mux_sel_coh_r0: state_o = bp_coh_states_e'(gpr_i[e_opd_r0][0+:$bits(bp_coh_states_e)]); + e_mux_sel_coh_r1: state_o = bp_coh_states_e'(gpr_i[e_opd_r1][0+:$bits(bp_coh_states_e)]); + e_mux_sel_coh_r2: state_o = bp_coh_states_e'(gpr_i[e_opd_r2][0+:$bits(bp_coh_states_e)]); + e_mux_sel_coh_r3: state_o = bp_coh_states_e'(gpr_i[e_opd_r3][0+:$bits(bp_coh_states_e)]); + e_mux_sel_coh_r4: state_o = bp_coh_states_e'(gpr_i[e_opd_r4][0+:$bits(bp_coh_states_e)]); + e_mux_sel_coh_r5: state_o = bp_coh_states_e'(gpr_i[e_opd_r5][0+:$bits(bp_coh_states_e)]); + e_mux_sel_coh_r6: state_o = bp_coh_states_e'(gpr_i[e_opd_r6][0+:$bits(bp_coh_states_e)]); + e_mux_sel_coh_r7: state_o = bp_coh_states_e'(gpr_i[e_opd_r7][0+:$bits(bp_coh_states_e)]); + e_mux_sel_coh_next_coh_state: state_o = mshr.next_coh_state; + e_mux_sel_coh_lru_coh_state: state_o = mshr.lru_coh_state; + e_mux_sel_sharer_state: state_o = sharers_coh_states_i[gpr_i[src_a_i.gpr[0+:$bits(bp_coh_states_e)]]]; + e_mux_sel_coh_owner_coh_state: state_o = mshr.owner_coh_state; + e_mux_sel_coh_inst_imm: state_o = bp_coh_states_e'(imm_i[0+:$bits(bp_coh_states_e)]); + default: state_o = e_COH_I; + endcase + + end // always_comb + +endmodule diff --git a/designs/black-parrot/src/bp/bp_cce_wrapper.sv b/designs/black-parrot/src/bp/bp_cce_wrapper.sv new file mode 100644 index 0000000..8351ee8 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_cce_wrapper.sv @@ -0,0 +1,122 @@ +/** + * + * Name: + * bp_cce_wrapper.sv + * + * Description: + * This is the top level module for the CCE. + * + * The LCE-CCE Interfaces use the BedRock Burst protocol. + * The CCE-MEM Intercaces use the BedRock Stream protocol + * + * It instantiates either the microcode or FSM CCE, based on the param in bp_params_p. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_cce_wrapper + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Interface Widths + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + ) + (input clk_i + , input reset_i + + // Configuration Interface + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // ucode programming interface, synchronous read, direct connection to RAM + , input ucode_v_i + , input ucode_w_i + , input [cce_pc_width_p-1:0] ucode_addr_i + , input [cce_instr_width_gp-1:0] ucode_data_i + , output logic [cce_instr_width_gp-1:0] ucode_data_o + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input [bedrock_fill_width_p-1:0] lce_req_data_i + , input lce_req_v_i + , output logic lce_req_ready_and_o + + , input [lce_resp_header_width_lp-1:0] lce_resp_header_i + , input [bedrock_fill_width_p-1:0] lce_resp_data_i + , input lce_resp_v_i + , output logic lce_resp_ready_and_o + + , output logic [lce_cmd_header_width_lp-1:0] lce_cmd_header_o + , output logic [bedrock_fill_width_p-1:0] lce_cmd_data_o + , output logic lce_cmd_v_o + , input lce_cmd_ready_and_i + + // CCE-MEM Interface + // BedRock Stream protocol: ready&valid + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + ); + + // Config Interface + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + + // Config bus casting + bp_cfg_bus_s cfg_bus_cast_i; + assign cfg_bus_cast_i = cfg_bus_i; + + if (cce_type_p == e_cce_ucode) begin : ucode + bp_cce + #(.bp_params_p(bp_params_p)) + cce + (.*); + end else if (cce_type_p == e_cce_fsm) begin : fsm + bp_cce_fsm + #(.bp_params_p(bp_params_p)) + cce + (.*); + end + + // parameter checks + + // cache organization + // all caches must have the same block size, which must equal CCE block size + // cache assoc and sets must be pow2 + if (icache_block_width_p != bedrock_block_width_p) $error("icache block width must match cce block width"); + if (!(`BSG_IS_POW2(icache_assoc_p) && `BSG_IS_POW2(icache_sets_p))) + $error("I$ sets and assoc must be power of two"); + if (dcache_block_width_p != bedrock_block_width_p) $error("dcache block width must match cce block width"); + if (!(`BSG_IS_POW2(dcache_assoc_p) && `BSG_IS_POW2(dcache_sets_p))) + $error("D$ sets and assoc must be power of two"); + // acclereator caches + if ((num_cacc_p) > 0 && (acache_block_width_p != bedrock_block_width_p)) $error("acache block width must match cce block width"); + if ((num_cacc_p > 0) && !(`BSG_IS_POW2(acache_assoc_p))) + $error("A$ assoc must be power of two or 0"); + if ((num_cacc_p > 0) && !(`BSG_IS_POW2(acache_sets_p))) + $error("A$ sets must be power of two or 0"); + + // coherence system block width is pow2 and between 64 and 1024 bits + if (!(`BSG_IS_POW2(bedrock_block_width_p) || bedrock_block_width_p < 64 || bedrock_block_width_p > 1024)) + $error("invalid CCE block width"); + + // way groups + if (!(`BSG_IS_POW2(cce_way_groups_p))) $error("Number of way groups must be a power of two"); + if (cce_way_groups_p < 1) $error("There must be at least one way group"); + + // bedrock data width must be pow2 between 64-bits and CCE block size + if (bedrock_fill_width_p < 64 || bedrock_fill_width_p > bedrock_block_width_p + || !(`BSG_IS_POW2(bedrock_fill_width_p))) + $error("CCE requires bedrock data width of between 64-bits and block width and power of 2 bits"); + +endmodule diff --git a/designs/black-parrot/src/bp/bp_common_accelerator_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_accelerator_pkgdef.svh new file mode 100644 index 0000000..c19bede --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_accelerator_pkgdef.svh @@ -0,0 +1,18 @@ +`ifndef BP_COMMON_ACCELERATOR_PKGDEF_SVH +`define BP_COMMON_ACCELERATOR_PKGDEF_SVH + + //vector-dot-product accelerator CSR indexes + localparam inputa_ptr_csr_idx_gp = 20'h0_0000; + localparam inputb_ptr_csr_idx_gp = 20'h0_0008; + localparam input_len_csr_idx_gp = 20'h0_0010; + localparam start_cmd_csr_idx_gp = 20'h0_0018; + localparam res_status_csr_idx_gp = 20'h0_0020; + localparam res_ptr_csr_idx_gp = 20'h0_0028; + localparam res_len_csr_idx_gp = 20'h0_0030; + localparam operation_csr_idx_gp = 20'h0_0038; + + + //loopback accelerator CSR indexes + localparam accel_wr_cnt_csr_idx_gp = 20'h0_0000; + +`endif diff --git a/designs/black-parrot/src/bp/bp_common_addr_defines.svh b/designs/black-parrot/src/bp/bp_common_addr_defines.svh new file mode 100644 index 0000000..6058fff --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_addr_defines.svh @@ -0,0 +1,27 @@ +`ifndef BP_COMMON_ADDR_DEFINES_SVH +`define BP_COMMON_ADDR_DEFINES_SVH + + `define declare_bp_memory_map(paddr_width_mp, daddr_width_mp) \ + typedef struct packed \ + { \ + logic [paddr_width_mp-daddr_width_mp-1:0] hio; \ + logic [daddr_width_mp-1:0] daddr; \ + } bp_global_addr_s; \ + \ + typedef struct packed \ + { \ + logic [paddr_width_mp-tile_id_width_gp-dev_id_width_gp-dev_addr_width_gp-1:0] \ + nonlocal; \ + logic [tile_id_width_gp-1:0] tile; \ + logic [dev_id_width_gp-1:0] dev; \ + logic [dev_addr_width_gp-1:0] addr; \ + } bp_local_addr_s + + `define bp_addr_is_aligned(addr_mp, num_bytes_mp) \ + (!(|{ addr_mp[$clog2(num_bytes_mp)-1:0] })) + + `define bp_addr_align(addr_mp, num_bytes_mp) \ + ((addr_mp >> $clog2(num_bytes_mp)) << $clog2(num_bytes_mp)) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_addr_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_addr_pkgdef.svh new file mode 100644 index 0000000..b530b91 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_addr_pkgdef.svh @@ -0,0 +1,30 @@ +`ifndef BP_COMMON_ADDR_PKGDEF +`define BP_COMMON_ADDR_PKGDEF + + // TODO: These could be parameterizable, but there are some constraints of + // of bit placement within the local uncached space. + // TL;DR 16MB ought to be enough for anyone + localparam tile_id_width_gp = 7; + localparam dev_id_width_gp = 4; + localparam dev_addr_width_gp = 20; + + localparam core_offset_width_gp = dev_addr_width_gp + dev_id_width_gp; + + localparam host_dev_gp = 1; + localparam cfg_dev_gp = 2; + localparam clint_dev_gp = 3; + localparam cache_dev_gp = 4; + + // 0x00_0(nnnN)(D)(A_AAAA) + localparam host_dev_base_addr_gp = 32'h0010_0000; + localparam cfg_dev_base_addr_gp = 32'h0020_0000; + localparam clint_dev_base_addr_gp = 32'h0030_0000; + localparam cache_dev_base_addr_gp = 32'h0040_0000; + + // TODO: This is hardcoded for a 32-bit DRAM address, will need to be adjusted + // for a different address space + localparam boot_base_addr_gp = 40'h00_0011_0000; + localparam dram_base_addr_gp = 40'h00_8000_0000; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_aviary_cfg_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_aviary_cfg_pkgdef.svh new file mode 100644 index 0000000..689931d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_aviary_cfg_pkgdef.svh @@ -0,0 +1,493 @@ + +`ifndef BP_COMMON_AVIARY_CFG_PKGDEF_SVH +`define BP_COMMON_AVIARY_CFG_PKGDEF_SVH + + // Suitably high enough to not run out of configs. + localparam max_cfgs = 128; + localparam lg_max_cfgs = $clog2(max_cfgs); + + // Configuration enums + typedef enum logic [3:0] + { + e_cfg_enabled = 4'b0000 + ,e_cfg_coherent = 4'b0001 + ,e_cfg_writeback = 4'b0010 + ,e_cfg_word_tracking = 4'b0011 + ,e_cfg_lr_sc = 4'b0100 + ,e_cfg_amo_swap = 4'b0101 + ,e_cfg_amo_fetch_logic = 4'b0110 + ,e_cfg_amo_fetch_arithmetic = 4'b0111 + ,e_cfg_hit_under_miss = 4'b1000 + ,e_cfg_misaligned = 4'b1001 + } bp_cache_features_e; + + typedef enum logic + { + e_basic = 1'b0 + ,e_catchup = 1'b1 + } bp_integer_support_e; + + typedef enum logic [1:0] + { + e_idiv = 2'b00 + ,e_imul = 2'b01 + ,e_imulh = 2'b10 + ,e_idiv2b = 2'b11 + } bp_muldiv_support_e; + + typedef enum logic [1:0] + { + e_fma = 2'b00 + ,e_fdivsqrt = 2'b01 + ,e_fdivsqrt2b = 2'b10 + } bp_fpu_support_e; + + typedef enum logic [1:0] + { + e_zba = 2'b00 + ,e_zbb = 2'b01 + ,e_zbc = 2'b10 + ,e_zbs = 2'b11 + } bp_bitmanip_support_e; + + typedef enum logic [15:0] + { + e_sacc_none = 0 + ,e_sacc_vdp = 1 + ,e_sacc_scratchpad = 2 + } bp_sacc_type_e; + + typedef enum logic [15:0] + { + e_cacc_none = 0 + ,e_cacc_vdp = 1 + } bp_cacc_type_e; + + typedef enum logic [1:0] + { + e_cce_uce = 0 + ,e_cce_fsm = 1 + ,e_cce_ucode = 2 + ,e_cce_hybrid = 3 + } bp_cce_type_e; + + typedef struct packed + { + // Dimensions of the different complexes + // Core Complex may be any integer unsigned (though has only been validated up to 4x4) + // All other Complexes are 1-dimensional + // [ ] + // [ I/O Complex ] + // [ ] + // + // [ ] [ ] [ ] + // [ Streaming Accelerator Complex ] [ Core Complex ] [ Coherent Accelerator Complex ] + // [ ] [ ] [ ] + // + // [ ] + // [ Memory Complex ] + // [ ] + // + integer unsigned cc_x_dim; + integer unsigned cc_y_dim; + integer unsigned ic_y_dim; + integer unsigned mc_y_dim; + integer unsigned cac_x_dim; + integer unsigned sac_x_dim; + + // The type of accelerator in the accelerator complexes, selected out of bp_cacc_type_e/bp_sacc_type_e + // Only supports homogeneous configurations + integer unsigned cacc_type; + integer unsigned sacc_type; + + // Number of CCEs/LCEs in the system. Must be consistent within complex dimensions + integer unsigned num_cce; + integer unsigned num_lce; + + // Virtual address width + // Only tested for SV39 (39-bit virtual address) + integer unsigned vaddr_width; + // Physical address width + // Only tested for 40-bit physical address + integer unsigned paddr_width; + // DRAM address width + // The max size of the connected DRAM i.e. cached address space + // Only tested for 32-bit cacheable address (4 GB space, with 2 GB local I/O) + integer unsigned daddr_width; + // Cacheable address width + // The max size cached by the L1 caches of the system + integer unsigned caddr_width; + // Address space ID width + // Currently unused, so set to 1 bit + integer unsigned asid_width; + + // Branch metadata information for the Front End + // Must be kept consistent with FE + integer unsigned branch_metadata_fwd_width; + integer unsigned ras_idx_width; + integer unsigned btb_tag_width; + integer unsigned btb_idx_width; + // bht_row_els is a physically-derived parameter. It describes the number + // of entries in a single row of the BHT RAM. There are 2 bits per entry. + // The tradeoff here is a wider RAM is most likely higher performance, + // but we need to carry that extra metadata throughout the pipeline to + // maintain 1r1w throughput without a RMW. + // Ghist is the global history width, which in our gselect + // Thus, the true BHT dimensions are (bht_idx_width+ghist_width)x(2*bht_row_els) + integer unsigned bht_idx_width; + integer unsigned bht_row_els; + integer unsigned ghist_width; + + // Capacity of the Instruction/Data TLBs + integer unsigned itlb_els_4k; + integer unsigned itlb_els_2m; + integer unsigned itlb_els_1g; + integer unsigned dtlb_els_4k; + integer unsigned dtlb_els_2m; + integer unsigned dtlb_els_1g; + + // I$ cache features + integer unsigned icache_features; + // I$ parameterizations + integer unsigned icache_sets; + integer unsigned icache_assoc; + integer unsigned icache_block_width; + integer unsigned icache_fill_width; + integer unsigned icache_data_width; + integer unsigned icache_mshr; + + // D$ cache features + integer unsigned dcache_features; + // D$ parameterizations + integer unsigned dcache_sets; + integer unsigned dcache_assoc; + integer unsigned dcache_block_width; + integer unsigned dcache_fill_width; + integer unsigned dcache_data_width; + integer unsigned dcache_mshr; + + // A$ cache features + integer unsigned acache_features; + // A$ parameterizations + integer unsigned acache_sets; + integer unsigned acache_assoc; + integer unsigned acache_block_width; + integer unsigned acache_fill_width; + integer unsigned acache_data_width; + integer unsigned acache_mshr; + + // CCE selection and parameters + // cce_type defined by bp_cce_type_e + integer unsigned cce_type; + // Determines the size of the CCE instruction RAM + integer unsigned cce_pc_width; + // The width of the coherence protocol block + integer unsigned bedrock_block_width; + // The width of the coherence protocol beats + integer unsigned bedrock_fill_width; + + // L2 slice parameters (per core) + // L2 cache features + integer unsigned l2_features; + integer unsigned l2_slices; + // Number of L2 banks present in the slice + integer unsigned l2_banks; + integer unsigned l2_data_width; + integer unsigned l2_sets; + integer unsigned l2_assoc; + integer unsigned l2_block_width; + integer unsigned l2_fill_width; + + // Size of the issue queue + integer unsigned fe_queue_fifo_els; + // Size of the cmd queue + integer unsigned fe_cmd_fifo_els; + // Integer support in the system. It is a bitmask with: + // bit 0: basic alu + // bit 1: catchup alu + integer unsigned integer_support; + // MULDIV support in the system. It is a bitmask with: + // bit 0: div + // bit 1: mul + // bit 2: iterative mulh + // bit 3: 2b iterative div + integer unsigned muldiv_support; + // Whether to support FPU + // bit 0: fma + // bit 1: iterative fdivsqrt + // bit 2: 2b iterative fdivsqrt + integer unsigned fpu_support; + // Whether to enable the "c" extension. + integer unsigned compressed_support; + // Whether to enable bitmanip extensions + integer unsigned bitmanip_support; + + // Whether the coherence network is on the core clock or on its own clock + integer unsigned async_coh_clk; + // Flit width of the coherence network. Has major impact on latency / area of the network + integer unsigned coh_noc_flit_width; + // Concentrator ID width of the coherence network. Corresponds to how many nodes can be on a + // single wormhole router + integer unsigned coh_noc_cid_width; + // Maximum number of flits in a single wormhole message. Determined by protocol and affects + // buffer size + integer unsigned coh_noc_len_width; + // Maximum credits supported by the network. Correlated to the bandwidth delay product + integer unsigned coh_noc_max_credits; + + // Whether the I/O network is on the core clock or on its own clock + integer unsigned async_mem_clk; + // Flit width of the I/O network. Has major impact on latency / area of the network + integer unsigned mem_noc_flit_width; + // Concentrator ID width of the I/O network. Corresponds to how many nodes can be on a + // single wormhole router + integer unsigned mem_noc_cid_width; + // Domain ID width of the I/O network. Corresponds to how many chips compose a multichip chain + integer unsigned mem_noc_did_width; + // Maximum number of flits in a single wormhole message. Determined by protocol and affects + // buffer size + integer unsigned mem_noc_len_width; + // Maximum credits supported by the network. Correlated to the bandwidth delay product + integer unsigned mem_noc_max_credits; + + // Whether the memory network is on the core clock or on its own clock + integer unsigned async_dma_clk; + // Flit width of the memory network. Has major impact on latency / area of the network + integer unsigned dma_noc_flit_width; + // Concentrator ID width of the memory network. Corresponds to how many nodes can be on a + // single wormhole router + integer unsigned dma_noc_cid_width; + // Maximum number of flits in a single wormhole message. Determined by protocol and affects + // buffer size + integer unsigned dma_noc_len_width; + // Maximum credits supported by the network. Correlated to the bandwidth delay product + integer unsigned dma_noc_max_credits; + + } bp_proc_param_s; + + localparam bp_proc_param_s bp_default_cfg_p = + '{cc_x_dim : 1 + ,cc_y_dim : 1 + ,ic_y_dim : 0 + ,mc_y_dim : 0 + ,cac_x_dim: 0 + ,sac_x_dim: 0 + ,cacc_type: e_cacc_none + ,sacc_type: e_sacc_none + + ,num_cce: 1 + ,num_lce: 2 + + ,vaddr_width: 39 + ,paddr_width: 40 + ,daddr_width: 33 + ,caddr_width: 32 + ,asid_width : 1 + + ,branch_metadata_fwd_width: 49 + ,ras_idx_width : 4 + ,btb_tag_width : 9 + ,btb_idx_width : 6 + ,bht_idx_width : 7 + ,bht_row_els : 4 + ,ghist_width : 2 + + ,itlb_els_4k : 8 + ,itlb_els_2m : 2 + ,itlb_els_1g : 1 + ,dtlb_els_4k : 8 + ,dtlb_els_2m : 2 + ,dtlb_els_1g : 1 + + ,icache_features : (1 << e_cfg_enabled) | (1 << e_cfg_misaligned) + ,icache_sets : 64 + ,icache_assoc : 8 + ,icache_block_width : 512 + ,icache_fill_width : 128 + ,icache_mshr : 1 + ,icache_data_width : 64 + + ,dcache_features : (1 << e_cfg_enabled) + | (1 << e_cfg_writeback) + | (1 << e_cfg_lr_sc) + | (1 << e_cfg_amo_swap) + | (1 << e_cfg_amo_fetch_logic) + | (1 << e_cfg_amo_fetch_arithmetic) + | (1 << e_cfg_hit_under_miss) + ,dcache_sets : 64 + ,dcache_assoc : 8 + ,dcache_block_width : 512 + ,dcache_fill_width : 128 + ,dcache_mshr : 1 + ,dcache_data_width : 64 + + ,acache_features : (1 << e_cfg_enabled) + ,acache_sets : 64 + ,acache_assoc : 8 + ,acache_block_width : 512 + ,acache_fill_width : 128 + ,acache_data_width : 64 + ,acache_mshr : 1 + + ,cce_type : e_cce_uce + ,cce_pc_width : 8 + ,bedrock_block_width : 512 + ,bedrock_fill_width : 128 + + ,l2_features : (1 << e_cfg_enabled) + | (1 << e_cfg_writeback) + | (1 << e_cfg_word_tracking) + | (1 << e_cfg_amo_swap) + | (1 << e_cfg_amo_fetch_logic) + | (1 << e_cfg_amo_fetch_arithmetic) + ,l2_slices : 2 + ,l2_banks : 2 + ,l2_data_width : 128 + ,l2_sets : 128 + ,l2_assoc : 8 + ,l2_block_width : 512 + ,l2_fill_width : 128 + + ,fe_queue_fifo_els : 8 + ,fe_cmd_fifo_els : 4 + ,integer_support : (1 << e_basic) | (1 << e_catchup) + ,muldiv_support : (1 << e_idiv) + | (1 << e_imul) + | (1 << e_imulh) + | (1 << e_idiv2b) + ,fpu_support : (1 << e_fma) | (1 << e_fdivsqrt) | (1 << e_fdivsqrt2b) + ,bitmanip_support : (1 << e_zba) | (1 << e_zbb) | (1 << e_zbs) + ,compressed_support: 1 + + ,async_coh_clk : 0 + ,coh_noc_flit_width : 128 + ,coh_noc_cid_width : 3 + ,coh_noc_len_width : 4 + ,coh_noc_max_credits : 32 + + ,async_mem_clk : 0 + ,mem_noc_flit_width : 128 + ,mem_noc_cid_width : 3 + ,mem_noc_did_width : 3 + ,mem_noc_len_width : 4 + ,mem_noc_max_credits : 32 + + ,async_dma_clk : 0 + ,dma_noc_flit_width : 128 + ,dma_noc_cid_width : 3 + ,dma_noc_len_width : 4 + ,dma_noc_max_credits : 32 + }; + + // BP_CUSTOM_DEFINES_PATH can be set to a file which has the custom defines below set + // Or, you can override the empty one in bp_common/src/include + `ifndef BP_CUSTOM_DEFINES_PATH + `define BP_CUSTOM_DEFINES_PATH "bp_common_aviary_custom_defines.svh" + `endif + `include `BP_CUSTOM_DEFINES_PATH + `ifndef BP_CUSTOM_BASE_CFG + `define BP_CUSTOM_BASE_CFG bp_default_cfg_p + `endif + // Custom, tick define-based configuration + localparam bp_proc_param_s bp_custom_cfg_p = + '{`bp_aviary_define_override(cc_x_dim, BP_CC_X_DIM, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(cc_y_dim, BP_CC_Y_DIM, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(ic_y_dim, BP_IC_Y_DIM, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(mc_y_dim, BP_MC_Y_DIM, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(cac_x_dim, BP_CAC_X_DIM, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(sac_x_dim, BP_SAC_X_DIM, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(cacc_type, BP_CACC_TYPE, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(sacc_type, BP_SACC_TYPE, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(num_cce, BP_NUM_CCE, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(num_lce, BP_NUM_LCE, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(vaddr_width, BP_VADDR_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(paddr_width, BP_PADDR_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(daddr_width, BP_DADDR_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(caddr_width, BP_CADDR_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(asid_width, BP_ASID_WIDTH, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(fe_queue_fifo_els, BP_FE_QUEUE_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(fe_cmd_fifo_els, BP_FE_CMD_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(integer_support, BP_INTEGER_SUPPORT, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(muldiv_support, BP_MULDIV_SUPPORT, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(fpu_support, BP_FPU_SUPPORT, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(bitmanip_support, BP_BITMANIP_SUPPORT, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(compressed_support, BP_COMPRESSED_SUPPORT, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(branch_metadata_fwd_width, BRANCH_METADATA_FWD_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(ras_idx_width, BP_RAS_IDX_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(btb_tag_width, BP_BTB_TAG_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(btb_idx_width, BP_BTB_IDX_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(bht_idx_width, BP_BHT_IDX_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(bht_row_els, BP_BHT_ROW_ELS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(ghist_width, BP_GHIST_WIDTH, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(itlb_els_4k, BP_ITLB_ELS_4K, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(itlb_els_2m, BP_ITLB_ELS_2M, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(itlb_els_1g, BP_ITLB_ELS_1G, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dtlb_els_4k, BP_DTLB_ELS_4K, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dtlb_els_2m, BP_DTLB_ELS_2M, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dtlb_els_1g, BP_DTLB_ELS_1G, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(icache_features, BP_ICACHE_FEATURES, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(icache_sets, BP_ICACHE_SETS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(icache_assoc, BP_ICACHE_ASSOC, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(icache_block_width, BP_ICACHE_BLOCK_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(icache_fill_width, BP_ICACHE_FILL_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(icache_data_width, BP_ICACHE_DATA_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(icache_mshr, BP_ICACHE_MSHR, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(dcache_features, BP_DCACHE_FEATURES, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dcache_sets, BP_DCACHE_SETS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dcache_assoc, BP_DCACHE_ASSOC, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dcache_block_width, BP_DCACHE_BLOCK_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dcache_fill_width, BP_DCACHE_FILL_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dcache_data_width, BP_DCACHE_DATA_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dcache_mshr, BP_DCACHE_MSHR, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(acache_features, BP_ACACHE_FEATURES, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(acache_sets, BP_ACACHE_SETS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(acache_assoc, BP_ACACHE_ASSOC, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(acache_block_width, BP_ACACHE_BLOCK_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(acache_fill_width, BP_ACACHE_FILL_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(acache_data_width, BP_ACACHE_DATA_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(acache_mshr, BP_ACACHE_MSHR, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(cce_type, BP_CCE_TYPE, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(cce_pc_width, BP_CCE_PC_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(bedrock_block_width, BP_BEDROCK_BLOCK_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(bedrock_fill_width, BP_BEDROCK_FILL_WIDTH, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(l2_features, BP_L2_FEATURES, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(l2_slices, BP_L2_SLICES, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(l2_banks, BP_L2_BANKS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(l2_data_width, BP_L2_DATA_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(l2_sets, BP_L2_SETS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(l2_assoc, BP_L2_ASSOC, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(l2_block_width, BP_L2_BLOCK_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(l2_fill_width, BP_L2_FILL_WIDTH, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(async_coh_clk, BP_ASYNC_COH_CLK, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(coh_noc_max_credits, BP_COH_NOC_MAX_CREDITS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(coh_noc_flit_width, BP_COH_NOC_FLIT_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(coh_noc_cid_width, BP_COH_NOC_CID_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(coh_noc_len_width, BP_COH_NOC_LEN_WIDTH, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(async_mem_clk, BP_ASYNC_IO_CLK, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(mem_noc_max_credits, BP_IO_NOC_MAX_CREDITS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(mem_noc_flit_width, BP_IO_NOC_FLIT_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(mem_noc_cid_width, BP_IO_NOC_CID_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(mem_noc_did_width, BP_IO_NOC_DID_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(mem_noc_len_width, BP_IO_NOC_LEN_WIDTH, `BP_CUSTOM_BASE_CFG) + + ,`bp_aviary_define_override(async_dma_clk, BP_ASYNC_MEM_CLK, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dma_noc_max_credits, BP_MEM_NOC_MAX_CREDITS, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dma_noc_flit_width, BP_MEM_NOC_FLIT_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dma_noc_cid_width, BP_MEM_NOC_CID_WIDTH, `BP_CUSTOM_BASE_CFG) + ,`bp_aviary_define_override(dma_noc_len_width, BP_MEM_NOC_LEN_WIDTH, `BP_CUSTOM_BASE_CFG) + }; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_aviary_custom_defines.svh b/designs/black-parrot/src/bp/bp_common_aviary_custom_defines.svh new file mode 100644 index 0000000..e69de29 diff --git a/designs/black-parrot/src/bp/bp_common_aviary_defines.svh b/designs/black-parrot/src/bp/bp_common_aviary_defines.svh new file mode 100644 index 0000000..4657eb0 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_aviary_defines.svh @@ -0,0 +1,321 @@ +/** + * + * bp_common_aviary_defines.svh + * + */ + +`ifndef BP_COMMON_AVIARY_DEFINES_SVH +`define BP_COMMON_AVIARY_DEFINES_SVH + + `define declare_bp_proc_params(bp_params_e_mp) \ + , localparam bp_proc_param_s proc_param_lp = all_cfgs_gp[bp_params_e_mp] \ + \ + , localparam cc_x_dim_p = proc_param_lp.cc_x_dim \ + , localparam cc_y_dim_p = proc_param_lp.cc_y_dim \ + \ + , localparam ic_x_dim_p = cc_x_dim_p \ + , localparam ic_y_dim_p = proc_param_lp.ic_y_dim \ + , localparam mc_x_dim_p = cc_x_dim_p \ + , localparam mc_y_dim_p = proc_param_lp.mc_y_dim \ + , localparam cac_x_dim_p = proc_param_lp.cac_x_dim \ + , localparam cac_y_dim_p = cc_y_dim_p \ + , localparam sac_x_dim_p = proc_param_lp.sac_x_dim \ + , localparam sac_y_dim_p = cc_y_dim_p \ + , localparam cacc_type_p = proc_param_lp.cacc_type \ + , localparam sacc_type_p = proc_param_lp.sacc_type \ + \ + , localparam num_core_p = cc_x_dim_p * cc_y_dim_p \ + , localparam num_io_p = ic_x_dim_p * ic_y_dim_p \ + , localparam num_l2e_p = mc_x_dim_p * mc_y_dim_p \ + , localparam num_cacc_p = cac_x_dim_p * cac_y_dim_p \ + , localparam num_sacc_p = sac_x_dim_p * sac_y_dim_p \ + \ + , localparam num_cce_p = proc_param_lp.num_cce \ + , localparam num_lce_p = proc_param_lp.num_lce \ + \ + , localparam num_pseudo_cce_p = num_core_p+num_io_p+num_l2e_p+num_cacc_p+num_sacc_p+1 \ + , localparam num_pseudo_lce_p = 2*num_core_p+num_io_p+num_l2e_p+num_cacc_p+num_sacc_p+1 \ + \ + , localparam core_id_width_p = `BSG_SAFE_CLOG2(num_core_p) \ + , localparam cce_id_width_p = `BSG_SAFE_CLOG2(num_pseudo_cce_p) \ + , localparam lce_id_width_p = `BSG_SAFE_CLOG2(num_pseudo_lce_p) \ + \ + , localparam vaddr_width_p = proc_param_lp.vaddr_width \ + , localparam paddr_width_p = proc_param_lp.paddr_width \ + , localparam daddr_width_p = proc_param_lp.daddr_width \ + , localparam caddr_width_p = proc_param_lp.caddr_width \ + , localparam asid_width_p = proc_param_lp.asid_width \ + , localparam hio_width_p = paddr_width_p - daddr_width_p \ + \ + , localparam branch_metadata_fwd_width_p = proc_param_lp.branch_metadata_fwd_width \ + , localparam ras_idx_width_p = proc_param_lp.ras_idx_width \ + , localparam btb_tag_width_p = proc_param_lp.btb_tag_width \ + , localparam btb_idx_width_p = proc_param_lp.btb_idx_width \ + , localparam bht_idx_width_p = proc_param_lp.bht_idx_width \ + , localparam bht_row_els_p = proc_param_lp.bht_row_els \ + , localparam ghist_width_p = proc_param_lp.ghist_width \ + , localparam bht_row_width_p = 2*bht_row_els_p \ + , localparam bht_offset_width_p = `BSG_SAFE_CLOG2(bht_row_els_p) \ + \ + , localparam itlb_els_4k_p = proc_param_lp.itlb_els_4k \ + , localparam itlb_els_2m_p = proc_param_lp.itlb_els_2m \ + , localparam itlb_els_1g_p = proc_param_lp.itlb_els_1g \ + , localparam dtlb_els_4k_p = proc_param_lp.dtlb_els_4k \ + , localparam dtlb_els_2m_p = proc_param_lp.dtlb_els_2m \ + , localparam dtlb_els_1g_p = proc_param_lp.dtlb_els_1g \ + \ + , localparam icache_features_p = proc_param_lp.icache_features \ + , localparam icache_sets_p = proc_param_lp.icache_sets \ + , localparam icache_assoc_p = proc_param_lp.icache_assoc \ + , localparam icache_block_width_p = proc_param_lp.icache_block_width \ + , localparam icache_fill_width_p = proc_param_lp.icache_fill_width \ + , localparam icache_data_width_p = proc_param_lp.icache_data_width \ + , localparam icache_mshr_p = proc_param_lp.icache_mshr \ + , localparam icache_req_id_width_p = `BSG_SAFE_CLOG2(icache_mshr_p) \ + \ + , localparam dcache_features_p = proc_param_lp.dcache_features \ + , localparam dcache_sets_p = proc_param_lp.dcache_sets \ + , localparam dcache_assoc_p = proc_param_lp.dcache_assoc \ + , localparam dcache_block_width_p = proc_param_lp.dcache_block_width \ + , localparam dcache_fill_width_p = proc_param_lp.dcache_fill_width \ + , localparam dcache_data_width_p = proc_param_lp.dcache_data_width \ + , localparam dcache_mshr_p = proc_param_lp.dcache_mshr \ + , localparam dcache_req_id_width_p = `BSG_SAFE_CLOG2(dcache_mshr_p) \ + \ + , localparam acache_features_p = proc_param_lp.acache_features \ + , localparam acache_sets_p = proc_param_lp.acache_sets \ + , localparam acache_assoc_p = proc_param_lp.acache_assoc \ + , localparam acache_block_width_p = proc_param_lp.acache_block_width \ + , localparam acache_fill_width_p = proc_param_lp.acache_fill_width \ + , localparam acache_data_width_p = proc_param_lp.acache_data_width \ + , localparam acache_mshr_p = proc_param_lp.acache_mshr \ + , localparam acache_req_id_width_p = `BSG_SAFE_CLOG2(acache_mshr_p) \ + \ + , localparam lce_assoc_p = \ + `BSG_MAX(dcache_assoc_p, `BSG_MAX(icache_assoc_p, num_cacc_p ? acache_assoc_p : '0)) \ + , localparam lce_assoc_width_p = `BSG_SAFE_CLOG2(lce_assoc_p) \ + , localparam lce_sets_p = \ + `BSG_MAX(dcache_sets_p, `BSG_MAX(icache_sets_p, num_cacc_p ? acache_sets_p : '0)) \ + , localparam lce_sets_width_p = `BSG_SAFE_CLOG2(lce_sets_p) \ + \ + , localparam cce_type_p = proc_param_lp.cce_type \ + , localparam cce_pc_width_p = proc_param_lp.cce_pc_width \ + , localparam bedrock_block_width_p = proc_param_lp.bedrock_block_width \ + , localparam bedrock_fill_width_p = proc_param_lp.bedrock_fill_width \ + , localparam num_cce_instr_ram_els_p = 2**cce_pc_width_p \ + , localparam cce_way_groups_p = \ + `BSG_MIN(dcache_sets_p, `BSG_MIN(icache_sets_p, num_cacc_p ? acache_sets_p : icache_sets_p)) \ + \ + /* L2 enable turns the L2 into a small write buffer, which is minimal size */ \ + , localparam l2_features_p = proc_param_lp.l2_features \ + , localparam l2_slices_p = l2_features_p[e_cfg_enabled] ? proc_param_lp.l2_slices : 1 \ + , localparam l2_banks_p = l2_features_p[e_cfg_enabled] ? proc_param_lp.l2_banks : 1 \ + , localparam l2_sets_p = l2_features_p[e_cfg_enabled] ? proc_param_lp.l2_sets : 4 \ + , localparam l2_assoc_p = l2_features_p[e_cfg_enabled] ? proc_param_lp.l2_assoc : 2 \ + , localparam l2_block_width_p = proc_param_lp.l2_block_width \ + , localparam l2_fill_width_p = proc_param_lp.l2_fill_width \ + , localparam l2_data_width_p = proc_param_lp.l2_data_width \ + , localparam l2_dmas_p = l2_slices_p * l2_banks_p \ + \ + , localparam l2_block_size_in_words_p = l2_block_width_p / l2_data_width_p \ + , localparam l2_block_size_in_fill_p = l2_block_width_p / l2_fill_width_p \ + \ + , localparam fe_queue_fifo_els_p = proc_param_lp.fe_queue_fifo_els \ + , localparam fe_cmd_fifo_els_p = proc_param_lp.fe_cmd_fifo_els \ + , localparam integer_support_p = proc_param_lp.integer_support \ + , localparam muldiv_support_p = proc_param_lp.muldiv_support \ + , localparam fpu_support_p = proc_param_lp.fpu_support \ + , localparam compressed_support_p = proc_param_lp.compressed_support \ + , localparam bitmanip_support_p = proc_param_lp.bitmanip_support \ + \ + , localparam async_coh_clk_p = proc_param_lp.async_coh_clk \ + , localparam coh_noc_max_credits_p = proc_param_lp.coh_noc_max_credits \ + , localparam coh_noc_flit_width_p = proc_param_lp.coh_noc_flit_width \ + , localparam coh_noc_cid_width_p = proc_param_lp.coh_noc_cid_width \ + , localparam coh_noc_len_width_p = proc_param_lp.coh_noc_len_width \ + , localparam coh_noc_y_cord_width_p = `BSG_SAFE_CLOG2(ic_y_dim_p+cc_y_dim_p+mc_y_dim_p+1) \ + , localparam coh_noc_x_cord_width_p = `BSG_SAFE_CLOG2(sac_x_dim_p+cc_x_dim_p+cac_x_dim_p+1) \ + , localparam coh_noc_dims_p = 2 \ + , localparam coh_noc_dirs_p = coh_noc_dims_p*2 + 1 \ + , localparam coh_noc_trans_p = 0 \ + , localparam int coh_noc_cord_markers_pos_p[coh_noc_dims_p:0] = coh_noc_trans_p \ + ? '{coh_noc_x_cord_width_p+coh_noc_y_cord_width_p, coh_noc_y_cord_width_p, 0} \ + : '{coh_noc_y_cord_width_p+coh_noc_x_cord_width_p, coh_noc_x_cord_width_p, 0} \ + , localparam coh_noc_cord_width_p = coh_noc_cord_markers_pos_p[coh_noc_dims_p] \ + \ + , localparam async_mem_clk_p = proc_param_lp.async_mem_clk \ + , localparam mem_noc_max_credits_p = proc_param_lp.mem_noc_max_credits \ + , localparam mem_noc_did_width_p = proc_param_lp.mem_noc_did_width \ + , localparam mem_noc_flit_width_p = proc_param_lp.mem_noc_flit_width \ + , localparam mem_noc_cid_width_p = proc_param_lp.mem_noc_cid_width \ + , localparam mem_noc_len_width_p = proc_param_lp.mem_noc_len_width \ + , localparam mem_noc_y_cord_width_p = 0 \ + , localparam mem_noc_x_cord_width_p = mem_noc_did_width_p \ + , localparam mem_noc_dims_p = 1 \ + , localparam mem_noc_cord_dims_p = 2 \ + , localparam mem_noc_dirs_p = mem_noc_cord_dims_p*2 + 1 \ + , localparam mem_noc_trans_p = 0 \ + , localparam int mem_noc_cord_markers_pos_p[mem_noc_cord_dims_p:0] = mem_noc_trans_p \ + ? '{mem_noc_x_cord_width_p+mem_noc_y_cord_width_p, mem_noc_y_cord_width_p, 0} \ + : '{mem_noc_y_cord_width_p+mem_noc_x_cord_width_p, mem_noc_x_cord_width_p, 0} \ + , localparam mem_noc_cord_width_p = mem_noc_cord_markers_pos_p[mem_noc_dims_p] \ + \ + , localparam async_dma_clk_p = proc_param_lp.async_dma_clk \ + , localparam dma_noc_max_credits_p = proc_param_lp.dma_noc_max_credits \ + , localparam dma_noc_flit_width_p = proc_param_lp.dma_noc_flit_width \ + , localparam dma_noc_cid_width_p = proc_param_lp.dma_noc_cid_width \ + , localparam dma_noc_len_width_p = proc_param_lp.dma_noc_len_width \ + , localparam dma_noc_y_cord_width_p = `BSG_SAFE_CLOG2(ic_y_dim_p+cc_y_dim_p+mc_y_dim_p+1) \ + , localparam dma_noc_x_cord_width_p = 0 \ + , localparam dma_noc_dims_p = 1 \ + , localparam dma_noc_cord_dims_p = 2 \ + , localparam dma_noc_dirs_p = dma_noc_dims_p*2 + 1 \ + , localparam dma_noc_trans_p = 1 \ + , localparam int dma_noc_cord_markers_pos_p[dma_noc_cord_dims_p:0] = dma_noc_trans_p \ + ? '{dma_noc_x_cord_width_p+dma_noc_y_cord_width_p, dma_noc_y_cord_width_p, 0} \ + : '{dma_noc_y_cord_width_p+dma_noc_x_cord_width_p, dma_noc_x_cord_width_p, 0} \ + , localparam dma_noc_cord_width_p = dma_noc_cord_markers_pos_p[dma_noc_dims_p] \ + \ + , localparam did_width_p = mem_noc_did_width_p \ + \ + , localparam etag_width_p = dword_width_gp - page_offset_width_gp \ + , localparam vtag_width_p = vaddr_width_p - page_offset_width_gp \ + , localparam ptag_width_p = paddr_width_p - page_offset_width_gp \ + , localparam dtag_width_p = daddr_width_p - page_offset_width_gp \ + , localparam ctag_width_p = caddr_width_p - page_offset_width_gp \ + , localparam icache_tag_width_p = caddr_width_p - \ + (`BSG_SAFE_CLOG2(icache_sets_p*icache_block_width_p/8)) \ + , localparam dcache_tag_width_p = caddr_width_p - \ + (`BSG_SAFE_CLOG2(dcache_sets_p*dcache_block_width_p/8)) \ + , localparam acache_tag_width_p = caddr_width_p - \ + (`BSG_SAFE_CLOG2(acache_sets_p*acache_block_width_p/8)) \ + \ + , localparam fetch_width_p = cinstr_width_gp + icache_data_width_p \ + , localparam fetch_cinstr_p = fetch_width_p >> 4 \ + , localparam fetch_sel_p = `BSG_SAFE_CLOG2(fetch_cinstr_p) \ + , localparam fetch_ptr_p = `BSG_WIDTH(fetch_cinstr_p) \ + , localparam fetch_bytes_p = fetch_width_p >> 3 \ + , localparam fetch_offset_p = `BSG_SAFE_CLOG2(fetch_bytes_p) \ + \ + , localparam issue_width_p = instr_width_gp \ + , localparam issue_cinstr_p = instr_width_gp >> 4 \ + , localparam issue_sel_p = `BSG_SAFE_CLOG2(issue_cinstr_p) \ + , localparam issue_ptr_p = `BSG_WIDTH(issue_cinstr_p) \ + , localparam issue_bytes_p = issue_width_p >> 3 \ + , localparam issue_offset_p = `BSG_SAFE_CLOG2(issue_bytes_p) \ + + `define bp_aviary_parameter_override(parameter_mp, override_cfg_mp, default_cfg_mp) \ + parameter_mp: (override_cfg_mp.``parameter_mp`` == "inv") \ + ? default_cfg_mp.``parameter_mp`` \ + : override_cfg_mp.``parameter_mp`` \ + + `define bp_aviary_define_override(parameter_mp, define_mp, default_cfg_mp) \ + `ifdef define_mp \ + parameter_mp: `define_mp \ + `else \ + parameter_mp: default_cfg_mp.``parameter_mp`` \ + `endif + + `define bp_aviary_derive_cfg(cfg_name_mp, override_cfg_mp, default_cfg_mp) \ + localparam bp_proc_param_s cfg_name_mp = \ + '{`bp_aviary_parameter_override(cc_x_dim, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(cc_y_dim, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(ic_y_dim, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(mc_y_dim, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(cac_x_dim, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(sac_x_dim, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(cacc_type, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(sacc_type, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(num_cce, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(num_lce, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(vaddr_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(paddr_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(daddr_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(caddr_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(asid_width, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(fe_queue_fifo_els, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(fe_cmd_fifo_els, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(integer_support, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(muldiv_support, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(fpu_support, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(compressed_support, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(bitmanip_support, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(branch_metadata_fwd_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(ras_idx_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(btb_tag_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(btb_idx_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(bht_idx_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(bht_row_els, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(ghist_width, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(itlb_els_4k, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(itlb_els_2m, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(itlb_els_1g, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dtlb_els_4k, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dtlb_els_2m, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dtlb_els_1g, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(icache_features, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(icache_sets, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(icache_assoc, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(icache_block_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(icache_fill_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(icache_data_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(icache_mshr, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(dcache_features, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dcache_sets, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dcache_assoc, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dcache_block_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dcache_fill_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dcache_data_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dcache_mshr, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(acache_features, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(acache_sets, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(acache_assoc, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(acache_block_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(acache_fill_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(acache_data_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(acache_mshr, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(cce_type, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(cce_pc_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(bedrock_block_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(bedrock_fill_width, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(l2_features, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(l2_slices, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(l2_banks, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(l2_data_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(l2_sets, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(l2_assoc, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(l2_block_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(l2_fill_width, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(async_coh_clk, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(coh_noc_max_credits, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(coh_noc_flit_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(coh_noc_cid_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(coh_noc_len_width, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(async_mem_clk, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(mem_noc_max_credits, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(mem_noc_flit_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(mem_noc_cid_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(mem_noc_did_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(mem_noc_len_width, override_cfg_mp, default_cfg_mp) \ + \ + ,`bp_aviary_parameter_override(async_dma_clk, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dma_noc_max_credits, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dma_noc_flit_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dma_noc_cid_width, override_cfg_mp, default_cfg_mp) \ + ,`bp_aviary_parameter_override(dma_noc_len_width, override_cfg_mp, default_cfg_mp) \ + } + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_aviary_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_aviary_pkgdef.svh new file mode 100644 index 0000000..1b4e6e2 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_aviary_pkgdef.svh @@ -0,0 +1,604 @@ +`ifndef BP_COMMON_AVIARY_PKGDEF_SVH +`define BP_COMMON_AVIARY_PKGDEF_SVH + + `include "bp_common_aviary_cfg_pkgdef.svh" + `include "bp_common_host_pkgdef.svh" + + // Default configuration is unicore + localparam bp_proc_param_s bp_unicore_cfg_p = bp_default_cfg_p; + + localparam bp_proc_param_s bp_unicore_megaparrot_override_p = + '{paddr_width : 56 + ,daddr_width: 55 + ,caddr_width: 54 + + ,branch_metadata_fwd_width: 50 + ,ras_idx_width : 3 + ,btb_tag_width : 9 + ,btb_idx_width : 8 + ,bht_idx_width : 8 + ,bht_row_els : 4 + ,ghist_width : 2 + + ,icache_sets : 64 + ,icache_assoc : 8 + ,icache_block_width : 512 + ,icache_fill_width : 512 + + ,dcache_sets : 64 + ,dcache_assoc : 8 + ,dcache_block_width : 512 + ,dcache_fill_width : 512 + + ,bedrock_block_width : 512 + ,bedrock_fill_width : 512 + + ,l2_banks : 8 + ,l2_data_width : 512 + ,l2_sets : 128 + ,l2_assoc : 8 + ,l2_block_width : 512 + ,l2_fill_width : 512 + + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_unicore_megaparrot_cfg_p + ,bp_unicore_megaparrot_override_p + ,bp_unicore_cfg_p + ); + + localparam bp_proc_param_s bp_unicore_tinyparrot_override_p = + '{paddr_width : 34 + + ,branch_metadata_fwd_width: 31 + ,ras_idx_width : 1 + ,btb_tag_width : 6 + ,btb_idx_width : 4 + ,bht_idx_width : 5 + ,bht_row_els : 2 + ,ghist_width : 2 + + ,icache_sets : 128 + ,icache_assoc : 1 + ,icache_block_width : 64 + ,icache_fill_width : 64 + + ,dcache_features : (1 << e_cfg_enabled) | (1 << e_cfg_lr_sc) + ,dcache_sets : 128 + ,dcache_assoc : 1 + ,dcache_block_width : 64 + ,dcache_fill_width : 64 + + ,bedrock_block_width: 64 + ,bedrock_fill_width : 64 + + ,l2_features : (1 << e_cfg_writeback) + | (1 << e_cfg_word_tracking) + | (1 << e_cfg_amo_swap) + | (1 << e_cfg_amo_fetch_logic) + | (1 << e_cfg_amo_fetch_arithmetic) + ,l2_data_width : 64 + ,l2_fill_width : 64 + + ,integer_support: (1 << e_basic) + ,muldiv_support : (1 << e_idiv) | (1 << e_imul) + ,fpu_support : (1 << e_fma) | (1 << e_fdivsqrt) + + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_unicore_tinyparrot_cfg_p + ,bp_unicore_tinyparrot_override_p + ,bp_unicore_cfg_p + ); + + localparam bp_proc_param_s bp_unicore_miniparrot_override_p = + '{paddr_width : 34 + + ,branch_metadata_fwd_width: 31 + ,ras_idx_width : 1 + ,btb_tag_width : 6 + ,btb_idx_width : 4 + ,bht_idx_width : 5 + ,bht_row_els : 2 + ,ghist_width : 2 + + ,icache_sets : 256 + ,icache_assoc : 2 + ,icache_block_width : 128 + ,icache_fill_width : 128 + + ,dcache_features : (1 << e_cfg_enabled) | (1 << e_cfg_lr_sc) + ,dcache_sets : 256 + ,dcache_assoc : 2 + ,dcache_block_width : 128 + ,dcache_fill_width : 128 + + ,bedrock_block_width: 128 + ,bedrock_fill_width : 128 + + // We use L2 for the write buffer support + ,l2_features : (1 << e_cfg_enabled) + | (1 << e_cfg_writeback) + | (1 << e_cfg_word_tracking) + | (1 << e_cfg_amo_swap) + | (1 << e_cfg_amo_fetch_logic) + | (1 << e_cfg_amo_fetch_arithmetic) + ,l2_data_width : 128 + ,l2_fill_width : 128 + + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_unicore_miniparrot_cfg_p + ,bp_unicore_miniparrot_override_p + ,bp_unicore_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_1_override_p = + '{cce_type : e_cce_fsm + ,ic_y_dim : 1 + ,icache_features : (1 << e_cfg_enabled) | (1 << e_cfg_coherent) + ,dcache_features : (1 << e_cfg_enabled) + | (1 << e_cfg_coherent) + | (1 << e_cfg_writeback) + | (1 << e_cfg_lr_sc) + | (1 << e_cfg_amo_swap) + | (1 << e_cfg_amo_fetch_logic) + | (1 << e_cfg_amo_fetch_arithmetic) + ,l2_features : (1 << e_cfg_enabled) | (1 << e_cfg_writeback) + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_cfg_p + ,bp_multicore_1_override_p + ,bp_default_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_1_megaparrot_override_p = + '{paddr_width : 56 + ,daddr_width: 55 + ,caddr_width: 54 + + ,branch_metadata_fwd_width: 46 + ,ras_idx_width : 1 + ,btb_tag_width : 9 + ,btb_idx_width : 8 + ,bht_idx_width : 8 + ,bht_row_els : 4 + ,ghist_width : 2 + + ,icache_sets : 64 + ,icache_assoc : 8 + ,icache_block_width : 512 + ,icache_fill_width : 512 + + ,dcache_sets : 64 + ,dcache_assoc : 8 + ,dcache_block_width : 512 + ,dcache_fill_width : 512 + + ,bedrock_block_width : 512 + ,bedrock_fill_width : 512 + + ,l2_banks : 8 + ,l2_data_width : 512 + ,l2_sets : 128 + ,l2_assoc : 8 + ,l2_block_width : 512 + ,l2_fill_width : 512 + + ,dma_noc_flit_width : 512 + ,coh_noc_flit_width : 512 + ,mem_noc_flit_width : 512 + ,dma_noc_cid_width : 4 + + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_megaparrot_cfg_p + ,bp_multicore_1_megaparrot_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_1_miniparrot_override_p = + '{paddr_width : 34 + ,daddr_width: 33 + ,caddr_width: 32 + + ,branch_metadata_fwd_width: 31 + ,ras_idx_width : 1 + ,btb_tag_width : 6 + ,btb_idx_width : 4 + ,bht_idx_width : 5 + ,bht_row_els : 2 + ,ghist_width : 2 + + ,icache_sets : 256 + ,icache_assoc : 2 + ,icache_block_width : 128 + ,icache_fill_width : 128 + + ,dcache_sets : 256 + ,dcache_assoc : 2 + ,dcache_block_width : 128 + ,dcache_fill_width : 128 + + ,acache_sets : 256 + ,acache_assoc : 2 + ,acache_block_width : 128 + ,acache_fill_width : 128 + + ,bedrock_block_width : 128 + ,bedrock_fill_width : 128 + + ,l2_data_width : 128 + ,l2_fill_width : 128 + + ,coh_noc_flit_width : 128 + ,dma_noc_flit_width : 128 + ,mem_noc_flit_width : 128 + + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_miniparrot_cfg_p + ,bp_multicore_1_miniparrot_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_1_l2e_override_p = + '{mc_y_dim : 1 + ,num_cce : 2 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_l2e_cfg_p + ,bp_multicore_1_l2e_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_2_override_p = + '{cc_x_dim : 2 + ,num_cce : 2 + ,num_lce : 4 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_2_cfg_p + ,bp_multicore_2_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_2_l2e_override_p = + '{mc_y_dim : 1 + ,num_cce : 4 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_2_l2e_cfg_p + ,bp_multicore_2_l2e_override_p + ,bp_multicore_2_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_3_override_p = + '{cc_x_dim : 3 + ,num_cce : 3 + ,num_lce : 6 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_3_cfg_p + ,bp_multicore_3_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_4_override_p = + '{cc_x_dim : 2 + ,cc_y_dim: 2 + ,num_cce : 4 + ,num_lce : 8 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_4_cfg_p + ,bp_multicore_4_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_4_l2e_override_p = + '{mc_y_dim : 1 + ,num_cce : 6 + ,l2_banks : 1 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_4_l2e_cfg_p + ,bp_multicore_4_l2e_override_p + ,bp_multicore_4_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_6_override_p = + '{cc_x_dim : 3 + ,cc_y_dim: 2 + ,num_cce : 6 + ,num_lce : 12 + ,l2_slices: 1 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_6_cfg_p + ,bp_multicore_6_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_8_override_p = + '{cc_x_dim : 4 + ,cc_y_dim: 2 + ,num_cce : 8 + ,num_lce : 16 + ,l2_slices: 1 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_8_cfg_p + ,bp_multicore_8_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_12_override_p = + '{cc_x_dim : 4 + ,cc_y_dim: 3 + ,num_cce : 12 + ,num_lce : 24 + ,l2_banks: 1 + ,l2_slices: 1 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_12_cfg_p + ,bp_multicore_12_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_16_override_p = + '{cc_x_dim : 4 + ,cc_y_dim: 4 + ,num_cce : 16 + ,num_lce : 32 + ,l2_banks: 1 + ,l2_slices: 1 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_16_cfg_p + ,bp_multicore_16_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_1_acc_scratchpad_override_p = + '{sac_x_dim: 1 + ,sacc_type: e_sacc_scratchpad + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_acc_scratchpad_cfg_p + ,bp_multicore_1_acc_scratchpad_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_1_acc_vdp_override_p = + '{cac_x_dim : 1 + ,sac_x_dim: 1 + ,cacc_type: e_cacc_vdp + ,sacc_type: e_sacc_vdp + ,num_lce : 3 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_acc_vdp_cfg_p + ,bp_multicore_1_acc_vdp_override_p + ,bp_multicore_1_cfg_p + ); + + + localparam bp_proc_param_s bp_multicore_4_acc_scratchpad_override_p = + '{sac_x_dim : 1 + ,sacc_type: e_sacc_scratchpad + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_4_acc_scratchpad_cfg_p + ,bp_multicore_4_acc_scratchpad_override_p + ,bp_multicore_4_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_4_acc_vdp_override_p = + '{cac_x_dim : 1 + ,sac_x_dim: 1 + ,cacc_type: e_cacc_vdp + ,sacc_type: e_sacc_vdp + ,num_lce : 10 + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_4_acc_vdp_cfg_p + ,bp_multicore_4_acc_vdp_override_p + ,bp_multicore_4_cfg_p + ); + + + localparam bp_proc_param_s bp_multicore_1_cce_ucode_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_cce_ucode_cfg_p + ,bp_multicore_1_cce_ucode_override_p + ,bp_multicore_1_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_1_cce_ucode_megaparrot_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_cce_ucode_megaparrot_cfg_p + ,bp_multicore_1_cce_ucode_megaparrot_override_p + ,bp_multicore_1_megaparrot_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_1_cce_ucode_miniparrot_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_1_cce_ucode_miniparrot_cfg_p + ,bp_multicore_1_cce_ucode_miniparrot_override_p + ,bp_multicore_1_miniparrot_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_2_cce_ucode_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_2_cce_ucode_cfg_p + ,bp_multicore_2_cce_ucode_override_p + ,bp_multicore_2_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_3_cce_ucode_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_3_cce_ucode_cfg_p + ,bp_multicore_3_cce_ucode_override_p + ,bp_multicore_3_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_4_cce_ucode_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_4_cce_ucode_cfg_p + ,bp_multicore_4_cce_ucode_override_p + ,bp_multicore_4_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_6_cce_ucode_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_6_cce_ucode_cfg_p + ,bp_multicore_6_cce_ucode_override_p + ,bp_multicore_6_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_8_cce_ucode_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_8_cce_ucode_cfg_p + ,bp_multicore_8_cce_ucode_override_p + ,bp_multicore_8_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_12_cce_ucode_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_12_cce_ucode_cfg_p + ,bp_multicore_12_cce_ucode_override_p + ,bp_multicore_12_cfg_p + ); + + localparam bp_proc_param_s bp_multicore_16_cce_ucode_override_p = + '{cce_type : e_cce_ucode + ,default : "inv" + }; + `bp_aviary_derive_cfg(bp_multicore_16_cce_ucode_cfg_p + ,bp_multicore_16_cce_ucode_override_p + ,bp_multicore_16_cfg_p + ); + + /* verilator lint_off WIDTH */ + parameter bp_proc_param_s [max_cfgs-1:0] all_cfgs_gp = + { + // L2 extension configurations + bp_multicore_4_l2e_cfg_p + ,bp_multicore_2_l2e_cfg_p + ,bp_multicore_1_l2e_cfg_p + + // Accelerator configurations + ,bp_multicore_4_acc_vdp_cfg_p + ,bp_multicore_4_acc_scratchpad_cfg_p + ,bp_multicore_1_acc_vdp_cfg_p + ,bp_multicore_1_acc_scratchpad_cfg_p + + // Ucode configurations + ,bp_multicore_16_cce_ucode_cfg_p + ,bp_multicore_12_cce_ucode_cfg_p + ,bp_multicore_8_cce_ucode_cfg_p + ,bp_multicore_6_cce_ucode_cfg_p + ,bp_multicore_4_cce_ucode_cfg_p + ,bp_multicore_3_cce_ucode_cfg_p + ,bp_multicore_2_cce_ucode_cfg_p + ,bp_multicore_1_cce_ucode_megaparrot_cfg_p + ,bp_multicore_1_cce_ucode_miniparrot_cfg_p + ,bp_multicore_1_cce_ucode_cfg_p + + // Multicore configurations + ,bp_multicore_16_cfg_p + ,bp_multicore_12_cfg_p + ,bp_multicore_8_cfg_p + ,bp_multicore_6_cfg_p + ,bp_multicore_4_cfg_p + ,bp_multicore_3_cfg_p + ,bp_multicore_2_cfg_p + ,bp_multicore_1_megaparrot_cfg_p + ,bp_multicore_1_miniparrot_cfg_p + ,bp_multicore_1_cfg_p + + // Unicore configurations + ,bp_unicore_megaparrot_cfg_p + ,bp_unicore_miniparrot_cfg_p + ,bp_unicore_tinyparrot_cfg_p + ,bp_unicore_cfg_p + + // A custom BP configuration generated from Makefile + ,bp_custom_cfg_p + // The default BP + ,bp_default_cfg_p + }; + /* verilator lint_on WIDTH */ + + // This enum MUST be kept up to date with the parameter array above + typedef enum bit [lg_max_cfgs-1:0] + { + // L2 extension configurations + e_bp_multicore_4_l2e_cfg = 32 + ,e_bp_multicore_2_l2e_cfg = 31 + ,e_bp_multicore_1_l2e_cfg = 30 + + // Accelerator configurations + ,e_bp_multicore_4_acc_vdp_cfg = 29 + ,e_bp_multicore_4_acc_scratchpad_cfg = 28 + ,e_bp_multicore_1_acc_vdp_cfg = 27 + ,e_bp_multicore_1_acc_scratchpad_cfg = 26 + + // Ucode configurations + ,e_bp_multicore_16_cce_ucode_cfg = 25 + ,e_bp_multicore_12_cce_ucode_cfg = 24 + ,e_bp_multicore_8_cce_ucode_cfg = 23 + ,e_bp_multicore_6_cce_ucode_cfg = 22 + ,e_bp_multicore_4_cce_ucode_cfg = 21 + ,e_bp_multicore_3_cce_ucode_cfg = 20 + ,e_bp_multicore_2_cce_ucode_cfg = 19 + ,e_bp_multicore_1_cce_ucode_megaparrot_cfg = 18 + ,e_bp_multicore_1_cce_ucode_miniparrot_cfg = 17 + ,e_bp_multicore_1_cce_ucode_cfg = 16 + + // Multicore configurations + ,e_bp_multicore_16_cfg = 15 + ,e_bp_multicore_12_cfg = 14 + ,e_bp_multicore_8_cfg = 13 + ,e_bp_multicore_6_cfg = 12 + ,e_bp_multicore_4_cfg = 11 + ,e_bp_multicore_3_cfg = 10 + ,e_bp_multicore_2_cfg = 9 + ,e_bp_multicore_1_megaparrot_cfg = 8 + ,e_bp_multicore_1_miniparrot_cfg = 7 + ,e_bp_multicore_1_cfg = 6 + + // Unicore configurations + ,e_bp_unicore_megaparrot_cfg = 5 + ,e_bp_unicore_miniparrot_cfg = 4 + ,e_bp_unicore_tinyparrot_cfg = 3 + ,e_bp_unicore_cfg = 2 + + // A custom BP configuration generated from `defines + ,e_bp_custom_cfg = 1 + // The default BP + ,e_bp_default_cfg = 0 + } bp_params_e; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_bedrock_if.svh b/designs/black-parrot/src/bp/bp_common_bedrock_if.svh new file mode 100644 index 0000000..bef45c9 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_bedrock_if.svh @@ -0,0 +1,205 @@ +/** + * bp_common_bedrock_if.svh + * + * This file defines the BedRock interface for BlackParrot, which is used to implement the + * coherence system between the CCEs and LCEs in BlackParrot and the networks between + * the CCE and Memory. + * + * The interface is defined as a set of parameterized structs. + * + * Users should use the declare_bp_bedrock_[lce/mem]_if and declare_bp_bedrock_[lce/mem]_if_widths + * macros to declare all of the widths and interface structs as needed for the LCE-CCE and MEM-CCE + * channels. + * + */ + +`ifndef BP_COMMON_BEDROCK_IF_SVH +`define BP_COMMON_BEDROCK_IF_SVH + + /* + * + * BedRock Interface + * + * The following enums and structs define the BedRock Interface within a BlackParrot coherence + * system. + * + * There are 5 message classes: + * 1. Request + * 2. Command + * 3. Fill + * 4. Response + * 5. Memory (Command and Response) + * + * The four LCE-CCE message types are carried on four physical networks: + * 1. Request (lowest priority) - from LCE to CCE + * 2. Command - from CCE to LCE + * 3. Fill - from LCE to LCE + * 4. Response (highest priority) - from LCE to CCE + * + * A Request message may cause a Command message. A Command message may cause a Fill or Response + * message. A Fill message may cause a Response message. + * A higher priority message may not cause a lower priority message to be sent, which avoids + * a circular dependency between message classes, and prevents certain instances of deadlock. + * + * The two memory networks (Command and Response) are carried on two physical networks between + * the UCE/CCE and Memory. + * + */ + + + /* + * bp_bedrock_***_header_s is the generic message struct for BedRock messages + * + * msg_type is a union of the LCE-CCE and Mem message types + * addr is the address used by the message + * size indicates the size in bytes of the message using the bp_bedrock_msg_size_e enum + * payload is an opaque field to the network, that is network specific (Req, Cmd, Fill, Resp, Mem) + * and each endpoint will interpret the field as appropriate + * + */ + // placed here for search: this macro defines types like bp_bedrock_mem_fwd_header_s + `define declare_bp_bedrock_header_s(addr_width_mp, payload_mp, name_mp) \ + typedef struct packed \ + { \ + payload_mp payload; \ + bp_bedrock_msg_size_e size; \ + logic [addr_width_mp-1:0] addr; \ + bp_bedrock_wr_subop_e subop; \ + bp_bedrock_msg_u msg_type; \ + } bp_bedrock_``name_mp``_header_s + + /* + * bp_bedrock_***_payload_s defines the payload for the various BedRock protocol channels + * + * Mem Payload: + * lce_id is the LCE that sent the initial request to the CCE + * way_id is the way within the cache miss address target set to fill the data in to + * state is the fill coherence state (may be changed if request was speculative) + * prefetch is set if the request was a prefetch from LCE (as opposed to CCE) + * uncached is set if the request was an uncached request from LCE + * speculative is set if the request was issued speculatively by the CCE + */ + + `define declare_bp_bedrock_payload_s(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + \ + typedef struct packed \ + { \ + logic [`BSG_SAFE_CLOG2(lce_assoc_mp)-1:0] lru_way_id; \ + bp_bedrock_req_non_excl_e non_exclusive; \ + logic [lce_id_width_mp-1:0] src_id; \ + logic [cce_id_width_mp-1:0] dst_id; \ + logic [did_width_mp-1:0] src_did; \ + } bp_bedrock_lce_req_payload_s; \ + \ + typedef struct packed \ + { \ + bp_coh_states_e target_state; \ + logic [`BSG_SAFE_CLOG2(lce_assoc_mp)-1:0] target_way_id; \ + logic [lce_id_width_mp-1:0] target; \ + bp_coh_states_e state; \ + logic [`BSG_SAFE_CLOG2(lce_assoc_mp)-1:0] way_id; \ + logic [cce_id_width_mp-1:0] src_id; \ + logic [lce_id_width_mp-1:0] dst_id; \ + logic [did_width_mp-1:0] src_did; \ + } bp_bedrock_lce_cmd_payload_s; \ + \ + typedef bp_bedrock_lce_cmd_payload_s bp_bedrock_lce_fill_payload_s; \ + \ + typedef struct packed \ + { \ + logic [lce_id_width_mp-1:0] src_id; \ + logic [cce_id_width_mp-1:0] dst_id; \ + logic [did_width_mp-1:0] src_did; \ + } bp_bedrock_lce_resp_payload_s; \ + \ + typedef struct packed \ + { \ + bp_coh_states_e state; \ + logic [`BSG_SAFE_CLOG2(lce_assoc_mp)-1:0] way_id; \ + logic [lce_id_width_mp-1:0] lce_id; \ + logic [did_width_mp-1:0] src_did; \ + logic prefetch; \ + logic uncached; \ + logic speculative; \ + } bp_bedrock_mem_fwd_payload_s; \ + \ + typedef bp_bedrock_mem_fwd_payload_s bp_bedrock_mem_rev_payload_s + + + /* + * BedRock Payload width macros + * + * Users should not need to call these directly and can instead use the BedRock Interface Macros + * that are defined further below. + */ + + `define bp_bedrock_req_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + (cce_id_width_mp+lce_id_width_mp+$bits(bp_bedrock_req_non_excl_e)+`BSG_SAFE_CLOG2(lce_assoc_mp)+did_width_mp) + + `define bp_bedrock_cmd_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + ((2*lce_id_width_mp)+cce_id_width_mp+(2*`BSG_SAFE_CLOG2(lce_assoc_mp))+(2*$bits(bp_coh_states_e))+did_width_mp) + + `define bp_bedrock_fill_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + `bp_bedrock_cmd_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) + + `define bp_bedrock_resp_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp) \ + (cce_id_width_mp+lce_id_width_mp+did_width_mp) + + `define bp_bedrock_fwd_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + (3+lce_id_width_mp+`BSG_SAFE_CLOG2(lce_assoc_mp)+$bits(bp_coh_states_e)+did_width_mp) + + `define bp_bedrock_rev_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + `bp_bedrock_fwd_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) + + `define declare_bp_bedrock_payload_widths(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + , localparam lce_req_payload_width_lp = `bp_bedrock_req_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + , localparam lce_cmd_payload_width_lp = `bp_bedrock_cmd_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + , localparam lce_fill_payload_width_lp = `bp_bedrock_fill_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + , localparam lce_resp_payload_width_lp = `bp_bedrock_resp_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp) \ + , localparam mem_fwd_payload_width_lp = `bp_bedrock_fwd_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + , localparam mem_rev_payload_width_lp = `bp_bedrock_rev_payload_width(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) + + /* + * BedRock Message width macros + * + * Users should not need to call these directly and can instead use the BedRock Interface Macros + * that are defined further below. + */ + + `define bp_bedrock_header_width(addr_width_mp, payload_width_mp) \ + ($bits(bp_bedrock_msg_u)+$bits(bp_bedrock_wr_subop_e)+addr_width_mp+$bits(bp_bedrock_msg_size_e)+payload_width_mp) + + `define declare_bp_bedrock_header_width(addr_width_mp, payload_width_mp, name_mp) \ + , localparam ``name_mp``_header_width_lp = `bp_bedrock_header_width(addr_width_mp, payload_width_mp) + + /* + * BedRock Interface Macros + */ + + `define declare_bp_bedrock_if_widths(addr_width_mp, lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + `declare_bp_bedrock_payload_widths(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + `declare_bp_bedrock_header_width(addr_width_mp, lce_req_payload_width_lp, lce_req) \ + `declare_bp_bedrock_header_width(addr_width_mp, lce_cmd_payload_width_lp, lce_cmd) \ + `declare_bp_bedrock_header_width(addr_width_mp, lce_fill_payload_width_lp, lce_fill) \ + `declare_bp_bedrock_header_width(addr_width_mp, lce_resp_payload_width_lp, lce_resp) \ + `declare_bp_bedrock_header_width(addr_width_mp, mem_fwd_payload_width_lp, mem_fwd) \ + `declare_bp_bedrock_header_width(addr_width_mp, mem_rev_payload_width_lp, mem_rev) + + `define declare_bp_bedrock_if(addr_width_mp, lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + `declare_bp_bedrock_payload_s(lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp); \ + `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_lce_req_payload_s, lce_req); \ + `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_lce_cmd_payload_s, lce_cmd); \ + `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_lce_fill_payload_s, lce_fill); \ + `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_lce_resp_payload_s, lce_resp); \ + `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_fwd_payload_s, mem_fwd); \ + `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_rev_payload_s, mem_rev) + + `define declare_bp_bedrock_generic_if_width(addr_width_mp, payload_width_mp, name_mp) \ + , localparam ``name_mp``_msg_payload_width_lp = payload_width_mp \ + `declare_bp_bedrock_header_width(addr_width_mp, ``name_mp``_msg_payload_width_lp, ``name_mp``) + + `define declare_bp_bedrock_generic_if(addr_width_mp, payload_width_mp, name_mp) \ + `declare_bp_bedrock_header_s(addr_width_mp, logic [payload_width_mp-1:0], ``name_mp``) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_bedrock_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_bedrock_pkgdef.svh new file mode 100644 index 0000000..5f75326 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_bedrock_pkgdef.svh @@ -0,0 +1,193 @@ + +`ifndef BP_COMMON_BEDROCK_PKGDEF_SVH +`define BP_COMMON_BEDROCK_PKGDEF_SVH + + /* + * BedRock Interface Enum Definitions + * + * These enums define the options for fields of the BedRock Interface messages. Clients should use + * the enums to set and compare fields of messages, rather than examining the bit pattern directly. + */ + + /* + * bp_bedrock_msg_size_e specifies the amount of data in the message, after the header + * + * Note: these enum values are fixed and should not be changed. This allows easily computing + * number of bytes in message = N bytes = (1 << e_bedrock_msg_size_N) + */ + typedef enum logic [2:0] + { + e_bedrock_msg_size_1 = 3'b000 // 1 byte + ,e_bedrock_msg_size_2 = 3'b001 // 2 bytes + ,e_bedrock_msg_size_4 = 3'b010 // 4 bytes + ,e_bedrock_msg_size_8 = 3'b011 // 8 bytes + ,e_bedrock_msg_size_16 = 3'b100 // 16 bytes + ,e_bedrock_msg_size_32 = 3'b101 // 32 bytes + ,e_bedrock_msg_size_64 = 3'b110 // 64 bytes + ,e_bedrock_msg_size_128 = 3'b111 // 128 bytes + } bp_bedrock_msg_size_e; + + /* + * bp_bedrock_fwd_type_e specifies the memory command from the UCE/CCE + * + * There are three types of commands: + * 1. Access to memory that should be cached in L2/LLC (rd/wr) + * 2. Access to memory that should remain uncached by L2/LLC (uc_rd/uc_wr) + * 3. Prefetch access to memory that should be cached in L2/LLC (pre) + * + * Cacheability of the data at the L1/LCE level is determined by the uncached bit within + * the payload of the message, and is managed by the LCE/CCE. This information is not + * exposed to memory/L2/LLC, allowing the CCE to maintain coherence for all required + * blocks. + * + */ + typedef enum logic [3:0] + { + e_bedrock_mem_rd = 4'b0000 // Cache block fetch / load / Get (cached in L2/LLC) + ,e_bedrock_mem_wr = 4'b0001 // Cache block write / writeback / store / Put (cached in L2/LLC) + ,e_bedrock_mem_amo = 4'b0010 // Atomic operation in L2/LLC + ,e_bedrock_mem_pre = 4'b1000 // Pre-fetch block request from CCE, fill into L2/LLC if able + } bp_bedrock_fwd_type_e; + + // rev messages are identical to fwd messages and can be safely casted between + typedef bp_bedrock_fwd_type_e bp_bedrock_rev_type_e; + + /* + * bp_bedrock_req_type_e specifies whether the containing message is related to a read or write + * cache miss request from and LCE. + */ + typedef enum logic [3:0] + { + e_bedrock_req_rd_miss = 4'b0000 // Read-miss + ,e_bedrock_req_wr_miss = 4'b0001 // Write-miss + ,e_bedrock_req_uc_rd = 4'b0010 // Uncached Read + ,e_bedrock_req_uc_wr = 4'b0011 // Uncached Write + ,e_bedrock_req_uc_amo = 4'b0100 // AMO + } bp_bedrock_req_type_e; + + /* + * bp_bedrock_wr_subop_e specifies the type of store + * Valid only for + * req: e_bedrock_req_uc_wr, e_bedrock_req_uc_amo + * mem_fwd: e_bedrock_mem_uc_wr, e_bedrock_mem_amo + */ + typedef enum logic [3:0] + { + e_bedrock_store = 4'b0000 + ,e_bedrock_amolr = 4'b0001 + ,e_bedrock_amosc = 4'b0010 + ,e_bedrock_amoswap = 4'b0011 + ,e_bedrock_amoadd = 4'b0100 + ,e_bedrock_amoxor = 4'b0101 + ,e_bedrock_amoand = 4'b0110 + ,e_bedrock_amoor = 4'b0111 + ,e_bedrock_amomin = 4'b1000 + ,e_bedrock_amomax = 4'b1001 + ,e_bedrock_amominu = 4'b1010 + ,e_bedrock_amomaxu = 4'b1011 + } bp_bedrock_wr_subop_e; + + + /* + * bp_bedrock_cmd_type_e defines commands from CCE to LCE + */ + typedef enum logic [3:0] + { + e_bedrock_cmd_sync = 4'b0000 // sync/ready, respond with sync_ack + ,e_bedrock_cmd_set_clear = 4'b0001 // clear cache set of address field + ,e_bedrock_cmd_inv = 4'b0010 // invalidate block, respond with inv_ack + ,e_bedrock_cmd_st = 4'b0011 // set state + ,e_bedrock_cmd_data = 4'b0100 // data, adddress, and state to LCE, i.e., cache block fill + ,e_bedrock_cmd_st_wakeup = 4'b0101 // set state and wakeup (upgrade response, state only) + ,e_bedrock_cmd_wb = 4'b0110 // writeback block + ,e_bedrock_cmd_st_wb = 4'b0111 // set state and writeback block + ,e_bedrock_cmd_tr = 4'b1000 // transfer block + ,e_bedrock_cmd_st_tr = 4'b1001 // set state and transfer block + ,e_bedrock_cmd_st_tr_wb = 4'b1010 // set state, transfer, and writeback block + ,e_bedrock_cmd_uc_data = 4'b1011 // uncached data + ,e_bedrock_cmd_uc_st_done = 4'b1100 // uncached request complete + } bp_bedrock_cmd_type_e; + + /* + * bp_bedrock_fill_type_e defines LCE to LCE messages + */ + typedef enum logic [3:0] + { + e_bedrock_fill_data = e_bedrock_cmd_data // data, adddress, and state to LCE, i.e., cache block fill + } bp_bedrock_fill_type_e; + + /* + * bp_bedrock_resp_type_e defines the different LCE-CCE response messages + */ + typedef enum logic [3:0] + { + e_bedrock_resp_sync_ack = 4'b0000 // ack to sync command. LCE is ready for cacheable operation + ,e_bedrock_resp_inv_ack = 4'b0001 // ack to invalidate. Block is now invalid at LCE + ,e_bedrock_resp_coh_ack = 4'b0010 // ack that coherence request is complete + ,e_bedrock_resp_wb = 4'b0011 // Normal Writeback Response (full data) + ,e_bedrock_resp_null_wb = 4'b0100 // Null Writeback Response (no data) + } bp_bedrock_resp_type_e; + + /* + * bp_bedrock_msg_u is a union that holds the LCE-CCE Req, Cmd, and Resp message types + */ + typedef union packed + { + bp_bedrock_req_type_e req; + bp_bedrock_cmd_type_e cmd; + bp_bedrock_fill_type_e fill; + bp_bedrock_resp_type_e resp; + bp_bedrock_fwd_type_e fwd; + bp_bedrock_rev_type_e rev; + } bp_bedrock_msg_u; + + /* + * bp_bedrock_req_non_excl_e specifies whether the requesting LCE would like a read-miss request + * to be returned in an exclusive coherence state if possible or not. An I$, for example, should + * set this bit to indicate that there is no benefit in the CCE granting a cache block in the E + * state as opposed to the S state in a MESI protocol. The CCE treats this bit as a hint, and is + * not required to follow it. + */ + typedef enum logic + { + e_bedrock_req_excl = 1'b0 // exclusive cache line request (read-only, exclusive request) + ,e_bedrock_req_non_excl = 1'b1 // non-exclusive cache line request (read-only, shared request) + } bp_bedrock_req_non_excl_e; + + /* + * bp_cce_coh_states_e defines the coherence states available in BlackParrot. Each bit represents + * a property of the cache block as defined below: + * 0: Shared (not Exclusive) + * 1: Owned + * 2: Potentially Dirty + * + * These properties are derived from "A Primer on Memory Consistency and Cache Coherence", and + * they allow an easy definition for the common MOESIF coherence states. + */ + typedef enum logic [2:0] + { + e_COH_I = 3'b000 // Invalid + ,e_COH_S = 3'b001 // Shared - clean, not owned, shared (not exclusive) + ,e_COH_E = 3'b010 // Exclusive - clean, owned, not shared (exclusive) + ,e_COH_F = 3'b011 // Forward - clean, owned, shared (not exclusive) + // unused = 3'b100 // potentially dirty, not owned, not shared (exclusive) + // unused = 3'b101 // potentially dirty, not owned, shared (not exclusive) + ,e_COH_M = 3'b110 // Modified - potentially dirty, owned, not shared (exclusive) + ,e_COH_O = 3'b111 // Owned - potentially dirty, owned, shared (not exclusive) + } bp_coh_states_e; + + /* + * payload mask parameters + * + * These masks define the BedRock message types that carry data. + * + */ + localparam mem_fwd_stream_mask_gp = (1 << e_bedrock_mem_wr) | (1 << e_bedrock_mem_amo); + localparam mem_rev_stream_mask_gp = (1 << e_bedrock_mem_rd) | (1 << e_bedrock_mem_amo); + localparam lce_req_stream_mask_gp = (1 << e_bedrock_req_uc_wr) | (1 << e_bedrock_req_uc_amo); + localparam lce_cmd_stream_mask_gp = (1 << e_bedrock_cmd_data) | (1 << e_bedrock_cmd_uc_data); + localparam lce_fill_stream_mask_gp = (1 << e_bedrock_fill_data); + localparam lce_resp_stream_mask_gp = (1 << e_bedrock_resp_wb); + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_bedrock_wormhole_defines.svh b/designs/black-parrot/src/bp/bp_common_bedrock_wormhole_defines.svh new file mode 100644 index 0000000..b23795a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_bedrock_wormhole_defines.svh @@ -0,0 +1,87 @@ +/** + * + * Name: + * bp_common_bedrock_wormhole_defines.svh + * + * Note: standard bsg_wormhole messages are {payload, len, cord} + * The messages defined here contain extra "header" fields specific + * to the networks that are considered part of the payload by the regular + * bsg_wormhole networks and routers. + * + */ + +`ifndef BP_COMMON_BEDROCK_WORMHOLE_DEFINES_SVH +`define BP_COMMON_BEDROCK_WORMHOLE_DEFINES_SVH + +`include "bsg_noc_links.svh" +`include "bsg_wormhole_router.svh" + + /* + * BedRock LCE Coherence Network Wormhole Packet Definitions + */ + + `define declare_bp_bedrock_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, struct_name_mp) \ + `declare_bsg_wormhole_concentrator_header_s(cord_width_mp, len_width_mp, cid_width_mp, bsg_``struct_name_mp``_router_hdr_s); \ + typedef struct packed \ + { \ + logic [`bp_bedrock_wormhole_packet_pad_width(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, $bits(msg_hdr_name_mp))-1:0] \ + pad; \ + msg_hdr_name_mp msg_hdr; \ + bsg_``struct_name_mp``_router_hdr_s rtr_hdr; \ + } bp_``struct_name_mp``_wormhole_header_s + + `define declare_bp_bedrock_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, struct_name_mp, data_width_mp) \ + `declare_bp_bedrock_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, struct_name_mp); \ + \ + typedef struct packed \ + { \ + logic [data_width_mp-1:0] data; \ + bp_``struct_name_mp``_wormhole_header_s header; \ + } bp_``struct_name_mp``_wormhole_packet_s + + `define bp_bedrock_wormhole_packet_pad_width(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_width_mp) \ + (flit_width_mp-((cord_width_mp+cid_width_mp+len_width_mp+msg_hdr_width_mp)%flit_width_mp)) + + `define bp_bedrock_wormhole_header_width(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_width_mp) \ + (cord_width_mp + len_width_mp + cid_width_mp + msg_hdr_width_mp \ + + `bp_bedrock_wormhole_packet_pad_width(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_width_mp) \ + ) + + `define bp_bedrock_wormhole_packet_width(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_width_mp, data_width_mp) \ + (data_width_mp \ + + `bp_bedrock_wormhole_header_width(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_width_mp) \ + ) + + // note: cid_width_mp is counted as part of the payload for a standard wormhole message + // wormhole message = {payload, len, cord} + `define bp_bedrock_wormhole_payload_width(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_width_mp, data_width_mp) \ + (`bp_bedrock_wormhole_packet_width(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_width_mp, data_width_mp) \ + - len_width_mp - cord_width_mp \ + ) + + `define declare_bp_lce_req_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp) \ + `declare_bp_bedrock_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, lce_req) + + `define declare_bp_lce_cmd_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp) \ + `declare_bp_bedrock_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, lce_cmd) + + `define declare_bp_lce_fill_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp) \ + `declare_bp_bedrock_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, lce_fill) + + `define declare_bp_lce_resp_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp) \ + `declare_bp_bedrock_wormhole_header_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, lce_resp) + + `define declare_bp_lce_req_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, data_width_mp) \ + `declare_bp_bedrock_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, lce_req, data_width_mp) + + `define declare_bp_lce_cmd_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, data_width_mp) \ + `declare_bp_bedrock_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, lce_cmd, data_width_mp) + + `define declare_bp_lce_fill_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, data_width_mp) \ + `declare_bp_bedrock_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, lce_fill, data_width_mp) + + `define declare_bp_lce_resp_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, data_width_mp) \ + `declare_bp_bedrock_wormhole_packet_s(flit_width_mp, cord_width_mp, len_width_mp, cid_width_mp, msg_hdr_name_mp, lce_resp, data_width_mp) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_cache_engine_if.svh b/designs/black-parrot/src/bp/bp_common_cache_engine_if.svh new file mode 100644 index 0000000..e255b77 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_cache_engine_if.svh @@ -0,0 +1,109 @@ +/** + * bp_common_cache_engine.svh + */ + +`ifndef BP_COMMON_CACHE_ENGINE_SVH +`define BP_COMMON_CACHE_ENGINE_SVH + + `define declare_bp_cache_req_s(data_width_mp, paddr_width_mp, id_width_mp, cache_name_mp) \ + typedef struct packed \ + { \ + logic [id_width_mp-1:0] id; \ + logic hit; \ + logic [data_width_mp-1:0] data; \ + bp_cache_req_size_e size; \ + logic [paddr_width_mp-1:0] addr; \ + bp_cache_req_msg_type_e msg_type; \ + bp_cache_req_wr_subop_e subop; \ + } bp_``cache_name_mp``_req_s + + `define bp_cache_req_width(data_width_mp, paddr_width_mp, id_width_mp, cache_name_mp) \ + (id_width_mp+1+data_width_mp+$bits(bp_cache_req_size_e)+paddr_width_mp+$bits(bp_cache_req_msg_type_e)+$bits(bp_cache_req_wr_subop_e)) + + `define declare_bp_cache_req_metadata_s(ways_mp, cache_name_mp) \ + typedef struct packed \ + { \ + logic [`BSG_SAFE_CLOG2(ways_mp)-1:0] hit_or_repl_way; \ + logic dirty; \ + } bp_``cache_name_mp``_req_metadata_s + + `define bp_cache_req_metadata_width(ways_mp) \ + (`BSG_SAFE_CLOG2(ways_mp)+1) + + `define bp_cache_data_mem_pkt_width(sets_mp, ways_mp, block_width_mp, fill_width_mp) \ + (`BSG_SAFE_CLOG2(sets_mp)+`BSG_SAFE_CLOG2(ways_mp)+fill_width_mp+(block_width_mp/fill_width_mp)+$bits(bp_cache_data_mem_opcode_e)) + + `define declare_bp_cache_tag_mem_pkt_s(sets_mp, ways_mp, tag_width_mp, cache_name_mp) \ + typedef struct packed \ + { \ + logic [`BSG_SAFE_CLOG2(sets_mp)-1:0] index; \ + logic [`BSG_SAFE_CLOG2(ways_mp)-1:0] way_id; \ + bp_coh_states_e state; \ + logic [tag_width_mp-1:0] tag; \ + bp_cache_tag_mem_opcode_e opcode; \ + } bp_``cache_name_mp``_tag_mem_pkt_s + + `define bp_cache_tag_mem_pkt_width(sets_mp, ways_mp, tag_width_mp) \ + (`BSG_SAFE_CLOG2(sets_mp)+`BSG_SAFE_CLOG2(ways_mp)+$bits(bp_coh_states_e)+tag_width_mp+$bits(bp_cache_tag_mem_opcode_e)) + + `define declare_bp_cache_tag_info_s(tag_width_mp, cache_name_mp) \ + typedef struct packed { \ + logic [$bits(bp_coh_states_e)-1:0] state; \ + logic [tag_width_mp-1:0] tag; \ + } bp_``cache_name_mp``_tag_info_s + + `define bp_cache_tag_info_width(tag_width_mp) \ + ($bits(bp_coh_states_e)+tag_width_mp) + + `define declare_bp_cache_stat_mem_pkt_s(sets_mp, ways_mp, cache_name_mp) \ + typedef struct packed \ + { \ + logic [`BSG_SAFE_CLOG2(sets_mp)-1:0] index; \ + logic [`BSG_SAFE_CLOG2(ways_mp)-1:0] way_id; \ + bp_cache_stat_mem_opcode_e opcode; \ + } bp_``cache_name_mp``_stat_mem_pkt_s + + `define bp_cache_stat_mem_pkt_width(sets_mp, ways_mp) \ + (`BSG_SAFE_CLOG2(sets_mp)+`BSG_SAFE_CLOG2(ways_mp)+$bits(bp_cache_stat_mem_opcode_e)) + + `define declare_bp_cache_stat_info_s(ways_mp, cache_name_mp) \ + typedef struct packed \ + { \ + logic [`BSG_SAFE_MINUS(ways_mp, 2):0] lru; \ + logic [ways_mp-1:0] dirty; \ + } bp_``cache_name_mp``_stat_info_s + + // Direct mapped caches need 2-bits in the stat info + `define bp_cache_stat_info_width(ways_mp) \ + (`BSG_MAX(2,2*ways_mp-1)) + + `define declare_bp_cache_data_mem_pkt_s(sets_mp, ways_mp, block_width_mp, fill_width_mp, cache_name_mp) \ + typedef struct packed \ + { \ + logic [`BSG_SAFE_CLOG2(sets_mp)-1:0] index; \ + logic [`BSG_SAFE_CLOG2(ways_mp)-1:0] way_id; \ + logic [fill_width_mp-1:0] data; \ + logic [(block_width_mp/fill_width_mp)-1:0] fill_index; \ + bp_cache_data_mem_opcode_e opcode; \ + } bp_``cache_name_mp``_data_mem_pkt_s + + `define declare_bp_cache_engine_generic_if(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp, cache_name_mp) \ + `declare_bp_cache_req_s(data_width_mp, addr_width_mp, id_width_mp, cache_name_mp); \ + `declare_bp_cache_req_metadata_s(ways_mp, cache_name_mp); \ + `declare_bp_cache_data_mem_pkt_s(sets_mp, ways_mp, block_width_mp, fill_width_mp, cache_name_mp); \ + `declare_bp_cache_tag_mem_pkt_s(sets_mp, ways_mp, tag_width_mp, cache_name_mp); \ + `declare_bp_cache_tag_info_s(tag_width_mp, cache_name_mp); \ + `declare_bp_cache_stat_mem_pkt_s(sets_mp, ways_mp, cache_name_mp); \ + `declare_bp_cache_stat_info_s(ways_mp, cache_name_mp) + + `define declare_bp_cache_engine_generic_if_widths(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp, cache_name_mp) \ + , localparam ``cache_name_mp``_req_width_lp = `bp_cache_req_width(data_width_mp, addr_width_mp, id_width_mp, cache_name_mp) \ + , localparam ``cache_name_mp``_req_metadata_width_lp = `bp_cache_req_metadata_width(ways_mp) \ + , localparam ``cache_name_mp``_data_mem_pkt_width_lp = `bp_cache_data_mem_pkt_width(sets_mp, ways_mp, block_width_mp, fill_width_mp) \ + , localparam ``cache_name_mp``_tag_mem_pkt_width_lp = `bp_cache_tag_mem_pkt_width(sets_mp, ways_mp, tag_width_mp) \ + , localparam ``cache_name_mp``_tag_info_width_lp = `bp_cache_tag_info_width(tag_width_mp) \ + , localparam ``cache_name_mp``_stat_mem_pkt_width_lp = `bp_cache_stat_mem_pkt_width(sets_mp, ways_mp) \ + , localparam ``cache_name_mp``_stat_info_width_lp = `bp_cache_stat_info_width(ways_mp) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_cache_engine_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_cache_engine_pkgdef.svh new file mode 100644 index 0000000..897409c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_cache_engine_pkgdef.svh @@ -0,0 +1,85 @@ + +`ifndef BP_COMMON_CACHE_ENGINE_PKGDEF_SVH +`define BP_COMMON_CACHE_ENGINE_PKGDEF_SVH + + typedef enum logic [3:0] + { + e_miss_load = 4'b0000 + ,e_miss_store = 4'b0001 + ,e_wt_store = 4'b0010 + ,e_uc_load = 4'b0011 + ,e_uc_store = 4'b0100 + ,e_uc_amo = 4'b0101 + ,e_cache_clean = 4'b0110 + ,e_cache_inval = 4'b0111 + ,e_cache_flush = 4'b1000 + ,e_cache_bclean = 4'b1011 + ,e_cache_binval = 4'b1100 + ,e_cache_bflush = 4'b1101 + } bp_cache_req_msg_type_e; + + typedef enum logic [2:0] + { + e_size_1B = 3'b000 + ,e_size_2B = 3'b001 + ,e_size_4B = 3'b010 + ,e_size_8B = 3'b011 + ,e_size_16B = 3'b100 + ,e_size_32B = 3'b101 + ,e_size_64B = 3'b110 + } bp_cache_req_size_e; + + // Relevant for uc_store and uc_amo + typedef enum logic [3:0] + { + // Return value of e_req_store is undefined, clients should not + // depend on it being zero + e_req_store = 4'b0000 + ,e_req_amolr = 4'b0001 + ,e_req_amosc = 4'b0010 + ,e_req_amoswap = 4'b0011 + ,e_req_amoadd = 4'b0100 + ,e_req_amoxor = 4'b0101 + ,e_req_amoand = 4'b0110 + ,e_req_amoor = 4'b0111 + ,e_req_amomin = 4'b1000 + ,e_req_amomax = 4'b1001 + ,e_req_amominu = 4'b1010 + ,e_req_amomaxu = 4'b1011 + } bp_cache_req_wr_subop_e; + + typedef enum logic [1:0] + { // write cache block + e_cache_data_mem_write + // read cache block + ,e_cache_data_mem_read + // write uncached load data + ,e_cache_data_mem_uncached + } bp_cache_data_mem_opcode_e; + + // Tag mem pkt opcodes + typedef enum logic [2:0] + {// clear all blocks in a set for a given index + e_cache_tag_mem_set_clear + // set tag and coherence state for given index and way_id + ,e_cache_tag_mem_set_tag + // set coherence state for given index and way_id + ,e_cache_tag_mem_set_state + // invalidate all ways in the set + ,e_cache_tag_mem_set_inval + // read tag mem packets for writeback and transfer (Used for UCE) + ,e_cache_tag_mem_read + } bp_cache_tag_mem_opcode_e; + + // Stat mem pkt opcodes + typedef enum logic [1:0] + { // clear all dirty bits and LRU bits to zero for given index. + e_cache_stat_mem_set_clear + // read stat_info for given index. + ,e_cache_stat_mem_read + // clear dirty bit for given index and way_id. + ,e_cache_stat_mem_clear_dirty + } bp_cache_stat_mem_opcode_e; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_cache_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_cache_pkgdef.svh new file mode 100644 index 0000000..4de2f73 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_cache_pkgdef.svh @@ -0,0 +1,52 @@ + +`ifndef BP_COMMON_CACHE_PKGDEF_SVH +`define BP_COMMON_CACHE_PKGDEF_SVH + + ///////////////////////////////////////////////////// + // bsg_cache operations // + ///////////////////////////////////////////////////// + // TAGST // st; address = way, index; data = tag // + // TAGFL // st; address = way, index; data = X // + // TAGLV // ld; address = way, index; data = X // + // TAGLA // ld; address = way, index; data = X // + ///////////////////////////////////////////////////// + // AFL // st; address = address ; data = X // + // AFLINV // st; address = address ; data = X // + // AINV // st; address = address ; data = X // + // ALOCK // st; address = address ; data = X // + // AUNLOCK // st; address = address ; data = X // + + localparam cache_base_addr_gp = (dev_id_width_gp+dev_addr_width_gp)'('h0400_0000); + + // This could be more efficiently matched to actual L2 architecture + typedef struct packed + { + logic [2:0] bank; + logic [2:0] way; + logic [7:0] index; + logic [5:0] addr; + } bp_me_l2_csr_addr_s; + + // bedrock addr[15:12] -> cache bank + // bedrock data[X : 3] -> cache addr[X : 3] + // bedrock data[3 : 0] -> cache data (used for lock op) + // 0000_0000_0000_00aa_a000 + localparam cache_afl_match_addr_gp = (dev_addr_width_gp)'('b0000_0000_0000_0000_0000); + localparam cache_aflinv_match_addr_gp = (dev_addr_width_gp)'('b0000_0000_0000_0000_1000); + localparam cache_ainv_match_addr_gp = (dev_addr_width_gp)'('b0000_0000_0000_0001_0000); + localparam cache_alock_match_addr_gp = (dev_addr_width_gp)'('b0000_0000_0000_0001_1000); + + // bedrock addr[15:12] -> cache bank + // bedrock addr[11: 6] -> way, index -> cache addr[addr:block_offset] + // bedrock data -> tag -> cache data + // bbbw_wwii_iiii_iioa_a000 + localparam cache_tagfl_match_addr_gp = (dev_addr_width_gp)'('b????_????_????_??10_0000); + localparam cache_taglv_match_addr_gp = (dev_addr_width_gp)'('b????_????_????_??10_1000); + localparam cache_tagla_match_addr_gp = (dev_addr_width_gp)'('b????_????_????_??11_0000); + localparam cache_tagst_match_addr_gp = (dev_addr_width_gp)'('b????_????_????_??11_1000); + + localparam cache_tagop_match_addr_gp = (dev_addr_width_gp)'('b????_????_????_??1?_????); + localparam cache_addrop_match_addr_gp = (dev_addr_width_gp)'('b????_????_????_??0?_????); + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_cfg_bus_defines.svh b/designs/black-parrot/src/bp/bp_common_cfg_bus_defines.svh new file mode 100644 index 0000000..bc1023a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_cfg_bus_defines.svh @@ -0,0 +1,35 @@ +`ifndef BP_COMMON_CFG_BUS_DEFINES_SVH +`define BP_COMMON_CFG_BUS_DEFINES_SVH + + `define declare_bp_cfg_bus_s(vaddr_width_mp, hio_width_mp, core_id_width_mp, cce_id_width_mp, lce_id_width_mp, did_width_mp) \ + typedef struct packed \ + { \ + logic freeze; \ + logic [vaddr_width_mp-1:0] npc; \ + logic [core_id_width_mp-1:0] core_id; \ + logic [lce_id_width_mp-1:0] icache_id; \ + bp_lce_mode_e icache_mode; \ + logic [lce_id_width_mp-1:0] dcache_id; \ + bp_lce_mode_e dcache_mode; \ + logic [cce_id_width_mp-1:0] cce_id; \ + bp_cce_mode_e cce_mode; \ + logic [hio_width_mp-1:0] hio_mask; \ + logic [did_width_mp-1:0] did; \ + } bp_cfg_bus_s + + `define bp_cfg_bus_width(vaddr_width_mp, hio_width_mp, core_id_width_mp, cce_id_width_mp, lce_id_width_mp, did_width_mp) \ + (1 \ + + vaddr_width_mp \ + + core_id_width_mp \ + + lce_id_width_mp \ + + $bits(bp_lce_mode_e) \ + + lce_id_width_mp \ + + $bits(bp_lce_mode_e) \ + + cce_id_width_mp \ + + $bits(bp_cce_mode_e) \ + + hio_width_mp \ + + did_width_mp \ + ) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_cfg_bus_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_cfg_bus_pkgdef.svh new file mode 100644 index 0000000..95fb2e5 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_cfg_bus_pkgdef.svh @@ -0,0 +1,55 @@ + +`ifndef BP_COMMON_CFG_BUS_PKGDEF_SVH +`define BP_COMMON_CFG_BUS_PKGDEF_SVH + + // LCE Operating Mode + // e_lce_mode_uncached: Cache treats all requests as uncached + // e_lce_mode_normal: Cache acts normally + // e_lce_mode_nonspec: Cache acts mostly normally, but will not send a speculative miss + typedef enum logic [1:0] + { + e_lce_mode_uncached = 0 + ,e_lce_mode_normal = 1 + ,e_lce_mode_nonspec = 2 + } bp_lce_mode_e; + + // CCE Operating Mode + // e_cce_mode_uncached: CCE supports uncached requests only + // e_cce_mode_normal: CCE supports cacheable requests + typedef enum logic + { + e_cce_mode_uncached = 0 + ,e_cce_mode_normal = 1 + } bp_cce_mode_e; + + // The overall memory map of the config link is: + // 16'h0000 - 16'h01ff: chip level config + // 16'h0200 - 16'h03ff: fe config + // 16'h0400 - 16'h05ff: be config + // 16'h0600 - 16'h07ff: me config + // 16'h0800 - 16'h7fff: reserved + // 16'h8000 - 16'h8fff: cce ucode + + localparam cfg_base_addr_gp = (dev_id_width_gp+dev_addr_width_gp)'('h0020_0000); + localparam cfg_match_addr_gp = (dev_id_width_gp+dev_addr_width_gp)'('h002?_????); + + localparam cfg_unused_00_gp = (dev_addr_width_gp)'('h0_0000); + localparam cfg_reg_freeze_gp = (dev_addr_width_gp)'('h0_0008); + localparam cfg_reg_npc_gp = (dev_addr_width_gp)'('h0_0010); + localparam cfg_reg_core_id_gp = (dev_addr_width_gp)'('h0_0018); + localparam cfg_reg_did_gp = (dev_addr_width_gp)'('h0_0020); + localparam cfg_reg_cord_gp = (dev_addr_width_gp)'('h0_0028); + localparam cfg_reg_host_did_gp = (dev_addr_width_gp)'('h0_0030); + // Used until PMP are setup properly + localparam cfg_reg_hio_mask_gp = (dev_addr_width_gp)'('h0_0038); + localparam cfg_reg_icache_id_gp = (dev_addr_width_gp)'('h0_0200); + localparam cfg_reg_icache_mode_gp = (dev_addr_width_gp)'('h0_0208); + localparam cfg_reg_dcache_id_gp = (dev_addr_width_gp)'('h0_0400); + localparam cfg_reg_dcache_mode_gp = (dev_addr_width_gp)'('h0_0408); + localparam cfg_reg_cce_id_gp = (dev_addr_width_gp)'('h0_0600); + localparam cfg_reg_cce_mode_gp = (dev_addr_width_gp)'('h0_0608); + localparam cfg_mem_cce_ucode_base_gp = (dev_addr_width_gp)'('h0_8000); + localparam cfg_mem_cce_ucode_match_gp = (dev_addr_width_gp)'('h0_8???); + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_clint_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_clint_pkgdef.svh new file mode 100644 index 0000000..9dc11f1 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_clint_pkgdef.svh @@ -0,0 +1,28 @@ + +`ifndef BP_COMMON_CLINT_PKGDEF_SVH +`define BP_COMMON_CLINT_PKGDEF_SVH + + + localparam clint_base_addr_gp = (dev_id_width_gp+dev_addr_width_gp)'('h30_0000); + localparam clint_match_addr_gp = (dev_id_width_gp+dev_addr_width_gp)'('h30_0???); + + localparam mipi_reg_base_addr_gp = dev_addr_width_gp'('h0_0000); + localparam mipi_reg_match_addr_gp = dev_addr_width_gp'('h0_0???); + + localparam mtimecmp_reg_base_addr_gp = dev_addr_width_gp'('h0_4000); + localparam mtimecmp_reg_match_addr_gp = dev_addr_width_gp'('h0_4???); + + localparam mtimesel_reg_base_addr_gp = dev_addr_width_gp'('h0_8000); + localparam mtimesel_reg_match_addr_gp = dev_addr_width_gp'('h0_8???); + + localparam mtime_reg_addr_gp = dev_addr_width_gp'('h0_bff8); + localparam mtime_reg_match_addr_gp = dev_addr_width_gp'('h0_bff?); + + localparam plic_reg_base_addr_gp = dev_addr_width_gp'('h0_b000); + localparam plic_reg_match_addr_gp = dev_addr_width_gp'('h0_b00?); + + localparam debug_reg_base_addr_gp = dev_addr_width_gp'('h0_c000); + localparam debug_reg_match_addr_gp = dev_addr_width_gp'('h0_c???); + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_core_if.svh b/designs/black-parrot/src/bp/bp_common_core_if.svh new file mode 100644 index 0000000..1154075 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_core_if.svh @@ -0,0 +1,261 @@ +/** + * + * bp_common_core_if.svh + * + * bp_core_interface.svh declares the interface between the BlackParrot Front End + * and Back End For simplicity and flexibility, these signals are declared as + * parameterizable structures. Each structure declares its width separately to + * avoid preprocessor ordering issues. + * + * Logically, the BE controls the FE and may command the FE to flush all the states, + * redirect the PC, etc. The FE uses its queue to supply the BE with (possibly + * speculative) instruction/PC pairs and inform the BE of any exceptions that have + * occurred within the unit (e.g., misaligned instruction fetch) so the BE may + * ensure all exceptions are taken precisely. The BE checks the PC in the + * instruction/PC pairs to make sure that the FE predictions correspond to + * correct architectural execution. + * + * NOTE: VCS can only handle packed unions where each member is the same size. Therefore, we + * need to do some macro hacking to get parameterized unions to work nicely. + * NOTE: Potentially could make sense to separate two unidirectional interface files. This one + * is a little overwhelming. + */ + +`ifndef BP_COMMON_CORE_IF_SVH +`define BP_COMMON_CORE_IF_SVH + + /* + * Clients need only use this macro to declare all parameterized structs for FE<->BE interface. + */ + `define declare_bp_core_if(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + /* \ + * \ + * bp_fe_queue_s contains the pc/instruction pair, along branch metadata for the branch \ + * predictor to update its internal data based on feedback from the BE as to \ + * whether this particular PC/instruction pair was correct. The BE does not look \ + * at the branch metadata, since this would mean that the BE implementation is \ + * tightly coupled to the FE implementation. \ + * Exceptions serviced inline with instructions. Otherwise we have no way of knowing if this \ + * exception is eclipsed by a preceding branch mispredict. Therefore, we support exceptions as \ + * alternate message types. \ + */ \ + typedef struct packed \ + { \ + logic [vaddr_width_mp-1:0] pc; \ + logic [fetch_width_p-1:0] instr; \ + logic [branch_metadata_fwd_width_mp-1:0] branch_metadata_fwd; \ + logic [fetch_ptr_p-1:0] count; \ + bp_fe_queue_type_e msg_type; \ + } bp_fe_queue_s; \ + \ + /* \ + * bp_fe_cmd_pc_redirect_operands_s provides the information needed during the pc \ + * redirection. command_queue_subopcode provides the reasons for pc redirection. \ + * branch_metadata_fwd provides the information of branch misprediction. \ + * translation_en tells whether the pc is virtual or physical in the case of context switch. \ + * priv is the privilege mode being switched to. \ + */ \ + typedef struct packed \ + { \ + bp_fe_command_queue_subopcodes_e subopcode; \ + logic [branch_metadata_fwd_width_mp-1:0] branch_metadata_fwd; \ + bp_fe_misprediction_reason_e misprediction_reason; \ + logic translation_en; \ + logic [1:0] priv; \ + \ + logic [`bp_fe_cmd_pc_redirect_operands_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)-1:0] \ + padding; \ + } bp_fe_cmd_pc_redirect_operands_s; \ + \ + /* \ + * bp_fe_attaboy_s provides branch prediction metadata back to the FE on the case of \ + * correct prediction, so that the FE can update its predictors accordingly. \ + */ \ + typedef struct packed \ + { \ + logic taken; \ + logic [branch_metadata_fwd_width_mp-1:0] branch_metadata_fwd; \ + \ + logic [`bp_fe_cmd_attaboy_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)-1:0] \ + padding; \ + } bp_fe_cmd_attaboy_s; \ + \ + /* \ + * bp_pte_leaf_s provides the information needed in the case of the page \ + * walk. The bp_pte_leaf_s contains the physical address and the \ + * additional bits in the page table entry (pte). \ + */ \ + typedef struct packed \ + { \ + logic [paddr_width_mp-page_offset_width_gp-1:0] ptag; \ + logic gigapage; \ + logic megapage; \ + logic a; \ + logic d; \ + logic u; \ + logic x; \ + logic w; \ + logic r; \ + } bp_pte_leaf_s; \ + \ + /* \ + * bp_fe_cmd_itlb_fill_s provides the virtual, physical translation plus the \ + * additional permission bits to the itlb in the case of page walk. Once the \ + * frontend sends the page fill request to the backend, the backend performs the \ + * page walk, and responds to the frontend with bp_fe_cmd_itlb_fill_s. \ + */ \ + typedef struct packed \ + { \ + bp_pte_leaf_s pte_leaf; \ + logic [instr_width_gp-1:0] instr; \ + logic [fetch_ptr_p-1:0] count; \ + logic [`bp_fe_cmd_itlb_fill_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)-1:0] \ + padding; \ + } bp_fe_cmd_itlb_fill_s; \ + \ + /* \ + * bp_fe_cmd_icache_fill_s indicates the alignment offset of the original \ + * miss which triggered this fill request. It carries partial instructions; \ + * the frontend will issue the remaining memory request upon receipt. \ + */ \ + typedef struct packed \ + { \ + logic [instr_width_gp-1:0] instr; \ + logic [fetch_ptr_p-1:0] count; \ + logic [`bp_fe_cmd_icache_fill_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)-1:0] \ + padding; \ + } bp_fe_cmd_icache_fill_s; \ + \ + /* \ + * bp_fe_cmd_itlb_fence_s consists of virtual address, asid, and flags for whether to flush \ + * all addresses and/or all asids. In the case of context switch, the itlb will perform itlb \ + * fence according to the asid. \ + */ \ + typedef struct packed \ + { \ + logic [asid_width_mp-1:0] asid; \ + logic flush_all_addresses; \ + logic flush_all_asid; \ + logic [`bp_fe_cmd_itlb_fence_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)-1:0] \ + padding; \ + } bp_fe_cmd_itlb_fence_s; \ + \ + /* \ + * bp_fe_cmd_s is the information backend provides to the frontend in the case of \ + * misprediction. It contains the branch_metadata_fwd information and \ + * misprediction reason. The BE does not examine the branch metadata, but does \ + * supply the misprediction reason. \ + */ \ + typedef struct packed \ + { \ + logic [vaddr_width_mp-1:0] npc; \ + bp_fe_command_queue_opcodes_e opcode; \ + union packed \ + { \ + bp_fe_cmd_pc_redirect_operands_s pc_redirect_operands; \ + bp_fe_cmd_attaboy_s attaboy; \ + bp_fe_cmd_itlb_fill_s itlb_fill_response; \ + bp_fe_cmd_itlb_fence_s itlb_fence; \ + bp_fe_cmd_icache_fill_s icache_fill_response; \ + } operands; \ + } bp_fe_cmd_s + + /* + * Declare all fe-be widths at once as localparams + */ + `define declare_bp_core_if_widths(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + , localparam fe_queue_width_lp=`bp_fe_queue_width(vaddr_width_mp, branch_metadata_fwd_width_mp) \ + , localparam fe_cmd_width_lp=`bp_fe_cmd_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) + + /* Declare width macros so that clients can use structs in ports before struct declaration */ + `define bp_fe_queue_width(vaddr_width_mp, branch_metadata_fwd_width_mp) \ + ($bits(bp_fe_queue_type_e)+branch_metadata_fwd_width_mp+fetch_width_p+fetch_ptr_p+vaddr_width_mp) + + `define bp_fe_cmd_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (vaddr_width_mp \ + + $bits(bp_fe_command_queue_opcodes_e) \ + + `bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + ) + + `define bp_fe_cmd_pc_redirect_operands_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)) + + `define bp_fe_cmd_attaboy_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)) + + `define bp_fe_cmd_itlb_fill_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)) + + `define bp_fe_cmd_icache_fill_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)) + + `define bp_pte_leaf_width(paddr_width_mp) \ + (paddr_width_mp - page_offset_width_gp + 8) + + `define bp_fe_cmd_itlb_fence_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp)) + + /* Ensure all members of packed unions have the same size. If parameterized unions are desired, + * examine this code carefully. Else, clients should not have to use these macros + */ + `define bp_fe_fetch_width_no_padding(vaddr_width_mp, branch_metadata_fwd_width_mp) \ + (vaddr_width_mp + instr_width_gp + branch_metadata_fwd_width_mp) + + `define bp_fe_exception_width_no_padding(vaddr_width_mp) \ + (vaddr_width_mp + instr_width_gp + $bits(bp_fe_exception_code_e) + 1) + + `define bp_fe_cmd_pc_redirect_operands_width_no_padding(branch_metadata_fwd_width_mp) \ + ($bits(bp_fe_command_queue_subopcodes_e) \ + + branch_metadata_fwd_width_mp + $bits(bp_fe_misprediction_reason_e) + 3) + + `define bp_fe_cmd_attaboy_width_no_padding(branch_metadata_fwd_width_mp) \ + ( 1+branch_metadata_fwd_width_mp) + + `define bp_fe_cmd_itlb_fill_width_no_padding(vaddr_width_mp, paddr_width_mp) \ + (`bp_pte_leaf_width(paddr_width_mp)+instr_width_gp+fetch_ptr_p) + + `define bp_fe_cmd_icache_fill_width_no_padding \ + (instr_width_gp+fetch_ptr_p) + + `define bp_fe_cmd_itlb_fence_width_no_padding(asid_width_mp) \ + (asid_width_mp + 2) + + `define bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (1+`BSG_MAX(`bp_fe_cmd_pc_redirect_operands_width_no_padding(branch_metadata_fwd_width_mp) \ + ,`BSG_MAX(`bp_fe_cmd_attaboy_width_no_padding(branch_metadata_fwd_width_mp) \ + ,`BSG_MAX(`bp_fe_cmd_itlb_fill_width_no_padding(vaddr_width_mp, paddr_width_mp) \ + ,`BSG_MAX(`bp_fe_cmd_itlb_fence_width_no_padding(asid_width_mp)\ + ,`bp_fe_cmd_icache_fill_width_no_padding \ + ) \ + ) \ + ) \ + ) \ + ) + + `define bp_fe_cmd_pc_redirect_operands_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + - `bp_fe_cmd_pc_redirect_operands_width_no_padding(branch_metadata_fwd_width_mp) \ + ) + + `define bp_fe_cmd_attaboy_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + - `bp_fe_cmd_attaboy_width_no_padding(branch_metadata_fwd_width_mp) \ + ) + + `define bp_fe_cmd_itlb_fill_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + - `bp_fe_cmd_itlb_fill_width_no_padding(vaddr_width_mp, paddr_width_mp) \ + ) + + `define bp_fe_cmd_icache_fill_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + - `bp_fe_cmd_icache_fill_width_no_padding \ + ) + + `define bp_fe_cmd_itlb_fence_padding_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + (`bp_fe_cmd_operands_u_width(vaddr_width_mp, paddr_width_mp, asid_width_mp, branch_metadata_fwd_width_mp) \ + - `bp_fe_cmd_itlb_fence_width_no_padding(asid_width_mp) \ + ) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_core_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_core_pkgdef.svh new file mode 100644 index 0000000..c06b77f --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_core_pkgdef.svh @@ -0,0 +1,79 @@ + +`ifndef BP_COMMON_CORE_PKGDEF_SVH +`define BP_COMMON_CORE_PKGDEF_SVH + + /* + * bp_fe_command_queue_opcodes_e defines the opcodes from backend to frontend in + * the cases of an exception. bp_fe_command_queue_opcodes_e explains the reason + * of why pc is redirected. Only e_op_pc_redirection contains possible at-fault + * redirections + * e_op_state_reset is used after the reset, which flushes all the states. + * e_op_pc_redirection defines the changes of PC, which happens during the branches. + * e_op_attaboy informs the frontend that the prediction is correct. + * e_op_icache_fill_response happens when icache non-speculatively misses + * e_op_icache_fence happens when there is flush in the icache. + * e_op_itlb_fill_response happens when itlb populates translation and restarts fetching + * e_op_itlb_fence issues a fence operation to itlb. + */ + typedef enum logic [2:0] + { + e_op_state_reset = 0 + ,e_op_pc_redirection = 1 + ,e_op_attaboy = 2 + ,e_op_icache_fill_response = 3 + ,e_op_icache_fence = 4 + ,e_op_itlb_fill_response = 5 + ,e_op_itlb_fence = 6 + ,e_op_wait = 7 + } bp_fe_command_queue_opcodes_e; + + /* + * bp_fe_misprediction_reason_e is the misprediction reason provided by the backend. + */ + typedef enum logic [1:0] + { + e_not_a_branch = 0 + ,e_incorrect_pred_taken = 1 + ,e_incorrect_pred_ntaken = 2 + } bp_fe_misprediction_reason_e; + + /* + * The exception code types. + * e_itlb_miss is for an ITLB miss + * e_instr_page_fault is for an access page fault + * e_instr_access_fault is when the physical address is not allowed for the access type + * e_icache_miss is for a nonspeculative I$ miss which needs to be confirmed by the backend + */ + typedef enum logic [2:0] + { + e_itlb_miss = 0 + ,e_instr_page_fault = 1 + ,e_instr_access_fault = 2 + ,e_icache_miss = 3 + ,e_instr_fetch = 4 + } bp_fe_queue_type_e; + + /* + * bp_fe_command_queue_subopcodes_e defines the subopcodes in the case of pc_redirection in + * bp_fe_command_queue_opcodes_e. It provides the reasons of why pc are redirected. + * e_subop_uret,sret,mret are the returns from trap and contain the pc where it returns. + * e_subop_interrupt is no-fault pc redirection. + * e_subop_branch_mispredict is at-fault PC redirection. + * e_subop_trap is at-fault PC redirection. It will changes the permission bits. + * e_subop_context_switch is no-fault PC redirection. It redirect pc to a new address space. + * e_subop_translation_switch is no-fault PC redirection resulting from translation mode changes + * e_subop_resume is resuming from a no-fault PC redirect wait state. + */ + typedef enum logic [2:0] + { + e_subop_eret + ,e_subop_interrupt + ,e_subop_branch_mispredict + ,e_subop_trap + ,e_subop_context_switch + ,e_subop_translation_switch + ,e_subop_resume + } bp_fe_command_queue_subopcodes_e; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_defines.svh b/designs/black-parrot/src/bp/bp_common_defines.svh new file mode 100644 index 0000000..093bbd8 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_defines.svh @@ -0,0 +1,18 @@ +`ifndef BP_COMMON_DEFINES_SVH +`define BP_COMMON_DEFINES_SVH + + `include "bsg_defines.sv" + `include "bp_common_addr_defines.svh" + `include "bp_common_aviary_defines.svh" + `include "bp_common_aviary_custom_defines.svh" + `include "bp_common_bedrock_if.svh" + `include "bp_common_bedrock_wormhole_defines.svh" + `include "bp_common_cache_engine_if.svh" + `include "bp_common_core_if.svh" + `include "bp_common_cfg_bus_defines.svh" + `include "bp_common_log_defines.svh" + `include "bp_common_rv64_instr_defines.svh" + `include "bp_common_rv64_csr_defines.svh" + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_host_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_host_pkgdef.svh new file mode 100644 index 0000000..e05e466 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_host_pkgdef.svh @@ -0,0 +1,36 @@ + +`ifndef BP_COMMON_HOST_PKGDEF_SVH +`define BP_COMMON_HOST_PKGDEF_SVH + + localparam host_base_addr_gp = (dev_id_width_gp+dev_addr_width_gp)'('h0010_0000); + localparam host_match_addr_gp = (dev_id_width_gp+dev_addr_width_gp)'('h001?_????); + + localparam getchar_base_addr_gp = (dev_addr_width_gp)'('h0_0000); + localparam getchar_match_addr_gp = (dev_addr_width_gp)'('h0_0???); + + localparam putchar_base_addr_gp = (dev_addr_width_gp)'('h0_1000); + localparam putchar_match_addr_gp = (dev_addr_width_gp)'('h0_1???); + + localparam finish_base_addr_gp = (dev_addr_width_gp)'('h0_2000); + localparam finish_match_addr_gp = (dev_addr_width_gp)'('h0_2???); + + localparam putch_core_base_addr_gp = (dev_addr_width_gp)'('h0_3000); + localparam putch_core_match_addr_gp = (dev_addr_width_gp)'('h0_3???); + + localparam signature_base_addr_gp = (dev_addr_width_gp)'('h0_4000); + localparam signature_match_addr_gp = (dev_addr_width_gp)'('h0_4???); + + localparam putint_base_addr_gp = (dev_addr_width_gp)'('h0_5000); + localparam putint_match_addr_gp = (dev_addr_width_gp)'('h0_5???); + + localparam bootrom_base_addr_gp = (dev_addr_width_gp)'('h1_0000); + localparam bootrom_match_addr_gp = (dev_addr_width_gp)'('h1_????); + + localparam paramrom_base_addr_gp = (dev_addr_width_gp)'('h2_0000); + localparam paramrom_match_addr_gp = (dev_addr_width_gp)'('h2_????); + + localparam debugrom_base_addr_gp = (dev_addr_width_gp)'('h3_0800); + localparam debugrom_match_addr_gp = (dev_addr_width_gp)'('h3_????); + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_log_defines.svh b/designs/black-parrot/src/bp/bp_common_log_defines.svh new file mode 100644 index 0000000..6f15d71 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_log_defines.svh @@ -0,0 +1,42 @@ +`ifndef BP_COMMON_LOG_DEFINES_SVH +`define BP_COMMON_LOG_DEFINES_SVH + + /* + * This macro allows users to log to different mediums depending on a parameter + * print_type_mp - The different outputs as a bitmask + * 0 - stdout ($display without newline) + * 1 - file + * file_mp - The name of the log file, optional if using stdout + * str_mp - This is the format string for the print statement. Must be enclosed in parentheses + * + * Example usage - + * `BP_LOG(0, `BP_LOG_STDOUT, ("I'm a display log %d", 2)); + * `BP_LOG(file, `BP_LOG_FILE, ("I'm a file log %d %d", 1, 2)); + * `BP_LOG(file, `BP_LOG_STDOUT | `BP_LOG_FILE, ("I'm both! %d", 3)); + * `BP_LOG(0, `BP_LOG_NONE, ("I'm neither %d", 4)); + * + * In practice, we expect users will set the log level as a module parameter rather than in the + * macro. + * An obvious enhancement is to add log levels to control verbosity. A less obvious enhancement is + * to support ordering of logs through a parameter. Perhaps #``delay_mp`` + */ + localparam bp_log_none_gp = 0; + localparam bp_log_stdout_gp = 1; + localparam bp_log_file_gp = 2; + + `define BP_LOG(print_type_mp=0, file_mp=0, str_mp) \ + do begin \ + if (print_type_mp[0]) $write("%s", $sformatf str_mp); \ + if (print_type_mp[1]) $fwrite(file_mp, "%s", $sformatf str_mp); \ + end while (0) + + `define bp_cast_i(struct_name_mp, port_mp) \ + struct_name_mp ``port_mp``_cast_i; \ + assign ``port_mp``_cast_i = ``port_mp``_i + + `define bp_cast_o(struct_name_mp, port_mp) \ + struct_name_mp ``port_mp``_cast_o; \ + assign ``port_mp``_o = ``port_mp``_cast_o + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_pkg.sv b/designs/black-parrot/src/bp/bp_common_pkg.sv new file mode 100644 index 0000000..40a5c4c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_pkg.sv @@ -0,0 +1,29 @@ +/* + * bp_common_pkg.sv + * + * Contains the interface structures used for communicating between FE, BE, ME in BlackParrot. + * Additionally contains global parameters used to configure the system. In the future, when + * multiple configurations are supported, these global parameters will belong to groups + * e.g. SV39, VM-disabled, ... + * + */ + + `include "bp_common_defines.svh" + +package bp_common_pkg; + + `include "bp_common_accelerator_pkgdef.svh" + `include "bp_common_addr_pkgdef.svh" + `include "bp_common_aviary_pkgdef.svh" + `include "bp_common_aviary_cfg_pkgdef.svh" + `include "bp_common_bedrock_pkgdef.svh" + `include "bp_common_cache_pkgdef.svh" + `include "bp_common_cache_engine_pkgdef.svh" + `include "bp_common_cfg_bus_pkgdef.svh" + `include "bp_common_clint_pkgdef.svh" + `include "bp_common_core_pkgdef.svh" + `include "bp_common_host_pkgdef.svh" + `include "bp_common_rv64_pkgdef.svh" + +endpackage + diff --git a/designs/black-parrot/src/bp/bp_common_rv64_csr_defines.svh b/designs/black-parrot/src/bp/bp_common_rv64_csr_defines.svh new file mode 100644 index 0000000..c7ed593 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_rv64_csr_defines.svh @@ -0,0 +1,1073 @@ +`ifndef BP_COMMON_RV64_CSR_DEFINES_SVH +`define BP_COMMON_RV64_CSR_DEFINES_SVH + + `define PRIV_MODE_M 2'b11 + `define PRIV_MODE_S 2'b01 + `define PRIV_MODE_U 1'b0 + + `define CSR_ADDR_USTATUS 12'h000 + `define CSR_ADDR_UIE 12'h004 + `define CSR_ADDR_UTVEC 12'h005 + + `define CSR_ADDR_USCRATCH 12'h040 + `define CSR_ADDR_UEPC 12'h041 + `define CSR_ADDR_UCAUSE 12'h042 + `define CSR_ADDR_UTVAL 12'h043 + `define CSR_ADDR_UIP 12'h044 + + `define CSR_ADDR_FFLAGS 12'h001 + `define CSR_ADDR_FRM 12'h002 + `define CSR_ADDR_FCSR 12'h003 + + `define CSR_ADDR_CYCLE 12'hc00 + `define CSR_ADDR_TIME 12'hc01 + `define CSR_ADDR_INSTRET 12'hc02 + `define CSR_ADDR_HPMCOUNTER3 12'hc03 + `define CSR_ADDR_HPMCOUNTER4 12'hc04 + `define CSR_ADDR_HPMCOUNTER5 12'hc05 + `define CSR_ADDR_HPMCOUNTER6 12'hc06 + `define CSR_ADDR_HPMCOUNTER7 12'hc07 + `define CSR_ADDR_HPMCOUNTER8 12'hc08 + `define CSR_ADDR_HPMCOUNTER9 12'hc09 + `define CSR_ADDR_HPMCOUNTER10 12'hc0a + `define CSR_ADDR_HPMCOUNTER11 12'hc0b + `define CSR_ADDR_HPMCOUNTER12 12'hc0c + `define CSR_ADDR_HPMCOUNTER13 12'hc0d + `define CSR_ADDR_HPMCOUNTER14 12'hc0e + `define CSR_ADDR_HPMCOUNTER15 12'hc0f + `define CSR_ADDR_HPMCOUNTER16 12'hc10 + `define CSR_ADDR_HPMCOUNTER17 12'hc11 + `define CSR_ADDR_HPMCOUNTER18 12'hc12 + `define CSR_ADDR_HPMCOUNTER19 12'hc13 + `define CSR_ADDR_HPMCOUNTER20 12'hc14 + `define CSR_ADDR_HPMCOUNTER21 12'hc15 + `define CSR_ADDR_HPMCOUNTER22 12'hc16 + `define CSR_ADDR_HPMCOUNTER23 12'hc17 + `define CSR_ADDR_HPMCOUNTER24 12'hc18 + `define CSR_ADDR_HPMCOUNTER25 12'hc19 + `define CSR_ADDR_HPMCOUNTER26 12'hc1a + `define CSR_ADDR_HPMCOUNTER27 12'hc1b + `define CSR_ADDR_HPMCOUNTER28 12'hc1c + `define CSR_ADDR_HPMCOUNTER29 12'hc1d + `define CSR_ADDR_HPMCOUNTER30 12'hc1e + `define CSR_ADDR_HPMCOUNTER31 12'hc1f + + `define CSR_ADDR_SSTATUS 12'h100 + `define CSR_ADDR_SEDELEG 12'h102 + `define CSR_ADDR_SIDELEG 12'h103 + `define CSR_ADDR_SIE 12'h104 + `define CSR_ADDR_STVEC 12'h105 + `define CSR_ADDR_SCOUNTEREN 12'h106 + + `define CSR_ADDR_SSCRATCH 12'h140 + `define CSR_ADDR_SEPC 12'h141 + `define CSR_ADDR_SCAUSE 12'h142 + `define CSR_ADDR_STVAL 12'h143 + `define CSR_ADDR_SIP 12'h144 + + `define CSR_ADDR_SATP 12'h180 + + `define CSR_ADDR_MVENDORID 12'hf11 + `define CSR_ADDR_MARCHID 12'hf12 + `define CSR_ADDR_MIMPID 12'hf13 + `define CSR_ADDR_MHARTID 12'hf14 + + `define CSR_ADDR_MSTATUS 12'h300 + `define CSR_ADDR_MISA 12'h301 + `define CSR_ADDR_MEDELEG 12'h302 + `define CSR_ADDR_MIDELEG 12'h303 + `define CSR_ADDR_MIE 12'h304 + `define CSR_ADDR_MTVEC 12'h305 + `define CSR_ADDR_MCOUNTEREN 12'h306 + + `define CSR_ADDR_MSCRATCH 12'h340 + `define CSR_ADDR_MEPC 12'h341 + `define CSR_ADDR_MCAUSE 12'h342 + `define CSR_ADDR_MTVAL 12'h343 + `define CSR_ADDR_MIP 12'h344 + + `define CSR_ADDR_PMPCFG0 12'h3a0 + `define CSR_ADDR_PMPCFG2 12'h3a2 + `define CSR_ADDR_PMPADDR0 12'h3b0 + `define CSR_ADDR_PMPADDR1 12'h3b1 + `define CSR_ADDR_PMPADDR2 12'h3b2 + `define CSR_ADDR_PMPADDR3 12'h3b3 + `define CSR_ADDR_PMPADDR4 12'h3b4 + `define CSR_ADDR_PMPADDR5 12'h3b5 + `define CSR_ADDR_PMPADDR6 12'h3b6 + `define CSR_ADDR_PMPADDR7 12'h3b7 + `define CSR_ADDR_PMPADDR8 12'h3b8 + `define CSR_ADDR_PMPADDR9 12'h3b9 + `define CSR_ADDR_PMPADDR10 12'h3ba + `define CSR_ADDR_PMPADDR11 12'h3bb + `define CSR_ADDR_PMPADDR12 12'h3bc + `define CSR_ADDR_PMPADDR13 12'h3bd + `define CSR_ADDR_PMPADDR14 12'h3be + `define CSR_ADDR_PMPADDR15 12'h3bf + + `define CSR_ADDR_MCYCLE 12'hb00 + `define CSR_ADDR_MINSTRET 12'hb02 + `define CSR_ADDR_MHPMCOUNTER3 12'hb03 + `define CSR_ADDR_MHPMCOUNTER4 12'hb04 + `define CSR_ADDR_MHPMCOUNTER5 12'hb05 + `define CSR_ADDR_MHPMCOUNTER6 12'hb06 + `define CSR_ADDR_MHPMCOUNTER7 12'hb07 + `define CSR_ADDR_MHPMCOUNTER8 12'hb08 + `define CSR_ADDR_MHPMCOUNTER9 12'hb09 + `define CSR_ADDR_MHPMCOUNTER10 12'hb0a + `define CSR_ADDR_MHPMCOUNTER11 12'hb0b + `define CSR_ADDR_MHPMCOUNTER12 12'hb0c + `define CSR_ADDR_MHPMCOUNTER13 12'hb0d + `define CSR_ADDR_MHPMCOUNTER14 12'hb0e + `define CSR_ADDR_MHPMCOUNTER15 12'hb0f + `define CSR_ADDR_MHPMCOUNTER16 12'hb10 + `define CSR_ADDR_MHPMCOUNTER17 12'hb11 + `define CSR_ADDR_MHPMCOUNTER18 12'hb12 + `define CSR_ADDR_MHPMCOUNTER19 12'hb13 + `define CSR_ADDR_MHPMCOUNTER20 12'hb14 + `define CSR_ADDR_MHPMCOUNTER21 12'hb15 + `define CSR_ADDR_MHPMCOUNTER22 12'hb16 + `define CSR_ADDR_MHPMCOUNTER23 12'hb17 + `define CSR_ADDR_MHPMCOUNTER24 12'hb18 + `define CSR_ADDR_MHPMCOUNTER25 12'hb19 + `define CSR_ADDR_MHPMCOUNTER26 12'hb1a + `define CSR_ADDR_MHPMCOUNTER27 12'hb1b + `define CSR_ADDR_MHPMCOUNTER28 12'hb1c + `define CSR_ADDR_MHPMCOUNTER29 12'hb1d + `define CSR_ADDR_MHPMCOUNTER30 12'hb1e + `define CSR_ADDR_MHPMCOUNTER31 12'hb1f + + `define CSR_ADDR_MCOUNTINHIBIT 12'h320 + `define CSR_ADDR_MHPMEVENT3 12'h323 + `define CSR_ADDR_MHPMEVENT4 12'h324 + `define CSR_ADDR_MHPMEVENT5 12'h325 + `define CSR_ADDR_MHPMEVENT6 12'h326 + `define CSR_ADDR_MHPMEVENT7 12'h327 + `define CSR_ADDR_MHPMEVENT8 12'h328 + `define CSR_ADDR_MHPMEVENT9 12'h329 + `define CSR_ADDR_MHPMEVENT10 12'h32a + `define CSR_ADDR_MHPMEVENT11 12'h32b + `define CSR_ADDR_MHPMEVENT12 12'h32c + `define CSR_ADDR_MHPMEVENT13 12'h32d + `define CSR_ADDR_MHPMEVENT14 12'h32e + `define CSR_ADDR_MHPMEVENT15 12'h32f + `define CSR_ADDR_MHPMEVENT16 12'h330 + `define CSR_ADDR_MHPMEVENT17 12'h331 + `define CSR_ADDR_MHPMEVENT18 12'h332 + `define CSR_ADDR_MHPMEVENT19 12'h333 + `define CSR_ADDR_MHPMEVENT20 12'h334 + `define CSR_ADDR_MHPMEVENT21 12'h335 + `define CSR_ADDR_MHPMEVENT22 12'h336 + `define CSR_ADDR_MHPMEVENT23 12'h337 + `define CSR_ADDR_MHPMEVENT24 12'h338 + `define CSR_ADDR_MHPMEVENT25 12'h339 + `define CSR_ADDR_MHPMEVENT26 12'h33a + `define CSR_ADDR_MHPMEVENT27 12'h33b + `define CSR_ADDR_MHPMEVENT28 12'h33c + `define CSR_ADDR_MHPMEVENT29 12'h33d + `define CSR_ADDR_MHPMEVENT30 12'h33e + `define CSR_ADDR_MHPMEVENT31 12'h33f + + `define CSR_ADDR_TSELECT 12'h7a0 + `define CSR_ADDR_TDATA1 12'h7a1 + `define CSR_ADDR_TDATA2 12'h7a2 + `define CSR_ADDR_TDATA3 12'h7a3 + + `define CSR_ADDR_DCSR 12'h7b0 + `define CSR_ADDR_DPC 12'h7b1 + `define CSR_ADDR_DSCRATCH0 12'h7b2 + `define CSR_ADDR_DSCRATCH1 12'h7b3 + +`define declare_csr_structs(vaddr_width_mp, paddr_width_mp) \ + typedef struct packed \ + { \ + /* Base address for traps */ \ + logic [61:0] base; \ + /* Trap Mode */ \ + /* 00 - Direct, all exceptions set pc to BASE */ \ + /* 01 - Vectored, interrupts set pc to BASE+4xcause */ \ + logic [1:0] mode; \ + } rv64_stvec_s; \ + \ + typedef struct packed \ + { \ + logic [(`BSG_MAX(vaddr_width_mp, paddr_width_mp)-2)-1:0] word_addr; \ + } bp_stvec_s; \ + \ + typedef struct packed \ + { \ + logic [31:3] hpm; \ + logic ir; \ + logic tm; \ + logic cy; \ + } rv64_scounteren_s; \ + \ + typedef struct packed \ + { \ + logic ir; \ + logic cy; \ + } bp_scounteren_s; \ + \ + typedef logic [63:0] rv64_sscratch_s; \ + typedef logic [63:0] bp_sscratch_s; \ + \ + typedef struct packed \ + { \ + logic [61:0] word_addr; \ + logic [0:0] align; \ + logic [0:0] zero; \ + } rv64_sepc_s; \ + typedef struct packed \ + { \ + logic [(`BSG_MAX(vaddr_width_mp, paddr_width_mp))-2:0] word_addr; \ + logic [0:0] align; \ + } bp_sepc_s; \ + \ + typedef struct packed \ + { \ + logic _interrupt; \ + logic [62:0] ecode; \ + } rv64_scause_s; \ + \ + typedef struct packed \ + { \ + logic _interrupt; \ + logic [3:0] ecode; \ + } bp_scause_s; \ + \ + typedef logic [63:0] rv64_stval_s; \ + typedef logic [`BSG_MAX(vaddr_width_mp, paddr_width_mp)-1:0] bp_stval_s; \ + \ + typedef struct packed \ + { \ + /* Translation Mode */ \ + /* 0000 - No Translation */ \ + /* 1000 - SV39 */ \ + /* 1001 - SV48 */ \ + /* Others reserved */ \ + logic [3:0] mode; \ + logic [15:0] asid; \ + logic [43:0] ppn; \ + } rv64_satp_s; \ + \ + typedef struct packed \ + { \ + /* We only support No Translation and SV39 */ \ + logic mode; \ + /* We don't currently have ASID support */ \ + /* We only support 39 bit physical address. */ \ + /* TODO: Generate this based on vaddr */ \ + logic [(paddr_width_mp-page_offset_width_gp)-1:0] ppn; \ + } bp_satp_s; \ + \ + typedef struct packed \ + { \ + /* State Dirty */ \ + /* 0 - FS and XS are both != 11 */ \ + /* 1 - set if FS or SX == 11 */ \ + /* Note: readonly */ \ + logic sd; \ + logic [26:0] wpri1; \ + /* XLEN */ \ + /* 01 - 32 bit data */ \ + /* 10 - 64 bit data */ \ + /* 11 - 128 bit data */ \ + /* MXL is in misa instead. */ \ + logic [1:0] sxl; \ + logic [1:0] uxl; \ + logic [8:0] wpri2; \ + /* Trap SRET */ \ + /* 0 - SRET permitted in S-mode */ \ + /* 1 - SRET in S-mode is illegal */ \ + logic tsr; \ + /* Trap WFI */ \ + /* 0 - WFI is permitted in S-mode */ \ + /* 1 - WFI is executed and not complete within implementation-defined time, is illegal */ \ + logic tw; \ + /* Trap VM */ \ + /* 0 - The following operations are legal */ \ + /* 1 - attempts to read or write satp or execute SFENCE.VMA in S-mode are illegal */ \ + logic tvm; \ + /* Make Executable Readable */ \ + /* 0 - only loads from pages marked readable succeed */ \ + /* 1 - loads from pages marked either readable or executable succeed */ \ + /* No effect when translation is disabled */ \ + logic mxr; \ + /* Supervisor User Memory */ \ + /* 0 - S-mode memory accesses to U-mode pages will fault */ \ + /* 1 - S-mode memory accesses to U-mode pages will succeed */ \ + logic sum; \ + /* Modify Privilege */ \ + /* 0 - translation and protection behave normally */ \ + /* 1 - load and stores are translated as though privilege mode is MPP */ \ + logic mprv; \ + /* Extension Status */ \ + /* 0 - off */ \ + /* 1 - initial (none dirty or clean) */ \ + /* 2 - clean (none dirty) */ \ + /* 3 - dirty */ \ + /* Hardwired to 0 in systems without extensions requiring context (vector) */ \ + logic [1:0] xs; \ + /* Floating-point Status */ \ + /* 0 - off */ \ + /* 1 - initial (none dirty or clean) */ \ + /* 2 - clean (none dirty) */ \ + /* 3 - dirty */ \ + /* Hardwired to 0 in systems without extensions requiring context (floating point) */ \ + logic [1:0] fs; \ + /* Previous Privilege */ \ + /* 11 - M */ \ + /* 01 - S */ \ + /* 00 - U */ \ + logic [1:0] mpp; \ + logic [1:0] wpri3; \ + logic spp; \ + /* Previous Interrupt Enable */ \ + /* 0 - Interrupt Previously Disabled for Privilege Mode */ \ + /* 1 - Interrupt Previously Enabled for Privilege Mode */ \ + logic mpie; \ + logic wpri4; \ + logic spie; \ + logic upie; \ + /* Global Interrupt Enable */ \ + /* 0 - Interrupt Disabled for Privilege Mode */ \ + /* 1 - Interrupt Enabled for Privilege Mode */ \ + logic mie; \ + logic wpri5; \ + logic sie; \ + logic uie; \ + } rv64_mstatus_s; \ + \ + typedef struct packed \ + { \ + logic tsr; \ + logic tw; \ + logic tvm; \ + \ + logic mxr; \ + logic sum; \ + logic mprv; \ + \ + logic [1:0] fs; \ + \ + logic [1:0] mpp; \ + logic spp; \ + \ + logic mpie; \ + logic spie; \ + \ + logic mie; \ + logic sie; \ + } bp_mstatus_s; \ + \ + typedef logic [63:0] rv64_medeleg_s; \ + /* Hardcode exception 10, 11, 14, 16+ to zero */ \ + typedef struct packed \ + { \ + logic [15:15] deleg_15; \ + logic [13:12] deleg_13to12; \ + logic [ 9: 0] deleg_9to0; \ + } bp_medeleg_s; \ + \ + typedef struct packed \ + { \ + logic [51:0] wpri1; \ + /* M-mode External Interrupt Delegation */ \ + logic mei; \ + logic wpri2; \ + /* S-mode External Interrupt Delegation */ \ + logic sei; \ + /* U-mode External Interrupt Delegation */ \ + logic uei; \ + /* M-mode Timer Interrupt Delegation */ \ + logic mti; \ + logic wpri3; \ + /* S-mode Timer Interrupt Delegation */ \ + logic sti; \ + /* U-mode Timer Interrupt Delegation */ \ + logic uti; \ + /* M-mode Software Interrupt Delegation */ \ + logic msi; \ + logic wpri4; \ + /* S-mode Software Interrupt Delegation */ \ + logic ssi; \ + /* U-mode Software Interrupt Delegation */ \ + logic usi; \ + } rv64_mideleg_s; \ + \ + typedef struct packed \ + { \ + logic sei; \ + logic sti; \ + logic ssi; \ + } bp_mideleg_s; \ + \ + typedef struct packed \ + { \ + logic [51:0] wpri1; \ + /* M-mode External Interrupt Enable */ \ + logic meie; \ + logic wpri2; \ + /* S-mode External Interrupt Enable */ \ + logic seie; \ + /* U-mode External Interrupt Enable */ \ + logic ueie; \ + /* M-mode Timer Interrupt Enable */ \ + logic mtie; \ + logic wpri3; \ + /* S-mode Timer Interrupt Enable */ \ + logic stie; \ + /* U-mode Timer Interrupt Enable */ \ + logic utie; \ + /* M-mode Software Interrupt Enable */ \ + logic msie; \ + logic wpri4; \ + /* S-mode Software Interrupt Enable */ \ + logic ssie; \ + /* U-mode Software Interrupt Enable */ \ + logic usie; \ + } rv64_mie_s; \ + \ + typedef struct packed \ + { \ + logic meie; \ + logic seie; \ + \ + logic mtie; \ + logic stie; \ + \ + logic msie; \ + logic ssie; \ + } bp_mie_s; \ + \ + typedef struct packed \ + { \ + /* Base address for traps */ \ + logic [61:0] base; \ + /* Trap Mode */ \ + /* 00 - Direct, all exceptions set pc to BASE */ \ + /* 01 - Vectored, interrupts set pc to BASE+4xcause */ \ + logic [1:0] mode; \ + } rv64_mtvec_s; \ + \ + typedef struct packed \ + { \ + logic [(`BSG_MAX(vaddr_width_mp, paddr_width_mp)-2)-1:0] word_addr; \ + } bp_mtvec_s; \ + \ + typedef struct packed \ + { \ + logic [31:3] hpm; \ + logic ir; \ + logic tm; \ + logic cy; \ + } rv64_mcounteren_s; \ + \ + typedef struct packed \ + { \ + logic ir; \ + logic cy; \ + } bp_mcounteren_s; \ + \ + typedef logic [63:0] rv64_mscratch_s; \ + typedef logic [63:0] bp_mscratch_s; \ + \ + typedef struct packed \ + { \ + logic [51:0] wpri1; \ + /* M-mode External Interrupt Pending */ \ + logic meip; \ + logic wpri2; \ + /* S-mode External Interrupt Pending */ \ + logic seip; \ + /* U-mode External Interrupt Pending */ \ + logic ueip; \ + /* M-mode Timer Interrupt Pending */ \ + logic mtip; \ + logic wpri3; \ + /* S-mode Timer Interrupt Pending */ \ + logic stip; \ + /* U-mode Timer Interrupt Pending */ \ + logic utip; \ + /* M-mode Software Interrupt Pending */ \ + logic msip; \ + logic wpri4; \ + /* S-mode Software Interrupt Pending */ \ + logic ssip; \ + /* U-mode Software Interrupt Pending */ \ + logic usip; \ + } rv64_mip_s; \ + \ + typedef struct packed \ + { \ + logic meip; \ + logic seip; \ + \ + logic mtip; \ + logic stip; \ + \ + logic msip; \ + logic ssip; \ + } bp_mip_s; \ + \ + typedef logic [63:0] rv64_mtval_s; \ + typedef logic [`BSG_MAX(vaddr_width_mp, paddr_width_mp)-1:0] bp_mtval_s; \ + \ + typedef struct packed \ + { \ + logic [61:0] word_addr; \ + logic [0:0] align; \ + logic [0:0] zero; \ + } rv64_mepc_s; \ + typedef struct packed \ + { \ + logic [`BSG_MAX(vaddr_width_mp, paddr_width_mp)-2:0] word_addr; \ + logic [0:0] align; \ + } bp_mepc_s; \ + \ + typedef struct packed \ + { \ + /* Locked - writes to this pmpcfg and corresponding pmpaddr are ignored */ \ + logic l; \ + logic [1:0] wpri; \ + /* Address Matching Mode */ \ + /* 00 - Off , Null region (disabled) */ \ + /* 01 - TOR , Top of range (pmpaddr[i-1] <=a< pmpaddr[i], or 0 <=a< pmpaddr[0]) */ \ + /* 10 - NA4 , Naturally aligned four-byte region */ \ + /* 11 - NAPOT, Naturally aligned power-of-two region */ \ + logic [1:0] a; \ + /* Execute permissions */ \ + logic x; \ + /* Write permissions */ \ + logic w; \ + /* Read permissions */ \ + logic r; \ + } rv64_pmpcfg_entry_s; \ + \ + typedef struct packed \ + { \ + rv64_pmpcfg_entry_s [7:0] pmpcfg; \ + } rv64_pmpcfg_s; \ + typedef rv64_pmpcfg_s rv64_pmpcfg0_s; \ + typedef rv64_pmpcfg_s rv64_pmpcfg1_s; \ + \ + typedef struct packed \ + { \ + rv64_pmpcfg_entry_s [3:0] pmpcfg; \ + } bp_pmpcfg_s; \ + \ + typedef bp_pmpcfg_s bp_pmpcfg0_s; \ + \ + typedef struct packed \ + { \ + logic [9:0] warl; \ + logic [53:0] addr_55_2; \ + } rv64_pmpaddr_s; \ + \ + typedef rv64_pmpaddr_s rv64_pmpaddr0_s; \ + typedef rv64_pmpaddr_s rv64_pmpaddr1_s; \ + typedef rv64_pmpaddr_s rv64_pmpaddr2_s; \ + typedef rv64_pmpaddr_s rv64_pmpaddr3_s; \ + \ + typedef struct packed \ + { \ + logic _interrupt; \ + logic [62:0] ecode; \ + } rv64_mcause_s; \ + \ + typedef struct packed \ + { \ + logic _interrupt; \ + logic [3:0] ecode; \ + } bp_mcause_s; \ + \ + typedef struct packed \ + { \ + logic [(`BSG_MAX(vaddr_width_mp, paddr_width_mp)-2)-1:0] word_addr; \ + } bp_pmpaddr_s; \ + \ + typedef bp_pmpaddr_s bp_pmpaddr0_s; \ + typedef bp_pmpaddr_s bp_pmpaddr1_s; \ + typedef bp_pmpaddr_s bp_pmpaddr2_s; \ + typedef bp_pmpaddr_s bp_pmpaddr3_s; \ + \ + typedef logic [63:0] rv64_mcounter_s; \ + typedef logic [47:0] bp_mcounter_s; \ + \ + typedef rv64_mcounter_s rv64_mcycle_s; \ + typedef rv64_mcounter_s rv64_minstret_s; \ + \ + typedef bp_mcounter_s bp_mcycle_s; \ + typedef bp_mcounter_s bp_minstret_s; \ + \ + typedef struct packed \ + { \ + logic [31:3] hpm; \ + logic ir; \ + logic warl; \ + logic cy; \ + } rv64_mcountinhibit_s; \ + \ + typedef struct packed \ + { \ + logic ir; \ + logic cy; \ + } bp_mcountinhibit_s; \ + \ + typedef struct packed \ + { \ + logic [23:0] warl; \ + logic [2:0] frm; \ + logic [4:0] fflags; \ + } rv64_fcsr_s; \ + \ + typedef struct packed \ + { \ + logic [2:0] frm; \ + logic [4:0] fflags; \ + } bp_fcsr_s; \ + \ + typedef struct packed \ + { \ + /* Debugger version */ \ + /* 0 : No external debug support */ \ + /* 4 : External debug support ala RISC-V Debug Spec */ \ + /* 15: Non-conformant RISC-V debug spec */ \ + logic [3:0] xdebugver; \ + logic [11:0] reserved1; \ + /* Ebreak M-mode behavior */ \ + /* 0 : behave normally */ \ + /* 1 : ebreak in M enters Debug Mode */ \ + logic ebreakm; \ + logic reserved2; \ + /* Ebreak S-mode behavior */ \ + /* 0 : behave normally */ \ + /* 1 : ebreak in S enters Debug Mode */ \ + logic ebreaks; \ + /* Ebreak U-mode behavior */ \ + /* 0 : behave normally */ \ + /* 1 : ebreak in U enters Debug Mode */ \ + logic ebreaku; \ + /* Stepping Interrupt Enable */ \ + /* 0 : Interrupts are disabled during single stepping */ \ + /* 1 : Interrupts are enabled during single stepping */ \ + logic stepie; \ + /* Stop Counters */ \ + /* 0 : Increment counters while in Debug Mode */ \ + /* 1 : Don't increment counters while in Debug Mode or ebreak->Debug Mode */ \ + logic stopcount; \ + /* Stop Timers */ \ + /* 0 : Increment timers as usual */ \ + /* 1 : Don't increment timers in Debug Mode */ \ + logic stoptime; \ + /* Cause of Debug Mode entry */ \ + /* 1 : Ebreak was executed (priority 3) */ \ + /* 2 : Trigger Module caused a breakpoint exception (priority 4) */ \ + /* 3 : Debugger requested entry using haltreq (priority 1) */ \ + /* 4 : Hart single stepped (priority 0) */ \ + /* 5*: Hart halted out of reset due to resethaltreq (priority 2) */ \ + /* *Also legal to report 3 */ \ + logic [3:0] cause; \ + logic reserved3; \ + /* MPRV Enable */ \ + /* 0 : MPRV is ignored in Debug Mode */ \ + /* 1 : MPRV is enabled in Debug Mode */ \ + logic mprven; \ + /* Non-Maskable-Interrupt Pending */ \ + /* 0 : No NMI pending */ \ + /* 1 : NMI pending */ \ + logic nmip; \ + /* Single Step Mode */ \ + /* 0 : Normal behavior during non-Debug Mode */ \ + /* 1 : Hart will only execute a single instruction and then enter Debug Mode. */ \ + /* If the instruction does not complete due to execption, hart enters */ \ + /* Debug Mode after setting exception registers. */ \ + logic step; \ + /* Privilege mode */ \ + /* The privilege level the hart was operating in prior to Debug Mode entry */ \ + /* 0 : U-mode */ \ + /* 1 : S-mode */ \ + /* 3 : M-mode */ \ + logic [1:0] prv; \ + } rv64_dcsr_s; \ + \ + typedef struct packed \ + { \ + logic ebreakm; \ + logic ebreaks; \ + logic ebreaku; \ + logic stepie; \ + logic [3:0] cause; \ + logic [1:0] prv; \ + logic mprven; \ + logic step; \ + } bp_dcsr_s; \ + \ + typedef logic [63:0] rv64_dpc_s; \ + typedef logic [`BSG_MAX(vaddr_width_mp, paddr_width_mp)-1:0] bp_dpc_s; \ + \ + typedef logic [63:0] rv64_dscratch0_s; \ + typedef logic [63:0] bp_dscratch0_s; \ + \ + typedef logic [63:0] rv64_dscratch1_s; \ + typedef logic [63:0] bp_dscratch1_s + + `define bp_stvec_width ($bits(bp_stvec_s)) + + `define compress_stvec_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{word_addr: data_cast_mp.base[0+:`BSG_MAX(vaddr_width_mp, paddr_width_mp)-2]} + + `define decompress_stvec_s(data_comp_mp) \ + '{base : `BSG_SIGN_EXTEND(data_comp_mp.word_addr, 62) \ + ,mode: 2'b00 \ + } + + `define bp_scounteren_width ($bits(bp_scounteren_s)) + + `define compress_scounteren_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{ir : data_cast_mp.ir \ + ,cy: data_cast_mp.cy \ + } + + `define decompress_scounteren_s(data_comp_mp) \ + '{ir : data_comp_mp.ir \ + ,cy: data_comp_mp.cy \ + ,default: '0 \ + } + + `define compress_sscratch_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + data_cast_mp[0+:64] + + `define decompress_sscratch_s(data_comp_mp) \ + 64'(data_comp_mp) + + `define compress_sepc_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{word_addr: `BSG_SIGN_EXTEND(data_cast_mp.word_addr, 62) \ + ,align : data_cast_mp.align \ + } + + `define decompress_sepc_s(data_comp_mp) \ + '{word_addr: `BSG_SIGN_EXTEND(data_comp_mp.word_addr, 62) \ + ,align : compressed_support_p && data_comp_mp.align \ + ,zero : 1'b0 \ + } + + `define compress_scause_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{_interrupt: data_cast_mp._interrupt \ + ,ecode: data_cast_mp.ecode[0+:4] \ + } + + `define decompress_scause_s(data_comp_mp) \ + '{_interrupt: data_comp_mp._interrupt \ + ,ecode: 63'(data_comp_mp.ecode) \ + } + + `define compress_stval_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + bp_stval_s'(data_cast_mp[0+:`BSG_MAX(vaddr_width_mp, paddr_width_mp)]) + + `define decompress_stval_s(data_comp_mp) \ + `BSG_SIGN_EXTEND(data_comp_mp, 64) + + `define bp_satp_width ($bits(bp_satp_s)) + + `define compress_satp_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{mode: data_cast_mp.mode[3] \ + ,ppn: data_cast_mp.ppn[(paddr_width_mp-page_offset_width_gp)-1:0] \ + } + + `define decompress_satp_s(data_comp_mp) \ + '{mode: {data_comp_mp.mode, 3'b000} \ + ,ppn: {16'h0, data_comp_mp.ppn} \ + ,default: '0 \ + } + + `define compress_mstatus_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{tsr : data_cast_mp.tsr \ + ,tw : data_cast_mp.tw \ + ,tvm : data_cast_mp.tvm \ + ,mxr : data_cast_mp.mxr \ + ,sum : data_cast_mp.sum \ + ,mprv: data_cast_mp.mprv \ + ,fs : data_cast_mp.fs \ + ,mpp : data_cast_mp.mpp \ + ,spp : data_cast_mp.spp \ + ,mpie: data_cast_mp.mpie \ + ,spie: data_cast_mp.spie \ + ,mie : data_cast_mp.mie \ + ,sie : data_cast_mp.sie \ + } + + `define decompress_mstatus_s(data_comp_mp) \ + '{sd : (data_comp_mp.fs == 2'b11) \ + ,sxl : 2'b10 \ + ,uxl : 2'b10 \ + ,tsr : data_comp_mp.tsr \ + ,tvm : data_comp_mp.tvm \ + ,tw : data_comp_mp.tw \ + ,mxr : data_comp_mp.mxr \ + ,sum : data_comp_mp.sum \ + ,mprv: data_comp_mp.mprv \ + ,fs : data_comp_mp.fs \ + ,mpp : data_comp_mp.mpp \ + ,spp : data_comp_mp.spp \ + ,mpie: data_comp_mp.mpie \ + ,spie: data_comp_mp.spie \ + ,mie : data_comp_mp.mie \ + ,sie : data_comp_mp.sie \ + ,default: '0 \ + } + + `define compress_medeleg_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{deleg_15 : data_cast_mp[15] \ + ,deleg_13to12: data_cast_mp[13:12] \ + ,deleg_9to0 : data_cast_mp[9:0] \ + } + + `define decompress_medeleg_s(data_comp_mp) \ + rv64_medeleg_s'({data_comp_mp.deleg_15 \ + ,1'b0 \ + ,data_comp_mp.deleg_13to12 \ + ,2'b0 \ + ,data_comp_mp.deleg_9to0 \ + }) + + `define compress_mideleg_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{sei : data_cast_mp.sei \ + ,sti: data_cast_mp.sti \ + ,ssi: data_cast_mp.ssi \ + } + + `define decompress_mideleg_s(data_comp_mp) \ + '{sei : data_comp_mp.sei \ + ,sti: data_comp_mp.sti \ + ,ssi: data_comp_mp.ssi \ + ,default: '0 \ + } + + `define compress_mie_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{meie : data_cast_mp.meie \ + ,seie: data_cast_mp.seie \ + \ + ,mtie: data_cast_mp.mtie \ + ,stie: data_cast_mp.stie \ + \ + ,msie: data_cast_mp.msie \ + ,ssie: data_cast_mp.ssie \ + } + + `define decompress_mie_s(data_comp_mp) \ + '{meie : data_comp_mp.meie \ + ,seie: data_comp_mp.seie \ + \ + ,mtie: data_comp_mp.mtie \ + ,stie: data_comp_mp.stie \ + \ + ,msie: data_comp_mp.msie \ + ,ssie: data_comp_mp.ssie \ + ,default: '0 \ + } + + `define bp_mtvec_width ($bits(bp_mtvec_s)) + + `define compress_mtvec_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{word_addr: data_cast_mp.base[0+:`BSG_MAX(vaddr_width_mp, paddr_width_mp)-2]} + + `define decompress_mtvec_s(data_comp_mp) \ + '{base : `BSG_SIGN_EXTEND(data_comp_mp.word_addr, 62) \ + ,mode: 2'b00 \ + } + + `define bp_mcounteren_width ($bits(bp_mcounteren_s)) + + `define compress_mcounteren_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{ir : data_cast_mp.ir \ + ,cy: data_cast_mp.cy \ + } + + `define decompress_mcounteren_s(data_comp_mp) \ + '{ir : data_comp_mp.ir \ + ,cy: data_comp_mp.cy \ + ,default: '0 \ + }; + + `define compress_mscratch_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + data_cast_mp[0+:64] + + `define decompress_mscratch_s(data_comp_mp) \ + 64'(data_comp_mp) + + `define compress_mip_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{meip : data_cast_mp.meip \ + ,seip: data_cast_mp.seip \ + \ + ,mtip: data_cast_mp.mtip \ + ,stip: data_cast_mp.stip \ + \ + ,msip: data_cast_mp.msip \ + ,ssip: data_cast_mp.ssip \ + } + + `define decompress_mip_s(data_comp_mp) \ + '{meip : data_comp_mp.meip \ + ,seip: data_comp_mp.seip \ + \ + ,mtip: data_comp_mp.mtip \ + ,stip: data_comp_mp.stip \ + \ + ,msip: data_comp_mp.msip \ + ,ssip: data_comp_mp.ssip \ + ,default: '0 \ + } + + `define compress_mtval_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + bp_mtval_s'(data_cast_mp[0+:`BSG_MAX(vaddr_width_mp, paddr_width_mp)]) + + `define decompress_mtval_s(data_comp_mp) \ + `BSG_SIGN_EXTEND(data_comp_mp, 64) + + `define compress_mepc_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{word_addr: `BSG_SIGN_EXTEND(data_cast_mp.word_addr, 62) \ + ,align : data_cast_mp.align \ + } + + `define decompress_mepc_s(data_comp_mp) \ + '{word_addr: `BSG_SIGN_EXTEND(data_comp_mp.word_addr, 62) \ + ,align : compressed_support_p && data_comp_mp.align \ + ,zero : 1'b0 \ + } + + `define compress_pmpcfg_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{pmpcfg: data_cast_mp.pmpcfg[0+:4]} + + `define decompress_pmpcfg_s(data_comp_mp) \ + '{pmpcfg: ($bits(rv64_pmpcfg_entry_s)*8)'(data_comp_mp.pmpcfg)} + + `define compress_pmpcfg0_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) `compress_pmpcfg_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) + `define compress_pmpcfg1_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) `compress_pmpcfg_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) + `define decompress_pmpcfg0_s(data_comp_mp) `decompress_pmpcfg_s(data_comp_mp) + `define decompress_pmpcfg1_s(data_comp_mp) `decompress_pmpcfg_s(data_comp_mp) + + `define compress_pmpaddr_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{word_addr: data_cast_mp.addr_55_2[0+:`BSG_MAX(vaddr_width_mp, paddr_width_mp)-2]} + + `define decompress_pmpaddr_s(data_comp_mp) \ + '{addr_55_2: 54'(data_comp_mp.word_addr) \ + ,default: '0 \ + } + + `define compress_pmpaddr0_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) `compress_pmpaddr_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) + `define compress_pmpaddr1_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) `compress_pmpaddr_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) + `define compress_pmpaddr2_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) `compress_pmpaddr_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) + `define compress_pmpaddr3_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) `compress_pmpaddr_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) + + `define decompress_pmpaddr0_s(data_cast_mp) `decompress_pmpaddr_s(data_cast_mp) + `define decompress_pmpaddr1_s(data_cast_mp) `decompress_pmpaddr_s(data_cast_mp) + `define decompress_pmpaddr2_s(data_cast_mp) `decompress_pmpaddr_s(data_cast_mp) + `define decompress_pmpaddr3_s(data_cast_mp) `decompress_pmpaddr_s(data_cast_mp) + + `define compress_mcause_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{_interrupt: data_cast_mp._interrupt \ + ,ecode: data_cast_mp.ecode[0+:4] \ + } + + `define decompress_mcause_s(data_comp_mp) \ + '{_interrupt: data_comp_mp._interrupt \ + ,ecode: 63'(data_comp_mp.ecode) \ + } + + `define compress_mcounter_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + bp_mcounter_s'(data_cast_mp[0+:48]) + + `define decompress_mcounter_s(data_comp_mp) \ + rv64_mcounter_s'(data_comp_mp) + + `define compress_mcycle_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) `compress_mcounter_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) + `define compress_minstret_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) `compress_mcounter_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) + + `define decompress_mcycle_s(data_comp_mp) `decompress_mcounter_s(data_comp_mp) + `define decompress_minstret_s(data_comp_mp) `decompress_mcounter_s(data_comp_mp) + + `define compress_mcountinhibit_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{ir : data_cast_mp.ir \ + ,cy: data_cast_mp.cy \ + } + + `define decompress_mcountinhibit_s(data_comp_mp) \ + '{ir : data_comp_mp.ir \ + ,cy: data_comp_mp.cy \ + ,default: '0 \ + } + + `define compress_fcsr_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{frm : data_cast_mp.frm \ + ,fflags: data_cast_mp.fflags \ + } + + `define decompress_fcsr_s(data_comp_mp) \ + '{frm : data_comp_mp.frm \ + ,fflags : data_comp_mp.fflags \ + ,default: '0 \ + } + + `define compress_dcsr_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + '{ebreakm : data_cast_mp.ebreakm \ + ,ebreaks: data_cast_mp.ebreaks \ + ,ebreaku: data_cast_mp.ebreaku \ + ,stepie : data_cast_mp.stepie \ + ,cause : data_cast_mp.cause \ + ,prv : data_cast_mp.prv \ + ,step : data_cast_mp.step \ + ,mprven : data_cast_mp.mprven \ + } + + `define decompress_dcsr_s(data_comp_mp) \ + '{xdebugver : 4'd4 \ + ,ebreakm : data_comp_mp.ebreakm \ + ,ebreaks : data_comp_mp.ebreakm \ + ,ebreaku : data_comp_mp.ebreakm \ + ,stepie : data_comp_mp.stepie \ + ,stopcount: 1'b0 \ + ,stoptime : 1'b0 \ + ,cause : data_comp_mp.cause \ + ,mprven : data_comp_mp.mprven \ + ,nmip : 1'b0 \ + ,step : data_comp_mp.step \ + ,prv : data_comp_mp.prv \ + ,default : '0 \ + } + + `define compress_dpc_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + bp_dpc_s'(data_cast_mp[0+:`BSG_MAX(vaddr_width_mp, paddr_width_mp)]) + + `define decompress_dpc_s(data_comp_mp) \ + `BSG_SIGN_EXTEND(data_comp_mp, 64) + + `define compress_dscratch0_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + data_cast_mp[0+:64] + + `define decompress_dscratch0_s(data_comp_mp) \ + 64'(data_comp_mp) + + `define compress_dscratch1_s(data_cast_mp, vaddr_width_mp, paddr_width_mp) \ + data_cast_mp[0+:64] + + `define decompress_dscratch1_s(data_comp_mp) \ + 64'(data_comp_mp) + + `define declare_csr_addr(csr_name_mp, vaddr_width_mp, paddr_width_mp) \ + /* verilator lint_off UNUSED */ \ + rv64_``csr_name_mp``_s ``csr_name_mp``_li, ``csr_name_mp``_lo; \ + bp_``csr_name_mp``_s ``csr_name_mp``_n, ``csr_name_mp``_r; \ + bsg_dff_reset \ + #(.width_p($bits(bp_``csr_name_mp``_s))) \ + ``csr_name_mp``_reg \ + (.clk_i(clk_i), .reset_i(reset_i), .data_i(``csr_name_mp``_n), .data_o(``csr_name_mp``_r)); \ + assign ``csr_name_mp``_lo = `decompress_``csr_name_mp``_s(``csr_name_mp``_r); \ + assign ``csr_name_mp``_n = `compress_``csr_name_mp``_s(``csr_name_mp``_li, vaddr_width_mp, paddr_width_mp) + /* verilator lint_on UNUSED */ + + `define declare_csr(csr_name_mp) \ + `declare_csr_addr(csr_name_mp, 0, 0) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_rv64_instr_defines.svh b/designs/black-parrot/src/bp/bp_common_rv64_instr_defines.svh new file mode 100644 index 0000000..28d713c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_rv64_instr_defines.svh @@ -0,0 +1,383 @@ +/** + * + * bp_common_rv64_instr_defines.svh + * Based off of: https://bitbucket.org/taylor-bsg/bsg_manycore/src/master/v/vanilla_bean/parameters.v + */ + +`ifndef BP_COMMON_RV64_INSTR_DEFINES_SVH +`define BP_COMMON_RV64_INSTR_DEFINES_SVH + + /* RISCV definitions */ + `define RV64_LUI_OP 7'b0110111 + `define RV64_AUIPC_OP 7'b0010111 + `define RV64_JAL_OP 7'b1101111 + `define RV64_JALR_OP 7'b1100111 + `define RV64_BRANCH_OP 7'b1100011 + `define RV64_LOAD_OP 7'b0000011 + `define RV64_STORE_OP 7'b0100011 + `define RV64_OP_IMM_OP 7'b0010011 + `define RV64_OP_OP 7'b0110011 + `define RV64_MISC_MEM_OP 7'b0001111 + `define RV64_SYSTEM_OP 7'b1110011 + `define RV64_OP_IMM_32_OP 7'b0011011 + `define RV64_OP_32_OP 7'b0111011 + `define RV64_AMO_OP 7'b0101111 + `define RV64_FLOAD_OP 7'b0000111 + `define RV64_FSTORE_OP 7'b0100111 + `define RV64_FP_OP 7'b1010011 + `define RV64_FMADD_OP 7'b1000011 + `define RV64_FMSUB_OP 7'b1000111 + `define RV64_FNMSUB_OP 7'b1001011 + `define RV64_FNMADD_OP 7'b1001111 + + // Some useful RV64 instruction macros + `define rv64_r_type(op, funct3, funct7) {``funct7``,{5{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} + `define rv64_i_type(op, funct3) {{12{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} + `define rv64_s_type(op, funct3) {{7{1'b?}},{5{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} + `define rv64_b_type(op, funct3) {{7{1'b?}},{5{1'b?}},{5{1'b?}},``funct3``,{5{1'b?}},``op``} + `define rv64_u_type(op) {{20{1'b?}},{5{1'b?}},``op``} + `define rv64_fma_type(op, pr2) {{5{1'b?}},``pr2``,{5{1'b?}},{5{1'b?}},{3{3'b?}},{5{1'b?}},``op``} + + // RV64 Immediate sign extension macros + `define rv64_signext_i_imm(instr) {{53{``instr``[31]}},``instr``[30:20]} + `define rv64_signext_s_imm(instr) {{53{``instr``[31]}},``instr[30:25],``instr``[11:7]} + `define rv64_signext_b_imm(instr) {{52{``instr``[31]}},``instr``[7],``instr``[30:25],``instr``[11:8], {1'b0}} + `define rv64_signext_u_imm(instr) {{32{``instr``[31]}},``instr``[31:12], {12{1'b0}}} + `define rv64_signext_j_imm(instr) {{44{``instr``[31]}},``instr``[19:12],``instr``[20],``instr``[30:21], {1'b0}} + `define rv64_signext_c_imm(instr) {{59{1'b0}},``instr``[19:15]} + + // Compressed quadrants + `define RV64_C0_OP 2'b00 + `define RV64_C1_OP 2'b01 + `define RV64_C2_OP 2'b10 + `define RV64_32B_OP 2'b11 + + `define rv64_signext_cj_imm(instr) {{53{``instr``[12]}},``instr``[8],``instr``[10:9],``instr``[6],``instr``[7],``instr``[2],``instr``[11],``instr``[5:3],1'b0} + `define rv64_signext_cb_imm(instr) {{53{``instr``[12]}},``instr``[6:5],``instr``[2],``instr``[11:10],``instr``[4:3],1'b0} + + `define RV64_C0_INSTR {14'b????_????_????_??,`RV64_C0_OP} + `define RV64_C1_INSTR {14'b????_????_????_??,`RV64_C1_OP} + `define RV64_C2_INSTR {14'b????_????_????_??,`RV64_C2_OP} + `define RV64_32B_INSTR {30'b????_????_????_??,`RV32_32B_OP} + + // I extension + `define RV64_LUI `rv64_u_type(`RV64_LUI_OP) + `define RV64_AUIPC `rv64_u_type(`RV64_AUIPC_OP) + `define RV64_JAL `rv64_u_type(`RV64_JAL_OP) + `define RV64_JALR `rv64_i_type(`RV64_JALR_OP,3'b000) + `define RV64_BRANCH `rv64_s_type(`RV64_BRANCH_OP,3'b???) + `define RV64_BEQ `rv64_s_type(`RV64_BRANCH_OP,3'b000) + `define RV64_BNE `rv64_s_type(`RV64_BRANCH_OP,3'b001) + `define RV64_BLT `rv64_s_type(`RV64_BRANCH_OP,3'b100) + `define RV64_BGE `rv64_s_type(`RV64_BRANCH_OP,3'b101) + `define RV64_BLTU `rv64_s_type(`RV64_BRANCH_OP,3'b110) + `define RV64_BGEU `rv64_s_type(`RV64_BRANCH_OP,3'b111) + `define RV64_LB `rv64_i_type(`RV64_LOAD_OP,3'b000) + `define RV64_LH `rv64_i_type(`RV64_LOAD_OP,3'b001) + `define RV64_LW `rv64_i_type(`RV64_LOAD_OP,3'b010) + `define RV64_LOAD `rv64_i_type(`RV64_LOAD_OP,3'b???) + `define RV64_LD `rv64_i_type(`RV64_LOAD_OP,3'b011) + `define RV64_LBU `rv64_i_type(`RV64_LOAD_OP,3'b100) + `define RV64_LHU `rv64_i_type(`RV64_LOAD_OP,3'b101) + `define RV64_LWU `rv64_i_type(`RV64_LOAD_OP,3'b110) + `define RV64_STORE `rv64_s_type(`RV64_STORE_OP,3'b???) + `define RV64_SB `rv64_s_type(`RV64_STORE_OP,3'b000) + `define RV64_SH `rv64_s_type(`RV64_STORE_OP,3'b001) + `define RV64_SW `rv64_s_type(`RV64_STORE_OP,3'b010) + `define RV64_SD `rv64_s_type(`RV64_STORE_OP,3'b011) + `define RV64_ADDI `rv64_i_type(`RV64_OP_IMM_OP,3'b000) + `define RV64_ADDIW `rv64_i_type(`RV64_OP_IMM_32_OP,3'b000) + `define RV64_SLTI `rv64_i_type(`RV64_OP_IMM_OP,3'b010) + `define RV64_SLTIU `rv64_i_type(`RV64_OP_IMM_OP,3'b011) + `define RV64_XORI `rv64_i_type(`RV64_OP_IMM_OP,3'b100) + `define RV64_ORI `rv64_i_type(`RV64_OP_IMM_OP,3'b110) + `define RV64_ANDI `rv64_i_type(`RV64_OP_IMM_OP,3'b111) + `define RV64_SLLI `rv64_r_type(`RV64_OP_IMM_OP,3'b001,7'b000000?) + `define RV64_SLLIW `rv64_r_type(`RV64_OP_IMM_32_OP,3'b001,7'b000000?) + `define RV64_SRLI `rv64_r_type(`RV64_OP_IMM_OP,3'b101,7'b000000?) + `define RV64_SRLIW `rv64_r_type(`RV64_OP_IMM_32_OP,3'b101,7'b000000?) + `define RV64_SRAI `rv64_r_type(`RV64_OP_IMM_OP,3'b101,7'b010000?) + `define RV64_SRAIW `rv64_r_type(`RV64_OP_IMM_32_OP,3'b101,7'b010000?) + `define RV64_ADD `rv64_r_type(`RV64_OP_OP,3'b000,7'b0000000) + `define RV64_ADDW `rv64_r_type(`RV64_OP_32_OP,3'b000,7'b0000000) + `define RV64_SUB `rv64_r_type(`RV64_OP_OP,3'b000,7'b0100000) + `define RV64_SUBW `rv64_r_type(`RV64_OP_32_OP,3'b000,7'b0100000) + `define RV64_SLL `rv64_r_type(`RV64_OP_OP,3'b001,7'b0000000) + `define RV64_SLLW `rv64_r_type(`RV64_OP_32_OP,3'b001,7'b0000000) + `define RV64_SLT `rv64_r_type(`RV64_OP_OP,3'b010,7'b0000000) + `define RV64_SLTU `rv64_r_type(`RV64_OP_OP,3'b011,7'b0000000) + `define RV64_XOR `rv64_r_type(`RV64_OP_OP,3'b100,7'b0000000) + `define RV64_SRL `rv64_r_type(`RV64_OP_OP,3'b101,7'b0000000) + `define RV64_SRLW `rv64_r_type(`RV64_OP_32_OP,3'b101,7'b0000000) + `define RV64_SRA `rv64_r_type(`RV64_OP_OP,3'b101,7'b0100000) + `define RV64_SRAW `rv64_r_type(`RV64_OP_32_OP,3'b101,7'b0100000) + `define RV64_OR `rv64_r_type(`RV64_OP_OP,3'b110,7'b0000000) + `define RV64_AND `rv64_r_type(`RV64_OP_OP,3'b111,7'b0000000) + `define RV64_CSRRW `rv64_i_type(`RV64_SYSTEM_OP,3'b001) + `define RV64_CSRRS `rv64_i_type(`RV64_SYSTEM_OP,3'b010) + `define RV64_CSRRC `rv64_i_type(`RV64_SYSTEM_OP,3'b011) + `define RV64_CSRRWI `rv64_i_type(`RV64_SYSTEM_OP,3'b101) + `define RV64_CSRRSI `rv64_i_type(`RV64_SYSTEM_OP,3'b110) + `define RV64_CSRRCI `rv64_i_type(`RV64_SYSTEM_OP,3'b111) + `define RV64_ECALL 32'b0000_0000_0000_0000_0000_0000_0111_0011 + `define RV64_EBREAK 32'b0000_0000_0001_0000_0000_0000_0111_0011 + `define RV64_URET 32'b0000_0000_0010_0000_0000_0000_0111_0011 + `define RV64_SRET 32'b0001_0000_0010_0000_0000_0000_0111_0011 + `define RV64_MRET 32'b0011_0000_0010_0000_0000_0000_0111_0011 + `define RV64_DRET 32'b0111_1011_0010_0000_0000_0000_0111_0011 + `define RV64_WFI 32'b0001_0000_0101_0000_0000_0000_0111_0011 + `define RV64_SFENCE_VMA 32'b0001_001?_????_????_?000_0000_0111_0011 + `define RV64_FENCE_I 32'b????_????_????_????_?001_????_?000_1111 + `define RV64_FENCE 32'b????_????_????_????_?000_????_?000_1111 + + // CMOs + `define RV64_CBO_INVAL 32'b000000000000_?????_010_00000_0001111 + `define RV64_CBO_CLEAN 32'b000000000001_?????_010_00000_0001111 + `define RV64_CBO_FLUSH 32'b000000000010_?????_010_00000_0001111 + `define RV64_CBO_ZERO 32'b000000000100_?????_010_00000_0001111 + `define RV64_CMO_PREFETCHI 32'b???????_00000_?????_110_00000_0010011 + `define RV64_CMO_PREFETCHR 32'b???????_00001_?????_110_00000_0010011 + `define RV64_CMO_PREFETCHW 32'b???????_00011_?????_110_00000_0010011 + + // CMO Custom -- Don't count on these staying the same!! + `define RV64_CMO_INVAL_ALL 32'b000000000000_?????_111_00000_0001111 + `define RV64_CMO_CLEAN_ALL 32'b000000000001_?????_111_00000_0001111 + `define RV64_CMO_FLUSH_ALL 32'b000000000010_?????_111_00000_0001111 + + // A extension + `define RV64_LRW 32'b0001_0??0_0000_????_?010_????_?010_1111 + `define RV64_SCW 32'b0001_1???_????_????_?010_????_?010_1111 + `define RV64_AMOSWAPW 32'b0000_1???_????_????_?010_????_?010_1111 + `define RV64_AMOADDW 32'b0000_0???_????_????_?010_????_?010_1111 + `define RV64_AMOXORW 32'b0010_0???_????_????_?010_????_?010_1111 + `define RV64_AMOANDW 32'b0110_0???_????_????_?010_????_?010_1111 + `define RV64_AMOORW 32'b0100_0???_????_????_?010_????_?010_1111 + `define RV64_AMOMINW 32'b1000_0???_????_????_?010_????_?010_1111 + `define RV64_AMOMAXW 32'b1010_0???_????_????_?010_????_?010_1111 + `define RV64_AMOMINUW 32'b1100_0???_????_????_?010_????_?010_1111 + `define RV64_AMOMAXUW 32'b1110_0???_????_????_?010_????_?010_1111 + `define RV64_LRD 32'b0001_0??0_0000_????_?011_????_?010_1111 + `define RV64_SCD 32'b0001_1???_????_????_?011_????_?010_1111 + `define RV64_AMOSWAPD 32'b0000_1???_????_????_?011_????_?010_1111 + `define RV64_AMOADDD 32'b0000_0???_????_????_?011_????_?010_1111 + `define RV64_AMOXORD 32'b0010_0???_????_????_?011_????_?010_1111 + `define RV64_AMOANDD 32'b0110_0???_????_????_?011_????_?010_1111 + `define RV64_AMOORD 32'b0100_0???_????_????_?011_????_?010_1111 + `define RV64_AMOMIND 32'b1000_0???_????_????_?011_????_?010_1111 + `define RV64_AMOMAXD 32'b1010_0???_????_????_?011_????_?010_1111 + `define RV64_AMOMINUD 32'b1100_0???_????_????_?011_????_?010_1111 + `define RV64_AMOMAXUD 32'b1110_0???_????_????_?011_????_?010_1111 + + // M extension + `define RV64_MUL `rv64_r_type(`RV64_OP_OP,3'b000,7'b0000001) + `define RV64_MULH `rv64_r_type(`RV64_OP_OP,3'b001,7'b0000001) + `define RV64_MULHSU `rv64_r_type(`RV64_OP_OP,3'b010,7'b0000001) + `define RV64_MULHU `rv64_r_type(`RV64_OP_OP,3'b011,7'b0000001) + `define RV64_DIV `rv64_r_type(`RV64_OP_OP,3'b100,7'b0000001) + `define RV64_DIVU `rv64_r_type(`RV64_OP_OP,3'b101,7'b0000001) + `define RV64_REM `rv64_r_type(`RV64_OP_OP,3'b110,7'b0000001) + `define RV64_REMU `rv64_r_type(`RV64_OP_OP,3'b111,7'b0000001) + + `define RV64_MULW `rv64_r_type(`RV64_OP_32_OP,3'b000,7'b0000001) + `define RV64_DIVW `rv64_r_type(`RV64_OP_32_OP,3'b100,7'b0000001) + `define RV64_DIVUW `rv64_r_type(`RV64_OP_32_OP,3'b101,7'b0000001) + `define RV64_REMW `rv64_r_type(`RV64_OP_32_OP,3'b110,7'b0000001) + `define RV64_REMUW `rv64_r_type(`RV64_OP_32_OP,3'b111,7'b0000001) + + // F extension + `define RV64_FL_W `rv64_i_type(`RV64_FLOAD_OP,3'b010) + `define RV64_FS_W `rv64_i_type(`RV64_FSTORE_OP,3'b010) + `define RV64_FMADD_S `rv64_fma_type(`RV64_FMADD_OP,2'b00) + `define RV64_FMSUB_S `rv64_fma_type(`RV64_FMSUB_OP,2'b00) + `define RV64_FNMSUB_S `rv64_fma_type(`RV64_FNMSUB_OP,2'b00) + `define RV64_FNMADD_S `rv64_fma_type(`RV64_FNMADD_OP,2'b00) + `define RV64_FADD_S `rv64_r_type(`RV64_FP_OP,3'b???,7'b0000000) + `define RV64_FSUB_S `rv64_r_type(`RV64_FP_OP,3'b???,7'b0000100) + `define RV64_FMUL_S `rv64_r_type(`RV64_FP_OP,3'b???,7'b0001000) + `define RV64_FDIV_S `rv64_r_type(`RV64_FP_OP,3'b???,7'b0001100) + `define RV64_FSQRT_S 32'b0101100_00000_?????_???_?????_1010011 + `define RV64_FSGNJ_S `rv64_r_type(`RV64_FP_OP,3'b000,7'b0010000) + `define RV64_FSGNJN_S `rv64_r_type(`RV64_FP_OP,3'b001,7'b0010000) + `define RV64_FSGNJX_S `rv64_r_type(`RV64_FP_OP,3'b010,7'b0010000) + `define RV64_FMIN_S `rv64_r_type(`RV64_FP_OP,3'b000,7'b0010100) + `define RV64_FMAX_S `rv64_r_type(`RV64_FP_OP,3'b001,7'b0010100) + `define RV64_FCVT_WS 32'b1100000_00000_?????_???_?????_1010011 + `define RV64_FCVT_WUS 32'b1100000_00001_?????_???_?????_1010011 + `define RV64_FMV_XW 32'b1110000_00000_?????_000_?????_1010011 + `define RV64_FEQ_S `rv64_r_type(`RV64_FP_OP,3'b010,7'b1010000) + `define RV64_FLT_S `rv64_r_type(`RV64_FP_OP,3'b001,7'b1010000) + `define RV64_FLE_S `rv64_r_type(`RV64_FP_OP,3'b000,7'b1010000) + `define RV64_FCLASS_S 32'b1110000_00000_?????_001_?????_1010011 + `define RV64_FCVT_SW 32'b1101000_00000_?????_???_?????_1010011 + `define RV64_FCVT_SWU 32'b1101000_00001_?????_???_?????_1010011 + `define RV64_FMV_WX 32'b1111000_00000_?????_000_?????_1010011 + `define RV64_FCVT_LS 32'b1100000_00010_?????_???_?????_1010011 + `define RV64_FCVT_LUS 32'b1100000_00011_?????_???_?????_1010011 + `define RV64_FCVT_SL 32'b1101000_00010_?????_???_?????_1010011 + `define RV64_FCVT_SLU 32'b1101000_00011_?????_???_?????_1010011 + + // D extension + `define RV64_FL_D `rv64_i_type(`RV64_FLOAD_OP,3'b011) + `define RV64_FS_D `rv64_i_type(`RV64_FSTORE_OP,3'b11) + `define RV64_FMADD_D `rv64_fma_type(`RV64_FMADD_OP,2'b01) + `define RV64_FMSUB_D `rv64_fma_type(`RV64_FMSUB_OP,2'b01) + `define RV64_FNMSUB_D `rv64_fma_type(`RV64_FNMSUB_OP,2'b01) + `define RV64_FNMADD_D `rv64_fma_type(`RV64_FNMADD_OP,2'b01) + `define RV64_FADD_D `rv64_r_type(`RV64_FP_OP,3'b???,7'b0000001) + `define RV64_FSUB_D `rv64_r_type(`RV64_FP_OP,3'b???,7'b0000101) + `define RV64_FMUL_D `rv64_r_type(`RV64_FP_OP,3'b???,7'b0001001) + `define RV64_FDIV_D `rv64_r_type(`RV64_FP_OP,3'b???,7'b0001101) + `define RV64_FSQRT_D 32'b0101101_00000_?????_???_?????_1010011 + `define RV64_FSGNJ_D `rv64_r_type(`RV64_FP_OP,3'b000,7'b0010001) + `define RV64_FSGNJN_D `rv64_r_type(`RV64_FP_OP,3'b001,7'b0010001) + `define RV64_FSGNJX_D `rv64_r_type(`RV64_FP_OP,3'b010,7'b0010001) + `define RV64_FMIN_D `rv64_r_type(`RV64_FP_OP,3'b000,7'b0010101) + `define RV64_FMAX_D `rv64_r_type(`RV64_FP_OP,3'b001,7'b0010101) + `define RV64_FCVT_SD 32'b0100000_00001_?????_???_?????_1010011 + `define RV64_FCVT_DS 32'b0100001_00000_?????_???_?????_1010011 + `define RV64_FEQ_D `rv64_r_type(`RV64_FP_OP,3'b010,7'b1010001) + `define RV64_FLT_D `rv64_r_type(`RV64_FP_OP,3'b001,7'b1010001) + `define RV64_FLE_D `rv64_r_type(`RV64_FP_OP,3'b000,7'b1010001) + `define RV64_FCLASS_D 32'b1110001_00000_?????_001_?????_1010011 + `define RV64_FCVT_WD 32'b1100001_00000_?????_???_?????_1010011 + `define RV64_FCVT_WUD 32'b1100001_00001_?????_???_?????_1010011 + `define RV64_FCVT_DW 32'b1101001_00000_?????_???_?????_1010011 + `define RV64_FCVT_DWU 32'b1101001_00001_?????_???_?????_1010011 + `define RV64_FCVT_LD 32'b1100001_00010_?????_???_?????_1010011 + `define RV64_FCVT_LUD 32'b1100001_00011_?????_???_?????_1010011 + `define RV64_FMV_XD 32'b1110001_00000_?????_000_?????_1010011 + `define RV64_FCVT_DL 32'b1101001_00010_?????_???_?????_1010011 + `define RV64_FCVT_DLU 32'b1101001_00011_?????_???_?????_1010011 + `define RV64_FMV_DX 32'b1111001_00000_?????_000_?????_1010011 + + // C extension + // Instruction expansions + `define rv64_r_type_exp(op, rd, funct3, rs1, rs2, funct7) {``funct7``,``rs2``,``rs1``,``funct3``,``rd``,``op``} + `define rv64_i_type_exp(op, rd, funct3, rs1, imm) {``imm``[11:0],``rs1``,``funct3``,``rd``,``op``} + `define rv64_s_type_exp(op, funct3, rs1, rs2, imm) {``imm``[11:5],``rs2``,``rs1``,``funct3``,``imm``[4:0],``op``} + `define rv64_u_type_exp(op, rd, imm) {``imm``[31:12],``rd``,``op``} + `define rv64_b_type_exp(op, funct3, rs1, rs2, imm) {``imm``[12],``imm``[10:5],``rs2``,``rs1``,``funct3``,``imm``[4:1],``imm``[11],``op``} + `define rv64_j_type_exp(op, rd, imm) {``imm``[20],``imm``[10:1],``imm``[11],``imm``[19:12],``rd``,``op``} + + // Instruction types + `define rv64_cr_type(op, funct4) {``funct4``,{5{1'b?}},{5{1'b?}},``op``} + `define rv64_ci_type(op, funct3) {``funct3``,{1{1'b?}},{5{1'b?}},{5{1'b?}},``op``} + `define rv64_css_type(op, funct3) {``funct3``,{6{1'b?}},{5{1'b?}},``op``} + `define rv64_ciw_type(op, funct3) {``funct3``,{8{1'b?}},{3{1'b?}},``op``} + `define rv64_cl_type(op, funct3) {``funct3``,{3{1'b?}},{3{1'b?}},{2{1'b?}},{3{1'b?}},``op``} + `define rv64_cs_type(op, funct3) {``funct3``,{3{1'b?}},{3{1'b?}},{2{1'b?}},{3{1'b?}},``op``} + `define rv64_ca_type(op, funct6, funct2) {``funct6``,{3{1'b?}},``funct2``,{3{1'b?}},``op``} + `define rv64_cb_type(op, funct3) {``funct3``,{3{1'b?}},{3{1'b?}},{5{1'b?}},``op``} + `define rv64_cb2_type(op, funct3, funct2) {``funct3``,{1{1'b?}},``funct2``,{3{1'b?}},{5{1'b?}},``op``} + `define rv64_cj_type(op, funct3) {``funct3``,{11{1'b?}},``op``} + + `define RV64_CLWSP `rv64_ci_type(`RV64_C2_OP,3'b010) + `define RV64_CLDSP `rv64_ci_type(`RV64_C2_OP,3'b011) + `define RV64_CSWSP `rv64_css_type(`RV64_C2_OP,3'b110) + `define RV64_CSDSP `rv64_css_type(`RV64_C2_OP,3'b111) + `define RV64_CLW `rv64_cl_type(`RV64_C0_OP,3'b010) + `define RV64_CLD `rv64_cl_type(`RV64_C0_OP,3'b011) + `define RV64_CSW `rv64_cs_type(`RV64_C0_OP,3'b110) + `define RV64_CSD `rv64_cs_type(`RV64_C0_OP,3'b111) + `define RV64_CJ `rv64_cj_type(`RV64_C1_OP,3'b101) + `define RV64_CJR 16'b1000_????_?000_0010 + `define RV64_CJALR 16'b1001_????_?000_0010 + `define RV64_CBEQZ `rv64_cb_type(`RV64_C1_OP,3'b110) + `define RV64_CBNEZ `rv64_cb_type(`RV64_C1_OP,3'b111) + `define RV64_CLI `rv64_ci_type(`RV64_C1_OP,3'b010) + `define RV64_CLUI `rv64_ci_type(`RV64_C1_OP,3'b011) + + `define RV64_CADDI `rv64_ci_type(`RV64_C1_OP,3'b000) + `define RV64_CADDIW `rv64_ci_type(`RV64_C1_OP,3'b001) + `define RV64_CADDI16SP 16'b011?_0001_0???_??01 + + `define RV64_CADDI4SPN `rv64_ciw_type(`RV64_C0_OP,3'b000) + `define RV64_CSLLI `rv64_ci_type(`RV64_C2_OP,3'b000) + `define RV64_CSRLI `rv64_cb2_type(`RV64_C1_OP,3'b100,2'b00) + `define RV64_CSRAI `rv64_cb2_type(`RV64_C1_OP,3'b100,2'b01) + `define RV64_CANDI `rv64_cb2_type(`RV64_C1_OP,3'b100,2'b10) + `define RV64_CMV `rv64_cr_type(`RV64_C2_OP,4'b1000) + `define RV64_CADD `rv64_cr_type(`RV64_C2_OP,4'b1001) + `define RV64_CAND `rv64_ca_type(`RV64_C1_OP,6'b100011,2'b11) + `define RV64_COR `rv64_ca_type(`RV64_C1_OP,6'b100011,2'b10) + `define RV64_CXOR `rv64_ca_type(`RV64_C1_OP,6'b100011,2'b01) + `define RV64_CSUB `rv64_ca_type(`RV64_C1_OP,6'b100011,2'b00) + `define RV64_CADDW `rv64_ca_type(`RV64_C1_OP,6'b100111,2'b01) + `define RV64_CSUBW `rv64_ca_type(`RV64_C1_OP,6'b100111,2'b00) + `define RV64_CILL 16'b0000_0000_0000_0000 + `define RV64_CNOP 16'b0000_0000_0000_0001 + `define RV64_CEBREAK 16'b1001_0000_0000_0010 + + `define RV64_CFLD `rv64_cs_type(`RV64_C0_OP,3'b001) + `define RV64_CFSD `rv64_cs_type(`RV64_C0_OP,3'b101) + `define RV64_CFLWSP `rv64_css_type(`RV64_C2_OP,3'b011) + `define RV64_CFLDSP `rv64_css_type(`RV64_C2_OP,3'b001) + `define RV64_CFSWSP `rv64_cl_type(`RV64_C2_OP,3'b111) + `define RV64_CFSDSP `rv64_cl_type(`RV64_C2_OP,3'b101) + + // Bitmanip + // expansions + `define rv64_fi_type(op, funct3, funct12) {``funct12``,{5{1'b?}},``funct3``,{5{1'b?}},``op``} + + // Zba + `define RV64_ADDUW `rv64_r_type(`RV64_OP_32_OP,3'b000,7'b0000100) + `define RV64_SH1ADD `rv64_r_type(`RV64_OP_OP,3'b010,7'b0010000) + `define RV64_SH1ADDUW `rv64_r_type(`RV64_OP_32_OP,3'b010,7'b0010000) + `define RV64_SH2ADD `rv64_r_type(`RV64_OP_OP,3'b100,7'b0010000) + `define RV64_SH2ADDUW `rv64_r_type(`RV64_OP_32_OP,3'b100,7'b0010000) + `define RV64_SH3ADD `rv64_r_type(`RV64_OP_OP,3'b110,7'b0010000) + `define RV64_SH3ADDUW `rv64_r_type(`RV64_OP_32_OP,3'b110,7'b0010000) + `define RV64_SLLIUW `rv64_fi_type(`RV64_OP_IMM_32_OP,3'b001,12'b000010??????) + + // Zbb + `define RV64_ANDN `rv64_r_type(`RV64_OP_OP,3'b111,7'b0100000) + `define RV64_CLZ `rv64_fi_type(`RV64_OP_IMM_OP,3'b001,12'b0110000_00000) + `define RV64_CLZW `rv64_fi_type(`RV64_OP_IMM_32_OP,3'b001,12'b0110000_00000) + `define RV64_CPOP `rv64_fi_type(`RV64_OP_IMM_OP,3'b001,12'b0110000_00010) + `define RV64_CPOPW `rv64_fi_type(`RV64_OP_IMM_32_OP,3'b001,12'b0110000_00010) + `define RV64_CTZ `rv64_fi_type(`RV64_OP_IMM_OP,3'b001,12'b0110000_00001) + `define RV64_CTZW `rv64_fi_type(`RV64_OP_IMM_32_OP,3'b001,12'b0110000_00001) + `define RV64_MAX `rv64_r_type(`RV64_OP_OP,3'b110,7'b0000101) + `define RV64_MAXU `rv64_r_type(`RV64_OP_OP,3'b111,7'b0000101) + `define RV64_MIN `rv64_r_type(`RV64_OP_OP,3'b100,7'b0000101) + `define RV64_MINU `rv64_r_type(`RV64_OP_OP,3'b101,7'b0000101) + `define RV64_ORCB `rv64_fi_type(`RV64_OP_IMM_OP,3'b101,12'b0010100_00111) + `define RV64_ORN `rv64_r_type(`RV64_OP_OP,3'b110,7'b0100000) + `define RV64_REV8 `rv64_fi_type(`RV64_OP_IMM_OP,3'b101,12'b011010111000) + `define RV64_ROL `rv64_r_type(`RV64_OP_OP,3'b001,7'b0110000) + `define RV64_ROLW `rv64_r_type(`RV64_OP_32_OP,3'b001,7'b0110000) + `define RV64_ROR `rv64_r_type(`RV64_OP_OP,3'b101,7'b0110000) + `define RV64_RORI `rv64_fi_type(`RV64_OP_IMM_OP,3'b101,12'b011000_??????) + `define RV64_RORIW `rv64_fi_type(`RV64_OP_IMM_32_OP,3'b101,12'b0110000_?????) + `define RV64_RORW `rv64_r_type(`RV64_OP_32_OP,3'b101,7'b0110000) + `define RV64_SEXTB `rv64_fi_type(`RV64_OP_IMM_OP,3'b001,12'b0110000_00100) + `define RV64_SEXTH `rv64_fi_type(`RV64_OP_IMM_OP,3'b001,12'b0110000_00101) + `define RV64_XNOR `rv64_r_type(`RV64_OP_OP,3'b100,7'b0100000) + `define RV64_ZEXTH `rv64_r_type(`RV64_OP_32_OP,3'b100,7'b0000100) + + // Zbc + `define RV64_CLMUL `rv64_r_type(`RV64_OP_OP,3'b001,7'b0000101) + `define RV64_CLMULH `rv64_r_type(`RV64_OP_OP,3'b011,7'b0000101) + `define RV64_CLMULR `rv64_r_type(`RV64_OP_OP,3'b010,7'b0000101) + + // Zbs + `define RV64_BCLR `rv64_r_type(`RV64_OP_OP,3'b001,7'b0100100) + `define RV64_BCLRI `rv64_fi_type(`RV64_OP_IMM_OP,3'b001,12'b010010_??????) + `define RV64_BEXT `rv64_r_type(`RV64_OP_OP,3'b101,7'b0100100) + `define RV64_BEXTI `rv64_fi_type(`RV64_OP_IMM_OP,3'b101,12'b010010_??????) + `define RV64_BINV `rv64_r_type(`RV64_OP_OP,3'b001,7'b0110100) + `define RV64_BINVI `rv64_fi_type(`RV64_OP_IMM_OP,3'b001,12'b011010_??????) + `define RV64_BSET `rv64_r_type(`RV64_OP_OP,3'b001,7'b0010100) + `define RV64_BSETI `rv64_fi_type(`RV64_OP_IMM_OP,3'b001,12'b001010_??????) + + // Fusion candidates + //`define RV64_ADD `rv64_r_type(`RV64_OP_OP,3'b000,7'b0000000) + `define RV64_LI {{12'b????????????},{5'b00000},{3'b000},{5'b?????},{7'b0010011}} + `define RV64_MV {{12'b000000000000},{5'b?????},{3'b000},{5'b?????},{7'b0010011}} + `define RV64_RET {{12'b000000000000},{5'b?????},{3'b000},{5'b00000},{7'b1100111}} + //`define RV64_BRANCH `rv64_s_type(`RV64_BRANCH_OP,3'b???) + //`define RV64_LUI `rv64_u_type(`RV64_LUI_OP) + //`define RV64_AUIPC `rv64_u_type(`RV64_AUIPC_OP) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_common_rv64_pkgdef.svh b/designs/black-parrot/src/bp/bp_common_rv64_pkgdef.svh new file mode 100644 index 0000000..b70734d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_common_rv64_pkgdef.svh @@ -0,0 +1,326 @@ +`ifndef BP_COMMON_RV64_PKGDEF_SVH +`define BP_COMMON_RV64_PKGDEF_SVH + + localparam dword_width_gp = 64; + localparam word_width_gp = 32; + localparam half_width_gp = 16; + localparam byte_width_gp = 8; + localparam cinstr_width_gp = 16; + localparam instr_width_gp = 32; + localparam csr_addr_width_gp = 12; + localparam reg_addr_width_gp = 5; + localparam page_offset_width_gp = 12; + + localparam rv64_rf_els_gp = 32; + localparam rv64_instr_width_gp = 32; + localparam rv64_eaddr_width_gp = 64; + localparam rv64_byte_width_gp = 8; + localparam rv64_hword_width_gp = 16; + localparam rv64_word_width_gp = 32; + localparam rv64_dword_width_gp = 64; + localparam rv64_reg_data_width_gp = 64; + localparam rv64_reg_addr_width_gp = 5; + localparam rv64_creg_addr_width_gp = 3; + localparam rv64_shamt_width_gp = 6; + localparam rv64_shamtw_width_gp = 5; + localparam rv64_opcode_width_gp = 7; + localparam rv64_copcode_width_gp = 2; + localparam rv64_funct2_width_gp = 2; + localparam rv64_funct3_width_gp = 3; + localparam rv64_funct4_width_gp = 4; + localparam rv64_funct6_width_gp = 6; + localparam rv64_funct7_width_gp = 7; + localparam rv64_csr_addr_width_gp = 12; + localparam rv64_priv_width_gp = 2; + + typedef struct packed + { + logic [rv64_funct7_width_gp-1:0] funct7; + logic [rv64_reg_addr_width_gp-1:0] rs2_addr; + logic [rv64_reg_addr_width_gp-1:0] rs1_addr; + logic [rv64_funct3_width_gp-1:0] funct3; + logic [rv64_reg_addr_width_gp-1:0] rd_addr; + logic [rv64_opcode_width_gp-1:0] opcode; + } rv64_instr_rtype_s; + + typedef struct packed + { + logic [rv64_reg_addr_width_gp-1:0] rs3_addr; + logic [1:0] fmt; + logic [rv64_reg_addr_width_gp-1:0] rs2_addr; + logic [rv64_reg_addr_width_gp-1:0] rs1_addr; + logic [2:0] rm; + logic [rv64_reg_addr_width_gp-1:0] rd_addr; + logic [rv64_opcode_width_gp-1:0] opcode; + } rv64_instr_fmatype_s; + + typedef struct packed + { + logic [rv64_funct7_width_gp-1:0] funct7; + logic [rv64_reg_addr_width_gp-1:0] rs2_addr; + logic [rv64_reg_addr_width_gp-1:0] rs1_addr; + logic [2:0] rm; + logic [rv64_reg_addr_width_gp-1:0] rd_addr; + logic [rv64_opcode_width_gp-1:0] opcode; + } rv64_instr_ftype_s; + + typedef struct packed + { + logic [11:0] imm12; + logic [rv64_reg_addr_width_gp-1:0] rs1; + logic [rv64_funct3_width_gp-1:0] funct3; + logic [rv64_reg_addr_width_gp-1:0] rd_addr; + logic [rv64_opcode_width_gp-1:0] opcode; + } rv64_instr_itype_s; + + typedef struct packed + { + logic [11:5] imm11to5; + logic [rv64_reg_addr_width_gp-1:0] rs2; + logic [rv64_reg_addr_width_gp-1:0] rs1; + logic [rv64_funct3_width_gp-1:0] funct3; + logic [4:0] imm4to0; + logic [rv64_opcode_width_gp-1:0] opcode; + } rv64_instr_stype_s; + + typedef struct packed + { + logic [19:0] imm20; + logic [rv64_reg_addr_width_gp-1:0] rd_addr; + logic [rv64_opcode_width_gp-1:0] opcode; + } rv64_instr_utype_s; + + typedef struct packed + { + logic imm12; + logic [10:5] imm10to5; + logic [rv64_reg_addr_width_gp-1:0] rs2; + logic [rv64_reg_addr_width_gp-1:0] rs1; + logic [rv64_funct3_width_gp-1:0] funct3; + logic [4:1] imm4to1; + logic imm11; + logic [rv64_opcode_width_gp-1:0] opcode; + } rv64_instr_btype_s; + + typedef struct packed + { + union packed + { + rv64_instr_rtype_s rtype; + rv64_instr_fmatype_s fmatype; + rv64_instr_ftype_s ftype; + rv64_instr_itype_s itype; + rv64_instr_stype_s stype; + rv64_instr_utype_s utype; + rv64_instr_btype_s btype; + } t; + } rv64_instr_s; + + typedef struct packed + { + logic [rv64_funct4_width_gp-1:0] funct4; + logic [rv64_reg_addr_width_gp-1:0] rdrs1_addr; + logic [rv64_reg_addr_width_gp-1:0] rs2_addr; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_crtype_s; + + typedef struct packed + { + logic [rv64_funct3_width_gp-1:0] funct3; + logic [5:5] imm5; + logic [rv64_reg_addr_width_gp-1:0] rdrs1_addr; + logic [4:0] imm4to0; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_citype_s; + + typedef struct packed + { + logic [rv64_funct3_width_gp-1:0] funct3; + logic [5:0] imm6; + logic [rv64_reg_addr_width_gp-1:0] rs2_addr; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_csstype_s; + + typedef struct packed + { + logic [rv64_funct3_width_gp-1:0] funct3; + logic [7:0] imm8; + logic [rv64_creg_addr_width_gp-1:0] rdp_addr; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_ciwtype_s; + + typedef struct packed + { + logic [rv64_funct3_width_gp-1:0] funct3; + logic [4:2] imm4to2; + logic [rv64_creg_addr_width_gp-1:0] rs1p_addr; + logic [1:0] imm1to0; + logic [rv64_creg_addr_width_gp-1:0] rdp_addr; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_cltype_s; + + typedef struct packed + { + logic [rv64_funct3_width_gp-1:0] funct3; + logic [4:2] imm4to2; + logic [rv64_creg_addr_width_gp-1:0] rs1p_addr; + logic [1:0] imm1to0; + logic [rv64_creg_addr_width_gp-1:0] rs2p_addr; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_cstype_s; + + typedef struct packed + { + logic [rv64_funct6_width_gp-1:0] funct6; + logic [rv64_creg_addr_width_gp-1:0] rdrs1p_addr; + logic [rv64_funct2_width_gp-1:0] funct2; + logic [rv64_creg_addr_width_gp-1:0] rs2p_addr; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_catype_s; + + typedef struct packed + { + logic [rv64_funct3_width_gp-1:0] funct3; + logic [7:5] offset7to5; + logic [rv64_creg_addr_width_gp-1:0] rdrs1p_addr; + logic [4:0] offset4to0; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_cbtype_s; + + typedef struct packed + { + logic [rv64_funct3_width_gp-1:0] funct3; + logic [10:0] target; + logic [rv64_copcode_width_gp-1:0] opcode; + } rv64_instr_cjtype_s; + + typedef struct packed + { + union packed + { + rv64_instr_crtype_s crtype; + rv64_instr_citype_s citype; + rv64_instr_csstype_s csstype; + rv64_instr_ciwtype_s ciwtype; + rv64_instr_cltype_s cltype; + rv64_instr_cstype_s cstype; + rv64_instr_catype_s catype; + rv64_instr_cbtype_s cbtype; + rv64_instr_cjtype_s cjtype; + } t; + } rv64_cinstr_s; + + typedef struct packed + { + // RISC-V exceptions + logic store_page_fault; + logic reserved2; + logic load_page_fault; + logic instr_page_fault; + logic ecall_m_mode; + logic reserved1; + logic ecall_s_mode; + logic ecall_u_mode; + logic store_access_fault; + logic store_misaligned; + logic load_access_fault; + logic load_misaligned; + logic breakpoint; + logic illegal_instr; + logic instr_access_fault; + logic instr_misaligned; + } rv64_exception_dec_s; + + typedef enum logic [2:0] + { + e_rne = 3'b000 + ,e_rtz = 3'b001 + ,e_rdn = 3'b010 + ,e_rup = 3'b011 + ,e_rmm = 3'b100 + // 3'b101, 3'b110 reserved + ,e_dyn = 3'b111 + } rv64_frm_e; + + typedef enum logic + { + e_fmt_single = 1'b0 + ,e_fmt_double = 1'b1 + } rv64_fmt_e; + + typedef struct packed + { + // Invalid operation + logic nv; + // Divide by zero + logic dz; + // Overflow + logic of; + // Underflow + logic uf; + // Inexact + logic nx; + } rv64_fflags_s; + + typedef struct packed + { + // Invalid operation + logic nv; + // Overflow + logic of; + // Inexact + logic nx; + } rv64_iflags_s; + + typedef struct packed + { + logic [53:0] padding; + logic q_nan; + logic s_nan; + logic p_inf; + logic p_norm; + logic p_sub; + logic p_zero; + logic n_zero; + logic n_sub; + logic n_norm; + logic n_inf; + } rv64_fclass_s; + + /* + * RV64 specifies a 64b effective address and 32b instruction. + * BlackParrot supports SV39 virtual memory, which specifies 39b virtual / 56b physical address. + * Effective addresses must have bits 39-63 match bit 38 + * or a page fault exception will occur during translation. + * Currently, we only support a very limited number of parameter configurations. + * Thought: We could have a `define surrounding core instantiations of each parameter and then + * when they import this package, `declare the if structs. No more casting! + */ + + localparam sv39_pte_width_gp = 64; + localparam sv39_levels_gp = 3; + localparam sv39_vaddr_width_gp = 39; + localparam sv39_paddr_width_gp = 56; + localparam sv39_ppn_width_gp = 44; + localparam sv39_page_idx_width_gp = 9; + localparam sv39_page_offset_width_gp = 12; + localparam sv39_page_size_in_bytes_gp = 1 << sv39_page_offset_width_gp; + localparam sv39_pte_size_in_bytes_gp = 8; + + typedef struct packed + { + logic [sv39_pte_width_gp-10-sv39_ppn_width_gp-1:0] reserved; + logic [sv39_ppn_width_gp-1:0] ppn; + logic [1:0] rsw; + logic d; + logic a; + logic g; + logic u; + logic x; + logic w; + logic r; + logic v; + } sv39_pte_s; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_core.sv b/designs/black-parrot/src/bp/bp_core.sv new file mode 100644 index 0000000..38fd93e --- /dev/null +++ b/designs/black-parrot/src/bp/bp_core.sv @@ -0,0 +1,391 @@ + +/** + * + * bp_core.sv + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" +`include "bsg_cache.svh" +`include "bsg_noc_links.svh" + +module bp_core + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + import bp_top_pkg::*; + import bsg_cache_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + , localparam dma_pkt_width_lp = `bsg_cache_dma_pkt_width(daddr_width_p, l2_block_size_in_words_p) + ) + (input clk_i + , input rt_clk_i + , input reset_i + + , output logic [cfg_bus_width_lp-1:0] cfg_bus_o + , output logic cce_ucode_v_o + , output logic cce_ucode_w_o + , output logic [cce_pc_width_p-1:0] cce_ucode_addr_o + , output logic [cce_instr_width_gp-1:0] cce_ucode_data_o + , input [cce_instr_width_gp-1:0] cce_ucode_data_i + + // Memory side connection + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + + , output logic [1:0][lce_req_header_width_lp-1:0] lce_req_header_o + , output logic [1:0][icache_fill_width_p-1:0] lce_req_data_o + , output logic [1:0] lce_req_v_o + , input [1:0] lce_req_ready_and_i + + , input [1:0][lce_cmd_header_width_lp-1:0] lce_cmd_header_i + , input [1:0][icache_fill_width_p-1:0] lce_cmd_data_i + , input [1:0] lce_cmd_v_i + , output logic [1:0] lce_cmd_ready_and_o + + , input [1:0][lce_fill_header_width_lp-1:0] lce_fill_header_i + , input [1:0][icache_fill_width_p-1:0] lce_fill_data_i + , input [1:0] lce_fill_v_i + , output logic [1:0] lce_fill_ready_and_o + + , output logic [1:0][lce_fill_header_width_lp-1:0] lce_fill_header_o + , output logic [1:0][icache_fill_width_p-1:0] lce_fill_data_o + , output logic [1:0] lce_fill_v_o + , input [1:0] lce_fill_ready_and_i + + , output logic [1:0][lce_resp_header_width_lp-1:0] lce_resp_header_o + , output logic [1:0][icache_fill_width_p-1:0] lce_resp_data_o + , output logic [1:0] lce_resp_v_o + , input [1:0] lce_resp_ready_and_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + , output logic [l2_slices_p-1:0][l2_banks_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_o + , output logic [l2_slices_p-1:0][l2_banks_p-1:0] dma_pkt_v_o + , input [l2_slices_p-1:0][l2_banks_p-1:0] dma_pkt_ready_and_i + + , input [l2_slices_p-1:0][l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_i + , input [l2_slices_p-1:0][l2_banks_p-1:0] dma_data_v_i + , output logic [l2_slices_p-1:0][l2_banks_p-1:0] dma_data_ready_and_o + + , output logic [l2_slices_p-1:0][l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_o + , output logic [l2_slices_p-1:0][l2_banks_p-1:0] dma_data_v_o + , input [l2_slices_p-1:0][l2_banks_p-1:0] dma_data_ready_and_i + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + + // Only CCE acts as a proc for multicore + localparam cce_proc_id_lp = 0; + localparam num_proc_lp = cce_proc_id_lp + 1; + localparam lg_num_proc_lp = `BSG_SAFE_CLOG2(num_proc_lp); + + localparam cfg_dev_id_lp = 0; + localparam clint_dev_id_lp = cfg_dev_id_lp + 1; + localparam l2s_dev_base_id_lp = clint_dev_id_lp + 1; + localparam loopback_dev_id_lp = l2s_dev_base_id_lp + l2_slices_p; + localparam num_dev_lp = loopback_dev_id_lp + 1; + localparam lg_num_dev_lp = `BSG_SAFE_CLOG2(num_dev_lp); + + // {CCE} + bp_bedrock_mem_fwd_header_s [num_proc_lp-1:0] proc_fwd_header_lo; + logic [num_proc_lp-1:0][bedrock_fill_width_p-1:0] proc_fwd_data_lo; + logic [num_proc_lp-1:0] proc_fwd_v_lo, proc_fwd_ready_and_li; + bp_bedrock_mem_rev_header_s [num_proc_lp-1:0] proc_rev_header_li; + logic [num_proc_lp-1:0][bedrock_fill_width_p-1:0] proc_rev_data_li; + logic [num_proc_lp-1:0] proc_rev_v_li, proc_rev_ready_and_lo; + + // Device-side CCE-Mem network connections + // {LOOPBACK, L2, CLINT, CFG} + bp_bedrock_mem_fwd_header_s [num_dev_lp-1:0] dev_fwd_header_li; + logic [num_dev_lp-1:0][bedrock_fill_width_p-1:0] dev_fwd_data_li; + logic [num_dev_lp-1:0] dev_fwd_v_li, dev_fwd_ready_and_lo; + bp_bedrock_mem_rev_header_s [num_dev_lp-1:0] dev_rev_header_lo; + logic [num_dev_lp-1:0][bedrock_fill_width_p-1:0] dev_rev_data_lo; + logic [num_dev_lp-1:0] dev_rev_v_lo, dev_rev_ready_and_li; + + bp_cfg_bus_s cfg_bus_lo; + logic debug_irq_li, timer_irq_li, software_irq_li, m_external_irq_li, s_external_irq_li; + bp_core_lite + #(.bp_params_p(bp_params_p)) + core_lite + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_lo) + + ,.lce_req_header_o(lce_req_header_o) + ,.lce_req_data_o(lce_req_data_o) + ,.lce_req_v_o(lce_req_v_o) + ,.lce_req_ready_and_i(lce_req_ready_and_i) + + ,.lce_cmd_header_i(lce_cmd_header_i) + ,.lce_cmd_data_i(lce_cmd_data_i) + ,.lce_cmd_v_i(lce_cmd_v_i) + ,.lce_cmd_ready_and_o(lce_cmd_ready_and_o) + + ,.lce_resp_header_o(lce_resp_header_o) + ,.lce_resp_data_o(lce_resp_data_o) + ,.lce_resp_v_o(lce_resp_v_o) + ,.lce_resp_ready_and_i(lce_resp_ready_and_i) + + ,.lce_fill_header_i(lce_fill_header_i) + ,.lce_fill_data_i(lce_fill_data_i) + ,.lce_fill_v_i(lce_fill_v_i) + ,.lce_fill_ready_and_o(lce_fill_ready_and_o) + + ,.lce_fill_header_o(lce_fill_header_o) + ,.lce_fill_data_o(lce_fill_data_o) + ,.lce_fill_v_o(lce_fill_v_o) + ,.lce_fill_ready_and_i(lce_fill_ready_and_i) + + ,.debug_irq_i(debug_irq_li) + ,.timer_irq_i(timer_irq_li) + ,.software_irq_i(software_irq_li) + ,.m_external_irq_i(m_external_irq_li) + ,.s_external_irq_i(s_external_irq_li) + ); + + // CCE drives all local memory requests + assign proc_fwd_header_lo[cce_proc_id_lp] = mem_fwd_header_i; + assign proc_fwd_data_lo[cce_proc_id_lp] = mem_fwd_data_i; + assign proc_fwd_v_lo[cce_proc_id_lp] = mem_fwd_v_i; + assign mem_fwd_ready_and_o = proc_fwd_ready_and_li[cce_proc_id_lp]; + + assign mem_rev_header_o = proc_rev_header_li[cce_proc_id_lp]; + assign mem_rev_data_o = proc_rev_data_li[cce_proc_id_lp]; + assign mem_rev_v_o = proc_rev_v_li[cce_proc_id_lp]; + assign proc_rev_ready_and_lo[cce_proc_id_lp] = mem_rev_ready_and_i; + + // Select destination of CCE-Mem command from CCE + logic [num_proc_lp-1:0][lg_num_dev_lp-1:0] proc_fwd_dst_lo; + for (genvar i = 0; i < num_proc_lp; i++) + begin : fwd_dest + bp_local_addr_s local_addr; + assign local_addr = proc_fwd_header_lo[i].addr; + wire [dev_id_width_gp-1:0] device_fwd_li = local_addr.dev; + wire is_local = (local_addr < dram_base_addr_gp); + + wire is_cfg_fwd = is_local & (device_fwd_li == cfg_dev_gp); + wire is_clint_fwd = is_local & (device_fwd_li == clint_dev_gp); + + wire is_l2s_fwd = ~is_local; + wire is_loopback_fwd = is_local & ~is_cfg_fwd & ~is_clint_fwd & ~is_l2s_fwd; + + localparam lg_l2_slices_lp = `BSG_SAFE_CLOG2(l2_slices_p); + logic [lg_l2_slices_lp-1:0] slice_id; + bp_me_dram_hash_encode + #(.bp_params_p(bp_params_p)) + slice_select + (.paddr_i(local_addr) + ,.data_i() + + ,.dram_o() + ,.daddr_o() + ,.slice_o(slice_id) + ,.bank_o() + ,.data_o() + ); + + logic [l2_slices_p-1:0] is_l2s_slice_fwd; + bsg_decode_with_v + #(.num_out_p(l2_slices_p)) + slice_decode + (.i(slice_id) + ,.v_i(is_l2s_fwd) + ,.o(is_l2s_slice_fwd) + ); + + wire [num_dev_lp-1:0] proc_fwd_dst_sel = + (is_cfg_fwd << cfg_dev_id_lp) + | (is_clint_fwd << clint_dev_id_lp) + | (is_l2s_slice_fwd << l2s_dev_base_id_lp) + | (is_loopback_fwd << loopback_dev_id_lp); + + bsg_encode_one_hot + #(.width_p(num_dev_lp), .lo_to_hi_p(1)) + fwd_pe + (.i(proc_fwd_dst_sel) + ,.addr_o(proc_fwd_dst_lo[i]) + ,.v_o() + ); + end + + bp_me_xbar_stream + #(.bp_params_p(bp_params_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.stream_mask_p(mem_fwd_stream_mask_gp) + ,.num_source_p(num_proc_lp) + ,.num_sink_p(num_dev_lp) + ) + fwd_xbar + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(proc_fwd_header_lo) + ,.msg_data_i(proc_fwd_data_lo) + ,.msg_v_i(proc_fwd_v_lo) + ,.msg_ready_and_o(proc_fwd_ready_and_li) + ,.msg_dst_i(proc_fwd_dst_lo) + + ,.msg_header_o(dev_fwd_header_li) + ,.msg_data_o(dev_fwd_data_li) + ,.msg_v_o(dev_fwd_v_li) + ,.msg_ready_and_i(dev_fwd_ready_and_lo) + ); + + // All CCE-Mem network responses go to the CCE on this tile (id = 0 in xbar) + wire [num_dev_lp-1:0][lg_num_proc_lp-1:0] dev_rev_dst_lo = '0; + bp_me_xbar_stream + #(.bp_params_p(bp_params_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.stream_mask_p(mem_rev_stream_mask_gp) + ,.num_source_p(num_dev_lp) + ,.num_sink_p(num_proc_lp) + ) + rev_xbar + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(dev_rev_header_lo) + ,.msg_data_i(dev_rev_data_lo) + ,.msg_v_i(dev_rev_v_lo) + ,.msg_ready_and_o(dev_rev_ready_and_li) + ,.msg_dst_i(dev_rev_dst_lo) + + ,.msg_header_o(proc_rev_header_li) + ,.msg_data_o(proc_rev_data_li) + ,.msg_v_o(proc_rev_v_li) + ,.msg_ready_and_i(proc_rev_ready_and_lo) + ); + + // Config + bp_me_cfg_slice + #(.bp_params_p(bp_params_p)) + cfg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.mem_fwd_header_i(dev_fwd_header_li[cfg_dev_id_lp]) + ,.mem_fwd_data_i(dev_fwd_data_li[cfg_dev_id_lp]) + ,.mem_fwd_v_i(dev_fwd_v_li[cfg_dev_id_lp]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[cfg_dev_id_lp]) + + ,.mem_rev_header_o(dev_rev_header_lo[cfg_dev_id_lp]) + ,.mem_rev_data_o(dev_rev_data_lo[cfg_dev_id_lp]) + ,.mem_rev_v_o(dev_rev_v_lo[cfg_dev_id_lp]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[cfg_dev_id_lp]) + + ,.cfg_bus_o(cfg_bus_lo) + ,.did_i(my_did_i) + ,.host_did_i(host_did_i) + ,.cord_i(my_cord_i) + + ,.cce_ucode_v_o(cce_ucode_v_o) + ,.cce_ucode_w_o(cce_ucode_w_o) + ,.cce_ucode_addr_o(cce_ucode_addr_o) + ,.cce_ucode_data_o(cce_ucode_data_o) + ,.cce_ucode_data_i(cce_ucode_data_i) + ); + assign cfg_bus_o = cfg_bus_lo; + + + // CLINT + bp_me_clint_slice + #(.bp_params_p(bp_params_p)) + clint + (.clk_i(clk_i) + ,.rt_clk_i(rt_clk_i) + ,.reset_i(reset_i) + ,.cfg_bus_i(cfg_bus_lo) + + ,.mem_fwd_header_i(dev_fwd_header_li[clint_dev_id_lp]) + ,.mem_fwd_data_i(dev_fwd_data_li[clint_dev_id_lp]) + ,.mem_fwd_v_i(dev_fwd_v_li[clint_dev_id_lp]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[clint_dev_id_lp]) + + ,.mem_rev_header_o(dev_rev_header_lo[clint_dev_id_lp]) + ,.mem_rev_data_o(dev_rev_data_lo[clint_dev_id_lp]) + ,.mem_rev_v_o(dev_rev_v_lo[clint_dev_id_lp]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[clint_dev_id_lp]) + + ,.debug_irq_o(debug_irq_li) + ,.timer_irq_o(timer_irq_li) + ,.software_irq_o(software_irq_li) + ,.m_external_irq_o(m_external_irq_li) + ,.s_external_irq_o(s_external_irq_li) + ); + + // CCE-Mem network to L2 Cache adapter + for (genvar i = 0; i < l2_slices_p; i++) + begin : slices + bp_me_cache_slice + #(.bp_params_p(bp_params_p)) + l2s + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.mem_fwd_header_i(dev_fwd_header_li[l2s_dev_base_id_lp+i]) + ,.mem_fwd_data_i(dev_fwd_data_li[l2s_dev_base_id_lp+i]) + ,.mem_fwd_v_i(dev_fwd_v_li[l2s_dev_base_id_lp+i]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[l2s_dev_base_id_lp+i]) + + ,.mem_rev_header_o(dev_rev_header_lo[l2s_dev_base_id_lp+i]) + ,.mem_rev_data_o(dev_rev_data_lo[l2s_dev_base_id_lp+i]) + ,.mem_rev_v_o(dev_rev_v_lo[l2s_dev_base_id_lp+i]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[l2s_dev_base_id_lp+i]) + + ,.dma_pkt_o(dma_pkt_o[i]) + ,.dma_pkt_v_o(dma_pkt_v_o[i]) + ,.dma_pkt_ready_and_i(dma_pkt_ready_and_i[i]) + + ,.dma_data_i(dma_data_i[i]) + ,.dma_data_v_i(dma_data_v_i[i]) + ,.dma_data_ready_and_o(dma_data_ready_and_o[i]) + + ,.dma_data_o(dma_data_o[i]) + ,.dma_data_v_o(dma_data_v_o[i]) + ,.dma_data_ready_and_i(dma_data_ready_and_i[i]) + ); + end + + // Loopback + bp_me_loopback + #(.bp_params_p(bp_params_p)) + loopback + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.mem_fwd_header_i(dev_fwd_header_li[loopback_dev_id_lp]) + ,.mem_fwd_data_i(dev_fwd_data_li[loopback_dev_id_lp]) + ,.mem_fwd_v_i(dev_fwd_v_li[loopback_dev_id_lp]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[loopback_dev_id_lp]) + + ,.mem_rev_header_o(dev_rev_header_lo[loopback_dev_id_lp]) + ,.mem_rev_data_o(dev_rev_data_lo[loopback_dev_id_lp]) + ,.mem_rev_v_o(dev_rev_v_lo[loopback_dev_id_lp]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[loopback_dev_id_lp]) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_core_complex.sv b/designs/black-parrot/src/bp/bp_core_complex.sv new file mode 100644 index 0000000..f91d260 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_core_complex.sv @@ -0,0 +1,228 @@ +/** + * + * bp_core_complex.v + * + */ + +`include "bsg_noc_links.svh" + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_core_complex + import bp_common_pkg::*; + import bp_be_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + ) + (input core_clk_i + , input rt_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input dma_clk_i + , input dma_reset_i + + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + + , input [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_hor_link_i + , output logic [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_hor_link_o + + , input [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_hor_link_i + , output logic [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_hor_link_o + + , input [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_hor_link_i + , output logic [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_hor_link_o + + , input [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_hor_link_i + , output logic [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_hor_link_o + + , input [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_ver_link_i + , output logic [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_ver_link_o + + , input [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_ver_link_i + , output logic [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_ver_link_o + + , input [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_ver_link_i + , output logic [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_ver_link_o + + , input [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_ver_link_i + , output logic [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_ver_link_o + + , input [S:N][cc_x_dim_p-1:0][dma_noc_ral_link_width_lp-1:0] dma_link_i + , output logic [S:N][cc_x_dim_p-1:0][dma_noc_ral_link_width_lp-1:0] dma_link_o + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, coh_noc_ral_link_s); + `declare_bsg_ready_and_link_sif_s(dma_noc_flit_width_p, dma_noc_ral_link_s); + + coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] lce_req_link_lo, lce_req_link_li; + coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] lce_cmd_link_lo, lce_cmd_link_li; + coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] lce_fill_link_lo, lce_fill_link_li; + coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] lce_resp_link_lo, lce_resp_link_li; + + dma_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:N] dma_link_lo, dma_link_li; + + coh_noc_ral_link_s [E:W][cc_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; + coh_noc_ral_link_s [S:N][cc_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo; + coh_noc_ral_link_s [E:W][cc_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; + coh_noc_ral_link_s [S:N][cc_x_dim_p-1:0] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; + coh_noc_ral_link_s [E:W][cc_y_dim_p-1:0] lce_fill_hor_link_li, lce_fill_hor_link_lo; + coh_noc_ral_link_s [S:N][cc_x_dim_p-1:0] lce_fill_ver_link_li, lce_fill_ver_link_lo; + coh_noc_ral_link_s [E:W][cc_y_dim_p-1:0] lce_resp_hor_link_li, lce_resp_hor_link_lo; + coh_noc_ral_link_s [S:N][cc_x_dim_p-1:0] lce_resp_ver_link_li, lce_resp_ver_link_lo; + + dma_noc_ral_link_s [S:N][cc_x_dim_p-1:0] mem_ver_link_lo, mem_ver_link_li; + + for (genvar j = 0; j < cc_y_dim_p; j++) + begin : y + for (genvar i = 0; i < cc_x_dim_p; i++) + begin : x + wire [coh_noc_cord_width_p-1:0] cord_li = {coh_noc_y_cord_width_p'(ic_y_dim_p+j) + ,coh_noc_x_cord_width_p'(sac_x_dim_p+i) + }; + bp_core_tile_node + #(.bp_params_p(bp_params_p)) + tile_node + (.core_clk_i(core_clk_i) + ,.rt_clk_i(rt_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.dma_clk_i(dma_clk_i) + ,.dma_reset_i(dma_reset_i) + + ,.my_did_i(my_did_i) + ,.host_did_i(host_did_i) + ,.my_cord_i(cord_li) + + ,.coh_lce_req_link_i(lce_req_link_li[j][i]) + ,.coh_lce_resp_link_i(lce_resp_link_li[j][i]) + ,.coh_lce_cmd_link_i(lce_cmd_link_li[j][i]) + ,.coh_lce_fill_link_i(lce_fill_link_li[j][i]) + + ,.coh_lce_req_link_o(lce_req_link_lo[j][i]) + ,.coh_lce_resp_link_o(lce_resp_link_lo[j][i]) + ,.coh_lce_cmd_link_o(lce_cmd_link_lo[j][i]) + ,.coh_lce_fill_link_o(lce_fill_link_lo[j][i]) + + ,.dma_link_i(dma_link_li[j][i]) + ,.dma_link_o(dma_link_lo[j][i]) + ); + end + end + + assign lce_req_hor_link_li = coh_req_hor_link_i; + assign lce_req_ver_link_li = coh_req_ver_link_i; + bsg_mesh_stitch + #(.width_p($bits(coh_noc_ral_link_s)) + ,.x_max_p(cc_x_dim_p) + ,.y_max_p(cc_y_dim_p) + ) + coh_req_mesh + (.outs_i(lce_req_link_lo) + ,.ins_o(lce_req_link_li) + + ,.hor_i(lce_req_hor_link_li) + ,.hor_o(lce_req_hor_link_lo) + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); + assign coh_req_hor_link_o = lce_req_hor_link_lo; + assign coh_req_ver_link_o = lce_req_ver_link_lo; + + assign lce_cmd_hor_link_li = coh_cmd_hor_link_i; + assign lce_cmd_ver_link_li = coh_cmd_ver_link_i; + bsg_mesh_stitch + #(.width_p($bits(coh_noc_ral_link_s)) + ,.x_max_p(cc_x_dim_p) + ,.y_max_p(cc_y_dim_p) + ) + coh_cmd_mesh + (.outs_i(lce_cmd_link_lo) + ,.ins_o(lce_cmd_link_li) + + ,.hor_i(lce_cmd_hor_link_li) + ,.hor_o(lce_cmd_hor_link_lo) + ,.ver_i(lce_cmd_ver_link_li) + ,.ver_o(lce_cmd_ver_link_lo) + ); + assign coh_cmd_hor_link_o = lce_cmd_hor_link_lo; + assign coh_cmd_ver_link_o = lce_cmd_ver_link_lo; + + assign lce_fill_hor_link_li = coh_fill_hor_link_i; + assign lce_fill_ver_link_li = coh_fill_ver_link_i; + bsg_mesh_stitch + #(.width_p($bits(coh_noc_ral_link_s)) + ,.x_max_p(cc_x_dim_p) + ,.y_max_p(cc_y_dim_p) + ) + coh_fill_mesh + (.outs_i(lce_fill_link_lo) + ,.ins_o(lce_fill_link_li) + + ,.hor_i(lce_fill_hor_link_li) + ,.hor_o(lce_fill_hor_link_lo) + ,.ver_i(lce_fill_ver_link_li) + ,.ver_o(lce_fill_ver_link_lo) + ); + assign coh_fill_hor_link_o = lce_fill_hor_link_lo; + assign coh_fill_ver_link_o = lce_fill_ver_link_lo; + + assign lce_resp_hor_link_li = coh_resp_hor_link_i; + assign lce_resp_ver_link_li = coh_resp_ver_link_i; + bsg_mesh_stitch + #(.width_p($bits(coh_noc_ral_link_s)) + ,.x_max_p(cc_x_dim_p) + ,.y_max_p(cc_y_dim_p) + ) + coh_resp_mesh + (.outs_i(lce_resp_link_lo) + ,.ins_o(lce_resp_link_li) + + ,.hor_i(lce_resp_hor_link_li) + ,.hor_o(lce_resp_hor_link_lo) + ,.ver_i(lce_resp_ver_link_li) + ,.ver_o(lce_resp_ver_link_lo) + ); + assign coh_resp_hor_link_o = lce_resp_hor_link_lo; + assign coh_resp_ver_link_o = lce_resp_ver_link_lo; + + dma_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] mem_mesh_lo, mem_mesh_li; + for (genvar i = 0; i < cc_y_dim_p; i++) + for (genvar j = 0; j < cc_x_dim_p; j++) + begin : link + assign mem_mesh_lo[i][j][S:N] = dma_link_lo[i][j][S:N]; + assign dma_link_li[i][j][S:N] = mem_mesh_li[i][j][S:N]; + end + assign mem_ver_link_li = dma_link_i; + bsg_mesh_stitch + #(.width_p($bits(dma_noc_ral_link_s)) + ,.x_max_p(cc_x_dim_p) + ,.y_max_p(cc_y_dim_p) + ) + mem_mesh + (.outs_i(mem_mesh_lo) + ,.ins_o(mem_mesh_li) + + ,.hor_i() + ,.hor_o() + ,.ver_i(mem_ver_link_li) + ,.ver_o(mem_ver_link_lo) + ); + assign dma_link_o = mem_ver_link_lo; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_core_lite.sv b/designs/black-parrot/src/bp/bp_core_lite.sv new file mode 100644 index 0000000..a224251 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_core_lite.sv @@ -0,0 +1,391 @@ +/** + * bp_core_lite.v + * + * icache is connected to 0. + * dcache is connected to 1. + */ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" +`include "bp_be_defines.svh" +`include "bp_top_defines.svh" + +module bp_core_lite + import bp_common_pkg::*; + import bp_fe_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + `declare_bp_fe_icache_engine_if_widths(paddr_width_p, icache_tag_width_p, icache_sets_p, icache_assoc_p, icache_data_width_p, icache_block_width_p, icache_fill_width_p, icache_req_id_width_p) + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, dcache_tag_width_p, dcache_sets_p, dcache_assoc_p, dcache_data_width_p, dcache_block_width_p, dcache_fill_width_p, dcache_req_id_width_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , output logic [1:0][lce_req_header_width_lp-1:0] lce_req_header_o + , output logic [1:0][icache_fill_width_p-1:0] lce_req_data_o + , output logic [1:0] lce_req_v_o + , input [1:0] lce_req_ready_and_i + + , input [1:0][lce_cmd_header_width_lp-1:0] lce_cmd_header_i + , input [1:0][icache_fill_width_p-1:0] lce_cmd_data_i + , input [1:0] lce_cmd_v_i + , output logic [1:0] lce_cmd_ready_and_o + + , input [1:0][lce_fill_header_width_lp-1:0] lce_fill_header_i + , input [1:0][icache_fill_width_p-1:0] lce_fill_data_i + , input [1:0] lce_fill_v_i + , output logic [1:0] lce_fill_ready_and_o + + , output logic [1:0][lce_fill_header_width_lp-1:0] lce_fill_header_o + , output logic [1:0][icache_fill_width_p-1:0] lce_fill_data_o + , output logic [1:0] lce_fill_v_o + , input [1:0] lce_fill_ready_and_i + + , output logic [1:0][lce_resp_header_width_lp-1:0] lce_resp_header_o + , output logic [1:0][icache_fill_width_p-1:0] lce_resp_data_o + , output logic [1:0] lce_resp_v_o + , input [1:0] lce_resp_ready_and_i + + , input debug_irq_i + , input timer_irq_i + , input software_irq_i + , input m_external_irq_i + , input s_external_irq_i + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_fe_icache_engine_if(paddr_width_p, icache_tag_width_p, icache_sets_p, icache_assoc_p, icache_data_width_p, icache_block_width_p, icache_fill_width_p, icache_req_id_width_p); + `declare_bp_be_dcache_engine_if(paddr_width_p, dcache_tag_width_p, dcache_sets_p, dcache_assoc_p, dcache_data_width_p, dcache_block_width_p, dcache_fill_width_p, dcache_req_id_width_p); + + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + + bp_fe_icache_req_s icache_req_lo; + logic icache_req_v_lo, icache_req_yumi_li, icache_req_lock_li; + bp_fe_icache_req_metadata_s icache_req_metadata_lo; + logic icache_req_metadata_v_lo; + logic [icache_req_id_width_p-1:0] icache_req_id_li; + logic icache_req_critical_li, icache_req_last_li; + logic icache_req_credits_full_li, icache_req_credits_empty_li; + + bp_be_dcache_req_s dcache_req_lo; + logic dcache_req_v_lo, dcache_req_yumi_li, dcache_req_lock_li; + bp_be_dcache_req_metadata_s dcache_req_metadata_lo; + logic dcache_req_metadata_v_lo; + logic [dcache_req_id_width_p-1:0] dcache_req_id_li; + logic dcache_req_critical_li, dcache_req_last_li; + logic dcache_req_credits_full_li, dcache_req_credits_empty_li; + + bp_fe_icache_tag_mem_pkt_s icache_tag_mem_pkt_li; + logic icache_tag_mem_pkt_v_li; + logic icache_tag_mem_pkt_yumi_lo; + bp_fe_icache_tag_info_s icache_tag_mem_lo; + + bp_fe_icache_data_mem_pkt_s icache_data_mem_pkt_li; + logic icache_data_mem_pkt_v_li; + logic icache_data_mem_pkt_yumi_lo; + logic [icache_block_width_p-1:0] icache_data_mem_lo; + + bp_fe_icache_stat_mem_pkt_s icache_stat_mem_pkt_li; + logic icache_stat_mem_pkt_v_li; + logic icache_stat_mem_pkt_yumi_lo; + bp_fe_icache_stat_info_s icache_stat_mem_lo; + + bp_be_dcache_tag_mem_pkt_s dcache_tag_mem_pkt_li; + logic dcache_tag_mem_pkt_v_li; + logic dcache_tag_mem_pkt_yumi_lo; + bp_be_dcache_tag_info_s dcache_tag_mem_lo; + + bp_be_dcache_data_mem_pkt_s dcache_data_mem_pkt_li; + logic dcache_data_mem_pkt_v_li; + logic dcache_data_mem_pkt_yumi_lo; + logic [dcache_block_width_p-1:0] dcache_data_mem_lo; + + bp_be_dcache_stat_mem_pkt_s dcache_stat_mem_pkt_li; + logic dcache_stat_mem_pkt_v_li; + logic dcache_stat_mem_pkt_yumi_lo; + bp_be_dcache_stat_info_s dcache_stat_mem_lo; + + wire posedge_clk = clk_i; + wire negedge_clk = ~clk_i; + + bp_core_minimal + #(.bp_params_p(bp_params_p)) + core_minimal + (.clk_i(posedge_clk) + ,.reset_i(reset_i) + ,.cfg_bus_i(cfg_bus_cast_i) + + ,.icache_req_o(icache_req_lo) + ,.icache_req_v_o(icache_req_v_lo) + ,.icache_req_yumi_i(icache_req_yumi_li) + ,.icache_req_lock_i(icache_req_lock_li) + ,.icache_req_metadata_o(icache_req_metadata_lo) + ,.icache_req_metadata_v_o(icache_req_metadata_v_lo) + ,.icache_req_id_i(icache_req_id_li) + ,.icache_req_critical_i(icache_req_critical_li) + ,.icache_req_last_i(icache_req_last_li) + ,.icache_req_credits_full_i(icache_req_credits_full_li) + ,.icache_req_credits_empty_i(icache_req_credits_empty_li) + + ,.icache_tag_mem_pkt_i(icache_tag_mem_pkt_li) + ,.icache_tag_mem_pkt_v_i(icache_tag_mem_pkt_v_li) + ,.icache_tag_mem_pkt_yumi_o(icache_tag_mem_pkt_yumi_lo) + ,.icache_tag_mem_o(icache_tag_mem_lo) + + ,.icache_data_mem_pkt_i(icache_data_mem_pkt_li) + ,.icache_data_mem_pkt_v_i(icache_data_mem_pkt_v_li) + ,.icache_data_mem_pkt_yumi_o(icache_data_mem_pkt_yumi_lo) + ,.icache_data_mem_o(icache_data_mem_lo) + + ,.icache_stat_mem_pkt_v_i(icache_stat_mem_pkt_v_li) + ,.icache_stat_mem_pkt_i(icache_stat_mem_pkt_li) + ,.icache_stat_mem_pkt_yumi_o(icache_stat_mem_pkt_yumi_lo) + ,.icache_stat_mem_o(icache_stat_mem_lo) + + ,.dcache_req_o(dcache_req_lo) + ,.dcache_req_v_o(dcache_req_v_lo) + ,.dcache_req_yumi_i(dcache_req_yumi_li) + ,.dcache_req_lock_i(dcache_req_lock_li) + ,.dcache_req_metadata_o(dcache_req_metadata_lo) + ,.dcache_req_metadata_v_o(dcache_req_metadata_v_lo) + ,.dcache_req_id_i(dcache_req_id_li) + ,.dcache_req_critical_i(dcache_req_critical_li) + ,.dcache_req_last_i(dcache_req_last_li) + ,.dcache_req_credits_full_i(dcache_req_credits_full_li) + ,.dcache_req_credits_empty_i(dcache_req_credits_empty_li) + + ,.dcache_tag_mem_pkt_i(dcache_tag_mem_pkt_li) + ,.dcache_tag_mem_pkt_v_i(dcache_tag_mem_pkt_v_li) + ,.dcache_tag_mem_pkt_yumi_o(dcache_tag_mem_pkt_yumi_lo) + ,.dcache_tag_mem_o(dcache_tag_mem_lo) + + ,.dcache_data_mem_pkt_i(dcache_data_mem_pkt_li) + ,.dcache_data_mem_pkt_v_i(dcache_data_mem_pkt_v_li) + ,.dcache_data_mem_pkt_yumi_o(dcache_data_mem_pkt_yumi_lo) + ,.dcache_data_mem_o(dcache_data_mem_lo) + + ,.dcache_stat_mem_pkt_v_i(dcache_stat_mem_pkt_v_li) + ,.dcache_stat_mem_pkt_i(dcache_stat_mem_pkt_li) + ,.dcache_stat_mem_pkt_yumi_o(dcache_stat_mem_pkt_yumi_lo) + ,.dcache_stat_mem_o(dcache_stat_mem_lo) + + ,.debug_irq_i(debug_irq_i) + ,.timer_irq_i(timer_irq_i) + ,.software_irq_i(software_irq_i) + ,.m_external_irq_i(m_external_irq_i) + ,.s_external_irq_i(s_external_irq_i) + ); + + bp_lce + #(.bp_params_p(bp_params_p) + ,.assoc_p(icache_assoc_p) + ,.sets_p(icache_sets_p) + ,.block_width_p(icache_block_width_p) + ,.fill_width_p(icache_fill_width_p) + ,.data_width_p(icache_data_width_p) + ,.tag_width_p(icache_tag_width_p) + ,.id_width_p(icache_req_id_width_p) + ,.timeout_max_limit_p(4) + ,.credits_p(coh_noc_max_credits_p) + ,.non_excl_reads_p(1) + ) + fe_lce + (.clk_i(posedge_clk) + ,.reset_i(reset_i) + + ,.did_i(cfg_bus_cast_i.did) + ,.lce_id_i(cfg_bus_cast_i.icache_id) + ,.lce_mode_i(cfg_bus_cast_i.icache_mode) + + ,.cache_req_i(icache_req_lo) + ,.cache_req_v_i(icache_req_v_lo) + ,.cache_req_yumi_o(icache_req_yumi_li) + ,.cache_req_lock_o(icache_req_lock_li) + ,.cache_req_metadata_i(icache_req_metadata_lo) + ,.cache_req_metadata_v_i(icache_req_metadata_v_lo) + ,.cache_req_id_o(icache_req_id_li) + ,.cache_req_critical_o(icache_req_critical_li) + ,.cache_req_last_o(icache_req_last_li) + ,.cache_req_credits_full_o(icache_req_credits_full_li) + ,.cache_req_credits_empty_o(icache_req_credits_empty_li) + + ,.tag_mem_pkt_o(icache_tag_mem_pkt_li) + ,.tag_mem_pkt_v_o(icache_tag_mem_pkt_v_li) + ,.tag_mem_pkt_yumi_i(icache_tag_mem_pkt_yumi_lo) + ,.tag_mem_i(icache_tag_mem_lo) + + ,.data_mem_pkt_o(icache_data_mem_pkt_li) + ,.data_mem_pkt_v_o(icache_data_mem_pkt_v_li) + ,.data_mem_pkt_yumi_i(icache_data_mem_pkt_yumi_lo) + ,.data_mem_i(icache_data_mem_lo) + + ,.stat_mem_pkt_v_o(icache_stat_mem_pkt_v_li) + ,.stat_mem_pkt_o(icache_stat_mem_pkt_li) + ,.stat_mem_pkt_yumi_i(icache_stat_mem_pkt_yumi_lo) + ,.stat_mem_i(icache_stat_mem_lo) + + ,.lce_req_header_o(lce_req_header_o[0]) + ,.lce_req_data_o(lce_req_data_o[0]) + ,.lce_req_v_o(lce_req_v_o[0]) + ,.lce_req_ready_and_i(lce_req_ready_and_i[0]) + + ,.lce_cmd_header_i(lce_cmd_header_i[0]) + ,.lce_cmd_data_i(lce_cmd_data_i[0]) + ,.lce_cmd_v_i(lce_cmd_v_i[0]) + ,.lce_cmd_ready_and_o(lce_cmd_ready_and_o[0]) + + ,.lce_fill_header_i(lce_fill_header_i[0]) + ,.lce_fill_data_i(lce_fill_data_i[0]) + ,.lce_fill_v_i(lce_fill_v_i[0]) + ,.lce_fill_ready_and_o(lce_fill_ready_and_o[0]) + + ,.lce_fill_header_o(lce_fill_header_o[0]) + ,.lce_fill_data_o(lce_fill_data_o[0]) + ,.lce_fill_v_o(lce_fill_v_o[0]) + ,.lce_fill_ready_and_i(lce_fill_ready_and_i[0]) + + ,.lce_resp_header_o(lce_resp_header_o[0]) + ,.lce_resp_data_o(lce_resp_data_o[0]) + ,.lce_resp_v_o(lce_resp_v_o[0]) + ,.lce_resp_ready_and_i(lce_resp_ready_and_i[0]) + ); + + logic [1:1][lce_req_header_width_lp-1:0] _lce_req_header_o; + logic [1:1][icache_fill_width_p-1:0] _lce_req_data_o; + logic [1:1] _lce_req_v_o; + logic [1:1] _lce_req_ready_and_i; + + logic [1:1][lce_cmd_header_width_lp-1:0] _lce_cmd_header_i; + logic [1:1][icache_fill_width_p-1:0] _lce_cmd_data_i; + logic [1:1] _lce_cmd_v_i; + logic [1:1] _lce_cmd_ready_and_o; + + logic [1:1][lce_fill_header_width_lp-1:0] _lce_fill_header_i; + logic [1:1][icache_fill_width_p-1:0] _lce_fill_data_i; + logic [1:1] _lce_fill_v_i; + logic [1:1] _lce_fill_ready_and_o; + + logic [1:1][lce_fill_header_width_lp-1:0] _lce_fill_header_o; + logic [1:1][icache_fill_width_p-1:0] _lce_fill_data_o; + logic [1:1] _lce_fill_v_o; + logic [1:1] _lce_fill_ready_and_i; + + logic [1:1][lce_resp_header_width_lp-1:0] _lce_resp_header_o; + logic [1:1][icache_fill_width_p-1:0] _lce_resp_data_o; + logic [1:1] _lce_resp_v_o; + logic [1:1] _lce_resp_ready_and_i; + bp_lce + #(.bp_params_p(bp_params_p) + ,.assoc_p(dcache_assoc_p) + ,.sets_p(dcache_sets_p) + ,.block_width_p(dcache_block_width_p) + ,.fill_width_p(dcache_fill_width_p) + ,.data_width_p(dcache_data_width_p) + ,.tag_width_p(dcache_tag_width_p) + ,.id_width_p(dcache_req_id_width_p) + ,.timeout_max_limit_p(4) + ,.credits_p(coh_noc_max_credits_p) + ) + be_lce + (.clk_i(negedge_clk) + ,.reset_i(reset_i) + + ,.did_i(cfg_bus_cast_i.did) + ,.lce_id_i(cfg_bus_cast_i.dcache_id) + ,.lce_mode_i(cfg_bus_cast_i.dcache_mode) + + ,.cache_req_i(dcache_req_lo) + ,.cache_req_v_i(dcache_req_v_lo) + ,.cache_req_yumi_o(dcache_req_yumi_li) + ,.cache_req_lock_o(dcache_req_lock_li) + ,.cache_req_metadata_i(dcache_req_metadata_lo) + ,.cache_req_metadata_v_i(dcache_req_metadata_v_lo) + ,.cache_req_id_o(dcache_req_id_li) + ,.cache_req_critical_o(dcache_req_critical_li) + ,.cache_req_last_o(dcache_req_last_li) + ,.cache_req_credits_full_o(dcache_req_credits_full_li) + ,.cache_req_credits_empty_o(dcache_req_credits_empty_li) + + ,.tag_mem_pkt_o(dcache_tag_mem_pkt_li) + ,.tag_mem_pkt_v_o(dcache_tag_mem_pkt_v_li) + ,.tag_mem_pkt_yumi_i(dcache_tag_mem_pkt_yumi_lo) + ,.tag_mem_i(dcache_tag_mem_lo) + + ,.data_mem_pkt_o(dcache_data_mem_pkt_li) + ,.data_mem_pkt_v_o(dcache_data_mem_pkt_v_li) + ,.data_mem_pkt_yumi_i(dcache_data_mem_pkt_yumi_lo) + ,.data_mem_i(dcache_data_mem_lo) + + ,.stat_mem_pkt_v_o(dcache_stat_mem_pkt_v_li) + ,.stat_mem_pkt_o(dcache_stat_mem_pkt_li) + ,.stat_mem_pkt_yumi_i(dcache_stat_mem_pkt_yumi_lo) + ,.stat_mem_i(dcache_stat_mem_lo) + + ,.lce_req_header_o(_lce_req_header_o[1]) + ,.lce_req_data_o(_lce_req_data_o[1]) + ,.lce_req_v_o(_lce_req_v_o[1]) + ,.lce_req_ready_and_i(_lce_req_ready_and_i[1]) + + ,.lce_cmd_header_i(_lce_cmd_header_i[1]) + ,.lce_cmd_data_i(_lce_cmd_data_i[1]) + ,.lce_cmd_v_i(_lce_cmd_v_i[1]) + ,.lce_cmd_ready_and_o(_lce_cmd_ready_and_o[1]) + + ,.lce_fill_header_i(_lce_fill_header_i[1]) + ,.lce_fill_data_i(_lce_fill_data_i[1]) + ,.lce_fill_v_i(_lce_fill_v_i[1]) + ,.lce_fill_ready_and_o(_lce_fill_ready_and_o[1]) + + ,.lce_fill_header_o(_lce_fill_header_o[1]) + ,.lce_fill_data_o(_lce_fill_data_o[1]) + ,.lce_fill_v_o(_lce_fill_v_o[1]) + ,.lce_fill_ready_and_i(_lce_fill_ready_and_i[1]) + + ,.lce_resp_header_o(_lce_resp_header_o[1]) + ,.lce_resp_data_o(_lce_resp_data_o[1]) + ,.lce_resp_v_o(_lce_resp_v_o[1]) + ,.lce_resp_ready_and_i(_lce_resp_ready_and_i[1]) + ); + + bsg_dlatch + #(.width_p($bits(bp_bedrock_lce_req_header_s)+$bits(bp_bedrock_lce_fill_header_s)+$bits(bp_bedrock_lce_resp_header_s)+3*dcache_fill_width_p+3*2), .i_know_this_is_a_bad_idea_p(1)) + posedge_latch + (.clk_i(posedge_clk) + ,.data_i({_lce_req_header_o[1], _lce_req_data_o[1], _lce_req_v_o[1] + ,_lce_fill_header_o[1], _lce_fill_data_o[1], _lce_fill_v_o[1] + ,_lce_resp_header_o[1], _lce_resp_data_o[1], _lce_resp_v_o[1] + ,lce_req_ready_and_i[1], lce_fill_ready_and_i[1], lce_resp_ready_and_i[1] + }) + ,.data_o({lce_req_header_o[1], lce_req_data_o[1], lce_req_v_o[1] + ,lce_fill_header_o[1], lce_fill_data_o[1], lce_fill_v_o[1] + ,lce_resp_header_o[1], lce_resp_data_o[1], lce_resp_v_o[1] + ,_lce_req_ready_and_i[1], _lce_fill_ready_and_i[1], _lce_resp_ready_and_i[1] + }) + ); + + bsg_dlatch + #(.width_p($bits(bp_bedrock_lce_cmd_header_s)+$bits(bp_bedrock_lce_fill_header_s)+2*dcache_fill_width_p+2*2), .i_know_this_is_a_bad_idea_p(1)) + negedge_latch + (.clk_i(negedge_clk) + ,.data_i({lce_cmd_header_i[1], lce_cmd_data_i[1], lce_cmd_v_i[1] + ,lce_fill_header_i[1], lce_fill_data_i[1], lce_fill_v_i[1] + ,_lce_cmd_ready_and_o[1], _lce_fill_ready_and_o[1] + }) + ,.data_o({_lce_cmd_header_i[1], _lce_cmd_data_i[1], _lce_cmd_v_i[1] + ,_lce_fill_header_i[1], _lce_fill_data_i[1], _lce_fill_v_i[1] + ,lce_cmd_ready_and_o[1], lce_fill_ready_and_o[1] + }) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_core_minimal.sv b/designs/black-parrot/src/bp/bp_core_minimal.sv new file mode 100644 index 0000000..cb3453c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_core_minimal.sv @@ -0,0 +1,194 @@ +/** + * bp_core_minimal.v + * + */ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" +`include "bp_be_defines.svh" +`include "bp_top_defines.svh" + +module bp_core_minimal + import bp_common_pkg::*; + import bp_fe_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_fe_icache_engine_if_widths(paddr_width_p, icache_tag_width_p, icache_sets_p, icache_assoc_p, icache_data_width_p, icache_block_width_p, icache_fill_width_p, icache_req_id_width_p) + `declare_bp_be_dcache_engine_if_widths(paddr_width_p, dcache_tag_width_p, dcache_sets_p, dcache_assoc_p, dcache_data_width_p, dcache_block_width_p, dcache_fill_width_p, dcache_req_id_width_p) + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + , output logic [icache_req_width_lp-1:0] icache_req_o + , output logic icache_req_v_o + , input icache_req_yumi_i + , input icache_req_lock_i + , output logic [icache_req_metadata_width_lp-1:0] icache_req_metadata_o + , output logic icache_req_metadata_v_o + , input [icache_req_id_width_p-1:0] icache_req_id_i + , input icache_req_critical_i + , input icache_req_last_i + , input icache_req_credits_full_i + , input icache_req_credits_empty_i + + , input [icache_tag_mem_pkt_width_lp-1:0] icache_tag_mem_pkt_i + , input icache_tag_mem_pkt_v_i + , output logic icache_tag_mem_pkt_yumi_o + , output logic [icache_tag_info_width_lp-1:0] icache_tag_mem_o + + , input [icache_data_mem_pkt_width_lp-1:0] icache_data_mem_pkt_i + , input icache_data_mem_pkt_v_i + , output logic icache_data_mem_pkt_yumi_o + , output logic [icache_block_width_p-1:0] icache_data_mem_o + + , input [icache_stat_mem_pkt_width_lp-1:0] icache_stat_mem_pkt_i + , input icache_stat_mem_pkt_v_i + , output logic icache_stat_mem_pkt_yumi_o + , output logic [icache_stat_info_width_lp-1:0] icache_stat_mem_o + + // D$ Engine Interface is clocked on the negedge of the clock. Must be attached to + // a negative-edge cache engine and synchronized before getting to the memory system + , output logic [dcache_req_width_lp-1:0] dcache_req_o + , output logic dcache_req_v_o + , input dcache_req_yumi_i + , input dcache_req_lock_i + , output logic [dcache_req_metadata_width_lp-1:0] dcache_req_metadata_o + , output logic dcache_req_metadata_v_o + , input [dcache_req_id_width_p-1:0] dcache_req_id_i + , input dcache_req_critical_i + , input dcache_req_last_i + , input dcache_req_credits_full_i + , input dcache_req_credits_empty_i + + , input [dcache_tag_mem_pkt_width_lp-1:0] dcache_tag_mem_pkt_i + , input dcache_tag_mem_pkt_v_i + , output logic dcache_tag_mem_pkt_yumi_o + , output logic [dcache_tag_info_width_lp-1:0] dcache_tag_mem_o + + , input [dcache_data_mem_pkt_width_lp-1:0] dcache_data_mem_pkt_i + , input dcache_data_mem_pkt_v_i + , output logic dcache_data_mem_pkt_yumi_o + , output logic [dcache_block_width_p-1:0] dcache_data_mem_o + + , input [dcache_stat_mem_pkt_width_lp-1:0] dcache_stat_mem_pkt_i + , input dcache_stat_mem_pkt_v_i + , output logic dcache_stat_mem_pkt_yumi_o + , output logic [dcache_stat_info_width_lp-1:0] dcache_stat_mem_o + + , input debug_irq_i + , input timer_irq_i + , input software_irq_i + , input m_external_irq_i + , input s_external_irq_i + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + + bp_fe_queue_s fe_queue_li, fe_queue_lo; + logic fe_queue_v_li, fe_queue_ready_and_lo; + bp_fe_cmd_s fe_cmd_lo; + logic fe_cmd_v_lo, fe_cmd_yumi_li; + + bp_fe_top + #(.bp_params_p(bp_params_p)) + fe + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_cast_i) + + ,.fe_queue_o(fe_queue_li) + ,.fe_queue_v_o(fe_queue_v_li) + ,.fe_queue_ready_and_i(fe_queue_ready_and_lo) + + ,.fe_cmd_i(fe_cmd_lo) + ,.fe_cmd_v_i(fe_cmd_v_lo) + ,.fe_cmd_yumi_o(fe_cmd_yumi_li) + + ,.cache_req_o(icache_req_o) + ,.cache_req_v_o(icache_req_v_o) + ,.cache_req_yumi_i(icache_req_yumi_i) + ,.cache_req_lock_i(icache_req_lock_i) + ,.cache_req_metadata_o(icache_req_metadata_o) + ,.cache_req_metadata_v_o(icache_req_metadata_v_o) + ,.cache_req_id_i(icache_req_id_i) + ,.cache_req_critical_i(icache_req_critical_i) + ,.cache_req_last_i(icache_req_last_i) + ,.cache_req_credits_full_i(icache_req_credits_full_i) + ,.cache_req_credits_empty_i(icache_req_credits_empty_i) + + ,.tag_mem_pkt_i(icache_tag_mem_pkt_i) + ,.tag_mem_pkt_v_i(icache_tag_mem_pkt_v_i) + ,.tag_mem_pkt_yumi_o(icache_tag_mem_pkt_yumi_o) + ,.tag_mem_o(icache_tag_mem_o) + + ,.data_mem_pkt_i(icache_data_mem_pkt_i) + ,.data_mem_pkt_v_i(icache_data_mem_pkt_v_i) + ,.data_mem_pkt_yumi_o(icache_data_mem_pkt_yumi_o) + ,.data_mem_o(icache_data_mem_o) + + ,.stat_mem_pkt_v_i(icache_stat_mem_pkt_v_i) + ,.stat_mem_pkt_i(icache_stat_mem_pkt_i) + ,.stat_mem_pkt_yumi_o(icache_stat_mem_pkt_yumi_o) + ,.stat_mem_o(icache_stat_mem_o) + ); + + bp_be_top + #(.bp_params_p(bp_params_p)) + be + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_cast_i) + + ,.fe_queue_i(fe_queue_li) + ,.fe_queue_v_i(fe_queue_v_li) + ,.fe_queue_ready_and_o(fe_queue_ready_and_lo) + + ,.fe_cmd_o(fe_cmd_lo) + ,.fe_cmd_v_o(fe_cmd_v_lo) + ,.fe_cmd_yumi_i(fe_cmd_yumi_li) + + ,.cache_req_o(dcache_req_o) + ,.cache_req_v_o(dcache_req_v_o) + ,.cache_req_yumi_i(dcache_req_yumi_i) + ,.cache_req_lock_i(dcache_req_lock_i) + ,.cache_req_metadata_o(dcache_req_metadata_o) + ,.cache_req_metadata_v_o(dcache_req_metadata_v_o) + ,.cache_req_id_i(dcache_req_id_i) + ,.cache_req_critical_i(dcache_req_critical_i) + ,.cache_req_last_i(dcache_req_last_i) + ,.cache_req_credits_full_i(dcache_req_credits_full_i) + ,.cache_req_credits_empty_i(dcache_req_credits_empty_i) + + ,.data_mem_pkt_i(dcache_data_mem_pkt_i) + ,.data_mem_pkt_v_i(dcache_data_mem_pkt_v_i) + ,.data_mem_pkt_yumi_o(dcache_data_mem_pkt_yumi_o) + ,.data_mem_o(dcache_data_mem_o) + + ,.tag_mem_pkt_i(dcache_tag_mem_pkt_i) + ,.tag_mem_pkt_v_i(dcache_tag_mem_pkt_v_i) + ,.tag_mem_pkt_yumi_o(dcache_tag_mem_pkt_yumi_o) + ,.tag_mem_o(dcache_tag_mem_o) + + ,.stat_mem_pkt_v_i(dcache_stat_mem_pkt_v_i) + ,.stat_mem_pkt_i(dcache_stat_mem_pkt_i) + ,.stat_mem_pkt_yumi_o(dcache_stat_mem_pkt_yumi_o) + ,.stat_mem_o(dcache_stat_mem_o) + + ,.debug_irq_i(debug_irq_i) + ,.timer_irq_i(timer_irq_i) + ,.software_irq_i(software_irq_i) + ,.m_external_irq_i(m_external_irq_i) + ,.s_external_irq_i(s_external_irq_i) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_core_tile.sv b/designs/black-parrot/src/bp/bp_core_tile.sv new file mode 100644 index 0000000..e90ec31 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_core_tile.sv @@ -0,0 +1,705 @@ +/** + * + * bp_core_tile.v + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" +`include "bsg_cache.svh" +`include "bsg_noc_links.svh" + +module bp_core_tile + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + import bp_top_pkg::*; + import bsg_cache_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + + // Wormhole parameters + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + ) + (input clk_i + , input rt_clk_i + , input reset_i + + // Memory side connection + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + + , input [coh_noc_ral_link_width_lp-1:0] lce_req_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_req_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_fill_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_fill_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_resp_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_resp_link_o + + , output logic [dma_noc_ral_link_width_lp-1:0] dma_link_o + , input [dma_noc_ral_link_width_lp-1:0] dma_link_i + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(dma_noc_flit_width_p, bp_dma_ready_and_link_s); + + // Reset + logic reset_r; + always_ff @(posedge clk_i) + reset_r <= reset_i; + + // LCE-CCE coherence network links + `bp_cast_i(bp_coh_ready_and_link_s, lce_req_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_req_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_cmd_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_cmd_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_fill_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_fill_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_resp_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_resp_link); + + // Core-side LCE-CCE network connections + bp_bedrock_lce_req_header_s [1:0] lce_req_header_lo; + logic [1:0][bedrock_fill_width_p-1:0] lce_req_data_lo; + logic [1:0] lce_req_v_lo, lce_req_ready_and_li; + logic [1:0][coh_noc_cord_width_p-1:0] lce_req_dst_cord_lo; + logic [1:0][coh_noc_cid_width_p-1:0] lce_req_dst_cid_lo; + + bp_bedrock_lce_cmd_header_s [1:0] lce_cmd_header_li; + logic [1:0][bedrock_fill_width_p-1:0] lce_cmd_data_li; + logic [1:0] lce_cmd_v_li, lce_cmd_ready_and_lo; + + bp_bedrock_lce_fill_header_s [1:0] lce_fill_header_li; + logic [1:0][bedrock_fill_width_p-1:0] lce_fill_data_li; + logic [1:0] lce_fill_v_li, lce_fill_ready_and_lo; + + bp_bedrock_lce_fill_header_s [1:0] lce_fill_header_lo; + logic [1:0][bedrock_fill_width_p-1:0] lce_fill_data_lo; + logic [1:0] lce_fill_v_lo, lce_fill_ready_and_li; + logic [1:0][coh_noc_cord_width_p-1:0] lce_fill_dst_cord_lo; + logic [1:0][coh_noc_cid_width_p-1:0] lce_fill_dst_cid_lo; + + bp_bedrock_lce_resp_header_s [1:0] lce_resp_header_lo; + logic [1:0][bedrock_fill_width_p-1:0] lce_resp_data_lo; + logic [1:0] lce_resp_v_lo, lce_resp_ready_and_li; + logic [1:0][coh_noc_cord_width_p-1:0] lce_resp_dst_cord_lo; + logic [1:0][coh_noc_cid_width_p-1:0] lce_resp_dst_cid_lo; + + // CCE-side LCE-CCE BedRock network + bp_bedrock_lce_req_header_s lce_req_header_li; + logic [bedrock_fill_width_p-1:0] lce_req_data_li; + logic lce_req_v_li, lce_req_ready_and_lo; + + bp_bedrock_lce_resp_header_s lce_resp_header_li; + logic [bedrock_fill_width_p-1:0] lce_resp_data_li; + logic lce_resp_v_li, lce_resp_ready_and_lo; + + bp_bedrock_lce_cmd_header_s lce_cmd_header_lo; + logic [bedrock_fill_width_p-1:0] lce_cmd_data_lo; + logic lce_cmd_v_lo, lce_cmd_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_cmd_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_cmd_dst_cid_lo; + + // LCE-CCE network links - unconcentrated + bp_coh_ready_and_link_s [1:0] lce_req_link_li, lce_req_link_lo; + bp_coh_ready_and_link_s [1:0] lce_cmd_link_li, lce_cmd_link_lo; + bp_coh_ready_and_link_s [1:0] lce_fill_link_li, lce_fill_link_lo; + bp_coh_ready_and_link_s [1:0] lce_resp_link_li, lce_resp_link_lo; + + bp_coh_ready_and_link_s cce_lce_req_link_lo; + bp_coh_ready_and_link_s cce_lce_resp_link_lo; + + // stub unused CCE link connections + // CCE does not send requests + assign cce_lce_req_link_lo.v = '0; + assign cce_lce_req_link_lo.data = '0; + // CCE does not send responses + assign cce_lce_resp_link_lo.v = '0; + assign cce_lce_resp_link_lo.data = '0; + + for (genvar i = 0; i < 2; i++) begin : lce + + // LCE request from LCE + bp_me_cce_id_to_cord + #(.bp_params_p(bp_params_p)) + req_router_cord + (.cce_id_i(lce_req_header_lo[i].payload.dst_id) + ,.cce_cord_o(lce_req_dst_cord_lo[i]) + ,.cce_cid_o(lce_req_dst_cid_lo[i]) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_req_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_req_header_lo[i]) + ,.pr_data_i(lce_req_data_lo[i]) + ,.pr_v_i(lce_req_v_lo[i]) + ,.pr_ready_and_o(lce_req_ready_and_li[i]) + ,.dst_cord_i(lce_req_dst_cord_lo[i]) + ,.dst_cid_i(lce_req_dst_cid_lo[i]) + + ,.link_data_o(lce_req_link_lo[i].data) + ,.link_v_o(lce_req_link_lo[i].v) + ,.link_ready_and_i(lce_req_link_li[i].ready_and_rev) + ); + // LCE does not receive requests + assign lce_req_link_lo[i].ready_and_rev = 1'b0; + + // LCE command to LCE + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_cmd_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_cmd_link_li[i].data) + ,.link_v_i(lce_cmd_link_li[i].v) + ,.link_ready_and_o(lce_cmd_link_lo[i].ready_and_rev) + + ,.pr_hdr_o(lce_cmd_header_li[i]) + ,.pr_data_o(lce_cmd_data_li[i]) + ,.pr_v_o(lce_cmd_v_li[i]) + ,.pr_ready_and_i(lce_cmd_ready_and_lo[i]) + ); + // LCE does not send commands + assign lce_cmd_link_lo[i].v = '0; + assign lce_cmd_link_lo[i].data = '0; + + // LCE fill to LCE + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_fill_header_width_lp) + ,.pr_payload_width_p(lce_fill_payload_width_lp) + ,.pr_stream_mask_p(lce_fill_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_fill_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_fill_link_li[i].data) + ,.link_v_i(lce_fill_link_li[i].v) + ,.link_ready_and_o(lce_fill_link_lo[i].ready_and_rev) + + ,.pr_hdr_o(lce_fill_header_li[i]) + ,.pr_data_o(lce_fill_data_li[i]) + ,.pr_v_o(lce_fill_v_li[i]) + ,.pr_ready_and_i(lce_fill_ready_and_lo[i]) + ); + + // LCE fill from LCE + bp_me_lce_id_to_cord + #(.bp_params_p(bp_params_p)) + fill_router_cord + (.lce_id_i(lce_fill_header_lo[i].payload.dst_id) + ,.lce_cord_o(lce_fill_dst_cord_lo[i]) + ,.lce_cid_o(lce_fill_dst_cid_lo[i]) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_fill_header_width_lp) + ,.pr_payload_width_p(lce_fill_payload_width_lp) + ,.pr_stream_mask_p(lce_fill_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_fill_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_fill_header_lo[i]) + ,.pr_data_i(lce_fill_data_lo[i]) + ,.pr_v_i(lce_fill_v_lo[i]) + ,.pr_ready_and_o(lce_fill_ready_and_li[i]) + ,.dst_cord_i(lce_fill_dst_cord_lo[i]) + ,.dst_cid_i(lce_fill_dst_cid_lo[i]) + + ,.link_data_o(lce_fill_link_lo[i].data) + ,.link_v_o(lce_fill_link_lo[i].v) + ,.link_ready_and_i(lce_fill_link_li[i].ready_and_rev) + ); + + // LCE Response from LCE + bp_me_cce_id_to_cord + #(.bp_params_p(bp_params_p)) + resp_router_cord + (.cce_id_i(lce_resp_header_lo[i].payload.dst_id) + ,.cce_cord_o(lce_resp_dst_cord_lo[i]) + ,.cce_cid_o(lce_resp_dst_cid_lo[i]) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_resp_header_width_lp) + ,.pr_payload_width_p(lce_resp_payload_width_lp) + ,.pr_stream_mask_p(lce_resp_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_resp_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_resp_header_lo[i]) + ,.pr_data_i(lce_resp_data_lo[i]) + ,.pr_v_i(lce_resp_v_lo[i]) + ,.pr_ready_and_o(lce_resp_ready_and_li[i]) + ,.dst_cord_i(lce_resp_dst_cord_lo[i]) + ,.dst_cid_i(lce_resp_dst_cid_lo[i]) + + ,.link_data_o(lce_resp_link_lo[i].data) + ,.link_v_o(lce_resp_link_lo[i].v) + ,.link_ready_and_i(lce_resp_link_li[i].ready_and_rev) + ); + // LCE does not receive responses + assign lce_resp_link_lo[i].ready_and_rev = 1'b0; + + end // lce to WH network connections + + // LCE to CCE request + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_req_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_req_link_cast_i.data) + ,.link_v_i(lce_req_link_cast_i.v) + ,.link_ready_and_o(cce_lce_req_link_lo.ready_and_rev) + + ,.pr_hdr_o(lce_req_header_li) + ,.pr_data_o(lce_req_data_li) + ,.pr_v_o(lce_req_v_li) + ,.pr_ready_and_i(lce_req_ready_and_lo) + ); + + // CCE to LCE command + bp_me_lce_id_to_cord + #(.bp_params_p(bp_params_p)) + cmd_router_cord + (.lce_id_i(lce_cmd_header_lo.payload.dst_id) + ,.lce_cord_o(lce_cmd_dst_cord_lo) + ,.lce_cid_o(lce_cmd_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_cmd_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_cmd_header_lo) + ,.pr_data_i(lce_cmd_data_lo) + ,.pr_v_i(lce_cmd_v_lo) + ,.pr_ready_and_o(lce_cmd_ready_and_li) + ,.dst_cord_i(lce_cmd_dst_cord_lo) + ,.dst_cid_i(lce_cmd_dst_cid_lo) + + ,.link_data_o(lce_cmd_link_cast_o.data) + ,.link_v_o(lce_cmd_link_cast_o.v) + ,.link_ready_and_i(lce_cmd_link_cast_i.ready_and_rev) + ); + + // LCE to CCE response + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_resp_header_width_lp) + ,.pr_payload_width_p(lce_resp_payload_width_lp) + ,.pr_stream_mask_p(lce_resp_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_resp_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_resp_link_cast_i.data) + ,.link_v_i(lce_resp_link_cast_i.v) + ,.link_ready_and_o(cce_lce_resp_link_lo.ready_and_rev) + + ,.pr_hdr_o(lce_resp_header_li) + ,.pr_data_o(lce_resp_data_li) + ,.pr_v_o(lce_resp_v_li) + ,.pr_ready_and_i(lce_resp_ready_and_lo) + ); + + // LCE-CCE Network Concentrators + + bp_coh_ready_and_link_s req_concentrated_link_li, req_concentrated_link_lo; + bp_coh_ready_and_link_s cmd_concentrated_link_li, cmd_concentrated_link_lo; + bp_coh_ready_and_link_s fill_concentrated_link_li, fill_concentrated_link_lo; + bp_coh_ready_and_link_s resp_concentrated_link_li, resp_concentrated_link_lo; + + assign req_concentrated_link_li = lce_req_link_cast_i; + assign lce_req_link_cast_o = '{data : req_concentrated_link_lo.data + ,v : req_concentrated_link_lo.v + ,ready_and_rev: cce_lce_req_link_lo.ready_and_rev + }; + bsg_wormhole_concentrator_in + #(.flit_width_p(coh_noc_flit_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.num_in_p(2) + ,.cord_width_p(coh_noc_cord_width_p) + ,.hold_on_valid_p(1) + ) + req_concentrator + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.links_v_i({lce_req_link_lo[1].v, lce_req_link_lo[0].v}) + ,.links_data_i({lce_req_link_lo[1].data, lce_req_link_lo[0].data}) + ,.links_ready_and_rev_o({lce_req_link_li[1].ready_and_rev, lce_req_link_li[0].ready_and_rev}) + + ,.concentrated_link_v_o(req_concentrated_link_lo.v) + ,.concentrated_link_data_o(req_concentrated_link_lo.data) + ,.concentrated_link_ready_and_rev_i(req_concentrated_link_li.ready_and_rev) + ); + assign lce_req_link_li[1].v = 1'b0; + assign lce_req_link_li[0].v = 1'b0; + assign lce_req_link_li[1].data = '0; + assign lce_req_link_li[0].data = '0; + assign req_concentrated_link_lo.ready_and_rev = 1'b0; + + assign cmd_concentrated_link_li = lce_cmd_link_cast_i; + assign lce_cmd_link_cast_o.ready_and_rev = cmd_concentrated_link_lo.ready_and_rev; + bsg_wormhole_concentrator_out + #(.flit_width_p(coh_noc_flit_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.num_in_p(2) + ,.cord_width_p(coh_noc_cord_width_p) + ,.hold_on_valid_p(1) + ) + cmd_concentrator + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.links_v_o({lce_cmd_link_li[1].v, lce_cmd_link_li[0].v}) + ,.links_data_o({lce_cmd_link_li[1].data, lce_cmd_link_li[0].data}) + ,.links_ready_and_rev_i({lce_cmd_link_lo[1].ready_and_rev, lce_cmd_link_lo[0].ready_and_rev}) + + ,.concentrated_link_v_i(cmd_concentrated_link_li.v) + ,.concentrated_link_data_i(cmd_concentrated_link_li.data) + ,.concentrated_link_ready_and_rev_o(cmd_concentrated_link_lo.ready_and_rev) + ); + assign lce_cmd_link_li[1].ready_and_rev = 1'b0; + assign lce_cmd_link_li[0].ready_and_rev = 1'b0; + assign cmd_concentrated_link_lo.v = 1'b0; + assign cmd_concentrated_link_lo.data = '0; + + assign fill_concentrated_link_li = lce_fill_link_cast_i; + assign lce_fill_link_cast_o = fill_concentrated_link_lo; + bsg_wormhole_concentrator + #(.flit_width_p(coh_noc_flit_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.num_in_p(2) + ,.cord_width_p(coh_noc_cord_width_p) + ,.hold_on_valid_p(1) + ) + fill_concentrator + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.links_i(lce_fill_link_lo) + ,.links_o(lce_fill_link_li) + + ,.concentrated_link_i(fill_concentrated_link_li) + ,.concentrated_link_o(fill_concentrated_link_lo) + ); + + assign resp_concentrated_link_li = lce_resp_link_cast_i; + assign lce_resp_link_cast_o = '{data : resp_concentrated_link_lo.data + ,v : resp_concentrated_link_lo.v + ,ready_and_rev: cce_lce_resp_link_lo.ready_and_rev + }; + bsg_wormhole_concentrator_in + #(.flit_width_p(coh_noc_flit_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.num_in_p(2) + ,.cord_width_p(coh_noc_cord_width_p) + ,.hold_on_valid_p(1) + ) + resp_concentrator + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.links_v_i({lce_resp_link_lo[1].v, lce_resp_link_lo[0].v}) + ,.links_data_i({lce_resp_link_lo[1].data, lce_resp_link_lo[0].data}) + ,.links_ready_and_rev_o({lce_resp_link_li[1].ready_and_rev, lce_resp_link_li[0].ready_and_rev}) + + ,.concentrated_link_v_o(resp_concentrated_link_lo.v) + ,.concentrated_link_data_o(resp_concentrated_link_lo.data) + ,.concentrated_link_ready_and_rev_i(resp_concentrated_link_li.ready_and_rev) + ); + assign lce_resp_link_li[1].v = 1'b0; + assign lce_resp_link_li[0].v = 1'b0; + assign lce_resp_link_li[1].data = '0; + assign lce_resp_link_li[0].data = '0; + assign resp_concentrated_link_lo.ready_and_rev = 1'b0; + + // Processor + bp_cfg_bus_s cfg_bus_lo; + logic cce_ucode_v_lo; + logic cce_ucode_w_lo; + logic [cce_pc_width_p-1:0] cce_ucode_addr_lo; + logic [cce_instr_width_gp-1:0] cce_ucode_data_lo, cce_ucode_data_li; + + bp_bedrock_mem_fwd_header_s mem_fwd_header_lo; + logic [bedrock_fill_width_p-1:0] mem_fwd_data_lo; + logic mem_fwd_v_lo, mem_fwd_ready_and_li; + bp_bedrock_mem_rev_header_s mem_rev_header_li; + logic [bedrock_fill_width_p-1:0] mem_rev_data_li; + logic mem_rev_v_li, mem_rev_ready_and_lo; + + `declare_bsg_cache_dma_pkt_s(daddr_width_p, l2_block_size_in_words_p); + bsg_cache_dma_pkt_s [l2_dmas_p-1:0] dma_pkt_lo; + logic [l2_dmas_p-1:0] dma_pkt_v_lo, dma_pkt_yumi_li; + logic [l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_li; + logic [l2_dmas_p-1:0] dma_data_v_li, dma_data_ready_and_lo; + logic [l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_lo; + logic [l2_dmas_p-1:0] dma_data_v_lo, dma_data_yumi_li; + bp_core + #(.bp_params_p(bp_params_p)) + core + (.clk_i(clk_i) + ,.rt_clk_i(rt_clk_i) + ,.reset_i(reset_r) + + ,.my_did_i(my_did_i) + ,.host_did_i(host_did_i) + ,.my_cord_i(my_cord_i) + + ,.cfg_bus_o(cfg_bus_lo) + ,.cce_ucode_v_o(cce_ucode_v_lo) + ,.cce_ucode_w_o(cce_ucode_w_lo) + ,.cce_ucode_addr_o(cce_ucode_addr_lo) + ,.cce_ucode_data_o(cce_ucode_data_lo) + ,.cce_ucode_data_i(cce_ucode_data_li) + + ,.lce_req_header_o(lce_req_header_lo) + ,.lce_req_data_o(lce_req_data_lo) + ,.lce_req_v_o(lce_req_v_lo) + ,.lce_req_ready_and_i(lce_req_ready_and_li) + + ,.lce_cmd_header_i(lce_cmd_header_li) + ,.lce_cmd_data_i(lce_cmd_data_li) + ,.lce_cmd_v_i(lce_cmd_v_li) + ,.lce_cmd_ready_and_o(lce_cmd_ready_and_lo) + + ,.lce_resp_header_o(lce_resp_header_lo) + ,.lce_resp_data_o(lce_resp_data_lo) + ,.lce_resp_v_o(lce_resp_v_lo) + ,.lce_resp_ready_and_i(lce_resp_ready_and_li) + + ,.lce_fill_header_i(lce_fill_header_li) + ,.lce_fill_data_i(lce_fill_data_li) + ,.lce_fill_v_i(lce_fill_v_li) + ,.lce_fill_ready_and_o(lce_fill_ready_and_lo) + + ,.lce_fill_header_o(lce_fill_header_lo) + ,.lce_fill_data_o(lce_fill_data_lo) + ,.lce_fill_v_o(lce_fill_v_lo) + ,.lce_fill_ready_and_i(lce_fill_ready_and_li) + + ,.mem_fwd_header_i(mem_fwd_header_lo) + ,.mem_fwd_data_i(mem_fwd_data_lo) + ,.mem_fwd_v_i(mem_fwd_v_lo) + ,.mem_fwd_ready_and_o(mem_fwd_ready_and_li) + + ,.mem_rev_header_o(mem_rev_header_li) + ,.mem_rev_data_o(mem_rev_data_li) + ,.mem_rev_v_o(mem_rev_v_li) + ,.mem_rev_ready_and_i(mem_rev_ready_and_lo) + + ,.dma_pkt_o(dma_pkt_lo) + ,.dma_pkt_v_o(dma_pkt_v_lo) + ,.dma_pkt_ready_and_i(dma_pkt_yumi_li) + + ,.dma_data_i(dma_data_li) + ,.dma_data_v_i(dma_data_v_li) + ,.dma_data_ready_and_o(dma_data_ready_and_lo) + + ,.dma_data_o(dma_data_lo) + ,.dma_data_v_o(dma_data_v_lo) + ,.dma_data_ready_and_i(dma_data_yumi_li) + ); + + // CCE: Cache Coherence Engine + bp_cce_wrapper + #(.bp_params_p(bp_params_p)) + cce + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.cfg_bus_i(cfg_bus_lo) + + ,.ucode_v_i(cce_ucode_v_lo) + ,.ucode_w_i(cce_ucode_w_lo) + ,.ucode_addr_i(cce_ucode_addr_lo) + ,.ucode_data_i(cce_ucode_data_lo) + ,.ucode_data_o(cce_ucode_data_li) + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + ,.lce_req_header_i(lce_req_header_li) + ,.lce_req_data_i(lce_req_data_li) + ,.lce_req_v_i(lce_req_v_li) + ,.lce_req_ready_and_o(lce_req_ready_and_lo) + + ,.lce_resp_header_i(lce_resp_header_li) + ,.lce_resp_data_i(lce_resp_data_li) + ,.lce_resp_v_i(lce_resp_v_li) + ,.lce_resp_ready_and_o(lce_resp_ready_and_lo) + + ,.lce_cmd_header_o(lce_cmd_header_lo) + ,.lce_cmd_data_o(lce_cmd_data_lo) + ,.lce_cmd_v_o(lce_cmd_v_lo) + ,.lce_cmd_ready_and_i(lce_cmd_ready_and_li) + + // CCE-MEM Interface + // BedRock Burst protocol: ready&valid + ,.mem_rev_header_i(mem_rev_header_li) + ,.mem_rev_data_i(mem_rev_data_li) + ,.mem_rev_v_i(mem_rev_v_li) + ,.mem_rev_ready_and_o(mem_rev_ready_and_lo) + + ,.mem_fwd_header_o(mem_fwd_header_lo) + ,.mem_fwd_data_o(mem_fwd_data_lo) + ,.mem_fwd_v_o(mem_fwd_v_lo) + ,.mem_fwd_ready_and_i(mem_fwd_ready_and_li) + ); + + bp_dma_ready_and_link_s [l2_dmas_p-1:0] dma_link_lo, dma_link_li; + for (genvar i = 0; i < l2_dmas_p; i++) + begin : dma + wire [dma_noc_cord_width_p-1:0] cord_li = my_cord_i[coh_noc_x_cord_width_p+:dma_noc_y_cord_width_p]; + wire [dma_noc_cid_width_p-1:0] cid_li = i; + + bsg_cache_dma_to_wormhole + #(.dma_addr_width_p(daddr_width_p) + ,.dma_burst_len_p(l2_block_size_in_fill_p) + ,.dma_mask_width_p(l2_block_size_in_words_p) + + ,.wh_flit_width_p(dma_noc_flit_width_p) + ,.wh_cid_width_p(dma_noc_cid_width_p) + ,.wh_len_width_p(dma_noc_len_width_p) + ,.wh_cord_width_p(dma_noc_cord_width_p) + ) + dma2wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.dma_pkt_i(dma_pkt_lo[i]) + ,.dma_pkt_v_i(dma_pkt_v_lo[i]) + ,.dma_pkt_yumi_o(dma_pkt_yumi_li[i]) + + ,.dma_data_o(dma_data_li[i]) + ,.dma_data_v_o(dma_data_v_li[i]) + ,.dma_data_ready_and_i(dma_data_ready_and_lo[i]) + + ,.dma_data_i(dma_data_lo[i]) + ,.dma_data_v_i(dma_data_v_lo[i]) + ,.dma_data_yumi_o(dma_data_yumi_li[i]) + + ,.wh_link_sif_i(dma_link_li[i]) + ,.wh_link_sif_o(dma_link_lo[i]) + + ,.my_wh_cord_i(cord_li) + ,.my_wh_cid_i(cid_li) + // TODO: Parameterizable? + ,.dest_wh_cord_i('1) + ,.dest_wh_cid_i('0) + ); + end + + bsg_wormhole_concentrator + #(.flit_width_p(dma_noc_flit_width_p) + ,.len_width_p(dma_noc_len_width_p) + ,.cid_width_p(dma_noc_cid_width_p) + ,.cord_width_p(dma_noc_cord_width_p) + ,.num_in_p(l2_dmas_p) + ,.hold_on_valid_p(1) + ) + dma_concentrate + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.links_i(dma_link_lo) + ,.links_o(dma_link_li) + + ,.concentrated_link_o(dma_link_o) + ,.concentrated_link_i(dma_link_i) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_core_tile_node.sv b/designs/black-parrot/src/bp/bp_core_tile_node.sv new file mode 100644 index 0000000..eb3847c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_core_tile_node.sv @@ -0,0 +1,142 @@ +/** + * + * bp_core_tile_node.v + * + */ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" +`include "bp_me_defines.svh" + +module bp_core_tile_node + import bp_common_pkg::*; + import bp_be_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + ) + (input core_clk_i + , input rt_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input dma_clk_i + , input dma_reset_i + + // Memory side connection + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + + // Connected to other tiles on east and west + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_fill_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_fill_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_o + + , input [S:N][dma_noc_ral_link_width_lp-1:0] dma_link_i + , output logic [S:N][dma_noc_ral_link_width_lp-1:0] dma_link_o + ); + + // Declare the routing links + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(dma_noc_flit_width_p, bp_dma_ready_and_link_s); + + // Tile-side coherence connections + bp_coh_ready_and_link_s core_lce_req_link_li, core_lce_req_link_lo; + bp_coh_ready_and_link_s core_lce_cmd_link_li, core_lce_cmd_link_lo; + bp_coh_ready_and_link_s core_lce_fill_link_li, core_lce_fill_link_lo; + bp_coh_ready_and_link_s core_lce_resp_link_li, core_lce_resp_link_lo; + + // Tile side membus connections + bp_dma_ready_and_link_s core_dma_link_lo, core_dma_link_li; + + bp_core_tile + #(.bp_params_p(bp_params_p)) + tile + (.clk_i(core_clk_i) + ,.rt_clk_i(rt_clk_i) + ,.reset_i(core_reset_i) + + // Memory side connection + ,.my_did_i(my_did_i) + ,.host_did_i(host_did_i) + ,.my_cord_i(my_cord_i) + + ,.lce_req_link_i(core_lce_req_link_li) + ,.lce_req_link_o(core_lce_req_link_lo) + + ,.lce_cmd_link_i(core_lce_cmd_link_li) + ,.lce_cmd_link_o(core_lce_cmd_link_lo) + + ,.lce_fill_link_i(core_lce_fill_link_li) + ,.lce_fill_link_o(core_lce_fill_link_lo) + + ,.lce_resp_link_i(core_lce_resp_link_li) + ,.lce_resp_link_o(core_lce_resp_link_lo) + + ,.dma_link_o(core_dma_link_lo) + ,.dma_link_i(core_dma_link_li) + ); + + bp_nd_socket + #(.flit_width_p(coh_noc_flit_width_p) + ,.dims_p(coh_noc_dims_p) + ,.cord_dims_p(coh_noc_dims_p) + ,.cord_markers_pos_p(coh_noc_cord_markers_pos_p) + ,.len_width_p(coh_noc_len_width_p) + ,.routing_matrix_p(StrictYX) + ,.async_clk_p(async_coh_clk_p) + ,.els_p(4) + ) + core_coh_socket + (.tile_clk_i(core_clk_i) + ,.tile_reset_i(core_reset_i) + ,.network_clk_i(coh_clk_i) + ,.network_reset_i(coh_reset_i) + ,.my_cord_i(my_cord_i) + ,.network_link_i({coh_lce_req_link_i, coh_lce_cmd_link_i, coh_lce_fill_link_i, coh_lce_resp_link_i}) + ,.network_link_o({coh_lce_req_link_o, coh_lce_cmd_link_o, coh_lce_fill_link_o, coh_lce_resp_link_o}) + ,.tile_link_i({core_lce_req_link_lo, core_lce_cmd_link_lo, core_lce_fill_link_lo, core_lce_resp_link_lo}) + ,.tile_link_o({core_lce_req_link_li, core_lce_cmd_link_li, core_lce_fill_link_li, core_lce_resp_link_li}) + ); + + + bp_nd_socket + #(.flit_width_p(dma_noc_flit_width_p) + ,.dims_p(dma_noc_dims_p) + ,.cord_dims_p(dma_noc_cord_dims_p) + ,.cord_markers_pos_p(dma_noc_cord_markers_pos_p) + ,.len_width_p(dma_noc_len_width_p) + ,.routing_matrix_p(StrictX) + ,.async_clk_p(async_dma_clk_p) + ,.els_p(1) + ) + core_mem_socket + (.tile_clk_i(core_clk_i) + ,.tile_reset_i(core_reset_i) + ,.network_clk_i(dma_clk_i) + ,.network_reset_i(dma_reset_i) + ,.my_cord_i(my_cord_i[coh_noc_x_cord_width_p+:dma_noc_y_cord_width_p]) + ,.network_link_i(dma_link_i) + ,.network_link_o(dma_link_o) + ,.tile_link_i(core_dma_link_lo) + ,.tile_link_o(core_dma_link_li) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_bht.sv b/designs/black-parrot/src/bp/bp_fe_bht.sv new file mode 100644 index 0000000..ef361a6 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_bht.sv @@ -0,0 +1,144 @@ +/* + * bp_fe_bht.v + * + * Branch History Table (BHT) records the information of the branch history, i.e. + * branch taken or not taken. + * Each entry consists of 2 bit saturation counter. If the counter value is in + * the positive regime, the BHT predicts "taken"; if the counter value is in the + * negative regime, the BHT predicts "not taken". The implementation of BHT is + * native to this design. + * 2-bit saturating counter(high_bit:prediction direction,low_bit:strong/weak prediction) + */ +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_bht + import bp_common_pkg::*; + import bp_fe_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam entry_width_lp = 2*bht_row_els_p + ) + (input clk_i + , input reset_i + + , output logic init_done_o + + , input w_v_i + , input w_force_i + , input [bht_idx_width_p-1:0] w_idx_i + , input [bht_offset_width_p-1:0] w_offset_i + , input [ghist_width_p-1:0] w_ghist_i + , input [bht_row_width_p-1:0] w_val_i + , input w_correct_i + , output logic w_yumi_o + + , input r_v_i + , input [vaddr_width_p-1:0] r_addr_i + , input [ghist_width_p-1:0] r_ghist_i + , output logic [bht_row_width_p-1:0] r_val_o + , output logic r_pred_o + , output logic [bht_idx_width_p-1:0] r_idx_o + , output logic [bht_offset_width_p-1:0] r_offset_o + ); + + // Initialization state machine + enum logic [1:0] {e_reset, e_clear, e_run} state_n, state_r; + wire is_reset = (state_r == e_reset); + wire is_clear = (state_r == e_clear); + wire is_run = (state_r == e_run); + + assign init_done_o = is_run; + + localparam hash_base_lp = 1; + localparam hash_width_lp = 1; + localparam addr_width_lp = bht_idx_width_p+ghist_width_p; + localparam bht_els_lp = 2**addr_width_lp; + localparam bht_init_lp = 2'b01; + logic [`BSG_WIDTH(bht_els_lp)-1:0] init_cnt; + bsg_counter_clear_up + #(.max_val_p(bht_els_lp), .init_val_p(0)) + init_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(1'b0) + ,.up_i(is_clear) + ,.count_o(init_cnt) + ); + wire finished_init = (init_cnt == bht_els_lp-1'b1); + + always_comb + case (state_r) + e_clear: state_n = finished_init ? e_run : e_clear; + e_run : state_n = e_run; + // e_reset + default: state_n = e_clear; + endcase + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + + logic rw_same_addr; + wire suppress_read = rw_same_addr & w_force_i; + wire suppress_write = rw_same_addr & !w_force_i; + + wire w_v_li = is_clear | (w_v_i & ~suppress_write); + wire [addr_width_lp-1:0] w_addr_li = is_clear ? init_cnt : {w_ghist_i, w_idx_i}; + wire [bht_row_els_p-1:0] w_mask_li = is_clear ? '1 : (1'b1 << w_offset_i); + logic [bht_row_width_p-1:0] w_data_li; + for (genvar i = 0; i < bht_row_els_p; i++) + begin : wval + assign w_data_li[2*i] = + is_clear ? bht_init_lp[0] : w_mask_li[i] ? ~w_correct_i : w_val_i[2*i]; + assign w_data_li[2*i+1] = + is_clear ? bht_init_lp[1] : w_mask_li[i] ? w_val_i[2*i+1] ^ (~w_correct_i & w_val_i[2*i]) : w_val_i[2*i+1]; + end + + // GSELECT + wire r_v_li = r_v_i & ~suppress_read; + wire [hash_width_lp-1:0] r_hash_li = r_addr_i[hash_base_lp+:hash_width_lp]; + wire [bht_idx_width_p-1:0] r_idx_li = r_addr_i[2+:bht_idx_width_p] ^ r_hash_li; + wire [addr_width_lp-1:0] r_addr_li = {r_ghist_i, r_idx_li}; + wire [bht_offset_width_p-1:0] r_offset_li = r_addr_i[2+bht_idx_width_p+:bht_offset_width_p]; + + assign rw_same_addr = r_v_i & w_v_i & (r_addr_li == w_addr_li); + + logic [bht_row_width_p-1:0] r_data_lo; + bsg_mem_1r1w_sync + #(.width_p(bht_row_width_p), .els_p(bht_els_lp), .latch_last_read_p(1)) + bht_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(w_v_li) + ,.w_addr_i(w_addr_li) + ,.w_data_i(w_data_li) + + ,.r_v_i(r_v_li) + ,.r_addr_i(r_addr_li) + ,.r_data_o(r_data_lo) + ); + assign w_yumi_o = is_run & w_v_li; + + bsg_dff_en + #(.width_p(bht_offset_width_p+bht_idx_width_p)) + pred_idx_reg + (.clk_i(clk_i) + ,.en_i(r_v_i) + ,.data_i({r_offset_li, r_idx_li}) + ,.data_o({r_offset_o, r_idx_o}) + ); + wire [`BSG_SAFE_CLOG2(bht_row_width_p)-1:0] pred_bit_lo = + (bht_row_els_p > 1) ? ((r_offset_o << 1'b1) + 1'b1) : 1'b1; + + assign r_val_o = r_data_lo; + assign r_pred_o = r_val_o[pred_bit_lo]; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_btb.sv b/designs/black-parrot/src/bp/bp_fe_btb.sv new file mode 100644 index 0000000..f89efd2 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_btb.sv @@ -0,0 +1,164 @@ +/* + * bp_fe_btb.v + * + * Branch Target Buffer (BTB) stores the addresses of the branch targets and the + * corresponding branch sites. Branch happens from the branch sites to the branch + * targets. In order to save the logic sizes, the BTB is designed to have limited + * entries for storing the branch sites, branch target pairs. The implementation + * uses the bsg_mem_1rw_sync_synth RAM design. + * + * Notes: + * BTB writes are prioritized over BTB reads, since they come on redirections and therefore + * the BTB read is most likely for an erroneous instruction, anyway. + */ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_btb + import bp_common_pkg::*; + import bp_fe_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input clk_i + , input reset_i + + , output logic init_done_o + + // Synchronous read + , input [vaddr_width_p-1:0] r_addr_i + , input r_v_i + , output logic [btb_tag_width_p-1:0] r_tag_o + , output logic [btb_idx_width_p-1:0] r_idx_o + , output logic [vaddr_width_p-1:0] r_tgt_o + , output logic r_tgt_v_o + , output logic r_tgt_jmp_o + + // Synchronous write + , input w_v_i + , input w_force_i + , input w_clr_i + , input w_jmp_i + , input [btb_tag_width_p-1:0] w_tag_i + , input [btb_idx_width_p-1:0] w_idx_i + , input [vaddr_width_p-1:0] w_tgt_i + , output logic w_yumi_o + ); + + /////////////////////// + // Initialization state machine + enum logic [1:0] {e_reset, e_clear, e_run} state_n, state_r; + wire is_reset = (state_r == e_reset); + wire is_clear = (state_r == e_clear); + wire is_run = (state_r == e_run); + + assign init_done_o = is_run; + + localparam hash_base_lp = 1; + localparam hash_width_lp = 1; + localparam btb_els_lp = 2**btb_idx_width_p; + localparam addr_width_lp = `BSG_SAFE_CLOG2(btb_els_lp); + logic [`BSG_WIDTH(btb_els_lp)-1:0] init_cnt; + bsg_counter_clear_up + #(.max_val_p(btb_els_lp), .init_val_p(0)) + init_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(1'b0) + ,.up_i(is_clear) + ,.count_o(init_cnt) + ); + wire finished_init = (init_cnt == btb_els_lp-1'b1); + + always_comb + case (state_r) + e_clear: state_n = finished_init ? e_run : e_clear; + e_run : state_n = e_run; + // e_reset + default: state_n = e_clear; + endcase + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + + typedef struct packed + { + logic v; + logic jmp; + logic [btb_tag_width_p-1:0] tag; + logic [vaddr_width_p-1:0] tgt; + } bp_btb_entry_s; + + logic rw_same_addr; + wire suppress_read = rw_same_addr & w_force_i; + wire suppress_write = rw_same_addr & !w_force_i; + + + bp_btb_entry_s w_data_li; + wire w_v_li = is_clear | (w_v_i & ~suppress_write); + wire [addr_width_lp-1:0] w_addr_li = is_clear ? init_cnt : w_idx_i; + // Bug in XSIM 2019.2 causes SEGV when assigning to structs with a mux + bp_btb_entry_s new_btb; + assign new_btb = '{v: 1'b1, jmp: w_jmp_i, tag: w_tag_i, tgt: w_tgt_i}; + assign w_data_li = (is_clear | (w_v_i & w_clr_i)) ? '0 : new_btb; + + bp_btb_entry_s r_data_lo; + wire r_v_li = r_v_i & ~suppress_read; + wire [hash_width_lp-1:0] r_hash_li = r_addr_i[hash_base_lp+:hash_width_lp]; + wire [btb_idx_width_p-1:0] r_idx_li = r_addr_i[2+:btb_idx_width_p] ^ r_hash_li; + wire [addr_width_lp-1:0] r_addr_li = r_idx_li; + wire [btb_tag_width_p-1:0] r_tag_li = r_addr_i[2+btb_idx_width_p+:btb_tag_width_p]; + + assign rw_same_addr = r_v_i & w_v_i & (r_idx_li == w_idx_i); + + bsg_mem_1r1w_sync + #(.width_p($bits(bp_btb_entry_s)), .els_p(btb_els_lp), .latch_last_read_p(1)) + btb_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(w_v_li) + ,.w_addr_i(w_addr_li) + ,.w_data_i(w_data_li) + + ,.r_v_i(r_v_li) + ,.r_addr_i(r_addr_li) + ,.r_data_o(r_data_lo) + ); + assign w_yumi_o = is_run & w_v_li; + + logic r_v_r; + bsg_dff_reset_set_clear + #(.width_p(1)) + r_v_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.set_i(r_v_li) + ,.clear_i(r_v_i) + ,.data_o(r_v_r) + ); + + bsg_dff_reset_en + #(.width_p(btb_idx_width_p+btb_tag_width_p)) + tag_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(r_v_i) + + ,.data_i({r_idx_li, r_tag_li}) + ,.data_o({r_idx_o, r_tag_o}) + ); + + assign r_tgt_v_o = r_v_r & r_data_lo.v & (r_data_lo.tag == r_tag_o); + assign r_tgt_jmp_o = r_v_r & r_data_lo.v & r_data_lo.jmp; + assign r_tgt_o = r_data_lo.tgt; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_controller.sv b/designs/black-parrot/src/bp/bp_fe_controller.sv new file mode 100644 index 0000000..cba6b20 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_controller.sv @@ -0,0 +1,301 @@ +/* + * bp_fe_controller.v + */ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_controller + import bp_fe_pkg::*; + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + + , localparam pte_leaf_width_lp = `bp_pte_leaf_width(paddr_width_p) + , localparam icache_pkt_width_lp = `bp_fe_icache_pkt_width(vaddr_width_p) + ) + (input clk_i + , input reset_i + + , input pc_gen_init_done_i + + , input [fe_cmd_width_lp-1:0] fe_cmd_i + , input fe_cmd_v_i + , output logic fe_cmd_yumi_o + + , output logic [fe_queue_width_lp-1:0] fe_queue_o + , output logic fe_queue_v_o + , input fe_queue_ready_and_i + + , output logic redirect_v_o + , output logic [vaddr_width_p-1:0] redirect_pc_o + , output logic [vaddr_width_p-1:0] redirect_npc_o + , output logic [cinstr_width_gp-1:0] redirect_instr_o + , output logic redirect_resume_o + , output logic redirect_br_v_o + , output logic redirect_br_taken_o + , output logic redirect_br_ntaken_o + , output logic redirect_br_nonbr_o + , output logic [branch_metadata_fwd_width_p-1:0] redirect_br_metadata_fwd_o + + , output logic attaboy_v_o + , output logic attaboy_force_o + , output logic [vaddr_width_p-1:0] attaboy_pc_o + , output logic attaboy_taken_o + , output logic attaboy_ntaken_o + , output logic [branch_metadata_fwd_width_p-1:0] attaboy_br_metadata_fwd_o + , input attaboy_yumi_i + + , input [vaddr_width_p-1:0] next_pc_i + + , input ovr_i + , output logic tl_flush_o + + , input tv_we_i + , input itlb_miss_tl_i + , input instr_page_fault_tl_i + , input instr_access_fault_tl_i + , input icache_miss_tv_i + , output logic tv_flush_o + + , input fetch_v_i + , input [vaddr_width_p-1:0] fetch_pc_i + , input [fetch_width_p-1:0] fetch_instr_i + , input [fetch_ptr_p-1:0] fetch_count_i + , input fetch_partial_i + , input [branch_metadata_fwd_width_p-1:0] fetch_br_metadata_fwd_i + , output logic fetch_yumi_o + + , output logic itlb_r_v_o + , output logic itlb_w_v_o + , output logic [vtag_width_p-1:0] itlb_w_vtag_o + , output logic [pte_leaf_width_lp-1:0] itlb_w_entry_o + , output logic itlb_fence_v_o + + , output logic icache_v_o + , output logic icache_force_o + , output logic [icache_pkt_width_lp-1:0] icache_pkt_o + , input icache_yumi_i + + , output logic shadow_priv_w_o + , output logic [rv64_priv_width_gp-1:0] shadow_priv_o + + , output logic shadow_translation_en_w_o + , output logic shadow_translation_en_o + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_fe_icache_pkt_s(vaddr_width_p); + `bp_cast_i(bp_fe_cmd_s, fe_cmd); + `bp_cast_o(bp_fe_queue_s, fe_queue); + `bp_cast_o(bp_fe_icache_pkt_s, icache_pkt); + + // FSM + enum logic [1:0] {e_reset, e_wait, e_run, e_resume} state_n, state_r; + + // Decoded state signals + wire is_reset = (state_r == e_reset); + wire is_run = (state_r == e_run); + wire is_wait = (state_r == e_wait); + wire is_resume = (state_r == e_resume); + + wire pc_redirect_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode == e_op_pc_redirection); + wire icache_fill_response_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode == e_op_icache_fill_response); + wire icache_fence_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode == e_op_icache_fence); + + wire state_reset_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode == e_op_state_reset); + wire itlb_fill_response_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode == e_op_itlb_fill_response); + wire itlb_fence_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode == e_op_itlb_fence); + wire wait_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode == e_op_wait); + + wire br_miss_v = pc_redirect_v & (fe_cmd_cast_i.operands.pc_redirect_operands.subopcode == e_subop_branch_mispredict); + wire eret_v = pc_redirect_v & (fe_cmd_cast_i.operands.pc_redirect_operands.subopcode == e_subop_eret); + wire interrupt_v = pc_redirect_v & (fe_cmd_cast_i.operands.pc_redirect_operands.subopcode == e_subop_interrupt); + wire trap_v = pc_redirect_v & (fe_cmd_cast_i.operands.pc_redirect_operands.subopcode == e_subop_trap); + wire translation_v = pc_redirect_v & (fe_cmd_cast_i.operands.pc_redirect_operands.subopcode == e_subop_translation_switch); + // Unsupported + //wire context_v = pc_redirect_v & (fe_cmd_cast_i.operands.pc_redirect_operands.subopcode == e_subop_context_switch); + + wire br_miss_taken = br_miss_v + & (fe_cmd_cast_i.operands.pc_redirect_operands.misprediction_reason == e_incorrect_pred_taken); + wire br_miss_ntaken = br_miss_v + & (fe_cmd_cast_i.operands.pc_redirect_operands.misprediction_reason == e_incorrect_pred_ntaken); + wire br_miss_nonbr = br_miss_v + & (fe_cmd_cast_i.operands.pc_redirect_operands.misprediction_reason == e_not_a_branch); + + wire attaboy_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode == e_op_attaboy); + wire cmd_nonattaboy_v = fe_cmd_v_i & (fe_cmd_cast_i.opcode != e_op_attaboy); + wire cmd_immediate_v = fe_cmd_v_i & (pc_redirect_v | icache_fill_response_v | wait_v); + wire cmd_complex_v = fe_cmd_v_i & (state_reset_v | itlb_fill_response_v | icache_fence_v | itlb_fence_v); + + assign redirect_v_o = !is_wait & cmd_nonattaboy_v; + assign redirect_pc_o = fe_cmd_cast_i.npc - (redirect_resume_o << 1'b1); + assign redirect_npc_o = fe_cmd_cast_i.npc; + assign redirect_br_v_o = !is_wait & br_miss_v; + assign redirect_br_taken_o = br_miss_taken; + assign redirect_br_ntaken_o = br_miss_ntaken; + assign redirect_br_nonbr_o = br_miss_nonbr; + assign redirect_br_metadata_fwd_o = fe_cmd_cast_i.operands.pc_redirect_operands.branch_metadata_fwd; + + assign attaboy_v_o = attaboy_v; + assign attaboy_force_o = ~fe_queue_ready_and_i; + assign attaboy_pc_o = fe_cmd_cast_i.npc; + assign attaboy_taken_o = attaboy_v & fe_cmd_cast_i.operands.attaboy.taken; + assign attaboy_ntaken_o = attaboy_v & ~fe_cmd_cast_i.operands.attaboy.taken; + assign attaboy_br_metadata_fwd_o = fe_cmd_cast_i.operands.attaboy.branch_metadata_fwd; + + assign shadow_priv_w_o = state_reset_v | trap_v | interrupt_v | eret_v; + assign shadow_priv_o = fe_cmd_cast_i.operands.pc_redirect_operands.priv; + + assign shadow_translation_en_w_o = state_reset_v | trap_v | interrupt_v | eret_v | translation_v; + assign shadow_translation_en_o = fe_cmd_cast_i.operands.pc_redirect_operands.translation_en; + + assign itlb_w_vtag_o = fe_cmd_cast_i.npc[vaddr_width_p-1-:vtag_width_p]; + assign itlb_w_entry_o = fe_cmd_cast_i.operands.itlb_fill_response.pte_leaf; + + assign icache_pkt_cast_o = + '{vaddr: next_pc_i + ,op : (is_run & icache_fence_v) ? e_icache_inval : e_icache_fetch + ,spec: !icache_fill_response_v + }; + + assign redirect_instr_o = itlb_fill_response_v + ? fe_cmd_cast_i.operands.itlb_fill_response.instr + : fe_cmd_cast_i.operands.icache_fill_response.instr; + assign redirect_resume_o = + itlb_fill_response_v + ? (fe_cmd_cast_i.operands.itlb_fill_response.count > '0) + : icache_fill_response_v + ? (fe_cmd_cast_i.operands.icache_fill_response.count > '0) + : '0; + + logic itlb_miss_tv_r, instr_page_fault_tv_r, instr_access_fault_tv_r; + bsg_dff_reset_en + #(.width_p(3)) + exception_reg + (.clk_i(clk_i) + ,.reset_i(reset_i || tv_flush_o) + ,.en_i(tv_we_i) + ,.data_i({itlb_miss_tl_i, instr_page_fault_tl_i, instr_access_fault_tl_i}) + ,.data_o({itlb_miss_tv_r, instr_page_fault_tv_r, instr_access_fault_tv_r}) + ); + wire if2_exception_v = |{itlb_miss_tv_r, instr_page_fault_tv_r, instr_access_fault_tv_r, icache_miss_tv_i}; + + wire fetch_instr_v = is_run && fe_queue_ready_and_i && fetch_v_i && (fetch_count_i > '0); + wire fetch_exception_v = is_run && fe_queue_ready_and_i && if2_exception_v && ~fetch_instr_v; + + assign fetch_yumi_o = is_run && fe_queue_ready_and_i && fetch_v_i; + always_comb + begin + fe_queue_v_o = (fetch_instr_v | fetch_exception_v); + + fe_queue_cast_o = '0; + fe_queue_cast_o.pc = fetch_pc_i; + fe_queue_cast_o.instr = fetch_instr_i; + fe_queue_cast_o.msg_type = fetch_instr_v + ? e_instr_fetch + : itlb_miss_tv_r + ? e_itlb_miss + : instr_page_fault_tv_r + ? e_instr_page_fault + : instr_access_fault_tv_r + ? e_instr_access_fault + : e_icache_miss; + fe_queue_cast_o.branch_metadata_fwd = fetch_br_metadata_fwd_i; + fe_queue_cast_o.count = fetch_instr_v ? fetch_count_i : fetch_partial_i; + end + + always_comb + begin + icache_v_o = 1'b0; + icache_force_o = 1'b0; + + itlb_r_v_o = 1'b0; + itlb_w_v_o = 1'b0; + itlb_fence_v_o = 1'b0; + + tl_flush_o = 1'b0; + tv_flush_o = 1'b0; + + fe_cmd_yumi_o = 1'b0; + + state_n = state_r; + + case (state_r) + e_reset: + begin + // Drain non-reset requests + fe_cmd_yumi_o = fe_cmd_v_i & !state_reset_v; + + state_n = (state_reset_v && pc_gen_init_done_i) ? e_resume : state_r; + end + e_wait: + begin + fe_cmd_yumi_o = attaboy_v && attaboy_yumi_i; + + tl_flush_o = 1'b1; + tv_flush_o = 1'b1; + + state_n = cmd_nonattaboy_v ? e_run : state_r; + end + e_resume: + begin + icache_v_o = fe_cmd_v_i; + itlb_r_v_o = icache_yumi_i; + + fe_cmd_yumi_o = icache_yumi_i; + + state_n = fe_cmd_yumi_o ? e_run : state_r; + end + e_run: + begin + if (cmd_immediate_v) + begin + icache_v_o = 1'b1; + icache_force_o = 1'b1; + itlb_r_v_o = icache_yumi_i; + + tv_flush_o = 1'b1; + + fe_cmd_yumi_o = icache_yumi_i; + end + else if (cmd_complex_v) + begin + icache_v_o = icache_fence_v && !icache_features_p[e_cfg_coherent]; + icache_force_o = 1'b1; + + itlb_w_v_o = itlb_fill_response_v; + itlb_fence_v_o = itlb_fence_v; + + tl_flush_o = itlb_fill_response_v | itlb_fence_v; + tv_flush_o = 1'b1; + + state_n = e_resume; + end + else + begin + icache_v_o = 1'b1; + icache_force_o = ovr_i; + itlb_r_v_o = icache_yumi_i; + + tv_flush_o = ovr_i; + + fe_cmd_yumi_o = attaboy_v && attaboy_yumi_i; + + state_n = fetch_exception_v ? e_wait : state_r; + end + end + endcase + end + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_defines.svh b/designs/black-parrot/src/bp/bp_fe_defines.svh new file mode 100644 index 0000000..0659b0d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_defines.svh @@ -0,0 +1,36 @@ +/* + * bp_fe_defines.svh + * + * bp_fe_defines.svh provides all the necessary structs for the Frontend submodules. + * Backend supplies the frontend with branch prediction results and exceptions + * codes. The Frontend should update the states accordingly. + */ + +`ifndef BP_FE_DEFINES_SVH +`define BP_FE_DEFINES_SVH + + `include "bsg_defines.sv" + `include "bp_fe_icache_defines.svh" + + `define declare_bp_fe_branch_metadata_fwd_s(ras_idx_width_mp, btb_tag_width_mp, btb_idx_width_mp, bht_idx_width_mp, ghist_width_mp, bht_row_els_mp) \ + typedef struct packed \ + { \ + logic site_br; \ + logic site_jal; \ + logic site_jalr; \ + logic site_call; \ + logic site_return; \ + logic src_ras; \ + logic src_btb; \ + logic [ras_idx_width_mp-1:0] ras_next; \ + logic [ras_idx_width_mp-1:0] ras_tos; \ + logic [btb_tag_width_mp-1:0] btb_tag; \ + logic [btb_idx_width_mp-1:0] btb_idx; \ + logic [bht_idx_width_mp-1:0] bht_idx; \ + logic [2*bht_row_els_mp-1:0] bht_row; \ + logic [`BSG_SAFE_CLOG2(bht_row_els_mp)-1:0] bht_offset; \ + logic [ghist_width_mp-1:0] ghist; \ + } bp_fe_branch_metadata_fwd_s + +`endif + diff --git a/designs/black-parrot/src/bp/bp_fe_icache.sv b/designs/black-parrot/src/bp/bp_fe_icache.sv new file mode 100644 index 0000000..de3790c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_icache.sv @@ -0,0 +1,744 @@ +/** + * + * Name: + * bp_fe_icache.sv + * + * Description: + * L1 Instruction Cache. Features: + * - Virtually-indexed, physically-tagged + * - 1-8 way set-associative + * - 64-512 bit block size (minimum 64-bit data mem bank size) + * - Separate speculative and non-speculative fetch commands + * + * An address is broken down as follows: + * physical address = [physical tag | virtual index | block offset] + * + * There are 3 large SRAMs (must be hardened for good QoR): + * - Tag Mem: Physical tags and coherence state + * - Data Mem: Cache data blocks. 1 bank per way, with data + * interleaved between the banks as bank_id = word_offset + way_id + * - Stat Mem: Contains the LRU and information for the cache line + * + * See interface for usage notes + * + * Notes: + * Supports multi-cycle fill/eviction with the UCE in unicore configuration + * Uses fill_index in data_mem_pkt to generate a write_mask for the data banks + * bank_width = block_width / assoc >= dword_width + * fill_width = N*bank_width <= block_width + */ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_icache + import bp_common_pkg::*; + import bp_fe_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // Default to icache parameters, but can override if needed + , parameter misaligned_p = icache_features_p[e_cfg_misaligned] + , parameter coherent_p = icache_features_p[e_cfg_coherent] + , parameter sets_p = icache_sets_p + , parameter assoc_p = icache_assoc_p + , parameter block_width_p = icache_block_width_p + , parameter fill_width_p = icache_fill_width_p + , parameter data_width_p = icache_data_width_p + , parameter tag_width_p = icache_tag_width_p + , parameter id_width_p = icache_req_id_width_p + + `declare_bp_fe_icache_engine_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p) + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + , localparam icache_pkt_width_lp = `bp_fe_icache_pkt_width(vaddr_width_p) + ) + (input clk_i + , input reset_i + + // Unused except for tracers + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // Cycle 0: "Decode" + // New I$ packet comes in for a fetch, fence or fill request + // v_i is raised when there is a new request + // yumi_o is raised when that request is accepted + // Normally, yumi_o waits for TL to be empty so as to not lose + // requests. However, when we're redirecting the I$ we may want + // to override the TL message right away. force_i says to accept + // regardless of v_tl_r status + , input [icache_pkt_width_lp-1:0] icache_pkt_i + , input v_i + , input force_i + , output yumi_o + , input tl_flush_i + + // Cycle 1: "Tag Lookup" + // TLB and PMA information comes in this cycle + // tv_flush_i eliminates the request in this stage, used for redirections + // We output tv_we as a signal to move parallel pipelines forward + , input [ptag_width_p-1:0] ptag_i + , input ptag_v_i + , input ptag_uncached_i + , input ptag_nonidem_i + , input ptag_dram_i + , input tv_flush_i + , output logic tv_we_o + + // Cycle 2: "Tag Verify" + // Data (or miss result) comes out of the cache + // Cache engine requests cannot be cancelled once they come here, but tv_flush_i + // will prevent them from escaping the I$. + // data_o is the outgoing data, with v_o being valid + // yumi_i is dequeues the data + , output logic [data_width_p-1:0] data_o + , output logic hit_v_o + , output logic miss_v_o + , output logic fence_v_o + , input yumi_i + + // Cache Engine Interface + // This is considered the "slow path", handling uncached requests + // and fill DMAs. It also handles coherence transactions for + // configurations which support that behavior + , output logic [icache_req_width_lp-1:0] cache_req_o + , output logic cache_req_v_o + , input cache_req_yumi_i + , input cache_req_lock_i + , output logic [icache_req_metadata_width_lp-1:0] cache_req_metadata_o + , output logic cache_req_metadata_v_o + , input [id_width_p-1:0] cache_req_id_i + , input cache_req_critical_i + , input cache_req_last_i + , input cache_req_credits_full_i + , input cache_req_credits_empty_i + + , input data_mem_pkt_v_i + , input [icache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , output logic data_mem_pkt_yumi_o + , output logic [block_width_p-1:0] data_mem_o + + , input tag_mem_pkt_v_i + , input [icache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , output logic tag_mem_pkt_yumi_o + , output logic [icache_tag_info_width_lp-1:0] tag_mem_o + + , input stat_mem_pkt_v_i + , input [icache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , output logic stat_mem_pkt_yumi_o + , output logic [icache_stat_info_width_lp-1:0] stat_mem_o + ); + + `declare_bp_fe_icache_engine_if(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p); + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + + // Various localparameters + localparam lg_assoc_lp =`BSG_SAFE_CLOG2(assoc_p); + localparam bank_width_lp = block_width_p / assoc_p; + localparam num_data_per_bank_lp = bank_width_lp / data_width_p; + localparam data_mem_mask_width_lp = (bank_width_lp >> 3); + localparam byte_offset_width_lp = `BSG_SAFE_CLOG2(bank_width_lp >> 3); + localparam bindex_width_lp = `BSG_SAFE_CLOG2(assoc_p); + localparam sindex_width_lp = `BSG_SAFE_CLOG2(sets_p); + localparam block_offset_width_lp = (assoc_p > 1) + ? (bindex_width_lp+byte_offset_width_lp) + : byte_offset_width_lp; + localparam block_size_in_fill_lp = block_width_p / fill_width_p; + localparam fill_size_in_bank_lp = fill_width_p / bank_width_lp; + + // State machine declaration + enum logic [1:0] {e_ready, e_miss, e_recover} state_n, state_r; + wire is_ready = (state_r == e_ready); + wire is_miss = (state_r == e_miss); + wire is_recover = (state_r == e_recover); + + // Feedback signals between stages + logic tl_we, tv_we; + logic v_tl_n, v_tl_r; + logic v_tv_n, v_tv_r; + + wire critical_recv = is_miss & cache_req_critical_i + & (~stat_mem_pkt_v_i | stat_mem_pkt_yumi_o) + & (~tag_mem_pkt_v_i | tag_mem_pkt_yumi_o) + & (~data_mem_pkt_v_i | data_mem_pkt_yumi_o); + wire complete_recv = is_miss & cache_req_last_i + & (~stat_mem_pkt_v_i | stat_mem_pkt_yumi_o) + & (~tag_mem_pkt_v_i | tag_mem_pkt_yumi_o) + & (~data_mem_pkt_v_i | data_mem_pkt_yumi_o); + + // Snoop signals + logic [block_width_p-1:0] snoop_data; + logic [assoc_p-1:0] snoop_hit; + logic [assoc_p-1:0] snoop_way; + logic [assoc_p-1:0] snoop_bank_sel_one_hot; + logic snoop_spec, snoop_uncached; + bp_fe_icache_decode_s snoop_decode; + + ///////////////////////////////////////////////////////////////////////////// + // Decode stage + ///////////////////////////////////////////////////////////////////////////// + `declare_bp_fe_icache_pkt_s(vaddr_width_p); + `bp_cast_i(bp_fe_icache_pkt_s, icache_pkt); + bp_fe_icache_decode_s decode_lo; + + wire [vaddr_width_p-1:0] vaddr = icache_pkt_cast_i.vaddr; + wire [vtag_width_p-1:0] vaddr_vtag = vaddr[(vaddr_width_p-1)-:vtag_width_p]; + wire [sindex_width_lp-1:0] vaddr_index = vaddr[block_offset_width_lp+:sindex_width_lp]; + wire [bindex_width_lp-1:0] vaddr_bank = vaddr[byte_offset_width_lp+:bindex_width_lp]; + + wire spec = icache_pkt_cast_i.spec; + + assign decode_lo = '{fetch_op : icache_pkt_cast_i.op inside {e_icache_fetch} + ,inval_op: icache_pkt_cast_i.op inside {e_icache_inval} + }; + + // Accept requests when we're in ready state and there's no blocked request in TL + // Also accept request when 'forced' + assign yumi_o = v_i & tl_we; + + /////////////////////////// + // Tag Mem Storage + /////////////////////////// + `bp_cast_i(bp_fe_icache_tag_mem_pkt_s, tag_mem_pkt); + logic tag_mem_v_li; + logic tag_mem_w_li; + logic [sindex_width_lp-1:0] tag_mem_addr_li; + bp_fe_icache_tag_info_s [assoc_p-1:0] tag_mem_w_mask_li; + bp_fe_icache_tag_info_s [assoc_p-1:0] tag_mem_data_li; + bp_fe_icache_tag_info_s [assoc_p-1:0] tag_mem_data_lo; + + bsg_mem_1rw_sync_mask_write_bit + #(.width_p(assoc_p*($bits(bp_fe_icache_tag_info_s))), .els_p(sets_p), .latch_last_read_p(1)) + tag_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(tag_mem_data_li) + ,.addr_i(tag_mem_addr_li) + ,.v_i(tag_mem_v_li) + ,.w_mask_i(tag_mem_w_mask_li) + ,.w_i(tag_mem_w_li) + ,.data_o(tag_mem_data_lo) + ); + + /////////////////////////// + // Data Mem Storage + /////////////////////////// + `bp_cast_i(bp_fe_icache_data_mem_pkt_s, data_mem_pkt); + localparam data_mem_addr_width_lp = (assoc_p > 1) ? (sindex_width_lp+bindex_width_lp) : sindex_width_lp; + logic [assoc_p-1:0] data_mem_v_li; + logic [assoc_p-1:0] data_mem_w_li; + logic [assoc_p-1:0][data_mem_addr_width_lp-1:0] data_mem_addr_li; + logic [assoc_p-1:0][bank_width_lp-1:0] data_mem_data_li; + logic [assoc_p-1:0][bank_width_lp-1:0] data_mem_data_lo; + + for (genvar bank = 0; bank < assoc_p; bank++) + begin: data_mems + bsg_mem_1rw_sync #(.width_p(bank_width_lp), .els_p(sets_p*assoc_p), .latch_last_read_p(1)) + data_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(data_mem_data_li[bank]) + ,.addr_i(data_mem_addr_li[bank]) + ,.v_i(data_mem_v_li[bank]) + ,.w_i(data_mem_w_li[bank]) + ,.data_o(data_mem_data_lo[bank]) + ); + end + + ///////////////////////////////////////////////////////////////////////////// + // TL Stage + ///////////////////////////////////////////////////////////////////////////// + logic [vaddr_width_p-1:0] vaddr_tl_r; + logic spec_tl_r; + bp_fe_icache_decode_s decode_tl_r; + + assign tl_we = v_tl_r ? (tv_we | force_i) : ~cache_req_lock_i; + bsg_dff_reset_en + #(.width_p(1)) + v_tl_reg + (.clk_i(clk_i) + ,.reset_i(reset_i | tl_flush_i) + ,.en_i(tl_we) + ,.data_i(yumi_o) + ,.data_o(v_tl_r) + ); + + // Save stage information + bsg_dff_reset_en + #(.width_p(vaddr_width_p+1+$bits(bp_fe_icache_decode_s))) + tl_stage_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(tl_we) + ,.data_i({vaddr, spec, decode_lo}) + ,.data_o({vaddr_tl_r, spec_tl_r, decode_tl_r}) + ); + + wire [paddr_width_p-1:0] paddr_tl = {ptag_i, vaddr_tl_r[0+:page_offset_width_gp]}; + wire [vtag_width_p-1:0] vaddr_vtag_tl = vaddr_tl_r[(vaddr_width_p-1)-:vtag_width_p]; + wire [sindex_width_lp-1:0] vaddr_index_tl = vaddr_tl_r[block_offset_width_lp+:sindex_width_lp]; + wire [bindex_width_lp-1:0] vaddr_bank_tl = vaddr_tl_r[byte_offset_width_lp+:bindex_width_lp]; + + // Concatenate unused bits from vaddr if any cache way size is not 4kb + localparam ctag_vbits_lp = page_offset_width_gp - (block_offset_width_lp + sindex_width_lp); + wire [ctag_vbits_lp-1:0] ctag_vbits = vaddr_tl_r[block_offset_width_lp+sindex_width_lp+:`BSG_MAX(ctag_vbits_lp,1)]; + // Causes segfault in Synopsys DC O-2018.06-SP4 + // wire [tag_width_p-1:0] ctag_li = {ptag_i, {ctag_vbits_lp!=0{ctag_vbits}}}; + wire [tag_width_p-1:0] ctag_li = ctag_vbits_lp ? {ptag_i, ctag_vbits} : ptag_i; + wire [ptag_width_p-1:tag_width_p] ptag_high_li = ptag_i >> tag_width_p; + + logic [assoc_p-1:0] way_v_tl, hit_v_tl; + for (genvar i = 0; i < assoc_p; i++) begin: tag_comp_tl + wire tag_match_tl = ptag_v_i & ~|ptag_high_li & (ctag_li == tag_mem_data_lo[i].tag); + assign way_v_tl[i] = (tag_mem_data_lo[i].state != e_COH_I); + assign hit_v_tl[i] = tag_match_tl & (tag_mem_data_lo[i].tag == ctag_li && way_v_tl[i]); + end + wire fetch_uncached_tl = (decode_tl_r.fetch_op & ptag_uncached_i); + wire fetch_cached_tl = (decode_tl_r.fetch_op & ~ptag_uncached_i); + wire spec_tl = (decode_tl_r.fetch_op & !ptag_v_i) + || (decode_tl_r.fetch_op & spec_tl_r & ptag_nonidem_i); + + logic [assoc_p-1:0] bank_sel_one_hot_tl; + bsg_decode + #(.num_out_p(assoc_p)) + offset_decode + (.i(vaddr_bank_tl) + ,.o(bank_sel_one_hot_tl) + ); + + ///////////////////////////////////////////////////////////////////////////// + // TV Stage + ///////////////////////////////////////////////////////////////////////////// + localparam snoop_offset_width_lp = `BSG_SAFE_CLOG2(fill_width_p/word_width_gp); + logic [paddr_width_p-1:0] paddr_tv_r; + logic [assoc_p-1:0] bank_sel_one_hot_tv_r, way_v_tv_r, hit_v_tv_r; + logic spec_tv_r, uncached_tv_r; + bp_fe_icache_decode_s decode_tv_r; + logic snoop_tv_r; + logic [assoc_p-1:0][bank_width_lp-1:0] ld_data_tv_r; + + assign tv_we = v_tv_r ? yumi_i : is_ready; + bsg_dff_reset_en + #(.width_p(1)) + v_tv_reg + (.clk_i(clk_i) + ,.reset_i(reset_i | tv_flush_i) + ,.en_i(tv_we) + ,.data_i(v_tl_r) + ,.data_o(v_tv_r) + ); + assign tv_we_o = tv_we; + + logic [assoc_p-1:0] bank_sel_one_hot_tv_n, way_v_tv_n, hit_v_tv_n; + logic [block_width_p-1:0] ld_data_tv_n; + logic spec_tv_n, uncached_tv_n; + bp_fe_icache_decode_s decode_tv_n; + bsg_mux + #(.width_p(3*assoc_p+block_width_p+2+$bits(bp_fe_icache_decode_s)), .els_p(2)) + hit_mux + (.data_i({{snoop_bank_sel_one_hot, snoop_way, snoop_hit, snoop_data + ,snoop_spec, snoop_uncached, snoop_decode} + ,{bank_sel_one_hot_tl, way_v_tl, hit_v_tl, data_mem_data_lo + ,spec_tl, fetch_uncached_tl, decode_tl_r} + }) + ,.sel_i(critical_recv) + ,.data_o({bank_sel_one_hot_tv_n, way_v_tv_n, hit_v_tv_n, ld_data_tv_n + ,spec_tv_n, uncached_tv_n, decode_tv_n}) + ); + + wire snoop_tv_n = critical_recv; + bsg_dff_reset_en + #(.width_p(block_width_p+1+3*assoc_p+2+$bits(bp_fe_icache_decode_s))) + tv_stage_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(tv_we | critical_recv) + ,.data_i({ld_data_tv_n, snoop_tv_n, bank_sel_one_hot_tv_n, way_v_tv_n, hit_v_tv_n + ,spec_tv_n, uncached_tv_n, decode_tv_n + }) + ,.data_o({ld_data_tv_r, snoop_tv_r, bank_sel_one_hot_tv_r, way_v_tv_r, hit_v_tv_r + ,spec_tv_r, uncached_tv_r, decode_tv_r + }) + ); + + wire [paddr_width_p-1:0] paddr_tv_n = critical_recv ? paddr_tv_r : paddr_tl; + bsg_dff_en + #(.width_p(paddr_width_p)) + paddr_reg + (.clk_i(clk_i) + ,.en_i(tv_we | critical_recv) + ,.data_i(paddr_tv_n) + ,.data_o(paddr_tv_r) + ); + + logic [lg_assoc_lp-1:0] invalid_way_tv; + logic invalid_exist_tv; + bsg_priority_encode + #(.width_p(assoc_p), .lo_to_hi_p(1)) + pe_invalid + (.i(~way_v_tv_r) + ,.v_o(invalid_exist_tv) + ,.addr_o(invalid_way_tv) + ); + + // If there is invalid way, then it take priority over LRU way. + logic [lg_assoc_lp-1:0] lru_encode; + wire [lg_assoc_lp-1:0] lru_way_li = invalid_exist_tv ? invalid_way_tv : lru_encode; + + logic [lg_assoc_lp-1:0] hit_index_tv; + logic hit_v_tv; + bsg_encode_one_hot + #(.width_p(assoc_p), .lo_to_hi_p(1)) + hit_index_encoder + (.i(hit_v_tv_r) + ,.addr_o(hit_index_tv) + ,.v_o(hit_v_tv) + ); + + logic [assoc_p-1:0] ld_data_way_select_tv; + bsg_adder_one_hot + #(.width_p(assoc_p)) + select_adder + (.a_i(hit_v_tv_r) + ,.b_i(bank_sel_one_hot_tv_r) + ,.o(ld_data_way_select_tv) + ); + + logic [bank_width_lp-1:0] ld_data_way_picked; + bsg_mux_one_hot + #(.width_p(bank_width_lp), .els_p(assoc_p)) + data_set_select_mux + (.data_i(ld_data_tv_r) + ,.sel_one_hot_i(ld_data_way_select_tv) + ,.data_o(ld_data_way_picked) + ); + + // TODO: Can retime manually for critical path? + logic [data_width_p-1:0] final_data_tv; + wire [`BSG_SAFE_CLOG2(num_data_per_bank_lp)-1:0] ld_data_word_sel_tv = + paddr_tv_r[2+:`BSG_SAFE_CLOG2(num_data_per_bank_lp)]; + bsg_mux + #(.width_p(data_width_p), .els_p(num_data_per_bank_lp)) + data_select_mux + (.data_i(ld_data_way_picked) + ,.sel_i(ld_data_word_sel_tv) + ,.data_o(final_data_tv) + ); + + assign data_o = final_data_tv; + assign hit_v_o = is_ready & v_tv_r & decode_tv_r.fetch_op & ~spec_tv_r & hit_v_tv; + assign miss_v_o = is_ready & v_tv_r & decode_tv_r.fetch_op & spec_tv_r & ~hit_v_tv; + assign fence_v_o = is_ready & v_tv_r & decode_tv_r.inval_op & snoop_tv_r; + + /////////////////////////// + // Stat Mem Storage + /////////////////////////// + `bp_cast_i(bp_fe_icache_stat_mem_pkt_s, stat_mem_pkt); + logic stat_mem_v_li; + logic stat_mem_w_li; + logic [sindex_width_lp-1:0] stat_mem_addr_li; + bp_fe_icache_stat_info_s stat_mem_data_li; + bp_fe_icache_stat_info_s stat_mem_mask_li; + bp_fe_icache_stat_info_s stat_mem_data_lo; + + bsg_mem_1rw_sync_mask_write_bit + #(.width_p(assoc_p-1), .els_p(sets_p), .latch_last_read_p(1)) + stat_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(stat_mem_data_li.lru) + ,.addr_i(stat_mem_addr_li) + ,.v_i(stat_mem_v_li) + ,.w_mask_i(stat_mem_mask_li.lru) + ,.w_i(stat_mem_w_li) + ,.data_o(stat_mem_data_lo.lru) + ); + assign stat_mem_data_lo.dirty = '0; + + bsg_lru_pseudo_tree_encode + #(.ways_p(assoc_p)) + lru_encoder + (.lru_i(stat_mem_data_lo.lru) + ,.way_id_o(lru_encode) + ); + + ///////////////////////////////////////////////////////////////////////////// + // Slow Path + ///////////////////////////////////////////////////////////////////////////// + `bp_cast_o(bp_fe_icache_req_s, cache_req); + `bp_cast_o(bp_fe_icache_req_metadata_s, cache_req_metadata); + + localparam block_req_size = bp_cache_req_size_e'(`BSG_SAFE_CLOG2(block_width_p/8)); + localparam uncached_req_size = bp_cache_req_size_e'(`BSG_SAFE_CLOG2(data_width_p/8)); + + wire cached_req = decode_tv_r.fetch_op & ~snoop_tv_r & ~hit_v_tv & ~uncached_tv_r & ~spec_tv_r; + wire uncached_req = decode_tv_r.fetch_op & ~snoop_tv_r & ~hit_v_tv & uncached_tv_r & ~spec_tv_r; + wire inval_req = decode_tv_r.inval_op & ~snoop_tv_r; + + assign cache_req_v_o = is_ready & v_tv_r & |{uncached_req, cached_req, inval_req} & ~tv_flush_i; + assign cache_req_cast_o = + '{addr : paddr_tv_r + ,size : bp_cache_req_size_e'(cached_req ? block_req_size : uncached_req_size) + ,msg_type: cached_req ? e_miss_load : uncached_req ? e_uc_load : e_cache_inval + ,subop : e_req_amoswap + ,hit : hit_v_tv + ,id : '0 + ,data : '0 + }; + + // The cache pipeline is designed to always send metadata a cycle after the request + wire cache_req_metadata_v = cache_req_yumi_i; + bsg_dff_reset + #(.width_p(1)) + cache_req_v_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(cache_req_metadata_v) + ,.data_o(cache_req_metadata_v_o) + ); + + logic metadata_hit_r; + logic [lg_assoc_lp-1:0] metadata_hit_index_r; + bsg_dff + #(.width_p(1+lg_assoc_lp)) + hit_reg + (.clk_i(clk_i) + ,.data_i({hit_v_tv, hit_index_tv}) + ,.data_o({metadata_hit_r, metadata_hit_index_r}) + ); + + wire [assoc_p-1:0] hit_or_repl_way = metadata_hit_r ? metadata_hit_index_r : lru_way_li; + assign cache_req_metadata_cast_o.hit_or_repl_way = hit_or_repl_way; + assign cache_req_metadata_cast_o.dirty = '0; + + ///////////////////////////////////////////////////////////////////////////// + // State machine + // e_ready : Cache is ready to accept requests + // e_miss : Cache is waiting for a cache request to be serviced + // e_recover : Reread the SRAMs to recover the updated TL state + ///////////////////////////////////////////////////////////////////////////// + always_comb + case (state_r) + e_ready : state_n = cache_req_yumi_i ? e_miss : state_r; + e_miss : state_n = complete_recv ? e_recover : state_r; + // e_recover: + default : state_n = e_ready; + endcase + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_ready; + else + state_r <= state_n; + + ///////////////////////////////////////////////////////////////////////////// + // SRAM Control + ///////////////////////////////////////////////////////////////////////////// + + wire do_recover = is_recover & ~yumi_o; + + /////////////////////////// + // Tag Mem Control + /////////////////////////// + + // Tag mem is bypassed if the index is the same on consecutive reads + wire tag_mem_bypass = v_tl_r & decode_tl_r.fetch_op & (vaddr_index == vaddr_index_tl); + wire tag_mem_fast_read = do_recover || yumi_o & decode_lo.fetch_op & ~tag_mem_bypass; + wire tag_mem_fast_write = 1'b0; + wire tag_mem_slow_read = tag_mem_pkt_yumi_o & (tag_mem_pkt_cast_i.opcode == e_cache_tag_mem_read) ; + wire tag_mem_slow_write = tag_mem_pkt_yumi_o & (tag_mem_pkt_cast_i.opcode != e_cache_tag_mem_read); + assign tag_mem_v_li = tag_mem_fast_read | tag_mem_fast_write | tag_mem_slow_read | tag_mem_slow_write; + assign tag_mem_w_li = tag_mem_fast_write | tag_mem_slow_write; + assign tag_mem_addr_li = tag_mem_fast_read + ? do_recover ? vaddr_index_tl : vaddr_index + : tag_mem_pkt_cast_i.index; + assign tag_mem_pkt_yumi_o = tag_mem_pkt_v_i & ~|tag_mem_fast_read; + + logic [assoc_p-1:0] tag_mem_way_one_hot; + bsg_decode + #(.num_out_p(assoc_p)) + tag_mem_way_decode + (.i(tag_mem_pkt_cast_i.way_id) + ,.o(tag_mem_way_one_hot) + ); + + always_comb + for (integer i = 0; i < assoc_p; i++) + case (tag_mem_pkt_cast_i.opcode) + e_cache_tag_mem_set_tag: + begin + tag_mem_data_li[i] = '{state: tag_mem_pkt_cast_i.state, tag: tag_mem_pkt_cast_i.tag}; + tag_mem_w_mask_li[i] = '{state: {$bits(bp_coh_states_e){tag_mem_way_one_hot[i]}} + ,tag : {tag_width_p{tag_mem_way_one_hot[i]}} + }; + end + e_cache_tag_mem_set_state: + begin + tag_mem_data_li[i] = '{state: tag_mem_pkt_cast_i.state, tag: '0}; + tag_mem_w_mask_li[i] = '{state: {$bits(bp_coh_states_e){tag_mem_way_one_hot[i]}}, tag: '0}; + end + e_cache_tag_mem_set_inval: + begin + tag_mem_data_li[i] = '{state: bp_coh_states_e'('0), tag: '0}; + tag_mem_w_mask_li[i] = '{state: bp_coh_states_e'('1), tag: '0}; + end + default: // e_cache_tag_mem_set_clear + begin + tag_mem_data_li[i] = '{state: bp_coh_states_e'('0), tag: '0}; + tag_mem_w_mask_li[i] = '{state: bp_coh_states_e'('1), tag: '1}; + end + endcase + + logic [lg_assoc_lp-1:0] tag_mem_pkt_way_r; + bsg_dff + #(.width_p(lg_assoc_lp)) + tag_mem_pkt_way_reg + (.clk_i(clk_i) + ,.data_i(tag_mem_pkt_cast_i.way_id) + ,.data_o(tag_mem_pkt_way_r) + ); + + assign tag_mem_o = tag_mem_data_lo[tag_mem_pkt_way_r]; + + /////////////////////////// + // Data Mem Control + /////////////////////////// + logic [assoc_p-1:0] vaddr_bank_dec; + bsg_decode + #(.num_out_p(assoc_p)) + bypass_bank_decode + (.i(vaddr_bank) + ,.o(vaddr_bank_dec) + ); + + // During a data mem bypass, only the necessary bank of data memory is read + logic [assoc_p-1:0] data_mem_bypass_select; + bsg_adder_one_hot + #(.width_p(assoc_p)) + data_mem_bank_select_adder + (.a_i(hit_v_tl) + ,.b_i(vaddr_bank_dec) + ,.o(data_mem_bypass_select) + ); + + wire [`BSG_SAFE_CLOG2(fill_width_p)-1:0] write_data_rot_li = data_mem_pkt_cast_i.way_id*bank_width_lp; + // Expand the bank write mask to bank width + logic [fill_width_p-1:0] data_mem_pkt_fill_data_li; + bsg_rotate_left + #(.width_p(fill_width_p)) + write_data_rotate + (.data_i(data_mem_pkt_cast_i.data) + ,.rot_i(write_data_rot_li) + ,.o(data_mem_pkt_fill_data_li) + ); + wire [assoc_p-1:0][bank_width_lp-1:0] data_mem_pkt_data_li = {block_size_in_fill_lp{data_mem_pkt_fill_data_li}}; + + logic [block_size_in_fill_lp-1:0][fill_size_in_bank_lp-1:0] data_mem_pkt_fill_mask_expanded; + bsg_expand_bitmask + #(.in_width_p(block_size_in_fill_lp), .expand_p(fill_size_in_bank_lp)) + fill_mask_expand + (.i(data_mem_pkt_cast_i.fill_index), .o(data_mem_pkt_fill_mask_expanded)); + + logic [assoc_p-1:0] data_mem_write_bank_mask; + wire [`BSG_SAFE_CLOG2(assoc_p)-1:0] write_mask_rot_li = data_mem_pkt_cast_i.way_id; + bsg_rotate_left + #(.width_p(assoc_p)) + write_mask_rotate + (.data_i(data_mem_pkt_fill_mask_expanded) + ,.rot_i(write_mask_rot_li) + ,.o(data_mem_write_bank_mask) + ); + + wire data_mem_bypass = v_tl_r & decode_tl_r.fetch_op & (vaddr_index == vaddr_index_tl) && (vaddr_vtag == vaddr_vtag_tl); + + logic [assoc_p-1:0] data_mem_fast_read, data_mem_fast_write, data_mem_slow_read, data_mem_slow_write; + for (genvar i = 0; i < assoc_p; i++) + begin : data_mem_lines + assign data_mem_slow_read[i] = data_mem_pkt_yumi_o & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_read); + assign data_mem_slow_write[i] = data_mem_pkt_yumi_o & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_write) & data_mem_write_bank_mask[i]; + + assign data_mem_fast_read[i] = do_recover || yumi_o & decode_lo.fetch_op & (~data_mem_bypass | data_mem_bypass_select[i]); + + assign data_mem_v_li[i] = data_mem_fast_read[i] | data_mem_slow_read[i] | data_mem_slow_write[i]; + assign data_mem_w_li[i] = data_mem_slow_write[i]; + wire [bindex_width_lp-1:0] data_mem_pkt_offset = (bindex_width_lp'(i) - data_mem_pkt_cast_i.way_id); + assign data_mem_addr_li[i] = data_mem_fast_read[i] + ? do_recover ? {vaddr_index_tl, {(assoc_p>1){vaddr_bank_tl}}} : {vaddr_index, {(assoc_p > 1){vaddr_bank}}} + : {data_mem_pkt_cast_i.index, {(assoc_p > 1){data_mem_pkt_offset}}}; + assign data_mem_data_li[i] = data_mem_pkt_data_li[i]; + end + assign data_mem_pkt_yumi_o = (data_mem_pkt_cast_i.opcode == e_cache_data_mem_uncached) + ? data_mem_pkt_v_i + : data_mem_pkt_v_i & ~|data_mem_fast_read; + + logic [lg_assoc_lp-1:0] data_mem_pkt_way_r; + bsg_dff + #(.width_p(lg_assoc_lp)) + data_mem_pkt_way_reg + (.clk_i(clk_i) + ,.data_i(data_mem_pkt_cast_i.way_id) + ,.data_o(data_mem_pkt_way_r) + ); + + wire [`BSG_SAFE_CLOG2(block_width_p)-1:0] read_data_rot_li = data_mem_pkt_way_r*bank_width_lp; + bsg_rotate_right + #(.width_p(block_width_p)) + read_data_rotate + (.data_i(data_mem_data_lo) + ,.rot_i(read_data_rot_li) + ,.o(data_mem_o) + ); + + /////////////////////////// + // Stat Mem Control + /////////////////////////// + wire stat_mem_fast_read = ~uncached_tv_r & cache_req_yumi_i; + wire stat_mem_fast_write = ~uncached_tv_r & yumi_i; + wire stat_mem_slow_write = stat_mem_pkt_v_i & (stat_mem_pkt_cast_i.opcode != e_cache_stat_mem_read); + assign stat_mem_pkt_yumi_o = stat_mem_pkt_v_i & ~stat_mem_fast_write & ~stat_mem_fast_read; + assign stat_mem_v_li = stat_mem_fast_read | stat_mem_fast_write | stat_mem_pkt_yumi_o; + assign stat_mem_w_li = stat_mem_fast_write | (stat_mem_pkt_yumi_o & stat_mem_slow_write); + assign stat_mem_addr_li = (stat_mem_fast_write | stat_mem_fast_read) + ? paddr_tv_r[block_offset_width_lp+:sindex_width_lp] + : stat_mem_pkt_cast_i.index; + + logic [`BSG_SAFE_MINUS(assoc_p, 2):0] lru_decode_data_lo, lru_decode_mask_lo; + bsg_lru_pseudo_tree_decode + #(.ways_p(assoc_p)) + lru_decode + (.way_id_i(hit_index_tv) + ,.data_o(lru_decode_data_lo) + ,.mask_o(lru_decode_mask_lo) + ); + + assign stat_mem_data_li.lru = stat_mem_fast_write ? lru_decode_data_lo : '0; + assign stat_mem_mask_li.lru = stat_mem_fast_write ? lru_decode_mask_lo : '1; + + assign stat_mem_o = stat_mem_data_lo; + + ///////////////////////////////////////////////////////////////////////////// + // Snoop Logic + ///////////////////////////////////////////////////////////////////////////// + wire [assoc_p-1:0] pseudo_hit = + (data_mem_pkt_v_i << data_mem_pkt_cast_i.way_id) | (tag_mem_pkt_v_i << tag_mem_pkt_cast_i.way_id); + assign snoop_hit = pseudo_hit; + assign snoop_way = pseudo_hit; + assign snoop_data = data_mem_data_li; + assign snoop_spec = spec_tv_r; + assign snoop_uncached = uncached_tv_r; + assign snoop_decode = decode_tv_r; + assign snoop_bank_sel_one_hot = bank_sel_one_hot_tv_r; + + // synopsys translate_off + if (`BSG_SAFE_CLOG2(block_width_p*sets_p/8) > page_offset_width_gp) begin + $error("Cache way size must be at most 4kB"); + end + + if (!(`BSG_IS_POW2(assoc_p))) + $error("Associativity must be power of two"); + // synopsys translate_on + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_icache_defines.svh b/designs/black-parrot/src/bp/bp_fe_icache_defines.svh new file mode 100644 index 0000000..c589bd2 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_icache_defines.svh @@ -0,0 +1,22 @@ +`ifndef BP_FE_ICACHE_DEFINES_SVH +`define BP_FE_ICACHE_DEFINES_SVH + + `define declare_bp_fe_icache_pkt_s(vaddr_width_mp) \ + typedef struct packed \ + { \ + logic [vaddr_width_mp-1:0] vaddr; \ + bp_fe_icache_op_e op; \ + logic spec; \ + } bp_fe_icache_pkt_s + + `define bp_fe_icache_pkt_width(vaddr_width_mp) \ + (1+vaddr_width_mp+$bits(bp_fe_icache_op_e)) + + `define declare_bp_fe_icache_engine_if(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp) \ + `declare_bp_cache_engine_generic_if(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp, fe_icache) + + `define declare_bp_fe_icache_engine_if_widths(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp) \ + `declare_bp_cache_engine_generic_if_widths(addr_width_mp, tag_width_mp, sets_mp, ways_mp, data_width_mp, block_width_mp, fill_width_mp, id_width_mp, icache) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_fe_icache_pkgdef.svh b/designs/black-parrot/src/bp/bp_fe_icache_pkgdef.svh new file mode 100644 index 0000000..a71ce4e --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_icache_pkgdef.svh @@ -0,0 +1,24 @@ +`ifndef BP_FE_ICACHE_PKGDEF_SVH +`define BP_FE_ICACHE_PKGDEF_SVH + + typedef enum + { + e_icache_fetch + ,e_icache_inval + } bp_fe_icache_op_e; + + typedef struct packed + { + logic fetch_op; + logic inval_op; + } bp_fe_icache_decode_s; + + typedef struct packed + { + bp_fe_icache_decode_s decode; + logic uncached; + logic spec; + } bp_fe_icache_req_payload_s; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_fe_nonsynth_icache_tracer.sv b/designs/black-parrot/src/bp/bp_fe_nonsynth_icache_tracer.sv new file mode 100644 index 0000000..df8ac81 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_nonsynth_icache_tracer.sv @@ -0,0 +1,152 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_fe_nonsynth_icache_tracer + import bp_common_pkg::*; + import bp_fe_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + , parameter assoc_p = 8 + , parameter sets_p = 64 + , parameter block_width_p = 512 + , parameter fill_width_p = 512 + , parameter trace_file_p = "icache" + , parameter tag_width_p = icache_tag_width_p + , parameter id_width_p = 1 + , parameter data_width_p = 64 + `declare_bp_fe_icache_engine_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p) + + // Calculated parameters + , localparam mhartid_width_lp = `BSG_SAFE_CLOG2(num_core_p) + , localparam bank_width_lp = block_width_p / assoc_p + , localparam icache_pkt_width_lp = `bp_fe_icache_pkt_width(vaddr_width_p) + ) + (input clk_i + , input reset_i + , input [mhartid_width_lp-1:0] mhartid_i + + , input [icache_pkt_width_lp-1:0] icache_pkt_i + , input v_i + , input force_i + , input yumi_o + + , input [icache_data_width_p-1:0] data_o + , input hit_v_o + + , input [icache_req_width_lp-1:0] cache_req_o + , input cache_req_v_o + , input cache_req_yumi_i + , input cache_req_lock_i + , input [icache_req_metadata_width_lp-1:0] cache_req_metadata_o + , input cache_req_metadata_v_o + , input cache_req_critical_i + , input cache_req_last_i + // Unused + , input cache_req_credits_full_i + , input cache_req_credits_empty_i + + , input data_mem_pkt_v_i + , input [icache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , input data_mem_pkt_yumi_o + , input [block_width_p-1:0] data_mem_o + + , input tag_mem_pkt_v_i + , input [icache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , input tag_mem_pkt_yumi_o + , input [icache_tag_info_width_lp-1:0] tag_mem_o + + , input stat_mem_pkt_v_i + , input [icache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , input stat_mem_pkt_yumi_o + , input [icache_stat_info_width_lp-1:0] stat_mem_o + + , input [paddr_width_p-1:0] paddr_tv_r + ); + + `declare_bp_fe_icache_engine_if(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p); + `declare_bp_fe_icache_pkt_s(vaddr_width_p); + bp_fe_icache_pkt_s icache_pkt_cast_i; + assign icache_pkt_cast_i = icache_pkt_i; + + bp_fe_icache_req_s cache_req_cast_o; + bp_fe_icache_req_metadata_s cache_req_metadata_cast_o; + assign cache_req_cast_o = cache_req_o; + assign cache_req_metadata_cast_o = cache_req_metadata_o; + + bp_fe_icache_data_mem_pkt_s data_mem_pkt_cast_i; + bp_fe_icache_tag_mem_pkt_s tag_mem_pkt_cast_i; + bp_fe_icache_stat_mem_pkt_s stat_mem_pkt_cast_i; + assign data_mem_pkt_cast_i = data_mem_pkt_i; + assign tag_mem_pkt_cast_i = tag_mem_pkt_i; + assign stat_mem_pkt_cast_i = stat_mem_pkt_i; + + logic [assoc_p-1:0][bank_width_lp-1:0] data_mem_cast_o; + bp_fe_icache_tag_info_s tag_mem_info_cast_o; + bp_fe_icache_tag_info_s stat_mem_info_cast_o; + assign data_mem_cast_o = data_mem_o; + assign tag_mem_info_cast_o = tag_mem_o; + assign stat_mem_info_cast_o = stat_mem_o; + + integer file; + string file_name; + always_ff @(negedge reset_i) + begin + file_name = $sformatf("%s_%x.trace", trace_file_p, mhartid_i); + file = $fopen(file_name, "w"); + $fwrite(file, "Coherent L1: %x\n", icache_features_p[e_cfg_coherent]); + end + + logic data_mem_read_r, tag_mem_read_r, stat_mem_read_r; + always_ff @(posedge clk_i) + if (reset_i) + begin + data_mem_read_r <= '0; + tag_mem_read_r <= '0; + stat_mem_read_r <= '0; + end + else + begin + data_mem_read_r <= data_mem_pkt_yumi_o & (data_mem_pkt_cast_i.opcode == e_cache_data_mem_read); + tag_mem_read_r <= tag_mem_pkt_yumi_o & (tag_mem_pkt_cast_i.opcode == e_cache_tag_mem_read); + stat_mem_read_r <= stat_mem_pkt_yumi_o & (stat_mem_pkt_cast_i.opcode == e_cache_stat_mem_read); + end + + always_ff @(posedge clk_i) + begin + if (yumi_o) + $fwrite(file, "%12t | access: %p\n", $time, icache_pkt_cast_i); + + if (data_mem_pkt_yumi_o) + $fwrite(file, "%12t | data_mem_pkt: %p\n", $time, data_mem_pkt_cast_i); + if (data_mem_read_r) + $fwrite(file, "%12t | data_mem_read: %x\n", $time, data_mem_cast_o); + + if (tag_mem_pkt_yumi_o) + $fwrite(file, "%12t | tag_mem_pkt: %p\n", $time, tag_mem_pkt_cast_i); + if (tag_mem_read_r) + $fwrite(file, "%12t | tag_mem_read: %x\n", $time, tag_mem_info_cast_o); + + if (stat_mem_pkt_yumi_o) + $fwrite(file, "%12t | stat_mem_pkt: %p\n", $time, stat_mem_pkt_cast_i); + if (stat_mem_read_r) + $fwrite(file, "%12t | stat_mem_read: %x\n", $time, stat_mem_info_cast_o); + + if (hit_v_o) + $fwrite(file, "%12t | fetch: [%x]->%x\n", $time, paddr_tv_r, data_o); + + if (cache_req_yumi_i) + $fwrite(file, "%12t | cache_req: %p\n", $time, cache_req_cast_o); + + if (cache_req_metadata_v_o) + $fwrite(file, "%12t | cache_req_metadata: %p\n", $time, cache_req_metadata_cast_o); + + if (cache_req_critical_i) + $fwrite(file, "%12t | cache_req_critical_i raised\n", $time); + + if (cache_req_last_i) + $fwrite(file, "%12t | cache_req_last_i raised\n", $time); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_pc_gen.sv b/designs/black-parrot/src/bp/bp_fe_pc_gen.sv new file mode 100644 index 0000000..e4fd0e1 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_pc_gen.sv @@ -0,0 +1,389 @@ +/* + * bp_fe_pc_gen.v + * + * pc_gen provides the pc for the itlb and icache. + * pc_gen also provides the BTB, BHT and RAS indexes for the backend (the queue + * between the frontend and the backend, i.e. the frontend queue). +*/ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_pc_gen + import bp_common_pkg::*; + import bp_fe_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + + , localparam scan_width_lp = $bits(bp_fe_scan_s) + ) + (input clk_i + , input reset_i + + , output logic init_done_o + + , input attaboy_v_i + , input attaboy_force_i + , input [vaddr_width_p-1:0] attaboy_pc_i + , input [branch_metadata_fwd_width_p-1:0] attaboy_br_metadata_fwd_i + , input attaboy_taken_i + , input attaboy_ntaken_i + , output logic attaboy_yumi_o + + , input redirect_v_i + , input [vaddr_width_p-1:0] redirect_pc_i + , input [vaddr_width_p-1:0] redirect_npc_i + , input redirect_br_v_i + , input [branch_metadata_fwd_width_p-1:0] redirect_br_metadata_fwd_i + , input redirect_br_taken_i + , input redirect_br_ntaken_i + , input redirect_br_nonbr_i + + , output logic [vaddr_width_p-1:0] next_pc_o + , input icache_yumi_i + + , output logic ovr_o + , input icache_tv_we_i + + , input icache_hit_v_i + , input icache_miss_v_i + , output logic icache_hit_yumi_o + , input [icache_data_width_p-1:0] icache_data_i + + , output logic if2_hit_v_o + , output logic if2_miss_v_o + , output logic [vaddr_width_p-1:0] if2_pc_o + , output logic [icache_data_width_p-1:0] if2_data_o + , output logic [branch_metadata_fwd_width_p-1:0] if2_br_metadata_fwd_o + , input if2_yumi_i + + , input fetch_yumi_i + , input [scan_width_lp-1:0] fetch_scan_i + , input [vaddr_width_p-1:0] fetch_pc_i + , input [fetch_ptr_p-1:0] fetch_count_i + , input fetch_startup_i + , input fetch_catchup_i + , input fetch_rebase_i + , input fetch_linear_i + , output logic fetch_taken_o + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_fe_branch_metadata_fwd_s(ras_idx_width_p, btb_tag_width_p, btb_idx_width_p, bht_idx_width_p, ghist_width_p, bht_row_els_p); + `bp_cast_i(bp_fe_branch_metadata_fwd_s, redirect_br_metadata_fwd); + `bp_cast_i(bp_fe_branch_metadata_fwd_s, attaboy_br_metadata_fwd); + + ///////////////////////////////////////////////////////////////////////////////////// + // IF0 + ///////////////////////////////////////////////////////////////////////////////////// + logic [ghist_width_p-1:0] ghistory_n, ghistory_r; + + logic [vaddr_width_p-1:0] next_pc; + logic [bht_row_width_p-1:0] bht_row_lo; + logic bht_pred_lo; + logic [vaddr_width_p-1:0] btb_br_tgt_lo; + logic btb_br_tgt_v_lo, btb_br_tgt_jmp_lo; + + /////////////////////////// + // Next PC calculation + /////////////////////////// + bp_fe_branch_metadata_fwd_s next_metadata, ovr_metadata; + logic next_pred, next_taken; + logic ovr_ret, ovr_btaken, ovr_jmp, ovr_rebase, ovr_linear, btb_taken; + logic [vaddr_width_p-1:0] pc_plus; + logic [vaddr_width_p-1:0] ras_tgt_lo, taken_tgt_lo, ntaken_tgt_lo, linear_tgt_lo; + logic [ras_idx_width_p-1:0] ras_next, ras_tos; + logic [btb_tag_width_p-1:0] btb_tag; + logic [btb_idx_width_p-1:0] btb_idx; + logic [bht_idx_width_p-1:0] bht_idx; + logic [bht_offset_width_p-1:0] bht_offset; + + // Note: "if" chain duplicated in in bp_fe_nonsynth_pc_gen_tracer.sv + always_comb begin + if (redirect_v_i) + begin + next_pred = 1'b0; + next_taken = redirect_br_taken_i; + next_pc = redirect_npc_i; + + next_metadata = redirect_br_metadata_fwd_cast_i; + end + else if (ovr_o) + begin + next_pred = ovr_btaken; + next_taken = ovr_ret | ovr_btaken | ovr_jmp; + next_pc = ovr_ret ? ras_tgt_lo : (ovr_btaken | ovr_jmp) ? taken_tgt_lo : ovr_rebase ? ntaken_tgt_lo : linear_tgt_lo; + + next_metadata = ovr_metadata; + next_metadata.src_ras = ovr_ret; + end + else + begin + next_pred = bht_pred_lo; + next_taken = btb_taken; + next_pc = btb_taken ? btb_br_tgt_lo : pc_plus; + + next_metadata = '0; + next_metadata.src_btb = btb_br_tgt_v_lo; + next_metadata.bht_row = bht_row_lo; + next_metadata.ghist = ghistory_r; + next_metadata.btb_tag = btb_tag; + next_metadata.btb_idx = btb_idx; + next_metadata.bht_idx = bht_idx; + next_metadata.bht_offset = bht_offset; + end + end + assign next_pc_o = next_pc; + + /////////////////////////// + // BTB + /////////////////////////// + logic btb_w_yumi_lo, btb_init_done_lo; + wire btb_r_v_li = icache_yumi_i; + wire btb_w_v_li = (redirect_br_v_i & redirect_br_taken_i & ~redirect_br_metadata_fwd_cast_i.src_btb & ~redirect_br_metadata_fwd_cast_i.src_ras) + | (redirect_br_v_i & redirect_br_taken_i & redirect_br_metadata_fwd_cast_i.src_btb & ~redirect_br_metadata_fwd_cast_i.src_ras) + | (attaboy_v_i & attaboy_taken_i & ~attaboy_br_metadata_fwd_cast_i.src_btb & ~attaboy_br_metadata_fwd_cast_i.src_ras) + | (redirect_br_v_i & redirect_br_taken_i & redirect_br_metadata_fwd_cast_i.src_btb & redirect_br_metadata_fwd_cast_i.src_ras) + | (redirect_br_v_i & redirect_br_nonbr_i & redirect_br_metadata_fwd_cast_i.src_btb); + wire btb_w_force_li = redirect_br_v_i | attaboy_force_i; + wire btb_clr_li = (redirect_br_v_i & redirect_br_taken_i & redirect_br_metadata_fwd_cast_i.src_btb & redirect_br_metadata_fwd_cast_i.src_ras) + | (redirect_br_v_i & redirect_br_nonbr_i & redirect_br_metadata_fwd_cast_i.src_btb); + wire btb_jmp_li = redirect_br_v_i ? (redirect_br_metadata_fwd_cast_i.site_jal | redirect_br_metadata_fwd_cast_i.site_jalr) : (attaboy_br_metadata_fwd_cast_i.site_jal | attaboy_br_metadata_fwd_cast_i.site_jalr); + wire [btb_tag_width_p-1:0] btb_tag_li = redirect_br_v_i ? redirect_br_metadata_fwd_cast_i.btb_tag : attaboy_br_metadata_fwd_cast_i.btb_tag; + wire [btb_idx_width_p-1:0] btb_idx_li = redirect_br_v_i ? redirect_br_metadata_fwd_cast_i.btb_idx : attaboy_br_metadata_fwd_cast_i.btb_idx; + wire [vaddr_width_p-1:0] btb_tgt_li = redirect_br_v_i ? redirect_pc_i : attaboy_pc_i; + wire [vaddr_width_p-1:0] btb_r_addr_li = next_pc; + + bp_fe_btb + #(.bp_params_p(bp_params_p)) + btb + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.r_addr_i(btb_r_addr_li) + ,.r_v_i(btb_r_v_li) + ,.r_idx_o(btb_idx) + ,.r_tag_o(btb_tag) + ,.r_tgt_o(btb_br_tgt_lo) + ,.r_tgt_v_o(btb_br_tgt_v_lo) + ,.r_tgt_jmp_o(btb_br_tgt_jmp_lo) + + ,.w_v_i(btb_w_v_li) + ,.w_force_i(btb_w_force_li) + ,.w_clr_i(btb_clr_li) + ,.w_jmp_i(btb_jmp_li) + ,.w_tag_i(btb_tag_li) + ,.w_idx_i(btb_idx_li) + ,.w_tgt_i(btb_tgt_li) + ,.w_yumi_o(btb_w_yumi_lo) + + ,.init_done_o(btb_init_done_lo) + ); + + /////////////////////////// + // BHT + /////////////////////////// + wire bht_r_v_li = icache_yumi_i; + wire [vaddr_width_p-1:0] bht_r_addr_li = next_pc; + wire [ghist_width_p-1:0] bht_r_ghist_li = ghistory_n; + wire bht_w_v_li = + (redirect_br_v_i & redirect_br_metadata_fwd_cast_i.site_br) | (attaboy_v_i & attaboy_br_metadata_fwd_cast_i.site_br); + wire bht_w_force_li = redirect_br_v_i | attaboy_force_i; + wire [bht_idx_width_p-1:0] bht_w_idx_li = + redirect_br_v_i ? redirect_br_metadata_fwd_cast_i.bht_idx : attaboy_br_metadata_fwd_cast_i.bht_idx; + wire [bht_offset_width_p-1:0] bht_w_offset_li = + redirect_br_v_i ? redirect_br_metadata_fwd_cast_i.bht_offset : attaboy_br_metadata_fwd_cast_i.bht_offset; + wire [ghist_width_p-1:0] bht_w_ghist_li = + redirect_br_v_i ? redirect_br_metadata_fwd_cast_i.ghist : attaboy_br_metadata_fwd_cast_i.ghist; + wire [bht_row_width_p-1:0] bht_row_li = + redirect_br_v_i ? redirect_br_metadata_fwd_cast_i.bht_row : attaboy_br_metadata_fwd_cast_i.bht_row; + logic bht_w_yumi_lo, bht_init_done_lo; + bp_fe_bht + #(.bp_params_p(bp_params_p)) + bht + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.r_v_i(bht_r_v_li) + ,.r_addr_i(bht_r_addr_li) + ,.r_ghist_i(bht_r_ghist_li) + ,.r_val_o(bht_row_lo) + ,.r_pred_o(bht_pred_lo) + ,.r_idx_o(bht_idx) + ,.r_offset_o(bht_offset) + + ,.w_v_i(bht_w_v_li) + ,.w_force_i(bht_w_force_li) + ,.w_idx_i(bht_w_idx_li) + ,.w_offset_i(bht_w_offset_li) + ,.w_ghist_i(bht_w_ghist_li) + ,.w_correct_i(attaboy_yumi_o) + ,.w_val_i(bht_row_li) + ,.w_yumi_o(bht_w_yumi_lo) + + ,.init_done_o(bht_init_done_lo) + ); + + ///////////////////////////////////////////////////////////////////////////////////// + // IF1 + ///////////////////////////////////////////////////////////////////////////////////// + bp_fe_branch_metadata_fwd_s metadata_if1_r; + logic pred_if1_r, taken_if1_r; + logic [vaddr_width_p-1:0] pc_if1, pc_if1_r, pc_if1_aligned; + bsg_dff_reset_en + #(.width_p(2+branch_metadata_fwd_width_p+vaddr_width_p)) + if1_stage_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(icache_yumi_i) + + ,.data_i({next_pred, next_taken, next_metadata, next_pc}) + ,.data_o({pred_if1_r, taken_if1_r, metadata_if1_r, pc_if1_r}) + ); + + // Scan fetched instruction + bp_fe_scan_s fetch_scan; + assign fetch_scan = fetch_scan_i; + + // Set the site type as it arrives in IF2 + bp_fe_branch_metadata_fwd_s metadata_if1; + always_comb + begin + metadata_if1 = metadata_if1_r; + + if (fetch_yumi_i) + begin + metadata_if1.site_br = fetch_scan.br; + metadata_if1.site_jal = fetch_scan.jal; + metadata_if1.site_jalr = fetch_scan.jalr; + metadata_if1.site_call = fetch_scan.call; + metadata_if1.site_return = fetch_scan._return; + end + end + assign ovr_metadata = metadata_if1; + + localparam icache_bytes_lp = icache_data_width_p >> 3; + assign pc_if1_aligned = `bp_addr_align(pc_if1_r, icache_bytes_lp); + assign pc_if1 = fetch_catchup_i ? ntaken_tgt_lo : pc_if1_r; + + assign btb_taken = btb_br_tgt_v_lo & (bht_pred_lo | btb_br_tgt_jmp_lo); + assign pc_plus = pc_if1_aligned + icache_bytes_lp; + + ///////////////////////////////////////////////////////////////////////////////////// + // IF2 + ///////////////////////////////////////////////////////////////////////////////////// + bp_fe_branch_metadata_fwd_s metadata_if2_n, metadata_if2_r, metadata_if2; + logic pred_if2_r, taken_if2_r; + logic [vaddr_width_p-1:0] pc_if2, pc_if2_r, pc_if2_aligned; + + assign metadata_if2_n = fetch_startup_i ? metadata_if2 : metadata_if1; + bsg_dff_reset_en + #(.width_p(2+vaddr_width_p+branch_metadata_fwd_width_p)) + if2_stage_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(icache_tv_we_i | fetch_catchup_i) + + ,.data_i({pred_if1_r, taken_if1_r, pc_if1, metadata_if2_n}) + ,.data_o({pred_if2_r, taken_if2_r, pc_if2_r, metadata_if2_r}) + ); + + always_comb + begin + metadata_if2 = metadata_if2_r; + + metadata_if2.ras_next = ras_next; + metadata_if2.ras_tos = ras_tos; + end + + assign pc_if2 = pc_if2_r; + assign pc_if2_aligned = `bp_addr_align(pc_if2, icache_bytes_lp); + + assign if2_hit_v_o = icache_hit_v_i; + assign if2_miss_v_o = icache_miss_v_i; + assign if2_pc_o = pc_if2_r; + assign if2_data_o = icache_data_i; + assign if2_br_metadata_fwd_o = metadata_if2; + assign icache_hit_yumi_o = icache_hit_v_i & if2_yumi_i; + + /////////////////////////// + // RAS Storage + /////////////////////////// + logic ras_init_done_lo; + logic ras_valid_lo, ras_call_li, ras_return_li; + logic [vaddr_width_p-1:0] ras_addr_li; + + wire ras_w_v_li = redirect_br_v_i; + wire [ras_idx_width_p-1:0] ras_w_next_li = redirect_br_metadata_fwd_cast_i.ras_next; + wire [ras_idx_width_p-1:0] ras_w_tos_li = redirect_br_metadata_fwd_cast_i.ras_tos; + bp_fe_ras + #(.bp_params_p(bp_params_p)) + ras + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.init_done_o(ras_init_done_lo) + + ,.restore_i(ras_w_v_li) + ,.w_next_i(ras_w_next_li) + ,.w_tos_i(ras_w_tos_li) + + ,.call_i(ras_call_li) + ,.addr_i(ras_addr_li) + + ,.v_o(ras_valid_lo) + ,.tgt_o(ras_tgt_lo) + ,.next_o(ras_next) + ,.tos_o(ras_tos) + ,.return_i(ras_return_li) + ); + + assign linear_tgt_lo = fetch_pc_i + fetch_scan.linear_imm; + assign ntaken_tgt_lo = fetch_pc_i + fetch_scan.ntaken_imm; + assign taken_tgt_lo = fetch_pc_i + fetch_scan.taken_imm; + + assign ras_call_li = fetch_yumi_i & fetch_scan.call; + assign ras_return_li = fetch_yumi_i & fetch_scan._return; + assign ras_addr_li = ntaken_tgt_lo; + + // Override calculations + wire btb_miss_ras = pc_if1_r != ras_tgt_lo; + wire btb_miss_br = pc_if1_r != taken_tgt_lo; + wire rebase_miss = !taken_if1_r; + wire linear_miss = taken_if1_r; + + assign ovr_ret = btb_miss_ras & fetch_scan._return & ras_valid_lo; + assign ovr_btaken = btb_miss_br & fetch_scan.br & pred_if1_r; + assign ovr_jmp = btb_miss_br & fetch_scan.jal; + assign ovr_linear = linear_miss & fetch_linear_i; + assign ovr_rebase = rebase_miss & fetch_rebase_i; + assign ovr_o = ovr_btaken | ovr_jmp | ovr_ret | ovr_linear | ovr_rebase; + + assign fetch_taken_o = taken_if1_r | ovr_ret | ovr_btaken | ovr_jmp; + + assign attaboy_yumi_o = attaboy_v_i & ~(bht_w_v_li & ~bht_w_yumi_lo) & ~(btb_w_v_li & ~btb_w_yumi_lo); + assign init_done_o = bht_init_done_lo & btb_init_done_lo & ras_init_done_lo; + + /////////////////////////// + // Global history + /////////////////////////// + assign ghistory_n = redirect_br_v_i + ? redirect_br_metadata_fwd_cast_i.ghist + : metadata_if1.site_br & ~ovr_o + ? {ghistory_r[0+:ghist_width_p-1], taken_if1_r} + : ghistory_r; + wire ghistory_w_v = redirect_br_v_i | icache_tv_we_i; + bsg_dff_reset_en + #(.width_p(ghist_width_p)) + ghist_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(ghistory_w_v) + + ,.data_i(ghistory_n) + ,.data_o(ghistory_r) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_pc_gen_pkgdef.svh b/designs/black-parrot/src/bp/bp_fe_pc_gen_pkgdef.svh new file mode 100644 index 0000000..411ae8c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_pc_gen_pkgdef.svh @@ -0,0 +1,36 @@ + +`ifndef BP_FE_PC_GEN_PKGDEF_SVH +`define BP_FE_PC_GEN_PKGDEF_SVH + + import bp_common_pkg::*; + + typedef struct packed + { + logic br; + logic jal; + logic jalr; + logic call; + logic _return; + logic full1; + logic full2; + logic comp; + logic [38:0] imm; + } bp_fe_decode_s; + + typedef struct packed + { + logic startup; + logic catchup; + logic rebase; + logic br; + logic jal; + logic jalr; + logic call; + logic _return; + logic [38:0] linear_imm; + logic [38:0] ntaken_imm; + logic [38:0] taken_imm; + } bp_fe_scan_s; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_fe_pkg.sv b/designs/black-parrot/src/bp/bp_fe_pkg.sv new file mode 100644 index 0000000..e82602c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_pkg.sv @@ -0,0 +1,8 @@ + +package bp_fe_pkg; + + `include "bp_fe_icache_pkgdef.svh" + `include "bp_fe_pc_gen_pkgdef.svh" + +endpackage + diff --git a/designs/black-parrot/src/bp/bp_fe_ras.sv b/designs/black-parrot/src/bp/bp_fe_ras.sv new file mode 100644 index 0000000..ac8e7a5 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_ras.sv @@ -0,0 +1,116 @@ +/* + * bp_fe_ras.sv + */ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_ras + import bp_common_pkg::*; + import bp_fe_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input clk_i + , input reset_i + + , output logic init_done_o + + , input restore_i + , input [ras_idx_width_p-1:0] w_next_i + , input [ras_idx_width_p-1:0] w_tos_i + + , input call_i + , input [vaddr_width_p-1:0] addr_i + + , output logic v_o + , output logic [vaddr_width_p-1:0] tgt_o + , output logic [ras_idx_width_p-1:0] next_o + , output logic [ras_idx_width_p-1:0] tos_o + , input return_i + ); + + /////////////////////// + // Initialization state machine + enum logic [1:0] {e_reset, e_clear, e_run} state_n, state_r; + wire is_reset = (state_r == e_reset); + wire is_clear = (state_r == e_clear); + wire is_run = (state_r == e_run); + + assign init_done_o = is_run; + + localparam ras_els_lp = 2**ras_idx_width_p; + logic [`BSG_WIDTH(ras_els_lp)-1:0] init_cnt; + bsg_counter_clear_up + #(.max_val_p(ras_els_lp), .init_val_p(0)) + init_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(1'b0) + ,.up_i(is_clear) + ,.count_o(init_cnt) + ); + wire finished_init = (init_cnt == ras_els_lp-1'b1); + + always_comb + case (state_r) + e_clear: state_n = finished_init ? e_run : e_clear; + e_run : state_n = e_run; + // e_reset + default: state_n = e_clear; + endcase + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + + logic [ras_idx_width_p-1:0] next_n, next_r; + logic [ras_idx_width_p-1:0] tos_n, tos_r; + logic [ras_idx_width_p-1:0] nos_lo; + logic [vaddr_width_p-1:0] tgt_lo; + + // Algorithm taken from "Recovery Requirements of Branch Prediction Storage + // Structures in the Presence of Mispredicted-Path Execution" + assign next_n = restore_i ? w_next_i : call_i ? (next_r+1'b1) : next_r; + assign tos_n = restore_i ? w_tos_i : call_i ? (next_r+1'b0) : return_i ? nos_lo : tos_r; + bsg_dff_reset + #(.width_p(2*ras_idx_width_p)) + ptr_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i({next_n, tos_n}) + ,.data_o({next_r, tos_r}) + ); + + wire w_v_li = is_run ? call_i : 1'b1; + wire [ras_idx_width_p-1:0] w_addr_li = is_run ? next_r : init_cnt; + wire [ras_idx_width_p+vaddr_width_p-1:0] w_data_li = is_run ? {tos_r, addr_i} : '0; + + // Needs to push/pop at the same time to comply with RISC-V hints, preventing + // hardening. But, we expect this to be a fairly small structure + bsg_mem_1r1w + #(.width_p(ras_idx_width_p+vaddr_width_p), .els_p(ras_els_lp), .read_write_same_addr_p(1)) + mem + (.w_clk_i(clk_i) + ,.w_reset_i(reset_i) + ,.w_v_i(w_v_li) + ,.w_addr_i(w_addr_li) + ,.w_data_i(w_data_li) + ,.r_v_i(return_i) + ,.r_addr_i(tos_r) + ,.r_data_o({nos_lo, tgt_lo}) + ); + assign tgt_o = tgt_lo; + assign next_o = next_r; + assign tos_o = tos_r; + + // Keeping track is more overhead than correcting misaligned stacks. See: + // "Improving Prediction for Procedure Returns with Return-Address-Stack Repair Mechanisms" + assign v_o = 1'b1; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_realigner.sv b/designs/black-parrot/src/bp/bp_fe_realigner.sv new file mode 100644 index 0000000..daf8f65 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_realigner.sv @@ -0,0 +1,105 @@ + /* + * bp_fe_realigner.sv + * + * 32-bit I$ output buffer which reconstructs 32-bit instructions fetched as two halves. + * Passes through the input data unmodified when the fetch is aligned. + */ +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_realigner + import bp_common_pkg::*; + import bp_fe_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam icache_cinstr_lp = icache_data_width_p / cinstr_width_gp + , localparam icache_sel_lp = `BSG_SAFE_CLOG2(icache_cinstr_lp) + , localparam scan_width_lp = $bits(bp_fe_scan_s) + ) + (input clk_i + , input reset_i + + // Fetch PC and I$ data + , input if2_hit_v_i + , input if2_miss_v_i + , input [vaddr_width_p-1:0] if2_pc_i + , input [icache_cinstr_lp-1:0][cinstr_width_gp-1:0] if2_data_i + , input [branch_metadata_fwd_width_p-1:0] if2_br_metadata_fwd_i + , output logic if2_yumi_o + + // Redirection from backend + // and whether to restore the instruction data + // and PC to resume a fetch + , input redirect_v_i + , input [vaddr_width_p-1:0] redirect_pc_i + , input [cinstr_width_gp-1:0] redirect_instr_i + , input [branch_metadata_fwd_width_p-1:0] redirect_br_metadata_fwd_i + , input redirect_resume_i + + // Assembled instruction, PC and count + , output logic assembled_v_o + , output logic [vaddr_width_p-1:0] assembled_pc_o + , output logic [fetch_cinstr_p-1:0][cinstr_width_gp-1:0] assembled_instr_o + , output logic [branch_metadata_fwd_width_p-1:0] assembled_br_metadata_fwd_o + , output logic [fetch_ptr_p-1:0] assembled_count_o + , output logic assembled_partial_o + , input [fetch_ptr_p-1:0] assembled_count_i + , input assembled_yumi_i + ); + + `declare_bp_fe_branch_metadata_fwd_s(ras_idx_width_p, btb_tag_width_p, btb_idx_width_p, bht_idx_width_p, ghist_width_p, bht_row_els_p); + + logic partial_w_v, partial_v_n, partial_v_r; + logic [vaddr_width_p-1:0] partial_pc_n, partial_pc_r; + logic [cinstr_width_gp-1:0] partial_instr_n, partial_instr_r; + + wire [icache_sel_lp-1:0] if2_pc_sel = if2_pc_i[1+:icache_sel_lp]; + wire [fetch_width_p-1:0] if2_shift = if2_pc_sel << 3'd4; + wire [fetch_width_p-1:0] if2_instr = if2_data_i >> if2_shift; + wire [fetch_ptr_p-1:0] if2_count = if2_hit_v_i ? (icache_cinstr_lp - if2_pc_sel) : 1'b0; + + bsg_dff_reset_en + #(.width_p(cinstr_width_gp+vaddr_width_p+1)) + partial_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(partial_w_v) + + ,.data_i({partial_instr_n, partial_pc_n, partial_v_n}) + ,.data_o({partial_instr_r, partial_pc_r, partial_v_r}) + ); + + wire [vaddr_width_p-1:0] realigned_pc = partial_pc_r; + wire [fetch_cinstr_p:0][cinstr_width_gp-1:0] realigned_instr = {if2_data_i, partial_instr_r}; + wire [fetch_ptr_p-1:0] realigned_count = if2_hit_v_i ? fetch_cinstr_p : 1'b1; + + // Store leftover into realigner + wire partial_store = (assembled_count_o - assembled_count_i == 2'd1); + // Drain leftover from realigner + wire partial_drain = (assembled_count_o - assembled_count_i > 2'd1); + + assign partial_w_v = redirect_v_i + | assembled_yumi_i + | if2_yumi_o; + assign partial_v_n = redirect_v_i ? redirect_resume_i + : assembled_yumi_i ? partial_store + : partial_v_r; + assign partial_pc_n = redirect_v_i ? redirect_pc_i + : assembled_yumi_i ? assembled_pc_o + (assembled_count_i << 1'b1) + : if2_pc_i; + assign partial_instr_n = redirect_v_i ? redirect_instr_i + : assembled_yumi_i ? if2_data_i[icache_cinstr_lp-1] + : if2_data_i[icache_cinstr_lp-1]; + + assign assembled_pc_o = partial_v_r ? realigned_pc : if2_pc_i; + assign assembled_instr_o = partial_v_r ? realigned_instr : if2_instr; + assign assembled_br_metadata_fwd_o = if2_br_metadata_fwd_i; + assign assembled_count_o = partial_v_r ? realigned_count : if2_count; + assign assembled_partial_o = partial_v_r; + + assign assembled_v_o = if2_hit_v_i | if2_miss_v_i; + assign if2_yumi_o = if2_hit_v_i & ~partial_drain & assembled_yumi_i; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_scan.sv b/designs/black-parrot/src/bp/bp_fe_scan.sv new file mode 100644 index 0000000..0dc4cda --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_scan.sv @@ -0,0 +1,204 @@ +/* + * bp_fe_instr_scan.v + * + * Instr scan check if the intruction is aligned, compressed, or normal instruction. + * The entire block is implemented in combinational logic, achieved within one cycle. +*/ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_scan + import bp_common_pkg::*; + import bp_fe_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam decode_width_lp = $bits(bp_fe_decode_s) + , localparam scan_width_lp = $bits(bp_fe_scan_s) + ) + (input assembled_v_i + , input [vaddr_width_p-1:0] assembled_pc_i + , input [fetch_cinstr_p-1:0][cinstr_width_gp-1:0] assembled_instr_i + , input [branch_metadata_fwd_width_p-1:0] assembled_br_metadata_fwd_i + , input [fetch_ptr_p-1:0] assembled_count_i + , input assembled_partial_i + , output logic [fetch_ptr_p-1:0] assembled_count_o + , output logic assembled_yumi_o + + , output logic fetch_v_o + , output logic [vaddr_width_p-1:0] fetch_pc_o + , output logic [fetch_width_p-1:0] fetch_instr_o + , output logic [branch_metadata_fwd_width_p-1:0] fetch_br_metadata_fwd_o + , output logic [fetch_ptr_p-1:0] fetch_count_o + , output logic fetch_partial_o + , output logic [scan_width_lp-1:0] fetch_scan_o + , output logic fetch_startup_o + , output logic fetch_catchup_o + , output logic fetch_rebase_o + , output logic fetch_linear_o + , input fetch_taken_i + , input fetch_yumi_i + ); + + `bp_cast_o(bp_fe_scan_s, fetch_scan); + + bp_fe_decode_s [fetch_cinstr_p : 0] decode_lo; + logic [fetch_cinstr_p :-1][cinstr_width_gp-1:0] instr; + logic [fetch_cinstr_p :-1] full1; + logic [fetch_cinstr_p : 0] branch; + logic [fetch_cinstr_p : 0] complete; + + assign instr = {assembled_instr_i, 16'b0}; + assign full1[-1] = 1'b0; + for (genvar i = 0; i <= fetch_cinstr_p; i++) + begin : scan + rv64_instr_rtype_s curr_instr; + + wire is_full1 = assembled_v_i && (i < assembled_count_i) && full1[i]; + wire is_full2 = assembled_v_i && (i < assembled_count_i) && full1[i-1]; + wire is_comp = assembled_v_i && (i < assembled_count_i) && !full1[i] & !full1[i-1]; + + assign curr_instr = is_full2 ? {instr[i], instr[i-1]} : instr[i]; + wire is_br = is_full2 && curr_instr inside {`RV64_BRANCH}; + wire is_jal = is_full2 && curr_instr inside {`RV64_JAL}; + wire is_jalr = is_full2 && curr_instr inside {`RV64_JALR}; + + wire is_link_dest = curr_instr.rd_addr inside {5'h1, 5'h5}; + wire is_link_src = curr_instr.rs1_addr inside {5'h1, 5'h5}; + wire is_link_match = is_link_src & is_link_dest & (curr_instr.rd_addr == curr_instr.rs1_addr); + wire is_call = (is_jal | is_jalr) & is_link_dest; + wire is_return = is_jalr & is_link_src & !is_link_match; + + wire is_cbr = is_comp && curr_instr inside {`RV64_CBEQZ, `RV64_CBNEZ}; + wire is_cj = is_comp && curr_instr inside {`RV64_CJ}; + wire is_cjr = is_comp && curr_instr inside {`RV64_CJR}; + wire is_cjalr = is_comp && curr_instr inside {`RV64_CJALR}; + + wire is_clink_dest = is_cjalr; + wire is_clink_src = curr_instr.rd_addr inside {5'h1, 5'h5}; + wire is_clink_match = is_clink_src & is_clink_dest & {curr_instr.rd_addr == 5'h1}; + wire is_ccall = (is_cj | is_cjr | is_cjalr) & is_clink_dest; + wire is_creturn = (is_cjr | is_cjalr) & is_clink_src & !is_clink_match; + + logic [vaddr_width_p-1:0] imm; + always_comb + if (is_br ) imm = `rv64_signext_b_imm(curr_instr ) + ((i - 1'b1) << 1'b1); + else if (is_jal) imm = `rv64_signext_j_imm(curr_instr ) + ((i - 1'b1) << 1'b1); + else if (is_cj ) imm = `rv64_signext_cj_imm(curr_instr) + ((i - 1'b0) << 1'b1); + else // if (is_cbr ) + imm = `rv64_signext_cb_imm(curr_instr) + ((i - 1'b0) << 1'b1); + + assign full1[i] = &curr_instr[0+:2] && !full1[i-1]; + assign branch[i] = is_br | is_jal | is_jalr | is_cbr | is_cj | is_cjr | is_cjalr; + assign complete[i] = is_comp || is_full2; + assign decode_lo[i] = + '{br : is_br | is_cbr + ,jal : is_jal | is_cj + ,jalr : is_jalr | is_cjr | is_cjalr + ,call : is_call | is_ccall + ,_return: is_return | is_creturn + ,imm : imm + ,full1 : is_full1 + ,full2 : is_full2 + ,comp : is_comp + }; + end + + logic any_complete; + logic [fetch_sel_p-1:0] complete_addr; + wire [fetch_cinstr_p-1:0] complete_vector = complete; + bsg_priority_encode + #(.width_p(fetch_cinstr_p), .lo_to_hi_p(0)) + complete_pe + (.i(complete_vector) + ,.addr_o(complete_addr) + ,.v_o(any_complete) + ); + wire [fetch_ptr_p-1:0] linear_sel = fetch_cinstr_p - 1'b1 - complete_addr; + wire [fetch_ptr_p-1:0] linear_count = any_complete ? linear_sel + 1'b1 : '0; + + logic any_branch; + logic [fetch_sel_p-1:0] branch_sel; + wire [fetch_cinstr_p-1:0] branch_vector = branch; + bsg_priority_encode + #(.width_p(fetch_cinstr_p), .lo_to_hi_p(1)) + branch_sel_pe + (.i(branch_vector) + ,.addr_o(branch_sel) + ,.v_o(any_branch) + ); + wire [fetch_ptr_p-1:0] branch_count = any_branch ? branch_sel + 1'b1 : '0; + + logic any_last_branch; + logic [fetch_ptr_p-1:0] last_branch_addr; + wire [fetch_cinstr_p :0] last_branch_vector = branch; + bsg_priority_encode + #(.width_p(fetch_cinstr_p+1), .lo_to_hi_p(0)) + second_branch_pe + (.i(last_branch_vector) + ,.addr_o(last_branch_addr) + ,.v_o(any_last_branch) + ); + + wire [fetch_ptr_p-1:0] last_branch_sel = fetch_cinstr_p - last_branch_addr; + wire [fetch_ptr_p-1:0] last_branch_count = any_last_branch ? last_branch_sel + 1'b1 : '0; + wire double_branch = any_branch && (branch_sel != last_branch_sel); + + bp_fe_decode_s branch_decode_lo; + bsg_mux + #(.width_p(decode_width_lp), .els_p(fetch_cinstr_p+1)) + branch_decode_mux + (.data_i(decode_lo) + ,.sel_i(branch_sel) + ,.data_o(branch_decode_lo) + ); + + bp_fe_decode_s next_decode_lo; + wire [fetch_ptr_p-1:0] next_sel = any_branch ? branch_sel+1'b1 : linear_sel+1'b1; + bsg_mux + #(.width_p(decode_width_lp), .els_p(fetch_cinstr_p+1)) + next_decode_mux + (.data_i(decode_lo) + ,.sel_i(next_sel) + ,.data_o(next_decode_lo) + ); + wire [fetch_ptr_p-1:0] next_count = any_complete ? next_sel : 1'b1; + + wire assembled_startup = ~any_branch & ~fetch_taken_i & ('0 == linear_count); + wire assembled_catchup = any_branch & ~fetch_taken_i & (assembled_count_i > branch_count) & ~double_branch; + wire assembled_rebase = any_branch & ~fetch_taken_i & (assembled_count_i > branch_count) & double_branch; + wire assembled_linear = ~any_branch & (assembled_count_i > linear_count); + always_comb + begin + fetch_scan_cast_o = '0; + fetch_scan_cast_o.linear_imm = (linear_count + 1'd1) << 3'b1; + fetch_scan_cast_o.ntaken_imm = (next_count + 1'd0) << 3'b1; + fetch_scan_cast_o.taken_imm = branch_decode_lo.imm; + + if (fetch_yumi_i) + begin + fetch_scan_cast_o.br = branch_decode_lo.br; + fetch_scan_cast_o.jal = branch_decode_lo.jal; + fetch_scan_cast_o.jalr = branch_decode_lo.jalr; + fetch_scan_cast_o.call = branch_decode_lo.call; + fetch_scan_cast_o._return = branch_decode_lo._return; + end + end + + assign fetch_v_o = assembled_v_i; + assign fetch_pc_o = assembled_pc_i; + assign fetch_instr_o = assembled_instr_i; + assign fetch_br_metadata_fwd_o = assembled_br_metadata_fwd_i; + assign fetch_partial_o = assembled_partial_i; + assign fetch_count_o = any_branch ? branch_count : linear_count; + assign fetch_startup_o = fetch_yumi_i & assembled_startup; + assign fetch_catchup_o = fetch_yumi_i & assembled_catchup; + assign fetch_rebase_o = fetch_yumi_i & assembled_rebase; + assign fetch_linear_o = fetch_yumi_i & assembled_linear; + + assign assembled_count_o = any_branch ? (assembled_rebase | fetch_taken_i) ? assembled_count_i : branch_count : linear_count; + assign assembled_yumi_o = fetch_yumi_i; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_fe_top.sv b/designs/black-parrot/src/bp/bp_fe_top.sv new file mode 100644 index 0000000..3b0ec46 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_fe_top.sv @@ -0,0 +1,440 @@ +/* + * bp_fe_top.v + */ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" + +module bp_fe_top + import bp_fe_pkg::*; + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_fe_icache_engine_if_widths(paddr_width_p, icache_tag_width_p, icache_sets_p, icache_assoc_p, icache_data_width_p, icache_block_width_p, icache_fill_width_p, icache_req_id_width_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + , input [fe_cmd_width_lp-1:0] fe_cmd_i + , input fe_cmd_v_i + , output logic fe_cmd_yumi_o + + , output logic [fe_queue_width_lp-1:0] fe_queue_o + , output logic fe_queue_v_o + , input fe_queue_ready_and_i + + , output logic [icache_req_width_lp-1:0] cache_req_o + , output logic cache_req_v_o + , input cache_req_yumi_i + , input cache_req_lock_i + , output logic [icache_req_metadata_width_lp-1:0] cache_req_metadata_o + , output logic cache_req_metadata_v_o + , input [icache_req_id_width_p-1:0] cache_req_id_i + , input cache_req_critical_i + , input cache_req_last_i + , input cache_req_credits_full_i + , input cache_req_credits_empty_i + + , input [icache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i + , input data_mem_pkt_v_i + , output logic data_mem_pkt_yumi_o + , output logic [icache_block_width_p-1:0] data_mem_o + + , input [icache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_i + , input tag_mem_pkt_v_i + , output logic tag_mem_pkt_yumi_o + , output logic [icache_tag_info_width_lp-1:0] tag_mem_o + + , input [icache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i + , input stat_mem_pkt_v_i + , output logic stat_mem_pkt_yumi_o + , output logic [icache_stat_info_width_lp-1:0] stat_mem_o + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_fe_branch_metadata_fwd_s(ras_idx_width_p, btb_tag_width_p, btb_idx_width_p, bht_idx_width_p, ghist_width_p, bht_row_els_p); + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + + logic [rv64_priv_width_gp-1:0] shadow_priv_n, shadow_priv_r; + logic shadow_priv_w; + bsg_dff_reset_en_bypass + #(.width_p(rv64_priv_width_gp)) + shadow_priv_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(shadow_priv_w) + ,.data_i(shadow_priv_n) + ,.data_o(shadow_priv_r) + ); + + logic shadow_translation_en_n, shadow_translation_en_r; + logic shadow_translation_en_w; + bsg_dff_reset_en_bypass + #(.width_p(1)) + shadow_translation_en_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(shadow_translation_en_w) + ,.data_i(shadow_translation_en_n) + ,.data_o(shadow_translation_en_r) + ); + + logic attaboy_v_li, attaboy_force_li, attaboy_yumi_lo, attaboy_taken_li, attaboy_ntaken_li; + logic [vaddr_width_p-1:0] attaboy_pc_li; + bp_fe_branch_metadata_fwd_s attaboy_br_metadata_fwd_li; + logic redirect_v_li, redirect_br_v_li, redirect_br_taken_li, redirect_br_ntaken_li, redirect_br_nonbr_li; + logic [vaddr_width_p-1:0] redirect_pc_li, redirect_npc_li; + logic [cinstr_width_gp-1:0] redirect_instr_li; + logic redirect_resume_li; + bp_fe_branch_metadata_fwd_s redirect_br_metadata_fwd_li; + + logic pc_gen_init_done_lo; + logic [vaddr_width_p-1:0] next_pc_lo; + logic ovr_lo; + + logic if2_hit_v_lo, if2_miss_v_lo, if2_yumi_li; + logic [vaddr_width_p-1:0] if2_pc_lo; + logic [icache_data_width_p-1:0] if2_data_lo; + bp_fe_branch_metadata_fwd_s if2_br_metadata_fwd_lo; + + `declare_bp_fe_icache_pkt_s(vaddr_width_p); + bp_fe_icache_pkt_s icache_pkt_li; + logic [icache_data_width_p-1:0] icache_data_lo; + logic icache_v_li, icache_force_li, icache_yumi_lo, tl_flush_lo; + logic icache_tv_we; + logic icache_hit_v_lo, icache_miss_v_lo, icache_fence_v_lo, icache_hit_yumi_li, icache_yumi_li; + + logic fetch_v_lo, fetch_yumi_li; + logic [vaddr_width_p-1:0] fetch_pc_lo; + logic [fetch_width_p-1:0] fetch_instr_lo; + bp_fe_branch_metadata_fwd_s fetch_br_metadata_fwd_lo; + bp_fe_scan_s fetch_scan_lo; + logic fetch_partial_lo, fetch_taken_li; + logic [fetch_ptr_p-1:0] fetch_count_lo; + logic fetch_startup_lo, fetch_catchup_lo, fetch_rebase_lo, fetch_linear_lo; + bp_fe_pc_gen + #(.bp_params_p(bp_params_p)) + pc_gen + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.init_done_o(pc_gen_init_done_lo) + + ,.attaboy_v_i(attaboy_v_li) + ,.attaboy_force_i(attaboy_force_li) + ,.attaboy_pc_i(attaboy_pc_li) + ,.attaboy_br_metadata_fwd_i(attaboy_br_metadata_fwd_li) + ,.attaboy_taken_i(attaboy_taken_li) + ,.attaboy_ntaken_i(attaboy_ntaken_li) + ,.attaboy_yumi_o(attaboy_yumi_lo) + + ,.redirect_v_i(redirect_v_li) + ,.redirect_pc_i(redirect_pc_li) + ,.redirect_npc_i(redirect_npc_li) + ,.redirect_br_v_i(redirect_br_v_li) + ,.redirect_br_metadata_fwd_i(redirect_br_metadata_fwd_li) + ,.redirect_br_taken_i(redirect_br_taken_li) + ,.redirect_br_ntaken_i(redirect_br_ntaken_li) + ,.redirect_br_nonbr_i(redirect_br_nonbr_li) + + ,.next_pc_o(next_pc_lo) + ,.icache_yumi_i(icache_yumi_lo) + + ,.ovr_o(ovr_lo) + ,.icache_tv_we_i(icache_tv_we) + + ,.icache_hit_v_i(icache_hit_v_lo) + ,.icache_miss_v_i(icache_miss_v_lo) + ,.icache_data_i(icache_data_lo) + ,.icache_hit_yumi_o(icache_hit_yumi_li) + + ,.if2_hit_v_o(if2_hit_v_lo) + ,.if2_miss_v_o(if2_miss_v_lo) + ,.if2_pc_o(if2_pc_lo) + ,.if2_data_o(if2_data_lo) + ,.if2_br_metadata_fwd_o(if2_br_metadata_fwd_lo) + ,.if2_yumi_i(if2_yumi_li) + + ,.fetch_pc_i(fetch_pc_lo) + ,.fetch_count_i(fetch_count_lo) + ,.fetch_scan_i(fetch_scan_lo) + ,.fetch_startup_i(fetch_startup_lo) + ,.fetch_catchup_i(fetch_catchup_lo) + ,.fetch_rebase_i(fetch_rebase_lo) + ,.fetch_linear_i(fetch_linear_lo) + ,.fetch_yumi_i(fetch_yumi_li) + ,.fetch_taken_o(fetch_taken_li) + ); + + logic itlb_r_v_li; + wire [dword_width_gp-1:0] r_eaddr_li = `BSG_SIGN_EXTEND(next_pc_lo, dword_width_gp); + wire [1:0] r_size_li = 2'b10; + + logic itlb_w_v_li, itlb_fence_v_li; + logic [vtag_width_p-1:0] itlb_w_vtag_li; + bp_pte_leaf_s itlb_w_tlb_entry_li; + + logic instr_access_fault_lo, instr_page_fault_lo; + logic ptag_v_lo, ptag_uncached_lo, ptag_nonidem_lo, ptag_dram_lo, ptag_miss_lo; + logic [ptag_width_p-1:0] ptag_lo; + logic tv_flush_lo; + + wire uncached_mode = (cfg_bus_cast_i.icache_mode == e_lce_mode_uncached); + wire nonspec_mode = (cfg_bus_cast_i.icache_mode == e_lce_mode_nonspec); + bp_mmu + #(.bp_params_p(bp_params_p) + ,.tlb_els_4k_p(itlb_els_4k_p) + ,.tlb_els_2m_p(itlb_els_2m_p) + ,.tlb_els_1g_p(itlb_els_1g_p) + ,.latch_last_read_p(1) + ) + immu + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.flush_i(tv_flush_lo) + ,.fence_i(itlb_fence_v_li) + ,.priv_mode_i(shadow_priv_r) + ,.trans_en_i(shadow_translation_en_r) + // Supervisor use of user memory is always disabled for immu + ,.sum_i('0) + // Immu does not handle dcache loads + ,.mxr_i('0) + ,.uncached_mode_i(uncached_mode) + ,.nonspec_mode_i(nonspec_mode) + ,.hio_mask_i(cfg_bus_cast_i.hio_mask) + + ,.w_v_i(itlb_w_v_li) + ,.w_vtag_i(itlb_w_vtag_li) + ,.w_entry_i(itlb_w_tlb_entry_li) + + ,.r_v_i(itlb_r_v_li) + ,.r_instr_i(1'b1) + ,.r_load_i('0) + ,.r_store_i('0) + ,.r_cbo_i('0) + ,.r_ptw_i('0) + ,.r_eaddr_i(r_eaddr_li) + ,.r_size_i(r_size_li) + + ,.r_v_o(ptag_v_lo) + ,.r_ptag_o(ptag_lo) + ,.r_instr_miss_o(ptag_miss_lo) + ,.r_load_miss_o() + ,.r_store_miss_o() + ,.r_uncached_o(ptag_uncached_lo) + ,.r_nonidem_o(ptag_nonidem_lo) + ,.r_dram_o(ptag_dram_lo) + ,.r_instr_misaligned_o() + ,.r_load_misaligned_o() + ,.r_store_misaligned_o() + ,.r_instr_access_fault_o(instr_access_fault_lo) + ,.r_load_access_fault_o() + ,.r_store_access_fault_o() + ,.r_instr_page_fault_o(instr_page_fault_lo) + ,.r_load_page_fault_o() + ,.r_store_page_fault_o() + ); + + bp_fe_icache + #(.bp_params_p(bp_params_p)) + icache + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cfg_bus_i(cfg_bus_i) + + ,.icache_pkt_i(icache_pkt_li) + ,.v_i(icache_v_li) + ,.force_i(icache_force_li) + ,.yumi_o(icache_yumi_lo) + ,.tl_flush_i(tl_flush_lo) + + ,.ptag_i(ptag_lo) + ,.ptag_v_i(ptag_v_lo) + ,.ptag_uncached_i(ptag_uncached_lo) + ,.ptag_nonidem_i(ptag_nonidem_lo) + ,.ptag_dram_i(ptag_dram_lo) + ,.tv_flush_i(tv_flush_lo) + ,.tv_we_o(icache_tv_we) + + ,.data_o(icache_data_lo) + ,.hit_v_o(icache_hit_v_lo) + ,.miss_v_o(icache_miss_v_lo) + ,.fence_v_o(icache_fence_v_lo) + ,.yumi_i(icache_yumi_li) + + ,.cache_req_o(cache_req_o) + ,.cache_req_v_o(cache_req_v_o) + ,.cache_req_yumi_i(cache_req_yumi_i) + ,.cache_req_lock_i(cache_req_lock_i) + ,.cache_req_metadata_o(cache_req_metadata_o) + ,.cache_req_metadata_v_o(cache_req_metadata_v_o) + ,.cache_req_id_i(cache_req_id_i) + ,.cache_req_critical_i(cache_req_critical_i) + ,.cache_req_last_i(cache_req_last_i) + ,.cache_req_credits_full_i(cache_req_credits_full_i) + ,.cache_req_credits_empty_i(cache_req_credits_empty_i) + + ,.data_mem_pkt_i(data_mem_pkt_i) + ,.data_mem_pkt_v_i(data_mem_pkt_v_i) + ,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o) + ,.data_mem_o(data_mem_o) + + ,.tag_mem_pkt_i(tag_mem_pkt_i) + ,.tag_mem_pkt_v_i(tag_mem_pkt_v_i) + ,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o) + ,.tag_mem_o(tag_mem_o) + + ,.stat_mem_pkt_v_i(stat_mem_pkt_v_i) + ,.stat_mem_pkt_i(stat_mem_pkt_i) + ,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o) + ,.stat_mem_o(stat_mem_o) + ); + // Autoacknowledge fence + assign icache_yumi_li = icache_hit_yumi_li || icache_fence_v_lo; + + logic assembled_v_lo, assembled_yumi_li; + logic [vaddr_width_p-1:0] assembled_pc_lo; + logic [fetch_cinstr_p-1:0][cinstr_width_gp-1:0] assembled_instr_lo; + bp_fe_branch_metadata_fwd_s assembled_br_metadata_fwd_lo; + logic assembled_partial_lo; + logic [fetch_ptr_p-1:0] assembled_count_lo, assembled_count_li; + bp_fe_realigner + #(.bp_params_p(bp_params_p)) + realigner + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.if2_hit_v_i(if2_hit_v_lo) + ,.if2_miss_v_i(if2_miss_v_lo) + ,.if2_pc_i(if2_pc_lo) + ,.if2_data_i(if2_data_lo) + ,.if2_br_metadata_fwd_i(if2_br_metadata_fwd_lo) + ,.if2_yumi_o(if2_yumi_li) + + ,.redirect_v_i(redirect_v_li) + ,.redirect_pc_i(redirect_pc_li) + ,.redirect_instr_i(redirect_instr_li) + ,.redirect_br_metadata_fwd_i(redirect_br_metadata_fwd_li) + ,.redirect_resume_i(redirect_resume_li) + + ,.assembled_v_o(assembled_v_lo) + ,.assembled_pc_o(assembled_pc_lo) + ,.assembled_instr_o(assembled_instr_lo) + ,.assembled_br_metadata_fwd_o(assembled_br_metadata_fwd_lo) + ,.assembled_partial_o(assembled_partial_lo) + ,.assembled_count_o(assembled_count_lo) + ,.assembled_count_i(assembled_count_li) + ,.assembled_yumi_i(assembled_yumi_li) + ); + + bp_fe_scan + #(.bp_params_p(bp_params_p)) + scan + (.assembled_v_i(assembled_v_lo) + ,.assembled_pc_i(assembled_pc_lo) + ,.assembled_instr_i(assembled_instr_lo) + ,.assembled_br_metadata_fwd_i(assembled_br_metadata_fwd_lo) + ,.assembled_partial_i(assembled_partial_lo) + ,.assembled_count_i(assembled_count_lo) + ,.assembled_count_o(assembled_count_li) + ,.assembled_yumi_o(assembled_yumi_li) + + ,.fetch_v_o(fetch_v_lo) + ,.fetch_pc_o(fetch_pc_lo) + ,.fetch_instr_o(fetch_instr_lo) + ,.fetch_br_metadata_fwd_o(fetch_br_metadata_fwd_lo) + ,.fetch_partial_o(fetch_partial_lo) + ,.fetch_count_o(fetch_count_lo) + ,.fetch_scan_o(fetch_scan_lo) + ,.fetch_startup_o(fetch_startup_lo) + ,.fetch_catchup_o(fetch_catchup_lo) + ,.fetch_rebase_o(fetch_rebase_lo) + ,.fetch_linear_o(fetch_linear_lo) + ,.fetch_yumi_i(fetch_yumi_li) + ,.fetch_taken_i(fetch_taken_li) + ); + + bp_fe_controller + #(.bp_params_p(bp_params_p)) + controller + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.pc_gen_init_done_i(pc_gen_init_done_lo) + + ,.fe_cmd_i(fe_cmd_i) + ,.fe_cmd_v_i(fe_cmd_v_i) + ,.fe_cmd_yumi_o(fe_cmd_yumi_o) + + ,.fe_queue_o(fe_queue_o) + ,.fe_queue_v_o(fe_queue_v_o) + ,.fe_queue_ready_and_i(fe_queue_ready_and_i) + + ,.redirect_v_o(redirect_v_li) + ,.redirect_pc_o(redirect_pc_li) + ,.redirect_npc_o(redirect_npc_li) + ,.redirect_instr_o(redirect_instr_li) + ,.redirect_resume_o(redirect_resume_li) + ,.redirect_br_v_o(redirect_br_v_li) + ,.redirect_br_taken_o(redirect_br_taken_li) + ,.redirect_br_ntaken_o(redirect_br_ntaken_li) + ,.redirect_br_nonbr_o(redirect_br_nonbr_li) + ,.redirect_br_metadata_fwd_o(redirect_br_metadata_fwd_li) + + ,.attaboy_v_o(attaboy_v_li) + ,.attaboy_force_o(attaboy_force_li) + ,.attaboy_pc_o(attaboy_pc_li) + ,.attaboy_br_metadata_fwd_o(attaboy_br_metadata_fwd_li) + ,.attaboy_taken_o(attaboy_taken_li) + ,.attaboy_ntaken_o(attaboy_ntaken_li) + ,.attaboy_yumi_i(attaboy_yumi_lo) + + ,.next_pc_i(next_pc_lo) + + ,.ovr_i(ovr_lo) + ,.tl_flush_o(tl_flush_lo) + + ,.itlb_miss_tl_i(ptag_miss_lo) + ,.instr_page_fault_tl_i(instr_page_fault_lo) + ,.instr_access_fault_tl_i(instr_access_fault_lo) + ,.icache_miss_tv_i(icache_miss_v_lo) + ,.tv_we_i(icache_tv_we) + ,.tv_flush_o(tv_flush_lo) + + ,.fetch_v_i(fetch_v_lo) + ,.fetch_pc_i(fetch_pc_lo) + ,.fetch_instr_i(fetch_instr_lo) + ,.fetch_br_metadata_fwd_i(fetch_br_metadata_fwd_lo) + ,.fetch_partial_i(fetch_partial_lo) + ,.fetch_count_i(fetch_count_lo) + ,.fetch_yumi_o(fetch_yumi_li) + + ,.itlb_r_v_o(itlb_r_v_li) + ,.itlb_w_v_o(itlb_w_v_li) + ,.itlb_w_vtag_o(itlb_w_vtag_li) + ,.itlb_w_entry_o(itlb_w_tlb_entry_li) + ,.itlb_fence_v_o(itlb_fence_v_li) + + ,.icache_v_o(icache_v_li) + ,.icache_force_o(icache_force_li) + ,.icache_pkt_o(icache_pkt_li) + ,.icache_yumi_i(icache_yumi_lo) + + ,.shadow_priv_o(shadow_priv_n) + ,.shadow_priv_w_o(shadow_priv_w) + + ,.shadow_translation_en_o(shadow_translation_en_n) + ,.shadow_translation_en_w_o(shadow_translation_en_w) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_io_cce.sv b/designs/black-parrot/src/bp/bp_io_cce.sv new file mode 100644 index 0000000..d47f929 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_io_cce.sv @@ -0,0 +1,212 @@ + +/* + * Name: + * bp_io_cce.sv + * + * Description: + * This module acts as a CCE for uncacheable IO memory accesses. + * + e It converts uncached load and store LCE to IO requests, and + * converts uncached IO responses to uncached LCE command messages. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_io_cce + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + ) + (input clk_i + , input reset_i + + , input [cce_id_width_p-1:0] cce_id_i + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input [bedrock_fill_width_p-1:0] lce_req_data_i + , input lce_req_v_i + , output logic lce_req_ready_and_o + + , output logic [lce_cmd_header_width_lp-1:0] lce_cmd_header_o + , output logic [bedrock_fill_width_p-1:0] lce_cmd_data_o + , output logic lce_cmd_v_o + , input lce_cmd_ready_and_i + + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `bp_cast_i(bp_bedrock_lce_req_header_s, lce_req_header); + `bp_cast_o(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_i(bp_bedrock_mem_rev_header_s, mem_rev_header); + `bp_cast_o(bp_bedrock_lce_cmd_header_s, lce_cmd_header); + + bp_bedrock_lce_req_header_s fsm_req_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_req_data_lo; + logic fsm_req_v_lo, fsm_req_yumi_li; + logic [paddr_width_p-1:0] fsm_req_addr_lo; + logic fsm_req_new_lo, fsm_req_critical_lo, fsm_req_last_lo; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_req_payload_width_lp) + ,.msg_stream_mask_p(lce_req_stream_mask_gp) + ,.fsm_stream_mask_p(lce_req_stream_mask_gp) + ) + req_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(lce_req_header_cast_i) + ,.msg_data_i(lce_req_data_i) + ,.msg_v_i(lce_req_v_i) + ,.msg_ready_and_o(lce_req_ready_and_o) + + ,.fsm_header_o(fsm_req_header_lo) + ,.fsm_data_o(fsm_req_data_lo) + ,.fsm_v_o(fsm_req_v_lo) + ,.fsm_yumi_i(fsm_req_yumi_li) + ,.fsm_addr_o(fsm_req_addr_lo) + ,.fsm_new_o(fsm_req_new_lo) + ,.fsm_critical_o(fsm_req_critical_lo) + ,.fsm_last_o(fsm_req_last_lo) + ); + + bp_bedrock_mem_fwd_header_s fsm_fwd_header_li; + logic [bedrock_fill_width_p-1:0] fsm_fwd_data_li; + logic fsm_fwd_v_li, fsm_fwd_ready_then_lo; + logic [paddr_width_p-1:0] fsm_fwd_addr_lo; + logic fsm_fwd_new_lo, fsm_fwd_critical_lo, fsm_fwd_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.msg_stream_mask_p(mem_fwd_stream_mask_gp) + ,.fsm_stream_mask_p(mem_fwd_stream_mask_gp) + ) + fwd_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(mem_fwd_header_cast_o) + ,.msg_data_o(mem_fwd_data_o) + ,.msg_v_o(mem_fwd_v_o) + ,.msg_ready_and_i(mem_fwd_ready_and_i) + + ,.fsm_header_i(fsm_fwd_header_li) + ,.fsm_data_i(fsm_fwd_data_li) + ,.fsm_v_i(fsm_fwd_v_li) + ,.fsm_ready_then_o(fsm_fwd_ready_then_lo) + ,.fsm_addr_o(fsm_fwd_addr_lo) + ,.fsm_new_o(fsm_fwd_new_lo) + ,.fsm_critical_o(fsm_fwd_critical_lo) + ,.fsm_last_o(fsm_fwd_last_lo) + ); + + bp_bedrock_mem_rev_header_s fsm_rev_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_rev_data_lo; + logic fsm_rev_v_lo, fsm_rev_yumi_li; + logic [paddr_width_p-1:0] fsm_rev_addr_lo; + logic fsm_rev_new_lo, fsm_rev_critical_lo, fsm_rev_last_lo; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.msg_stream_mask_p(mem_rev_stream_mask_gp) + ,.fsm_stream_mask_p(mem_rev_stream_mask_gp) + ) + rev_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(mem_rev_header_cast_i) + ,.msg_data_i(mem_rev_data_i) + ,.msg_v_i(mem_rev_v_i) + ,.msg_ready_and_o(mem_rev_ready_and_o) + + ,.fsm_header_o(fsm_rev_header_lo) + ,.fsm_data_o(fsm_rev_data_lo) + ,.fsm_v_o(fsm_rev_v_lo) + ,.fsm_yumi_i(fsm_rev_yumi_li) + ,.fsm_addr_o(fsm_rev_addr_lo) + ,.fsm_new_o(fsm_rev_new_lo) + ,.fsm_critical_o(fsm_rev_critical_lo) + ,.fsm_last_o(fsm_rev_last_lo) + ); + + bp_bedrock_lce_cmd_header_s fsm_cmd_header_li; + logic [bedrock_fill_width_p-1:0] fsm_cmd_data_li; + logic fsm_cmd_v_li, fsm_cmd_ready_then_lo; + logic [paddr_width_p-1:0] fsm_cmd_addr_lo; + logic fsm_cmd_new_lo, fsm_cmd_critical_lo, fsm_cmd_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_cmd_payload_width_lp) + ,.msg_stream_mask_p(lce_cmd_stream_mask_gp) + ,.fsm_stream_mask_p(lce_cmd_stream_mask_gp) + ) + cmd_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(lce_cmd_header_cast_o) + ,.msg_data_o(lce_cmd_data_o) + ,.msg_v_o(lce_cmd_v_o) + ,.msg_ready_and_i(lce_cmd_ready_and_i) + + ,.fsm_header_i(fsm_cmd_header_li) + ,.fsm_data_i(fsm_cmd_data_li) + ,.fsm_v_i(fsm_cmd_v_li) + ,.fsm_ready_then_o(fsm_cmd_ready_then_lo) + ,.fsm_addr_o(fsm_cmd_addr_lo) + ,.fsm_new_o(fsm_cmd_new_lo) + ,.fsm_critical_o(fsm_cmd_critical_lo) + ,.fsm_last_o(fsm_cmd_last_lo) + ); + + wire lce_req_wr_not_rd = (fsm_req_header_lo.msg_type.req == e_bedrock_req_uc_wr); + wire mem_rev_wr_not_rd = (fsm_rev_header_lo.msg_type.rev == e_bedrock_mem_wr); + always_comb + begin + fsm_fwd_header_li.msg_type = lce_req_wr_not_rd ? e_bedrock_mem_wr : e_bedrock_mem_rd; + fsm_fwd_header_li.subop = e_bedrock_store; // TODO: support I/O AMOs + fsm_fwd_header_li.addr = fsm_req_header_lo.addr; + fsm_fwd_header_li.size = fsm_req_header_lo.size; + fsm_fwd_header_li.payload = '0; + fsm_fwd_header_li.payload.lce_id = fsm_req_header_lo.payload.src_id; + fsm_fwd_header_li.payload.src_did = fsm_req_header_lo.payload.src_did; + fsm_fwd_header_li.payload.uncached = 1'b1; + fsm_fwd_data_li = fsm_req_data_lo; + fsm_fwd_v_li = fsm_fwd_ready_then_lo & fsm_req_v_lo; + fsm_req_yumi_li = fsm_fwd_v_li; + + fsm_cmd_header_li.msg_type = mem_rev_wr_not_rd ? e_bedrock_cmd_uc_st_done : e_bedrock_cmd_uc_data; + fsm_cmd_header_li.subop = e_bedrock_store; // TODO: support I/O AMOs + fsm_cmd_header_li.addr = fsm_rev_header_lo.addr; + fsm_cmd_header_li.size = fsm_rev_header_lo.size; + fsm_cmd_header_li.payload = '0; + fsm_cmd_header_li.payload.src_id = cce_id_i; + fsm_cmd_header_li.payload.dst_id = fsm_rev_header_lo.payload.lce_id; + fsm_cmd_header_li.payload.src_did = fsm_rev_header_lo.payload.src_did; + fsm_cmd_data_li = fsm_rev_data_lo; + fsm_cmd_v_li = fsm_cmd_ready_then_lo & fsm_rev_v_lo; + fsm_rev_yumi_li = fsm_cmd_v_li; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_io_complex.sv b/designs/black-parrot/src/bp/bp_io_complex.sv new file mode 100644 index 0000000..01eaee9 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_io_complex.sv @@ -0,0 +1,169 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_io_complex + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) + ) + (input core_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input mem_clk_i + , input mem_reset_i + + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + + , input [ic_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_link_i + , output logic [ic_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_link_o + + , input [ic_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_i + , output logic [ic_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_o + + , input [E:W][mem_noc_ral_link_width_lp-1:0] mem_fwd_link_i + , output logic [E:W][mem_noc_ral_link_width_lp-1:0] mem_fwd_link_o + + , input [E:W][mem_noc_ral_link_width_lp-1:0] mem_rev_link_i + , output logic [E:W][mem_noc_ral_link_width_lp-1:0] mem_rev_link_o + ); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bp_mem_ready_and_link_s); + + bp_mem_ready_and_link_s [ic_x_dim_p-1:0][E:W] mem_fwd_link_li, mem_fwd_link_lo, mem_rev_link_li, mem_rev_link_lo; + bp_mem_ready_and_link_s [E:W] mem_fwd_hor_link_li, mem_fwd_hor_link_lo, mem_rev_hor_link_li, mem_rev_hor_link_lo; + bp_coh_ready_and_link_s [ic_x_dim_p-1:0][S:W] lce_req_link_li, lce_req_link_lo, lce_cmd_link_li, lce_cmd_link_lo; + bp_coh_ready_and_link_s [S:N][ic_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo, lce_cmd_ver_link_li, lce_cmd_ver_link_lo; + bp_coh_ready_and_link_s [E:W] lce_req_hor_link_li, lce_req_hor_link_lo, lce_cmd_hor_link_li, lce_cmd_hor_link_lo; + + for (genvar i = 0; i < ic_x_dim_p; i++) + begin : node + wire [coh_noc_cord_width_p-1:0] cord_li = {'0, coh_noc_x_cord_width_p'(i+sac_x_dim_p)}; + bp_io_tile_node + #(.bp_params_p(bp_params_p)) + io + (.core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.mem_clk_i(mem_clk_i) + ,.mem_reset_i(mem_reset_i) + + ,.host_did_i(host_did_i) + ,.my_did_i(my_did_i) + ,.my_cord_i(cord_li) + + ,.coh_lce_req_link_i(lce_req_link_li[i]) + ,.coh_lce_req_link_o(lce_req_link_lo[i]) + + ,.coh_lce_cmd_link_i(lce_cmd_link_li[i]) + ,.coh_lce_cmd_link_o(lce_cmd_link_lo[i]) + + ,.mem_fwd_link_i(mem_fwd_link_li[i]) + ,.mem_fwd_link_o(mem_fwd_link_lo[i]) + + ,.mem_rev_link_i(mem_rev_link_li[i]) + ,.mem_rev_link_o(mem_rev_link_lo[i]) + ); + end + + assign lce_req_ver_link_li[N] = '0; + assign lce_req_ver_link_li[S] = coh_req_link_i; + assign lce_req_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(ic_x_dim_p) + ,.y_max_p(1) + ) + coh_req_mesh + (.outs_i(lce_req_link_lo) + ,.ins_o(lce_req_link_li) + + ,.hor_i(lce_req_hor_link_li) + ,.hor_o(lce_req_hor_link_lo) + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); + assign coh_req_link_o = lce_req_ver_link_lo[S]; + + assign lce_cmd_ver_link_li[N] = '0; + assign lce_cmd_ver_link_li[S] = coh_cmd_link_i; + assign lce_cmd_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(ic_x_dim_p) + ,.y_max_p(1) + ) + coh_cmd_mesh + (.outs_i(lce_cmd_link_lo) + ,.ins_o(lce_cmd_link_li) + + ,.hor_i(lce_cmd_hor_link_li) + ,.hor_o(lce_cmd_hor_link_lo) + ,.ver_i(lce_cmd_ver_link_li) + ,.ver_o(lce_cmd_ver_link_lo) + ); + assign coh_cmd_link_o = lce_cmd_ver_link_lo[S]; + + bp_mem_ready_and_link_s [ic_x_dim_p-1:0][S:W] mem_fwd_mesh_lo, mem_fwd_mesh_li; + for (genvar i = 0; i < ic_x_dim_p; i++) + begin : cmd_link + assign mem_fwd_mesh_lo[i][E:W] = mem_fwd_link_lo[i][E:W]; + assign mem_fwd_link_li[i][E:W] = mem_fwd_mesh_li[i][E:W]; + end + assign mem_fwd_hor_link_li = mem_fwd_link_i; + bsg_mesh_stitch + #(.width_p(mem_noc_ral_link_width_lp) + ,.x_max_p(ic_x_dim_p) + ,.y_max_p(1) + ) + fwd_mesh + (.outs_i(mem_fwd_mesh_lo) + ,.ins_o(mem_fwd_mesh_li) + + ,.hor_i(mem_fwd_hor_link_li) + ,.hor_o(mem_fwd_hor_link_lo) + ,.ver_i() + ,.ver_o() + ); + assign mem_fwd_link_o = mem_fwd_hor_link_lo; + + bp_mem_ready_and_link_s [ic_x_dim_p-1:0][S:W] mem_rev_mesh_lo, mem_rev_mesh_li; + for (genvar i = 0; i < ic_x_dim_p; i++) + begin : resp_link + assign mem_rev_mesh_lo[i][E:W] = mem_rev_link_lo[i][E:W]; + assign mem_rev_link_li[i][E:W] = mem_rev_mesh_li[i][E:W]; + end + assign mem_rev_hor_link_li = mem_rev_link_i; + bsg_mesh_stitch + #(.width_p(mem_noc_ral_link_width_lp) + ,.x_max_p(ic_x_dim_p) + ,.y_max_p(ic_y_dim_p) + ) + rev_mesh + (.outs_i(mem_rev_mesh_lo) + ,.ins_o(mem_rev_mesh_li) + + ,.hor_i(mem_rev_hor_link_li) + ,.hor_o(mem_rev_hor_link_lo) + ,.ver_i() + ,.ver_o() + ); + assign mem_rev_link_o = mem_rev_hor_link_lo; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_io_link_to_lce.sv b/designs/black-parrot/src/bp/bp_io_link_to_lce.sv new file mode 100644 index 0000000..bc28bf1 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_io_link_to_lce.sv @@ -0,0 +1,221 @@ + +/* + * Name: + * bp_io_link_to_lce.sv + * + * Description: + * This module converts IO Command messages to LCE Requests and IO Response + * messages to LCE Commands. This module only supports uncached accesses. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_io_link_to_lce + import bp_common_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + ) + (input clk_i + , input reset_i + + , input [lce_id_width_p-1:0] lce_id_i + + // Bedrock Burst: ready&valid + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + , output logic [lce_req_header_width_lp-1:0] lce_req_header_o + , output logic [bedrock_fill_width_p-1:0] lce_req_data_o + , output logic lce_req_v_o + , input lce_req_ready_and_i + + , input [lce_cmd_header_width_lp-1:0] lce_cmd_header_i + , input [bedrock_fill_width_p-1:0] lce_cmd_data_i + , input lce_cmd_v_i + , output logic lce_cmd_ready_and_o + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_o(bp_bedrock_mem_rev_header_s, mem_rev_header); + `bp_cast_o(bp_bedrock_lce_req_header_s, lce_req_header); + `bp_cast_i(bp_bedrock_lce_cmd_header_s, lce_cmd_header); + + bp_bedrock_mem_fwd_header_s fsm_fwd_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_fwd_data_lo; + logic fsm_fwd_v_lo, fsm_fwd_yumi_li; + logic [paddr_width_p-1:0] fsm_fwd_addr_lo; + logic fsm_fwd_new_lo, fsm_fwd_critical_lo, fsm_fwd_last_lo; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.msg_stream_mask_p(mem_fwd_stream_mask_gp) + ,.fsm_stream_mask_p(mem_fwd_stream_mask_gp) + ) + fwd_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(mem_fwd_header_cast_i) + ,.msg_data_i(mem_fwd_data_i) + ,.msg_v_i(mem_fwd_v_i) + ,.msg_ready_and_o(mem_fwd_ready_and_o) + + ,.fsm_header_o(fsm_fwd_header_lo) + ,.fsm_data_o(fsm_fwd_data_lo) + ,.fsm_v_o(fsm_fwd_v_lo) + ,.fsm_yumi_i(fsm_fwd_yumi_li) + ,.fsm_addr_o(fsm_fwd_addr_lo) + ,.fsm_new_o(fsm_fwd_new_lo) + ,.fsm_critical_o(fsm_fwd_critical_lo) + ,.fsm_last_o(fsm_fwd_last_lo) + ); + + bp_bedrock_lce_req_header_s fsm_req_header_li; + logic [bedrock_fill_width_p-1:0] fsm_req_data_li; + logic fsm_req_v_li, fsm_req_ready_then_lo; + logic [paddr_width_p-1:0] fsm_req_addr_lo; + logic fsm_req_new_lo, fsm_req_critical_lo, fsm_req_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_req_payload_width_lp) + ,.msg_stream_mask_p(lce_req_stream_mask_gp) + ,.fsm_stream_mask_p(lce_req_stream_mask_gp) + ) + req_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(lce_req_header_cast_o) + ,.msg_data_o(lce_req_data_o) + ,.msg_v_o(lce_req_v_o) + ,.msg_ready_and_i(lce_req_ready_and_i) + + ,.fsm_header_i(fsm_req_header_li) + ,.fsm_data_i(fsm_req_data_li) + ,.fsm_v_i(fsm_req_v_li) + ,.fsm_ready_then_o(fsm_req_ready_then_lo) + ,.fsm_addr_o(fsm_req_addr_lo) + ,.fsm_new_o(fsm_req_new_lo) + ,.fsm_critical_o(fsm_req_critical_lo) + ,.fsm_last_o(fsm_req_last_lo) + ); + + bp_bedrock_lce_cmd_header_s fsm_cmd_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_cmd_data_lo; + logic fsm_cmd_v_lo, fsm_cmd_yumi_li; + logic [paddr_width_p-1:0] fsm_cmd_addr_lo; + logic fsm_cmd_new_lo, fsm_cmd_critical_lo, fsm_cmd_last_lo; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(lce_cmd_payload_width_lp) + ,.msg_stream_mask_p(lce_cmd_stream_mask_gp) + ,.fsm_stream_mask_p(lce_cmd_stream_mask_gp) + ) + cmd_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(lce_cmd_header_cast_i) + ,.msg_data_i(lce_cmd_data_i) + ,.msg_v_i(lce_cmd_v_i) + ,.msg_ready_and_o(lce_cmd_ready_and_o) + + ,.fsm_header_o(fsm_cmd_header_lo) + ,.fsm_data_o(fsm_cmd_data_lo) + ,.fsm_v_o(fsm_cmd_v_lo) + ,.fsm_yumi_i(fsm_cmd_yumi_li) + ,.fsm_addr_o(fsm_cmd_addr_lo) + ,.fsm_new_o(fsm_cmd_new_lo) + ,.fsm_critical_o(fsm_cmd_critical_lo) + ,.fsm_last_o(fsm_cmd_last_lo) + ); + + bp_bedrock_mem_rev_header_s fsm_rev_header_li; + logic [bedrock_fill_width_p-1:0] fsm_rev_data_li; + logic fsm_rev_v_li, fsm_rev_ready_then_lo; + logic [paddr_width_p-1:0] fsm_rev_addr_lo; + logic fsm_rev_new_lo, fsm_rev_critical_lo, fsm_rev_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.msg_stream_mask_p(mem_rev_stream_mask_gp) + ,.fsm_stream_mask_p(mem_rev_stream_mask_gp) + ) + rev_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(mem_rev_header_cast_o) + ,.msg_data_o(mem_rev_data_o) + ,.msg_v_o(mem_rev_v_o) + ,.msg_ready_and_i(mem_rev_ready_and_i) + + ,.fsm_header_i(fsm_rev_header_li) + ,.fsm_data_i(fsm_rev_data_li) + ,.fsm_v_i(fsm_rev_v_li) + ,.fsm_ready_then_o(fsm_rev_ready_then_lo) + ,.fsm_addr_o(fsm_rev_addr_lo) + ,.fsm_new_o(fsm_rev_new_lo) + ,.fsm_critical_o(fsm_rev_critical_lo) + ,.fsm_last_o(fsm_rev_last_lo) + ); + + logic [cce_id_width_p-1:0] cce_id_lo; + bp_me_addr_to_cce_id + #(.bp_params_p(bp_params_p)) + addr_map + (.paddr_i(fsm_fwd_header_lo.addr) + ,.cce_id_o(cce_id_lo) + ); + + wire mem_fwd_wr_not_rd = (fsm_fwd_header_lo.msg_type == e_bedrock_mem_wr); + wire lce_cmd_wr_not_rd = (fsm_cmd_header_lo.msg_type == e_bedrock_cmd_uc_st_done); + always_comb + begin + fsm_req_header_li.msg_type = mem_fwd_wr_not_rd ? e_bedrock_req_uc_wr : e_bedrock_req_uc_rd; + fsm_req_header_li.subop = e_bedrock_store; // TODO: support I/O AMOs + fsm_req_header_li.addr = fsm_fwd_header_lo.addr; + fsm_req_header_li.size = fsm_fwd_header_lo.size; + fsm_req_header_li.payload = '0; + fsm_req_header_li.payload.src_id = lce_id_i; + fsm_req_header_li.payload.dst_id = cce_id_lo; + fsm_req_header_li.payload.src_did = fsm_fwd_header_lo.payload.src_did; + fsm_req_data_li = fsm_fwd_data_lo; + fsm_req_v_li = fsm_req_ready_then_lo & fsm_fwd_v_lo; + fsm_fwd_yumi_li = fsm_req_v_li; + + fsm_rev_header_li.msg_type = lce_cmd_wr_not_rd ? e_bedrock_mem_wr : e_bedrock_mem_rd; + fsm_rev_header_li.subop = e_bedrock_store; // TODO: support I/O AMOs + fsm_rev_header_li.addr = fsm_cmd_header_lo.addr; + fsm_rev_header_li.size = fsm_cmd_header_lo.size; + fsm_rev_header_li.payload = '0; + fsm_rev_header_li.payload.src_did = fsm_cmd_header_lo.payload.src_did; + fsm_rev_data_li = fsm_cmd_data_lo; + fsm_rev_v_li = fsm_rev_ready_then_lo & fsm_cmd_v_lo; + fsm_cmd_yumi_li = fsm_rev_v_li; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_io_tile.sv b/designs/black-parrot/src/bp/bp_io_tile.sv new file mode 100644 index 0000000..1d3a60a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_io_tile.sv @@ -0,0 +1,406 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_io_tile + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) + ) + (input clk_i + , input reset_i + + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + + , input [coh_noc_ral_link_width_lp-1:0] lce_req_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_req_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_o + + , input [mem_noc_ral_link_width_lp-1:0] mem_fwd_link_i + , output logic [mem_noc_ral_link_width_lp-1:0] mem_fwd_link_o + + , input [mem_noc_ral_link_width_lp-1:0] mem_rev_link_i + , output logic [mem_noc_ral_link_width_lp-1:0] mem_rev_link_o + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_noc_ready_and_link_sif_s); + `bp_cast_i(bp_coh_noc_ready_and_link_sif_s, lce_req_link); + `bp_cast_o(bp_coh_noc_ready_and_link_sif_s, lce_req_link); + `bp_cast_i(bp_coh_noc_ready_and_link_sif_s, lce_cmd_link); + `bp_cast_o(bp_coh_noc_ready_and_link_sif_s, lce_cmd_link); + + // I/O Link to LCE connections + bp_bedrock_mem_fwd_header_s mem_fwd_header_li; + logic [bedrock_fill_width_p-1:0] mem_fwd_data_li; + logic mem_fwd_v_li, mem_fwd_ready_and_lo; + + bp_bedrock_mem_rev_header_s mem_rev_header_lo; + logic [bedrock_fill_width_p-1:0] mem_rev_data_lo; + logic mem_rev_v_lo, mem_rev_ready_and_li; + + bp_bedrock_lce_req_header_s lce_req_header_lo; + logic [bedrock_fill_width_p-1:0] lce_req_data_lo; + logic lce_req_v_lo, lce_req_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_req_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_req_dst_cid_lo; + + bp_bedrock_lce_cmd_header_s lce_cmd_header_li; + logic [bedrock_fill_width_p-1:0] lce_cmd_data_li; + logic lce_cmd_v_li, lce_cmd_ready_and_lo; + + // I/O CCE connections + bp_bedrock_lce_cmd_header_s lce_cmd_header_lo; + logic [bedrock_fill_width_p-1:0] lce_cmd_data_lo; + logic lce_cmd_v_lo, lce_cmd_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_cmd_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_cmd_dst_cid_lo; + + bp_bedrock_lce_req_header_s lce_req_header_li; + logic [bedrock_fill_width_p-1:0] lce_req_data_li; + logic lce_req_v_li, lce_req_ready_and_lo; + + bp_bedrock_mem_fwd_header_s mem_fwd_header_lo; + logic [bedrock_fill_width_p-1:0] mem_fwd_data_lo; + logic mem_fwd_v_lo, mem_fwd_ready_and_li; + + bp_bedrock_mem_rev_header_s mem_rev_header_li; + logic [bedrock_fill_width_p-1:0] mem_rev_data_li; + logic mem_rev_v_li, mem_rev_ready_and_lo; + + logic reset_r; + always_ff @(posedge clk_i) + reset_r <= reset_i; + + logic [cce_id_width_p-1:0] cce_id_li; + logic [lce_id_width_p-1:0] lce_id_li; + bp_me_cord_to_id + #(.bp_params_p(bp_params_p)) + id_map + (.cord_i(my_cord_i) + ,.core_id_o() + ,.cce_id_o(cce_id_li) + ,.lce_id0_o(lce_id_li) + ,.lce_id1_o() + ); + + bp_io_link_to_lce + #(.bp_params_p(bp_params_p)) + lce_link + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.lce_id_i(lce_id_li) + + ,.mem_fwd_header_i(mem_fwd_header_li) + ,.mem_fwd_data_i(mem_fwd_data_li) + ,.mem_fwd_v_i(mem_fwd_v_li) + ,.mem_fwd_ready_and_o(mem_fwd_ready_and_lo) + + ,.mem_rev_header_o(mem_rev_header_lo) + ,.mem_rev_data_o(mem_rev_data_lo) + ,.mem_rev_v_o(mem_rev_v_lo) + ,.mem_rev_ready_and_i(mem_rev_ready_and_li) + + ,.lce_req_header_o(lce_req_header_lo) + ,.lce_req_data_o(lce_req_data_lo) + ,.lce_req_v_o(lce_req_v_lo) + ,.lce_req_ready_and_i(lce_req_ready_and_li) + + ,.lce_cmd_header_i(lce_cmd_header_li) + ,.lce_cmd_data_i(lce_cmd_data_li) + ,.lce_cmd_v_i(lce_cmd_v_li) + ,.lce_cmd_ready_and_o(lce_cmd_ready_and_lo) + ); + + bp_io_cce + #(.bp_params_p(bp_params_p)) + io_cce + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.cce_id_i(cce_id_li) + + ,.lce_req_header_i(lce_req_header_li) + ,.lce_req_data_i(lce_req_data_li) + ,.lce_req_v_i(lce_req_v_li) + ,.lce_req_ready_and_o(lce_req_ready_and_lo) + + ,.lce_cmd_header_o(lce_cmd_header_lo) + ,.lce_cmd_data_o(lce_cmd_data_lo) + ,.lce_cmd_v_o(lce_cmd_v_lo) + ,.lce_cmd_ready_and_i(lce_cmd_ready_and_li) + + ,.mem_fwd_header_o(mem_fwd_header_lo) + ,.mem_fwd_data_o(mem_fwd_data_lo) + ,.mem_fwd_v_o(mem_fwd_v_lo) + ,.mem_fwd_ready_and_i(mem_fwd_ready_and_li) + + ,.mem_rev_header_i(mem_rev_header_li) + ,.mem_rev_data_i(mem_rev_data_li) + ,.mem_rev_v_i(mem_rev_v_li) + ,.mem_rev_ready_and_o(mem_rev_ready_and_lo) + ); + + // LCE Req Link WH-Burst conversion + bp_me_cce_id_to_cord + #(.bp_params_p(bp_params_p)) + req_router_cord + (.cce_id_i(lce_req_header_lo.payload.dst_id) + ,.cce_cord_o(lce_req_dst_cord_lo) + ,.cce_cid_o(lce_req_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_req_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_req_header_lo) + ,.pr_data_i(lce_req_data_lo) + ,.pr_v_i(lce_req_v_lo) + ,.pr_ready_and_o(lce_req_ready_and_li) + ,.dst_cord_i(lce_req_dst_cord_lo) + ,.dst_cid_i(lce_req_dst_cid_lo) + + ,.link_data_o(lce_req_link_cast_o.data) + ,.link_v_o(lce_req_link_cast_o.v) + ,.link_ready_and_i(lce_req_link_cast_i.ready_and_rev) + ); + + // WH to Burst (lce_req_header_li) + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_req_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_req_link_cast_i.data) + ,.link_v_i(lce_req_link_cast_i.v) + ,.link_ready_and_o(lce_req_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_req_header_li) + ,.pr_data_o(lce_req_data_li) + ,.pr_v_o(lce_req_v_li) + ,.pr_ready_and_i(lce_req_ready_and_lo) + ); + + // LCE cmd Link WH-Burst conversion + bp_me_lce_id_to_cord + #(.bp_params_p(bp_params_p)) + cmd_router_cord + (.lce_id_i(lce_cmd_header_lo.payload.dst_id) + ,.lce_cord_o(lce_cmd_dst_cord_lo) + ,.lce_cid_o(lce_cmd_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_cmd_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_cmd_header_lo) + ,.pr_data_i(lce_cmd_data_lo) + ,.pr_v_i(lce_cmd_v_lo) + ,.pr_ready_and_o(lce_cmd_ready_and_li) + ,.dst_cord_i(lce_cmd_dst_cord_lo) + ,.dst_cid_i(lce_cmd_dst_cid_lo) + + ,.link_data_o(lce_cmd_link_cast_o.data) + ,.link_v_o(lce_cmd_link_cast_o.v) + ,.link_ready_and_i(lce_cmd_link_cast_i.ready_and_rev) + ); + + // WH to Burst (lce_cmd_header_li) + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_cmd_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_cmd_link_cast_i.data) + ,.link_v_i(lce_cmd_link_cast_i.v) + ,.link_ready_and_o(lce_cmd_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_cmd_header_li) + ,.pr_data_o(lce_cmd_data_li) + ,.pr_v_o(lce_cmd_v_li) + ,.pr_ready_and_i(lce_cmd_ready_and_lo) + ); + + // I/O Link Send and Receive + bp_global_addr_s global_addr_lo; + bp_local_addr_s local_addr_lo; + + assign global_addr_lo = mem_fwd_header_lo.addr; + assign local_addr_lo = mem_fwd_header_lo.addr; + + wire is_host_addr = (~local_addr_lo.nonlocal && (local_addr_lo.dev inside {host_dev_gp})); + wire [mem_noc_did_width_p-1:0] dst_did_lo = is_host_addr ? host_did_i : global_addr_lo.hio; + + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bsg_ready_and_link_sif_s); + `bp_cast_i(bsg_ready_and_link_sif_s, mem_fwd_link); + `bp_cast_o(bsg_ready_and_link_sif_s, mem_rev_link); + `bp_cast_o(bsg_ready_and_link_sif_s, mem_fwd_link); + `bp_cast_i(bsg_ready_and_link_sif_s, mem_rev_link); + + wire [mem_noc_cord_width_p-1:0] mem_fwd_dst_cord_lo = dst_did_lo; + wire [mem_noc_cid_width_p-1:0] mem_fwd_dst_cid_lo = '0; + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(mem_noc_flit_width_p) + ,.cord_width_p(mem_noc_cord_width_p) + ,.len_width_p(mem_noc_len_width_p) + ,.cid_width_p(mem_noc_cid_width_p) + ,.pr_hdr_width_p(mem_fwd_header_width_lp) + ,.pr_payload_width_p(mem_fwd_payload_width_lp) + ,.pr_stream_mask_p(mem_fwd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + mem_fwd_stream_to_wormhole + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(mem_fwd_header_lo) + ,.pr_data_i(mem_fwd_data_lo) + ,.pr_v_i(mem_fwd_v_lo) + ,.pr_ready_and_o(mem_fwd_ready_and_li) + ,.dst_cord_i(mem_fwd_dst_cord_lo) + ,.dst_cid_i(mem_fwd_dst_cid_lo) + + ,.link_data_o(mem_fwd_link_cast_o.data) + ,.link_v_o(mem_fwd_link_cast_o.v) + ,.link_ready_and_i(mem_fwd_link_cast_i.ready_and_rev) + ); + + wire [mem_noc_cord_width_p-1:0] mem_rev_dst_cord_lo = mem_rev_header_lo.payload.src_did; + wire [mem_noc_cid_width_p-1:0] mem_rev_dst_cid_lo = '0; + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(mem_noc_flit_width_p) + ,.cord_width_p(mem_noc_cord_width_p) + ,.len_width_p(mem_noc_len_width_p) + ,.cid_width_p(mem_noc_cid_width_p) + ,.pr_hdr_width_p(mem_rev_header_width_lp) + ,.pr_payload_width_p(mem_rev_payload_width_lp) + ,.pr_stream_mask_p(mem_rev_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + mem_rev_stream_to_wormhole + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(mem_rev_header_lo) + ,.pr_data_i(mem_rev_data_lo) + ,.pr_v_i(mem_rev_v_lo) + ,.pr_ready_and_o(mem_rev_ready_and_li) + ,.dst_cord_i(mem_rev_dst_cord_lo) + ,.dst_cid_i(mem_rev_dst_cid_lo) + + ,.link_data_o(mem_rev_link_cast_o.data) + ,.link_v_o(mem_rev_link_cast_o.v) + ,.link_ready_and_i(mem_rev_link_cast_i.ready_and_rev) + ); + + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(mem_noc_flit_width_p) + ,.cord_width_p(mem_noc_cord_width_p) + ,.len_width_p(mem_noc_len_width_p) + ,.cid_width_p(mem_noc_cid_width_p) + ,.pr_hdr_width_p(mem_fwd_header_width_lp) + ,.pr_payload_width_p(mem_fwd_payload_width_lp) + ,.pr_stream_mask_p(mem_fwd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + mem_fwd_wormhole_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(mem_fwd_link_cast_i.data) + ,.link_v_i(mem_fwd_link_cast_i.v) + ,.link_ready_and_o(mem_fwd_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(mem_fwd_header_li) + ,.pr_data_o(mem_fwd_data_li) + ,.pr_v_o(mem_fwd_v_li) + ,.pr_ready_and_i(mem_fwd_ready_and_lo) + ); + + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(mem_noc_flit_width_p) + ,.cord_width_p(mem_noc_cord_width_p) + ,.len_width_p(mem_noc_len_width_p) + ,.cid_width_p(mem_noc_cid_width_p) + ,.pr_hdr_width_p(mem_rev_header_width_lp) + ,.pr_payload_width_p(mem_rev_payload_width_lp) + ,.pr_stream_mask_p(mem_rev_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + mem_rev_wormhole_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(mem_rev_link_cast_i.data) + ,.link_v_i(mem_rev_link_cast_i.v) + ,.link_ready_and_o(mem_rev_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(mem_rev_header_li) + ,.pr_data_o(mem_rev_data_li) + ,.pr_v_o(mem_rev_v_li) + ,.pr_ready_and_i(mem_rev_ready_and_lo) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_io_tile_node.sv b/designs/black-parrot/src/bp/bp_io_tile_node.sv new file mode 100644 index 0000000..756a7fe --- /dev/null +++ b/designs/black-parrot/src/bp/bp_io_tile_node.sv @@ -0,0 +1,123 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_io_tile_node + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) + ) + (input core_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input mem_clk_i + , input mem_reset_i + + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o + + , input [E:W][mem_noc_ral_link_width_lp-1:0] mem_fwd_link_i + , output logic [E:W][mem_noc_ral_link_width_lp-1:0] mem_fwd_link_o + + , input [E:W][mem_noc_ral_link_width_lp-1:0] mem_rev_link_i + , output logic [E:W][mem_noc_ral_link_width_lp-1:0] mem_rev_link_o + ); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bp_mem_ready_and_link_s); + + // Tile-side coherence connections + bp_coh_ready_and_link_s core_lce_req_link_li, core_lce_req_link_lo; + bp_coh_ready_and_link_s core_lce_cmd_link_li, core_lce_cmd_link_lo; + + // Tile side IO connections + bp_mem_ready_and_link_s core_mem_fwd_link_li, core_mem_fwd_link_lo; + bp_mem_ready_and_link_s core_mem_rev_link_li, core_mem_rev_link_lo; + + bp_io_tile + #(.bp_params_p(bp_params_p)) + io_tile + (.clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.host_did_i(host_did_i) + ,.my_did_i(my_did_i) + ,.my_cord_i(my_cord_i) + + ,.lce_req_link_i(core_lce_req_link_li) + ,.lce_req_link_o(core_lce_req_link_lo) + + ,.lce_cmd_link_i(core_lce_cmd_link_li) + ,.lce_cmd_link_o(core_lce_cmd_link_lo) + + ,.mem_fwd_link_i(core_mem_fwd_link_li) + ,.mem_fwd_link_o(core_mem_fwd_link_lo) + + ,.mem_rev_link_i(core_mem_rev_link_li) + ,.mem_rev_link_o(core_mem_rev_link_lo) + ); + + + bp_nd_socket + #(.flit_width_p(coh_noc_flit_width_p) + ,.dims_p(coh_noc_dims_p) + ,.cord_dims_p(coh_noc_dims_p) + ,.cord_markers_pos_p(coh_noc_cord_markers_pos_p) + ,.len_width_p(coh_noc_len_width_p) + ,.routing_matrix_p(StrictYX) + ,.async_clk_p(async_coh_clk_p) + ,.els_p(2) + ) + io_coh_socket + (.tile_clk_i(core_clk_i) + ,.tile_reset_i(core_reset_i) + ,.network_clk_i(coh_clk_i) + ,.network_reset_i(coh_reset_i) + ,.my_cord_i(my_cord_i) + ,.network_link_i({coh_lce_req_link_i, coh_lce_cmd_link_i}) + ,.network_link_o({coh_lce_req_link_o, coh_lce_cmd_link_o}) + ,.tile_link_i({core_lce_req_link_lo, core_lce_cmd_link_lo}) + ,.tile_link_o({core_lce_req_link_li, core_lce_cmd_link_li}) + ); + + bp_nd_socket + #(.flit_width_p(mem_noc_flit_width_p) + ,.dims_p(mem_noc_dims_p) + ,.cord_dims_p(mem_noc_cord_dims_p) + ,.cord_markers_pos_p(mem_noc_cord_markers_pos_p) + ,.len_width_p(mem_noc_len_width_p) + ,.routing_matrix_p(StrictX) + ,.async_clk_p(async_mem_clk_p) + ,.els_p(2) + ) + io_socket + (.tile_clk_i(core_clk_i) + ,.tile_reset_i(core_reset_i) + ,.network_clk_i(mem_clk_i) + ,.network_reset_i(mem_reset_i) + ,.my_cord_i(mem_noc_cord_width_p'(my_did_i)) + ,.network_link_i({mem_fwd_link_i, mem_rev_link_i}) + ,.network_link_o({mem_fwd_link_o, mem_rev_link_o}) + ,.tile_link_i({core_mem_fwd_link_lo, core_mem_rev_link_lo}) + ,.tile_link_o({core_mem_fwd_link_li, core_mem_rev_link_li}) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_l2e_tile.sv b/designs/black-parrot/src/bp/bp_l2e_tile.sv new file mode 100644 index 0000000..07f0f2b --- /dev/null +++ b/designs/black-parrot/src/bp/bp_l2e_tile.sv @@ -0,0 +1,466 @@ +/** + * + * bp_l2e_tile.v + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" +`include "bsg_cache.svh" +`include "bsg_noc_links.svh" + +module bp_l2e_tile + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + import bp_top_pkg::*; + import bsg_cache_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + // Wormhole parameters + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + ) + (input clk_i + , input reset_i + + // Memory side connection + , input [mem_noc_did_width_p-1:0] my_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + + , input [coh_noc_ral_link_width_lp-1:0] lce_req_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_req_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_resp_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_resp_link_o + + , output logic [dma_noc_ral_link_width_lp-1:0] dma_link_o + , input [dma_noc_ral_link_width_lp-1:0] dma_link_i + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(dma_noc_flit_width_p, bp_dma_ready_and_link_s); + + // Reset + logic reset_r; + always_ff @(posedge clk_i) + reset_r <= reset_i; + + // Config bus + bp_cfg_bus_s cfg_bus_lo; + + // LCE-CCE coherence network links + `bp_cast_i(bp_coh_ready_and_link_s, lce_req_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_cmd_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_resp_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_req_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_cmd_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_resp_link); + + // stub unused LCE-CCE connections + assign lce_req_link_cast_o.v = '0; + assign lce_req_link_cast_o.data = '0; + assign lce_cmd_link_cast_o.ready_and_rev = '0; + assign lce_resp_link_cast_o.v = '0; + assign lce_resp_link_cast_o.data = '0; + + // CCE-side LCE-CCE network connections + bp_bedrock_lce_req_header_s lce_req_header_li; + logic [bedrock_fill_width_p-1:0] lce_req_data_li; + logic lce_req_v_li, lce_req_ready_and_lo; + + bp_bedrock_lce_cmd_header_s lce_cmd_header_lo; + logic [bedrock_fill_width_p-1:0] lce_cmd_data_lo; + logic lce_cmd_v_lo, lce_cmd_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_cmd_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_cmd_dst_cid_lo; + + bp_bedrock_lce_resp_header_s lce_resp_header_li; + logic [bedrock_fill_width_p-1:0] lce_resp_data_li; + logic lce_resp_v_li, lce_resp_ready_and_lo; + + // LCE to CCE request + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_req_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_req_link_cast_i.data) + ,.link_v_i(lce_req_link_cast_i.v) + ,.link_ready_and_o(lce_req_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_req_header_li) + ,.pr_data_o(lce_req_data_li) + ,.pr_v_o(lce_req_v_li) + ,.pr_ready_and_i(lce_req_ready_and_lo) + ); + + // CCE to LCE command + // encode the header into WH format + bp_me_lce_id_to_cord + #(.bp_params_p(bp_params_p)) + cmd_router_cord + (.lce_id_i(lce_cmd_header_lo.payload.dst_id) + ,.lce_cord_o(lce_cmd_dst_cord_lo) + ,.lce_cid_o(lce_cmd_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_cmd_burst_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_cmd_header_lo) + ,.pr_data_i(lce_cmd_data_lo) + ,.pr_v_i(lce_cmd_v_lo) + ,.pr_ready_and_o(lce_cmd_ready_and_li) + ,.dst_cord_i(lce_cmd_dst_cord_lo) + ,.dst_cid_i(lce_cmd_dst_cid_lo) + + ,.link_data_o(lce_cmd_link_cast_o.data) + ,.link_v_o(lce_cmd_link_cast_o.v) + ,.link_ready_and_i(lce_cmd_link_cast_i.ready_and_rev) + ); + + // LCE to CCE response + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_resp_header_width_lp) + ,.pr_payload_width_p(lce_resp_payload_width_lp) + ,.pr_stream_mask_p(lce_resp_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + lce_resp_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_resp_link_cast_i.data) + ,.link_v_i(lce_resp_link_cast_i.v) + ,.link_ready_and_o(lce_resp_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_resp_header_li) + ,.pr_data_o(lce_resp_data_li) + ,.pr_v_o(lce_resp_v_li) + ,.pr_ready_and_i(lce_resp_ready_and_lo) + ); + + // CCE-side CCE-Mem network connections + bp_bedrock_mem_fwd_header_s mem_fwd_header_lo; + logic [bedrock_fill_width_p-1:0] mem_fwd_data_lo; + logic mem_fwd_v_lo, mem_fwd_ready_and_li; + bp_bedrock_mem_rev_header_s mem_rev_header_li; + logic [bedrock_fill_width_p-1:0] mem_rev_data_li; + logic mem_rev_v_li, mem_rev_ready_and_lo; + + // Device-side CCE-Mem network connections + // dev_fwd[2:0] = {CCE loopback, CFG, memory (cache)} + bp_bedrock_mem_fwd_header_s [2:0] dev_fwd_header_li; + logic [2:0][bedrock_fill_width_p-1:0] dev_fwd_data_li; + logic [2:0] dev_fwd_v_li, dev_fwd_ready_and_lo; + bp_bedrock_mem_rev_header_s [2:0] dev_rev_header_lo; + logic [2:0][bedrock_fill_width_p-1:0] dev_rev_data_lo; + logic [2:0] dev_rev_v_lo, dev_rev_ready_and_li; + + // Config + logic cce_ucode_v_lo; + logic cce_ucode_w_lo; + logic [cce_pc_width_p-1:0] cce_ucode_addr_lo; + logic [cce_instr_width_gp-1:0] cce_ucode_data_lo, cce_ucode_data_li; + logic [bedrock_fill_width_p-1:0] cfg_data_lo, cfg_data_li; + bp_me_cfg_slice + #(.bp_params_p(bp_params_p)) + cfgs + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.mem_fwd_header_i(dev_fwd_header_li[1]) + ,.mem_fwd_data_i(dev_fwd_data_li[1]) + ,.mem_fwd_v_i(dev_fwd_v_li[1]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[1]) + + ,.mem_rev_header_o(dev_rev_header_lo[1]) + ,.mem_rev_data_o(dev_rev_data_lo[1]) + ,.mem_rev_v_o(dev_rev_v_lo[1]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[1]) + + ,.cfg_bus_o(cfg_bus_lo) + ,.did_i(my_did_i) + ,.host_did_i('0) + ,.cord_i(my_cord_i) + + ,.cce_ucode_v_o(cce_ucode_v_lo) + ,.cce_ucode_w_o(cce_ucode_w_lo) + ,.cce_ucode_addr_o(cce_ucode_addr_lo) + ,.cce_ucode_data_o(cce_ucode_data_lo) + ,.cce_ucode_data_i(cce_ucode_data_li) + ); + + // CCE-Mem Loopback + bp_me_loopback + #(.bp_params_p(bp_params_p)) + loopback + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.mem_fwd_header_i(dev_fwd_header_li[2]) + ,.mem_fwd_data_i(dev_fwd_data_li[2]) + ,.mem_fwd_v_i(dev_fwd_v_li[2]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[2]) + + ,.mem_rev_header_o(dev_rev_header_lo[2]) + ,.mem_rev_data_o(dev_rev_data_lo[2]) + ,.mem_rev_v_o(dev_rev_v_lo[2]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[2]) + ); + + // Select destination of CCE-Mem command from CCE + logic [`BSG_SAFE_CLOG2(3)-1:0] mem_fwd_dst_lo; + bp_local_addr_s local_addr; + assign local_addr = mem_fwd_header_lo.addr; + wire [dev_id_width_gp-1:0] device_fwd_li = local_addr.dev; + wire local_fwd_li = (mem_fwd_header_lo.addr < dram_base_addr_gp); + + wire is_cfg_fwd = local_fwd_li & (device_fwd_li == cfg_dev_gp); + wire is_mem_fwd = ~local_fwd_li || (local_fwd_li & (device_fwd_li == cache_dev_gp)); + wire is_loopback_fwd = local_fwd_li & ~is_cfg_fwd & ~is_mem_fwd; + + bsg_encode_one_hot + #(.width_p(3), .lo_to_hi_p(1)) + fwd_pe + (.i({is_loopback_fwd, is_cfg_fwd, is_mem_fwd}) + ,.addr_o(mem_fwd_dst_lo) + ,.v_o() + ); + + // All CCE-Mem network responses go to the CCE on this tile (id = 0 in xbar) + wire [2:0] dev_rev_dst_lo = '0; + + bp_me_xbar_stream + #(.bp_params_p(bp_params_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.stream_mask_p(mem_fwd_stream_mask_gp) + ,.num_source_p(1) + ,.num_sink_p(3) + ) + fwd_xbar + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.msg_header_i(mem_fwd_header_lo) + ,.msg_data_i(mem_fwd_data_lo) + ,.msg_v_i(mem_fwd_v_lo) + ,.msg_ready_and_o(mem_fwd_ready_and_li) + ,.msg_dst_i(mem_fwd_dst_lo) + + ,.msg_header_o(dev_fwd_header_li) + ,.msg_data_o(dev_fwd_data_li) + ,.msg_v_o(dev_fwd_v_li) + ,.msg_ready_and_i(dev_fwd_ready_and_lo) + ); + + bp_me_xbar_stream + #(.bp_params_p(bp_params_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.stream_mask_p(mem_rev_stream_mask_gp) + ,.num_source_p(3) + ,.num_sink_p(1) + ) + rev_xbar + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.msg_header_i(dev_rev_header_lo) + ,.msg_data_i(dev_rev_data_lo) + ,.msg_v_i(dev_rev_v_lo) + ,.msg_ready_and_o(dev_rev_ready_and_li) + ,.msg_dst_i(dev_rev_dst_lo) + + ,.msg_header_o(mem_rev_header_li) + ,.msg_data_o(mem_rev_data_li) + ,.msg_v_o(mem_rev_v_li) + ,.msg_ready_and_i(mem_rev_ready_and_lo) + ); + + // CCE: Cache Coherence Engine + bp_cce_wrapper + #(.bp_params_p(bp_params_p)) + cce + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.cfg_bus_i(cfg_bus_lo) + + ,.ucode_v_i(cce_ucode_v_lo) + ,.ucode_w_i(cce_ucode_w_lo) + ,.ucode_addr_i(cce_ucode_addr_lo) + ,.ucode_data_i(cce_ucode_data_lo) + ,.ucode_data_o(cce_ucode_data_li) + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + ,.lce_req_header_i(lce_req_header_li) + ,.lce_req_data_i(lce_req_data_li) + ,.lce_req_v_i(lce_req_v_li) + ,.lce_req_ready_and_o(lce_req_ready_and_lo) + + ,.lce_resp_header_i(lce_resp_header_li) + ,.lce_resp_data_i(lce_resp_data_li) + ,.lce_resp_v_i(lce_resp_v_li) + ,.lce_resp_ready_and_o(lce_resp_ready_and_lo) + + ,.lce_cmd_header_o(lce_cmd_header_lo) + ,.lce_cmd_data_o(lce_cmd_data_lo) + ,.lce_cmd_v_o(lce_cmd_v_lo) + ,.lce_cmd_ready_and_i(lce_cmd_ready_and_li) + + // CCE-MEM Interface + // BedRock Burst protocol: ready&valid + ,.mem_rev_header_i(mem_rev_header_li) + ,.mem_rev_data_i(mem_rev_data_li) + ,.mem_rev_v_i(mem_rev_v_li) + ,.mem_rev_ready_and_o(mem_rev_ready_and_lo) + + ,.mem_fwd_header_o(mem_fwd_header_lo) + ,.mem_fwd_data_o(mem_fwd_data_lo) + ,.mem_fwd_v_o(mem_fwd_v_lo) + ,.mem_fwd_ready_and_i(mem_fwd_ready_and_li) + ); + + // CCE-Mem network to L2 Cache adapter + `declare_bsg_cache_dma_pkt_s(daddr_width_p, l2_block_size_in_words_p); + bsg_cache_dma_pkt_s [l2_banks_p-1:0] dma_pkt_lo; + logic [l2_banks_p-1:0] dma_pkt_v_lo, dma_pkt_yumi_li; + logic [l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_li; + logic [l2_banks_p-1:0] dma_data_v_li, dma_data_ready_and_lo; + logic [l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_lo; + logic [l2_banks_p-1:0] dma_data_v_lo, dma_data_yumi_li; + bp_me_cache_slice + #(.bp_params_p(bp_params_p)) + l2s + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.mem_fwd_header_i(dev_fwd_header_li[0]) + ,.mem_fwd_data_i(dev_fwd_data_li[0]) + ,.mem_fwd_v_i(dev_fwd_v_li[0]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[0]) + + ,.mem_rev_header_o(dev_rev_header_lo[0]) + ,.mem_rev_data_o(dev_rev_data_lo[0]) + ,.mem_rev_v_o(dev_rev_v_lo[0]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[0]) + + ,.dma_pkt_o(dma_pkt_lo) + ,.dma_pkt_v_o(dma_pkt_v_lo) + ,.dma_pkt_ready_and_i(dma_pkt_yumi_li) + + ,.dma_data_i(dma_data_li) + ,.dma_data_v_i(dma_data_v_li) + ,.dma_data_ready_and_o(dma_data_ready_and_lo) + + ,.dma_data_o(dma_data_lo) + ,.dma_data_v_o(dma_data_v_lo) + ,.dma_data_ready_and_i(dma_data_yumi_li) + ); + + bp_dma_ready_and_link_s [l2_banks_p-1:0] dma_link_lo, dma_link_li; + for (genvar i = 0; i < l2_banks_p; i++) + begin : dma + wire [dma_noc_cord_width_p-1:0] cord_li = my_cord_i[coh_noc_x_cord_width_p+:dma_noc_y_cord_width_p]; + wire [dma_noc_cid_width_p-1:0] cid_li = i; + + bsg_cache_dma_to_wormhole + #(.dma_addr_width_p(daddr_width_p) + ,.dma_burst_len_p(l2_block_size_in_fill_p) + ,.dma_mask_width_p(l2_block_size_in_words_p) + + ,.wh_flit_width_p(dma_noc_flit_width_p) + ,.wh_cid_width_p(dma_noc_cid_width_p) + ,.wh_len_width_p(dma_noc_len_width_p) + ,.wh_cord_width_p(dma_noc_cord_width_p) + ) + dma2wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.dma_pkt_i(dma_pkt_lo[i]) + ,.dma_pkt_v_i(dma_pkt_v_lo[i]) + ,.dma_pkt_yumi_o(dma_pkt_yumi_li[i]) + + ,.dma_data_o(dma_data_li[i]) + ,.dma_data_v_o(dma_data_v_li[i]) + ,.dma_data_ready_and_i(dma_data_ready_and_lo[i]) + + ,.dma_data_i(dma_data_lo[i]) + ,.dma_data_v_i(dma_data_v_lo[i]) + ,.dma_data_yumi_o(dma_data_yumi_li[i]) + + ,.wh_link_sif_i(dma_link_li[i]) + ,.wh_link_sif_o(dma_link_lo[i]) + + ,.my_wh_cord_i(cord_li) + ,.my_wh_cid_i(cid_li) + // TODO: Parameterizable? + ,.dest_wh_cord_i('1) + ,.dest_wh_cid_i('0) + ); + end + + bsg_wormhole_concentrator + #(.flit_width_p(dma_noc_flit_width_p) + ,.len_width_p(dma_noc_len_width_p) + ,.cid_width_p(dma_noc_cid_width_p) + ,.cord_width_p(dma_noc_cord_width_p) + ,.num_in_p(l2_banks_p) + ,.hold_on_valid_p(1) + ) + dma_concentrate + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.links_i(dma_link_lo) + ,.links_o(dma_link_li) + + ,.concentrated_link_o(dma_link_o) + ,.concentrated_link_i(dma_link_i) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_l2e_tile_node.sv b/designs/black-parrot/src/bp/bp_l2e_tile_node.sv new file mode 100644 index 0000000..5b9b35b --- /dev/null +++ b/designs/black-parrot/src/bp/bp_l2e_tile_node.sv @@ -0,0 +1,122 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_l2e_tile_node + import bp_common_pkg::*; + import bp_be_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + ) + (input core_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input dma_clk_i + , input dma_reset_i + + , input [mem_noc_did_width_p-1:0] my_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_o + + , input [S:N][dma_noc_ral_link_width_lp-1:0] dma_link_i + , output logic [S:N][dma_noc_ral_link_width_lp-1:0] dma_link_o + ); + + // Declare the routing links + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(dma_noc_flit_width_p, bp_dma_ready_and_link_s); + + // Tile-side coherence connections + bp_coh_ready_and_link_s l2e_lce_req_link_li, l2e_lce_req_link_lo; + bp_coh_ready_and_link_s l2e_lce_cmd_link_li, l2e_lce_cmd_link_lo; + bp_coh_ready_and_link_s l2e_lce_resp_link_li, l2e_lce_resp_link_lo; + + // Tile side membus connections + bp_dma_ready_and_link_s l2e_dma_link_lo, l2e_dma_link_li; + + bp_l2e_tile + #(.bp_params_p(bp_params_p)) + l2e_tile + (.clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.my_did_i(my_did_i) + ,.my_cord_i(my_cord_i) + + ,.lce_req_link_i(l2e_lce_req_link_li) + ,.lce_req_link_o(l2e_lce_req_link_lo) + + ,.lce_cmd_link_i(l2e_lce_cmd_link_li) + ,.lce_cmd_link_o(l2e_lce_cmd_link_lo) + + ,.lce_resp_link_i(l2e_lce_resp_link_li) + ,.lce_resp_link_o(l2e_lce_resp_link_lo) + + ,.dma_link_o(l2e_dma_link_lo) + ,.dma_link_i(l2e_dma_link_li) + ); + + bp_nd_socket + #(.flit_width_p(coh_noc_flit_width_p) + ,.dims_p(coh_noc_dims_p) + ,.cord_dims_p(coh_noc_dims_p) + ,.cord_markers_pos_p(coh_noc_cord_markers_pos_p) + ,.len_width_p(coh_noc_len_width_p) + ,.routing_matrix_p(StrictYX) + ,.async_clk_p(async_coh_clk_p) + ,.els_p(3) + ) + l2e_coh_socket + (.tile_clk_i(core_clk_i) + ,.tile_reset_i(core_reset_i) + ,.network_clk_i(coh_clk_i) + ,.network_reset_i(coh_reset_i) + ,.my_cord_i(my_cord_i) + ,.network_link_i({coh_lce_req_link_i, coh_lce_cmd_link_i, coh_lce_resp_link_i}) + ,.network_link_o({coh_lce_req_link_o, coh_lce_cmd_link_o, coh_lce_resp_link_o}) + ,.tile_link_i({l2e_lce_req_link_lo, l2e_lce_cmd_link_lo, l2e_lce_resp_link_lo}) + ,.tile_link_o({l2e_lce_req_link_li, l2e_lce_cmd_link_li, l2e_lce_resp_link_li}) + ); + + bp_nd_socket + #(.flit_width_p(dma_noc_flit_width_p) + ,.dims_p(dma_noc_dims_p) + ,.cord_dims_p(dma_noc_cord_dims_p) + ,.cord_markers_pos_p(dma_noc_cord_markers_pos_p) + ,.len_width_p(dma_noc_len_width_p) + ,.routing_matrix_p(StrictX) + ,.async_clk_p(async_dma_clk_p) + ,.els_p(1) + ) + l2e_mem_socket + (.tile_clk_i(core_clk_i) + ,.tile_reset_i(core_reset_i) + ,.network_clk_i(dma_clk_i) + ,.network_reset_i(dma_reset_i) + ,.my_cord_i(my_cord_i[coh_noc_x_cord_width_p+:dma_noc_y_cord_width_p]) + ,.network_link_i(dma_link_i) + ,.network_link_o(dma_link_o) + ,.tile_link_i(l2e_dma_link_lo) + ,.tile_link_o(l2e_dma_link_li) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_lce.sv b/designs/black-parrot/src/bp/bp_lce.sv new file mode 100644 index 0000000..325e7ec --- /dev/null +++ b/designs/black-parrot/src/bp/bp_lce.sv @@ -0,0 +1,318 @@ +/** + * Name: + * bp_lce.sv + * + * + * Description: + * Generic Local Cache/Coherence Engine (LCE). + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_lce + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // parameters specific to this LCE (these match the cache managed by the LCE) + , parameter `BSG_INV_PARAM(assoc_p) + , parameter `BSG_INV_PARAM(sets_p) + , parameter `BSG_INV_PARAM(block_width_p) + , parameter `BSG_INV_PARAM(fill_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(id_width_p) + + // LCE-cache interface timeout in cycles + , parameter timeout_max_limit_p=4 + // maximum number of outstanding transactions + , parameter credits_p = coh_noc_max_credits_p + // issue non-exclusive read requests + , parameter non_excl_reads_p = 0 + , parameter `BSG_INV_PARAM(tag_width_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + `declare_bp_cache_engine_generic_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p, cache) + ) + ( + input clk_i + , input reset_i + + // LCE Configuration + , input [did_width_p-1:0] did_i + , input [lce_id_width_p-1:0] lce_id_i + , input bp_lce_mode_e lce_mode_i + + // Cache-LCE Interface + // valid->yumi; metadata is valid once after request valid + // metadata arrives in the same cycle as req, or any cycle after, but before the next request + // can arrive, as indicated by the metadata_v_i signal + , input [cache_req_width_lp-1:0] cache_req_i + , input cache_req_v_i + , output logic cache_req_yumi_o + , output logic cache_req_lock_o + , input [cache_req_metadata_width_lp-1:0] cache_req_metadata_i + , input cache_req_metadata_v_i + , output logic cache_req_critical_o + , output logic [id_width_p-1:0] cache_req_id_o + , output logic cache_req_last_o + , output logic cache_req_credits_full_o + , output logic cache_req_credits_empty_o + + // LCE-Cache Interface + // valid->yumi + // commands issued that read and return data have data returned the cycle after + // the valid->yumi command handshake occurs + , output logic tag_mem_pkt_v_o + , output logic [cache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_o + , input tag_mem_pkt_yumi_i + , input [cache_tag_info_width_lp-1:0] tag_mem_i + + , output logic data_mem_pkt_v_o + , output logic [cache_data_mem_pkt_width_lp-1:0] data_mem_pkt_o + , input data_mem_pkt_yumi_i + , input [block_width_p-1:0] data_mem_i + + , output logic stat_mem_pkt_v_o + , output logic [cache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_o + , input stat_mem_pkt_yumi_i + , input [cache_stat_info_width_lp-1:0] stat_mem_i + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , output logic [lce_req_header_width_lp-1:0] lce_req_header_o + , output logic [bedrock_fill_width_p-1:0] lce_req_data_o + , output logic lce_req_v_o + , input lce_req_ready_and_i + + , input [lce_cmd_header_width_lp-1:0] lce_cmd_header_i + , input [bedrock_fill_width_p-1:0] lce_cmd_data_i + , input lce_cmd_v_i + , output logic lce_cmd_ready_and_o + + , input [lce_fill_header_width_lp-1:0] lce_fill_header_i + , input [bedrock_fill_width_p-1:0] lce_fill_data_i + , input lce_fill_v_i + , output logic lce_fill_ready_and_o + + , output logic [lce_fill_header_width_lp-1:0] lce_fill_header_o + , output logic [bedrock_fill_width_p-1:0] lce_fill_data_o + , output logic lce_fill_v_o + , input lce_fill_ready_and_i + + , output logic [lce_resp_header_width_lp-1:0] lce_resp_header_o + , output logic [bedrock_fill_width_p-1:0] lce_resp_data_o + , output logic lce_resp_v_o + , input lce_resp_ready_and_i + ); + + // LCE/Cache Parameter Constraints + if ((sets_p <= 1) || !(`BSG_IS_POW2(sets_p))) + $error("LCE sets must be greater than 1 and power of two"); + if (!(`BSG_IS_POW2(assoc_p))) + $error("LCE assoc must be power of two"); + if (!(`BSG_IS_POW2(block_width_p))) + $error("LCE block width must be a power of two"); + if (block_width_p < 64 || block_width_p > 1024) + $error("LCE block width must be between 8 and 128 bytes"); + // cache request packet data width == dword_width_gp + // LCE only supports single data beat for requests + if (fill_width_p < dword_width_gp) + $error("fill width must be greater or equal than cache request data width"); + + `declare_bp_cache_engine_generic_if(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p, cache); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + // LCE Request Module + logic req_busy_lo; + logic credit_return_lo; + logic cache_req_done_lo; + logic sync_done_lo; + logic cache_init_done_lo; + bp_lce_req + #(.bp_params_p(bp_params_p) + ,.assoc_p(assoc_p) + ,.sets_p(sets_p) + ,.block_width_p(block_width_p) + ,.fill_width_p(fill_width_p) + ,.data_width_p(data_width_p) + ,.tag_width_p(tag_width_p) + ,.credits_p(credits_p) + ,.non_excl_reads_p(non_excl_reads_p) + ,.id_width_p(id_width_p) + ) + request + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.did_i(did_i) + ,.lce_id_i(lce_id_i) + ,.lce_mode_i(lce_mode_i) + ,.sync_done_i(sync_done_lo) + ,.cache_init_done_i(cache_init_done_lo) + + ,.busy_o(req_busy_lo) + + ,.cache_req_i(cache_req_i) + ,.cache_req_v_i(cache_req_v_i) + ,.cache_req_yumi_o(cache_req_yumi_o) + ,.cache_req_metadata_i(cache_req_metadata_i) + ,.cache_req_metadata_v_i(cache_req_metadata_v_i) + ,.cache_req_credits_full_o(cache_req_credits_full_o) + ,.cache_req_credits_empty_o(cache_req_credits_empty_o) + ,.credit_return_i(credit_return_lo) + ,.cache_req_done_i(cache_req_done_lo) + + ,.lce_req_header_o(lce_req_header_o) + ,.lce_req_data_o(lce_req_data_o) + ,.lce_req_v_o(lce_req_v_o) + ,.lce_req_ready_and_i(lce_req_ready_and_i) + ); + + // To prevent unnecessary arbitration on the critical cache request ports, we multiplex + // LCE cmds and LCE fills into a single stream at this point. This could be done for + // perhaps a bit less overhead at the netlist level, but it's more challenging to + // verify protocol/deadlock correctness at that level. At this level, we can simply + // say that it's sufficient to buffer a full output fill message such that it's never + // the case that an input cmd is blocked by an output fill + bp_bedrock_lce_cmd_header_s lce_cmd_header_li; + logic [fill_width_p-1:0] lce_cmd_data_li; + logic lce_cmd_v_li, lce_cmd_ready_and_lo; + + bp_me_xbar_stream + #(.bp_params_p(bp_params_p) + ,.payload_width_p(lce_cmd_payload_width_lp) + ,.stream_mask_p(lce_cmd_stream_mask_gp) + ,.num_source_p(2) + ,.num_sink_p(1) + ) + lce_cmd_fill_xbar + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i({lce_cmd_header_i, lce_fill_header_i}) + ,.msg_data_i({lce_cmd_data_i, lce_fill_data_i}) + ,.msg_v_i({lce_cmd_v_i, lce_fill_v_i}) + ,.msg_ready_and_o({lce_cmd_ready_and_o, lce_fill_ready_and_o}) + ,.msg_dst_i('0) // Single destination + + ,.msg_header_o(lce_cmd_header_li) + ,.msg_data_o(lce_cmd_data_li) + ,.msg_v_o(lce_cmd_v_li) + ,.msg_ready_and_i(lce_cmd_ready_and_lo) + ); + + bp_bedrock_lce_fill_header_s lce_fill_header_lo; + logic [fill_width_p-1:0] lce_fill_data_lo; + logic lce_fill_v_lo, lce_fill_ready_and_li; + bsg_two_fifo + #(.width_p(fill_width_p+$bits(bp_bedrock_lce_fill_header_s))) + lce_fill_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i({lce_fill_data_lo, lce_fill_header_lo}) + ,.v_i(lce_fill_v_lo) + ,.ready_param_o(lce_fill_ready_and_li) + + ,.data_o({lce_fill_data_o, lce_fill_header_o}) + ,.v_o(lce_fill_v_o) + ,.yumi_i(lce_fill_ready_and_i & lce_fill_v_o) + ); + + // LCE Command Module + bp_lce_cmd + #(.bp_params_p(bp_params_p) + ,.assoc_p(assoc_p) + ,.sets_p(sets_p) + ,.block_width_p(block_width_p) + ,.fill_width_p(fill_width_p) + ,.data_width_p(data_width_p) + ,.tag_width_p(tag_width_p) + ,.id_width_p(id_width_p) + ) + command + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.lce_id_i(lce_id_i) + ,.lce_mode_i(lce_mode_i) + + ,.cache_init_done_o(cache_init_done_lo) + ,.sync_done_o(sync_done_lo) + ,.cache_req_id_o(cache_req_id_o) + ,.cache_req_critical_o(cache_req_critical_o) + ,.cache_req_last_o(cache_req_last_o) + ,.credit_return_o(credit_return_lo) + ,.cache_req_done_o(cache_req_done_lo) + + ,.data_mem_pkt_o(data_mem_pkt_o) + ,.data_mem_pkt_v_o(data_mem_pkt_v_o) + ,.data_mem_pkt_yumi_i(data_mem_pkt_yumi_i) + ,.data_mem_i(data_mem_i) + + ,.tag_mem_pkt_o(tag_mem_pkt_o) + ,.tag_mem_pkt_v_o(tag_mem_pkt_v_o) + ,.tag_mem_pkt_yumi_i(tag_mem_pkt_yumi_i) + ,.tag_mem_i(tag_mem_i) + + ,.stat_mem_pkt_o(stat_mem_pkt_o) + ,.stat_mem_pkt_v_o(stat_mem_pkt_v_o) + ,.stat_mem_pkt_yumi_i(stat_mem_pkt_yumi_i) + ,.stat_mem_i(stat_mem_i) + + ,.lce_cmd_header_i(lce_cmd_header_li) + ,.lce_cmd_data_i(lce_cmd_data_li) + ,.lce_cmd_v_i(lce_cmd_v_li) + ,.lce_cmd_ready_and_o(lce_cmd_ready_and_lo) + + ,.lce_fill_header_o(lce_fill_header_lo) + ,.lce_fill_data_o(lce_fill_data_lo) + ,.lce_fill_v_o(lce_fill_v_lo) + ,.lce_fill_ready_and_i(lce_fill_ready_and_li) + + ,.lce_resp_header_o(lce_resp_header_o) + ,.lce_resp_data_o(lce_resp_data_o) + ,.lce_resp_v_o(lce_resp_v_o) + ,.lce_resp_ready_and_i(lce_resp_ready_and_i) + ); + + // LCE timeout logic + // + // LCE can read/write to data_mem, tag_mem, and stat_mem during cycles the cache itself is + // not using them. To prevent the LCE from stalling for too long while waiting for one of + // these ports, or when processing an inbound LCE command, there is a timer that raises the + // LCE's busy_o signal to prevent the cache from issuing a new request, thereby + // freeing up a cycle for the LCE to use these resources. + + logic [`BSG_SAFE_CLOG2(timeout_max_limit_p+1)-1:0] timeout_cnt_r; + wire coherence_blocked = + (data_mem_pkt_v_o & ~data_mem_pkt_yumi_i) + | (tag_mem_pkt_v_o & ~tag_mem_pkt_yumi_i) + | (stat_mem_pkt_v_o & ~stat_mem_pkt_yumi_i); + + bsg_counter_clear_up + #(.max_val_p(timeout_max_limit_p) + ,.init_val_p(0) + ,.disable_overflow_warning_p(1) + ) + timeout_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(~coherence_blocked) + ,.up_i(coherence_blocked) + ,.count_o(timeout_cnt_r) + ); + wire timeout = (timeout_cnt_r == timeout_max_limit_p); + + // LCE is ready to accept new cache requests if: + // - LCE Request module is ready to accept a request (does not account for a free credit) + // - timout signal is low, indicating LCE isn't blocked on using data/tag/stat mem + // This signal acts as a hint to the cache that the LCE is not ready for a request. + // The cache_req_yumi_o signal actually controls whether the LCE accepts a request. + assign cache_req_lock_o = timeout | req_busy_lo | ~cache_init_done_lo; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_lce) diff --git a/designs/black-parrot/src/bp/bp_lce_cmd.sv b/designs/black-parrot/src/bp/bp_lce_cmd.sv new file mode 100644 index 0000000..da61d84 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_lce_cmd.sv @@ -0,0 +1,726 @@ +/** + * Name: + * bp_lce_cmd.sv + * + * Description: + * LCE command handler + * + * The LCE Command module processes inbound commands and issues responses to the CCE + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_lce_cmd + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // parameters specific to this LCE (these match the cache managed by the LCE) + , parameter `BSG_INV_PARAM(assoc_p) + , parameter `BSG_INV_PARAM(sets_p) + , parameter `BSG_INV_PARAM(block_width_p) + , parameter `BSG_INV_PARAM(fill_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(tag_width_p) + , parameter `BSG_INV_PARAM(id_width_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + `declare_bp_cache_engine_generic_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p, cache) + ) + ( + input clk_i + , input reset_i + + // LCE Configuration + , input [lce_id_width_p-1:0] lce_id_i + , input bp_lce_mode_e lce_mode_i + + , output logic cache_init_done_o + , output logic sync_done_o + + // LCE-Cache Interface + // valid->yumi + // commands issued that read and return data have data returned the cycle after + // the valid->yumi command handshake occurs + , output logic tag_mem_pkt_v_o + , output logic [cache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_o + , input tag_mem_pkt_yumi_i + , input [cache_tag_info_width_lp-1:0] tag_mem_i + + , output logic data_mem_pkt_v_o + , output logic [cache_data_mem_pkt_width_lp-1:0] data_mem_pkt_o + , input data_mem_pkt_yumi_i + , input [block_width_p-1:0] data_mem_i + + , output logic stat_mem_pkt_v_o + , output logic [cache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_o + , input stat_mem_pkt_yumi_i + , input [cache_stat_info_width_lp-1:0] stat_mem_i + + // request complete signals + // cached requests and uncached loads block in the caches, but uncached stores do not + // cache_req_last_o is routed to the cache to indicate a blocking request is complete + , output logic [id_width_p-1:0] cache_req_id_o + , output logic cache_req_critical_o + , output logic cache_req_last_o + + // uncached store request complete is used by the LCE to decrement the request credit counter + // when an uncached store complete, but is not routed to the cache because the caches do not + // block (miss) on uncached stores + , output logic credit_return_o + , output logic cache_req_done_o + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , input [lce_cmd_header_width_lp-1:0] lce_cmd_header_i + , input [bedrock_fill_width_p-1:0] lce_cmd_data_i + , input lce_cmd_v_i + , output logic lce_cmd_ready_and_o + + , output logic [lce_fill_header_width_lp-1:0] lce_fill_header_o + , output logic [bedrock_fill_width_p-1:0] lce_fill_data_o + , output logic lce_fill_v_o + , input lce_fill_ready_and_i + + , output logic [lce_resp_header_width_lp-1:0] lce_resp_header_o + , output logic [bedrock_fill_width_p-1:0] lce_resp_data_o + , output logic lce_resp_v_o + , input lce_resp_ready_and_i + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_cache_engine_generic_if(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p, cache); + `bp_cast_i(bp_bedrock_lce_cmd_header_s, lce_cmd_header); + `bp_cast_o(bp_bedrock_lce_fill_header_s, lce_fill_header); + `bp_cast_o(bp_bedrock_lce_resp_header_s, lce_resp_header); + + `bp_cast_o(bp_cache_data_mem_pkt_s, data_mem_pkt); + `bp_cast_o(bp_cache_tag_mem_pkt_s, tag_mem_pkt); + `bp_cast_o(bp_cache_stat_mem_pkt_s, stat_mem_pkt); + + // number of fill per block + localparam block_size_in_fill_lp = block_width_p / fill_width_p; + // number of bits to select fill per block + localparam fill_cnt_width_lp = `BSG_SAFE_CLOG2(block_size_in_fill_lp); + localparam fill_offset_width_lp = `BSG_SAFE_CLOG2(fill_width_p>>3); + localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p); + localparam lg_sets_lp = `BSG_SAFE_CLOG2(sets_p); + // bytes per cache block + localparam block_size_in_bytes_lp = (block_width_p/8); + // number of bits for byte select in block + localparam block_byte_offset_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_lp); + // tag offset + localparam tag_offset_lp = block_byte_offset_lp + (sets_p > 1 ? lg_sets_lp : 0); + // coherence request size for cached requests + localparam cmd_block_size_lp = bp_bedrock_msg_size_e'(`BSG_SAFE_CLOG2(block_width_p/8)); + + // FSM states + enum logic [3:0] { + e_reset + ,e_clear + ,e_ready + ,e_tr + ,e_stat_clear + ,e_wb + ,e_wb_dirty_rd + ,e_coh_ack + } state_n, state_r; + + bp_bedrock_lce_cmd_header_s fsm_cmd_header_li; + logic [paddr_width_p-1:0] fsm_cmd_addr_li; + logic [fill_width_p-1:0] fsm_cmd_data_li; + logic fsm_cmd_v_li, fsm_cmd_yumi_lo; + logic fsm_cmd_new_li, fsm_cmd_critical_li, fsm_cmd_last_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(fill_width_p) + ,.payload_width_p(lce_cmd_payload_width_lp) + ,.msg_stream_mask_p(lce_cmd_stream_mask_gp) + ,.fsm_stream_mask_p(lce_cmd_stream_mask_gp) + ) + cmd_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(lce_cmd_header_cast_i) + ,.msg_data_i(lce_cmd_data_i) + ,.msg_v_i(lce_cmd_v_i) + ,.msg_ready_and_o(lce_cmd_ready_and_o) + + ,.fsm_header_o(fsm_cmd_header_li) + ,.fsm_addr_o(fsm_cmd_addr_li) + ,.fsm_data_o(fsm_cmd_data_li) + ,.fsm_v_o(fsm_cmd_v_li) + ,.fsm_yumi_i(fsm_cmd_yumi_lo) + ,.fsm_new_o(fsm_cmd_new_li) + ,.fsm_critical_o(fsm_cmd_critical_li) + ,.fsm_last_o(fsm_cmd_last_li) + ); + + // Save off the command header for usage in fill and resp networks + bp_bedrock_lce_cmd_header_s fsm_cmd_header_r; + bsg_dff_en + #(.width_p($bits(bp_bedrock_lce_cmd_header_s))) + fsm_cmd_header_reg + (.clk_i(clk_i) + ,.en_i(fsm_cmd_yumi_lo) + ,.data_i(fsm_cmd_header_li) + ,.data_o(fsm_cmd_header_r) + ); + + bp_bedrock_lce_fill_header_s fsm_fill_header_lo; + logic [fill_width_p-1:0] fsm_fill_data_lo; + logic fsm_fill_v_lo, fsm_fill_ready_then_li; + logic [paddr_width_p-1:0] fsm_fill_addr_lo; + logic fsm_fill_new_lo, fsm_fill_critical_lo, fsm_fill_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(fill_width_p) + ,.payload_width_p(lce_fill_payload_width_lp) + ,.msg_stream_mask_p(lce_fill_stream_mask_gp) + ,.fsm_stream_mask_p(lce_fill_stream_mask_gp) + ) + lce_fill_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(lce_fill_header_cast_o) + ,.msg_data_o(lce_fill_data_o) + ,.msg_v_o(lce_fill_v_o) + ,.msg_ready_and_i(lce_fill_ready_and_i) + + ,.fsm_header_i(fsm_fill_header_lo) + ,.fsm_addr_o(fsm_fill_addr_lo) + ,.fsm_data_i(fsm_fill_data_lo) + ,.fsm_v_i(fsm_fill_v_lo) + ,.fsm_ready_then_o(fsm_fill_ready_then_li) + ,.fsm_new_o(fsm_fill_new_lo) + ,.fsm_critical_o(fsm_fill_critical_lo) + ,.fsm_last_o(fsm_fill_last_lo) + ); + + bp_bedrock_lce_resp_header_s fsm_resp_header_lo; + logic [fill_width_p-1:0] fsm_resp_data_lo; + logic fsm_resp_v_lo, fsm_resp_ready_then_li; + logic [paddr_width_p-1:0] fsm_resp_addr_lo; + logic fsm_resp_new_lo, fsm_resp_critical_lo, fsm_resp_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(fill_width_p) + ,.payload_width_p(lce_resp_payload_width_lp) + ,.msg_stream_mask_p(lce_resp_stream_mask_gp) + ,.fsm_stream_mask_p(lce_resp_stream_mask_gp) + ) + lce_resp_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(lce_resp_header_cast_o) + ,.msg_data_o(lce_resp_data_o) + ,.msg_v_o(lce_resp_v_o) + ,.msg_ready_and_i(lce_resp_ready_and_i) + + ,.fsm_header_i(fsm_resp_header_lo) + ,.fsm_addr_o(fsm_resp_addr_lo) + ,.fsm_data_i(fsm_resp_data_lo) + ,.fsm_v_i(fsm_resp_v_lo) + ,.fsm_ready_then_o(fsm_resp_ready_then_li) + ,.fsm_new_o(fsm_resp_new_lo) + ,.fsm_critical_o(fsm_resp_critical_lo) + ,.fsm_last_o(fsm_resp_last_lo) + ); + + logic [block_width_p-1:0] dirty_data_r; + wire dirty_data_read = data_mem_pkt_yumi_i & (data_mem_pkt_cast_o.opcode == e_cache_data_mem_read); + bsg_dff_sync_read + #(.width_p(block_width_p), .bypass_p(1)) + dirty_data_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(data_mem_i) + ,.v_n_i(dirty_data_read) + + ,.data_o(dirty_data_r) + ); + + // data mux to pick fill word for sending in command/response data beat + logic [fill_width_p-1:0] dirty_data_selected; + logic [`BSG_SAFE_CLOG2(block_size_in_fill_lp)-1:0] dirty_data_select; + bsg_mux + #(.width_p(fill_width_p), .els_p(block_size_in_fill_lp)) + dirty_data_mux + (.data_i(dirty_data_r) + ,.sel_i(dirty_data_select) + ,.data_o(dirty_data_selected) + ); + + bp_cache_tag_info_s dirty_tag_r; + wire dirty_tag_read = tag_mem_pkt_yumi_i & (tag_mem_pkt_cast_o.opcode == e_cache_tag_mem_read); + bsg_dff_sync_read + #(.width_p($bits(bp_cache_tag_info_s)), .bypass_p(1)) + dirty_tag_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(tag_mem_i) + ,.v_n_i(dirty_tag_read) + + ,.data_o(dirty_tag_r) + ); + + bp_cache_stat_info_s dirty_stat_r; + wire dirty_stat_read = stat_mem_pkt_yumi_i & (stat_mem_pkt_cast_o.opcode == e_cache_stat_mem_read); + bsg_dff_sync_read + #(.width_p($bits(bp_cache_stat_info_s)), .bypass_p(1)) + dirty_stat_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(stat_mem_i) + ,.v_n_i(dirty_stat_read) + + ,.data_o(dirty_stat_r) + ); + + // LCE Command module is ready after it clears the cache's tag and stat memories + assign cache_init_done_o = (state_r != e_reset) && (state_r != e_clear); + + // counter used by Command FSM to perform sync sequence + // width for counter used during initiliazation and for sync messages + localparam cnt_width_lp = `BSG_MAX(cce_id_width_p+1, `BSG_SAFE_CLOG2(sets_p)+1); + localparam cnt_max_val_lp = ((2**cnt_width_lp)-1); + + logic cnt_inc, cnt_clear; + logic [cnt_width_lp-1:0] cnt_r; + bsg_counter_clear_up + #(.max_val_p(cnt_max_val_lp) + ,.init_val_p(0) + ,.disable_overflow_warning_p(1) + ) + counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(cnt_clear) + ,.up_i(cnt_inc) + ,.count_o(cnt_r) + ); + + wire sync_done = (state_r == e_ready) & cnt_clear; + bsg_dff_reset_set_clear + #(.width_p(1)) + sync_done_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.set_i(sync_done) + ,.clear_i(1'b0) + ,.data_o(sync_done_o) + ); + + localparam bank_width_lp = block_width_p / assoc_p; + localparam byte_offset_width_lp = `BSG_SAFE_CLOG2(bank_width_lp>>3); + localparam bank_offset_width_lp = `BSG_SAFE_CLOG2(assoc_p); + localparam fill_size_in_bank_lp = fill_width_p / bank_width_lp; + localparam bank_sub_offset_width_lp = $clog2(fill_size_in_bank_lp); + wire [block_size_in_fill_lp-1:0] fill_index_shift = {{(assoc_p != 1){fsm_cmd_addr_li[byte_offset_width_lp+:bank_offset_width_lp] >> bank_sub_offset_width_lp}}, {(assoc_p == 1){'0}}}; + + always_comb begin + + state_n = state_r; + + credit_return_o = '0; + // raised request is fully resolved + cache_req_done_o = '0; + cache_req_last_o = 1'b0; + cache_req_critical_o = 1'b0; + cache_req_id_o = '0; // Only 1 outstanding request supported + + // LCE-CCE Interface signals + fsm_cmd_yumi_lo = 1'b0; + + fsm_fill_header_lo = '0; + fsm_fill_data_lo = '0; + fsm_fill_v_lo = 1'b0; + + fsm_resp_header_lo = '0; + fsm_resp_data_lo = '0; + fsm_resp_v_lo = 1'b0; + + // Counter + cnt_inc = 1'b0; + cnt_clear = 1'b0; + dirty_data_select = '0; + + // LCE-Cache Interface signals + data_mem_pkt_cast_o = '0; + data_mem_pkt_v_o = 1'b0; + tag_mem_pkt_cast_o = '0; + tag_mem_pkt_v_o = 1'b0; + stat_mem_pkt_cast_o = '0; + stat_mem_pkt_v_o = 1'b0; + + // Command FSM + unique case (state_r) + + e_reset: begin + state_n = e_clear; + end + + // After reset is complete, the LCE Command module clears the tag and stat memories + // of the cache it manages, initializing the cache for operation. + e_clear: begin + tag_mem_pkt_cast_o.index = cnt_r[0+:lg_sets_lp]; + tag_mem_pkt_cast_o.state = e_COH_I; + tag_mem_pkt_cast_o.tag = '0; + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_clear; + tag_mem_pkt_v_o = 1'b1; + + stat_mem_pkt_cast_o.index = cnt_r[0+:lg_sets_lp]; + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_set_clear; + stat_mem_pkt_v_o = 1'b1; + + cnt_clear = (cnt_r == cnt_width_lp'(sets_p-1)) & tag_mem_pkt_yumi_i & stat_mem_pkt_yumi_i; + cnt_inc = (cnt_r < cnt_width_lp'(sets_p-1)) & tag_mem_pkt_yumi_i & stat_mem_pkt_yumi_i; + + state_n = cnt_clear ? e_ready : state_r; + end + + // Ready for LCE Commands + // A command is dequeued when the command module finishes processing the command. + e_ready: begin + unique case (fsm_cmd_header_li.msg_type.cmd) + + /* + * Commands that don't read/write cache data memory + */ + + // Sync + e_bedrock_cmd_sync: begin + fsm_resp_header_lo.payload.dst_id = fsm_cmd_header_li.payload.src_id; + fsm_resp_header_lo.payload.src_id = lce_id_i; + fsm_resp_header_lo.msg_type.resp = e_bedrock_resp_sync_ack; + // handshake + // response (r&v) can send when header is valid + fsm_resp_v_lo = fsm_resp_ready_then_li & fsm_cmd_v_li; + // header (v->y) consumed when response sends + fsm_cmd_yumi_lo = fsm_resp_v_lo; + + // reset the counter when last sync is received and ack is sent + cnt_clear = (cnt_r == cnt_width_lp'(num_cce_p-1)) & fsm_cmd_yumi_lo; + // increment as long as not resetting counter + cnt_inc = (cnt_r < cnt_width_lp'(num_cce_p-1)) & fsm_cmd_yumi_lo; + end + + // Set Clear - invalidate entire set specified by command + // cache tag and stat writes are idempotent + e_bedrock_cmd_set_clear: begin + tag_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_clear; + tag_mem_pkt_v_o = fsm_cmd_v_li; + + stat_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_set_clear; + stat_mem_pkt_v_o = fsm_cmd_v_li; + + // consume header when tag and stat packets consumed together + fsm_cmd_yumi_lo = tag_mem_pkt_yumi_i & stat_mem_pkt_yumi_i; + + end + + // Invalidate Tag - write tag mem and send Invalidate Ack + // cache tag write is idempotent + e_bedrock_cmd_inv: begin + tag_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + tag_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + tag_mem_pkt_cast_o.state = e_COH_I; + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_state; + tag_mem_pkt_v_o = fsm_resp_ready_then_li & fsm_cmd_v_li; + + // response can send if tag mem packet consumed by cache + fsm_resp_v_lo = tag_mem_pkt_yumi_i; + fsm_resp_header_lo.addr = fsm_cmd_header_li.addr; + fsm_resp_header_lo.msg_type.resp = e_bedrock_resp_inv_ack; + fsm_resp_header_lo.payload.src_id = lce_id_i; + fsm_resp_header_lo.payload.dst_id = fsm_cmd_header_li.payload.src_id; + + // consume command header when response sends + fsm_cmd_yumi_lo = fsm_resp_v_lo; + + end + + // Set State + // Write the state as commanded, no response sent + // cache tag write is idempotent + // Set State and Wakeup + e_bedrock_cmd_st + , e_bedrock_cmd_st_wakeup: begin + tag_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + tag_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + tag_mem_pkt_cast_o.state = fsm_cmd_header_li.payload.state; + tag_mem_pkt_cast_o.tag = '0; + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_state; + tag_mem_pkt_v_o = fsm_cmd_v_li; + + data_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + + // consume header when tag write consumed by cache + fsm_cmd_yumi_lo = tag_mem_pkt_yumi_i; + + // inform cache that tag is returning to resolve miss + cache_req_critical_o = fsm_cmd_v_li & (fsm_cmd_header_li.msg_type inside {e_bedrock_cmd_st_wakeup}); + + state_n = (tag_mem_pkt_yumi_i && (fsm_cmd_header_li.msg_type inside {e_bedrock_cmd_st_wakeup})) + ? e_coh_ack + : state_r; + end + + /* + * Commands that read/write cache data memory + */ + + // Data and Tag - cache block data, tag, and state from coherence directory + // completes a regular cache miss + // sends tag in this state, and data in next state + e_bedrock_cmd_data: begin + tag_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + tag_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + tag_mem_pkt_cast_o.state = fsm_cmd_header_li.payload.state; + tag_mem_pkt_cast_o.tag = fsm_cmd_header_li.addr[tag_offset_lp+:tag_width_p]; + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_tag; + tag_mem_pkt_v_o = fsm_cmd_v_li & fsm_cmd_new_li; + + data_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + data_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + data_mem_pkt_cast_o.data = fsm_cmd_data_li; + data_mem_pkt_cast_o.fill_index = 1'b1 << fill_index_shift; + data_mem_pkt_cast_o.opcode = e_cache_data_mem_write; + data_mem_pkt_v_o = fsm_cmd_v_li; + + fsm_cmd_yumi_lo = (~tag_mem_pkt_v_o | tag_mem_pkt_yumi_i) & data_mem_pkt_yumi_i; + + cache_req_critical_o = fsm_cmd_v_li & fsm_cmd_critical_li; + + state_n = (fsm_cmd_yumi_lo & fsm_cmd_last_li) + ? e_coh_ack + : state_r; + end + + // Uncached Data - uncached load returning from memory + // sends data to cache and raises request complete signal for one cycle + // requires valid header (buffered) and data + // note: supports uncached accesses up to dword_width_gp size + e_bedrock_cmd_uc_data: begin + data_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + // This replication only works for up to 64b uncached requests + data_mem_pkt_cast_o.data = {(fill_width_p/dword_width_gp){fsm_cmd_data_li[0+:dword_width_gp]}}; + data_mem_pkt_cast_o.opcode = e_cache_data_mem_uncached; + data_mem_pkt_v_o = fsm_cmd_v_li; + + // consume single data beat and header when data packet is consumed by cache + fsm_cmd_yumi_lo = data_mem_pkt_yumi_i & fsm_cmd_new_li; + + // raise request complete signal when data consumed + cache_req_critical_o = fsm_cmd_v_li & fsm_cmd_critical_li; + cache_req_last_o = cache_req_critical_o; + cache_req_done_o = fsm_cmd_yumi_lo & cache_req_last_o; + credit_return_o = cache_req_done_o; + end + + // Uncached Store/Req Done + e_bedrock_cmd_uc_st_done: begin + fsm_cmd_yumi_lo = fsm_cmd_v_li; + credit_return_o = fsm_cmd_yumi_lo; + end + + // Writeback + // Set State and Writeback + e_bedrock_cmd_wb + , e_bedrock_cmd_st_wb: begin + // read block from data mem + // data will be available in the first cycle of e_wb state + data_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + data_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + data_mem_pkt_cast_o.opcode = e_cache_data_mem_read; + data_mem_pkt_v_o = fsm_cmd_v_li; + + // update state - write is idempotent + tag_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + tag_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + tag_mem_pkt_cast_o.state = fsm_cmd_header_li.payload.state; + tag_mem_pkt_cast_o.tag = fsm_cmd_header_li.addr[tag_offset_lp+:tag_width_p]; + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_state; + tag_mem_pkt_v_o = fsm_cmd_v_li + & (fsm_cmd_header_li.msg_type.cmd inside {e_bedrock_cmd_st_wb}); + + // read stat mem to determine if line is dirty + stat_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + stat_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_read; + stat_mem_pkt_v_o = fsm_cmd_v_li; + + fsm_cmd_yumi_lo = data_mem_pkt_yumi_i & stat_mem_pkt_yumi_i & (~tag_mem_pkt_v_o | tag_mem_pkt_yumi_i); + + state_n = fsm_cmd_yumi_lo + ? e_wb + : state_r; + + end + + // Transfer + // Set State and Transfer + // Set State, Transfer, and Writeback + e_bedrock_cmd_tr + , e_bedrock_cmd_st_tr + , e_bedrock_cmd_st_tr_wb: begin + // read block from data mem + // data will be available in the first cycle of e_tr state + data_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + data_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + data_mem_pkt_cast_o.opcode = e_cache_data_mem_read; + data_mem_pkt_v_o = fsm_cmd_v_li; + + // update state + tag_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + tag_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + tag_mem_pkt_cast_o.state = fsm_cmd_header_li.payload.state; + tag_mem_pkt_cast_o.tag = fsm_cmd_header_li.addr[tag_offset_lp+:tag_width_p]; + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_state; + tag_mem_pkt_v_o = fsm_cmd_v_li + & (fsm_cmd_header_li.msg_type.cmd inside {e_bedrock_cmd_st_tr, e_bedrock_cmd_st_tr_wb}); + + // try to speculatively read stat memory for writeback + stat_mem_pkt_cast_o.index = fsm_cmd_header_li.addr[block_byte_offset_lp+:lg_sets_lp]; + stat_mem_pkt_cast_o.way_id = fsm_cmd_header_li.payload.way_id[0+:lg_assoc_lp]; + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_read; + stat_mem_pkt_v_o = fsm_cmd_v_li + & (fsm_cmd_header_li.msg_type.cmd == e_bedrock_cmd_st_tr_wb); + + // for both of these commands, do the transfer next + state_n = (data_mem_pkt_yumi_i & (~tag_mem_pkt_v_o | tag_mem_pkt_yumi_i) & (~stat_mem_pkt_v_o | stat_mem_pkt_yumi_i)) + ? e_tr + : state_r; + + end + + // for other message types in this state, use default as defined at top. + default: begin + state_n = state_r; + end + + endcase // cmd.msg_type case + end // e_ready + + // Transfer + // send e_bedrock_fill_data header to target LCE + // three commands enter this state: tr, st_tr, and st_tr_wb + e_tr: begin + + fsm_fill_header_lo.msg_type.fill = e_bedrock_fill_data; + fsm_fill_header_lo.addr = fsm_cmd_header_li.addr; + fsm_fill_header_lo.size = bp_bedrock_msg_size_e'(cmd_block_size_lp); + fsm_fill_header_lo.payload.dst_id = fsm_cmd_header_li.payload.target; + // set src to be the CCE that sent the transfer command so the destination LCE knows + // which CCE it must send its coherence ack to when the data command arrives + fsm_fill_header_lo.payload.src_id = fsm_cmd_header_li.payload.src_id; + fsm_fill_header_lo.payload.way_id = fsm_cmd_header_li.payload.target_way_id; + fsm_fill_header_lo.payload.state = fsm_cmd_header_li.payload.target_state; + + dirty_data_select = fsm_fill_addr_lo[fill_offset_width_lp+:fill_cnt_width_lp]; + fsm_fill_data_lo = dirty_data_selected; + + // handshake - r&v + fsm_fill_v_lo = fsm_fill_ready_then_li & fsm_cmd_v_li; + fsm_cmd_yumi_lo = fsm_fill_v_lo & fsm_fill_last_lo; + + // send transfer data in next state + state_n = fsm_cmd_yumi_lo + ? (fsm_cmd_header_li.msg_type.cmd == e_bedrock_cmd_st_tr_wb) + ? e_wb + : ((fsm_cmd_header_li.msg_type.cmd == e_bedrock_cmd_st_tr) && fsm_cmd_header_li.payload.state == e_COH_I) + ? e_stat_clear + : e_ready + : state_r; + + end // e_tr + + // Transfer Data to target LCE + e_stat_clear: begin + + // clear dirty bit if command is e_lce_st_tr (not doing writeback) and block + // is changing to invalid, since transfer target will take ownership of dirty block. + // Thus, this LCE needs to make block clean (without the writeback). + stat_mem_pkt_cast_o.index = fsm_cmd_header_r.addr[block_byte_offset_lp+:lg_sets_lp]; + stat_mem_pkt_cast_o.way_id = fsm_cmd_header_r.payload.way_id[0+:lg_assoc_lp]; + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_clear_dirty; + stat_mem_pkt_v_o = 1'b1; + + // move to next state when last data beat sends + // do a writeback if needed, otherwise go to ready + state_n = stat_mem_pkt_yumi_i + ? e_ready + : state_r; + + end // e_stat_clear + + // Writeback + // send writeback or null writeback header response, based on dirty bit from stat mem read + // three commands enter this state: wb, st_wb, and st_tr_wb + e_wb: begin + + fsm_resp_header_lo.addr = fsm_cmd_header_r.addr; + fsm_resp_header_lo.msg_type.resp = dirty_stat_r.dirty[fsm_cmd_header_r.payload.way_id[0+:lg_assoc_lp]] + ? e_bedrock_resp_wb + : e_bedrock_resp_null_wb; + fsm_resp_header_lo.payload.src_id = lce_id_i; + fsm_resp_header_lo.payload.dst_id = fsm_cmd_header_r.payload.src_id; + fsm_resp_header_lo.size = bp_bedrock_msg_size_e'(dirty_stat_r.dirty[fsm_cmd_header_r.payload.way_id[0+:lg_assoc_lp]] + ? cmd_block_size_lp + : e_bedrock_msg_size_1); + dirty_data_select = fsm_resp_addr_lo[fill_offset_width_lp+:fill_cnt_width_lp]; + fsm_resp_data_lo = dirty_data_selected; + fsm_resp_v_lo = fsm_resp_ready_then_li; + + state_n = (fsm_resp_v_lo & fsm_resp_last_lo) + ? dirty_stat_r.dirty[fsm_cmd_header_r.payload.way_id[0+:lg_assoc_lp]] + ? e_stat_clear + : e_ready + : state_r; + + end // e_wb + + // Send Coherence Ack message and raise request complete for one cycle + e_coh_ack: begin + fsm_resp_header_lo.addr = fsm_cmd_header_r.addr; + fsm_resp_header_lo.msg_type.resp = e_bedrock_resp_coh_ack; + fsm_resp_header_lo.payload.src_id = lce_id_i; + fsm_resp_header_lo.payload.dst_id = fsm_cmd_header_r.payload.src_id; + fsm_resp_v_lo = fsm_resp_ready_then_li; + + // cache request is complete when coherence ack sends + cache_req_last_o = fsm_resp_v_lo & fsm_resp_last_lo; + cache_req_done_o = fsm_resp_v_lo & fsm_resp_last_lo; + credit_return_o = cache_req_done_o; + + state_n = credit_return_o ? e_ready : state_r; + + end // e_coh_ack + + // we should never get in this state, but if we do, return to reset + default: begin + state_n = e_reset; + end + endcase // state + end + + // synopsys sync_set_reset "reset_i" + always_ff @ (posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_lce_cmd) diff --git a/designs/black-parrot/src/bp/bp_lce_req.sv b/designs/black-parrot/src/bp/bp_lce_req.sv new file mode 100644 index 0000000..2b0ee01 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_lce_req.sv @@ -0,0 +1,327 @@ +/** + * Name: + * bp_lce_req.sv + * + * Description: + * LCE request handler. + * + * Issues LCE requests when cache misses arrive. Supports cached, uncached, and uncached atomic + * requests. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_lce_req + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + // parameters specific to this LCE (these match the cache managed by the LCE) + , parameter `BSG_INV_PARAM(assoc_p) + , parameter `BSG_INV_PARAM(sets_p) + , parameter `BSG_INV_PARAM(block_width_p) + , parameter `BSG_INV_PARAM(fill_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(tag_width_p) + , parameter `BSG_INV_PARAM(id_width_p) + + // LCE-cache interface timeout in cycles + , parameter timeout_max_limit_p=4 + // maximum number of outstanding transactions + , parameter credits_p = coh_noc_max_credits_p + // issue non-exclusive read requests + , parameter non_excl_reads_p = 0 + + // byte offset bits required per bedrock data channel beat + , localparam bedrock_byte_offset_lp = `BSG_SAFE_CLOG2(fill_width_p/8) + , localparam bit [paddr_width_p-1:0] req_addr_mask = {paddr_width_p{1'b1}} << bedrock_byte_offset_lp + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + `declare_bp_cache_engine_generic_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p, cache) + ) + ( + input clk_i + , input reset_i + + // LCE Configuration + , input [did_width_p-1:0] did_i + , input [lce_id_width_p-1:0] lce_id_i + , input bp_lce_mode_e lce_mode_i + , input cache_init_done_i + , input sync_done_i + + // LCE Req is not able to accept requests + , output logic busy_o + + // Cache-LCE Interface + // ready / valid handshake + // metadata arrives in the same cycle as req, or any cycle after, but before the next request + // can arrive, as indicated by the metadata_v_i signal + , input [cache_req_width_lp-1:0] cache_req_i + , input cache_req_v_i + , output logic cache_req_yumi_o + , input [cache_req_metadata_width_lp-1:0] cache_req_metadata_i + , input cache_req_metadata_v_i + + // LCE-Cache Interface + , output logic cache_req_credits_full_o + , output logic cache_req_credits_empty_o + + // LCE Cmd - LCE Req Interface + // request complete signal from LCE Cmd module - Cached Load/Store and Uncached Load + // this signal is raised exactly once, for a single cycle, per request completing, and it + // can be raised at any time after the LCE request sends out + , input credit_return_i + , input cache_req_done_i + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , output logic [lce_req_header_width_lp-1:0] lce_req_header_o + , output logic [bedrock_fill_width_p-1:0] lce_req_data_o + , output logic lce_req_v_o + , input lce_req_ready_and_i + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_cache_engine_generic_if(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p, cache); + `bp_cast_o(bp_bedrock_lce_req_header_s, lce_req_header); + `bp_cast_i(bp_cache_req_s, cache_req); + `bp_cast_i(bp_cache_req_metadata_s, cache_req_metadata); + + enum logic [2:0] {e_reset, e_ready, e_request, e_send, e_backoff} state_n, state_r; + wire is_reset = (state_r == e_reset); + wire is_ready = (state_r == e_ready); + wire is_request = (state_r == e_request); + wire is_send = (state_r == e_send); + wire is_backoff = (state_r == e_backoff); + + logic cache_req_ready_lo; + bp_cache_req_s cache_req_r; + logic cache_req_v_r, cache_req_done; + bsg_two_fifo + #(.width_p($bits(bp_cache_req_s)), .ready_THEN_valid_p(1)) + cache_req_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(cache_req_cast_i) + ,.v_i(cache_req_yumi_o) + ,.ready_param_o(cache_req_ready_lo) + + ,.data_o(cache_req_r) + ,.v_o(cache_req_v_r) + ,.yumi_i(cache_req_done) + ); + + bp_cache_req_metadata_s cache_req_metadata, cache_req_metadata_r; + logic cache_req_metadata_v_r; + bsg_two_fifo + #(.width_p($bits(bp_cache_req_metadata_s)), .ready_THEN_valid_p(1)) + cache_req_metadata_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(cache_req_metadata_cast_i) + ,.v_i(cache_req_metadata_v_i & (cache_req_metadata_v_r | ~cache_req_done)) + ,.ready_param_o(/* Follows cache req fifo */) + + ,.data_o(cache_req_metadata_r) + ,.v_o(cache_req_metadata_v_r) + ,.yumi_i(cache_req_metadata_v_r & cache_req_done) + ); + assign cache_req_metadata = cache_req_metadata_v_r ? cache_req_metadata_r : cache_req_metadata_cast_i; + wire cache_req_metadata_v = cache_req_metadata_v_i | cache_req_metadata_v_r; + + wire miss_load_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_miss_load}; + wire miss_store_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_miss_store}; + wire miss_v_li = cache_req_v_i & miss_load_v_li | miss_store_v_li; + wire bclean_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_cache_bclean}; + wire clean_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_cache_clean}; + wire uc_load_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_uc_load}; + wire uc_amo_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_uc_amo}; + wire uc_store_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_uc_store}; + wire blocking_v_li = miss_load_v_li | miss_store_v_li | uc_load_v_li | uc_amo_v_li; + wire nonblocking_v_li = uc_store_v_li; + + bp_bedrock_lce_req_header_s fsm_req_header_lo; + logic [paddr_width_p-1:0] fsm_req_addr_lo; + logic [fill_width_p-1:0] fsm_req_data_lo; + logic fsm_req_v_lo, fsm_req_ready_then_li; + logic fsm_req_new_lo, fsm_req_critical_lo, fsm_req_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(fill_width_p) + ,.payload_width_p(lce_req_payload_width_lp) + ,.msg_stream_mask_p(lce_req_stream_mask_gp) + ,.fsm_stream_mask_p(lce_req_stream_mask_gp) + ) + lce_req_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(lce_req_header_cast_o) + ,.msg_data_o(lce_req_data_o) + ,.msg_v_o(lce_req_v_o) + ,.msg_ready_and_i(lce_req_ready_and_i) + + ,.fsm_header_i(fsm_req_header_lo) + ,.fsm_addr_o(fsm_req_addr_lo) + ,.fsm_data_i(fsm_req_data_lo) + ,.fsm_v_i(fsm_req_v_lo) + ,.fsm_ready_then_o(fsm_req_ready_then_li) + ,.fsm_new_o(fsm_req_new_lo) + ,.fsm_critical_o(fsm_req_critical_lo) + ,.fsm_last_o(fsm_req_last_lo) + ); + + wire miss_load_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_miss_load}; + wire miss_store_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_miss_store}; + wire miss_v_r = miss_load_v_r | miss_store_v_r; + wire bflush_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_cache_bclean, e_cache_binval, e_cache_bflush}; + wire clean_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_cache_clean}; + wire uc_load_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_uc_load}; + wire uc_amo_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_uc_amo}; + wire uc_store_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_uc_store}; + wire blocking_v_r = miss_load_v_r | miss_store_v_r | uc_load_v_r | uc_amo_v_r; + wire nonblocking_v_r = uc_store_v_r; + + // Outstanding request credit counter + // one credit used per LCE request sent + logic [`BSG_WIDTH(credits_p)-1:0] credit_count_lo; + wire credit_v_li = fsm_req_v_lo & fsm_req_new_lo; + wire credit_ready_then_li = fsm_req_ready_then_li; + wire credit_returned_li = credit_return_i; + bsg_flow_counter + #(.els_p(credits_p), .ready_THEN_valid_p(1)) + req_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_i(credit_v_li) + ,.ready_param_i(credit_ready_then_li) + ,.yumi_i(credit_returned_li) + ,.count_o(credit_count_lo) + ); + assign cache_req_credits_full_o = cache_req_v_r && (credit_count_lo == credits_p); + assign cache_req_credits_empty_o = ~cache_req_v_r && (credit_count_lo == '0); + + // Request Address to CCE + logic [cce_id_width_p-1:0] req_cce_id_lo; + bp_me_addr_to_cce_id + #(.bp_params_p(bp_params_p)) + req_map + (.paddr_i(cache_req_r.addr) + ,.cce_id_o(req_cce_id_lo) + ); + + // LCE should suppress messages if in reset or we are not synchronized with the CCE + // busy being lowered does not guarantee that this module will accept a valid cache request + // packet (refer to cache_req_yumi_o below). + assign busy_o = ~sync_done_i && (lce_mode_i == e_lce_mode_normal); + + // atomic request subop determination + bp_bedrock_wr_subop_e req_subop; + always_comb + unique case (cache_req_r.subop) + e_req_amolr : req_subop = e_bedrock_amolr; + e_req_amosc : req_subop = e_bedrock_amosc; + e_req_amoswap: req_subop = e_bedrock_amoswap; + e_req_amoadd : req_subop = e_bedrock_amoadd; + e_req_amoxor : req_subop = e_bedrock_amoxor; + e_req_amoand : req_subop = e_bedrock_amoand; + e_req_amoor : req_subop = e_bedrock_amoor; + e_req_amomin : req_subop = e_bedrock_amomin; + e_req_amomax : req_subop = e_bedrock_amomax; + e_req_amominu: req_subop = e_bedrock_amominu; + e_req_amomaxu: req_subop = e_bedrock_amomaxu; + default : req_subop = e_bedrock_store; + endcase + + always_comb + begin + // Request message defaults + fsm_req_header_lo = '0; + fsm_req_header_lo.addr = cache_req_r.addr; + fsm_req_header_lo.size = bp_bedrock_msg_size_e'(cache_req_r.size); + fsm_req_header_lo.payload.dst_id = req_cce_id_lo; + fsm_req_header_lo.payload.src_id = lce_id_i; + fsm_req_header_lo.payload.src_did = did_i; + fsm_req_header_lo.payload.lru_way_id = lce_assoc_width_p'(cache_req_metadata.hit_or_repl_way); + fsm_req_header_lo.payload.non_exclusive = + (miss_load_v_r && (non_excl_reads_p == 1)) ? e_bedrock_req_non_excl : e_bedrock_req_excl; + fsm_req_header_lo.subop = bflush_v_r ? e_bedrock_amoor : req_subop; + fsm_req_data_lo = cache_req_r.data; + + // Send request header when able + // requires valid cache request and possibly valid metadata (cached requests only) + unique case (cache_req_r.msg_type) + e_cache_bflush: fsm_req_header_lo.msg_type.req = e_bedrock_req_uc_wr; + e_uc_store : fsm_req_header_lo.msg_type.req = e_bedrock_req_uc_wr; + e_uc_load : fsm_req_header_lo.msg_type.req = e_bedrock_req_uc_rd; + e_uc_amo : fsm_req_header_lo.msg_type.req = e_bedrock_req_uc_amo; + e_miss_load : fsm_req_header_lo.msg_type.req = e_bedrock_req_rd_miss; + e_miss_store : fsm_req_header_lo.msg_type.req = e_bedrock_req_wr_miss; + default: begin end + endcase + end + + always_comb + begin + cache_req_yumi_o = '0; + fsm_req_v_lo = '0; + cache_req_done = '0; + + case (state_r) + e_ready: + begin + cache_req_yumi_o = cache_req_v_i & cache_req_ready_lo & (~cache_req_v_r | nonblocking_v_li); + + state_n = cache_req_yumi_o + ? blocking_v_li + ? e_send + : e_ready + : cache_req_v_i ? e_backoff : state_r; + end + e_send: + begin + fsm_req_v_lo = fsm_req_ready_then_li & ~cache_req_credits_full_o; + + state_n = (fsm_req_v_lo & fsm_req_last_lo) ? e_request : state_r; + end + e_request: + begin + cache_req_done = cache_req_done_i; + + state_n = cache_req_done ? e_ready : state_r; + end + e_backoff: + begin + state_n = fsm_req_ready_then_li ? e_ready : state_r; + end + // e_reset: + default : state_n = cache_init_done_i ? e_ready : state_r; + endcase + + // Fire off a non-blocking request opportunistically if we have one + // Could eke out some performance by changing ~fsm_req_v_lo to blocking_req_v_lo + //if (nonblocking_v_r & ~fsm_req_v_lo) + if (is_ready & nonblocking_v_r) + begin + fsm_req_v_lo = fsm_req_ready_then_li & ~cache_req_credits_full_o; + + cache_req_done = fsm_req_v_lo & fsm_req_last_lo; + end + end + + // synopsys sync_set_reset "reset_i" + always_ff @ (posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_lce_req) + diff --git a/designs/black-parrot/src/bp/bp_me_addr_to_cce_id.sv b/designs/black-parrot/src/bp/bp_me_addr_to_cce_id.sv new file mode 100644 index 0000000..eca1a08 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_addr_to_cce_id.sv @@ -0,0 +1,83 @@ +/** + * + * Name: + * bp_me_addr_to_cce_id.sv + * + * Description: + * Computes ID of CCE that is responsible for managing a physical address. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_addr_to_cce_id + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input [paddr_width_p-1:0] paddr_i + + , output logic [cce_id_width_p-1:0] cce_id_o + ); + + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + + bp_global_addr_s global_addr_li; + bp_local_addr_s local_addr_li; + + assign global_addr_li = paddr_i; + assign local_addr_li = paddr_i; + + // CCE: CC -> MC -> CAC -> SAC -> IOC + localparam max_cc_cce_lp = num_core_p; + localparam max_mc_cce_lp = max_cc_cce_lp + num_l2e_p; + localparam max_cac_cce_lp = max_mc_cce_lp + num_cacc_p; + localparam max_sac_cce_lp = max_cac_cce_lp + num_sacc_p; + localparam max_ioc_cce_lp = max_sac_cce_lp + num_io_p; + + wire external_io_v_li = (global_addr_li.hio > 2'd1); + wire local_addr_v_li = (paddr_i < dram_base_addr_gp); + wire dram_addr_v_li = (paddr_i >= dram_base_addr_gp) && ~|paddr_i[paddr_width_p-1:daddr_width_p]; + + localparam block_offset_lp = `BSG_SAFE_CLOG2(bedrock_block_width_p/8); + localparam lg_num_cce_lp = `BSG_SAFE_CLOG2(num_cce_p); + + // convert miss address (excluding block offset bits) into CCE ID + // For now, assume all CCE's have ID [0,num_core_p-1] and addresses are striped + // at the cache block granularity + logic [lce_sets_width_p-1:0] hash_addr_li; + logic [lg_num_cce_lp-1:0] cce_dst_id_lo; + assign hash_addr_li = {<< {paddr_i[block_offset_lp+:lce_sets_width_p]}}; + bsg_hash_bank + #(.banks_p(num_cce_p) // number of CCE's to spread way groups over + ,.width_p(lce_sets_width_p) // width of address input + ) + addr_to_cce_id + (.i(hash_addr_li) + ,.bank_o(cce_dst_id_lo) + ,.index_o() + ); + + always_comb + begin + cce_id_o = '0; + if (external_io_v_li || (local_addr_v_li && (local_addr_li.dev inside {host_dev_gp}))) + // Stripe by 4kiB page, start at io CCE id + cce_id_o = (num_io_p > 1) + ? max_sac_cce_lp + paddr_i[page_offset_width_gp+: (num_io_p > 1 ? `BSG_SAFE_CLOG2(num_io_p) : 1)] + : max_sac_cce_lp; + else if (local_addr_v_li) + // Split uncached I/O region by max 128 cores + cce_id_o = local_addr_li.tile; + else if (dram_addr_v_li) + // Stripe by cache line + cce_id_o[0+:lg_num_cce_lp] = cce_dst_id_lo; + else + cce_id_o = (num_sacc_p > 1) + ? max_cac_cce_lp + paddr_i[paddr_width_p-hio_width_p-1-: (num_sacc_p > 1 ? `BSG_SAFE_CLOG2(num_sacc_p) : 1)] + : max_cac_cce_lp; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_bedrock_register.sv b/designs/black-parrot/src/bp/bp_me_bedrock_register.sv new file mode 100644 index 0000000..d9111ed --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_bedrock_register.sv @@ -0,0 +1,155 @@ +/** + * + * Name: + * bp_me_bedrock_register.sv + * + * Description: + * This module is used to interface a BP Stream interface to a general-purpose + * register read/write interface. The data is stored externally so that + * control/status registers can be controlled by this interface while + * retaining special semantics. Registers are assumed to be synchronous + * read/write which is compatible (although suboptimal) for asynchronous + * registers. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_bedrock_register + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + // The width of the registers. Currently, must all be the same. + , parameter reg_data_width_p = dword_width_gp + // The address width of the registers. For addresses less than paddr_width_p, + // the upper bits of the paddr are ignored for matching purposes + , parameter reg_addr_width_p = paddr_width_p + // The number of registers to control + , parameter els_p = 1 + + // We would like to use unpacked here, but Verilator 4.202 does not support it + // Unsupported tristate construct: INITITEM + //// An unpacked array of integer register base addresses + //// e.g. localparam integer base_addr_lp [1:0] = '{0xf00bad, 0x00cafe} + //// Can also accept pattern matches such as 0x8??? + //, parameter integer base_addr_p [els_p-1:0] = '{0} + , parameter [els_p-1:0][reg_addr_width_p-1:0] base_addr_p = '0 + + , localparam lg_reg_data_width_lp = `BSG_WIDTH(`BSG_SAFE_CLOG2(reg_data_width_p/8)) + ) + (input clk_i + , input reset_i + + // Network-side BP-Stream interface + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + + // Synchronous register read/write interface. + // Actually 1rw, but expose both ports to prevent unnecessary and gates + // Assume latch last read behavior at registers, and do not have + // unnecessary read/writes. This could be parameterizable, but requires + // a read register in this module to do and maintain helpfulness + , output logic [els_p-1:0] r_v_o + , output logic [els_p-1:0] w_v_o + , output logic [reg_addr_width_p-1:0] addr_o + , output logic [lg_reg_data_width_lp-1:0] size_o + , output logic [reg_data_width_p-1:0] data_o + , input [els_p-1:0][reg_data_width_p-1:0] data_i + ); + + if (dword_width_gp != 64) $error("BedRock interface data width must be 64-bits"); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_o(bp_bedrock_mem_rev_header_s, mem_rev_header); + + bp_bedrock_mem_fwd_header_s mem_fwd_header_li; + logic [bedrock_fill_width_p-1:0] mem_fwd_data_li; + logic mem_fwd_v_li, mem_fwd_yumi_li; + bsg_one_fifo + #(.width_p($bits(bp_bedrock_mem_fwd_header_s)+bedrock_fill_width_p)) + fwd_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i({mem_fwd_data_i, mem_fwd_header_cast_i}) + ,.v_i(mem_fwd_v_i) + ,.ready_and_o(mem_fwd_ready_and_o) + + ,.data_o({mem_fwd_data_li, mem_fwd_header_li}) + ,.v_o(mem_fwd_v_li) + ,.yumi_i(mem_fwd_yumi_li) + ); + + logic v_r; + wire wr_not_rd = mem_fwd_header_li.msg_type == e_bedrock_mem_wr; + wire rd_not_wr = mem_fwd_header_li.msg_type == e_bedrock_mem_rd; + wire v_n = mem_fwd_v_li & ~v_r; + logic [els_p-1:0] r_v_r; + bsg_dff_reset_set_clear + #(.width_p(1+els_p), .clear_over_set_p(1)) + v_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + // We also track reads which don't match to prevent deadlock + ,.set_i({v_n, r_v_o}) + ,.clear_i({(els_p+1){mem_fwd_yumi_li}}) + ,.data_o({v_r, r_v_r}) + ); + + logic [reg_data_width_p-1:0] rdata_lo; + bsg_mux_one_hot + #(.width_p(reg_data_width_p), .els_p(els_p)) + rmux_oh + (.data_i(data_i) + ,.sel_one_hot_i(r_v_r) + ,.data_o(rdata_lo) + ); + + for (genvar i = 0; i < els_p; i++) + begin : dec + wire addr_match = mem_fwd_v_li & (mem_fwd_header_li.addr[0+:reg_addr_width_p] inside {base_addr_p[i]}); + assign r_v_o[i] = ~v_r & addr_match & ~wr_not_rd; + assign w_v_o[i] = ~v_r & addr_match & wr_not_rd; + end + + assign addr_o = mem_fwd_header_li.addr[0+:reg_addr_width_p]; + assign size_o = mem_fwd_header_li.size; + assign data_o = mem_fwd_data_li; + + assign mem_rev_header_cast_o = mem_fwd_header_li; + assign mem_rev_v_o = v_r; + assign mem_fwd_yumi_li = mem_rev_ready_and_i & mem_rev_v_o; + + localparam sel_width_lp = `BSG_SAFE_CLOG2(dword_width_gp>>3); + localparam size_width_lp = `BSG_SAFE_CLOG2(sel_width_lp); + bsg_bus_pack + #(.in_width_p(dword_width_gp), .out_width_p(bedrock_fill_width_p)) + fwd_bus_pack + (.data_i(rdata_lo) + ,.sel_i('0) // We are aligned + ,.size_i(mem_rev_header_cast_o.size[0+:size_width_lp]) + ,.data_o(mem_rev_data_o) + ); + + // synopsys translate_off + always_ff @(negedge clk_i) + begin + assert(reset_i !== '0 || ~mem_fwd_v_li | (v_r | ~wr_not_rd | |w_v_o) | (v_r | ~rd_not_wr | |r_v_o)) + else $error("Command to non-existent register: %x", addr_o); + end + // synopsys translate_on + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_cache_controller.sv b/designs/black-parrot/src/bp/bp_me_cache_controller.sv new file mode 100644 index 0000000..f6d4646 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cache_controller.sv @@ -0,0 +1,486 @@ +/* + * Name: + * bp_me_cache_controller.sv + * + * Description: + * This module converts an arriving BedRock Stream message into a bsg_cache message, and + * converts bsg_cache responses to outgoing BedRock Stream messages. + * + * After reset lowers, this module initializes all of the connected cache's tags and valid bits + * by clearing them and making all lines invalid. + * + * The data width is l2_data_width_p on both the BedRock Stream and cache interfaces. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bsg_cache.svh" + +module bp_me_cache_controller + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_cache_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + // L2 organization and interface + , localparam cache_pkt_width_lp = `bsg_cache_pkt_width(daddr_width_p, l2_data_width_p) + ) + (input clk_i + , input reset_i + + // BedRock Stream interface + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + // cache-side + , output logic [l2_banks_p-1:0][cache_pkt_width_lp-1:0] cache_pkt_o + , output logic [l2_banks_p-1:0] cache_pkt_v_o + , input [l2_banks_p-1:0] cache_pkt_yumi_i + + , input [l2_banks_p-1:0][l2_data_width_p-1:0] cache_data_i + , input [l2_banks_p-1:0] cache_data_v_i + , output logic [l2_banks_p-1:0] cache_data_yumi_o + ); + + // L2 derived params + localparam l2_blocks_per_bank_lp = (l2_assoc_p*l2_sets_p); + localparam l2_blocks_lp = l2_banks_p * l2_blocks_per_bank_lp; + localparam lg_l2_banks_lp = `BSG_SAFE_CLOG2(l2_banks_p); + localparam lg_l2_sets_lp = `BSG_SAFE_CLOG2(l2_sets_p); + localparam lg_l2_assoc_lp = `BSG_SAFE_CLOG2(l2_assoc_p); + localparam lg_l2_blocks_per_bank_lp = `BSG_SAFE_CLOG2(l2_blocks_per_bank_lp); + localparam lg_l2_blocks_lp = `BSG_SAFE_CLOG2(l2_blocks_lp); + localparam l2_block_offset_width_lp = `BSG_SAFE_CLOG2(l2_block_width_p/8); + localparam data_bytes_lp = (l2_data_width_p/8); + localparam data_byte_offset_width_lp = `BSG_SAFE_CLOG2(data_bytes_lp); + + `declare_bsg_cache_pkt_s(daddr_width_p, l2_data_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + + bsg_cache_pkt_s cache_pkt; + assign cache_pkt_o = {l2_banks_p{cache_pkt}}; + + enum logic [2:0] {e_reset, e_clear, e_drain, e_ready, e_uc_flush} state_n, state_r; + wire is_reset = (state_r == e_reset); + wire is_flush = (state_r == e_uc_flush); + wire is_clear = (state_r == e_clear); + wire is_drain = (state_r == e_drain); + wire is_ready = (state_r == e_ready); + + bp_bedrock_mem_fwd_header_s fsm_fwd_header_li; + logic [l2_data_width_p-1:0] fsm_fwd_data_li; + logic fsm_fwd_v_li, fsm_fwd_yumi_lo; + logic [paddr_width_p-1:0] fsm_fwd_addr_li; + logic fsm_fwd_new_li, fsm_fwd_critical_li, fsm_fwd_last_li; + + bp_bedrock_mem_rev_header_s fsm_rev_header_lo; + logic [l2_data_width_p-1:0] fsm_rev_data_lo; + logic fsm_rev_v_lo, fsm_rev_ready_then_li; + logic [paddr_width_p-1:0] fsm_rev_addr_lo; + logic fsm_rev_new_lo, fsm_rev_critical_lo, fsm_rev_last_lo; + + // Enough to saturate l2 banks, may be overprovisioned + localparam cache_metadata_fifo_els_lp = 3*l2_banks_p; + localparam cache_metadata_fifo_width_lp = $bits(bp_bedrock_mem_rev_header_s)+lg_l2_banks_lp; + + // Hack because the bsg_cache does not have introspection + logic [l2_banks_p-1:0] op_v_lo, op_data_lo; + for (genvar i = 0; i < l2_banks_p; i++) + begin : tag + bsg_fifo_1r1w_small + #(.width_p(1), .ready_THEN_valid_p(1) ,.els_p(3)) + fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(is_ready) + ,.v_i(cache_pkt_yumi_i[i]) + ,.ready_param_o() + + ,.data_o(op_data_lo[i]) + ,.v_o(op_v_lo[i]) + ,.yumi_i(cache_data_yumi_o[i]) + ); + end + + logic [cache_metadata_fifo_width_lp-1:0] fsm_fwd_metadata_li, fsm_rev_metadata_lo; + bp_me_stream_pump + #(.bp_params_p(bp_params_p) + ,.in_data_width_p(l2_data_width_p) + ,.in_payload_width_p(mem_fwd_payload_width_lp) + ,.in_msg_stream_mask_p(mem_fwd_stream_mask_gp) + ,.in_fsm_stream_mask_p(mem_fwd_stream_mask_gp | mem_rev_stream_mask_gp) + ,.out_data_width_p(l2_data_width_p) + ,.out_payload_width_p(mem_rev_payload_width_lp) + ,.out_msg_stream_mask_p(mem_rev_stream_mask_gp) + ,.out_fsm_stream_mask_p(mem_fwd_stream_mask_gp | mem_rev_stream_mask_gp) + ,.metadata_fifo_width_p(cache_metadata_fifo_width_lp) + ,.metadata_fifo_els_p(cache_metadata_fifo_els_lp) + ) + stream_pump + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.in_msg_header_i(mem_fwd_header_i) + ,.in_msg_data_i(mem_fwd_data_i) + ,.in_msg_v_i(mem_fwd_v_i) + ,.in_msg_ready_and_o(mem_fwd_ready_and_o) + + ,.in_fsm_header_o(fsm_fwd_header_li) + ,.in_fsm_data_o(fsm_fwd_data_li) + ,.in_fsm_v_o(fsm_fwd_v_li) + ,.in_fsm_yumi_i(fsm_fwd_yumi_lo) + + ,.in_fsm_metadata_i(fsm_fwd_metadata_li) + ,.in_fsm_addr_o(fsm_fwd_addr_li) + ,.in_fsm_new_o(fsm_fwd_new_li) + ,.in_fsm_critical_o(fsm_fwd_critical_li) + ,.in_fsm_last_o(fsm_fwd_last_li) + + ,.out_msg_header_o(mem_rev_header_o) + ,.out_msg_data_o(mem_rev_data_o) + ,.out_msg_v_o(mem_rev_v_o) + ,.out_msg_ready_and_i(mem_rev_ready_and_i) + + ,.out_fsm_header_i(fsm_rev_header_lo) + ,.out_fsm_data_i(fsm_rev_data_lo) + ,.out_fsm_v_i(fsm_rev_v_lo) + ,.out_fsm_ready_then_o(fsm_rev_ready_then_li) + + ,.out_fsm_metadata_o(fsm_rev_metadata_lo) + ,.out_fsm_addr_o(fsm_rev_addr_lo) + ,.out_fsm_new_o(fsm_rev_new_lo) + ,.out_fsm_critical_o(fsm_rev_critical_lo) + ,.out_fsm_last_o(fsm_rev_last_lo) + ); + + bp_local_addr_s local_addr_li; + assign local_addr_li = fsm_fwd_addr_li; + localparam [paddr_width_p-1:0] l1c_l2c_base_lp = dram_base_addr_gp; + localparam [paddr_width_p-1:0] l1uc_l2c_base_lp = (1'b1 << caddr_width_p); + localparam [paddr_width_p-1:0] l1uc_l2uc_base_lp = (1'b1 << caddr_width_p) | dram_base_addr_gp; + wire is_uc_op = (local_addr_li >= l1uc_l2c_base_lp) && (local_addr_li < l1uc_l2uc_base_lp); + wire is_word_op = (fsm_fwd_header_li.size == e_bedrock_msg_size_4); + + logic [lg_l2_blocks_lp-1:0] set_cnt; + logic set_clear, set_up; + bsg_counter_clear_up + #(.max_val_p(l2_blocks_lp-1), .init_val_p(0)) + set_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(set_clear) + ,.up_i(set_up) + ,.count_o(set_cnt) + ); + wire set_done = (set_cnt == l2_blocks_lp-1); + wire [lg_l2_banks_lp-1:0] cnt_bank_lo = set_cnt / l2_blocks_per_bank_lp; + + // cache packet data and mask mux elements + // each mux has one element per power of 2 in [1, N] where N is log2(L2 data width bytes) + // e.g.: 64-bit data width = 8B = 2^3 -> 4 muxes for 1B, 2B, 4B, 8B + // e.g.: 128-bit data width = 16B = 2^4 -> 5 muxes for 1B, 2B, 4B, 8B, 16B + // e.g.: 256-bit data width = 32B = 2^5 -> 6 muxes for 1B, 2B, 4B, 8B, 16B, 32B + // e.g.: 512-bit data width = 64B = 2^6 -> 7 muxes for 1B, 2B, 4B, 8B, 16B, 32B, 64B + // e.g.: 1024-bit data width = 128B = 2^7 -> 8 muxes for 1B, 2B, 4B, 8B, 16B, 32B, 64B, 128B + localparam mux_els_lp = data_byte_offset_width_lp+1; + localparam lg_mux_els_lp = `BSG_SAFE_CLOG2(mux_els_lp); + logic [mux_els_lp-1:0][data_bytes_lp-1:0] cache_pkt_mask_mux_li; + for (genvar i = 0; i < mux_els_lp; i++) + begin : cache_pkt_sel + // width of slice, in bits + // smallest granularity is 1 byte = 8 bits + localparam slice_width_bytes_lp = (2**i); + localparam slice_width_lp = (slice_width_bytes_lp << 3); + // number of slice_width_lp parts that comprise in/out data + localparam num_slices_lp = (l2_data_width_p/slice_width_lp); + localparam lg_num_slices_lp = `BSG_SAFE_CLOG2(num_slices_lp); + + // Mask + if (i == mux_els_lp-1) + begin: max_size + assign cache_pkt_mask_mux_li[i] = {data_bytes_lp{1'b1}}; + end + else + begin: non_max_size + + // determine which slice being used based on the mem_fwd address + // i = 0, slices are 1B wide + // i = 1, slices are 2B wide + // i = 2, slices are 4B wide + // etc. + wire [lg_num_slices_lp-1:0] slice_index = fsm_fwd_addr_li[i+:lg_num_slices_lp]; + // one-hot decoded slice index - bit n is set when targeting slice n + wire [num_slices_lp-1:0] decoded_slice_index = (1'b1 << slice_index); + + // expand the one-hot decoded slice index into a bit-mask for the cache packet + bsg_expand_bitmask + #(.in_width_p(num_slices_lp) + ,.expand_p(slice_width_bytes_lp)) + mask_expand + (.i(decoded_slice_index) + ,.o(cache_pkt_mask_mux_li[i]) + ); + end + end + + // cache mask has one entry per byte in l2_data_width_p + logic [data_bytes_lp-1:0] cache_pkt_mask_lo; + wire [lg_mux_els_lp-1:0] cache_pkt_sel_li = (1'b1 << fsm_fwd_header_li.size) > data_bytes_lp + ? lg_mux_els_lp'(mux_els_lp-1) + : fsm_fwd_header_li.size[0+:lg_mux_els_lp]; + bsg_mux + #(.width_p(data_bytes_lp), .els_p(mux_els_lp)) + cache_pkt_mask_mux + (.data_i(cache_pkt_mask_mux_li) + ,.sel_i(cache_pkt_sel_li) + ,.data_o(cache_pkt_mask_lo) + ); + + // Swizzle address bits for L2 cache command + logic fwd_pkt_dram_lo; + logic [daddr_width_p-1:0] fwd_pkt_daddr_lo; + logic [l2_data_width_p-1:0] fwd_pkt_data_lo; + logic [lg_l2_banks_lp-1:0] fwd_pkt_bank_lo; + bp_me_dram_hash_encode + #(.bp_params_p(bp_params_p)) + bank_select + (.paddr_i(fsm_fwd_addr_li) + ,.data_i(fsm_fwd_data_li) + + ,.dram_o(fwd_pkt_dram_lo) + ,.daddr_o(fwd_pkt_daddr_lo) + ,.bank_o(fwd_pkt_bank_lo) + ,.data_o(fwd_pkt_data_lo) + ,.slice_o() + ); + + logic cache_pkt_v_lo; + wire [lg_l2_banks_lp-1:0] cache_fwd_bank_lo = is_clear ? cnt_bank_lo : fwd_pkt_bank_lo; + bsg_decode_with_v + #(.num_out_p(l2_banks_p)) + decode + (.i(cache_fwd_bank_lo) + ,.v_i(cache_pkt_v_lo) + ,.o(cache_pkt_v_o) + ); + wire cache_pkt_yumi_li = fsm_fwd_v_li & cache_pkt_yumi_i[cache_fwd_bank_lo]; + + logic [lg_l2_banks_lp-1:0] cache_rev_bank_lo; + assign fsm_fwd_metadata_li = {fwd_pkt_bank_lo, fsm_fwd_header_li}; + assign {cache_rev_bank_lo, fsm_rev_header_lo} = fsm_rev_metadata_lo; + + // mem_rev data selection + // For B/H/W/D ops, data returned from cache is at the LSB, but it may not for M ops + // on bsg_bus_pack: + // sel_i = which unit (byte) to start selection at from cache_data_i + // size_i = log2(size in bytes) of selection to make + // bus pack has log2(l2_data_width_p/8) = log2(l2 data width bytes) mux elements + // == data_byte_offset_width_lp + localparam bus_pack_size_width_lp = `BSG_WIDTH(data_byte_offset_width_lp); + + // size to use is set to max size if response is larger than data width (indicating a multi-beat + // message will be sent and therefore each data beat will be full and valid), + // otherwise extract size from memory response header + wire [bus_pack_size_width_lp-1:0] fsm_rev_size_li = + ((1'b1 << fsm_rev_header_lo.size) > data_bytes_lp) + ? data_byte_offset_width_lp + : fsm_rev_header_lo.size[0+:bus_pack_size_width_lp]; + + logic [l2_data_width_p-1:0] cache_data_li; + bsg_mux + #(.width_p(l2_data_width_p), .els_p(l2_banks_p)) + resp_bank_sel + (.data_i(cache_data_i) + ,.sel_i(cache_rev_bank_lo) + ,.data_o(cache_data_li) + ); + + bsg_bus_pack + #(.in_width_p(l2_data_width_p)) + mem_rev_data_bus_pack + (.data_i(cache_data_li) + ,.sel_i('0) // Data is always aligned + ,.size_i(fsm_rev_size_li) + ,.data_o(fsm_rev_data_lo) + ); + + // FSM + always_comb + begin + cache_pkt = '0; + cache_pkt_v_lo = '0; + cache_data_yumi_o = '0; + + fsm_fwd_yumi_lo = 1'b0; + + fsm_rev_v_lo = 1'b0; + + set_clear = 1'b0; + set_up = 1'b0; + + state_n = state_r; + + unique case (state_r) + e_reset: + begin + state_n = e_clear; + end + e_clear: + begin + cache_pkt_v_lo = 1'b1; + cache_pkt.opcode = TAGST; + cache_pkt.addr = set_cnt << l2_block_offset_width_lp; + cache_pkt.data = '0; + cache_pkt.mask = '0; + + set_up = ~set_done; + set_clear = set_done & |cache_pkt_yumi_i; + + cache_data_yumi_o = cache_data_v_i; + + state_n = set_clear ? e_drain : e_clear; + end + e_drain: + begin + cache_data_yumi_o = cache_data_v_i; + + state_n = (fsm_rev_ready_then_li | cache_data_v_i) ? e_drain : e_ready; + end + e_ready: + begin + if (!fwd_pkt_dram_lo) + unique casez (local_addr_li.addr) + // Tag ops + cache_tagfl_match_addr_gp : cache_pkt.opcode = TAGFL; + cache_taglv_match_addr_gp : cache_pkt.opcode = TAGLV; + cache_tagla_match_addr_gp : cache_pkt.opcode = TAGLA; + cache_tagst_match_addr_gp : cache_pkt.opcode = TAGST; + // Address ops + cache_afl_match_addr_gp : cache_pkt.opcode = AFL; + cache_aflinv_match_addr_gp : cache_pkt.opcode = AFLINV; + cache_ainv_match_addr_gp : cache_pkt.opcode = AINV; + cache_alock_match_addr_gp : cache_pkt.opcode = fwd_pkt_data_lo[0] ? ALOCK : AUNLOCK; + default : begin end + endcase + else + unique casez (fsm_fwd_header_li.msg_type) + e_bedrock_mem_rd: + case (fsm_fwd_header_li.size) + e_bedrock_msg_size_1: cache_pkt.opcode = LB; + e_bedrock_msg_size_2: cache_pkt.opcode = LH; + e_bedrock_msg_size_4: cache_pkt.opcode = LW; + e_bedrock_msg_size_8: cache_pkt.opcode = LD; + //e_bedrock_msg_size_16 + //,e_bedrock_msg_size_32 + //,e_bedrock_msg_size_64 + //,e_bedrock_msg_size_128 + default: cache_pkt.opcode = LM; + endcase + e_bedrock_mem_wr, e_bedrock_mem_amo: + case (fsm_fwd_header_li.size) + e_bedrock_msg_size_1: cache_pkt.opcode = SB; + e_bedrock_msg_size_2: cache_pkt.opcode = SH; + e_bedrock_msg_size_4, e_bedrock_msg_size_8: + case (fsm_fwd_header_li.subop) + e_bedrock_store : cache_pkt.opcode = is_word_op ? SW : SD; + e_bedrock_amoswap: cache_pkt.opcode = is_word_op ? AMOSWAP_W : AMOSWAP_D; + e_bedrock_amoadd : cache_pkt.opcode = is_word_op ? AMOADD_W : AMOADD_D; + e_bedrock_amoxor : cache_pkt.opcode = is_word_op ? AMOXOR_W : AMOXOR_D; + e_bedrock_amoand : cache_pkt.opcode = is_word_op ? AMOAND_W : AMOAND_D; + e_bedrock_amoor : cache_pkt.opcode = is_word_op ? AMOOR_W : AMOOR_D; + e_bedrock_amomin : cache_pkt.opcode = is_word_op ? AMOMIN_W : AMOMIN_D; + e_bedrock_amomax : cache_pkt.opcode = is_word_op ? AMOMAX_W : AMOMAX_D; + e_bedrock_amominu: cache_pkt.opcode = is_word_op ? AMOMINU_W : AMOMINU_D; + e_bedrock_amomaxu: cache_pkt.opcode = is_word_op ? AMOMAXU_W : AMOMAXU_D; + default : begin end + endcase + //e_bedrock_msg_size_16 + //,e_bedrock_msg_size_32 + //,e_bedrock_msg_size_64 + //,e_bedrock_msg_size_128 + default: cache_pkt.opcode = SM; + endcase + default: cache_pkt.opcode = LB; + endcase + + cache_pkt.addr = fwd_pkt_daddr_lo; + cache_pkt.data = fwd_pkt_data_lo; + cache_pkt.mask = cache_pkt_mask_lo; + + if (is_uc_op) + begin + cache_pkt_v_lo = fsm_fwd_v_li; + fsm_fwd_yumi_lo = cache_pkt_yumi_li & ~fsm_fwd_last_li; + + state_n = (fsm_fwd_v_li & fsm_fwd_last_li & cache_pkt_yumi_li) ? e_uc_flush : state_r; + end + else + begin + cache_pkt_v_lo = fsm_fwd_v_li; + fsm_fwd_yumi_lo = cache_pkt_yumi_li; + end + end + e_uc_flush: + begin + cache_pkt_v_lo = fsm_fwd_v_li; + cache_pkt.opcode = AFLINV; + cache_pkt.addr = fwd_pkt_daddr_lo; + cache_pkt.data = fwd_pkt_data_lo; + cache_pkt.mask = cache_pkt_mask_lo; + + fsm_fwd_yumi_lo = cache_pkt_yumi_li; + + state_n = fsm_fwd_yumi_lo ? e_drain : state_r; + end + default : begin end + endcase + + for (integer i = 0; i < l2_banks_p; i++) + if (op_v_lo[i] & op_data_lo[i] & (i == cache_rev_bank_lo)) + begin + fsm_rev_v_lo = fsm_rev_ready_then_li & cache_data_v_i[i]; + cache_data_yumi_o[i] = fsm_rev_v_lo; + end + else if (op_v_lo[i] & ~op_data_lo[i]) + begin + cache_data_yumi_o[i] = cache_data_v_i[i]; + end + end + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + + // synopsys translate_off + always_ff @(negedge clk_i) + begin + assert(reset_i !== '0 || ~fsm_fwd_v_li + || ~(fsm_fwd_header_li.msg_type inside {e_bedrock_mem_wr}) + || ~(fsm_fwd_header_li.subop inside {e_bedrock_amolr, e_bedrock_amosc}) + ) + else $error("LR/SC not supported in bsg_cache"); + end + // synopsys translate_on + + // requirement from BedRock Stream interface + if (!(`BSG_IS_POW2(l2_data_width_p) || l2_data_width_p < 64 || l2_data_width_p > 512)) + $error("L2 data width must be 64, 128, 256, or 512"); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_cache_slice.sv b/designs/black-parrot/src/bp/bp_me_cache_slice.sv new file mode 100644 index 0000000..bac1ff9 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cache_slice.sv @@ -0,0 +1,172 @@ +/** + * + * Name: + * bp_me_cache_slice.sv + * + * Description: + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bsg_cache.svh" +`include "bsg_noc_links.svh" + +module bp_me_cache_slice + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + import bsg_cache_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam dma_pkt_width_lp = `bsg_cache_dma_pkt_width(daddr_width_p, l2_block_size_in_words_p) + ) + (input clk_i + , input reset_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + // DRAM interface + , output logic [l2_banks_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_o + , output logic [l2_banks_p-1:0] dma_pkt_v_o + , input [l2_banks_p-1:0] dma_pkt_ready_and_i + + , input [l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_i + , input [l2_banks_p-1:0] dma_data_v_i + , output logic [l2_banks_p-1:0] dma_data_ready_and_o + + , output logic [l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_o + , output logic [l2_banks_p-1:0] dma_data_v_o + , input [l2_banks_p-1:0] dma_data_ready_and_i + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + `declare_bsg_cache_pkt_s(daddr_width_p, l2_data_width_p); + bsg_cache_pkt_s [l2_banks_p-1:0] cache_pkt_li; + logic [l2_banks_p-1:0] cache_pkt_v_li, cache_pkt_yumi_lo; + logic [l2_banks_p-1:0][l2_data_width_p-1:0] cache_data_lo; + logic [l2_banks_p-1:0] cache_data_v_lo, cache_data_yumi_li; + + // TODO: Buffering can be reduced by only saving headers per stream + bp_bedrock_mem_fwd_header_s mem_fwd_header_li; + logic [bedrock_fill_width_p-1:0] mem_fwd_data_li; + logic mem_fwd_v_li, mem_fwd_ready_and_lo; + bsg_fifo_1r1w_small + #(.width_p($bits(bp_bedrock_mem_fwd_header_s)+bedrock_fill_width_p) + // Buffer 1 full cache line to prevent writeback deadlock + ,.els_p(`BSG_MAX(2, bedrock_block_width_p/bedrock_fill_width_p)) + ) + fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i({mem_fwd_data_i, mem_fwd_header_i}) + ,.v_i(mem_fwd_v_i) + ,.ready_param_o(mem_fwd_ready_and_o) + + ,.data_o({mem_fwd_data_li, mem_fwd_header_li}) + ,.v_o(mem_fwd_v_li) + ,.yumi_i(mem_fwd_ready_and_lo & mem_fwd_v_li) + ); + + bp_me_cache_controller + #(.bp_params_p(bp_params_p)) + cache_controller + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.mem_fwd_header_i(mem_fwd_header_li) + ,.mem_fwd_data_i(mem_fwd_data_li) + ,.mem_fwd_v_i(mem_fwd_v_li) + ,.mem_fwd_ready_and_o(mem_fwd_ready_and_lo) + + ,.mem_rev_header_o(mem_rev_header_o) + ,.mem_rev_data_o(mem_rev_data_o) + ,.mem_rev_v_o(mem_rev_v_o) + ,.mem_rev_ready_and_i(mem_rev_ready_and_i) + + ,.cache_pkt_o(cache_pkt_li) + ,.cache_pkt_v_o(cache_pkt_v_li) + ,.cache_pkt_yumi_i(cache_pkt_yumi_lo) + + ,.cache_data_i(cache_data_lo) + ,.cache_data_v_i(cache_data_v_lo) + ,.cache_data_yumi_o(cache_data_yumi_li) + ); + + `declare_bsg_cache_dma_pkt_s(daddr_width_p, l2_block_size_in_words_p); + bsg_cache_dma_pkt_s [l2_banks_p-1:0] dma_pkt_lo, dma_pkt_cast_o; + for (genvar i = 0; i < l2_banks_p; i++) + begin : bank + bsg_cache + #(.addr_width_p(daddr_width_p) + ,.data_width_p(l2_data_width_p) + ,.dma_data_width_p(l2_fill_width_p) + ,.block_size_in_words_p(l2_block_size_in_words_p) + ,.sets_p(l2_sets_p) + ,.ways_p(l2_assoc_p) + ,.amo_support_p(((l2_features_p[e_cfg_amo_swap]) << e_cache_amo_swap) + | ((l2_features_p[e_cfg_amo_fetch_logic]) << e_cache_amo_xor) + | ((l2_features_p[e_cfg_amo_fetch_logic]) << e_cache_amo_and) + | ((l2_features_p[e_cfg_amo_fetch_logic]) << e_cache_amo_or) + | ((l2_features_p[e_cfg_amo_fetch_arithmetic]) << e_cache_amo_add) + | ((l2_features_p[e_cfg_amo_fetch_arithmetic]) << e_cache_amo_min) + | ((l2_features_p[e_cfg_amo_fetch_arithmetic]) << e_cache_amo_max) + | ((l2_features_p[e_cfg_amo_fetch_arithmetic]) << e_cache_amo_minu) + | ((l2_features_p[e_cfg_amo_fetch_arithmetic]) << e_cache_amo_maxu) + ) + ,.word_tracking_p(l2_features_p[e_cfg_word_tracking]) + ) + cache + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.cache_pkt_i(cache_pkt_li[i]) + ,.v_i(cache_pkt_v_li[i]) + ,.yumi_o(cache_pkt_yumi_lo[i]) + + ,.data_o(cache_data_lo[i]) + ,.v_o(cache_data_v_lo[i]) + ,.yumi_i(cache_data_yumi_li[i]) + + ,.dma_pkt_o(dma_pkt_lo[i]) + ,.dma_pkt_v_o(dma_pkt_v_o[i]) + ,.dma_pkt_yumi_i(dma_pkt_ready_and_i[i] & dma_pkt_v_o[i]) + + ,.dma_data_i(dma_data_i[i]) + ,.dma_data_v_i(dma_data_v_i[i]) + ,.dma_data_ready_and_o(dma_data_ready_and_o[i]) + + ,.dma_data_o(dma_data_o[i]) + ,.dma_data_v_o(dma_data_v_o[i]) + ,.dma_data_yumi_i(dma_data_ready_and_i[i] & dma_data_v_o[i]) + + ,.v_we_o() + ); + + bp_me_dram_hash_decode + #(.bp_params_p(bp_params_p)) + dma_addr_hash_decode + (.daddr_i(dma_pkt_lo[i].addr) + ,.daddr_o(dma_pkt_cast_o[i].addr) + ); + assign dma_pkt_cast_o[i].write_not_read = dma_pkt_lo[i].write_not_read; + assign dma_pkt_cast_o[i].mask = dma_pkt_lo[i].mask; + assign dma_pkt_o[i] = dma_pkt_cast_o[i]; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_cce_defines.svh b/designs/black-parrot/src/bp/bp_me_cce_defines.svh new file mode 100644 index 0000000..319db39 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cce_defines.svh @@ -0,0 +1,42 @@ +`ifndef BP_ME_CCE_DEFINES_SVH +`define BP_ME_CCE_DEFINES_SVH + + // Miss Status Handling Register Struct + // This struct tracks the information required to process an LCE request + `define declare_bp_cce_mshr_s(paddr_width_mp, lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + typedef struct packed \ + { \ + logic [lce_id_width_mp-1:0] owner_lce_id; \ + logic [`BSG_SAFE_CLOG2(lce_assoc_mp)-1:0] owner_way_id; \ + bp_coh_states_e owner_coh_state; \ + bp_cce_flags_s flags; \ + bp_coh_states_e lru_coh_state; \ + logic [paddr_width_mp-1:0] lru_paddr; \ + logic [`BSG_SAFE_CLOG2(lce_assoc_mp)-1:0] lru_way_id; \ + logic [`BSG_SAFE_CLOG2(lce_assoc_mp)-1:0] way_id; \ + logic [paddr_width_mp-1:0] paddr; \ + bp_coh_states_e next_coh_state; \ + logic [lce_id_width_mp-1:0] lce_id; \ + logic [did_width_mp-1:0] src_did; \ + bp_bedrock_msg_size_e msg_size; \ + bp_bedrock_wr_subop_e msg_subop; \ + bp_bedrock_msg_u msg_type; \ + } bp_cce_mshr_s + + `define declare_bp_cce_dir_entry_s(tag_width_mp) \ + typedef struct packed \ + { \ + logic [tag_width_mp-1:0] tag; \ + bp_coh_states_e state; \ + } dir_entry_s + + `define bp_cce_mshr_width(paddr_width_mp, lce_id_width_mp, cce_id_width_mp, did_width_mp, lce_assoc_mp) \ + ((2*lce_id_width_mp)+(3*`BSG_SAFE_CLOG2(lce_assoc_mp))+(2*paddr_width_mp) \ + +(3*$bits(bp_coh_states_e))+$bits(bp_cce_flags_s)+$bits(bp_bedrock_msg_size_e) \ + +$bits(bp_bedrock_msg_u)+$bits(bp_bedrock_wr_subop_e)+did_width_mp) + + `define bp_cce_dir_entry_width(tag_width_mp) \ + ($bits(bp_coh_states_e)+tag_width_mp) + +`endif + diff --git a/designs/black-parrot/src/bp/bp_me_cce_id_to_cord.sv b/designs/black-parrot/src/bp/bp_me_cce_id_to_cord.sv new file mode 100644 index 0000000..cb33801 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cce_id_to_cord.sv @@ -0,0 +1,72 @@ +/** + * + * Name: + * bp_me_cce_id_to_cord.sv + * + * Description: + * Computes network coordinates from CCE ID + * + */ + +// TODO: Configure to handle network configurations more flexibly +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_cce_id_to_cord + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input [cce_id_width_p-1:0] cce_id_i + , output logic [coh_noc_cord_width_p-1:0] cce_cord_o + , output logic [coh_noc_cid_width_p-1:0] cce_cid_o + ); + + + // CCE: CC -> MC -> CAC -> SAC -> IOC + localparam max_cc_cce_lp = num_core_p; + localparam max_mc_cce_lp = max_cc_cce_lp + num_l2e_p; + localparam max_cac_cce_lp = max_mc_cce_lp + num_cacc_p; + localparam max_sac_cce_lp = max_cac_cce_lp + num_sacc_p; + localparam max_ioc_cce_lp = max_sac_cce_lp + num_io_p; + + // TODO: We only support 1 additional column / row for non-core-complex accelerators + always_comb + // Core complex + if (cce_id_i < max_cc_cce_lp) + begin + cce_cord_o[0+:coh_noc_x_cord_width_p] = sac_x_dim_p + (cce_id_i % cc_x_dim_p); + cce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = ic_y_dim_p + (cce_id_i / cc_x_dim_p); + cce_cid_o = '0; + end + // Memory complex + else if (cce_id_i < max_mc_cce_lp) + begin + cce_cord_o[0+:coh_noc_x_cord_width_p] = sac_x_dim_p + (cce_id_i % cc_x_dim_p); + cce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = ic_y_dim_p + cc_y_dim_p; + cce_cid_o = '0; + end + // Coherent accelerator complex + else if (cce_id_i < max_cac_cce_lp) + begin + cce_cord_o[0+:coh_noc_x_cord_width_p] = sac_x_dim_p + cc_x_dim_p; + cce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = ic_y_dim_p + (cce_id_i % cc_y_dim_p); + cce_cid_o = '0; + end + // Streaming accelerator complex + else if (cce_id_i < max_sac_cce_lp) + begin + cce_cord_o[0+:coh_noc_x_cord_width_p] = '0; + cce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = ic_y_dim_p + (cce_id_i % cc_y_dim_p); + cce_cid_o = '0; + end + // IO complex + else + begin + cce_cord_o[0+:coh_noc_x_cord_width_p] = sac_x_dim_p + (cce_id_i % cc_x_dim_p); + cce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = '0; + cce_cid_o = '0; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_cce_inst_defines.svh b/designs/black-parrot/src/bp/bp_me_cce_inst_defines.svh new file mode 100644 index 0000000..68c663e --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cce_inst_defines.svh @@ -0,0 +1,44 @@ +`ifndef BP_ME_CCE_INST_DEFINES_SVH +`define BP_ME_CCE_INST_DEFINES_SVH + + /* + * Instruction width definitions + */ + + // Instructions are 32-bits wide with 2 bits of attached metadata + // cce_instr_width_gp should be equal to 34, and used when passing instruction+metadata + `define bp_cce_inst_data_width 32 + `define bp_cce_inst_metadata_width 2 + `define bp_cce_inst_op_width 3 + `define bp_cce_inst_minor_op_width 4 + + // Microcode RAM address width + // 9 bits allows up to 512 instructions + // this must be greater or equal to cce_pc_width_p in bp_common_aviary_pkg + `define bp_cce_inst_addr_width 9 + + // Immediate field widths + `define bp_cce_inst_imm1_width 1 + `define bp_cce_inst_imm2_width 2 + `define bp_cce_inst_imm4_width 4 + `define bp_cce_inst_imm8_width 8 + `define bp_cce_inst_imm16_width 16 + + /* + * General Purpose Registers + * + * Note: number of GPRs must be less than or equal to the number that can be + * represented in the GPR operand enum. Currently, the maximum is 16 GPRs, but only + * 8 are actually implemented and used. + */ + + `define bp_cce_inst_num_gpr 8 + // Note: this is hard-coded so it can be used in part-select / bit-slicing expressions + `define bp_cce_inst_gpr_sel_width 3 + //`BSG_SAFE_CLOG2(`bp_cce_inst_num_gpr) + `define bp_cce_inst_gpr_width 64 + + `define bp_cce_inst_opd_width 4 + +`endif + diff --git a/designs/black-parrot/src/bp/bp_me_cce_inst_pkgdef.svh b/designs/black-parrot/src/bp/bp_me_cce_inst_pkgdef.svh new file mode 100644 index 0000000..3c01342 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cce_inst_pkgdef.svh @@ -0,0 +1,876 @@ +/** + * + * Name: + * bp_cce_inst_pkgdef.svh + * + * Description: + * This file describes the CCE microcode instructions. Any changes made to this file must be + * reflected in the source code of the CCE microcode assembler, too. + * + * This file defines both the assembler generated and internally decoded formats of the microcode. + * + * Some software operations are supported via assembler transforms rather than being supported + * directly in hardware (e.g., ALU increment and decrement). + * + * Note: this file may rely on defines from bsg_defines.h in the BaseJump STL repo. + * Note: this file relies on bp_common_bedrock_if.svh + */ + +`ifndef BP_CCE_INST_PKGDEF_SVH +`define BP_CCE_INST_PKGDEF_SVH + + /* + * Major Op Codes + */ + localparam cce_instr_width_gp = 34; + + typedef enum logic [2:0] { + e_op_alu = 3'b000 // ALU operation + ,e_op_branch = 3'b001 // Branch (control flow) operation + ,e_op_reg_data = 3'b010 // Register data movement operation + //,e_op_mem = 3'b011 // Memory data operation (not implemented) + ,e_op_flag = 3'b100 + ,e_op_dir = 3'b101 + ,e_op_queue = 3'b110 + //,e_op_unused = 3'b111 + } bp_cce_inst_op_e; + + /* + * Minor Op Codes + */ + + // Minor ALU Op Codes + typedef enum logic [3:0] { + e_add_op = 4'b0000 // Add + ,e_sub_op = 4'b0001 // Subtract + ,e_lsh_op = 4'b0010 // Left Shift + ,e_rsh_op = 4'b0011 // Right Shift + ,e_and_op = 4'b0100 // Bit-wise AND + ,e_or_op = 4'b0101 // Bit-wise OR + ,e_xor_op = 4'b0110 // Bit-wise XOR + ,e_neg_op = 4'b0111 // Bit-wise negation (unary) + ,e_addi_op = 4'b1000 // Add immediate + //,e_nop_op = 4'b1000 // Null Operation (r0 = r0 + 0) + //,e_inc_op = 4'b1000 // Increment register by 1 + ,e_subi_op = 4'b1001 // Subtract immediate + //,e_dec_op = 4'b1001 // Decrement register by 1 + ,e_lshi_op = 4'b1010 // Left Shift immediate + ,e_rshi_op = 4'b1011 // Right Shift immediate + ,e_not_op = 4'b1111 // Logical Not + } bp_cce_inst_minor_alu_op_e; + + // Minor Branch Op Codes + typedef enum logic [3:0] { + e_beq_op = 4'b0000 // Branch if A == B + //,e_bi_op = 4'b0000 // Unconditional Branch, or Branch if A == A + ,e_bne_op = 4'b0001 // Branch if A != B + ,e_blt_op = 4'b0010 // Branch if A < B + //,e_bgt_op = 4'b0010 // Branch if A > B, or B < A + ,e_ble_op = 4'b0011 // Branch if A <= B + //,e_bge_op = 4'b0011 // Branch if A >= B, or B <= A + + ,e_bs_op = 4'b0100 // Branch if special == GPR + ,e_bss_op = 4'b0101 // Branch if special == special + + ,e_beqi_op = 4'b1000 // Branch if A == immediate + //,e_bz_op = 4'b1000 // Branch if A == 0 + ,e_bneqi_op = 4'b1001 // Branch if A != immediate + //,e_bnz_op = 4'b1001 // Branch if A != 0 + + ,e_bsi_op = 4'b1100 // Branch if special == immediate + } bp_cce_inst_minor_branch_op_e; + + // Minor Register Data Movement Op Codes + typedef enum logic [3:0] { + e_mov_op = 4'b0000 // Move GPR to GPR + ,e_movsg_op = 4'b0001 // Move Special Register to GPR + ,e_movgs_op = 4'b0010 // Move GPR to Special Register + //,e_ld_flags_op = 4'b0010 // MSHR.flags = GPR[0+:num_flags] + ,e_movfg_op = 4'b0011 // Move Flag to GPR[0] + ,e_movgf_op = 4'b0100 // Move GPR[0] to Flag + ,e_movpg_op = 4'b0101 // Move Param to GPR + ,e_movgp_op = 4'b0110 // Move GPR to Param + ,e_movi_op = 4'b1000 // Move Immediate to GPR + ,e_movis_op = 4'b1001 // Move Immediate to Special Register + //,e_ld_flags_i_op = 4'b1001 // MSHR.flags = imm[0+:num_flags] + //,e_clf_op = 4'b1001 // MSHR.flags = 0 + ,e_movip_op = 4'b1010 // Move Immediate to Param Register + ,e_clm_op = 4'b1111 // Clear MSHR register + } bp_cce_inst_minor_reg_data_op_e; + + // Minor Memory Op Codes + // Note: these are not implemented in the CCE by default. In software, the e_m* operations + // operate on global memory (i.e., physical/main memory in the system). There is a bit + // in the instruction encoding to indicate local (i.e., CCE scratchpad) or global memory + // operation. + typedef enum logic [3:0] { + e_ldb_op = 4'b0000 // Load byte from memory + ,e_ldh_op = 4'b0001 // Load half-word from memory + ,e_ldw_op = 4'b0010 // Load word from memory + ,e_ldd_op = 4'b0011 // Load double-word from memory + ,e_stb_op = 4'b0100 // Store byte to memory + ,e_sth_op = 4'b0101 // Store half-word to memory + ,e_stw_op = 4'b0110 // Store word to memory + ,e_std_op = 4'b0111 // Store double-word to memory + } bp_cce_inst_minor_mem_op_e; + + // Minor Flag Op Codes + typedef enum logic [3:0] { + e_sf_op = 4'b0000 // Move imm[0] = 1 to flag + //,e_sfz_op = 4'b0000 // Move imm[0] = 0 to flag + ,e_andf_op = 4'b0001 // Logical AND two flags to GPR + ,e_orf_op = 4'b0010 // Logical OR two flags to GPR + ,e_nandf_op = 4'b0011 // Logical NAND two flags to GPR + ,e_norf_op = 4'b0100 // Logical NOR two flags to GPR + ,e_notf_op = 4'b0101 // Logical not of flag + + ,e_bf_op = 4'b1000 // Branch if (MSHR.Flags & mask) == mask + ,e_bfz_op = 4'b1001 // Branch if (MSHR.Flags & mask) == 0 + ,e_bfnz_op = 4'b1010 // Branch if (MSHR.Flags & mask) != 0 + ,e_bfnot_op = 4'b1011 // Branch if (MSHR.Flags & mask) != mask + } bp_cce_inst_minor_flag_op_e; + + // Minor Directory Op Codes + typedef enum logic [3:0] { + e_rdp_op = 4'b0000 // Read Pending Bit + ,e_rdw_op = 4'b0001 // Read Directory Way Group + ,e_rde_op = 4'b0010 // Read Directory Entry + ,e_wdp_op = 4'b0100 // Write Pending Bit + ,e_clp_op = 4'b0101 // Clear Pending Bit + ,e_clr_op = 4'b0110 // Clear Directory Row + ,e_wde_op = 4'b0111 // Write Directory Entry + ,e_wds_op = 4'b1000 // Write Directory Entry State + ,e_gad_op = 4'b1001 // Generate Auxiliary Data + } bp_cce_inst_minor_dir_op_e; + + // Minor Queue Op Codes + // 1. poph does not dequeue data or memory, but captures the standard header fields into the MSHR, + // and also captures the message type into the specified GPR. + // 2. popd dequeues a single 64-bit data packet into a single GPR. The user must first have at + // at least done a poph to determine that data was available and so ucode can use size + // field in MSHR to determine how many packets to dequeue. + // 3. popq dequeues only the header. We assume that all data has been popped off + // either by popd commands, or by the message unit auto-forward mechanism, or by issuing + // a pushq command that consumes the data (e.g., an explicit pushq memCmd that consumes an + // lceResp containing writeback data). No state is written from the message to the CCE. + + typedef enum logic [3:0] { + e_wfq_op = 4'b0000 // Wait for Queue Valid + ,e_pushq_op = 4'b0001 // Push Queue + //,e_pushqc_op = 4'b0001 // Push Queue Custom Message + ,e_popq_op = 4'b0010 // Pop Queue - dequeue the header + ,e_poph_op = 4'b0011 // Pop Header From Queue - does not pop message + // TODO: popd not yet fully supported - will be supported after serdes changes + ,e_popd_op = 4'b0100 // Pop Data From Queue + ,e_specq_op = 4'b0101 // Write or read speculative access bits + ,e_inv_op = 4'b1000 // Send all Invalidations based on sharers vector + } bp_cce_inst_minor_queue_op_e; + + // Minor Op Code Union + typedef union packed { + bp_cce_inst_minor_alu_op_e alu_minor_op; + bp_cce_inst_minor_branch_op_e branch_minor_op; + bp_cce_inst_minor_reg_data_op_e reg_data_minor_op; + //bp_cce_inst_minor_mem_op_e mem_minor_op; + bp_cce_inst_minor_flag_op_e flag_minor_op; + bp_cce_inst_minor_dir_op_e dir_minor_op; + bp_cce_inst_minor_queue_op_e queue_minor_op; + // unused op + } bp_cce_inst_minor_op_u; + + + /* + * ALU Unit Operation + */ + typedef enum logic [3:0] { + e_alu_add = 4'b0000 // Add + ,e_alu_sub = 4'b0001 // Subtract + ,e_alu_lsh = 4'b0010 // Left Shift + ,e_alu_rsh = 4'b0011 // Right Shift + ,e_alu_and = 4'b0100 // Bit-wise AND + ,e_alu_or = 4'b0101 // Bit-wise OR + ,e_alu_xor = 4'b0110 // Bit-wise XOR + ,e_alu_neg = 4'b0111 // Bit-wise negation (unary) + ,e_alu_not = 4'b1000 // Logical Not (unary) + ,e_alu_nand = 4'b1001 // Logical Not of Bit-wise And + ,e_alu_nor = 4'b1010 // Logical Not of Bit-wise Or + } bp_cce_inst_alu_op_e; + + /* + * Branch Unit Operation + */ + typedef enum logic [1:0] { + e_branch_eq = 2'b00 // Branch if A == B + ,e_branch_neq = 2'b01 // Branch if A != B + ,e_branch_lt = 2'b10 // Branch if A < B + ,e_branch_le = 2'b11 // Branch if A <= B + } bp_cce_inst_branch_op_e; + + /* + * Speculative Bits Unit Operation + */ + typedef enum logic [3:0] { + e_spec_set = 4'b0000 // Set spec bit to 1 + ,e_spec_unset = 4'b0001 // Set spec bit to 0 + ,e_spec_squash = 4'b0010 // Set squash bit to 1, clear spec bit + ,e_spec_fwd_mod = 4'b0011 // Set fwd_mod bit to 1, clear spec bit, set state to state + ,e_spec_rd_spec = 4'b1000 // Read spec bit to sf + } bp_cce_inst_spec_op_e; + + /* + * Operand Selects + */ + + // GPR Operand Select + // GPR's can be source or destination + typedef enum logic [3:0] { + e_opd_r0 = 4'b0000 + ,e_opd_r1 = 4'b0001 + ,e_opd_r2 = 4'b0010 + ,e_opd_r3 = 4'b0011 + ,e_opd_r4 = 4'b0100 + ,e_opd_r5 = 4'b0101 + ,e_opd_r6 = 4'b0110 + ,e_opd_r7 = 4'b0111 + } bp_cce_inst_opd_gpr_e; + + // Flag Operand Select + // Flags can be source or destination + typedef enum logic [3:0] { + e_opd_rqf = 4'b0000 + ,e_opd_ucf = 4'b0001 + ,e_opd_nerf = 4'b0010 + ,e_opd_nwbf = 4'b0011 + ,e_opd_pf = 4'b0100 + ,e_opd_sf = 4'b0101 // also not used, when would it be? + // Basic flags from GAD + // cached dirty == cmf | cof + // cached maybe dirty == cmf | cof | cef + // cached owned (transfer) == cef | cmf | cof | cff + // cached == csf | cef | cmf | cof | cff + // not cached == not(any c*f flag) + // invalidate = rqf & csf + ,e_opd_csf = 4'b0110 + ,e_opd_cef = 4'b0111 + ,e_opd_cmf = 4'b1000 + ,e_opd_cof = 4'b1001 + ,e_opd_cff = 4'b1010 + // special flags from GAD + ,e_opd_rf = 4'b1011 // requesting LCE needs replacement + ,e_opd_uf = 4'b1100 // rqf & (rsf | rof | rff) + // atomics + ,e_opd_arf = 4'b1101 // atomic request + ,e_opd_anrf = 4'b1110 // atomic no return + // coherence PMA + ,e_opd_rcf = 4'b1111 // request to coherent memory + } bp_cce_inst_opd_flag_e; + + // Control Flag one hot encoding + typedef enum logic [15:0] { + e_flag_rqf = 16'b0000_0000_0000_0001 // request type flag + ,e_flag_ucf = 16'b0000_0000_0000_0010 // uncached request flag + ,e_flag_nerf = 16'b0000_0000_0000_0100 // non-exclusive request flag + ,e_flag_nwbf = 16'b0000_0000_0000_1000 // null writeback flag + ,e_flag_pf = 16'b0000_0000_0001_0000 // pending flag + ,e_flag_sf = 16'b0000_0000_0010_0000 // speculative flag + ,e_flag_csf = 16'b0000_0000_0100_0000 // cached S by other flag + ,e_flag_cef = 16'b0000_0000_1000_0000 // cached E by other flag + ,e_flag_cmf = 16'b0000_0001_0000_0000 // cached M by other flag + ,e_flag_cof = 16'b0000_0010_0000_0000 // cached O by other flag + ,e_flag_cff = 16'b0000_0100_0000_0000 // cached F by other flag + ,e_flag_rf = 16'b0000_1000_0000_0000 // replacement flag + ,e_flag_uf = 16'b0001_0000_0000_0000 // upgrade flag + ,e_flag_arf = 16'b0010_0000_0000_0000 // atomic request flag + ,e_flag_anrf = 16'b0100_0000_0000_0000 // atomic no return flag + ,e_flag_rcf = 16'b1000_0000_0000_0000 // request to coherent memory flag + } bp_cce_inst_flag_onehot_e; + + // Special Operand Select + typedef enum logic [3:0] { + // MSHR fields can be source or destination + e_opd_req_lce = 4'b0000 // MSHR.lce_id + ,e_opd_req_addr = 4'b0001 // MSHR.paddr + ,e_opd_req_way = 4'b0010 // MSHR.way_id + ,e_opd_lru_addr = 4'b0011 // MSHR.lru_paddr + ,e_opd_lru_way = 4'b0100 // MSHR.lru_way_id + ,e_opd_owner_lce = 4'b0101 // MSHR.owner_lce_id + ,e_opd_owner_way = 4'b0110 // MSHR.owner_way_id + ,e_opd_next_coh_state = 4'b0111 // MSHR.next_coh_state + ,e_opd_flags = 4'b1000 // MSHR.flags & imm[0+:num_flags] + ,e_opd_msg_size = 4'b1001 // MSHR.msg_size + ,e_opd_lru_coh_state = 4'b1010 // MSHR.lru_coh_state + ,e_opd_owner_coh_state = 4'b1011 // MSHR.owner_coh_state + + // sharers vectors require src_b to provide GPR rX containing index to use + // These can only be used as source a, not as source b or destinations + ,e_opd_sharers_hit = 4'b1101 // sharers_hits[rX] + ,e_opd_sharers_way = 4'b1110 // sharers_ways[rX] + ,e_opd_sharers_state = 4'b1111 // sharers_states[rX] + } bp_cce_inst_opd_special_e; + + // Params Operand Select + typedef enum logic [3:0] { + // These four parameters can only be sources + e_opd_cce_id = 4'b0000 // ID of this CCE + ,e_opd_num_lce = 4'b0001 // total number of LCE in system + ,e_opd_num_cce = 4'b0010 // total number of CCE in system + ,e_opd_num_wg = 4'b0011 // Number of WG managed by this CCE + // The following can be source or destination + ,e_opd_auto_fwd_msg = 4'b0100 // Message auto-forward control + ,e_opd_coh_state_default = 4'b0101 // Default for MSHR.next_coh_state + } bp_cce_inst_opd_params_e; + + // Queue valid signals and message types + // These can only be used as sources + typedef enum logic [3:0] { + e_opd_mem_rev_v = 4'b0000 + ,e_opd_lce_resp_v = 4'b0001 + ,e_opd_pending_v = 4'b0010 + ,e_opd_lce_req_v = 4'b0011 + ,e_opd_lce_resp_type = 4'b0100 + ,e_opd_mem_rev_type = 4'b0101 + ,e_opd_lce_resp_data = 4'b0110 + ,e_opd_mem_rev_data = 4'b0111 + ,e_opd_lce_req_data = 4'b1000 + } bp_cce_inst_opd_queue_e; + + /* + * Source Operands + */ + + // Source Union + typedef union packed { + bp_cce_inst_opd_gpr_e gpr; + bp_cce_inst_opd_flag_e flag; + bp_cce_inst_opd_special_e special; + bp_cce_inst_opd_params_e param; + bp_cce_inst_opd_queue_e q; + } bp_cce_inst_src_u; + + typedef enum logic [2:0] { + e_src_sel_gpr + ,e_src_sel_flag + ,e_src_sel_special + ,e_src_sel_param + ,e_src_sel_queue + ,e_src_sel_imm + ,e_src_sel_zero + } bp_cce_inst_src_sel_e; + + /* + * Destination Operands + */ + + // Destination Union + typedef union packed { + bp_cce_inst_opd_gpr_e gpr; + bp_cce_inst_opd_flag_e flag; + bp_cce_inst_opd_special_e special; + bp_cce_inst_opd_params_e param; + } bp_cce_inst_dst_u; + + typedef enum logic [1:0] { + e_dst_sel_gpr + ,e_dst_sel_flag + ,e_dst_sel_special + ,e_dst_sel_param + } bp_cce_inst_dst_sel_e; + + /* + * MUX Controls + * + * These are used to pick where an address, LCE ID, or way ID are sourced from for + * various instructions, including message and directory operations. + */ + + // Address + typedef enum logic [3:0] { + e_mux_sel_addr_r0 = 4'b0000 + ,e_mux_sel_addr_r1 = 4'b0001 + ,e_mux_sel_addr_r2 = 4'b0010 + ,e_mux_sel_addr_r3 = 4'b0011 + ,e_mux_sel_addr_r4 = 4'b0100 + ,e_mux_sel_addr_r5 = 4'b0101 + ,e_mux_sel_addr_r6 = 4'b0110 + ,e_mux_sel_addr_r7 = 4'b0111 + ,e_mux_sel_addr_mshr_req = 4'b1000 + ,e_mux_sel_addr_mshr_lru = 4'b1001 + ,e_mux_sel_addr_lce_req = 4'b1010 + ,e_mux_sel_addr_lce_resp = 4'b1011 + ,e_mux_sel_addr_mem_rev = 4'b1100 + ,e_mux_sel_addr_pending = 4'b1101 + ,e_mux_sel_addr_0 = 4'b1111 // constant 0 + } bp_cce_inst_mux_sel_addr_e; + + // LCE ID + typedef enum logic [3:0] { + e_mux_sel_lce_r0 = 4'b0000 + ,e_mux_sel_lce_r1 = 4'b0001 + ,e_mux_sel_lce_r2 = 4'b0010 + ,e_mux_sel_lce_r3 = 4'b0011 + ,e_mux_sel_lce_r4 = 4'b0100 + ,e_mux_sel_lce_r5 = 4'b0101 + ,e_mux_sel_lce_r6 = 4'b0110 + ,e_mux_sel_lce_r7 = 4'b0111 + ,e_mux_sel_lce_mshr_req = 4'b1000 + ,e_mux_sel_lce_mshr_owner = 4'b1001 + ,e_mux_sel_lce_lce_req = 4'b1010 + ,e_mux_sel_lce_lce_resp = 4'b1011 + ,e_mux_sel_lce_mem_rev = 4'b1100 + ,e_mux_sel_lce_pending = 4'b1101 + ,e_mux_sel_lce_0 = 4'b1111 // constant 0 + } bp_cce_inst_mux_sel_lce_e; + + // Way + typedef enum logic [3:0] { + e_mux_sel_way_r0 = 4'b0000 + ,e_mux_sel_way_r1 = 4'b0001 + ,e_mux_sel_way_r2 = 4'b0010 + ,e_mux_sel_way_r3 = 4'b0011 + ,e_mux_sel_way_r4 = 4'b0100 + ,e_mux_sel_way_r5 = 4'b0101 + ,e_mux_sel_way_r6 = 4'b0110 + ,e_mux_sel_way_r7 = 4'b0111 + ,e_mux_sel_way_mshr_req = 4'b1000 + ,e_mux_sel_way_mshr_owner = 4'b1001 + ,e_mux_sel_way_mshr_lru = 4'b1010 + ,e_mux_sel_way_sh_way = 4'b1011 // Sharer's vector ways, indexed by src_a + ,e_mux_sel_way_0 = 4'b1111 // constant 0 + } bp_cce_inst_mux_sel_way_e; + + // Coherence State + // source select for directory coherence state input + typedef enum logic [3:0] { + e_mux_sel_coh_r0 = 4'b0000 + ,e_mux_sel_coh_r1 = 4'b0001 + ,e_mux_sel_coh_r2 = 4'b0010 + ,e_mux_sel_coh_r3 = 4'b0011 + ,e_mux_sel_coh_r4 = 4'b0100 + ,e_mux_sel_coh_r5 = 4'b0101 + ,e_mux_sel_coh_r6 = 4'b0110 + ,e_mux_sel_coh_r7 = 4'b0111 + ,e_mux_sel_coh_next_coh_state = 4'b1000 + ,e_mux_sel_coh_lru_coh_state = 4'b1001 + ,e_mux_sel_sharer_state = 4'b1010 // Sharer's vector states, indexed by src_a + ,e_mux_sel_coh_owner_coh_state = 4'b1011 + ,e_mux_sel_coh_inst_imm = 4'b1111 + } bp_cce_inst_mux_sel_coh_state_e; + + /* + * Source and Destination Queue Selects and One-hot masks + */ + + // Source queue one hot + // order: {lceReq, lceResp, memResp, pending} + typedef enum logic [3:0] { + e_src_q_pending = 4'b0001 + ,e_src_q_mem_rev = 4'b0010 + ,e_src_q_lce_resp = 4'b0100 + ,e_src_q_lce_req = 4'b1000 + } bp_cce_inst_src_q_e; + + // Source queue select + typedef enum logic [1:0] { + e_src_q_sel_lce_req = 2'b00 + ,e_src_q_sel_mem_rev = 2'b01 + ,e_src_q_sel_pending = 2'b10 + ,e_src_q_sel_lce_resp = 2'b11 + } bp_cce_inst_src_q_sel_e; + + // Destination queue one hot + typedef enum logic [1:0] { + e_dst_q_lce_cmd = 2'b01 + ,e_dst_q_mem_fwd = 2'b10 + } bp_cce_inst_dst_q_e; + + // Destination queue select + typedef enum logic [1:0] { + e_dst_q_sel_lce_cmd = 2'b00 + ,e_dst_q_sel_mem_fwd = 2'b01 + } bp_cce_inst_dst_q_sel_e; + + /* + * Instruction Struct Definitions + * + * Each instruction is 32-bits wide. There are also two metadata bits attached to each + * instruction that indicate if the instruction is a branch and if the branch should + * be predicted taken or not. The metadata bits enable the pre-decoder to quickly decide + * what PC should be (speculatively) fetched next. + * + * Each instruction contains: + * op (3-bits) + * minor_op (4-bits) + * instruction type specific struct with padding (25-bits) + * + * Any changes made to this file must be reflected in the C version used by the assembler, and + * in the assembler itself. + * + */ + + `define bp_cce_inst_type_u_width \ + (`bp_cce_inst_data_width-`bp_cce_inst_op_width-`bp_cce_inst_minor_op_width) + + /* + * 2-Register Encoding + * + */ + + `define bp_cce_inst_rtype_pad (`bp_cce_inst_type_u_width-`bp_cce_inst_opd_width \ + -(2*`bp_cce_inst_opd_width)) + + typedef struct packed { + logic [`bp_cce_inst_rtype_pad-1:0] pad; + bp_cce_inst_src_u src_b; + bp_cce_inst_dst_u dst; + bp_cce_inst_src_u src_a; + } bp_cce_inst_rtype_s; + + /* + * Immediate Encoding + * + */ + + `define bp_cce_inst_itype_pad (`bp_cce_inst_type_u_width-`bp_cce_inst_opd_width \ + -`bp_cce_inst_opd_width-`bp_cce_inst_imm16_width) + + typedef struct packed { + logic [`bp_cce_inst_imm16_width-1:0] imm; + logic [`bp_cce_inst_itype_pad-1:0] pad; + bp_cce_inst_dst_u dst; + bp_cce_inst_src_u src_a; + } bp_cce_inst_itype_s; + + /* + * Memory Load Encoding (same as I-Type) + * rd = mem[ra+imm] + * + * Src and dst can only be GPR + */ + + // no padding needed + + typedef struct packed { + logic [`bp_cce_inst_imm16_width-1:0] imm; + logic global_mem; + bp_cce_inst_opd_gpr_e dst; + bp_cce_inst_opd_gpr_e src_a; + } bp_cce_inst_mltype_s; + + /* + * Memory Store Encoding (basically I-Type, but second source instead of destination) + * mem[ra+imm] = rb + * + * Src and dst can only be GPR + */ + + // no padding needed + + typedef struct packed { + logic [`bp_cce_inst_imm16_width-1:0] imm; + logic global_mem; + bp_cce_inst_opd_gpr_e src_b; + bp_cce_inst_opd_gpr_e src_a; + } bp_cce_inst_mstype_s; + + /* + * Branch Encoding + * + */ + + `define bp_cce_inst_btype_pad (`bp_cce_inst_type_u_width-`bp_cce_inst_imm4_width \ + -(2*`bp_cce_inst_opd_width)-`bp_cce_inst_addr_width) + + typedef struct packed { + logic [`bp_cce_inst_addr_width-1:0] target; + logic [`bp_cce_inst_btype_pad-1:0] pad; + bp_cce_inst_src_u src_b; + logic [`bp_cce_inst_imm4_width-1:0] pad4; + bp_cce_inst_src_u src_a; + } bp_cce_inst_btype_s; + + /* + * Branch-Immediate Encoding + * + */ + + `define bp_cce_inst_bitype_pad (`bp_cce_inst_type_u_width-`bp_cce_inst_opd_width \ + -`bp_cce_inst_imm8_width-`bp_cce_inst_addr_width) + + typedef struct packed { + logic [`bp_cce_inst_addr_width-1:0] target; + logic [`bp_cce_inst_bitype_pad-1:0] pad; + logic [`bp_cce_inst_imm8_width-1:0] imm; + bp_cce_inst_src_u src_a; + } bp_cce_inst_bitype_s; + + /* + * Branch-Flag Encoding + * + */ + + // no padding, target and immediate occupy exactly 25 bits + + typedef struct packed { + logic [`bp_cce_inst_addr_width-1:0] target; + logic [`bp_cce_inst_imm16_width-1:0] imm; + } bp_cce_inst_bftype_s; + + /* + * SpecQ Encoding (S-Type) + * + */ + + `define bp_cce_inst_stype_pad (`bp_cce_inst_type_u_width-$bits(bp_cce_inst_spec_op_e) \ + -$bits(bp_cce_inst_mux_sel_addr_e)-$bits(bp_coh_states_e)-`bp_cce_inst_opd_width) + + typedef struct packed { + logic [`bp_cce_inst_stype_pad-1:0] pad; + bp_coh_states_e state; + bp_cce_inst_mux_sel_addr_e addr_sel; + bp_cce_inst_opd_gpr_e dst; + bp_cce_inst_spec_op_e cmd; + } bp_cce_inst_stype_s; + + /* + * Directory Pending Encoding (DP-Type) + * + */ + + `define bp_cce_inst_dptype_pad (`bp_cce_inst_type_u_width-$bits(bp_cce_inst_mux_sel_addr_e) \ + -`bp_cce_inst_opd_width-1) + + typedef struct packed { + logic [`bp_cce_inst_dptype_pad-1:0] pad; + logic pending; + bp_cce_inst_opd_gpr_e dst; + bp_cce_inst_mux_sel_addr_e addr_sel; + } bp_cce_inst_dptype_s; + + /* + * Directory Read Encoding (DR-Type) + * + */ + + `define bp_cce_inst_drtype_pad (`bp_cce_inst_type_u_width-$bits(bp_cce_inst_mux_sel_addr_e) \ + -$bits(bp_cce_inst_mux_sel_way_e)-(2*$bits(bp_cce_inst_mux_sel_way_e)) \ + -(2*`bp_cce_inst_opd_width)) + + typedef struct packed { + logic [`bp_cce_inst_drtype_pad-1:0] pad; + bp_cce_inst_opd_gpr_e src_a; + bp_cce_inst_mux_sel_way_e lru_way_sel; + bp_cce_inst_mux_sel_way_e way_sel; + bp_cce_inst_mux_sel_lce_e lce_sel; + bp_cce_inst_opd_gpr_e dst; + bp_cce_inst_mux_sel_addr_e addr_sel; + } bp_cce_inst_drtype_s; + + /* + * Directory Write Encoding (DW-Type) + * + */ + + `define bp_cce_inst_dwtype_pad (`bp_cce_inst_type_u_width-$bits(bp_cce_inst_mux_sel_addr_e) \ + -$bits(bp_cce_inst_mux_sel_way_e)-$bits(bp_cce_inst_mux_sel_way_e) \ + -$bits(bp_cce_inst_mux_sel_coh_state_e)-$bits(bp_coh_states_e)-`bp_cce_inst_opd_width) + + typedef struct packed { + logic [`bp_cce_inst_dwtype_pad-1:0] pad; + bp_cce_inst_opd_gpr_e src_a; + bp_coh_states_e state; + bp_cce_inst_mux_sel_way_e way_sel; + bp_cce_inst_mux_sel_lce_e lce_sel; + bp_cce_inst_mux_sel_coh_state_e state_sel; + bp_cce_inst_mux_sel_addr_e addr_sel; + } bp_cce_inst_dwtype_s; + + /* + * Pop Queue Encoding + * + */ + + `define bp_cce_inst_popq_pad (`bp_cce_inst_type_u_width-$bits(bp_cce_inst_src_q_sel_e) \ + -`bp_cce_inst_opd_width-`bp_cce_inst_imm2_width-1) + + typedef struct packed { + logic write_pending; + logic [`bp_cce_inst_popq_pad-1:0] pad; + bp_cce_inst_opd_gpr_e dst; + logic [`bp_cce_inst_imm2_width-1:0] pad2; + bp_cce_inst_src_q_sel_e src_q; + } bp_cce_inst_popq_s; + + /* + * Push Queue Encoding + * + */ + + typedef struct packed { + logic write_pending; + union packed + { + bp_cce_inst_mux_sel_way_e way_sel; + /* msg_size field must be same or fewer bits than way_sel field + * currently, msg_size requires 3 bits to hold bp_mem_msg_size_e from + * bp_common_lce_cce_if.svh + */ + logic [$bits(bp_cce_inst_mux_sel_way_e)-1:0] msg_size; + } way_or_size; + bp_cce_inst_opd_queue_e src_a; + bp_cce_inst_mux_sel_lce_e lce_sel; + bp_cce_inst_mux_sel_addr_e addr_sel; + union packed + { + bp_bedrock_cmd_type_e lce_cmd; + bp_bedrock_fwd_type_e mem_fwd; + } cmd; + logic spec; + logic custom; + bp_cce_inst_dst_q_sel_e dst_q; + } bp_cce_inst_pushq_s; + + /* + * Instruction Type Struct Union + */ + + typedef union packed { + bp_cce_inst_rtype_s rtype; + bp_cce_inst_itype_s itype; + bp_cce_inst_mltype_s mltype; + bp_cce_inst_mstype_s mstype; + bp_cce_inst_btype_s btype; + bp_cce_inst_bitype_s bitype; + bp_cce_inst_bftype_s bftype; + bp_cce_inst_stype_s stype; + bp_cce_inst_dptype_s dptype; + bp_cce_inst_dwtype_s dwtype; + bp_cce_inst_drtype_s drtype; + bp_cce_inst_popq_s popq; + bp_cce_inst_pushq_s pushq; + } bp_cce_inst_type_u; + + typedef struct packed { + logic predict_taken; + logic branch; + bp_cce_inst_type_u type_u; + bp_cce_inst_minor_op_u minor_op_u; + bp_cce_inst_op_e op; + } bp_cce_inst_s; + + /* + * bp_cce_inst_decoded_s defines the decoded form of the CCE microcode instructions + * + */ + typedef struct packed { + + // instruction is valid + logic v; + + // branch and predict taken bits from raw instruction + logic branch; + logic predict_taken; + + // Basic operation information + bp_cce_inst_op_e op; + bp_cce_inst_minor_op_u minor_op_u; + + // Destination and Source signals with selects + bp_cce_inst_dst_u dst; + bp_cce_inst_dst_sel_e dst_sel; + bp_cce_inst_src_u src_a; + bp_cce_inst_src_sel_e src_a_sel; + bp_cce_inst_src_u src_b; + bp_cce_inst_src_sel_e src_b_sel; + + // Address, LCE, Way, and Coherence State Selects + // These are used by directory, pending bits, speculative bits, messages, etc. + // note: addr_bypass signal generated by src_sel depending on mux signal + // bypass will occur for GPR as source + bp_cce_inst_mux_sel_addr_e addr_sel; + bp_cce_inst_mux_sel_lce_e lce_sel; + bp_cce_inst_mux_sel_way_e way_sel; + bp_cce_inst_mux_sel_way_e lru_way_sel; + bp_cce_inst_mux_sel_coh_state_e coh_state_sel; + + // Immediate + logic [`bp_cce_inst_gpr_width-1:0] imm; + + // ALU Unit + bp_cce_inst_alu_op_e alu_op; + + // Branch Unit + bp_cce_inst_branch_op_e branch_op; + logic [`bp_cce_inst_addr_width-1:0] branch_target; + + // Directory + logic dir_r_v; + logic dir_w_v; + + // GAD Module + logic gad_v; + + // WFQ + logic wfq_v; + + // Pending Bits + logic pending_r_v; + logic pending_w_v; + logic pending_bit; + logic pending_clear; + + // Speculative Memory Access Bits + logic spec_r_v; + logic spec_w_v; + logic spec_v; + logic spec_squash_v; + logic spec_fwd_mod_v; + logic spec_state_v; + bp_cce_spec_s spec_bits; + + // Message Unit / Messages + logic poph; + logic popq; + logic popd; + logic pushq; + logic pushq_custom; + bp_bedrock_msg_size_e msg_size; + bp_cce_inst_dst_q_sel_e pushq_qsel; + bp_cce_inst_src_q_sel_e popq_qsel; + logic lce_req_yumi; + logic lce_resp_yumi; + logic mem_rev_yumi; + logic pending_yumi; + logic lce_cmd_v; + bp_bedrock_cmd_type_e lce_cmd; + logic mem_fwd_v; + bp_bedrock_fwd_type_e mem_fwd; + logic inv_cmd_v; + + // GPR write mask + logic [`bp_cce_inst_num_gpr-1:0] gpr_w_v; + + // MSHR write signals + logic mshr_clear; + logic lce_w_v; + logic addr_w_v; + logic way_w_v; + logic lru_addr_w_v; + logic lru_way_w_v; + logic owner_lce_w_v; + logic owner_way_w_v; + logic next_coh_state_w_v; + logic lru_coh_state_w_v; + logic owner_coh_state_w_v; + // Flag write mask - for instructions that write flags, e.g., GAD, poph, mov, sf + logic [$bits(bp_cce_inst_flag_onehot_e)-1:0] flag_w_v; + logic msg_size_w_v; + // Special/Param registers + logic coh_state_w_v; + logic auto_fwd_msg_w_v; + + // stall counter + logic clr_stall_cnt; + + } bp_cce_inst_decoded_s; + +`endif diff --git a/designs/black-parrot/src/bp/bp_me_cce_pkgdef.svh b/designs/black-parrot/src/bp/bp_me_cce_pkgdef.svh new file mode 100644 index 0000000..b1fd5c1 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cce_pkgdef.svh @@ -0,0 +1,49 @@ +/** + * + * Name: + * bp_me_cce_pkgdef.svh + * + * Description: + */ + +`ifndef BP_ME_CCE_PKGDEF_SVH +`define BP_ME_CCE_PKGDEF_SVH + + // Struct that defines speculative memory access tracking metadata + // This is used in the decoded instruction and the bp_cce_spec module + typedef struct packed + { + logic spec; + logic squash; + logic fwd_mod; + bp_coh_states_e state; + } bp_cce_spec_s; + + // Coherence Request Processing Flags + // TODO: reorder this struct - requires reording in CCE instruction define and ucode assembler + typedef struct packed { + // request to cacheable address + logic cacheable_address; + // atomics + logic atomic_no_return; + logic atomic; + // GAD flags + logic upgrade; + logic replacement; + logic cached_forward; + logic cached_owned; + logic cached_modified; + logic cached_exclusive; + logic cached_shared; + // misc flags + logic speculative; + logic pending; + logic null_writeback; + // request flags + logic non_exclusive; + logic uncached; + logic write_not_read; + } bp_cce_flags_s; + +`endif + diff --git a/designs/black-parrot/src/bp/bp_me_cfg_slice.sv b/designs/black-parrot/src/bp/bp_me_cfg_slice.sv new file mode 100644 index 0000000..b655e5c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cfg_slice.sv @@ -0,0 +1,167 @@ +/** + * + * Name: + * bp_me_cfg_slice.sv + * + * Description: + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_cfg_slice + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + , output logic [cfg_bus_width_lp-1:0] cfg_bus_o + , input [did_width_p-1:0] did_i + , input [did_width_p-1:0] host_did_i + , input [coh_noc_cord_width_p-1:0] cord_i + + // ucode programming interface, synchronous read, direct connection to RAM + , output logic cce_ucode_v_o + , output logic cce_ucode_w_o + , output logic [cce_pc_width_p-1:0] cce_ucode_addr_o + , output logic [cce_instr_width_gp-1:0] cce_ucode_data_o + , input [cce_instr_width_gp-1:0] cce_ucode_data_i + ); + + if (dword_width_gp != 64) $error("BedRock interface data width must be 64-bits"); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `bp_cast_o(bp_cfg_bus_s, cfg_bus); + + localparam reg_els_lp = 10; + + logic cord_r_v_li, did_r_v_li, host_did_r_v_li, hio_mask_r_v_li; + logic cord_w_v_li, did_w_v_li, host_did_w_v_li, hio_mask_w_v_li; + logic cce_ucode_r_v_li, cce_mode_r_v_li, dcache_mode_r_v_li, icache_mode_r_v_li; + logic npc_r_v_li, freeze_r_v_li; + logic cce_ucode_w_v_li, cce_mode_w_v_li, dcache_mode_w_v_li, icache_mode_w_v_li; + logic npc_w_v_li, freeze_w_v_li; + logic [dev_addr_width_gp-1:0] addr_lo; + logic [dword_width_gp-1:0] data_lo; + logic [reg_els_lp-1:0][dword_width_gp-1:0] data_li; + bp_me_bedrock_register + #(.bp_params_p(bp_params_p) + ,.reg_data_width_p(dword_width_gp) + ,.reg_addr_width_p(dev_addr_width_gp) + ,.els_p(reg_els_lp) + ,.base_addr_p({cfg_reg_cord_gp, cfg_reg_did_gp, cfg_reg_host_did_gp, cfg_reg_hio_mask_gp + ,cfg_reg_cce_mode_gp, cfg_reg_dcache_mode_gp, cfg_reg_icache_mode_gp + ,cfg_mem_cce_ucode_match_gp + ,cfg_reg_npc_gp, cfg_reg_freeze_gp + }) + ) + register + (.* + ,.r_v_o({cord_r_v_li, did_r_v_li, host_did_r_v_li, hio_mask_r_v_li + ,cce_mode_r_v_li, dcache_mode_r_v_li, icache_mode_r_v_li + ,cce_ucode_r_v_li + ,npc_r_v_li, freeze_r_v_li + }) + ,.w_v_o({cord_w_v_li, did_w_v_li, host_did_w_v_li, hio_mask_w_v_li + ,cce_mode_w_v_li, dcache_mode_w_v_li, icache_mode_w_v_li + ,cce_ucode_w_v_li + ,npc_w_v_li, freeze_w_v_li + }) + ,.addr_o(addr_lo) + ,.size_o() + ,.data_o(data_lo) + ,.data_i(data_li) + ); + + logic freeze_r; + logic [vaddr_width_p-1:0] npc_r; + bp_lce_mode_e icache_mode_r; + bp_lce_mode_e dcache_mode_r; + bp_cce_mode_e cce_mode_r; + logic [hio_width_p-1:0] hio_mask_r; + always_ff @(posedge clk_i) + if (reset_i) + begin + freeze_r <= 1'b1; + npc_r <= boot_base_addr_gp; + icache_mode_r <= e_lce_mode_uncached; + dcache_mode_r <= e_lce_mode_uncached; + cce_mode_r <= e_cce_mode_uncached; + hio_mask_r <= '0; + end + else + begin + freeze_r <= freeze_w_v_li ? data_lo : freeze_r; + npc_r <= npc_w_v_li ? data_lo : npc_r; + icache_mode_r <= bp_lce_mode_e'(icache_mode_w_v_li ? data_lo : icache_mode_r); + dcache_mode_r <= bp_lce_mode_e'(dcache_mode_w_v_li ? data_lo : dcache_mode_r); + cce_mode_r <= bp_cce_mode_e'(cce_mode_w_v_li ? data_lo : cce_mode_r); + hio_mask_r <= hio_mask_w_v_li ? data_lo : hio_mask_r; + end + + // Access to CCE ucode memory must be aligned + localparam cce_pc_offset_width_lp = `BSG_SAFE_CLOG2(`BSG_CDIV(cce_instr_width_gp,8)); + // Prevent writing CCE ucode if we're already out of uncached mode. + // We could also handle this by software, but seems dangerous to allow in hardware + assign cce_ucode_v_o = (cce_mode_r == e_cce_mode_uncached) & (cce_ucode_r_v_li | cce_ucode_w_v_li); + assign cce_ucode_w_o = (cce_mode_r == e_cce_mode_uncached) & cce_ucode_w_v_li; + assign cce_ucode_addr_o = addr_lo[cce_pc_offset_width_lp+:cce_pc_width_p]; + assign cce_ucode_data_o = data_lo[0+:cce_instr_width_gp]; + + logic [core_id_width_p-1:0] core_id_li; + logic [cce_id_width_p-1:0] cce_id_li; + logic [lce_id_width_p-1:0] icache_id_li, dcache_id_li; + bp_me_cord_to_id + #(.bp_params_p(bp_params_p)) + id_map + (.cord_i(cord_i) + ,.core_id_o(core_id_li) + ,.cce_id_o(cce_id_li) + ,.lce_id0_o(icache_id_li) + ,.lce_id1_o(dcache_id_li) + ); + + assign cfg_bus_cast_o = '{freeze: freeze_r + ,npc: npc_r + ,core_id: core_id_li + ,icache_id: icache_id_li + ,icache_mode: icache_mode_r + ,dcache_id: dcache_id_li + ,dcache_mode: dcache_mode_r + ,cce_id: cce_id_li + ,cce_mode: cce_mode_r + ,hio_mask: hio_mask_r + ,did: did_i + }; + + assign data_li[0] = freeze_r; + assign data_li[1] = npc_r; + assign data_li[2] = cce_ucode_data_i; + assign data_li[3] = icache_mode_r; + assign data_li[4] = dcache_mode_r; + assign data_li[5] = cce_mode_r; + assign data_li[6] = hio_mask_r; + assign data_li[7] = host_did_i; + assign data_li[8] = did_i; + assign data_li[9] = cord_i; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_clint_slice.sv b/designs/black-parrot/src/bp/bp_me_clint_slice.sv new file mode 100644 index 0000000..c0e9b62 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_clint_slice.sv @@ -0,0 +1,215 @@ +/** + * + * Name: + * bp_me_clint_slice.sv + * + * Description: + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_clint_slice + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input rt_clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + // Local interrupts + , output logic debug_irq_o + , output logic software_irq_o + , output logic timer_irq_o + , output logic m_external_irq_o + , output logic s_external_irq_o + ); + + if (dword_width_gp != 64) $error("BedRock interface data width must be 64-bits"); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, caddr_width_p); + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + + localparam reg_els_lp = 6; + + logic [dev_addr_width_gp-1:0] addr_lo; + logic [dword_width_gp-1:0] data_lo; + logic [reg_els_lp-1:0][dword_width_gp-1:0] data_li; + logic debug_w_v_li; + logic plic_w_v_li; + logic mtime_w_v_li, mtimesel_w_v_li, mtimecmp_w_v_li, mipi_w_v_li; + bp_me_bedrock_register + #(.bp_params_p(bp_params_p) + ,.reg_data_width_p(dword_width_gp) + ,.reg_addr_width_p(dev_addr_width_gp) + ,.els_p(reg_els_lp) + ,.base_addr_p({debug_reg_match_addr_gp, plic_reg_match_addr_gp, mtime_reg_addr_gp, mtimesel_reg_match_addr_gp, mtimecmp_reg_match_addr_gp, mipi_reg_match_addr_gp}) + ) + register + (.* + // We ignore reads because these are all asynchronous registers + ,.r_v_o() + ,.w_v_o({debug_w_v_li, plic_w_v_li, mtime_w_v_li, mtimesel_w_v_li, mtimecmp_w_v_li, mipi_w_v_li}) + ,.addr_o(addr_lo) + ,.size_o() + ,.data_o(data_lo) + ,.data_i(data_li) + ); + + logic [1:0] mtimesel_r; + wire [1:0] mtimesel_n = data_lo; + bsg_dff_reset_en + #(.width_p(2)) + mtimesel_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.en_i(mtimesel_w_v_li) + ,.data_i(mtimesel_n) + ,.data_o(mtimesel_r) + ); + + // 8:1 downsample + logic clk_ds_lo; + bsg_counter_clock_downsample + #(.width_p(3)) + ds + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.val_i(3'b111) + ,.clk_r_o(clk_ds_lo) + ); + + logic rt_clk_lo; + bsg_mux + #(.width_p(1), .els_p(4), .balanced_p(1), .harden_p(1)) + rtc_mux + (.data_i({1'b0, rt_clk_i, clk_ds_lo, clk_i}) + ,.sel_i(mtimesel_r) + ,.data_o(rt_clk_lo) + ); + + logic [dword_width_gp-1:0] mtime_gray_r; + bsg_async_ptr_gray + #(.lg_size_p(dword_width_gp)) + mtime_gray + (.w_clk_i(rt_clk_lo) + ,.w_reset_i(reset_i) + ,.w_inc_i(1'b1) // Can enable / disable through mtimesel + ,.r_clk_i(clk_i) + ,.w_ptr_binary_r_o() + ,.w_ptr_gray_r_o() + ,.w_ptr_gray_r_rsync_o(mtime_gray_r) + ); + // Cannot write the RTC. If needed, raise an issue + wire unused = mtime_w_v_li; + + logic [dword_width_gp-1:0] mtime_r; + bsg_gray_to_binary + #(.width_p(dword_width_gp)) + g2b + (.gray_i(mtime_gray_r) + ,.binary_o(mtime_r) + ); + + logic [dword_width_gp-1:0] mtimecmp_r; + wire [dword_width_gp-1:0] mtimecmp_n = data_lo; + bsg_dff_reset_en + #(.width_p(dword_width_gp)) + mtimecmp_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.en_i(mtimecmp_w_v_li) + ,.data_i(mtimecmp_n) + ,.data_o(mtimecmp_r) + ); + assign timer_irq_o = (mtime_r >= mtimecmp_r); + + logic mipi_r; + wire mipi_n = data_lo[0]; + bsg_dff_reset_en + #(.width_p(1)) + mipi_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(mipi_w_v_li) + + ,.data_i(mipi_n) + ,.data_o(mipi_r) + ); + assign software_irq_o = mipi_r; + + // This scheme can be used for N PLIC bits, which may be required in + // a distributed PLIC scheme. However, for now we only support + // M and S mode external interrupts. This code doesn't work for + // only a single PLIC bit. + localparam plic_els_lp = 2; + localparam lg_plic_els_lp = `BSG_SAFE_CLOG2(plic_els_lp); + logic [plic_els_lp-1:0] plic_n, plic_r; + wire [lg_plic_els_lp-1:0] plic_addr_li = addr_lo[2+:lg_plic_els_lp]; + + always_comb + begin + plic_n = plic_r; + plic_n[plic_addr_li] = data_lo[0]; + end + + bsg_dff_reset_en + #(.width_p(plic_els_lp)) + plic_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(plic_w_v_li) + ,.data_i(plic_n) + ,.data_o(plic_r) + ); + wire plic_lo = plic_r[plic_addr_li]; + assign m_external_irq_o = plic_r[0]; + assign s_external_irq_o = plic_r[1]; + + logic debug_r; + wire debug_n = data_lo[0]; + bsg_dff_reset_en + #(.width_p(1)) + debug_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(debug_w_v_li) + ,.data_i(debug_n) + ,.data_o(debug_r) + ); + assign debug_irq_o = debug_r; + + assign data_li[0] = mipi_r; + assign data_li[1] = mtimecmp_r; + assign data_li[2] = mtimesel_r; + assign data_li[3] = mtime_r; + assign data_li[4] = plic_lo; + assign data_li[5] = debug_r; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_cord_to_id.sv b/designs/black-parrot/src/bp/bp_me_cord_to_id.sv new file mode 100644 index 0000000..8f29ee0 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_cord_to_id.sv @@ -0,0 +1,91 @@ +/** + * + * Name: + * bp_me_cord_to_id.sv + * + * Description: + * This is helper module to convert a coordinate into a set of ids. It assumes that + * the SoC topology is a fixed 2d mesh with a set mapping. Should be made more flexible + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_cord_to_id + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input [coh_noc_cord_width_p-1:0] cord_i + , output logic [core_id_width_p-1:0] core_id_o + , output logic [cce_id_width_p-1:0] cce_id_o + , output logic [lce_id_width_p-1:0] lce_id0_o + , output logic [lce_id_width_p-1:0] lce_id1_o + ); + + wire [coh_noc_x_cord_width_p-1:0] xcord_li = cord_i[0+:coh_noc_x_cord_width_p]; + wire [coh_noc_y_cord_width_p-1:0] ycord_li = cord_i[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p]; + + // CCE: CC -> MC -> CAC -> SAC -> IOC + localparam max_cc_cce_lp = num_core_p; + localparam max_mc_cce_lp = max_cc_cce_lp + num_l2e_p; + localparam max_cac_cce_lp = max_mc_cce_lp + num_cacc_p; + localparam max_sac_cce_lp = max_cac_cce_lp + num_sacc_p; + localparam max_ic_cce_lp = max_sac_cce_lp + num_io_p; + + // LCE: CC -> CAC -> MC -> SAC -> IOC + localparam max_cc_lce_lp = num_core_p*2; + localparam max_cac_lce_lp = max_cc_lce_lp + num_cacc_p; + localparam max_mc_lce_lp = max_cac_lce_lp + num_l2e_p; + localparam max_sac_lce_lp = max_mc_lce_lp + num_sacc_p; + localparam max_ic_lce_lp = max_sac_lce_lp + num_io_p; + + wire cord_in_cc_li = (xcord_li >= sac_x_dim_p) & (xcord_li < sac_x_dim_p+cc_x_dim_p) + & (ycord_li >= ic_y_dim_p) & (ycord_li < ic_y_dim_p+cc_y_dim_p); + wire cord_in_mc_li = (ycord_li >= ic_y_dim_p+cc_y_dim_p); + wire cord_in_cac_li = (xcord_li >= cc_x_dim_p+sac_x_dim_p); + wire cord_in_sac_li = (xcord_li < sac_x_dim_p); + wire cord_in_io_li = (ycord_li < ic_y_dim_p); + + assign core_id_o = cce_id_o[0+:core_id_width_p]; + always_comb + if (cce_type_p == e_cce_uce) + begin + cce_id_o = 1'b0; + lce_id0_o = 1'b0; + lce_id1_o = 1'b1; + end + else if (cord_in_cc_li) + begin + cce_id_o = (xcord_li-sac_x_dim_p) + cc_x_dim_p * (ycord_li-ic_y_dim_p); + lce_id0_o = (cce_id_o << 1'b1) + 1'b0; + lce_id1_o = (cce_id_o << 1'b1) + 1'b1; + end + else if (cord_in_mc_li) + begin + cce_id_o = max_cc_cce_lp + (xcord_li-sac_x_dim_p); + lce_id0_o = max_cac_lce_lp + (xcord_li-sac_x_dim_p); + lce_id1_o = 'X; + end + else if (cord_in_cac_li) + begin + cce_id_o = max_mc_cce_lp + (ycord_li-ic_y_dim_p); + lce_id0_o = max_cc_lce_lp + (ycord_li-ic_y_dim_p); + lce_id1_o = 'X; + end + else if (cord_in_sac_li) + begin + cce_id_o = max_cac_cce_lp + (ycord_li-ic_y_dim_p); + lce_id0_o = max_mc_lce_lp + (ycord_li-ic_y_dim_p); + lce_id1_o = 'X; + end + else // if (cord_in_io_li) + begin + cce_id_o = max_sac_cce_lp + (xcord_li-sac_x_dim_p); + lce_id0_o = max_sac_lce_lp + (xcord_li-sac_x_dim_p); + lce_id1_o = 'X; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_defines.svh b/designs/black-parrot/src/bp/bp_me_defines.svh new file mode 100644 index 0000000..bd01fd6 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_defines.svh @@ -0,0 +1,10 @@ +`ifndef BP_ME_DEFINES_SVH +`define BP_ME_DEFINES_SVH + + `include "bsg_cache.svh" + + `include "bp_me_cce_defines.svh" + `include "bp_me_cce_inst_defines.svh" + +`endif + diff --git a/designs/black-parrot/src/bp/bp_me_dram_hash_decode.sv b/designs/black-parrot/src/bp/bp_me_dram_hash_decode.sv new file mode 100644 index 0000000..05b7e20 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_dram_hash_decode.sv @@ -0,0 +1,70 @@ +/* + * Name: + * bp_me_dram_hash_decode.sv + * + * Description: + * This module reverses the bit swizzling applied by bp_me_dram_hash_encode. + * + * IN: [ tag ][ bank ][ slice ][ cce ][ set ][ block ] + * OUT: [ tag ][ set ][ bank ][ slice ][ cce ][ block ] + * + */ + +`include "bp_common_defines.svh" + +module bp_me_dram_hash_decode + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam lg_num_cce_lp = `BSG_SAFE_CLOG2(num_cce_p) + , localparam lg_l2_slices_lp = `BSG_SAFE_CLOG2(l2_slices_p) + , localparam lg_l2_banks_lp = `BSG_SAFE_CLOG2(l2_banks_p) + , localparam lg_l2_sets_lp = `BSG_SAFE_CLOG2(l2_sets_p) + ) + (input [daddr_width_p-1:0] daddr_i + , output logic [daddr_width_p-1:0] daddr_o + ); + + // set, bank, slice, and cce index widths may be 0 (if there is only 1 cce, slice per cce, + // bank per slice, or set per bank), which needs to be accounted for when extracting bits + + localparam l2_block_offset_width_lp = `BSG_SAFE_CLOG2(l2_block_width_p/8); + localparam l2_set_index_width_lp = (l2_sets_p > 1) ? lg_l2_sets_lp : 0; + localparam l2_bank_index_width_lp = (l2_banks_p > 1) ? lg_l2_banks_lp : 0; + localparam l2_slice_index_width_lp = (l2_slices_p > 1) ? lg_l2_slices_lp : 0; + localparam l2_cce_index_width_lp = (num_cce_p > 1) ? lg_num_cce_lp : 0; + + // compute offsets for each field in the IN address + localparam l2_set_offset_lp = l2_block_offset_width_lp; + localparam l2_cce_offset_lp = l2_set_offset_lp + l2_set_index_width_lp; + localparam l2_slice_offset_lp = l2_cce_offset_lp + l2_cce_index_width_lp; + localparam l2_bank_offset_lp = l2_slice_offset_lp + l2_slice_index_width_lp; + localparam l2_tag_offset_lp = l2_bank_offset_lp + l2_bank_index_width_lp; + + // compute tag width (remaining high-order bits) + localparam l2_tag_width_lp = daddr_width_p - l2_tag_offset_lp; + + // extract fields (use offset above to compute start bit, but extract bits ignoring if size of field is 0) + wire [l2_block_offset_width_lp-1:0] block = daddr_i[0+:l2_block_offset_width_lp]; + wire [lg_l2_sets_lp-1:0] set = daddr_i[l2_set_offset_lp+:lg_l2_sets_lp]; + wire [lg_num_cce_lp-1:0] cce = daddr_i[l2_cce_offset_lp+:lg_num_cce_lp]; + wire [lg_l2_slices_lp-1:0] slice = daddr_i[l2_slice_offset_lp+:lg_l2_slices_lp]; + wire [lg_l2_banks_lp-1:0] bank = daddr_i[l2_bank_offset_lp+:lg_l2_banks_lp]; + wire [l2_tag_width_lp-1:0] tag = daddr_i[l2_tag_offset_lp+:l2_tag_width_lp]; + + // assemble the address + // note: using concatentation and replication operators would be preferred here, + // but Vivado (xsim) v2022.1 throws a fatal error when using them to assemble addr. + logic [daddr_width_p-1:0] addr; + assign addr[l2_tag_offset_lp+:l2_tag_width_lp] = tag; + assign addr[0+:l2_block_offset_width_lp] = block; + if (num_cce_p > 1) assign addr[l2_cce_offset_lp+:lg_num_cce_lp] = cce; + if (l2_slices_p > 1) assign addr[l2_slice_offset_lp+:lg_l2_slices_lp] = slice; + if (l2_banks_p > 1) assign addr[l2_bank_offset_lp+:lg_l2_banks_lp] = bank; + if (l2_sets_p > 1) assign addr[l2_set_offset_lp+:lg_l2_sets_lp] = set; + + assign daddr_o = addr; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_dram_hash_encode.sv b/designs/black-parrot/src/bp/bp_me_dram_hash_encode.sv new file mode 100644 index 0000000..f35495b --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_dram_hash_encode.sv @@ -0,0 +1,106 @@ +/* + * Name: + * bp_me_dram_hash_encode.sv + * + * Description: + * This module swizzles bits in an address, primarily to enable uniform access to L2/memory + * in a BlackParrot multicore. + * + * ADDR: [ block number ][ block ] + * IN: [ tag ][ set ][ bank ][ slice ][ cce ][ block ] + * OUT: [ tag ][ bank ][ slice ][ cce ][ set ][ block ] + * + * Blocks are striped across CCEs by bsg_hash_bank using least-significant log2(num_cce_p) bits + * from the block number field. Blocks are then distributed across slices and across banks at + * the selected L2. + * + * This hashing assumes the number of slices, banks, and sets are powers of two. The number + * of CCEs (L2s) must be a value supported by bsg_hash_bank. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_dram_hash_encode + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam lg_num_cce_lp = `BSG_SAFE_CLOG2(num_cce_p) + , localparam lg_l2_slices_lp = `BSG_SAFE_CLOG2(l2_slices_p) + , localparam lg_l2_banks_lp = `BSG_SAFE_CLOG2(l2_banks_p) + , localparam lg_l2_sets_lp = `BSG_SAFE_CLOG2(l2_sets_p) + ) + (input [paddr_width_p-1:0] paddr_i + , input [bedrock_fill_width_p-1:0] data_i + + , output logic dram_o + , output logic [daddr_width_p-1:0] daddr_o + , output logic [lg_l2_slices_lp-1:0] slice_o + , output logic [lg_l2_banks_lp-1:0] bank_o + , output logic [l2_data_width_p-1:0] data_o + ); + + bp_me_l2_csr_addr_s tag_addr_li; + assign tag_addr_li = paddr_i; + + wire is_dram_addr = paddr_i >= dram_base_addr_gp; + wire is_csr_addr = paddr_i < dram_base_addr_gp; + wire is_tag_op = is_csr_addr & paddr_i[0+:dev_addr_width_gp] inside {cache_tagop_match_addr_gp}; + wire is_lock_op = is_csr_addr & paddr_i[0+:dev_addr_width_gp] inside {cache_alock_match_addr_gp}; + wire is_addr_op = is_csr_addr & paddr_i[0+:dev_addr_width_gp] inside {cache_addrop_match_addr_gp}; + + // set, bank, slice, and cce index widths may be 0 (if there is only 1 cce, slice per cce, + // bank per slice, or set per bank), which needs to be accounted for when extracting bits + + localparam l2_block_offset_width_lp = `BSG_SAFE_CLOG2(l2_block_width_p/8); + localparam l2_set_index_width_lp = (l2_sets_p > 1) ? lg_l2_sets_lp : 0; + localparam l2_bank_index_width_lp = (l2_banks_p > 1) ? lg_l2_banks_lp : 0; + localparam l2_slice_index_width_lp = (l2_slices_p > 1) ? lg_l2_slices_lp : 0; + localparam l2_cce_index_width_lp = (num_cce_p > 1) ? lg_num_cce_lp : 0; + + // compute offsets for each field in the IN address + localparam l2_cce_offset_lp = l2_block_offset_width_lp; + localparam l2_slice_offset_lp = l2_cce_offset_lp + l2_cce_index_width_lp; + localparam l2_bank_offset_lp = l2_slice_offset_lp + l2_slice_index_width_lp; + localparam l2_set_offset_lp = l2_bank_offset_lp + l2_bank_index_width_lp; + localparam l2_tag_offset_lp = l2_set_offset_lp + l2_set_index_width_lp; + + // compute tag width (remaining high-order bits) + localparam l2_tag_width_lp = daddr_width_p - l2_tag_offset_lp; + + wire [daddr_width_p-1:0] tag_addr = {tag_addr_li.way, tag_addr_li.index} << l2_block_offset_width_lp; + wire [daddr_width_p-1:0] daddr = is_tag_op ? tag_addr : is_addr_op ? data_i : paddr_i; + + // extract fields (use offset above to compute start bit, but extract bits ignoring if size of field is 0) + wire [l2_block_offset_width_lp-1:0] block = daddr[0+:l2_block_offset_width_lp]; + wire [lg_num_cce_lp-1:0] cce = daddr[l2_cce_offset_lp+:lg_num_cce_lp]; + wire [lg_l2_slices_lp-1:0] slice = daddr[l2_slice_offset_lp+:lg_l2_slices_lp]; + wire [lg_l2_banks_lp-1:0] bank = daddr[l2_bank_offset_lp+:lg_l2_banks_lp]; + wire [lg_l2_sets_lp-1:0] set = daddr[l2_set_offset_lp+:lg_l2_sets_lp]; + wire [l2_tag_width_lp-1:0] tag = daddr[l2_tag_offset_lp+:l2_tag_width_lp]; + + // assemble the address + // note: using concatentation and replication operators would be preferred here, + // but Vivado (xsim) v2022.1 throws a fatal error when using them to assemble addr. + logic [daddr_width_p-1:0] addr; + assign addr[l2_tag_offset_lp+:l2_tag_width_lp] = tag; + assign addr[0+:l2_block_offset_width_lp] = block; + if (num_cce_p > 1) assign addr[l2_cce_offset_lp+:lg_num_cce_lp] = cce; + if (l2_slices_p > 1) assign addr[l2_slice_offset_lp+:lg_l2_slices_lp] = slice; + if (l2_banks_p > 1) assign addr[l2_bank_offset_lp+:lg_l2_banks_lp] = bank; + if (l2_sets_p > 1) assign addr[l2_set_offset_lp+:lg_l2_sets_lp] = set; + + wire [dev_id_width_gp-1:0] tag_dev = paddr_i[dev_addr_width_gp+:dev_id_width_gp]; + wire [lg_l2_slices_lp-1:0] tag_slice = tag_dev - cache_dev_gp; + + assign dram_o = is_dram_addr; + assign daddr_o = is_tag_op ? tag_addr : addr ; + assign slice_o = (l2_slices_p > 1) ? is_tag_op ? tag_slice : slice : '0; + assign bank_o = (l2_banks_p > 1) ? is_tag_op ? tag_addr_li.bank : bank : '0; + assign data_o = data_i; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_lce_id_to_cord.sv b/designs/black-parrot/src/bp/bp_me_lce_id_to_cord.sv new file mode 100644 index 0000000..a6abdba --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_lce_id_to_cord.sv @@ -0,0 +1,70 @@ +/** + * + * Name: + * bp_me_lce_id_to_cord.sv + * + * Description: + * TODO: Should be replaced by a lookup table. Programmable? + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_lce_id_to_cord + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + ) + (input [lce_id_width_p-1:0] lce_id_i + , output logic [coh_noc_cord_width_p-1:0] lce_cord_o + , output logic [coh_noc_cid_width_p-1:0] lce_cid_o + ); + + // LCE: CC -> CAC -> MC -> SAC -> IOC + localparam max_cc_lce_lp = num_core_p*2; + localparam max_cac_lce_lp = max_cc_lce_lp + num_cacc_p; + localparam max_mc_lce_lp = max_cac_lce_lp + num_l2e_p; + localparam max_sac_lce_lp = max_mc_lce_lp + num_sacc_p; + localparam max_ic_lce_lp = max_sac_lce_lp + num_io_p; + + // TODO: We only support 1 additional column / row for non-core-complex accelerators + always_comb + // Core complex + if (lce_id_i < max_cc_lce_lp) + begin + lce_cord_o[0+:coh_noc_x_cord_width_p] = sac_x_dim_p + ((lce_id_i>>1'b1) % cc_x_dim_p); + lce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = ic_y_dim_p + ((lce_id_i>>1'b1) / cc_x_dim_p); + lce_cid_o = lce_id_i[0]; + end + // Coherent accelerator complex + else if (lce_id_i < max_cac_lce_lp) + begin + lce_cord_o[0+:coh_noc_x_cord_width_p] = sac_x_dim_p + cc_x_dim_p; + lce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = ic_y_dim_p + (lce_id_i % cc_y_dim_p); + lce_cid_o = '0; + end + // Streaming accelerator complex + else if (lce_id_i < max_sac_lce_lp) + begin + lce_cord_o[0+:coh_noc_x_cord_width_p] = '0; + lce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = ic_y_dim_p + (lce_id_i % cc_y_dim_p); + lce_cid_o = '0; + end + // Memory complex + else if (lce_id_i < max_mc_lce_lp) + begin + lce_cord_o[0+:coh_noc_x_cord_width_p] = sac_x_dim_p + (lce_id_i % cc_x_dim_p); + lce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = ic_y_dim_p + cc_y_dim_p + 1'b1; + lce_cid_o = '0; + end + // IO complex + else + begin + lce_cord_o[0+:coh_noc_x_cord_width_p] = sac_x_dim_p +(lce_id_i-max_sac_lce_lp) % ic_x_dim_p; + lce_cord_o[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p] = '0; + lce_cid_o = '0; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_loopback.sv b/designs/black-parrot/src/bp/bp_me_loopback.sv new file mode 100644 index 0000000..5f103ca --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_loopback.sv @@ -0,0 +1,108 @@ +/** + * + * Name: + * bp_me_loopback.sv + * + * Description: + * This module is an active tie-off. That is, requests to this module will return the header + * with a zero payload. This is useful to not stall the network in the case of an erroneous + * address, or prevent deadlock at network boundaries + * + */ +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_loopback + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + ) + (input clk_i + , input reset_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_o(bp_bedrock_mem_rev_header_s, mem_rev_header); + + bp_bedrock_mem_fwd_header_s fsm_fwd_header_lo; + logic [bedrock_fill_width_p-1:0] fsm_fwd_data_lo; + logic fsm_fwd_v_lo, fsm_fwd_yumi_li; + logic [paddr_width_p-1:0] fsm_fwd_addr_lo; + logic fsm_fwd_new_lo, fsm_fwd_critical_lo, fsm_fwd_last_lo; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.msg_stream_mask_p(mem_fwd_stream_mask_gp) + ,.fsm_stream_mask_p(mem_fwd_stream_mask_gp | mem_rev_stream_mask_gp) + ) + fwd_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(mem_fwd_header_cast_i) + ,.msg_data_i(mem_fwd_data_i) + ,.msg_v_i(mem_fwd_v_i) + ,.msg_ready_and_o(mem_fwd_ready_and_o) + + ,.fsm_header_o(fsm_fwd_header_lo) + ,.fsm_data_o(fsm_fwd_data_lo) + ,.fsm_v_o(fsm_fwd_v_lo) + ,.fsm_yumi_i(fsm_fwd_yumi_li) + ,.fsm_addr_o(fsm_fwd_addr_lo) + ,.fsm_new_o(fsm_fwd_new_lo) + ,.fsm_critical_o(fsm_fwd_critical_lo) + ,.fsm_last_o(fsm_fwd_last_lo) + ); + + bp_bedrock_mem_rev_header_s fsm_rev_header_li; + logic [bedrock_fill_width_p-1:0] fsm_rev_data_li; + logic fsm_rev_v_li, fsm_rev_ready_then_lo; + logic [paddr_width_p-1:0] fsm_rev_addr_lo; + logic fsm_rev_new_lo, fsm_rev_critical_lo, fsm_rev_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.msg_stream_mask_p(mem_rev_stream_mask_gp) + ,.fsm_stream_mask_p(mem_fwd_stream_mask_gp | mem_rev_stream_mask_gp) + ) + rev_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(mem_rev_header_cast_o) + ,.msg_data_o(mem_rev_data_o) + ,.msg_v_o(mem_rev_v_o) + ,.msg_ready_and_i(mem_rev_ready_and_i) + + ,.fsm_header_i(fsm_rev_header_li) + ,.fsm_data_i(fsm_rev_data_li) + ,.fsm_v_i(fsm_rev_v_li) + ,.fsm_ready_then_o(fsm_rev_ready_then_lo) + ,.fsm_addr_o(fsm_rev_addr_lo) + ,.fsm_new_o(fsm_rev_new_lo) + ,.fsm_critical_o(fsm_rev_critical_lo) + ,.fsm_last_o(fsm_rev_last_lo) + ); + + assign fsm_rev_header_li = fsm_fwd_header_lo; + assign fsm_rev_data_li = fsm_fwd_data_lo; + assign fsm_rev_v_li = fsm_rev_ready_then_lo & fsm_fwd_v_lo; + assign fsm_fwd_yumi_li = fsm_rev_v_li; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_nonsynth_cce_inst_tracer.sv b/designs/black-parrot/src/bp/bp_me_nonsynth_cce_inst_tracer.sv new file mode 100644 index 0000000..55cbfc6 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_nonsynth_cce_inst_tracer.sv @@ -0,0 +1,327 @@ +/** + * + * Name: + * bp_me_nonsynth_cce_inst_tracer.v + * + * Description: + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_nonsynth_cce_inst_tracer + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam cce_inst_trace_file_p = "cce_inst" + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + ) + (input clk_i + , input reset_i + , input [cce_id_width_p-1:0] cce_id_i + , input [cce_pc_width_p-1:0] pc_i + , input instruction_v_i + , input bp_cce_inst_s instruction_i + , input stall_i + ); + + integer file; + string file_name; + + always_ff @(negedge reset_i) begin + file_name = $sformatf("%s_%x.trace", cce_inst_trace_file_p, cce_id_i); + file = $fopen(file_name, "w"); + $fwrite(file, "CCE Instruction Trace for CCE[%x]\n", cce_id_i); + $fwrite(file, "Time |: PC,Valid,Op,MinorOp,InstructionBits,Assembly\n"); + end + + always_ff @(negedge clk_i) begin + if (~reset_i & instruction_v_i & ~stall_i) begin + $fwrite(file, "%12t |: %H,%b,%b,%b,%b,", $time, pc_i, instruction_v_i + , instruction_i.op, instruction_i.minor_op_u, instruction_i.type_u); + case(instruction_i.op) + e_op_alu: begin + case(instruction_i.minor_op_u) + e_add_op: begin + $fwrite(file, "add"); + $fwrite(file, " r%0d r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_sub_op: begin + $fwrite(file, "sub"); + $fwrite(file, " r%0d r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_lsh_op: begin + $fwrite(file, "lsh"); + $fwrite(file, " r%0d r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_rsh_op: begin + $fwrite(file, "rsh"); + $fwrite(file, " r%0d r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_and_op: begin + $fwrite(file, "and"); + $fwrite(file, " r%0d r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_or_op: begin + $fwrite(file, "or"); + $fwrite(file, " r%0d r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_xor_op: begin + $fwrite(file, "xor"); + $fwrite(file, " r%0d r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_neg_op: begin + $fwrite(file, "neg"); + $fwrite(file, " r%0d r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_addi_op: begin + $fwrite(file, "addi"); + $fwrite(file, " r%0d 0x%X r%0d", instruction_i.type_u.itype.src_a, instruction_i.type_u.itype.imm, instruction_i.type_u.itype.dst); //itype + end + e_subi_op: begin + $fwrite(file, "subi"); + $fwrite(file, " r%0d 0x%X r%0d", instruction_i.type_u.itype.src_a, instruction_i.type_u.itype.imm, instruction_i.type_u.itype.dst); //itype + end + e_lshi_op: begin + $fwrite(file, "lshi"); + $fwrite(file, " r%0d 0x%X r%0d", instruction_i.type_u.itype.src_a, instruction_i.type_u.itype.imm, instruction_i.type_u.itype.dst); //itype + end + e_rshi_op: begin + $fwrite(file, "rshi"); + $fwrite(file, " r%0d 0x%X r%0d", instruction_i.type_u.itype.src_a, instruction_i.type_u.itype.imm, instruction_i.type_u.itype.dst); //itype + end + e_not_op: begin + $fwrite(file, "not"); + $fwrite(file, " r%0d", instruction_i.type_u.rtype.dst); + end + default: $fwrite(file, "invalid op"); + endcase + end + e_op_branch: begin + case(instruction_i.minor_op_u) + e_beq_op: begin + $fwrite(file, "beq"); + $fwrite(file, " r%0d r%0d 0x%X", instruction_i.type_u.btype.src_a, instruction_i.type_u.btype.src_b, instruction_i.type_u.btype.target); //btype + end + e_bne_op: begin + $fwrite(file, "bne"); + $fwrite(file, " r%0d r%0d 0x%X", instruction_i.type_u.btype.src_a, instruction_i.type_u.btype.src_b, instruction_i.type_u.btype.target); //btype + end + e_blt_op: begin + $fwrite(file, "blt"); + $fwrite(file, " r%0d r%0d 0x%X", instruction_i.type_u.btype.src_a, instruction_i.type_u.btype.src_b, instruction_i.type_u.btype.target); //btype + end + e_ble_op: begin + $fwrite(file, "ble"); + $fwrite(file, " r%0d r%0d 0x%X", instruction_i.type_u.btype.src_a, instruction_i.type_u.btype.src_b, instruction_i.type_u.btype.target); //btype + end + e_bs_op: begin + $fwrite(file, "bs"); + $fwrite(file, " rs%0d r%0d 0x%X", instruction_i.type_u.btype.src_a, instruction_i.type_u.btype.src_b, instruction_i.type_u.btype.target); //btype + end + e_bss_op: begin + $fwrite(file, "bss"); + $fwrite(file, " rs%0d rs%0d 0x%X", instruction_i.type_u.btype.src_a, instruction_i.type_u.btype.src_b, instruction_i.type_u.btype.target); //btype + end + e_beqi_op: begin + $fwrite(file, "beqi"); + $fwrite(file, " r%0d 0x%X 0x%X", instruction_i.type_u.bitype.src_a, instruction_i.type_u.bitype.imm, instruction_i.type_u.bitype.target); //bitype + end + e_bneqi_op: begin + $fwrite(file, "bneqi"); + $fwrite(file, " r%0d 0x%X 0x%X", instruction_i.type_u.bitype.src_a, instruction_i.type_u.bitype.imm, instruction_i.type_u.bitype.target); //bitype + end + e_bsi_op: begin + $fwrite(file, "bsi"); + $fwrite(file, " rs%0d 0x%X 0x%X", instruction_i.type_u.bitype.src_a, instruction_i.type_u.bitype.imm, instruction_i.type_u.bitype.target); //bitype + end + default: $fwrite(file, "invalid op"); + endcase + end + e_op_reg_data: begin + case(instruction_i.minor_op_u) + e_mov_op: begin + $fwrite(file, "mov"); + $fwrite(file, " r%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.dst); //rtype + end + e_movsg_op: begin + $fwrite(file, "movsg"); + $fwrite(file, " rs%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.dst); //rtype + end + e_movgs_op: begin + $fwrite(file, "movgs"); + $fwrite(file, " r%0d rs%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.dst); //rtype + end + e_movfg_op: begin + $fwrite(file, "movfg"); + $fwrite(file, " f%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.dst); //rtype + end + e_movgf_op: begin + $fwrite(file, "movgf"); + $fwrite(file, " r%0d f%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.dst); //rtype + end + e_movpg_op: begin + $fwrite(file, "movpg"); + $fwrite(file, " p%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.dst); //rtype + end + e_movgp_op: begin + $fwrite(file, "movgp"); + $fwrite(file, " r%0d p%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.dst); //rtype + end + e_movi_op: begin + $fwrite(file, "movi"); + $fwrite(file, " 0x%X r%0d",instruction_i.type_u.itype.imm, instruction_i.type_u.itype.dst); //itype + end + e_movis_op: begin + $fwrite(file, "movis"); + $fwrite(file, " 0x%X rs%0d",instruction_i.type_u.itype.imm, instruction_i.type_u.itype.dst); //itype + end + e_movip_op: begin + $fwrite(file, "movip"); + $fwrite(file, " 0x%X r%0d",instruction_i.type_u.itype.imm, instruction_i.type_u.itype.dst); //itype + end + e_clm_op: begin + $fwrite(file, "clm"); + //no arguments + end + default: $fwrite(file, "invalid op"); + endcase + end + e_op_flag: begin + case(instruction_i.minor_op_u) + e_sf_op: begin + $fwrite(file, "sf"); + $fwrite(file, " f%X",instruction_i.type_u.itype.imm); //itype + end + e_andf_op: begin + $fwrite(file, "andf"); + $fwrite(file, " f%0d f%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_orf_op: begin + $fwrite(file, "orf"); + $fwrite(file, " f%0d f%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_nandf_op: begin + $fwrite(file, "nandf"); + $fwrite(file, " f%0d f%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_norf_op: begin + $fwrite(file, "norf"); + $fwrite(file, " f%0d f%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.src_b, instruction_i.type_u.rtype.dst); //rtype + end + e_notf_op: begin + $fwrite(file, "notf"); + $fwrite(file, " f%0d r%0d", instruction_i.type_u.rtype.src_a, instruction_i.type_u.rtype.dst); //rtype + end + e_bf_op: begin + $fwrite(file, "bf"); + $fwrite(file, " 0x%X f%0d", instruction_i.type_u.bftype.target, instruction_i.type_u.bftype.imm); //bftype + end + e_bfz_op: begin + $fwrite(file, "bfz"); + $fwrite(file, " 0x%X f%0d", instruction_i.type_u.bftype.target, instruction_i.type_u.bftype.imm); //bftype + end + e_bfnz_op: begin + $fwrite(file, "bfnz"); + $fwrite(file, " 0x%X f%0d", instruction_i.type_u.bftype.target, instruction_i.type_u.bftype.imm); //bftype + end + e_bfnot_op: begin + $fwrite(file, "bfnot"); + $fwrite(file, " 0x%X f%0d", instruction_i.type_u.bftype.target, instruction_i.type_u.bftype.imm); //bftype + end + default: $fwrite(file, "invalid op"); + endcase + end + e_op_dir: begin + case(instruction_i.minor_op_u) + e_rdp_op: begin + $fwrite(file, "rdp"); + $fwrite(file, " addr=%0d", instruction_i.type_u.dptype.addr_sel); //dptype + end + e_rdw_op: begin + $fwrite(file, "rdw"); + $fwrite(file, " addr=%0d lce=%0d lru_way=%0d dst=%0d", instruction_i.type_u.drtype.addr_sel, instruction_i.type_u.drtype.lce_sel, instruction_i.type_u.drtype.lru_way_sel, instruction_i.type_u.drtype.dst); //drtype + end + e_rde_op: begin + $fwrite(file, "rde"); + $fwrite(file, " addr=%0d lce=%0d way=%0d dst=%0d", instruction_i.type_u.drtype.addr_sel, instruction_i.type_u.drtype.lce_sel, instruction_i.type_u.drtype.way_sel, instruction_i.type_u.drtype.dst); //drtype + end + e_wdp_op: begin + $fwrite(file, "wdp"); + $fwrite(file, " addr=%0d p=%0d", instruction_i.type_u.dptype.addr_sel, instruction_i.type_u.dptype.pending); //dptype + end + e_clp_op: begin + $fwrite(file, "clp"); + $fwrite(file, " addr=%0d", instruction_i.type_u.dptype.addr_sel); //dptype + end + e_clr_op: begin + $fwrite(file, "clr"); + $fwrite(file, " addr=%0d lce=%0d", instruction_i.type_u.drtype.addr_sel, instruction_i.type_u.drtype.lce_sel); //drtype + end + e_wde_op: begin + $fwrite(file, "wde"); + $fwrite(file, " addr=%0d lce=%0d way=%0d state=%0d", instruction_i.type_u.dwtype.addr_sel, instruction_i.type_u.dwtype.lce_sel, instruction_i.type_u.dwtype.way_sel, instruction_i.type_u.dwtype.state); //dwtype + end + e_wds_op: begin + $fwrite(file, "wds"); + $fwrite(file, " addr=%0d lce=%0d way=%0d state=%0d", instruction_i.type_u.dwtype.addr_sel, instruction_i.type_u.dwtype.lce_sel, instruction_i.type_u.dwtype.way_sel, instruction_i.type_u.dwtype.state); //dwtype + end + e_gad_op: begin + $fwrite(file, "gad"); + //no arguments + end + default: $fwrite(file, "invalid op"); + endcase + end + e_op_queue: begin + case(instruction_i.minor_op_u) + e_wfq_op: begin + $fwrite(file, "wfq"); + $fwrite(file, " q%0d", instruction_i.type_u.itype.imm); //itype + end + e_pushq_op: begin + $fwrite(file, "pushq"); + $fwrite(file, " q%0d cmd addr=%0d lce=%0d way=%0d wp=%0d spec=%0d", instruction_i.type_u.pushq.dst_q, instruction_i.type_u.pushq.addr_sel, instruction_i.type_u.pushq.lce_sel, instruction_i.type_u.pushq.way_or_size.way_sel, instruction_i.type_u.pushq.write_pending, instruction_i.type_u.pushq.spec); //pushq + end + e_popq_op: begin + $fwrite(file, "popq"); + $fwrite(file, " q%0d", instruction_i.type_u.popq.src_q); //popq + end + e_poph_op: begin + $fwrite(file, "poph"); + $fwrite(file, " q%0d r%0d", instruction_i.type_u.popq.src_q, instruction_i.type_u.popq.dst); //popq + end + e_popd_op: begin + $fwrite(file, "popd"); + $fwrite(file, " q%0d r%0d", instruction_i.type_u.popq.src_q, instruction_i.type_u.popq.dst); //popq + end + e_specq_op: begin + $fwrite(file, "specq "); + case(instruction_i.type_u.stype.cmd) + e_spec_set: $fwrite(file, "spec_set"); + e_spec_unset: $fwrite(file, "spec_unset"); + e_spec_squash: $fwrite(file, "spec_squash"); + e_spec_fwd_mod: $fwrite(file, "spec_fwd_mod"); + e_spec_rd_spec: $fwrite(file, "spec_rd_spec"); + default: $fwrite(file, "invalid command"); + endcase + $fwrite(file, " %0d", instruction_i.type_u.stype.addr_sel); + end + e_inv_op: begin + $fwrite(file, "inv"); + //no arguments + end + default: $fwrite(file, "invalid op"); + endcase + end + default: $fwrite(file, "invalid op"); + endcase + $fwrite(file, "\n"); + end // ~reset_i + end //always_ff + +endmodule diff --git a/designs/black-parrot/src/bp/bp_me_nonsynth_cce_pending_tracer.sv b/designs/black-parrot/src/bp/bp_me_nonsynth_cce_pending_tracer.sv new file mode 100644 index 0000000..cdfac5d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_nonsynth_cce_pending_tracer.sv @@ -0,0 +1,70 @@ +/** + * + * Name: + * bp_me_nonsynth_cce_pending_tracer + * + * Description: + * CCE pending bit tracer + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_nonsynth_cce_pending_tracer + import bp_common_pkg::*; + #(parameter `BSG_INV_PARAM(num_way_groups_p) + , parameter `BSG_INV_PARAM(cce_id_width_p) + , parameter `BSG_INV_PARAM(paddr_width_p) + + // Default parameters + , parameter width_p = 3 // pending bit counter width + + , parameter cce_pending_trace_file_p = "cce_pending" + + // Derived parameters + , localparam lg_num_way_groups_lp = `BSG_SAFE_CLOG2(num_way_groups_p) + ) + (input clk_i + , input reset_i + , input [cce_id_width_p-1:0] cce_id_i + , input [num_way_groups_p-1:0][width_p-1:0] pending_bits_i + , input w_v_i + , input [lg_num_way_groups_lp-1:0] w_wg_i + , input [paddr_width_p-1:0] w_addr_i + , input pending_i + , input clear_i + ); + + integer file; + string file_name; + + always_ff @(negedge reset_i) begin + file_name = $sformatf("%s_%x.trace", cce_pending_trace_file_p, cce_id_i); + file = $fopen(file_name, "w"); + end + + // Tracer + always_ff @(negedge clk_i) begin + if (~reset_i) begin + if (w_v_i) begin + if (clear_i) begin + $fdisplay(file, "%12t |: CCE[%0d] addr[%H] wg[%d] clear" + , $time, cce_id_i, w_addr_i, w_wg_i + ); + end + else if (pending_i) begin + $fdisplay(file, "%12t |: CCE[%0d] addr[%H] wg[%d] incr := %0d" + , $time, cce_id_i, w_addr_i, w_wg_i, pending_bits_i[w_wg_i] + 'd1 + ); + end + else if (~pending_i) begin + $fdisplay(file, "%12t |: CCE[%0d] addr[%H] wg[%d] decr := %0d" + , $time, cce_id_i, w_addr_i, w_wg_i, pending_bits_i[w_wg_i] - 'd1 + ); + end + end + end // reset + end // always_ff + +endmodule diff --git a/designs/black-parrot/src/bp/bp_me_nonsynth_cce_perf.sv b/designs/black-parrot/src/bp/bp_me_nonsynth_cce_perf.sv new file mode 100644 index 0000000..ad42a37 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_nonsynth_cce_perf.sv @@ -0,0 +1,150 @@ +/** + * + * Name: + * bp_me_nonsynth_cce_perf.sv + * + * Description: + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_nonsynth_cce_perf + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam cnt_max_lp = 64'h0FFF_FFFF_FFFF_FFFF + , localparam cce_trace_file_p = "cce_perf" + , localparam cnt_ptr_width_lp = `BSG_SAFE_CLOG2(cnt_max_lp+1) + ) + (input clk_i + , input reset_i + , input [cce_id_width_p-1:0] cce_id_i + , input req_start_i + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input req_end_i + , input cmd_send_i + , input [lce_cmd_header_width_lp-1:0] lce_cmd_header_i + , input resp_receive_i + , input [lce_resp_header_width_lp-1:0] lce_resp_header_i + , input mem_rev_receive_i + , input mem_rev_squash_i + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input mem_fwd_send_i + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + bp_bedrock_lce_req_header_s lce_req; + + integer file; + string file_name; + + always_ff @(negedge reset_i) begin + file_name = $sformatf("%s_%x.trace", cce_trace_file_p, cce_id_i); + file = $fopen(file_name, "w"); + $fdisplay(file, "Time |: Cycle,CCE,Op,Latency"); + end + + logic req_started_r; + + logic cnt_up; + wire cnt_clr = ~req_started_r & req_start_i; + logic [cnt_ptr_width_lp-1:0] cnt; + bsg_counter_clear_up + #(.max_val_p(cnt_max_lp) + ,.init_val_p('0) + ) + req_latency_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(cnt_clr) + ,.up_i(cnt_up) + ,.count_o(cnt) + ); + + logic [cnt_ptr_width_lp-1:0] total_cycles, idle_cycles; + + bsg_counter_clear_up + #(.max_val_p(cnt_max_lp) + ,.init_val_p('0) + ) + cycles_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(reset_i) + ,.up_i(1'b1) + ,.count_o(total_cycles) + ); + + // idle when not actively processing a request + bsg_counter_clear_up + #(.max_val_p(cnt_max_lp) + ,.init_val_p('0) + ) + idle_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(reset_i) + ,.up_i(~cnt_up) + ,.count_o(idle_cycles) + ); + + bsg_dff_reset_en + #(.width_p($bits(bp_bedrock_lce_req_header_s))) + lce_req_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(cnt_clr) + ,.data_i(lce_req_header_i) + ,.data_o(lce_req) + ); + + always_ff @(posedge clk_i) begin + if (reset_i) begin + req_started_r <= 1'b0; + cnt_up <= 1'b0; + end else begin + if (~req_started_r & req_start_i) begin + req_started_r <= 1'b1; + cnt_up <= 1'b1; + end + if (req_started_r & req_end_i) begin + cnt_up <= 1'b0; + req_started_r <= 1'b0; + end + end + end + + string op; + always_comb begin + case (lce_req.msg_type.req) + e_bedrock_req_rd_miss: op = "RD"; + e_bedrock_req_wr_miss: op = "WR"; + e_bedrock_req_uc_rd: op = "UC_RD"; + e_bedrock_req_uc_wr: op = "UC_WR"; + default: op = "BAD"; + endcase + end + + // Tracer + always_ff @(negedge clk_i) begin + if (~reset_i) begin + if (req_started_r & req_end_i) begin + $fdisplay(file, "%12t |: %0d,%0d,%s,%0d", $time, total_cycles, cce_id_i, op, cnt+'d1); + end + end // reset + end // always_ff + + final begin + $fdisplay(file, "%12t |: total: %0d", $time, total_cycles); + $fdisplay(file, "%12t |: busy: %0d", $time, total_cycles - idle_cycles); + $fdisplay(file, "%12t |: idle: %0d", $time, idle_cycles); + end + +endmodule diff --git a/designs/black-parrot/src/bp/bp_me_nonsynth_cce_tracer.sv b/designs/black-parrot/src/bp/bp_me_nonsynth_cce_tracer.sv new file mode 100644 index 0000000..76826ac --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_nonsynth_cce_tracer.sv @@ -0,0 +1,214 @@ +/** + * + * Name: + * bp_me_nonsynth_cce_tracer.v + * + * Description: + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_nonsynth_cce_tracer + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam cce_trace_file_p = "cce" + + // Derived parameters + , localparam block_size_in_bytes_lp = (bedrock_block_width_p/8) + , localparam lg_block_size_in_bytes_lp = `BSG_SAFE_CLOG2(block_size_in_bytes_lp) + + // number of way groups managed by this CCE + , localparam num_way_groups_lp = `BSG_CDIV(cce_way_groups_p, num_cce_p) + , localparam lg_num_way_groups_lp = `BSG_SAFE_CLOG2(num_way_groups_lp) + , localparam lg_cce_way_groups_lp = `BSG_SAFE_CLOG2(cce_way_groups_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + ) + (input clk_i + , input reset_i + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + , input [lce_req_header_width_lp-1:0] lce_req_header_i + , input [bedrock_fill_width_p-1:0] lce_req_data_i + , input lce_req_v_i + , input lce_req_ready_and_i + + , input [lce_resp_header_width_lp-1:0] lce_resp_header_i + , input [bedrock_fill_width_p-1:0] lce_resp_data_i + , input lce_resp_v_i + , input lce_resp_ready_and_i + + , input [lce_cmd_header_width_lp-1:0] lce_cmd_header_i + , input [bedrock_fill_width_p-1:0] lce_cmd_data_i + , input lce_cmd_v_i + , input lce_cmd_ready_and_i + + // CCE-MEM Interface + // BedRock Stream protocol: ready&valid + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , input mem_rev_ready_and_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , input mem_fwd_ready_and_i + + , input [cce_id_width_p-1:0] cce_id_i + ); + + // LCE-CCE and Mem-CCE Interface + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + // LCE-CCE Interface structs + `bp_cast_i(bp_bedrock_lce_req_header_s, lce_req_header); + `bp_cast_i(bp_bedrock_lce_cmd_header_s, lce_cmd_header); + `bp_cast_i(bp_bedrock_lce_resp_header_s, lce_resp_header); + + // CCE-MEM Interface structs + `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_i(bp_bedrock_mem_rev_header_s, mem_rev_header); + + integer file; + string file_name; + + always_ff @(negedge reset_i) begin + file_name = $sformatf("%s_%x.trace", cce_trace_file_p, cce_id_i); + file = $fopen(file_name, "w"); + end + + // Tracer + always_ff @(negedge clk_i) begin + if (~reset_i) begin + // inbound messages + if (lce_req_v_i & lce_req_ready_and_i) begin + if (lce_req_header_cast_i.msg_type.req == e_bedrock_req_rd_miss + | lce_req_header_cast_i.msg_type.req == e_bedrock_req_wr_miss) begin + $fdisplay(file, "%12t |: CCE[%0d] REQ LCE[%0d] addr[%H] wg[%0d] wr[%0b] ne[%0b] uc[%0b] lruWay[%0d]" + , $time, lce_req_header_cast_i.payload.dst_id, lce_req_header_cast_i.payload.src_id + , lce_req_header_cast_i.addr + , lce_req_header_cast_i.addr[lg_block_size_in_bytes_lp +: lg_cce_way_groups_lp] + , (lce_req_header_cast_i.msg_type.req == e_bedrock_req_wr_miss) + , lce_req_header_cast_i.payload.non_exclusive + , 1'b0 + , lce_req_header_cast_i.payload.lru_way_id + ); + end + if (lce_req_header_cast_i.msg_type.req == e_bedrock_req_uc_rd) begin + $fdisplay(file, "%12t |: CCE[%0d] REQ LCE[%0d] addr[%H] wr[%0b] ne[%0b] uc[%0b] lruWay[%0d] lruDirty[%0b]" + , $time, lce_req_header_cast_i.payload.dst_id, lce_req_header_cast_i.payload.src_id + , lce_req_header_cast_i.addr, (lce_req_header_cast_i.msg_type.req == e_bedrock_req_uc_wr) + , 1'b0 + , 1'b1 + , '0, '0 + ); + end + if (lce_req_header_cast_i.msg_type.req == e_bedrock_req_uc_wr) begin + $fdisplay(file, "%12t |: CCE[%0d] REQ LCE[%0d] addr[%H] wr[%0b] ne[%0b] uc[%0b] lruWay[%0d] lruDirty[%0b]" + , $time, lce_req_header_cast_i.payload.dst_id, lce_req_header_cast_i.payload.src_id + , lce_req_header_cast_i.addr, (lce_req_header_cast_i.msg_type.req == e_bedrock_req_uc_wr) + , 1'b0 + , 1'b1 + , '0, '0 + ); + end + end + if (lce_req_v_i & lce_req_ready_and_i) begin + $fdisplay(file, "%12t |: LCE REQ DATA %H" + , $time, lce_req_data_i + ); + end + if (lce_resp_v_i & lce_resp_ready_and_i) begin + if ((lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_sync_ack) + | (lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_inv_ack) + | (lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_coh_ack)) begin + $fdisplay(file, "%12t |: CCE[%0d] RESP LCE[%0d] addr[%H] wg[%0d] ack[%4b]" + , $time, lce_resp_header_cast_i.payload.dst_id, lce_resp_header_cast_i.payload.src_id + , lce_resp_header_cast_i.addr + , lce_resp_header_cast_i.addr[lg_block_size_in_bytes_lp +: lg_cce_way_groups_lp] + , lce_resp_header_cast_i.msg_type.resp + ); + end + if ((lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_wb) + | (lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_null_wb)) begin + $fdisplay(file, "%12t |: CCE[%0d] DATA RESP LCE[%0d] addr[%H] wg[%0d] null_wb[%0b]" + , $time, lce_resp_header_cast_i.payload.dst_id, lce_resp_header_cast_i.payload.src_id + , lce_resp_header_cast_i.addr + , lce_resp_header_cast_i.addr[lg_block_size_in_bytes_lp +: lg_cce_way_groups_lp] + , (lce_resp_header_cast_i.msg_type.resp == e_bedrock_resp_null_wb) + ); + end + end + if (lce_resp_v_i & lce_resp_ready_and_i) begin + $fdisplay(file, "%12t |: LCE RESP DATA %H" + , $time, lce_resp_data_i + ); + end + if (mem_rev_v_i & mem_rev_ready_and_i) begin + if (mem_rev_header_cast_i.msg_type.rev == e_bedrock_mem_wr) begin + $fdisplay(file, "%12t |: CCE[%0d] MEM REV wb[%0b] addr[%H] wg[%0d] lce[%0d] way[%0d]" + , $time, cce_id_i, (mem_rev_header_cast_i.msg_type.rev == e_bedrock_mem_wr) + , mem_rev_header_cast_i.addr + , mem_rev_header_cast_i.addr[lg_block_size_in_bytes_lp +: lg_cce_way_groups_lp] + , mem_rev_header_cast_i.payload.lce_id, mem_rev_header_cast_i.payload.way_id + ); + end + if (mem_rev_header_cast_i.msg_type.rev == e_bedrock_mem_rd) begin + $fdisplay(file, "%12t |: CCE[%0d] MEM DATA RESP addr[%H] wg[%0d] lce[%0d] way[%0d] state[%3b] spec[%0b] %H" + , $time, cce_id_i, mem_rev_header_cast_i.addr + , mem_rev_header_cast_i.addr[lg_block_size_in_bytes_lp +: lg_cce_way_groups_lp] + , mem_rev_header_cast_i.payload.lce_id, mem_rev_header_cast_i.payload.way_id + , mem_rev_header_cast_i.payload.state + , mem_rev_header_cast_i.payload.speculative + , mem_rev_data_i + ); + end + end + // outbound messages + if (lce_cmd_v_i & lce_cmd_ready_and_i) begin + $fdisplay(file, "%12t |: CCE[%0d] CMD LCE[%0d] addr[%H] wg[%0d] cmd[%4b] way[%0d] state[%3b] tgt[%0d] tgtWay[%0d] tgtSt[%3b]" + , $time, lce_cmd_header_cast_i.payload.src_id, lce_cmd_header_cast_i.payload.dst_id + , lce_cmd_header_cast_i.addr + , lce_cmd_header_cast_i.addr[lg_block_size_in_bytes_lp +: lg_cce_way_groups_lp] + , lce_cmd_header_cast_i.msg_type.cmd, lce_cmd_header_cast_i.payload.way_id + , lce_cmd_header_cast_i.payload.state, lce_cmd_header_cast_i.payload.target + , lce_cmd_header_cast_i.payload.target_way_id + , lce_cmd_header_cast_i.payload.target_state + ); + end + if (lce_cmd_v_i & lce_cmd_ready_and_i) begin + $fdisplay(file, "%12t |: LCE CMD DATA %H" + , $time, lce_cmd_data_i + ); + end + if (mem_fwd_v_i & mem_fwd_ready_and_i) begin + if (mem_fwd_header_cast_i.msg_type.fwd == e_bedrock_mem_rd) begin + $fdisplay(file, "%12t |: CCE[%0d] MEM FWD addr[%H] wg[%0d] lce[%0d] way[%0d] spec[%0b]" + , $time, cce_id_i, mem_fwd_header_cast_i.addr + , mem_fwd_header_cast_i.addr[lg_block_size_in_bytes_lp +: lg_cce_way_groups_lp] + , mem_fwd_header_cast_i.payload.lce_id + , mem_fwd_header_cast_i.payload.way_id, mem_fwd_header_cast_i.payload.speculative + ); + end + if (mem_fwd_header_cast_i.msg_type.fwd == e_bedrock_mem_wr) begin + $fdisplay(file, "%12t |: CCE[%0d] MEM DATA FWD wb[%0b] addr[%H] wg[%0d] lce[%0d] way[%0d] state[%3b] %H" + , $time, cce_id_i, (mem_fwd_header_cast_i.msg_type.fwd == e_bedrock_mem_wr) + , mem_fwd_header_cast_i.addr + , mem_fwd_header_cast_i.addr[lg_block_size_in_bytes_lp +: lg_cce_way_groups_lp] + , mem_fwd_header_cast_i.payload.lce_id, mem_fwd_header_cast_i.payload.way_id + , mem_fwd_header_cast_i.payload.state + , mem_fwd_data_i + ); + end + end + end // reset & trace + end // always_ff + +endmodule diff --git a/designs/black-parrot/src/bp/bp_me_nonsynth_dev_tracer.sv b/designs/black-parrot/src/bp/bp_me_nonsynth_dev_tracer.sv new file mode 100644 index 0000000..55b2217 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_nonsynth_dev_tracer.sv @@ -0,0 +1,89 @@ +/** + * + * Name: + * bp_me_nonsynth_dev_tracer.sv + * + * Description: + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_nonsynth_dev_tracer + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter trace_file_p = "dev" + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + ) + (input clk_i + , input reset_i + + , input [core_id_width_p-1:0] mhartid_i + + // CCE-MEM Interface + // BedRock Stream protocol: ready&valid + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , input mem_fwd_ready_and_i + + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , input mem_rev_ready_and_i + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + + `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_i(bp_bedrock_mem_rev_header_s, mem_rev_header); + + integer file; + string file_name; + + always_ff @(negedge reset_i) + begin + file_name = $sformatf("%s_%x.trace", trace_file_p, mhartid_i); + file = $fopen(file_name, "w"); + end + + // Tracer + always_ff @(negedge clk_i) begin + if (~reset_i) begin + if (mem_fwd_v_i & mem_fwd_ready_and_i) begin + $fdisplay(file, "%12t |: MEM FWD addr[%H] msg[%b] size[%b]" + , $time + , mem_fwd_header_cast_i.addr + , mem_fwd_header_cast_i.msg_type.fwd + , mem_fwd_header_cast_i.size + ); + if (mem_fwd_header_cast_i.msg_type.fwd == e_bedrock_mem_wr) begin + $fdisplay(file, "%12t |: MEM FWD DATA %H" + , $time + , mem_fwd_data_i + ); + end + end + if (mem_rev_v_i & mem_rev_ready_and_i) begin + $fdisplay(file, "%12t |: MEM REV addr[%H] msg[%b] size[%b]" + , $time + , mem_rev_header_cast_i.addr + , mem_rev_header_cast_i.msg_type.rev + , mem_rev_header_cast_i.size + ); + if (mem_rev_header_cast_i.msg_type.rev == e_bedrock_mem_rd) begin + $fdisplay(file, "%12t |: MEM REV DATA %H" + , $time + , mem_rev_data_i + ); + end + end + end // reset & trace + end // always_ff + +endmodule diff --git a/designs/black-parrot/src/bp/bp_me_nonsynth_lce_tracer.sv b/designs/black-parrot/src/bp/bp_me_nonsynth_lce_tracer.sv new file mode 100644 index 0000000..052a402 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_nonsynth_lce_tracer.sv @@ -0,0 +1,210 @@ +/** + * bp_me_nonsynth_lce_tracer.v + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_nonsynth_lce_tracer + import bp_common_pkg::*; + import bp_me_nonsynth_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(sets_p) + , parameter `BSG_INV_PARAM(assoc_p) + , parameter `BSG_INV_PARAM(block_width_p) + , parameter `BSG_INV_PARAM(fill_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + + , localparam lce_trace_file_p = "lce" + + , localparam block_size_in_bytes_lp=(block_width_p / 8) + + , localparam block_offset_bits_lp=`BSG_SAFE_CLOG2(block_size_in_bytes_lp) + + , localparam lg_sets_lp=`BSG_SAFE_CLOG2(sets_p) + , localparam lg_assoc_lp=`BSG_SAFE_CLOG2(assoc_p) + + , localparam ptag_width_lp=(paddr_width_p-lg_sets_lp-block_offset_bits_lp) + + , localparam lg_num_cce_lp=`BSG_SAFE_CLOG2(num_cce_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam integer cnt_max_lp = 1<<31 + , localparam cnt_ptr_width_lp = `BSG_SAFE_CLOG2(cnt_max_lp+1) + ) + ( + input clk_i + ,input reset_i + + ,input [lce_id_width_p-1:0] lce_id_i + + // LCE-CCE Interface + ,input [lce_req_header_width_lp-1:0] lce_req_header_i + ,input [bedrock_fill_width_p-1:0] lce_req_data_i + ,input lce_req_v_i + ,input lce_req_ready_and_i + + ,input [lce_cmd_header_width_lp-1:0] lce_cmd_header_i + ,input [bedrock_fill_width_p-1:0] lce_cmd_data_i + ,input lce_cmd_v_i + ,input lce_cmd_ready_and_i + + ,input [lce_fill_header_width_lp-1:0] lce_fill_header_i + ,input [bedrock_fill_width_p-1:0] lce_fill_data_i + ,input lce_fill_v_i + ,input lce_fill_ready_and_i + + ,input [lce_fill_header_width_lp-1:0] lce_fill_o_header_i + ,input [bedrock_fill_width_p-1:0] lce_fill_o_data_i + ,input lce_fill_o_v_i + ,input lce_fill_o_ready_and_i + + ,input [lce_resp_header_width_lp-1:0] lce_resp_header_i + ,input [bedrock_fill_width_p-1:0] lce_resp_data_i + ,input lce_resp_v_i + ,input lce_resp_ready_and_i + + ,input cache_req_last_i + ); + + // LCE-CCE interface structs + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `bp_cast_i(bp_bedrock_lce_req_header_s, lce_req_header); + `bp_cast_i(bp_bedrock_lce_cmd_header_s, lce_cmd_header); + `bp_cast_i(bp_bedrock_lce_resp_header_s, lce_resp_header); + `bp_cast_i(bp_bedrock_lce_fill_header_s, lce_fill_header); + `bp_cast_i(bp_bedrock_lce_fill_header_s, lce_fill_o_header); + + // Structs for output messages + + integer file; + string file_name; + + always_ff @(negedge reset_i) begin + file_name = $sformatf("%s_%x.trace", lce_trace_file_p, lce_id_i); + file = $fopen(file_name, "w"); + end + + logic cnt_up; + wire req_cnt_clr = lce_req_v_i & lce_req_ready_and_i; + logic [cnt_ptr_width_lp-1:0] req_cnt; + bsg_counter_clear_up + #(.max_val_p(cnt_max_lp) + ,.init_val_p('0) + ) + req_latency_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(req_cnt_clr) + ,.up_i(cnt_up) + ,.count_o(req_cnt) + ); + + wire uc_req = lce_req_header_cast_i.msg_type.req inside {e_bedrock_req_uc_rd, e_bedrock_req_uc_wr}; + + always_ff @(negedge clk_i) begin + if (reset_i) begin + cnt_up <= 1'b0; + end else begin + + // LCE-CCE Interface + + // request to CCE + if (lce_req_v_i & lce_req_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] REQ addr[%H] cce[%0d] msg[%b] uc[%b] tag[%H] set[%0d] ne[%b] lru[%0d] size[%b]" + , $time, lce_req_header_cast_i.payload.src_id, lce_req_header_cast_i.addr, lce_req_header_cast_i.payload.dst_id, lce_req_header_cast_i.msg_type + , uc_req + , lce_req_header_cast_i.addr[paddr_width_p-1:(lg_sets_lp+block_offset_bits_lp)] + , lce_req_header_cast_i.addr[block_offset_bits_lp+:lg_sets_lp] + , lce_req_header_cast_i.payload.non_exclusive, lce_req_header_cast_i.payload.lru_way_id + , lce_req_header_cast_i.size + ); + cnt_up <= 1'b1; + end + if (lce_req_v_i & lce_req_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] REQ DATA %H" + , $time, lce_id_i + , lce_req_data_i + ); + end + + // response to CCE + if (lce_resp_v_i & lce_resp_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] RESP addr[%H] cce[%0d] msg[%b] set[%0d] size[%b]" + , $time, lce_resp_header_cast_i.payload.src_id, lce_resp_header_cast_i.addr, lce_resp_header_cast_i.payload.dst_id, lce_resp_header_cast_i.msg_type.resp + , lce_resp_header_cast_i.addr[block_offset_bits_lp+:lg_sets_lp] + , lce_resp_header_cast_i.size + ); + end + if (lce_resp_v_i & lce_resp_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] RESP DATA %H" + , $time, lce_id_i + , lce_resp_data_i + ); + end + + // command to LCE + if (lce_cmd_v_i & lce_cmd_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] CMD IN addr[%H] cce[%0d] msg[%b] set[%0d] way[%0d] state[%b] tgt[%0d] tgt_way[%0d] tgt_state[%b] size[%b]" + , $time, lce_cmd_header_cast_i.payload.dst_id, lce_cmd_header_cast_i.addr, lce_cmd_header_cast_i.payload.src_id, lce_cmd_header_cast_i.msg_type.cmd + , lce_cmd_header_cast_i.addr[block_offset_bits_lp+:lg_sets_lp], lce_cmd_header_cast_i.payload.way_id, lce_cmd_header_cast_i.payload.state, lce_cmd_header_cast_i.payload.target + , lce_cmd_header_cast_i.payload.target_way_id + , lce_cmd_header_cast_i.payload.target_state + , lce_cmd_header_cast_i.size + ); + end + if (lce_cmd_v_i & lce_cmd_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] CMD DATA %H" + , $time, lce_id_i + , lce_cmd_data_i + ); + end + + // Fill to LCE + if (lce_fill_v_i & lce_fill_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] FILL IN addr[%H] cce[%0d] msg[%b] set[%0d] way[%0d] state[%b] size[%b]" + , $time, lce_fill_header_cast_i.payload.dst_id, lce_fill_header_cast_i.addr + , lce_fill_header_cast_i.payload.src_id, lce_fill_header_cast_i.msg_type.fill + , lce_fill_header_cast_i.addr[block_offset_bits_lp+:lg_sets_lp] + , lce_fill_header_cast_i.payload.way_id, lce_fill_header_cast_i.payload.state + , lce_fill_header_cast_i.size + ); + end + if (lce_fill_v_i & lce_fill_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] FILL DATA %H" + , $time, lce_id_i + , lce_fill_data_i + ); + end + + // Fill from LCE + if (lce_fill_o_v_i & lce_fill_o_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] FILL OUT dst[%0d] addr[%H] CCE[%0d] msg[%b] set[%0d] way[%0d] state[%b] size[%b]" + , $time, lce_id_i, lce_fill_o_header_cast_i.payload.dst_id, lce_fill_o_header_cast_i.addr + , lce_fill_o_header_cast_i.payload.src_id, lce_fill_o_header_cast_i.msg_type.fill + , lce_fill_o_header_cast_i.addr[block_offset_bits_lp+:lg_sets_lp] + , lce_fill_o_header_cast_i.payload.way_id, lce_fill_o_header_cast_i.payload.state + , lce_fill_o_header_cast_i.size + ); + end + if (lce_fill_o_v_i & lce_fill_o_ready_and_i) begin + $fdisplay(file, "%12t |: LCE[%0d] FILL OUT DATA %H" + , $time, lce_id_i + , lce_fill_o_data_i + ); + end + + + if (cache_req_last_i) begin + cnt_up <= 1'b0; + $fdisplay(file, "%12t |: LCE[%0d] ReqLat: %d", $time, lce_id_i, req_cnt); + end + + end // ~reset_i + end // always_ff + +endmodule diff --git a/designs/black-parrot/src/bp/bp_me_nonsynth_pkg.sv b/designs/black-parrot/src/bp/bp_me_nonsynth_pkg.sv new file mode 100644 index 0000000..841c408 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_nonsynth_pkg.sv @@ -0,0 +1,50 @@ +/** + * Name: + * + * bp_me_nonsynth_pkg.svh + * + * Description: + */ + +package bp_me_nonsynth_pkg; + + // bits: 3 = store/load + // 2 = unsigned/signed + // 1:0 = size (1, 2, 4, 8 bytes) + typedef enum logic [3:0] { + + e_opcode_lbu = 4'b0100 // load byte unsigned + ,e_opcode_lhu = 4'b0101 // load half unsigned + ,e_opcode_lwu = 4'b0110 // load word unsigned + + ,e_opcode_lb = 4'b0000 // load byte + ,e_opcode_lh = 4'b0001 // load half + ,e_opcode_lw = 4'b0010 // load word + ,e_opcode_ld = 4'b0011 // load double + + ,e_opcode_sb = 4'b1000 // store byte + ,e_opcode_sh = 4'b1001 // store half + ,e_opcode_sw = 4'b1010 // store word + ,e_opcode_sd = 4'b1011 // store double + + // TODO: LR/SC not yet supported in nonsynth cache + //,e_opcode_lrw = 4'b0111 // load reserved word + //,e_opcode_scw = 4'b1100 // store conditional word + + //,e_opcode_lrd = 4'b1101 // load reserved double + //,e_opcode_scd = 4'b1110 // store conditional double + + } bp_me_nonsynth_opcode_e; + + `define declare_bp_me_nonsynth_tr_pkt_s(addr_width_mp, data_width_mp) \ + typedef struct packed { \ + bp_me_nonsynth_opcode_e cmd; \ + logic [addr_width_mp-1:0] paddr; \ + logic uncached; \ + logic [data_width_mp-1:0] data; \ + } bp_me_nonsynth_tr_pkt_s; + + `define bp_me_nonsynth_tr_pkt_width(addr_width_mp, data_width_mp) \ + ($bits(bp_me_nonsynth_opcode_e)+addr_width_mp+1+data_width_mp) + +endpackage diff --git a/designs/black-parrot/src/bp/bp_me_pkg.sv b/designs/black-parrot/src/bp/bp_me_pkg.sv new file mode 100644 index 0000000..f19c88a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_pkg.sv @@ -0,0 +1,18 @@ +/* + * bp_me_pkg.svh + * + * Contains the interface structures used for communicating between the CCE and Memory. + * + */ + + `include "bp_me_defines.svh" + +package bp_me_pkg; + + import bp_common_pkg::*; + + `include "bp_me_cce_pkgdef.svh" + `include "bp_me_cce_inst_pkgdef.svh" + +endpackage + diff --git a/designs/black-parrot/src/bp/bp_me_stream_gearbox.sv b/designs/black-parrot/src/bp/bp_me_stream_gearbox.sv new file mode 100644 index 0000000..4227671 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_stream_gearbox.sv @@ -0,0 +1,127 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_stream_gearbox + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(in_data_width_p) + , parameter `BSG_INV_PARAM(out_data_width_p) + , parameter `BSG_INV_PARAM(payload_width_p) + , parameter `BSG_INV_PARAM(stream_mask_p) + `declare_bp_bedrock_generic_if_width(paddr_width_p, payload_width_p, xce) + ) + (input clk_i + , input reset_i + + , input [xce_header_width_lp-1:0] msg_header_i + , input [in_data_width_p-1:0] msg_data_i + , input msg_v_i + , output logic msg_ready_and_o + + , output logic [xce_header_width_lp-1:0] msg_header_o + , output logic [out_data_width_p-1:0] msg_data_o + , output logic msg_v_o + , input msg_ready_param_i + ); + + `declare_bp_bedrock_generic_if(paddr_width_p, payload_width_p, xce); + `bp_cast_i(bp_bedrock_xce_header_s, msg_header); + `bp_cast_o(bp_bedrock_xce_header_s, msg_header); + + bp_bedrock_xce_header_s msg_header_li; + logic [in_data_width_p-1:0] msg_data_li; + logic msg_v_li, msg_ready_and_lo; + + bsg_two_fifo + #(.width_p($bits(bp_bedrock_xce_header_s)+in_data_width_p)) + fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i({msg_header_cast_i, msg_data_i}) + ,.v_i(msg_v_i) + ,.ready_param_o(msg_ready_and_o) + + ,.data_o({msg_header_li, msg_data_li}) + ,.v_o(msg_v_li) + ,.yumi_i(msg_ready_and_lo & msg_v_li) + ); + + // Header passes right through + assign msg_header_cast_o = msg_header_li; + + if (in_data_width_p < out_data_width_p) + begin : widen + localparam in_max_len_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_128), in_data_width_p); + logic [in_max_len_lp-1:0] in_len_lo; + bp_bedrock_size_to_len + #(.beat_width_p(in_data_width_p), .len_width_p(in_max_len_lp)) + in_s2l + (.size_i(msg_header_li.size), .len_o(in_len_lo)); + + localparam sipop_els_lp = out_data_width_p / in_data_width_p; + wire full_sipop = in_len_lo >= sipop_els_lp; + wire empty_sipop = !stream_mask_p[msg_header_li.msg_type]; + wire [`BSG_SAFE_CLOG2(sipop_els_lp)-1:0] sipop_len_li = + empty_sipop ? '0 : full_sipop ? '1 : in_len_lo; + bsg_serial_in_parallel_out_passthrough_dynamic + #(.width_p(in_data_width_p), .els_p(sipop_els_lp)) + sipop + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(msg_data_li) + ,.v_i(msg_v_li) + ,.len_i(sipop_len_li) + ,.ready_and_o(msg_ready_and_lo) + + ,.data_o(msg_data_o) + ,.v_o(msg_v_o) + ,.ready_and_i(msg_ready_param_i) + ); + end + else if (in_data_width_p > out_data_width_p) + begin : narrow + localparam out_max_len_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_128), out_data_width_p); + logic [out_max_len_lp-1:0] out_len_lo; + bp_bedrock_size_to_len + #(.beat_width_p(out_data_width_p), .len_width_p(out_max_len_lp)) + out_s2l + (.size_i(msg_header_li.size), .len_o(out_len_lo)); + + localparam pisop_els_lp = in_data_width_p / out_data_width_p; + wire full_pisop = out_len_lo >= pisop_els_lp; + wire empty_pisop = !stream_mask_p[msg_header_li.msg_type]; + wire [`BSG_SAFE_CLOG2(pisop_els_lp)-1:0] pisop_len_li = + empty_pisop ? '0 : full_pisop ? '1 : out_len_lo; + bsg_parallel_in_serial_out_passthrough_dynamic + #(.width_p(out_data_width_p), .els_p(pisop_els_lp)) + pisop + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(msg_data_li) + ,.v_i(msg_v_li) + ,.len_i(pisop_len_li) + ,.ready_and_o(msg_ready_and_lo) + + ,.data_o(msg_data_o) + ,.v_o(msg_v_o) + ,.ready_and_i(msg_ready_param_i) + ); + end + else + begin + assign msg_data_o = msg_data_li; + assign msg_v_o = msg_v_li; + assign msg_ready_and_lo = msg_ready_param_i; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_stream_gearbox) + diff --git a/designs/black-parrot/src/bp/bp_me_stream_pump.sv b/designs/black-parrot/src/bp/bp_me_stream_pump.sv new file mode 100644 index 0000000..1e60246 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_stream_pump.sv @@ -0,0 +1,156 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_stream_pump + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(in_data_width_p) + , parameter `BSG_INV_PARAM(in_payload_width_p) + + , parameter `BSG_INV_PARAM(in_msg_stream_mask_p) + , parameter `BSG_INV_PARAM(in_fsm_stream_mask_p) + + , parameter `BSG_INV_PARAM(out_data_width_p) + , parameter `BSG_INV_PARAM(out_payload_width_p) + + , parameter `BSG_INV_PARAM(out_msg_stream_mask_p) + , parameter `BSG_INV_PARAM(out_fsm_stream_mask_p) + + , parameter `BSG_INV_PARAM(metadata_fifo_width_p) + , parameter `BSG_INV_PARAM(metadata_fifo_els_p) + + `declare_bp_bedrock_generic_if_width(paddr_width_p, in_payload_width_p, in) + `declare_bp_bedrock_generic_if_width(paddr_width_p, out_payload_width_p, out) + ) + (input clk_i + , input reset_i + + // Input + , input [in_header_width_lp-1:0] in_msg_header_i + , input [bedrock_fill_width_p-1:0] in_msg_data_i + , input in_msg_v_i + , output logic in_msg_ready_and_o + + , output logic [in_header_width_lp-1:0] in_fsm_header_o + , output logic [in_data_width_p-1:0] in_fsm_data_o + , output logic in_fsm_v_o + , input in_fsm_yumi_i + + , input [metadata_fifo_width_p-1:0] in_fsm_metadata_i + , output logic [paddr_width_p-1:0] in_fsm_addr_o + , output logic in_fsm_new_o + , output logic in_fsm_critical_o + , output logic in_fsm_last_o + + , output logic [out_header_width_lp-1:0] out_msg_header_o + , output logic [bedrock_fill_width_p-1:0] out_msg_data_o + , output logic out_msg_v_o + , input out_msg_ready_and_i + + , input [out_header_width_lp-1:0] out_fsm_header_i + , input [out_data_width_p-1:0] out_fsm_data_i + , input out_fsm_v_i + , output logic out_fsm_ready_then_o + + , output logic [metadata_fifo_width_p-1:0] out_fsm_metadata_o + , output logic [paddr_width_p-1:0] out_fsm_addr_o + , output logic out_fsm_new_o + , output logic out_fsm_last_o + , output logic out_fsm_critical_o + ); + + logic in_fsm_v_lo, in_fsm_yumi_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(in_data_width_p) + ,.payload_width_p(in_payload_width_p) + ,.msg_stream_mask_p(in_msg_stream_mask_p) + ,.fsm_stream_mask_p(in_fsm_stream_mask_p) + ) + in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(in_msg_header_i) + ,.msg_data_i(in_msg_data_i) + ,.msg_v_i(in_msg_v_i) + ,.msg_ready_and_o(in_msg_ready_and_o) + + ,.fsm_header_o(in_fsm_header_o) + ,.fsm_data_o(in_fsm_data_o) + ,.fsm_v_o(in_fsm_v_lo) + ,.fsm_yumi_i(in_fsm_yumi_li) + ,.fsm_addr_o(in_fsm_addr_o) + ,.fsm_new_o(in_fsm_new_o) + ,.fsm_critical_o(in_fsm_critical_o) + ,.fsm_last_o(in_fsm_last_o) + ); + + logic out_fsm_ready_then_lo, out_fsm_v_li; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(out_data_width_p) + ,.payload_width_p(out_payload_width_p) + ,.msg_stream_mask_p(out_msg_stream_mask_p) + ,.fsm_stream_mask_p(out_fsm_stream_mask_p) + ) + out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(out_msg_header_o) + ,.msg_data_o(out_msg_data_o) + ,.msg_v_o(out_msg_v_o) + ,.msg_ready_and_i(out_msg_ready_and_i) + + ,.fsm_header_i(out_fsm_header_i) + ,.fsm_data_i(out_fsm_data_i) + ,.fsm_v_i(out_fsm_v_li) + ,.fsm_ready_then_o(out_fsm_ready_then_lo) + ,.fsm_addr_o(out_fsm_addr_o) + ,.fsm_new_o(out_fsm_new_o) + ,.fsm_critical_o(out_fsm_critical_o) + ,.fsm_last_o(out_fsm_last_o) + ); + + logic [metadata_fifo_width_p-1:0] stream_fifo_data_li; + logic stream_fifo_ready_then_lo, stream_fifo_v_li; + logic [metadata_fifo_width_p-1:0] stream_fifo_data_lo; + logic stream_fifo_v_lo, stream_fifo_yumi_li; + bsg_fifo_1r1w_small + #(.width_p(metadata_fifo_width_p) + ,.els_p(metadata_fifo_els_p) + ,.ready_THEN_valid_p(1) + ) + stream_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(stream_fifo_data_li) + ,.v_i(stream_fifo_v_li) + ,.ready_param_o(stream_fifo_ready_then_lo) + + ,.data_o(stream_fifo_data_lo) + ,.v_o(stream_fifo_v_lo) + ,.yumi_i(stream_fifo_yumi_li) + ); + + // Handshakes + assign in_fsm_v_o = in_fsm_v_lo & stream_fifo_ready_then_lo; + assign in_fsm_yumi_li = in_fsm_yumi_i; + + assign stream_fifo_data_li = in_fsm_metadata_i; + assign stream_fifo_v_li = in_fsm_yumi_i & in_fsm_new_o; + + assign out_fsm_metadata_o = stream_fifo_data_lo; + assign out_fsm_ready_then_o = out_fsm_ready_then_lo & stream_fifo_v_lo; + assign out_fsm_v_li = out_fsm_v_i; + + assign stream_fifo_yumi_li = out_fsm_v_i & out_fsm_last_o; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_me_stream_pump_control.sv b/designs/black-parrot/src/bp/bp_me_stream_pump_control.sv new file mode 100644 index 0000000..ce07639 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_stream_pump_control.sv @@ -0,0 +1,186 @@ +/** + * + * Name: + * bp_me_stream_pump_control.sv + * + * Description: + * Generates the stream word/cnt portion of a BedRock Stream protocol message address given + * an initial stream word and transaction size in stream words (both zero-based). + * + * size_li is the zero-based transaction size (e.g., a transaction of 4 stream words has size_li = 3) + * - size_li+1 should be a power of two + * + * wrap_o is a count that wraps around at the end of the naturally aligned sub-block with + * size size_li targeted by the transaction. wrap_o is typically used directed in the stream + * message address. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_stream_pump_control + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + , parameter `BSG_INV_PARAM(payload_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(stream_mask_p) + , parameter `BSG_INV_PARAM(widest_beat_size_p) + `declare_bp_bedrock_generic_if_width(paddr_width_p, payload_width_p, xce) + ) + (input clk_i + , input reset_i + + // Move to next beat + , input [xce_header_width_lp-1:0] header_i + , input ack_i + + // wrap-around count, used to construct proper stream beat address + // wraps within sub-block aligned portion of block targeted by request + , output logic [paddr_width_p-1:0] addr_o + , output logic first_o + , output logic critical_o + , output logic last_o + ); + + `declare_bp_bedrock_generic_if(paddr_width_p, payload_width_p, xce); + `bp_cast_i(bp_bedrock_xce_header_s, header); + + localparam bytes_lp = data_width_p >> 3; + localparam width_lp = `BSG_SAFE_CLOG2(bedrock_block_width_p/data_width_p); + localparam offset_width_lp = `BSG_SAFE_CLOG2(bytes_lp); + wire [$bits(bp_bedrock_msg_size_e)-1:0] beat_size = `BSG_SAFE_CLOG2(bytes_lp); + + if (bedrock_block_width_p == data_width_p) + begin : z + assign addr_o = header_cast_i.addr; + assign first_o = 1'b1; + assign critical_o = 1'b1; + assign last_o = 1'b1; + end + else + begin : nz + enum logic {e_ready, e_stream} state_n, state_r; + wire is_ready = (state_r == e_ready); + wire is_stream = (state_r == e_stream); + + wire [width_lp-1:0] stream_size = + `BSG_MAX((1'b1 << header_cast_i.size) / bytes_lp, 1'b1) - 1'b1; + wire stream = stream_mask_p[header_cast_i.msg_type]; + wire [width_lp-1:0] size_li = stream ? stream_size : '0; + wire [paddr_width_p-1:0] req_mask = ~((1'b1 << header_cast_i.size) - 1'b1); + wire [paddr_width_p-1:0] max_mask = ~((1'b1 << widest_beat_size_p) - 1'b1); + wire [paddr_width_p-1:0] addr_mask = `BSG_MAX(req_mask, max_mask); + wire [paddr_width_p-1:0] beat_mask = ~((1'b1 << beat_size) - 1'b1); + wire [paddr_width_p-1:0] final_mask = `BSG_MAX(addr_mask, beat_mask); + + wire [paddr_width_p-1:0] base_addr = header_cast_i.addr & addr_mask; + wire [paddr_width_p-1:0] critical_addr = header_cast_i.addr & beat_mask; + + wire [width_lp-1:0] first_cnt = base_addr[offset_width_lp+:width_lp]; + wire [width_lp-1:0] critical_cnt = critical_addr[offset_width_lp+:width_lp]; + wire [width_lp-1:0] last_cnt = first_cnt + size_li; + + logic [width_lp-1:0] cnt_r; + wire [width_lp-1:0] cnt_val_li = first_cnt + ack_i; + bsg_counter_set_en + #(.max_val_p(2**width_lp-1), .reset_val_p('0)) + counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.set_i(is_ready) + ,.en_i(ack_i) + ,.val_i(cnt_val_li) + ,.count_o(cnt_r) + ); + wire [width_lp-1:0] cnt_lo = is_ready ? first_cnt : cnt_r; + + assign first_o = is_ready; + assign critical_o = (critical_cnt == cnt_lo); + assign last_o = (last_cnt == cnt_lo); + + // Dynamically generate sub-block wrapped stream count + // The count is wrapped within the size_li aligned portion of the block containing first_cnt + // + // A canonical block address can be viewed as: + // __________________________________________________________ + // | | block offset | block address + // | upper address |________________________________________| + // | | stream count | stream offset | stream word address + // |________________|____________________|___________________| + // where stream offset is a byte offset of the current stream word and stream count is + // the current stream word portion of the block, having width = stream data channel width + // + // stream count is further divided into: + // __________________________________________________ + // | sub-block number | sub-block count | + // |_________________________|_______________________| + // + // To produce wrap_o, which is the sub-block aligned and wrapped count, the sub-block number + // field is held constant while sub-block count comes from the counter. The number of bits + // derived from the counter versus the initial stream word input (first_cnt) is determined by + // the transaction size (size_li) input. + // + // For example, consider a system with max_val_p = 7 (8 stream words per block), where a block + // comprises stream words [7, 6, 5, 4, 3, 2, 1, 0], listed most to least significant. + // An exampe system like this could have 512 bit blocks with a stream data width of 64 bits. + // 3 bits = log2(512/64) are required for the stream count. The transaction size (size_li) + // determines how many bits are used from first_cnt and cnt_r to produce wrap_o. + + // E.g., max_val_p = 7 for a system with 512-bit blocks and 64-bit stream data width + // A 512-bit transaction sets size_li = 7 and a 256-bit transactions sets size_li = 3 + // 512-bit, size_li = 7, first_cnt = 2: wrap_o = 2, 3, 4, 5, 6, 7, 0, 1 + // 256-bit, size_li = 3, first_cnt = 2: wrap_o = 2, 3, 0, 1 + // 512-bit, size_li = 7, first_cnt = 6: wrap_o = 6, 7, 0, 1, 2, 3, 4, 5 + // 256-bit, size_li = 3, first_cnt = 6: wrap_o = 6, 7, 4, 5 + + // if size_li+1 is not a power of two, the transaction wraps as if size_li+1 is the next + // power of two (e.g., max_val_p = 3, then size_li = 2 wraps same as size_li = 3) + + // selection input used to pick bits from block-wrapped and sub-block wrapped counts + logic [width_lp-1:0] wrap_sel_li; + for (genvar i = 0; i < width_lp; i++) + begin : cnt_sel + assign wrap_sel_li[i] = size_li >= 2**i; + end + + // sub-block wrapped and aligned count (stream word) + logic [width_lp-1:0] wrap_lo; + bsg_mux_bitwise + #(.width_p(width_lp)) + wrap_mux + (.data0_i(first_cnt) + ,.data1_i(cnt_lo) + ,.sel_i(wrap_sel_li) + ,.data_o(wrap_lo) + ); + + localparam block_offset_width_lp = `BSG_SAFE_CLOG2(bedrock_block_width_p >> 3); + wire [`BSG_SAFE_MINUS(width_lp,1):0] wrap_cnt = is_ready ? first_cnt : wrap_lo; + wire [paddr_width_p-1:block_offset_width_lp] high_bits = + header_cast_i.addr[paddr_width_p-1:block_offset_width_lp]; + wire [offset_width_lp-1:0] low_bits = header_cast_i.addr[0+:offset_width_lp]; + + assign addr_o = {high_bits, {bedrock_block_width_p>data_width_p{wrap_cnt}}, low_bits} & final_mask; + + always_comb + case (state_r) + e_stream: state_n = (ack_i & last_o) ? e_ready : e_stream; + default : state_n = (ack_i & ~last_o) ? e_stream : e_ready; + endcase + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_ready; + else + state_r <= state_n; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_stream_pump_control) + diff --git a/designs/black-parrot/src/bp/bp_me_stream_pump_in.sv b/designs/black-parrot/src/bp/bp_me_stream_pump_in.sv new file mode 100644 index 0000000..c3f01b5 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_stream_pump_in.sv @@ -0,0 +1,164 @@ +/** + * + * Name: + * bp_me_stream_pump_in.sv + * + * Description: + * Provides an FSM with control signals for an inbound BedRock Stream interface. + * This module buffers the inbound BedRock Stream channel and exposes it to the FSM. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_stream_pump_in + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(data_width_p) + // width of BedRock message payload + , parameter `BSG_INV_PARAM(payload_width_p) + + // Bitmasks that specify which message types may have multiple beats on either + // the msg input side or FSM output side. + // Each mask is constructed as (1 << e_rd/wr_msg | 1 << e_uc_rd/wr_msg) + // There are three cases: + // 1. Message types that are set in msg_stream_mask_p but not in + // fsm_stream_mask_p will result in N:1 conversion from msg->FSM ports. + // This is rarely used. + // 2. Message types that are set as part of fsm_stream_mask_p but not set in + // msg_stream_mask_p result in a 1:N conversion from msg->FSM ports. + // For example, in BlackParrot a read command for 64B to the + // cache arriving on the BedRock Stream input can be decomposed into a stream of + // 8B reads on the FSM output port. + // 3. Message types set in both will have N:N beats. Every beat on the input + // will produce a beat on the output. This is commonly used for all messages + // with data payloads. + // Constructed as (1 << e_rd/wr_msg | 1 << e_uc_rd/wr_msg) + , parameter `BSG_INV_PARAM(msg_stream_mask_p) + , parameter `BSG_INV_PARAM(fsm_stream_mask_p) + + `declare_bp_bedrock_generic_if_width(paddr_width_p, payload_width_p, xce) + ) + (input clk_i + , input reset_i + + // Input BedRock Stream + , input [xce_header_width_lp-1:0] msg_header_i + , input [bedrock_fill_width_p-1:0] msg_data_i + , input msg_v_i + , output logic msg_ready_and_o + + // FSM consumer side + , output logic [xce_header_width_lp-1:0] fsm_header_o + , output logic [data_width_p-1:0] fsm_data_o + , output logic fsm_v_o + , input fsm_yumi_i + // FSM control signals + // fsm_addr is the effective address of the beat + , output logic [paddr_width_p-1:0] fsm_addr_o + // fsm_new is raised when first beat of every message is acked + , output logic fsm_new_o + // fsm_critical is raised on the critical beat of every message + , output logic fsm_critical_o + // fsm_last is raised on last beat of every message + , output logic fsm_last_o + ); + + `declare_bp_bedrock_generic_if(paddr_width_p, payload_width_p, xce); + `bp_cast_i(bp_bedrock_xce_header_s, msg_header); + `bp_cast_o(bp_bedrock_xce_header_s, fsm_header); + + localparam fsm_bytes_lp = data_width_p >> 3; + localparam fsm_words_lp = bedrock_block_width_p / data_width_p; + localparam fsm_cnt_width_lp = `BSG_SAFE_CLOG2(fsm_words_lp); + + bp_bedrock_xce_header_s msg_header_li; + logic [data_width_p-1:0] msg_data_li; + logic msg_v_li, msg_yumi_lo; + bp_me_stream_gearbox + #(.bp_params_p(bp_params_p) + ,.in_data_width_p(bedrock_fill_width_p) + ,.out_data_width_p(data_width_p) + ,.payload_width_p(payload_width_p) + ,.stream_mask_p(msg_stream_mask_p) + ) + gearbox + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(msg_header_cast_i) + ,.msg_data_i(msg_data_i) + ,.msg_v_i(msg_v_i) + ,.msg_ready_and_o(msg_ready_and_o) + + ,.msg_header_o(msg_header_li) + ,.msg_data_o(msg_data_li) + ,.msg_v_o(msg_v_li) + ,.msg_ready_param_i(msg_yumi_lo) + ); + + wire [fsm_cnt_width_lp-1:0] stream_size = + `BSG_MAX((1'b1 << msg_header_li.size) / fsm_bytes_lp, 1'b1) - 1'b1; + wire nz_stream = stream_size > '0; + wire fsm_stream = fsm_stream_mask_p[msg_header_li.msg_type]; + wire msg_stream = msg_stream_mask_p[msg_header_li.msg_type]; + // TODO: This could be dynamically adjusted depending on target + localparam widest_beat_width_lp = + `BSG_MAX(icache_fill_width_p, `BSG_MAX(dcache_fill_width_p, bedrock_fill_width_p)); + localparam widest_beat_size_lp = `BSG_SAFE_CLOG2(widest_beat_width_lp)-1; + + logic cnt_up; + bp_me_stream_pump_control + #(.bp_params_p(bp_params_p) + ,.stream_mask_p(fsm_stream_mask_p) + ,.data_width_p(data_width_p) + ,.payload_width_p(payload_width_p) + ,.widest_beat_size_p(widest_beat_size_lp) + ) + pump_control + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.header_i(fsm_header_cast_o) + ,.ack_i(cnt_up) + + ,.addr_o(fsm_addr_o) + ,.first_o(fsm_new_o) + ,.last_o(fsm_last_o) + ,.critical_o(fsm_critical_o) + ); + + assign fsm_header_cast_o = msg_header_li; + assign fsm_data_o = msg_data_li; + + always_comb + if (~msg_stream & fsm_stream & nz_stream) + begin + // 1:N + // convert one msg message into stream of N FSM messages + fsm_v_o = msg_v_li; + msg_yumi_lo = fsm_last_o & fsm_yumi_i; + cnt_up = fsm_yumi_i; + end + else + begin + // 1:1 + fsm_v_o = msg_v_li; + msg_yumi_lo = fsm_yumi_i; + cnt_up = fsm_yumi_i; + end + + // parameter checks + if (bedrock_block_width_p % data_width_p != 0) + $error("bedrock_block_width_p must be evenly divisible by data_width_p"); + if (bedrock_block_width_p < data_width_p) + $error("bedrock_block_width_p must be at least as large as data_width_p"); + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_stream_pump_in) + diff --git a/designs/black-parrot/src/bp/bp_me_stream_pump_out.sv b/designs/black-parrot/src/bp/bp_me_stream_pump_out.sv new file mode 100644 index 0000000..03fba5a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_stream_pump_out.sv @@ -0,0 +1,164 @@ +/** + * + * Name: + * bp_me_stream_pump_out.sv + * + * Description: + * Generates a BedRock Stream protocol output message from an FSM that provides + * a base header and, if required, data words. The base header is held constant + * by the FSM throughout the transaction. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_stream_pump_out + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(data_width_p) + // width of BedRock message payload + , parameter `BSG_INV_PARAM(payload_width_p) + + // Bitmasks that specify which message types may have multiple beats on either + // the FSM input side or msg output side. + // Each mask is constructed as (1 << e_rd/wr_msg | 1 << e_uc_rd/wr_msg) + // There are three cases: + // 1. Message types that are set in msg_stream_mask_p but not in + // fsm_stream_mask_p will result in 1:N conversion from FSM->msg ports. + // 2. Message types that are set as part of fsm_stream_mask_p but not set in + // msg_stream_mask_p result in a N:1 conversion from FSM->msg ports. + // 3. Message types set in both will have N:N beats. Every beat on the input + // will produce a beat on the output. This is commonly used for all messages + // with data payloads. + // Constructed as (1 << e_rd/wr_msg | 1 << e_uc_rd/wr_msg) + , parameter `BSG_INV_PARAM(msg_stream_mask_p) + , parameter `BSG_INV_PARAM(fsm_stream_mask_p) + + `declare_bp_bedrock_generic_if_width(paddr_width_p, payload_width_p, xce) + ) + (input clk_i + , input reset_i + + // Output BedRock Stream + , output logic [xce_header_width_lp-1:0] msg_header_o + , output logic [bedrock_fill_width_p-1:0] msg_data_o + , output logic msg_v_o + , input msg_ready_and_i + + // FSM producer side + // FSM must hold fsm_header_i constant throughout the transaction + // (i.e., through cycle fsm_last_o is raised) + , input [xce_header_width_lp-1:0] fsm_header_i + , input [data_width_p-1:0] fsm_data_i + , input fsm_v_i + , output logic fsm_ready_then_o + + // FSM control signals + // fsm_addr is the effective address of the beat + , output logic [paddr_width_p-1:0] fsm_addr_o + // fsm_new is raised when first beat of every message is acked + , output logic fsm_new_o + // fsm_last is raised on last beat of every message + , output logic fsm_last_o + // fsm_critical is raised on critical beat of every message + , output logic fsm_critical_o + ); + + `declare_bp_bedrock_generic_if(paddr_width_p, payload_width_p, xce); + `bp_cast_i(bp_bedrock_xce_header_s, fsm_header); + `bp_cast_o(bp_bedrock_xce_header_s, msg_header); + + localparam fsm_bytes_lp = data_width_p >> 3; + localparam fsm_words_lp = bedrock_block_width_p / data_width_p; + localparam fsm_cnt_width_lp = `BSG_SAFE_CLOG2(fsm_words_lp); + + bp_bedrock_xce_header_s msg_header_lo; + logic [data_width_p-1:0] msg_data_lo; + logic msg_v_lo, msg_ready_and_li; + bp_me_stream_gearbox + #(.bp_params_p(bp_params_p) + ,.in_data_width_p(data_width_p) + ,.out_data_width_p(bedrock_fill_width_p) + ,.payload_width_p(payload_width_p) + ,.stream_mask_p(msg_stream_mask_p) + ) + gearbox + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(msg_header_lo) + ,.msg_data_i(msg_data_lo) + ,.msg_v_i(msg_v_lo) + ,.msg_ready_and_o(msg_ready_and_li) + + ,.msg_header_o(msg_header_cast_o) + ,.msg_data_o(msg_data_o) + ,.msg_v_o(msg_v_o) + ,.msg_ready_param_i(msg_ready_and_i) + ); + + wire [fsm_cnt_width_lp-1:0] stream_size = + `BSG_MAX((1'b1 << fsm_header_cast_i.size) / fsm_bytes_lp, 1'b1) - 1'b1; + wire nz_stream = stream_size > '0; + wire fsm_stream = fsm_stream_mask_p[fsm_header_cast_i.msg_type]; + wire msg_stream = msg_stream_mask_p[fsm_header_cast_i.msg_type]; + + // TODO: This could be dynamically adjusted depending on target + localparam widest_beat_width_lp = + `BSG_MAX(icache_fill_width_p, `BSG_MAX(dcache_fill_width_p, bedrock_fill_width_p)); + localparam widest_beat_size_lp = `BSG_SAFE_CLOG2(widest_beat_width_lp)-1; + logic cnt_up; + bp_me_stream_pump_control + #(.bp_params_p(bp_params_p) + ,.stream_mask_p(fsm_stream_mask_p) + ,.data_width_p(data_width_p) + ,.payload_width_p(payload_width_p) + ,.widest_beat_size_p(widest_beat_size_lp) + ) + pump_control + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.header_i(fsm_header_cast_i) + ,.ack_i(cnt_up) + + ,.addr_o(fsm_addr_o) + ,.first_o(fsm_new_o) + ,.last_o(fsm_last_o) + ,.critical_o(fsm_critical_o) + ); + + assign msg_header_lo = fsm_header_cast_i; + assign msg_data_lo = fsm_data_i; + + always_comb + if (fsm_stream & ~msg_stream & nz_stream) + begin + // N:1 + // ack all but first FSM beat silently + fsm_ready_then_o = msg_ready_and_li; + msg_v_lo = fsm_v_i & fsm_new_o; + cnt_up = fsm_v_i; + end + else + begin + // 1:1 + fsm_ready_then_o = msg_ready_and_li; + msg_v_lo = fsm_v_i; + cnt_up = msg_v_lo; + end + + // parameter checks + if (bedrock_block_width_p % data_width_p != 0) + $error("bedrock_block_width_p must be evenly divisible by data_width_p"); + if (bedrock_block_width_p < data_width_p) + $error("bedrock_block_width_p must be at least as large as data_width_p"); + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_stream_pump_out) + diff --git a/designs/black-parrot/src/bp/bp_me_stream_to_wormhole.sv b/designs/black-parrot/src/bp/bp_me_stream_to_wormhole.sv new file mode 100644 index 0000000..0ea9a36 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_stream_to_wormhole.sv @@ -0,0 +1,193 @@ +/** + * + * Name: + * bp_me_stream_to_wormhole.sv + * + * Description: + * Converts BedRock Burst protocol to wormhole router stream. + * The data width of the BedRock Burst protocol is first gearboxed to match the + * wormhole network flit width. + * + * Assumptions: + * Usage of this module requires correctly formed wormhole headers. The length + * field of the wormhole message determines how many protocol data beats are + * expected (some multiple or divisor of the flit_width). We expect most + * link and protocol data width to be powers of 2 (32, 64, 512), so this + * length restriction is lenient. + * + * - data width is a multiple of flit width (would be easy to add support) + * - header width is a multiple of flit width (would be more challenging) + * - header width == wormhole header width + protocol header width + * - wormhole packets are laid out like the following: + * ---------------------------------------------------------------- + * | data | data | data | data | pad pr_hdr cid len cord | + * ---------------------------------------------------------------- + * - header flits do not contain any data + * - the example above shows the entire header in a single flit, but it + * may require more than one wormhole link flits if pr_hdr length + * is greater than flit_width - cord_width - len_width - cid_width + * + * Input Burst message has a single header beat and zero or more data beats. + * This module does not accept data until the header sends. + * Header must be formatted for wormhole network as shown above. + * + */ + +`include "bsg_defines.sv" +`include "bp_common_defines.svh" + +module bp_me_stream_to_wormhole + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + // The wormhole router protocol information + // flit_width_p: number of physical data wires between links + // cord_width_p: the width of the {y,x} coordinate of the destination + // len_width_p : the width of the length field, denoting #flits+1 + // cid_width : the width of the concentrator id of the destination + // Default to 0 for cord and cid, so that this module can be used either + // for concentrator or router + , parameter `BSG_INV_PARAM(flit_width_p) + , parameter `BSG_INV_PARAM(cord_width_p) + , parameter `BSG_INV_PARAM(len_width_p) + , parameter cid_width_p = 0 + + // Higher level protocol information + , parameter `BSG_INV_PARAM(pr_hdr_width_p) + , parameter `BSG_INV_PARAM(pr_payload_width_p) + , parameter `BSG_INV_PARAM(pr_stream_mask_p) + , parameter `BSG_INV_PARAM(pr_data_width_p) + + // Computed wormhole header parameters. These can be overridden directly if desired. + // Size of the wormhole header + the protocol header + , parameter wh_hdr_width_p = cord_width_p + len_width_p + cid_width_p + pr_hdr_width_p + // offset of protocol header in deserialized wormhole header + , parameter wh_pr_hdr_offset_p = (cord_width_p + len_width_p + cid_width_p) + // offset of length field in wormhole header + , parameter wh_len_offset_p = cord_width_p + + // Number of wormhole link flits per wormhole header + , localparam [len_width_p-1:0] hdr_len_lp = `BSG_CDIV(wh_hdr_width_p, flit_width_p) + + // padding in wormhole header + , localparam wh_hdr_pad_lp = (flit_width_p*hdr_len_lp) - wh_hdr_width_p + ) + (input clk_i + , input reset_i + + // BedRock Burst input channel + // ready&valid + , input [pr_hdr_width_p-1:0] pr_hdr_i + , input [pr_data_width_p-1:0] pr_data_i + , input pr_v_i + , output logic pr_ready_and_o + , input [cord_width_p-1:0] dst_cord_i + , input [cid_width_p-1:0] dst_cid_i + + // Wormhole output + // ready&valid + , output logic [flit_width_p-1:0] link_data_o + , output logic link_v_o + , input link_ready_and_i + ); + + // parameter checks + if (!(`BSG_IS_POW2(pr_data_width_p)) || !(`BSG_IS_POW2(flit_width_p))) + $error("Protocol and Network data width must be powers of 2"); + + `declare_bp_bedrock_generic_if(paddr_width_p, pr_payload_width_p, msg); + `bp_cast_i(bp_bedrock_msg_header_s, pr_hdr); + + // WH control signals + logic is_hdr, is_data, wh_has_data, wh_last_data; + + `declare_bp_bedrock_wormhole_header_s(flit_width_p, cord_width_p, len_width_p, cid_width_p, bp_bedrock_msg_header_s, bedrock); + bp_bedrock_wormhole_header_s pr_wh_hdr_lo; + + bp_me_wormhole_header_encode + #(.bp_params_p(bp_params_p) + ,.flit_width_p(flit_width_p) + ,.cord_width_p(cord_width_p) + ,.cid_width_p(cid_width_p) + ,.len_width_p(len_width_p) + ,.payload_width_p(pr_payload_width_p) + ,.stream_mask_p(pr_stream_mask_p) + ) + encode + (.header_i(pr_hdr_cast_i) + ,.dst_cord_i(dst_cord_i) + ,.dst_cid_i(dst_cid_i) + ,.wh_header_o(pr_wh_hdr_lo) + ); + wire [(flit_width_p*hdr_len_lp)-1:0] pr_wh_hdr_padded_li = pr_wh_hdr_lo; + + // Header is input all at once and streamed out 1 flit at a time + logic piso_ready_and_lo, piso_v_li; + logic [flit_width_p-1:0] wh_hdr_lo; + logic wh_hdr_ready_and_li, wh_hdr_v_lo; + assign piso_v_li = is_hdr & pr_v_i; + bsg_parallel_in_serial_out_passthrough + #(.width_p(flit_width_p), .els_p(hdr_len_lp)) + hdr_piso + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(pr_wh_hdr_padded_li) + ,.v_i(piso_v_li) + ,.ready_and_o(piso_ready_and_lo) + + ,.data_o(wh_hdr_lo) + ,.v_o(wh_hdr_v_lo) + ,.ready_and_i(wh_hdr_ready_and_li) + ); + assign wh_hdr_ready_and_li = is_hdr & link_ready_and_i; + + logic [pr_data_width_p-1:0] wh_data_r; + bsg_dff_en + #(.width_p(pr_data_width_p)) + wh_data_reg + (.clk_i(clk_i) + ,.en_i(pr_ready_and_o & pr_v_i) + ,.data_i(pr_data_i) + ,.data_o(wh_data_r) + ); + + logic wh_data_v_r; + bsg_dff_reset_set_clear + #(.width_p(1)) + wh_data_v_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.set_i(pr_ready_and_o & pr_v_i & wh_has_data) + ,.clear_i(link_ready_and_i & link_v_o & is_data) + ,.data_o(wh_data_v_r) + ); + + assign pr_ready_and_o = is_hdr ? piso_ready_and_lo : (~wh_last_data & link_ready_and_i); + + // Identifies which flits are header vs data flits + bp_me_wormhole_stream_control + #(.len_width_p(len_width_p), .hdr_len_p(hdr_len_lp)) + stream_control + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.len_i(pr_wh_hdr_lo[wh_len_offset_p+:len_width_p]) + ,.link_accept_i(link_ready_and_i & link_v_o) + + ,.is_hdr_o(is_hdr) + ,.has_data_o(wh_has_data) + ,.is_data_o(is_data) + ,.last_data_o(wh_last_data) + ); + + // patch header or data flits to link + assign link_data_o = is_hdr ? wh_hdr_lo : wh_data_r; + assign link_v_o = is_hdr ? wh_hdr_v_lo : wh_data_v_r; + + if (flit_width_p != pr_data_width_p) + $error("flit_width_p %d != pr_data_width_p %d", flit_width_p, pr_data_width_p); + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_stream_to_wormhole) + diff --git a/designs/black-parrot/src/bp/bp_me_wormhole_header_encode.sv b/designs/black-parrot/src/bp/bp_me_wormhole_header_encode.sv new file mode 100644 index 0000000..3b8cd1a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_wormhole_header_encode.sv @@ -0,0 +1,100 @@ +/** + * Name: + * bp_me_wormhole_header_encode.sv + * + * Description: + * Generic BedRock to wormhole packet header encoder that takes a generic bedrock header + * as input and forms it into a wormhole packet header. + * + * packet = {payload, cid, length, cord} + */ + +`include "bp_common_defines.svh" + +module bp_me_wormhole_header_encode + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(flit_width_p) + , parameter `BSG_INV_PARAM(cord_width_p) + , parameter `BSG_INV_PARAM(cid_width_p) + , parameter `BSG_INV_PARAM(len_width_p) + , parameter `BSG_INV_PARAM(payload_width_p) + + `declare_bp_bedrock_generic_if_width(paddr_width_p, payload_width_p, msg) + + // Constructed as (1 << e_rd/wr_msg | 1 << e_uc_rd/wr_msg) + , parameter stream_mask_p = 0 + + , localparam wh_header_width_lp = + `bp_bedrock_wormhole_header_width(flit_width_p, cord_width_p, len_width_p, cid_width_p, msg_header_width_lp) + ) + (input [msg_header_width_lp-1:0] header_i + + , input [cord_width_p-1:0] dst_cord_i + , input [cid_width_p-1:0] dst_cid_i + + , output logic [wh_header_width_lp-1:0] wh_header_o + ); + + `declare_bp_bedrock_generic_if(paddr_width_p, payload_width_p, msg); + `bp_cast_i(bp_bedrock_msg_header_s, header); + + `declare_bp_bedrock_wormhole_header_s(flit_width_p, cord_width_p, len_width_p, cid_width_p, bp_bedrock_msg_header_s, bedrock); + `bp_cast_o(bp_bedrock_wormhole_header_s, wh_header); + + // TODO: could leverage bp_bedrock_size_to_len to compute these values + // Pre-compute flits per header and flits per data (zero-based) + localparam msg_hdr_len_lp = `BSG_CDIV(wh_header_width_lp, flit_width_p) - 1; + localparam msg_data_len_1_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_1), flit_width_p) - 1; + localparam msg_data_len_2_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_2), flit_width_p) - 1; + localparam msg_data_len_4_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_4), flit_width_p) - 1; + localparam msg_data_len_8_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_8), flit_width_p) - 1; + localparam msg_data_len_16_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_16), flit_width_p) - 1; + localparam msg_data_len_32_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_32), flit_width_p) - 1; + localparam msg_data_len_64_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_64), flit_width_p) - 1; + localparam msg_data_len_128_lp = `BSG_CDIV(8*(1 << e_bedrock_msg_size_128), flit_width_p) - 1; + // Pre-compute full message flits (hdr + data flits) + // note: need to add back 1 since both hdr and data lengths are zero-based + localparam msg_len_1_lp = msg_data_len_1_lp + msg_hdr_len_lp + 1; + localparam msg_len_2_lp = msg_data_len_2_lp + msg_hdr_len_lp + 1; + localparam msg_len_4_lp = msg_data_len_4_lp + msg_hdr_len_lp + 1; + localparam msg_len_8_lp = msg_data_len_8_lp + msg_hdr_len_lp + 1; + localparam msg_len_16_lp = msg_data_len_16_lp + msg_hdr_len_lp + 1; + localparam msg_len_32_lp = msg_data_len_32_lp + msg_hdr_len_lp + 1; + localparam msg_len_64_lp = msg_data_len_64_lp + msg_hdr_len_lp + 1; + localparam msg_len_128_lp = msg_data_len_128_lp + msg_hdr_len_lp + 1; + + logic [len_width_p-1:0] msg_len_li; + + always_comb + begin + wh_header_cast_o = '0; + + wh_header_cast_o.msg_hdr = header_cast_i; + wh_header_cast_o.rtr_hdr.cord = dst_cord_i; + wh_header_cast_o.rtr_hdr.cid = dst_cid_i; + + unique case (header_cast_i.size) + e_bedrock_msg_size_1 : msg_len_li = len_width_p'(msg_len_1_lp); + e_bedrock_msg_size_2 : msg_len_li = len_width_p'(msg_len_2_lp); + e_bedrock_msg_size_4 : msg_len_li = len_width_p'(msg_len_4_lp); + e_bedrock_msg_size_8 : msg_len_li = len_width_p'(msg_len_8_lp); + e_bedrock_msg_size_16 : msg_len_li = len_width_p'(msg_len_16_lp); + e_bedrock_msg_size_32 : msg_len_li = len_width_p'(msg_len_32_lp); + e_bedrock_msg_size_64 : msg_len_li = len_width_p'(msg_len_64_lp); + e_bedrock_msg_size_128: msg_len_li = len_width_p'(msg_len_128_lp); + default: msg_len_li = '0; + endcase + + if (stream_mask_p[header_cast_i.msg_type]) + wh_header_cast_o.rtr_hdr.len = len_width_p'(msg_len_li); + else + wh_header_cast_o.rtr_hdr.len = len_width_p'(msg_hdr_len_lp); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_wormhole_header_encode) + diff --git a/designs/black-parrot/src/bp/bp_me_wormhole_stream_control.sv b/designs/black-parrot/src/bp/bp_me_wormhole_stream_control.sv new file mode 100644 index 0000000..2acd96b --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_wormhole_stream_control.sv @@ -0,0 +1,149 @@ +/** + * + * Name: + * bp_me_wormhole_stream_control.sv + * + * Description: + * Handles flow control for a bsg_wormhole packet. Given a length of + * wormhole packet and a begin transaction signal, this module tracks which + * flits are header flits and which are data flits. + * + * A bsg_wormhole packet is assumed to be laid out as: + * ---------------------------------------------------------------- + * | data | data | data | data | pad pr_hdr len cord | + * ---------------------------------------------------------------- + * - header flits do not contain any data + * - the example above shows the entire header in a single flit, but it + * may require more than one wormhole link flits if pr_hdr width is + * greater than flit_width - cord_width - len_width. + * In general, a wormhole packet has one or more header flits and zero or + * more data flits. + * + * For this module, all that is required is that the first header flit + * contains the wormhole message length, passed in as len_i. + * + */ + +`include "bsg_defines.sv" + +module bp_me_wormhole_stream_control + #(parameter `BSG_INV_PARAM(len_width_p) + , parameter [len_width_p-1:0] `BSG_INV_PARAM(hdr_len_p) + ) + (input clk_i + , input reset_i + + , input [len_width_p-1:0] len_i + , input link_accept_i + + , output logic is_hdr_o + , output logic has_data_o + , output logic is_data_o + , output logic last_data_o + ); + + enum logic {e_hdr, e_data} state_n, state_r; + wire is_hdr = (state_r == e_hdr); + wire is_data = (state_r == e_data); + + assign is_hdr_o = is_hdr; + assign is_data_o = is_data; + + // Wormhole len is defined to be (num_flits-1), add it back here + wire [len_width_p-1:0] data_len_li = len_i - hdr_len_p + (len_width_p)'(1); + + // count from num_flits to zero, count_r_o==1 means last flit + logic [len_width_p-1:0] hdr_flit_cnt, data_flit_cnt; + + // Sending last hdr flit (single header packets are always good to go) + wire hdr_flit_last = (hdr_flit_cnt == (len_width_p)'(1)) || (hdr_len_p == 1); + // Sending last data flit + wire data_flit_last = (data_flit_cnt == (len_width_p)'(1)); + // All hdr flits are sent + wire hdr_flit_done = (hdr_flit_cnt == '0); + // All data flits are sent + wire data_flit_done = (data_flit_cnt == '0); + + assign last_data_o = is_data & data_flit_last; + + // Set counter value when new packet hdr arrives + // and all hdr flits are sent + // (set data_flit_counter in same cycle) + wire set_counter = is_hdr & hdr_flit_done & link_accept_i; + + bsg_counter_set_down + #(.width_p(len_width_p) + ,.init_val_p(0) + // allow set down same cycle to avoid bubble + ,.set_and_down_exclusive_p(0) + ) + hdr_flit_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.set_i(set_counter) + ,.val_i(hdr_len_p) + ,.down_i(is_hdr & link_accept_i) + ,.count_r_o(hdr_flit_cnt) + ); + + bsg_counter_set_down + #(.width_p(len_width_p) + ,.init_val_p(0) + // allow set down same cycle to avoid bubble + ,.set_and_down_exclusive_p(0) + ) + data_flit_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.set_i(set_counter) + ,.val_i(data_len_li) + ,.down_i(is_data & link_accept_i) + ,.count_r_o(data_flit_cnt) + ); + + wire e_hdr_to_e_data; + + // Single hdr flit + if (hdr_len_p == 1) begin + // When wormhole link accept flit + // and data flit non-zero + // and is_hdr (avoid possible X-pessimism in simulation) + // + // (data_flit_done signal takes one cycle to be registered, not useful + // in this case, extract data_len_li signal directly from hdr) + assign e_hdr_to_e_data = (link_accept_i & is_hdr & data_len_li != '0); + assign has_data_o = (data_len_li != '0); + // Multiple hdr flits + end else begin + // When wormhole link accept flit + // and sending last hdr flit + // and data flit non-zero + // + // (data_len_li signal only meaningful in first hdr flit, not useful + // in this case, use registered data_flit_done signal from data_flit_counter) + assign e_hdr_to_e_data = (link_accept_i & hdr_flit_last & ~data_flit_done); + assign has_data_o = ~data_flit_done; + end + + // When wormhole link accept flit and sending last data flit + wire e_data_to_e_hdr = link_accept_i & data_flit_last; + + always_comb begin + case (state_r) + e_hdr : state_n = (e_hdr_to_e_data) ? e_data : e_hdr; + e_data : state_n = (e_data_to_e_hdr) ? e_hdr : e_data; + default: state_n = e_hdr; + endcase + end + + always_ff @(posedge clk_i) begin + if (reset_i) + state_r <= e_hdr; + else + state_r <= state_n; + end + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_wormhole_stream_control) + diff --git a/designs/black-parrot/src/bp/bp_me_wormhole_to_stream.sv b/designs/black-parrot/src/bp/bp_me_wormhole_to_stream.sv new file mode 100644 index 0000000..ea57d4c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_wormhole_to_stream.sv @@ -0,0 +1,151 @@ +/** + * + * Name: + * bp_me_wormhole_to_stream.sv + * + * Description: + * Converts a wormhole router stream to BedRock Burst protocol without + * deserializing the data. + * + * The data arriving on from the wormhole network is gearboxed to match the + * BedRock protocol data width. + * + * Assumptions: + * Usage of this module requires correctly formed wormhole headers. The length + * field of the wormhole message determines how many protocol data beats are + * expected (some multiple or divisor of the flit_width). We expect most + * link and protocol data width to be powers of 2 (32, 64, 512), so this + * length restriction is lenient. + * + * - data width is a multiple of flit width + * - header width is a multiple of flit width + * - header width == wormhole header width + protocol header width + * - wormhole packets are laid out like the following: + * ---------------------------------------------------------------- + * | data | data | data | data | pad pr_hdr cid len cord | + * ---------------------------------------------------------------- + * - header flits do not contain any data + * - the example above shows the entire header in a single flit, but it + * may require more than one wormhole link flits if pr_hdr length + * is greater than flit_width - cord_width - len_width - cid_width + * + * Burst header is output before data. + * + */ + +`include "bsg_defines.sv" +`include "bp_common_defines.svh" + +module bp_me_wormhole_to_stream + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + // The wormhole router protocol information + // flit_width_p: number of physical data wires between links + // cord_width_p: the width of the {y,x} coordinate of the destination + // len_width_p : the width of the length field, denoting #flits+1 + // cid_width : the width of the concentrator id of the destination + // Default to 0 for cid so that this module can be used either + // for concentrator or router + , parameter `BSG_INV_PARAM(flit_width_p) + , parameter `BSG_INV_PARAM(cord_width_p) + , parameter `BSG_INV_PARAM(len_width_p) + , parameter cid_width_p = 0 + + // Higher level protocol information + , parameter `BSG_INV_PARAM(pr_hdr_width_p) + , parameter `BSG_INV_PARAM(pr_payload_width_p) + , parameter `BSG_INV_PARAM(pr_stream_mask_p) + , parameter `BSG_INV_PARAM(pr_data_width_p) + + // Computed wormhole header parameters. These can be overridden directly if desired. + // Size of the wormhole header + the protocol header + , parameter wh_hdr_width_p = cord_width_p + len_width_p + cid_width_p + pr_hdr_width_p + // offset of protocol header in deserialized wormhole header + , parameter wh_pr_hdr_offset_p = (cord_width_p + len_width_p + cid_width_p) + // offset of length field in wormhole header + , parameter wh_len_offset_p = cord_width_p + + // Number of wormhole link flits per wormhole header + , localparam [len_width_p-1:0] hdr_len_lp = `BSG_CDIV(wh_hdr_width_p, flit_width_p) + ) + (input clk_i + , input reset_i + + // The output of a wormhole network + , input [flit_width_p-1:0] link_data_i + , input link_v_i + , output logic link_ready_and_o + + // BedRock Burst output + , output logic [pr_hdr_width_p-1:0] pr_hdr_o + , output logic [pr_data_width_p-1:0] pr_data_o + , output logic pr_v_o + , input pr_ready_and_i + ); + + `declare_bp_bedrock_generic_if(paddr_width_p, pr_payload_width_p, msg); + `bp_cast_o(bp_bedrock_msg_header_s, pr_hdr); + + // parameter checks + if (!(`BSG_IS_POW2(pr_data_width_p)) || !(`BSG_IS_POW2(flit_width_p))) + $error("Protocol and Network data width must be powers of 2"); + + // WH control signals + logic is_hdr, is_data, wh_has_data, wh_last_data; + + // Header SIPO + // Aggregate flits until we have a full header-worth of data + logic sipo_ready_and_lo, sipo_v_li; + logic [(flit_width_p*hdr_len_lp)-1:0] wh_hdr_lo; + logic pr_hdr_v_lo, pr_hdr_yumi_li; + bsg_serial_in_parallel_out_full + #(.width_p(flit_width_p), .els_p(hdr_len_lp)) + hdr_sipo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(link_data_i) + ,.v_i(sipo_v_li) + ,.ready_and_o(sipo_ready_and_lo) + + ,.data_o(wh_hdr_lo) + ,.v_o(pr_hdr_v_lo) + ,.yumi_i(pr_hdr_yumi_li) + ); + wire pr_has_data_lo = pr_stream_mask_p[pr_hdr_cast_o.msg_type]; + wire pr_last_data_lo = wh_last_data; + assign sipo_v_li = is_hdr & link_v_i; + + assign pr_hdr_cast_o = wh_hdr_lo[wh_pr_hdr_offset_p+:pr_hdr_width_p]; + assign pr_data_o = link_data_i; + assign pr_v_o = is_hdr ? (pr_hdr_v_lo & ~pr_has_data_lo) : link_v_i; + assign pr_hdr_yumi_li = pr_ready_and_i & pr_v_o & (~pr_has_data_lo | pr_last_data_lo); + + assign link_ready_and_o = is_hdr ? sipo_ready_and_lo : pr_ready_and_i; + + // Identifies which flits are header vs data flits + bp_me_wormhole_stream_control + #(.len_width_p(len_width_p) + ,.hdr_len_p(hdr_len_lp) + ) + stream_control + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.len_i(link_data_i[wh_len_offset_p+:len_width_p]) + ,.link_accept_i(link_ready_and_o & link_v_i) + + ,.is_hdr_o(is_hdr) + ,.has_data_o(wh_has_data) + ,.is_data_o(is_data) + ,.last_data_o(wh_last_data) + ); + + if (flit_width_p != pr_data_width_p) + $error("flit_width_p %d != pr_data_width_p %d", flit_width_p, pr_data_width_p); + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_wormhole_to_stream) + diff --git a/designs/black-parrot/src/bp/bp_me_xbar_stream.sv b/designs/black-parrot/src/bp/bp_me_xbar_stream.sv new file mode 100644 index 0000000..3b7c835 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_me_xbar_stream.sv @@ -0,0 +1,131 @@ +/** + * + * Name: + * bp_me_xbar_stream.sv + * + * Description: + * This xbar arbitrates BedRock Stream messages between N sources and M sinks. + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_me_xbar_stream + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(payload_width_p) + , parameter `BSG_INV_PARAM(num_source_p) + , parameter `BSG_INV_PARAM(num_sink_p) + , parameter `BSG_INV_PARAM(stream_mask_p) + `declare_bp_bedrock_generic_if_width(paddr_width_p, payload_width_p, xbar) + + , localparam lg_num_source_lp = `BSG_SAFE_CLOG2(num_source_p) + , localparam lg_num_sink_lp = `BSG_SAFE_CLOG2(num_sink_p) + ) + (input clk_i + , input reset_i + + , input [num_source_p-1:0][xbar_header_width_lp-1:0] msg_header_i + , input [num_source_p-1:0][bedrock_fill_width_p-1:0] msg_data_i + , input [num_source_p-1:0] msg_v_i + , output logic [num_source_p-1:0] msg_ready_and_o + , input [num_source_p-1:0][lg_num_sink_lp-1:0] msg_dst_i + + , output logic [num_sink_p-1:0][xbar_header_width_lp-1:0] msg_header_o + , output logic [num_sink_p-1:0][bedrock_fill_width_p-1:0] msg_data_o + , output logic [num_sink_p-1:0] msg_v_o + , input [num_sink_p-1:0] msg_ready_and_i + ); + + `declare_bp_bedrock_generic_if(paddr_width_p, payload_width_p, xbar); + bp_bedrock_xbar_header_s [num_source_p-1:0] msg_header_li; + logic [num_source_p-1:0][bedrock_fill_width_p-1:0] msg_data_li; + logic [num_source_p-1:0] msg_v_li, msg_yumi_lo; + logic [num_source_p-1:0][lg_num_sink_lp-1:0] msg_dst_li; + + for (genvar i = 0; i < num_source_p; i++) + begin : buffer + bsg_two_fifo + #(.width_p(lg_num_sink_lp+bedrock_fill_width_p+xbar_header_width_lp)) + in_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i({msg_dst_i[i], msg_data_i[i], msg_header_i[i]}) + ,.v_i(msg_v_i[i]) + ,.ready_param_o(msg_ready_and_o[i]) + + ,.data_o({msg_dst_li[i], msg_data_li[i], msg_header_li[i]}) + ,.v_o(msg_v_li[i]) + ,.yumi_i(msg_yumi_lo[i]) + ); + end + + logic [num_sink_p-1:0] msg_unlock_li; + logic [num_sink_p-1:0][num_source_p-1:0] grants_oi_one_hot_lo; + bsg_crossbar_control_locking_o_by_i + #(.i_els_p(num_source_p), .o_els_p(num_sink_p)) + cbc + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.valid_i(msg_v_li) + ,.sel_io_i(msg_dst_li) + ,.yumi_o(msg_yumi_lo) + + ,.ready_and_i(msg_ready_and_i) + ,.valid_o(msg_v_o) + ,.unlock_i(msg_unlock_li) + ,.grants_oi_one_hot_o(grants_oi_one_hot_lo) + ); + + logic [num_source_p-1:0][xbar_header_width_lp+bedrock_fill_width_p-1:0] source_combine; + logic [num_sink_p-1:0][xbar_header_width_lp+bedrock_fill_width_p-1:0] sink_combine; + for (genvar i = 0; i < num_source_p; i++) + begin : source_comb + assign source_combine[i] = {msg_header_li[i], msg_data_li[i]}; + end + for (genvar i = 0; i < num_sink_p; i++) + begin : sink_comb + // We just use this to indicate the end of packets for unlocking + logic msg_last_lo; + bp_me_stream_pump_control + #(.bp_params_p(bp_params_p) + ,.stream_mask_p(stream_mask_p) + ,.data_width_p(bedrock_fill_width_p) + ,.payload_width_p(payload_width_p) + ,.widest_beat_size_p(e_size_1B) + ) + pump_control + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.header_i(msg_header_o[i]) + ,.ack_i(msg_ready_and_i[i] & msg_v_o[i]) + + ,.addr_o() + ,.first_o() + ,.critical_o() + ,.last_o(msg_last_lo) + ); + + assign {msg_header_o[i], msg_data_o[i]} = sink_combine[i]; + assign msg_unlock_li[i] = msg_ready_and_i[i] & msg_v_o[i] & msg_last_lo; + end + + bsg_crossbar_o_by_i + #(.i_els_p(num_source_p), .o_els_p(num_sink_p), .width_p(xbar_header_width_lp+bedrock_fill_width_p)) + cb + (.i(source_combine) + ,.sel_oi_one_hot_i(grants_oi_one_hot_lo) + ,.o(sink_combine) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bp_me_xbar_stream) + diff --git a/designs/black-parrot/src/bp/bp_mem_complex.sv b/designs/black-parrot/src/bp/bp_mem_complex.sv new file mode 100644 index 0000000..6c17b6c --- /dev/null +++ b/designs/black-parrot/src/bp/bp_mem_complex.sv @@ -0,0 +1,197 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" +`include "bp_me_defines.svh" + +module bp_mem_complex + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + ) + (input core_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input dma_clk_i + , input dma_reset_i + + , input [mem_noc_did_width_p-1:0] my_did_i + + , input [mc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_link_i + , output logic [mc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_link_o + + , input [mc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_i + , output logic [mc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_o + + , input [mc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_link_i + , output logic [mc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_link_o + + , input [S:N][mc_x_dim_p-1:0][dma_noc_ral_link_width_lp-1:0] dma_link_i + , output logic [S:N][mc_x_dim_p-1:0][dma_noc_ral_link_width_lp-1:0] dma_link_o + ); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(dma_noc_flit_width_p, bp_dma_ready_and_link_s); + + bp_coh_ready_and_link_s [mc_x_dim_p-1:0][S:W] lce_req_link_li, lce_req_link_lo; + bp_coh_ready_and_link_s [E:W] lce_req_hor_link_li, lce_req_hor_link_lo; + bp_coh_ready_and_link_s [S:N][mc_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo; + bp_coh_ready_and_link_s [mc_x_dim_p-1:0][S:W] lce_cmd_link_li, lce_cmd_link_lo; + bp_coh_ready_and_link_s [E:W] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; + bp_coh_ready_and_link_s [S:N][mc_x_dim_p-1:0] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; + bp_coh_ready_and_link_s [mc_x_dim_p-1:0][S:W] lce_resp_link_li, lce_resp_link_lo; + bp_coh_ready_and_link_s [E:W] lce_resp_hor_link_li, lce_resp_hor_link_lo; + bp_coh_ready_and_link_s [S:N][mc_x_dim_p-1:0] lce_resp_ver_link_li, lce_resp_ver_link_lo; + + bp_dma_ready_and_link_s [mc_x_dim_p-1:0][S:N] dma_link_li, dma_link_lo; + bp_dma_ready_and_link_s [S:N][mc_x_dim_p-1:0] mem_ver_link_li, mem_ver_link_lo; + + for (genvar i = 0; i < mc_x_dim_p; i++) + begin : node + wire [coh_noc_cord_width_p-1:0] cord_li = {coh_noc_y_cord_width_p'(1'b1+cc_y_dim_p), coh_noc_x_cord_width_p'(i+sac_x_dim_p)}; + + if (mc_y_dim_p > 0) + begin : node + bp_l2e_tile_node + #(.bp_params_p(bp_params_p)) + l2e + (.core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.dma_clk_i(dma_clk_i) + ,.dma_reset_i(dma_reset_i) + + ,.my_did_i(my_did_i) + ,.my_cord_i(cord_li) + + ,.coh_lce_req_link_i(lce_req_link_li[i]) + ,.coh_lce_req_link_o(lce_req_link_lo[i]) + + ,.coh_lce_cmd_link_i(lce_cmd_link_li[i]) + ,.coh_lce_cmd_link_o(lce_cmd_link_lo[i]) + + ,.coh_lce_resp_link_i(lce_resp_link_li[i]) + ,.coh_lce_resp_link_o(lce_resp_link_lo[i]) + + ,.dma_link_i(dma_link_li[i]) + ,.dma_link_o(dma_link_lo[i]) + ); + end + else + begin : stub + assign lce_req_link_lo[i] = '0; + assign lce_cmd_link_lo[i] = '0; + assign lce_resp_link_lo[i] = '0; + + assign dma_link_lo[i] = '0; + end + end + + if (mc_y_dim_p > 0) + begin : stitch + assign lce_req_ver_link_li[N] = coh_req_link_i; + assign lce_req_ver_link_li[S] = '0; + assign lce_req_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(mc_x_dim_p) + ,.y_max_p(1) + ) + coh_req_mesh + (.outs_i(lce_req_link_lo) + ,.ins_o(lce_req_link_li) + + ,.hor_i(lce_req_hor_link_li) + ,.hor_o(lce_req_hor_link_lo) + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); + assign coh_req_link_o = lce_req_ver_link_lo[N]; + + assign lce_cmd_ver_link_li[N] = coh_cmd_link_i; + assign lce_cmd_ver_link_li[S] = '0; + assign lce_cmd_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(mc_x_dim_p) + ,.y_max_p(1) + ) + coh_cmd_mesh + (.outs_i(lce_cmd_link_lo) + ,.ins_o(lce_cmd_link_li) + + ,.hor_i(lce_cmd_hor_link_li) + ,.hor_o(lce_cmd_hor_link_lo) + ,.ver_i(lce_cmd_ver_link_li) + ,.ver_o(lce_cmd_ver_link_lo) + ); + assign coh_cmd_link_o = lce_cmd_ver_link_lo[N]; + + assign lce_resp_ver_link_li[N] = coh_resp_link_i; + assign lce_resp_ver_link_li[S] = '0; + assign lce_resp_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(mc_x_dim_p) + ,.y_max_p(1) + ) + coh_resp_mesh + (.outs_i(lce_resp_link_lo) + ,.ins_o(lce_resp_link_li) + + ,.hor_i(lce_resp_hor_link_li) + ,.hor_o(lce_resp_hor_link_lo) + ,.ver_i(lce_resp_ver_link_li) + ,.ver_o(lce_resp_ver_link_lo) + ); + assign coh_resp_link_o = lce_resp_ver_link_lo[N]; + + bp_dma_ready_and_link_s [mc_x_dim_p-1:0][S:W] mem_mesh_lo, mem_mesh_li; + for (genvar j = 0; j < mc_x_dim_p; j++) + begin : link + assign mem_mesh_lo[j][S:N] = dma_link_lo[j]; + assign dma_link_li[j] = mem_mesh_li[j][S:N]; + end + assign mem_ver_link_li[N] = dma_link_i[N]; + bsg_mesh_stitch + #(.width_p($bits(bp_dma_ready_and_link_s)) + ,.x_max_p(mc_x_dim_p) + ,.y_max_p(1) + ) + mem_mesh + (.outs_i(mem_mesh_lo) + ,.ins_o(mem_mesh_li) + + ,.hor_i() + ,.hor_o() + ,.ver_i(mem_ver_link_li) + ,.ver_o(mem_ver_link_lo) + ); + assign dma_link_o[N] = mem_ver_link_lo[N]; + end + else + begin : stub + assign coh_req_link_o = '0; + assign coh_cmd_link_o = '0; + assign coh_resp_link_o = '0; + + assign mem_ver_link_lo[S] = dma_link_i[N]; + assign dma_link_o[N] = mem_ver_link_li[S]; + end + + assign dma_link_o[S] = mem_ver_link_lo[S]; + assign mem_ver_link_li[S] = dma_link_i[S]; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_mmu.sv b/designs/black-parrot/src/bp/bp_mmu.sv new file mode 100644 index 0000000..b69ec26 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_mmu.sv @@ -0,0 +1,209 @@ +/* + * bp_mmu.v + */ + +`include "bp_common_defines.svh" + +module bp_mmu + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + , parameter `BSG_INV_PARAM(tlb_els_4k_p) + , parameter `BSG_INV_PARAM(tlb_els_2m_p) + , parameter `BSG_INV_PARAM(tlb_els_1g_p) + , parameter latch_last_read_p = 0 + + , localparam entry_width_lp = `bp_pte_leaf_width(paddr_width_p) + ) + (input clk_i + , input reset_i + + , input flush_i + , input fence_i + , input [1:0] priv_mode_i + , input trans_en_i + , input sum_i + , input mxr_i + , input uncached_mode_i + , input nonspec_mode_i + , input [hio_width_p-1:0] hio_mask_i + + , input w_v_i + , input [vtag_width_p-1:0] w_vtag_i + , input [entry_width_lp-1:0] w_entry_i + + , input r_v_i + , input r_instr_i + , input r_load_i + , input r_store_i + , input [dword_width_gp-1:0] r_eaddr_i + , input [1:0] r_size_i + , input r_cbo_i + , input r_ptw_i + + , output logic r_v_o + , output logic [ptag_width_p-1:0] r_ptag_o + , output logic r_instr_miss_o + , output logic r_load_miss_o + , output logic r_store_miss_o + , output logic r_uncached_o + , output logic r_nonidem_o + , output logic r_dram_o + , output logic r_instr_access_fault_o + , output logic r_load_access_fault_o + , output logic r_store_access_fault_o + , output logic r_instr_misaligned_o + , output logic r_load_misaligned_o + , output logic r_store_misaligned_o + , output logic r_instr_page_fault_o + , output logic r_load_page_fault_o + , output logic r_store_page_fault_o + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + + // This logic only works for 8-byte words max. + logic r_misaligned; + always_comb + case ({r_ptw_i, r_cbo_i, r_size_i}) + {2'b00, 2'b01}: r_misaligned = |r_eaddr_i[0+:1]; + {2'b00, 2'b10}: r_misaligned = |r_eaddr_i[0+:2]; + {2'b00, 2'b11}: r_misaligned = |r_eaddr_i[0+:3]; + default: r_misaligned = '0; + endcase + + logic r_instr_r, r_load_r, r_store_r, r_cbo_r, r_ptw_r, r_misaligned_r, trans_r; + logic [etag_width_p-1:0] r_etag_r; + wire [etag_width_p-1:0] r_etag_li = r_eaddr_i[dword_width_gp-1-:etag_width_p]; + wire trans_li = trans_en_i & ~r_ptw_i; + bsg_dff_reset_en + #(.width_p(7+etag_width_p)) + read_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(r_v_i) + + ,.data_i({trans_li, r_misaligned, r_instr_i, r_load_i, r_store_i, r_cbo_i, r_ptw_i, r_etag_li}) + ,.data_o({trans_r, r_misaligned_r, r_instr_r, r_load_r, r_store_r, r_cbo_r, r_ptw_r, r_etag_r}) + ); + + logic r_v_r; + bsg_dff_reset_set_clear + #(.width_p(1)) + r_v_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.set_i(r_v_i) + ,.clear_i(flush_i || !latch_last_read_p) + ,.data_o(r_v_r) + ); + + logic tlb_r_v_lo; + bp_pte_leaf_s tlb_r_entry_lo; + wire tlb_r_v_li = r_v_i | flush_i; + wire tlb_w_v_li = w_v_i; + wire tlb_v_li = tlb_r_v_li | tlb_w_v_li; + wire [vtag_width_p-1:0] tlb_vtag_li = w_v_i ? w_vtag_i : r_etag_li; + bp_tlb + #(.bp_params_p(bp_params_p), .els_4k_p(tlb_els_4k_p), .els_2m_p(tlb_els_2m_p), .els_1g_p(tlb_els_1g_p)) + tlb + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.fence_i(fence_i) + + ,.v_i(tlb_v_li) + ,.w_i(tlb_w_v_li) + ,.vtag_i(tlb_vtag_li) + ,.entry_i(w_entry_i) + + ,.v_o(tlb_r_v_lo) + ,.entry_o(tlb_r_entry_lo) + ); + + bp_pte_leaf_s tlb_r_entry_r; + logic tlb_r_v_r; + bsg_dff_sync_read + #(.width_p(1+$bits(bp_pte_leaf_s)), .bypass_p(1)) + entry_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.v_n_i(tlb_r_v_li) + ,.data_i({tlb_r_v_lo, tlb_r_entry_lo}) + ,.data_o({tlb_r_v_r, tlb_r_entry_r}) + ); + + bp_pte_leaf_s passthrough_entry, tlb_entry_lo; + assign passthrough_entry = '{ptag: r_etag_r, default: '0}; + assign tlb_entry_lo = trans_r ? tlb_r_entry_r : passthrough_entry; + wire tlb_v_lo = trans_r ? tlb_r_v_r : r_v_r; + + wire ptag_v_lo = tlb_v_lo; + wire [ptag_width_p-1:0] ptag_lo = tlb_entry_lo.ptag; + logic ptag_uncached_lo, ptag_nonidem_lo, ptag_dram_lo; + bp_pma + #(.bp_params_p(bp_params_p)) + pma + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.ptag_i(ptag_lo) + ,.uncached_mode_i(uncached_mode_i) + ,.nonspec_mode_i(nonspec_mode_i) + + ,.uncached_o(ptag_uncached_lo) + ,.nonidem_o(ptag_nonidem_lo) + ,.dram_o(ptag_dram_lo) + ); + + // Fault if higher bits of eaddr do not match vaddr MSB + wire eaddr_fault_v = ~&r_etag_r[etag_width_p-1:vtag_width_p-1] & |r_etag_r[etag_width_p-1:vtag_width_p-1]; + wire cached_fault_v = r_cbo_r & ptag_v_lo & ptag_uncached_lo; + // Fault if hio bit is not enabled and we're accessing that hio + wire hio_fault_v = (r_instr_r & ptag_v_lo & ptag_lo[ptag_width_p-1-:hio_width_p] != '0) + || (ptag_v_lo & ptag_lo[ptag_width_p-1-:hio_width_p] & ~hio_mask_i); + + // Access faults + wire instr_access_fault_v = r_instr_r & hio_fault_v; + wire load_access_fault_v = r_load_r & cached_fault_v; + wire store_access_fault_v = r_store_r & cached_fault_v; + wire any_access_fault_v = |{instr_access_fault_v, load_access_fault_v, store_access_fault_v}; + + // Page faults + wire instr_exe_page_fault_v = tlb_v_lo & ~tlb_entry_lo.x; + wire instr_priv_page_fault_v = tlb_v_lo & (((priv_mode_i == `PRIV_MODE_S) & tlb_entry_lo.u) + | ((priv_mode_i == `PRIV_MODE_U) & ~tlb_entry_lo.u) + ); + wire data_priv_page_fault = tlb_v_lo & (((priv_mode_i == `PRIV_MODE_S) & ~sum_i & tlb_entry_lo.u) + | ((priv_mode_i == `PRIV_MODE_U) & ~tlb_entry_lo.u) + ); + wire data_read_page_fault = tlb_v_lo & ~(tlb_entry_lo.r | (tlb_entry_lo.x & mxr_i)); + wire data_write_page_fault = tlb_v_lo & ~(tlb_entry_lo.w & tlb_entry_lo.d); + wire instr_page_fault_v = trans_r & r_instr_r & (instr_priv_page_fault_v | instr_exe_page_fault_v | eaddr_fault_v); + wire load_page_fault_v = trans_r & r_load_r & (data_priv_page_fault | data_read_page_fault | eaddr_fault_v); + wire store_page_fault_v = trans_r & r_store_r & (data_priv_page_fault | data_write_page_fault | eaddr_fault_v); + wire any_page_fault_v = |{instr_page_fault_v, load_page_fault_v, store_page_fault_v}; + + wire any_fault_v = any_access_fault_v | any_page_fault_v; + + assign r_v_o = r_v_r & tlb_v_lo & ~any_fault_v; + assign r_instr_miss_o = r_v_r & ~tlb_v_lo & ~any_fault_v & r_instr_r; + assign r_load_miss_o = r_v_r & ~tlb_v_lo & ~any_fault_v & r_load_r; + assign r_store_miss_o = r_v_r & ~tlb_v_lo & ~any_fault_v & r_store_r; + assign r_instr_misaligned_o = r_v_r & r_misaligned_r & r_instr_r; + assign r_load_misaligned_o = r_v_r & r_misaligned_r & r_load_r; + assign r_store_misaligned_o = r_v_r & r_misaligned_r & r_store_r; + assign r_instr_access_fault_o = r_v_r & instr_access_fault_v; + assign r_load_access_fault_o = r_v_r & load_access_fault_v; + assign r_store_access_fault_o = r_v_r & store_access_fault_v; + assign r_instr_page_fault_o = r_v_r & instr_page_fault_v; + assign r_load_page_fault_o = r_v_r & load_page_fault_v; + assign r_store_page_fault_o = r_v_r & store_page_fault_v; + assign r_ptag_o = ptag_lo; + assign r_uncached_o = ptag_uncached_lo; + assign r_nonidem_o = ptag_nonidem_lo; + assign r_dram_o = ptag_dram_lo; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_mmu) + diff --git a/designs/black-parrot/src/bp/bp_monitor.cpp b/designs/black-parrot/src/bp/bp_monitor.cpp new file mode 100644 index 0000000..8437205 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_monitor.cpp @@ -0,0 +1,21 @@ +#include "svdpi.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace std; + +extern "C" int getchar() { + return getchar(); +} + diff --git a/designs/black-parrot/src/bp/bp_multicore.sv b/designs/black-parrot/src/bp/bp_multicore.sv new file mode 100644 index 0000000..c17440f --- /dev/null +++ b/designs/black-parrot/src/bp/bp_multicore.sv @@ -0,0 +1,221 @@ +/** + * + * bp_multicore.v + * + */ + +`include "bsg_noc_links.svh" + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_multicore + import bp_common_pkg::*; + import bp_be_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) + ) + (input core_clk_i + , input rt_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input mem_clk_i + , input mem_reset_i + + , input dma_clk_i + , input dma_reset_i + + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + + , input [E:W][mem_noc_ral_link_width_lp-1:0] mem_fwd_link_i + , output logic [E:W][mem_noc_ral_link_width_lp-1:0] mem_fwd_link_o + + , input [E:W][mem_noc_ral_link_width_lp-1:0] mem_rev_link_i + , output logic [E:W][mem_noc_ral_link_width_lp-1:0] mem_rev_link_o + + , output logic [S:N][mc_x_dim_p-1:0][dma_noc_ral_link_width_lp-1:0] dma_link_o + , input [S:N][mc_x_dim_p-1:0][dma_noc_ral_link_width_lp-1:0] dma_link_i + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bp_mem_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(dma_noc_flit_width_p, bp_dma_ready_and_link_s); + + bp_coh_ready_and_link_s [E:W][cc_y_dim_p-1:0] coh_req_hor_link_li, coh_req_hor_link_lo; + bp_coh_ready_and_link_s [E:W][cc_y_dim_p-1:0] coh_cmd_hor_link_li, coh_cmd_hor_link_lo; + bp_coh_ready_and_link_s [E:W][cc_y_dim_p-1:0] coh_fill_hor_link_li, coh_fill_hor_link_lo; + bp_coh_ready_and_link_s [E:W][cc_y_dim_p-1:0] coh_resp_hor_link_li, coh_resp_hor_link_lo; + + bp_coh_ready_and_link_s [S:N][cc_x_dim_p-1:0] coh_req_ver_link_li, coh_req_ver_link_lo; + bp_coh_ready_and_link_s [S:N][cc_x_dim_p-1:0] coh_cmd_ver_link_li, coh_cmd_ver_link_lo; + bp_coh_ready_and_link_s [S:N][cc_x_dim_p-1:0] coh_fill_ver_link_li, coh_fill_ver_link_lo; + bp_coh_ready_and_link_s [S:N][cc_x_dim_p-1:0] coh_resp_ver_link_li, coh_resp_ver_link_lo; + + bp_dma_ready_and_link_s [S:N][cc_x_dim_p-1:0] dma_link_li, dma_link_lo; + + // IO and SACC complexes only use Req/Cmd networks + assign coh_resp_ver_link_li[N] = '0; + assign coh_resp_hor_link_li[W] = '0; + assign coh_fill_ver_link_li[N] = '0; + assign coh_fill_hor_link_li[W] = '0; + // Memory complex does not use Fill network + assign coh_fill_ver_link_li[S] = '0; + + assign dma_link_li[N] = '0; + bp_core_complex + #(.bp_params_p(bp_params_p)) + cc + (.core_clk_i(core_clk_i) + ,.rt_clk_i(rt_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.dma_clk_i(dma_clk_i) + ,.dma_reset_i(dma_reset_i) + + ,.my_did_i(my_did_i) + ,.host_did_i(host_did_i) + + ,.coh_req_hor_link_i(coh_req_hor_link_li) + ,.coh_req_hor_link_o(coh_req_hor_link_lo) + + ,.coh_cmd_hor_link_i(coh_cmd_hor_link_li) + ,.coh_cmd_hor_link_o(coh_cmd_hor_link_lo) + + ,.coh_fill_hor_link_i(coh_fill_hor_link_li) + ,.coh_fill_hor_link_o(coh_fill_hor_link_lo) + + ,.coh_resp_hor_link_i(coh_resp_hor_link_li) + ,.coh_resp_hor_link_o(coh_resp_hor_link_lo) + + ,.coh_req_ver_link_i(coh_req_ver_link_li) + ,.coh_req_ver_link_o(coh_req_ver_link_lo) + + ,.coh_cmd_ver_link_i(coh_cmd_ver_link_li) + ,.coh_cmd_ver_link_o(coh_cmd_ver_link_lo) + + ,.coh_fill_ver_link_i(coh_fill_ver_link_li) + ,.coh_fill_ver_link_o(coh_fill_ver_link_lo) + + ,.coh_resp_ver_link_i(coh_resp_ver_link_li) + ,.coh_resp_ver_link_o(coh_resp_ver_link_lo) + + ,.dma_link_i(dma_link_li) + ,.dma_link_o(dma_link_lo) + ); + + bp_io_complex + #(.bp_params_p(bp_params_p)) + ic + (.core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.mem_clk_i(mem_clk_i) + ,.mem_reset_i(mem_reset_i) + + ,.my_did_i(my_did_i) + ,.host_did_i(host_did_i) + + ,.coh_req_link_i(coh_req_ver_link_lo[N]) + ,.coh_req_link_o(coh_req_ver_link_li[N]) + + ,.coh_cmd_link_i(coh_cmd_ver_link_lo[N]) + ,.coh_cmd_link_o(coh_cmd_ver_link_li[N]) + + ,.mem_fwd_link_i(mem_fwd_link_i) + ,.mem_fwd_link_o(mem_fwd_link_o) + + ,.mem_rev_link_i(mem_rev_link_i) + ,.mem_rev_link_o(mem_rev_link_o) + ); + + bp_dma_ready_and_link_s [S:N][cc_x_dim_p-1:0] l2e_dma_link_li, l2e_dma_link_lo; + bp_mem_complex + #(.bp_params_p(bp_params_p)) + mc + (.core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.dma_clk_i(dma_clk_i) + ,.dma_reset_i(dma_reset_i) + + ,.my_did_i(my_did_i) + + ,.coh_req_link_i(coh_req_ver_link_lo[S]) + ,.coh_req_link_o(coh_req_ver_link_li[S]) + + ,.coh_cmd_link_i(coh_cmd_ver_link_lo[S]) + ,.coh_cmd_link_o(coh_cmd_ver_link_li[S]) + + ,.coh_resp_link_i(coh_resp_ver_link_lo[S]) + ,.coh_resp_link_o(coh_resp_ver_link_li[S]) + + ,.dma_link_i(l2e_dma_link_li) + ,.dma_link_o(l2e_dma_link_lo) + ); + assign l2e_dma_link_li[N] = dma_link_lo[S]; + assign dma_link_li[S] = l2e_dma_link_lo[N]; + + assign l2e_dma_link_li[S] = dma_link_i[S]; + assign dma_link_o[S] = l2e_dma_link_lo[S]; + + bp_cacc_complex + #(.bp_params_p(bp_params_p)) + cac + (.core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.coh_req_link_i(coh_req_hor_link_lo[E]) + ,.coh_req_link_o(coh_req_hor_link_li[E]) + + ,.coh_cmd_link_i(coh_cmd_hor_link_lo[E]) + ,.coh_cmd_link_o(coh_cmd_hor_link_li[E]) + + ,.coh_fill_link_i(coh_fill_hor_link_lo[E]) + ,.coh_fill_link_o(coh_fill_hor_link_li[E]) + + ,.coh_resp_link_i(coh_resp_hor_link_lo[E]) + ,.coh_resp_link_o(coh_resp_hor_link_li[E]) + ); + + bp_sacc_complex + #(.bp_params_p(bp_params_p)) + sac + (.core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.coh_req_link_i(coh_req_hor_link_lo[W]) + ,.coh_req_link_o(coh_req_hor_link_li[W]) + + ,.coh_cmd_link_i(coh_cmd_hor_link_lo[W]) + ,.coh_cmd_link_o(coh_cmd_hor_link_li[W]) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nd_socket.sv b/designs/black-parrot/src/bp/bp_nd_socket.sv new file mode 100644 index 0000000..0f4b7d9 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nd_socket.sv @@ -0,0 +1,99 @@ +/** + * + * bp_nd_socket.v + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_nd_socket + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter `BSG_INV_PARAM(flit_width_p) + , parameter len_width_p = 1 + , parameter dims_p = 2 + , parameter cord_dims_p = dims_p + , parameter int cord_markers_pos_p[cord_dims_p:0] = '{ 5, 4, 0 } + , localparam dirs_lp = dims_p*2+1 + , parameter bit [1:0][dirs_lp-1:0][dirs_lp-1:0] routing_matrix_p = (dims_p == 2) ? StrictXY : StrictX + , parameter async_clk_p = 0 + , parameter els_p = 0 + + , localparam ral_link_width_lp = `bsg_ready_and_link_sif_width(flit_width_p) + ) + (input tile_clk_i + , input tile_reset_i + + , input network_clk_i + , input network_reset_i + + , input [cord_markers_pos_p[dims_p]-1:0] my_cord_i + + , input [els_p-1:0][dirs_lp-2:0][ral_link_width_lp-1:0] network_link_i + , output [els_p-1:0][dirs_lp-2:0][ral_link_width_lp-1:0] network_link_o + + , input [els_p-1:0][ral_link_width_lp-1:0] tile_link_i + , output [els_p-1:0][ral_link_width_lp-1:0] tile_link_o + + ); + + + `declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_s); + bsg_ready_and_link_s [els_p-1:0] network_link_li, network_link_lo; + +for (genvar i=0; i < els_p; i++) + begin: routers + if (async_clk_p == 1) + begin : async + bsg_async_noc_link + #(.width_p(flit_width_p) + ,.lg_size_p(3) + ) + cdc + (.aclk_i(tile_clk_i) + ,.areset_i(tile_reset_i) + + ,.bclk_i(network_clk_i) + ,.breset_i(network_reset_i) + + ,.alink_i(tile_link_i[i]) + ,.alink_o(tile_link_o[i]) + + ,.blink_i(network_link_lo[i]) + ,.blink_o(network_link_li[i]) + ); + end + else + begin : sync + assign network_link_li[i] = tile_link_i[i]; + assign tile_link_o[i] = network_link_lo[i]; + end + + bsg_wormhole_router + #(.flit_width_p(flit_width_p) + ,.dims_p(dims_p) + ,.cord_dims_p(cord_dims_p) + ,.cord_markers_pos_p(cord_markers_pos_p) + ,.len_width_p(len_width_p) + ,.reverse_order_p(1) + ,.routing_matrix_p(routing_matrix_p) + ,.hold_on_valid_p(1) + ) + router + (.clk_i(network_clk_i) + ,.reset_i(network_reset_i) + + ,.my_cord_i(my_cord_i) + + ,.link_i({network_link_i[i], network_link_li[i]}) + ,.link_o({network_link_o[i], network_link_lo[i]}) + ); + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bp_nd_socket) + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_branch_profiler.sv b/designs/black-parrot/src/bp/bp_nonsynth_branch_profiler.sv new file mode 100644 index 0000000..7321af3 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_branch_profiler.sv @@ -0,0 +1,141 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_nonsynth_branch_profiler + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + + , parameter branch_trace_file_p = "branch" + ) + (input clk_i + , input reset_i + + , input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i + + , input [fe_cmd_width_lp-1:0] fe_cmd_o + , input fe_cmd_yumi_i + + , input commit_v_i + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_fe_branch_metadata_fwd_s(ras_idx_width_p, btb_tag_width_p, btb_idx_width_p, bht_idx_width_p, ghist_width_p, bht_row_els_p); + bp_fe_cmd_s fe_cmd; + bp_fe_branch_metadata_fwd_s branch_metadata; + assign fe_cmd = fe_cmd_o; + + wire pc_redirect_v = fe_cmd_yumi_i + & (fe_cmd.opcode == e_op_pc_redirection) + & (fe_cmd.operands.pc_redirect_operands.subopcode == e_subop_branch_mispredict); + wire attaboy_v = fe_cmd_yumi_i & (fe_cmd.opcode == e_op_attaboy); + + assign branch_metadata = pc_redirect_v + ? fe_cmd.operands.pc_redirect_operands.branch_metadata_fwd + : fe_cmd.operands.attaboy.branch_metadata_fwd; + + integer branch_histo [longint]; + integer miss_histo [longint]; + + integer instr_cnt; + integer attaboy_cnt; + integer redirect_cnt; + integer br_cnt; + integer jal_cnt; + integer jalr_cnt; + integer call_cnt; + integer ret_cnt; + integer btb_hit_cnt; + integer ras_hit_cnt; + integer bht_hit_cnt; + + integer file; + string file_name; + always_ff @(negedge reset_i) + begin + file_name = $sformatf("%s_%x.stats", branch_trace_file_p, mhartid_i); + file = $fopen(file_name, "w"); + end + + always_ff @(negedge clk_i) + if (reset_i) + begin + instr_cnt <= 0; + attaboy_cnt <= 0; + redirect_cnt <= 0; + br_cnt <= 0; + jal_cnt <= 0; + jalr_cnt <= 0; + call_cnt <= 0; + ret_cnt <= 0; + btb_hit_cnt <= 0; + ras_hit_cnt <= 0; + bht_hit_cnt <= 0; + end + else + begin + instr_cnt <= instr_cnt + commit_v_i; + attaboy_cnt <= attaboy_cnt + attaboy_v; + redirect_cnt <= redirect_cnt + pc_redirect_v; + if (attaboy_v) + begin + br_cnt <= br_cnt + branch_metadata.site_br; + jal_cnt <= jal_cnt + branch_metadata.site_jal; + jalr_cnt <= jalr_cnt + branch_metadata.site_jalr; + call_cnt <= call_cnt + branch_metadata.site_call; + ret_cnt <= ret_cnt + branch_metadata.site_return; + + btb_hit_cnt <= btb_hit_cnt + branch_metadata.src_btb; + bht_hit_cnt <= bht_hit_cnt + branch_metadata.site_br; + ras_hit_cnt <= ras_hit_cnt + branch_metadata.src_ras; + + if (branch_histo.exists(fe_cmd.npc)) + begin + branch_histo[fe_cmd.npc] <= branch_histo[fe_cmd.npc] + 1; + miss_histo[fe_cmd.npc] <= miss_histo[fe_cmd.npc] + 0; + end + else + begin + branch_histo[fe_cmd.npc] <= 1; + miss_histo[fe_cmd.npc] <= 0; + end + end + else if (pc_redirect_v) + begin + br_cnt <= br_cnt + branch_metadata.site_br; + jal_cnt <= jal_cnt + branch_metadata.site_jal; + jalr_cnt <= jalr_cnt + branch_metadata.site_jalr; + call_cnt <= call_cnt + branch_metadata.site_call; + ret_cnt <= ret_cnt + branch_metadata.site_return; + + if (branch_histo.exists(fe_cmd.npc)) + begin + branch_histo[fe_cmd.npc] <= branch_histo[fe_cmd.npc] + 1; + miss_histo[fe_cmd.npc] <= miss_histo[fe_cmd.npc] + 1; + end + else + begin + branch_histo[fe_cmd.npc] <= 1; + miss_histo[fe_cmd.npc] <= 1; + end + end + end + + final + begin + $fwrite(file, "Branch statistics\n"); + $fwrite(file, "MPKI: %d\n", redirect_cnt / (instr_cnt / 1000)); + $fwrite(file, "BTB hit%%: %d (%d/%d)\n", (btb_hit_cnt * 100) / (br_cnt+jal_cnt+jalr_cnt), btb_hit_cnt, br_cnt+jal_cnt+jalr_cnt); + $fwrite(file, "BHT hit%%: %d (%d/%d)\n", (bht_hit_cnt * 100) / (br_cnt), bht_hit_cnt, br_cnt); + $fwrite(file, "RAS hit%%: %d (%d/%d)\n", (ras_hit_cnt * 100) / (ret_cnt), ras_hit_cnt, ret_cnt); + $fwrite(file, "==================================== Branches ======================================\n"); + $fwrite(file, "[target\t]\t\toccurances\t\tmisses\t\tmiss%%]\n"); + foreach (branch_histo[key]) + $fwrite(file, "[%x] %d %d %d\n", key, branch_histo[key], miss_histo[key], (miss_histo[key]*100)/branch_histo[key]); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_core_profiler.sv b/designs/black-parrot/src/bp/bp_nonsynth_core_profiler.sv new file mode 100644 index 0000000..a4f5c3a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_core_profiler.sv @@ -0,0 +1,303 @@ + + typedef struct packed + { + logic icache_miss; + logic branch_override; + logic ret_override; + logic realigner; + logic fe_cmd; + logic mispredict; + logic control_haz; + logic data_haz; + logic aux_dep; + logic load_dep; + logic mul_dep; + logic fma_dep; + logic sb_iraw_dep; + logic sb_fraw_dep; + logic sb_iwaw_dep; + logic sb_fwaw_dep; + logic struct_haz; + logic idiv_haz; + logic fdiv_haz; + logic ptw_busy; + logic special; + logic replay; + logic exception; + logic _interrupt; + logic itlb_miss; + logic dtlb_miss; + logic dcache_miss; + logic unknown; + } bp_stall_reason_s; + + typedef enum logic [4:0] + { + icache_miss = 5'd27 + ,branch_override = 5'd26 + ,ret_override = 5'd25 + ,realigner = 5'd24 + ,fe_cmd = 5'd23 + ,mispredict = 5'd22 + ,control_haz = 5'd21 + ,data_haz = 5'd20 + ,aux_dep = 5'd19 + ,load_dep = 5'd18 + ,mul_dep = 5'd17 + ,fma_dep = 5'd16 + ,sb_iraw_dep = 5'd15 + ,sb_fraw_dep = 5'd14 + ,sb_iwaw_dep = 5'd13 + ,sb_fwaw_dep = 5'd12 + ,struct_haz = 5'd11 + ,idiv_haz = 5'd10 + ,fdiv_haz = 5'd9 + ,ptw_busy = 5'd8 + ,special = 5'd7 + ,replay = 5'd6 + ,exception = 5'd5 + ,_interrupt = 5'd4 + ,itlb_miss = 5'd3 + ,dtlb_miss = 5'd2 + ,dcache_miss = 5'd1 + ,unknown = 5'd0 + } bp_stall_reason_e; + +// The BlackParrot core pipeline is a mostly non-stalling pipeline, decoupled between the front-end +// and back-end. +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" +`include "bp_be_defines.svh" + +module bp_nonsynth_core_profiler + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + , parameter stall_trace_file_p = "stall" + + ) + (input clk_i + , input reset_i + + , input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i + + // FE events + , input fe_queue_ready_and_i + + , input br_ovr_i + , input ret_ovr_i + , input realigner_i + , input icache_data_v_i + , input icache_v_i + , input icache_yumi_i + + // Backwards ISS events + // TODO: Differentiate between different FE cmds + , input fe_cmd_nonattaboy_i + , input fe_queue_empty_i + + // ISD events + , input dcache_miss_i + , input mispredict_i + , input control_haz_i + , input data_haz_i + , input aux_dep_i + , input load_dep_i + , input mul_dep_i + , input fma_dep_i + , input sb_iraw_dep_i + , input sb_fraw_dep_i + , input sb_iwaw_dep_i + , input sb_fwaw_dep_i + , input struct_haz_i + , input idiv_haz_i + , input fdiv_haz_i + , input ptw_busy_i + + // ALU events + + // MUL events + + // MEM events + + // Trap packet + , input [retire_pkt_width_lp-1:0] retire_pkt_i + , input [commit_pkt_width_lp-1:0] commit_pkt_i + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + + localparam num_stages_p = 7; + bp_stall_reason_s [num_stages_p-1:0] stall_stage_n, stall_stage_r; + bsg_dff_reset + #(.width_p($bits(bp_stall_reason_s)*num_stages_p)) + stall_pipe + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(stall_stage_n) + ,.data_o(stall_stage_r) + ); + + bp_be_retire_pkt_s retire_pkt; + assign retire_pkt = retire_pkt_i; + + bp_be_commit_pkt_s commit_pkt; + assign commit_pkt = commit_pkt_i; + + logic [29:0] cycle_cnt; + bsg_counter_clear_up + #(.max_val_p(2**30-1), .init_val_p(0)) + cycle_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(1'b0) + ,.up_i(1'b1) + ,.count_o(cycle_cnt) + ); + + always_comb + begin + // IF0 + stall_stage_n[0] = '0; + stall_stage_n[0].fe_cmd |= fe_cmd_nonattaboy_i; + + // IF1 + stall_stage_n[1] = stall_stage_r[0]; + stall_stage_n[1].fe_cmd |= fe_cmd_nonattaboy_i; + stall_stage_n[1].icache_miss |= ~icache_data_v_i; + stall_stage_n[1].branch_override |= br_ovr_i; + stall_stage_n[1].ret_override |= ret_ovr_i; + + // IF2 + stall_stage_n[2] = stall_stage_r[1]; + stall_stage_n[2].fe_cmd |= fe_cmd_nonattaboy_i; + stall_stage_n[2].icache_miss |= ~icache_data_v_i; + stall_stage_n[2].mispredict |= mispredict_i; + stall_stage_n[2].realigner |= realigner_i; + + // ISD + // Dispatch stalls + stall_stage_n[3] = stall_stage_r[2]; + stall_stage_n[3].fe_cmd |= fe_cmd_nonattaboy_i; + stall_stage_n[3].icache_miss |= ~icache_data_v_i; + stall_stage_n[3].mispredict |= mispredict_i; + stall_stage_n[3].data_haz |= data_haz_i; + stall_stage_n[3].aux_dep |= aux_dep_i; + stall_stage_n[3].load_dep |= load_dep_i; + stall_stage_n[3].mul_dep |= mul_dep_i; + stall_stage_n[3].fma_dep |= fma_dep_i; + stall_stage_n[3].sb_iraw_dep |= sb_iraw_dep_i; + stall_stage_n[3].sb_fraw_dep |= sb_fraw_dep_i; + stall_stage_n[3].sb_iwaw_dep |= sb_iwaw_dep_i; + stall_stage_n[3].sb_fwaw_dep |= sb_fwaw_dep_i; + stall_stage_n[3].struct_haz |= struct_haz_i; + stall_stage_n[3].idiv_haz |= idiv_haz_i; + stall_stage_n[3].fdiv_haz |= fdiv_haz_i; + stall_stage_n[3].ptw_busy |= ptw_busy_i; + stall_stage_n[3].control_haz |= control_haz_i; + + stall_stage_n[3].special |= |retire_pkt.special; + stall_stage_n[3].replay |= |retire_pkt.exception; + stall_stage_n[3].exception |= commit_pkt.exception; + stall_stage_n[3]._interrupt |= commit_pkt._interrupt; + stall_stage_n[3].itlb_miss |= commit_pkt.itlb_miss | commit_pkt.itlb_fill_v; + stall_stage_n[3].icache_miss |= commit_pkt.icache_miss; + stall_stage_n[3].dtlb_miss |= commit_pkt.dtlb_load_miss | commit_pkt.dtlb_store_miss | commit_pkt.dtlb_fill_v; + stall_stage_n[3].dcache_miss |= commit_pkt.dcache_miss | dcache_miss_i; + + // EX1 + // BE exception stalls + stall_stage_n[4] = stall_stage_r[3]; + stall_stage_n[4].special |= |retire_pkt.special; + stall_stage_n[4].replay |= |retire_pkt.exception; + stall_stage_n[4].exception |= commit_pkt.exception; + stall_stage_n[4]._interrupt |= commit_pkt._interrupt; + stall_stage_n[4].itlb_miss |= commit_pkt.itlb_miss | commit_pkt.itlb_fill_v; + stall_stage_n[4].icache_miss |= commit_pkt.icache_miss; + stall_stage_n[4].dtlb_miss |= commit_pkt.dtlb_load_miss | commit_pkt.dtlb_store_miss | commit_pkt.dtlb_fill_v; + stall_stage_n[4].dcache_miss |= commit_pkt.dcache_miss | dcache_miss_i; + + // EX2 + // BE exception stalls + stall_stage_n[5] = stall_stage_r[4]; + stall_stage_n[5].special |= |retire_pkt.special; + stall_stage_n[5].replay |= |retire_pkt.exception; + stall_stage_n[5].exception |= commit_pkt.exception; + stall_stage_n[5]._interrupt |= commit_pkt._interrupt; + stall_stage_n[5].itlb_miss |= commit_pkt.itlb_miss | commit_pkt.itlb_fill_v; + stall_stage_n[5].icache_miss |= commit_pkt.icache_miss; + stall_stage_n[5].dtlb_miss |= commit_pkt.dtlb_load_miss | commit_pkt.dtlb_store_miss | commit_pkt.dtlb_fill_v; + stall_stage_n[5].dcache_miss |= commit_pkt.dcache_miss | dcache_miss_i; + + // EX3 + // BE exception stalls + stall_stage_n[6] = stall_stage_r[5]; + stall_stage_n[6].special |= |retire_pkt.special; + stall_stage_n[6].replay |= |retire_pkt.exception; + stall_stage_n[6].exception |= commit_pkt.exception; + stall_stage_n[6]._interrupt |= commit_pkt._interrupt; + stall_stage_n[6].itlb_miss |= commit_pkt.itlb_miss | commit_pkt.itlb_fill_v; + stall_stage_n[6].icache_miss |= commit_pkt.icache_miss; + stall_stage_n[6].dtlb_miss |= commit_pkt.dtlb_load_miss | commit_pkt.dtlb_store_miss | commit_pkt.dtlb_fill_v; + stall_stage_n[6].dcache_miss |= commit_pkt.dcache_miss | dcache_miss_i; + end + + bp_stall_reason_s stall_reason_dec; + assign stall_reason_dec = stall_stage_n[num_stages_p-1]; + logic [$bits(bp_stall_reason_e)-1:0] stall_reason_lo; + bp_stall_reason_e bp_stall_reason_enum; + logic stall_reason_v; + bsg_priority_encode + #(.width_p($bits(bp_stall_reason_s)), .lo_to_hi_p(1)) + stall_encode + (.i(stall_reason_dec) + ,.addr_o(stall_reason_lo) + ,.v_o(stall_reason_v) + ); + assign bp_stall_reason_enum = bp_stall_reason_e'(stall_reason_lo); + + int stall_hist [bp_stall_reason_e]; + always_ff @(posedge clk_i) + if (~reset_i & ~commit_pkt.instret) begin + stall_hist[bp_stall_reason_enum] <= stall_hist[bp_stall_reason_enum] + 1'b1; + end + + integer file; + string file_name; + always_ff @(negedge reset_i) + begin + file_name = $sformatf("%s_%x.trace", stall_trace_file_p, mhartid_i); + file = $fopen(file_name, "w"); + $fwrite(file, "%s,%s,%s,%s,%s\n", "cycle", "x", "y", "pc", "operation"); + end + + wire x_cord_li = '0; + wire y_cord_li = '0; + + always_ff @(negedge clk_i) + begin + if (~reset_i & commit_pkt.instret) + $fwrite(file, "%0d,%x,%x,%x,%s", cycle_cnt, x_cord_li, y_cord_li, commit_pkt.pc, "instr"); + else if (~reset_i) + $fwrite(file, "%0d,%x,%x,%x,%s", cycle_cnt, x_cord_li, y_cord_li, commit_pkt.pc, bp_stall_reason_enum.name()); + + if (~reset_i) + $fwrite(file, "\n"); + end + + final + begin + $fwrite(file, "=============================\n"); + $fwrite(file, "Total Stalls:\n"); + foreach (stall_hist[i]) + $fwrite(file, "%s: %0d\n", i.name(), stall_hist[i]); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_cosim.sv b/designs/black-parrot/src/bp/bp_nonsynth_cosim.sv new file mode 100644 index 0000000..2a625a8 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_cosim.sv @@ -0,0 +1,309 @@ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" + +module bp_nonsynth_cosim + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + , parameter commit_trace_file_p = "commit" + + , localparam max_instr_lp = 2**30 + , localparam decode_width_lp = $bits(bp_be_decode_s) + ) + (input clk_i + , input reset_i + , input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i + + , input trace_en_i + , input checkpoint_i + + , input [decode_width_lp-1:0] decode_i + + , input is_debug_mode_i + , input [commit_pkt_width_lp-1:0] commit_pkt_i + + , input [1:0] priv_mode_i + , input [dword_width_gp-1:0] mstatus_i + , input [dword_width_gp-1:0] mcause_i + , input [dword_width_gp-1:0] scause_i + + , input ird_w_v_i + , input [rv64_reg_addr_width_gp-1:0] ird_addr_i + , input [dpath_width_gp-1:0] ird_data_i + + , input frd_w_v_i + , input [rv64_reg_addr_width_gp-1:0] frd_addr_i + , input [dpath_width_gp-1:0] frd_data_i + + , input cache_req_yumi_i + , input cache_req_nonblocking_i + , input cache_req_complete_i + + , input cosim_clk_i + , input cosim_reset_i + ); + + import "DPI-C" context function chandle cosim_init(input int hartid, input int ncpus, input bit checkpoint); + import "DPI-C" context function void cosim_finish(input chandle cosim_handle); + import "DPI-C" context function int cosim_step(input chandle cosim_handle, + input int hartid, + input longint pc, + input int insn, + input longint wdata, + input longint status, + input longint cause + ); + import "DPI-C" context function int cosim_trap(input chandle cosim_handle, + input int hartid, + input longint pc, + input int insn, + input longint wdata, + input longint status, + input longint cause + ); + + wire posedge_clk = clk_i; + wire negedge_clk = ~clk_i; + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + bp_be_commit_pkt_s commit_pkt; + assign commit_pkt = commit_pkt_i; + + bp_be_decode_s decode_r; + bsg_dff_chain + #(.width_p($bits(bp_be_decode_s)), .num_stages_p(4)) + reservation_pipe + (.clk_i(posedge_clk) + ,.data_i(decode_i) + ,.data_o(decode_r) + ); + + bp_be_commit_pkt_s commit_pkt_r; + logic is_debug_mode_r; + bsg_dff_chain + #(.width_p(1+$bits(commit_pkt)), .num_stages_p(1)) + commit_pkt_reg + (.clk_i(posedge_clk) + + ,.data_i({is_debug_mode_i, commit_pkt}) + ,.data_o({is_debug_mode_r, commit_pkt_r}) + ); + + logic cache_req_complete_r, cache_req_v_r; + // We filter out for ready so that the request only tracks once + wire cache_req_v_li = cache_req_yumi_i & ~cache_req_nonblocking_i; + bsg_dff_chain + #(.width_p(2), .num_stages_p(2)) + cache_req_reg + (.clk_i(negedge_clk) + + ,.data_i({cache_req_complete_i, cache_req_v_li}) + ,.data_o({cache_req_complete_r, cache_req_v_r}) + ); + + logic commit_fifo_full_lo; + logic commit_debug_r; + logic instret_v_r; + logic trap_v_r; + logic [vaddr_width_p-1:0] commit_pc_r; + rv64_instr_fmatype_s commit_instr, commit_instr_r; + logic commit_ird_w_v_r; + logic commit_frd_w_v_r; + logic commit_req_v_r; + logic [dword_width_gp-1:0] cause_r, mstatus_r; + logic commit_fifo_v_lo, commit_fifo_yumi_li; + wire instret_v_li = commit_pkt_r.instret; + wire [vaddr_width_p-1:0] commit_pc_li = commit_pkt_r.pc; + wire [instr_width_gp-1:0] commit_instr_li = commit_pkt_r.instr; + wire commit_ird_w_v_li = instret_v_li & decode_r.irf_w_v; + wire commit_frd_w_v_li = instret_v_li & decode_r.frf_w_v; + wire commit_req_v_li = instret_v_li & cache_req_v_r; + wire trap_v_li = commit_pkt_r.exception | commit_pkt_r._interrupt; + wire [dword_width_gp-1:0] cause_li = (priv_mode_i == `PRIV_MODE_M) ? mcause_i : scause_i; + wire [dword_width_gp-1:0] mstatus_li = mstatus_i; + wire commit_fifo_v_li = instret_v_li | trap_v_li; + bsg_async_fifo + #(.width_p(3+vaddr_width_p+instr_width_gp+3+2*dword_width_gp), .lg_size_p(10)) + commit_fifo + (.w_clk_i(posedge_clk) + ,.w_reset_i(reset_i) + ,.w_enq_i(commit_fifo_v_li & ~commit_fifo_full_lo) + ,.w_data_i({is_debug_mode_r, instret_v_li, trap_v_li, commit_pc_li, commit_instr_li, commit_ird_w_v_li, commit_frd_w_v_li, commit_req_v_li, cause_li, mstatus_li}) + ,.w_full_o(commit_fifo_full_lo) + + ,.r_clk_i(cosim_clk_i) + ,.r_reset_i(cosim_reset_i) + ,.r_deq_i(commit_fifo_v_lo & commit_fifo_yumi_li) + ,.r_data_o({commit_debug_r, instret_v_r, trap_v_r, commit_pc_r, commit_instr_r, commit_ird_w_v_r, commit_frd_w_v_r, commit_req_v_r, cause_r, mstatus_r}) + ,.r_valid_o(commit_fifo_v_lo) + ); + + localparam rf_els_lp = 2**reg_addr_width_gp; + bp_be_fp_reg_s [rf_els_lp-1:0] frd_data_r; + bp_be_int_reg_s [rf_els_lp-1:0] ird_data_r; + logic [rf_els_lp-1:0] ird_fifo_v_lo, frd_fifo_v_lo; + logic [rf_els_lp-1:0][int_rec_width_gp-1:0] ird_raw_li; + logic [rf_els_lp-1:0][dp_rec_width_gp-1:0] frd_raw_li; + + for (genvar i = 0; i < rf_els_lp; i++) + begin : iwb + wire fill = ird_w_v_i & (ird_addr_i == i); + wire deallocate = commit_ird_w_v_r & (commit_instr_r.rd_addr == i) & commit_fifo_yumi_li; + bsg_async_fifo + #(.width_p(dpath_width_gp), .lg_size_p(10)) + ird_fifo + (.w_clk_i(posedge_clk) + ,.w_reset_i(reset_i) + ,.w_enq_i(fill) + ,.w_data_i(ird_data_i) + ,.w_full_o() + + ,.r_clk_i(cosim_clk_i) + ,.r_reset_i(cosim_reset_i) + ,.r_deq_i(deallocate) + ,.r_data_o(ird_data_r[i]) + ,.r_valid_o(ird_fifo_v_lo[i]) + ); + + logic [dpath_width_gp-1:0] ird_data_lo; + bp_be_int_unbox + #(.bp_params_p(bp_params_p)) + int_unbox + (.reg_i(ird_data_r[i]) + ,.tag_i(e_int_dword) + ,.unsigned_i(1'b0) + ,.val_o(ird_raw_li[i]) + ); + end + + for (genvar i = 0; i < rf_els_lp; i++) + begin : fwb + wire fill = frd_w_v_i & (frd_addr_i == i); + wire deallocate = commit_frd_w_v_r & (commit_instr_r.rd_addr == i) & commit_fifo_yumi_li; + bsg_async_fifo + #(.width_p(dpath_width_gp), .lg_size_p(10)) + frd_fifo + (.w_clk_i(posedge_clk) + ,.w_reset_i(reset_i) + ,.w_enq_i(fill) + ,.w_data_i(frd_data_i) + ,.w_full_o() + + ,.r_clk_i(cosim_clk_i) + ,.r_reset_i(cosim_reset_i) + ,.r_deq_i(deallocate) + ,.r_data_o(frd_data_r[i]) + ,.r_valid_o(frd_fifo_v_lo[i]) + ); + + bp_be_fp_unbox + #(.bp_params_p(bp_params_p)) + fp_unbox + (.reg_i(frd_data_r[i]) + ,.tag_i(frd_data_r[i].tag) + ,.raw_i(1'b1) + ,.val_o(frd_raw_li[i]) + ); + end + + wire commit_ird_v_lo = ird_fifo_v_lo[commit_instr_r.rd_addr]; + wire commit_frd_v_lo = frd_fifo_v_lo[commit_instr_r.rd_addr]; + + // We don't need to cross domains explicitly here, because using the slower clock is conservative + logic [`BSG_WIDTH(128)-1:0] req_cnt_lo; + bsg_counter_up_down + #(.max_val_p(128), .init_val_p(0), .max_step_p(1)) + req_counter + (.clk_i(negedge_clk) + ,.reset_i(reset_i) + + ,.up_i(cache_req_v_r) + ,.down_i(cache_req_complete_r) + + ,.count_o(req_cnt_lo) + ); + wire req_v_lo = ~cache_req_v_r & (req_cnt_lo == '0); + + assign commit_fifo_yumi_li = commit_fifo_v_lo & ((~commit_ird_w_v_r | commit_ird_v_lo) + & (~commit_frd_w_v_r | commit_frd_v_lo) + & (~commit_req_v_r | req_v_lo) + ); + wire commit_iwb_li = commit_fifo_v_lo & (commit_ird_w_v_r & ird_fifo_v_lo[commit_instr_r.rd_addr]); + wire commit_fwb_li = commit_fifo_v_lo & (commit_frd_w_v_r & frd_fifo_v_lo[commit_instr_r.rd_addr]); + + chandle cosim_handle; + initial cosim_handle = cosim_init(mhartid_i, num_core_p, checkpoint_i); + + wire [dword_width_gp-1:0] cosim_pc_li = `BSG_SIGN_EXTEND(commit_pc_r, dword_width_gp); + wire [instr_width_gp-1:0] cosim_instr_li = commit_instr_r; + wire [dword_width_gp-1:0] cosim_cause_li = cause_r; + wire [dpath_width_gp-1:0] cosim_ireg_li = ird_data_r[commit_instr_r.rd_addr]; + wire [dword_width_gp-1:0] cosim_ird_li = ird_raw_li[commit_instr_r.rd_addr]; + wire [dpath_width_gp-1:0] cosim_freg_li = frd_data_r[commit_instr_r.rd_addr]; + wire [dword_width_gp-1:0] cosim_frd_li = frd_raw_li[commit_instr_r.rd_addr]; + wire [dword_width_gp-1:0] cosim_rd_li = commit_fwb_li ? cosim_frd_li : cosim_ird_li; + wire [dword_width_gp-1:0] cosim_status_li = mstatus_r; + integer ret_code; + always_ff @(posedge cosim_clk_i) + if (cosim_reset_i || commit_debug_r || !commit_pc_r) + ret_code <= 0; + else if (commit_fifo_yumi_li & trap_v_r) + ret_code <= cosim_trap(cosim_handle, mhartid_i, cosim_pc_li, cosim_instr_li, cosim_rd_li, cosim_status_li, cosim_cause_li); + else if (commit_fifo_yumi_li & instret_v_r) + ret_code <= cosim_step(cosim_handle, mhartid_i, cosim_pc_li, cosim_instr_li, cosim_rd_li, cosim_status_li, cosim_cause_li); + + // ret_code: {exit_code, terminate} + logic terminate; + always_ff @(negedge cosim_clk_i) + if (ret_code) + begin + $display("[BSG-FAIL] co-simulation failure: exit code: %d", (ret_code >> 1)); + $finish(); + end + else if (commit_fifo_v_li & commit_fifo_full_lo) + begin + $display("[BSG-FAIL] co-simulation fifo overrun, core %x", mhartid_i); + $finish(); + end + + // final + final begin + if (!reset_i) cosim_finish(cosim_handle); + end + + // Commit trace + integer file; + string file_name; + always_ff @(negedge reset_i) + begin + file_name = $sformatf("%s_%x.trace", commit_trace_file_p, mhartid_i); + file = $fopen(file_name, "w"); + end + + logic [`BSG_SAFE_CLOG2(max_instr_lp+1)-1:0] instr_cnt; + always_ff @(posedge cosim_clk_i) + if (trace_en_i & commit_fifo_yumi_li & commit_pc_r != '0) + begin + instr_cnt <= instr_cnt + 1'b1; + $fwrite(file, "%x %x %x %x ", mhartid_i, cosim_pc_li, cosim_instr_li, instr_cnt); + if (instret_v_r & commit_ird_w_v_r) + $fwrite(file, "%x %x", commit_instr_r.rd_addr, cosim_ird_li); + if (instret_v_r & commit_frd_w_v_r) + $fwrite(file, "%x %x", commit_instr_r.rd_addr, cosim_frd_li); + if (trap_v_r) + $fwrite(file, " %x %x <- trap", cause_r, mstatus_r); + $fwrite(file, "\n"); + end + + // final + final begin + $fclose(file); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_dram.sv b/designs/black-parrot/src/bp/bp_nonsynth_dram.sv new file mode 100644 index 0000000..0d75a6e --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_dram.sv @@ -0,0 +1,370 @@ + +/** + * bp_nonsynth_dram.v + */ + +`define dram_pkg bsg_dramsim3_lpddr3_8gb_x32_1600_pkg + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_nonsynth_dram + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_axi_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , parameter num_dma_p = 0 + , parameter preload_mem_p = 0 + , parameter mem_bytes_p = 0 + , parameter dram_type_p = "" + , localparam dma_pkt_width_lp = `bsg_cache_dma_pkt_width(daddr_width_p, l2_block_size_in_words_p) + ) + (input clk_i + , input reset_i + + , input [num_dma_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_i + , input [num_dma_p-1:0] dma_pkt_v_i + , output logic [num_dma_p-1:0] dma_pkt_yumi_o + + , output logic [num_dma_p-1:0][l2_fill_width_p-1:0] dma_data_o + , output logic [num_dma_p-1:0] dma_data_v_o + , input [num_dma_p-1:0] dma_data_ready_and_i + + , input [num_dma_p-1:0][l2_fill_width_p-1:0] dma_data_i + , input [num_dma_p-1:0] dma_data_v_i + , output logic [num_dma_p-1:0] dma_data_yumi_o + + , input dram_clk_i + , input dram_reset_i + ); + + import "DPI-C" context function + void bsg_mem_dma_set(chandle handle, longint unsigned addr, byte val); + + if (dram_type_p == "dramsim3") + begin : dramsim3 + `dram_pkg::dram_ch_addr_s dram_read_done_ch_addr_lo; + + logic [`dram_pkg::channel_addr_width_p-1:0] dram_ch_addr_li; + logic dram_write_not_read_li, dram_v_li, dram_yumi_lo; + logic [`dram_pkg::data_width_p-1:0] dram_data_li; + logic [(`dram_pkg::data_width_p>>3)-1:0] dram_mask_li; + + logic dram_data_v_li, dram_data_yumi_lo; + logic [`dram_pkg::data_width_p-1:0] dram_data_lo; + logic dram_data_v_lo; + + if (num_dma_p & (num_dma_p-1) != 0) + begin : npot + $error("bsg_cache_to_test_dram doesn't support NPOT number of caches. Use AXI mem instead"); + end + + // TODO: May need to use actual hash function + localparam dram_channel_addr_width_lp = `dram_pkg::channel_addr_width_p; + localparam cache_bank_addr_width_lp = dram_channel_addr_width_lp - `BSG_SAFE_CLOG2(num_dma_p); + bsg_cache_to_test_dram + #(.num_cache_p(num_dma_p) + ,.addr_width_p(daddr_width_p) + ,.data_width_p(l2_data_width_p) + ,.block_size_in_words_p(l2_block_size_in_words_p) + ,.cache_bank_addr_width_p(cache_bank_addr_width_lp) + ,.dma_data_width_p(l2_fill_width_p) + + ,.dram_channel_addr_width_p(`dram_pkg::channel_addr_width_p) + ,.dram_data_width_p(`dram_pkg::data_width_p) + ) + cache_to_tram + (.core_clk_i(clk_i) + ,.core_reset_i(reset_i) + + ,.dma_pkt_i(dma_pkt_i) + ,.dma_pkt_v_i(dma_pkt_v_i) + ,.dma_pkt_yumi_o(dma_pkt_yumi_o) + + ,.dma_data_o(dma_data_o) + ,.dma_data_v_o(dma_data_v_o) + ,.dma_data_ready_and_i(dma_data_ready_and_i) + + ,.dma_data_i(dma_data_i) + ,.dma_data_v_i(dma_data_v_i) + ,.dma_data_yumi_o(dma_data_yumi_o) + + ,.dram_clk_i(dram_clk_i) + ,.dram_reset_i(dram_reset_i) + + ,.dram_req_v_o(dram_v_li) + ,.dram_write_not_read_o(dram_write_not_read_li) + ,.dram_ch_addr_o(dram_ch_addr_li) + ,.dram_req_yumi_i(dram_yumi_lo) + ,.dram_data_v_o(dram_data_v_li) + ,.dram_data_o(dram_data_li) + ,.dram_mask_o(dram_mask_li) + ,.dram_data_yumi_i(dram_data_yumi_lo) + + ,.dram_data_v_i(dram_data_v_lo) + ,.dram_data_i(dram_data_lo) + ,.dram_ch_addr_i(dram_read_done_ch_addr_lo) + ); + + bsg_nonsynth_dramsim3 + #(.channel_addr_width_p(`dram_pkg::channel_addr_width_p) + ,.data_width_p(`dram_pkg::data_width_p) + ,.num_channels_p(`dram_pkg::num_channels_p) + ,.num_columns_p(`dram_pkg::num_columns_p) + ,.num_rows_p(`dram_pkg::num_rows_p) + ,.num_ba_p(`dram_pkg::num_ba_p) + ,.num_bg_p(`dram_pkg::num_bg_p) + ,.num_ranks_p(`dram_pkg::num_ranks_p) + ,.address_mapping_p(`dram_pkg::address_mapping_p) + ,.size_in_bits_p(`dram_pkg::size_in_bits_p) + ,.config_p(`dram_pkg::config_p) + ,.masked_p(l2_features_p[e_cfg_word_tracking]) + ,.init_mem_p(1) + ,.base_id_p(0) + ) + dram + (.clk_i(dram_clk_i) + ,.reset_i(dram_reset_i) + + ,.v_i(dram_v_li) + ,.write_not_read_i(dram_write_not_read_li) + ,.ch_addr_i(dram_ch_addr_li) + ,.mask_i(dram_mask_li) + ,.yumi_o(dram_yumi_lo) + + ,.data_v_i(dram_data_v_li) + ,.data_i(dram_data_li) + ,.data_yumi_o(dram_data_yumi_lo) + + ,.data_v_o(dram_data_v_lo) + ,.data_o(dram_data_lo) + ,.read_done_ch_addr_o(dram_read_done_ch_addr_lo) + + ,.write_done_o() + ,.write_done_ch_addr_o() + ,.print_stat_clk_i('0) + ,.print_stat_reset_i('0) + ,.print_stat_v_i('0) + ,.print_stat_tag_i('0) + ); + + // This whole segment is unoptimized because it's storing this memory even though it's + // only used for initialization. We could read byte-by-byte to avoid this + logic [7:0] preload_mem [integer]; + logic [dram_channel_addr_width_lp-1:0] ch_addr_li; + logic [7:0] ch_data_li; + localparam lg_num_l2_slices_lp = `BSG_SAFE_CLOG2(l2_slices_p); + localparam lg_num_l2_banks_lp = `BSG_SAFE_CLOG2(l2_banks_p); + localparam lg_num_dma_lp = `BSG_SAFE_CLOG2(num_dma_p); + logic [paddr_width_p-1:0] preload_addr_li; + logic [`BSG_SAFE_CLOG2(l2_slices_p)-1:0] preload_slice_lo; + logic [`BSG_SAFE_CLOG2(l2_banks_p)-1:0] preload_bank_lo; + logic [`BSG_SAFE_CLOG2(l2_banks_p*l2_slices_p)-1:0] preload_dma_lo; + assign ch_addr_li = {preload_dma_lo + ,{(dram_channel_addr_width_lp-cache_bank_addr_width_lp-lg_num_dma_lp){1'b0}} + ,preload_addr_li[cache_bank_addr_width_lp-1:0] + }; + initial + if (preload_mem_p) begin + $readmemh("prog.mem", preload_mem); + foreach (preload_mem[i]) begin + preload_addr_li = dram_base_addr_gp+i; + ch_data_li = preload_mem[i]; + #1; + bsg_mem_dma_set( + dram.channels[0].channel.memory, ch_addr_li, ch_data_li + ); + end + end + + bp_me_dram_hash_encode + #(.bp_params_p(bp_params_p)) + dma_hash + (.paddr_i(preload_addr_li) + ,.data_i() + ,.daddr_o() + ,.slice_o(preload_slice_lo) + ,.bank_o(preload_bank_lo) + ,.dram_o() + ,.data_o() + ); + assign preload_dma_lo = preload_slice_lo*l2_slices_p + preload_bank_lo; + end + else if (dram_type_p == "axi") + begin : axi + localparam axi_id_width_p = 6; + localparam axi_addr_width_p = 64; + localparam axi_data_width_p = l2_fill_width_p; + localparam axi_strb_width_p = axi_data_width_p >> 3; + localparam axi_burst_len_p = l2_block_width_p / l2_fill_width_p; + + localparam mem_els_lp = mem_bytes_p/(axi_data_width_p/8); + + logic [axi_id_width_p-1:0] axi_awid; + logic [caddr_width_p-1:0] axi_awaddr_addr; + logic axi_awaddr_addr_unused; + logic [`BSG_SAFE_CLOG2(num_dma_p)-1:0] axi_awaddr_cache_id; + logic [7:0] axi_awlen; + logic [2:0] axi_awsize; + logic [1:0] axi_awburst; + logic [3:0] axi_awcache; + logic [2:0] axi_awprot; + logic axi_awlock, axi_awvalid, axi_awready; + + logic [axi_data_width_p-1:0] axi_wdata; + logic [axi_strb_width_p-1:0] axi_wstrb; + logic axi_wlast, axi_wvalid, axi_wready; + + logic [axi_id_width_p-1:0] axi_bid; + logic [1:0] axi_bresp; + logic axi_bvalid, axi_bready; + + logic [axi_id_width_p-1:0] axi_arid; + logic [caddr_width_p-1:0] axi_araddr_addr; + logic axi_araddr_addr_unused; + logic [`BSG_SAFE_CLOG2(num_dma_p)-1:0] axi_araddr_cache_id; + logic [7:0] axi_arlen; + logic [2:0] axi_arsize; + logic [1:0] axi_arburst; + logic [3:0] axi_arcache; + logic [2:0] axi_arprot; + logic axi_arlock, axi_arvalid, axi_arready; + + logic [axi_id_width_p-1:0] axi_rid; + logic [axi_data_width_p-1:0] axi_rdata; + logic [1:0] axi_rresp; + logic axi_rlast, axi_rvalid, axi_rready; + + bsg_cache_to_axi + #(.addr_width_p(daddr_width_p) + ,.data_width_p(l2_fill_width_p) + ,.mask_width_p(l2_block_size_in_words_p) + ,.block_size_in_words_p(l2_block_size_in_fill_p) + ,.num_cache_p(num_dma_p) + ,.axi_id_width_p(axi_id_width_p) + ,.axi_data_width_p(axi_data_width_p) + ,.axi_burst_len_p(axi_burst_len_p) + ,.axi_burst_type_p(e_axi_burst_wrap) + ,.ordering_en_p(1) + ) + cache2axi + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.dma_pkt_i(dma_pkt_i) + ,.dma_pkt_v_i(dma_pkt_v_i) + ,.dma_pkt_yumi_o(dma_pkt_yumi_o) + + ,.dma_data_o(dma_data_o) + ,.dma_data_v_o(dma_data_v_o) + ,.dma_data_ready_and_i(dma_data_ready_and_i) + + ,.dma_data_i(dma_data_i) + ,.dma_data_v_i(dma_data_v_i) + ,.dma_data_yumi_o(dma_data_yumi_o) + + ,.axi_awid_o(axi_awid) + ,.axi_awaddr_addr_o({axi_awaddr_addr_unused, axi_awaddr_addr}) + ,.axi_awaddr_cache_id_o(axi_awaddr_cache_id) + ,.axi_awlen_o(axi_awlen) + ,.axi_awsize_o(axi_awsize) + ,.axi_awburst_o(axi_awburst) + ,.axi_awcache_o(axi_awcache) + ,.axi_awprot_o(axi_awprot) + ,.axi_awlock_o(axi_awlock) + ,.axi_awvalid_o(axi_awvalid) + ,.axi_awready_i(axi_awready) + + ,.axi_wdata_o(axi_wdata) + ,.axi_wstrb_o(axi_wstrb) + ,.axi_wlast_o(axi_wlast) + ,.axi_wvalid_o(axi_wvalid) + ,.axi_wready_i(axi_wready) + + ,.axi_bid_i(axi_bid) + ,.axi_bresp_i(axi_bresp) + ,.axi_bvalid_i(axi_bvalid) + ,.axi_bready_o(axi_bready) + ,.axi_arid_o(axi_arid) + ,.axi_araddr_addr_o({axi_araddr_addr_unused, axi_araddr_addr}) + ,.axi_araddr_cache_id_o(axi_araddr_cache_id) + ,.axi_arlen_o(axi_arlen) + ,.axi_arsize_o(axi_arsize) + ,.axi_arburst_o(axi_arburst) + ,.axi_arcache_o(axi_arcache) + ,.axi_arprot_o(axi_arprot) + ,.axi_arlock_o(axi_arlock) + ,.axi_arvalid_o(axi_arvalid) + ,.axi_arready_i(axi_arready) + + ,.axi_rid_i(axi_rid) + ,.axi_rdata_i(axi_rdata) + ,.axi_rresp_i(axi_rresp) + ,.axi_rlast_i(axi_rlast) + ,.axi_rvalid_i(axi_rvalid) + ,.axi_rready_o(axi_rready) + ); + + wire [axi_addr_width_p-1:0] axi_araddr = {axi_araddr_cache_id, (axi_araddr_addr-dram_base_addr_gp)}; + wire [axi_addr_width_p-1:0] axi_awaddr = {axi_awaddr_cache_id, (axi_awaddr_addr-dram_base_addr_gp)}; + + bsg_nonsynth_axi_mem + #(.axi_id_width_p(axi_id_width_p) + ,.axi_addr_width_p(axi_addr_width_p) + ,.axi_data_width_p(axi_data_width_p) + ,.axi_len_width_p(8) + ,.mem_els_p(mem_els_lp) + ,.init_data_p('0) + ) + axi_mem + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.axi_awid_i(axi_awid) + ,.axi_awaddr_i(axi_awaddr) + ,.axi_awvalid_i(axi_awvalid) + ,.axi_awready_o(axi_awready) + ,.axi_awburst_i(axi_awburst) + ,.axi_awlen_i(axi_awlen) + + ,.axi_wdata_i(axi_wdata) + ,.axi_wstrb_i(axi_wstrb) + ,.axi_wlast_i(axi_wlast) + ,.axi_wvalid_i(axi_wvalid) + ,.axi_wready_o(axi_wready) + + ,.axi_bid_o(axi_bid) + ,.axi_bresp_o(axi_bresp) + ,.axi_bvalid_o(axi_bvalid) + ,.axi_bready_i(axi_bready) + + ,.axi_arid_i(axi_arid) + ,.axi_araddr_i(axi_araddr) + ,.axi_arvalid_i(axi_arvalid) + ,.axi_arready_o(axi_arready) + ,.axi_arburst_i(axi_arburst) + ,.axi_arlen_i(axi_arlen) + + ,.axi_rid_o(axi_rid) + ,.axi_rdata_o(axi_rdata) + ,.axi_rresp_o(axi_rresp) + ,.axi_rlast_o(axi_rlast) + ,.axi_rvalid_o(axi_rvalid) + ,.axi_rready_i(axi_rready) + ); + + if (preload_mem_p) + begin : preload + $error("Preloading is not supported for AXI"); + end + end + else + begin : no_mem + $error("Must select dram_type as either dramsim3, dmc, or axi"); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_host.sv b/designs/black-parrot/src/bp/bp_nonsynth_host.sv new file mode 100644 index 0000000..f9abd42 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_host.sv @@ -0,0 +1,195 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_nonsynth_host + import bp_common_pkg::*; + import bp_be_pkg::*; + import bsg_noc_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , parameter icache_trace_p = 0 + , parameter dcache_trace_p = 0 + , parameter lce_trace_p = 0 + , parameter cce_trace_p = 0 + , parameter dram_trace_p = 0 + , parameter vm_trace_p = 0 + , parameter cmt_trace_p = 0 + , parameter core_profile_p = 0 + , parameter pc_gen_trace_p = 0 + , parameter pc_profile_p = 0 + , parameter br_profile_p = 0 + , parameter cosim_p = 0 + , parameter dev_trace_p = 0 + ) + (input clk_i + , input reset_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + ); + + import "DPI-C" context function int getchar(); + + integer tmp; + integer stdout[num_core_p]; + integer stdout_global; + integer signature; + + always_ff @(negedge reset_i) + begin + for (integer j = 0; j < num_core_p; j++) + begin + tmp = $fopen($sformatf("stdout_%0x.txt", j), "w"); + stdout[j] = tmp; + end + stdout_global = $fopen("stdout_global.txt", "w"); + signature = $fopen("DUT-blackparrot.signature", "w"); + end + + localparam bedrock_reg_els_lp = 8; + logic putint_r_v_li, signature_r_v_li, paramrom_r_v_li, bootrom_r_v_li, finish_r_v_li, getchar_r_v_li, putchar_r_v_li, putch_core_r_v_li; + logic putint_w_v_li, signature_w_v_li, paramrom_w_v_li, bootrom_w_v_li, finish_w_v_li, getchar_w_v_li, putchar_w_v_li, putch_core_w_v_li; + logic [dev_addr_width_gp-1:0] addr_lo; + logic [`BSG_WIDTH(`BSG_SAFE_CLOG2(dword_width_gp/8))-1:0] size_lo; + logic [dword_width_gp-1:0] data_lo; + logic [bedrock_reg_els_lp-1:0][dword_width_gp-1:0] data_li; + bp_me_bedrock_register + #(.bp_params_p(bp_params_p) + ,.reg_data_width_p(dword_width_gp) + ,.reg_addr_width_p(dev_addr_width_gp) + ,.els_p(bedrock_reg_els_lp) + ,.base_addr_p({putint_match_addr_gp, signature_match_addr_gp, paramrom_match_addr_gp, bootrom_match_addr_gp, finish_match_addr_gp, getchar_match_addr_gp, putchar_match_addr_gp, putch_core_match_addr_gp}) + ) + register + (.* + ,.r_v_o({putint_r_v_li, signature_r_v_li, paramrom_r_v_li, bootrom_r_v_li, finish_r_v_li, getchar_r_v_li, putchar_r_v_li, putch_core_r_v_li}) + ,.w_v_o({putint_w_v_li, signature_w_v_li, paramrom_w_v_li, bootrom_w_v_li, finish_w_v_li, getchar_w_v_li, putchar_w_v_li, putch_core_w_v_li}) + ,.addr_o(addr_lo) + ,.size_o(size_lo) + ,.data_o(data_lo) + ,.data_i(data_li) + ); + localparam byte_offset_width_lp = 3; + localparam lg_num_core_lp = `BSG_SAFE_CLOG2(num_core_p); + wire [lg_num_core_lp-1:0] addr_core_enc = addr_lo[byte_offset_width_lp+:lg_num_core_lp]; + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + bp_bedrock_mem_fwd_header_s mem_fwd_header_li; + assign mem_fwd_header_li = mem_fwd_header_i; + wire [hio_width_p-1:0] hio_id = mem_fwd_header_li.addr[paddr_width_p-1-:hio_width_p]; + always_comb + if (mem_fwd_v_i & (hio_id != '0)) + $display("[BSG-WARNING]: Accessing hio %0h. Sending loopback message!", hio_id); + + // for some reason, VCS doesn't like finish_w_v_li << addr_core_enc + wire [num_core_p-1:0] finish_set = finish_w_v_li ? (1'b1 << addr_core_enc) : 1'b0; + logic [num_core_p-1:0] finish_r; + bsg_dff_reset_set_clear + #(.width_p(num_core_p)) + finish_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.set_i(finish_set) + ,.clear_i('0) + ,.data_o(finish_r) + ); + + integer ret; + logic [7:0] ch; + always_ff @(negedge clk_i) + begin + if (putchar_w_v_li) begin + $write("%c", data_lo[0+:8]); + $fwrite(stdout_global, "%c", data_lo[0+:8]); + end + + if (putch_core_w_v_li) begin + $write("%c", data_lo[0+:8]); + $fwrite(stdout[addr_core_enc], "%c", data_lo[0+:8]); + end + + if (putint_w_v_li) begin + $write("%x", data_lo[0+:dword_width_gp]); + end + + if (getchar_r_v_li) begin + ch <= getchar(); + end + + if (mem_fwd_ready_and_o & mem_fwd_v_i & (hio_id != '0)) + $error("Warning: Accesing illegal hio %0h. Sending loopback message!", hio_id); + for (integer i = 0; i < num_core_p; i++) + begin + // PASS when returned value in finish packet is zero + if (finish_set[i] & (data_lo[0+:8] == 8'(0))) + $display("[BSG-INFO]: CORE%0x FINISH PASS", i); + // FAIL when returned value in finish packet is non-zero + if (finish_set[i] & (data_lo[0+:8] != 8'(0))) + begin + $display("[BSG-FAIL]: CORE%0x FINISH FAIL", i); + $finish(); + end + + end + + if (signature_w_v_li) + $fwrite(signature, "%8x\n", data_lo[0+:32]); + + if (putint_w_v_li) begin + $write("%x", data_lo); + end + + if (&finish_r) + begin + $display("[BSG-PASS]: All cores finished! Terminating..."); + $finish(); + end + end + + final + begin + $fclose(signature); + $fclose(stdout_global); + for (integer j = 0; j < num_core_p; j++) + $fclose(stdout[j]); + $system("stty echo"); + end + + localparam param_els_lp = `BSG_CDIV($bits(proc_param_lp),word_width_gp); + localparam lg_param_els_lp = `BSG_SAFE_CLOG2(param_els_lp); + logic [lg_param_els_lp-1:0] paramrom_addr_li; + logic [word_width_gp-1:0] paramrom_data_lo; + // Reverse address to index in reverse struct order + assign paramrom_addr_li = param_els_lp-1'b1-addr_lo[2+:lg_param_els_lp]; + bsg_rom_param + #(.data_p(proc_param_lp) + ,.data_width_p($bits(proc_param_lp)) + ,.width_p(word_width_gp) + ,.els_p(param_els_lp) + ) + param_rom + (.addr_i(paramrom_addr_li) + ,.data_o(paramrom_data_lo) + ); + wire [bedrock_block_width_p-1:0] paramrom_final_lo = {bedrock_block_width_p/word_width_gp{paramrom_data_lo}}; + + assign data_li[0] = '0; + assign data_li[1] = '0; + assign data_li[2] = ch; + assign data_li[3] = finish_r; + assign data_li[4] = '0; + assign data_li[5] = paramrom_final_lo; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_if_verif.sv b/designs/black-parrot/src/bp/bp_nonsynth_if_verif.sv new file mode 100644 index 0000000..d153e2b --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_if_verif.sv @@ -0,0 +1,167 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" +`include "bp_fe_defines.svh" + +module bp_nonsynth_if_verif + import bp_common_pkg::*; + import bp_fe_pkg::*; + import bp_be_pkg::*; + import bsg_noc_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (); + + bp_proc_param_s proc_param; + assign proc_param = all_cfgs_gp[bp_params_p]; + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_fe_branch_metadata_fwd_s(ras_idx_width_p, btb_tag_width_p, btb_idx_width_p, bht_idx_width_p, ghist_width_p, bht_row_els_p); + + initial + begin + $display("########### BP Parameters ##############"); + // This throws an std::length_error in Verilator 4.031 based on the length of + // this (admittedly massive) parameter + `ifndef VERILATOR + $display("bp_params_e %s: bp_proc_param_s %p", bp_params_p.name(), proc_param); + `endif + $display("########### TOP IF ##############"); + $display("bp_cfg_bus_s bits: struct %d width %d", $bits(bp_cfg_bus_s), cfg_bus_width_lp); + + $display("########### FE-BE IF ##############"); + $display("bp_fe_queue_s bits: struct %d width %d", $bits(bp_fe_queue_s), fe_queue_width_lp); + $display("bp_fe_cmd_s bits: struct %d width %d", $bits(bp_fe_cmd_s), fe_cmd_width_lp); + + $display("########### LCE-CCE IF ##############"); + $display("bp_bedrock_lce_req_header_s bits: struct %d width %d", $bits(bp_bedrock_lce_req_header_s), lce_req_header_width_lp); + $display("bp_bedrock_lce_cmd_header_s bits: struct %d width %d", $bits(bp_bedrock_lce_cmd_header_s), lce_cmd_header_width_lp); + $display("bp_bedrock_lce_fill_header_s bits: struct %d width %d", $bits(bp_bedrock_lce_fill_header_s), lce_fill_header_width_lp); + $display("bp_bedrock_lce_resp_header_s bits: struct %d width %d", $bits(bp_bedrock_lce_resp_header_s), lce_resp_header_width_lp); + + $display("########### CCE-MEM IF ##############"); + $display("bp_bedrock_mem_fwd_header_s bits: struct %d width %d", $bits(bp_bedrock_mem_fwd_header_s), mem_fwd_header_width_lp); + $display("bp_bedrock_mem_rev_header_s bits: struct %d width %d", $bits(bp_bedrock_mem_rev_header_s), mem_rev_header_width_lp); + + if (!(num_cce_p inside {1,2,3,4,6,7,8,12,14,15,16,24,28,30,31,32})) begin + $error("Error: unsupported number of CCE's"); + end + + end + + // General + if (mc_y_dim_p > 2) + $error("Error: Multi-row L2 expansion nodes not yet supported"); + if (sac_x_dim_p > 1) + $error("Error: Must have <= 1 column of streaming accelerators"); + if (cac_x_dim_p > 1) + $error("Error: Must have <= 1 column of coherent accelerators"); + if (dword_width_gp != 64) + $error("Error: BlackParrot is only tested with 64-bit dword width"); + + // Front End + + + // Core or Features + if (!muldiv_support_p[e_imul]) + $error("IMUL is not currently support in emulation"); + if (!muldiv_support_p[e_idiv]) + $error("IDIV is not currently support in emulation"); + if (!fpu_support_p) + $error("FPU cannot currently be disabled"); + if (branch_metadata_fwd_width_p != $bits(bp_fe_branch_metadata_fwd_s)) + $error("Branch metadata width: %d != width of branch metadata struct: %d", branch_metadata_fwd_width_p, $bits(bp_fe_branch_metadata_fwd_s)); + if (~|{dcache_features_p[e_cfg_lr_sc], l2_features_p[e_cfg_lr_sc]}) + $warning("Warning: Atomics cannot be emulated without LR/SC. Those instructions will fail"); + + // L1 Caches + if ((bedrock_block_width_p == 256) && (dcache_assoc_p == 8 || icache_assoc_p == 8)) + $error("Error: We can't maintain 64-bit dwords with a 256-bit cache block size and 8-way cache associativity"); + if ((bedrock_block_width_p == 128) && (dcache_assoc_p == 4 || dcache_assoc_p == 8 || icache_assoc_p == 4 || icache_assoc_p == 8)) + $error("Error: We can't maintain 64-bit dwords with a 128-bit cache block size and 4-way or 8-way cache associativity"); + if ((dcache_features_p[e_cfg_writeback] == 0) && (dcache_features_p[e_cfg_coherent] == 1)) + $error("Error: Writethrough with coherent_l1 is unsupported"); + if ((icache_fill_width_p > icache_block_width_p) || (dcache_fill_width_p > dcache_block_width_p)) + $error("Error: Cache fill width should be less or equal to L1 cache block width"); + if ((icache_fill_width_p % (icache_block_width_p/icache_assoc_p) != 0) || (dcache_fill_width_p % (dcache_block_width_p / dcache_assoc_p) != 0)) + $error("Error: Cache fill width should be a multiple of cache bank width"); + if (icache_fill_width_p != dcache_fill_width_p) + $error("Error: L1-Cache fill width should be the same"); + if (icache_fill_width_p < (icache_block_width_p / icache_assoc_p)) + $error("Error: L1 I$ requires fill width greater than bank width (block width / assoc)"); + if (dcache_fill_width_p < (dcache_block_width_p / dcache_assoc_p)) + $error("Error: L1 D$ requires fill width greater than bank width (block width / assoc)"); + if (icache_mshr_p != 1 && dcache_mshr_p !=1 || acache_mshr_p != 1) + $error("MSHR must be 1 for all caches"); + + // Address Widths + if (vaddr_width_p != 39) + $warning("Warning: VM will not work without 39 bit vaddr"); + if (paddr_width_p > 56) + $warning("Warning: paddr > 56 has not been tested"); + if (paddr_width_p < 33) + $warning("Warning: paddr < 33 has not been tested"); + if (daddr_width_p < 32) + $warning("Warning: daddr < 32 has not been tested"); + if (caddr_width_p < 31) + $warning("Warning: caddr < 31 has not been tested"); + if (caddr_width_p >= daddr_width_p) + $warning("Warning: caddr must <= daddr"); + if (daddr_width_p >= paddr_width_p) + $error("Error: caddr cannot exceed paddr_width_p-1"); + + // L2 Cache + if (l2_fill_width_p < l2_data_width_p) + $error("Error: L2 fill width must be at least as large as L2 data width"); + if (l2_block_width_p > 1024) + $error("Error: L2 block width must be less than 1024"); + if (!`BSG_IS_POW2((l2_fill_width_p/l2_data_width_p))) + $error("Error: L2 fill width must be POW2 multiple of L2 data width"); + if (!`BSG_IS_POW2(l2_dmas_p)) + $error("Error: L2 banks must be a power of two"); + + // Unicore + if ((cce_type_p == e_cce_uce) && (icache_fill_width_p != dcache_fill_width_p)) + $error("Error: unicore requires L1-Cache fill width to match"); + if ((cce_type_p == e_cce_uce) && (num_core_p != 1)) + $error("Error: Unicore only supports a single core configuration in the tethered testbench"); + if ((cce_type_p == e_cce_uce) && (bedrock_fill_width_p < dword_width_gp)) + $error("Error: Unicore requires UCE fill width to be at least dword width"); + + // Multicore + if ((cce_type_p != e_cce_uce) && (ic_y_dim_p != 1)) + $error("Error: Must have exactly 1 row of I/O routers for multicore"); + if ((cce_type_p != e_cce_uce) && (l2_data_width_p != bedrock_fill_width_p)) + $error("Error: Multicore requires L2 data width same as BedRock data width"); + if ((cce_type_p != e_cce_uce) && (icache_fill_width_p != dcache_fill_width_p)) + $error("Error: Multicore requires L1-Cache fill width to be the same"); + if ((cce_type_p != e_cce_uce) && (num_cacc_p > 0) && (icache_fill_width_p != acache_fill_width_p)) + $error("Error: Multicore requires L1-Cache fill width to be the same"); + if ((cce_type_p != e_cce_uce) && (dcache_block_width_p != icache_block_width_p)) + $error("Error: Multicore requires L1-Cache block width to be the same"); + if ((cce_type_p != e_cce_uce) && (num_cacc_p > 0) && (icache_block_width_p != acache_block_width_p)) + $error("Error: Multicore requires L1-Cache block width to be the same"); + if ((cce_type_p != e_cce_uce) && (l2_block_width_p < icache_block_width_p)) + $error("Error: Multicore requires L2-Cache block width to be at least L1-Cache block width"); + if ((cce_type_p != e_cce_uce) && (bedrock_fill_width_p < dword_width_gp)) + $error("Error: Multicore requires BedRock data width to be at least dword width"); + if ((cce_type_p != e_cce_uce) && (bedrock_fill_width_p > icache_fill_width_p)) + $error("Error: Multicore requires BedRock data width to be no larger than cache fill width"); + if ((cce_type_p != e_cce_uce) && l2_features_p[e_cfg_enabled] && (|{l2_features_p[e_cfg_lr_sc], l2_features_p[e_cfg_amo_swap], l2_features_p[e_cfg_amo_fetch_logic], l2_features_p[e_cfg_amo_fetch_arithmetic]})) + $error("Error: Multicore does not support L2 atomics"); + if ((cce_type_p != e_cce_uce) && (`BSG_SAFE_CLOG2(icache_block_width_p*icache_sets_p/8) > page_offset_width_gp) && (`BSG_SAFE_CLOG2(dcache_block_width_p*dcache_sets_p/8) > page_offset_width_gp)) + $error("Error: Multicore requires total cache size to be equal to 4kB * associativity"); + + if (num_cce_p/mc_x_dim_p*l2_dmas_p > 16) + $error("Round robin arbiter currently only supports 16 entries"); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_nbf_loader.sv b/designs/black-parrot/src/bp/bp_nonsynth_nbf_loader.sv new file mode 100644 index 0000000..bdb7e4a --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_nbf_loader.sv @@ -0,0 +1,201 @@ +/** + * bp_nonsynth_nbf_loader.v + * + */ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_nonsynth_nbf_loader + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , parameter nbf_filename_p = "prog.nbf" + , parameter verbose_p = 1 + ) + (input clk_i + , input reset_i + + , input [lce_id_width_p-1:0] lce_id_i + , input [did_width_p-1:0] did_i + + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + + , output logic done_o + ); + + // all messages are single beat + wire unused = &{mem_rev_data_i}; + + enum logic [2:0] { e_reset, e_send, e_fence, e_read, e_done} state_n, state_r; + wire is_reset = (state_r == e_reset); + wire is_send_nbf = (state_r == e_send); + wire is_fence = (state_r == e_fence); + wire is_read = (state_r == e_read); + wire is_done = (state_r == e_done); + + localparam max_nbf_index_lp = 2**25; + localparam nbf_index_width_lp = `BSG_SAFE_CLOG2(max_nbf_index_lp); + localparam nbf_data_width_lp = 64; + localparam nbf_addr_width_lp = nbf_data_width_lp; + localparam nbf_opcode_width_lp = 8; + typedef struct packed + { + logic [nbf_opcode_width_lp-1:0] opcode; + logic [nbf_addr_width_lp-1:0] addr; + logic [nbf_data_width_lp-1:0] data; + } bp_nbf_s; + + // read nbf file + bp_nbf_s nbf [max_nbf_index_lp-1:0]; + initial $readmemh(nbf_filename_p, nbf); + + bp_nbf_s curr_nbf; + logic [nbf_index_width_lp-1:0] nbf_index_r, nbf_index_n; + assign curr_nbf = nbf[nbf_index_r]; + + wire is_fence_packet = (curr_nbf.opcode == 8'hFE); + wire is_finish_packet = (curr_nbf.opcode == 8'hFF); + wire is_read_packet = (curr_nbf.opcode[5] == 1'b1) & ~is_fence_packet & ~is_finish_packet; + wire is_store_packet = (curr_nbf.opcode[5] == 1'b0) & ~is_fence_packet & ~is_finish_packet; + + wire next_nbf = (is_send_nbf && ((mem_fwd_ready_and_i & mem_fwd_v_o) || is_fence_packet || is_finish_packet)); + bsg_counter_clear_up + #(.max_val_p(max_nbf_index_lp-1), .init_val_p(0)) + nbf_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(1'b0) + ,.up_i(next_nbf) + ,.count_o(nbf_index_r) + ); + + localparam heartbeat_lp = 1000; + always_ff @(negedge clk_i) + begin + if (verbose_p && next_nbf && is_fence_packet) + $display("NBF fence packet : %d [%x] (%p)", nbf_index_r, curr_nbf, curr_nbf); + if (verbose_p && next_nbf && is_finish_packet) + $display("NBF finish packet : %d [%x] (%p)", nbf_index_r, curr_nbf, curr_nbf); + if (verbose_p && next_nbf && (nbf_index_r % heartbeat_lp == 0)) + $display("NBF heartbeat : %d [%x] (%p)", nbf_index_r, curr_nbf, curr_nbf); + end + + logic [dword_width_gp-1:0] read_data_r; + bsg_dff_reset_en + #(.width_p(dword_width_gp)) + read_data_expected + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.en_i(is_read_packet) + ,.data_i(curr_nbf.data[0+:dword_width_gp]) + ,.data_o(read_data_r) + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `bp_cast_o(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_i(bp_bedrock_mem_rev_header_s, mem_rev_header); + + logic [`BSG_WIDTH(mem_noc_max_credits_p)-1:0] credit_count_lo; + bsg_flow_counter + #(.els_p(mem_noc_max_credits_p)) + nbf_fc + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.v_i(mem_fwd_v_o) + ,.ready_param_i(mem_fwd_ready_and_i) + + ,.yumi_i(mem_rev_v_i) + ,.count_o(credit_count_lo) + ); + wire credits_full_lo = (credit_count_lo == mem_noc_max_credits_p); + wire credits_empty_lo = (credit_count_lo == '0); + assign mem_rev_ready_and_o = 1'b1; + + localparam sel_width_lp = `BSG_SAFE_CLOG2(nbf_data_width_lp>>3); + localparam size_width_lp = `BSG_SAFE_CLOG2(sel_width_lp); + bsg_bus_pack + #(.in_width_p(nbf_data_width_lp), .out_width_p(bedrock_fill_width_p)) + fwd_bus_pack + (.data_i(curr_nbf.data) + ,.sel_i('0) // We are aligned + ,.size_i(mem_fwd_header_cast_o.size[0+:size_width_lp]) + ,.data_o(mem_fwd_data_o) + ); + + always_comb + begin + mem_fwd_header_cast_o = '0; + mem_fwd_header_cast_o.payload.lce_id = lce_id_i; + mem_fwd_header_cast_o.payload.src_did = did_i; + mem_fwd_header_cast_o.addr = curr_nbf.addr; + mem_fwd_header_cast_o.msg_type.fwd = curr_nbf.opcode[5] ? e_bedrock_mem_rd : e_bedrock_mem_wr; + mem_fwd_header_cast_o.subop = e_bedrock_store; + case (curr_nbf.opcode[1:0]) + 2'b00: mem_fwd_header_cast_o.size = e_bedrock_msg_size_1; + 2'b01: mem_fwd_header_cast_o.size = e_bedrock_msg_size_2; + 2'b10: mem_fwd_header_cast_o.size = e_bedrock_msg_size_4; + 2'b11: mem_fwd_header_cast_o.size = e_bedrock_msg_size_8; + default: mem_fwd_header_cast_o.size = e_bedrock_msg_size_4; + endcase + end + + assign mem_fwd_v_o = ~credits_full_lo & is_send_nbf & ~is_fence_packet & ~is_finish_packet; + + wire read_return = is_read & mem_rev_v_i & (mem_rev_header_cast_i.msg_type == e_bedrock_mem_rd); + always_comb + unique casez (state_r) + e_reset : state_n = reset_i ? e_reset : e_send; + e_send : state_n = is_fence_packet + ? e_fence + : is_finish_packet + ? e_done + : (is_read_packet & mem_fwd_ready_and_i & mem_fwd_v_o) + ? e_read + : e_send; + e_read : state_n = read_return ? e_send : e_read; + e_fence : state_n = credits_empty_lo ? e_send : e_fence; + e_done : state_n = e_done; + default : state_n = e_reset; + endcase + assign done_o = is_done; + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + + // synopsys translate_off + always_ff @(negedge clk_i) + begin + if (state_r != e_done && state_n == e_done) + $display("NBF loader done!"); + assert(reset_i !== '0 || ~read_return || read_data_r == mem_rev_data_i[0+:dword_width_gp]) + else $error("Validation mismatch: addr: %d %d %d", mem_rev_header_cast_i.addr, mem_rev_data_i, read_data_r); + end + // synopsys translate_on + + + if (nbf_data_width_lp != dword_width_gp) + $error("NBF data width must be same as dword_width_gp"); + if (dword_width_gp < nbf_data_width_lp) + $error("NBF IO data width must be as large as NBF data width"); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_pc_profiler.sv b/designs/black-parrot/src/bp/bp_nonsynth_pc_profiler.sv new file mode 100644 index 0000000..79c7835 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_pc_profiler.sv @@ -0,0 +1,59 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_nonsynth_pc_profiler + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + `declare_bp_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p) + + , parameter pc_trace_file_p = "pc" + + ) + (input clk_i + , input reset_i + + , input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i + + // Commit packet + , input [commit_pkt_width_lp-1:0] commit_pkt + ); + + `declare_bp_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p, fetch_ptr_p, issue_ptr_p); + bp_be_commit_pkt_s commit_pkt_cast_i; + assign commit_pkt_cast_i = commit_pkt; + + integer histogram [longint]; + + integer file; + string file_name; + always_ff @(negedge reset_i) + begin + file_name = $sformatf("%s_%x.histogram", pc_trace_file_p, mhartid_i); + file = $fopen(file_name, "w"); + end + + logic [dword_width_gp-1:0] count; + always_ff @(posedge clk_i) + begin + if (reset_i) + count <= '0; + else + count <= count + 1'b1; + + if (commit_pkt_cast_i.instret) + if (histogram.exists(commit_pkt_cast_i.pc)) + histogram[commit_pkt_cast_i.pc] <= histogram[commit_pkt_cast_i.pc] + 1'b1; + else + histogram[commit_pkt_cast_i.pc] <= 1'b1; + end + + final + foreach (histogram[key]) + $fwrite(file, "[%x] %x\n", key, histogram[key]); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_perf.sv b/designs/black-parrot/src/bp/bp_nonsynth_perf.sv new file mode 100644 index 0000000..a1238fd --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_perf.sv @@ -0,0 +1,111 @@ +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_nonsynth_perf + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam max_instr_lp = 2**30-1 + , localparam max_clock_lp = 2**30-1 + ) + (input clk_i + , input reset_i + + , input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i + + , input [31:0] warmup_instr_i + , input [31:0] max_instr_i + + , input commit_v_i + , input is_debug_mode_i + ); + + logic [29:0] warmup_cnt; + logic warm; + bsg_counter_clear_up + #(.max_val_p(2**30-1), .init_val_p(0)) + warmup_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(1'b0) + ,.up_i(commit_v_i & ~warm) + ,.count_o(warmup_cnt) + ); + assign warm = (warmup_cnt == warmup_instr_i); + + logic [63:0] clk_cnt_r; + logic [63:0] instr_cnt_r; + + logic [num_core_p-1:0] program_finish_r; + always_ff @(posedge clk_i) + begin + if (reset_i | ~warm | is_debug_mode_i) + begin + clk_cnt_r <= '0; + instr_cnt_r <= '0; + end + else + begin + clk_cnt_r <= clk_cnt_r + 64'b1; + instr_cnt_r <= instr_cnt_r + commit_v_i; + end + end + + logic [`BSG_SAFE_CLOG2(max_instr_lp+1)-1:0] instr_cnt; + bsg_counter_clear_up + #(.max_val_p(max_instr_lp), .init_val_p(0)) + instr_counter + (.clk_i(clk_i) + ,.reset_i(reset_i | is_debug_mode_i) + + ,.clear_i(1'b0) + ,.up_i(commit_v_i) + ,.count_o(instr_cnt) + ); + wire complete = (instr_cnt == max_instr_i && max_instr_i > 0); + + logic [`BSG_SAFE_CLOG2(max_clock_lp+1)-1:0] clk_cnt; + bsg_counter_clear_up + #(.max_val_p(max_clock_lp), .init_val_p(0)) + clk_counter + (.clk_i(clk_i) + ,.reset_i(reset_i | is_debug_mode_i) + + ,.clear_i(1'b0) + ,.up_i(commit_v_i) + ,.count_o(clk_cnt) + ); + + logic finish_r; + bsg_dff_reset_set_clear + #(.width_p(1)) + finish_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.set_i(complete) + ,.clear_i('0) + ,.data_o(finish_r) + ); + + always_ff @(negedge clk_i) + if (finish_r) + begin + $display("[BSG-PASS]: Completed %x instructions, finishing...", max_instr_i); + $finish(); + end + + final + begin + $display("[BSG-STAT][4]:"); + $display("[CORE%0x]:", mhartid_i); + $display("\tclk : %d", clk_cnt_r); + $display("\tinstr : %d", instr_cnt_r); + $display("\tmIPC : %d", instr_cnt_r * 1000 / clk_cnt_r); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_vm_tracer.sv b/designs/black-parrot/src/bp/bp_nonsynth_vm_tracer.sv new file mode 100644 index 0000000..5757537 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_vm_tracer.sv @@ -0,0 +1,122 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_nonsynth_vm_tracer + import bp_common_pkg::*; + import bp_fe_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter vm_trace_file_p = "vm" + + , localparam itlb_entry_width_lp = `bp_pte_leaf_width(paddr_width_p) + , localparam dtlb_entry_width_lp = `bp_pte_leaf_width(paddr_width_p) + ) + (input clk_i + , input reset_i + + , input [core_id_width_p-1:0] mhartid_i + + , input itlb_clear_i + , input itlb_fill_v_i + , input itlb_fill_g_i + , input itlb_fill_m_i + , input [vtag_width_p-1:0] itlb_vtag_i + , input [itlb_entry_width_lp-1:0] itlb_entry_i + , input itlb_r_v_i + + , input dtlb_clear_i + , input dtlb_fill_v_i + , input dtlb_fill_g_i + , input dtlb_fill_m_i + , input [vtag_width_p-1:0] dtlb_vtag_i + , input [dtlb_entry_width_lp-1:0] dtlb_entry_i + , input dtlb_r_v_i + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + bp_pte_leaf_s itlb_w_entry; + bp_pte_leaf_s dtlb_w_entry; + + assign itlb_w_entry = itlb_entry_i; + assign dtlb_w_entry = dtlb_entry_i; + + integer file; + string file_name; + + always_ff @(negedge reset_i) + begin + file_name = $sformatf("%s_%x.trace", vm_trace_file_p, mhartid_i); + file = $fopen(file_name, "w"); + end + + always_ff @(negedge clk_i) + begin + if (itlb_clear_i) + $fwrite(file, "%12t | ITLB Clear\n", $time); + if (itlb_fill_v_i) + $fwrite(file, "%12t | ITLB map %x -> %x [R:%x W:%x X:%x] MP: %x GP: %x\n" //A:%x D:%x]" + ,$time + ,itlb_vtag_i + ,itlb_w_entry.ptag + ,itlb_w_entry.r + ,itlb_w_entry.w + ,itlb_w_entry.x + ,itlb_fill_m_i + ,itlb_fill_g_i + //,itlb_w_entry.a + //,itlb_w_entry.d + ); + if (dtlb_clear_i) + $fwrite(file, "%12t | DTLB Clear\n", $time); + if (dtlb_fill_v_i) + $fwrite(file, "%12t | DTLB map %x -> %x [R:%x W:%x X:%x] MP: %x GP: %x\n" //A:%x D:%x]" + ,$time + ,dtlb_vtag_i + ,dtlb_w_entry.ptag + ,dtlb_w_entry.r + ,dtlb_w_entry.w + ,dtlb_w_entry.x + ,dtlb_fill_m_i + ,dtlb_fill_g_i + //,dtlb_w_entry.a + //,dtlb_w_entry.d + ); + end +// << (itlb_fill_g_i * 2 * sv39_page_idx_width_gp) + + + logic [30:0] itlb_read_count_r; + bsg_counter_clear_up + #(.max_val_p(2**31-1), .init_val_p(0)) + itlb_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i('0) + ,.up_i(itlb_r_v_i) + ,.count_o(itlb_read_count_r) + ); + + logic [30:0] dtlb_read_count_r; + bsg_counter_clear_up + #(.max_val_p(2**31-1), .init_val_p(0)) + dtlb_counter + (.clk_i(~clk_i) + ,.reset_i(reset_i) + + ,.clear_i('0) + ,.up_i(dtlb_r_v_i) + ,.count_o(dtlb_read_count_r) + ); + + final + begin + $fwrite(file, "%12t | Total ITLB read access count is %0d.\n", $time, itlb_read_count_r); + $fwrite(file, "%12t | Total DTLB read access count is %0d.\n", $time, dtlb_read_count_r); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_nonsynth_watchdog.sv b/designs/black-parrot/src/bp/bp_nonsynth_watchdog.sv new file mode 100644 index 0000000..c857294 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_nonsynth_watchdog.sv @@ -0,0 +1,120 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_nonsynth_watchdog + import bp_common_pkg::*; + import bp_be_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , parameter `BSG_INV_PARAM(stall_cycles_p) + , parameter `BSG_INV_PARAM(halt_cycles_p) + , parameter `BSG_INV_PARAM(heartbeat_instr_p) + + // Something super big + , parameter max_instr_lp = 2**30 + ) + (input clk_i + , input reset_i + + , input wfi_i + + , input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i + + , input [vaddr_width_p-1:0] npc_i + , input instret_i + ); + + enum logic {e_run, e_halt} state_n, state_r; + wire is_run = (state_r == e_run); + wire is_halt = (state_r == e_halt); + + logic [vaddr_width_p-1:0] npc_r; + bsg_dff_reset + #(.width_p(vaddr_width_p)) + npc_reg + (.clk_i(clk_i) + ,.reset_i(reset_i | is_halt) + + ,.data_i(npc_i) + ,.data_o(npc_r) + ); + wire npc_change = (npc_i != npc_r); + + logic [`BSG_SAFE_CLOG2(stall_cycles_p)-1:0] stall_cnt; + bsg_counter_clear_up + #(.max_val_p(stall_cycles_p), .init_val_p(0)) + stall_counter + (.clk_i(clk_i) + ,.reset_i(reset_i | wfi_i | is_halt) + + ,.clear_i(npc_change) + ,.up_i(1'b1) + ,.count_o(stall_cnt) + ); + + logic [`BSG_SAFE_CLOG2(stall_cycles_p)-1:0] halt_cnt; + bsg_counter_clear_up + #(.max_val_p(stall_cycles_p), .init_val_p(0)) + halt_counter + (.clk_i(clk_i) + ,.reset_i(reset_i | wfi_i | is_halt) + + ,.clear_i(npc_change) + ,.up_i(instret_i) + ,.count_o(halt_cnt) + ); + + logic [`BSG_SAFE_CLOG2(max_instr_lp+1)-1:0] instr_cnt; + bsg_counter_clear_up + #(.max_val_p(max_instr_lp), .init_val_p(0)) + instr_counter + (.clk_i(clk_i) + ,.reset_i(reset_i | is_halt) + + ,.clear_i(1'b0) + ,.up_i(instret_i) + ,.count_o(instr_cnt) + ); + + always_comb + case (state_r) + e_run: state_n = (halt_cnt == halt_cycles_p) ? e_halt : e_run; + default: state_n = state_r; + endcase + + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_run; + else + state_r <= state_n; + + always_ff @(negedge clk_i) + begin + if (reset_i === '0 && is_halt && halt_cnt >= halt_cycles_p) + begin + $display("[BSG-INFO]: Core %x halt detected!", mhartid_i); + end + assert(reset_i !== '0 || (stall_cnt < stall_cycles_p)) else + begin + $display("[BSG-FAIL]: Core %x stalled for %d cycles!", mhartid_i, stall_cnt); + $finish(); + end + assert(reset_i !== '0 || (npc_r !== 'X)) else + begin + $display("[BSG-FAIL]: Core %x PC has become X!", mhartid_i); + $finish(); + end + end + + always_ff @(negedge clk_i) + begin + if (reset_i === '0 && (instr_cnt > '0) && (instr_cnt % heartbeat_instr_p == '0) & instret_i) + begin + $display("[BSG-INFO]: %d instructions completed (%d total)", heartbeat_instr_p, instr_cnt); + end + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_pma.sv b/designs/black-parrot/src/bp/bp_pma.sv new file mode 100644 index 0000000..56f8a7b --- /dev/null +++ b/designs/black-parrot/src/bp/bp_pma.sv @@ -0,0 +1,32 @@ + +`include "bp_common_defines.svh" + +module bp_pma + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + ) + (input clk_i + , input reset_i + + , input [ptag_width_p-1:0] ptag_i + , input uncached_mode_i + , input nonspec_mode_i + + , output logic uncached_o + , output logic nonidem_o + , output logic dram_o + ); + + wire is_local_addr = (ptag_i < (dram_base_addr_gp >> page_offset_width_gp)); + wire is_io_addr = (ptag_i[ptag_width_p-1:dtag_width_p] != '0); + wire is_uc_addr = (ptag_i[ptag_width_p-1:(caddr_width_p - page_offset_width_gp)] != '0); + + assign uncached_o = (is_uc_addr | is_io_addr | is_local_addr | uncached_mode_i); + // For now, uncached mode also means non-idempotency. Will reevaluate if we need + // a high-performance, unsafe, uncached mode + assign nonidem_o = (is_uc_addr | is_io_addr | is_local_addr | uncached_mode_i | nonspec_mode_i); + assign dram_o = (~is_local_addr & ~is_io_addr & ~is_uc_addr); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_processor.sv b/designs/black-parrot/src/bp/bp_processor.sv new file mode 100644 index 0000000..9af6a9d --- /dev/null +++ b/designs/black-parrot/src/bp/bp_processor.sv @@ -0,0 +1,306 @@ +/** + * + * bp_processor.sv + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" +`include "bp_me_defines.svh" +`include "bsg_noc_links.svh" + +module bp_processor + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam dma_pkt_width_lp = `bsg_cache_dma_pkt_width(daddr_width_p, l2_block_size_in_words_p) + ) + (input clk_i + , input rt_clk_i + , input reset_i + + , input [did_width_p-1:0] my_did_i + , input [did_width_p-1:0] host_did_i + + // Outgoing I/O + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + + // Incoming I/O + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + // DRAM interface + , output logic [num_cce_p-1:0][l2_dmas_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_o + , output logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_pkt_v_o + , input [num_cce_p-1:0][l2_dmas_p-1:0] dma_pkt_ready_and_i + + , input [num_cce_p-1:0][l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_i + , input [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_v_i + , output logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_ready_and_o + + , output logic [num_cce_p-1:0][l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_o + , output logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_v_o + , input [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_ready_and_i + ); + + if (cce_type_p != e_cce_uce) + begin : m + + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bp_mem_noc_ral_link_s); + `declare_bsg_ready_and_link_sif_s(dma_noc_flit_width_p, bp_dma_noc_ral_link_s); + + bp_mem_noc_ral_link_s [E:W] proc_fwd_link_li, proc_fwd_link_lo; + bp_mem_noc_ral_link_s [E:W] proc_rev_link_li, proc_rev_link_lo; + bp_dma_noc_ral_link_s [S:N][mc_x_dim_p-1:0] dma_link_lo, dma_link_li; + + assign dma_link_li[N] = '0; + assign proc_fwd_link_li[W] = '0; + assign proc_rev_link_li[W] = '0; + + bp_multicore + #(.bp_params_p(bp_params_p)) + multicore + (.core_clk_i(clk_i) + ,.rt_clk_i(rt_clk_i) + ,.core_reset_i(reset_i) + + ,.coh_clk_i(clk_i) + ,.coh_reset_i(reset_i) + + ,.mem_clk_i(clk_i) + ,.mem_reset_i(reset_i) + + ,.dma_clk_i(clk_i) + ,.dma_reset_i(reset_i) + + ,.my_did_i(my_did_i) + ,.host_did_i(host_did_i) + + ,.mem_fwd_link_i(proc_fwd_link_li) + ,.mem_fwd_link_o(proc_fwd_link_lo) + + ,.mem_rev_link_i(proc_rev_link_li) + ,.mem_rev_link_o(proc_rev_link_lo) + + ,.dma_link_i(dma_link_li) + ,.dma_link_o(dma_link_lo) + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bsg_ready_and_link_sif_s); + `bp_cast_i(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_o(bp_bedrock_mem_rev_header_s, mem_rev_header); + `bp_cast_o(bp_bedrock_mem_fwd_header_s, mem_fwd_header); + `bp_cast_i(bp_bedrock_mem_rev_header_s, mem_rev_header); + + wire [mem_noc_cord_width_p-1:0] mem_fwd_dst_cord_li = my_did_i; + wire [mem_noc_cid_width_p-1:0] mem_fwd_dst_cid_li = '0; + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(mem_noc_flit_width_p) + ,.cord_width_p(mem_noc_cord_width_p) + ,.len_width_p(mem_noc_len_width_p) + ,.cid_width_p(mem_noc_cid_width_p) + ,.pr_hdr_width_p(mem_fwd_header_width_lp) + ,.pr_payload_width_p(mem_fwd_payload_width_lp) + ,.pr_stream_mask_p(mem_fwd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + mem_fwd_stream_to_wormhole + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.pr_hdr_i(mem_fwd_header_cast_i) + ,.pr_data_i(mem_fwd_data_i) + ,.pr_v_i(mem_fwd_v_i) + ,.pr_ready_and_o(mem_fwd_ready_and_o) + ,.dst_cord_i(mem_fwd_dst_cord_li) + ,.dst_cid_i(mem_fwd_dst_cid_li) + + ,.link_data_o(proc_fwd_link_li[E].data) + ,.link_v_o(proc_fwd_link_li[E].v) + ,.link_ready_and_i(proc_fwd_link_lo[E].ready_and_rev) + ); + + wire [mem_noc_cord_width_p-1:0] mem_rev_dst_cord_li = mem_rev_header_cast_i.payload.src_did; + wire [mem_noc_cid_width_p-1:0] mem_rev_dst_cid_li = '0; + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(mem_noc_flit_width_p) + ,.cord_width_p(mem_noc_cord_width_p) + ,.len_width_p(mem_noc_len_width_p) + ,.cid_width_p(mem_noc_cid_width_p) + ,.pr_hdr_width_p(mem_rev_header_width_lp) + ,.pr_payload_width_p(mem_rev_payload_width_lp) + ,.pr_stream_mask_p(mem_rev_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + mem_rev_stream_to_wormhole + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.pr_hdr_i(mem_rev_header_cast_i) + ,.pr_data_i(mem_rev_data_i) + ,.pr_v_i(mem_rev_v_i) + ,.pr_ready_and_o(mem_rev_ready_and_o) + ,.dst_cord_i(mem_rev_dst_cord_li) + ,.dst_cid_i(mem_rev_dst_cid_li) + + ,.link_data_o(proc_rev_link_li[E].data) + ,.link_v_o(proc_rev_link_li[E].v) + ,.link_ready_and_i(proc_rev_link_lo[E].ready_and_rev) + ); + + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(mem_noc_flit_width_p) + ,.cord_width_p(mem_noc_cord_width_p) + ,.len_width_p(mem_noc_len_width_p) + ,.cid_width_p(mem_noc_cid_width_p) + ,.pr_hdr_width_p(mem_fwd_header_width_lp) + ,.pr_payload_width_p(mem_fwd_payload_width_lp) + ,.pr_stream_mask_p(mem_fwd_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + mem_fwd_wormhole_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.link_data_i(proc_fwd_link_lo[E].data) + ,.link_v_i(proc_fwd_link_lo[E].v) + ,.link_ready_and_o(proc_fwd_link_li[E].ready_and_rev) + + ,.pr_hdr_o(mem_fwd_header_cast_o) + ,.pr_data_o(mem_fwd_data_o) + ,.pr_v_o(mem_fwd_v_o) + ,.pr_ready_and_i(mem_fwd_ready_and_i) + ); + + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(mem_noc_flit_width_p) + ,.cord_width_p(mem_noc_cord_width_p) + ,.len_width_p(mem_noc_len_width_p) + ,.cid_width_p(mem_noc_cid_width_p) + ,.pr_hdr_width_p(mem_rev_header_width_lp) + ,.pr_payload_width_p(mem_rev_payload_width_lp) + ,.pr_stream_mask_p(mem_rev_stream_mask_gp) + ,.pr_data_width_p(bedrock_fill_width_p) + ) + mem_rev_wormhole_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.link_data_i(proc_rev_link_lo[E].data) + ,.link_v_i(proc_rev_link_lo[E].v) + ,.link_ready_and_o(proc_rev_link_li[E].ready_and_rev) + + ,.pr_hdr_o(mem_rev_header_cast_o) + ,.pr_data_o(mem_rev_data_o) + ,.pr_v_o(mem_rev_v_o) + ,.pr_ready_and_i(mem_rev_ready_and_i) + ); + + import bsg_cache_pkg::*; + `declare_bsg_cache_wh_header_flit_s(dma_noc_flit_width_p, dma_noc_cord_width_p, dma_noc_len_width_p, dma_noc_cid_width_p); + localparam dma_per_col_lp = num_cce_p/mc_x_dim_p*l2_dmas_p; + logic [mc_x_dim_p-1:0][dma_per_col_lp-1:0][dma_pkt_width_lp-1:0] dma_pkt_lo; + logic [mc_x_dim_p-1:0][dma_per_col_lp-1:0] dma_pkt_v_lo, dma_pkt_yumi_li; + logic [mc_x_dim_p-1:0][dma_per_col_lp-1:0][l2_fill_width_p-1:0] dma_data_lo; + logic [mc_x_dim_p-1:0][dma_per_col_lp-1:0] dma_data_v_lo, dma_data_yumi_li; + logic [mc_x_dim_p-1:0][dma_per_col_lp-1:0][l2_fill_width_p-1:0] dma_data_li; + logic [mc_x_dim_p-1:0][dma_per_col_lp-1:0] dma_data_v_li, dma_data_ready_and_lo; + for (genvar i = 0; i < mc_x_dim_p; i++) + begin : column + bsg_cache_wh_header_flit_s header_flit; + assign header_flit = dma_link_lo[S][i].data; + wire [`BSG_SAFE_CLOG2(dma_per_col_lp)-1:0] dma_id_li = + l2_dmas_p*(header_flit.src_cord-1)+header_flit.src_cid; + bsg_wormhole_to_cache_dma_fanout + #(.wh_flit_width_p(dma_noc_flit_width_p) + ,.wh_cid_width_p(dma_noc_cid_width_p) + ,.wh_len_width_p(dma_noc_len_width_p) + ,.wh_cord_width_p(dma_noc_cord_width_p) + + ,.num_dma_p(dma_per_col_lp) + ,.dma_addr_width_p(daddr_width_p) + ,.dma_burst_len_p(l2_block_size_in_fill_p) + ,.dma_mask_width_p(l2_block_size_in_words_p) + ) + wh_to_cache_dma + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.wh_link_sif_i(dma_link_lo[S][i]) + ,.wh_dma_id_i(dma_id_li) + ,.wh_link_sif_o(dma_link_li[S][i]) + + ,.dma_pkt_o(dma_pkt_lo[i]) + ,.dma_pkt_v_o(dma_pkt_v_lo[i]) + ,.dma_pkt_yumi_i(dma_pkt_yumi_li[i]) + + ,.dma_data_i(dma_data_li[i]) + ,.dma_data_v_i(dma_data_v_li[i]) + ,.dma_data_ready_and_o(dma_data_ready_and_lo[i]) + + ,.dma_data_o(dma_data_lo[i]) + ,.dma_data_v_o(dma_data_v_lo[i]) + ,.dma_data_yumi_i(dma_data_yumi_li[i]) + ); + end + + // Transpose the DMA IDs + for (genvar i = 0; i < num_cce_p; i++) + begin : rof1 + for (genvar j = 0; j < l2_dmas_p; j++) + begin : rof2 + localparam col_lp = i%mc_x_dim_p; + localparam col_pos_lp = (i/mc_x_dim_p)*l2_dmas_p+j; + + assign dma_pkt_o[i][j] = dma_pkt_lo[col_lp][col_pos_lp]; + assign dma_pkt_v_o[i][j] = dma_pkt_v_lo[col_lp][col_pos_lp]; + assign dma_pkt_yumi_li[col_lp][col_pos_lp] = dma_pkt_ready_and_i[i][j] & dma_pkt_v_o[i][j]; + + assign dma_data_o[i][j] = dma_data_lo[col_lp][col_pos_lp]; + assign dma_data_v_o[i][j] = dma_data_v_lo[col_lp][col_pos_lp]; + assign dma_data_yumi_li[col_lp][col_pos_lp] = dma_data_ready_and_i[i][j] & dma_data_v_o[i][j]; + + assign dma_data_li[col_lp][col_pos_lp] = dma_data_i[i][j]; + assign dma_data_v_li[col_lp][col_pos_lp] = dma_data_v_i[i][j]; + assign dma_data_ready_and_o[i][j] = dma_data_ready_and_lo[col_lp][col_pos_lp]; + end + end + end + else + begin : u + bp_unicore + #(.bp_params_p(bp_params_p)) + unicore + (.my_cord_i('0), .*); + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_sacc_complex.sv b/designs/black-parrot/src/bp/bp_sacc_complex.sv new file mode 100644 index 0000000..98e15db --- /dev/null +++ b/designs/black-parrot/src/bp/bp_sacc_complex.sv @@ -0,0 +1,121 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_sacc_complex + import bp_common_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + ) + (input core_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input [sac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_link_i + , output [sac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_link_o + + , input [sac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_i + , output [sac_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_o + + ); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + + bp_coh_ready_and_link_s [sac_y_dim_p-1:0][S:W] lce_req_link_li, lce_req_link_lo; + bp_coh_ready_and_link_s [E:W][sac_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; + bp_coh_ready_and_link_s [S:N] lce_req_ver_link_li, lce_req_ver_link_lo; + + bp_coh_ready_and_link_s [sac_y_dim_p-1:0][S:W] lce_cmd_link_li, lce_cmd_link_lo; + bp_coh_ready_and_link_s [E:W][sac_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; + bp_coh_ready_and_link_s [S:N] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; + + + for (genvar j=0; j < sac_y_dim_p; j++) + begin : y + wire [coh_noc_cord_width_p-1:0] cord_li = {coh_noc_y_cord_width_p'(ic_y_dim_p+j), + coh_noc_x_cord_width_p'(sac_x_dim_p-1)}; + if (sac_x_dim_p>0) + begin : node + bp_sacc_tile_node + #(.bp_params_p(bp_params_p)) + accel_tile_node + (.core_clk_i(core_clk_i) + ,.core_reset_i(core_reset_i) + + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + + ,.my_cord_i(cord_li) + + ,.coh_lce_req_link_i(lce_req_link_li[j]) + ,.coh_lce_cmd_link_i(lce_cmd_link_li[j]) + + ,.coh_lce_req_link_o(lce_req_link_lo[j]) + ,.coh_lce_cmd_link_o(lce_cmd_link_lo[j]) + ); + end + else + begin : stub + assign lce_req_link_lo[j] = '0; + assign lce_cmd_link_lo[j] = '0; + end + end + + + + if (sac_x_dim_p > 0) + begin : sac_stitch + assign lce_req_ver_link_li = '0; + assign lce_req_hor_link_li[W] = '0; + assign lce_req_hor_link_li[E] = coh_req_link_i; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(sac_x_dim_p) + ,.y_max_p(sac_y_dim_p) + ) + coh_req_mesh + (.outs_i(lce_req_link_lo) + ,.ins_o(lce_req_link_li) + + ,.hor_i(lce_req_hor_link_li) + ,.hor_o(lce_req_hor_link_lo) + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); + assign coh_req_link_o = lce_req_hor_link_lo[E]; + + assign lce_cmd_ver_link_li = '0; + assign lce_cmd_hor_link_li[W] = '0; + assign lce_cmd_hor_link_li[E] = coh_cmd_link_i; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(sac_x_dim_p) + ,.y_max_p(sac_y_dim_p) + ) + coh_cmd_mesh + (.outs_i(lce_cmd_link_lo) + ,.ins_o(lce_cmd_link_li) + + ,.hor_i(lce_cmd_hor_link_li) + ,.hor_o(lce_cmd_hor_link_lo) + ,.ver_i(lce_cmd_ver_link_li) + ,.ver_o(lce_cmd_ver_link_lo) + ); + assign coh_cmd_link_o = lce_cmd_hor_link_lo[E]; + end + else + begin : stub + assign coh_req_link_o = '0; + assign coh_cmd_link_o = '0; + end + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_sacc_scratchpad.sv b/designs/black-parrot/src/bp/bp_sacc_scratchpad.sv new file mode 100644 index 0000000..ede6a3e --- /dev/null +++ b/designs/black-parrot/src/bp/bp_sacc_scratchpad.sv @@ -0,0 +1,106 @@ +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_sacc_scratchpad + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + , localparam cfg_bus_width_lp= `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [lce_id_width_p-1:0] lce_id_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [acache_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [acache_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + ); + + // CCE-IO interface is used for uncached requests-read/write memory mapped CSR + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + + logic r_v_li, w_v_li; + logic [paddr_width_p-1:0] addr_lo; + logic [dword_width_gp-1:0] data_li, data_lo; + bp_me_bedrock_register + #(.bp_params_p(bp_params_p) + ,.els_p(1) + ,.reg_addr_width_p(paddr_width_p) + ,.base_addr_p({64'b????????????????}) + ) + register + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.r_v_o(r_v_li) + ,.w_v_o(w_v_li) + ,.addr_o(addr_lo) + ,.size_o() + ,.data_o(data_lo) + ,.data_i(data_li) + + ,.* + ); + + bp_local_addr_s local_addr_lo; + bp_global_addr_s global_addr_lo; + assign global_addr_lo = addr_lo; + assign local_addr_lo = addr_lo; + + wire csr_w_v_li = w_v_li && (addr_lo inside {accel_wr_cnt_csr_idx_gp}); + wire csr_r_v_li = r_v_li && (addr_lo inside {accel_wr_cnt_csr_idx_gp}); + wire [dword_width_gp-1:0] csr_data_li = data_lo; + + wire spm_w_v_li = w_v_li && (global_addr_lo.hio == 1); + wire spm_r_v_li = r_v_li && (global_addr_lo.hio == 1); + wire [dword_width_gp-1:0] spm_data_li = data_lo; + + logic [dword_width_gp-1:0] spm_data_lo; + logic [`BSG_SAFE_CLOG2(20)-1:0] spm_addr_li; + logic [9:0] spm_write_cnt; + bsg_counter_clear_up + #(.max_val_p(2**10-1), .init_val_p(0)) + write_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(1'b0) + ,.up_i(spm_w_v_li) + ,.count_o(spm_write_cnt) + ); + wire [dword_width_gp-1:0] csr_data_lo = spm_write_cnt; + + assign spm_addr_li = addr_lo >> 3; + bsg_mem_1rw_sync + #(.width_p(64), .els_p(20)) + accel_spm + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(spm_data_li) + ,.addr_i(spm_addr_li) + ,.v_i(spm_r_v_li | spm_w_v_li) + ,.w_i(spm_w_v_li) + ,.data_o(spm_data_lo) + ); + + logic spm_r_v_r; + always_ff @(posedge clk_i) + spm_r_v_r <= spm_r_v_li; + + assign data_li = spm_r_v_r ? spm_data_lo : csr_data_lo; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_sacc_scratchpad) + diff --git a/designs/black-parrot/src/bp/bp_sacc_tile.sv b/designs/black-parrot/src/bp/bp_sacc_tile.sv new file mode 100644 index 0000000..c6d1163 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_sacc_tile.sv @@ -0,0 +1,327 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_be_defines.svh" +`include "bp_top_defines.svh" +`include "bsg_cache.svh" +`include "bsg_noc_links.svh" + +module bp_sacc_tile + import bp_common_pkg::*; + import bp_me_pkg::*; + import bp_be_pkg::*; + import bp_top_pkg::*; + import bsg_cache_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) + , parameter accelerator_type_p = e_sacc_vdp + ) + (input clk_i + , input reset_i + + , input [coh_noc_cord_width_p-1:0] my_cord_i + + , input [coh_noc_ral_link_width_lp-1:0] lce_req_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_req_link_o + + , input [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_i + , output logic [coh_noc_ral_link_width_lp-1:0] lce_cmd_link_o + + ); + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + + // LCE-CCE link casts + `bp_cast_i(bp_coh_ready_and_link_s, lce_req_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_req_link); + `bp_cast_i(bp_coh_ready_and_link_s, lce_cmd_link); + `bp_cast_o(bp_coh_ready_and_link_s, lce_cmd_link); + + // I/O Link to LCE connections + bp_bedrock_lce_req_header_s lce_req_header_lo; + logic [acache_fill_width_p-1:0] lce_req_data_lo; + logic lce_req_v_lo, lce_req_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_req_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_req_dst_cid_lo; + + bp_bedrock_lce_cmd_header_s lce_cmd_header_li; + logic [acache_fill_width_p-1:0] lce_cmd_data_li; + logic lce_cmd_v_li, lce_cmd_ready_and_lo; + + // I/O CCE connections + bp_bedrock_lce_cmd_header_s lce_cmd_header_lo; + logic [acache_fill_width_p-1:0] lce_cmd_data_lo; + logic lce_cmd_v_lo, lce_cmd_ready_and_li; + logic [coh_noc_cord_width_p-1:0] lce_cmd_dst_cord_lo; + logic [coh_noc_cid_width_p-1:0] lce_cmd_dst_cid_lo; + + bp_bedrock_lce_req_header_s lce_req_header_li; + logic [acache_fill_width_p-1:0] lce_req_data_li; + logic lce_req_v_li, lce_req_ready_and_lo; + + bp_bedrock_mem_fwd_header_s mem_fwd_header_lo; + logic [acache_fill_width_p-1:0] mem_fwd_data_lo; + logic mem_fwd_v_lo, mem_fwd_ready_and_li; + + bp_bedrock_mem_rev_header_s mem_rev_header_li; + logic [acache_fill_width_p-1:0] mem_rev_data_li; + logic mem_rev_v_li, mem_rev_ready_and_lo; + + logic reset_r; + always_ff @(posedge clk_i) + reset_r <= reset_i; + + logic [cce_id_width_p-1:0] cce_id_li; + logic [lce_id_width_p-1:0] lce_id_li; + bp_me_cord_to_id + #(.bp_params_p(bp_params_p)) + id_map + (.cord_i(my_cord_i) + ,.core_id_o() + ,.cce_id_o(cce_id_li) + ,.lce_id0_o(lce_id_li) + ,.lce_id1_o() + ); + + bp_io_link_to_lce + #(.bp_params_p(bp_params_p)) + lce_link + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.lce_id_i(lce_id_li) + + ,.mem_fwd_header_i('0) + ,.mem_fwd_data_i('0) + ,.mem_fwd_v_i(1'b0) + ,.mem_fwd_ready_and_o() + + ,.mem_rev_header_o() + ,.mem_rev_data_o() + ,.mem_rev_v_o() + ,.mem_rev_ready_and_i(1'b0) + + ,.lce_req_header_o(lce_req_header_lo) + ,.lce_req_data_o(lce_req_data_lo) + ,.lce_req_v_o(lce_req_v_lo) + ,.lce_req_ready_and_i(lce_req_ready_and_li) + + ,.lce_cmd_header_i(lce_cmd_header_li) + ,.lce_cmd_data_i(lce_cmd_data_li) + ,.lce_cmd_v_i(lce_cmd_v_li) + ,.lce_cmd_ready_and_o(lce_cmd_ready_and_lo) + ); + + bp_io_cce + #(.bp_params_p(bp_params_p)) + io_cce + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.cce_id_i(cce_id_li) + + ,.lce_req_header_i(lce_req_header_li) + ,.lce_req_data_i(lce_req_data_li) + ,.lce_req_v_i(lce_req_v_li) + ,.lce_req_ready_and_o(lce_req_ready_and_lo) + + ,.lce_cmd_header_o(lce_cmd_header_lo) + ,.lce_cmd_data_o(lce_cmd_data_lo) + ,.lce_cmd_v_o(lce_cmd_v_lo) + ,.lce_cmd_ready_and_i(lce_cmd_ready_and_li) + + ,.mem_fwd_header_o(mem_fwd_header_lo) + ,.mem_fwd_data_o(mem_fwd_data_lo) + ,.mem_fwd_v_o(mem_fwd_v_lo) + ,.mem_fwd_ready_and_i(mem_fwd_ready_and_li) + + ,.mem_rev_header_i(mem_rev_header_li) + ,.mem_rev_data_i(mem_rev_data_li) + ,.mem_rev_v_i(mem_rev_v_li) + ,.mem_rev_ready_and_o(mem_rev_ready_and_lo) + ); + + if (sacc_type_p == e_sacc_vdp) + begin : sacc_vdp + bp_sacc_vdp + #(.bp_params_p(bp_params_p)) + accelerator + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.lce_id_i(lce_id_li) + + ,.mem_fwd_header_i(mem_fwd_header_lo) + ,.mem_fwd_data_i(mem_fwd_data_lo) + ,.mem_fwd_v_i(mem_fwd_v_lo) + ,.mem_fwd_ready_and_o(mem_fwd_ready_and_li) + + ,.mem_rev_header_o(mem_rev_header_li) + ,.mem_rev_data_o(mem_rev_data_li) + ,.mem_rev_v_o(mem_rev_v_li) + ,.mem_rev_ready_and_i(mem_rev_ready_and_lo) + ); + end + else if (sacc_type_p == e_sacc_scratchpad) + begin : sacc_scratchpad + bp_sacc_scratchpad + #(.bp_params_p(bp_params_p)) + accelerator + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.lce_id_i(lce_id_li) + + ,.mem_fwd_header_i(mem_fwd_header_lo) + ,.mem_fwd_data_i(mem_fwd_data_lo) + ,.mem_fwd_v_i(mem_fwd_v_lo) + ,.mem_fwd_ready_and_o(mem_fwd_ready_and_li) + + ,.mem_rev_header_o(mem_rev_header_li) + ,.mem_rev_data_o(mem_rev_data_li) + ,.mem_rev_v_o(mem_rev_v_li) + ,.mem_rev_ready_and_i(mem_rev_ready_and_lo) + ); + end + else + begin : none + assign mem_fwd_ready_and_li = 1'b0; + assign mem_rev_header_li = '0; + assign mem_rev_data_li = '0; + assign mem_rev_v_li = 1'b0; + end + + // Burst to WH (lce_req_header_lo) + bp_me_cce_id_to_cord + #(.bp_params_p(bp_params_p)) + req_router_cord + (.cce_id_i(lce_req_header_lo.payload.dst_id) + ,.cce_cord_o(lce_req_dst_cord_lo) + ,.cce_cid_o(lce_req_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_req_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_req_header_lo) + ,.pr_data_i(lce_req_data_lo) + ,.pr_v_i(lce_req_v_lo) + ,.pr_ready_and_o(lce_req_ready_and_li) + ,.dst_cord_i(lce_req_dst_cord_lo) + ,.dst_cid_i(lce_req_dst_cid_lo) + + ,.link_data_o(lce_req_link_cast_o.data) + ,.link_v_o(lce_req_link_cast_o.v) + ,.link_ready_and_i(lce_req_link_cast_i.ready_and_rev) + ); + + // WH to Burst (lce_cmd_header_li) + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_cmd_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_cmd_link_cast_i.data) + ,.link_v_i(lce_cmd_link_cast_i.v) + ,.link_ready_and_o(lce_cmd_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_cmd_header_li) + ,.pr_data_o(lce_cmd_data_li) + ,.pr_v_o(lce_cmd_v_li) + ,.pr_ready_and_i(lce_cmd_ready_and_lo) + ); + + // WH to Burst (lce_req_header_li) + bp_me_wormhole_to_stream + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_req_header_width_lp) + ,.pr_payload_width_p(lce_req_payload_width_lp) + ,.pr_stream_mask_p(lce_req_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_req_wh_to_stream + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.link_data_i(lce_req_link_cast_i.data) + ,.link_v_i(lce_req_link_cast_i.v) + ,.link_ready_and_o(lce_req_link_cast_o.ready_and_rev) + + ,.pr_hdr_o(lce_req_header_li) + ,.pr_data_o(lce_req_data_li) + ,.pr_v_o(lce_req_v_li) + ,.pr_ready_and_i(lce_req_ready_and_lo) + ); + + // Burst to WH (lce_cmd_header_lo) + bp_me_lce_id_to_cord + #(.bp_params_p(bp_params_p)) + cmd_router_cord + (.lce_id_i(lce_cmd_header_lo.payload.dst_id) + ,.lce_cord_o(lce_cmd_dst_cord_lo) + ,.lce_cid_o(lce_cmd_dst_cid_lo) + ); + + bp_me_stream_to_wormhole + #(.bp_params_p(bp_params_p) + ,.flit_width_p(coh_noc_flit_width_p) + ,.cord_width_p(coh_noc_cord_width_p) + ,.len_width_p(coh_noc_len_width_p) + ,.cid_width_p(coh_noc_cid_width_p) + ,.pr_hdr_width_p(lce_cmd_header_width_lp) + ,.pr_payload_width_p(lce_cmd_payload_width_lp) + ,.pr_stream_mask_p(lce_cmd_stream_mask_gp) + ,.pr_data_width_p(acache_fill_width_p) + ) + lce_cmd_stream_to_wh + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.pr_hdr_i(lce_cmd_header_lo) + ,.pr_data_i(lce_cmd_data_lo) + ,.pr_v_i(lce_cmd_v_lo) + ,.pr_ready_and_o(lce_cmd_ready_and_li) + ,.dst_cord_i(lce_cmd_dst_cord_lo) + ,.dst_cid_i(lce_cmd_dst_cid_lo) + + ,.link_data_o(lce_cmd_link_cast_o.data) + ,.link_v_o(lce_cmd_link_cast_o.v) + ,.link_ready_and_i(lce_cmd_link_cast_i.ready_and_rev) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_sacc_tile_node.sv b/designs/black-parrot/src/bp/bp_sacc_tile_node.sv new file mode 100644 index 0000000..9c4d453 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_sacc_tile_node.sv @@ -0,0 +1,81 @@ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" + +module bp_sacc_tile_node + import bp_common_pkg::*; + import bp_be_pkg::*; + import bsg_noc_pkg::*; + import bsg_wormhole_router_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam dma_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(dma_noc_flit_width_p) + , parameter accelerator_type_p = 1 + ) + (input core_clk_i + , input core_reset_i + + , input coh_clk_i + , input coh_reset_i + + , input [coh_noc_cord_width_p-1:0] my_cord_i + // Connected to other tiles on east and west + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o + + , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i + , output logic [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o + ); + + // Declare the routing links + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + + // Tile-side coherence connections + bp_coh_ready_and_link_s accel_lce_req_link_li, accel_lce_req_link_lo; + bp_coh_ready_and_link_s accel_lce_cmd_link_li, accel_lce_cmd_link_lo; + + + bp_sacc_tile + #(.bp_params_p(bp_params_p)) + accel_tile + (.clk_i(core_clk_i) + ,.reset_i(core_reset_i) + + ,.my_cord_i(my_cord_i) + + ,.lce_req_link_i(accel_lce_req_link_li) + ,.lce_req_link_o(accel_lce_req_link_lo) + + ,.lce_cmd_link_i(accel_lce_cmd_link_li) + ,.lce_cmd_link_o(accel_lce_cmd_link_lo) + ); + + + bp_nd_socket + #(.flit_width_p(coh_noc_flit_width_p) + ,.dims_p(coh_noc_dims_p) + ,.cord_dims_p(coh_noc_dims_p) + ,.cord_markers_pos_p(coh_noc_cord_markers_pos_p) + ,.len_width_p(coh_noc_len_width_p) + ,.routing_matrix_p(StrictYX) + ,.async_clk_p(async_coh_clk_p) + ,.els_p(2) + ) + sac_coh_socket + (.tile_clk_i(core_clk_i) + ,.tile_reset_i(core_reset_i) + ,.network_clk_i(coh_clk_i) + ,.network_reset_i(coh_reset_i) + ,.my_cord_i(my_cord_i) + ,.network_link_i({coh_lce_req_link_i, coh_lce_cmd_link_i}) + ,.network_link_o({coh_lce_req_link_o, coh_lce_cmd_link_o}) + ,.tile_link_i({accel_lce_req_link_lo, accel_lce_cmd_link_lo}) + ,.tile_link_o({accel_lce_req_link_li, accel_lce_cmd_link_li}) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_sacc_vdp.sv b/designs/black-parrot/src/bp/bp_sacc_vdp.sv new file mode 100644 index 0000000..a99a0dc --- /dev/null +++ b/designs/black-parrot/src/bp/bp_sacc_vdp.sv @@ -0,0 +1,246 @@ +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" + +module bp_sacc_vdp + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [lce_id_width_p-1:0] lce_id_i + + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [acache_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [acache_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + ); + + // CCE-IO interface is used for uncached requests-read/write memory mapped CSR + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + + logic r_v_li, w_v_li; + logic [paddr_width_p-1:0] addr_lo; + logic [dword_width_gp-1:0] data_li, data_lo; + bp_me_bedrock_register + #(.bp_params_p(bp_params_p) + ,.els_p(1) + ,.reg_addr_width_p(paddr_width_p) + ,.base_addr_p({64'b????????????????}) + ) + register + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.r_v_o(r_v_li) + ,.w_v_o(w_v_li) + ,.addr_o(addr_lo) + ,.size_o() + ,.data_o(data_lo) + ,.data_i(data_li) + + ,.* + ); + + bp_local_addr_s local_addr_lo; + bp_global_addr_s global_addr_lo; + assign global_addr_lo = addr_lo; + assign local_addr_lo = addr_lo; + + logic [63:0] start_cmd, input_a_ptr, input_b_ptr, input_len; + logic [63:0] res_ptr, res_len, operation, spm_data_lo, vdp_result; + logic [7:0][63:0] vector_a; + logic [7:0][63:0] vector_b; + logic [2:0] len_a_cnt, len_b_cnt; + logic second_operand; + + enum logic [3:0] + { + e_wait + ,e_fetch_vec1 + ,e_wb_vec1 + ,e_fetch_vec2 + ,e_wb_vec2 + ,e_wb_result + } state_n, state_r; + + wire is_done = (state_r inside {e_wait}); + + logic spm_internal_r_v_li, spm_internal_w_v_li; + logic [paddr_width_p-1:0] spm_internal_addr; + + logic vector_w_v_li; + + always_ff @(posedge clk_i) + begin + if (reset_i || is_done) + begin + len_a_cnt <= '0; + len_b_cnt <= '0; + vector_a <= '0; + vector_b <= '0; + end + else if (vector_w_v_li & ~second_operand) + begin + vector_a[len_a_cnt] <= spm_data_lo; + len_a_cnt <= len_a_cnt + 1'b1; + end + else if (vector_w_v_li & second_operand) + begin + vector_b[len_b_cnt] <= spm_data_lo; + len_b_cnt <= len_b_cnt + 1'b1; + end + end + + wire csr_w_v_li = w_v_li && (global_addr_lo.hio == 0); + wire csr_r_v_li = r_v_li && (global_addr_lo.hio == 0); + + wire spm_external_w_v_li = w_v_li && (global_addr_lo.hio == 1); + wire spm_external_r_v_li = r_v_li && (global_addr_lo.hio == 1); + wire [paddr_width_p-1:0] spm_external_addr = addr_lo; + + // SPM + wire [paddr_width_p-1:0] spm_selected_addr = + (spm_external_r_v_li | spm_external_w_v_li) ? spm_external_addr : spm_internal_addr; + wire [`BSG_SAFE_CLOG2(20)-1:0] spm_addr_li = spm_selected_addr >> 3; + wire [63:0] spm_data_li = spm_external_w_v_li ? data_lo : vdp_result; + bsg_mem_1rw_sync + #(.width_p(64), .els_p(20)) + accel_spm + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.data_i(spm_data_li) + ,.addr_i(spm_addr_li) + ,.v_i(spm_internal_r_v_li | spm_external_r_v_li | spm_internal_w_v_li | spm_external_w_v_li) + ,.w_i(spm_internal_w_v_li | spm_external_w_v_li) + ,.data_o(spm_data_lo) + ); + + always_ff @(posedge clk_i) + begin + if (reset_i) + begin + input_a_ptr <= '0; + input_b_ptr <= '0; + input_len <= '0; + start_cmd <= '0; + res_ptr <= '0; + res_len <= '0; + operation <= '0; + end + else if (csr_w_v_li) + unique casez (local_addr_lo.addr) + inputa_ptr_csr_idx_gp : input_a_ptr <= data_lo; + inputb_ptr_csr_idx_gp : input_b_ptr <= data_lo; + input_len_csr_idx_gp : input_len <= data_lo; + start_cmd_csr_idx_gp : start_cmd <= data_lo; + res_ptr_csr_idx_gp : res_ptr <= data_lo; + res_len_csr_idx_gp : res_len <= data_lo; + operation_csr_idx_gp : operation <= data_lo; + default : begin end + endcase + + if (state_r == e_fetch_vec1) + start_cmd <= '0; + end + + logic [dword_width_gp-1:0] csr_data_lo; + always_comb + unique casez (local_addr_lo.addr) + inputa_ptr_csr_idx_gp : csr_data_lo = input_a_ptr; + inputb_ptr_csr_idx_gp : csr_data_lo = input_b_ptr; + input_len_csr_idx_gp : csr_data_lo = input_len; + start_cmd_csr_idx_gp : csr_data_lo = start_cmd; + res_status_csr_idx_gp : csr_data_lo = is_done; + res_ptr_csr_idx_gp : csr_data_lo = res_ptr; + res_len_csr_idx_gp : csr_data_lo = res_len; + //operation_csr_idx_gp: + default: csr_data_lo = operation; + endcase + + logic spm_r_v_r; + always_ff @(posedge clk_i) + begin + spm_r_v_r <= spm_external_r_v_li | spm_internal_r_v_li; + end + assign data_li = spm_r_v_r ? spm_data_lo : csr_data_lo; + + always_comb + begin + spm_internal_w_v_li = '0; + spm_internal_r_v_li = '0; + spm_internal_addr = '0; + + vector_w_v_li = '0; + + second_operand = '0; + + state_n = state_r; + + case (state_r) + e_wait: + begin + state_n = start_cmd ? e_fetch_vec1 : state_r; + end + e_fetch_vec1: + begin + spm_internal_r_v_li = '1; + spm_internal_addr = (input_a_ptr+len_a_cnt*8); + state_n = e_wb_vec1; + end + e_wb_vec1: + begin + vector_w_v_li = 1'b1; + state_n = (len_a_cnt == input_len-1) ? e_fetch_vec2 : e_fetch_vec1; + end + e_fetch_vec2: + begin + second_operand = 1'b1; + spm_internal_r_v_li = '1; + spm_internal_addr = (input_b_ptr+len_b_cnt*8); + state_n = e_wb_vec2; + end + e_wb_vec2: + begin + vector_w_v_li = 1'b1; + second_operand = 1'b1; + state_n = (len_b_cnt == input_len-1) ? e_wb_result : e_fetch_vec2; + end + e_wb_result: + begin + spm_internal_w_v_li = '1; + spm_internal_addr = res_ptr; + state_n = e_wait; + end + endcase + end + + // dot_product unit + logic [7:0][63:0] product_res; + logic [3:0][63:0] sum_l1; + logic [1:0][63:0] sum_l2; + for (genvar i = 0; i < 8; i++) assign product_res[i] = vector_a[i] * vector_b[i]; + for (genvar i = 0; i < 4; i++) assign sum_l1[i] = product_res[2*i] + product_res[2*i+1]; + for (genvar i = 0; i < 2; i++) assign sum_l2[i] = sum_l1[2*i] + sum_l1[2*i+1]; + assign vdp_result = (sum_l2[0] + sum_l2[1]); + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_wait; + else + state_r <= state_n; + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_tlb.sv b/designs/black-parrot/src/bp/bp_tlb.sv new file mode 100644 index 0000000..207b363 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_tlb.sv @@ -0,0 +1,288 @@ + +`include "bp_common_defines.svh" + +// See diagram here: +// https://docs.google.com/presentation/d/1Lzs5EM5lxArRA8suZOd7sWpTPywQMzN7OwANmOuS5_U/edit +// In general, the idea is to have a data store for 4k pages and a separate data store for 1g +// pages. Then we mux high PPNs and metadata from both 4k + 1g storage, and mux low PPNs +// only from 4k storage + +module bp_tlb + import bp_common_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + , parameter `BSG_INV_PARAM(els_1g_p) + , parameter `BSG_INV_PARAM(els_2m_p) + , parameter `BSG_INV_PARAM(els_4k_p) + + , parameter pte_width_p = sv39_pte_width_gp + , parameter page_table_depth_p = sv39_levels_gp + , parameter pte_size_in_bytes_p = sv39_pte_size_in_bytes_gp + , parameter page_idx_width_p = sv39_page_idx_width_gp + + , localparam entry_width_lp = `bp_pte_leaf_width(paddr_width_p) + ) + (input clk_i + , input reset_i + , input fence_i + + // Single read-write port, but writes also "read" from the TLB + , input v_i + , input w_i + , input [vtag_width_p-1:0] vtag_i + , input [entry_width_lp-1:0] entry_i + + , output logic v_o + , output logic [entry_width_lp-1:0] entry_o + ); + + `declare_bp_core_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p); + `bp_cast_i(bp_pte_leaf_s, entry); + // Signals must be 1 width + localparam els_1g_lp = `BSG_MAX(els_1g_p, 1); + localparam els_2m_lp = `BSG_MAX(els_2m_p, 1); + + localparam r_entry_low_bits_lp = 1*sv39_page_idx_width_gp; + localparam r_entry_med_bits_lp = 1*sv39_page_idx_width_gp; + localparam r_entry_high_bits_lp = $bits(bp_pte_leaf_s) - r_entry_med_bits_lp - r_entry_low_bits_lp; + + wire r_v_li = v_i & ~w_i; + wire w_v_li = v_i & w_i; + + // We shift so that ppn bits are LSB + bp_pte_leaf_s entry_shifted; + localparam [`BSG_SAFE_CLOG2(entry_width_lp)-1:0] entry_shamt_lp = ptag_width_p; + bsg_rotate_left + #(.width_p($bits(bp_pte_leaf_s))) + entry_shift + (.data_i(entry_cast_i) + ,.rot_i(entry_shamt_lp) + ,.o(entry_shifted) + ); + + logic [vtag_width_p-1:0] vtag_r; + bsg_dff_en + #(.width_p(vtag_width_p)) + vtag_reg + (.clk_i(clk_i) + ,.en_i(v_i) + ,.data_i(vtag_i) + ,.data_o(vtag_r) + ); + wire [r_entry_low_bits_lp-1:0] passthrough_low_bits = vtag_r[0+:r_entry_low_bits_lp]; + wire [r_entry_med_bits_lp-1:0] passthrough_med_bits = vtag_r[r_entry_low_bits_lp+:r_entry_med_bits_lp]; + + wire fill_gigapage = w_v_li & entry_cast_i.gigapage & (els_1g_p > 0); + wire fill_megapage = w_v_li & entry_cast_i.megapage & (els_2m_p > 0); + wire fill_kilopage = w_v_li & ~fill_gigapage & ~fill_megapage; + + logic flush_4k_li; + logic [els_4k_p-1:0] tag_r_match_4k_lo; + logic [els_4k_p-1:0] tag_empty_4k_lo; + logic [els_4k_p-1:0] repl_way_4k_lo; + wire [els_4k_p-1:0] tag_4k_w_v_li = ({els_4k_p{fill_kilopage}} & repl_way_4k_lo) | {els_4k_p{flush_4k_li}}; + bsg_cam_1r1w_tag_array + #(.width_p(vtag_width_p), .els_p(els_4k_p)) + tag_array_4k + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(tag_4k_w_v_li) + ,.w_set_not_clear_i(~flush_4k_li) + ,.w_tag_i(vtag_i) + ,.w_empty_o(tag_empty_4k_lo) + + ,.r_v_i(1'b1) + ,.r_tag_i(vtag_r) + ,.r_match_o(tag_r_match_4k_lo) + ); + wire any_match_4k_lo = |tag_r_match_4k_lo; + + bsg_cam_1r1w_replacement + #(.els_p(els_4k_p)) + replacement_4k + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.read_v_i(tag_r_match_4k_lo) + + ,.alloc_v_i(fill_kilopage) + ,.alloc_empty_i(tag_empty_4k_lo) + ,.alloc_v_o(repl_way_4k_lo) + ); + + logic flush_2m_li; + logic [els_2m_lp-1:0] tag_r_match_2m_lo; + logic [els_2m_lp-1:0] tag_empty_2m_lo; + logic [els_2m_lp-1:0] repl_way_2m_lo; + wire [els_2m_lp-1:0] tag_2m_w_v_li = ({els_2m_lp{fill_megapage}} & repl_way_2m_lo) | {els_2m_lp{flush_2m_li}}; + bsg_cam_1r1w_tag_array + #(.width_p(vtag_width_p), .els_p(els_2m_p)) + tag_array_2m + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(tag_2m_w_v_li) + ,.w_set_not_clear_i(~flush_2m_li) + ,.w_tag_i(vtag_i) + ,.w_empty_o(tag_empty_2m_lo) + + ,.r_v_i(1'b1) + ,.r_tag_i(vtag_r) + ,.r_match_o(tag_r_match_2m_lo) + ); + wire any_match_2m_lo = |tag_r_match_2m_lo; + + bsg_cam_1r1w_replacement + #(.els_p(els_2m_p)) + replacement_2m + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.read_v_i(tag_r_match_2m_lo) + + ,.alloc_v_i(fill_megapage) + ,.alloc_empty_i(tag_empty_2m_lo) + ,.alloc_v_o(repl_way_2m_lo) + ); + + logic flush_1g_li; + logic [els_1g_lp-1:0] tag_r_match_1g_lo; + logic [els_1g_lp-1:0] tag_empty_1g_lo; + logic [els_1g_lp-1:0] repl_way_1g_lo; + wire [els_1g_lp-1:0] tag_1g_w_v_li = ({els_1g_lp{fill_gigapage}} & repl_way_1g_lo) | {els_1g_lp{flush_1g_li}}; + bsg_cam_1r1w_tag_array + #(.width_p(vtag_width_p), .els_p(els_1g_p)) + tag_array_1g + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.w_v_i(tag_1g_w_v_li) + ,.w_set_not_clear_i(~flush_1g_li) + ,.w_tag_i(vtag_i) + ,.w_empty_o(tag_empty_1g_lo) + + ,.r_v_i(1'b1) + ,.r_tag_i(vtag_r) + ,.r_match_o(tag_r_match_1g_lo) + ); + wire any_match_1g_lo = |tag_r_match_1g_lo; + + bsg_cam_1r1w_replacement + #(.els_p(els_1g_p)) + replacement_1g + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.read_v_i(tag_r_match_1g_lo) + + ,.alloc_v_i(fill_gigapage) + ,.alloc_empty_i(tag_empty_1g_lo) + ,.alloc_v_o(repl_way_1g_lo) + ); + + logic [els_4k_p-1:0][r_entry_high_bits_lp-1:0] data_4k_high_r; + logic [els_4k_p-1:0][r_entry_med_bits_lp-1:0] data_4k_med_r; + logic [els_4k_p-1:0][r_entry_low_bits_lp-1:0] data_4k_low_r; + wire [els_4k_p-1:0] mem_4k_w_v_li = ({els_4k_p{fill_kilopage}} & repl_way_4k_lo); + for (genvar i = 0; i < els_4k_p; i++) + begin : mem_array_4k + bsg_dff_en + #(.width_p(entry_width_lp)) + mem_reg + (.clk_i(clk_i) + ,.en_i(mem_4k_w_v_li[i]) + ,.data_i(entry_shifted) + ,.data_o({data_4k_high_r[i], data_4k_med_r[i], data_4k_low_r[i]}) + ); + end + + logic [els_2m_lp-1:0][r_entry_high_bits_lp-1:0] data_2m_high_r; + logic [els_2m_lp-1:0][r_entry_med_bits_lp-1:0] data_2m_med_r; + wire [els_2m_lp-1:0] mem_2m_w_v_li = ({els_2m_lp{fill_megapage}} & repl_way_2m_lo); + if (els_2m_p == 0) begin assign data_2m_high_r = '0; assign data_2m_med_r = '0; end + else + for (genvar i = 0; i < els_2m_p; i++) + begin : mem_array_2m + bsg_dff_en + #(.width_p(r_entry_high_bits_lp+r_entry_med_bits_lp)) + mem_reg + (.clk_i(clk_i) + ,.en_i(mem_2m_w_v_li[i]) + ,.data_i(entry_shifted[r_entry_low_bits_lp+:r_entry_med_bits_lp+r_entry_high_bits_lp]) + ,.data_o({data_2m_high_r[i], data_2m_med_r[i]}) + ); + end + + logic [els_1g_lp-1:0][r_entry_high_bits_lp-1:0] data_1g_high_r; + wire [els_1g_lp-1:0] mem_1g_w_v_li = ({els_1g_lp{fill_gigapage}} & repl_way_1g_lo); + if (els_1g_p == 0) begin assign data_1g_high_r = '0; end + else + for (genvar i = 0; i < els_1g_p; i++) + begin : mem_array_1g + bsg_dff_en + #(.width_p(r_entry_high_bits_lp)) + mem_reg + (.clk_i(clk_i) + ,.en_i(mem_1g_w_v_li[i]) + ,.data_i(entry_shifted[r_entry_low_bits_lp+r_entry_med_bits_lp+:r_entry_high_bits_lp]) + ,.data_o(data_1g_high_r[i]) + ); + end + + bp_pte_leaf_s r_entry; + bsg_mux_one_hot + #(.width_p(r_entry_low_bits_lp), .els_p(els_4k_p+1)) + one_hot_sel_low + (.data_i({passthrough_low_bits, data_4k_low_r}) + ,.sel_one_hot_i({(any_match_1g_lo | any_match_2m_lo), tag_r_match_4k_lo}) + ,.data_o(r_entry[0+:r_entry_low_bits_lp]) + ); + + bsg_mux_one_hot + #(.width_p(r_entry_med_bits_lp), .els_p(els_4k_p+els_2m_p+1)) + one_hot_sel_med + (.data_i({passthrough_med_bits, data_2m_med_r, data_4k_med_r}) + ,.sel_one_hot_i({any_match_1g_lo, tag_r_match_2m_lo, tag_r_match_4k_lo}) + ,.data_o(r_entry[r_entry_low_bits_lp+:r_entry_med_bits_lp]) + ); + + bsg_mux_one_hot + #(.width_p(r_entry_high_bits_lp), .els_p(els_4k_p+els_2m_p+els_1g_lp)) + one_hot_sel_high + (.data_i({data_1g_high_r, data_2m_high_r, data_4k_high_r}) + ,.sel_one_hot_i({tag_r_match_1g_lo, tag_r_match_2m_lo, tag_r_match_4k_lo}) + ,.data_o(r_entry[r_entry_low_bits_lp+r_entry_med_bits_lp+:r_entry_high_bits_lp]) + ); + + logic [`BSG_WIDTH(3)-1:0] match_cnt; + bsg_popcount + #(.width_p(3)) + mpc + (.i({any_match_1g_lo, any_match_2m_lo, any_match_4k_lo}) + ,.o(match_cnt) + ); + wire single_match = (match_cnt == 1'b1); + wire multi_match = (match_cnt > 1'b1); + + assign flush_4k_li = fence_i | (any_match_1g_lo & any_match_4k_lo) | (any_match_2m_lo & any_match_4k_lo); + assign flush_2m_li = fence_i | (any_match_1g_lo & any_match_2m_lo); + assign flush_1g_li = fence_i; + + // We shift so that ppn bits are LSB + bp_pte_leaf_s entry_unshifted; + bsg_rotate_right + #(.width_p($bits(bp_pte_leaf_s))) + entry_unshift + (.data_i(r_entry) + ,.rot_i(entry_shamt_lp) + ,.o(entry_unshifted) + ); + + assign entry_o = entry_unshifted; + assign v_o = single_match; + +endmodule + +`BSG_ABSTRACT_MODULE(bp_tlb) + diff --git a/designs/black-parrot/src/bp/bp_top_defines.svh b/designs/black-parrot/src/bp/bp_top_defines.svh new file mode 100644 index 0000000..28625c9 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_top_defines.svh @@ -0,0 +1,5 @@ +`ifndef BP_TOP_DEFINES_SVH +`define BP_TOP_DEFINES_SVH + +`endif + diff --git a/designs/black-parrot/src/bp/bp_top_pkg.sv b/designs/black-parrot/src/bp/bp_top_pkg.sv new file mode 100644 index 0000000..46b3e60 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_top_pkg.sv @@ -0,0 +1,7 @@ + + `include "bp_top_defines.svh" + +package bp_top_pkg; + +endpackage + diff --git a/designs/black-parrot/src/bp/bp_uce.sv b/designs/black-parrot/src/bp/bp_uce.sv new file mode 100644 index 0000000..2af5111 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_uce.sv @@ -0,0 +1,837 @@ +/** + * + * Name: + * bp_uce.sv + * + * Description: + * This is the top level module for the UCE + * + */ + +`include "bp_common_defines.svh" +`include "bp_me_defines.svh" + +module bp_uce + import bp_common_pkg::*; + import bp_me_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + , parameter `BSG_INV_PARAM(writeback_p) + , parameter `BSG_INV_PARAM(assoc_p) + , parameter `BSG_INV_PARAM(sets_p) + , parameter `BSG_INV_PARAM(block_width_p) + , parameter `BSG_INV_PARAM(fill_width_p) + , parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(tag_width_p) + , parameter `BSG_INV_PARAM(id_width_p) + + `declare_bp_cache_engine_generic_if_widths(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p, cache) + ) + (input clk_i + , input reset_i + + , input [did_width_p-1:0] did_i + , input [lce_id_width_p-1:0] lce_id_i + + , input [cache_req_width_lp-1:0] cache_req_i + , input cache_req_v_i + , output logic cache_req_yumi_o + , output logic cache_req_lock_o + , input [cache_req_metadata_width_lp-1:0] cache_req_metadata_i + , input cache_req_metadata_v_i + , output logic [id_width_p-1:0] cache_req_id_o + , output logic cache_req_critical_o + , output logic cache_req_last_o + , output logic cache_req_credits_full_o + , output logic cache_req_credits_empty_o + + , output logic [cache_tag_mem_pkt_width_lp-1:0] tag_mem_pkt_o + , output logic tag_mem_pkt_v_o + , input tag_mem_pkt_yumi_i + , input [cache_tag_info_width_lp-1:0] tag_mem_i + + , output logic [cache_data_mem_pkt_width_lp-1:0] data_mem_pkt_o + , output logic data_mem_pkt_v_o + , input data_mem_pkt_yumi_i + , input [block_width_p-1:0] data_mem_i + + , output logic [cache_stat_mem_pkt_width_lp-1:0] stat_mem_pkt_o + , output logic stat_mem_pkt_v_o + , input stat_mem_pkt_yumi_i + , input [cache_stat_info_width_lp-1:0] stat_mem_i + + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + ); + + localparam bank_width_lp = block_width_p / assoc_p; + localparam num_dwords_per_bank_lp = bank_width_lp / dword_width_gp; + localparam byte_offset_width_lp = `BSG_SAFE_CLOG2(bank_width_lp>>3); + // Words per line == associativity + localparam bank_offset_width_lp = `BSG_SAFE_CLOG2(assoc_p); + localparam block_offset_width_lp = (assoc_p > 1) ? (bank_offset_width_lp + byte_offset_width_lp) : byte_offset_width_lp; + localparam index_width_lp = `BSG_SAFE_CLOG2(sets_p); + localparam way_width_lp = `BSG_SAFE_CLOG2(assoc_p); + localparam block_size_in_fill_lp = block_width_p / fill_width_p; + localparam fill_size_in_bank_lp = fill_width_p / bank_width_lp; + localparam fill_cnt_width_lp = `BSG_SAFE_CLOG2(block_size_in_fill_lp); + localparam fill_offset_width_lp = `BSG_SAFE_CLOG2(fill_width_p>>3); + localparam bank_sub_offset_width_lp = $clog2(fill_size_in_bank_lp); + + localparam bp_bedrock_msg_size_e block_msg_size_lp = (block_width_p == 512) + ? e_bedrock_msg_size_64 + : (block_width_p == 256) + ? e_bedrock_msg_size_32 + : (block_width_p == 128) + ? e_bedrock_msg_size_16 + : (block_width_p == 64) + ? e_bedrock_msg_size_8 + : e_bedrock_msg_size_64; + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_cache_engine_generic_if(paddr_width_p, tag_width_p, sets_p, assoc_p, data_width_p, block_width_p, fill_width_p, id_width_p, cache); + + `bp_cast_i(bp_cache_req_s, cache_req); + `bp_cast_i(bp_cache_req_metadata_s, cache_req_metadata); + `bp_cast_o(bp_cache_tag_mem_pkt_s, tag_mem_pkt); + `bp_cast_o(bp_cache_data_mem_pkt_s, data_mem_pkt); + `bp_cast_o(bp_cache_stat_mem_pkt_s, stat_mem_pkt); + + enum logic [4:0] { + e_reset + ,e_init + ,e_backoff + ,e_inval + ,e_clean_read + ,e_clean_scan + ,e_clean_write + ,e_clean_fence + ,e_bclean_evict + ,e_bclean_writeback_req + ,e_ready + ,e_uc_writeback_evict + ,e_uc_writeback_write_req + ,e_send_critical + ,e_writeback_evict + ,e_writeback_read_wait + ,e_writeback_write_req + ,e_write_wait + ,e_read_wait + ,e_uc_read_wait + } state_n, state_r; + + wire is_reset = (state_r == e_reset); + wire is_backoff = (state_r == e_backoff); + wire is_inval = (state_r == e_inval); + wire is_init = (state_r == e_init); + wire is_clean_read = (state_r == e_clean_read); + wire is_clean_scan = (state_r == e_clean_scan); + wire is_clean_write = (state_r == e_clean_write); + wire is_clean_fence = (state_r == e_clean_fence); + wire is_ready = (state_r == e_ready); + wire is_send_critical = (state_r == e_send_critical); + wire is_writeback_evict = (state_r == e_writeback_evict); // read dirty data from cache to UCE + wire is_writeback_read = (state_r == e_writeback_read_wait); // read data from L2 to cache + wire is_writeback_wb = (state_r == e_writeback_write_req); // send dirty data from UCE to L2 + wire is_write_request = (state_r == e_write_wait); + wire is_read_request = (state_r == e_read_wait); + wire is_uc_read_wait = (state_r == e_uc_read_wait); + + logic cache_req_ready_lo; + bp_cache_req_s cache_req_r; + logic cache_req_v_r, cache_req_done; + bsg_two_fifo + #(.width_p($bits(bp_cache_req_s)), .ready_THEN_valid_p(1)) + cache_req_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(cache_req_cast_i) + ,.v_i(cache_req_yumi_o) + ,.ready_param_o(cache_req_ready_lo) + + ,.data_o(cache_req_r) + ,.v_o(cache_req_v_r) + ,.yumi_i(cache_req_v_r & cache_req_done) + ); + + bp_cache_req_metadata_s cache_req_metadata, cache_req_metadata_r; + logic cache_req_metadata_v_r; + bsg_two_fifo + #(.width_p($bits(bp_cache_req_metadata_s)), .ready_THEN_valid_p(1)) + cache_req_metadata_fifo + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(cache_req_metadata_cast_i) + ,.v_i(cache_req_metadata_v_i & (cache_req_metadata_v_r | ~cache_req_done)) + ,.ready_param_o(/* Follows cache req fifo */) + + ,.data_o(cache_req_metadata_r) + ,.v_o(cache_req_metadata_v_r) + ,.yumi_i(cache_req_metadata_v_r & cache_req_done) + ); + assign cache_req_metadata = cache_req_metadata_v_r ? cache_req_metadata_r : cache_req_metadata_cast_i; + wire cache_req_metadata_v = cache_req_metadata_v_i | cache_req_metadata_v_r; + + logic [block_width_p-1:0] dirty_data_r; + wire dirty_data_read = data_mem_pkt_v_o & (data_mem_pkt_cast_o.opcode == e_cache_data_mem_read); + bsg_dff_sync_read + #(.width_p(block_width_p), .bypass_p(1)) + dirty_data_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(data_mem_i) + ,.v_n_i(dirty_data_read) + + ,.data_o(dirty_data_r) + ); + + bp_cache_tag_info_s dirty_tag_r; + wire dirty_tag_read = tag_mem_pkt_v_o & (tag_mem_pkt_cast_o.opcode == e_cache_tag_mem_read); + bsg_dff_sync_read + #(.width_p($bits(bp_cache_tag_info_s)), .bypass_p(1)) + dirty_tag_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(tag_mem_i) + ,.v_n_i(dirty_tag_read) + + ,.data_o(dirty_tag_r) + ); + + bp_cache_stat_info_s dirty_stat_r; + wire dirty_stat_read = stat_mem_pkt_v_o & (stat_mem_pkt_cast_o.opcode == e_cache_stat_mem_read); + bsg_dff_sync_read + #(.width_p($bits(bp_cache_stat_info_s)), .bypass_p(1)) + dirty_stat_reg + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.data_i(stat_mem_i) + ,.v_n_i(dirty_stat_read) + + ,.data_o(dirty_stat_r) + ); + + bp_bedrock_mem_fwd_header_s fsm_fwd_header_lo; + logic [fill_width_p-1:0] fsm_fwd_data_lo; + logic fsm_fwd_v_lo, fsm_fwd_ready_then_li; + logic [paddr_width_p-1:0] fsm_fwd_addr_lo; + logic fsm_fwd_new_lo, fsm_fwd_critical_lo, fsm_fwd_last_lo; + bp_me_stream_pump_out + #(.bp_params_p(bp_params_p) + ,.data_width_p(fill_width_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.msg_stream_mask_p(mem_fwd_stream_mask_gp) + ,.fsm_stream_mask_p(mem_fwd_stream_mask_gp) + ) + uce_pump_out + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_o(mem_fwd_header_o) + ,.msg_data_o(mem_fwd_data_o) + ,.msg_v_o(mem_fwd_v_o) + ,.msg_ready_and_i(mem_fwd_ready_and_i) + + ,.fsm_header_i(fsm_fwd_header_lo) + ,.fsm_data_i(fsm_fwd_data_lo) + ,.fsm_v_i(fsm_fwd_v_lo) + ,.fsm_ready_then_o(fsm_fwd_ready_then_li) + ,.fsm_addr_o(fsm_fwd_addr_lo) + ,.fsm_new_o(fsm_fwd_new_lo) + ,.fsm_critical_o(fsm_fwd_critical_lo) + ,.fsm_last_o(fsm_fwd_last_lo) + ); + + bp_bedrock_mem_rev_header_s fsm_rev_header_li; + logic [fill_width_p-1:0] fsm_rev_data_li; + logic fsm_rev_v_li, fsm_rev_yumi_lo; + logic [paddr_width_p-1:0] fsm_rev_addr_li; + logic fsm_rev_new_li, fsm_rev_critical_li, fsm_rev_last_li; + bp_me_stream_pump_in + #(.bp_params_p(bp_params_p) + ,.data_width_p(fill_width_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.msg_stream_mask_p(mem_rev_stream_mask_gp) + ,.fsm_stream_mask_p(mem_rev_stream_mask_gp) + ) + uce_pump_in + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.msg_header_i(mem_rev_header_i) + ,.msg_data_i(mem_rev_data_i) + ,.msg_v_i(mem_rev_v_i) + ,.msg_ready_and_o(mem_rev_ready_and_o) + + ,.fsm_header_o(fsm_rev_header_li) + ,.fsm_data_o(fsm_rev_data_li) + ,.fsm_v_o(fsm_rev_v_li) + ,.fsm_yumi_i(fsm_rev_yumi_lo) + ,.fsm_addr_o(fsm_rev_addr_li) + ,.fsm_new_o(fsm_rev_new_li) + ,.fsm_critical_o(fsm_rev_critical_li) + ,.fsm_last_o(fsm_rev_last_li) + ); + + // We check for uncached stores ealier than other requests, because they get sent out in ready + wire miss_load_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_miss_load}; + wire miss_store_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_miss_store}; + wire miss_v_li = cache_req_v_i & miss_load_v_li | miss_store_v_li; + wire wt_store_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_wt_store}; + wire uc_load_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_uc_load}; + wire uc_store_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_uc_store}; + wire uc_amo_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_uc_amo}; + wire uc_evict_v_li = (uc_load_v_li | uc_store_v_li | uc_amo_v_li) & writeback_p & cache_req_cast_i.hit; + wire inval_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_cache_inval}; + wire clean_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_cache_clean}; + wire flush_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_cache_flush}; + wire binval_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_cache_binval}; + wire bclean_v_li = cache_req_v_i & cache_req_cast_i.msg_type inside {e_cache_bclean}; + wire nonblocking_v_li = cache_req_v_i & (uc_store_v_li | wt_store_v_li) & ~uc_evict_v_li; + + wire store_resp_v_li = fsm_rev_v_li & fsm_rev_header_li.msg_type inside {e_bedrock_mem_wr}; + wire load_resp_v_li = fsm_rev_v_li & fsm_rev_header_li.msg_type inside {e_bedrock_mem_rd, e_bedrock_mem_amo}; + + wire miss_load_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_miss_load}; + wire miss_store_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_miss_store}; + wire miss_v_r = cache_req_v_r & miss_load_v_r | miss_store_v_r; + wire wt_store_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_wt_store}; + wire uc_load_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_uc_load}; + wire uc_store_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_uc_store}; + wire uc_amo_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_uc_amo}; + wire uc_evict_v_r = (uc_load_v_r | uc_store_v_r | uc_amo_v_r) & writeback_p & cache_req_r.hit; + wire inval_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_cache_inval}; + wire clean_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_cache_clean}; + wire flush_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_cache_flush}; + wire binval_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_cache_binval}; + wire bclean_v_r = cache_req_v_r & cache_req_r.msg_type inside {e_cache_bclean}; + wire nonblocking_v_r = cache_req_v_r & (uc_store_v_r | wt_store_v_r) & ~uc_evict_v_r; + + wire [block_size_in_fill_lp-1:0] fill_index_shift = (assoc_p > 1) ? (fsm_rev_addr_li[byte_offset_width_lp+:bank_offset_width_lp] >> bank_sub_offset_width_lp) : '0; + + logic [index_width_lp-1:0] index_cnt; + logic index_clear, index_up; + bsg_counter_clear_up + #(.max_val_p(sets_p-1) + ,.init_val_p(0) + ,.disable_overflow_warning_p(1) + ) + index_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(index_clear) + ,.up_i(index_up) + + ,.count_o(index_cnt) + ); + wire index_done = index_up && ((sets_p == 1) || (index_cnt == sets_p-1)); + + logic [`BSG_SAFE_CLOG2(assoc_p)-1:0] way_cnt; + logic way_clear, way_up; + bsg_counter_clear_up + #(.max_val_p(assoc_p-1) + ,.init_val_p(0) + ,.disable_overflow_warning_p(1) + ) + way_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(way_clear) + ,.up_i(way_up) + + ,.count_o(way_cnt) + ); + wire way_done = way_up && ((assoc_p == 1) || (way_cnt == assoc_p-1)); + + // Outstanding Requests Counter - counts all requests, cached and uncached + // + logic [`BSG_WIDTH(coh_noc_max_credits_p)-1:0] credit_count_lo; + bsg_flow_counter + #(.els_p(coh_noc_max_credits_p), .ready_THEN_valid_p(1)) + credit_counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + // credit consumed when memory command sends + ,.v_i(fsm_fwd_v_lo & fsm_fwd_last_lo) + ,.ready_param_i(fsm_fwd_ready_then_li) + + // credit returned when memory response fully consumed + ,.yumi_i(fsm_rev_yumi_lo & fsm_rev_last_li) + ,.count_o(credit_count_lo) + ); + assign cache_req_credits_full_o = cache_req_v_r && (credit_count_lo == coh_noc_max_credits_p); + assign cache_req_credits_empty_o = ~cache_req_v_r && (credit_count_lo == 0); + + logic [fill_width_p-1:0] writeback_data; + wire [fill_cnt_width_lp-1:0] dirty_data_select = fsm_fwd_addr_lo[fill_offset_width_lp+:fill_cnt_width_lp]; + bsg_mux + #(.width_p(fill_width_p), .els_p(block_size_in_fill_lp)) + writeback_mux + (.data_i(dirty_data_r) + ,.sel_i(dirty_data_select) + ,.data_o(writeback_data) + ); + + bp_cache_req_wr_subop_e cache_wr_subop; + bp_bedrock_wr_subop_e mem_wr_subop; + always_comb + begin + cache_wr_subop = cache_req_r.subop; + unique case (cache_wr_subop) + e_req_amolr : mem_wr_subop = e_bedrock_amolr; + e_req_amosc : mem_wr_subop = e_bedrock_amosc; + e_req_amoswap: mem_wr_subop = e_bedrock_amoswap; + e_req_amoadd : mem_wr_subop = e_bedrock_amoadd; + e_req_amoxor : mem_wr_subop = e_bedrock_amoxor; + e_req_amoand : mem_wr_subop = e_bedrock_amoand; + e_req_amoor : mem_wr_subop = e_bedrock_amoor; + e_req_amomin : mem_wr_subop = e_bedrock_amomin; + e_req_amomax : mem_wr_subop = e_bedrock_amomax; + e_req_amominu: mem_wr_subop = e_bedrock_amominu; + e_req_amomaxu: mem_wr_subop = e_bedrock_amomaxu; + default : mem_wr_subop = e_bedrock_store; + endcase + end + + // We ack mem_revs for stores no matter what, so load_resp_yumi_lo is for other responses + logic load_resp_yumi_lo; + assign fsm_rev_yumi_lo = load_resp_yumi_lo | store_resp_v_li; + assign cache_req_lock_o = is_reset | is_init | inval_v_r | clean_v_r | flush_v_r; + logic blocking_req_v_lo; + always_comb + begin + cache_req_yumi_o = '0; + + index_up = '0; + index_clear = '0; + way_up = '0; + way_clear = '0; + + tag_mem_pkt_cast_o = '0; + tag_mem_pkt_v_o = '0; + data_mem_pkt_cast_o = '0; + data_mem_pkt_v_o = '0; + stat_mem_pkt_cast_o = '0; + stat_mem_pkt_v_o = '0; + + cache_req_critical_o = '0; + cache_req_last_o = '0; + cache_req_done = '0; + + fsm_fwd_header_lo = '0; + fsm_fwd_data_lo = '0; + fsm_fwd_v_lo = '0; + + load_resp_yumi_lo = '0; + + state_n = state_r; + + unique case (state_r) + e_reset: + begin + state_n = e_init; + end + + e_init, e_inval: + begin + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_clear; + tag_mem_pkt_cast_o.index = index_cnt; + tag_mem_pkt_v_o = 1'b1; + + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_set_clear; + stat_mem_pkt_cast_o.index = index_cnt; + stat_mem_pkt_v_o = 1'b1; + + index_up = tag_mem_pkt_yumi_i & stat_mem_pkt_yumi_i; + + cache_req_critical_o = is_inval & index_done; + cache_req_last_o = cache_req_critical_o; + cache_req_done = cache_req_last_o; + + state_n = (index_done & index_up) ? e_ready : state_r; + end + + e_backoff: + begin + state_n = fsm_fwd_ready_then_li ? e_ready : state_r; + end + + e_clean_read: + begin + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_read; + stat_mem_pkt_cast_o.index = index_cnt; + stat_mem_pkt_v_o = 1'b1; + + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_inval; + tag_mem_pkt_cast_o.index = index_cnt; + tag_mem_pkt_v_o = flush_v_r; + + state_n = (stat_mem_pkt_yumi_i & (~tag_mem_pkt_v_o | tag_mem_pkt_yumi_i)) + ? e_clean_scan + : state_r; + end + + e_clean_scan: + if (~|dirty_stat_r) + begin + way_clear = 1'b1; + index_up = way_clear; + + state_n = index_done + ? e_clean_fence + : e_clean_read; + end + else if (dirty_stat_r[way_cnt]) + begin + data_mem_pkt_cast_o.opcode = e_cache_data_mem_read; + data_mem_pkt_cast_o.index = index_cnt; + data_mem_pkt_cast_o.way_id = way_cnt; + data_mem_pkt_cast_o.fill_index = {block_size_in_fill_lp{1'b1}}; + data_mem_pkt_v_o = 1'b1; + + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_read; + tag_mem_pkt_cast_o.index = index_cnt; + tag_mem_pkt_cast_o.way_id = way_cnt; + tag_mem_pkt_v_o = 1'b1; + + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_clear_dirty; + stat_mem_pkt_cast_o.index = index_cnt; + stat_mem_pkt_cast_o.way_id = way_cnt; + stat_mem_pkt_v_o = 1'b1; + + state_n = (data_mem_pkt_yumi_i & tag_mem_pkt_yumi_i & stat_mem_pkt_yumi_i) + ? e_clean_write + : state_r; + end + else + begin + way_up = 1'b1; + index_up = way_done; + + state_n = (index_done & way_done) + ? e_clean_fence + : way_done + ? e_clean_read + : e_clean_scan; + end + + e_clean_write: + begin + fsm_fwd_header_lo.msg_type = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = {dirty_tag_r.tag, index_cnt, block_offset_width_lp'(0)}; + fsm_fwd_header_lo.size = block_msg_size_lp; + fsm_fwd_header_lo.payload.way_id = lce_assoc_p'(cache_req_metadata.hit_or_repl_way); + fsm_fwd_header_lo.payload.lce_id = lce_id_i; + fsm_fwd_header_lo.payload.src_did = did_i; + fsm_fwd_data_lo = writeback_data; + fsm_fwd_v_lo = fsm_fwd_ready_then_li & ~cache_req_credits_full_o; + + way_up = fsm_fwd_v_lo & fsm_fwd_last_lo; + index_up = way_done; + + state_n = (index_done & way_done) + ? e_clean_fence + : index_up + ? e_clean_read + : way_up + ? e_clean_scan + : e_clean_write; + end + + e_clean_fence: + begin + cache_req_critical_o = (credit_count_lo == '0); + cache_req_last_o = cache_req_critical_o; + cache_req_done = cache_req_last_o; + + state_n = cache_req_last_o ? e_ready : state_r; + end + + e_bclean_evict: + begin + data_mem_pkt_cast_o.opcode = e_cache_data_mem_read; + data_mem_pkt_cast_o.index = cache_req_r.addr[block_offset_width_lp+:index_width_lp]; + data_mem_pkt_cast_o.way_id = cache_req_metadata.hit_or_repl_way; + data_mem_pkt_cast_o.fill_index = {block_size_in_fill_lp{1'b1}}; + data_mem_pkt_v_o = 1'b1; + + state_n = data_mem_pkt_yumi_i ? e_bclean_writeback_req : state_r; + end + + e_bclean_writeback_req: + begin + fsm_fwd_header_lo.msg_type = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = {cache_req_r.addr[paddr_width_p-1:block_offset_width_lp], block_offset_width_lp'(0)}; + fsm_fwd_header_lo.size = block_msg_size_lp; + fsm_fwd_header_lo.payload.way_id = lce_assoc_p'(cache_req_metadata.hit_or_repl_way); + fsm_fwd_header_lo.payload.lce_id = lce_id_i; + fsm_fwd_data_lo = writeback_data; + fsm_fwd_v_lo = fsm_fwd_ready_then_li & cache_req_metadata.dirty; + + cache_req_done = ~cache_req_metadata.dirty || (fsm_fwd_v_lo & fsm_fwd_last_lo); + + state_n = cache_req_done ? e_ready : state_r; + end + + e_ready: + begin + cache_req_yumi_o = cache_req_v_i & cache_req_ready_lo & (~cache_req_v_r | nonblocking_v_li); + + state_n = cache_req_yumi_o + ? (flush_v_li | clean_v_li) + ? e_clean_read + : inval_v_li + ? e_inval + : bclean_v_li + ? e_bclean_evict + : uc_evict_v_li + ? e_uc_writeback_evict + : nonblocking_v_li + ? e_ready + : e_send_critical + : cache_req_v_i ? e_backoff : state_r; + end + + e_uc_writeback_evict: + begin + data_mem_pkt_cast_o.opcode = e_cache_data_mem_read; + data_mem_pkt_cast_o.index = cache_req_r.addr[block_offset_width_lp+:index_width_lp]; + data_mem_pkt_cast_o.way_id = cache_req_metadata.hit_or_repl_way; + data_mem_pkt_cast_o.fill_index = {block_size_in_fill_lp{1'b1}}; + data_mem_pkt_v_o = cache_req_metadata.dirty; + + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_clear_dirty; + stat_mem_pkt_cast_o.index = cache_req_r.addr[block_offset_width_lp+:index_width_lp]; + stat_mem_pkt_cast_o.way_id = cache_req_metadata.hit_or_repl_way; + stat_mem_pkt_v_o = cache_req_metadata.dirty; + + state_n = cache_req_metadata.dirty + ? (data_mem_pkt_yumi_i & stat_mem_pkt_yumi_i) + ? e_uc_writeback_write_req + : state_r + : e_send_critical; + end + + e_uc_writeback_write_req: + begin + fsm_fwd_header_lo.msg_type = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = {cache_req_r.addr[paddr_width_p-1:block_offset_width_lp], block_offset_width_lp'(0)}; + fsm_fwd_header_lo.size = block_msg_size_lp; + fsm_fwd_header_lo.payload.way_id = lce_assoc_p'(cache_req_metadata.hit_or_repl_way); + fsm_fwd_header_lo.payload.lce_id = lce_id_i; + fsm_fwd_header_lo.payload.src_did = did_i; + fsm_fwd_data_lo = writeback_data; + fsm_fwd_v_lo = fsm_fwd_ready_then_li & ~cache_req_credits_full_o; + + state_n = (fsm_fwd_v_lo & fsm_fwd_last_lo) + ? e_send_critical + : state_r; + end + + e_send_critical: + if (miss_v_r) + begin + fsm_fwd_header_lo.msg_type = e_bedrock_mem_rd; + fsm_fwd_header_lo.addr = cache_req_r.addr; + fsm_fwd_header_lo.size = bp_bedrock_msg_size_e'(cache_req_r.size); + fsm_fwd_header_lo.payload.way_id = lce_assoc_p'(cache_req_metadata.hit_or_repl_way); + fsm_fwd_header_lo.payload.lce_id = lce_id_i; + fsm_fwd_header_lo.payload.src_did = did_i; + fsm_fwd_v_lo = fsm_fwd_ready_then_li & ~cache_req_credits_full_o; + + state_n = (fsm_fwd_v_lo & fsm_fwd_last_lo) + ? cache_req_metadata.dirty + ? e_writeback_evict + : e_read_wait + : state_r; + end + else if (uc_load_v_r | uc_amo_v_r) + begin + fsm_fwd_header_lo.msg_type = uc_load_v_r ? e_bedrock_mem_rd : e_bedrock_mem_amo; + fsm_fwd_header_lo.addr = cache_req_r.addr; + fsm_fwd_header_lo.size = bp_bedrock_msg_size_e'(cache_req_r.size); + fsm_fwd_header_lo.payload.way_id = lce_assoc_p'(cache_req_metadata.hit_or_repl_way); + fsm_fwd_header_lo.payload.lce_id = lce_id_i; + fsm_fwd_header_lo.payload.src_did = did_i; + fsm_fwd_header_lo.subop = mem_wr_subop; + fsm_fwd_data_lo = {fill_width_p/dword_width_gp{cache_req_r.data}}; + fsm_fwd_v_lo = fsm_fwd_ready_then_li & ~cache_req_credits_full_o; + + state_n = (fsm_fwd_v_lo & fsm_fwd_last_lo) ? e_uc_read_wait : state_r; + end + else if (uc_store_v_r) + begin + fsm_fwd_header_lo.msg_type = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = cache_req_r.addr; + fsm_fwd_header_lo.size = bp_bedrock_msg_size_e'(cache_req_r.size); + fsm_fwd_header_lo.payload.way_id = lce_assoc_p'(cache_req_metadata.hit_or_repl_way); + fsm_fwd_header_lo.payload.lce_id = lce_id_i; + fsm_fwd_header_lo.payload.src_did = did_i; + fsm_fwd_header_lo.subop = mem_wr_subop; + fsm_fwd_data_lo = {fill_width_p/dword_width_gp{cache_req_r.data}}; + fsm_fwd_v_lo = fsm_fwd_ready_then_li & ~cache_req_credits_full_o; + + cache_req_done = fsm_fwd_v_lo & fsm_fwd_last_lo; + + state_n = cache_req_done ? e_ready : state_r; + end + + e_writeback_evict: + begin + data_mem_pkt_cast_o.opcode = e_cache_data_mem_read; + data_mem_pkt_cast_o.index = cache_req_r.addr[block_offset_width_lp+:index_width_lp]; + data_mem_pkt_cast_o.way_id = cache_req_metadata.hit_or_repl_way; + data_mem_pkt_cast_o.fill_index = {block_size_in_fill_lp{1'b1}}; + data_mem_pkt_v_o = 1'b1; + + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_read; + tag_mem_pkt_cast_o.index = cache_req_r.addr[block_offset_width_lp+:index_width_lp]; + tag_mem_pkt_cast_o.way_id = cache_req_metadata.hit_or_repl_way; + tag_mem_pkt_v_o = 1'b1; + + stat_mem_pkt_cast_o.opcode = e_cache_stat_mem_clear_dirty; + stat_mem_pkt_cast_o.index = cache_req_r.addr[block_offset_width_lp+:index_width_lp]; + stat_mem_pkt_cast_o.way_id = cache_req_metadata.hit_or_repl_way; + stat_mem_pkt_v_o = 1'b1; + + state_n = (data_mem_pkt_yumi_i & tag_mem_pkt_yumi_i & stat_mem_pkt_yumi_i) ? e_writeback_read_wait : e_writeback_evict; + end + + e_writeback_read_wait: + begin + // send the sub-block from L2 to cache + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_tag; + tag_mem_pkt_cast_o.index = fsm_rev_addr_li[block_offset_width_lp+:index_width_lp]; + // We fill in M because we don't want to trigger additional coherence traffic + tag_mem_pkt_cast_o.way_id = fsm_rev_header_li.payload.way_id[0+:`BSG_SAFE_CLOG2(assoc_p)]; + tag_mem_pkt_cast_o.state = e_COH_M; + tag_mem_pkt_cast_o.tag = fsm_rev_addr_li[block_offset_width_lp+index_width_lp+:tag_width_p]; + tag_mem_pkt_v_o = load_resp_v_li & fsm_rev_new_li; + + data_mem_pkt_cast_o.opcode = e_cache_data_mem_write; + data_mem_pkt_cast_o.index = fsm_rev_addr_li[block_offset_width_lp+:index_width_lp]; + data_mem_pkt_cast_o.way_id = fsm_rev_header_li.payload.way_id[0+:`BSG_SAFE_CLOG2(assoc_p)]; + data_mem_pkt_cast_o.data = fsm_rev_data_li; + data_mem_pkt_cast_o.fill_index = 1'b1 << fill_index_shift; + data_mem_pkt_v_o = load_resp_v_li; + + load_resp_yumi_lo = (~fsm_rev_new_li | tag_mem_pkt_yumi_i) && data_mem_pkt_yumi_i; + + cache_req_critical_o = load_resp_v_li & fsm_rev_critical_li; + cache_req_last_o = load_resp_v_li & fsm_rev_last_li; + + state_n = (load_resp_yumi_lo & cache_req_last_o) ? e_writeback_write_req : e_writeback_read_wait; + end + + e_writeback_write_req: + begin + fsm_fwd_header_lo.msg_type = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = {dirty_tag_r.tag, cache_req_r.addr[block_offset_width_lp+:index_width_lp], block_offset_width_lp'(0)}; + fsm_fwd_header_lo.size = block_msg_size_lp; + fsm_fwd_header_lo.payload.way_id = lce_assoc_p'(cache_req_metadata.hit_or_repl_way); + fsm_fwd_header_lo.payload.lce_id = lce_id_i; + fsm_fwd_header_lo.payload.src_did = did_i; + fsm_fwd_data_lo = writeback_data; + fsm_fwd_v_lo = fsm_fwd_ready_then_li & ~cache_req_credits_full_o; + + cache_req_done = fsm_fwd_v_lo & fsm_fwd_last_lo; + + state_n = cache_req_done ? e_ready : e_writeback_write_req; + end + + e_read_wait: + begin + // send the sub-block from L2 to cache + tag_mem_pkt_cast_o.opcode = e_cache_tag_mem_set_tag; + tag_mem_pkt_cast_o.index = fsm_rev_addr_li[block_offset_width_lp+:index_width_lp]; + // We fill in M because we don't want to trigger additional coherence traffic + tag_mem_pkt_cast_o.way_id = fsm_rev_header_li.payload.way_id[0+:`BSG_SAFE_CLOG2(assoc_p)]; + tag_mem_pkt_cast_o.state = e_COH_M; + tag_mem_pkt_cast_o.tag = fsm_rev_addr_li[block_offset_width_lp+index_width_lp+:tag_width_p]; + tag_mem_pkt_v_o = load_resp_v_li & fsm_rev_new_li; + + data_mem_pkt_cast_o.opcode = e_cache_data_mem_write; + data_mem_pkt_cast_o.index = fsm_rev_addr_li[block_offset_width_lp+:index_width_lp]; + data_mem_pkt_cast_o.way_id = fsm_rev_header_li.payload.way_id[0+:`BSG_SAFE_CLOG2(assoc_p)]; + data_mem_pkt_cast_o.data = fsm_rev_data_li; + data_mem_pkt_cast_o.fill_index = 1'b1 << fill_index_shift; + data_mem_pkt_v_o = load_resp_v_li; + + load_resp_yumi_lo = (~fsm_rev_new_li | tag_mem_pkt_yumi_i) && data_mem_pkt_yumi_i; + + cache_req_critical_o = load_resp_v_li & fsm_rev_critical_li; + cache_req_last_o = load_resp_v_li & fsm_rev_last_li; + cache_req_done = cache_req_last_o & load_resp_yumi_lo; + + state_n = cache_req_done ? e_ready : e_read_wait; + end + + e_uc_read_wait: + begin + data_mem_pkt_cast_o.opcode = e_cache_data_mem_uncached; + data_mem_pkt_cast_o.data = {(fill_width_p/dword_width_gp){fsm_rev_data_li[0+:dword_width_gp]}}; + data_mem_pkt_v_o = load_resp_v_li; + + load_resp_yumi_lo = data_mem_pkt_yumi_i; + + cache_req_critical_o = load_resp_v_li & fsm_rev_critical_li; + cache_req_last_o = load_resp_v_li & fsm_rev_last_li; + cache_req_done = cache_req_last_o & load_resp_yumi_lo; + + state_n = cache_req_done ? e_ready : e_uc_read_wait; + end + default: state_n = e_reset; + endcase + + // Fire off a non-blocking request opportunistically if we have one + // Could eke out some performance by changing ~fsm_fwd_v_lo to blocking_req_v_lo + //if (nonblocking_v_r & ~fsm_fwd_v_lo) + if (is_ready & nonblocking_v_r) + begin + fsm_fwd_header_lo.msg_type = e_bedrock_mem_wr; + fsm_fwd_header_lo.addr = cache_req_r.addr; + fsm_fwd_header_lo.size = bp_bedrock_msg_size_e'(cache_req_r.size); + fsm_fwd_header_lo.payload.way_id = lce_assoc_p'(cache_req_metadata.hit_or_repl_way); + fsm_fwd_header_lo.payload.lce_id = lce_id_i; + fsm_fwd_header_lo.payload.src_did = did_i; + fsm_fwd_header_lo.subop = wt_store_v_r ? e_bedrock_store : mem_wr_subop; + fsm_fwd_data_lo = {fill_width_p/dword_width_gp{cache_req_r.data}}; + fsm_fwd_v_lo = fsm_fwd_ready_then_li & ~cache_req_credits_full_o; + + cache_req_done = fsm_fwd_v_lo & fsm_fwd_last_lo; + end + end + + // synopsys sync_set_reset "reset_i" + always_ff @(posedge clk_i) + if (reset_i) + state_r <= e_reset; + else + state_r <= state_n; + + // synopsys translate_off + always_ff @(negedge clk_i) + assert(reset_i !== '0 || (writeback_p == 1) || !(state_r inside {e_uc_writeback_evict, e_writeback_evict, e_uc_writeback_write_req, e_writeback_read_wait, e_writeback_write_req})) + else $error("writethrough cache should not be in writeback states"); + // synopsys translate_on + +endmodule + +`BSG_ABSTRACT_MODULE(bp_uce) + diff --git a/designs/black-parrot/src/bp/bp_unicore.sv b/designs/black-parrot/src/bp/bp_unicore.sv new file mode 100644 index 0000000..69ac5df --- /dev/null +++ b/designs/black-parrot/src/bp/bp_unicore.sv @@ -0,0 +1,383 @@ +/** + * + * Name: + * bp_unicore.sv + * + * Description: + * This is the top level module for a unicore BlackParrot processor. + * + */ + +`include "bp_common_defines.svh" +`include "bp_fe_defines.svh" +`include "bp_be_defines.svh" +`include "bp_me_defines.svh" +`include "bp_top_defines.svh" +`include "bsg_cache.svh" +`include "bsg_noc_links.svh" + +module bp_unicore + import bsg_wormhole_router_pkg::*; + import bp_common_pkg::*; + import bp_fe_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + import bp_top_pkg::*; + import bsg_noc_pkg::*; + import bsg_cache_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam dma_pkt_width_lp = `bsg_cache_dma_pkt_width(daddr_width_p, l2_block_size_in_words_p) + ) + (input clk_i + , input rt_clk_i + , input reset_i + + , input [mem_noc_did_width_p-1:0] my_did_i + , input [mem_noc_did_width_p-1:0] host_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + + // Outgoing I/O + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + + // Incoming I/O + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + // DRAM interface + , output logic [l2_slices_p-1:0][l2_banks_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_o + , output logic [l2_slices_p-1:0][l2_banks_p-1:0] dma_pkt_v_o + , input [l2_slices_p-1:0][l2_banks_p-1:0] dma_pkt_ready_and_i + + , input [l2_slices_p-1:0][l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_i + , input [l2_slices_p-1:0][l2_banks_p-1:0] dma_data_v_i + , output logic [l2_slices_p-1:0][l2_banks_p-1:0] dma_data_ready_and_o + + , output logic [l2_slices_p-1:0][l2_banks_p-1:0][l2_fill_width_p-1:0] dma_data_o + , output logic [l2_slices_p-1:0][l2_banks_p-1:0] dma_data_v_o + , input [l2_slices_p-1:0][l2_banks_p-1:0] dma_data_ready_and_i + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `declare_bp_memory_map(paddr_width_p, daddr_width_p); + + // Reset + logic reset_r; + always_ff @(posedge clk_i) + reset_r <= reset_i; + + localparam icache_proc_id_lp = 0; + localparam dcache_proc_id_lp = icache_proc_id_lp + 1; + localparam io_proc_id_lp = dcache_proc_id_lp + 1; + localparam num_proc_lp = io_proc_id_lp + 1; + localparam lg_num_proc_lp = `BSG_SAFE_CLOG2(num_proc_lp); + + localparam cfg_dev_id_lp = 0; + localparam clint_dev_id_lp = cfg_dev_id_lp + 1; + localparam l2s_dev_base_id_lp = clint_dev_id_lp + 1; + localparam loopback_dev_id_lp = l2s_dev_base_id_lp + l2_slices_p; + localparam io_dev_id_lp = loopback_dev_id_lp + 1; + localparam num_dev_lp = io_dev_id_lp + 1; + localparam lg_num_dev_lp = `BSG_SAFE_CLOG2(num_dev_lp); + + // {IO, BE UCE, FE UCE} + bp_bedrock_mem_fwd_header_s [num_proc_lp-1:0] proc_fwd_header_lo; + logic [num_proc_lp-1:0][bedrock_fill_width_p-1:0] proc_fwd_data_lo; + logic [num_proc_lp-1:0] proc_fwd_v_lo, proc_fwd_ready_and_li; + bp_bedrock_mem_rev_header_s [num_proc_lp-1:0] proc_rev_header_li; + logic [num_proc_lp-1:0][bedrock_fill_width_p-1:0] proc_rev_data_li; + logic [num_proc_lp-1:0] proc_rev_v_li, proc_rev_ready_and_lo; + + // {LOOPBACK, IO, L2, CLINT, CFG} + bp_bedrock_mem_fwd_header_s [num_dev_lp-1:0] dev_fwd_header_li; + logic [num_dev_lp-1:0][bedrock_fill_width_p-1:0] dev_fwd_data_li; + logic [num_dev_lp-1:0] dev_fwd_v_li, dev_fwd_ready_and_lo; + bp_bedrock_mem_rev_header_s [num_dev_lp-1:0] dev_rev_header_lo; + logic [num_dev_lp-1:0][bedrock_fill_width_p-1:0] dev_rev_data_lo; + logic [num_dev_lp-1:0] dev_rev_v_lo, dev_rev_ready_and_li; + + bp_cfg_bus_s cfg_bus_lo; + logic debug_irq_li, timer_irq_li, software_irq_li, m_external_irq_li, s_external_irq_li; + bp_unicore_lite + #(.bp_params_p(bp_params_p)) + unicore_lite + (.clk_i(clk_i) + ,.reset_i(reset_r) + ,.cfg_bus_i(cfg_bus_lo) + + ,.mem_fwd_header_o({proc_fwd_header_lo[dcache_proc_id_lp], proc_fwd_header_lo[icache_proc_id_lp]}) + ,.mem_fwd_data_o({proc_fwd_data_lo[dcache_proc_id_lp], proc_fwd_data_lo[icache_proc_id_lp]}) + ,.mem_fwd_v_o({proc_fwd_v_lo[dcache_proc_id_lp], proc_fwd_v_lo[icache_proc_id_lp]}) + ,.mem_fwd_ready_and_i({proc_fwd_ready_and_li[dcache_proc_id_lp], proc_fwd_ready_and_li[icache_proc_id_lp]}) + + ,.mem_rev_header_i({proc_rev_header_li[dcache_proc_id_lp], proc_rev_header_li[icache_proc_id_lp]}) + ,.mem_rev_data_i({proc_rev_data_li[dcache_proc_id_lp], proc_rev_data_li[icache_proc_id_lp]}) + ,.mem_rev_v_i({proc_rev_v_li[dcache_proc_id_lp], proc_rev_v_li[icache_proc_id_lp]}) + ,.mem_rev_ready_and_o({proc_rev_ready_and_lo[dcache_proc_id_lp], proc_rev_ready_and_lo[icache_proc_id_lp]}) + + ,.debug_irq_i(debug_irq_li) + ,.timer_irq_i(timer_irq_li) + ,.software_irq_i(software_irq_li) + ,.m_external_irq_i(m_external_irq_li) + ,.s_external_irq_i(s_external_irq_li) + ); + + // Assign incoming I/O as basically another UCE interface + assign proc_fwd_header_lo[io_proc_id_lp] = mem_fwd_header_i; + assign proc_fwd_data_lo[io_proc_id_lp] = mem_fwd_data_i; + assign proc_fwd_v_lo[io_proc_id_lp] = mem_fwd_v_i; + assign mem_fwd_ready_and_o = proc_fwd_ready_and_li[io_proc_id_lp]; + + assign mem_rev_header_o = proc_rev_header_li[io_proc_id_lp]; + assign mem_rev_data_o = proc_rev_data_li[io_proc_id_lp]; + assign mem_rev_v_o = proc_rev_v_li[io_proc_id_lp]; + assign proc_rev_ready_and_lo[io_proc_id_lp] = mem_rev_ready_and_i; + + // Select destination of commands + logic [num_proc_lp-1:0][lg_num_dev_lp-1:0] proc_fwd_dst_lo; + for (genvar i = 0; i < num_proc_lp; i++) + begin : fwd_dest + bp_local_addr_s local_addr; + assign local_addr = proc_fwd_header_lo[i].addr; + wire [dev_id_width_gp-1:0] device_fwd_li = local_addr.dev; + wire is_local = (proc_fwd_header_lo[i].addr < dram_base_addr_gp); + wire is_my_core = is_local & (local_addr.tile == cfg_bus_lo.core_id); + wire is_other_core = is_local & (local_addr.tile != cfg_bus_lo.core_id); + wire is_other_hio = (local_addr[paddr_width_p-1-:hio_width_p] != 0); + + wire is_cfg_fwd = is_my_core & is_local & (device_fwd_li == cfg_dev_gp); + wire is_clint_fwd = is_my_core & is_local & (device_fwd_li == clint_dev_gp); + wire is_host_fwd = is_my_core & is_local & (device_fwd_li == host_dev_gp); + + wire is_io_fwd = is_host_fwd | is_other_hio | is_other_core; + wire is_l2s_fwd = ~is_local & ~is_io_fwd; + wire is_loopback_fwd = ~is_cfg_fwd & ~is_clint_fwd & ~is_io_fwd & ~is_l2s_fwd; + + localparam lg_l2_slices_lp = `BSG_SAFE_CLOG2(l2_slices_p); + logic [lg_l2_slices_lp-1:0] slice; + bp_me_dram_hash_encode + #(.bp_params_p(bp_params_p)) + slice_select + (.paddr_i(local_addr) + ,.data_i() + + ,.dram_o() + ,.daddr_o() + ,.slice_o(slice) + ,.bank_o() + ,.data_o() + ); + + logic [l2_slices_p-1:0] is_l2s_slice_fwd; + bsg_decode_with_v + #(.num_out_p(l2_slices_p)) + slice_decode + (.i(slice) + ,.v_i(is_l2s_fwd) + ,.o(is_l2s_slice_fwd) + ); + + wire [num_dev_lp-1:0] proc_fwd_dst_sel = + (is_cfg_fwd << cfg_dev_id_lp) + | (is_clint_fwd << clint_dev_id_lp) + | (is_l2s_slice_fwd << l2s_dev_base_id_lp) + | (is_loopback_fwd << loopback_dev_id_lp) + | (is_io_fwd << io_dev_id_lp); + + bsg_encode_one_hot + #(.width_p(num_dev_lp), .lo_to_hi_p(1)) + fwd_pe + (.i(proc_fwd_dst_sel) + ,.addr_o(proc_fwd_dst_lo[i]) + ,.v_o() + ); + end + + logic [num_dev_lp-1:0][lg_num_proc_lp-1:0] dev_rev_dst_lo; + for (genvar i = 0; i < num_dev_lp; i++) + begin : dev_lce_id + wire [did_width_p-1:0] dev_rev_did_li = dev_rev_header_lo[i].payload.src_did; + wire [lg_num_proc_lp-1:0] dev_rev_proc_id_li = dev_rev_header_lo[i].payload.lce_id; + wire remote_did_li = (dev_rev_did_li > 0) && (dev_rev_did_li != my_did_i); + assign dev_rev_dst_lo[i] = remote_did_li ? io_proc_id_lp : dev_rev_proc_id_li; + end + + bp_me_xbar_stream + #(.bp_params_p(bp_params_p) + ,.payload_width_p(mem_fwd_payload_width_lp) + ,.stream_mask_p(mem_fwd_stream_mask_gp) + ,.num_source_p(num_proc_lp) + ,.num_sink_p(num_dev_lp) + ) + fwd_xbar + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.msg_header_i(proc_fwd_header_lo) + ,.msg_data_i(proc_fwd_data_lo) + ,.msg_v_i(proc_fwd_v_lo) + ,.msg_ready_and_o(proc_fwd_ready_and_li) + ,.msg_dst_i(proc_fwd_dst_lo) + + ,.msg_header_o(dev_fwd_header_li) + ,.msg_data_o(dev_fwd_data_li) + ,.msg_v_o(dev_fwd_v_li) + ,.msg_ready_and_i(dev_fwd_ready_and_lo) + ); + + bp_me_xbar_stream + #(.bp_params_p(bp_params_p) + ,.payload_width_p(mem_rev_payload_width_lp) + ,.stream_mask_p(mem_rev_stream_mask_gp) + ,.num_source_p(num_dev_lp) + ,.num_sink_p(num_proc_lp) + ) + rev_xbar + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.msg_header_i(dev_rev_header_lo) + ,.msg_data_i(dev_rev_data_lo) + ,.msg_v_i(dev_rev_v_lo) + ,.msg_ready_and_o(dev_rev_ready_and_li) + ,.msg_dst_i(dev_rev_dst_lo) + + ,.msg_header_o(proc_rev_header_li) + ,.msg_data_o(proc_rev_data_li) + ,.msg_v_o(proc_rev_v_li) + ,.msg_ready_and_i(proc_rev_ready_and_lo) + ); + + bp_me_cfg_slice + #(.bp_params_p(bp_params_p)) + cfgs + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.mem_fwd_header_i(dev_fwd_header_li[cfg_dev_id_lp]) + ,.mem_fwd_data_i(dev_fwd_data_li[cfg_dev_id_lp]) + ,.mem_fwd_v_i(dev_fwd_v_li[cfg_dev_id_lp]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[cfg_dev_id_lp]) + + ,.mem_rev_header_o(dev_rev_header_lo[cfg_dev_id_lp]) + ,.mem_rev_data_o(dev_rev_data_lo[cfg_dev_id_lp]) + ,.mem_rev_v_o(dev_rev_v_lo[cfg_dev_id_lp]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[cfg_dev_id_lp]) + + ,.cfg_bus_o(cfg_bus_lo) + ,.did_i(my_did_i) + ,.host_did_i(host_did_i) + ,.cord_i(my_cord_i) + + ,.cce_ucode_v_o() + ,.cce_ucode_w_o() + ,.cce_ucode_addr_o() + ,.cce_ucode_data_o() + ,.cce_ucode_data_i('0) + ); + + bp_me_clint_slice + #(.bp_params_p(bp_params_p)) + clint + (.clk_i(clk_i) + ,.rt_clk_i(rt_clk_i) + ,.reset_i(reset_r) + ,.cfg_bus_i(cfg_bus_lo) + + ,.mem_fwd_header_i(dev_fwd_header_li[clint_dev_id_lp]) + ,.mem_fwd_data_i(dev_fwd_data_li[clint_dev_id_lp]) + ,.mem_fwd_v_i(dev_fwd_v_li[clint_dev_id_lp]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[clint_dev_id_lp]) + + ,.mem_rev_header_o(dev_rev_header_lo[clint_dev_id_lp]) + ,.mem_rev_data_o(dev_rev_data_lo[clint_dev_id_lp]) + ,.mem_rev_v_o(dev_rev_v_lo[clint_dev_id_lp]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[clint_dev_id_lp]) + + ,.debug_irq_o(debug_irq_li) + ,.timer_irq_o(timer_irq_li) + ,.software_irq_o(software_irq_li) + ,.m_external_irq_o(m_external_irq_li) + ,.s_external_irq_o(s_external_irq_li) + ); + + for (genvar i = 0; i < l2_slices_p; i++) + begin : slices + bp_me_cache_slice + #(.bp_params_p(bp_params_p)) + l2s + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.mem_fwd_header_i(dev_fwd_header_li[l2s_dev_base_id_lp+i]) + ,.mem_fwd_data_i(dev_fwd_data_li[l2s_dev_base_id_lp+i]) + ,.mem_fwd_v_i(dev_fwd_v_li[l2s_dev_base_id_lp+i]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[l2s_dev_base_id_lp+i]) + + ,.mem_rev_header_o(dev_rev_header_lo[l2s_dev_base_id_lp+i]) + ,.mem_rev_data_o(dev_rev_data_lo[l2s_dev_base_id_lp+i]) + ,.mem_rev_v_o(dev_rev_v_lo[l2s_dev_base_id_lp+i]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[l2s_dev_base_id_lp+i]) + + ,.dma_pkt_o(dma_pkt_o[i]) + ,.dma_pkt_v_o(dma_pkt_v_o[i]) + ,.dma_pkt_ready_and_i(dma_pkt_ready_and_i[i]) + + ,.dma_data_i(dma_data_i[i]) + ,.dma_data_v_i(dma_data_v_i[i]) + ,.dma_data_ready_and_o(dma_data_ready_and_o[i]) + + ,.dma_data_o(dma_data_o[i]) + ,.dma_data_v_o(dma_data_v_o[i]) + ,.dma_data_ready_and_i(dma_data_ready_and_i[i]) + ); + end + + // Assign I/O as another device + assign mem_fwd_header_o = dev_fwd_header_li[io_dev_id_lp]; + assign mem_fwd_data_o = dev_fwd_data_li[io_dev_id_lp]; + assign mem_fwd_v_o = dev_fwd_v_li[io_dev_id_lp]; + assign dev_fwd_ready_and_lo[io_dev_id_lp] = mem_fwd_ready_and_i; + + assign dev_rev_header_lo[io_dev_id_lp] = mem_rev_header_i; + assign dev_rev_data_lo[io_dev_id_lp] = mem_rev_data_i; + assign dev_rev_v_lo[io_dev_id_lp] = mem_rev_v_i; + assign mem_rev_ready_and_o = dev_rev_ready_and_li[io_dev_id_lp]; + + bp_me_loopback + #(.bp_params_p(bp_params_p)) + loopback + (.clk_i(clk_i) + ,.reset_i(reset_r) + + ,.mem_fwd_header_i(dev_fwd_header_li[loopback_dev_id_lp]) + ,.mem_fwd_data_i(dev_fwd_data_li[loopback_dev_id_lp]) + ,.mem_fwd_v_i(dev_fwd_v_li[loopback_dev_id_lp]) + ,.mem_fwd_ready_and_o(dev_fwd_ready_and_lo[loopback_dev_id_lp]) + ,.mem_rev_header_o(dev_rev_header_lo[loopback_dev_id_lp]) + ,.mem_rev_data_o(dev_rev_data_lo[loopback_dev_id_lp]) + ,.mem_rev_v_o(dev_rev_v_lo[loopback_dev_id_lp]) + ,.mem_rev_ready_and_i(dev_rev_ready_and_li[loopback_dev_id_lp]) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bp_unicore_lite.sv b/designs/black-parrot/src/bp/bp_unicore_lite.sv new file mode 100644 index 0000000..7743740 --- /dev/null +++ b/designs/black-parrot/src/bp/bp_unicore_lite.sv @@ -0,0 +1,301 @@ + +`include "bp_common_defines.svh" +`include "bp_top_defines.svh" +`include "bp_fe_defines.svh" +`include "bp_be_defines.svh" + +module bp_unicore_lite + import bsg_wormhole_router_pkg::*; + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_fe_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p) + ) + (input clk_i + , input reset_i + + , input [cfg_bus_width_lp-1:0] cfg_bus_i + + // Outgoing BP Stream Mem Buses from I$ and D$ + , output logic [1:0][mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [1:0][bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic [1:0] mem_fwd_v_o + , input [1:0] mem_fwd_ready_and_i + + , input [1:0][mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [1:0][bedrock_fill_width_p-1:0] mem_rev_data_i + , input [1:0] mem_rev_v_i + , output logic [1:0] mem_rev_ready_and_o + + , input debug_irq_i + , input timer_irq_i + , input software_irq_i + , input m_external_irq_i + , input s_external_irq_i + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, did_width_p); + `declare_bp_fe_icache_engine_if(paddr_width_p, icache_tag_width_p, icache_sets_p, icache_assoc_p, icache_data_width_p, icache_block_width_p, icache_fill_width_p, icache_req_id_width_p); + `declare_bp_be_dcache_engine_if(paddr_width_p, dcache_tag_width_p, dcache_sets_p, dcache_assoc_p, dcache_data_width_p, dcache_block_width_p, dcache_fill_width_p, dcache_req_id_width_p); + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + `bp_cast_i(bp_cfg_bus_s, cfg_bus); + + bp_fe_icache_req_s icache_req_lo; + logic icache_req_v_lo, icache_req_yumi_li, icache_req_lock_li, icache_req_metadata_v_lo; + bp_fe_icache_req_metadata_s icache_req_metadata_lo; + logic [icache_req_id_width_p-1:0] icache_req_id_li; + logic icache_req_critical_li, icache_req_last_li; + logic icache_req_credits_full_li, icache_req_credits_empty_li; + + bp_fe_icache_tag_mem_pkt_s icache_tag_mem_pkt_li; + logic icache_tag_mem_pkt_v_li, icache_tag_mem_pkt_yumi_lo; + bp_fe_icache_tag_info_s icache_tag_mem_lo; + bp_fe_icache_data_mem_pkt_s icache_data_mem_pkt_li; + logic icache_data_mem_pkt_v_li, icache_data_mem_pkt_yumi_lo; + logic [icache_block_width_p-1:0] icache_data_mem_lo; + bp_fe_icache_stat_mem_pkt_s icache_stat_mem_pkt_li; + logic icache_stat_mem_pkt_v_li, icache_stat_mem_pkt_yumi_lo; + bp_fe_icache_stat_info_s icache_stat_mem_lo; + + bp_be_dcache_req_s dcache_req_lo; + logic dcache_req_v_lo, dcache_req_yumi_li, dcache_req_lock_li, dcache_req_metadata_v_lo; + bp_be_dcache_req_metadata_s dcache_req_metadata_lo; + logic [dcache_req_id_width_p-1:0] dcache_req_id_li; + logic dcache_req_critical_li, dcache_req_last_li; + logic dcache_req_credits_full_li, dcache_req_credits_empty_li; + + bp_be_dcache_tag_mem_pkt_s dcache_tag_mem_pkt_li; + logic dcache_tag_mem_pkt_v_li, dcache_tag_mem_pkt_yumi_lo; + bp_be_dcache_tag_info_s dcache_tag_mem_lo; + bp_be_dcache_data_mem_pkt_s dcache_data_mem_pkt_li; + logic dcache_data_mem_pkt_v_li, dcache_data_mem_pkt_yumi_lo; + logic [dcache_block_width_p-1:0] dcache_data_mem_lo; + bp_be_dcache_stat_mem_pkt_s dcache_stat_mem_pkt_li; + logic dcache_stat_mem_pkt_v_li, dcache_stat_mem_pkt_yumi_lo; + bp_be_dcache_stat_info_s dcache_stat_mem_lo; + + wire posedge_clk = clk_i; + wire negedge_clk = ~clk_i; + + wire [did_width_p-1:0] did_li = cfg_bus_cast_i.did; + wire [1:0][lce_id_width_p-1:0] lce_id_li = {cfg_bus_cast_i.dcache_id, cfg_bus_cast_i.icache_id}; + bp_core_minimal + #(.bp_params_p(bp_params_p)) + core_minimal + (.clk_i(posedge_clk) + ,.reset_i(reset_i) + ,.cfg_bus_i(cfg_bus_cast_i) + + ,.icache_req_o(icache_req_lo) + ,.icache_req_v_o(icache_req_v_lo) + ,.icache_req_yumi_i(icache_req_yumi_li) + ,.icache_req_lock_i(icache_req_lock_li) + ,.icache_req_metadata_o(icache_req_metadata_lo) + ,.icache_req_metadata_v_o(icache_req_metadata_v_lo) + ,.icache_req_id_i(icache_req_id_li) + ,.icache_req_critical_i(icache_req_critical_li) + ,.icache_req_last_i(icache_req_last_li) + ,.icache_req_credits_full_i(icache_req_credits_full_li) + ,.icache_req_credits_empty_i(icache_req_credits_empty_li) + + ,.icache_tag_mem_pkt_i(icache_tag_mem_pkt_li) + ,.icache_tag_mem_pkt_v_i(icache_tag_mem_pkt_v_li) + ,.icache_tag_mem_pkt_yumi_o(icache_tag_mem_pkt_yumi_lo) + ,.icache_tag_mem_o(icache_tag_mem_lo) + + ,.icache_data_mem_pkt_i(icache_data_mem_pkt_li) + ,.icache_data_mem_pkt_v_i(icache_data_mem_pkt_v_li) + ,.icache_data_mem_pkt_yumi_o(icache_data_mem_pkt_yumi_lo) + ,.icache_data_mem_o(icache_data_mem_lo) + + ,.icache_stat_mem_pkt_v_i(icache_stat_mem_pkt_v_li) + ,.icache_stat_mem_pkt_i(icache_stat_mem_pkt_li) + ,.icache_stat_mem_pkt_yumi_o(icache_stat_mem_pkt_yumi_lo) + ,.icache_stat_mem_o(icache_stat_mem_lo) + + ,.dcache_req_o(dcache_req_lo) + ,.dcache_req_v_o(dcache_req_v_lo) + ,.dcache_req_yumi_i(dcache_req_yumi_li) + ,.dcache_req_lock_i(dcache_req_lock_li) + ,.dcache_req_metadata_o(dcache_req_metadata_lo) + ,.dcache_req_metadata_v_o(dcache_req_metadata_v_lo) + ,.dcache_req_id_i(dcache_req_id_li) + ,.dcache_req_critical_i(dcache_req_critical_li) + ,.dcache_req_last_i(dcache_req_last_li) + ,.dcache_req_credits_full_i(dcache_req_credits_full_li) + ,.dcache_req_credits_empty_i(dcache_req_credits_empty_li) + + ,.dcache_tag_mem_pkt_i(dcache_tag_mem_pkt_li) + ,.dcache_tag_mem_pkt_v_i(dcache_tag_mem_pkt_v_li) + ,.dcache_tag_mem_pkt_yumi_o(dcache_tag_mem_pkt_yumi_lo) + ,.dcache_tag_mem_o(dcache_tag_mem_lo) + + ,.dcache_data_mem_pkt_i(dcache_data_mem_pkt_li) + ,.dcache_data_mem_pkt_v_i(dcache_data_mem_pkt_v_li) + ,.dcache_data_mem_pkt_yumi_o(dcache_data_mem_pkt_yumi_lo) + ,.dcache_data_mem_o(dcache_data_mem_lo) + + ,.dcache_stat_mem_pkt_v_i(dcache_stat_mem_pkt_v_li) + ,.dcache_stat_mem_pkt_i(dcache_stat_mem_pkt_li) + ,.dcache_stat_mem_pkt_yumi_o(dcache_stat_mem_pkt_yumi_lo) + ,.dcache_stat_mem_o(dcache_stat_mem_lo) + + ,.debug_irq_i(debug_irq_i) + ,.timer_irq_i(timer_irq_i) + ,.software_irq_i(software_irq_i) + ,.m_external_irq_i(m_external_irq_i) + ,.s_external_irq_i(s_external_irq_i) + ); + + bp_uce + #(.bp_params_p(bp_params_p) + ,.assoc_p(icache_assoc_p) + ,.sets_p(icache_sets_p) + ,.block_width_p(icache_block_width_p) + ,.fill_width_p(icache_fill_width_p) + ,.data_width_p(icache_data_width_p) + ,.tag_width_p(icache_tag_width_p) + ,.id_width_p(icache_req_id_width_p) + ,.writeback_p(icache_features_p[e_cfg_writeback]) + ) + icache_uce + (.clk_i(posedge_clk) + ,.reset_i(reset_i) + + ,.did_i(did_li) + ,.lce_id_i(lce_id_li[0]) + + ,.cache_req_i(icache_req_lo) + ,.cache_req_v_i(icache_req_v_lo) + ,.cache_req_yumi_o(icache_req_yumi_li) + ,.cache_req_lock_o(icache_req_lock_li) + ,.cache_req_metadata_i(icache_req_metadata_lo) + ,.cache_req_metadata_v_i(icache_req_metadata_v_lo) + ,.cache_req_id_o(icache_req_id_li) + ,.cache_req_critical_o(icache_req_critical_li) + ,.cache_req_last_o(icache_req_last_li) + ,.cache_req_credits_full_o(icache_req_credits_full_li) + ,.cache_req_credits_empty_o(icache_req_credits_empty_li) + + ,.tag_mem_pkt_o(icache_tag_mem_pkt_li) + ,.tag_mem_pkt_v_o(icache_tag_mem_pkt_v_li) + ,.tag_mem_pkt_yumi_i(icache_tag_mem_pkt_yumi_lo) + ,.tag_mem_i(icache_tag_mem_lo) + + ,.data_mem_pkt_o(icache_data_mem_pkt_li) + ,.data_mem_pkt_v_o(icache_data_mem_pkt_v_li) + ,.data_mem_pkt_yumi_i(icache_data_mem_pkt_yumi_lo) + ,.data_mem_i(icache_data_mem_lo) + + ,.stat_mem_pkt_o(icache_stat_mem_pkt_li) + ,.stat_mem_pkt_v_o(icache_stat_mem_pkt_v_li) + ,.stat_mem_pkt_yumi_i(icache_stat_mem_pkt_yumi_lo) + ,.stat_mem_i(icache_stat_mem_lo) + + ,.mem_fwd_header_o(mem_fwd_header_o[0]) + ,.mem_fwd_data_o(mem_fwd_data_o[0]) + ,.mem_fwd_v_o(mem_fwd_v_o[0]) + ,.mem_fwd_ready_and_i(mem_fwd_ready_and_i[0]) + + ,.mem_rev_header_i(mem_rev_header_i[0]) + ,.mem_rev_data_i(mem_rev_data_i[0]) + ,.mem_rev_v_i(mem_rev_v_i[0]) + ,.mem_rev_ready_and_o(mem_rev_ready_and_o[0]) + ); + + bp_bedrock_mem_fwd_header_s [1:1] _mem_fwd_header_o; + logic [1:1][bedrock_fill_width_p-1:0] _mem_fwd_data_o; + logic [1:1] _mem_fwd_v_o, _mem_fwd_ready_and_i; + bp_bedrock_mem_rev_header_s [1:1] _mem_rev_header_i; + logic [1:1][bedrock_fill_width_p-1:0] _mem_rev_data_i; + logic [1:1] _mem_rev_v_i, _mem_rev_ready_and_o; + bp_uce + #(.bp_params_p(bp_params_p) + ,.assoc_p(dcache_assoc_p) + ,.sets_p(dcache_sets_p) + ,.block_width_p(dcache_block_width_p) + ,.fill_width_p(dcache_fill_width_p) + ,.data_width_p(dcache_data_width_p) + ,.tag_width_p(dcache_tag_width_p) + ,.id_width_p(dcache_req_id_width_p) + ,.writeback_p(dcache_features_p[e_cfg_writeback]) + ) + dcache_uce + (.clk_i(negedge_clk) + ,.reset_i(reset_i) + + ,.did_i(did_li) + ,.lce_id_i(lce_id_li[1]) + + ,.cache_req_i(dcache_req_lo) + ,.cache_req_v_i(dcache_req_v_lo) + ,.cache_req_yumi_o(dcache_req_yumi_li) + ,.cache_req_lock_o(dcache_req_lock_li) + ,.cache_req_metadata_i(dcache_req_metadata_lo) + ,.cache_req_metadata_v_i(dcache_req_metadata_v_lo) + ,.cache_req_id_o(dcache_req_id_li) + ,.cache_req_critical_o(dcache_req_critical_li) + ,.cache_req_last_o(dcache_req_last_li) + ,.cache_req_credits_full_o(dcache_req_credits_full_li) + ,.cache_req_credits_empty_o(dcache_req_credits_empty_li) + + ,.tag_mem_pkt_o(dcache_tag_mem_pkt_li) + ,.tag_mem_pkt_v_o(dcache_tag_mem_pkt_v_li) + ,.tag_mem_pkt_yumi_i(dcache_tag_mem_pkt_yumi_lo) + ,.tag_mem_i(dcache_tag_mem_lo) + + ,.data_mem_pkt_o(dcache_data_mem_pkt_li) + ,.data_mem_pkt_v_o(dcache_data_mem_pkt_v_li) + ,.data_mem_pkt_yumi_i(dcache_data_mem_pkt_yumi_lo) + ,.data_mem_i(dcache_data_mem_lo) + + ,.stat_mem_pkt_o(dcache_stat_mem_pkt_li) + ,.stat_mem_pkt_v_o(dcache_stat_mem_pkt_v_li) + ,.stat_mem_pkt_yumi_i(dcache_stat_mem_pkt_yumi_lo) + ,.stat_mem_i(dcache_stat_mem_lo) + + ,.mem_fwd_header_o(_mem_fwd_header_o[1]) + ,.mem_fwd_data_o(_mem_fwd_data_o[1]) + ,.mem_fwd_v_o(_mem_fwd_v_o[1]) + ,.mem_fwd_ready_and_i(_mem_fwd_ready_and_i[1]) + + ,.mem_rev_header_i(_mem_rev_header_i[1]) + ,.mem_rev_data_i(_mem_rev_data_i[1]) + ,.mem_rev_v_i(_mem_rev_v_i[1]) + ,.mem_rev_ready_and_o(_mem_rev_ready_and_o[1]) + ); + + // Synchronize back to posedge clk + bsg_dlatch + #(.width_p($bits(bp_bedrock_mem_fwd_header_s)+bedrock_fill_width_p+2), .i_know_this_is_a_bad_idea_p(1)) + posedge_latch + (.clk_i(posedge_clk) + ,.data_i({_mem_fwd_header_o[1], _mem_fwd_data_o[1], _mem_fwd_v_o[1] + ,mem_fwd_ready_and_i[1] + }) + ,.data_o({mem_fwd_header_o[1], mem_fwd_data_o[1], mem_fwd_v_o[1] + ,_mem_fwd_ready_and_i[1] + }) + ); + + // Synchronize back to negedge clk + bsg_dlatch + #(.width_p($bits(bp_bedrock_mem_fwd_header_s)+bedrock_fill_width_p+2), .i_know_this_is_a_bad_idea_p(1)) + negedge_latch + (.clk_i(negedge_clk) + ,.data_i({mem_rev_header_i[1], mem_rev_data_i[1], mem_rev_v_i[1] + ,_mem_rev_ready_and_o[1] + }) + ,.data_o({_mem_rev_header_i[1], _mem_rev_data_i[1], _mem_rev_v_i[1] + ,mem_rev_ready_and_o[1] + }) + ); + +endmodule + diff --git a/designs/black-parrot/src/bp/bsg_async_noc_link.sv b/designs/black-parrot/src/bp/bsg_async_noc_link.sv new file mode 100644 index 0000000..6641e91 --- /dev/null +++ b/designs/black-parrot/src/bp/bsg_async_noc_link.sv @@ -0,0 +1,83 @@ + +`include "bsg_defines.sv" +`include "bsg_noc_links.svh" + +module bsg_async_noc_link + import bsg_noc_pkg::*; + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(lg_size_p) + + , parameter bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(width_p) + ) + (input aclk_i + , input areset_i + + , input bclk_i + , input breset_i + + , input [bsg_ready_and_link_sif_width_lp-1:0] alink_i + , output [bsg_ready_and_link_sif_width_lp-1:0] alink_o + + , input [bsg_ready_and_link_sif_width_lp-1:0] blink_i + , output [bsg_ready_and_link_sif_width_lp-1:0] blink_o + ); + + `declare_bsg_ready_and_link_sif_s(width_p, bsg_ready_and_link_sif_s); + + bsg_ready_and_link_sif_s alink_cast_i, alink_cast_o; + bsg_ready_and_link_sif_s blink_cast_i, blink_cast_o; + + assign alink_cast_i = alink_i; + assign blink_cast_i = blink_i; + + assign alink_o = alink_cast_o; + assign blink_o = blink_cast_o; + + logic alink_full_lo; + assign alink_cast_o.ready_and_rev = ~alink_full_lo; + wire alink_enq_li = alink_cast_i.v & alink_cast_o.ready_and_rev; + wire blink_deq_li = blink_cast_o.v & blink_cast_i.ready_and_rev; + bsg_async_fifo + #(.width_p(width_p) + ,.lg_size_p(lg_size_p) + ) + link_a_to_b + (.w_clk_i(aclk_i) + ,.w_reset_i(areset_i) + ,.w_enq_i(alink_enq_li) + ,.w_data_i(alink_cast_i.data) + ,.w_full_o(alink_full_lo) + + ,.r_clk_i(bclk_i) + ,.r_reset_i(breset_i) + ,.r_deq_i(blink_deq_li) + ,.r_data_o(blink_cast_o.data) + ,.r_valid_o(blink_cast_o.v) + ); + + logic blink_full_lo; + assign blink_cast_o.ready_and_rev = ~blink_full_lo; + wire blink_enq_li = blink_cast_i.v & blink_cast_o.ready_and_rev; + wire alink_deq_li = alink_cast_o.v & alink_cast_i.ready_and_rev; + bsg_async_fifo + #(.width_p(width_p) + ,.lg_size_p(lg_size_p) + ) + link_b_to_a + (.w_clk_i(bclk_i) + ,.w_reset_i(breset_i) + ,.w_enq_i(blink_enq_li) + ,.w_data_i(blink_cast_i.data) + ,.w_full_o(blink_full_lo) + + ,.r_clk_i(aclk_i) + ,.r_reset_i(areset_i) + ,.r_deq_i(alink_deq_li) + ,.r_data_o(alink_cast_o.data) + ,.r_valid_o(alink_cast_o.v) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_async_noc_link) + diff --git a/designs/black-parrot/src/bp/bsg_bus_pack.sv b/designs/black-parrot/src/bp/bsg_bus_pack.sv new file mode 100644 index 0000000..211a503 --- /dev/null +++ b/designs/black-parrot/src/bp/bsg_bus_pack.sv @@ -0,0 +1,64 @@ + +`include "bsg_defines.sv" + +module bsg_bus_pack + #(// Width of the bus + parameter `BSG_INV_PARAM(in_width_p) + , parameter out_width_p = in_width_p + + // Selection granularity of the bus, default to byte width + , parameter unit_width_p = 8 + , localparam sel_width_lp = `BSG_SAFE_CLOG2(in_width_p/unit_width_p) + , localparam size_width_lp = `BSG_WIDTH(sel_width_lp) + ) + (input [in_width_p-1:0] data_i + , input [sel_width_lp-1:0] sel_i + , input [size_width_lp-1:0] size_i + , output logic [out_width_p-1:0] data_o + ); + + localparam lg_unit_width_lp = `BSG_SAFE_CLOG2(unit_width_p); + logic [in_width_p-1:0] data_rot_lo; + bsg_rotate_right + #(.width_p(in_width_p)) + rot + (.data_i(data_i) + // Align to unit granularity + ,.rot_i({sel_i, {lg_unit_width_lp{1'b0}}}) + ,.o(data_rot_lo) + ); + + localparam num_size_lp = 2**size_width_lp; + logic [num_size_lp-1:0][in_width_p-1:0] data_repl_lo; + for (genvar i = 0; i <= sel_width_lp; i++) + begin : repl + localparam slice_width_lp = (unit_width_p*(2**i)); + assign data_repl_lo[i] = {in_width_p/slice_width_lp{data_rot_lo[0+:slice_width_lp]}}; + end + + logic [in_width_p-1:0] data_lo; + bsg_mux + #(.width_p(in_width_p), .els_p(num_size_lp)) + repl_mux + (.data_i(data_repl_lo) + ,.sel_i(size_i) + ,.data_o(data_lo) + ); + + if (out_width_p > in_width_p) + assign data_o = {out_width_p/in_width_p{data_lo}}; + else + assign data_o = data_lo[0+:out_width_p]; + + // synopsys translate_off + if (!`BSG_IS_POW2(in_width_p) || !`BSG_IS_POW2(out_width_p)) + $fatal(1, "Bus width must be a power of 2"); + + if (unit_width_p < 2) + $fatal(1, "Bit width replication unsupported"); + // synopsys translate_on + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_bus_pack) + diff --git a/designs/black-parrot/src/bp/bsg_dff_sync_read.sv b/designs/black-parrot/src/bp/bsg_dff_sync_read.sv new file mode 100644 index 0000000..8c8fe99 --- /dev/null +++ b/designs/black-parrot/src/bp/bsg_dff_sync_read.sv @@ -0,0 +1,60 @@ + +`include "bsg_defines.sv" + +// This module buffers data on a synchronous read, useful for buffering +// things like an synchronous SRAM read +module bsg_dff_sync_read + #(parameter `BSG_INV_PARAM(width_p) + // Whether data is available synchronously or asynchronously + , parameter bypass_p = 0 + ) + (input clk_i + , input reset_i + + // v_n_i is high the cycle before the data comes in + // The stored data will always be overwritten + , input v_n_i + , input [width_p-1:0] data_i + + , output logic [width_p-1:0] data_o + ); + + logic v_r; + bsg_dff + #(.width_p(1)) + v_reg + (.clk_i(clk_i) + + ,.data_i(v_n_i) + ,.data_o(v_r) + ); + + if (bypass_p == 1) + begin : bypass + bsg_dff_en_bypass + #(.width_p(width_p)) + data_reg + (.clk_i(clk_i) + + ,.en_i(v_r) + ,.data_i(data_i) + ,.data_o(data_o) + ); + end + else + begin : no_bypass + bsg_dff_en + #(.width_p(width_p)) + data_reg + (.clk_i(clk_i) + + ,.en_i(v_r) + ,.data_i(data_i) + ,.data_o(data_o) + ); + end + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_dff_sync_read) + diff --git a/designs/black-parrot/src/bp/bsg_fifo_1r1w_rolly.sv b/designs/black-parrot/src/bp/bsg_fifo_1r1w_rolly.sv new file mode 100644 index 0000000..a23dce3 --- /dev/null +++ b/designs/black-parrot/src/bp/bsg_fifo_1r1w_rolly.sv @@ -0,0 +1,107 @@ + +`include "bsg_defines.sv" + +module bsg_fifo_1r1w_rolly + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter ready_THEN_valid_p = 0 + + , localparam ptr_width_lp = `BSG_SAFE_CLOG2(els_p) + ) + (input clk_i + , input reset_i + + , input clr_v_i + , input deq_v_i + , input roll_v_i + + , input [width_p-1:0] data_i + , input v_i + , output ready_o + + , output [width_p-1:0] data_o + , output v_o + , input yumi_i + ); + + // One read pointer, one write pointer, one checkpoint pointer + // ptr_width + 1 for wrap bit + logic [ptr_width_lp:0] wptr_r, rptr_r, cptr_r; + + // Used to catch up on roll and clear + logic [ptr_width_lp:0] rptr_jmp, wptr_jmp; + + // Operations + wire enq = ready_THEN_valid_p ? v_i : ready_o & v_i; + wire deq = deq_v_i; + wire read = yumi_i; + wire clr = clr_v_i; + wire roll = roll_v_i; + + assign rptr_jmp = roll + ? (cptr_r - rptr_r + (ptr_width_lp+1)'(deq)) + : read + ? ((ptr_width_lp+1)'(1)) + : ((ptr_width_lp+1)'(0)); + + assign wptr_jmp = clr + ? (rptr_r - wptr_r + (ptr_width_lp+1)'(read)) + : enq + ? ((ptr_width_lp+1)'(1)) + : ((ptr_width_lp+1)'(0)); + + wire empty = (rptr_r[0+:ptr_width_lp] == wptr_r[0+:ptr_width_lp]) + & (rptr_r[ptr_width_lp] == wptr_r[ptr_width_lp]); + wire full = (cptr_r[0+:ptr_width_lp] == wptr_r[0+:ptr_width_lp]) + & (cptr_r[ptr_width_lp] != wptr_r[ptr_width_lp]); + + assign ready_o = ~clr & ~full; + assign v_o = ~roll & ~empty; + + bsg_circular_ptr + #(.slots_p(2*els_p), .max_add_p(1)) + cptr + (.clk(clk_i) + ,.reset_i(reset_i) + ,.add_i(deq_v_i) + ,.o(cptr_r) + ,.n_o() + ); + + bsg_circular_ptr + #(.slots_p(2*els_p),.max_add_p(2*els_p-1)) + wptr + (.clk(clk_i) + ,.reset_i(reset_i) + ,.add_i(wptr_jmp) + ,.o(wptr_r) + ,.n_o() + ); + + bsg_circular_ptr + #(.slots_p(2*els_p), .max_add_p(2*els_p-1)) + rptr_circ_ptr + (.clk(clk_i) + ,.reset_i(reset_i) + ,.add_i(rptr_jmp) + ,.o(rptr_r) + ,.n_o() + ); + + bsg_mem_1r1w + #(.width_p(width_p), .els_p(els_p)) + fifo_mem + (.w_clk_i(clk_i) + ,.w_reset_i(reset_i) + ,.w_v_i(enq) + ,.w_addr_i(wptr_r[0+:ptr_width_lp]) + ,.w_data_i(data_i) + ,.r_v_i(read) + ,.r_addr_i(rptr_r[0+:ptr_width_lp]) + ,.r_data_o(data_o) + ); + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_rolly) + diff --git a/designs/black-parrot/src/bp/bsg_parallel_in_serial_out_passthrough_dynamic.sv b/designs/black-parrot/src/bp/bsg_parallel_in_serial_out_passthrough_dynamic.sv new file mode 100644 index 0000000..e820119 --- /dev/null +++ b/designs/black-parrot/src/bp/bsg_parallel_in_serial_out_passthrough_dynamic.sv @@ -0,0 +1,113 @@ +// +// This data structure takes in a multi-word data and serializes +// it to a single word output. This module is helpful on both sides. +// Note: +// A transaction starts when ready_and_o & v_i. data_i must +// stay constant for the entirety of the transaction until +// ready_and_o is asserted. +// This may make the module incompatible with upstream modules that +// multiplex multiple inputs and can change which input they multiplex +// on the fly based on arrival of new inputs. + +`include "bsg_defines.sv" + +module bsg_parallel_in_serial_out_passthrough_dynamic #( parameter `BSG_INV_PARAM(width_p ) + , parameter `BSG_INV_PARAM(els_p ) + , parameter hi_to_lo_p = 0 + , parameter lg_max_els_lp = `BSG_SAFE_CLOG2(els_p) + ) + ( input clk_i + , input reset_i + + // Data Input Channel + , input v_i + , input [els_p-1:0][width_p-1:0] data_i + , input [lg_max_els_lp-1:0] len_i // Must remain constant + , output ready_and_o + + // Data Output Channel + , output v_o + , output [width_p-1:0] data_o + , input ready_and_i + ); + + logic [els_p-1:0] count_r; + // For single word piso, we're just passing through the signals + if (els_p == 1) + begin : single_word + assign count_r = 1'b1; + assign ready_and_o = ready_and_i; + end + else + begin : multi_word + logic last_word; + bsg_counter_clear_up_one_hot + #(.max_val_p(els_p-1), .init_val_p(1)) + counter + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.clear_i(ready_and_o & v_i) + ,.up_i(v_o & ready_and_i & ~last_word) + ,.count_r_o(count_r) + ); + + assign last_word = count_r[len_i]; + + assign ready_and_o = ready_and_i & last_word; + end + + // If send hi_to_lo, reverse the input data array + logic [els_p-1:0][width_p-1:0] data_li; + + if (hi_to_lo_p == 0) + begin: lo2hi + assign data_li = data_i; + end + else + begin: hi2lo + bsg_array_reverse + #(.width_p(width_p), .els_p(els_p)) + bar + (.i(data_i) + ,.o(data_li) + ); + end + + bsg_mux_one_hot + #(.width_p(width_p), .els_p(els_p)) + data_mux + (.data_i(data_li) + ,.sel_one_hot_i(count_r) + ,.data_o(data_o) + ); + assign v_o = v_i; + + //synopsys translate_off + logic [els_p-1:0][width_p-1:0] initial_data_r; + bsg_dff_en + #(.width_p(width_p*els_p)) + initial_data_reg + (.clk_i(clk_i) + ,.en_i(count_r[0] & v_i) + + ,.data_i(data_i) + ,.data_o(initial_data_r) + ); + + always_ff @(negedge clk_i) + begin + if (~reset_i & (count_r[0] === 1'b0)) + begin + assert (v_i) + else $error("v_i must be held high during the entire PISO transaction"); + assert (data_i === initial_data_r) + else $error("data_i must be held constant during the entire PISO transaction"); + end + end + //synopsys translate_on + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_parallel_in_serial_out_passthrough_dynamic) + diff --git a/designs/black-parrot/src/bp/bsg_rom_param.sv b/designs/black-parrot/src/bp/bsg_rom_param.sv new file mode 100644 index 0000000..489ae41 --- /dev/null +++ b/designs/black-parrot/src/bp/bsg_rom_param.sv @@ -0,0 +1,21 @@ + +`include "bsg_defines.sv" + +module bsg_rom_param + #(parameter `BSG_INV_PARAM(data_width_p) + , parameter `BSG_INV_PARAM(data_p) + , parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + + , localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p) + ) + (input [lg_els_lp-1:0] addr_i + , output logic [width_p-1:0] data_o + ); + + assign data_o = data_p[addr_i*width_p+:width_p]; + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_rom_param) + diff --git a/designs/black-parrot/src/bp/bsg_serial_in_parallel_out_passthrough_dynamic.sv b/designs/black-parrot/src/bp/bsg_serial_in_parallel_out_passthrough_dynamic.sv new file mode 100644 index 0000000..4ab5f73 --- /dev/null +++ b/designs/black-parrot/src/bp/bsg_serial_in_parallel_out_passthrough_dynamic.sv @@ -0,0 +1,95 @@ + + +/** + * bsg_serial_in_parallel_out_passthrough_dynamic.v + */ + +`include "bsg_defines.sv" + +module bsg_serial_in_parallel_out_passthrough_dynamic + #(parameter `BSG_INV_PARAM(width_p) + , parameter `BSG_INV_PARAM(els_p) + , parameter lg_max_els_lp = `BSG_SAFE_CLOG2(els_p) + , hi_to_lo_p = 0 + ) + (input clk_i + , input reset_i + + , input v_i + , input [lg_max_els_lp-1:0] len_i + , output logic ready_and_o + , input [width_p-1:0] data_i + + , output logic [els_p-1:0][width_p-1:0] data_o + , output logic v_o + , input ready_and_i + ); + + localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p); + + logic [els_p-1:0] count_r; + logic last_word; + + assign v_o = v_i & last_word; + assign ready_and_o = ready_and_i; + + wire sending = v_o & ready_and_i; // we have all the items, and downstream is ready + wire receiving = v_i & ready_and_o; // data is coming in, and we have space + + // counts one hot, from 0 to width_p + // contains one hot pointer to word to write to + // simultaneous restart and increment are allowed + + if (els_p == 1) + begin : single_word + assign count_r = 1'b1; + assign last_word = 1'b1; + end + else + begin : multi_word + bsg_counter_clear_up_one_hot + #(.max_val_p(els_p-1)) + bcoh + (.clk_i(clk_i) + ,.reset_i(reset_i) + ,.clear_i(sending) + ,.up_i(receiving & ~last_word) + ,.count_r_o(count_r) + ); + assign last_word = count_r[len_i]; + end + + logic [els_p-1:0][width_p-1:0] data_lo; + + for (genvar i = 0; i < els_p-1; i++) + begin: rof + wire my_turn = v_i & count_r[i]; + bsg_dff_en_bypass #(.width_p(width_p)) dff + (.clk_i + ,.data_i + ,.en_i (my_turn) + ,.data_o (data_lo [i]) + ); + end + assign data_lo[els_p-1] = data_i; + + // If send hi_to_lo, reverse the output data array + if (hi_to_lo_p == 0) + begin: lo2hi + assign data_o = data_lo; + end + else + begin: hi2lo + bsg_array_reverse + #(.width_p(width_p), .els_p(els_p)) + bar + (.i(data_lo) + ,.o(data_o) + ); + end + + +endmodule + +`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out_passthrough_dynamic) + diff --git a/designs/black-parrot/src/bp/null_cosim.cpp b/designs/black-parrot/src/bp/null_cosim.cpp new file mode 100644 index 0000000..7f337e1 --- /dev/null +++ b/designs/black-parrot/src/bp/null_cosim.cpp @@ -0,0 +1,35 @@ + +#include "svdpi.h" +#include +#include "stdlib.h" +#include +#include + +extern "C" void* cosim_init(int hartid, int ncpus, int memory_size, bool checkpoint) { + return NULL; +} + +extern "C" int cosim_step(void *handle, + int hartid, + uint64_t pc, + uint32_t insn, + uint64_t wdata, + uint64_t status, + uint64_t cause) { + return 0; +} + +extern "C" int cosim_trap(void *handle, + int hartid, + uint64_t pc, + uint32_t insn, + uint64_t wdata, + uint64_t status, + uint64_t cause) { + return 0; +} + +extern "C" void cosim_finish(void *handle) { + +} + diff --git a/designs/black-parrot/src/bp/testbench.sv b/designs/black-parrot/src/bp/testbench.sv new file mode 100644 index 0000000..c0e3c90 --- /dev/null +++ b/designs/black-parrot/src/bp/testbench.sv @@ -0,0 +1,729 @@ +/** + * + * testbench.v + * + */ + +`include "bsg_noc_links.svh" + +`ifndef BP_SIM_CLK_PERIOD +`define BP_SIM_CLK_PERIOD 10 +`endif + +`ifndef BP_RT_CLK_PERIOD +`define BP_RT_CLK_PERIOD 100 +`endif + +module testbench + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg // Replaced by the flow with a specific bp_cfg + `declare_bp_proc_params(bp_params_p) + `declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p) + + // TRACE enable parameters + , parameter icache_trace_p = 0 + , parameter dcache_trace_p = 0 + , parameter lce_trace_p = 0 + , parameter cce_trace_p = 0 + , parameter dram_trace_p = 0 + , parameter vm_trace_p = 0 + , parameter cmt_trace_p = 0 + , parameter core_profile_p = 0 + , parameter pc_gen_trace_p = 0 + , parameter pc_profile_p = 0 + , parameter br_profile_p = 0 + , parameter dev_trace_p = 0 + + // COSIM parameters + , parameter cosim_p = 0 + , parameter checkpoint_p = 0 + , parameter warmup_instr_p = 0 + , parameter max_instr_p = 0 + + // DRAM parameters + , parameter dram_type_p = "dramsim3" // Replaced by the flow with a specific dram_type + , parameter preload_mem_p = 0 + ); + + export "DPI-C" function get_dram_period; + export "DPI-C" function get_sim_period; + + function int get_dram_period(); + return (`dram_pkg::tck_ps); + endfunction + + function int get_sim_period(); + return (`BP_SIM_CLK_PERIOD); + endfunction + + `declare_bp_bedrock_if(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p); + +// Bit to deal with initial X->0 transition detection + bit clk_i, reset_i; + bit rt_clk_i, cosim_clk_i, cosim_reset_i, dram_clk_i, dram_reset_i; + + bsg_nonsynth_clock_gen + #(.cycle_time_p(`BP_SIM_CLK_PERIOD)) + clock_gen + (.o(clk_i)); + + bsg_nonsynth_reset_gen + #(.num_clocks_p(1) + ,.reset_cycles_lo_p(0) + ,.reset_cycles_hi_p(20) + ) + reset_gen + (.clk_i(clk_i) + ,.async_reset_o(reset_i) + ); + + bsg_nonsynth_clock_gen + #(.cycle_time_p(`dram_pkg::tck_ps)) + dram_clock_gen + (.o(dram_clk_i)); + + bsg_nonsynth_reset_gen + #(.num_clocks_p(1) + ,.reset_cycles_lo_p(0) + ,.reset_cycles_hi_p(10) + ) + dram_reset_gen + (.clk_i(dram_clk_i) + ,.async_reset_o(dram_reset_i) + ); + + bsg_nonsynth_clock_gen + #(.cycle_time_p(`BP_SIM_CLK_PERIOD/5)) + cosim_clk_gen + (.o(cosim_clk_i)); + + bsg_nonsynth_reset_gen + #(.num_clocks_p(1) + ,.reset_cycles_lo_p(0) + ,.reset_cycles_hi_p(10) + ) + cosim_reset_gen + (.clk_i(cosim_clk_i) + ,.async_reset_o(cosim_reset_i) + ); + + bsg_nonsynth_clock_gen + #(.cycle_time_p(`BP_RT_CLK_PERIOD)) + rt_clk_gen + (.o(rt_clk_i)); + + logic freeze; + if (cce_type_p != e_cce_uce) + assign freeze = wrapper.processor.m.multicore.cc.y[0].x[0].tile_node.tile.cfg_bus_lo.freeze; + else + assign freeze = wrapper.processor.u.unicore.cfg_bus_lo.freeze; + + bp_bedrock_mem_fwd_header_s proc_fwd_header_lo; + logic [bedrock_fill_width_p-1:0] proc_fwd_data_lo; + logic proc_fwd_v_lo, proc_fwd_ready_and_li; + bp_bedrock_mem_rev_header_s proc_rev_header_li; + logic [bedrock_fill_width_p-1:0] proc_rev_data_li; + logic proc_rev_v_li, proc_rev_ready_and_lo; + + bp_bedrock_mem_fwd_header_s proc_fwd_header_li; + logic [bedrock_fill_width_p-1:0] proc_fwd_data_li; + logic proc_fwd_v_li, proc_fwd_ready_and_lo; + bp_bedrock_mem_rev_header_s proc_rev_header_lo; + logic [bedrock_fill_width_p-1:0] proc_rev_data_lo; + logic proc_rev_v_lo, proc_rev_ready_and_li; + + `declare_bsg_cache_dma_pkt_s(daddr_width_p, l2_block_size_in_words_p); + bsg_cache_dma_pkt_s [num_cce_p-1:0][l2_dmas_p-1:0] dma_pkt_lo; + logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_pkt_v_lo, dma_pkt_yumi_li; + logic [num_cce_p-1:0][l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_lo; + logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_v_lo, dma_data_yumi_li; + logic [num_cce_p-1:0][l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_li; + logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_v_li, dma_data_ready_and_lo; + + wire [mem_noc_did_width_p-1:0] proc_did_li = 1; + wire [mem_noc_did_width_p-1:0] host_did_li = '1; + wrapper + #(.bp_params_p(bp_params_p)) + wrapper + (.clk_i(clk_i) + ,.rt_clk_i(rt_clk_i) + ,.reset_i(reset_i) + + ,.my_did_i(proc_did_li) + ,.host_did_i(host_did_li) + + ,.mem_fwd_header_o(proc_fwd_header_lo) + ,.mem_fwd_data_o(proc_fwd_data_lo) + ,.mem_fwd_v_o(proc_fwd_v_lo) + ,.mem_fwd_ready_and_i(proc_fwd_ready_and_li) + + ,.mem_rev_header_i(proc_rev_header_li) + ,.mem_rev_data_i(proc_rev_data_li) + ,.mem_rev_v_i(proc_rev_v_li) + ,.mem_rev_ready_and_o(proc_rev_ready_and_lo) + + ,.mem_fwd_header_i(proc_fwd_header_li) + ,.mem_fwd_data_i(proc_fwd_data_li) + ,.mem_fwd_v_i(proc_fwd_v_li) + ,.mem_fwd_ready_and_o(proc_fwd_ready_and_lo) + + ,.mem_rev_header_o(proc_rev_header_lo) + ,.mem_rev_data_o(proc_rev_data_lo) + ,.mem_rev_v_o(proc_rev_v_lo) + ,.mem_rev_ready_and_i(proc_rev_ready_and_li) + + ,.dma_pkt_o(dma_pkt_lo) + ,.dma_pkt_v_o(dma_pkt_v_lo) + ,.dma_pkt_ready_and_i(dma_pkt_yumi_li) + + ,.dma_data_i(dma_data_li) + ,.dma_data_v_i(dma_data_v_li) + ,.dma_data_ready_and_o(dma_data_ready_and_lo) + + ,.dma_data_o(dma_data_lo) + ,.dma_data_v_o(dma_data_v_lo) + ,.dma_data_ready_and_i(dma_data_yumi_li) + ); + + bp_nonsynth_dram + #(.bp_params_p(bp_params_p) + ,.num_dma_p(num_cce_p*l2_dmas_p) + ,.preload_mem_p(preload_mem_p) + ,.dram_type_p(dram_type_p) + ,.mem_bytes_p(2**29) + ) + dram + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.dma_pkt_i(dma_pkt_lo) + ,.dma_pkt_v_i(dma_pkt_v_lo) + ,.dma_pkt_yumi_o(dma_pkt_yumi_li) + + ,.dma_data_o(dma_data_li) + ,.dma_data_v_o(dma_data_v_li) + ,.dma_data_ready_and_i(dma_data_ready_and_lo) + + ,.dma_data_i(dma_data_lo) + ,.dma_data_v_i(dma_data_v_lo) + ,.dma_data_yumi_o(dma_data_yumi_li) + + ,.dram_clk_i(dram_clk_i) + ,.dram_reset_i(dram_reset_i) + ); + + logic nbf_done_lo; + wire [lce_id_width_p-1:0] io_lce_id_li = num_core_p*2+num_cacc_p+num_l2e_p+num_sacc_p+num_io_p; + bp_nonsynth_nbf_loader + #(.bp_params_p(bp_params_p)) + nbf_loader + (.clk_i(clk_i) + ,.reset_i(reset_i) + + ,.lce_id_i(io_lce_id_li) + ,.did_i(host_did_li) + + ,.mem_fwd_header_o(proc_fwd_header_li) + ,.mem_fwd_data_o(proc_fwd_data_li) + ,.mem_fwd_v_o(proc_fwd_v_li) + ,.mem_fwd_ready_and_i(proc_fwd_ready_and_lo) + + // NOTE: IO response ready_o is always high - acts as sink + ,.mem_rev_header_i(proc_rev_header_lo) + ,.mem_rev_data_i(proc_rev_data_lo) + ,.mem_rev_v_i(proc_rev_v_lo) + ,.mem_rev_ready_and_o(proc_rev_ready_and_li) + + ,.done_o(nbf_done_lo) + ); + + bp_nonsynth_host + #(.bp_params_p(bp_params_p) + ,.icache_trace_p(icache_trace_p) + ,.dcache_trace_p(dcache_trace_p) + ,.lce_trace_p(lce_trace_p) + ,.cce_trace_p(cce_trace_p) + ,.dram_trace_p(dram_trace_p) + ,.vm_trace_p(vm_trace_p) + ,.cmt_trace_p(cmt_trace_p) + ,.core_profile_p(core_profile_p) + ,.pc_gen_trace_p(pc_gen_trace_p) + ,.pc_profile_p(pc_profile_p) + ,.br_profile_p(br_profile_p) + ,.cosim_p(cosim_p) + ,.dev_trace_p(dev_trace_p) + ) + host + (.clk_i(clk_i && !freeze) + ,.reset_i(reset_i) + + ,.mem_fwd_header_i(proc_fwd_header_lo) + ,.mem_fwd_data_i(proc_fwd_data_lo) + ,.mem_fwd_v_i(proc_fwd_v_lo) + ,.mem_fwd_ready_and_o(proc_fwd_ready_and_li) + + ,.mem_rev_header_o(proc_rev_header_li) + ,.mem_rev_data_o(proc_rev_data_li) + ,.mem_rev_v_o(proc_rev_v_li) + ,.mem_rev_ready_and_i(proc_rev_ready_and_lo) + ); + + // Perf always enabled + localparam perf_en_p = 1; + bind bp_be_top + bp_nonsynth_perf + #(.bp_params_p(bp_params_p)) + perf + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.perf_en_p) + ,.warmup_instr_i(testbench.warmup_instr_p) + ,.max_instr_i(testbench.max_instr_p) + + ,.mhartid_i(calculator.pipe_sys.csr.cfg_bus_cast_i.core_id) + + ,.commit_v_i(calculator.commit_pkt_cast_o.instret) + ,.is_debug_mode_i(calculator.pipe_sys.csr.is_debug_mode) + ); + + // Watchdog always enabled + localparam watchdog_en_p = 1; + bind bp_be_top + bp_nonsynth_watchdog + #(.bp_params_p(bp_params_p) + ,.stall_cycles_p(100000) + ,.halt_cycles_p(10000) + ,.heartbeat_instr_p(10000) + ) + watchdog + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.watchdog_en_p) + ,.wfi_i(director.is_wait) + + ,.mhartid_i(calculator.pipe_sys.csr.cfg_bus_cast_i.core_id) + + ,.npc_i(calculator.pipe_sys.csr.apc_r) + ,.instret_i(calculator.commit_pkt_cast_o.instret) + ); + + + bind bp_be_top + bp_nonsynth_cosim + #(.bp_params_p(bp_params_p)) + cosim + (.clk_i(clk_i) + ,.reset_i(reset_i) + + // We want to pass these values as parameters, but cannot in Verilator 4.025 + // Parameter-resolved constants must not use dotted references + ,.trace_en_i(testbench.cmt_trace_p == 1) + ,.mhartid_i(calculator.pipe_sys.csr.cfg_bus_cast_i.core_id) + ,.checkpoint_i(testbench.checkpoint_p == 1) + + ,.decode_i(calculator.dispatch_pkt_cast_i.decode) + + ,.is_debug_mode_i(calculator.pipe_sys.csr.is_debug_mode) + ,.commit_pkt_i(calculator.commit_pkt_cast_o) + + ,.priv_mode_i(calculator.pipe_sys.csr.priv_mode_r) + ,.mstatus_i(calculator.pipe_sys.csr.mstatus_lo) + ,.mcause_i(calculator.pipe_sys.csr.mcause_lo) + ,.scause_i(calculator.pipe_sys.csr.scause_lo) + + ,.ird_w_v_i(scheduler.iwb_pkt_cast_i.ird_w_v) + ,.ird_addr_i(scheduler.iwb_pkt_cast_i.rd_addr) + ,.ird_data_i(scheduler.iwb_pkt_cast_i.rd_data) + + ,.frd_w_v_i(scheduler.fwb_pkt_cast_i.frd_w_v) + ,.frd_addr_i(scheduler.fwb_pkt_cast_i.rd_addr) + ,.frd_data_i(scheduler.fwb_pkt_cast_i.rd_data) + + ,.cache_req_yumi_i(calculator.pipe_mem.dcache.cache_req_yumi_i) + ,.cache_req_nonblocking_i(calculator.pipe_mem.dcache.nonblocking_req) + ,.cache_req_complete_i(calculator.pipe_mem.dcache.complete_recv) + + ,.cosim_clk_i(testbench.cosim_clk_i) + ,.cosim_reset_i(testbench.cosim_reset_i) + ); + + bind bp_fe_icache + bp_fe_nonsynth_icache_tracer + #(.bp_params_p(bp_params_p) + ,.assoc_p(assoc_p) + ,.sets_p(sets_p) + ,.block_width_p(block_width_p) + ,.fill_width_p(fill_width_p) + ,.tag_width_p(tag_width_p) + ,.id_width_p(id_width_p) + ,.data_width_p(data_width_p) + ) + icache_tracer + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.icache_trace_p) + ,.mhartid_i(cfg_bus_cast_i.core_id) + ,.* + ); + + bind bp_be_dcache + bp_be_nonsynth_dcache_tracer + #(.bp_params_p(bp_params_p) + ,.assoc_p(assoc_p) + ,.sets_p(sets_p) + ,.block_width_p(block_width_p) + ,.fill_width_p(fill_width_p) + ,.tag_width_p(tag_width_p) + ,.id_width_p(id_width_p) + ) + dcache_tracer + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.dcache_trace_p) + ,.mhartid_i(cfg_bus_cast_i.core_id) + ,.* + ); + + bind bp_core_minimal + bp_nonsynth_vm_tracer + #(.bp_params_p(bp_params_p)) + vm_tracer + (.clk_i(clk_i && testbench.vm_trace_p) + ,.reset_i(reset_i || testbench.vm_trace_p) + ,.mhartid_i(be.calculator.pipe_sys.csr.cfg_bus_cast_i.core_id) + + ,.itlb_clear_i(fe.immu.tlb.fence_i) + ,.itlb_fill_v_i(fe.immu.tlb.w_v_li) + ,.itlb_fill_g_i(fe.immu.tlb.entry_cast_i.gigapage) + ,.itlb_fill_m_i(fe.immu.tlb.entry_cast_i.megapage) + ,.itlb_vtag_i(fe.immu.tlb.vtag_i) + ,.itlb_entry_i(fe.immu.tlb.entry_i) + ,.itlb_r_v_i(fe.immu.tlb.r_v_li) + + ,.dtlb_clear_i(be.calculator.pipe_mem.dmmu.tlb.fence_i) + ,.dtlb_fill_v_i(be.calculator.pipe_mem.dmmu.tlb.w_v_li) + ,.dtlb_fill_g_i(be.calculator.pipe_mem.dmmu.tlb.entry_cast_i.gigapage) + ,.dtlb_fill_m_i(be.calculator.pipe_mem.dmmu.tlb.entry_cast_i.megapage) + ,.dtlb_vtag_i(be.calculator.pipe_mem.dmmu.tlb.vtag_i) + ,.dtlb_entry_i(be.calculator.pipe_mem.dmmu.tlb.entry_i) + ,.dtlb_r_v_i(be.calculator.pipe_mem.dmmu.tlb.r_v_li) + ); + + bind bp_core_minimal + bp_nonsynth_core_profiler + #(.bp_params_p(bp_params_p)) + core_profiler + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.core_profile_p) + + ,.mhartid_i(be.calculator.pipe_sys.csr.cfg_bus_cast_i.core_id) + + ,.fe_queue_ready_and_i(fe.fe_queue_ready_and_i) + + ,.br_ovr_i(fe.pc_gen.ovr_btaken | fe.pc_gen.ovr_jmp) + ,.ret_ovr_i(fe.pc_gen.ovr_ret) + ,.realigner_i(1'b0) + + ,.icache_data_v_i(fe.icache.hit_v_o) + ,.icache_v_i(fe.icache.v_i) + ,.icache_yumi_i(fe.icache.yumi_o) + + ,.fe_cmd_nonattaboy_i(be.director.fe_cmd_v_li) + ,.fe_queue_empty_i(be.scheduler.issue_queue.empty) + + ,.mispredict_i(be.director.npc_mismatch_v) + ,.dcache_miss_i(be.calculator.pipe_mem.dcache.busy_o) + ,.control_haz_i(be.detector.control_haz_v) + ,.data_haz_i(be.detector.data_haz_v) + ,.aux_dep_i((be.detector.dep_status_r[0].aux_iwb_v + | be.detector.dep_status_r[0].aux_fwb_v + ) & be.detector.data_haz_v + ) + ,.load_dep_i((be.detector.dep_status_r[0].emem_iwb_v + | be.detector.dep_status_r[0].fmem_iwb_v + | be.detector.dep_status_r[1].fmem_iwb_v + | be.detector.dep_status_r[0].emem_fwb_v + | be.detector.dep_status_r[0].fmem_fwb_v + | be.detector.dep_status_r[1].fmem_fwb_v + ) & be.detector.data_haz_v + ) + ,.mul_dep_i((be.detector.dep_status_r[0].mul_iwb_v + | be.detector.dep_status_r[1].mul_iwb_v + | be.detector.dep_status_r[2].mul_iwb_v + ) & be.detector.data_haz_v + ) + ,.fma_dep_i((be.detector.dep_status_r[0].fma_fwb_v + | be.detector.dep_status_r[1].fma_fwb_v + | be.detector.dep_status_r[2].fma_fwb_v + | be.detector.dep_status_r[3].fma_fwb_v + ) & be.detector.data_haz_v + ) + ,.sb_iraw_dep_i((be.detector.irs1_sb_raw_haz_v + | be.detector.irs2_sb_raw_haz_v + ) & be.detector.data_haz_v + ) + ,.sb_fraw_dep_i((be.detector.frs1_sb_raw_haz_v + | be.detector.frs2_sb_raw_haz_v + | be.detector.frs3_sb_raw_haz_v + ) & be.detector.data_haz_v + ) + ,.sb_iwaw_dep_i(be.detector.ird_sb_waw_haz_v & be.detector.data_haz_v) + ,.sb_fwaw_dep_i(be.detector.frd_sb_waw_haz_v & be.detector.data_haz_v) + ,.struct_haz_i(be.detector.struct_haz_v | be.scheduler.late_wb_yumi_o) + ,.idiv_haz_i(be.detector.idiv_busy_i & be.detector.issue_pkt_cast_i.decode.pipe_long_v) + ,.fdiv_haz_i(be.detector.fdiv_busy_i & be.detector.issue_pkt_cast_i.decode.pipe_long_v) + ,.ptw_busy_i(be.scheduler.ptw_busy_lo) + + ,.retire_pkt_i(be.calculator.pipe_sys.retire_pkt) + ,.commit_pkt_i(be.calculator.pipe_sys.commit_pkt_cast_o) + ); + + bind bp_be_top + bp_nonsynth_pc_profiler + #(.bp_params_p(bp_params_p)) + pc_profiler + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.pc_profile_p) + + ,.mhartid_i(calculator.pipe_sys.csr.cfg_bus_cast_i.core_id) + + ,.commit_pkt(calculator.commit_pkt_cast_o) + ); + + bind bp_be_top + bp_nonsynth_branch_profiler + #(.bp_params_p(bp_params_p)) + branch_profiler + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.br_profile_p) + + ,.mhartid_i(director.cfg_bus_cast_i.core_id) + + ,.fe_cmd_o(director.fe_cmd_o) + ,.fe_cmd_yumi_i(director.fe_cmd_yumi_i) + + ,.commit_v_i(calculator.commit_pkt_cast_o.instret) + ); + + bind bp_me_clint_slice + bp_me_nonsynth_dev_tracer + #(.bp_params_p(bp_params_p) + ,.trace_file_p("clint") + ) + clint_tracer + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.dev_trace_p) + ,.mhartid_i(cfg_bus_cast_i.core_id) + + ,.mem_fwd_header_i(mem_fwd_header_i) + ,.mem_fwd_data_i(mem_fwd_data_i) + ,.mem_fwd_v_i(mem_fwd_v_i) + ,.mem_fwd_ready_and_i(mem_fwd_ready_and_o) + + ,.mem_rev_header_i(mem_rev_header_o) + ,.mem_rev_data_i(mem_rev_data_o) + ,.mem_rev_v_i(mem_rev_v_o) + ,.mem_rev_ready_and_i(mem_rev_ready_and_i) + ); + + if (cce_type_p != e_cce_uce) + begin + bind bp_cce_wrapper + bp_me_nonsynth_cce_tracer + #(.bp_params_p(bp_params_p)) + cce_tracer + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.cce_trace_p) + + ,.cce_id_i(cfg_bus_cast_i.cce_id) + + // LCE-CCE Interface + // BedRock Burst protocol: ready&valid + ,.lce_req_header_i(lce_req_header_i) + ,.lce_req_data_i(lce_req_data_i) + ,.lce_req_v_i(lce_req_v_i) + ,.lce_req_ready_and_i(lce_req_ready_and_o) + + ,.lce_cmd_header_i(lce_cmd_header_o) + ,.lce_cmd_data_i(lce_cmd_data_o) + ,.lce_cmd_v_i(lce_cmd_v_o) + ,.lce_cmd_ready_and_i(lce_cmd_ready_and_i) + + ,.lce_resp_header_i(lce_resp_header_i) + ,.lce_resp_data_i(lce_resp_data_i) + ,.lce_resp_v_i(lce_resp_v_i) + ,.lce_resp_ready_and_i(lce_resp_ready_and_o) + + // CCE-MEM Interface + // BedRock Stream protocol: ready&valid + ,.mem_rev_header_i(mem_rev_header_i) + ,.mem_rev_data_i(mem_rev_data_i) + ,.mem_rev_v_i(mem_rev_v_i) + ,.mem_rev_ready_and_i(mem_rev_ready_and_o) + + ,.mem_fwd_header_i(mem_fwd_header_o) + ,.mem_fwd_data_i(mem_fwd_data_o) + ,.mem_fwd_v_i(mem_fwd_v_o) + ,.mem_fwd_ready_and_i(mem_fwd_ready_and_i) + ); + + bind bp_lce + bp_me_nonsynth_lce_tracer + #(.bp_params_p(bp_params_p) + ,.sets_p(sets_p) + ,.assoc_p(assoc_p) + ,.block_width_p(block_width_p) + ,.fill_width_p(fill_width_p) + ,.data_width_p(data_width_p) + ) + lce_tracer + (.clk_i(clk_i && ~testbench.freeze) + ,.reset_i(reset_i || !testbench.lce_trace_p) + + ,.lce_id_i(lce_id_i) + + ,.lce_req_header_i(lce_req_header_o) + ,.lce_req_data_i(lce_req_data_o) + ,.lce_req_v_i(lce_req_v_o) + ,.lce_req_ready_and_i(lce_req_ready_and_i) + + ,.lce_cmd_header_i(lce_cmd_header_i) + ,.lce_cmd_data_i(lce_cmd_data_i) + ,.lce_cmd_v_i(lce_cmd_v_i) + ,.lce_cmd_ready_and_i(lce_cmd_ready_and_o) + + ,.lce_fill_header_i(lce_fill_header_i) + ,.lce_fill_data_i(lce_fill_data_i) + ,.lce_fill_v_i(lce_fill_v_i) + ,.lce_fill_ready_and_i(lce_fill_ready_and_o) + + ,.lce_fill_o_header_i(lce_fill_header_o) + ,.lce_fill_o_data_i(lce_fill_data_o) + ,.lce_fill_o_v_i(lce_fill_v_o) + ,.lce_fill_o_ready_and_i(lce_fill_ready_and_i) + + ,.lce_resp_header_i(lce_resp_header_o) + ,.lce_resp_data_i(lce_resp_data_o) + ,.lce_resp_v_i(lce_resp_v_o) + ,.lce_resp_ready_and_i(lce_resp_ready_and_i) + + ,.cache_req_last_i(cache_req_last_o) + ); + + bind bp_cce_pending_bits + bp_me_nonsynth_cce_pending_tracer + #(.num_way_groups_p(num_way_groups_p) + ,.cce_id_width_p(cce_id_width_p) + ,.width_p(width_p) + ,.paddr_width_p(paddr_width_p) + ) + cce_pending_tracer + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.cce_trace_p) + ,.cce_id_i(cce_id_i) + ,.pending_bits_i(pending_bits_r) + ,.w_v_i(w_v_i) + ,.w_wg_i(w_wg) + ,.w_addr_i(w_addr_i) + ,.pending_i(pending_i) + ,.clear_i(clear_i) + ); + + // CCE instruction tracer + // this is connected to the instruction registered in the EX stage + if (cce_type_p == e_cce_ucode) begin + bind bp_cce + bp_me_nonsynth_cce_inst_tracer + #(.bp_params_p(bp_params_p)) + cce_inst_tracer + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.cce_trace_p) + ,.cce_id_i(cfg_bus_cast_i.cce_id) + ,.pc_i(inst_decode.ex_pc_r) + ,.instruction_v_i(inst_decode.inst_v_r) + ,.instruction_i(inst_decode.inst_r) + ,.stall_i(stall_lo) + ); + + bind bp_cce + bp_me_nonsynth_cce_perf + #(.bp_params_p(bp_params_p)) + cce_perf + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.cce_trace_p) + ,.cce_id_i(cfg_bus_cast_i.cce_id) + ,.req_start_i(req_start) + ,.req_end_i(req_end) + ,.lce_req_header_i(fsm_req_header_li) + ,.cmd_send_i(fsm_cmd_v_lo) + ,.lce_cmd_header_i(fsm_cmd_header_lo) + ,.resp_receive_i(fsm_resp_yumi_lo) + ,.lce_resp_header_i(fsm_resp_header_li) + ,.mem_rev_receive_i(fsm_rev_yumi_lo & fsm_rev_last_li) + ,.mem_rev_squash_i(fsm_rev_yumi_lo & fsm_rev_last_li & spec_bits_lo.squash) + ,.mem_rev_header_i(fsm_rev_header_li) + ,.mem_fwd_send_i(fsm_fwd_v_lo & fsm_fwd_new_lo) + ,.mem_fwd_header_i(fsm_fwd_header_lo) + ); + end else if (cce_type_p == e_cce_fsm) begin + bind bp_cce_fsm + bp_me_nonsynth_cce_perf + #(.bp_params_p(bp_params_p)) + cce_perf + (.clk_i(clk_i && !testbench.freeze) + ,.reset_i(reset_i || !testbench.cce_trace_p) + ,.cce_id_i(cfg_bus_cast_i.cce_id) + ,.req_start_i(lce_req_v_i & (state_r == e_ready)) + ,.req_end_i(state_r == e_ready) + ,.lce_req_header_i(fsm_req_header_li) + ,.cmd_send_i(fsm_cmd_v_lo) + ,.lce_cmd_header_i(fsm_cmd_header_lo) + ,.resp_receive_i(fsm_resp_yumi_lo) + ,.lce_resp_header_i(fsm_resp_header_li) + ,.mem_rev_receive_i(fsm_rev_yumi_lo & fsm_rev_last_li) + ,.mem_rev_squash_i(fsm_rev_yumi_lo & spec_bits_lo.squash & fsm_rev_last_li) + ,.mem_rev_header_i(fsm_rev_header_li) + ,.mem_fwd_send_i(fsm_fwd_v_lo & fsm_fwd_new_lo) + ,.mem_fwd_header_i(fsm_fwd_header_lo) + ); + end + end + + bp_nonsynth_if_verif + #(.bp_params_p(bp_params_p)) + if_verif + (); + +`ifdef ASSERT_ENABLE + initial + begin + $assertoff(); + @(posedge clk_i); + @(negedge reset_i); + $asserton(); + end +`endif + +`ifdef TRACE_ENABLE + string dumpfile; + initial + if ($value$plusargs("bsg_trace=%s", dumpfile)) + begin + $display("[BSG-INFO]: Dumping to %s", dumpfile); +`ifdef FSDB_ENABLE + $fsdbDumpfile(dumpfile); + $fsdbDumpvars(0,testbench.wrapper); +`elsif VPD_ENABLE + $vcdplusfile(dumpfile); + $vcdpluson(0,testbench.wrapper); + $vcdplusautoflushon(); +`else + $dumpfile(dumpfile); + $dumpvars(0,testbench.wrapper); +`endif + end +`endif + +`include "__rtlmeter_top_include.vh" + +endmodule + diff --git a/designs/black-parrot/src/bp/wrapper.sv b/designs/black-parrot/src/bp/wrapper.sv new file mode 100644 index 0000000..320488b --- /dev/null +++ b/designs/black-parrot/src/bp/wrapper.sv @@ -0,0 +1,74 @@ +/** + * + * wrapper.sv + * + */ + +`include "bp_common_defines.svh" +`include "bp_be_defines.svh" +`include "bp_me_defines.svh" +`include "bsg_noc_links.svh" + +module wrapper + import bsg_wormhole_router_pkg::*; + import bp_common_pkg::*; + import bp_be_pkg::*; + import bp_me_pkg::*; + import bsg_noc_pkg::*; + #(parameter bp_params_e bp_params_p = e_bp_default_cfg + `declare_bp_proc_params(bp_params_p) + + `declare_bp_bedrock_if_widths(paddr_width_p, lce_id_width_p, cce_id_width_p, did_width_p, lce_assoc_p) + + , localparam dma_pkt_width_lp = `bsg_cache_dma_pkt_width(daddr_width_p, l2_block_size_in_words_p) + ) + (input clk_i + , input rt_clk_i + , input reset_i + + , input [did_width_p-1:0] my_did_i + , input [did_width_p-1:0] host_did_i + + // Outgoing I/O + , output logic [mem_fwd_header_width_lp-1:0] mem_fwd_header_o + , output logic [bedrock_fill_width_p-1:0] mem_fwd_data_o + , output logic mem_fwd_v_o + , input mem_fwd_ready_and_i + + , input [mem_rev_header_width_lp-1:0] mem_rev_header_i + , input [bedrock_fill_width_p-1:0] mem_rev_data_i + , input mem_rev_v_i + , output logic mem_rev_ready_and_o + + // Incoming I/O + , input [mem_fwd_header_width_lp-1:0] mem_fwd_header_i + , input [bedrock_fill_width_p-1:0] mem_fwd_data_i + , input mem_fwd_v_i + , output logic mem_fwd_ready_and_o + + , output logic [mem_rev_header_width_lp-1:0] mem_rev_header_o + , output logic [bedrock_fill_width_p-1:0] mem_rev_data_o + , output logic mem_rev_v_o + , input mem_rev_ready_and_i + + // DRAM interface + , output logic [num_cce_p-1:0][l2_dmas_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_o + , output logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_pkt_v_o + , input [num_cce_p-1:0][l2_dmas_p-1:0] dma_pkt_ready_and_i + + , input [num_cce_p-1:0][l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_i + , input [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_v_i + , output logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_ready_and_o + + , output logic [num_cce_p-1:0][l2_dmas_p-1:0][l2_fill_width_p-1:0] dma_data_o + , output logic [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_v_o + , input [num_cce_p-1:0][l2_dmas_p-1:0] dma_data_ready_and_i + ); + + bp_processor + #(.bp_params_p(bp_params_p)) + processor + (.*); + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/HardFloat_consts.vi b/designs/black-parrot/src/hardfloat/HardFloat_consts.vi new file mode 100644 index 0000000..0ec3590 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/HardFloat_consts.vi @@ -0,0 +1,58 @@ + +/*============================================================================ + +This Verilog include file is part of the Berkeley HardFloat IEEE Floating- +Point Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +`define round_near_even 3'b000 +`define round_minMag 3'b001 +`define round_min 3'b010 +`define round_max 3'b011 +`define round_near_maxMag 3'b100 +`define round_odd 3'b110 + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +`define floatControlWidth 1 +`define flControl_tininessBeforeRounding 1'b0 +`define flControl_tininessAfterRounding 1'b1 + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +`define flRoundOpt_sigMSBitAlwaysZero 1 +`define flRoundOpt_subnormsAlwaysExact 2 +`define flRoundOpt_neverUnderflows 4 +`define flRoundOpt_neverOverflows 8 + diff --git a/designs/black-parrot/src/hardfloat/HardFloat_localFuncs.vi b/designs/black-parrot/src/hardfloat/HardFloat_localFuncs.vi new file mode 100644 index 0000000..787c0b3 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/HardFloat_localFuncs.vi @@ -0,0 +1,49 @@ + +/*============================================================================ + +This Verilog include file is part of the Berkeley HardFloat IEEE Floating- +Point Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +function integer clog2; + input integer fa; + + begin + fa = fa - 1; + for (clog2 = 0; fa > 0; clog2 = clog2 + 1) fa = fa>>1; + end + +endfunction + diff --git a/designs/black-parrot/src/hardfloat/HardFloat_primitives.v b/designs/black-parrot/src/hardfloat/HardFloat_primitives.v new file mode 100644 index 0000000..3274104 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/HardFloat_primitives.v @@ -0,0 +1,173 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + reverse#(parameter width = 1) ( + input [(width - 1):0] in, output [(width - 1):0] out + ); + + genvar ix; + generate + for (ix = 0; ix < width; ix = ix + 1) begin :Bit + assign out[ix] = in[width - 1 - ix]; + end + endgenerate + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + lowMaskHiLo#( + parameter inWidth = 1, + parameter topBound = 1, + parameter bottomBound = 0 + ) ( + input [(inWidth - 1):0] in, + output [(topBound - bottomBound - 1):0] out + ); + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + localparam numInVals = 1<>>in)>>(numInVals - topBound); + reverse#(topBound - bottomBound) reverse(reverseOut, out); + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + lowMaskLoHi#( + parameter inWidth = 1, + parameter topBound = 0, + parameter bottomBound = 1 + ) ( + input [(inWidth - 1):0] in, + output [(bottomBound - topBound - 1):0] out + ); + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + localparam numInVals = 1<>>~in)>>(topBound + 1); + reverse#(bottomBound - topBound) reverse(reverseOut, out); + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + countLeadingZeros#(parameter inWidth = 1, parameter countWidth = 1) ( + input [(inWidth - 1):0] in, output [(countWidth - 1):0] count + ); + + wire [(inWidth - 1):0] reverseIn; + reverse#(inWidth) reverse_in(in, reverseIn); + wire [inWidth:0] oneLeastReverseIn = + {1'b1, reverseIn} & ({1'b0, ~reverseIn} + 1); + genvar ix; + generate + for (ix = 0; ix <= inWidth; ix = ix + 1) begin :Bit + wire [(countWidth - 1):0] countSoFar; + if (ix == 0) begin + assign countSoFar = 0; + end else begin + assign countSoFar = + Bit[ix - 1].countSoFar | (oneLeastReverseIn[ix] ? ix : 0); + if (ix == inWidth) assign count = countSoFar; + end + end + endgenerate + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + compressBy2#(parameter inWidth = 1) ( + input [(inWidth - 1):0] in, output [((inWidth - 1)/2):0] out + ); + + localparam maxBitNumReduced = (inWidth - 1)/2; + genvar ix; + generate + for (ix = 0; ix < maxBitNumReduced; ix = ix + 1) begin :Bit + assign out[ix] = |in[(ix*2 + 1):ix*2]; + end + endgenerate + assign out[maxBitNumReduced] = |in[(inWidth - 1):maxBitNumReduced*2]; + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + compressBy4#(parameter inWidth = 1) ( + input [(inWidth - 1):0] in, output [(inWidth - 1)/4:0] out + ); + + localparam maxBitNumReduced = (inWidth - 1)/4; + genvar ix; + generate + for (ix = 0; ix < maxBitNumReduced; ix = ix + 1) begin :Bit + assign out[ix] = |in[(ix*4 + 3):ix*4]; + end + endgenerate + assign out[maxBitNumReduced] = |in[(inWidth - 1):maxBitNumReduced*4]; + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/HardFloat_rawFN.v b/designs/black-parrot/src/hardfloat/HardFloat_rawFN.v new file mode 100644 index 0000000..4a631d1 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/HardFloat_rawFN.v @@ -0,0 +1,458 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +`include "HardFloat_consts.vi" +`include "HardFloat_specialize.vi" + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + recFNToRawFN#(parameter expWidth = 3, parameter sigWidth = 3) ( + input [(expWidth + sigWidth):0] in, + output isNaN, + output isInf, + output isZero, + output sign, + output signed [(expWidth + 1):0] sExp, + output [sigWidth:0] sig + ); + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire [expWidth:0] exp; + wire [(sigWidth - 2):0] fract; + assign {sign, exp, fract} = in; + wire isSpecial = (exp>>(expWidth - 1) == 'b11); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + assign isNaN = isSpecial && exp[expWidth - 2]; + assign isInf = isSpecial && !exp[expWidth - 2]; + assign isZero = (exp>>(expWidth - 2) == 'b000); + assign sExp = exp; + assign sig = {1'b0, !isZero, fract}; + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + roundAnyRawFNToRecFN#( + parameter inExpWidth = 3, + parameter inSigWidth = 3, + parameter outExpWidth = 3, + parameter outSigWidth = 3, + parameter options = 0 + ) ( + input [(`floatControlWidth - 1):0] control, + input invalidExc, // overrides 'infiniteExc' and 'in_*' inputs + input infiniteExc, // overrides 'in_*' inputs except 'in_sign' + input in_isNaN, + input in_isInf, + input in_isZero, + input in_sign, + input signed [(inExpWidth + 1):0] in_sExp, // limited range allowed + input [inSigWidth:0] in_sig, + input [2:0] roundingMode, + output [(outExpWidth + outSigWidth):0] out, + output [4:0] exceptionFlags + ); + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + localparam sigMSBitAlwaysZero = + ((options & `flRoundOpt_sigMSBitAlwaysZero) != 0); + localparam effectiveInSigWidth = + sigMSBitAlwaysZero ? inSigWidth : inSigWidth + 1; + localparam neverUnderflows = + ((options + & (`flRoundOpt_neverUnderflows + | `flRoundOpt_subnormsAlwaysExact)) + != 0) + || (inExpWidth < outExpWidth); + localparam neverOverflows = + ((options & `flRoundOpt_neverOverflows) != 0) + || (inExpWidth < outExpWidth); + localparam adjustedExpWidth = + (inExpWidth < outExpWidth) ? outExpWidth + 1 + : (inExpWidth == outExpWidth) ? inExpWidth + 2 + : inExpWidth + 3; + localparam outNaNExp = 7<<(outExpWidth - 2); + localparam outInfExp = 6<<(outExpWidth - 2); + localparam outMaxFiniteExp = outInfExp - 1; + localparam outMinNormExp = (1<<(outExpWidth - 1)) + 2; + localparam outMinNonzeroExp = outMinNormExp - outSigWidth + 1; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire roundingMode_near_even = (roundingMode == `round_near_even); + wire roundingMode_minMag = (roundingMode == `round_minMag); + wire roundingMode_min = (roundingMode == `round_min); + wire roundingMode_max = (roundingMode == `round_max); + wire roundingMode_near_maxMag = (roundingMode == `round_near_maxMag); + wire roundingMode_odd = (roundingMode == `round_odd); + wire roundMagUp = + (roundingMode_min && in_sign) || (roundingMode_max && !in_sign); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaNOut = invalidExc || (!infiniteExc && in_isNaN); +`ifdef HardFloat_propagateNaNPayloads + wire propagateNaNPayload = isNaNOut; +`else + wire propagateNaNPayload = 0; +`endif + wire signed [(adjustedExpWidth - 1):0] sAdjustedExp = + in_sExp + ((1<>3 : adjustedSig>>2; + assign common_overflow = 0; + assign common_totalUnderflow = 0; + assign common_underflow = 0; + assign common_inexact = 0; + end else begin + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + wire [(outSigWidth + 2):0] roundMask; + if (neverUnderflows) begin + assign roundMask = {doShiftSigDown1, 2'b11}; + end else begin + wire [outSigWidth:0] roundMask_main; + lowMaskLoHi#( + outExpWidth + 1, + outMinNormExp - outSigWidth - 1, + outMinNormExp + ) lowMask_roundMask( + sAdjustedExp[outExpWidth:0] + | (propagateNaNPayload ? 1'b1<>1; + wire [(outSigWidth + 2):0] roundPosMask = + ~shiftedRoundMask & roundMask; + wire roundPosBit = + (|(adjustedSig[(outSigWidth + 2):3] + & roundPosMask[(outSigWidth + 2):3])) + || ((|(adjustedSig[2:0] & roundPosMask[2:0])) + && !propagateNaNPayload); + wire anyRoundExtra = + (|(adjustedSig[(outSigWidth + 2):3] + & shiftedRoundMask[(outSigWidth + 2):3])) + || ((|(adjustedSig[2:0] & shiftedRoundMask[2:0])) + && !propagateNaNPayload); + wire anyRound = roundPosBit || anyRoundExtra; + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + wire roundIncr = + ((roundingMode_near_even || roundingMode_near_maxMag) + && roundPosBit) + || (roundMagUp && anyRound); + wire [(outSigWidth + 1):0] roundedSig = + roundIncr + ? (((adjustedSig | roundMask)>>2) + 1) + & ~(roundingMode_near_even && roundPosBit + && !anyRoundExtra + ? roundMask>>1 : 0) + : (adjustedSig & ~roundMask)>>2 + | (roundingMode_odd && anyRound + ? roundPosMask>>1 : 0); + wire signed [adjustedExpWidth:0] sExtAdjustedExp = sAdjustedExp; + wire signed [adjustedExpWidth:0] sRoundedExp = + sExtAdjustedExp + (roundedSig>>outSigWidth); + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + assign common_expOut = sRoundedExp; + assign common_fractOut = + doShiftSigDown1 ? roundedSig>>1 : roundedSig; + assign common_overflow = + neverOverflows ? 0 : (sRoundedExp>>>(outExpWidth - 1) >= 3); + assign common_totalUnderflow = + neverUnderflows ? 0 : (sRoundedExp < outMinNonzeroExp); + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + wire unboundedRange_roundPosBit = + doShiftSigDown1 ? adjustedSig[2] : adjustedSig[1]; + wire unboundedRange_anyRound = + (doShiftSigDown1 && adjustedSig[2]) || (|adjustedSig[1:0]); + wire unboundedRange_roundIncr = + ((roundingMode_near_even || roundingMode_near_maxMag) + && unboundedRange_roundPosBit) + || (roundMagUp && unboundedRange_anyRound); + wire roundCarry = + doShiftSigDown1 + ? roundedSig[outSigWidth + 1] : roundedSig[outSigWidth]; + assign common_underflow = + neverUnderflows ? 0 + : common_totalUnderflow + || (anyRound && (sAdjustedExp>>>outExpWidth <= 0) + && (doShiftSigDown1 + ? roundMask[3] : roundMask[2]) + && !(((control + & `flControl_tininessAfterRounding) + != 0) + && !(doShiftSigDown1 ? roundMask[4] + : roundMask[3]) + && roundCarry && roundPosBit + && unboundedRange_roundIncr)); + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + assign common_inexact = common_totalUnderflow || anyRound; + end + endgenerate + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire notNaN_isSpecialInfOut = infiniteExc || in_isInf; + wire commonCase = !isNaNOut && !notNaN_isSpecialInfOut && !in_isZero; + wire overflow = commonCase && common_overflow; + wire underflow = commonCase && common_underflow; + wire inexact = overflow || (commonCase && common_inexact); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire overflow_roundMagUp = + roundingMode_near_even || roundingMode_near_maxMag || roundMagUp; + wire pegMinNonzeroMagOut = + commonCase && common_totalUnderflow + && (roundMagUp || roundingMode_odd); + wire pegMaxFiniteMagOut = overflow && !overflow_roundMagUp; + wire notNaN_isInfOut = + notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ +`ifdef HardFloat_propagateNaNPayloads + wire signOut = in_sign; +`else + wire signOut = isNaNOut ? `HardFloat_signDefaultNaN : in_sign; +`endif + wire [outExpWidth:0] expOut = + (common_expOut + & ~(in_isZero || common_totalUnderflow ? 7<<(outExpWidth - 2) : 0) + & ~(pegMinNonzeroMagOut ? ~outMinNonzeroExp : 0) + & ~(pegMaxFiniteMagOut ? 1<<(outExpWidth - 1) : 0) + & ~(notNaN_isInfOut ? 1<<(outExpWidth - 2) : 0)) + | (pegMinNonzeroMagOut ? outMinNonzeroExp : 0) + | (pegMaxFiniteMagOut ? outMaxFiniteExp : 0) + | (notNaN_isInfOut ? outInfExp : 0) + | (isNaNOut ? outNaNExp : 0); +`ifdef HardFloat_propagateNaNPayloads + wire [(outSigWidth - 2):0] fractOut = + {isNaNOut + || (!in_isZero && !common_totalUnderflow + && common_fractOut[outSigWidth - 2]), + isNaNOut || (!in_isZero && !common_totalUnderflow) + ? common_fractOut[(outSigWidth - 3):0] : 1'b0} + | {(outSigWidth - 1){pegMaxFiniteMagOut}}; +`else + wire [(outSigWidth - 2):0] fractOut = + (isNaNOut ? `HardFloat_fractDefaultNaN(outSigWidth) : 0) + | (!in_isZero && !common_totalUnderflow + ? common_fractOut & `HardFloat_fractDefaultNaN(outSigWidth) : 0) + | (!isNaNOut && !in_isZero && !common_totalUnderflow + ? common_fractOut & ~`HardFloat_fractDefaultNaN(outSigWidth) + : 0) + | {(outSigWidth - 1){pegMaxFiniteMagOut}}; +`endif + assign out = {signOut, expOut, fractOut}; + assign exceptionFlags = + {invalidExc, infiniteExc, overflow, underflow, inexact}; + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + roundRawFNToRecFN#( + parameter expWidth = 3, + parameter sigWidth = 3, + parameter options = 0 + ) ( + input [(`floatControlWidth - 1):0] control, + input invalidExc, // overrides 'infiniteExc' and 'in_*' inputs + input infiniteExc, // overrides 'in_*' inputs except 'in_sign' + input in_isNaN, + input in_isInf, + input in_isZero, + input in_sign, + input signed [(expWidth + 1):0] in_sExp, // limited range allowed + input [(sigWidth + 2):0] in_sig, + input [2:0] roundingMode, + output [(expWidth + sigWidth):0] out, + output [4:0] exceptionFlags + ); + + roundAnyRawFNToRecFN#(expWidth, sigWidth + 2, expWidth, sigWidth, options) + roundAnyRawFNToRecFN( + control, + invalidExc, + infiniteExc, + in_isNaN, + in_isInf, + in_isZero, + in_sign, + in_sExp, + in_sig, + roundingMode, + out, + exceptionFlags + ); + +endmodule + +// DWP (BSG) 02/01/2023 +// This module is used for mixed-precision operations +// The input is a RAW FP value which is then +// - rounded to the max precision +// - rounded to an intermediate precision and upconverted back to a higher precision +// Output is recoded + +module + roundRawFNtoRecFN_mixed#( + parameter fullExpWidth = 3, + parameter fullSigWidth = 3, + parameter midExpWidth = 3, + parameter midSigWidth = 3, + parameter outExpWidth = 3, + parameter outSigWidth = 3 + ) ( + input [(`floatControlWidth - 1):0] control, + input invalidExc, // overrides 'infiniteExc' and 'in_*' inputs + input infiniteExc, // overrides 'in_*' inputs except 'in_sign' + input in_isNaN, + input in_isInf, + input in_isZero, + input in_sign, + input signed [(fullExpWidth + 1):0] in_sExp, // limited range allowed + input [(fullSigWidth + 2):0] in_sig, + input [2:0] roundingMode, + output [(outExpWidth + outSigWidth):0] fullOut, + output [4:0] fullExceptionFlags, + output [(outExpWidth + outSigWidth):0] midOut, + output [4:0] midExceptionFlags + ); + + // synopsys translate_off + if ((midExpWidth > fullExpWidth) || (midSigWidth > fullSigWidth)) + $error("Intermediate rounding must be smaller than input"); + + if ((midExpWidth > outExpWidth) || (midSigWidth > outSigWidth)) + $error("Intermediate rounding must be smaller than output"); + // synopsys translate_on + + roundAnyRawFNToRecFN + #(.inExpWidth(fullExpWidth) + ,.inSigWidth(fullSigWidth+2) // See the HardFloat docs for an explanation + ,.outExpWidth(fullExpWidth) + ,.outSigWidth(fullSigWidth) + ) + round64 + (.control(control) + ,.invalidExc(invalidExc) + ,.infiniteExc(infiniteExc) + ,.in_isNaN(in_isNaN) + ,.in_isInf(in_isInf) + ,.in_isZero(in_isZero) + ,.in_sign(in_sign) + ,.in_sExp(in_sExp) + ,.in_sig(in_sig) + ,.roundingMode(roundingMode) + + ,.out(fullOut) + ,.exceptionFlags(fullExceptionFlags) + ); + + wire [(midExpWidth + midSigWidth):0] midResult; + roundAnyRawFNToRecFN + #(.inExpWidth(fullExpWidth) + ,.inSigWidth(fullSigWidth+2) // See the HardFloat docs for an explanation + ,.outExpWidth(midExpWidth) + ,.outSigWidth(midSigWidth) + ) + round32 + (.control(control) + ,.invalidExc(invalidExc) + ,.infiniteExc(infiniteExc) + ,.in_isNaN(in_isNaN) + ,.in_isInf(in_isInf) + ,.in_isZero(in_isZero) + ,.in_sign(in_sign) + ,.in_sExp(in_sExp) + ,.in_sig(in_sig) + ,.roundingMode(roundingMode) + + ,.out(midResult) + ,.exceptionFlags(midExceptionFlags) + ); + + recFNToRecFN_unsafe + #(.inExpWidth(midExpWidth) + ,.inSigWidth(midSigWidth) + ,.outExpWidth(outExpWidth) + ,.outSigWidth(outSigWidth) + ) + recover + (.in(midResult) + ,.out(midOut) + ); + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/HardFloat_specialize.v b/designs/black-parrot/src/hardfloat/HardFloat_specialize.v new file mode 100644 index 0000000..48eb58e --- /dev/null +++ b/designs/black-parrot/src/hardfloat/HardFloat_specialize.v @@ -0,0 +1,52 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + iNFromException#(parameter width = 1) ( + input signedOut, + input isNaN, + input sign, + output [(width - 1):0] out + ); + + wire maxInt = isNaN || !sign; + assign out = {signedOut ^ maxInt, {(width - 1){maxInt}}}; + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/HardFloat_specialize.vi b/designs/black-parrot/src/hardfloat/HardFloat_specialize.vi new file mode 100644 index 0000000..ada7462 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/HardFloat_specialize.vi @@ -0,0 +1,49 @@ + +/*============================================================================ + +This Verilog include file is part of the Berkeley HardFloat IEEE Floating- +Point Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +`define flControl_default `flControl_tininessAfterRounding + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +//`define HardFloat_propagateNaNPayloads + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +`define HardFloat_signDefaultNaN 1'b0 +`define HardFloat_fractDefaultNaN(sigWidth) {1'b1, {((sigWidth) - 2){1'b0}}} + diff --git a/designs/black-parrot/src/hardfloat/compareRecFN.v b/designs/black-parrot/src/hardfloat/compareRecFN.v new file mode 100644 index 0000000..3317a25 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/compareRecFN.v @@ -0,0 +1,106 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + compareRecFN#(parameter expWidth = 3, parameter sigWidth = 3) ( + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + input signaling, + output lt, + output eq, + output gt, + output unordered, + output [4:0] exceptionFlags + ); + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaNA, isInfA, isZeroA, signA; + wire signed [(expWidth + 1):0] sExpA; + wire [sigWidth:0] sigA; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA); + wire isSigNaNA; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA); + wire isNaNB, isInfB, isZeroB, signB; + wire signed [(expWidth + 1):0] sExpB; + wire [sigWidth:0] sigB; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB); + wire isSigNaNB; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire ordered = !isNaNA && !isNaNB; + wire bothInfs = isInfA && isInfB; + wire bothZeros = isZeroA && isZeroB; + // FIX provided by John Hauser. + // If one of input is recoded infinity with some bits in exp as x, + // expExps and common_ltMags go x, which propagates to the outputs. + // wire eqExps = (sExpA == sExpB); + // wire common_ltMags = (sExpA < sExpB) || (eqExps && (sigA < sigB)); + wire eqHiExps = (sExpA>>(expWidth - 2) == sExpB>>(expWidth - 2)); + wire eqExps = + eqHiExps && (sExpA[(expWidth - 3):0] == sExpB[(expWidth - 3):0]); + wire common_ltMags = + (sExpA>>(expWidth - 2) < sExpB>>(expWidth - 2)) + || (eqHiExps + && (sExpA[(expWidth - 3):0] < sExpB[(expWidth - 3):0])) + || (eqExps && (sigA < sigB)); + + wire common_eqMags = eqExps && (sigA == sigB); + wire ordered_lt = + !bothZeros + && ((signA && !signB) + || (!bothInfs + && ((signA && !common_ltMags && !common_eqMags) + || (!signB && common_ltMags)))); + wire ordered_eq = + bothZeros || ((signA == signB) && (bothInfs || common_eqMags)); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire invalid = isSigNaNA || isSigNaNB || (signaling && !ordered); + assign lt = ordered && ordered_lt; + assign eq = ordered && ordered_eq; + assign gt = ordered && !ordered_lt && !ordered_eq; + assign unordered = !ordered; + assign exceptionFlags = {invalid, 4'b0}; + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/divSqrtRecFN.v b/designs/black-parrot/src/hardfloat/divSqrtRecFN.v new file mode 100644 index 0000000..e85e24b --- /dev/null +++ b/designs/black-parrot/src/hardfloat/divSqrtRecFN.v @@ -0,0 +1,171 @@ +//==================================================================== +// Schematics: https://docs.google.com/presentation/d/1CLZtLB3oHdmMLjzTL960ydjGzhS26V1yuOX5suPqSh4/edit?usp=sharing +//==================================================================== + +`include "HardFloat_consts.vi" +`include "HardFloat_specialize.vi" + +module + divSqrtRecFN#( + parameter expWidth = 8, parameter sigWidth = 24, + parameter options = 0, parameter bits_per_iter_p = 1 + ) ( + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input nReset, + input clock, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input [(`floatControlWidth - 1):0] control, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output inReady, + input inValid, + input sqrtOp, + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + input [2:0] roundingMode, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output outValid, + output sqrtOpOut, + output [(expWidth + sigWidth):0] out, + output [4:0] exceptionFlags + ); + + generate + if(bits_per_iter_p == 2) + begin: divSqrtTwoBitPerIter + divSqrtRecFN_medium#(expWidth,sigWidth,options) + divSqrtRecFN_2bit( + nReset, + clock, + control, + inReady, + inValid, + sqrtOp, + a, + b, + roundingMode, + outValid, + sqrtOpOut, + out, + exceptionFlags + ); + end + else + begin: divSqrtOneBitPerIter + divSqrtRecFN_small#(expWidth,sigWidth,options) + divSqrtRecFN_1bit( + nReset, + clock, + control, + inReady, + inValid, + sqrtOp, + a, + b, + roundingMode, + outValid, + sqrtOpOut, + out, + exceptionFlags + ); + end + endgenerate + +endmodule + +module + divSqrtRecFNToRaw #( + parameter expWidth = 8, parameter sigWidth = 24, + parameter options = 0, parameter bits_per_iter_p = 1 + ) ( + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input nReset, + input clock, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input [(`floatControlWidth - 1):0] control, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output inReady, + input inValid, + input sqrtOp, + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + input [2:0] roundingMode, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output outValid, + output sqrtOpOut, + output [2:0] roundingModeOut, + output invalidExc, + output infiniteExc, + output out_isNaN, + output out_isInf, + output out_isZero, + output out_sign, + output signed [(expWidth + 1):0] out_sExp, + output [(sigWidth + 2):0] out_sig + ); + + generate + if(bits_per_iter_p == 2) + begin: divSqrtTwoBitPerIter + divSqrtRecFNToRaw_medium#(expWidth, sigWidth, options) + divSqrtRecFNToRaw( + nReset, + clock, + control, + inReady, + inValid, + sqrtOp, + a, + b, + roundingMode, + outValid, + sqrtOpOut, + roundingModeOut, + invalidExc, + infiniteExc, + out_isNaN, + out_isInf, + out_isZero, + out_sign, + out_sExp, + out_sig + ); + end + else + begin: divSqrtOneBitPerIter + divSqrtRecFNToRaw_small#(expWidth, sigWidth, options) + divSqrtRecFNToRaw( + nReset, + clock, + control, + inReady, + inValid, + sqrtOp, + a, + b, + roundingMode, + outValid, + sqrtOpOut, + roundingModeOut, + invalidExc, + infiniteExc, + out_isNaN, + out_isInf, + out_isZero, + out_sign, + out_sExp, + out_sig + ); + end + endgenerate + + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/divSqrtRecFN_medium.v b/designs/black-parrot/src/hardfloat/divSqrtRecFN_medium.v new file mode 100644 index 0000000..85d1ca8 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/divSqrtRecFN_medium.v @@ -0,0 +1,368 @@ +`include "HardFloat_consts.vi" +`include "HardFloat_specialize.vi" + +/*---------------------------------------------------------------------------- +| Computes a division or square root for floating-point in recoded form. +| Multiple clock cycles are needed for each division or square-root operation, +| except possibly in special cases. +*----------------------------------------------------------------------------*/ + +module + divSqrtRecFNToRaw_medium#( + parameter expWidth = 8, parameter sigWidth = 24, parameter options = 0 + ) ( + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input nReset, + input clock, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input [(`floatControlWidth - 1):0] control, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output inReady, + input inValid, + input sqrtOp, + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + input [2:0] roundingMode, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output outValid, + output sqrtOpOut, + output [2:0] roundingModeOut, + output invalidExc, + output infiniteExc, + output out_isNaN, + output out_isInf, + output out_isZero, + output out_sign, + output signed [(expWidth + 1):0] out_sExp, + output [(sigWidth + 2):0] out_sig + ); + `include "HardFloat_localFuncs.vi" + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaNA_S, isInfA_S, isZeroA_S, signA_S; + wire signed [(expWidth + 1):0] sExpA_S; + wire [sigWidth:0] sigA_S; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_a( + a, isNaNA_S, isInfA_S, isZeroA_S, signA_S, sExpA_S, sigA_S); + wire isSigNaNA_S; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA_S); + wire isNaNB_S, isInfB_S, isZeroB_S, signB_S; + wire signed [(expWidth + 1):0] sExpB_S; + wire [sigWidth:0] sigB_S; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_b( + b, isNaNB_S, isInfB_S, isZeroB_S, signB_S, sExpB_S, sigB_S); + wire isSigNaNB_S; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB_S); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire notSigNaNIn_invalidExc_S_div = + (isZeroA_S && isZeroB_S) || (isInfA_S && isInfB_S); + wire notSigNaNIn_invalidExc_S_sqrt = !isNaNA_S && !isZeroA_S && signA_S; + wire majorExc_S = + sqrtOp ? isSigNaNA_S || notSigNaNIn_invalidExc_S_sqrt + : isSigNaNA_S || isSigNaNB_S || notSigNaNIn_invalidExc_S_div + || (!isNaNA_S && !isInfA_S && isZeroB_S); + wire isNaN_S = + sqrtOp ? isNaNA_S || notSigNaNIn_invalidExc_S_sqrt + : isNaNA_S || isNaNB_S || notSigNaNIn_invalidExc_S_div; + + wire isInf_S = sqrtOp ? isInfA_S : isInfA_S || isZeroB_S; + wire isZero_S = sqrtOp ? isZeroA_S : isZeroA_S || isInfB_S; + wire sign_S = signA_S ^ (!sqrtOp && signB_S); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire specialCaseA_S = isNaNA_S || isInfA_S || isZeroA_S; + wire specialCaseB_S = isNaNB_S || isInfB_S || isZeroB_S; + wire normalCase_S_div = !specialCaseA_S && !specialCaseB_S; + wire normalCase_S_sqrt = !specialCaseA_S && !signA_S; + wire normalCase_S = sqrtOp ? normalCase_S_sqrt : normalCase_S_div; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire signed [(expWidth + 2):0] sExpQuot_S_div = + sExpA_S + {{3{sExpB_S[expWidth]}}, ~sExpB_S[(expWidth - 1):0]}; + wire signed [(expWidth + 1):0] sSatExpQuot_S_div = + {(7<<(expWidth - 2) <= sExpQuot_S_div) ? 4'b0110 + : sExpQuot_S_div[(expWidth + 1):(expWidth - 2)], + sExpQuot_S_div[(expWidth - 3): 0]}; + wire evenSqrt_S = sqrtOp && !sExpA_S[0]; + wire oddSqrt_S = sqrtOp && sExpA_S[0]; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + reg [(clog2(sigWidth + 3) - 1):0] cycleNum; + reg sqrtOp_Z, majorExc_Z; + reg isNaN_Z, isInf_Z, isZero_Z, sign_Z; + reg signed [(expWidth + 1):0] sExp_Z; + reg [(sigWidth - 2):0] fractB_Z; + reg [2:0] roundingMode_Z; + /*------------------------------------------------------------------------ + | (The most-significant and least-significant bits of 'rem_Z' are needed + | only for square roots.) + *------------------------------------------------------------------------*/ + reg [(sigWidth + 1):0] rem_Z; + reg notZeroRem_Z; + reg [(sigWidth + 1):0] sigX_Z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire idle = (cycleNum == 0); + assign inReady = (cycleNum <= 1); + wire entering = inReady && inValid; + wire entering_normalCase = entering && normalCase_S; + wire skipCycle2 = (cycleNum == 4) && sigX_Z[sigWidth + 1]; + wire step1Case = skipCycle2 || (cycleNum <= 2); + + always @(posedge clock) begin + if (!nReset) begin + cycleNum <= 0; + end else begin + if (inValid || !idle) begin + cycleNum <= + (entering && !normalCase_S ? 1 : 0) + | (entering_normalCase + ? (sqrtOp ? (sExpA_S[0] ? sigWidth : sigWidth + 1) + : sigWidth + 2) + : 0) + | (!idle ? (cycleNum - (step1Case ? 1 : 2)) : 0); + end + end + end + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + + always @(posedge clock) begin + if (!nReset) begin + sqrtOp_Z <= 1'b0; + majorExc_Z <= 1'b0; + isNaN_Z <= 1'b0; + isInf_Z <= 1'b0; + isZero_Z <= 1'b0; + sign_Z <= 1'b0; + sExp_Z <= '0; + roundingMode_Z <= '0; + fractB_Z <= '0; + end + else begin + if (entering) begin + sqrtOp_Z <= sqrtOp; + majorExc_Z <= majorExc_S; + isNaN_Z <= isNaN_S; + isInf_Z <= isInf_S; + isZero_Z <= isZero_S; + sign_Z <= sign_S; + end + if (entering_normalCase) begin + sExp_Z <= sqrtOp ? (sExpA_S>>>1) + (1<<(expWidth - 1)) + : sSatExpQuot_S_div; + roundingMode_Z <= roundingMode; + end + + if (entering_normalCase && !sqrtOp) begin + fractB_Z <= sigB_S[(sigWidth - 2):0]; + end + + end + end + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire [1:0] decHiSigA_S = sigA_S[(sigWidth - 1):(sigWidth - 2)] - 1; + wire [(sigWidth + 2):0] rem = inReady ? + (oddSqrt_S ? + {decHiSigA_S, sigA_S[(sigWidth - 3):0], 3'b0} + : sigA_S<<1) + : rem_Z<<1; + wire [sigWidth:0] bitMask = ({{(sigWidth + 2){1'b0}}, 1'b1}<>2; + wire [sigWidth:0] bitMaskNext = bitMask>>1; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + + wire loadDiv = inReady && !sqrtOp; + wire loadEvenSqrt = inReady && evenSqrt_S; + wire loadOddSqrt = inReady && oddSqrt_S; + wire calc = !inReady; + wire calcDiv = calc && !sqrtOp_Z; + wire calcSqrt = calc && sqrtOp_Z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire [(sigWidth + 1):0] trialTerm; + + wire [4:0] [sigWidth+1:0] trialTermMuxIn = { + {sigB_S, 1'b0}, + {1'b0, 1'b1, sigWidth ' (1'b0)}, + {3'b101, (sigWidth-1) ' (1'b0)}, + {1'b0, {1'b1, fractB_Z}, 1'b0}, + {{sigX_Z[sigWidth:0],1'b0} | bitMask} + }; + + wire [4:0] trialTermSel = { + loadDiv, + loadEvenSqrt, + loadOddSqrt, + calcDiv, + calcSqrt + }; + + bsg_mux_one_hot #(.width_p(sigWidth+2),.els_p(5)) + trialTerm_mux( + .data_i(trialTermMuxIn), + .sel_one_hot_i(trialTermSel), + .data_o(trialTerm) + ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + + wire signed [(sigWidth + 3):0] trialRem1 = rem - trialTerm; + wire newBit1 = (0 <= trialRem1); + wire [(sigWidth + 1):0] sigXNext = sigX_Z | (newBit1 ? bitMask : 0); + wire [(sigWidth + 1):0] trialTermNext = sqrtOp_Z ? + sigXNext<<1 | bitMaskNext + :trialTerm; + wire [(sigWidth + 2):0] remNext = (newBit1 ? (trialRem1[(sigWidth + 1):0]) : (rem[(sigWidth + 1):0]))<<1; + wire signed [(sigWidth + 3):0] trialRem2 = remNext - trialTermNext ; + wire newBit2 = (0 <= trialRem2); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + + wire [(sigWidth + 1):0] sigX_N; + wire [3:0] [(sigWidth+1):0] sigX_NMuxIn = { + {newBit1, (sigWidth+1) ' (1'b0)}, + {2'b01, sigWidth ' (1'b0)}, + {2'b01, newBit1, (sigWidth-1) ' (1'b0)}, + {sigXNext | (newBit2 ? bitMaskNext : (sigWidth + 1) ' (1'b0))} + }; + + wire [3:0] sigX_NSel = { + loadDiv, + loadEvenSqrt, + loadOddSqrt, + calc + }; + + bsg_mux_one_hot #(.width_p(sigWidth+2),.els_p(4)) + sigX_N_mux( + .data_i(sigX_NMuxIn), + .sel_one_hot_i(sigX_NSel), + .data_o(sigX_N) + ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + + always @(posedge clock) begin + if (!nReset) begin + rem_Z <='0; + sigX_Z <='0; + notZeroRem_Z <= 1'b0; + end + else begin + if (entering_normalCase || (cycleNum > 2)) begin + rem_Z <= (inReady || skipCycle2) ? (newBit1 ? trialRem1 : rem) + :(newBit2 ? trialRem2 : remNext); + end + + if (entering_normalCase || (!inReady && (newBit1 | newBit2))) begin + notZeroRem_Z <= (trialRem1 != 0 && trialRem2 != 0); + sigX_Z <= sigX_N; + end + + end + end + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + assign outValid = (cycleNum == 1); + assign sqrtOpOut = sqrtOp_Z; + assign roundingModeOut = roundingMode_Z; + assign invalidExc = majorExc_Z && isNaN_Z; + assign infiniteExc = majorExc_Z && !isNaN_Z; + assign out_isNaN = isNaN_Z; + assign out_isInf = isInf_Z; + assign out_isZero = isZero_Z; + assign out_sign = sign_Z; + assign out_sExp = sExp_Z; + assign out_sig = {sigX_Z, notZeroRem_Z}; + +endmodule +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + divSqrtRecFN_medium#( + parameter expWidth = 8, parameter sigWidth = 24, parameter options = 0 + ) ( + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input nReset, + input clock, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input [(`floatControlWidth - 1):0] control, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output inReady, + input inValid, + input sqrtOp, + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + input [2:0] roundingMode, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output outValid, + output sqrtOpOut, + output [(expWidth + sigWidth):0] out, + output [4:0] exceptionFlags + ); + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + //wire sqrtOpOut; + wire [2:0] roundingModeOut; + wire invalidExc, infiniteExc, out_isNaN, out_isInf, out_isZero, out_sign; + wire signed [(expWidth + 1):0] out_sExp; + wire [(sigWidth + 2):0] out_sig; + divSqrtRecFNToRaw_medium#(expWidth, sigWidth, options) + divSqrtRecFNToRaw( + nReset, + clock, + control, + inReady, + inValid, + sqrtOp, + a, + b, + roundingMode, + outValid, + sqrtOpOut, + roundingModeOut, + invalidExc, + infiniteExc, + out_isNaN, + out_isInf, + out_isZero, + out_sign, + out_sExp, + out_sig + ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundRawFNToRecFN#(expWidth, sigWidth, 0) + roundRawOut( + control, + invalidExc, + infiniteExc, + out_isNaN, + out_isInf, + out_isZero, + out_sign, + out_sExp, + out_sig, + roundingModeOut, + out, + exceptionFlags + ); + +endmodule diff --git a/designs/black-parrot/src/hardfloat/divSqrtRecFN_small.v b/designs/black-parrot/src/hardfloat/divSqrtRecFN_small.v new file mode 100644 index 0000000..b55e75a --- /dev/null +++ b/designs/black-parrot/src/hardfloat/divSqrtRecFN_small.v @@ -0,0 +1,372 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +`include "HardFloat_consts.vi" +`include "HardFloat_specialize.vi" + +/*---------------------------------------------------------------------------- +| Computes a division or square root for floating-point in recoded form. +| Multiple clock cycles are needed for each division or square-root operation, +| except possibly in special cases. +*----------------------------------------------------------------------------*/ + +module + divSqrtRecFNToRaw_small#( + parameter expWidth = 3, parameter sigWidth = 3, parameter options = 0 + ) ( + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input nReset, + input clock, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + input [(`floatControlWidth - 1):0] control, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output inReady, + input inValid, + input sqrtOp, + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + input [2:0] roundingMode, + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + output outValid, + output sqrtOpOut, + output [2:0] roundingModeOut, + output invalidExc, + output infiniteExc, + output out_isNaN, + output out_isInf, + output out_isZero, + output out_sign, + output signed [(expWidth + 1):0] out_sExp, + output [(sigWidth + 2):0] out_sig + ); +`include "HardFloat_localFuncs.vi" + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaNA_S, isInfA_S, isZeroA_S, signA_S; + wire signed [(expWidth + 1):0] sExpA_S; + wire [sigWidth:0] sigA_S; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_a( + a, isNaNA_S, isInfA_S, isZeroA_S, signA_S, sExpA_S, sigA_S); + wire isSigNaNA_S; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA_S); + wire isNaNB_S, isInfB_S, isZeroB_S, signB_S; + wire signed [(expWidth + 1):0] sExpB_S; + wire [sigWidth:0] sigB_S; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_b( + b, isNaNB_S, isInfB_S, isZeroB_S, signB_S, sExpB_S, sigB_S); + wire isSigNaNB_S; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB_S); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire notSigNaNIn_invalidExc_S_div = + (isZeroA_S && isZeroB_S) || (isInfA_S && isInfB_S); + wire notSigNaNIn_invalidExc_S_sqrt = !isNaNA_S && !isZeroA_S && signA_S; + wire majorExc_S = + sqrtOp ? isSigNaNA_S || notSigNaNIn_invalidExc_S_sqrt + : isSigNaNA_S || isSigNaNB_S || notSigNaNIn_invalidExc_S_div + || (!isNaNA_S && !isInfA_S && isZeroB_S); + wire isNaN_S = + sqrtOp ? isNaNA_S || notSigNaNIn_invalidExc_S_sqrt + : isNaNA_S || isNaNB_S || notSigNaNIn_invalidExc_S_div; +`ifdef HardFloat_propagateNaNPayloads + wire signNaN_S; + wire [(sigWidth - 2):0] fractNaN_S; + propagateFloatNaN_divSqrt#(sigWidth) + propagateNaN( + control, + sqrtOp, + isNaNA_S, + signA_S, + sigA_S[(sigWidth - 2):0], + isNaNB_S, + signB_S, + sigB_S[(sigWidth - 2):0], + signNaN_S, + fractNaN_S + ); +`endif + wire isInf_S = sqrtOp ? isInfA_S : isInfA_S || isZeroB_S; + wire isZero_S = sqrtOp ? isZeroA_S : isZeroA_S || isInfB_S; + wire sign_S = signA_S ^ (!sqrtOp && signB_S); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire specialCaseA_S = isNaNA_S || isInfA_S || isZeroA_S; + wire specialCaseB_S = isNaNB_S || isInfB_S || isZeroB_S; + wire normalCase_S_div = !specialCaseA_S && !specialCaseB_S; + wire normalCase_S_sqrt = !specialCaseA_S && !signA_S; + wire normalCase_S = sqrtOp ? normalCase_S_sqrt : normalCase_S_div; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire signed [(expWidth + 2):0] sExpQuot_S_div = + sExpA_S + {{3{sExpB_S[expWidth]}}, ~sExpB_S[(expWidth - 1):0]}; + wire signed [(expWidth + 1):0] sSatExpQuot_S_div = + {(7<<(expWidth - 2) <= sExpQuot_S_div) ? 4'b0110 + : sExpQuot_S_div[(expWidth + 1):(expWidth - 2)], + sExpQuot_S_div[(expWidth - 3): 0]}; + wire evenSqrt_S = sqrtOp && !sExpA_S[0]; + wire oddSqrt_S = sqrtOp && sExpA_S[0]; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + reg [(clog2(sigWidth + 3) - 1):0] cycleNum; + reg sqrtOp_Z, majorExc_Z; + reg isNaN_Z, isInf_Z, isZero_Z, sign_Z; + reg signed [(expWidth + 1):0] sExp_Z; + reg [(sigWidth - 2):0] fractB_Z; + reg [2:0] roundingMode_Z; + /*------------------------------------------------------------------------ + | (The most-significant and least-significant bits of 'rem_Z' are needed + | only for square roots.) + *------------------------------------------------------------------------*/ + reg [(sigWidth + 1):0] rem_Z; + reg notZeroRem_Z; + reg [(sigWidth + 1):0] sigX_Z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire idle = (cycleNum == 0); + assign inReady = (cycleNum <= 1); + wire entering = inReady && inValid; + wire entering_normalCase = entering && normalCase_S; + wire skipCycle2 = (cycleNum == 3) && sigX_Z[sigWidth + 1]; + always @(posedge clock) begin + if (!nReset) begin + cycleNum <= 0; + end else begin + if (!idle || inValid) begin + cycleNum <= + (entering && !normalCase_S ? 1 : 0) + | (entering_normalCase + ? (sqrtOp ? (sExpA_S[0] ? sigWidth : sigWidth + 1) + : sigWidth + 2) + : 0) + | (!idle && !skipCycle2 ? cycleNum - 1 : 0) + | (!idle && skipCycle2 ? 1 : 0); + end + end + end + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + always @(posedge clock) begin + if (!nReset) begin + sqrtOp_Z <= 1'b0; + majorExc_Z <= 1'b0; + isNaN_Z <= 1'b0; + isInf_Z <= 1'b0; + isZero_Z <= 1'b0; + sign_Z <= 1'b0; + sExp_Z <= '0; + roundingMode_Z <= '0; + fractB_Z <= '0; + end + else begin + if (entering) begin + sqrtOp_Z <= sqrtOp; + majorExc_Z <= majorExc_S; + isNaN_Z <= isNaN_S; + isInf_Z <= isInf_S; + isZero_Z <= isZero_S; +`ifdef HardFloat_propagateNaNPayloads + sign_Z <= isNaN_S ? signNaN_S : sign_S; +`else + sign_Z <= sign_S; +`endif + end + if (entering_normalCase) begin + sExp_Z <= + sqrtOp ? (sExpA_S>>>1) + (1<<(expWidth - 1)) + : sSatExpQuot_S_div; + roundingMode_Z <= roundingMode; + end + if (entering_normalCase && !sqrtOp) begin + fractB_Z <= sigB_S[(sigWidth - 2):0]; + end + end + end + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire [1:0] decHiSigA_S = sigA_S[(sigWidth - 1):(sigWidth - 2)] - 1; + wire [(sigWidth + 2):0] rem = + (inReady && !oddSqrt_S ? sigA_S<<1 : 0) + | (inReady && oddSqrt_S + ? {decHiSigA_S, sigA_S[(sigWidth - 3):0], 3'b0} : 0) + | (!inReady ? rem_Z<<1 : 0); + wire [sigWidth:0] bitMask = ({{(sigWidth + 2){1'b0}}, 1'b1}<>2; + wire [(sigWidth + 1):0] trialTerm = + ( inReady && !sqrtOp ? sigB_S<<1 : 0) + | ( inReady && evenSqrt_S ? 1< 2)) begin + rem_Z <= newBit ? trialRem : rem; + end +`ifdef HardFloat_propagateNaNPayloads + if ( + (entering && isNaN_S) || entering_normalCase + || (!inReady && newBit) + ) begin + notZeroRem_Z <= (trialRem != 0); + sigX_Z <= + (inReady && isNaN_S ? {1'b1, fractNaN_S, 2'b00} : 0) + | (inReady && !isNaN_S && !sqrtOp ? newBit<<(sigWidth + 1) : 0) + | (inReady && !isNaN_S && sqrtOp ? 1<>(extIntWidth - intWidth); + assign isZero = !sig[intWidth - 1]; + assign sExp = {2'b10, ~adjustedNormDist}; + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + iNToRecFN#( + parameter intWidth = 1, parameter expWidth = 3, parameter sigWidth = 3 + ) ( + input [(`floatControlWidth - 1):0] control, + input signedIn, + input [(intWidth - 1):0] in, + input [2:0] roundingMode, + output [(expWidth + sigWidth):0] out, + output [4:0] exceptionFlags + ); +`include "HardFloat_localFuncs.vi" + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + localparam intExpWidth = clog2(intWidth) + 1; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isZero, sign; + wire signed [(intExpWidth + 1):0] sExp; + wire [intWidth:0] sig; + iNToRawFN#(intWidth) iNToRawFN(signedIn, in, isZero, sign, sExp, sig); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundAnyRawFNToRecFN#( + intExpWidth, + intWidth, + expWidth, + sigWidth, + `flRoundOpt_sigMSBitAlwaysZero | `flRoundOpt_neverUnderflows + ) roundRawToOut( + control, + 1'b0, + 1'b0, + 1'b0, + 1'b0, + isZero, + sign, + sExp, + sig, + roundingMode, + out, + exceptionFlags + ); + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/isSigNaNRecFN.v b/designs/black-parrot/src/hardfloat/isSigNaNRecFN.v new file mode 100644 index 0000000..90ff391 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/isSigNaNRecFN.v @@ -0,0 +1,50 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + isSigNaNRecFN#(parameter expWidth = 3, parameter sigWidth = 3) ( + input [(expWidth + sigWidth):0] in, output isSigNaN + ); + + wire isNaN = + (in[(expWidth + sigWidth - 1):(expWidth + sigWidth - 3)] == 'b111); + assign isSigNaN = isNaN && !in[sigWidth - 2]; + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/mulAddRecFN.v b/designs/black-parrot/src/hardfloat/mulAddRecFN.v new file mode 100644 index 0000000..87d8e40 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/mulAddRecFN.v @@ -0,0 +1,565 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +`include "HardFloat_consts.vi" +`include "HardFloat_specialize.vi" + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + mulAddRecFNToRaw_preMul#( + parameter expWidth = 3, parameter sigWidth = 3, parameter imulEn = 1 + ) ( + control, + op, + a, + b, + c, + roundingMode, + mulAddA, + mulAddB, + mulAddC, + intermed_compactState, + intermed_sExp, + intermed_CDom_CAlignDist, + intermed_highAlignedSigC + ); +`include "HardFloat_localFuncs.vi" + input [(`floatControlWidth - 1):0] control; + input [2:0] op; + input [(expWidth + sigWidth):0] a; + input [(expWidth + sigWidth):0] b; + input [(expWidth + sigWidth):0] c; + input [2:0] roundingMode; + output [(sigWidth - 1):0] mulAddA; + output [(sigWidth - 1):0] mulAddB; + output [(sigWidth*2 - 1):0] mulAddC; + output [5:0] intermed_compactState; + output signed [(expWidth + 1):0] intermed_sExp; + output [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist; + output [(sigWidth + 1):0] intermed_highAlignedSigC; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + localparam prodWidth = sigWidth*2; + localparam sigSumWidth = sigWidth + prodWidth + 3; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaNA, isInfA, isZeroA, signA; + wire signed [(expWidth + 1):0] sExpA; + wire [sigWidth:0] sigA; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA); + wire isSigNaNA; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA); + wire isNaNB, isInfB, isZeroB, signB; + wire signed [(expWidth + 1):0] sExpB; + wire [sigWidth:0] sigB; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB); + wire isSigNaNB; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB); + wire isNaNC, isInfC, isZeroC, signC; + wire signed [(expWidth + 1):0] sExpC; + wire [sigWidth:0] sigC; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_c(c, isNaNC, isInfC, isZeroC, signC, sExpC, sigC); + wire isSigNaNC; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_c(c, isSigNaNC); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire signProd = signA ^ signB ^ op[1]; + wire signed [(expWidth + 2):0] sExpAlignedProd = + sExpA + sExpB + (-(1<>>CAlignDist; + localparam CGrainAlign = (sigSumWidth - sigWidth - 1) & 3; + wire [(sigWidth + CGrainAlign):0] grainAlignedSigC = sigC<>3, + doSubMags ? (&mainAlignedSigC[2:0]) && !reduced4CExtra + : (|mainAlignedSigC[2:0]) || reduced4CExtra}; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaNAOrB = isNaNA || isNaNB; + wire isNaNAny = isNaNAOrB || isNaNC; + wire isInfAOrB = isInfA || isInfB; + wire invalidProd = (isInfA && isZeroB) || (isZeroA && isInfB); + wire notSigNaN_invalidExc = + invalidProd || (!isNaNAOrB && isInfAOrB && isInfC && doSubMags); + wire invalidExc = + isSigNaNA || isSigNaNB || isSigNaNC || notSigNaN_invalidExc; + wire notNaN_addZeros = (isZeroA || isZeroB) && isZeroC; + wire specialCase = isNaNAny || isInfAOrB || isInfC || notNaN_addZeros; + wire specialNotNaN_signOut = + (isInfAOrB && signProd) || (isInfC && opSignC) + || (notNaN_addZeros && !roundingMode_min && signProd && opSignC) + || (notNaN_addZeros && roundingMode_min && (signProd || opSignC)); +`ifdef HardFloat_propagateNaNPayloads + wire signNaN; + wire [(sigWidth - 2):0] fractNaN; + propagateFloatNaN_mulAdd#(sigWidth) + propagateNaN( + control, + op[1:0], + isNaNA, + signA, + sigA[(sigWidth - 2):0], + isNaNB, + signB, + sigB[(sigWidth - 2):0], + invalidProd, + isNaNC, + signC, + sigC[(sigWidth - 2):0], + signNaN, + fractNaN + ); + wire isNaNOut = isNaNAny || notSigNaN_invalidExc; + wire special_signOut = + isNaNAny || notSigNaN_invalidExc ? signNaN : specialNotNaN_signOut; +`else + wire special_signOut = specialNotNaN_signOut; +`endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if(imulEn) begin: fi1 + // This part has been modified so that we can support RISC-V integer multiply instruction MUL. + // Please refer to the document for detailed implementation. + assign mulAddA = op[2] ? a[sigWidth-1:0] : sigA; + assign mulAddB = op[2] ? b[sigWidth-1:0] : sigB; + // Generate modification bits + wire [expWidth-1:0] aux_part = a[expWidth-1:0] * b[sigWidth+:expWidth] + a[sigWidth+:expWidth] * b[expWidth-1:0]; + assign mulAddC = op[2] ? {{(sigWidth - expWidth){1'b0}}, aux_part, {sigWidth{1'b0}}} : alignedSigC[prodWidth:1]; + end + else begin: fi2 + assign mulAddA = sigA; + assign mulAddB = sigB; + assign mulAddC = alignedSigC[prodWidth:1]; + end + assign intermed_compactState = + {specialCase, + invalidExc || (!specialCase && signProd ), +`ifdef HardFloat_propagateNaNPayloads + isNaNOut || (!specialCase && doSubMags ), +`else + isNaNAny || (!specialCase && doSubMags ), +`endif + isInfAOrB || isInfC || (!specialCase && CIsDominant ), + notNaN_addZeros || (!specialCase && alignedSigC[0]), + special_signOut}; + assign intermed_sExp = sExpSum; + assign intermed_CDom_CAlignDist = CAlignDist[(clog2(sigWidth + 1) - 1):0]; + assign intermed_highAlignedSigC = +`ifdef HardFloat_propagateNaNPayloads + isNaNOut ? fractNaN : +`endif + alignedSigC[(sigSumWidth - 1):(prodWidth + 1)]; + +endmodule + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + mulAddRecFNToRaw_postMul#(parameter expWidth = 3, parameter sigWidth = 3) ( + intermed_compactState, + intermed_sExp, + intermed_CDom_CAlignDist, + intermed_highAlignedSigC, + mulAddResult, + roundingMode, + invalidExc, + out_isNaN, + out_isInf, + out_isZero, + out_sign, + out_sExp, + out_sig + ); +`include "HardFloat_localFuncs.vi" + input [5:0] intermed_compactState; + input signed [(expWidth + 1):0] intermed_sExp; + input [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist; + input [(sigWidth + 1):0] intermed_highAlignedSigC; + input [sigWidth*2:0] mulAddResult; + input [2:0] roundingMode; + output invalidExc; + output out_isNaN; + output out_isInf; + output out_isZero; + output out_sign; + output signed [(expWidth + 1):0] out_sExp; + output [(sigWidth + 2):0] out_sig; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + localparam prodWidth = sigWidth*2; + localparam sigSumWidth = sigWidth + prodWidth + 3; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire specialCase = intermed_compactState[5]; + assign invalidExc = specialCase && intermed_compactState[4]; + assign out_isNaN = specialCase && intermed_compactState[3]; + assign out_isInf = specialCase && intermed_compactState[2]; + wire notNaN_addZeros = specialCase && intermed_compactState[1]; + wire signProd = intermed_compactState[4]; + wire doSubMags = intermed_compactState[3]; + wire CIsDominant = intermed_compactState[2]; + wire bit0AlignedSigC = intermed_compactState[1]; + wire special_signOut = intermed_compactState[0]; +`ifdef HardFloat_propagateNaNPayloads + wire [(sigWidth - 2):0] fractNaN = intermed_highAlignedSigC; +`endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire opSignC = signProd ^ doSubMags; + wire [(sigWidth + 1):0] incHighAlignedSigC = intermed_highAlignedSigC + 1; + wire [(sigSumWidth - 1):0] sigSum = + {mulAddResult[prodWidth] ? incHighAlignedSigC + : intermed_highAlignedSigC, + mulAddResult[(prodWidth - 1):0], + bit0AlignedSigC}; + wire roundingMode_min = (roundingMode == `round_min); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire CDom_sign = opSignC; + wire signed [(expWidth + 1):0] CDom_sExp = intermed_sExp - doSubMags; + wire [(sigWidth*2 + 1):0] CDom_absSigSum = + doSubMags ? ~sigSum[(sigSumWidth - 1):(sigWidth + 1)] + : {1'b0, intermed_highAlignedSigC[(sigWidth + 1):sigWidth], + sigSum[(sigSumWidth - 3):(sigWidth + 2)]}; + wire CDom_absSigSumExtra = + doSubMags ? !(&sigSum[sigWidth:1]) : |sigSum[(sigWidth + 1):1]; + wire [(sigWidth + 4):0] CDom_mainSig = + (CDom_absSigSum<>(sigWidth - 3); + wire [((sigWidth | 3) - 1):0] CDom_grainAlignedLowSig = + CDom_absSigSum[(sigWidth - 1):0]<<(~sigWidth & 3); + wire [sigWidth/4:0] CDom_reduced4LowSig; + compressBy4#(sigWidth | 3) + compressBy4_CDom_absSigSum( + CDom_grainAlignedLowSig, CDom_reduced4LowSig); + wire [(sigWidth/4 - 1):0] CDom_sigExtraMask; + lowMaskLoHi#(clog2(sigWidth + 1) - 2, 0, sigWidth/4) + lowMask_CDom_sigExtraMask( + intermed_CDom_CAlignDist[(clog2(sigWidth + 1) - 1):2], + CDom_sigExtraMask + ); + wire CDom_reduced4SigExtra = |(CDom_reduced4LowSig & CDom_sigExtraMask); + wire [(sigWidth + 2):0] CDom_sig = + {CDom_mainSig>>3, + (|CDom_mainSig[2:0]) || CDom_reduced4SigExtra || CDom_absSigSumExtra}; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire notCDom_signSigSum = sigSum[prodWidth + 3]; + wire [(prodWidth + 2):0] notCDom_absSigSum = + notCDom_signSigSum ? ~sigSum[(prodWidth + 2):0] + : sigSum[(prodWidth + 2):0] + doSubMags; + wire [(prodWidth + 2)/2:0] notCDom_reduced2AbsSigSum; + compressBy2#(prodWidth + 3) + compressBy2_notCDom_absSigSum( + notCDom_absSigSum, notCDom_reduced2AbsSigSum); + wire [(clog2(prodWidth + 4) - 2):0] notCDom_normDistReduced2; + //countLeadingZeros#((prodWidth + 2)/2 + 1, clog2(prodWidth + 4) - 1) + // countLeadingZeros_notCDom( + // notCDom_reduced2AbsSigSum, notCDom_normDistReduced2); + bsg_counting_leading_zeros #( + .width_p((prodWidth + 2)/2 + 1) + ) clz ( + .a_i(notCDom_reduced2AbsSigSum) + ,.num_zero_o(notCDom_normDistReduced2) + ); + wire [(clog2(prodWidth + 4) - 1):0] notCDom_nearNormDist = + notCDom_normDistReduced2<<1; + wire signed [(expWidth + 1):0] notCDom_sExp = + intermed_sExp - notCDom_nearNormDist; + wire [(sigWidth + 4):0] notCDom_mainSig = + ({1'b0, notCDom_absSigSum}<>(sigWidth - 1); + wire [(((sigWidth/2 + 1) | 1) - 1):0] CDom_grainAlignedLowReduced2Sig = + notCDom_reduced2AbsSigSum[sigWidth/2:0]<<((sigWidth/2) & 1); + wire [(sigWidth + 2)/4:0] notCDom_reduced4AbsSigSum; + compressBy2#((sigWidth/2 + 1) | 1) + compressBy2_notCDom_reduced2AbsSigSum( + CDom_grainAlignedLowReduced2Sig, notCDom_reduced4AbsSigSum); + wire [((sigWidth + 2)/4 - 1):0] notCDom_sigExtraMask; + lowMaskLoHi#(clog2(prodWidth + 4) - 2, 0, (sigWidth + 2)/4) + lowMask_notCDom_sigExtraMask( + notCDom_normDistReduced2[(clog2(prodWidth + 4) - 2):1], + notCDom_sigExtraMask + ); + wire notCDom_reduced4SigExtra = + |(notCDom_reduced4AbsSigSum & notCDom_sigExtraMask); + wire [(sigWidth + 2):0] notCDom_sig = + {notCDom_mainSig>>3, + (|notCDom_mainSig[2:0]) || notCDom_reduced4SigExtra}; + wire notCDom_completeCancellation = + (notCDom_sig[(sigWidth + 2):(sigWidth + 1)] == 0); + wire notCDom_sign = + notCDom_completeCancellation ? roundingMode_min + : signProd ^ notCDom_signSigSum; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + assign out_isZero = + notNaN_addZeros || (!CIsDominant && notCDom_completeCancellation); + assign out_sign = + ( specialCase && special_signOut) + || (!specialCase && CIsDominant && CDom_sign ) + || (!specialCase && !CIsDominant && notCDom_sign ); + assign out_sExp = CIsDominant ? CDom_sExp : notCDom_sExp; +`ifdef HardFloat_propagateNaNPayloads + assign out_sig = + out_isNaN ? {1'b1, fractNaN, 2'b00} + : CIsDominant ? CDom_sig : notCDom_sig; +`else + assign out_sig = CIsDominant ? CDom_sig : notCDom_sig; +`endif + +endmodule + +/*---------------------------------------------------------------------------- + *----------------------------------------------------------------------------*/ + +module + mulAddRecFNToRaw#( + parameter expWidth = 3, + parameter sigWidth = 3, + parameter pipelineStages = 0, //no pipelining, default: 0; 64b, Zynq 7020 @ 50 MHz: 3 + parameter imulEn = 1'b1 // set 1 to enable integer MUL. + ) ( input clock, + input [(`floatControlWidth - 1):0] control, + // by set op[2] to 1, we can reuse this module to execute RISC-V integer multiply instruction MUL. + input [2:0] op, + // Note that for both signed and unsigned multiply, the results are the same, because we truncate the sign extension when evaluating the lower part. + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + input [(expWidth + sigWidth):0] c, + input [2:0] roundingMode, + output invalidExc, + output out_isNaN, + output out_isInf, + output out_isZero, + output out_sign, + output signed [(expWidth + 1):0] out_sExp, + output [(sigWidth + 2):0] out_sig, + // The output port of integer multiply. + output [expWidth + sigWidth-1:0] out_imul + ); +`include "HardFloat_localFuncs.vi" + + wire [(sigWidth - 1):0] mulAddA, mulAddB; + wire [(sigWidth*2 - 1):0] mulAddC; + wire [sigWidth*2:0] mulAddResult; + wire [5:0] intermed_compactState, intermed_compactState_Z; + wire signed [(expWidth + 1):0] intermed_sExp, intermed_sExp_Z; + wire [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist, intermed_CDom_CAlignDist_Z; + wire [(sigWidth + 1):0] intermed_highAlignedSigC, intermed_highAlignedSigC_Z; + wire [2:0] roundingMode_Z; + + mulAddRecFNToRaw_preMul#(expWidth, sigWidth, imulEn) + mulAddToRaw_preMul( + control, + op, + a, + b, + c, + roundingMode, + mulAddA, + mulAddB, + mulAddC, + intermed_compactState, + intermed_sExp, + intermed_CDom_CAlignDist, + intermed_highAlignedSigC + ); + + // MAC + bsg_mul_add_unsigned#(sigWidth, sigWidth, 2*sigWidth, 2*sigWidth+1, pipelineStages) + mulAdd ( + .clk_i(clock), + .a_i(mulAddA), + .b_i(mulAddB), + .c_i(mulAddC), + .o(mulAddResult) + ); + + bsg_dff_chain#($bits({intermed_compactState, intermed_sExp, intermed_CDom_CAlignDist, + intermed_highAlignedSigC, roundingMode}), pipelineStages) + shuntMulAdd ( + .clk_i(clock), + .data_i({intermed_compactState, intermed_sExp, intermed_CDom_CAlignDist, + intermed_highAlignedSigC, roundingMode}), + .data_o({intermed_compactState_Z, intermed_sExp_Z, intermed_CDom_CAlignDist_Z, + intermed_highAlignedSigC_Z, roundingMode_Z}) + ); + + mulAddRecFNToRaw_postMul#(expWidth, sigWidth) + mulAddToRaw_postMul( + intermed_compactState_Z, + intermed_sExp_Z, + intermed_CDom_CAlignDist_Z, + intermed_highAlignedSigC_Z, + mulAddResult, + roundingMode_Z, + invalidExc, + out_isNaN, + out_isInf, + out_isZero, + out_sign, + out_sExp, + out_sig + ); + assign out_imul = mulAddResult[expWidth + sigWidth-1:0]; +endmodule + +/*---------------------------------------------------------------------------- + * pipelineStages is used to insert pipelining registers according to the + * following placement: + * ... ... + * | mulAddRecFNToRaw -> consumes pipeline_p[0] + * | | | + * shunt pre_round | -> consumes pipeline_p[1] + * \ / | + * roundRawOut | + * | | + * fma_out imul_out + *----------------------------------------------------------------------------*/ + +module + mulAddRecFN#( + parameter expWidth = 3, + parameter sigWidth = 3, + parameter int pipelineStages[1:0] = {0,0}, + parameter imulEn = 1'b1 + ) ( input clock, + input [(`floatControlWidth - 1):0] control, + input [2:0] op, + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + input [(expWidth + sigWidth):0] c, + input [2:0] roundingMode, + output [(expWidth + sigWidth):0] out, + output [4:0] exceptionFlags, + output [expWidth + sigWidth-1:0] out_imul + ); + + wire invalidExc, out_isNaN, out_isInf, out_isZero, out_sign; + wire invalidExc_Z, out_isNaN_Z, out_isInf_Z, out_isZero_Z, out_sign_Z; + wire signed [(expWidth + 1):0] out_sExp, out_sExp_Z; + wire [(sigWidth + 2):0] out_sig, out_sig_Z; + wire [2:0] roundingMode_Z; + wire [(`floatControlWidth - 1):0] control_Z; + + mulAddRecFNToRaw#(expWidth, sigWidth, pipelineStages[0], imulEn) + mulAddRecFNToRaw( + clock, + control, + op, + a, + b, + c, + roundingMode, + invalidExc, + out_isNaN, + out_isInf, + out_isZero, + out_sign, + out_sExp, + out_sig, + out_imul + ); + + bsg_dff_chain#(5 + $bits({out_sExp_Z, out_sig_Z}), pipelineStages[1]) + pre_round ( + .clk_i(clock), + .data_i({invalidExc, out_isNaN, out_isInf, out_isZero, out_sign, + out_sExp, out_sig}), + .data_o({invalidExc_Z, out_isNaN_Z, out_isInf_Z, out_isZero_Z, out_sign_Z, + out_sExp_Z, out_sig_Z}) + ); + + bsg_dff_chain#($bits({roundingMode, control}), pipelineStages[0] + pipelineStages[1]) + shunt ( + .clk_i(clock), + .data_i({roundingMode, control}), + .data_o({roundingMode_Z, control_Z}) + ); + + roundRawFNToRecFN#(expWidth, sigWidth, 0) + roundRawOut( + control_Z, + invalidExc_Z, + 1'b0, + out_isNaN_Z, + out_isInf_Z, + out_isZero_Z, + out_sign_Z, + out_sExp_Z, + out_sig_Z, + roundingMode_Z, + out, + exceptionFlags + ); +endmodule + diff --git a/designs/black-parrot/src/hardfloat/mulRecFN.v b/designs/black-parrot/src/hardfloat/mulRecFN.v new file mode 100644 index 0000000..4f94bd5 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/mulRecFN.v @@ -0,0 +1,237 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +`include "HardFloat_consts.vi" +`include "HardFloat_specialize.vi" + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + mulRecFNToFullRaw#(parameter expWidth = 3, parameter sigWidth = 3) ( + input [(`floatControlWidth - 1):0] control, + input [(expWidth + sigWidth):0] a, + input [(expWidth + sigWidth):0] b, + output invalidExc, + output out_isNaN, + output out_isInf, + output out_isZero, + output out_sign, + output signed [(expWidth + 1):0] out_sExp, + output [(sigWidth*2 - 1):0] out_sig + ); + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaNA, isInfA, isZeroA, signA; + wire signed [(expWidth + 1):0] sExpA; + wire [sigWidth:0] sigA; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA); + wire isSigNaNA; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA); + wire isNaNB, isInfB, isZeroB, signB; + wire signed [(expWidth + 1):0] sExpB; + wire [sigWidth:0] sigB; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB); + wire isSigNaNB; + isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire notSigNaN_invalidExc = (isInfA && isZeroB) || (isZeroA && isInfB); + wire notNaN_isInfOut = isInfA || isInfB; + wire notNaN_isZeroOut = isZeroA || isZeroB; + wire notNaN_signOut = signA ^ signB; + wire signed [(expWidth + 1):0] common_sExpOut = + sExpA + sExpB - (1<>(expWidth - 2) == 'b010) && (sExp[(expWidth - 3):0] <= 1)) + || (sExp>>(expWidth - 1) == 'b00); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire [(normDistWidth - 1):0] denormShiftDist = minNormExp - 1 - sExp; + wire [(expWidth - 1):0] expOut = + (isSubnormal ? 0 : sExp - minNormExp + 1) + | (isNaN || isInf ? {expWidth{1'b1}} : 0); + wire [(sigWidth - 2):0] fractOut = + isSubnormal ? (sig>>1)>>denormShiftDist : isInf ? 0 : sig; + assign out = {sign, expOut, fractOut}; + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/recFNToIN.v b/designs/black-parrot/src/hardfloat/recFNToIN.v new file mode 100644 index 0000000..7f951a5 --- /dev/null +++ b/designs/black-parrot/src/hardfloat/recFNToIN.v @@ -0,0 +1,140 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +`include "HardFloat_consts.vi" +`include "HardFloat_specialize.vi" + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + recFNToIN#( + parameter expWidth = 3, parameter sigWidth = 3, parameter intWidth = 1 + ) ( + input [(`floatControlWidth - 1):0] control, + input [(expWidth + sigWidth):0] in, + input [2:0] roundingMode, + input signedOut, + output [(intWidth - 1):0] out, + output [2:0] intExceptionFlags + ); +`include "HardFloat_localFuncs.vi" + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + localparam intExpWidth = clog2(intWidth); + localparam boundedIntExpWidth = + (expWidth <= intExpWidth) ? expWidth - 1 : intExpWidth; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaN, isInf, isZero, sign; + wire signed [(expWidth + 1):0] sExp; + wire [sigWidth:0] sig; + recFNToRawFN#(expWidth, sigWidth) + recFNToRawFN(in, isNaN, isInf, isZero, sign, sExp, sig); + wire magGeOne = sExp[expWidth]; + wire [(expWidth - 1):0] posExp = sExp[(expWidth - 1):0]; + wire magJustBelowOne = !magGeOne && (&posExp); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire roundingMode_near_even = (roundingMode == `round_near_even); + wire roundingMode_minMag = (roundingMode == `round_minMag); + wire roundingMode_min = (roundingMode == `round_min); + wire roundingMode_max = (roundingMode == `round_max); + wire roundingMode_near_maxMag = (roundingMode == `round_near_maxMag); + wire roundingMode_odd = (roundingMode == `round_odd); + /*------------------------------------------------------------------------ + | Assuming the input floating-point value is not a NaN, its magnitude is + | at least 1, and it is not obviously so large as to lead to overflow, + | convert its significand to fixed-point (i.e., with the binary point in a + | fixed location). For a non-NaN input with a magnitude less than 1, this + | expression contrives to ensure that the integer bits of 'alignedSig' + | will all be zeros. + *------------------------------------------------------------------------*/ + wire [(intWidth + sigWidth - 1):0] shiftedSig = + {magGeOne, sig[(sigWidth - 2):0]} + <<(magGeOne ? sExp[(boundedIntExpWidth - 1):0] : 0); + wire [(intWidth + 1):0] alignedSig = + {shiftedSig>>(sigWidth - 2), |shiftedSig[(sigWidth - 3):0]}; + wire [(intWidth - 1):0] unroundedInt = alignedSig>>2; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire common_inexact = magGeOne ? |alignedSig[1:0] : !isZero; + wire roundIncr_near_even = + (magGeOne && ((&alignedSig[2:1]) || (&alignedSig[1:0]))) + || (magJustBelowOne && (|alignedSig[1:0]) ); + wire roundIncr_near_maxMag = + (magGeOne && alignedSig[1]) || magJustBelowOne; + wire roundIncr = + (roundingMode_near_even && roundIncr_near_even ) + || (roundingMode_near_maxMag && roundIncr_near_maxMag ) + || ((roundingMode_min || roundingMode_odd) && (sign && common_inexact)) + || (roundingMode_max && (!sign && common_inexact)); + wire [(intWidth - 1):0] complUnroundedInt = + sign ? ~unroundedInt : unroundedInt; + wire [(intWidth - 1):0] roundedInt = + (roundIncr ^ sign ? complUnroundedInt + 1 : complUnroundedInt) + | (roundingMode_odd && common_inexact); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire magGeOne_atOverflowEdge = (posExp == intWidth - 1); + wire roundCarryBut2 = (&unroundedInt[(intWidth - 3):0]) && roundIncr; + wire common_overflow = + magGeOne + ? (posExp >= intWidth) + || (signedOut + ? (sign ? magGeOne_atOverflowEdge + && ((|unroundedInt[(intWidth - 2):0]) + || roundIncr) + : magGeOne_atOverflowEdge + || ((posExp == intWidth - 2) + && roundCarryBut2)) + : sign || (magGeOne_atOverflowEdge + && unroundedInt[intWidth - 2] + && roundCarryBut2)) + : !signedOut && sign && roundIncr; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire invalidExc = isNaN || isInf; + wire overflow = !invalidExc && common_overflow; + wire inexact = !invalidExc && !common_overflow && common_inexact; + wire [(intWidth - 1):0] excOut; + iNFromException#(intWidth) iNFromException(signedOut, isNaN, sign, excOut); + assign out = invalidExc || common_overflow ? excOut : roundedInt; + assign intExceptionFlags = {invalidExc, overflow, inexact}; + +endmodule + diff --git a/designs/black-parrot/src/hardfloat/recFNToRecFN.v b/designs/black-parrot/src/hardfloat/recFNToRecFN.v new file mode 100644 index 0000000..5d1ca3b --- /dev/null +++ b/designs/black-parrot/src/hardfloat/recFNToRecFN.v @@ -0,0 +1,171 @@ + +/*============================================================================ + +This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point +Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +`include "HardFloat_consts.vi" +`include "HardFloat_specialize.vi" + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +module + recFNToRecFN#( + parameter inExpWidth = 3, + parameter inSigWidth = 3, + parameter outExpWidth = 3, + parameter outSigWidth = 3 + ) ( + input [(`floatControlWidth - 1):0] control, + input [(inExpWidth + inSigWidth):0] in, + input [2:0] roundingMode, + output [(outExpWidth + outSigWidth):0] out, + output [4:0] exceptionFlags + ); + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + wire isNaN, isInf, isZero, sign; + wire signed [(inExpWidth + 1):0] sExpIn; + wire [inSigWidth:0] sigIn; + recFNToRawFN#(inExpWidth, inSigWidth) + inToRawIn(in, isNaN, isInf, isZero, sign, sExpIn, sigIn); + wire isSigNaN; + isSigNaNRecFN#(inExpWidth, inSigWidth) isSigNaNIn(in, isSigNaN); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + generate + if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) begin + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + wire [(outExpWidth + outSigWidth):0] tentativeOut = + in<<(outSigWidth - inSigWidth); +`ifdef HardFloat_propagateNaNPayloads + assign out = tentativeOut | isNaN<<(outSigWidth - 2); +`else + assign out = + isNaN + ? {`HardFloat_signDefaultNaN, 3'b111} + <<(outExpWidth + outSigWidth - 3) + | `HardFloat_fractDefaultNaN(outSigWidth) + : tentativeOut; +`endif + assign exceptionFlags = {isSigNaN, 4'b0000}; + end else begin + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + roundAnyRawFNToRecFN#( + inExpWidth, + inSigWidth, + outExpWidth, + outSigWidth, + `flRoundOpt_sigMSBitAlwaysZero + ) roundRawInToOut( + control, + isSigNaN, + 1'b0, + isNaN, + isInf, + isZero, + sign, + sExpIn, + sigIn, + roundingMode, + out, + exceptionFlags + ); + end + endgenerate + +endmodule + +// DWP (BSG): This module converts between precisions when exactness can be guaranteed +// and therefore rounding is not needed +module + recFNToRecFN_unsafe#( + parameter inExpWidth = 3, + parameter inSigWidth = 3, + parameter outExpWidth = 3, + parameter outSigWidth = 3 + ) ( + input [(inExpWidth + inSigWidth):0] in, + output [(outExpWidth + outSigWidth):0] out + ); + + wire sign; + wire [inExpWidth:0] exp; + wire [(inSigWidth - 2):0] fract; + assign {sign, exp, fract} = in; + + wire isSpecial = (exp>>(inExpWidth - 1) == 'b11); + wire isNaN = isSpecial && exp[inExpWidth - 2]; + wire isInf = isSpecial && !exp[inExpWidth - 2]; + wire isZero = (exp>>(inExpWidth - 2) == 'b000); + + localparam biasAdj = (1 << outExpWidth) - (1 << inExpWidth); + localparam sigAdj = (outSigWidth - inSigWidth); + wire [outExpWidth:0] nanExp = 3'b111 << (outExpWidth-2); + wire [outExpWidth:0] infExp = 2'b11 << (outExpWidth-1); + wire [outExpWidth:0] zeroExp = {outExpWidth+1{1'b0}}; + + wire [outSigWidth-2:0] inFract = in[0+:inSigWidth-1]; + wire [outSigWidth-2:0] inFractAdjusted; + if (outSigWidth > inSigWidth) begin + assign inFractAdjusted = + isNaN ? {1'b1, {outSigWidth-2{1'b0}}} + : isInf ? {outSigWidth-1{1'b0}} + : isZero ? {outSigWidth-1{1'b0}} + : (inFract << sigAdj); + end else begin + assign inFractAdjusted = + isNaN ? {1'b1, {outSigWidth-2{1'b0}}} + : isInf ? {outSigWidth-1{1'b0}} + : isZero ? {outSigWidth-1{1'b0}} + : inFract[inSigWidth-2:inSigWidth-outSigWidth]; + end + wire [outExpWidth:0] inExp = in[inSigWidth-1+:inExpWidth+1]; + wire [outExpWidth:0] inExpAdjusted = + isNaN ? nanExp + : isInf ? infExp + : isZero ? zeroExp + : (inExp + biasAdj); + wire inSign = in[inSigWidth+inExpWidth]; + wire inSignAdjusted = + isNaN ? 1'b0 + : inSign; + + assign out = {inSignAdjusted, inExpAdjusted, inFractAdjusted}; + +endmodule + diff --git a/designs/black-parrot/tests/hello/prog.mem b/designs/black-parrot/tests/hello/prog.mem new file mode 100755 index 0000000..0f9fc93 --- /dev/null +++ b/designs/black-parrot/tests/hello/prog.mem @@ -0,0 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00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20 59 00 80 00 00 00 00 E0 7C 00 80 00 00 00 00 +FF FF FF FF FF FF FF FF 00 00 02 00 00 00 00 00 +50 07 20 80 00 00 00 00 E0 7C 00 80 00 00 00 00 diff --git a/designs/black-parrot/tests/hello/prog.nbf b/designs/black-parrot/tests/hello/prog.nbf new file mode 100644 index 0000000..ffde51c --- /dev/null +++ b/designs/black-parrot/tests/hello/prog.nbf @@ -0,0 +1,12 @@ +02_0000000000200008_0000000000000001 +02_0000000000200010_0000000080000000 +02_0000000000200608_0000000000000001 +02_0000000000200208_0000000000000001 +02_0000000000200408_0000000000000001 +02_0000000000308000_0000000000000001 +fe_0000000000000000_0000000000000000 +fe_0000000000000000_0000000000000000 +fe_0000000000000000_0000000000000000 +02_0000000000200008_0000000000000000 +fe_0000000000000000_0000000000000000 +ff_0000000000000000_0000000000000000 diff --git a/designs/black-parrot/tests/hello/prog.riscv b/designs/black-parrot/tests/hello/prog.riscv new file mode 100755 index 0000000..3fc8c71 Binary files /dev/null and b/designs/black-parrot/tests/hello/prog.riscv differ diff --git a/designs/black-parrot/tests/post.bash b/designs/black-parrot/tests/post.bash new file mode 100755 index 0000000..8cbd9cc --- /dev/null +++ b/designs/black-parrot/tests/post.bash @@ -0,0 +1,6 @@ +#!/bin/bash +set -x +set -e +# stdout must contain '' +grep -q "All cores finished! Terminating" _execute/stdout.log +