Internal error when assigning a hierarchical reference of an interface to a wire

[sterin]

Assigning a hierarchical reference of an interface to a wire results in an internal error instead of reporting an error.

interface A;
endinterface

module B#(parameter P);
  A a();
endmodule

module test;
  B #(0) b();
  wire xxx = b.a;
endmodule

Results in an internal error:

%Error: Internal Error: bug.sv:10:16: /path/to/verilator/src/V3Broken.cpp:168: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ /path/to/verilator/build/src/V3Ast__gen_impl.h:4717
                                     : ... note: In instance 'test'
   10 |   wire xxx = b.a;
      |                ^
                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

However, when B is not parameterized, Verilator issues an error, which is the expected behavior:

interface A;
endinterface

module B;
  A a();
endmodule

module test;
  B b();
  wire xxx = b.a;
endmodule

%Error: bug3.sv:10:16: Operator ASSIGNW expected non-interface on Assign RHS but 'a__Viftop' is an interface.
                     : ... note: In instance 'test'
   10 |   wire xxx = b.a;
      |                ^
%Error: Exiting due to 1 error(s)

Similarly, when B is parameterizd with a default value and b is instantiated with the default value, an error is reported as expected.

interface A;
endinterface

module B#(parameter P=0);
  A a();
endmodule

module test;
  B #(0) b();
  wire xxx = b.a;
endmodule

Only when the parameter value at instantiation is different from the default value, there is an internal error:

interface A;
endinterface

module B#(parameter P=0);
  A a();
endmodule

module test;
  B #(1) b();
  wire xxx = b.a;
endmodule

What 'verilator' command line do we use to run your example?

verilator --timing --trace --top-module test --binary bug.sv

What 'verilator --version' are you using? Did you try it with the git master version?

Verilator 5.030 and latest master.

What OS and distribution are you using?

Ubuntu 22.04 under WSL.

May we assist you in trying to fix this in Verilator yourself?

If this look like someone who is a Verilator beginner could reasonably handle.

[wsnyder]

I pushed test cases to master. The error is coming right after V3Param which is before it gets to the "right" error. V3Param tracks interfaces during it's elaboration, so I suspect it gets confused by the lack of a correct interface connection.

Assistance welcome, look in V3Param for the IfaceRef tracking.